diff --git a/db/.cmp.kpt b/db/.cmp.kpt index eda2417..efaf4e4 100644 Binary files a/db/.cmp.kpt and b/db/.cmp.kpt differ diff --git a/db/altsyncram_6u14.tdf b/db/altsyncram_6u14.tdf new file mode 100644 index 0000000..d1f9a5b --- /dev/null +++ b/db/altsyncram_6u14.tdf @@ -0,0 +1,439 @@ +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=0 NUMWORDS_B=0 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=12 WIDTH_B=12 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_6u14 +( + address_a[6..0] : input; + address_b[6..0] : input; + clock0 : input; + clock1 : input; + clocken1 : input; + data_a[11..0] : input; + q_b[11..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 12, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 12, + PORT_B_READ_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[6..0] : WIRE; + address_b_wire[6..0] : WIRE; + +BEGIN + ram_block1a[11..0].clk0 = clock0; + ram_block1a[11..0].clk1 = clock1; + ram_block1a[11..0].ena0 = wren_a; + ram_block1a[11..0].ena1 = clocken1; + ram_block1a[11..0].portaaddr[] = ( address_a_wire[6..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[11..0].portawe = wren_a; + ram_block1a[11..0].portbaddr[] = ( address_b_wire[6..0]); + ram_block1a[11..0].portbre = B"111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[11..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_eh91.tdf b/db/altsyncram_eh91.tdf new file mode 100644 index 0000000..6856b9b --- /dev/null +++ b/db/altsyncram_eh91.tdf @@ -0,0 +1,417 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom/hc91.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_c8a (data[0..0]) +RETURNS ( eq[1..0]); +FUNCTION mux_3nb (data[15..0], sel[0..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 16 reg 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_eh91 +( + address_a[13..0] : input; + clock0 : input; + q_a[7..0] : output; +) +VARIABLE + address_reg_a[0..0] : dffe; + out_address_reg_a[0..0] : dffe; + rden_decode : decode_c8a; + mux2 : mux_3nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/hc91.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[0..0] : WIRE; + address_a_wire[13..0] : WIRE; + rden_decode_addr_sel_a[0..0] : WIRE; + w_addr_val_a3w[0..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + rden_decode.data[] = w_addr_val_a3w[]; + mux2.data[] = ( ram_block1a[15..0].portadataout[0..0]); + mux2.sel[] = out_address_reg_a[].q; + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].ena0 = ( rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]); + ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[15..0].portare = B"1111111111111111"; + address_a_sel[0..0] = address_a[13..13]; + address_a_wire[] = address_a[]; + q_a[] = mux2.result[]; + rden_decode_addr_sel_a[0..0] = address_a_wire[13..13]; + w_addr_val_a3w[] = rden_decode_addr_sel_a[]; +END; +--VALID FILE diff --git a/db/cmpr_ngc.tdf b/db/cmpr_ngc.tdf new file mode 100644 index 0000000..ffdc5d0 --- /dev/null +++ b/db/cmpr_ngc.tdf @@ -0,0 +1,41 @@ +--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=1 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = +SUBDESIGN cmpr_ngc +( + aeb : output; + dataa[0..0] : input; + datab[0..0] : input; +) +VARIABLE + aeb_result_wire[0..0] : WIRE; + aneb_result_wire[0..0] : WIRE; + data_wire[1..0] : WIRE; + eq_wire : WIRE; + +BEGIN + aeb = eq_wire; + aeb_result_wire[] = (! aneb_result_wire[]); + aneb_result_wire[] = (data_wire[0..0] $ data_wire[1..1]); + data_wire[] = ( datab[0..0], dataa[0..0]); + eq_wire = aeb_result_wire[]; +END; +--VALID FILE diff --git a/db/cmpr_qgc.tdf b/db/cmpr_qgc.tdf new file mode 100644 index 0000000..32f342c --- /dev/null +++ b/db/cmpr_qgc.tdf @@ -0,0 +1,41 @@ +--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=4 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = +SUBDESIGN cmpr_qgc +( + aeb : output; + dataa[3..0] : input; + datab[3..0] : input; +) +VARIABLE + aeb_result_wire[0..0] : WIRE; + aneb_result_wire[0..0] : WIRE; + data_wire[9..0] : WIRE; + eq_wire : WIRE; + +BEGIN + aeb = eq_wire; + aeb_result_wire[] = (! aneb_result_wire[]); + aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]); + data_wire[] = ( datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[6..6] $ data_wire[7..7]) # (data_wire[8..8] $ data_wire[9..9])), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5]))); + eq_wire = aeb_result_wire[]; +END; +--VALID FILE diff --git a/db/cmpr_qkk.tdf b/db/cmpr_qkk.tdf new file mode 100644 index 0000000..cb943d2 --- /dev/null +++ b/db/cmpr_qkk.tdf @@ -0,0 +1,41 @@ +--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="NO" aeb dataa datab CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = +SUBDESIGN cmpr_qkk +( + aeb : output; + dataa[4..0] : input; + datab[4..0] : input; +) +VARIABLE + aeb_result_wire[0..0] : WIRE; + aneb_result_wire[0..0] : WIRE; + data_wire[12..0] : WIRE; + eq_wire : WIRE; + +BEGIN + aeb = eq_wire; + aeb_result_wire[] = (! aneb_result_wire[]); + aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]); + data_wire[] = ( datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[11..11] $ data_wire[12..12]), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6]))); + eq_wire = aeb_result_wire[]; +END; +--VALID FILE diff --git a/db/cntr_23j.tdf b/db/cntr_23j.tdf new file mode 100644 index 0000000..ead3418 --- /dev/null +++ b/db/cntr_23j.tdf @@ -0,0 +1,86 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=1 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=1 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION cmpr_ngc (dataa[0..0], datab[0..0]) +RETURNS ( aeb); + +--synthesis_resources = lut 1 reg 1 +SUBDESIGN cntr_23j +( + clk_en : input; + clock : input; + q[0..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[0..0] : dffeas; + cmpr1 : cmpr_ngc; + aclr_actual : WIRE; + cnt_en : NODE; + compare_result : WIRE; + cout_actual : WIRE; + data[0..0] : NODE; + external_cin : WIRE; + modulus_bus[0..0] : WIRE; + modulus_trigger : WIRE; + s_val[0..0] : WIRE; + safe_q[0..0] : WIRE; + sload : NODE; + sset : NODE; + time_to_clear : WIRE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[0..0].cin = ( external_cin); + counter_comb_bita[0..0].dataa = ( counter_reg_bit[0..0].q); + counter_comb_bita[0..0].datab = ( updown_dir); + counter_comb_bita[0..0].datad = ( B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir)))))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger); + cmpr1.dataa[] = safe_q[]; + cmpr1.datab[] = modulus_bus[]; + aclr_actual = B"0"; + cnt_en = VCC; + compare_result = cmpr1.aeb; + cout_actual = (counter_comb_bita[0].cout # (time_to_clear & updown_dir)); + data[] = GND; + external_cin = B"1"; + modulus_bus[] = B"0"; + modulus_trigger = cout_actual; + q[] = safe_q[]; + s_val[] = B"1"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + time_to_clear = compare_result; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/db/cntr_bgi.tdf b/db/cntr_bgi.tdf new file mode 100644 index 0000000..251e3b8 --- /dev/null +++ b/db/cntr_bgi.tdf @@ -0,0 +1,102 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=12 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=4 clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION cmpr_qgc (dataa[3..0], datab[3..0]) +RETURNS ( aeb); + +--synthesis_resources = lut 4 reg 4 +SUBDESIGN cntr_bgi +( + clock : input; + q[3..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[3..0] : dffeas; + cmpr1 : cmpr_qgc; + aclr_actual : WIRE; + clk_en : NODE; + cnt_en : NODE; + compare_result : WIRE; + cout_actual : WIRE; + data[3..0] : NODE; + external_cin : WIRE; + modulus_bus[3..0] : WIRE; + modulus_trigger : WIRE; + s_val[3..0] : WIRE; + safe_q[3..0] : WIRE; + sload : NODE; + sset : NODE; + time_to_clear : WIRE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[3..0].cin = ( counter_comb_bita[2..0].cout, external_cin); + counter_comb_bita[3..0].dataa = ( counter_reg_bit[3..0].q); + counter_comb_bita[3..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[3..0].datad = ( B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir)))))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[3..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger); + cmpr1.dataa[] = safe_q[]; + cmpr1.datab[] = modulus_bus[]; + aclr_actual = B"0"; + clk_en = VCC; + cnt_en = VCC; + compare_result = cmpr1.aeb; + cout_actual = (counter_comb_bita[3].cout # (time_to_clear & updown_dir)); + data[] = GND; + external_cin = B"1"; + modulus_bus[] = B"1011"; + modulus_trigger = cout_actual; + q[] = safe_q[]; + s_val[] = B"1111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + time_to_clear = compare_result; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/db/cntr_egi.tdf b/db/cntr_egi.tdf new file mode 100644 index 0000000..5c0a017 --- /dev/null +++ b/db/cntr_egi.tdf @@ -0,0 +1,102 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=15 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=4 clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION cmpr_qgc (dataa[3..0], datab[3..0]) +RETURNS ( aeb); + +--synthesis_resources = lut 4 reg 4 +SUBDESIGN cntr_egi +( + clock : input; + q[3..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[3..0] : dffeas; + cmpr1 : cmpr_qgc; + aclr_actual : WIRE; + clk_en : NODE; + cnt_en : NODE; + compare_result : WIRE; + cout_actual : WIRE; + data[3..0] : NODE; + external_cin : WIRE; + modulus_bus[3..0] : WIRE; + modulus_trigger : WIRE; + s_val[3..0] : WIRE; + safe_q[3..0] : WIRE; + sload : NODE; + sset : NODE; + time_to_clear : WIRE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[3..0].cin = ( counter_comb_bita[2..0].cout, external_cin); + counter_comb_bita[3..0].dataa = ( counter_reg_bit[3..0].q); + counter_comb_bita[3..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[3..0].datad = ( B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir)))))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[3..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger); + cmpr1.dataa[] = safe_q[]; + cmpr1.datab[] = modulus_bus[]; + aclr_actual = B"0"; + clk_en = VCC; + cnt_en = VCC; + compare_result = cmpr1.aeb; + cout_actual = (counter_comb_bita[3].cout # (time_to_clear & updown_dir)); + data[] = GND; + external_cin = B"1"; + modulus_bus[] = B"1110"; + modulus_trigger = cout_actual; + q[] = safe_q[]; + s_val[] = B"1111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + time_to_clear = compare_result; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/db/cntr_i6j.tdf b/db/cntr_i6j.tdf new file mode 100644 index 0000000..8fa4b49 --- /dev/null +++ b/db/cntr_i6j.tdf @@ -0,0 +1,101 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=128 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=7 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 7 reg 7 +SUBDESIGN cntr_i6j +( + clk_en : input; + clock : input; + q[6..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita6 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[6..0] : dffeas; + aclr_actual : WIRE; + cnt_en : NODE; + data[6..0] : NODE; + external_cin : WIRE; + s_val[6..0] : WIRE; + safe_q[6..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[6..0].cin = ( counter_comb_bita[5..0].cout, external_cin); + counter_comb_bita[6..0].dataa = ( counter_reg_bit[6..0].q); + counter_comb_bita[6..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[6..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[6..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = B"0"; + cnt_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"1111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/db/decode_dvf.tdf b/db/decode_dvf.tdf new file mode 100644 index 0000000..251ccfc --- /dev/null +++ b/db/decode_dvf.tdf @@ -0,0 +1,35 @@ +--lpm_decode CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_DECODES=2 LPM_WIDTH=1 data enable eq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 1 +SUBDESIGN decode_dvf +( + data[0..0] : input; + enable : input; + eq[1..0] : output; +) +VARIABLE + eq_node[1..0] : WIRE; + +BEGIN + eq[] = eq_node[]; + eq_node[] = ( (data[] & enable), ((! data[]) & enable)); +END; +--VALID FILE diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index a9de2b0..97f5d49 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/mux_ssc.tdf b/db/mux_ssc.tdf new file mode 100644 index 0000000..ebc9ef7 --- /dev/null +++ b/db/mux_ssc.tdf @@ -0,0 +1,67 @@ +--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=2 LPM_WIDTH=15 LPM_WIDTHS=1 data result sel +--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 15 +SUBDESIGN mux_ssc +( + data[29..0] : input; + result[14..0] : output; + sel[0..0] : input; +) +VARIABLE + result_node[14..0] : WIRE; + sel_node[0..0] : WIRE; + w_data102w[1..0] : WIRE; + w_data114w[1..0] : WIRE; + w_data126w[1..0] : WIRE; + w_data138w[1..0] : WIRE; + w_data150w[1..0] : WIRE; + w_data162w[1..0] : WIRE; + w_data174w[1..0] : WIRE; + w_data18w[1..0] : WIRE; + w_data30w[1..0] : WIRE; + w_data42w[1..0] : WIRE; + w_data4w[1..0] : WIRE; + w_data54w[1..0] : WIRE; + w_data66w[1..0] : WIRE; + w_data78w[1..0] : WIRE; + w_data90w[1..0] : WIRE; + +BEGIN + result[] = result_node[]; + result_node[] = ( ((sel_node[] & w_data174w[1..1]) # ((! sel_node[]) & w_data174w[0..0])), ((sel_node[] & w_data162w[1..1]) # ((! sel_node[]) & w_data162w[0..0])), ((sel_node[] & w_data150w[1..1]) # ((! sel_node[]) & w_data150w[0..0])), ((sel_node[] & w_data138w[1..1]) # ((! sel_node[]) & w_data138w[0..0])), ((sel_node[] & w_data126w[1..1]) # ((! sel_node[]) & w_data126w[0..0])), ((sel_node[] & w_data114w[1..1]) # ((! sel_node[]) & w_data114w[0..0])), ((sel_node[] & w_data102w[1..1]) # ((! sel_node[]) & w_data102w[0..0])), ((sel_node[] & w_data90w[1..1]) # ((! sel_node[]) & w_data90w[0..0])), ((sel_node[] & w_data78w[1..1]) # ((! sel_node[]) & w_data78w[0..0])), ((sel_node[] & w_data66w[1..1]) # ((! sel_node[]) & w_data66w[0..0])), ((sel_node[] & w_data54w[1..1]) # ((! sel_node[]) & w_data54w[0..0])), ((sel_node[] & w_data42w[1..1]) # ((! sel_node[]) & w_data42w[0..0])), ((sel_node[] & w_data30w[1..1]) # ((! sel_node[]) & w_data30w[0..0])), ((sel_node[] & w_data18w[1..1]) # ((! sel_node[]) & w_data18w[0..0])), ((sel_node[] & w_data4w[1..1]) # ((! sel_node[]) & w_data4w[0..0]))); + sel_node[] = ( sel[0..0]); + w_data102w[] = ( data[23..23], data[8..8]); + w_data114w[] = ( data[24..24], data[9..9]); + w_data126w[] = ( data[25..25], data[10..10]); + w_data138w[] = ( data[26..26], data[11..11]); + w_data150w[] = ( data[27..27], data[12..12]); + w_data162w[] = ( data[28..28], data[13..13]); + w_data174w[] = ( data[29..29], data[14..14]); + w_data18w[] = ( data[16..16], data[1..1]); + w_data30w[] = ( data[17..17], data[2..2]); + w_data42w[] = ( data[18..18], data[3..3]); + w_data4w[] = ( data[15..15], data[0..0]); + w_data54w[] = ( data[19..19], data[4..4]); + w_data66w[] = ( data[20..20], data[5..5]); + w_data78w[] = ( data[21..21], data[6..6]); + w_data90w[] = ( data[22..22], data[7..7]); +END; +--VALID FILE diff --git a/db/pll_sdram_altpll.v b/db/pll_sdram_altpll.v new file mode 100644 index 0000000..b6f82e8 --- /dev/null +++ b/db/pll_sdram_altpll.v @@ -0,0 +1,92 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=50 clk0_duty_cycle=50 clk0_multiply_by=133 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll_sdram" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END +//CBXI_INSTANCE_NAME="spectrum_pll_sdram_sdram_clocks_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module pll_sdram_altpll + ( + clk, + inclk) /* synthesis synthesis_clearbox=1 */; + output [4:0] clk; + input [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + + cycloneive_pll pll1 + ( + .activeclock(), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .areset(1'b0), + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 50, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 133, + pll1.clk0_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}; +endmodule //pll_sdram_altpll +//VALID FILE diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 2f381ab..52251c9 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,329 +1,354 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899774991 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:42:54 2022 " "Processing started: Sat Apr 2 14:42:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648899775174 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775242 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775243 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775244 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775244 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775245 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775245 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775246 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775246 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775248 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775248 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775249 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775249 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775253 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775253 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775255 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775255 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775256 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775256 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775257 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775257 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775259 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775259 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775260 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775286 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775287 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775288 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775288 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775289 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775289 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775290 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775291 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775292 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775292 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775293 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775293 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775294 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775295 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775295 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775297 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775298 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775299 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775299 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775300 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775301 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775301 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648899775305 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648899775305 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775305 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775306 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775309 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775310 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775310 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775311 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775312 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775312 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775313 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775313 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775616 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775616 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775617 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775618 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775621 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775621 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648899775785 ""} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775804 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775853 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899775854 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775905 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775949 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775949 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775949 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775993 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775993 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775993 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775997 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776001 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776002 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776052 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776052 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776052 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776096 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776096 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776096 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776102 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776106 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776107 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776158 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776158 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776158 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776202 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776202 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776203 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776246 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776246 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776247 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776291 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776291 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776293 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776297 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776326 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776330 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776381 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776381 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776382 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 303 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776384 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776385 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776395 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776398 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776399 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776448 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776449 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776450 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776451 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776453 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776454 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776456 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776457 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 347 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776460 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776463 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776464 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776465 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776479 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776480 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776481 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776481 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776483 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776484 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776485 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776486 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776487 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776488 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776489 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776489 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776490 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776491 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776493 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776493 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776496 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776496 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776497 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776498 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776499 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776500 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776502 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776514 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776515 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776517 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776518 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776519 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776522 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776523 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776524 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776524 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776525 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776526 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776527 ""} -{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 47 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 72 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 97 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 122 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 147 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a5 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a5\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 172 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a6 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a6\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 197 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a7 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a7\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 222 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a8 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a9 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 272 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a10 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 297 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a11 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 322 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a12 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a12\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 347 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a13 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a13\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 372 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a14 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a14\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 397 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a15 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a15\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 422 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a16 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a16\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 447 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a17 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a17\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 472 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a18 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a18\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 497 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a19 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a19\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 522 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a20 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a20\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 547 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a21 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a21\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 572 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a22 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a22\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 597 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a23 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a23\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 622 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a24 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a24\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 647 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a25 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a25\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 672 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a26 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a26\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 697 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a27 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a27\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 722 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a28 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a28\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 747 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a29 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a29\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 772 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a30 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a30\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 797 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a31 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a31\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 822 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1648899776831 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1648899776831 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648899781398 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648899781498 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648899781504 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648899781529 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648899781529 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[33]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|DRAM_CS_N"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648899784991 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648899785379 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648899788636 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648899788723 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648899788976 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899788976 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899789231 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899789231 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648899789231 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2957 " "Implemented 2957 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_OPINS" "85 " "Implemented 85 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2809 " "Implemented 2809 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Implemented 32 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648899789231 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648899789231 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 146 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 146 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "457 " "Peak virtual memory: 457 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:09 2022 " "Processing ended: Sat Apr 2 14:43:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899790598 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899790599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:10 2022 " "Processing started: Sat Apr 2 14:43:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899790599 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648899790599 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648899790599 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648899790623 ""} -{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648899790624 ""} -{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648899790624 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648899790713 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648899790729 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790766 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790767 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790767 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790833 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1262 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790833 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648899790833 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1230 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1231 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648899790835 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648899790913 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648899790924 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648899791139 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5104 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5106 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5108 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5110 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5112 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648899791146 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648899791149 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648899791155 ""} -{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 12000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 12000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 15489 " "The value of the parameter \"Min Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 15489" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 26455 " "The value of the parameter \"Max Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 26455" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} { 0 { 0 ""} 0 1261 9662 10382 0} } } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1648899791688 ""} -{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1648899791706 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648899792341 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792349 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792349 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648899792349 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648899792351 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792352 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792352 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648899792352 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648899792352 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} -{ "Warning" "WSTA_SCC_LOOP" "507 " "Found combinational loop of 507 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datab " "Node \"z80_\|alu_\|db_high\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datac " "Node \"z80_\|alu_\|db_high\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|dataa " "Node \"z80_\|alu_\|db\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|combout " "Node \"z80_\|alu_\|db\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|dataa " "Node \"z80_\|alu_\|db\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datab " "Node \"z80_\|alu_\|db_high\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|combout " "Node \"z80_\|alu_\|db_high\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|combout " "Node \"z80_\|alu_\|db_high\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|combout " "Node \"z80_\|alu_\|db_high\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|combout " "Node \"z80_\|alu_\|db_high\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|datab " "Node \"z80_\|alu_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|combout " "Node \"z80_\|alu_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datab " "Node \"z80_\|alu_control_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datac " "Node \"z80_\|alu_control_\|db\[5\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|datab " "Node \"z80_\|alu_\|db\[5\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|combout " "Node \"z80_\|alu_\|db\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datab " "Node \"z80_\|alu_\|db_high\[3\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|combout " "Node \"z80_\|alu_\|db_high\[3\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datab " "Node \"z80_\|alu_\|db_high\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|combout " "Node \"z80_\|alu_\|db_high\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|combout " "Node \"z80_\|alu_\|db_high\[3\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|datab " "Node \"z80_\|alu_\|db\[7\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|combout " "Node \"z80_\|alu_\|db\[7\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datab " "Node \"z80_\|alu_\|db_high\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|combout " "Node \"z80_\|alu_\|db_high\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|combout " "Node \"z80_\|alu_\|db_high\[2\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|combout " "Node \"z80_\|alu_\|db_high\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|combout " "Node \"z80_\|alu_\|db_high\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|combout " "Node \"z80_\|alu_\|db_high\[2\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|datab " "Node \"z80_\|alu_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|combout " "Node \"z80_\|alu_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|datab " "Node \"z80_\|alu_\|db_high\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|combout " "Node \"z80_\|alu_\|db_high\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|datab " "Node \"z80_\|alu_\|db_high\[2\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datad " "Node \"z80_\|alu_control_\|db\[6\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|datad " "Node \"z80_\|alu_control_\|db\[6\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|combout " "Node \"z80_\|alu_control_\|db\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|dataa " "Node \"z80_\|alu_\|db\[6\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|combout " "Node \"z80_\|alu_\|db\[6\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|dataa " "Node \"z80_\|alu_\|db\[6\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|datab " "Node \"z80_\|alu_\|db\[6\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|datac " "Node \"z80_\|alu_control_\|db\[7\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|combout " "Node \"z80_\|alu_control_\|db\[7\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datac " "Node \"z80_\|alu_control_\|db\[7\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datad " "Node \"z80_\|alu_control_\|db\[7\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datad " "Node \"z80_\|alu_control_\|db\[7\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|dataa " "Node \"z80_\|alu_\|db\[7\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|combout " "Node \"z80_\|alu_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|dataa " "Node \"z80_\|alu_\|db\[7\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|combout " "Node \"z80_\|alu_control_\|db\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datab " "Node \"z80_\|alu_control_\|db\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datab " "Node \"z80_\|alu_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|combout " "Node \"z80_\|alu_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|datac " "Node \"z80_\|alu_control_\|db\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datac " "Node \"z80_\|alu_control_\|db\[1\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datad " "Node \"z80_\|alu_control_\|db\[1\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|dataa " "Node \"z80_\|alu_\|db\[1\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|combout " "Node \"z80_\|alu_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|dataa " "Node \"z80_\|alu_\|db\[1\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datad " "Node \"z80_\|alu_control_\|db\[1\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datab " "Node \"z80_\|alu_\|db_low\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|datab " "Node \"z80_\|alu_\|db\[2\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|combout " "Node \"z80_\|alu_\|db\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|dataa " "Node \"z80_\|alu_\|db\[2\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|combout " "Node \"z80_\|alu_\|db\[2\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|dataa " "Node \"z80_\|alu_\|db\[2\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|datab " "Node \"z80_\|alu_\|db\[2\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datab " "Node \"z80_\|alu_\|db_low\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|datab " "Node \"z80_\|alu_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|combout " "Node \"z80_\|alu_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|dataa " "Node \"z80_\|alu_\|db\[3\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|combout " "Node \"z80_\|alu_\|db\[3\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|datab " "Node \"z80_\|alu_\|db\[3\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datac " "Node \"z80_\|alu_\|db_high\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datac " "Node \"z80_\|alu_\|db_high\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|combout " "Node \"z80_\|alu_\|db_high\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datab " "Node \"z80_\|alu_\|db_high\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datac " "Node \"z80_\|alu_\|db_low\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datab " "Node \"z80_\|alu_\|db_high\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|combout " "Node \"z80_\|alu_\|db_high\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|datac " "Node \"z80_\|alu_\|db_high\[1\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datac " "Node \"z80_\|alu_\|db_high\[3\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|dataa " "Node \"z80_\|alu_\|db\[3\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|datab " "Node \"z80_\|alu_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|datab " "Node \"z80_\|alu_\|db\[7\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datab " "Node \"z80_\|alu_\|db_high\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datac " "Node \"z80_\|alu_\|db_low\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datac " "Node \"z80_\|alu_\|db_low\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|datab " "Node \"z80_\|alu_\|db_high\[2\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|dataa " "Node \"z80_\|alu_\|db\[5\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datab " "Node \"z80_\|alu_\|db_high\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|datab " "Node \"z80_\|alu_\|db\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datac " "Node \"z80_\|alu_\|db_low\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datad " "Node \"z80_\|alu_\|db_high\[1\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datab " "Node \"z80_\|alu_control_\|db\[4\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648899792360 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "507 " "Design contains combinational loop of 507 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648899792376 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648899792410 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648899792410 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648899792425 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648899792427 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648899792427 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5089 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2809 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1227 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4150 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 73 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1471 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4185 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4158 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4159 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4160 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4161 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4162 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4163 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4164 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4165 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4166 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 683 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792621 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 917 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792621 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792621 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 754 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792621 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648899793449 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648899793453 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648899793453 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648899793457 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648899793462 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648899793466 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648899793466 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648899793469 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648899794289 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 I/O Input Buffer " "Packed 8 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648899794293 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648899794293 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648899794293 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648899794293 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648899794431 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899794433 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648899795941 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899796762 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648899796784 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648899799543 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899799543 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648899800437 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648899803211 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648899803211 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899805930 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648899805932 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648899805932 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.88 " "Total time spent on timing analysis during the Fitter is 1.88 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648899806074 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648899806133 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648899806898 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648899806949 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648899807650 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899808810 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648899809279 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "57 Cyclone IV E " "57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 169 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 170 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 171 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 176 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 223 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 224 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 191 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 192 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 194 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 195 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 197 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 199 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 201 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 203 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 205 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 206 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 22 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 234 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 135 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 220 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 136 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 222 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 221 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 230 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648899809297 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648899809632 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 568 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 568 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "639 " "Peak virtual memory: 639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:30 2022 " "Processing ended: Sat Apr 2 14:43:30 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648899810355 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648899812346 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899812347 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:32 2022 " "Processing started: Sat Apr 2 14:43:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899812347 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648899812347 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648899812347 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648899813443 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648899813473 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:33 2022 " "Processing ended: Sat Apr 2 14:43:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648899813776 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648899814393 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648899815598 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:35 2022 " "Processing started: Sat Apr 2 14:43:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648899815626 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648899815806 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815807 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815847 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815848 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648899816257 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816265 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816266 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648899816266 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648899816268 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} -{ "Warning" "WSTA_SCC_LOOP" "507 " "Found combinational loop of 507 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datad " "Node \"z80_\|alu_control_\|db\[1\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datac " "Node \"z80_\|alu_control_\|db\[1\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|dataa " "Node \"z80_\|alu_\|db\[1\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|combout " "Node \"z80_\|alu_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datab " "Node \"z80_\|alu_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|combout " "Node \"z80_\|alu_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datac " "Node \"z80_\|alu_\|db_low\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datac " "Node \"z80_\|alu_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datad " "Node \"z80_\|alu_\|db_low\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datac " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|datad " "Node \"z80_\|alu_control_\|db\[0\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|combout " "Node \"z80_\|alu_control_\|db\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datad " "Node \"z80_\|bus_control_\|db\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datad " "Node \"z80_\|alu_control_\|db\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|datad " "Node \"z80_\|alu_\|db_high\[3\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|combout " "Node \"z80_\|alu_\|db_high\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datab " "Node \"z80_\|alu_\|db_high\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|combout " "Node \"z80_\|alu_\|db_high\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datad " "Node \"z80_\|alu_\|db_high\[3\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|combout " "Node \"z80_\|alu_\|db_high\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|datad " "Node \"z80_\|alu_\|db_high\[3\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|combout " "Node \"z80_\|alu_\|db_high\[3\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|datac " "Node \"z80_\|alu_\|db\[7\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|combout " "Node \"z80_\|alu_\|db\[7\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|combout " "Node \"z80_\|alu_\|db_high\[2\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|datad " "Node \"z80_\|alu_\|db_high\[2\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|combout " "Node \"z80_\|alu_\|db_high\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datad " "Node \"z80_\|alu_\|db_high\[2\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|combout " "Node \"z80_\|alu_\|db_high\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|datad " "Node \"z80_\|alu_\|db_high\[2\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|combout " "Node \"z80_\|alu_\|db_high\[2\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|datac " "Node \"z80_\|alu_\|db\[6\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|combout " "Node \"z80_\|alu_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|datac " "Node \"z80_\|alu_\|db_high\[2\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|combout " "Node \"z80_\|alu_\|db_high\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datab " "Node \"z80_\|alu_\|db_high\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|combout " "Node \"z80_\|alu_\|db_high\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|datac " "Node \"z80_\|alu_\|db_high\[1\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|combout " "Node \"z80_\|alu_\|db_high\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|combout " "Node \"z80_\|alu_\|db_high\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|datac " "Node \"z80_\|alu_\|db\[5\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|combout " "Node \"z80_\|alu_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datad " "Node \"z80_\|alu_\|db_high\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datac " "Node \"z80_\|alu_control_\|db\[5\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datac " "Node \"z80_\|bus_control_\|db\[5\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datab " "Node \"z80_\|alu_\|db_high\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|combout " "Node \"z80_\|alu_\|db_high\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datab " "Node \"z80_\|alu_\|db_high\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|combout " "Node \"z80_\|alu_\|db_high\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|datab " "Node \"z80_\|alu_\|db_high\[1\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datac " "Node \"z80_\|alu_\|db_high\[3\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|combout " "Node \"z80_\|alu_\|db_high\[3\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datab " "Node \"z80_\|alu_\|db_high\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datac " "Node \"z80_\|alu_control_\|db\[5\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datab " "Node \"z80_\|alu_control_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|datab " "Node \"z80_\|alu_\|db\[2\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|combout " "Node \"z80_\|alu_\|db\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datad " "Node \"z80_\|alu_\|db_low\[1\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datac " "Node \"z80_\|alu_\|db_low\[2\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datac " "Node \"z80_\|alu_\|db_low\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datad " "Node \"z80_\|alu_\|db_low\[3\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datad " "Node \"z80_\|alu_\|db_low\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|datac " "Node \"z80_\|alu_\|db\[3\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|combout " "Node \"z80_\|alu_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|datab " "Node \"z80_\|alu_\|db\[3\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|combout " "Node \"z80_\|alu_\|db\[3\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datac " "Node \"z80_\|alu_\|db_high\[1\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datac " "Node \"z80_\|alu_\|db_high\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datab " "Node \"z80_\|alu_\|db_high\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datac " "Node \"z80_\|alu_\|db\[4\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|datab " "Node \"z80_\|alu_\|db\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|combout " "Node \"z80_\|alu_\|db\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datad " "Node \"z80_\|alu_\|db_high\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datad " "Node \"z80_\|alu_\|db_low\[3\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|dataa " "Node \"z80_\|alu_\|db\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datad " "Node \"z80_\|alu_control_\|db\[4\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datab " "Node \"z80_\|alu_control_\|db\[4\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datac " "Node \"z80_\|bus_control_\|db\[4\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datab " "Node \"z80_\|alu_control_\|db\[4\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datad " "Node \"z80_\|alu_\|db_low\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datab " "Node \"z80_\|alu_\|db_low\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datac " "Node \"z80_\|alu_\|db_high\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datac " "Node \"z80_\|alu_\|db_low\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datab " "Node \"z80_\|alu_\|db_high\[3\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datac " "Node \"z80_\|alu_\|db_low\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|datad " "Node \"z80_\|alu_\|db\[3\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datad " "Node \"z80_\|alu_\|db_low\[2\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datac " "Node \"z80_\|alu_\|db_low\[3\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|datab " "Node \"z80_\|alu_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|datad " "Node \"z80_\|alu_\|db\[2\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|combout " "Node \"z80_\|alu_\|db\[2\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|datac " "Node \"z80_\|alu_\|db\[2\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datac " "Node \"z80_\|bus_control_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datab " "Node \"z80_\|bus_control_\|db\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datab " "Node \"z80_\|alu_control_\|db\[2\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|datab " "Node \"z80_\|alu_\|db\[2\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datab " "Node \"z80_\|alu_control_\|db\[2\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datad " "Node \"z80_\|alu_\|db_low\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datab " "Node \"z80_\|alu_\|db_high\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|datad " "Node \"z80_\|alu_\|db\[5\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|combout " "Node \"z80_\|alu_\|db\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|datab " "Node \"z80_\|alu_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|datab " "Node \"z80_\|alu_\|db\[5\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|datad " "Node \"z80_\|alu_\|db_high\[2\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|datac " "Node \"z80_\|alu_control_\|db\[6\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|combout " "Node \"z80_\|alu_control_\|db\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|datab " "Node \"z80_\|bus_control_\|db\[6\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datab " "Node \"z80_\|alu_control_\|db\[6\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|datab " "Node \"z80_\|alu_\|db\[6\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|combout " "Node \"z80_\|alu_\|db\[6\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|datab " "Node \"z80_\|alu_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|datad " "Node \"z80_\|alu_\|db\[6\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|datac " "Node \"z80_\|alu_\|db\[7\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|combout " "Node \"z80_\|alu_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|datab " "Node \"z80_\|alu_\|db\[7\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datad " "Node \"z80_\|alu_\|db_high\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|datab " "Node \"z80_\|alu_control_\|db\[7\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|combout " "Node \"z80_\|alu_control_\|db\[7\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datad " "Node \"z80_\|alu_control_\|db\[7\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|datab " "Node \"z80_\|bus_control_\|db\[7\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datad " "Node \"z80_\|alu_control_\|db\[7\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datac " "Node \"z80_\|alu_control_\|db\[7\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|datab " "Node \"z80_\|alu_\|db\[7\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datac " "Node \"z80_\|alu_control_\|db\[7\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datab " "Node \"z80_\|alu_control_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datac " "Node \"z80_\|alu_\|db_low\[2\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|datab " "Node \"z80_\|alu_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|datac " "Node \"z80_\|bus_control_\|db\[1\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datab " "Node \"z80_\|alu_control_\|db\[1\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648899816276 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "507 " "Design contains combinational loop of 507 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648899816292 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899816322 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899816322 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816452 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648899816455 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648899816475 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899816506 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899816506 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.375 " "Worst-case setup slack is -18.375" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.375 -543.462 CLOCK_50 " " -18.375 -543.462 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.723 -41.132 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.723 -41.132 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.035 -48.241 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.035 -48.241 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.057 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.057 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.477 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.477 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.953 " "Worst-case hold slack is -0.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.953 -14.699 CLOCK_50 " " -0.953 -14.699 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.936 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.936 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.224 " "Worst-case recovery slack is -6.224" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.224 -458.974 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.224 -458.974 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.682 " "Worst-case removal slack is 3.682" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.682 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.682 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.776 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.776 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.603 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.603 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648899816659 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648899816695 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648899817630 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899817793 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899817793 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817795 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899817812 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899817812 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.547 " "Worst-case setup slack is -17.547" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.547 -513.385 CLOCK_50 " " -17.547 -513.385 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -38.471 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.416 -38.471 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.660 -42.274 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.660 -42.274 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.134 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.134 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.130 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.130 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.767 " "Worst-case hold slack is -0.767" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.767 -11.715 CLOCK_50 " " -0.767 -11.715 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.928 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.928 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.744 " "Worst-case recovery slack is -5.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.744 -423.185 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.744 -423.185 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.356 " "Worst-case removal slack is 3.356" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.356 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.356 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.792 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.792 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.487 0.000 CLOCK_50 " " 9.487 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648899818028 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899818319 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899818319 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818321 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899818328 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899818328 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.145 " "Worst-case setup slack is -15.145" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.145 -411.914 CLOCK_50 " " -15.145 -411.914 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.764 -34.680 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.764 -34.680 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.778 -28.278 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -1.778 -28.278 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.051 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.051 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.528 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 5.528 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.677 " "Worst-case hold slack is -0.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.677 -10.405 CLOCK_50 " " -0.677 -10.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.892 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.892 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.692 " "Worst-case recovery slack is -4.692" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.692 -358.022 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.692 -358.022 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.517 " "Worst-case removal slack is 2.517" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.517 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.517 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.784 " "Worst-case minimum pulse width slack is 4.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.790 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.790 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648899819047 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648899819047 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 528 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 528 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "445 " "Peak virtual memory: 445 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:39 2022 " "Processing ended: Sat Apr 2 14:43:39 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899821564 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:41 2022 " "Processing started: Sat Apr 2 14:43:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899821566 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899822459 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899822787 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823112 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823439 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823700 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823957 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899824212 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899824471 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:44 2022 " "Processing ended: Sat Apr 2 14:43:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1242 s " "Quartus II Full Compilation was successful. 0 errors, 1242 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899825249 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242561778 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242561779 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:56:01 2022 " "Processing started: Wed Apr 6 13:56:01 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242561779 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1649242561779 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1649242561779 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1649242561967 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562037 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562037 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562040 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562040 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562041 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562041 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562042 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562042 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562043 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562043 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562044 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562044 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562045 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562045 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562046 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562046 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562047 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562047 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562048 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562048 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562048 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562048 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562049 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562049 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562050 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562050 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562051 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562051 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562051 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562051 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562052 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562052 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562053 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562053 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562054 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562054 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562055 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562055 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562055 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562055 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562056 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562056 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562082 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562082 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562083 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562083 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562084 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562084 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562085 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562085 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562086 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562086 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562087 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562088 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562088 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562089 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562089 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562090 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562090 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562091 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562091 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562092 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562092 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562092 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562092 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562093 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562093 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562094 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562094 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562095 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562095 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562096 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562096 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562096 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562096 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562097 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562097 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562098 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1649242562101 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1649242562101 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562101 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562102 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562102 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562104 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562104 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562105 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562105 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562106 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562106 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562109 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562109 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562110 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562110 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562111 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562111 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562112 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562112 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562410 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562410 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562410 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562411 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562411 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562411 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562414 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562415 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562416 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562416 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562418 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562418 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562419 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562419 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(118) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(118)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 118 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242562420 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(120) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(120)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 120 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242562420 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(122) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(122)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 122 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242562420 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(124) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(124)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 124 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242562420 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(126) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(126)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 126 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242562420 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(128) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(128)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 128 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242562420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram " "Found entity 1: sdram" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562421 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562421 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 SDRAM_ctrl " "Found entity 1: SDRAM_ctrl" { } { { "sdram_ctrl.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_ctrl.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562422 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "sdram_controller.v(166) " "Verilog HDL warning at sdram_controller.v(166): extended using \"x\" or \"z\"" { } { { "sdram_controller.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_controller.v" 166 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1649242562422 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller_new " "Found entity 1: sdram_controller_new" { } { { "sdram_controller.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_controller.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562423 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562423 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sdram " "Found entity 1: pll_sdram" { } { { "pll_sdram.v" "" { Text "/home/benny/work/fpga/spectrum/pll_sdram.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562424 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562424 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 debouncer " "Found entity 1: debouncer" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562425 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562425 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1649242562631 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_io_read_requested spectrum.sv(114) " "Verilog HDL or VHDL warning at spectrum.sv(114): object \"is_io_read_requested\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 114 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242562633 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_io_write_requested spectrum.sv(115) " "Verilog HDL or VHDL warning at spectrum.sv(115): object \"is_io_write_requested\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 115 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242562633 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_rom_address spectrum.sv(118) " "Verilog HDL or VHDL warning at spectrum.sv(118): object \"is_rom_address\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 118 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242562633 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "kempston_last_fire_state spectrum.sv(133) " "Verilog HDL or VHDL warning at spectrum.sv(133): object \"kempston_last_fire_state\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 133 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242562633 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sdram_write_request spectrum.sv(231) " "Verilog HDL or VHDL warning at spectrum.sv(231): object \"sdram_write_request\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 231 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242562633 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 spectrum.sv(141) " "Verilog HDL assignment warning at spectrum.sv(141): truncated value with size 32 to match size of target (18)" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 141 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1649242562635 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debouncer debouncer:debounce_turbo " "Elaborating entity \"debouncer\" for hierarchy \"debouncer:debounce_turbo\"" { } { { "spectrum.sv" "debounce_turbo" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 54 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562655 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 debouncer.v(13) " "Verilog HDL assignment warning at debouncer.v(13): truncated value with size 32 to match size of target (21)" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 13 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1649242562656 "|spectrum|debouncer:debounce_turbo"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562658 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562713 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562714 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242562714 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562768 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562768 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562769 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562814 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562815 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562860 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562860 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562860 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 207 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562864 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562868 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562870 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242562870 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562921 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562921 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562922 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242562966 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242562966 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562967 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562973 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562978 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242562978 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242562979 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242562979 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242563031 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242563031 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563031 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242563076 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242563076 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563077 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242563120 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242563120 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563121 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242563165 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242563165 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563165 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 258 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563168 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 148 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563172 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563201 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563205 ""} } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242563205 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242563256 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242563256 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563257 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 321 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563259 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563261 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563270 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242563274 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563275 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242563275 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242563324 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242563324 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563325 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563326 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563327 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563329 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563331 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563332 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563333 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 365 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563336 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563339 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563340 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563341 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563356 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563358 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563360 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563361 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563363 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563364 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563365 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563366 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563367 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563368 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563369 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563370 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563371 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563372 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563373 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563374 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563376 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563377 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563378 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563379 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563380 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563381 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563383 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563398 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563400 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563401 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563402 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563403 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563407 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563407 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563408 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563409 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563410 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563411 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242563412 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1649242568495 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] sdram_read_request " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"sdram_read_request\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal5 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal5\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal5 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal5\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568601 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1649242568601 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242568607 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1649242568607 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1649242568633 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1649242568633 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242572088 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242572088 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242572088 "|spectrum|DRAM_CS_N"} { "Warning" "WMLS_MLS_STUCK_PIN" "kempston_gnd GND " "Pin \"kempston_gnd\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 36 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242572088 "|spectrum|kempston_gnd"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1649242572088 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1649242572497 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1649242576275 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1649242576367 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1649242576642 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242576642 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242576917 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242576917 "|spectrum|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242576917 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1649242576917 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "3146 " "Implemented 3146 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Implemented 18 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1649242576917 ""} { "Info" "ICUT_CUT_TM_OPINS" "84 " "Implemented 84 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1649242576917 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1649242576917 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2960 " "Implemented 2960 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1649242576917 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1649242576917 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1649242576917 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1649242576917 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 117 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 117 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242576939 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:56:16 2022 " "Processing ended: Wed Apr 6 13:56:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242576939 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242576939 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242576939 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242576939 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242578327 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242578328 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:56:17 2022 " "Processing started: Wed Apr 6 13:56:17 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242578328 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1649242578328 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1649242578328 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1649242578353 ""} +{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1649242578353 ""} +{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1649242578354 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1649242578455 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1649242578473 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1649242578519 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1649242578520 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1649242578520 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242578587 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1277 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242578587 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1649242578587 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242578588 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1245 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242578588 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1246 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242578588 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1649242578588 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1649242578679 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1649242578692 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1649242578915 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1649242578915 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1649242578915 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1649242578915 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5987 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242578922 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5989 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242578922 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5991 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242578922 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5993 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242578922 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5995 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242578922 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1649242578922 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1649242578926 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1649242578933 ""} +{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 12000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 12000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 15489 " "The value of the parameter \"Min Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 15489" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 26455 " "The value of the parameter \"Max Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 26455" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242579600 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} { 0 { 0 ""} 0 1276 9662 10382 0} } } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1649242579600 ""} +{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 258 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1649242579620 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1649242580299 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580308 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580308 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1649242580308 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580310 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580310 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580310 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580310 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580310 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1649242580310 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580311 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580311 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1649242580311 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1649242580311 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580312 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580312 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580312 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580312 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242580312 ""} +{ "Warning" "WSTA_SCC_LOOP" "518 " "Found combinational loop of 518 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|combout " "Node \"z80_\|bus_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datab " "Node \"z80_\|alu_\|db_high\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|combout " "Node \"z80_\|alu_\|db_high\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datab " "Node \"z80_\|alu_\|db_high\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datab " "Node \"z80_\|alu_\|db_high\[3\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|datab " "Node \"z80_\|alu_\|db_high\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datab " "Node \"z80_\|alu_control_\|db\[3\]~34\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|datab " "Node \"z80_\|bus_control_\|db\[3\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|combout " "Node \"z80_\|bus_control_\|db\[3\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|datab " "Node \"z80_\|alu_control_\|db\[3\]~33\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|combout " "Node \"z80_\|alu_control_\|db\[3\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datac " "Node \"z80_\|alu_\|db_low\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|combout " "Node \"z80_\|alu_\|db_low\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datab " "Node \"z80_\|alu_\|db_low\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|datab " "Node \"z80_\|alu_control_\|db\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|combout " "Node \"z80_\|alu_control_\|db\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|datab " "Node \"z80_\|bus_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|combout " "Node \"z80_\|bus_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|dataa " "Node \"z80_\|bus_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|combout " "Node \"z80_\|bus_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datab " "Node \"z80_\|alu_control_\|db\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datab " "Node \"z80_\|alu_\|db_low\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datab " "Node \"z80_\|alu_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datab " "Node \"z80_\|bus_control_\|db\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|combout " "Node \"z80_\|bus_control_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datab " "Node \"z80_\|alu_control_\|db\[2\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datab " "Node \"z80_\|alu_\|db_low\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|datac " "Node \"z80_\|alu_control_\|db\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|datab " "Node \"z80_\|bus_control_\|db\[1\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|combout " "Node \"z80_\|bus_control_\|db\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datab " "Node \"z80_\|alu_control_\|db\[1\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datab " "Node \"z80_\|alu_\|db_low\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|combout " "Node \"z80_\|alu_\|db_low\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|combout " "Node \"z80_\|alu_control_\|db\[4\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datad " "Node \"z80_\|alu_control_\|db\[4\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|datab " "Node \"z80_\|bus_control_\|db\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|combout " "Node \"z80_\|bus_control_\|db\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datab " "Node \"z80_\|alu_\|db_low\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datac " "Node \"z80_\|alu_\|db_low\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|datac " "Node \"z80_\|alu_control_\|db\[4\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datab " "Node \"z80_\|alu_control_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|datab " "Node \"z80_\|bus_control_\|db\[5\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|datac " "Node \"z80_\|alu_control_\|db\[6\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|datab " "Node \"z80_\|bus_control_\|db\[6\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datab " "Node \"z80_\|alu_control_\|db\[6\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datac " "Node \"z80_\|alu_control_\|db\[7\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|datab " "Node \"z80_\|bus_control_\|db\[7\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|combout " "Node \"z80_\|bus_control_\|db\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|combout " "Node \"z80_\|bus_control_\|db\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datab " "Node \"z80_\|alu_control_\|db\[7\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datac " "Node \"z80_\|alu_control_\|db\[5\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datac " "Node \"z80_\|alu_\|db_low\[2\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datac " "Node \"z80_\|alu_\|db_low\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242580319 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 36 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 35 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1649242580319 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "518 " "Design contains combinational loop of 518 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1649242580336 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242580370 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242580370 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242580370 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242580370 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1649242580386 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1649242580388 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242580388 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1649242580388 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580595 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debouncer:debounce_turbo\|r_State " "Destination node debouncer:debounce_turbo\|r_State" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 8 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { debouncer:debounce_turbo|r_State } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1539 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580595 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debouncer:debounce_autofire\|r_State " "Destination node debouncer:debounce_autofire\|r_State" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 8 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { debouncer:debounce_autofire|r_State } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1878 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580595 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242580595 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5970 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580595 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580595 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580595 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2559 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1242 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4480 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 44 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1568 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4514 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4487 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4488 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4489 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4490 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4491 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4492 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4493 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4494 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4495 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242580596 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242580596 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 688 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580596 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580597 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 928 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580597 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242580597 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 758 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242580597 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1649242581474 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1649242581478 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1649242581478 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1649242581483 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1649242581488 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1649242581492 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1649242581492 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1649242581495 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1649242582355 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1649242582359 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1649242582359 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1649242582359 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242582514 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1649242582514 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242582516 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1649242584077 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242584981 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1649242585004 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1649242588424 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242588424 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1649242589375 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.4% " "7e+02 ns of routing delay (approximately 1.4% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1649242592000 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1649242592689 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1649242592689 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:07 " "Fitter routing operations ending: elapsed time is 00:00:07" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242596433 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1649242596436 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1649242596436 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.08 " "Total time spent on timing analysis during the Fitter is 2.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1649242596589 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1649242596650 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1649242597485 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1649242597538 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1649242598300 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242599575 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1649242600167 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "64 Cyclone IV E " "64 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 169 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 170 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 171 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 176 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 177 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 178 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 184 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 185 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 186 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 229 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 230 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 192 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 194 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 195 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 197 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 199 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 201 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 203 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 205 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 206 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 207 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 22 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 240 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[0\] 3.3-V LVTTL B4 " "Pin kempston\[0\] uses I/O standard 3.3-V LVTTL at B4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 221 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[1\] 3.3-V LVTTL A4 " "Pin kempston\[1\] uses I/O standard 3.3-V LVTTL at A4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 222 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[2\] 3.3-V LVTTL B5 " "Pin kempston\[2\] uses I/O standard 3.3-V LVTTL at B5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 223 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[3\] 3.3-V LVTTL A5 " "Pin kempston\[3\] uses I/O standard 3.3-V LVTTL at A5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 224 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[4\] 3.3-V LVTTL D5 " "Pin kempston\[4\] uses I/O standard 3.3-V LVTTL at D5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 225 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 138 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 226 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "turbo_button 3.3-V LVTTL J13 " "Pin turbo_button uses I/O standard 3.3-V LVTTL at J13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { turbo_button } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "turbo_button" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 37 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { turbo_button } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 248 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston_autofire_button 3.3-V LVTTL J14 " "Pin kempston_autofire_button uses I/O standard 3.3-V LVTTL at J14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston_autofire_button } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston_autofire_button" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 40 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston_autofire_button } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 249 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 228 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 139 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 227 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 236 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242600187 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1649242600187 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1649242600566 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 575 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 575 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "637 " "Peak virtual memory: 637 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242601423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:56:41 2022 " "Processing ended: Wed Apr 6 13:56:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242601423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Elapsed time: 00:00:24" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242601423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242601423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1649242601423 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1649242602983 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242602984 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:56:42 2022 " "Processing started: Wed Apr 6 13:56:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242602984 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1649242602984 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1649242602984 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1649242604193 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1649242604222 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "387 " "Peak virtual memory: 387 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242604537 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:56:44 2022 " "Processing ended: Wed Apr 6 13:56:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242604537 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242604537 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242604537 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1649242604537 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1649242604835 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1649242606062 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:56:45 2022 " "Processing started: Wed Apr 6 13:56:45 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242606062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1649242606062 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1649242606063 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1649242606090 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1649242606300 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1649242606301 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1649242606351 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1649242606351 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1649242606796 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606806 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606806 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1649242606806 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606807 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606807 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606807 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606807 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606807 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606807 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606808 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606808 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1649242606808 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1649242606808 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606809 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606809 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606810 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606810 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242606810 ""} +{ "Warning" "WSTA_SCC_LOOP" "518 " "Found combinational loop of 518 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datad " "Node \"z80_\|alu_\|db_high\[3\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datad " "Node \"z80_\|alu_\|db_high\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|combout " "Node \"z80_\|alu_\|db_low\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datad " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datac " "Node \"z80_\|alu_\|db\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|datac " "Node \"z80_\|alu_control_\|db\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datab " "Node \"z80_\|alu_control_\|db\[1\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|combout " "Node \"z80_\|bus_control_\|db\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|datab " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datac " "Node \"z80_\|alu_\|db\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datac " "Node \"z80_\|alu_\|db_low\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datac " "Node \"z80_\|alu_\|db_low\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datad " "Node \"z80_\|alu_\|db_low\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datac " "Node \"z80_\|alu_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datad " "Node \"z80_\|bus_control_\|db\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|datab " "Node \"z80_\|bus_control_\|db\[2\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|combout " "Node \"z80_\|bus_control_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|datac " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datad " "Node \"z80_\|alu_\|db\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datad " "Node \"z80_\|alu_control_\|db\[2\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datad " "Node \"z80_\|alu_\|db_low\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datad " "Node \"z80_\|alu_\|db_low\[3\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datac " "Node \"z80_\|alu_\|db_low\[3\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datad " "Node \"z80_\|alu_\|db_low\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datac " "Node \"z80_\|alu_\|db\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datab " "Node \"z80_\|alu_\|db_high\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datac " "Node \"z80_\|alu_\|db\[4\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datad " "Node \"z80_\|alu_\|db_high\[1\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datad " "Node \"z80_\|alu_\|db\[5\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|datac " "Node \"z80_\|alu_\|db_high\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|combout " "Node \"z80_\|alu_\|db_high\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datab " "Node \"z80_\|alu_\|db_high\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datad " "Node \"z80_\|alu_\|db_high\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datab " "Node \"z80_\|alu_control_\|db\[6\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|datab " "Node \"z80_\|bus_control_\|db\[6\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|datac " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|datad " "Node \"z80_\|alu_control_\|db\[6\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datac " "Node \"z80_\|alu_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datad " "Node \"z80_\|alu_control_\|db\[5\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datad " "Node \"z80_\|alu_control_\|db\[5\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|datad " "Node \"z80_\|bus_control_\|db\[5\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|combout " "Node \"z80_\|bus_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datad " "Node \"z80_\|alu_\|db_high\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datac " "Node \"z80_\|alu_\|db_low\[3\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datac " "Node \"z80_\|alu_\|db_low\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|datad " "Node \"z80_\|alu_\|db_low\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|combout " "Node \"z80_\|alu_\|db_low\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datac " "Node \"z80_\|alu_\|db_low\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datab " "Node \"z80_\|alu_control_\|db\[5\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datad " "Node \"z80_\|alu_\|db_low\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datad " "Node \"z80_\|alu_\|db\[5\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datad " "Node \"z80_\|alu_\|db\[4\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|datab " "Node \"z80_\|alu_control_\|db\[4\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|combout " "Node \"z80_\|alu_control_\|db\[4\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datab " "Node \"z80_\|alu_control_\|db\[4\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datab " "Node \"z80_\|alu_control_\|db\[4\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|datab " "Node \"z80_\|bus_control_\|db\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|combout " "Node \"z80_\|bus_control_\|db\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datad " "Node \"z80_\|alu_\|db_high\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datad " "Node \"z80_\|alu_\|db_low\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datad " "Node \"z80_\|alu_\|db_low\[2\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datad " "Node \"z80_\|alu_\|db_high\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datad " "Node \"z80_\|alu_\|db_low\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datad " "Node \"z80_\|alu_\|db_low\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|datab " "Node \"z80_\|bus_control_\|db\[3\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|combout " "Node \"z80_\|bus_control_\|db\[3\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|datab " "Node \"z80_\|alu_control_\|db\[3\]~33\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|combout " "Node \"z80_\|alu_control_\|db\[3\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datab " "Node \"z80_\|alu_\|db_low\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datad " "Node \"z80_\|alu_\|db\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datab " "Node \"z80_\|alu_control_\|db\[3\]~34\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datab " "Node \"z80_\|alu_\|db_low\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datac " "Node \"z80_\|alu_\|db\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|datac " "Node \"z80_\|alu_control_\|db\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|combout " "Node \"z80_\|alu_control_\|db\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|datab " "Node \"z80_\|bus_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|combout " "Node \"z80_\|bus_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|datac " "Node \"z80_\|bus_control_\|db\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|combout " "Node \"z80_\|bus_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|datac " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datad " "Node \"z80_\|alu_control_\|db\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datad " "Node \"z80_\|alu_\|db_high\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datac " "Node \"z80_\|alu_control_\|db\[7\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datad " "Node \"z80_\|alu_control_\|db\[7\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|datad " "Node \"z80_\|bus_control_\|db\[7\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|combout " "Node \"z80_\|bus_control_\|db\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|datac " "Node \"z80_\|bus_control_\|db\[7\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|combout " "Node \"z80_\|bus_control_\|db\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|datab " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datad " "Node \"z80_\|alu_control_\|db\[7\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242606817 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 36 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 35 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1649242606817 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "518 " "Design contains combinational loop of 518 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1649242606833 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242606864 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242606864 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242606864 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242606864 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1649242606997 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1649242607000 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1649242607029 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1649242607082 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1649242607082 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.476 " "Worst-case setup slack is -18.476" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.476 -808.800 CLOCK_50 " " -18.476 -808.800 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.513 -282.972 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.513 -282.972 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.734 -42.279 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.734 -42.279 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 70.299 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 70.299 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242607082 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.344 " "Worst-case hold slack is 0.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.382 0.000 CLOCK_50 " " 0.382 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242607090 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.210 " "Worst-case recovery slack is -6.210" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.210 -460.961 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.210 -460.961 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607091 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242607091 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.689 " "Worst-case removal slack is 3.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.689 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.689 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607092 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242607092 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.490 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.490 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242607093 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1649242607265 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1649242607304 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1649242608317 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242608494 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242608494 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242608494 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242608494 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608497 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1649242608520 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1649242608520 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.646 " "Worst-case setup slack is -17.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.646 -768.789 CLOCK_50 " " -17.646 -768.789 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.953 -254.832 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.953 -254.832 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -39.535 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.416 -39.535 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.951 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.951 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 70.438 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 70.438 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242608524 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.300 " "Worst-case hold slack is 0.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.312 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.333 0.000 CLOCK_50 " " 0.333 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242608535 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.734 " "Worst-case recovery slack is -5.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608539 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608539 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.734 -425.150 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.734 -425.150 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608539 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242608539 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.370 " "Worst-case removal slack is 3.370" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608543 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608543 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.370 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.370 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608543 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242608543 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.589 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.589 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.487 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.487 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242608547 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1649242608761 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242609077 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242609077 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242609077 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242609077 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609080 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1649242609089 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1649242609089 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.170 " "Worst-case setup slack is -15.170" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.170 -635.207 CLOCK_50 " " -15.170 -635.207 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.647 -193.116 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -5.647 -193.116 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.810 -35.303 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.810 -35.303 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.131 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.131 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 70.800 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 70.800 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242609096 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.179 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.201 0.000 CLOCK_50 " " 0.201 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242609110 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.684 " "Worst-case recovery slack is -4.684" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.684 -359.024 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.684 -359.024 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609119 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242609119 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.507 " "Worst-case removal slack is 2.507" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609127 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609127 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609127 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242609127 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.784 " "Worst-case minimum pulse width slack is 4.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.525 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.525 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242609134 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1649242609878 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1649242609878 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 545 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 545 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "437 " "Peak virtual memory: 437 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242610158 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:56:50 2022 " "Processing ended: Wed Apr 6 13:56:50 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242610158 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242610158 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242610158 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242610158 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242612075 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242612075 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:56:51 2022 " "Processing started: Wed Apr 6 13:56:51 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242612075 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1649242612075 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1649242612076 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242613075 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242613438 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242613802 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242614169 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242614461 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242614747 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242615032 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242615319 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242615427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:56:55 2022 " "Processing ended: Wed Apr 6 13:56:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242615427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242615427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242615427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242615427 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1237 s " "Quartus II Full Compilation was successful. 0 errors, 1237 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242615618 ""} diff --git a/db/sld_ela_trigger_cso.tdf b/db/sld_ela_trigger_cso.tdf new file mode 100644 index 0000000..825dd76 --- /dev/null +++ b/db/sld_ela_trigger_cso.tdf @@ -0,0 +1,55 @@ +--sld_ela_trigger DATA_BITS=12 INVERSION_MASK=00000000 INVERSION_MASK_LENGTH=1 LEVEL_NAMES="sld_reserved_spectrum_auto_signaltap_0_1_eb98," POWER_UP_TRIGGER=0 TRIGGER_LEVEL=1 acq_clk data_in reset_all setup_bit_in setup_bit_out setup_ena tck trigger_level_match_out +--VERSION_BEGIN 13.1 cbx_mgl 2013:10:17:09:48:49:SJ cbx_sld_ela_trigger 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION sld_reserved_spectrum_auto_signaltap_0_1_eb98 (acq_clk, data_in[11..0], reset_all, setup_bit_in, setup_ena, tck) +WITH ( ASYNC_ENABLED, DATA_BITS, SYNC_ENABLED, TRIGGER_LEVEL) +RETURNS ( setup_bit_out, trigger); + +--synthesis_resources = sld_reserved_spectrum_auto_signaltap_0_1_eb98 1 +SUBDESIGN sld_ela_trigger_cso +( + acq_clk : input; + data_in[11..0] : input; + reset_all : input; + setup_bit_in : input; + setup_bit_out : output; + setup_ena : input; + tck : input; + trigger_level_match_out[0..0] : output; +) +VARIABLE + mgl_prim1 : sld_reserved_spectrum_auto_signaltap_0_1_eb98 + WITH ( + ASYNC_ENABLED = 0, + DATA_BITS = 12, + SYNC_ENABLED = 0, + TRIGGER_LEVEL = 1 + ); + +BEGIN + mgl_prim1.acq_clk = acq_clk; + mgl_prim1.data_in[] = data_in[]; + mgl_prim1.reset_all = reset_all; + mgl_prim1.setup_bit_in = setup_bit_in; + mgl_prim1.setup_ena = setup_ena; + mgl_prim1.tck = tck; + setup_bit_out = mgl_prim1.setup_bit_out; + trigger_level_match_out[] = ( mgl_prim1.trigger); +END; +--VALID FILE diff --git a/db/sld_reserved_spectrum_auto_signaltap_0_1_eb98.v b/db/sld_reserved_spectrum_auto_signaltap_0_1_eb98.v new file mode 100644 index 0000000..0aa2ba7 Binary files /dev/null and b/db/sld_reserved_spectrum_auto_signaltap_0_1_eb98.v differ diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index 4bd46bb..b12affb 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index afee0b5..e96f6bb 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.(1).cnf.cdb b/db/spectrum.(1).cnf.cdb index 384073a..7c935a8 100644 Binary files a/db/spectrum.(1).cnf.cdb and b/db/spectrum.(1).cnf.cdb differ diff --git a/db/spectrum.(1).cnf.hdb b/db/spectrum.(1).cnf.hdb index 5ce7543..066be78 100644 Binary files a/db/spectrum.(1).cnf.hdb and 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file mode 100644 index 0000000..b29e6c8 Binary files /dev/null and b/db/spectrum.(99).cnf.cdb differ diff --git a/db/spectrum.(99).cnf.hdb b/db/spectrum.(99).cnf.hdb new file mode 100644 index 0000000..91d9706 Binary files /dev/null and b/db/spectrum.(99).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index 1efcd5f..c13cfab 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900269993 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:09 2022 " "Processing started: Sat Apr 2 14:51:09 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648900271169 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648900271197 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:11 2022 " "Processing ended: Sat Apr 2 14:51:11 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648900271509 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242697905 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242697906 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:58:17 2022 " "Processing started: Wed Apr 6 13:58:17 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242697906 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1649242697906 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1649242697907 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1649242699125 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1649242699154 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "387 " "Peak virtual memory: 387 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242699474 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:58:19 2022 " "Processing ended: Wed Apr 6 13:58:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242699474 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242699474 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242699474 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1649242699474 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index 89f0c36..bf18b98 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index 779674f..08f6e4c 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.autoh_e40e1.map.reg_db.cdb b/db/spectrum.autoh_e40e1.map.reg_db.cdb new file mode 100644 index 0000000..2dc683d Binary files /dev/null and b/db/spectrum.autoh_e40e1.map.reg_db.cdb differ diff --git a/db/spectrum.autos_3e921.map.reg_db.cdb b/db/spectrum.autos_3e921.map.reg_db.cdb new file mode 100644 index 0000000..764fe06 Binary files /dev/null and b/db/spectrum.autos_3e921.map.reg_db.cdb differ diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index d979dcc..1555c01 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index b0c9443..e4373b0 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index e0a5d80..5526819 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index c595e18..83fb2a3 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.logdb b/db/spectrum.cmp.logdb index c9b0d34..cf74e81 100644 --- a/db/spectrum.cmp.logdb +++ b/db/spectrum.cmp.logdb @@ -12,17 +12,17 @@ IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,PASS,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,0 such failures found.,,I/O,, IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,PASS,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,PASS,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,, -IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, @@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,114;29;114;0;0;114;114;0;114;114;0;0;0;0;57;0;0;57;0;0;10;0;0;0;0;0;0;114;0;0, +IO_RULES_MATRIX,Total Pass,120;29;120;0;0;120;120;0;120;120;0;0;0;7;64;0;0;64;7;0;10;0;0;0;0;0;0;120;0;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,0;85;0;114;114;0;0;114;0;0;114;114;114;114;57;114;114;57;114;114;104;114;114;114;114;114;114;0;114;114, +IO_RULES_MATRIX,Total Inapplicable,0;91;0;120;120;0;0;120;0;0;120;120;120;113;56;120;120;56;113;120;110;120;120;120;120;120;120;0;120;120, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, @@ -62,6 +62,7 @@ IO_RULES_MATRIX,VGA_B[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;P IO_RULES_MATRIX,VGA_HS,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,VGA_VS,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,GPIO_1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,GPIO_1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, @@ -95,8 +96,6 @@ IO_RULES_MATRIX,GPIO_1[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass IO_RULES_MATRIX,GPIO_1[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,GPIO_1[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,GPIO_1[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,GPIO_1[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,buzzer_out,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,DRAM_BA[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,DRAM_BA[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, @@ -121,6 +120,7 @@ IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass; IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,DRAM_ADDR[12],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston_gnd,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,I2C_SCLK,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,I2C_SDAT,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,DRAM_DQ[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, @@ -140,16 +140,22 @@ IO_RULES_MATRIX,DRAM_DQ[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pas IO_RULES_MATRIX,DRAM_DQ[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,DRAM_DQ[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,raw_loader_in,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,turbo_button,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,kempston_autofire_button,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,PS2_DAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,PS2_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,AUD_ADCDAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,30, -IO_RULES_SUMMARY,Number of I/O Rules Passed,11, +IO_RULES_SUMMARY,Number of I/O Rules Passed,13, IO_RULES_SUMMARY,Number of I/O Rules Failed,0, IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,17, diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 4536bbc..36e430f 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd index ff393bd..19d3e57 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd index 3a5105f..f6e2a56 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd index 2f59583..132cd4e 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/db/spectrum.db_info b/db/spectrum.db_info index cf5f9fd..e3c7a4b 100644 --- a/db/spectrum.db_info +++ b/db/spectrum.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Version_Index = 318808576 -Creation_Time = Sat Apr 2 13:37:52 2022 +Creation_Time = Wed Apr 6 13:46:32 2022 diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index 6331e6f..3ab1c43 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900279498 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:19 2022 " "Processing started: Sat Apr 2 14:51:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280426 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280767 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281107 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281449 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281719 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281988 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282253 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282522 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:22 2022 " "Processing ended: Sat Apr 2 14:51:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242706812 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242706813 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:58:26 2022 " "Processing started: Wed Apr 6 13:58:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242706813 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1649242706813 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1649242706813 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242707796 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242708169 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242708530 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242708893 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242709181 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242709466 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242709750 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1649242710036 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242710140 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:58:30 2022 " "Processing ended: Wed Apr 6 13:58:30 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242710140 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242710140 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242710140 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242710140 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index 1afde46..169b6c9 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,77 +1,79 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648900247191 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648900247208 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648900247247 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648900247248 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648900247248 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247311 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1256 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247311 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648900247311 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247312 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247312 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1225 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247312 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648900247312 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648900247395 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648900247407 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648900247623 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648900247623 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648900247623 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648900247623 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5702 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5704 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5706 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5708 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5710 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648900247630 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648900247633 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648900247640 ""} -{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 12000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 12000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 15489 " "The value of the parameter \"Min Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 15489" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 26455 " "The value of the parameter \"Max Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 26455" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} { 0 { 0 ""} 0 1255 9662 10382 0} } } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1648900248191 ""} -{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1648900248210 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648900248866 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248875 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248875 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648900248875 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648900248877 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248878 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248878 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648900248878 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648900248878 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} -{ "Warning" "WSTA_SCC_LOOP" "513 " "Found combinational loop of 513 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~33\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|combout " "Node \"z80_\|alu_control_\|db\[4\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datac " "Node \"z80_\|alu_control_\|db\[4\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|datad " "Node \"z80_\|alu_control_\|db\[4\]~33\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datab " "Node \"z80_\|alu_\|db_high\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|combout " "Node \"z80_\|alu_\|db_high\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|datab " "Node \"z80_\|alu_control_\|db\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|combout " "Node \"z80_\|alu_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|datac " "Node \"z80_\|alu_control_\|db\[5\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|combout " "Node \"z80_\|alu_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datab " "Node \"z80_\|alu_\|db_high\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|combout " "Node \"z80_\|alu_\|db_high\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datab " "Node \"z80_\|alu_\|db_high\[3\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datac " "Node \"z80_\|alu_control_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|combout " "Node \"z80_\|alu_control_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[6\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datab " "Node \"z80_\|alu_control_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datac " "Node \"z80_\|alu_\|db_low\[0\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|combout " "Node \"z80_\|alu_\|db_low\[0\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|combout " "Node \"z80_\|alu_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|combout " "Node \"z80_\|alu_control_\|db\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datac " "Node \"z80_\|alu_control_\|db\[0\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|datab " "Node \"z80_\|alu_control_\|db\[0\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|combout " "Node \"z80_\|alu_control_\|db\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datab " "Node \"z80_\|alu_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|datab " "Node \"z80_\|alu_\|db_low\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|combout " "Node \"z80_\|alu_\|db_low\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|combout " "Node \"z80_\|alu_\|db_low\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|datab " "Node \"z80_\|alu_\|db_low\[1\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|combout " "Node \"z80_\|alu_\|db_low\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|combout " "Node \"z80_\|alu_\|db_low\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datab " "Node \"z80_\|alu_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|datac " "Node \"z80_\|alu_\|db_low\[3\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|combout " "Node \"z80_\|alu_\|db_low\[3\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datab " "Node \"z80_\|alu_\|db_high\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|datab " "Node \"z80_\|alu_control_\|db\[3\]~36\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|combout " "Node \"z80_\|alu_control_\|db\[3\]~36\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datac " "Node \"z80_\|alu_\|db_low\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|combout " "Node \"z80_\|alu_\|db_low\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datad " "Node \"z80_\|alu_\|db_low\[0\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datac " "Node \"z80_\|alu_\|db_high\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~36\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datab " "Node \"z80_\|alu_\|db_low\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|combout " "Node \"z80_\|alu_\|db_low\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|datac " "Node \"z80_\|alu_\|db_low\[2\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datab " "Node \"z80_\|alu_\|db_low\[3\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datac " "Node \"z80_\|alu_control_\|db\[2\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|datac " "Node \"z80_\|alu_control_\|db\[2\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|combout " "Node \"z80_\|alu_control_\|db\[2\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|datad " "Node \"z80_\|alu_control_\|db\[2\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|datab " "Node \"z80_\|alu_\|db_low\[1\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datac " "Node \"z80_\|alu_control_\|db\[1\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|datab " "Node \"z80_\|alu_control_\|db\[1\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|combout " "Node \"z80_\|alu_control_\|db\[1\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datab " "Node \"z80_\|alu_control_\|db\[1\]~26\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datad " "Node \"z80_\|alu_control_\|db\[7\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|datad " "Node \"z80_\|alu_control_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|combout " "Node \"z80_\|alu_control_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|datad " "Node \"z80_\|alu_control_\|db\[7\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|combout " "Node \"z80_\|alu_control_\|db\[7\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datab " "Node \"z80_\|alu_control_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datac " "Node \"z80_\|alu_\|db_low\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datac " "Node \"z80_\|alu_\|db_low\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datab " "Node \"z80_\|alu_\|db_high\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datac " "Node \"z80_\|alu_\|db_low\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datac " "Node \"z80_\|alu_\|db_high\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648900248886 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "513 " "Design contains combinational loop of 513 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648900248903 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648900248934 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648900248934 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648900248949 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648900248951 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648900248951 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249144 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5687 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249144 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2863 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4204 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 73 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1499 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4239 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4212 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4213 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4214 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4215 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4216 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4217 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4218 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4219 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4220 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 675 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249146 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 912 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249146 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249146 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 747 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249146 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648900249996 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648900250000 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648900250000 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648900250004 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648900250009 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648900250013 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648900250013 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648900250016 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648900250850 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648900250854 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648900250854 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648900250854 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648900251001 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900251003 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648900252550 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900253381 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648900253404 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648900256519 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900256519 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648900257442 ""} -{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.5% " "7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648900259807 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648900260438 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648900260438 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900263821 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648900263823 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648900263823 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.84 " "Total time spent on timing analysis during the Fitter is 1.84 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648900263969 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648900264030 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648900264828 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648900264880 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648900265610 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900266817 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648900267295 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "57 Cyclone IV E " "57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 169 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 170 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 171 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 176 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 223 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 224 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 191 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 192 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 194 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 195 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 197 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 199 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 201 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 203 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 205 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 206 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 22 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 234 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 135 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 220 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 222 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 136 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 221 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 230 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648900267314 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648900267670 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 574 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 574 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "641 " "Peak virtual memory: 641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900268503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:08 2022 " "Processing ended: Sat Apr 2 14:51:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900268503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900268503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900268503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648900268503 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1649242673339 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1649242673357 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1649242673403 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1649242673404 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1649242673404 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242673471 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1277 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242673471 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1649242673471 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242673473 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1245 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242673473 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1246 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1649242673473 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1649242673473 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1649242673561 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1649242673574 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1649242673797 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1649242673797 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1649242673797 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1649242673797 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5987 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242673804 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5989 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242673804 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5991 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242673804 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5993 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242673804 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5995 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1649242673804 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1649242673804 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1649242673807 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1649242673814 ""} +{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 12000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 12000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 15489 " "The value of the parameter \"Min Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 15489" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 26455 " "The value of the parameter \"Max Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 26455" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1649242674473 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} { 0 { 0 ""} 0 1276 9662 10382 0} } } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1649242674473 ""} +{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 258 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1649242674494 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1649242675174 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675183 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675183 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1649242675183 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675185 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675185 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675185 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675185 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675185 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1649242675185 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675186 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675186 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1649242675186 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1649242675186 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675187 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675187 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675187 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675187 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1649242675187 ""} +{ "Warning" "WSTA_SCC_LOOP" "518 " "Found combinational loop of 518 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|combout " "Node \"z80_\|bus_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datab " "Node \"z80_\|alu_\|db_high\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|combout " "Node \"z80_\|alu_\|db_high\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datab " "Node \"z80_\|alu_\|db_high\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datab " "Node \"z80_\|alu_\|db_high\[3\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|datab " "Node \"z80_\|alu_\|db_high\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datab " "Node \"z80_\|alu_control_\|db\[3\]~34\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|datab " "Node \"z80_\|bus_control_\|db\[3\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|combout " "Node \"z80_\|bus_control_\|db\[3\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|datab " "Node \"z80_\|alu_control_\|db\[3\]~33\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|combout " "Node \"z80_\|alu_control_\|db\[3\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datac " "Node \"z80_\|alu_\|db_low\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|combout " "Node \"z80_\|alu_\|db_low\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datab " "Node \"z80_\|alu_\|db_low\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|datab " "Node \"z80_\|alu_control_\|db\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|combout " "Node \"z80_\|alu_control_\|db\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|datab " "Node \"z80_\|bus_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|combout " "Node \"z80_\|bus_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|dataa " "Node \"z80_\|bus_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|combout " "Node \"z80_\|bus_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datab " "Node \"z80_\|alu_control_\|db\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datab " "Node \"z80_\|alu_\|db_low\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datab " "Node \"z80_\|alu_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datab " "Node \"z80_\|bus_control_\|db\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|combout " "Node \"z80_\|bus_control_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datab " "Node \"z80_\|alu_control_\|db\[2\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datab " "Node \"z80_\|alu_\|db_low\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|datac " "Node \"z80_\|alu_control_\|db\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|datab " "Node \"z80_\|bus_control_\|db\[1\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|combout " "Node \"z80_\|bus_control_\|db\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datab " "Node \"z80_\|alu_control_\|db\[1\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datab " "Node \"z80_\|alu_\|db_low\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|combout " "Node \"z80_\|alu_\|db_low\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|combout " "Node \"z80_\|alu_control_\|db\[4\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datad " "Node \"z80_\|alu_control_\|db\[4\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|datab " "Node \"z80_\|bus_control_\|db\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|combout " "Node \"z80_\|bus_control_\|db\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datab " "Node \"z80_\|alu_\|db_low\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datac " "Node \"z80_\|alu_\|db_low\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|datac " "Node \"z80_\|alu_control_\|db\[4\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datab " "Node \"z80_\|alu_control_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|datab " "Node \"z80_\|bus_control_\|db\[5\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|datac " "Node \"z80_\|alu_control_\|db\[6\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|datab " "Node \"z80_\|bus_control_\|db\[6\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datab " "Node \"z80_\|alu_control_\|db\[6\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datac " "Node \"z80_\|alu_control_\|db\[7\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|datab " "Node \"z80_\|bus_control_\|db\[7\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|combout " "Node \"z80_\|bus_control_\|db\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|combout " "Node \"z80_\|bus_control_\|db\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|dataa " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datab " "Node \"z80_\|alu_control_\|db\[7\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datac " "Node \"z80_\|alu_control_\|db\[5\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datac " "Node \"z80_\|alu_\|db_low\[2\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datac " "Node \"z80_\|alu_\|db_low\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242675194 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 36 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 35 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1649242675194 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "518 " "Design contains combinational loop of 518 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1649242675211 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242675244 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242675244 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242675244 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1649242675244 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1649242675259 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1649242675261 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1649242675262 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1649242675262 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675468 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debouncer:debounce_turbo\|r_State " "Destination node debouncer:debounce_turbo\|r_State" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 8 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { debouncer:debounce_turbo|r_State } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1539 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675468 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debouncer:debounce_autofire\|r_State " "Destination node debouncer:debounce_autofire\|r_State" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 8 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { debouncer:debounce_autofire|r_State } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1878 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675468 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242675468 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5970 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675468 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1276 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1244 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2559 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1242 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4480 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242675469 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 44 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1568 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675469 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4514 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4487 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4488 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4489 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4490 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4491 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4492 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4493 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4494 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4495 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1649242675470 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1649242675470 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 688 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675470 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 928 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675470 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1649242675470 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 758 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1649242675470 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1649242676349 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1649242676353 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1649242676354 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1649242676358 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1649242676364 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1649242676367 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1649242676367 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1649242676371 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1649242677236 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1649242677240 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1649242677240 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1649242677240 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1649242677395 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1649242677395 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242677397 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1649242678963 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242679867 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1649242679890 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1649242683311 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242683311 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1649242684260 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.4% " "7e+02 ns of routing delay (approximately 1.4% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1649242686877 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1649242687552 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1649242687552 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:07 " "Fitter routing operations ending: elapsed time is 00:00:07" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242691324 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1649242691326 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1649242691326 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.06 " "Total time spent on timing analysis during the Fitter is 2.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1649242691482 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1649242691545 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1649242692381 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1649242692434 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1649242693197 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1649242694482 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1649242695082 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "64 Cyclone IV E " "64 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 169 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 170 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 171 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 176 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 177 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 178 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 184 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 185 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 186 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 229 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 230 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 192 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 194 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 195 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 197 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 199 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 201 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 203 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 205 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 206 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 207 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 22 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 240 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[0\] 3.3-V LVTTL B4 " "Pin kempston\[0\] uses I/O standard 3.3-V LVTTL at B4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 221 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[1\] 3.3-V LVTTL A4 " "Pin kempston\[1\] uses I/O standard 3.3-V LVTTL at A4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 222 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[2\] 3.3-V LVTTL B5 " "Pin kempston\[2\] uses I/O standard 3.3-V LVTTL at B5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 223 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[3\] 3.3-V LVTTL A5 " "Pin kempston\[3\] uses I/O standard 3.3-V LVTTL at A5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 224 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston\[4\] 3.3-V LVTTL D5 " "Pin kempston\[4\] uses I/O standard 3.3-V LVTTL at D5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 35 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 225 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 138 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 226 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "turbo_button 3.3-V LVTTL J13 " "Pin turbo_button uses I/O standard 3.3-V LVTTL at J13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { turbo_button } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "turbo_button" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 37 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { turbo_button } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 248 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "kempston_autofire_button 3.3-V LVTTL J14 " "Pin kempston_autofire_button uses I/O standard 3.3-V LVTTL at J14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { kempston_autofire_button } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "kempston_autofire_button" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 40 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { kempston_autofire_button } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 249 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 228 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 139 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 227 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 236 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1649242695104 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1649242695104 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1649242695484 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 575 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 575 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "645 " "Peak virtual memory: 645 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242696338 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:58:16 2022 " "Processing ended: Wed Apr 6 13:58:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242696338 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Elapsed time: 00:00:24" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242696338 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242696338 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1649242696338 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index da0c20c..cafc7cd 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,90 +1,88 @@ |spectrum -LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE -LED[1] <= -LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE -LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE -LED[4] <= -LED[5] <= -LED[6] <= -LED[7] <= -CLOCK_50 => CLOCK_50.IN4 +LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE +LED[1] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE +LED[2] << turbo.DB_MAX_OUTPUT_PORT_TYPE +LED[3] << kempston[0].DB_MAX_OUTPUT_PORT_TYPE +LED[4] << kempston[1].DB_MAX_OUTPUT_PORT_TYPE +LED[5] << kempston[2].DB_MAX_OUTPUT_PORT_TYPE +LED[6] << kempston[3].DB_MAX_OUTPUT_PORT_TYPE +LED[7] << LED.DB_MAX_OUTPUT_PORT_TYPE +CLOCK_50 => CLOCK_50.IN6 KEY[0] => reset.IN1 KEY[1] => nNMI.IN1 PS2_CLK => PS2_CLK.IN1 PS2_DAT => PS2_DAT.IN1 I2C_SCLK <> ula:ula_.I2C_SCLK I2C_SDAT <> ula:ula_.I2C_SDAT -AUD_XCK <= ula:ula_.AUD_XCK -AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK -AUD_DACLRCK <= ula:ula_.AUD_DACLRCK -AUD_BCLK <= ula:ula_.AUD_BCLK -AUD_DACDAT <= ula:ula_.AUD_DACDAT +AUD_XCK << ula:ula_.AUD_XCK +AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK +AUD_DACLRCK << ula:ula_.AUD_DACLRCK +AUD_BCLK << ula:ula_.AUD_BCLK +AUD_DACDAT << ula:ula_.AUD_DACDAT AUD_ADCDAT => AUD_ADCDAT.IN1 -VGA_R[0] <= ula:ula_.VGA_R -VGA_R[1] <= ula:ula_.VGA_R -VGA_R[2] <= ula:ula_.VGA_R -VGA_R[3] <= ula:ula_.VGA_R -VGA_G[0] <= ula:ula_.VGA_G -VGA_G[1] <= ula:ula_.VGA_G -VGA_G[2] <= ula:ula_.VGA_G -VGA_G[3] <= ula:ula_.VGA_G -VGA_B[0] <= ula:ula_.VGA_B -VGA_B[1] <= ula:ula_.VGA_B -VGA_B[2] <= ula:ula_.VGA_B -VGA_B[3] <= ula:ula_.VGA_B -VGA_HS <= ula:ula_.VGA_HS -VGA_VS <= ula:ula_.VGA_VS +VGA_R[0] << ula:ula_.VGA_R +VGA_R[1] << ula:ula_.VGA_R +VGA_R[2] << ula:ula_.VGA_R +VGA_R[3] << ula:ula_.VGA_R +VGA_G[0] << ula:ula_.VGA_G +VGA_G[1] << ula:ula_.VGA_G +VGA_G[2] << ula:ula_.VGA_G +VGA_G[3] << ula:ula_.VGA_G +VGA_B[0] << ula:ula_.VGA_B +VGA_B[1] << ula:ula_.VGA_B +VGA_B[2] << ula:ula_.VGA_B +VGA_B[3] << ula:ula_.VGA_B +VGA_HS << ula:ula_.VGA_HS +VGA_VS << ula:ula_.VGA_VS SW[0] => ~NO_FANOUT~ SW[1] => LED[0].DATAIN SW[1] => comb.OUTPUTSELECT -SW[2] => SW[2].IN1 +SW[2] => ~NO_FANOUT~ SW[3] => ~NO_FANOUT~ -GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK -GPIO_1[25] <= z80_top_direct_n:z80_.nHALT -GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH -GPIO_1[27] <= z80_top_direct_n:z80_.nWR -GPIO_1[28] <= z80_top_direct_n:z80_.nRD -GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ -GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ -GPIO_1[31] <= z80_top_direct_n:z80_.nM1 -GPIO_1[32] <= -GPIO_1[33] <= -buzzer_out <= ula:ula_.beep +GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK +GPIO_1[25] << z80_top_direct_n:z80_.nHALT +GPIO_1[26] << z80_top_direct_n:z80_.nRFSH +GPIO_1[27] << z80_top_direct_n:z80_.nWR +GPIO_1[28] << z80_top_direct_n:z80_.nRD +GPIO_1[29] << z80_top_direct_n:z80_.nIORQ +GPIO_1[30] << z80_top_direct_n:z80_.nMREQ +GPIO_1[31] << z80_top_direct_n:z80_.nM1 +buzzer_out << ula:ula_.beep raw_loader_in => raw_loader_in.IN1 -DRAM_BA[0] <= sdram_controller:sdram_.DRAM_BA -DRAM_BA[1] <= sdram_controller:sdram_.DRAM_BA -DRAM_DQM[0] <= sdram_controller:sdram_.DRAM_DQM -DRAM_DQM[1] <= sdram_controller:sdram_.DRAM_DQM -DRAM_RAS_N <= sdram_controller:sdram_.DRAM_RAS_N -DRAM_CAS_N <= sdram_controller:sdram_.DRAM_CAS_N -DRAM_CKE <= sdram_controller:sdram_.DRAM_CKE -DRAM_CLK <= sdram_controller:sdram_.DRAM_CLK -DRAM_WE_N <= sdram_controller:sdram_.DRAM_WE_N -DRAM_CS_N <= sdram_controller:sdram_.DRAM_CS_N +DRAM_BA[0] << sdram_controller:sdram_.DRAM_BA +DRAM_BA[1] << sdram_controller:sdram_.DRAM_BA +DRAM_DQM[0] << sdram_controller:sdram_.DRAM_DQM +DRAM_DQM[1] << sdram_controller:sdram_.DRAM_DQM +DRAM_RAS_N << sdram_controller:sdram_.DRAM_RAS_N +DRAM_CAS_N << sdram_controller:sdram_.DRAM_CAS_N +DRAM_CKE << sdram_controller:sdram_.DRAM_CKE +DRAM_CLK << sdram_controller:sdram_.DRAM_CLK +DRAM_WE_N << sdram_controller:sdram_.DRAM_WE_N +DRAM_CS_N << sdram_controller:sdram_.DRAM_CS_N DRAM_DQ[0] <> sdram_controller:sdram_.DRAM_DQ DRAM_DQ[1] <> sdram_controller:sdram_.DRAM_DQ DRAM_DQ[2] <> sdram_controller:sdram_.DRAM_DQ @@ -101,19 +99,88 @@ DRAM_DQ[12] <> sdram_controller:sdram_.DRAM_DQ DRAM_DQ[13] <> sdram_controller:sdram_.DRAM_DQ DRAM_DQ[14] <> sdram_controller:sdram_.DRAM_DQ DRAM_DQ[15] <> sdram_controller:sdram_.DRAM_DQ -DRAM_ADDR[0] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[1] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[2] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[3] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[4] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[5] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[6] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[7] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[8] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[9] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[10] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[11] <= sdram_controller:sdram_.DRAM_ADDR -DRAM_ADDR[12] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[0] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[1] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[2] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[3] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[4] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[5] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[6] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[7] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[8] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[9] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[10] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[11] << sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[12] << sdram_controller:sdram_.DRAM_ADDR +kempston[0] => LED[3].DATAIN +kempston[0] => D.DATAB +kempston[1] => LED[4].DATAIN +kempston[1] => D.DATAB +kempston[2] => LED[5].DATAIN +kempston[2] => D.DATAB +kempston[3] => LED[6].DATAIN +kempston[3] => D.DATAB +kempston[4] => LED.IN1 +kempston[4] => D.IN1 +kempston_gnd << +turbo_button => turbo_button.IN1 +kempston_autofire_button => kempston_autofire_button.IN1 + + +|spectrum|debouncer:debounce_turbo +i_Clk => r_State.CLK +i_Clk => r_Count[0].CLK +i_Clk => r_Count[1].CLK +i_Clk => r_Count[2].CLK +i_Clk => r_Count[3].CLK +i_Clk => r_Count[4].CLK +i_Clk => r_Count[5].CLK +i_Clk => r_Count[6].CLK +i_Clk => r_Count[7].CLK +i_Clk => r_Count[8].CLK +i_Clk => r_Count[9].CLK +i_Clk => r_Count[10].CLK +i_Clk => r_Count[11].CLK +i_Clk => r_Count[12].CLK +i_Clk => r_Count[13].CLK +i_Clk => r_Count[14].CLK +i_Clk => r_Count[15].CLK +i_Clk => r_Count[16].CLK +i_Clk => r_Count[17].CLK +i_Clk => r_Count[18].CLK +i_Clk => r_Count[19].CLK +i_Clk => r_Count[20].CLK +i_Switch => always0.IN1 +i_Switch => r_State.DATAB +o_Switch <= r_State.DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|debouncer:debounce_autofire +i_Clk => r_State.CLK +i_Clk => r_Count[0].CLK +i_Clk => r_Count[1].CLK +i_Clk => r_Count[2].CLK +i_Clk => r_Count[3].CLK +i_Clk => r_Count[4].CLK +i_Clk => r_Count[5].CLK +i_Clk => r_Count[6].CLK +i_Clk => r_Count[7].CLK +i_Clk => r_Count[8].CLK +i_Clk => r_Count[9].CLK +i_Clk => r_Count[10].CLK +i_Clk => r_Count[11].CLK +i_Clk => r_Count[12].CLK +i_Clk => r_Count[13].CLK +i_Clk => r_Count[14].CLK +i_Clk => r_Count[15].CLK +i_Clk => r_Count[16].CLK +i_Clk => r_Count[17].CLK +i_Clk => r_Count[18].CLK +i_Clk => r_Count[19].CLK +i_Clk => r_Count[20].CLK +i_Switch => always0.IN1 +i_Switch => r_State.DATAB +o_Switch <= r_State.DB_MAX_OUTPUT_PORT_TYPE |spectrum|rom0:rom @@ -2144,6 +2211,8 @@ address[23] => Equal7.IN13 address[23] => n.DATAB address[23] => n.DATAB req_read => n.OUTPUTSELECT +req_read => n.OUTPUTSELECT +req_write => n.OUTPUTSELECT req_write => n.OUTPUTSELECT data_out[0] <= r.data_out_low[0].DB_MAX_OUTPUT_PORT_TYPE data_out[1] <= r.data_out_low[1].DB_MAX_OUTPUT_PORT_TYPE diff --git a/db/spectrum.hif b/db/spectrum.hif index 49fd970..a72c0e7 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo index 7280a98..cea9bd8 100644 Binary files a/db/spectrum.ipinfo and b/db/spectrum.ipinfo differ diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html index ada819b..35751e0 100644 --- a/db/spectrum.lpc.html +++ b/db/spectrum.lpc.html @@ -1743,4 +1743,36 @@ 0 0 + +debounce_autofire +2 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 + + +debounce_turbo +2 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 + diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 7019611..6578418 100644 Binary files a/db/spectrum.lpc.rdb and b/db/spectrum.lpc.rdb differ diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt index ef961e3..0cb13dd 100644 --- a/db/spectrum.lpc.txt +++ b/db/spectrum.lpc.txt @@ -1620,5 +1620,35 @@ Constant Bidir : 0 Unused Bidir : 0 Input only Bidir : 0 Output only Bidir : 0 + +Hierarchy : debounce_autofire +Input : 2 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 1 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : debounce_turbo +Input : 2 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 1 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 +--------------------------------------------------------------------------------+ diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index 00ac7a9..8d2e38b 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index 7a78eb8..20dcf53 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index 9e8549c..81fb6d7 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index c4fb4be..8a9fa12 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index 7cedb0f..177fdca 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,168 +1,185 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900231311 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:50:31 2022 " "Processing started: Sat Apr 2 14:50:31 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648900231497 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231565 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231566 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231566 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231567 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231567 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231568 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231569 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231569 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231570 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231570 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231571 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231571 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231572 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231573 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231574 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231574 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231576 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231578 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231579 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231580 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231580 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231582 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231582 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231607 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231608 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231608 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231609 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231609 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231610 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231610 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231611 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231612 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231613 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231614 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231614 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231616 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231616 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231617 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231619 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231619 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231620 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231620 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231621 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231621 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648900231625 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648900231625 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231625 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231625 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231626 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231626 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231627 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231627 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231628 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231628 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231629 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231630 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231630 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231631 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231632 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231920 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231920 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231921 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231921 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231921 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231924 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231924 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231925 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231925 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231926 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231926 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231928 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231928 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231928 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231929 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231929 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648900232089 ""} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648900232093 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648900232093 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648900232093 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232106 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232153 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232154 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232201 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232201 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232202 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232243 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232244 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232285 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232285 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232285 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232288 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232293 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232294 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232342 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232342 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232384 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232384 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232384 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232390 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232394 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232395 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232444 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232444 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232486 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232486 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232486 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232526 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232527 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232568 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232568 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232570 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232574 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232601 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232605 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232653 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232653 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232654 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 303 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232656 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232658 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232666 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232670 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232717 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232717 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232718 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232719 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232720 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232722 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232723 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232725 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232726 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 347 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232729 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232732 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232733 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232733 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232747 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232748 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232748 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232749 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232751 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232752 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232753 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232753 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232754 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232755 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232756 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232757 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232758 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232759 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232760 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232761 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232763 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232764 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232765 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232765 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232767 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232768 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232769 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232781 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232782 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232784 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232784 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232785 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232789 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232790 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232790 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232791 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232792 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232793 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232794 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648900237557 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648900237657 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648900237663 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648900237687 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648900237688 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|GPIO_1[33]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|DRAM_CS_N"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648900241055 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648900241438 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648900245124 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648900245212 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648900245470 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900245470 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900245726 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900245726 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648900245726 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "3006 " "Implemented 3006 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_OPINS" "85 " "Implemented 85 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2826 " "Implemented 2826 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648900245726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648900245726 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 112 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900245751 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:50:45 2022 " "Processing ended: Sat Apr 2 14:50:45 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242656891 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242656892 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:57:36 2022 " "Processing started: Wed Apr 6 13:57:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242656892 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1649242656892 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1649242656892 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1649242657098 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657169 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657169 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657170 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657170 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657171 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657171 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657172 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657172 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657173 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657173 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657175 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657175 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657176 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657176 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657177 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657177 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657178 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657178 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657179 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657179 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657180 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657180 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657180 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657180 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657181 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657181 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657182 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657182 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657182 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657182 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657183 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657183 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657184 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657184 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657185 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657185 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657186 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657186 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657186 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657186 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657211 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657211 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657212 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657212 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657213 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657213 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657214 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657214 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657215 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657215 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657217 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657217 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657217 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657217 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657218 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657218 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657219 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657219 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657220 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657220 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657221 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657221 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657222 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657222 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657223 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657223 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657224 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657224 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657225 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657225 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657226 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657226 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657227 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657227 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657227 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657227 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1649242657230 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1649242657230 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657230 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657230 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657231 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657231 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657233 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657233 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657234 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657234 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657235 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657235 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657236 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657236 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657237 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657237 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657238 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657238 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657537 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657537 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657538 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657538 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657542 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657542 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657543 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657543 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657544 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657544 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657544 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657546 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657546 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(118) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(118)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 118 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242657546 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(120) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(120)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 120 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242657547 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(122) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(122)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 122 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242657547 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(124) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(124)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 124 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242657547 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(126) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(126)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 126 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242657547 ""} +{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "IOB sdram.v(128) " "Unrecognized synthesis attribute \"IOB\" at sdram.v(128)" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 128 0 0 } } } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1649242657547 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram " "Found entity 1: sdram" { } { { "sdram.v" "" { Text "/home/benny/work/fpga/spectrum/sdram.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657548 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 SDRAM_ctrl " "Found entity 1: SDRAM_ctrl" { } { { "sdram_ctrl.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_ctrl.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657548 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "sdram_controller.v(166) " "Verilog HDL warning at sdram_controller.v(166): extended using \"x\" or \"z\"" { } { { "sdram_controller.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_controller.v" 166 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1649242657549 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller_new " "Found entity 1: sdram_controller_new" { } { { "sdram_controller.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_controller.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657550 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sdram " "Found entity 1: pll_sdram" { } { { "pll_sdram.v" "" { Text "/home/benny/work/fpga/spectrum/pll_sdram.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657551 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657551 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 debouncer " "Found entity 1: debouncer" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657552 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657552 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1649242657759 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_io_read_requested spectrum.sv(114) " "Verilog HDL or VHDL warning at spectrum.sv(114): object \"is_io_read_requested\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 114 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242657761 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_io_write_requested spectrum.sv(115) " "Verilog HDL or VHDL warning at spectrum.sv(115): object \"is_io_write_requested\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 115 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242657761 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_rom_address spectrum.sv(118) " "Verilog HDL or VHDL warning at spectrum.sv(118): object \"is_rom_address\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 118 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242657761 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "kempston_last_fire_state spectrum.sv(133) " "Verilog HDL or VHDL warning at spectrum.sv(133): object \"kempston_last_fire_state\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 133 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242657761 "|spectrum"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sdram_write_request spectrum.sv(231) " "Verilog HDL or VHDL warning at spectrum.sv(231): object \"sdram_write_request\" assigned a value but never read" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 231 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1649242657761 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 spectrum.sv(141) " "Verilog HDL assignment warning at spectrum.sv(141): truncated value with size 32 to match size of target (18)" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 141 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1649242657761 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debouncer debouncer:debounce_turbo " "Elaborating entity \"debouncer\" for hierarchy \"debouncer:debounce_turbo\"" { } { { "spectrum.sv" "debounce_turbo" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 54 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657764 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 debouncer.v(13) " "Verilog HDL assignment warning at debouncer.v(13): truncated value with size 32 to match size of target (21)" { } { { "debouncer.v" "" { Text "/home/benny/work/fpga/spectrum/debouncer.v" 13 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1649242657764 "|spectrum|debouncer:debounce_turbo"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657766 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657820 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242657821 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657822 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242657822 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657870 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657870 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657870 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657912 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657912 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657912 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242657953 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242657953 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657954 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 207 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657957 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657961 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242657962 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242657963 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242657963 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658011 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658011 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658011 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658053 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658053 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658053 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658059 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658063 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658064 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242658064 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658114 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658114 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658114 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658156 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658156 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658156 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658197 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658197 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658197 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658238 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658238 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658239 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 258 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658241 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 148 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658244 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658272 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658276 ""} } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242658276 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658325 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658326 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 321 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658328 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658329 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658338 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658342 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1649242658342 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1649242658390 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1649242658390 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658390 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658392 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658392 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658394 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658396 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658397 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658398 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 365 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658401 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658406 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658420 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658421 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658422 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658423 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658425 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658425 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658426 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658427 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658428 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658429 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658430 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658431 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658431 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658433 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658434 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658435 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658437 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658438 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658438 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658439 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658441 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658442 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658443 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658456 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658457 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658458 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658459 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658460 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658463 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658464 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658465 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658466 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658467 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658467 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1649242658468 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1649242663442 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] sdram_read_request " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"sdram_read_request\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal5 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal5\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal5 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal5\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663549 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1649242663549 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 92 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1649242663556 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1649242663556 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1649242663581 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1649242663582 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242667048 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242667048 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242667048 "|spectrum|DRAM_CS_N"} { "Warning" "WMLS_MLS_STUCK_PIN" "kempston_gnd GND " "Pin \"kempston_gnd\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 36 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1649242667048 "|spectrum|kempston_gnd"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1649242667048 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1649242667453 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1649242671179 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1649242671270 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1649242671544 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242671544 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242671828 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242671828 "|spectrum|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242671828 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1649242671828 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "3146 " "Implemented 3146 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Implemented 18 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1649242671829 ""} { "Info" "ICUT_CUT_TM_OPINS" "84 " "Implemented 84 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1649242671829 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1649242671829 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2960 " "Implemented 2960 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1649242671829 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1649242671829 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1649242671829 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1649242671829 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 117 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 117 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242671854 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:57:51 2022 " "Processing ended: Wed Apr 6 13:57:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242671854 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242671854 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242671854 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242671854 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index 52f00df..465bdea 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index 41cb0c6..3619cc0 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index dfad412..d946f9c 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pplq.rdb b/db/spectrum.pplq.rdb index 9ea6ac9..9e9f17c 100644 Binary files a/db/spectrum.pplq.rdb and b/db/spectrum.pplq.rdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index 8ef606a..5540cd5 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.quiproj.9074.rdr.flock b/db/spectrum.qns similarity index 100% rename from db/spectrum.quiproj.9074.rdr.flock rename to db/spectrum.qns diff --git a/output_files/pll_i2s.qip b/db/spectrum.quiproj.432415.rdr.flock similarity index 100% rename from output_files/pll_i2s.qip rename to db/spectrum.quiproj.432415.rdr.flock diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb index 97d5738..451dddd 100644 Binary files a/db/spectrum.root_partition.map.reg_db.cdb and b/db/spectrum.root_partition.map.reg_db.cdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index 6c009f6..f0e9921 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index 1d7f141..0106c4f 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index 428ce67..5f41ded 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index ef445e7..e30cc9e 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index b843ee9..3999d04 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index f5da734..80864ec 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index 267d834..0d5e4b0 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,58 +1,64 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900273361 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900273361 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:13 2022 " "Processing started: Sat Apr 2 14:51:13 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900273361 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900273361 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900273362 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648900273389 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648900273585 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648900273586 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648900273629 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648900273629 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648900274051 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274060 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274060 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648900274060 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648900274062 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274063 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} -{ "Warning" "WSTA_SCC_LOOP" "513 " "Found combinational loop of 513 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|datad " "Node \"z80_\|alu_control_\|db\[2\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|combout " "Node \"z80_\|alu_control_\|db\[2\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datab " "Node \"z80_\|alu_control_\|db\[2\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datac " "Node \"z80_\|bus_control_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datac " "Node \"z80_\|bus_control_\|db\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datad " "Node \"z80_\|alu_\|db\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datac " "Node \"z80_\|alu_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|datad " "Node \"z80_\|alu_\|db_low\[1\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|combout " "Node \"z80_\|alu_\|db_low\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|datac " "Node \"z80_\|alu_\|db_low\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|combout " "Node \"z80_\|alu_\|db_low\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|combout " "Node \"z80_\|alu_\|db_low\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datac " "Node \"z80_\|alu_\|db\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|datab " "Node \"z80_\|alu_control_\|db\[1\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|combout " "Node \"z80_\|alu_control_\|db\[1\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|datad " "Node \"z80_\|alu_control_\|db\[1\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datad " "Node \"z80_\|alu_\|db\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|datab " "Node \"z80_\|alu_\|db_low\[1\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datac " "Node \"z80_\|alu_\|db_low\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datad " "Node \"z80_\|alu_\|db_low\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datab " "Node \"z80_\|alu_\|db_low\[0\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|combout " "Node \"z80_\|alu_\|db_low\[0\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datad " "Node \"z80_\|alu_\|db_high\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datac " "Node \"z80_\|alu_\|db_high\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datad " "Node \"z80_\|alu_\|db_high\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datad " "Node \"z80_\|alu_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datab " "Node \"z80_\|alu_\|db_high\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datab " "Node \"z80_\|alu_\|db_high\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|combout " "Node \"z80_\|alu_\|db_high\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datad " "Node \"z80_\|alu_\|db_high\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datac " "Node \"z80_\|alu_\|db_high\[3\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datac " "Node \"z80_\|alu_\|db_high\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|combout " "Node \"z80_\|alu_\|db_high\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datad " "Node \"z80_\|alu_\|db_high\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datac " "Node \"z80_\|alu_\|db\[5\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|datad " "Node \"z80_\|alu_control_\|db\[5\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|combout " "Node \"z80_\|alu_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|dataa " "Node \"z80_\|bus_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datad " "Node \"z80_\|alu_\|db_high\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datad " "Node \"z80_\|alu_\|db_low\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|datad " "Node \"z80_\|alu_\|db_low\[1\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|datac " "Node \"z80_\|sw1_\|db_down\[5\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|combout " "Node \"z80_\|alu_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datad " "Node \"z80_\|alu_\|db_high\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datad " "Node \"z80_\|alu_\|db_low\[3\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|datad " "Node \"z80_\|alu_\|db_low\[3\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|combout " "Node \"z80_\|alu_\|db_low\[3\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~36\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|combout " "Node \"z80_\|alu_control_\|db\[3\]~36\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|datad " "Node \"z80_\|alu_control_\|db\[3\]~36\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datad " "Node \"z80_\|alu_\|db\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datac " "Node \"z80_\|bus_control_\|db\[3\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|datab " "Node \"z80_\|sw1_\|db_down\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datad " "Node \"z80_\|alu_\|db_low\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|combout " "Node \"z80_\|alu_\|db_low\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|datad " "Node \"z80_\|alu_\|db_low\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|combout " "Node \"z80_\|alu_\|db_low\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datad " "Node \"z80_\|alu_\|db_high\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datac " "Node \"z80_\|alu_\|db_high\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datad " "Node \"z80_\|alu_\|db\[4\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datac " "Node \"z80_\|alu_control_\|db\[4\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|datad " "Node \"z80_\|alu_control_\|db\[4\]~33\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|combout " "Node \"z80_\|alu_control_\|db\[4\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datac " "Node \"z80_\|alu_control_\|db\[4\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datac " "Node \"z80_\|alu_\|db\[4\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datac " "Node \"z80_\|alu_\|db\[4\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datac " "Node \"z80_\|bus_control_\|db\[4\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|datac " "Node \"z80_\|alu_control_\|db\[4\]~33\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|datad " "Node \"z80_\|alu_\|db_low\[0\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|combout " "Node \"z80_\|alu_\|db_low\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datac " "Node \"z80_\|alu_\|db_low\[0\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datad " "Node \"z80_\|alu_\|db_low\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datad " "Node \"z80_\|alu_\|db_high\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datad " "Node \"z80_\|alu_\|db_high\[3\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datad " "Node \"z80_\|alu_\|db_high\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datad " "Node \"z80_\|alu_\|db\[4\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datad " "Node \"z80_\|alu_\|db_low\[3\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datad " "Node \"z80_\|alu_\|db_low\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datac " "Node \"z80_\|alu_\|db_high\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datac " "Node \"z80_\|alu_\|db\[3\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datad " "Node \"z80_\|alu_\|db_low\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datad " "Node \"z80_\|alu_\|db_low\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datab " "Node \"z80_\|alu_\|db_low\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|datac " "Node \"z80_\|alu_control_\|db\[5\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datac " "Node \"z80_\|alu_\|db\[5\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datad " "Node \"z80_\|alu_\|db_high\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datac " "Node \"z80_\|alu_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datad " "Node \"z80_\|alu_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datab " "Node \"z80_\|alu_control_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|combout " "Node \"z80_\|alu_control_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datad " "Node \"z80_\|bus_control_\|db\[6\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|datac " "Node \"z80_\|sw1_\|db_down\[6\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datad " "Node \"z80_\|alu_control_\|db\[6\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datac " "Node \"z80_\|alu_control_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datad " "Node \"z80_\|alu_control_\|db\[7\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|datad " "Node \"z80_\|alu_control_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|combout " "Node \"z80_\|alu_control_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|datad " "Node \"z80_\|alu_control_\|db\[7\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|combout " "Node \"z80_\|alu_control_\|db\[7\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|datab " "Node \"z80_\|alu_control_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datac " "Node \"z80_\|alu_\|db\[7\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datac " "Node \"z80_\|alu_control_\|db\[7\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datad " "Node \"z80_\|alu_control_\|db\[0\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|combout " "Node \"z80_\|alu_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|combout " "Node \"z80_\|alu_control_\|db\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|datad " "Node \"z80_\|alu_control_\|db\[0\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|combout " "Node \"z80_\|alu_control_\|db\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datab " "Node \"z80_\|alu_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datac " "Node \"z80_\|alu_\|db\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datac " "Node \"z80_\|alu_\|db_low\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datac " "Node \"z80_\|alu_\|db\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datac " "Node \"z80_\|alu_\|db_low\[3\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648900274071 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "513 " "Design contains combinational loop of 513 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648900274088 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900274118 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900274118 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274248 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648900274250 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648900274279 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648900274329 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648900274329 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.571 " "Worst-case setup slack is -18.571" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.571 -821.372 CLOCK_50 " " -18.571 -821.372 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.747 -287.138 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.747 -287.138 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.731 -41.432 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.731 -41.432 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.915 -2.915 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.915 -2.915 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.503 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.503 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.342 " "Worst-case hold slack is 0.342" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.359 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.359 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.373 0.000 CLOCK_50 " " 0.373 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.212 " "Worst-case recovery slack is -6.212" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.212 -460.730 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.212 -460.730 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.666 " "Worst-case removal slack is 3.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.666 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.666 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.597 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.597 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648900274504 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648900274542 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648900275511 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900275682 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900275682 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275685 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648900275705 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648900275705 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.727 " "Worst-case setup slack is -17.727" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.727 -781.205 CLOCK_50 " " -17.727 -781.205 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.896 -255.894 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.896 -255.894 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.422 -38.759 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.422 -38.759 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.786 -2.786 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.786 -2.786 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.148 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.148 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.339 0.000 CLOCK_50 " " 0.339 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.735 " "Worst-case recovery slack is -5.735" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.735 -424.927 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.735 -424.927 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.339 " "Worst-case removal slack is 3.339" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.339 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.339 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.596 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.596 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648900275928 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900276228 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900276228 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276230 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648900276238 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648900276238 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.243 " "Worst-case setup slack is -15.243" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.243 -641.328 CLOCK_50 " " -15.243 -641.328 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.921 -171.346 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.921 -171.346 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.770 -34.841 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.770 -34.841 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.098 " "Worst-case hold slack is 0.098" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.098 0.000 CLOCK_50 " " 0.098 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.684 " "Worst-case recovery slack is -4.684" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.684 -358.844 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.684 -358.844 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.507 " "Worst-case removal slack is 2.507" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.783 " "Worst-case minimum pulse width slack is 4.783" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.783 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.783 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648900276955 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648900276955 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 534 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 534 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "445 " "Peak virtual memory: 445 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900277219 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:17 2022 " "Processing ended: Sat Apr 2 14:51:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1649242700900 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1649242700901 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 6 13:58:20 2022 " "Processing started: Wed Apr 6 13:58:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1649242700901 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1649242700901 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1649242700901 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1649242700929 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1649242701138 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1649242701140 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1649242701189 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1649242701189 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1649242701639 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701648 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701649 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1649242701649 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701650 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701650 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701650 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701650 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701650 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701650 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701651 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701651 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1649242701651 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1649242701651 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701652 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701652 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701652 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701652 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1649242701653 ""} +{ "Warning" "WSTA_SCC_LOOP" "518 " "Found combinational loop of 518 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datad " "Node \"z80_\|alu_\|db_high\[3\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datad " "Node \"z80_\|alu_\|db_high\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|combout " "Node \"z80_\|alu_\|db_low\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datad " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datac " "Node \"z80_\|alu_\|db\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|datac " "Node \"z80_\|alu_control_\|db\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datab " "Node \"z80_\|alu_control_\|db\[1\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~9\|combout " "Node \"z80_\|bus_control_\|db\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|datab " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datac " "Node \"z80_\|alu_\|db\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~33\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datac " "Node \"z80_\|alu_\|db_low\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~2\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datac " "Node \"z80_\|alu_\|db_low\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datad " "Node \"z80_\|alu_\|db_low\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datac " "Node \"z80_\|alu_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datad " "Node \"z80_\|bus_control_\|db\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|datab " "Node \"z80_\|bus_control_\|db\[2\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~14\|combout " "Node \"z80_\|bus_control_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|datac " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datad " "Node \"z80_\|alu_\|db\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datad " "Node \"z80_\|alu_control_\|db\[2\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~43\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datad " "Node \"z80_\|alu_\|db_low\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datad " "Node \"z80_\|alu_\|db_low\[3\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datac " "Node \"z80_\|alu_\|db_low\[3\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datad " "Node \"z80_\|alu_\|db_low\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datac " "Node \"z80_\|alu_\|db\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datab " "Node \"z80_\|alu_\|db_high\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datac " "Node \"z80_\|alu_\|db\[4\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datad " "Node \"z80_\|alu_\|db_high\[1\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datad " "Node \"z80_\|alu_\|db\[5\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|datac " "Node \"z80_\|alu_\|db_high\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|combout " "Node \"z80_\|alu_\|db_high\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datab " "Node \"z80_\|alu_\|db_high\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datad " "Node \"z80_\|alu_\|db_high\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datab " "Node \"z80_\|alu_control_\|db\[6\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|datab " "Node \"z80_\|bus_control_\|db\[6\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~7\|combout " "Node \"z80_\|bus_control_\|db\[6\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|datac " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|datad " "Node \"z80_\|alu_control_\|db\[6\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datac " "Node \"z80_\|alu_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datad " "Node \"z80_\|alu_control_\|db\[5\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~53\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datad " "Node \"z80_\|alu_control_\|db\[5\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|datad " "Node \"z80_\|bus_control_\|db\[5\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~16\|combout " "Node \"z80_\|bus_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datad " "Node \"z80_\|alu_\|db_high\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datac " "Node \"z80_\|alu_\|db_low\[3\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datac " "Node \"z80_\|alu_\|db_low\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|datad " "Node \"z80_\|alu_\|db_low\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~8\|combout " "Node \"z80_\|alu_\|db_low\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datac " "Node \"z80_\|alu_\|db_low\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datab " "Node \"z80_\|alu_control_\|db\[5\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datad " "Node \"z80_\|alu_\|db_low\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datad " "Node \"z80_\|alu_\|db\[5\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datad " "Node \"z80_\|alu_\|db\[4\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|datab " "Node \"z80_\|alu_control_\|db\[4\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|combout " "Node \"z80_\|alu_control_\|db\[4\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datab " "Node \"z80_\|alu_control_\|db\[4\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datab " "Node \"z80_\|alu_control_\|db\[4\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|datab " "Node \"z80_\|bus_control_\|db\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~18\|combout " "Node \"z80_\|bus_control_\|db\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datad " "Node \"z80_\|alu_\|db_high\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datad " "Node \"z80_\|alu_\|db_low\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datad " "Node \"z80_\|alu_\|db_low\[2\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datad " "Node \"z80_\|alu_\|db_high\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datad " "Node \"z80_\|alu_\|db_low\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datad " "Node \"z80_\|alu_\|db_low\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|datab " "Node \"z80_\|bus_control_\|db\[3\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~20\|combout " "Node \"z80_\|bus_control_\|db\[3\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|datab " "Node \"z80_\|alu_control_\|db\[3\]~33\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~33\|combout " "Node \"z80_\|alu_control_\|db\[3\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datab " "Node \"z80_\|alu_\|db_low\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datad " "Node \"z80_\|alu_\|db\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~58\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datab " "Node \"z80_\|alu_control_\|db\[3\]~34\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~63\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~19\|datab " "Node \"z80_\|alu_\|db_low\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datac " "Node \"z80_\|alu_\|db\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|datac " "Node \"z80_\|alu_control_\|db\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~23\|combout " "Node \"z80_\|alu_control_\|db\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|datab " "Node \"z80_\|bus_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~11\|combout " "Node \"z80_\|bus_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|datac " "Node \"z80_\|bus_control_\|db\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~12\|combout " "Node \"z80_\|bus_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|datac " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datad " "Node \"z80_\|alu_control_\|db\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datad " "Node \"z80_\|alu_\|db_high\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datac " "Node \"z80_\|alu_control_\|db\[7\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datad " "Node \"z80_\|alu_control_\|db\[7\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|datad " "Node \"z80_\|bus_control_\|db\[7\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~4\|combout " "Node \"z80_\|bus_control_\|db\[7\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|datac " "Node \"z80_\|bus_control_\|db\[7\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~6\|combout " "Node \"z80_\|bus_control_\|db\[7\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|datab " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout " "Node \"z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datad " "Node \"z80_\|alu_control_\|db\[7\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1649242701659 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 36 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 35 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1649242701659 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "518 " "Design contains combinational loop of 518 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1649242701676 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242701707 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242701707 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242701707 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242701707 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701841 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1649242701844 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1649242701873 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1649242701927 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1649242701927 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.476 " "Worst-case setup slack is -18.476" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.476 -808.800 CLOCK_50 " " -18.476 -808.800 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.513 -282.972 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.513 -282.972 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.734 -42.279 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.734 -42.279 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 70.299 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 70.299 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242701928 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.344 " "Worst-case hold slack is 0.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.382 0.000 CLOCK_50 " " 0.382 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242701936 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.210 " "Worst-case recovery slack is -6.210" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701937 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701937 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.210 -460.961 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.210 -460.961 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701937 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242701937 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.689 " "Worst-case removal slack is 3.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.689 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.689 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701938 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242701938 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.490 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.490 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242701939 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1649242702113 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1649242702152 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1649242703171 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703355 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703355 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703355 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703355 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703358 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1649242703381 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1649242703381 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.646 " "Worst-case setup slack is -17.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.646 -768.789 CLOCK_50 " " -17.646 -768.789 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.953 -254.832 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.953 -254.832 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -39.535 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.416 -39.535 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.951 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.951 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 70.438 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 70.438 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703384 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.300 " "Worst-case hold slack is 0.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.312 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.333 0.000 CLOCK_50 " " 0.333 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703395 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.734 " "Worst-case recovery slack is -5.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.734 -425.150 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.734 -425.150 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703399 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703399 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.370 " "Worst-case removal slack is 3.370" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.370 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.370 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703403 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.589 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.589 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.487 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.487 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703407 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1649242703621 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703933 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_autofire\|r_State " "Node: debouncer:debounce_autofire\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703933 "|spectrum|debouncer:debounce_autofire|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "debouncer:debounce_turbo\|r_State " "Node: debouncer:debounce_turbo\|r_State was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703933 "|spectrum|debouncer:debounce_turbo|r_State"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1649242703933 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703936 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1649242703945 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1649242703945 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.170 " "Worst-case setup slack is -15.170" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.170 -635.207 CLOCK_50 " " -15.170 -635.207 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.647 -193.116 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -5.647 -193.116 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.810 -35.303 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.810 -35.303 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.131 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.131 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 70.800 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 70.800 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703951 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.179 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.201 0.000 CLOCK_50 " " 0.201 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703965 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.684 " "Worst-case recovery slack is -4.684" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.684 -359.024 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.684 -359.024 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703971 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703971 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.507 " "Worst-case removal slack is 2.507" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703978 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703978 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.784 " "Worst-case minimum pulse width slack is 4.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.525 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.525 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1649242703985 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1649242704694 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1649242704694 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 545 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 545 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1649242704971 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 6 13:58:24 2022 " "Processing ended: Wed Apr 6 13:58:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1649242704971 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1649242704971 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1649242704971 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1649242704971 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index b97bc3f..40951fe 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index 3281638..3c63c99 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index e1687d8..25eab37 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index 897fa00..b051186 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index f730213..9abe8b0 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.tmw_info b/db/spectrum.tmw_info new file mode 100644 index 0000000..0ba653f --- /dev/null +++ b/db/spectrum.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:00:58 +start_analysis_synthesis:s:00:00:18-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:26-start_full_compilation +start_assembler:s:00:00:03-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation +start_eda_netlist_writer:s:00:00:05-start_full_compilation diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index f447e9d..a8aea93 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/db/stp1_auto_stripped.stp b/db/stp1_auto_stripped.stp new file mode 100644 index 0000000..0470247 --- /dev/null +++ b/db/stp1_auto_stripped.stp @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 111111111111 + 111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + +
+ + + + + + + + + + + + + + diff --git a/debouncer.v b/debouncer.v new file mode 100644 index 0000000..5af84d1 --- /dev/null +++ b/debouncer.v @@ -0,0 +1,30 @@ +module debouncer(input i_Clk, input i_Switch, output o_Switch); + + parameter c_DEBOUNCE_LIMIT = 1100000; // 30 ms at 50 MHz + + reg [20:0] r_Count = 0; + reg r_State = 1'b0; + + always @(posedge i_Clk) + begin + // Switch input is different than internal switch value, so an input is + // changing. Increase the counter until it is stable for enough time. + if (i_Switch !== r_State && r_Count < c_DEBOUNCE_LIMIT) + r_Count <= r_Count + 1; + + // End of counter reached, switch is stable, register it, reset counter + else if (r_Count == c_DEBOUNCE_LIMIT) + begin + r_State <= i_Switch; + r_Count <= 0; + end + + // Switches are the same state, reset the counter + else + r_Count <= 0; + end + + // Assign internal register to output (debounced!) + assign o_Switch = r_State; + +endmodule \ No newline at end of file diff --git a/output_files/pll_video.qip b/debouncer.v.bak similarity index 100% rename from output_files/pll_video.qip rename to debouncer.v.bak diff --git a/greybox_tmp/cbx_args.txt b/greybox_tmp/cbx_args.txt index 483f345..f2b2d27 100644 --- a/greybox_tmp/cbx_args.txt +++ b/greybox_tmp/cbx_args.txt @@ -1,12 +1,8 @@ BANDWIDTH_TYPE=AUTO -CLK0_DIVIDE_BY=1 +CLK0_DIVIDE_BY=50 CLK0_DUTY_CYCLE=50 -CLK0_MULTIPLY_BY=2 +CLK0_MULTIPLY_BY=133 CLK0_PHASE_SHIFT=0 -CLK1_DIVIDE_BY=1 -CLK1_DUTY_CYCLE=50 -CLK1_MULTIPLY_BY=2 -CLK1_PHASE_SHIFT=3000 COMPENSATE_CLOCK=CLK0 INCLK0_INPUT_FREQUENCY=20000 INTENDED_DEVICE_FAMILY="Cyclone IV E" @@ -39,7 +35,7 @@ PORT_SCANDONE=PORT_UNUSED PORT_SCANREAD=PORT_UNUSED PORT_SCANWRITE=PORT_UNUSED PORT_clk0=PORT_USED -PORT_clk1=PORT_USED +PORT_clk1=PORT_UNUSED PORT_clk2=PORT_UNUSED PORT_clk3=PORT_UNUSED PORT_clk4=PORT_UNUSED @@ -60,4 +56,3 @@ CBX_AUTO_BLACKBOX=ALL inclk inclk clk -clk diff --git a/incremental_db/compiled_partitions/spectrum.autoh_e40e1.map.cdb b/incremental_db/compiled_partitions/spectrum.autoh_e40e1.map.cdb new file mode 100644 index 0000000..2b4486b Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.autoh_e40e1.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.autoh_e40e1.map.dpi b/incremental_db/compiled_partitions/spectrum.autoh_e40e1.map.dpi new file mode 100644 index 0000000..2dfdf36 Binary files /dev/null and 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a/incremental_db/compiled_partitions/spectrum.autos_3e921.map.cdb b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.cdb new file mode 100644 index 0000000..5f3bddc Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.autos_3e921.map.dpi b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.dpi new file mode 100644 index 0000000..83aec60 Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.autos_3e921.map.hdb b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.hdb new file mode 100644 index 0000000..0c7030e Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.autos_3e921.map.kpt b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.kpt new file mode 100644 index 0000000..9f2aea5 Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.kpt differ diff --git a/incremental_db/compiled_partitions/spectrum.autos_3e921.map.logdb b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/incremental_db/compiled_partitions/spectrum.autos_3e921.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index 2442bd6..373285b 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index 24f6d67..8cbf848 100644 Binary files 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b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info index 4d6b0af..13ab4e2 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index e39484c..61d7b38 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index abe150d..ac02ec8 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index 7674f9d..f7788b6 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/output_files/greybox_tmp/cbx_args.txt b/output_files.old/greybox_tmp/cbx_args.txt similarity index 100% rename from output_files/greybox_tmp/cbx_args.txt rename to output_files.old/greybox_tmp/cbx_args.txt diff --git a/output_files/led_patterns.mif b/output_files.old/led_patterns.mif similarity index 100% rename from output_files/led_patterns.mif rename to output_files.old/led_patterns.mif diff --git a/output_files.old/output_files/sdram.v b/output_files.old/output_files/sdram.v new file mode 100644 index 0000000..c06deb8 --- /dev/null +++ b/output_files.old/output_files/sdram.v @@ -0,0 +1,436 @@ +/* + This SDRAM controller is for the Mojo's SDRAM shield which uses + a 48LC32M8A2-7E SDRAM chip. This module was designed under the + assumption that the click rate is 100MHz. Timing values would + need to be re-evaluated under different clock rates. + + This controller features two baisc improvements over the most + basic of controllers. It does burst reads and writes of 4 bytes, + and it only closes a row when it has to. +*/ + +module sdram ( + input clk, + input rst, + + // these signals go directly to the IO pins + output sdram_clk, + output sdram_cle, + output sdram_cs, + output sdram_cas, + output sdram_ras, + output sdram_we, + output sdram_dqm, + output [1:0] sdram_ba, + output [12:0] sdram_a, + inout [7:0] sdram_dq, + + // User interface + input [22:0] addr, // address to read/write + input rw, // 1 = write, 0 = read + input [31:0] data_in, // data from a read + output [31:0] data_out, // data for a write + output busy, // controller is busy when high + input in_valid, // pulse high to initiate a read/write + output out_valid // pulses high when data from read is valid + ); + + // Commands for the SDRAM + localparam CMD_UNSELECTED = 4'b1000; + localparam CMD_NOP = 4'b0111; + localparam CMD_ACTIVE = 4'b0011; + localparam CMD_READ = 4'b0101; + localparam CMD_WRITE = 4'b0100; + localparam CMD_TERMINATE = 4'b0110; + localparam CMD_PRECHARGE = 4'b0010; + localparam CMD_REFRESH = 4'b0001; + localparam CMD_LOAD_MODE_REG = 4'b0000; + + localparam STATE_SIZE = 4; + localparam INIT = 0, + WAIT = 1, + PRECHARGE_INIT = 2, + REFRESH_INIT_1 = 3, + REFRESH_INIT_2 = 4, + LOAD_MODE_REG = 5, + IDLE = 6, + REFRESH = 7, + ACTIVATE = 8, + READ = 9, + READ_RES = 10, + WRITE = 11, + PRECHARGE = 12; + + wire sdram_clk_ddr; + + // This is used to drive the SDRAM clock + ODDR2 #( + .DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC") + ) ODDR2_inst ( + .Q(sdram_clk_ddr), // 1-bit DDR output data + .C0(clk), // 1-bit clock input + .C1(~clk), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) // 1-bit set input + ); + + IODELAY2 #( + .IDELAY_VALUE(0), + .IDELAY_MODE("NORMAL"), + .ODELAY_VALUE(100), // value of 100 seems to work at 100MHz + .IDELAY_TYPE("FIXED"), + .DELAY_SRC("ODATAIN"), + .DATA_RATE("SDR") + ) IODELAY_inst ( + .IDATAIN(1'b0), + .T(1'b0), + .ODATAIN(sdram_clk_ddr), + .CAL(1'b0), + .IOCLK0(1'b0), + .IOCLK1(1'b0), + .CLK(1'b0), + .INC(1'b0), + .CE(1'b0), + .RST(1'b0), + .BUSY(), + .DATAOUT(), + .DATAOUT2(), + .TOUT(), + .DOUT(sdram_clk) + ); + + // registers for SDRAM signals + reg cle_d, dqm_d; + reg [3:0] cmd_d; + reg [1:0] ba_d; + reg [12:0] a_d; + reg [7:0] dq_d; + reg [7:0] dqi_d; + + // We want the output/input registers to be embedded in the + // IO buffers so we set IOB to "TRUE". This is to ensure all + // the signals are sent and received at the same time. + (* IOB = "TRUE" *) + reg cle_q, dqm_q; + (* IOB = "TRUE" *) + reg [3:0] cmd_q; + (* IOB = "TRUE" *) + reg [1:0] ba_q; + (* IOB = "TRUE" *) + reg [12:0] a_q; + (* IOB = "TRUE" *) + reg [7:0] dq_q; + (* IOB = "TRUE" *) + reg [7:0] dqi_q; + reg dq_en_d, dq_en_q; + + // Output assignments + assign sdram_cle = cle_q; + assign sdram_cs = cmd_q[3]; + assign sdram_ras = cmd_q[2]; + assign sdram_cas = cmd_q[1]; + assign sdram_we = cmd_q[0]; + assign sdram_dqm = dqm_q; + assign sdram_ba = ba_q; + assign sdram_a = a_q; + assign sdram_dq = dq_en_q ? dq_q : 8'hZZ; // only drive when dq_en_q is 1 + + reg [STATE_SIZE-1:0] state_d, state_q = INIT; + reg [STATE_SIZE-1:0] next_state_d, next_state_q; + + reg [22:0] addr_d, addr_q; + reg [31:0] data_d, data_q; + reg out_valid_d, out_valid_q; + + assign data_out = data_q; + assign busy = !ready_q; + assign out_valid = out_valid_q; + + reg [15:0] delay_ctr_d, delay_ctr_q; + reg [1:0] byte_ctr_d, byte_ctr_q; + + reg [9:0] refresh_ctr_d, refresh_ctr_q; + reg refresh_flag_d, refresh_flag_q; + + reg ready_d, ready_q; + reg saved_rw_d, saved_rw_q; + reg [22:0] saved_addr_d, saved_addr_q; + reg [31:0] saved_data_d, saved_data_q; + + reg rw_op_d, rw_op_q; + + reg [3:0] row_open_d, row_open_q; + reg [12:0] row_addr_d[3:0], row_addr_q[3:0]; + + reg [2:0] precharge_bank_d, precharge_bank_q; + integer i; + + always @* begin + // Default values + dq_d = dq_q; + dqi_d = sdram_dq; + dq_en_d = 1'b0; // normally keep the bus in high-Z + cle_d = cle_q; + cmd_d = CMD_NOP; // default to NOP + dqm_d = 1'b0; + ba_d = 2'd0; + a_d = 25'd0; + state_d = state_q; + next_state_d = next_state_q; + delay_ctr_d = delay_ctr_q; + addr_d = addr_q; + data_d = data_q; + out_valid_d = 1'b0; + precharge_bank_d = precharge_bank_q; + rw_op_d = rw_op_q; + byte_ctr_d = 2'd0; + + row_open_d = row_open_q; + + // row_addr is a 2d array and must be coppied this way + for (i = 0; i < 4; i = i + 1) + row_addr_d[i] = row_addr_q[i]; + + // The data in the SDRAM must be refreshed periodically. + // This conter ensures that the data remains intact. + refresh_flag_d = refresh_flag_q; + refresh_ctr_d = refresh_ctr_q + 1'b1; + if (refresh_ctr_q > 10'd750) begin + refresh_ctr_d = 10'd0; + refresh_flag_d = 1'b1; + end + + saved_rw_d = saved_rw_q; + saved_data_d = saved_data_q; + saved_addr_d = saved_addr_q; + ready_d = ready_q; + + // This is a queue of 1 for read/write operations. + // When the queue is empty we aren't busy and can + // accept another request. + if (ready_q && in_valid) begin + saved_rw_d = rw; + saved_data_d = data_in; + saved_addr_d = addr; + ready_d = 1'b0; + end + + case (state_q) + ///// INITALIZATION ///// + INIT: begin + ready_d = 1'b0; + row_open_d = 4'b0; + out_valid_d = 1'b0; + a_d = 13'b0; + ba_d = 2'b0; + cle_d = 1'b1; + state_d = WAIT; + delay_ctr_d = 16'd10100; // wait for 101us + next_state_d = PRECHARGE_INIT; + dq_en_d = 1'b0; + end + WAIT: begin + delay_ctr_d = delay_ctr_q - 1'b1; + if (delay_ctr_q == 13'd0) begin + state_d = next_state_q; + if (next_state_q == WRITE) begin + dq_en_d = 1'b1; // enable the bus early + dq_d = data_q[7:0]; + end + end + end + PRECHARGE_INIT: begin + cmd_d = CMD_PRECHARGE; + a_d[10] = 1'b1; // all banks + ba_d = 2'd0; + state_d = WAIT; + next_state_d = REFRESH_INIT_1; + delay_ctr_d = 13'd0; + end + REFRESH_INIT_1: begin + cmd_d = CMD_REFRESH; + state_d = WAIT; + delay_ctr_d = 13'd7; + next_state_d = REFRESH_INIT_2; + end + REFRESH_INIT_2: begin + cmd_d = CMD_REFRESH; + state_d = WAIT; + delay_ctr_d = 13'd7; + next_state_d = LOAD_MODE_REG; + end + LOAD_MODE_REG: begin + cmd_d = CMD_LOAD_MODE_REG; + ba_d = 2'b0; + // Reserved, Burst Access, Standard Op, CAS = 2, Sequential, Burst = 4 + a_d = {3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b010}; //010 + state_d = WAIT; + delay_ctr_d = 13'd1; + next_state_d = IDLE; + refresh_flag_d = 1'b0; + refresh_ctr_d = 10'b1; + ready_d = 1'b1; + end + + ///// IDLE STATE ///// + IDLE: begin + if (refresh_flag_q) begin // we need to do a refresh + state_d = PRECHARGE; + next_state_d = REFRESH; + precharge_bank_d = 3'b100; // all banks + refresh_flag_d = 1'b0; // clear the refresh flag + end else if (!ready_q) begin // operation waiting + ready_d = 1'b1; // clear the queue + rw_op_d = saved_rw_q; // save the values we'll need later + addr_d = saved_addr_q; + + if (saved_rw_q) // Write + data_d = saved_data_q; + + // if the row is open we don't have to activate it + if (row_open_q[saved_addr_q[9:8]]) begin + if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin + // Row is already open + if (saved_rw_q) + state_d = WRITE; + else + state_d = READ; + end else begin + // A different row in the bank is open + state_d = PRECHARGE; // precharge open row + precharge_bank_d = {1'b0, saved_addr_q[9:8]}; + next_state_d = ACTIVATE; // open current row + end + end else begin + // no rows open + state_d = ACTIVATE; // open the row + end + end + end + + ///// REFRESH ///// + REFRESH: begin + cmd_d = CMD_REFRESH; + state_d = WAIT; + delay_ctr_d = 13'd6; // gotta wait 7 clocks (66ns) + next_state_d = IDLE; + end + + ///// ACTIVATE ///// + ACTIVATE: begin + cmd_d = CMD_ACTIVE; + a_d = addr_q[22:10]; + ba_d = addr_q[9:8]; + delay_ctr_d = 13'd0; + state_d = WAIT; + + if (rw_op_q) + next_state_d = WRITE; + else + next_state_d = READ; + + row_open_d[addr_q[9:8]] = 1'b1; // row is now open + row_addr_d[addr_q[9:8]] = addr_q[22:10]; + end + + ///// READ ///// + READ: begin + cmd_d = CMD_READ; + a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0}; + ba_d = addr_q[9:8]; + state_d = WAIT; + delay_ctr_d = 13'd2; // wait for the data to show up + next_state_d = READ_RES; + + end + READ_RES: begin + byte_ctr_d = byte_ctr_q + 1'b1; // we need to read in 4 bytes + data_d = {dqi_q, data_q[31:8]}; // shift the data in + if (byte_ctr_q == 2'd3) begin + out_valid_d = 1'b1; + state_d = IDLE; + end + end + + ///// WRITE ///// + WRITE: begin + byte_ctr_d = byte_ctr_q + 1'b1; // send out 4 bytes + + if (byte_ctr_q == 2'd0) // first byte send write command + cmd_d = CMD_WRITE; + + dq_d = data_q[7:0]; + data_d = {8'h00, data_q[31:8]}; // shift the data out + dq_en_d = 1'b1; // enable out bus + a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00}; + ba_d = addr_q[9:8]; + + if (byte_ctr_q == 2'd3) begin + state_d = IDLE; + end + end + + ///// PRECHARGE ///// + PRECHARGE: begin + cmd_d = CMD_PRECHARGE; + a_d[10] = precharge_bank_q[2]; // all banks + ba_d = precharge_bank_q[1:0]; + state_d = WAIT; + delay_ctr_d = 13'd0; + + if (precharge_bank_q[2]) begin + row_open_d = 4'b0000; // closed all rows + end else begin + row_open_d[precharge_bank_q[1:0]] = 1'b0; // closed one row + end + end + + default: state_d = INIT; + endcase + + end + + always @(posedge clk) begin + if(rst) begin + cle_q <= 1'b0; + dq_en_q <= 1'b0; + state_q <= INIT; + ready_q <= 1'b0; + end else begin + cle_q <= cle_d; + dq_en_q <= dq_en_d; + state_q <= state_d; + ready_q <= ready_d; + end + + saved_rw_q <= saved_rw_d; + saved_data_q <= saved_data_d; + saved_addr_q <= saved_addr_d; + + cmd_q <= cmd_d; + dqm_q <= dqm_d; + ba_q <= ba_d; + a_q <= a_d; + dq_q <= dq_d; + dqi_q <= dqi_d; + + next_state_q <= next_state_d; + refresh_flag_q <= refresh_flag_d; + refresh_ctr_q <= refresh_ctr_d; + data_q <= data_d; + addr_q <= addr_d; + out_valid_q <= out_valid_d; + row_open_q <= row_open_d; + for (i = 0; i < 4; i = i + 1) + row_addr_q[i] <= row_addr_d[i]; + precharge_bank_q <= precharge_bank_d; + rw_op_q <= rw_op_d; + byte_ctr_q <= byte_ctr_d; + delay_ctr_q <= delay_ctr_d; + end +endmodule diff --git a/output_files/ram_video.qip b/output_files.old/pll_i2s.qip similarity index 100% rename from output_files/ram_video.qip rename to output_files.old/pll_i2s.qip diff --git a/output_files/rom_scr.qip b/output_files.old/pll_video.qip similarity index 100% rename from output_files/rom_scr.qip rename to output_files.old/pll_video.qip diff --git a/output_files.old/ram_video.qip b/output_files.old/ram_video.qip new file mode 100644 index 0000000..e69de29 diff --git a/output_files.old/rom_scr.qip b/output_files.old/rom_scr.qip new file mode 100644 index 0000000..e69de29 diff --git a/output_files.old/spectrum.asm.rpt b/output_files.old/spectrum.asm.rpt new file mode 100644 index 0000000..2a976a5 --- /dev/null +++ b/output_files.old/spectrum.asm.rpt @@ -0,0 +1,186 @@ +Assembler report for spectrum +Sat Apr 2 16:35:54 2022 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: spectrum.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Apr 2 16:35:54 2022 ; +; Revision Name ; spectrum ; +; Top-level Entity Name ; spectrum ; +; Family ; Cyclone IV E ; +; Device ; EP4CE22F17C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Assembler Settings ; ++--------------------------------------------------------------------------------+ +Option : Use smart compilation +Setting : Off +Default Value : Off + +Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation +Setting : On +Default Value : On + +Option : Enable compact report table +Setting : Off +Default Value : Off + +Option : Generate compressed bitstreams +Setting : On +Default Value : On + +Option : Compression mode +Setting : Off +Default Value : Off + +Option : Clock source for configuration device +Setting : Internal +Default Value : Internal + +Option : Clock frequency of the configuration device +Setting : 10 MHZ +Default Value : 10 MHz + +Option : Divide clock frequency by +Setting : 1 +Default Value : 1 + +Option : Auto user code +Setting : On +Default Value : On + +Option : Use configuration device +Setting : Off +Default Value : Off + +Option : Configuration device +Setting : Auto +Default Value : Auto + +Option : Configuration device auto user code +Setting : Off +Default Value : Off + +Option : Generate Tabular Text File (.ttf) For Target Device +Setting : Off +Default Value : Off + +Option : Generate Raw Binary File (.rbf) For Target Device +Setting : Off +Default Value : Off + +Option : Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device +Setting : Off +Default Value : Off + +Option : Hexadecimal Output File start address +Setting : 0 +Default Value : 0 + +Option : Hexadecimal Output File count direction +Setting : Up +Default Value : Up + +Option : Release clears before tri-states +Setting : Off +Default Value : Off + +Option : Auto-restart configuration after error +Setting : On +Default Value : On + +Option : Enable OCT_DONE +Setting : Off +Default Value : Off + +Option : Generate Serial Vector Format File (.svf) for Target Device +Setting : Off +Default Value : Off + +Option : Generate a JEDEC STAPL Format File (.jam) for Target Device +Setting : Off +Default Value : Off + +Option : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device +Setting : Off +Default Value : Off + +Option : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device +Setting : On +Default Value : On ++--------------------------------------------------------------------------------+ + + + ++---------------------------+ +; Assembler Generated Files ; ++---------------------------+ +; File Name ; ++---------------------------+ +; spectrum.sof ; ++---------------------------+ + + ++----------------------------------------+ +; Assembler Device Options: spectrum.sof ; ++----------------+-----------------------+ +; Option ; Setting ; ++----------------+-----------------------+ +; Device ; EP4CE22F17C6 ; +; JTAG usercode ; 0x00589516 ; +; Checksum ; 0x00589516 ; ++----------------+-----------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Assembler + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Sat Apr 2 16:35:52 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 399 megabytes + Info: Processing ended: Sat Apr 2 16:35:54 2022 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/output_files.old/spectrum.cdf b/output_files.old/spectrum.cdf new file mode 100644 index 0000000..e4b0607 --- /dev/null +++ b/output_files.old/spectrum.cdf @@ -0,0 +1,13 @@ +/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP4CE22F17) Path("/home/benny/work/fpga/spectrum/output_files/") File("spectrum.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/output_files.old/spectrum.done b/output_files.old/spectrum.done new file mode 100644 index 0000000..a72b5f0 --- /dev/null +++ b/output_files.old/spectrum.done @@ -0,0 +1 @@ +Sat Apr 2 18:51:29 2022 diff --git a/output_files.old/spectrum.eda.rpt b/output_files.old/spectrum.eda.rpt new file mode 100644 index 0000000..be158c7 --- /dev/null +++ b/output_files.old/spectrum.eda.rpt @@ -0,0 +1,107 @@ +EDA Netlist Writer report for spectrum +Sat Apr 2 16:36:04 2022 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Sat Apr 2 16:36:04 2022 ; +; Revision Name ; spectrum ; +; Top-level Entity Name ; spectrum ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------------------------------------------+ +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum.vo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo ; +; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_v.sdo ; ++--------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit EDA Netlist Writer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Sat Apr 2 16:36:01 2022 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum +Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum_min_1200mv_0c_fast.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 384 megabytes + Info: Processing ended: Sat Apr 2 16:36:04 2022 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/output_files.old/spectrum.fit.rpt b/output_files.old/spectrum.fit.rpt new file mode 100644 index 0000000..3fb3f0b --- /dev/null +++ b/output_files.old/spectrum.fit.rpt @@ -0,0 +1,26840 @@ +Fitter report for spectrum +Sat Apr 2 16:35:50 2022 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Fitter Netlist Optimizations + 7. Ignored Assignments + 8. Incremental Compilation Preservation Summary + 9. Incremental Compilation Partition Settings + 10. Incremental Compilation Placement Preservation + 11. Pin-Out File + 12. Fitter Resource Usage Summary + 13. Fitter Partition Statistics + 14. Input Pins + 15. Output Pins + 16. Bidir Pins + 17. Dual Purpose and Dedicated Pins + 18. I/O Bank Usage + 19. All Package Pins + 20. PLL Summary + 21. PLL Usage + 22. Fitter Resource Utilization by Entity + 23. Delay Chain Summary + 24. Pad To Core Delay Chain Fanout + 25. Control Signals + 26. Global & Other Fast Signals + 27. Non-Global High Fan-Out Signals + 28. Fitter RAM Summary + 29. |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM + 30. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM + 31. |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM + 32. Routing Usage Summary + 33. LAB Logic Elements + 34. LAB-wide Signals + 35. LAB Signals Sourced + 36. LAB Signals Sourced Out + 37. LAB Distinct Inputs + 38. I/O Rules Summary + 39. I/O Rules Details + 40. I/O Rules Matrix + 41. Fitter Device Options + 42. Operating Settings and Conditions + 43. Estimated Delay Added for Hold Timing Summary + 44. Estimated Delay Added for Hold Timing Details + 45. Fitter Messages + 46. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------+ +; Fitter Status ; Successful - Sat Apr 2 16:35:50 2022 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; spectrum ; +; Top-level Entity Name ; spectrum ; +; Family ; Cyclone IV E ; +; Device ; EP4CE22F17C6 ; +; Timing Models ; Final ; +; Total logic elements ; 2,621 / 22,320 ( 12 % ) ; +; Total combinational functions ; 2,487 / 22,320 ( 11 % ) ; +; Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; +; Total registers ; 664 ; +; Total pins ; 114 / 154 ( 74 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; +; Total PLLs ; 2 / 4 ( 50 % ) ; ++------------------------------------+--------------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------------------+ +Option : Device +Setting : EP4CE22F17C6 +Default Value : + +Option : Nominal Core Supply Voltage +Setting : 1.2V +Default Value : + +Option : Minimum Core Junction Temperature +Setting : 0 +Default Value : + +Option : Maximum Core Junction Temperature +Setting : 85 +Default Value : + +Option : Fit Attempts to Skip +Setting : 0 +Default Value : 0.0 + +Option : Device I/O Standard +Setting : 2.5 V +Default Value : + +Option : Use smart compilation +Setting : Off +Default Value : Off + +Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation +Setting : On +Default Value : On + +Option : Enable compact report table +Setting : Off +Default Value : Off + +Option : Auto Merge PLLs +Setting : On +Default Value : On + +Option : Router Timing Optimization Level +Setting : Normal +Default Value : Normal + +Option : Perform Clocking Topology Analysis During Routing +Setting : Off +Default Value : Off + +Option : Placement Effort Multiplier +Setting : 1.0 +Default Value : 1.0 + +Option : Router Effort Multiplier +Setting : 1.0 +Default Value : 1.0 + +Option : Optimize Hold Timing +Setting : All Paths +Default Value : All Paths + +Option : Optimize Multi-Corner Timing +Setting : On +Default Value : On + +Option : PowerPlay Power Optimization +Setting : Normal compilation +Default Value : Normal compilation + +Option : SSN Optimization +Setting : Off +Default Value : Off + +Option : Optimize Timing +Setting : Normal compilation +Default Value : Normal compilation + +Option : Optimize Timing for ECOs +Setting : Off +Default Value : Off + +Option : Regenerate full fit report during ECO compiles +Setting : Off +Default Value : Off + +Option : Optimize IOC Register Placement for Timing +Setting : Normal +Default Value : Normal + +Option : Limit to One Fitting Attempt +Setting : Off +Default Value : Off + +Option : Final Placement Optimizations +Setting : Automatically +Default Value : Automatically + +Option : Fitter Aggressive Routability Optimizations +Setting : Automatically +Default Value : Automatically + +Option : Fitter Initial Placement Seed +Setting : 1 +Default Value : 1 + +Option : PCI I/O +Setting : Off +Default Value : Off + +Option : Weak Pull-Up Resistor +Setting : Off +Default Value : Off + +Option : Enable Bus-Hold Circuitry +Setting : Off +Default Value : Off + +Option : Auto Packed Registers +Setting : Auto +Default Value : Auto + +Option : Auto Delay Chains +Setting : On +Default Value : On + +Option : Auto Delay Chains for High Fanout Input Pins +Setting : Off +Default Value : Off + +Option : Allow Single-ended Buffer for Differential-XSTL Input +Setting : Off +Default Value : Off + +Option : Treat Bidirectional Pin as Output Pin +Setting : Off +Default Value : Off + +Option : Perform Physical Synthesis for Combinational Logic for Fitting +Setting : Off +Default Value : Off + +Option : Perform Physical Synthesis for Combinational Logic for Performance +Setting : Off +Default Value : Off + +Option : Perform Register Duplication for Performance +Setting : Off +Default Value : Off + +Option : Perform Logic to Memory Mapping for Fitting +Setting : Off +Default Value : Off + +Option : Perform Register Retiming for Performance +Setting : Off +Default Value : Off + +Option : Perform Asynchronous Signal Pipelining +Setting : Off +Default Value : Off + +Option : Fitter Effort +Setting : Auto Fit +Default Value : Auto Fit + +Option : Physical Synthesis Effort Level +Setting : Normal +Default Value : Normal + +Option : Logic Cell Insertion - Logic Duplication +Setting : Auto +Default Value : Auto + +Option : Auto Register Duplication +Setting : Auto +Default Value : Auto + +Option : Auto Global Clock +Setting : On +Default Value : On + +Option : Auto Global Register Control Signals +Setting : On +Default Value : On + +Option : Reserve all unused pins +Setting : As input tri-stated with weak pull-up +Default Value : As input tri-stated with weak pull-up + +Option : Synchronizer Identification +Setting : Off +Default Value : Off + +Option : Enable Beneficial Skew Optimization +Setting : On +Default Value : On + +Option : Optimize Design for Metastability +Setting : On +Default Value : On + +Option : Force Fitter to Avoid Periphery Placement Warnings +Setting : Off +Default Value : Off + +Option : Enable input tri-state on active configuration pins in user mode +Setting : Off +Default Value : Off ++--------------------------------------------------------------------------------+ + + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------+ +; I/O Assignment Warnings ; ++---------------+------------------------+ +; Pin Name ; Reason ; ++---------------+------------------------+ +; LED[0] ; Missing drive strength ; +; LED[1] ; Missing drive strength ; +; LED[2] ; Missing drive strength ; +; LED[3] ; Missing drive strength ; +; LED[4] ; Missing drive strength ; +; LED[5] ; Missing drive strength ; +; LED[6] ; Missing drive strength ; +; LED[7] ; Missing drive strength ; +; AUD_XCK ; Missing drive strength ; +; AUD_ADCLRCK ; Missing drive strength ; +; AUD_DACLRCK ; Missing drive strength ; +; AUD_BCLK ; Missing drive strength ; +; AUD_DACDAT ; Missing drive strength ; +; VGA_R[0] ; Missing drive strength ; +; VGA_R[1] ; Missing drive strength ; +; VGA_R[2] ; Missing drive strength ; +; VGA_R[3] ; Missing drive strength ; +; VGA_G[0] ; Missing drive strength ; +; VGA_G[1] ; Missing drive strength ; +; VGA_G[2] ; Missing drive strength ; +; VGA_G[3] ; Missing drive strength ; +; VGA_B[0] ; Missing drive strength ; +; VGA_B[1] ; Missing drive strength ; +; VGA_B[2] ; Missing drive strength ; +; VGA_B[3] ; Missing drive strength ; +; VGA_HS ; Missing drive strength ; +; VGA_VS ; Missing drive strength ; +; GPIO_1[0] ; Missing drive strength ; +; GPIO_1[1] ; Missing drive strength ; +; GPIO_1[2] ; Missing drive strength ; +; GPIO_1[3] ; Missing drive strength ; +; GPIO_1[4] ; Missing drive strength ; +; GPIO_1[5] ; Missing drive strength ; +; GPIO_1[6] ; Missing drive strength ; +; GPIO_1[7] ; Missing drive strength ; +; GPIO_1[8] ; Missing drive strength ; +; GPIO_1[9] ; Missing drive strength ; +; GPIO_1[10] ; Missing drive strength ; +; GPIO_1[11] ; Missing drive strength ; +; GPIO_1[12] ; Missing drive strength ; +; GPIO_1[13] ; Missing drive strength ; +; GPIO_1[14] ; Missing drive strength ; +; GPIO_1[15] ; Missing drive strength ; +; GPIO_1[16] ; Missing drive strength ; +; GPIO_1[17] ; Missing drive strength ; +; GPIO_1[18] ; Missing drive strength ; +; GPIO_1[19] ; Missing drive strength ; +; GPIO_1[20] ; Missing drive strength ; +; GPIO_1[21] ; Missing drive strength ; +; GPIO_1[22] ; Missing drive strength ; +; GPIO_1[23] ; Missing drive strength ; +; GPIO_1[24] ; Missing drive strength ; +; GPIO_1[25] ; Missing drive strength ; +; GPIO_1[26] ; Missing drive strength ; +; GPIO_1[27] ; Missing drive strength ; +; GPIO_1[28] ; Missing drive strength ; +; GPIO_1[29] ; Missing drive strength ; +; GPIO_1[30] ; Missing drive strength ; +; GPIO_1[31] ; Missing drive strength ; +; GPIO_1[32] ; Missing drive strength ; +; GPIO_1[33] ; Missing drive strength ; +; buzzer_out ; Missing drive strength ; +; DRAM_BA[0] ; Missing drive strength ; +; DRAM_BA[1] ; Missing drive strength ; +; DRAM_DQM[0] ; Missing drive strength ; +; DRAM_DQM[1] ; Missing drive strength ; +; DRAM_RAS_N ; Missing drive strength ; +; DRAM_CAS_N ; Missing drive strength ; +; DRAM_CKE ; Missing drive strength ; +; DRAM_CLK ; Missing drive strength ; +; DRAM_WE_N ; Missing drive strength ; +; DRAM_CS_N ; Missing drive strength ; +; DRAM_ADDR[0] ; Missing drive strength ; +; DRAM_ADDR[1] ; Missing drive strength ; +; DRAM_ADDR[2] ; Missing drive strength ; +; DRAM_ADDR[3] ; Missing drive strength ; +; DRAM_ADDR[4] ; Missing drive strength ; +; DRAM_ADDR[5] ; Missing drive strength ; +; DRAM_ADDR[6] ; Missing drive strength ; +; DRAM_ADDR[7] ; Missing drive strength ; +; DRAM_ADDR[8] ; Missing drive strength ; +; DRAM_ADDR[9] ; Missing drive strength ; +; DRAM_ADDR[10] ; Missing drive strength ; +; DRAM_ADDR[11] ; Missing drive strength ; +; DRAM_ADDR[12] ; Missing drive strength ; +; I2C_SCLK ; Missing drive strength ; +; I2C_SDAT ; Missing drive strength ; +; DRAM_DQ[0] ; Missing drive strength ; +; DRAM_DQ[1] ; Missing drive strength ; +; DRAM_DQ[2] ; Missing drive strength ; +; DRAM_DQ[3] ; Missing drive strength ; +; DRAM_DQ[4] ; Missing drive strength ; +; DRAM_DQ[5] ; Missing drive strength ; +; DRAM_DQ[6] ; Missing drive strength ; +; DRAM_DQ[7] ; Missing drive strength ; +; DRAM_DQ[8] ; Missing drive strength ; +; DRAM_DQ[9] ; Missing drive strength ; +; DRAM_DQ[10] ; Missing drive strength ; +; DRAM_DQ[11] ; Missing drive strength ; +; DRAM_DQ[12] ; Missing drive strength ; +; DRAM_DQ[13] ; Missing drive strength ; +; DRAM_DQ[14] ; Missing drive strength ; +; DRAM_DQ[15] ; Missing drive strength ; ++---------------+------------------------+ + + ++--------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++--------------------------------------------------------------------------------+ +Node : sdram_controller:sdram_|r.address[0] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[0]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[0]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[1] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[1]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[1]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[2] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[2]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[3] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[3]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[4] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[4] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[4]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[4]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[5] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[5] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[5]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[5]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[6] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[6]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[7] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[7]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[8] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[8]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[9] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[9]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[10] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[10]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[10] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[10]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[10]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[11]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[12]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.bank[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_BA[0]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.bank[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_BA[1]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.dq_masks[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_DQM[0]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.dq_masks[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_DQM[1]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.state[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_WE_N~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.state[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_CAS_N~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.state[2] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_RAS_N~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : I2C_SCLK~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Action : Inverted +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : I2C_SDAT~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Action : Inverted +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : AUD_BCLK~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : AUD_ADCLRCK~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : AUD_DACLRCK~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : AUD_XCK~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : AUD_DACDAT~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|video:video_|VGA_HS +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|video:video_|VGA_HS +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : VGA_HS~output +Destination Port : I +Destination Port Name : + +Node : ula:ula_|video:video_|VGA_VS +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : ula:ula_|video:video_|VGA_VS +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : VGA_VS~output +Destination Port : I +Destination Port Name : ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------------------------------------------------------------------------+ +Name : Location +Ignored Entity : +Ignored From : +Ignored To : ADC_CS_N +Ignored Value : PIN_A10 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : ADC_SADDR +Ignored Value : PIN_B10 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : ADC_SCLK +Ignored Value : PIN_B14 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : ADC_SDAT +Ignored Value : PIN_A9 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : EPCS_ASDO +Ignored Value : PIN_C1 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : EPCS_DATA0 +Ignored Value : PIN_H2 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : EPCS_DCLK +Ignored Value : PIN_H1 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : EPCS_NCSO +Ignored Value : PIN_D2 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[0] +Ignored Value : PIN_D3 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[1] +Ignored Value : PIN_C3 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[2] +Ignored Value : PIN_A2 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[3] +Ignored Value : PIN_A3 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[4] +Ignored Value : PIN_B3 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[5] +Ignored Value : PIN_B4 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[6] +Ignored Value : PIN_A4 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[7] +Ignored Value : PIN_B5 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[8] +Ignored Value : PIN_A5 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0[9] +Ignored Value : PIN_D5 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0_IN[0] +Ignored Value : PIN_A8 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_0_IN[1] +Ignored Value : PIN_B8 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_1_IN[0] +Ignored Value : PIN_T9 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_1_IN[1] +Ignored Value : PIN_R9 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[0] +Ignored Value : PIN_A14 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[10] +Ignored Value : PIN_F14 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[11] +Ignored Value : PIN_G16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[12] +Ignored Value : PIN_G15 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[1] +Ignored Value : PIN_B16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[2] +Ignored Value : PIN_C14 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[3] +Ignored Value : PIN_C16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[4] +Ignored Value : PIN_C15 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[5] +Ignored Value : PIN_D16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[6] +Ignored Value : PIN_D15 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[7] +Ignored Value : PIN_D14 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[8] +Ignored Value : PIN_F15 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2[9] +Ignored Value : PIN_F16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2_IN[0] +Ignored Value : PIN_E15 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2_IN[1] +Ignored Value : PIN_E16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : GPIO_2_IN[2] +Ignored Value : PIN_M16 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : G_SENSOR_CS_N +Ignored Value : PIN_G5 +Ignored Source : QSF Assignment + +Name : Location +Ignored Entity : +Ignored From : +Ignored To : G_SENSOR_INT +Ignored Value : PIN_M2 +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : ADC_CS_N +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : ADC_SADDR +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : ADC_SCLK +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : ADC_SDAT +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : EPCS_ASDO +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : EPCS_DATA0 +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : EPCS_DCLK +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : EPCS_NCSO +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[0] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[1] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[2] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[3] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[4] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[5] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[6] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[7] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[8] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0[9] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0_IN[0] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_0_IN[1] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_1_IN[0] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_1_IN[1] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[0] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[10] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[11] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[12] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[1] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[2] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[3] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[4] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[5] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[6] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[7] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[8] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2[9] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2_IN[0] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2_IN[1] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : GPIO_2_IN[2] +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : G_SENSOR_CS_N +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment + +Name : I/O Standard +Ignored Entity : spectrum +Ignored From : +Ignored To : G_SENSOR_INT +Ignored Value : 3.3-V LVTTL +Ignored Source : QSF Assignment ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++--------------------------------------------------------------------------------+ +Type : Placement (by node) +Total [A + B] : +From Design Partitions [A] : +From Rapid Recompile [B] : + +Type : -- Requested +Total [A + B] : 0.00 % ( 0 / 3459 ) +From Design Partitions [A] : 0.00 % ( 0 / 3459 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3459 ) + +Type : -- Achieved +Total [A + B] : 0.00 % ( 0 / 3459 ) +From Design Partitions [A] : 0.00 % ( 0 / 3459 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3459 ) + +Type : +Total [A + B] : +From Design Partitions [A] : +From Rapid Recompile [B] : + +Type : Routing (by net) +Total [A + B] : +From Design Partitions [A] : +From Rapid Recompile [B] : + +Type : -- Requested +Total [A + B] : 0.00 % ( 0 / 0 ) +From Design Partitions [A] : 0.00 % ( 0 / 0 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 0 ) + +Type : -- Achieved +Total [A + B] : 0.00 % ( 0 / 0 ) +From Design Partitions [A] : 0.00 % ( 0 / 0 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 0 ) ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------------------------------------------------------+ +Partition Name : Top +Partition Type : User-created +Netlist Type Used : Source File +Preservation Level Used : N/A +Netlist Type Requested : Source File +Preservation Level Requested : N/A +Contents : + +Partition Name : hard_block:auto_generated_inst +Partition Type : Auto-generated +Netlist Type Used : Source File +Preservation Level Used : N/A +Netlist Type Requested : Source File +Preservation Level Requested : N/A +Contents : hard_block:auto_generated_inst ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------------------------------------------------------+ +Partition Name : Top +Preservation Achieved : 0.00 % ( 0 / 3442 ) +Preservation Level Used : N/A +Netlist Type Used : Source File +Preservation Method : N/A +Notes : + +Partition Name : hard_block:auto_generated_inst +Preservation Achieved : 0.00 % ( 0 / 17 ) +Preservation Level Used : N/A +Netlist Type Used : Source File +Preservation Method : N/A +Notes : ++--------------------------------------------------------------------------------+ + + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.pin. + + ++--------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------+ +; Total logic elements ; 2,621 / 22,320 ( 12 % ) ; +; -- Combinational with no register ; 1986 ; +; -- Register only ; 134 ; +; -- Combinational with a register ; 501 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 1780 ; +; -- 3 input functions ; 422 ; +; -- <=2 input functions ; 285 ; +; -- Register only ; 134 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 2411 ; +; -- arithmetic mode ; 76 ; +; ; ; +; Total registers* ; 664 / 23,018 ( 3 % ) ; +; -- Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; +; -- I/O registers ; 29 / 698 ( 4 % ) ; +; ; ; +; Total LABs: partially or completely used ; 193 / 1,395 ( 14 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 114 / 154 ( 74 % ) ; +; -- Clock pins ; 5 / 7 ( 71 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 10 ; +; M9Ks ; 64 / 66 ( 97 % ) ; +; Total block memory bits ; 524,288 / 608,256 ( 86 % ) ; +; Total block memory implementation bits ; 589,824 / 608,256 ( 97 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; +; PLLs ; 2 / 4 ( 50 % ) ; +; Global clocks ; 10 / 20 ( 50 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 6% / 5% / 6% ; +; Peak interconnect usage (total/H/V) ; 27% / 25% / 30% ; +; Maximum fan-out ; 435 ; +; Highest non-global fan-out ; 76 ; +; Total fan-out ; 12665 ; +; Average fan-out ; 3.56 ; ++---------------------------------------------+----------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++--------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++--------------------------------------------------------------------------------+ +Statistic : Difficulty Clustering Region +Top : Low +hard_block:auto_generated_inst : Low + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Total logic elements +Top : 2621 / 22320 ( 12 % ) +hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) + +Statistic : -- Combinational with no register +Top : 1986 +hard_block:auto_generated_inst : 0 + +Statistic : -- Register only +Top : 134 +hard_block:auto_generated_inst : 0 + +Statistic : -- Combinational with a register +Top : 501 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Logic element usage by number of LUT inputs +Top : +hard_block:auto_generated_inst : + +Statistic : -- 4 input functions +Top : 1780 +hard_block:auto_generated_inst : 0 + +Statistic : -- 3 input functions +Top : 422 +hard_block:auto_generated_inst : 0 + +Statistic : -- <=2 input functions +Top : 285 +hard_block:auto_generated_inst : 0 + +Statistic : -- Register only +Top : 134 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Logic elements by mode +Top : +hard_block:auto_generated_inst : + +Statistic : -- normal mode +Top : 2411 +hard_block:auto_generated_inst : 0 + +Statistic : -- arithmetic mode +Top : 76 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Total registers +Top : 664 +hard_block:auto_generated_inst : 0 + +Statistic : -- Dedicated logic registers +Top : 635 / 22320 ( 3 % ) +hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) + +Statistic : -- I/O registers +Top : 58 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Total LABs: partially or completely used +Top : 193 / 1395 ( 14 % ) +hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Virtual pins +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : I/O pins +Top : 114 +hard_block:auto_generated_inst : 0 + +Statistic : Embedded Multiplier 9-bit elements +Top : 0 / 132 ( 0 % ) +hard_block:auto_generated_inst : 0 / 132 ( 0 % ) + +Statistic : Total memory bits +Top : 524288 +hard_block:auto_generated_inst : 0 + +Statistic : Total RAM block bits +Top : 589824 +hard_block:auto_generated_inst : 0 + +Statistic : PLL +Top : 0 / 4 ( 0 % ) +hard_block:auto_generated_inst : 2 / 4 ( 50 % ) + +Statistic : M9K +Top : 64 / 66 ( 96 % ) +hard_block:auto_generated_inst : 0 / 66 ( 0 % ) + +Statistic : Clock control block +Top : 6 / 24 ( 25 % ) +hard_block:auto_generated_inst : 5 / 24 ( 20 % ) + +Statistic : Double Data Rate I/O output circuitry +Top : 29 / 220 ( 13 % ) +hard_block:auto_generated_inst : 0 / 220 ( 0 % ) + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Connections +Top : +hard_block:auto_generated_inst : + +Statistic : -- Input Connections +Top : 278 +hard_block:auto_generated_inst : 2 + +Statistic : -- Registered Input Connections +Top : 258 +hard_block:auto_generated_inst : 0 + +Statistic : -- Output Connections +Top : 20 +hard_block:auto_generated_inst : 260 + +Statistic : -- Registered Output Connections +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Internal Connections +Top : +hard_block:auto_generated_inst : + +Statistic : -- Total Connections +Top : 12669 +hard_block:auto_generated_inst : 274 + +Statistic : -- Registered Connections +Top : 3435 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : External Connections +Top : +hard_block:auto_generated_inst : + +Statistic : -- Top +Top : 36 +hard_block:auto_generated_inst : 262 + +Statistic : -- hard_block:auto_generated_inst +Top : 262 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Partition Interface +Top : +hard_block:auto_generated_inst : + +Statistic : -- Input Ports +Top : 11 +hard_block:auto_generated_inst : 2 + +Statistic : -- Output Ports +Top : 85 +hard_block:auto_generated_inst : 6 + +Statistic : -- Bidir Ports +Top : 18 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Registered Ports +Top : +hard_block:auto_generated_inst : + +Statistic : -- Registered Input Ports +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Registered Output Ports +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : +Top : +hard_block:auto_generated_inst : + +Statistic : Port Connectivity +Top : +hard_block:auto_generated_inst : + +Statistic : -- Input Ports driven by GND +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Output Ports driven by GND +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Input Ports driven by VCC +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Output Ports driven by VCC +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Input Ports with no Source +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Output Ports with no Source +Top : 0 +hard_block:auto_generated_inst : 0 + +Statistic : -- Input Ports with no Fanout +Top : 0 +hard_block:auto_generated_inst : 1 + +Statistic : -- Output Ports with no Fanout +Top : 0 +hard_block:auto_generated_inst : 0 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Input Pins ; ++--------------------------------------------------------------------------------+ +Name : AUD_ADCDAT +Pin # : D8 +I/O Bank : 8 +X coordinate : 23 +Y coordinate : 34 +Z coordinate : 21 +Combinational Fan-Out : 1 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : CLOCK_50 +Pin # : R8 +I/O Bank : 3 +X coordinate : 27 +Y coordinate : 0 +Z coordinate : 21 +Combinational Fan-Out : 52 +Registered Fan-Out : 0 +Global : yes +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : KEY[0] +Pin # : J15 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 14 +Z coordinate : 0 +Combinational Fan-Out : 1 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : KEY[1] +Pin # : E1 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 16 +Z coordinate : 7 +Combinational Fan-Out : 1 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : PS2_CLK +Pin # : D6 +I/O Bank : 8 +X coordinate : 9 +Y coordinate : 34 +Z coordinate : 7 +Combinational Fan-Out : 1 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : PS2_DAT +Pin # : B7 +I/O Bank : 8 +X coordinate : 18 +Y coordinate : 34 +Z coordinate : 0 +Combinational Fan-Out : 3 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : SW[0] +Pin # : M1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 16 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : SW[1] +Pin # : T8 +I/O Bank : 3 +X coordinate : 27 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : SW[2] +Pin # : B9 +I/O Bank : 7 +X coordinate : 25 +Y coordinate : 34 +Z coordinate : 7 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : SW[3] +Pin # : M15 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 17 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : raw_loader_in +Pin # : B6 +I/O Bank : 8 +X coordinate : 16 +Y coordinate : 34 +Z coordinate : 7 +Combinational Fan-Out : 3 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Pins ; ++--------------------------------------------------------------------------------+ +Name : AUD_ADCLRCK +Pin # : E7 +I/O Bank : 8 +X coordinate : 16 +Y coordinate : 34 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : AUD_BCLK +Pin # : E6 +I/O Bank : 8 +X coordinate : 14 +Y coordinate : 34 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : AUD_DACDAT +Pin # : C8 +I/O Bank : 8 +X coordinate : 23 +Y coordinate : 34 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : AUD_DACLRCK +Pin # : C6 +I/O Bank : 8 +X coordinate : 18 +Y coordinate : 34 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : AUD_XCK +Pin # : A7 +I/O Bank : 8 +X coordinate : 20 +Y coordinate : 34 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[0] +Pin # : P2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 4 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[10] +Pin # : N2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 8 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[11] +Pin # : N1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 7 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[12] +Pin # : L4 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 6 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[1] +Pin # : N5 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[2] +Pin # : N6 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[3] +Pin # : M8 +I/O Bank : 3 +X coordinate : 20 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[4] +Pin # : P8 +I/O Bank : 3 +X coordinate : 25 +Y coordinate : 0 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[5] +Pin # : T7 +I/O Bank : 3 +X coordinate : 18 +Y coordinate : 0 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[6] +Pin # : N8 +I/O Bank : 3 +X coordinate : 20 +Y coordinate : 0 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[7] +Pin # : T6 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[8] +Pin # : R1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 5 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[9] +Pin # : P1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 4 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_BA[0] +Pin # : M7 +I/O Bank : 3 +X coordinate : 11 +Y coordinate : 0 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_BA[1] +Pin # : M6 +I/O Bank : 3 +X coordinate : 7 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CAS_N +Pin # : L1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 11 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CKE +Pin # : L7 +I/O Bank : 3 +X coordinate : 16 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CLK +Pin # : R4 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CS_N +Pin # : P6 +I/O Bank : 3 +X coordinate : 11 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_DQM[0] +Pin # : R6 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_DQM[1] +Pin # : T5 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_RAS_N +Pin # : L2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 11 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_WE_N +Pin # : C2 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 27 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[0] +Pin # : F13 +I/O Bank : 6 +X coordinate : 53 +Y coordinate : 21 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[10] +Pin # : P11 +I/O Bank : 4 +X coordinate : 38 +Y coordinate : 0 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[11] +Pin # : R10 +I/O Bank : 4 +X coordinate : 34 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[12] +Pin # : N12 +I/O Bank : 4 +X coordinate : 47 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[13] +Pin # : P9 +I/O Bank : 4 +X coordinate : 38 +Y coordinate : 0 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[14] +Pin # : N9 +I/O Bank : 4 +X coordinate : 29 +Y coordinate : 0 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[15] +Pin # : N11 +I/O Bank : 4 +X coordinate : 43 +Y coordinate : 0 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[16] +Pin # : L16 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 11 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[17] +Pin # : K16 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 12 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[18] +Pin # : R16 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 8 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[19] +Pin # : L15 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 11 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[1] +Pin # : T15 +I/O Bank : 4 +X coordinate : 45 +Y coordinate : 0 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[20] +Pin # : P15 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 6 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[21] +Pin # : P16 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 7 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[22] +Pin # : R14 +I/O Bank : 4 +X coordinate : 49 +Y coordinate : 0 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[23] +Pin # : N16 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 9 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[24] +Pin # : N15 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 9 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[25] +Pin # : P14 +I/O Bank : 4 +X coordinate : 49 +Y coordinate : 0 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[26] +Pin # : L14 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 9 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[27] +Pin # : N14 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 6 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[28] +Pin # : M10 +I/O Bank : 4 +X coordinate : 43 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[29] +Pin # : L13 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 10 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[2] +Pin # : T14 +I/O Bank : 4 +X coordinate : 45 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[30] +Pin # : J16 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 14 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[31] +Pin # : K15 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 13 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[32] +Pin # : J13 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 16 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[33] +Pin # : J14 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 15 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[3] +Pin # : T13 +I/O Bank : 4 +X coordinate : 40 +Y coordinate : 0 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[4] +Pin # : R13 +I/O Bank : 4 +X coordinate : 40 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[5] +Pin # : T12 +I/O Bank : 4 +X coordinate : 36 +Y coordinate : 0 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[6] +Pin # : R12 +I/O Bank : 4 +X coordinate : 36 +Y coordinate : 0 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[7] +Pin # : T11 +I/O Bank : 4 +X coordinate : 36 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[8] +Pin # : T10 +I/O Bank : 4 +X coordinate : 34 +Y coordinate : 0 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : GPIO_1[9] +Pin # : R11 +I/O Bank : 4 +X coordinate : 34 +Y coordinate : 0 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +TRI Primitive : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[0] +Pin # : A15 +I/O Bank : 7 +X coordinate : 38 +Y coordinate : 34 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[1] +Pin # : A13 +I/O Bank : 7 +X coordinate : 49 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[2] +Pin # : B13 +I/O Bank : 7 +X coordinate : 49 +Y coordinate : 34 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[3] +Pin # : A11 +I/O Bank : 7 +X coordinate : 40 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[4] +Pin # : D1 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 25 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[5] +Pin # : F3 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 26 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[6] +Pin # : B1 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 28 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : LED[7] +Pin # : L3 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 10 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_B[0] +Pin # : C11 +I/O Bank : 7 +X coordinate : 38 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_B[1] +Pin # : B11 +I/O Bank : 7 +X coordinate : 40 +Y coordinate : 34 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_B[2] +Pin # : A12 +I/O Bank : 7 +X coordinate : 43 +Y coordinate : 34 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_B[3] +Pin # : D11 +I/O Bank : 7 +X coordinate : 51 +Y coordinate : 34 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_G[0] +Pin # : C9 +I/O Bank : 7 +X coordinate : 31 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_G[1] +Pin # : D9 +I/O Bank : 7 +X coordinate : 31 +Y coordinate : 34 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_G[2] +Pin # : E11 +I/O Bank : 7 +X coordinate : 45 +Y coordinate : 34 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_G[3] +Pin # : E10 +I/O Bank : 7 +X coordinate : 45 +Y coordinate : 34 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_HS +Pin # : D12 +I/O Bank : 7 +X coordinate : 51 +Y coordinate : 34 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_R[0] +Pin # : E8 +I/O Bank : 8 +X coordinate : 20 +Y coordinate : 34 +Z coordinate : 7 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_R[1] +Pin # : F8 +I/O Bank : 8 +X coordinate : 20 +Y coordinate : 34 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_R[2] +Pin # : F9 +I/O Bank : 7 +X coordinate : 34 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_R[3] +Pin # : E9 +I/O Bank : 7 +X coordinate : 29 +Y coordinate : 34 +Z coordinate : 14 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : VGA_VS +Pin # : B12 +I/O Bank : 7 +X coordinate : 43 +Y coordinate : 34 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : buzzer_out +Pin # : A6 +I/O Bank : 8 +X coordinate : 16 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Bidir Pins ; ++--------------------------------------------------------------------------------+ +Name : DRAM_DQ[0] +Pin # : G2 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 23 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[10] +Pin # : T3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[11] +Pin # : R3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[12] +Pin # : R5 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[13] +Pin # : P3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[14] +Pin # : N3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[15] +Pin # : K1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 12 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[1] +Pin # : G1 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 23 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[2] +Pin # : L8 +I/O Bank : 3 +X coordinate : 18 +Y coordinate : 0 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[3] +Pin # : K5 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 7 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[4] +Pin # : K2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 12 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[5] +Pin # : J2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 15 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[6] +Pin # : J1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 15 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[7] +Pin # : R7 +I/O Bank : 3 +X coordinate : 16 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[8] +Pin # : T4 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[9] +Pin # : T2 +I/O Bank : 3 +X coordinate : 3 +Y coordinate : 0 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : I2C_SCLK +Pin # : F2 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 24 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : yes +Output Enable Register : no +Power Up High : yes +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : ula:ula_|i2c_loader:i2c_loader_|scl_out (inverted) +Output Enable Group : - + +Name : I2C_SDAT +Pin # : F1 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 23 +Z coordinate : 0 +Combinational Fan-Out : 3 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : yes +Output Enable Register : no +Power Up High : yes +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : ula:ula_|i2c_loader:i2c_loader_|sda_out (inverted) +Output Enable Group : - ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++--------------------------------------------------------------------------------+ +Location : C1 +Pin Name : DIFFIO_L3n, DATA1, ASDO +Reserved As : As input tri-stated +User Signal Name : ~ALTERA_ASDO_DATA1~ +Pin Type : Dual Purpose Pin + +Location : D2 +Pin Name : DIFFIO_L4p, FLASH_nCE, nCSO +Reserved As : As input tri-stated +User Signal Name : ~ALTERA_FLASH_nCE_nCSO~ +Pin Type : Dual Purpose Pin + +Location : F4 +Pin Name : nSTATUS +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : H1 +Pin Name : DCLK +Reserved As : As output driving ground +User Signal Name : ~ALTERA_DCLK~ +Pin Type : Dual Purpose Pin + +Location : H2 +Pin Name : DATA0 +Reserved As : As input tri-stated +User Signal Name : ~ALTERA_DATA0~ +Pin Type : Dual Purpose Pin + +Location : H5 +Pin Name : nCONFIG +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : J3 +Pin Name : nCE +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : J16 +Pin Name : DIFFIO_R9n, DEV_OE +Reserved As : Use as regular IO +User Signal Name : GPIO_1[30] +Pin Type : Dual Purpose Pin + +Location : J15 +Pin Name : DIFFIO_R9p, DEV_CLRn +Reserved As : Use as regular IO +User Signal Name : KEY[0] +Pin Type : Dual Purpose Pin + +Location : H14 +Pin Name : CONF_DONE +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : H13 +Pin Name : MSEL0 +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : H12 +Pin Name : MSEL1 +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : G12 +Pin Name : MSEL2 +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : G12 +Pin Name : MSEL3 +Reserved As : - +User Signal Name : - +Pin Type : Dedicated Programming Pin + +Location : F16 +Pin Name : DIFFIO_R4n, nCEO +Reserved As : Use as programming pin +User Signal Name : ~ALTERA_nCEO~ +Pin Type : Dual Purpose Pin + +Location : B11 +Pin Name : DIFFIO_T20p, PADD0 +Reserved As : Use as regular IO +User Signal Name : VGA_B[1] +Pin Type : Dual Purpose Pin + +Location : A15 +Pin Name : DIFFIO_T19n, PADD1 +Reserved As : Use as regular IO +User Signal Name : LED[0] +Pin Type : Dual Purpose Pin + +Location : F9 +Pin Name : DIFFIO_T17p, PADD4, DQS2T/CQ3T,DPCLK8 +Reserved As : Use as regular IO +User Signal Name : VGA_R[2] +Pin Type : Dual Purpose Pin + +Location : C9 +Pin Name : DIFFIO_T15n, PADD7 +Reserved As : Use as regular IO +User Signal Name : VGA_G[0] +Pin Type : Dual Purpose Pin + +Location : D9 +Pin Name : DIFFIO_T15p, PADD8 +Reserved As : Use as regular IO +User Signal Name : VGA_G[1] +Pin Type : Dual Purpose Pin + +Location : E9 +Pin Name : DIFFIO_T13p, PADD12, DQS4T/CQ5T,DPCLK9 +Reserved As : Use as regular IO +User Signal Name : VGA_R[3] +Pin Type : Dual Purpose Pin + +Location : C8 +Pin Name : DIFFIO_T11p, PADD17, DQS5T/CQ5T#,DPCLK10 +Reserved As : Use as regular IO +User Signal Name : AUD_DACDAT +Pin Type : Dual Purpose Pin + +Location : E8 +Pin Name : DIFFIO_T10n, DATA2 +Reserved As : Use as regular IO +User Signal Name : VGA_R[0] +Pin Type : Dual Purpose Pin + +Location : F8 +Pin Name : DIFFIO_T10p, DATA3 +Reserved As : Use as regular IO +User Signal Name : VGA_R[1] +Pin Type : Dual Purpose Pin + +Location : A7 +Pin Name : DIFFIO_T9n, PADD18 +Reserved As : Use as regular IO +User Signal Name : AUD_XCK +Pin Type : Dual Purpose Pin + +Location : B7 +Pin Name : DIFFIO_T9p, DATA4 +Reserved As : Use as regular IO +User Signal Name : PS2_DAT +Pin Type : Dual Purpose Pin + +Location : A6 +Pin Name : DIFFIO_T7n, DATA14, DQS3T/CQ3T#,DPCLK11 +Reserved As : Use as regular IO +User Signal Name : buzzer_out +Pin Type : Dual Purpose Pin + +Location : B6 +Pin Name : DIFFIO_T7p, DATA13 +Reserved As : Use as regular IO +User Signal Name : raw_loader_in +Pin Type : Dual Purpose Pin + +Location : E7 +Pin Name : DATA5 +Reserved As : Use as regular IO +User Signal Name : AUD_ADCLRCK +Pin Type : Dual Purpose Pin + +Location : E6 +Pin Name : DIFFIO_T6p, DATA6 +Reserved As : Use as regular IO +User Signal Name : AUD_BCLK +Pin Type : Dual Purpose Pin + +Location : D6 +Pin Name : DIFFIO_T4n, DATA9 +Reserved As : Use as regular IO +User Signal Name : PS2_CLK +Pin Type : Dual Purpose Pin ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; I/O Bank Usage ; ++--------------------------------------------------------------------------------+ +I/O Bank : 1 +Usage : 13 / 14 ( 93 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 2 +Usage : 15 / 16 ( 94 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 3 +Usage : 25 / 25 ( 100 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 4 +Usage : 18 / 20 ( 90 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 5 +Usage : 17 / 18 ( 94 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 6 +Usage : 2 / 13 ( 15 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 7 +Usage : 17 / 24 ( 71 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- + +I/O Bank : 8 +Usage : 12 / 24 ( 50 % ) +VCCIO Voltage : 3.3V +VREF Voltage : -- ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; All Package Pins ; ++--------------------------------------------------------------------------------+ +Location : A1 +Pad Number : +I/O Bank : 8 +Pin Name/Usage : VCCIO8 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : A2 +Pad Number : 238 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : A3 +Pad Number : 239 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : A4 +Pad Number : 236 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : A5 +Pad Number : 232 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : A6 +Pad Number : 225 +I/O Bank : 8 +Pin Name/Usage : buzzer_out +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : A7 +Pad Number : 220 +I/O Bank : 8 +Pin Name/Usage : AUD_XCK +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : A8 +Pad Number : 211 +I/O Bank : 8 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : A9 +Pad Number : 209 +I/O Bank : 7 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : A10 +Pad Number : 198 +I/O Bank : 7 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : A11 +Pad Number : 188 +I/O Bank : 7 +Pin Name/Usage : LED[3] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : A12 +Pad Number : 186 +I/O Bank : 7 +Pin Name/Usage : VGA_B[2] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : A13 +Pad Number : 179 +I/O Bank : 7 +Pin Name/Usage : LED[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : A14 +Pad Number : 181 +I/O Bank : 7 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : A15 +Pad Number : 191 +I/O Bank : 7 +Pin Name/Usage : LED[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : A16 +Pad Number : +I/O Bank : 7 +Pin Name/Usage : VCCIO7 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : B1 +Pad Number : 5 +I/O Bank : 1 +Pin Name/Usage : LED[6] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B2 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : B3 +Pad Number : 242 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : B4 +Pad Number : 237 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : B5 +Pad Number : 233 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : B6 +Pad Number : 226 +I/O Bank : 8 +Pin Name/Usage : raw_loader_in +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B7 +Pad Number : 221 +I/O Bank : 8 +Pin Name/Usage : PS2_DAT +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B8 +Pad Number : 212 +I/O Bank : 8 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : B9 +Pad Number : 210 +I/O Bank : 7 +Pin Name/Usage : SW[2] +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B10 +Pad Number : 199 +I/O Bank : 7 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : B11 +Pad Number : 189 +I/O Bank : 7 +Pin Name/Usage : VGA_B[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B12 +Pad Number : 187 +I/O Bank : 7 +Pin Name/Usage : VGA_VS +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B13 +Pad Number : 180 +I/O Bank : 7 +Pin Name/Usage : LED[2] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : B14 +Pad Number : 182 +I/O Bank : 7 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : B15 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : B16 +Pad Number : 164 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : C1 +Pad Number : 7 +I/O Bank : 1 +Pin Name/Usage : ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : N +Bus Hold : no +Weak Pull Up : On + +Location : C2 +Pad Number : 6 +I/O Bank : 1 +Pin Name/Usage : DRAM_WE_N +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : C3 +Pad Number : 245 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : C4 +Pad Number : +I/O Bank : 8 +Pin Name/Usage : VCCIO8 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : C5 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : C6 +Pad Number : 224 +I/O Bank : 8 +Pin Name/Usage : AUD_DACLRCK +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : C7 +Pad Number : +I/O Bank : 8 +Pin Name/Usage : VCCIO8 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : C8 +Pad Number : 215 +I/O Bank : 8 +Pin Name/Usage : AUD_DACDAT +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : C9 +Pad Number : 200 +I/O Bank : 7 +Pin Name/Usage : VGA_G[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : C10 +Pad Number : +I/O Bank : 7 +Pin Name/Usage : VCCIO7 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : C11 +Pad Number : 190 +I/O Bank : 7 +Pin Name/Usage : VGA_B[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : C12 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : C13 +Pad Number : +I/O Bank : 7 +Pin Name/Usage : VCCIO7 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : C14 +Pad Number : 175 +I/O Bank : 7 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : C15 +Pad Number : 174 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : C16 +Pad Number : 173 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : D1 +Pad Number : 10 +I/O Bank : 1 +Pin Name/Usage : LED[4] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : D2 +Pad Number : 9 +I/O Bank : 1 +Pin Name/Usage : ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : N +Bus Hold : no +Weak Pull Up : On + +Location : D3 +Pad Number : 246 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : D4 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCD_PLL3 +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : D5 +Pad Number : 241 +I/O Bank : 8 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : D6 +Pad Number : 234 +I/O Bank : 8 +Pin Name/Usage : PS2_CLK +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : D7 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : D8 +Pad Number : 216 +I/O Bank : 8 +Pin Name/Usage : AUD_ADCDAT +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : D9 +Pad Number : 201 +I/O Bank : 7 +Pin Name/Usage : VGA_G[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : D10 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : D11 +Pad Number : 177 +I/O Bank : 7 +Pin Name/Usage : VGA_B[3] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : D12 +Pad Number : 178 +I/O Bank : 7 +Pin Name/Usage : VGA_HS +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : D13 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCD_PLL2 +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : D14 +Pad Number : 176 +I/O Bank : 7 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : D15 +Pad Number : 170 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : D16 +Pad Number : 169 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : E1 +Pad Number : 26 +I/O Bank : 1 +Pin Name/Usage : KEY[1] +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E2 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E3 +Pad Number : +I/O Bank : 1 +Pin Name/Usage : VCCIO1 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E4 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E5 +Pad Number : +I/O Bank : +Pin Name/Usage : GNDA3 +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E6 +Pad Number : 231 +I/O Bank : 8 +Pin Name/Usage : AUD_BCLK +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E7 +Pad Number : 227 +I/O Bank : 8 +Pin Name/Usage : AUD_ADCLRCK +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E8 +Pad Number : 218 +I/O Bank : 8 +Pin Name/Usage : VGA_R[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E9 +Pad Number : 205 +I/O Bank : 7 +Pin Name/Usage : VGA_R[3] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E10 +Pad Number : 184 +I/O Bank : 7 +Pin Name/Usage : VGA_G[3] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E11 +Pad Number : 183 +I/O Bank : 7 +Pin Name/Usage : VGA_G[2] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : E12 +Pad Number : +I/O Bank : +Pin Name/Usage : GNDA2 +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E13 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E14 +Pad Number : +I/O Bank : 6 +Pin Name/Usage : VCCIO6 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E15 +Pad Number : 151 +I/O Bank : 6 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : E16 +Pad Number : 150 +I/O Bank : 6 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F1 +Pad Number : 14 +I/O Bank : 1 +Pin Name/Usage : I2C_SDAT +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : F2 +Pad Number : 13 +I/O Bank : 1 +Pin Name/Usage : I2C_SCLK +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : F3 +Pad Number : 8 +I/O Bank : 1 +Pin Name/Usage : LED[5] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : F4 +Pad Number : 11 +I/O Bank : 1 +Pin Name/Usage : ^nSTATUS +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F5 +Pad Number : +I/O Bank : -- +Pin Name/Usage : VCCA3 +Dir. : power +I/O Standard : +Voltage : 2.5V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F6 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F7 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F8 +Pad Number : 219 +I/O Bank : 8 +Pin Name/Usage : VGA_R[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : F9 +Pad Number : 197 +I/O Bank : 7 +Pin Name/Usage : VGA_R[2] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : F10 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F11 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F12 +Pad Number : +I/O Bank : -- +Pin Name/Usage : VCCA2 +Dir. : power +I/O Standard : +Voltage : 2.5V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F13 +Pad Number : 161 +I/O Bank : 6 +Pin Name/Usage : GPIO_1[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : F14 +Pad Number : 167 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : F15 +Pad Number : 163 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : F16 +Pad Number : 162 +I/O Bank : 6 +Pin Name/Usage : ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : N +Bus Hold : no +Weak Pull Up : Off + +Location : G1 +Pad Number : 16 +I/O Bank : 1 +Pin Name/Usage : DRAM_DQ[1] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : G2 +Pad Number : 15 +I/O Bank : 1 +Pin Name/Usage : DRAM_DQ[0] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : G3 +Pad Number : +I/O Bank : 1 +Pin Name/Usage : VCCIO1 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G4 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G5 +Pad Number : 12 +I/O Bank : 1 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : G6 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G7 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G8 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G9 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G10 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G11 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G12 +Pad Number : 155 +I/O Bank : 6 +Pin Name/Usage : ^MSEL2 +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G12 +Pad Number : 156 +I/O Bank : 6 +Pin Name/Usage : ^MSEL3 +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G13 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G14 +Pad Number : +I/O Bank : 6 +Pin Name/Usage : VCCIO6 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : G15 +Pad Number : 160 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : G16 +Pad Number : 159 +I/O Bank : 6 +Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : no +Weak Pull Up : On + +Location : H1 +Pad Number : 17 +I/O Bank : 1 +Pin Name/Usage : ~ALTERA_DCLK~ +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : N +Bus Hold : no +Weak Pull Up : On + +Location : H2 +Pad Number : 18 +I/O Bank : 1 +Pin Name/Usage : ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : N +Bus Hold : no +Weak Pull Up : On + +Location : H3 +Pad Number : 21 +I/O Bank : 1 +Pin Name/Usage : #TCK +Dir. : input +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H4 +Pad Number : 20 +I/O Bank : 1 +Pin Name/Usage : #TDI +Dir. : input +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H5 +Pad Number : 19 +I/O Bank : 1 +Pin Name/Usage : ^nCONFIG +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H6 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H7 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H8 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H9 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H10 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H11 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H12 +Pad Number : 154 +I/O Bank : 6 +Pin Name/Usage : ^MSEL1 +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H13 +Pad Number : 153 +I/O Bank : 6 +Pin Name/Usage : ^MSEL0 +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H14 +Pad Number : 152 +I/O Bank : 6 +Pin Name/Usage : ^CONF_DONE +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H15 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : H16 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J1 +Pad Number : 30 +I/O Bank : 2 +Pin Name/Usage : DRAM_DQ[6] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : J2 +Pad Number : 29 +I/O Bank : 2 +Pin Name/Usage : DRAM_DQ[5] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : J3 +Pad Number : 24 +I/O Bank : 1 +Pin Name/Usage : ^nCE +Dir. : +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J4 +Pad Number : 23 +I/O Bank : 1 +Pin Name/Usage : #TDO +Dir. : output +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J5 +Pad Number : 22 +I/O Bank : 1 +Pin Name/Usage : #TMS +Dir. : input +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J6 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J7 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J8 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J9 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J10 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J11 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J12 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : J13 +Pad Number : 146 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[32] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : J14 +Pad Number : 144 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[33] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : J15 +Pad Number : 143 +I/O Bank : 5 +Pin Name/Usage : KEY[0] +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : J16 +Pad Number : 142 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[30] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : K1 +Pad Number : 37 +I/O Bank : 2 +Pin Name/Usage : DRAM_DQ[15] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : K2 +Pad Number : 36 +I/O Bank : 2 +Pin Name/Usage : DRAM_DQ[4] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : K3 +Pad Number : +I/O Bank : 2 +Pin Name/Usage : VCCIO2 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K4 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K5 +Pad Number : 45 +I/O Bank : 2 +Pin Name/Usage : DRAM_DQ[3] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : K6 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K7 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K8 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K9 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K10 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K11 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K12 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K13 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K14 +Pad Number : +I/O Bank : 5 +Pin Name/Usage : VCCIO5 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : K15 +Pad Number : 141 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[31] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : K16 +Pad Number : 140 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[17] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L1 +Pad Number : 39 +I/O Bank : 2 +Pin Name/Usage : DRAM_CAS_N +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L2 +Pad Number : 38 +I/O Bank : 2 +Pin Name/Usage : DRAM_RAS_N +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L3 +Pad Number : 40 +I/O Bank : 2 +Pin Name/Usage : LED[7] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L4 +Pad Number : 46 +I/O Bank : 2 +Pin Name/Usage : DRAM_ADDR[12] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L5 +Pad Number : +I/O Bank : -- +Pin Name/Usage : VCCA1 +Dir. : power +I/O Standard : +Voltage : 2.5V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : L6 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : L7 +Pad Number : 75 +I/O Bank : 3 +Pin Name/Usage : DRAM_CKE +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L8 +Pad Number : 79 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[2] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L9 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : L10 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : L11 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : L12 +Pad Number : +I/O Bank : -- +Pin Name/Usage : VCCA4 +Dir. : power +I/O Standard : +Voltage : 2.5V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : L13 +Pad Number : 136 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[29] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L14 +Pad Number : 134 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[26] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L15 +Pad Number : 138 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[19] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : L16 +Pad Number : 137 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[16] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M1 +Pad Number : 28 +I/O Bank : 2 +Pin Name/Usage : SW[0] +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M2 +Pad Number : 27 +I/O Bank : 2 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M3 +Pad Number : +I/O Bank : 2 +Pin Name/Usage : VCCIO2 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M4 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M5 +Pad Number : +I/O Bank : +Pin Name/Usage : GNDA1 +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M6 +Pad Number : 64 +I/O Bank : 3 +Pin Name/Usage : DRAM_BA[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M7 +Pad Number : 68 +I/O Bank : 3 +Pin Name/Usage : DRAM_BA[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M8 +Pad Number : 81 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[3] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M9 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M10 +Pad Number : 111 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[28] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M11 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCINT +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M12 +Pad Number : +I/O Bank : +Pin Name/Usage : GNDA4 +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M13 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M14 +Pad Number : +I/O Bank : 5 +Pin Name/Usage : VCCIO5 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : M15 +Pad Number : 149 +I/O Bank : 5 +Pin Name/Usage : SW[3] +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : M16 +Pad Number : 148 +I/O Bank : 5 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Row I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : N1 +Pad Number : 44 +I/O Bank : 2 +Pin Name/Usage : DRAM_ADDR[11] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N2 +Pad Number : 43 +I/O Bank : 2 +Pin Name/Usage : DRAM_ADDR[10] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N3 +Pad Number : 52 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[14] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N4 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCD_PLL1 +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : N5 +Pad Number : 62 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N6 +Pad Number : 63 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[2] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N7 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : N8 +Pad Number : 82 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[6] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N9 +Pad Number : 93 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[14] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N10 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : N11 +Pad Number : 112 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[15] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N12 +Pad Number : 117 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[12] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N13 +Pad Number : +I/O Bank : +Pin Name/Usage : VCCD_PLL4 +Dir. : power +I/O Standard : +Voltage : 1.2V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : N14 +Pad Number : 126 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[27] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N15 +Pad Number : 133 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[24] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : N16 +Pad Number : 132 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[23] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P1 +Pad Number : 51 +I/O Bank : 2 +Pin Name/Usage : DRAM_ADDR[9] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P2 +Pad Number : 50 +I/O Bank : 2 +Pin Name/Usage : DRAM_ADDR[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P3 +Pad Number : 53 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[13] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P4 +Pad Number : +I/O Bank : 3 +Pin Name/Usage : VCCIO3 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : P5 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : P6 +Pad Number : 67 +I/O Bank : 3 +Pin Name/Usage : DRAM_CS_N +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P7 +Pad Number : +I/O Bank : 3 +Pin Name/Usage : VCCIO3 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : P8 +Pad Number : 85 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[4] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P9 +Pad Number : 105 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[13] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P10 +Pad Number : +I/O Bank : 4 +Pin Name/Usage : VCCIO4 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : P11 +Pad Number : 106 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[10] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P12 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : P13 +Pad Number : +I/O Bank : 4 +Pin Name/Usage : VCCIO4 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : P14 +Pad Number : 119 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[25] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P15 +Pad Number : 127 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[20] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : P16 +Pad Number : 128 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[21] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R1 +Pad Number : 49 +I/O Bank : 2 +Pin Name/Usage : DRAM_ADDR[8] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R2 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : R3 +Pad Number : 54 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[11] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R4 +Pad Number : 60 +I/O Bank : 3 +Pin Name/Usage : DRAM_CLK +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R5 +Pad Number : 71 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[12] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R6 +Pad Number : 73 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQM[0] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R7 +Pad Number : 76 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[7] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R8 +Pad Number : 86 +I/O Bank : 3 +Pin Name/Usage : CLOCK_50 +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R9 +Pad Number : 88 +I/O Bank : 4 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : R10 +Pad Number : 96 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[11] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R11 +Pad Number : 98 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[9] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R12 +Pad Number : 100 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[6] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R13 +Pad Number : 107 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[4] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R14 +Pad Number : 120 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[22] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : R15 +Pad Number : +I/O Bank : +Pin Name/Usage : GND +Dir. : gnd +I/O Standard : +Voltage : +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : R16 +Pad Number : 129 +I/O Bank : 5 +Pin Name/Usage : GPIO_1[18] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Row I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T1 +Pad Number : +I/O Bank : 3 +Pin Name/Usage : VCCIO3 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : T2 +Pad Number : 59 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[9] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T3 +Pad Number : 55 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[10] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T4 +Pad Number : 61 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQ[8] +Dir. : bidir +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T5 +Pad Number : 72 +I/O Bank : 3 +Pin Name/Usage : DRAM_DQM[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T6 +Pad Number : 74 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[7] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T7 +Pad Number : 77 +I/O Bank : 3 +Pin Name/Usage : DRAM_ADDR[5] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T8 +Pad Number : 87 +I/O Bank : 3 +Pin Name/Usage : SW[1] +Dir. : input +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T9 +Pad Number : 89 +I/O Bank : 4 +Pin Name/Usage : GND+ +Dir. : +I/O Standard : +Voltage : +I/O Type : Column I/O +User Assignment : +Bus Hold : -- +Weak Pull Up : -- + +Location : T10 +Pad Number : 97 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[8] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T11 +Pad Number : 99 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[7] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T12 +Pad Number : 101 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[5] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T13 +Pad Number : 108 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[3] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T14 +Pad Number : 115 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[2] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T15 +Pad Number : 116 +I/O Bank : 4 +Pin Name/Usage : GPIO_1[1] +Dir. : output +I/O Standard : 3.3-V LVTTL +Voltage : +I/O Type : Column I/O +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off + +Location : T16 +Pad Number : +I/O Bank : 4 +Pin Name/Usage : VCCIO4 +Dir. : power +I/O Standard : +Voltage : 3.3V +I/O Type : -- +User Assignment : +Bus Hold : -- +Weak Pull Up : -- ++--------------------------------------------------------------------------------+ + +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++--------------------------------------------------------------------------------+ +; PLL Summary ; ++--------------------------------------------------------------------------------+ +Name : SDC pin name +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : ula_|pll_|altpll_component|auto_generated|pll1 + +Name : PLL mode +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Normal +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Normal + +Name : Compensate clock +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : clock0 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : clock0 + +Name : Compensated input/output pins +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Switchover type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Input frequency 0 +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 50.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 50.0 MHz + +Name : Input frequency 1 +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Nominal PFD frequency +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 50.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 7.1 MHz + +Name : Nominal VCO frequency +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 500.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 1007.1 MHz + +Name : VCO post scale K counter +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 2 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : VCO frequency control +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Auto +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Auto + +Name : VCO phase shift step +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 250 ps +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 124 ps + +Name : VCO multiply +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : VCO divide +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Freq min lock +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 30.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 37.8 MHz + +Name : Freq max lock +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 65.02 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 64.56 MHz + +Name : M VCO Tap +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 0 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 0 + +Name : M Initial +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 1 + +Name : M value +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 10 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 141 + +Name : N value +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 7 + +Name : Charge pump current +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : setting 1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : setting 1 + +Name : Loop filter resistance +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : setting 27 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : setting 16 + +Name : Loop filter capacitance +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : setting 0 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : setting 0 + +Name : Bandwidth +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 1.03 MHz to 1.97 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 340 kHz to 540 kHz + +Name : Bandwidth type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Medium +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Medium + +Name : Real time reconfigurable +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Off +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Off + +Name : Scan chain MIF file +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Preserve PLL counter order +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Off +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Off + +Name : PLL location +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : PLL_1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : PLL_4 + +Name : Inclk0 signal +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : CLOCK_50 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : CLOCK_50 + +Name : Inclk1 signal +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Inclk0 signal type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Dedicated Pin +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Dedicated Pin + +Name : Inclk1 signal type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; PLL Usage ; ++--------------------------------------------------------------------------------+ +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] +Output Clock : clock0 +Mult : 2 +Div : 1 +Output Frequency : 100.0 MHz +Phase Shift : 0 (0 ps) +Phase Shift Step : 9.00 (250 ps) +Duty Cycle : 50/50 +Counter : C1 +Counter Value : 5 +High / Low : 3/2 Odd +Cascade Input : -- +Initial : 1 +VCO Tap : 0 +SDC Pin Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] +Output Clock : clock1 +Mult : 2 +Div : 1 +Output Frequency : 100.0 MHz +Phase Shift : 108 (3000 ps) +Phase Shift Step : 9.00 (250 ps) +Duty Cycle : 50/50 +Counter : C0 +Counter Value : 5 +High / Low : 3/2 Odd +Cascade Input : -- +Initial : 2 +VCO Tap : 4 +SDC Pin Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] +Output Clock : clock0 +Mult : 141 +Div : 280 +Output Frequency : 25.18 MHz +Phase Shift : 0 (0 ps) +Phase Shift Step : 1.12 (124 ps) +Duty Cycle : 50/50 +Counter : C0 +Counter Value : 40 +High / Low : 20/20 Even +Cascade Input : -- +Initial : 1 +VCO Tap : 0 +SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] +Output Clock : clock1 +Mult : 47 +Div : 168 +Output Frequency : 13.99 MHz +Phase Shift : 0 (0 ps) +Phase Shift Step : 0.62 (124 ps) +Duty Cycle : 50/50 +Counter : C2 +Counter Value : 72 +High / Low : 36/36 Even +Cascade Input : -- +Initial : 1 +VCO Tap : 0 +SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] +Output Clock : clock2 +Mult : 47 +Div : 98 +Output Frequency : 23.98 MHz +Phase Shift : 0 (0 ps) +Phase Shift Step : 1.07 (124 ps) +Duty Cycle : 50/50 +Counter : C1 +Counter Value : 42 +High / Low : 21/21 Even +Cascade Input : -- +Initial : 1 +VCO Tap : 0 +SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++--------------------------------------------------------------------------------+ +Compilation Hierarchy Node : |spectrum +Logic Cells : 2621 (97) +Dedicated Logic Registers : 635 (0) +I/O Registers : 29 (29) +Memory Bits : 524288 +M9Ks : 64 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 114 +Virtual Pins : 0 +LUT-Only LCs : 1986 (96) +Register-Only LCs : 134 (0) +LUT/Register LCs : 501 (1) +Full Hierarchy Name : |spectrum +Library Name : work + +Compilation Hierarchy Node : |ram16:ram0| +Logic Cells : 4 (0) +Dedicated Logic Registers : 2 (0) +I/O Registers : 0 (0) +Memory Bits : 131072 +M9Ks : 16 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 1 (0) +Full Hierarchy Name : |spectrum|ram16:ram0 +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +Logic Cells : 4 (0) +Dedicated Logic Registers : 2 (0) +I/O Registers : 0 (0) +Memory Bits : 131072 +M9Ks : 16 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 1 (0) +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_7ti2:auto_generated| +Logic Cells : 4 (2) +Dedicated Logic Registers : 2 (2) +I/O Registers : 0 (0) +Memory Bits : 131072 +M9Ks : 16 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 1 (1) +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated +Library Name : work + +Compilation Hierarchy Node : |decode_jsa:decode2| +Logic Cells : 2 (2) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (2) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2 +Library Name : work + +Compilation Hierarchy Node : |ram32:ram1| +Logic Cells : 18 (0) +Dedicated Logic Registers : 4 (0) +I/O Registers : 0 (0) +Memory Bits : 262144 +M9Ks : 32 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 14 (0) +Register-Only LCs : 2 (0) +LUT/Register LCs : 2 (0) +Full Hierarchy Name : |spectrum|ram32:ram1 +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +Logic Cells : 18 (0) +Dedicated Logic Registers : 4 (0) +I/O Registers : 0 (0) +Memory Bits : 262144 +M9Ks : 32 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 14 (0) +Register-Only LCs : 2 (0) +LUT/Register LCs : 2 (0) +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| +Logic Cells : 18 (4) +Dedicated Logic Registers : 4 (4) +I/O Registers : 0 (0) +Memory Bits : 262144 +M9Ks : 32 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 14 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 2 (0) +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated +Library Name : work + +Compilation Hierarchy Node : |decode_f8a:rden_decode| +Logic Cells : 1 (1) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode +Library Name : work + +Compilation Hierarchy Node : |decode_msa:decode3| +Logic Cells : 7 (7) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3 +Library Name : work + +Compilation Hierarchy Node : |mux_6nb:mux2| +Logic Cells : 8 (8) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 6 (6) +Register-Only LCs : 0 (0) +LUT/Register LCs : 2 (2) +Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 +Library Name : work + +Compilation Hierarchy Node : |rom0:rom| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 131072 +M9Ks : 16 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 131072 +M9Ks : 16 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 131072 +M9Ks : 16 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated +Library Name : work + +Compilation Hierarchy Node : |sdram_controller:sdram_| +Logic Cells : 230 (230) +Dedicated Logic Registers : 44 (44) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 185 (185) +Register-Only LCs : 9 (9) +LUT/Register LCs : 36 (36) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_ +Library Name : work + +Compilation Hierarchy Node : |sdram_clk_gen:sdram_clk_pll| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll +Library Name : work + +Compilation Hierarchy Node : |altpll:altpll_component| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component +Library Name : work + +Compilation Hierarchy Node : |sdram_clk_gen_altpll:auto_generated| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated +Library Name : work + +Compilation Hierarchy Node : |ula:ula_| +Logic Cells : 459 (9) +Dedicated Logic Registers : 223 (7) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 236 (2) +Register-Only LCs : 36 (2) +LUT/Register LCs : 187 (5) +Full Hierarchy Name : |spectrum|ula:ula_ +Library Name : work + +Compilation Hierarchy Node : |clocks:clocks_| +Logic Cells : 2 (2) +Dedicated Logic Registers : 2 (2) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 2 (2) +Full Hierarchy Name : |spectrum|ula:ula_|clocks:clocks_ +Library Name : work + +Compilation Hierarchy Node : |i2c_loader:i2c_loader_| +Logic Cells : 82 (82) +Dedicated Logic Registers : 34 (34) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 48 (48) +Register-Only LCs : 0 (0) +LUT/Register LCs : 34 (34) +Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_ +Library Name : work + +Compilation Hierarchy Node : |i2s_intf:i2s_intf_| +Logic Cells : 70 (70) +Dedicated Logic Registers : 41 (41) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 29 (29) +Register-Only LCs : 2 (2) +LUT/Register LCs : 39 (39) +Full Hierarchy Name : |spectrum|ula:ula_|i2s_intf:i2s_intf_ +Library Name : work + +Compilation Hierarchy Node : |pll:pll_| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_ +Library Name : work + +Compilation Hierarchy Node : |altpll:altpll_component| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_|altpll:altpll_component +Library Name : work + +Compilation Hierarchy Node : |pll_altpll:auto_generated| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated +Library Name : work + +Compilation Hierarchy Node : |ps2_keyboard:ps2_keyboard_| +Logic Cells : 29 (29) +Dedicated Logic Registers : 24 (24) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 5 (5) +Register-Only LCs : 5 (5) +LUT/Register LCs : 19 (19) +Full Hierarchy Name : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_ +Library Name : work + +Compilation Hierarchy Node : |video:video_| +Logic Cells : 126 (126) +Dedicated Logic Registers : 72 (72) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 54 (54) +Register-Only LCs : 27 (27) +LUT/Register LCs : 45 (45) +Full Hierarchy Name : |spectrum|ula:ula_|video:video_ +Library Name : work + +Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| +Logic Cells : 149 (149) +Dedicated Logic Registers : 43 (43) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 98 (98) +Register-Only LCs : 0 (0) +LUT/Register LCs : 51 (51) +Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ +Library Name : work + +Compilation Hierarchy Node : |z80_top_direct_n:z80_| +Logic Cells : 1817 (2) +Dedicated Logic Registers : 362 (1) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1453 (1) +Register-Only LCs : 86 (0) +LUT/Register LCs : 278 (2) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ +Library Name : work + +Compilation Hierarchy Node : |address_latch:address_latch_| +Logic Cells : 54 (24) +Dedicated Logic Registers : 16 (16) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 38 (8) +Register-Only LCs : 7 (7) +LUT/Register LCs : 9 (9) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_ +Library Name : work + +Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| +Logic Cells : 30 (13) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 30 (13) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec +Library Name : work + +Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0 +Library Name : work + +Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_10| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10 +Library Name : work + +Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_2| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2 +Library Name : work + +Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_4| +Logic Cells : 2 (2) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (2) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4 +Library Name : work + +Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_7| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7 +Library Name : work + +Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_9| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9 +Library Name : work + +Compilation Hierarchy Node : |address_pins:address_pins_| +Logic Cells : 32 (32) +Dedicated Logic Registers : 16 (16) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 16 (16) +Register-Only LCs : 0 (0) +LUT/Register LCs : 16 (16) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_ +Library Name : work + +Compilation Hierarchy Node : |alu:alu_| +Logic Cells : 132 (92) +Dedicated Logic Registers : 20 (20) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 111 (71) +Register-Only LCs : 0 (0) +LUT/Register LCs : 21 (5) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_ +Library Name : work + +Compilation Hierarchy Node : |alu_bit_select:b2v_input_bit_select| +Logic Cells : 2 (2) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (2) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select +Library Name : work + +Compilation Hierarchy Node : |alu_core:b2v_core| +Logic Cells : 23 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 23 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core +Library Name : work + +Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_0| +Logic Cells : 7 (7) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0 +Library Name : work + +Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| +Logic Cells : 4 (4) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 4 (4) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1 +Library Name : work + +Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_2| +Logic Cells : 7 (7) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2 +Library Name : work + +Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| +Logic Cells : 5 (5) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 5 (5) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3 +Library Name : work + +Compilation Hierarchy Node : |alu_mux_2z:b2v_op1_latch_mux_high| +Logic Cells : 5 (5) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high +Library Name : work + +Compilation Hierarchy Node : |alu_mux_3z:b2v_op1_latch_mux_low| +Logic Cells : 9 (9) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 5 (5) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low +Library Name : work + +Compilation Hierarchy Node : |alu_mux_3z:b2v_op2_latch_mux_high| +Logic Cells : 9 (9) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 5 (5) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high +Library Name : work + +Compilation Hierarchy Node : |alu_mux_3z:b2v_op2_latch_mux_low| +Logic Cells : 8 (8) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 4 (4) +Register-Only LCs : 0 (0) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_low +Library Name : work + +Compilation Hierarchy Node : |alu_control:alu_control_| +Logic Cells : 42 (37) +Dedicated Logic Registers : 2 (2) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 40 (35) +Register-Only LCs : 0 (0) +LUT/Register LCs : 2 (2) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_ +Library Name : work + +Compilation Hierarchy Node : |alu_mux_4:b2v_inst_cond_mux| +Logic Cells : 2 (2) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (2) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_4:b2v_inst_cond_mux +Library Name : work + +Compilation Hierarchy Node : |alu_mux_8:b2v_inst_shift_mux| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux +Library Name : work + +Compilation Hierarchy Node : |alu_flags:alu_flags_| +Logic Cells : 59 (59) +Dedicated Logic Registers : 10 (10) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 49 (49) +Register-Only LCs : 0 (0) +LUT/Register LCs : 10 (10) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_ +Library Name : work + +Compilation Hierarchy Node : |bus_control:bus_control_| +Logic Cells : 18 (18) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 12 (12) +Register-Only LCs : 0 (0) +LUT/Register LCs : 6 (6) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|bus_control:bus_control_ +Library Name : work + +Compilation Hierarchy Node : |clk_delay:clk_delay_| +Logic Cells : 3 (3) +Dedicated Logic Registers : 2 (2) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 1 (1) +LUT/Register LCs : 1 (1) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ +Library Name : work + +Compilation Hierarchy Node : |data_pins:data_pins_| +Logic Cells : 9 (9) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_ +Library Name : work + +Compilation Hierarchy Node : |data_switch:sw2_| +Logic Cells : 1 (1) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ +Library Name : work + +Compilation Hierarchy Node : |data_switch_mask:sw1_| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 2 (2) +Register-Only LCs : 0 (0) +LUT/Register LCs : 1 (1) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_ +Library Name : work + +Compilation Hierarchy Node : |decode_state:decode_state_| +Logic Cells : 14 (14) +Dedicated Logic Registers : 6 (6) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 8 (8) +Register-Only LCs : 0 (0) +LUT/Register LCs : 6 (6) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode_state_ +Library Name : work + +Compilation Hierarchy Node : |execute:execute_| +Logic Cells : 930 (930) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 923 (923) +Register-Only LCs : 0 (0) +LUT/Register LCs : 7 (7) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_ +Library Name : work + +Compilation Hierarchy Node : |interrupts:interrupts_| +Logic Cells : 15 (15) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 7 (7) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|interrupts:interrupts_ +Library Name : work + +Compilation Hierarchy Node : |ir:ir_| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|ir:ir_ +Library Name : work + +Compilation Hierarchy Node : |memory_ifc:memory_ifc_| +Logic Cells : 21 (21) +Dedicated Logic Registers : 20 (20) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 6 (6) +LUT/Register LCs : 14 (14) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_ +Library Name : work + +Compilation Hierarchy Node : |pin_control:pin_control_| +Logic Cells : 19 (19) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 19 (19) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_control_ +Library Name : work + +Compilation Hierarchy Node : |pla_decode:pla_decode_| +Logic Cells : 73 (73) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 73 (73) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_decode_ +Library Name : work + +Compilation Hierarchy Node : |reg_control:reg_control_| +Logic Cells : 29 (29) +Dedicated Logic Registers : 4 (4) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 24 (24) +Register-Only LCs : 0 (0) +LUT/Register LCs : 5 (5) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_control_ +Library Name : work + +Compilation Hierarchy Node : |reg_file:reg_file_| +Logic Cells : 349 (125) +Dedicated Logic Registers : 224 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 125 (125) +Register-Only LCs : 65 (0) +LUT/Register LCs : 159 (147) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_ +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_af2_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_af2_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_af_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 8 (8) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_bc2_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_bc2_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_bc_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_bc_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de2_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de2_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_de_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_de_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl2_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl2_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_ir_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_ir_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_ix_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_ix_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_iy_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_iy_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_pc_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_pc_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_pc_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_pc_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_sp_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_sp_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_lo +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_hi| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 5 (5) +LUT/Register LCs : 3 (3) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi +Library Name : work + +Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo| +Logic Cells : 8 (8) +Dedicated Logic Registers : 8 (8) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_lo +Library Name : work + +Compilation Hierarchy Node : |resets:resets_| +Logic Cells : 7 (7) +Dedicated Logic Registers : 6 (6) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 1 (1) +LUT/Register LCs : 5 (5) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|resets:resets_ +Library Name : work + +Compilation Hierarchy Node : |sequencer:sequencer_| +Logic Cells : 11 (11) +Dedicated Logic Registers : 11 (11) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 11 (11) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|sequencer:sequencer_ +Library Name : work ++--------------------------------------------------------------------------------+ + +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------------------------------------------------------------------------------+ +Name : LED[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[4] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[5] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[6] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : LED[7] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : AUD_XCK +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : AUD_ADCLRCK +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : AUD_DACLRCK +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : AUD_BCLK +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : AUD_DACDAT +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : VGA_R[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_R[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_R[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_R[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_G[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_G[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_G[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_G[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_B[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_B[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_B[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_B[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : VGA_HS +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : VGA_VS +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : SW[0] +Pin Type : Input +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : SW[3] +Pin Type : Input +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[4] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[5] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[6] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[7] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[8] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[9] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[10] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[11] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[12] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[13] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[14] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[15] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[16] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[17] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[18] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[19] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[20] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[21] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[22] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[23] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[24] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[25] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[26] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[27] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[28] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[29] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[30] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[31] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[32] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : GPIO_1[33] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : buzzer_out +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_BA[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_BA[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_DQM[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_DQM[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_RAS_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_CAS_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_CKE +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_CLK +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_WE_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_CS_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_ADDR[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[4] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[5] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[6] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[7] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[8] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[9] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[10] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[11] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[12] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : I2C_SCLK +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : I2C_SDAT +Pin Type : Bidir +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_DQ[0] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[1] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[2] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[3] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[4] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[5] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[6] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[7] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[8] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[9] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[10] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[11] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[12] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[13] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[14] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[15] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : SW[1] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : SW[2] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : raw_loader_in +Pin Type : Input +Pad to Core 0 : (6) 1314 ps +Pad to Core 1 : (0) 0 ps +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : KEY[0] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : CLOCK_50 +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : PS2_DAT +Pin Type : Input +Pad to Core 0 : (6) 1314 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : KEY[1] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : PS2_CLK +Pin Type : Input +Pad to Core 0 : (6) 1314 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : AUD_ADCDAT +Pin Type : Input +Pad to Core 0 : -- +Pad to Core 1 : (0) 0 ps +Pad to Input Register : -- +TCO : -- +TCOE : -- ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------------------------------------------+ +Source Pin / Fanout : SW[0] +Pad To Core Index : +Setting : + +Source Pin / Fanout : SW[3] +Pad To Core Index : +Setting : + +Source Pin / Fanout : I2C_SCLK +Pad To Core Index : +Setting : + +Source Pin / Fanout : I2C_SDAT +Pad To Core Index : +Setting : + +Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|sda_out~1 +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~1 +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~5 +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : DRAM_DQ[0] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[1] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[2] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[3] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[4] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[5] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[6] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[7] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[8] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[9] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[10] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[11] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[12] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[13] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[14] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[15] +Pad To Core Index : +Setting : + +Source Pin / Fanout : SW[1] +Pad To Core Index : +Setting : + +Source Pin / Fanout : SW[2] +Pad To Core Index : +Setting : + +Source Pin / Fanout : raw_loader_in +Pad To Core Index : +Setting : + +Source Pin / Fanout : - D[6]~84 +Pad To Core Index : 1 +Setting : 0 + +Source Pin / Fanout : - ula:ula_|beep~0 +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : - LED[3]~output +Pad To Core Index : 1 +Setting : 0 + +Source Pin / Fanout : KEY[0] +Pad To Core Index : +Setting : + +Source Pin / Fanout : - reset +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : CLOCK_50 +Pad To Core Index : +Setting : + +Source Pin / Fanout : PS2_DAT +Pad To Core Index : +Setting : + +Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|always1~0 +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready~0 +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : KEY[1] +Pad To Core Index : +Setting : + +Source Pin / Fanout : PS2_CLK +Pad To Core Index : +Setting : + +Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7] +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : AUD_ADCDAT +Pad To Core Index : +Setting : + +Source Pin / Fanout : - ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]~20 +Pad To Core Index : 1 +Setting : 0 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------------------------------------------------------------+ +Name : CLOCK_50 +Location : PIN_R8 +Fan-Out : 34 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK15 +Enable Signal Source Name : -- + +Name : CLOCK_50 +Location : PIN_R8 +Fan-Out : 3 +Usage : Clock +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : D[0]~105 +Location : LCCOMB_X27_Y25_N30 +Fan-Out : 12 +Usage : Output enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : KEY[1] +Location : PIN_E1 +Fan-Out : 1 +Usage : Clock +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 +Location : LCCOMB_X25_Y19_N22 +Fan-Out : 8 +Usage : Write enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 +Location : LCCOMB_X25_Y19_N0 +Fan-Out : 8 +Usage : Write enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 +Location : LCCOMB_X25_Y19_N24 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] +Location : LCCOMB_X25_Y19_N2 +Fan-Out : 8 +Usage : Write enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 +Location : LCCOMB_X25_Y19_N20 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] +Location : LCCOMB_X25_Y19_N10 +Fan-Out : 8 +Usage : Write enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] +Location : LCCOMB_X25_Y19_N12 +Fan-Out : 8 +Usage : Write enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 +Location : LCCOMB_X25_Y19_N14 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] +Location : LCCOMB_X25_Y19_N26 +Fan-Out : 8 +Usage : Write enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 +Location : LCCOMB_X25_Y19_N16 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : reset +Location : LCCOMB_X52_Y14_N4 +Fan-Out : 149 +Usage : Async. clear, Async. load +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK5 +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|Mux13~3 +Location : LCCOMB_X23_Y17_N2 +Fan-Out : 7 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|Mux19~0 +Location : LCCOMB_X21_Y18_N28 +Fan-Out : 6 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|Mux84~1 +Location : LCCOMB_X24_Y18_N12 +Fan-Out : 16 +Usage : Output enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.act_row[0]~1 +Location : LCCOMB_X24_Y19_N10 +Fan-Out : 5 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.address[3]~19 +Location : LCCOMB_X23_Y19_N10 +Fan-Out : 6 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.bank[0]~6 +Location : LCCOMB_X21_Y20_N30 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.rf_counter[1]~32 +Location : LCCOMB_X19_Y19_N30 +Fan-Out : 10 +Usage : Sync. clear +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.state[7] +Location : FF_X24_Y18_N31 +Fan-Out : 47 +Usage : Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] +Location : PLL_1 +Fan-Out : 64 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK4 +Enable Signal Source Name : -- + +Name : ula:ula_|always0~3 +Location : LCCOMB_X27_Y25_N12 +Fan-Out : 7 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|clocks:clocks_|clk_cpu +Location : FF_X25_Y33_N11 +Fan-Out : 435 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK12 +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|WideAnd0 +Location : LCCOMB_X1_Y24_N30 +Fan-Out : 17 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~3 +Location : LCCOMB_X3_Y24_N10 +Fan-Out : 3 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 +Location : LCCOMB_X1_Y23_N20 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Location : FF_X1_Y23_N31 +Fan-Out : 22 +Usage : Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 +Location : LCCOMB_X3_Y23_N10 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~12 +Location : LCCOMB_X3_Y23_N18 +Fan-Out : 6 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|state.Start +Location : FF_X3_Y24_N21 +Fan-Out : 20 +Usage : Sync. clear, Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 +Location : LCCOMB_X2_Y23_N0 +Fan-Out : 5 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2s_intf:i2s_intf_|Equal0~2 +Location : LCCOMB_X17_Y31_N10 +Fan-Out : 37 +Usage : Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 +Location : LCCOMB_X15_Y32_N30 +Fan-Out : 5 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~2 +Location : LCCOMB_X16_Y32_N16 +Fan-Out : 17 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] +Location : PLL_4 +Fan-Out : 110 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK18 +Enable Signal Source Name : -- + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] +Location : PLL_4 +Fan-Out : 2 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK17 +Enable Signal Source Name : -- + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] +Location : PLL_4 +Fan-Out : 82 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK19 +Enable Signal Source Name : -- + +Name : ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge +Location : FF_X23_Y15_N5 +Fan-Out : 6 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready +Location : FF_X27_Y15_N13 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 +Location : LCCOMB_X27_Y15_N16 +Fan-Out : 9 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|video:video_|Decoder0~0 +Location : LCCOMB_X36_Y32_N4 +Fan-Out : 16 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|video:video_|Decoder0~1 +Location : LCCOMB_X36_Y32_N30 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|video:video_|Decoder0~2 +Location : LCCOMB_X35_Y32_N6 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|video:video_|Equal3~1 +Location : LCCOMB_X37_Y32_N20 +Fan-Out : 16 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|video:video_|vram_address[8]~1 +Location : LCCOMB_X35_Y32_N2 +Fan-Out : 4 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ula:ula_|video:video_|vram_address~0 +Location : LCCOMB_X35_Y32_N22 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 +Location : LCCOMB_X25_Y19_N28 +Fan-Out : 48 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 +Location : LCCOMB_X38_Y23_N12 +Fan-Out : 4 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena +Location : LCCOMB_X38_Y23_N0 +Fan-Out : 4 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena +Location : LCCOMB_X37_Y22_N22 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq +Location : LCCOMB_X31_Y20_N28 +Fan-Out : 24 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 +Location : LCCOMB_X32_Y22_N28 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 +Location : LCCOMB_X31_Y17_N16 +Fan-Out : 16 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low +Location : LCCOMB_X39_Y17_N12 +Fan-Out : 15 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 +Location : LCCOMB_X39_Y17_N30 +Fan-Out : 16 +Usage : Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 +Location : LCCOMB_X38_Y20_N14 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 +Location : LCCOMB_X38_Y20_N10 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_im_we +Location : LCCOMB_X32_Y21_N30 +Fan-Out : 3 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 +Location : LCCOMB_X32_Y21_N20 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 +Location : LCCOMB_X35_Y17_N14 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 +Location : LCCOMB_X40_Y20_N28 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|fpga_reset +Location : FF_X25_Y33_N1 +Fan-Out : 2 +Usage : Async. clear +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK14 +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 +Location : LCCOMB_X31_Y18_N20 +Fan-Out : 2 +Usage : Async. clear +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK13 +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_15 +Location : LCCOMB_X34_Y22_N24 +Fan-Out : 1 +Usage : Async. clear +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_9 +Location : LCCOMB_X31_Y18_N12 +Fan-Out : 1 +Usage : Async. clear +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 +Location : LCCOMB_X35_Y20_N6 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~1 +Location : LCCOMB_X31_Y19_N22 +Fan-Out : 16 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 +Location : LCCOMB_X32_Y23_N30 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 +Location : LCCOMB_X30_Y23_N28 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 +Location : LCCOMB_X31_Y25_N8 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 +Location : LCCOMB_X31_Y25_N28 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 +Location : LCCOMB_X31_Y23_N10 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 +Location : LCCOMB_X31_Y22_N4 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 +Location : LCCOMB_X31_Y23_N0 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 +Location : LCCOMB_X31_Y22_N2 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 +Location : LCCOMB_X30_Y25_N28 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 +Location : LCCOMB_X29_Y23_N2 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 +Location : LCCOMB_X30_Y25_N8 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 +Location : LCCOMB_X29_Y23_N0 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 +Location : LCCOMB_X29_Y23_N22 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 +Location : LCCOMB_X30_Y23_N2 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 +Location : LCCOMB_X29_Y25_N8 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 +Location : LCCOMB_X29_Y23_N4 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 +Location : LCCOMB_X30_Y20_N18 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 +Location : LCCOMB_X30_Y19_N22 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 +Location : LCCOMB_X31_Y23_N16 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 +Location : LCCOMB_X31_Y22_N8 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 +Location : LCCOMB_X31_Y25_N6 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 +Location : LCCOMB_X31_Y25_N22 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 +Location : LCCOMB_X29_Y20_N14 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 +Location : LCCOMB_X29_Y22_N4 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 +Location : LCCOMB_X31_Y23_N30 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 +Location : LCCOMB_X31_Y22_N30 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 +Location : LCCOMB_X29_Y20_N6 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 +Location : LCCOMB_X29_Y22_N18 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Location : FF_X27_Y25_N9 +Fan-Out : 77 +Usage : Output enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Location : FF_X27_Y25_N9 +Fan-Out : 72 +Usage : Async. clear +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK8 +Enable Signal Source Name : -- ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++--------------------------------------------------------------------------------+ +Name : CLOCK_50 +Location : PIN_R8 +Fan-Out : 34 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK15 +Enable Signal Source Name : -- + +Name : reset +Location : LCCOMB_X52_Y14_N4 +Fan-Out : 149 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK5 +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] +Location : PLL_1 +Fan-Out : 64 +Fan-Out Using Intentional Clock Skew : 5 +Global Resource Used : Global Clock +Global Line Name : GCLK4 +Enable Signal Source Name : -- + +Name : ula:ula_|clocks:clocks_|clk_cpu +Location : FF_X25_Y33_N11 +Fan-Out : 435 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK12 +Enable Signal Source Name : -- + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] +Location : PLL_4 +Fan-Out : 110 +Fan-Out Using Intentional Clock Skew : 19 +Global Resource Used : Global Clock +Global Line Name : GCLK18 +Enable Signal Source Name : -- + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] +Location : PLL_4 +Fan-Out : 2 +Fan-Out Using Intentional Clock Skew : 2 +Global Resource Used : Global Clock +Global Line Name : GCLK17 +Enable Signal Source Name : -- + +Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] +Location : PLL_4 +Fan-Out : 82 +Fan-Out Using Intentional Clock Skew : 44 +Global Resource Used : Global Clock +Global Line Name : GCLK19 +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|fpga_reset +Location : FF_X25_Y33_N1 +Fan-Out : 2 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK14 +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 +Location : LCCOMB_X31_Y18_N20 +Fan-Out : 2 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK13 +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Location : FF_X27_Y25_N9 +Fan-Out : 72 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK8 +Enable Signal Source Name : -- ++--------------------------------------------------------------------------------+ + + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-------------------------------------------------------------------------------------------------------------------------------+---------+ +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 76 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~21 ; 72 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 71 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~17 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~24 ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~16 ; 68 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 67 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[4]~28 ; 66 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~27 ; 66 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~26 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~25 ; 65 ; +; sdram_controller:sdram_|r.state[4] ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]~31 ; 64 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]~30 ; 64 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]~29 ; 64 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 63 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 61 ; +; sdram_controller:sdram_|r.state[8] ; 57 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 57 ; +; sdram_controller:sdram_|r.state[6] ; 56 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 55 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 54 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 53 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 52 ; +; z80_top_direct_n:z80_|nM1_int~2 ; 50 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 ; 48 ; +; sdram_controller:sdram_|r.state[7] ; 47 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 45 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 44 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~6 ; 43 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 43 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~2 ; 39 ; +; ula:ula_|zx_keyboard:zx_keyboard_|released ; 38 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 38 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 37 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 37 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 37 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 37 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 37 ; +; ula:ula_|i2s_intf:i2s_intf_|Equal0~2 ; 37 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 36 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 35 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 35 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 34 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 34 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 33 ; +; sdram_controller:sdram_|r.state[5] ; 33 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 33 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~18 ; 33 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 32 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 32 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 31 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 31 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 30 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~34 ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 27 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 27 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~2 ; 27 ; +; sdram_controller:sdram_|r.wr_pending ; 25 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~15 ; 25 ; +; ~GND ; 24 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~44 ; 24 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 24 ; +; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq ; 24 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 24 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 23 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 23 ; +; Equal2~1 ; 23 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 23 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Data ; 23 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 22 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~11 ; 22 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 22 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~14 ; 22 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~1 ; 22 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 22 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~23 ; 22 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~33 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~29 ; 21 ; +; sdram_controller:sdram_|r.rd_pending ; 21 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~3 ; 21 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Start ; 20 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~36 ; 19 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~42 ; 19 ; +; sdram_controller:sdram_|Equal7~2 ; 19 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 19 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 19 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~6 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_we~8 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 18 ; +; ula:ula_|i2c_loader:i2c_loader_|WideAnd0 ; 17 ; +; ula:ula_|video:video_|vram_address[10] ; 17 ; +; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 17 ; +; sdram_controller:sdram_|r.rf_pending ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 17 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~22 ; 17 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~2 ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~16 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 ; 16 ; +; sdram_controller:sdram_|Mux84~1 ; 16 ; +; ula:ula_|video:video_|vram_address[12] ; 16 ; +; ula:ula_|video:video_|vram_address[11] ; 16 ; +; ula:ula_|video:video_|vram_address[9] ; 16 ; +; ula:ula_|video:video_|vram_address[8] ; 16 ; +; ula:ula_|video:video_|vram_address[7] ; 16 ; +; ula:ula_|video:video_|vram_address[6] ; 16 ; +; ula:ula_|video:video_|vram_address[5] ; 16 ; +; ula:ula_|video:video_|vram_address[4] ; 16 ; +; ula:ula_|video:video_|vram_address[3] ; 16 ; +; ula:ula_|video:video_|vram_address[2] ; 16 ; +; ula:ula_|video:video_|vram_address[1] ; 16 ; +; ula:ula_|video:video_|vram_address[0] ; 16 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~1 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; +; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~52 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~5 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~3 ; 16 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 16 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 16 ; +; ula:ula_|video:video_|Decoder0~0 ; 16 ; +; ula:ula_|video:video_|Equal3~1 ; 16 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_exx ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~2 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 15 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 15 ; +; ula:ula_|video:video_|Equal1~0 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~15 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~90 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~80 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]~71 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]~62 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]~52 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]~42 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[1]~32 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~84 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~75 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~66 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~57 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~48 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~39 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~30 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~21 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~22 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~9 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~7 ; 14 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~3 ; 14 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|in_halt ; 14 ; +; ula:ula_|video:video_|vga_hc[2] ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~7 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~8 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~0 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 13 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 13 ; +; ula:ula_|video:video_|vga_hc[1] ; 13 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 13 ; +; D[0]~105 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~14 ; 12 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 12 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 12 ; +; Equal2~0 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~2 ; 12 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~15 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~15 ; 11 ; +; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~4 ; 11 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] ; 11 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] ; 11 ; +; sdram_controller:sdram_|r.rf_counter[1]~32 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~2 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~6 ; 10 ; +; sdram_controller:sdram_|process_0~2 ; 10 ; +; D[3]~94 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 10 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 10 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 10 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_48 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_34 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_30 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_50 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_46 ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Idle ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Ack ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_zero ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~8 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_lq ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~12 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~5 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 9 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 9 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_80 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_76~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~12 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_64~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_40~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_36~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~8 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_38~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~2 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~7 ; 9 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_oe~1 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_oe~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~15 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 9 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~2 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_72 ; 9 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sw_4d_hi~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_60 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; +; D[4]~96 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~10 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 9 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; +; ula:ula_|video:video_|vga_hc[3] ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~9 ; 8 ; +; ula:ula_|video:video_|vram_address~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~20 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~21 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 8 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus ; 8 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 ; 8 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~5 ; 8 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~6 ; 8 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~4 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] ; 8 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~17 ; 8 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~17 ; 8 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 8 ; +; ula:ula_|video:video_|Decoder0~2 ; 8 ; +; ula:ula_|video:video_|Decoder0~1 ; 8 ; +; sdram_controller:sdram_|r.init_counter[0] ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal48~0 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~1 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal37~0 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~21 ; 8 ; +; D[0]~51 ; 8 ; +; D[2]~39 ; 8 ; +; D[1]~32 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~0 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 8 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 8 ; +; ula:ula_|video:video_|vga_hc[0] ; 8 ; +; ula:ula_|video:video_|vga_hc[6] ; 8 ; +; ula:ula_|video:video_|vga_vc[5] ; 8 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 7 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_44 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal38~2 ; 7 ; +; ula:ula_|always0~3 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 7 ; +; ula:ula_|i2c_loader:i2c_loader_|nbyte[0] ; 7 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~13 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~9 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~25 ; 7 ; +; D[7]~100 ; 7 ; +; D[6]~99 ; 7 ; +; D[5]~97 ; 7 ; +; ExtRamWE~0 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~33 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~29 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~18 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~24 ; 7 ; +; sdram_controller:sdram_|r.address[3]~11 ; 7 ; +; sdram_controller:sdram_|Mux13~3 ; 7 ; +; sdram_controller:sdram_|r.init_counter[1] ; 7 ; +; sdram_controller:sdram_|r.init_counter[7] ; 7 ; +; sdram_controller:sdram_|n~2 ; 7 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~1 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 7 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 7 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 7 ; +; ula:ula_|video:video_|vga_hc[8] ; 7 ; +; ula:ula_|video:video_|vga_hc[7] ; 7 ; +; ula:ula_|video:video_|vga_vc[9] ; 7 ; +; ula:ula_|video:video_|vga_vc[1] ; 7 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] ; 7 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] ; 7 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~9 ; 6 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~3 ; 6 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~7 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~14 ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~12 ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|nbyte[1] ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~20 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[0]~18 ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[2] ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~6 ; 6 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|rsel3 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~3 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[1]~20 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~35 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~7 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~5 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~3 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~2 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~37 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla82M1T1_16 ; 6 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~25 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~1 ; 6 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~17 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 6 ; +; sdram_controller:sdram_|r.address[3]~19 ; 6 ; +; sdram_controller:sdram_|Mux19~0 ; 6 ; +; sdram_controller:sdram_|r.address[3]~6 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~12 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 6 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_39 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 6 ; +; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; +; ula:ula_|video:video_|screen_en~1 ; 6 ; +; ula:ula_|video:video_|vga_hc[9] ; 6 ; +; ula:ula_|video:video_|vga_vc[8] ; 6 ; +; ula:ula_|video:video_|vga_vc[7] ; 6 ; +; ula:ula_|video:video_|vga_vc[4] ; 6 ; +; ula:ula_|video:video_|vga_vc[6] ; 6 ; +; ula:ula_|video:video_|vga_vc[3] ; 6 ; +; ula:ula_|video:video_|vga_vc[2] ; 6 ; +; ula:ula_|video:video_|vga_vc[0] ; 6 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 ; 5 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_32 ; 5 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_iy~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla89M1T2_3 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~8 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~19 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~45 ; 5 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[0] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[5]~24 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[6]~22 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|cy_out~0 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[1]~16 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_low ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[3]~14 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[2]~12 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[4]~10 ; 5 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~33 ; 5 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~38 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_mask543_en~0 ; 5 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~16 ; 5 ; +; sdram_controller:sdram_|r.act_row[0]~1 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[0]~26 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~37 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[1] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~11 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~15 ; 5 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~9 ; 5 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~4 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~23 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[1]~17 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~11 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~6 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~12 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~24 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~41 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_ir~1 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~16 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 ; 5 ; +; sdram_controller:sdram_|Mux24~0 ; 5 ; +; sdram_controller:sdram_|n~3 ; 5 ; +; sdram_controller:sdram_|process_0~3 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~7 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~7 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal29~0 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMWrite~3 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~2 ; 5 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nIORQ_out~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~1 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|Equal1~0 ; 5 ; +; ula:ula_|video:video_|vga_hc[5] ; 5 ; +; ula:ula_|video:video_|vga_hc[4] ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 ; 5 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~3 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~37 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal72~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf2_we ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~8 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla57M1T4_4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 4 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Pause ; 4 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[1] ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69~2 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71~2 ; 4 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Stop ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~36 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~27 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~23 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~20 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~17 ; 4 ; +; ula:ula_|video:video_|vram_address[8]~1 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af2~0 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~14 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~5 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[2]~14 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~8 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|alu_core_cf_in~0 ; 4 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_cf ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla66npla53M1T1_15 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~32 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 4 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~9 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~5 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]~24 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[6]~21 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[5]~18 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[4]~15 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[3]~12 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]~9 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]~6 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~2 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~50 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~21 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~38 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~34 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~18 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~15 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[12] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[13] ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~12 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|carry_borrow_out~0 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~27 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~26 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~9 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[10] ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~6 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~3 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[8] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[6] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[3] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[5] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~16 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~11 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~8 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~1 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~30 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~5 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~20 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~6 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~11 ; 4 ; +; sdram_controller:sdram_|Equal2~2 ; 4 ; +; sdram_controller:sdram_|r.init_counter[2] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla42M3T3_6 ; 4 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~1 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~2 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~8 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal46~0 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 4 ; +; ula:ula_|i2s_intf:i2s_intf_|Equal1~1 ; 4 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_16 ; 4 ; +; ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 4 ; +; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; +; sdram_controller:sdram_|r.address[4]~_Duplicate_1 ; 4 ; +; sdram_controller:sdram_|r.address[0]~_Duplicate_1 ; 4 ; +; PS2_DAT~input ; 3 ; +; raw_loader_in~input ; 3 ; +; I2C_SDAT~input ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_use_cf2~13 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~91 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~43 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~42 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_im_we ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~16 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~85 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~15 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~84 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 3 ; +; sdram_controller:sdram_|n~5 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~54 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~35 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~3 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|state~24 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[2] ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg~4 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|divider[0] ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|scl_out~0 ; 3 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_instIFF2 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~17 ; 3 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~2 ; 3 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~24 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|rsel0 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~24 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~10 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; +; sdram_controller:sdram_|Mux4~0 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_pf ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~11 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~1 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~2 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|cy_out~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op2_high[0] ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~17 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~17 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_sf ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_nop3pla68M3T1_20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~11 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op2_low[0] ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~12 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~81 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~54 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~49 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~10 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~13 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~11 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~9 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~3 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~1 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~43 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|carry_borrow_out~0 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~21 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|carry_borrow_out~0 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|carry_borrow_out~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~23 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~83 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~78 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~71 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~52 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~13 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~7 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~31 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~6 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~14 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~43 ; 3 ; +; sdram_controller:sdram_|Mux13~4 ; 3 ; +; sdram_controller:sdram_|Mux23~1 ; 3 ; +; sdram_controller:sdram_|Mux23~0 ; 3 ; +; sdram_controller:sdram_|r.init_counter[3] ; 3 ; +; sdram_controller:sdram_|r.init_counter[8] ; 3 ; +; sdram_controller:sdram_|r.init_counter[9] ; 3 ; +; sdram_controller:sdram_|r.init_counter[10] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~48 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~46 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~45 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~40 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal4~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~29 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~1 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~2 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal79~0 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~2 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc~1 ; 3 ; +; D[7]~92 ; 3 ; +; D[5]~83 ; 3 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~24 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIORead~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIOWrite~0 ; 3 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|LessThan0~0 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~0 ; 3 ; +; ula:ula_|video:video_|VGA_B[0]~1 ; 3 ; +; ula:ula_|video:video_|VGA_G[0]~0 ; 3 ; +; ula:ula_|video:video_|VGA_B[1]~0 ; 3 ; +; ula:ula_|video:video_|VGA_R[0]~0 ; 3 ; +; ula:ula_|video:video_|cindex[2]~0 ; 3 ; +; ula:ula_|video:video_|disp_enable~1 ; 3 ; +; ula:ula_|video:video_|Equal2~0 ; 3 ; +; ula:ula_|video:video_|LessThan6~0 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 ; 3 ; +; sdram_controller:sdram_|r.address[11]~5 ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[7] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[3] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] ; 3 ; +; sdram_controller:sdram_|r.address[10]~_Duplicate_1 ; 3 ; +; sdram_controller:sdram_|r.address[5]~_Duplicate_1 ; 3 ; +; sdram_controller:sdram_|r.address[1]~_Duplicate_1 ; 3 ; +; CLOCK_50~input ; 2 ; +; SW[2]~input ; 2 ; +; SW[1]~input ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~45 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~47 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~89 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~50 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~47 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_4~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[2]~27 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~46 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~46 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~9 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~132 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 ; 2 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~41 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~44 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~19 ; 2 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~46 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~88 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla9M1T5_2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~27 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 2 ; +; sdram_controller:sdram_|Mux10~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~40 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla6M1T4_4 ; 2 ; +; D[6]~109 ; 2 ; +; D[4]~107 ; 2 ; +; D[3]~106 ; 2 ; +; D[0]~104 ; 2 ; +; D[2]~103 ; 2 ; +; D[2]~102 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~12 ; 2 ; +; D[1]~101 ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg~15 ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|Mux35~0 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Done~1 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Done~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|Equal0~1 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[1] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[2] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[3] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[4] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[5] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[6] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|sda_out~4 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|sda_out~1 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|scl_out~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_parity_out ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~24 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf2 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~0 ; 2 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~10 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~37 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~35 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~33 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~31 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~29 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~21 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~28 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~25 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~23 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~15 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 ; 2 ; +; sdram_controller:sdram_|Equal0~2 ; 2 ; +; sdram_controller:sdram_|Mux6~3 ; 2 ; +; sdram_controller:sdram_|Mux6~2 ; 2 ; +; sdram_controller:sdram_|Mux71~8 ; 2 ; +; sdram_controller:sdram_|Mux13~5 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|sel[1]~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~7 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[0]~3 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~39 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT3_3 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_hf ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf2 ; 2 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal64~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~38 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~36 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_nf_we~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[1]~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_high[1] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~14 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~14 ; 2 ; ++-------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++--------------------------------------------------------------------------------+ +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : True Dual Port +Clock Mode : Dual Clocks +Port A Depth : 16384 +Port A Width : 8 +Port B Depth : 16384 +Port B Width : 8 +Port A Input Registers : yes +Port A Output Registers : yes +Port B Input Registers : yes +Port B Output Registers : yes +Size : 131072 +Implementation Port A Depth : 16384 +Implementation Port A Width : 8 +Implementation Port B Depth : 16384 +Implementation Port B Width : 8 +Implementation Bits : 131072 +M9Ks : 16 +MIF : ula/test_scr.hex +Location : M9K_X22_Y20_N0, M9K_X22_Y31_N0, M9K_X22_Y19_N0, M9K_X33_Y28_N0, M9K_X33_Y18_N0, M9K_X22_Y18_N0, M9K_X33_Y27_N0, M9K_X22_Y32_N0, M9K_X22_Y25_N0, M9K_X33_Y24_N0, M9K_X33_Y20_N0, M9K_X33_Y19_N0, M9K_X22_Y33_N0, M9K_X33_Y30_N0, M9K_X33_Y21_N0, M9K_X33_Y23_N0 +Mixed Width RDW Mode : Don't care +Port A RDW Mode : Old data +Port B RDW Mode : Old data +Fits in MLABs : No - Unknown + +Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : Single Port +Clock Mode : Single Clock +Port A Depth : 32768 +Port A Width : 8 +Port B Depth : -- +Port B Width : -- +Port A Input Registers : yes +Port A Output Registers : yes +Port B Input Registers : -- +Port B Output Registers : -- +Size : 262144 +Implementation Port A Depth : 32768 +Implementation Port A Width : 8 +Implementation Port B Depth : -- +Implementation Port B Width : -- +Implementation Bits : 262144 +M9Ks : 32 +MIF : led_patterns.mif +Location : M9K_X22_Y5_N0, M9K_X22_Y16_N0, M9K_X22_Y14_N0, M9K_X22_Y10_N0, M9K_X22_Y15_N0, M9K_X22_Y12_N0, M9K_X22_Y13_N0, M9K_X22_Y11_N0, M9K_X22_Y17_N0, M9K_X33_Y7_N0, M9K_X33_Y5_N0, M9K_X22_Y7_N0, M9K_X33_Y25_N0, M9K_X22_Y30_N0, M9K_X22_Y28_N0, M9K_X33_Y10_N0, M9K_X22_Y22_N0, M9K_X22_Y23_N0, M9K_X22_Y24_N0, M9K_X22_Y21_N0, M9K_X33_Y12_N0, M9K_X33_Y9_N0, M9K_X33_Y17_N0, M9K_X33_Y11_N0, M9K_X22_Y29_N0, M9K_X33_Y26_N0, M9K_X22_Y26_N0, M9K_X22_Y27_N0, M9K_X33_Y16_N0, M9K_X33_Y13_N0, M9K_X33_Y15_N0, M9K_X33_Y14_N0 +Mixed Width RDW Mode : Don't care +Port A RDW Mode : Old data +Port B RDW Mode : Old data +Fits in MLABs : No - Unknown + +Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : ROM +Clock Mode : Single Clock +Port A Depth : 16384 +Port A Width : 8 +Port B Depth : -- +Port B Width : -- +Port A Input Registers : yes +Port A Output Registers : yes +Port B Input Registers : -- +Port B Output Registers : -- +Size : 131072 +Implementation Port A Depth : 16384 +Implementation Port A Width : 8 +Implementation Port B Depth : -- +Implementation Port B Width : -- +Implementation Bits : 131072 +M9Ks : 16 +MIF : ./rom/gw03.hex +Location : M9K_X33_Y6_N0, M9K_X22_Y8_N0, M9K_X33_Y31_N0, M9K_X33_Y2_N0, M9K_X22_Y4_N0, M9K_X33_Y32_N0, M9K_X22_Y6_N0, M9K_X22_Y9_N0, M9K_X33_Y8_N0, M9K_X22_Y2_N0, M9K_X33_Y3_N0, M9K_X33_Y33_N0, M9K_X22_Y3_N0, M9K_X33_Y22_N0, M9K_X33_Y4_N0, M9K_X33_Y29_N0 +Mixed Width RDW Mode : Don't care +Port A RDW Mode : Old data +Port B RDW Mode : Old data +Fits in MLABs : No - Unknown ++--------------------------------------------------------------------------------+ + +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(10000001) (201) (129) (81) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(10000001) (201) (129) (81) ; +;8;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;24;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;32;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;40;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;48;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;56;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;64;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;72;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;80;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;88;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;96;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;296;(00000000) (0) (0) (00) ;(00000000) (0) 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+;16248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 5,309 / 71,559 ( 7 % ) ; +; C16 interconnects ; 176 / 2,597 ( 7 % ) ; +; C4 interconnects ; 2,927 / 46,848 ( 6 % ) ; +; Direct links ; 462 / 71,559 ( < 1 % ) ; +; Global clocks ; 10 / 20 ( 50 % ) ; +; Local interconnects ; 1,391 / 24,624 ( 6 % ) ; +; R24 interconnects ; 152 / 2,496 ( 6 % ) ; +; R4 interconnects ; 3,072 / 62,424 ( 5 % ) ; ++-----------------------+------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 13.58) ; Number of LABs (Total = 193) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 9 ; +; 2 ; 6 ; +; 3 ; 3 ; +; 4 ; 2 ; +; 5 ; 2 ; +; 6 ; 1 ; +; 7 ; 3 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 2 ; +; 11 ; 1 ; +; 12 ; 6 ; +; 13 ; 8 ; +; 14 ; 13 ; +; 15 ; 21 ; +; 16 ; 114 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 1.17) ; Number of LABs (Total = 193) ; ++------------------------------------+-------------------------------+ +; 1 Async. clear ; 52 ; +; 1 Clock ; 107 ; +; 1 Clock enable ; 28 ; +; 1 Sync. load ; 7 ; +; 2 Async. clears ; 2 ; +; 2 Clock enables ; 25 ; +; 2 Clocks ; 4 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 16.56) ; Number of LABs (Total = 193) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 7 ; +; 2 ; 3 ; +; 3 ; 3 ; +; 4 ; 5 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 3 ; +; 10 ; 2 ; +; 11 ; 0 ; +; 12 ; 7 ; +; 13 ; 9 ; +; 14 ; 3 ; +; 15 ; 14 ; +; 16 ; 49 ; +; 17 ; 11 ; +; 18 ; 10 ; +; 19 ; 10 ; +; 20 ; 8 ; +; 21 ; 6 ; +; 22 ; 8 ; +; 23 ; 8 ; +; 24 ; 5 ; +; 25 ; 3 ; +; 26 ; 5 ; +; 27 ; 4 ; +; 28 ; 1 ; +; 29 ; 2 ; +; 30 ; 0 ; +; 31 ; 1 ; +; 32 ; 3 ; ++----------------------------------------------+-------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 8.59) ; Number of LABs (Total = 193) ; ++-------------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 14 ; +; 2 ; 6 ; +; 3 ; 4 ; +; 4 ; 8 ; +; 5 ; 9 ; +; 6 ; 10 ; +; 7 ; 15 ; +; 8 ; 27 ; +; 9 ; 19 ; +; 10 ; 21 ; +; 11 ; 18 ; +; 12 ; 7 ; +; 13 ; 10 ; +; 14 ; 13 ; +; 15 ; 6 ; +; 16 ; 5 ; +; 17 ; 1 ; ++-------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 19.68) ; Number of LABs (Total = 193) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 5 ; +; 3 ; 6 ; +; 4 ; 4 ; +; 5 ; 1 ; +; 6 ; 4 ; +; 7 ; 2 ; +; 8 ; 3 ; +; 9 ; 4 ; +; 10 ; 5 ; +; 11 ; 4 ; +; 12 ; 10 ; +; 13 ; 8 ; +; 14 ; 5 ; +; 15 ; 7 ; +; 16 ; 2 ; +; 17 ; 7 ; +; 18 ; 6 ; +; 19 ; 9 ; +; 20 ; 2 ; +; 21 ; 8 ; +; 22 ; 6 ; +; 23 ; 7 ; +; 24 ; 5 ; +; 25 ; 8 ; +; 26 ; 8 ; +; 27 ; 6 ; +; 28 ; 4 ; +; 29 ; 8 ; +; 30 ; 6 ; +; 31 ; 13 ; +; 32 ; 16 ; +; 33 ; 3 ; ++----------------------------------------------+-------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 11 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 19 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------------------------------------------------------------------------+ +Status : Pass +ID : IO_000001 +Category : Capacity Checks +Rule Description : Number of pins in an I/O bank should not exceed the number of locations available. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000002 +Category : Capacity Checks +Rule Description : Number of clocks in an I/O bank should not exceed the number of clocks available. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000003 +Category : Capacity Checks +Rule Description : Number of pins in a Vrefgroup should not exceed the number of locations available. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000004 +Category : Voltage Compatibility Checks +Rule Description : The I/O bank should support the requested VCCIO. +Severity : Critical +Information : No IOBANK_VCCIO assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000005 +Category : Voltage Compatibility Checks +Rule Description : The I/O bank should not have competing VREF values. +Severity : Critical +Information : No VREF I/O Standard assignments found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000006 +Category : Voltage Compatibility Checks +Rule Description : The I/O bank should not have competing VCCIO values. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000007 +Category : Valid Location Checks +Rule Description : Checks for unavailable locations. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000008 +Category : Valid Location Checks +Rule Description : Checks for reserved locations. +Severity : Critical +Information : No reserved LogicLock region found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000009 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested I/O standard. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000010 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested I/O direction. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000011 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested Current Strength. +Severity : Critical +Information : No Current Strength assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000012 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested On Chip Termination value. +Severity : Critical +Information : No Termination assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000013 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested Bus Hold value. +Severity : Critical +Information : No Enable Bus-Hold Circuitry assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000014 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested Weak Pull Up value. +Severity : Critical +Information : No Weak Pull-Up Resistor assignments found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000015 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested PCI Clamp Diode. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000018 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the requested Current Strength. +Severity : Critical +Information : No Current Strength assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000019 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the requested On Chip Termination value. +Severity : Critical +Information : No Termination assignments found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000020 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the requested PCI Clamp Diode. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000021 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the requested Weak Pull Up value. +Severity : Critical +Information : No Weak Pull-Up Resistor assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000022 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the requested Bus Hold value. +Severity : Critical +Information : No Enable Bus-Hold Circuitry assignments found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000023 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the Open Drain value. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000024 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O direction should support the On Chip Termination value. +Severity : Critical +Information : No Termination assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000026 +Category : I/O Properties Checks for One I/O +Rule Description : On Chip Termination and Current Strength should not be used at the same time. +Severity : Critical +Information : No Current Strength or Termination assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000027 +Category : I/O Properties Checks for One I/O +Rule Description : Weak Pull Up and Bus Hold should not be used at the same time. +Severity : Critical +Information : No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000045 +Category : I/O Properties Checks for One I/O +Rule Description : The I/O standard should support the requested Slew Rate value. +Severity : Critical +Information : No Slew Rate assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000046 +Category : I/O Properties Checks for One I/O +Rule Description : The location should support the requested Slew Rate value. +Severity : Critical +Information : No Slew Rate assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000047 +Category : I/O Properties Checks for One I/O +Rule Description : On Chip Termination and Slew Rate should not be used at the same time. +Severity : Critical +Information : No Slew Rate assignments found. +Area : I/O +Extra Information : + +Status : Pass +ID : IO_000033 +Category : Electromigration Checks +Rule Description : Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. +Severity : Critical +Information : 0 such failures found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000034 +Category : SI Related Distance Checks +Rule Description : Single-ended outputs should be 5 LAB row(s) away from a differential I/O. +Severity : High +Information : No Differential I/O Standard assignments found. +Area : I/O +Extra Information : + +Status : Inapplicable +ID : IO_000042 +Category : SI Related SSO Limit Checks +Rule Description : No more than 20 outputs are allowed in a VREF group when VREF is being read from. +Severity : High +Information : No VREF I/O Standard assignments found. +Area : I/O +Extra Information : ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------------------------------------------------------------------+ +Pin/Rules : Total Pass +IO_000001 : 114 +IO_000002 : 29 +IO_000003 : 114 +IO_000004 : 0 +IO_000005 : 0 +IO_000006 : 114 +IO_000007 : 114 +IO_000008 : 0 +IO_000009 : 114 +IO_000010 : 114 +IO_000011 : 0 +IO_000012 : 0 +IO_000013 : 0 +IO_000014 : 0 +IO_000015 : 57 +IO_000018 : 0 +IO_000019 : 0 +IO_000020 : 57 +IO_000021 : 0 +IO_000022 : 0 +IO_000023 : 10 +IO_000024 : 0 +IO_000026 : 0 +IO_000027 : 0 +IO_000045 : 0 +IO_000046 : 0 +IO_000047 : 0 +IO_000033 : 114 +IO_000034 : 0 +IO_000042 : 0 + +Pin/Rules : Total Unchecked +IO_000001 : 0 +IO_000002 : 0 +IO_000003 : 0 +IO_000004 : 0 +IO_000005 : 0 +IO_000006 : 0 +IO_000007 : 0 +IO_000008 : 0 +IO_000009 : 0 +IO_000010 : 0 +IO_000011 : 0 +IO_000012 : 0 +IO_000013 : 0 +IO_000014 : 0 +IO_000015 : 0 +IO_000018 : 0 +IO_000019 : 0 +IO_000020 : 0 +IO_000021 : 0 +IO_000022 : 0 +IO_000023 : 0 +IO_000024 : 0 +IO_000026 : 0 +IO_000027 : 0 +IO_000045 : 0 +IO_000046 : 0 +IO_000047 : 0 +IO_000033 : 0 +IO_000034 : 0 +IO_000042 : 0 + +Pin/Rules : Total Inapplicable +IO_000001 : 0 +IO_000002 : 85 +IO_000003 : 0 +IO_000004 : 114 +IO_000005 : 114 +IO_000006 : 0 +IO_000007 : 0 +IO_000008 : 114 +IO_000009 : 0 +IO_000010 : 0 +IO_000011 : 114 +IO_000012 : 114 +IO_000013 : 114 +IO_000014 : 114 +IO_000015 : 57 +IO_000018 : 114 +IO_000019 : 114 +IO_000020 : 57 +IO_000021 : 114 +IO_000022 : 114 +IO_000023 : 104 +IO_000024 : 114 +IO_000026 : 114 +IO_000027 : 114 +IO_000045 : 114 +IO_000046 : 114 +IO_000047 : 114 +IO_000033 : 0 +IO_000034 : 114 +IO_000042 : 114 + +Pin/Rules : Total Fail +IO_000001 : 0 +IO_000002 : 0 +IO_000003 : 0 +IO_000004 : 0 +IO_000005 : 0 +IO_000006 : 0 +IO_000007 : 0 +IO_000008 : 0 +IO_000009 : 0 +IO_000010 : 0 +IO_000011 : 0 +IO_000012 : 0 +IO_000013 : 0 +IO_000014 : 0 +IO_000015 : 0 +IO_000018 : 0 +IO_000019 : 0 +IO_000020 : 0 +IO_000021 : 0 +IO_000022 : 0 +IO_000023 : 0 +IO_000024 : 0 +IO_000026 : 0 +IO_000027 : 0 +IO_000045 : 0 +IO_000046 : 0 +IO_000047 : 0 +IO_000033 : 0 +IO_000034 : 0 +IO_000042 : 0 + +Pin/Rules : LED[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[4] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[5] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[6] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : LED[7] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : AUD_XCK +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : AUD_ADCLRCK +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : AUD_DACLRCK +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : AUD_BCLK +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : AUD_DACDAT +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_R[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_R[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_R[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_R[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_G[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable 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Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_G[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_B[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_B[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_B[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_B[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_HS +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : VGA_VS +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : SW[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : SW[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[4] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[5] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[6] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[7] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[8] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[9] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[10] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[11] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[12] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[13] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[14] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[15] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[16] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[17] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[18] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[19] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[20] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[21] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[22] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[23] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[24] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[25] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[26] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[27] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[28] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[29] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[30] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[31] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[32] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : GPIO_1[33] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : buzzer_out +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_BA[0] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_BA[1] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQM[0] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQM[1] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_RAS_N +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CAS_N +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CKE +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CLK +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_WE_N +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CS_N +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[0] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[1] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[2] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[3] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[4] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[5] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[6] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[7] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[8] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[9] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[10] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[11] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[12] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : I2C_SCLK +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : I2C_SDAT +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[4] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[5] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[6] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[7] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[8] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[9] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[10] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[11] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[12] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[13] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[14] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[15] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : SW[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : SW[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : raw_loader_in +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : KEY[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : CLOCK_50 +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : PS2_DAT +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : KEY[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : PS2_CLK +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : AUD_ADCDAT +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable ++--------------------------------------------------------------------------------+ + + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++--------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++--------------------------------------------------------------------------------+ +Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Destination Clock(s) : CLOCK_50 +Delay Added in ns : 548.1 + +Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Destination Clock(s) : CLOCK_50,ula_|pll_|altpll_component|auto_generated|pll1|clk[0],I/O +Delay Added in ns : 24.8 ++--------------------------------------------------------------------------------+ + +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++--------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++--------------------------------------------------------------------------------+ +Source Register : ula:ula_|video:video_|vram_address[8] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.267 + +Source Register : ula:ula_|video:video_|vram_address[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.267 + +Source Register : ula:ula_|video:video_|vram_address[11] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.267 + +Source Register : ula:ula_|video:video_|vram_address[12] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.267 + +Source Register : ula:ula_|video:video_|vram_address[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.196 + +Source Register : ula:ula_|video:video_|vram_address[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.194 + +Source Register : ula:ula_|video:video_|vram_address[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.193 + +Source Register : ula:ula_|video:video_|vram_address[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 2.985 + +Source Register : ula:ula_|video:video_|vram_address[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 2.985 + +Source Register : ula:ula_|video:video_|vram_address[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 2.985 + +Source Register : ula:ula_|video:video_|vram_address[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 2.985 + +Source Register : ula:ula_|video:video_|vram_address[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 2.945 + +Source Register : ula:ula_|video:video_|vram_address[10] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 2.932 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 1.828 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 1.778 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.194 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.186 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.147 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 1.136 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 1.132 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 1.090 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.996 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.983 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.882 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.872 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.827 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.825 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.815 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.792 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.778 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.710 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.637 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.625 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.625 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.622 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.618 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.600 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.579 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.574 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.552 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.549 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.535 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.516 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.506 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.479 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.441 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.421 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.415 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.415 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.415 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.415 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|in_halt +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|M5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.390 ++--------------------------------------------------------------------------------+ + +Note: This table only shows the top 100 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP4CE22F17C6 for design "spectrum" +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1" as Cyclone IV E PLL type + Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] port + Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] port +Info (15535): Implemented PLL "ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type + Info (15099): Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port + Info (15099): Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port + Info (15099): Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE10F17C6 is compatible + Info (176445): Device EP4CE6F17C6 is compatible + Info (176445): Device EP4CE15F17C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Warning (176127): The parameters of the PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 and the PLL sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged + Info (176120): The values of the parameter "M" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "M" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 10 + Info (176121): The value of the parameter "M" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 141 + Info (176120): The values of the parameter "N" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "N" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 1 + Info (176121): The value of the parameter "N" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 7 + Info (176120): The values of the parameter "LOOP FILTER R" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "LOOP FILTER R" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 4000 + Info (176121): The value of the parameter "LOOP FILTER R" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 12000 + Info (176120): The values of the parameter "VCO POST SCALE" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "VCO POST SCALE" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 2 + Info (176121): The value of the parameter "VCO POST SCALE" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 1 + Info (176120): The values of the parameter "Min VCO Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Min VCO Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 1538 + Info (176121): The value of the parameter "Min VCO Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 769 + Info (176120): The values of the parameter "Max VCO Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Max VCO Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 3333 + Info (176121): The value of the parameter "Max VCO Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 1666 + Info (176120): The values of the parameter "Center VCO Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Center VCO Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 1538 + Info (176121): The value of the parameter "Center VCO Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 769 + Info (176120): The values of the parameter "Min Lock Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Min Lock Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 15380 + Info (176121): The value of the parameter "Min Lock Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 15489 + Info (176120): The values of the parameter "Max Lock Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Max Lock Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 33330 + Info (176121): The value of the parameter "Max Lock Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 26455 +Critical Warning (176598): PLL "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_R8" +Info (332104): Reading SDC File: 'spectrum.sdc' +Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port +Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument is an empty collection + Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}] +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} + Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} +Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin +Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection + Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}] +Info (332151): Clock uncertainty is not calculated until you update the timing netlist. +Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock +Warning (332125): Found combinational loop of 509 nodes + Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~8|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~9|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~9|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|datab" + Warning (332126): Node "z80_|alu_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~10|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~14|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~27|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~27|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~23|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|dataa" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|dataa" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~10|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|dataa" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~26|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datab" + Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" + Warning (332126): Node "z80_|alu_|db[4]~8|dataa" + Warning (332126): Node "z80_|alu_|db[4]~8|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~33|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~33|combout" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datab" + Warning (332126): Node "z80_|alu_|db[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|datab" + Warning (332126): Node "z80_|alu_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa" + Warning (332126): Node "z80_|alu_control_|db[0]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~14|dataa" + Warning (332126): Node "z80_|alu_control_|db[0]~14|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~10|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~6|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~7|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datab" + Warning (332126): Node "z80_|alu_|db[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~7|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~0|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~0|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~1|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~1|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|combout" + Warning (332126): Node "z80_|alu_|db[3]~14|dataa" + Warning (332126): Node "z80_|alu_|db[3]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~36|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~36|combout" + Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|alu_|db[3]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~1|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~30|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~37|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~37|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|dataa" + Warning (332126): Node "z80_|alu_|db[2]~11|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~15|datab" + Warning (332126): Node "z80_|alu_|db[1]~15|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~16|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~27|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|datad" + Warning (332126): Node "z80_|alu_|db[1]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~2|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~33|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datac" + Warning (332126): Node "z80_|alu_|db[4]~8|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~0|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~17|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~16|datac" + Warning (332126): Node "z80_|alu_control_|db[5]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~17|dataa" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~20|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datad" + Warning (332126): Node "z80_|alu_|db[7]~19|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datac" +Critical Warning (332081): Design contains combinational loop of 509 nodes. Estimating the delays through the loop. +Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 7 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 10.000 beep + Info (332111): 20.000 CLOCK_50 + Info (332111): 10.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332111): 10.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + Info (332111): 39.716 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332111): 71.489 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332111): 41.702 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 +Info (176353): Automatically promoted node sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_1) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C0 of PLL_1) + Info (176355): Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0 +Info (176353): Automatically promoted node ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_4) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 +Info (176353): Automatically promoted node ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_4) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 +Info (176353): Automatically promoted node ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_4) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 +Info (176353): Automatically promoted node ula:ula_|clocks:clocks_|clk_cpu + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node ula:ula_|clocks:clocks_|clk_cpu~0 +Info (176353): Automatically promoted node reset + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node z80_top_direct_n:z80_|resets:resets_|x1~0 +Info (176353): Automatically promoted node z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node GPIO_1[30]~output + Info (176357): Destination node GPIO_1[0]~output + Info (176357): Destination node GPIO_1[1]~output + Info (176357): Destination node GPIO_1[2]~output + Info (176357): Destination node GPIO_1[3]~output + Info (176357): Destination node GPIO_1[4]~output + Info (176357): Destination node GPIO_1[5]~output + Info (176357): Destination node GPIO_1[6]~output + Info (176357): Destination node GPIO_1[7]~output + Info (176357): Destination node GPIO_1[8]~output + Info (176358): Non-global destination nodes limited to 10 nodes +Info (176353): Automatically promoted node z80_top_direct_n:z80_|fpga_reset + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176353): Automatically promoted node z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176218): Packed 29 registers into blocks of type I/O Output Buffer + Extra Info (176220): Created 15 register duplicates +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "EPCS_ASDO" is assigned to location or region, but does not exist in design + Warning (15706): Node "EPCS_DATA0" is assigned to location or region, but does not exist in design + Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "EPCS_NCSO" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0_IN[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0_IN[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1_IN[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1_IN[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2_IN[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2_IN[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 +Info (170193): Fitter routing operations beginning +Info (170089): 6e+02 ns of routing delay (approximately 1.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. +Info (170195): Router estimated average interconnect usage is 5% of the available device resources + Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:06 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 1.96 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning (169177): 57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. + Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at M1 + Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at M15 + Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at F13 + Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at T15 + Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at T14 + Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at T13 + Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at R13 + Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at T12 + Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at R12 + Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at T11 + Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at T10 + Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at R11 + Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at P11 + Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at R10 + Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at N12 + Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at P9 + Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at N9 + Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at N11 + Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at L16 + Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at K16 + Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at R16 + Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at L15 + Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at P15 + Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at P16 + Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R14 + Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at N16 + Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at N14 + Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at M10 + Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at L13 + Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at J16 + Info (169178): Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2 + Info (169178): Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1 + Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at G2 + Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G1 + Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at L8 + Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at K5 + Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at K2 + Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at J2 + Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at J1 + Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at R7 + Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at T4 + Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at T2 + Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at T3 + Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at R3 + Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at R5 + Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at P3 + Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at N3 + Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at K1 + Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at T8 + Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at B9 + Info (169178): Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6 + Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at J15 + Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 + Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7 + Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at E1 + Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6 + Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8 +Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg +Info: Quartus II 32-bit Fitter was successful. 0 errors, 570 warnings + Info: Peak virtual memory: 645 megabytes + Info: Processing ended: Sat Apr 2 16:35:51 2022 + Info: Elapsed time: 00:00:23 + Info: Total CPU time (on all processors): 00:00:23 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg. + + diff --git a/output_files.old/spectrum.fit.smsg b/output_files.old/spectrum.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/output_files.old/spectrum.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/output_files.old/spectrum.fit.summary b/output_files.old/spectrum.fit.summary new file mode 100644 index 0000000..7a16a6c --- /dev/null +++ b/output_files.old/spectrum.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Sat Apr 2 16:35:50 2022 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : spectrum +Top-level Entity Name : spectrum +Family : Cyclone IV E +Device : EP4CE22F17C6 +Timing Models : Final +Total logic elements : 2,621 / 22,320 ( 12 % ) + Total combinational functions : 2,487 / 22,320 ( 11 % ) + Dedicated logic registers : 635 / 22,320 ( 3 % ) +Total registers : 664 +Total pins : 114 / 154 ( 74 % ) +Total virtual pins : 0 +Total memory bits : 524,288 / 608,256 ( 86 % ) +Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) +Total PLLs : 2 / 4 ( 50 % ) diff --git a/output_files.old/spectrum.flow.rpt b/output_files.old/spectrum.flow.rpt new file mode 100644 index 0000000..5b60e6a --- /dev/null +++ b/output_files.old/spectrum.flow.rpt @@ -0,0 +1,337 @@ +Flow report for spectrum +Sat Apr 2 18:53:05 2022 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+--------------------------------------------+ +; Flow Status ; Flow Failed - Sat Apr 2 18:53:05 2022 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; spectrum ; +; Top-level Entity Name ; spectrum ; +; Family ; Cyclone IV E ; +; Device ; EP4CE22F17C6 ; +; Timing Models ; Final ; +; Total logic elements ; N/A until Partition Merge ; +; Total combinational functions ; N/A until Partition Merge ; +; Dedicated logic registers ; N/A until Partition Merge ; +; Total registers ; N/A until Partition Merge ; +; Total pins ; N/A until Partition Merge ; +; Total virtual pins ; N/A until Partition Merge ; +; Total memory bits ; N/A until Partition Merge ; +; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ; +; Total PLLs ; N/A until Partition Merge ; ++------------------------------------+--------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/02/2022 18:53:05 ; +; Main task ; Compilation ; +; Revision Name ; spectrum ; ++-------------------+---------------------+ + + ++--------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------------------------------------------------+ +Assignment Name : COMPILER_SIGNATURE_ID +Value : 0.164891478433237 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : EDA_OUTPUT_DATA_FORMAT +Value : Verilog Hdl +Default Value : -- +Entity Name : -- +Section Id : eda_simulation + +Assignment Name : EDA_SIMULATION_TOOL +Value : ModelSim-Altera (Verilog) +Default Value : +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : ROM: 1-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : RAM: 2-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : RAM: 1-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : ALTPLL +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : ROM: 1-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : ALTPLL +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : RAM: 2-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_NAME +Value : ALTPLL +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.0 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MAX_CORE_JUNCTION_TEMP +Value : 85 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MIN_CORE_JUNCTION_TEMP +Value : 0 +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : rom0_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : ram16_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : ram32_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : pll_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : pll.ppf +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : rom_scr_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : pll_video_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : pll_video.ppf +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : ram_video_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : sdram_clk_gen_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : sdram_clk_gen.ppf +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE +Value : 1.2V +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : PARTITION_COLOR +Value : 16764057 +Default Value : -- +Entity Name : -- +Section Id : Top + +Assignment Name : PARTITION_FITTER_PRESERVATION_LEVEL +Value : PLACEMENT_AND_ROUTING +Default Value : -- +Entity Name : -- +Section Id : Top + +Assignment Name : PARTITION_NETLIST_TYPE +Value : SOURCE +Default Value : -- +Entity Name : -- +Section Id : Top + +Assignment Name : PROJECT_OUTPUT_DIRECTORY +Value : output_files +Default Value : -- +Entity Name : -- +Section Id : -- ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++--------------------------------------------------------------------------------+ +Module Name : Analysis & Synthesis +Elapsed Time : 00:00:01 +Average Processors Used : 1.0 +Peak Virtual Memory : 397 MB +Total CPU Time (on all processors) : 00:00:01 + +Module Name : Total +Elapsed Time : 00:00:01 +Average Processors Used : -- +Peak Virtual Memory : -- +Total CPU Time (on all processors) : 00:00:01 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Flow OS Summary ; ++--------------------------------------------------------------------------------+ +Module Name : Analysis & Synthesis +Machine Hostname : alpha +OS Name : Ubuntu 21.10 +OS Version : 21 +Processor type : x86_64 ++--------------------------------------------------------------------------------+ + + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum + + + diff --git a/output_files.old/spectrum.jdi b/output_files.old/spectrum.jdi new file mode 100644 index 0000000..931dc02 --- /dev/null +++ b/output_files.old/spectrum.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/output_files.old/spectrum.map.rpt b/output_files.old/spectrum.map.rpt new file mode 100644 index 0000000..d2dd7d5 --- /dev/null +++ b/output_files.old/spectrum.map.rpt @@ -0,0 +1,544 @@ +Analysis & Synthesis report for spectrum +Sat Apr 2 18:53:05 2022 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Messages + 6. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+--------------------------------------------+ +; Analysis & Synthesis Status ; Failed - Sat Apr 2 18:53:05 2022 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; spectrum ; +; Top-level Entity Name ; spectrum ; +; Family ; Cyclone IV E ; +; Total logic elements ; N/A until Partition Merge ; +; Total combinational functions ; N/A until Partition Merge ; +; Dedicated logic registers ; N/A until Partition Merge ; +; Total registers ; N/A until Partition Merge ; +; Total pins ; N/A until Partition Merge ; +; Total virtual pins ; N/A until Partition Merge ; +; Total memory bits ; N/A until Partition Merge ; +; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ; +; Total PLLs ; N/A until Partition Merge ; ++------------------------------------+--------------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------------------------+ +Option : Device +Setting : EP4CE22F17C6 +Default Value : + +Option : Top-level entity name +Setting : spectrum +Default Value : spectrum + +Option : Family name +Setting : Cyclone IV E +Default Value : Cyclone IV GX + +Option : Use smart compilation +Setting : Off +Default Value : Off + +Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation +Setting : On +Default Value : On + +Option : Enable compact report table +Setting : Off +Default Value : Off + +Option : Restructure Multiplexers +Setting : Auto +Default Value : Auto + +Option : Create Debugging Nodes for IP Cores +Setting : Off +Default Value : Off + +Option : Preserve fewer node names +Setting : On +Default Value : On + +Option : Disable OpenCore Plus hardware evaluation +Setting : Off +Default Value : Off + +Option : Verilog Version +Setting : Verilog_2001 +Default Value : Verilog_2001 + +Option : VHDL Version +Setting : VHDL_1993 +Default Value : VHDL_1993 + +Option : State Machine Processing +Setting : Auto +Default Value : Auto + +Option : Safe State Machine +Setting : Off +Default Value : Off + +Option : Extract Verilog State Machines +Setting : On +Default Value : On + +Option : Extract VHDL State Machines +Setting : On +Default Value : On + +Option : Ignore Verilog initial constructs +Setting : Off +Default Value : Off + +Option : Iteration limit for constant Verilog loops +Setting : 5000 +Default Value : 5000 + +Option : Iteration limit for non-constant Verilog loops +Setting : 250 +Default Value : 250 + +Option : Add Pass-Through Logic to Inferred RAMs +Setting : On +Default Value : On + +Option : Infer RAMs from Raw Logic +Setting : On +Default Value : On + +Option : Parallel Synthesis +Setting : On +Default Value : On + +Option : DSP Block Balancing +Setting : Auto +Default Value : Auto + +Option : NOT Gate Push-Back +Setting : On +Default Value : On + +Option : Power-Up Don't Care +Setting : On +Default Value : On + +Option : Remove Redundant Logic Cells +Setting : Off +Default Value : Off + +Option : Remove Duplicate Registers +Setting : On +Default Value : On + +Option : Ignore CARRY Buffers +Setting : Off +Default Value : Off + +Option : Ignore CASCADE Buffers +Setting : Off +Default Value : Off + +Option : Ignore GLOBAL Buffers +Setting : Off +Default Value : Off + +Option : Ignore ROW GLOBAL Buffers +Setting : Off +Default Value : Off + +Option : Ignore LCELL Buffers +Setting : Off +Default Value : Off + +Option : Ignore SOFT Buffers +Setting : On +Default Value : On + +Option : Limit AHDL Integers to 32 Bits +Setting : Off +Default Value : Off + +Option : Optimization Technique +Setting : Balanced +Default Value : Balanced + +Option : Carry Chain Length +Setting : 70 +Default Value : 70 + +Option : Auto Carry Chains +Setting : On +Default Value : On + +Option : Auto Open-Drain Pins +Setting : On +Default Value : On + +Option : Perform WYSIWYG Primitive Resynthesis +Setting : Off +Default Value : Off + +Option : Auto ROM Replacement +Setting : On +Default Value : On + +Option : Auto RAM Replacement +Setting : On +Default Value : On + +Option : Auto DSP Block Replacement +Setting : On +Default Value : On + +Option : Auto Shift Register Replacement +Setting : Auto +Default Value : Auto + +Option : Allow Shift Register Merging across Hierarchies +Setting : Auto +Default Value : Auto + +Option : Auto Clock Enable Replacement +Setting : On +Default Value : On + +Option : Strict RAM Replacement +Setting : Off +Default Value : Off + +Option : Allow Synchronous Control Signals +Setting : On +Default Value : On + +Option : Force Use of Synchronous Clear Signals +Setting : Off +Default Value : Off + +Option : Auto RAM Block Balancing +Setting : On +Default Value : On + +Option : Auto RAM to Logic Cell Conversion +Setting : Off +Default Value : Off + +Option : Auto Resource Sharing +Setting : Off +Default Value : Off + +Option : Allow Any RAM Size For Recognition +Setting : Off +Default Value : Off + +Option : Allow Any ROM Size For Recognition +Setting : Off +Default Value : Off + +Option : Allow Any Shift Register Size For Recognition +Setting : Off +Default Value : Off + +Option : Use LogicLock Constraints during Resource Balancing +Setting : On +Default Value : On + +Option : Ignore translate_off and synthesis_off directives +Setting : Off +Default Value : Off + +Option : Timing-Driven Synthesis +Setting : On +Default Value : On + +Option : Report Parameter Settings +Setting : On +Default Value : On + +Option : Report Source Assignments +Setting : On +Default Value : On + +Option : Report Connectivity Checks +Setting : On +Default Value : On + +Option : Ignore Maximum Fan-Out Assignments +Setting : Off +Default Value : Off + +Option : Synchronization Register Chain Length +Setting : 2 +Default Value : 2 + +Option : PowerPlay Power Optimization +Setting : Normal compilation +Default Value : Normal compilation + +Option : HDL message level +Setting : Level2 +Default Value : Level2 + +Option : Suppress Register Optimization Related Messages +Setting : Off +Default Value : Off + +Option : Number of Removed Registers Reported in Synthesis Report +Setting : 5000 +Default Value : 5000 + +Option : Number of Swept Nodes Reported in Synthesis Report +Setting : 5000 +Default Value : 5000 + +Option : Number of Inverted Registers Reported in Synthesis Report +Setting : 100 +Default Value : 100 + +Option : Clock MUX Protection +Setting : On +Default Value : On + +Option : Auto Gated Clock Conversion +Setting : Off +Default Value : Off + +Option : Block Design Naming +Setting : Auto +Default Value : Auto + +Option : SDC constraint protection +Setting : Off +Default Value : Off + +Option : Synthesis Effort +Setting : Auto +Default Value : Auto + +Option : Shift Register Replacement - Allow Asynchronous Clear Signal +Setting : On +Default Value : On + +Option : Pre-Mapping Resynthesis Optimization +Setting : Off +Default Value : Off + +Option : Analysis & Synthesis Message Level +Setting : Medium +Default Value : Medium + +Option : Disable Register Merging Across Hierarchies +Setting : Auto +Default Value : Auto + +Option : Resource Aware Inference For Block RAM +Setting : On +Default Value : On + +Option : Synthesis Seed +Setting : 1 +Default Value : 1 ++--------------------------------------------------------------------------------+ + + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Analysis & Synthesis + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Sat Apr 2 18:53:04 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv + Info (12023): Found entity 1: spectrum +Info (12021): Found 1 design units, including 1 entities, in source file rom0.v + Info (12023): Found entity 1: rom0 +Info (12021): Found 1 design units, including 1 entities, in source file ram16.v + Info (12023): Found entity 1: ram16 +Info (12021): Found 1 design units, including 1 entities, in source file ram32.v + Info (12023): Found entity 1: ram32 +Info (12021): Found 1 design units, including 1 entities, in source file pll.v + Info (12023): Found entity 1: pll +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu.v + Info (12023): Found entity 1: alu +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v + Info (12023): Found entity 1: alu_bit_select +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v + Info (12023): Found entity 1: alu_control +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v + Info (12023): Found entity 1: alu_core +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v + Info (12023): Found entity 1: alu_flags +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v + Info (12023): Found entity 1: alu_mux_2 +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v + Info (12023): Found entity 1: alu_mux_2z +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v + Info (12023): Found entity 1: alu_mux_3z +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v + Info (12023): Found entity 1: alu_mux_4 +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v + Info (12023): Found entity 1: alu_mux_8 +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v + Info (12023): Found entity 1: alu_prep_daa +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v + Info (12023): Found entity 1: alu_select +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v + Info (12023): Found entity 1: alu_shifter_core +Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v + Info (12023): Found entity 1: alu_slice +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v + Info (12023): Found entity 1: clk_delay +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v + Info (12023): Found entity 1: decode_state +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/execute.v + Info (12023): Found entity 1: execute +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v + Info (12023): Found entity 1: interrupts +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/ir.v + Info (12023): Found entity 1: ir +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v + Info (12023): Found entity 1: memory_ifc +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v + Info (12023): Found entity 1: pin_control +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v + Info (12023): Found entity 1: pla_decode +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/resets.v + Info (12023): Found entity 1: resets +Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v + Info (12023): Found entity 1: sequencer +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v + Info (12023): Found entity 1: address_latch +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v + Info (12023): Found entity 1: address_mux +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v + Info (12023): Found entity 1: address_pins +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v + Info (12023): Found entity 1: bus_control +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v + Info (12023): Found entity 1: bus_switch +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v + Info (12023): Found entity 1: control_pins_n +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v + Info (12023): Found entity 1: data_pins +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v + Info (12023): Found entity 1: data_switch +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v + Info (12023): Found entity 1: data_switch_mask +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v + Info (12023): Found entity 1: inc_dec +Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v + Info (12023): Found entity 1: inc_dec_2bit +Info (12021): Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v + Info (12023): Found entity 1: z80_top_direct_n +Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v + Info (12023): Found entity 1: reg_control +Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v + Info (12023): Found entity 1: reg_file +Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v + Info (12023): Found entity 1: reg_latch +Info (12021): Found 1 design units, including 1 entities, in source file ula/clocks.sv + Info (12023): Found entity 1: clocks +Info (12021): Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv + Info (12023): Found entity 1: zx_keyboard +Info (12021): Found 1 design units, including 1 entities, in source file ula/video.sv + Info (12023): Found entity 1: video +Info (12021): Found 1 design units, including 1 entities, in source file ula/ula.sv + Info (12023): Found entity 1: ula +Info (12021): Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv + Info (12023): Found entity 1: ps2_keyboard +Info (12021): Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd + Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch + Info (12023): Found entity 1: i2c_loader +Info (12021): Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd + Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch + Info (12023): Found entity 1: i2s_intf +Info (12021): Found 1 design units, including 1 entities, in source file rom_scr.v + Info (12023): Found entity 1: rom_scr +Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v + Info (12023): Found entity 1: pll_video +Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v + Info (12023): Found entity 1: ram_video +Info (12021): Found 2 design units, including 1 entities, in source file sdram.vhdl + Info (12022): Found design unit 1: sdram_controller-rtl + Info (12023): Found entity 1: sdram_controller +Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v + Info (12023): Found entity 1: sdram_clk_gen +Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(118) +Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(120) +Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(122) +Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(124) +Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(126) +Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(128) +Info (12021): Found 1 design units, including 1 entities, in source file output_files/output_files/sdram.v + Info (12023): Found entity 1: sdram +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128) +Error (10228): Verilog HDL error at sdram.v(12): module "sdram" cannot be declared more than once File: /home/benny/work/fpga/spectrum/sdram.v Line: 12 +Info (10499): HDL info at sdram.v(12): see declaration for object "sdram" +Info (12021): Found 0 design units, including 0 entities, in source file sdram.v +Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg +Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 13 warnings + Error: Peak virtual memory: 397 megabytes + Error: Processing ended: Sat Apr 2 18:53:05 2022 + Error: Elapsed time: 00:00:01 + Error: Total CPU time (on all processors): 00:00:01 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg. + + diff --git a/output_files.old/spectrum.map.smsg b/output_files.old/spectrum.map.smsg new file mode 100644 index 0000000..c246cc5 --- /dev/null +++ b/output_files.old/spectrum.map.smsg @@ -0,0 +1,2 @@ +Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(19): object "nRESET" differs only in case from object "nreset" in the same scope +Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(22): object "CLK" differs only in case from object "clk" in the same scope diff --git a/output_files.old/spectrum.map.summary b/output_files.old/spectrum.map.summary new file mode 100644 index 0000000..fc76ca8 --- /dev/null +++ b/output_files.old/spectrum.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Failed - Sat Apr 2 18:53:05 2022 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : spectrum +Top-level Entity Name : spectrum +Family : Cyclone IV E +Total logic elements : N/A until Partition Merge + Total combinational functions : N/A until Partition Merge + Dedicated logic registers : N/A until Partition Merge +Total registers : N/A until Partition Merge +Total pins : N/A until Partition Merge +Total virtual pins : N/A until Partition Merge +Total memory bits : N/A until Partition Merge +Embedded Multiplier 9-bit elements : N/A until Partition Merge +Total PLLs : N/A until Partition Merge diff --git a/output_files.old/spectrum.pin b/output_files.old/spectrum.pin new file mode 100644 index 0000000..23d60f8 --- /dev/null +++ b/output_files.old/spectrum.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +CHIP "spectrum" ASSIGNED TO AN: EP4CE22F17C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 3.3V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +buzzer_out : A6 : output : 3.3-V LVTTL : : 8 : Y +AUD_XCK : A7 : output : 3.3-V LVTTL : : 8 : Y +GND+ : A8 : : : : 8 : +GND+ : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y +VGA_B[2] : A12 : output : 3.3-V LVTTL : : 7 : Y +LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : A16 : power : : 3.3V : 7 : +LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y +GND : B2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +raw_loader_in : B6 : input : 3.3-V LVTTL : : 8 : Y +PS2_DAT : B7 : input : 3.3-V LVTTL : : 8 : Y +GND+ : B8 : : : : 8 : +SW[2] : B9 : input : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +VGA_B[1] : B11 : output : 3.3-V LVTTL : : 7 : Y +VGA_VS : B12 : output : 3.3-V LVTTL : : 7 : Y +LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +GND : B15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N +DRAM_WE_N : C2 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +VCCIO8 : C4 : power : : 3.3V : 8 : +GND : C5 : gnd : : : : +AUD_DACLRCK : C6 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : C7 : power : : 3.3V : 8 : +AUD_DACDAT : C8 : output : 3.3-V LVTTL : : 8 : Y +VGA_G[0] : C9 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : C10 : power : : 3.3V : 7 : +VGA_B[0] : C11 : output : 3.3-V LVTTL : : 7 : Y +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 3.3V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : +LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : +VCCD_PLL3 : D4 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +PS2_CLK : D6 : input : 3.3-V LVTTL : : 8 : Y +GND : D7 : gnd : : : : +AUD_ADCDAT : D8 : input : 3.3-V LVTTL : : 8 : Y +VGA_G[1] : D9 : output : 3.3-V LVTTL : : 7 : Y +GND : D10 : gnd : : : : +VGA_B[3] : D11 : output : 3.3-V LVTTL : : 7 : Y +VGA_HS : D12 : output : 3.3-V LVTTL : : 7 : Y +VCCD_PLL2 : D13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 : +KEY[1] : E1 : input : 3.3-V LVTTL : : 1 : Y +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 3.3V : 1 : +GND : E4 : gnd : : : : +GNDA3 : E5 : gnd : : : : +AUD_BCLK : E6 : output : 3.3-V LVTTL : : 8 : Y +AUD_ADCLRCK : E7 : output : 3.3-V LVTTL : : 8 : Y +VGA_R[0] : E8 : output : 3.3-V LVTTL : : 8 : Y +VGA_R[3] : E9 : output : 3.3-V LVTTL : : 7 : Y +VGA_G[3] : E10 : output : 3.3-V LVTTL : : 7 : Y +VGA_G[2] : E11 : output : 3.3-V LVTTL : : 7 : Y +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 3.3V : 6 : +GND+ : E15 : : : : 6 : +GND+ : E16 : : : : 6 : +I2C_SDAT : F1 : bidir : 3.3-V LVTTL : : 1 : Y +I2C_SCLK : F2 : bidir : 3.3-V LVTTL : : 1 : Y +LED[5] : F3 : output : 3.3-V LVTTL : : 1 : Y +nSTATUS : F4 : : : : 1 : +VCCA3 : F5 : power : : 2.5V : : +GND : F6 : gnd : : : : +VCCINT : F7 : power : : 1.2V : : +VGA_R[1] : F8 : output : 3.3-V LVTTL : : 8 : Y +VGA_R[2] : F9 : output : 3.3-V LVTTL : : 7 : Y +GND : F10 : gnd : : : : +VCCINT : F11 : power : : 1.2V : : +VCCA2 : F12 : power : : 2.5V : : +GPIO_1[0] : F13 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 3.3-V LVTTL : : 6 : N +DRAM_DQ[1] : G1 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[0] : G2 : bidir : 3.3-V LVTTL : : 1 : Y +VCCIO1 : G3 : power : : 3.3V : 1 : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +GND : G11 : gnd : : : : +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 3.3V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 : +~ALTERA_DCLK~ : H1 : output : 3.3-V LVTTL : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 3.3-V LVTTL : : 1 : N +TCK : H3 : input : : : 1 : +TDI : H4 : input : : : 1 : +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +DRAM_DQ[6] : J1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[5] : J2 : bidir : 3.3-V LVTTL : : 2 : Y +nCE : J3 : : : : 1 : +TDO : J4 : output : : : 1 : +TMS : J5 : input : : : 1 : +VCCINT : J6 : power : : 1.2V : : +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +GND : J11 : gnd : : : : +VCCINT : J12 : power : : 1.2V : : +GPIO_1[32] : J13 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[33] : J14 : output : 3.3-V LVTTL : : 5 : Y +KEY[0] : J15 : input : 3.3-V LVTTL : : 5 : Y +GPIO_1[30] : J16 : output : 3.3-V LVTTL : : 5 : Y +DRAM_DQ[15] : K1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[4] : K2 : bidir : 3.3-V LVTTL : : 2 : Y +VCCIO2 : K3 : power : : 3.3V : 2 : +GND : K4 : gnd : : : : +DRAM_DQ[3] : K5 : bidir : 3.3-V LVTTL : : 2 : Y +GND : K6 : gnd : : : : +VCCINT : K7 : power : : 1.2V : : +GND : K8 : gnd : : : : +VCCINT : K9 : power : : 1.2V : : +VCCINT : K10 : power : : 1.2V : : +VCCINT : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 3.3V : 5 : +GPIO_1[31] : K15 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[17] : K16 : output : 3.3-V LVTTL : : 5 : Y +DRAM_CAS_N : L1 : output : 3.3-V LVTTL : : 2 : Y +DRAM_RAS_N : L2 : output : 3.3-V LVTTL : : 2 : Y +LED[7] : L3 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[12] : L4 : output : 3.3-V LVTTL : : 2 : Y +VCCA1 : L5 : power : : 2.5V : : +VCCINT : L6 : power : : 1.2V : : +DRAM_CKE : L7 : output : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[2] : L8 : bidir : 3.3-V LVTTL : : 3 : Y +GND : L9 : gnd : : : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +VCCA4 : L12 : power : : 2.5V : : +GPIO_1[29] : L13 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[26] : L14 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[19] : L15 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[16] : L16 : output : 3.3-V LVTTL : : 5 : Y +SW[0] : M1 : input : 3.3-V LVTTL : : 2 : Y +GND+ : M2 : : : : 2 : +VCCIO2 : M3 : power : : 3.3V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +DRAM_BA[1] : M6 : output : 3.3-V LVTTL : : 3 : Y +DRAM_BA[0] : M7 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[3] : M8 : output : 3.3-V LVTTL : : 3 : Y +VCCINT : M9 : power : : 1.2V : : +GPIO_1[28] : M10 : output : 3.3-V LVTTL : : 4 : Y +VCCINT : M11 : power : : 1.2V : : +GNDA4 : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 3.3V : 5 : +SW[3] : M15 : input : 3.3-V LVTTL : : 5 : Y +GND+ : M16 : : : : 5 : +DRAM_ADDR[11] : N1 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[10] : N2 : output : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[14] : N3 : bidir : 3.3-V LVTTL : : 3 : Y +VCCD_PLL1 : N4 : power : : 1.2V : : +DRAM_ADDR[1] : N5 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[2] : N6 : output : 3.3-V LVTTL : : 3 : Y +GND : N7 : gnd : : : : +DRAM_ADDR[6] : N8 : output : 3.3-V LVTTL : : 3 : Y +GPIO_1[14] : N9 : output : 3.3-V LVTTL : : 4 : Y +GND : N10 : gnd : : : : +GPIO_1[15] : N11 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[12] : N12 : output : 3.3-V LVTTL : : 4 : Y +VCCD_PLL4 : N13 : power : : 1.2V : : +GPIO_1[27] : N14 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[24] : N15 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[23] : N16 : output : 3.3-V LVTTL : : 5 : Y +DRAM_ADDR[9] : P1 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[0] : P2 : output : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[13] : P3 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : P4 : power : : 3.3V : 3 : +GND : P5 : gnd : : : : +DRAM_CS_N : P6 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : P7 : power : : 3.3V : 3 : +DRAM_ADDR[4] : P8 : output : 3.3-V LVTTL : : 3 : Y +GPIO_1[13] : P9 : output : 3.3-V LVTTL : : 4 : Y +VCCIO4 : P10 : power : : 3.3V : 4 : +GPIO_1[10] : P11 : output : 3.3-V LVTTL : : 4 : Y +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 3.3V : 4 : +GPIO_1[25] : P14 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[20] : P15 : output : 3.3-V LVTTL : : 5 : Y +GPIO_1[21] : P16 : output : 3.3-V LVTTL : : 5 : Y +DRAM_ADDR[8] : R1 : output : 3.3-V LVTTL : : 2 : Y +GND : R2 : gnd : : : : +DRAM_DQ[11] : R3 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_CLK : R4 : output : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[12] : R5 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQM[0] : R6 : output : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[7] : R7 : bidir : 3.3-V LVTTL : : 3 : Y +CLOCK_50 : R8 : input : 3.3-V LVTTL : : 3 : Y +GND+ : R9 : : : : 4 : +GPIO_1[11] : R10 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[9] : R11 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[6] : R12 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[4] : R13 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[22] : R14 : output : 3.3-V LVTTL : : 4 : Y +GND : R15 : gnd : : : : +GPIO_1[18] : R16 : output : 3.3-V LVTTL : : 5 : Y +VCCIO3 : T1 : power : : 3.3V : 3 : +DRAM_DQ[9] : T2 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[10] : T3 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[8] : T4 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQM[1] : T5 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[7] : T6 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[5] : T7 : output : 3.3-V LVTTL : : 3 : Y +SW[1] : T8 : input : 3.3-V LVTTL : : 3 : Y +GND+ : T9 : : : : 4 : +GPIO_1[8] : T10 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[7] : T11 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[5] : T12 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[3] : T13 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[2] : T14 : output : 3.3-V LVTTL : : 4 : Y +GPIO_1[1] : T15 : output : 3.3-V LVTTL : : 4 : Y +VCCIO4 : T16 : power : : 3.3V : 4 : diff --git a/output_files.old/spectrum.sof b/output_files.old/spectrum.sof new file mode 100644 index 0000000..15cd976 Binary files /dev/null and b/output_files.old/spectrum.sof differ diff --git a/output_files.old/spectrum.sta.rpt b/output_files.old/spectrum.sta.rpt new file mode 100644 index 0000000..b48df1b --- /dev/null +++ b/output_files.old/spectrum.sta.rpt @@ -0,0 +1,56010 @@ +TimeQuest Timing Analyzer report for spectrum +Sat Apr 2 16:35:59 2022 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1200mV 85C Model Setup Summary + 9. Slow 1200mV 85C Model Hold Summary + 10. Slow 1200mV 85C Model Recovery Summary + 11. Slow 1200mV 85C Model Removal Summary + 12. Slow 1200mV 85C Model Minimum Pulse Width Summary + 13. Slow 1200mV 85C Model Setup: 'CLOCK_50' + 14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 17. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 18. Slow 1200mV 85C Model Hold: 'CLOCK_50' + 19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 21. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 22. Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 23. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 24. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 25. Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 26. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' + 27. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 28. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 29. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 30. Setup Times + 31. Hold Times + 32. Clock to Output Times + 33. Minimum Clock to Output Times + 34. Propagation Delay + 35. Minimum Propagation Delay + 36. Output Enable Times + 37. Minimum Output Enable Times + 38. Output Disable Times + 39. Minimum Output Disable Times + 40. Slow 1200mV 85C Model Metastability Report + 41. Slow 1200mV 0C Model Fmax Summary + 42. Slow 1200mV 0C Model Setup Summary + 43. Slow 1200mV 0C Model Hold Summary + 44. Slow 1200mV 0C Model Recovery Summary + 45. Slow 1200mV 0C Model Removal Summary + 46. Slow 1200mV 0C Model Minimum Pulse Width Summary + 47. Slow 1200mV 0C Model Setup: 'CLOCK_50' + 48. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 49. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 50. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 51. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 52. Slow 1200mV 0C Model Hold: 'CLOCK_50' + 53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 54. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 55. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 56. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 57. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 58. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 59. Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 60. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 61. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 62. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 63. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 64. Setup Times + 65. Hold Times + 66. Clock to Output Times + 67. Minimum Clock to Output Times + 68. Propagation Delay + 69. Minimum Propagation Delay + 70. Output Enable Times + 71. Minimum Output Enable Times + 72. Output Disable Times + 73. Minimum Output Disable Times + 74. Slow 1200mV 0C Model Metastability Report + 75. Fast 1200mV 0C Model Setup Summary + 76. Fast 1200mV 0C Model Hold Summary + 77. Fast 1200mV 0C Model Recovery Summary + 78. Fast 1200mV 0C Model Removal Summary + 79. Fast 1200mV 0C Model Minimum Pulse Width Summary + 80. Fast 1200mV 0C Model Setup: 'CLOCK_50' + 81. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 82. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 83. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 84. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 85. Fast 1200mV 0C Model Hold: 'CLOCK_50' + 86. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 88. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 89. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 90. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 91. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 92. Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 93. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 94. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 95. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 96. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 97. Setup Times + 98. Hold Times + 99. Clock to Output Times +100. Minimum Clock to Output Times +101. Propagation Delay +102. Minimum Propagation Delay +103. Output Enable Times +104. Minimum Output Enable Times +105. Output Disable Times +106. Minimum Output Disable Times +107. Fast 1200mV 0C Model Metastability Report +108. Multicorner Timing Analysis Summary +109. Setup Times +110. Hold Times +111. Clock to Output Times +112. Minimum Clock to Output Times +113. Propagation Delay +114. Minimum Propagation Delay +115. Board Trace Model Assignments +116. Input Transition Times +117. Signal Integrity Metrics (Slow 1200mv 0c Model) +118. Signal Integrity Metrics (Slow 1200mv 85c Model) +119. Signal Integrity Metrics (Fast 1200mv 0c Model) +120. Setup Transfers +121. Hold Transfers +122. Recovery Transfers +123. Removal Transfers +124. Report TCCS +125. Report RSKM +126. Unconstrained Paths +127. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+----------------------------------------------------+ +; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; spectrum ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE22F17C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+----------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------------------------------------------------------------------------+ +; SDC File List ; ++--------------------------------------------------------------------------------+ +SDC File Path : spectrum.sdc +Status : OK +Read at : Sat Apr 2 16:35:56 2022 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Clocks ; ++--------------------------------------------------------------------------------+ +Clock Name : beep +Type : Base +Period : 10.000 +Frequency : 100.0 MHz +Rise : 0.000 +Fall : 5.000 +Duty Cycle : +Divide by : +Multiply by : +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : +Master : +Source : +Targets : { ula:ula_|beep } + +Clock Name : CLOCK_50 +Type : Base +Period : 20.000 +Frequency : 50.0 MHz +Rise : 0.000 +Fall : 10.000 +Duty Cycle : +Divide by : +Multiply by : +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : +Master : +Source : +Targets : { CLOCK_50 } + +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Type : Generated +Period : 10.000 +Frequency : 100.0 MHz +Rise : 0.000 +Fall : 5.000 +Duty Cycle : 50.00 +Divide by : 1 +Multiply by : 2 +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0] +Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] } + +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] +Type : Generated +Period : 10.000 +Frequency : 100.0 MHz +Rise : 3.000 +Fall : 8.000 +Duty Cycle : 50.00 +Divide by : 1 +Multiply by : 2 +Phase : 108.0 +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0] +Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] } + +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Type : Generated +Period : 39.716 +Frequency : 25.18 MHz +Rise : 0.000 +Fall : 19.858 +Duty Cycle : 50.00 +Divide by : 280 +Multiply by : 141 +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0] +Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[0] } + +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Type : Generated +Period : 71.489 +Frequency : 13.99 MHz +Rise : 0.000 +Fall : 35.744 +Duty Cycle : 50.00 +Divide by : 168 +Multiply by : 47 +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0] +Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[1] } + +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Type : Generated +Period : 41.702 +Frequency : 23.98 MHz +Rise : 0.000 +Fall : 20.851 +Duty Cycle : 50.00 +Divide by : 98 +Multiply by : 47 +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0] +Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] } ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++--------------------------------------------------------------------------------+ +Fmax : 48.05 MHz +Restricted Fmax : 48.05 MHz +Clock Name : CLOCK_50 +Note : + +Fmax : 129.33 MHz +Restricted Fmax : 129.33 MHz +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Note : + +Fmax : 133.33 MHz +Restricted Fmax : 133.33 MHz +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Note : + +Fmax : 197.71 MHz +Restricted Fmax : 197.71 MHz +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Note : + +Fmax : 938.97 MHz +Restricted Fmax : 500.0 MHz +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Note : limit due to minimum period restriction (tmin) ++--------------------------------------------------------------------------------+ + +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++--------------------------------------------------------------------------------+ +Clock : CLOCK_50 +Slack : -18.257 +End Point TNS : -809.639 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -7.550 +End Point TNS : -292.429 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -4.737 +End Point TNS : -40.228 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : -2.914 +End Point TNS : -2.914 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 2.500 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++--------------------------------------------------------------------------------+ +Clock : CLOCK_50 +Slack : -0.026 +End Point TNS : -0.026 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.342 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 0.342 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 0.343 +End Point TNS : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.358 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery Summary ; ++--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -6.225 +End Point TNS : -455.695 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal Summary ; ++--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 3.696 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++--------------------------------------------------------------------------------+ +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.752 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 9.489 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 19.601 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 20.596 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 35.503 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : -18.257 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 8.098 + +Slack : -18.195 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 7.749 + +Slack : -18.184 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 8.025 + +Slack : -18.113 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.954 + +Slack : -18.106 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.664 + +Slack : -18.104 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.945 + +Slack : -18.066 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 7.620 + +Slack : -18.063 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.904 + +Slack : -18.044 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 7.611 + +Slack : -18.027 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.868 + +Slack : -18.022 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.863 + +Slack : -18.015 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.835 + +Slack : -18.012 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.562 + +Slack : -18.006 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.564 + +Slack : -17.976 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.796 + +Slack : -17.966 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.807 + +Slack : -17.962 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.803 + +Slack : -17.961 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 7.517 + +Slack : -17.955 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.513 + +Slack : -17.950 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.526 +Data Delay : 7.498 + +Slack : -17.947 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.505 + +Slack : -17.941 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.782 + +Slack : -17.937 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 7.488 + +Slack : -17.915 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.465 + +Slack : -17.915 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 7.482 + +Slack : -17.898 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.739 + +Slack : -17.887 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 7.439 + +Slack : -17.885 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.443 + +Slack : -17.884 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.702 + +Slack : -17.877 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.435 + +Slack : -17.861 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.411 + +Slack : -17.838 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.658 + +Slack : -17.818 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.376 + +Slack : -17.797 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.615 + +Slack : -17.790 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.631 + +Slack : -17.782 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.623 + +Slack : -17.761 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.311 + +Slack : -17.754 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.304 + +Slack : -17.741 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.259 +Data Delay : 7.556 + +Slack : -17.732 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 7.288 + +Slack : -17.732 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.552 + +Slack : -17.721 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.526 +Data Delay : 7.269 + +Slack : -17.717 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 7.270 + +Slack : -17.712 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.553 + +Slack : -17.706 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.519 +Data Delay : 7.261 + +Slack : -17.706 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.526 + +Slack : -17.693 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.254 + +Slack : -17.691 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.511 + +Slack : -17.686 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.527 + +Slack : -17.678 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.228 + +Slack : -17.672 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 7.225 + +Slack : -17.669 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.255 +Data Delay : 7.488 + +Slack : -17.663 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.213 + +Slack : -17.647 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.488 + +Slack : -17.640 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.255 +Data Delay : 7.459 + +Slack : -17.632 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.473 + +Slack : -17.631 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.451 + +Slack : -17.624 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.465 + +Slack : -17.615 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.433 + +Slack : -17.610 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.160 + +Slack : -17.608 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 7.162 + +Slack : -17.585 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.259 +Data Delay : 7.400 + +Slack : -17.585 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 7.147 + +Slack : -17.578 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 7.144 + +Slack : -17.570 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.259 +Data Delay : 7.385 + +Slack : -17.568 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.386 + +Slack : -17.565 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.406 + +Slack : -17.560 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.401 + +Slack : -17.557 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 7.117 + +Slack : -17.555 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.519 +Data Delay : 7.110 + +Slack : -17.542 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.383 + +Slack : -17.539 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.254 +Data Delay : 7.359 + +Slack : -17.536 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.354 + +Slack : -17.529 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.370 + +Slack : -17.512 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.330 + +Slack : -17.490 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 7.055 + +Slack : -17.488 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 7.041 + +Slack : -17.487 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.328 + +Slack : -17.486 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.045 + +Slack : -17.482 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 7.047 + +Slack : -17.480 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.041 + +Slack : -17.478 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.037 + +Slack : -17.472 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.313 + +Slack : -17.445 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.263 + +Slack : -17.443 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.996 + +Slack : -17.430 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.982 + +Slack : -17.428 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.986 + +Slack : -17.394 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.953 + +Slack : -17.386 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.945 + +Slack : -17.383 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.944 + +Slack : -17.376 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.217 + +Slack : -17.374 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.933 + +Slack : -17.369 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.933 + +Slack : -17.338 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.259 +Data Delay : 7.153 + +Slack : -17.325 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 6.888 + +Slack : -17.291 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.256 +Data Delay : 7.109 + +Slack : -17.275 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 6.838 + +Slack : -17.275 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.837 + +Slack : -17.268 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.834 + +Slack : -17.267 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 6.830 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : -7.550 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.288 +Data Delay : 5.370 + +Slack : -7.542 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.301 +Data Delay : 5.349 + +Slack : -7.478 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 5.592 + +Slack : -7.352 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.285 +Data Delay : 5.175 + +Slack : -7.350 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.286 +Data Delay : 5.172 + +Slack : -7.292 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 5.120 + +Slack : -7.289 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 5.113 + +Slack : -7.286 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 5.103 + +Slack : -7.284 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 5.099 + +Slack : -7.281 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.297 +Data Delay : 5.092 + +Slack : -7.273 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 5.091 + +Slack : -7.265 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 5.082 + +Slack : -7.241 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.282 +Data Delay : 5.067 + +Slack : -7.233 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 5.046 + +Slack : -7.231 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 5.049 + +Slack : -7.220 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.986 +Data Delay : 5.342 + +Slack : -7.217 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.990 +Data Delay : 5.335 + +Slack : -7.173 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.288 +Data Delay : 4.993 + +Slack : -7.169 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 5.289 + +Slack : -7.117 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.296 +Data Delay : 4.929 + +Slack : -7.113 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.289 +Data Delay : 4.932 + +Slack : -7.088 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.300 +Data Delay : 4.896 + +Slack : -7.084 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.909 + +Slack : -7.082 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.261 +Data Delay : 4.929 + +Slack : -7.078 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.281 +Data Delay : 4.905 + +Slack : -7.024 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.275 +Data Delay : 4.857 + +Slack : -7.022 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.868 + +Slack : -7.013 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.867 + +Slack : -7.011 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.256 +Data Delay : 4.863 + +Slack : -7.008 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.274 +Data Delay : 4.842 + +Slack : -6.982 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.841 + +Slack : -6.981 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.847 + +Slack : -6.979 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.278 +Data Delay : 4.809 + +Slack : -6.975 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.270 +Data Delay : 4.813 + +Slack : -6.969 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.308 +Data Delay : 4.769 + +Slack : -6.968 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 4.835 + +Slack : -6.964 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.276 +Data Delay : 4.796 + +Slack : -6.960 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.826 + +Slack : -6.926 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 4.793 + +Slack : -6.860 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.286 +Data Delay : 4.682 + +Slack : -6.848 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.253 +Data Delay : 4.703 + +Slack : -6.848 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.672 + +Slack : -6.839 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.663 + +Slack : -6.830 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.667 + +Slack : -6.812 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.267 +Data Delay : 4.653 + +Slack : -6.803 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.662 + +Slack : -6.802 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.661 + +Slack : -6.800 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.253 +Data Delay : 4.655 + +Slack : -6.798 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.652 + +Slack : -6.794 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.622 + +Slack : -6.789 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.286 +Data Delay : 4.611 + +Slack : -6.787 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.287 +Data Delay : 4.608 + +Slack : -6.781 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.610 + +Slack : -6.773 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.601 + +Slack : -6.772 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.272 +Data Delay : 4.608 + +Slack : -6.757 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.608 + +Slack : -6.755 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.246 +Data Delay : 4.617 + +Slack : -6.752 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.250 +Data Delay : 4.610 + +Slack : -6.748 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.599 + +Slack : -6.743 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.250 +Data Delay : 4.601 + +Slack : -6.739 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.568 + +Slack : -6.717 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.568 + +Slack : -6.715 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.294 +Data Delay : 4.529 + +Slack : -6.704 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.564 + +Slack : -6.699 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.536 + +Slack : -6.690 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.527 + +Slack : -6.688 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.504 + +Slack : -6.687 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.541 + +Slack : -6.678 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 4.495 + +Slack : -6.662 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.525 + +Slack : -6.658 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.524 + +Slack : -6.650 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.487 + +Slack : -6.649 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.513 + +Slack : -6.644 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.265 +Data Delay : 4.487 + +Slack : -6.641 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.504 + +Slack : -6.629 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.246 +Data Delay : 4.491 + +Slack : -6.617 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.263 +Data Delay : 4.462 + +Slack : -6.616 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.470 + +Slack : -6.609 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.269 +Data Delay : 4.448 + +Slack : -6.607 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.453 + +Slack : -6.607 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.471 + +Slack : -6.590 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.300 +Data Delay : 4.398 + +Slack : -6.565 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.394 + +Slack : -6.535 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.276 +Data Delay : 4.367 + +Slack : -6.534 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.304 +Data Delay : 4.338 + +Slack : -6.532 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 4.389 + +Slack : -6.526 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.385 + +Slack : -6.521 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.345 + +Slack : -6.519 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.278 +Data Delay : 4.349 + +Slack : -6.515 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.282 +Data Delay : 4.341 + +Slack : -6.510 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.364 + +Slack : -6.510 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.253 +Data Delay : 4.365 + +Slack : -6.507 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.302 +Data Delay : 4.313 + +Slack : -6.497 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.301 +Data Delay : 4.304 + +Slack : -6.486 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.345 + +Slack : -6.481 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.278 +Data Delay : 4.311 + +Slack : -6.478 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.341 + +Slack : -6.474 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.267 +Data Delay : 4.315 + +Slack : -6.469 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.332 + +Slack : -6.453 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 4.310 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.737 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.193 +Data Delay : 2.828 + +Slack : -4.251 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.173 +Data Delay : 2.803 + +Slack : -4.251 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.173 +Data Delay : 2.803 + +Slack : -4.052 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.621 + +Slack : -4.052 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.621 + +Slack : -4.052 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.621 + +Slack : -4.052 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.621 + +Slack : -4.052 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.621 + +Slack : -3.592 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.203 +Data Delay : 2.174 + +Slack : -3.137 +From Node : AUD_ADCDAT +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.177 +Data Delay : 1.693 + +Slack : 16.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.388 +Data Delay : 3.473 + +Slack : 16.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.388 +Data Delay : 3.473 + +Slack : 16.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.388 +Data Delay : 3.473 + +Slack : 16.985 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.388 +Data Delay : 3.473 + +Slack : 17.024 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.387 +Data Delay : 3.435 + +Slack : 17.024 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.387 +Data Delay : 3.435 + +Slack : 17.024 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.387 +Data Delay : 3.435 + +Slack : 17.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.388 +Data Delay : 3.395 + +Slack : 17.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.388 +Data Delay : 3.395 + +Slack : 17.115 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.300 + +Slack : 17.115 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.300 + +Slack : 17.115 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.300 + +Slack : 17.115 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.300 + +Slack : 17.148 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.387 +Data Delay : 3.311 + +Slack : 17.148 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.387 +Data Delay : 3.311 + +Slack : 17.157 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.259 + +Slack : 17.157 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.259 + +Slack : 17.157 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.259 + +Slack : 17.203 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.212 + +Slack : 17.203 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.212 + +Slack : 17.239 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.176 + +Slack : 17.239 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.176 + +Slack : 17.239 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.176 + +Slack : 17.239 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.176 + +Slack : 17.278 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.138 + +Slack : 17.278 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.138 + +Slack : 17.278 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.138 + +Slack : 17.280 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.136 + +Slack : 17.280 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.136 + +Slack : 17.317 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.098 + +Slack : 17.317 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.098 + +Slack : 17.356 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.059 + +Slack : 17.356 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.059 + +Slack : 17.356 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.059 + +Slack : 17.356 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.059 + +Slack : 17.398 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.018 + +Slack : 17.398 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.018 + +Slack : 17.398 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.018 + +Slack : 17.402 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.014 + +Slack : 17.402 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.014 + +Slack : 17.438 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.977 + +Slack : 17.438 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.977 + +Slack : 17.521 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.895 + +Slack : 17.521 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.895 + +Slack : 17.628 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 3.165 + +Slack : 17.628 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 3.165 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.036 +Data Delay : 3.160 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.036 +Data Delay : 3.160 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.036 +Data Delay : 3.160 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.036 +Data Delay : 3.160 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.036 +Data Delay : 3.160 + +Slack : 17.747 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 3.003 + +Slack : 17.747 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 3.003 + +Slack : 17.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.651 + +Slack : 17.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.651 + +Slack : 17.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.651 + +Slack : 17.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.651 + +Slack : 17.769 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.998 + +Slack : 17.769 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.998 + +Slack : 17.769 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.998 + +Slack : 17.769 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.998 + +Slack : 17.769 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.998 + +Slack : 17.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.389 +Data Delay : 2.683 + +Slack : 17.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.389 +Data Delay : 2.683 + +Slack : 17.774 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.389 +Data Delay : 2.683 + +Slack : 17.806 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.610 + +Slack : 17.806 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.610 + +Slack : 17.806 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.610 + +Slack : 17.856 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.559 + +Slack : 17.856 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.559 + +Slack : 17.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.550 + +Slack : 17.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.550 + +Slack : 17.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.550 + +Slack : 17.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.550 + +Slack : 17.879 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.419 +Data Delay : 2.453 + +Slack : 17.882 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 2.868 + +Slack : 17.882 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 2.868 + +Slack : 17.893 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.521 + +Slack : 17.893 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.521 + +Slack : 17.893 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.521 + +Slack : 17.904 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.863 + +Slack : 17.904 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.863 + +Slack : 17.904 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.863 + +Slack : 17.904 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.863 + +Slack : 17.904 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 2.863 + +Slack : 17.907 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.509 + +Slack : 17.907 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.509 + +Slack : 17.907 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.509 + +Slack : 17.915 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.389 +Data Delay : 2.542 + +Slack : 17.918 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.389 +Data Delay : 2.539 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : -2.914 +From Node : SW[2] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.423 +Clock Skew : 0.216 +Data Delay : 1.508 + +Slack : 70.424 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.078 +Data Delay : 0.982 + +Slack : 70.747 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.078 +Data Delay : 0.659 + +Slack : 70.747 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.078 +Data Delay : 0.659 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 2.500 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.983 + +Slack : 2.646 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.417 +Data Delay : 6.835 + +Slack : 2.851 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.632 + +Slack : 2.853 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.435 +Data Delay : 6.612 + +Slack : 2.868 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.615 + +Slack : 2.875 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.608 + +Slack : 2.883 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.434 +Data Delay : 6.583 + +Slack : 2.918 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.414 +Data Delay : 6.566 + +Slack : 2.990 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.490 + +Slack : 2.997 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.417 +Data Delay : 6.484 + +Slack : 3.005 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.475 + +Slack : 3.014 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.417 +Data Delay : 6.467 + +Slack : 3.021 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.417 +Data Delay : 6.460 + +Slack : 3.125 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.358 + +Slack : 3.149 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.331 + +Slack : 3.204 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.435 +Data Delay : 6.261 + +Slack : 3.221 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.435 +Data Delay : 6.244 + +Slack : 3.228 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.435 +Data Delay : 6.237 + +Slack : 3.232 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 6.250 + +Slack : 3.232 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 6.250 + +Slack : 3.234 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.434 +Data Delay : 6.232 + +Slack : 3.251 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.434 +Data Delay : 6.215 + +Slack : 3.258 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.434 +Data Delay : 6.208 + +Slack : 3.269 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.414 +Data Delay : 6.215 + +Slack : 3.278 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.099 +Data Delay : 6.523 + +Slack : 3.286 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.414 +Data Delay : 6.198 + +Slack : 3.293 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.414 +Data Delay : 6.191 + +Slack : 3.301 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 6.501 + +Slack : 3.332 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.148 + +Slack : 3.347 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.133 + +Slack : 3.391 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.089 + +Slack : 3.393 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.087 + +Slack : 3.406 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.074 + +Slack : 3.408 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 6.072 + +Slack : 3.410 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 6.048 + +Slack : 3.450 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.033 + +Slack : 3.474 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.440 +Data Delay : 5.986 + +Slack : 3.476 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 6.007 + +Slack : 3.490 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.968 + +Slack : 3.493 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 5.990 + +Slack : 3.500 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 5.980 + +Slack : 3.500 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.415 +Data Delay : 5.983 + +Slack : 3.517 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 5.963 + +Slack : 3.524 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 5.956 + +Slack : 3.534 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 6.285 + +Slack : 3.552 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.437 +Data Delay : 5.911 + +Slack : 3.555 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 6.261 + +Slack : 3.568 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 6.249 + +Slack : 3.583 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.899 + +Slack : 3.583 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.899 + +Slack : 3.596 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.417 +Data Delay : 5.885 + +Slack : 3.600 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.882 + +Slack : 3.600 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.882 + +Slack : 3.606 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 6.212 + +Slack : 3.606 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 6.212 + +Slack : 3.607 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.875 + +Slack : 3.607 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.875 + +Slack : 3.676 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.099 +Data Delay : 6.125 + +Slack : 3.699 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 6.103 + +Slack : 3.740 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 6.081 + +Slack : 3.752 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.417 +Data Delay : 5.729 + +Slack : 3.757 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 6.060 + +Slack : 3.758 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.416 +Data Delay : 5.724 + +Slack : 3.761 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.697 + +Slack : 3.774 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.434 +Data Delay : 5.692 + +Slack : 3.778 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.680 + +Slack : 3.778 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 6.043 + +Slack : 3.778 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 6.043 + +Slack : 3.785 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.673 + +Slack : 3.788 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 6.033 + +Slack : 3.792 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.666 + +Slack : 3.803 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.435 +Data Delay : 5.662 + +Slack : 3.816 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.440 +Data Delay : 5.644 + +Slack : 3.832 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.626 + +Slack : 3.833 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.434 +Data Delay : 5.633 + +Slack : 3.840 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.097 +Data Delay : 5.963 + +Slack : 3.841 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.978 + +Slack : 3.843 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.978 + +Slack : 3.865 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 5.615 + +Slack : 3.868 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.414 +Data Delay : 5.616 + +Slack : 3.870 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.096 +Data Delay : 5.934 + +Slack : 3.875 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.440 +Data Delay : 5.585 + +Slack : 3.877 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.440 +Data Delay : 5.583 + +Slack : 3.880 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.418 +Data Delay : 5.600 + +Slack : 3.891 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.567 + +Slack : 3.892 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.397 +Data Delay : 5.706 + +Slack : 3.893 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.442 +Data Delay : 5.565 + +Slack : 3.894 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.437 +Data Delay : 5.569 + +Slack : 3.923 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.896 + +Slack : 3.932 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.887 + +Slack : 3.944 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.437 +Data Delay : 5.519 + +Slack : 3.945 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.876 + +Slack : 3.951 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.437 +Data Delay : 5.512 + +Slack : 3.953 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 5.863 + +Slack : 3.988 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.833 + +Slack : 4.003 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.816 + +Slack : 4.004 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 5.814 + +Slack : 4.004 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 5.814 + +Slack : 4.015 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 5.801 + +Slack : 4.028 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 5.789 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : -0.026 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.652 +Data Delay : 2.917 + +Slack : 0.114 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.650 +Data Delay : 3.055 + +Slack : 0.520 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.738 + +Slack : 0.521 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.658 +Data Delay : 3.470 + +Slack : 0.590 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.651 +Data Delay : 3.532 + +Slack : 1.019 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 3.870 + +Slack : 1.021 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.362 +Data Delay : 3.674 + +Slack : 1.025 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 3.874 + +Slack : 1.035 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 3.890 + +Slack : 1.037 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 3.880 + +Slack : 1.051 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 3.902 + +Slack : 1.051 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 3.902 + +Slack : 1.052 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 3.901 + +Slack : 1.056 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 3.899 + +Slack : 1.056 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 3.904 + +Slack : 1.057 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 3.898 + +Slack : 1.057 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.549 +Data Delay : 3.897 + +Slack : 1.058 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 3.906 + +Slack : 1.063 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 3.907 + +Slack : 1.064 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 3.913 + +Slack : 1.077 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.912 + +Slack : 1.078 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.925 + +Slack : 1.081 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.549 +Data Delay : 3.921 + +Slack : 1.084 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.931 + +Slack : 1.085 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.547 +Data Delay : 3.923 + +Slack : 1.087 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 3.942 + +Slack : 1.091 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 3.939 + +Slack : 1.100 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 3.936 + +Slack : 1.100 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 3.955 + +Slack : 1.105 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.940 + +Slack : 1.105 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.652 +Data Delay : 4.048 + +Slack : 1.107 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.547 +Data Delay : 3.945 + +Slack : 1.107 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 3.951 + +Slack : 1.107 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 3.952 + +Slack : 1.110 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 3.947 + +Slack : 1.113 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.960 + +Slack : 1.116 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.951 + +Slack : 1.117 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.964 + +Slack : 1.117 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 3.953 + +Slack : 1.119 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.363 +Data Delay : 3.773 + +Slack : 1.122 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 3.967 + +Slack : 1.122 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 3.968 + +Slack : 1.124 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 3.972 + +Slack : 1.127 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.962 + +Slack : 1.128 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 3.965 + +Slack : 1.129 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.976 + +Slack : 1.129 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 3.977 + +Slack : 1.130 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.548 +Data Delay : 3.969 + +Slack : 1.136 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.543 +Data Delay : 3.970 + +Slack : 1.139 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.974 + +Slack : 1.141 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.988 + +Slack : 1.143 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.978 + +Slack : 1.144 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.543 +Data Delay : 3.978 + +Slack : 1.145 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.547 +Data Delay : 3.983 + +Slack : 1.146 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.362 +Data Delay : 3.799 + +Slack : 1.148 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.003 + +Slack : 1.150 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 3.997 + +Slack : 1.151 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 3.986 + +Slack : 1.151 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 3.987 + +Slack : 1.151 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.001 + +Slack : 1.153 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.000 + +Slack : 1.153 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 3.989 + +Slack : 1.153 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 3.989 + +Slack : 1.154 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 3.991 + +Slack : 1.156 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.005 + +Slack : 1.157 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.543 +Data Delay : 3.991 + +Slack : 1.159 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.003 + +Slack : 1.161 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.360 +Data Delay : 3.812 + +Slack : 1.162 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.355 +Data Delay : 3.808 + +Slack : 1.164 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 4.000 + +Slack : 1.164 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.011 + +Slack : 1.165 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.014 + +Slack : 1.166 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.011 + +Slack : 1.170 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.015 + +Slack : 1.171 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.018 + +Slack : 1.171 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.547 +Data Delay : 4.009 + +Slack : 1.171 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.015 + +Slack : 1.173 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.565 +Data Delay : 4.029 + +Slack : 1.176 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.545 +Data Delay : 4.012 + +Slack : 1.177 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.358 +Data Delay : 3.826 + +Slack : 1.177 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 4.014 + +Slack : 1.178 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.030 + +Slack : 1.180 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 4.017 + +Slack : 1.180 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.638 +Data Delay : 4.109 + +Slack : 1.182 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 4.033 + +Slack : 1.184 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.543 +Data Delay : 4.018 + +Slack : 1.186 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 4.023 + +Slack : 1.189 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.036 + +Slack : 1.190 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 4.025 + +Slack : 1.193 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 4.028 + +Slack : 1.193 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.544 +Data Delay : 4.028 + +Slack : 1.193 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.543 +Data Delay : 4.027 + +Slack : 1.193 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.038 + +Slack : 1.194 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.043 + +Slack : 1.195 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.547 +Data Delay : 4.033 + +Slack : 1.196 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.037 + +Slack : 1.198 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.045 + +Slack : 1.199 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.047 + +Slack : 1.200 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.565 +Data Delay : 4.056 + +Slack : 1.201 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.546 +Data Delay : 4.038 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.342 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vga_vc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.546 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 0.767 + +Slack : 0.547 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.782 + +Slack : 0.552 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.772 + +Slack : 0.553 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.773 + +Slack : 0.657 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.876 + +Slack : 0.787 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.008 + +Slack : 0.826 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.046 + +Slack : 0.859 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.084 + +Slack : 0.866 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.086 + +Slack : 0.873 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.108 + +Slack : 0.968 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.194 + +Slack : 0.986 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.066 +Data Delay : 1.209 + +Slack : 0.998 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.224 + +Slack : 1.070 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.291 + +Slack : 1.087 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.308 + +Slack : 1.088 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 0.989 + +Slack : 1.088 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 0.989 + +Slack : 1.100 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.321 + +Slack : 1.115 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 1.016 + +Slack : 1.133 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.353 + +Slack : 1.142 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.284 +Data Delay : 1.015 + +Slack : 1.142 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.367 + +Slack : 1.191 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 1.060 + +Slack : 1.193 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 1.062 + +Slack : 1.202 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 1.426 + +Slack : 1.215 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.440 + +Slack : 1.215 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.802 + +Slack : 1.216 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.441 + +Slack : 1.229 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.449 + +Slack : 1.231 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 1.132 + +Slack : 1.234 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.459 + +Slack : 1.242 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.829 + +Slack : 1.249 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.475 + +Slack : 1.249 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.475 + +Slack : 1.253 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 1.154 + +Slack : 1.257 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 1.158 + +Slack : 1.257 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.483 + +Slack : 1.267 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.284 +Data Delay : 1.140 + +Slack : 1.269 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.495 + +Slack : 1.271 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.497 + +Slack : 1.276 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.284 +Data Delay : 1.149 + +Slack : 1.276 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.502 + +Slack : 1.278 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.285 +Data Delay : 1.150 + +Slack : 1.288 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.284 +Data Delay : 1.161 + +Slack : 1.295 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.516 + +Slack : 1.303 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.285 +Data Delay : 1.175 + +Slack : 1.316 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.542 + +Slack : 1.316 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.542 + +Slack : 1.331 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.066 +Data Delay : 1.554 + +Slack : 1.336 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.256 +Data Delay : 1.237 + +Slack : 1.347 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.066 +Data Delay : 1.570 + +Slack : 1.360 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.585 + +Slack : 1.369 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.595 + +Slack : 1.369 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 1.593 + +Slack : 1.371 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.597 + +Slack : 1.379 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.605 + +Slack : 1.381 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.607 + +Slack : 1.381 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.607 + +Slack : 1.391 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.617 + +Slack : 1.398 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.624 + +Slack : 1.400 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.987 + +Slack : 1.400 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.626 + +Slack : 1.402 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.628 + +Slack : 1.404 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.991 + +Slack : 1.408 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.634 + +Slack : 1.423 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.648 + +Slack : 1.472 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 2.059 + +Slack : 1.481 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.707 + +Slack : 1.483 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.708 + +Slack : 1.491 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.717 + +Slack : 1.495 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 1.719 + +Slack : 1.512 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.738 + +Slack : 1.513 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 1.382 + +Slack : 1.515 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 1.384 + +Slack : 1.516 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.066 +Data Delay : 1.739 + +Slack : 1.520 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.066 +Data Delay : 1.743 + +Slack : 1.527 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.285 +Data Delay : 1.399 + +Slack : 1.538 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.758 + +Slack : 1.551 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.772 + +Slack : 1.558 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.784 + +Slack : 1.558 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.784 + +Slack : 1.559 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.785 + +Slack : 1.564 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.784 + +Slack : 1.565 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.785 + +Slack : 1.571 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.797 + +Slack : 1.571 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.797 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.342 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.577 + +Slack : 0.345 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.580 + +Slack : 0.576 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.811 + +Slack : 1.324 +From Node : SW[2] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : -0.017 +Clock Skew : 0.636 +Data Delay : 1.190 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.343 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.577 + +Slack : 0.343 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.577 + +Slack : 0.344 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.577 + +Slack : 0.346 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.580 + +Slack : 0.346 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.580 + +Slack : 0.346 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.580 + +Slack : 0.347 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.580 + +Slack : 0.357 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.591 + +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.592 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.359 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.593 + +Slack : 0.359 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.593 + +Slack : 0.359 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.593 + +Slack : 0.359 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.593 + +Slack : 0.360 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.594 + +Slack : 0.360 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.594 + +Slack : 0.360 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.580 + +Slack : 0.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.580 + +Slack : 0.362 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.597 + +Slack : 0.373 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.593 + +Slack : 0.374 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.594 + +Slack : 0.378 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.611 + +Slack : 0.394 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.628 + +Slack : 0.407 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.626 + +Slack : 0.478 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.698 + +Slack : 0.534 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.753 + +Slack : 0.535 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.769 + +Slack : 0.536 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.770 + +Slack : 0.538 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.772 + +Slack : 0.538 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.772 + +Slack : 0.540 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.774 + +Slack : 0.543 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.778 + +Slack : 0.543 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.778 + +Slack : 0.545 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.780 + +Slack : 0.553 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.757 + +Slack : 0.556 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.790 + +Slack : 0.559 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.779 + +Slack : 0.562 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.782 + +Slack : 0.571 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.805 + +Slack : 0.571 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.790 + +Slack : 0.573 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.793 + +Slack : 0.574 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.794 + +Slack : 0.576 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.810 + +Slack : 0.582 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.802 + +Slack : 0.589 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.823 + +Slack : 0.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.412 +Data Delay : 1.161 + +Slack : 0.594 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.828 + +Slack : 0.594 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.813 + +Slack : 0.598 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.832 + +Slack : 0.605 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.825 + +Slack : 0.607 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.826 + +Slack : 0.609 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.828 + +Slack : 0.618 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.852 + +Slack : 0.618 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.837 + +Slack : 0.623 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.857 + +Slack : 0.648 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.868 + +Slack : 0.672 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.875 + +Slack : 0.686 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.120 +Data Delay : 0.963 + +Slack : 0.688 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.907 + +Slack : 0.694 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.897 + +Slack : 0.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.936 + +Slack : 0.727 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.947 + +Slack : 0.736 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.955 + +Slack : 0.755 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.443 +Data Delay : 1.355 + +Slack : 0.764 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.983 + +Slack : 0.777 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.412 +Data Delay : 1.346 + +Slack : 0.803 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.049 +Data Delay : 1.009 + +Slack : 0.818 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.053 + +Slack : 0.819 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.054 + +Slack : 0.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.052 + +Slack : 0.831 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.066 + +Slack : 0.833 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.068 + +Slack : 0.834 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.054 + +Slack : 0.834 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.054 + +Slack : 0.836 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.070 + +Slack : 0.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.058 + +Slack : 0.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.058 + +Slack : 0.838 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.072 + +Slack : 0.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.072 + +Slack : 0.839 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.060 + +Slack : 0.841 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.075 + +Slack : 0.844 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.065 + +Slack : 0.845 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.066 + +Slack : 0.845 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.079 + +Slack : 0.846 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.066 + +Slack : 0.848 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.068 + +Slack : 0.849 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.850 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.070 + +Slack : 0.855 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.074 + +Slack : 0.863 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.097 + +Slack : 0.865 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.099 + +Slack : 0.881 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.100 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.358 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.359 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.359 +From Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.361 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.580 + +Slack : 0.361 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.580 + +Slack : 0.380 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.598 + +Slack : 0.420 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.638 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.720 + +Slack : 0.557 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.776 + +Slack : 0.558 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.776 + +Slack : 0.558 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.777 + +Slack : 0.559 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.777 + +Slack : 0.559 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.777 + +Slack : 0.560 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.778 + +Slack : 0.560 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.779 + +Slack : 0.561 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.562 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.780 + +Slack : 0.562 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.780 + +Slack : 0.563 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.781 + +Slack : 0.563 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.781 + +Slack : 0.569 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.788 + +Slack : 0.570 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.789 + +Slack : 0.570 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.789 + +Slack : 0.571 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.790 + +Slack : 0.572 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.572 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.572 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.574 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.793 + +Slack : 0.574 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.793 + +Slack : 0.580 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.798 + +Slack : 0.687 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.905 + +Slack : 0.832 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.051 + +Slack : 0.833 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.052 + +Slack : 0.833 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.051 + +Slack : 0.833 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.051 + +Slack : 0.834 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.052 + +Slack : 0.836 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.054 + +Slack : 0.838 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.056 + +Slack : 0.844 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.063 + +Slack : 0.845 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.064 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.065 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.065 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.065 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.066 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.067 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.851 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.069 + +Slack : 0.852 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.070 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.078 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.078 + +Slack : 0.860 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.079 + +Slack : 0.861 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.080 + +Slack : 0.861 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.080 + +Slack : 0.861 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.080 + +Slack : 0.861 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.080 + +Slack : 0.863 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.082 + +Slack : 0.863 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.082 + +Slack : 0.891 +From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.109 + +Slack : 0.942 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.161 + +Slack : 0.943 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.161 + +Slack : 0.943 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.161 + +Slack : 0.944 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.162 + +Slack : 0.944 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.163 + +Slack : 0.945 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.163 + +Slack : 0.945 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.163 + +Slack : 0.946 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.164 + +Slack : 0.946 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.164 + +Slack : 0.947 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.166 + +Slack : 0.955 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.174 + +Slack : 0.956 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.175 + +Slack : 0.956 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.175 + +Slack : 0.956 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.175 + +Slack : 0.957 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.176 + +Slack : 0.958 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.177 + +Slack : 0.958 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.177 + +Slack : 0.959 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.177 + +Slack : 0.960 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.178 + +Slack : 0.961 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.179 + +Slack : 0.961 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.179 + +Slack : 0.962 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.180 + +Slack : 0.963 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.181 + +Slack : 0.964 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.182 + +Slack : 0.970 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.189 + +Slack : 0.971 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.190 + +Slack : 0.971 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.190 + +Slack : 0.972 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.191 + +Slack : 0.973 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.192 + +Slack : 0.973 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.192 + +Slack : 0.973 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.192 + +Slack : 0.973 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.192 + +Slack : 0.975 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.194 + +Slack : 0.975 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.194 + +Slack : 0.990 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.209 + +Slack : 0.997 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.215 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -6.225 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.164 +Data Delay : 4.343 + +Slack : -6.223 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 4.344 + +Slack : -6.223 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 4.342 + +Slack : -6.223 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.164 +Data Delay : 4.341 + +Slack : -6.223 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.165 +Data Delay : 4.340 + +Slack : -5.985 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.193 +Data Delay : 4.076 + +Slack : -5.971 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.195 +Data Delay : 4.060 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.142 +Data Delay : 3.944 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.924 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.924 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.924 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.924 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.924 + +Slack : -5.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.155 +Data Delay : 3.930 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.155 +Data Delay : 3.930 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.155 +Data Delay : 3.930 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.924 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.922 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.155 +Data Delay : 3.930 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.155 +Data Delay : 3.930 + +Slack : -5.706 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.155 +Data Delay : 3.930 + +Slack : -5.397 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.149 +Data Delay : 3.922 + +Slack : -5.384 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.167 +Data Delay : 3.930 + +Slack : -5.380 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.177 +Data Delay : 3.936 + +Slack : -5.372 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.173 +Data Delay : 3.924 + +Slack : -5.372 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.173 +Data Delay : 3.924 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.197 +Data Delay : 3.932 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.919 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.919 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.919 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.931 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.923 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.923 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.923 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.923 + +Slack : -5.356 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.923 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.185 +Data Delay : 3.919 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.185 +Data Delay : 3.919 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.184 +Data Delay : 3.918 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.924 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.924 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.924 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.924 + +Slack : -5.355 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.924 + +Slack : -5.342 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.203 +Data Delay : 3.924 + +Slack : -5.342 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.203 +Data Delay : 3.924 + +Slack : -5.342 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.203 +Data Delay : 3.924 + +Slack : -5.342 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.203 +Data Delay : 3.924 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.622 +Data Delay : 3.559 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.622 +Data Delay : 3.559 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.622 +Data Delay : 3.559 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.622 +Data Delay : 3.559 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.557 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.557 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.557 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.557 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.557 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.553 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.553 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.603 +Data Delay : 3.552 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.559 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.559 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.559 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.559 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.559 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.616 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.712 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.568 + +Slack : 3.727 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.591 +Data Delay : 3.559 + +Slack : 3.727 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.591 +Data Delay : 3.559 + +Slack : 3.736 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.596 +Data Delay : 3.573 + +Slack : 3.741 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.585 +Data Delay : 3.567 + +Slack : 3.746 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.567 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.559 + +Slack : 4.075 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.557 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.076 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.580 + +Slack : 4.077 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.249 +Data Delay : 3.567 + +Slack : 4.077 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.249 +Data Delay : 3.567 + +Slack : 4.077 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.249 +Data Delay : 3.567 + +Slack : 4.077 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.249 +Data Delay : 3.567 + +Slack : 4.077 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.249 +Data Delay : 3.567 + +Slack : 4.077 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.249 +Data Delay : 3.567 + +Slack : 4.294 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.190 +Data Delay : 3.669 + +Slack : 4.309 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.192 +Data Delay : 3.686 + +Slack : 4.520 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.225 +Data Delay : 3.926 + +Slack : 4.520 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.223 +Data Delay : 3.924 + +Slack : 4.520 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 3.923 + +Slack : 4.520 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 3.922 + +Slack : 4.522 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 3.925 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.755 +Actual Width : 4.971 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.755 +Actual Width : 4.971 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.755 +Actual Width : 4.971 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.755 +Actual Width : 4.971 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.755 +Actual Width : 4.971 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[0] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[2] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[3] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[6] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[7] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[0] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[1] + +Slack : 4.844 +Actual Width : 5.028 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.844 +Actual Width : 5.028 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.844 +Actual Width : 5.028 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.844 +Actual Width : 5.028 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.844 +Actual Width : 5.028 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 19.601 +Actual Width : 19.831 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.601 +Actual Width : 19.831 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 + +Slack : 19.601 +Actual Width : 19.831 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + +Slack : 19.601 +Actual Width : 19.831 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 19.601 +Actual Width : 19.831 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 19.601 +Actual Width : 19.831 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[0] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[1] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[2] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[3] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[4] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[5] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[6] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[7] + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.604 +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 + +Slack : 20.604 +Actual Width : 20.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.608 +Actual Width : 20.824 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.608 +Actual Width : 20.824 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.608 +Actual Width : 20.824 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] + +Slack : 20.647 +Actual Width : 20.863 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] + +Slack : 20.647 +Actual Width : 20.863 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] + +Slack : 20.647 +Actual Width : 20.863 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] + +Slack : 20.647 +Actual Width : 20.863 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] + +Slack : 20.647 +Actual Width : 20.863 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] + +Slack : 20.660 +Actual Width : 20.876 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] + +Slack : 20.686 +Actual Width : 20.870 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.686 +Actual Width : 20.870 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.686 +Actual Width : 20.870 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.686 +Actual Width : 20.870 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.689 +Actual Width : 20.873 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 35.503 +Actual Width : 35.719 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.503 +Actual Width : 35.719 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] + +Slack : 35.584 +Actual Width : 35.768 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.584 +Actual Width : 35.768 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] + +Slack : 35.726 +Actual Width : 35.726 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] + +Slack : 35.726 +Actual Width : 35.726 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk + +Slack : 35.743 +Actual Width : 35.743 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.743 +Actual Width : 35.743 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.746 +Actual Width : 35.746 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.746 +Actual Width : 35.746 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.762 +Actual Width : 35.762 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] + +Slack : 35.762 +Actual Width : 35.762 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk + +Slack : 69.489 +Actual Width : 71.489 +Required Width : 2.000 +Type : Min Period +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 69.489 +Actual Width : 71.489 +Required Width : 2.000 +Type : Min Period +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Setup Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.512 +Fall : 1.781 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 3.245 +Fall : 3.515 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : 1.011 +Fall : 1.277 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : 1.011 +Fall : 1.277 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : 1.263 +Fall : 1.501 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.820 +Fall : 3.101 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Hold Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.077 +Fall : -1.324 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -2.311 +Fall : -2.564 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : -0.397 +Fall : -0.660 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : -0.397 +Fall : -0.660 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : -0.644 +Fall : -0.873 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : -0.977 +Fall : -1.214 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 10.793 +Fall : 10.789 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 9.931 +Fall : 9.913 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 9.959 +Fall : 10.101 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 9.579 +Fall : 9.547 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 10.004 +Fall : 10.080 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 10.661 +Fall : 10.706 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 10.516 +Fall : 10.623 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 10.720 +Fall : 10.719 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 10.793 +Fall : 10.789 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 10.560 +Fall : 10.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 10.028 +Fall : 10.042 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 9.968 +Fall : 10.109 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 9.866 +Fall : 9.872 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 9.785 +Fall : 9.851 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 10.384 +Fall : 10.396 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 10.128 +Fall : 10.166 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 10.560 +Fall : 10.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 10.152 +Fall : 10.092 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 3.321 +Fall : 3.234 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 3.296 +Fall : 3.214 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 3.416 +Fall : 3.331 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.419 +Fall : 3.334 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 3.294 +Fall : 3.212 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.417 +Fall : 3.332 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.411 +Fall : 6.384 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.780 +Fall : 5.845 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.176 +Fall : 6.240 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.956 +Fall : 5.950 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 6.111 +Fall : 6.220 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.151 +Fall : 6.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.145 +Fall : 6.180 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.074 +Fall : 6.119 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.150 +Fall : 6.186 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 6.401 +Fall : 6.369 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 6.411 +Fall : 6.384 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 5.985 +Fall : 5.938 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 5.985 +Fall : 5.938 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 6.305 +Fall : 6.309 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 5.992 +Fall : 5.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 5.992 +Fall : 5.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 6.005 +Fall : 5.971 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.417 +Fall : 3.332 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.423 +Fall : 3.338 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.576 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.505 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 8.268 +Fall : 8.331 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 8.040 +Fall : 8.140 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.800 +Fall : 7.856 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 7.312 +Fall : 7.306 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.984 +Fall : 8.035 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 7.683 +Fall : 7.767 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 8.090 +Fall : 8.178 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 8.141 +Fall : 8.187 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 8.268 +Fall : 8.331 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 8.137 +Fall : 8.269 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 8.137 +Fall : 8.269 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.809 +Fall : 7.864 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 7.599 +Fall : 7.631 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.765 +Fall : 7.806 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.406 +Fall : 7.457 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 7.702 +Fall : 7.721 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.981 +Fall : 8.036 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 7.627 +Fall : 7.634 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 8.089 +Fall : 7.827 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 8.089 +Fall : 7.827 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 6.289 +Fall : 6.217 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 6.465 +Fall : 6.464 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 6.666 +Fall : 6.710 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 6.731 +Fall : 6.659 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 6.731 +Fall : 6.656 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 6.730 +Fall : 6.659 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 6.646 +Fall : 6.554 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 6.632 +Fall : 6.539 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 2.863 +Fall : 2.776 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 6.755 +Fall : 6.797 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 6.714 +Fall : 6.797 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 6.755 +Fall : 6.698 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 6.322 +Fall : 6.341 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 6.698 +Fall : 6.778 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 2.861 +Fall : 2.774 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 2.859 +Fall : 2.772 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 2.858 +Fall : 2.771 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 2.862 +Fall : 2.775 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 4.881 +Fall : 4.517 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 2.860 +Fall : 2.773 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 2.951 +Fall : 2.866 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.953 +Fall : 2.868 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 8.068 +Fall : 8.062 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 8.089 +Fall : 8.099 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 8.228 +Fall : 8.251 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 8.101 +Fall : 8.062 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 8.451 +Fall : 8.514 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 8.068 +Fall : 8.141 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 8.897 +Fall : 9.033 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 8.748 +Fall : 8.814 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 9.005 +Fall : 8.991 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.797 +Fall : 7.838 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 8.183 +Fall : 8.224 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 8.236 +Fall : 8.257 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 8.380 +Fall : 8.378 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 8.245 +Fall : 8.300 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.797 +Fall : 7.838 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 8.561 +Fall : 8.633 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 8.591 +Fall : 8.667 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 8.392 +Fall : 8.326 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 2.874 +Fall : 2.792 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.004 +Fall : 2.919 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.900 +Fall : 2.813 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.900 +Fall : 2.813 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 2.899 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.901 +Fall : 2.814 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 2.898 +Fall : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 2.899 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 2.876 +Fall : 2.794 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.004 +Fall : 2.919 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 2.996 +Fall : 2.911 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 2.998 +Fall : 2.913 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 2.874 +Fall : 2.792 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 2.898 +Fall : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 2.898 +Fall : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 2.899 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 2.996 +Fall : 2.911 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.779 +Fall : 4.767 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.192 +Fall : 5.251 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.572 +Fall : 5.630 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.361 +Fall : 5.349 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.506 +Fall : 5.608 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.551 +Fall : 5.625 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.543 +Fall : 5.574 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.416 +Fall : 5.449 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.547 +Fall : 5.576 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 5.179 +Fall : 5.181 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 5.188 +Fall : 5.195 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 4.779 +Fall : 4.767 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 4.779 +Fall : 4.767 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 5.086 +Fall : 5.123 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 4.786 +Fall : 4.772 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 4.786 +Fall : 4.772 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 4.801 +Fall : 4.801 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 2.996 +Fall : 2.911 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.003 +Fall : 2.918 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.164 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.093 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.901 +Fall : 5.952 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.979 +Fall : 6.964 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.644 +Fall : 6.692 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 6.371 +Fall : 6.434 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.901 +Fall : 5.952 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.705 +Fall : 6.771 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.846 +Fall : 6.936 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.290 +Fall : 6.333 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.894 +Fall : 6.938 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 5.695 +Fall : 5.738 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.073 +Fall : 7.089 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 6.652 +Fall : 6.698 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 6.650 +Fall : 6.750 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 5.695 +Fall : 5.738 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 6.434 +Fall : 6.468 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 6.510 +Fall : 6.536 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 6.133 +Fall : 6.186 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 6.281 +Fall : 6.273 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 3.926 +Fall : 3.804 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 5.792 +Fall : 5.405 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 3.926 +Fall : 3.804 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 4.153 +Fall : 4.026 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 4.346 +Fall : 4.263 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 4.034 +Fall : 3.919 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 4.129 +Fall : 4.032 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 4.129 +Fall : 4.035 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 4.048 +Fall : 3.934 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 4.034 +Fall : 3.919 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 2.461 +Fall : 2.374 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 3.998 +Fall : 3.893 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 4.374 +Fall : 4.331 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 4.524 +Fall : 4.485 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 3.998 +Fall : 3.893 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 4.359 +Fall : 4.312 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 2.460 +Fall : 2.373 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 2.457 +Fall : 2.370 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 2.456 +Fall : 2.369 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 2.460 +Fall : 2.373 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 4.479 +Fall : 4.115 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 2.458 +Fall : 2.371 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 2.549 +Fall : 2.464 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.551 +Fall : 2.466 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 4.628 +RF : +FR : +FF : 4.693 + +Input Port : SW[2] +Output Port : LED[2] +RR : 4.044 +RF : +FR : +FF : 4.195 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.977 +RF : +FR : +FF : 7.192 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.783 +RF : +FR : +FF : 7.007 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 4.317 +RF : +FR : +FF : 4.516 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 4.491 +RF : +FR : +FF : 4.559 + +Input Port : SW[2] +Output Port : LED[2] +RR : 3.930 +RF : +FR : +FF : 4.081 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.742 +RF : +FR : +FF : 6.952 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.553 +RF : +FR : +FF : 6.773 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 4.185 +RF : +FR : +FF : 4.382 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.940 +Fall : 5.807 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.085 +Fall : 5.963 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.085 +Fall : 5.963 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.943 +Fall : 5.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 6.155 +Fall : 6.035 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.974 +Fall : 5.852 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.968 +Fall : 5.846 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.968 +Fall : 5.846 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.940 +Fall : 5.807 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.744 +Fall : 4.611 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.911 +Fall : 4.789 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.911 +Fall : 4.789 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.747 +Fall : 4.614 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.974 +Fall : 4.854 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.804 +Fall : 4.682 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.798 +Fall : 4.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.798 +Fall : 4.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.744 +Fall : 4.611 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.939 +1 to Hi-Z : 6.072 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 6.066 +1 to Hi-Z : 6.188 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 6.066 +1 to Hi-Z : 6.188 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.942 +1 to Hi-Z : 6.075 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 6.198 +1 to Hi-Z : 6.318 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.966 +1 to Hi-Z : 6.088 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.953 +1 to Hi-Z : 6.075 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.953 +1 to Hi-Z : 6.075 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.939 +1 to Hi-Z : 6.072 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.708 +1 to Hi-Z : 4.841 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.859 +1 to Hi-Z : 4.981 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.859 +1 to Hi-Z : 4.981 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.711 +1 to Hi-Z : 4.844 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.981 +1 to Hi-Z : 5.101 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.762 +1 to Hi-Z : 4.884 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.750 +1 to Hi-Z : 4.872 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.750 +1 to Hi-Z : 4.872 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.708 +1 to Hi-Z : 4.841 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++--------------------------------------------------------------------------------+ +Fmax : 50.55 MHz +Restricted Fmax : 50.55 MHz +Clock Name : CLOCK_50 +Note : + +Fmax : 144.18 MHz +Restricted Fmax : 144.18 MHz +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Note : + +Fmax : 148.41 MHz +Restricted Fmax : 148.41 MHz +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Note : + +Fmax : 219.83 MHz +Restricted Fmax : 219.83 MHz +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Note : + +Fmax : 1052.63 MHz +Restricted Fmax : 500.0 MHz +Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Note : limit due to minimum period restriction (tmin) ++--------------------------------------------------------------------------------+ + +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++--------------------------------------------------------------------------------+ +Clock : CLOCK_50 +Slack : -17.443 +End Point TNS : -768.889 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -6.729 +End Point TNS : -260.267 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -4.426 +End Point TNS : -37.694 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : -2.785 +End Point TNS : -2.785 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 3.262 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++--------------------------------------------------------------------------------+ +Clock : CLOCK_50 +Slack : 0.059 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.298 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 0.298 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 0.298 +End Point TNS : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.312 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery Summary ; ++--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -5.745 +End Point TNS : -420.318 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal Summary ; ++--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 3.369 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++--------------------------------------------------------------------------------+ +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.746 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 9.487 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 19.597 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 20.589 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 35.491 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : -17.443 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.253 + +Slack : -17.356 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.166 + +Slack : -17.341 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.894 + +Slack : -17.318 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.128 + +Slack : -17.269 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.079 + +Slack : -17.266 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.824 + +Slack : -17.250 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.816 + +Slack : -17.244 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.054 + +Slack : -17.237 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.790 + +Slack : -17.231 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.041 + +Slack : -17.215 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.025 + +Slack : -17.214 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.764 + +Slack : -17.203 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.525 +Data Delay : 6.752 + +Slack : -17.187 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.997 + +Slack : -17.182 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.975 + +Slack : -17.179 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.730 + +Slack : -17.166 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.722 + +Slack : -17.165 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.975 + +Slack : -17.163 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.721 + +Slack : -17.163 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.721 + +Slack : -17.151 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.944 + +Slack : -17.146 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.712 + +Slack : -17.141 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.951 + +Slack : -17.137 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.695 + +Slack : -17.131 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.681 + +Slack : -17.127 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.937 + +Slack : -17.111 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.661 + +Slack : -17.098 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.890 + +Slack : -17.059 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.617 + +Slack : -17.057 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.610 + +Slack : -17.053 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.611 + +Slack : -17.052 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.604 + +Slack : -17.033 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.591 + +Slack : -17.023 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.816 + +Slack : -17.014 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.565 + +Slack : -17.014 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.806 + +Slack : -16.988 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.538 + +Slack : -16.985 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.795 + +Slack : -16.969 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.779 + +Slack : -16.966 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.525 +Data Delay : 6.515 + +Slack : -16.964 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.286 +Data Delay : 6.752 + +Slack : -16.952 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.505 + +Slack : -16.950 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.760 + +Slack : -16.932 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.519 +Data Delay : 6.487 + +Slack : -16.930 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.723 + +Slack : -16.930 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.723 + +Slack : -16.929 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.485 + +Slack : -16.916 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.709 + +Slack : -16.911 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.462 + +Slack : -16.909 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.459 + +Slack : -16.892 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.702 + +Slack : -16.887 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.447 + +Slack : -16.877 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.669 + +Slack : -16.867 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.677 + +Slack : -16.866 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.676 + +Slack : -16.855 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.647 + +Slack : -16.851 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.401 + +Slack : -16.850 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.660 + +Slack : -16.850 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.642 + +Slack : -16.849 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.642 + +Slack : -16.829 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.519 +Data Delay : 6.384 + +Slack : -16.821 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.286 +Data Delay : 6.609 + +Slack : -16.820 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.373 + +Slack : -16.813 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.623 + +Slack : -16.812 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.371 + +Slack : -16.809 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.286 +Data Delay : 6.597 + +Slack : -16.808 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.361 + +Slack : -16.805 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.597 + +Slack : -16.805 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.615 + +Slack : -16.799 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 6.364 + +Slack : -16.796 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.606 + +Slack : -16.789 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.599 + +Slack : -16.781 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.574 + +Slack : -16.780 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.572 + +Slack : -16.765 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.327 + +Slack : -16.759 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.551 + +Slack : -16.744 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.304 + +Slack : -16.738 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.296 + +Slack : -16.726 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.536 + +Slack : -16.722 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.280 + +Slack : -16.715 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.268 + +Slack : -16.713 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.277 + +Slack : -16.700 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.252 + +Slack : -16.697 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.261 + +Slack : -16.694 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.252 + +Slack : -16.687 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.478 + +Slack : -16.672 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.232 + +Slack : -16.671 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.229 + +Slack : -16.666 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.476 + +Slack : -16.662 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.472 + +Slack : -16.655 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.213 + +Slack : -16.645 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.203 + +Slack : -16.616 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 6.181 + +Slack : -16.598 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.286 +Data Delay : 6.386 + +Slack : -16.598 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 6.163 + +Slack : -16.583 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.142 + +Slack : -16.576 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.386 + +Slack : -16.567 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.377 + +Slack : -16.565 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.126 + +Slack : -16.563 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.124 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : -6.729 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.021 +Data Delay : 4.808 + +Slack : -6.702 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.793 + +Slack : -6.669 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.746 +Data Delay : 5.023 + +Slack : -6.543 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.005 +Data Delay : 4.638 + +Slack : -6.538 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.634 + +Slack : -6.520 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.611 + +Slack : -6.517 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.608 + +Slack : -6.505 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.595 + +Slack : -6.488 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.575 + +Slack : -6.487 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.571 + +Slack : -6.475 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.566 + +Slack : -6.461 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 4.560 + +Slack : -6.460 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.556 + +Slack : -6.441 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 +Data Delay : 4.526 + +Slack : -6.428 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.738 +Data Delay : 4.790 + +Slack : -6.427 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.741 +Data Delay : 4.786 + +Slack : -6.414 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.511 + +Slack : -6.381 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.740 +Data Delay : 4.741 + +Slack : -6.366 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.007 +Data Delay : 4.459 + +Slack : -6.352 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.436 + +Slack : -6.344 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.021 +Data Delay : 4.423 + +Slack : -6.322 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.412 + +Slack : -6.291 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 4.389 + +Slack : -6.284 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.384 + +Slack : -6.273 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.980 +Data Delay : 4.393 + +Slack : -6.259 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 4.383 + +Slack : -6.246 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.995 +Data Delay : 4.351 + +Slack : -6.238 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.338 + +Slack : -6.230 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.975 +Data Delay : 4.355 + +Slack : -6.230 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 4.337 + +Slack : -6.229 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.983 +Data Delay : 4.346 + +Slack : -6.225 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.992 +Data Delay : 4.333 + +Slack : -6.220 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.971 +Data Delay : 4.349 + +Slack : -6.216 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.356 + +Slack : -6.215 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.028 +Data Delay : 4.287 + +Slack : -6.213 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.353 + +Slack : -6.201 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.961 +Data Delay : 4.340 + +Slack : -6.186 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.996 +Data Delay : 4.290 + +Slack : -6.171 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.311 + +Slack : -6.131 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 4.258 + +Slack : -6.109 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.007 +Data Delay : 4.202 + +Slack : -6.101 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.201 + +Slack : -6.098 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.198 + +Slack : -6.093 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.189 + +Slack : -6.086 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 4.185 + +Slack : -6.072 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.975 +Data Delay : 4.197 + +Slack : -6.071 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.989 +Data Delay : 4.182 + +Slack : -6.070 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 4.200 + +Slack : -6.067 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 4.193 + +Slack : -6.064 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.160 + +Slack : -6.063 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 4.169 + +Slack : -6.062 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 4.168 + +Slack : -6.056 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.156 + +Slack : -6.055 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.146 + +Slack : -6.050 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 4.142 + +Slack : -6.043 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.969 +Data Delay : 4.174 + +Slack : -6.000 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.977 +Data Delay : 4.123 + +Slack : -5.999 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 4.127 + +Slack : -5.989 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.967 +Data Delay : 4.122 + +Slack : -5.988 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 4.118 + +Slack : -5.987 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.074 + +Slack : -5.974 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.978 +Data Delay : 4.096 + +Slack : -5.972 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.977 +Data Delay : 4.095 + +Slack : -5.964 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 4.052 + +Slack : -5.962 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.975 +Data Delay : 4.087 + +Slack : -5.961 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.990 +Data Delay : 4.071 + +Slack : -5.951 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.011 +Data Delay : 4.040 + +Slack : -5.943 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.962 +Data Delay : 4.081 + +Slack : -5.942 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.969 +Data Delay : 4.073 + +Slack : -5.938 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.990 +Data Delay : 4.048 + +Slack : -5.935 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.967 +Data Delay : 4.068 + +Slack : -5.934 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.069 + +Slack : -5.931 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 4.065 + +Slack : -5.926 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.061 + +Slack : -5.915 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 4.039 + +Slack : -5.913 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.991 +Data Delay : 4.022 + +Slack : -5.912 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 4.019 + +Slack : -5.904 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.020 + +Slack : -5.893 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.021 +Data Delay : 3.972 + +Slack : -5.889 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.024 + +Slack : -5.881 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.983 +Data Delay : 3.998 + +Slack : -5.867 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 3.985 + +Slack : -5.820 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 3.948 + +Slack : -5.817 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 3.916 + +Slack : -5.814 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.999 +Data Delay : 3.915 + +Slack : -5.813 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 3.943 + +Slack : -5.806 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 3.932 + +Slack : -5.805 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.932 + +Slack : -5.804 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.998 +Data Delay : 3.906 + +Slack : -5.803 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.006 +Data Delay : 3.897 + +Slack : -5.796 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 3.892 + +Slack : -5.790 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.023 +Data Delay : 3.867 + +Slack : -5.787 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 3.887 + +Slack : -5.786 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.969 +Data Delay : 3.917 + +Slack : -5.771 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.989 +Data Delay : 3.882 + +Slack : -5.770 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 3.904 + +Slack : -5.767 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.022 +Data Delay : 3.845 + +Slack : -5.761 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.888 + +Slack : -5.753 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.021 +Data Delay : 3.832 + +Slack : -5.752 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.985 +Data Delay : 3.867 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.426 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.115 +Data Delay : 2.600 + +Slack : -3.973 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.211 +Data Delay : 2.563 + +Slack : -3.973 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.211 +Data Delay : 2.563 + +Slack : -3.794 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.402 + +Slack : -3.794 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.402 + +Slack : -3.794 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.402 + +Slack : -3.794 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.402 + +Slack : -3.794 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.402 + +Slack : -3.385 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.239 +Data Delay : 2.003 + +Slack : -2.967 +From Node : AUD_ADCDAT +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.214 +Data Delay : 1.560 + +Slack : 17.383 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.133 + +Slack : 17.383 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.133 + +Slack : 17.383 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.133 + +Slack : 17.383 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.133 + +Slack : 17.400 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.116 + +Slack : 17.400 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.116 + +Slack : 17.400 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.116 + +Slack : 17.457 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.059 + +Slack : 17.457 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 3.059 + +Slack : 17.491 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.986 + +Slack : 17.491 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.986 + +Slack : 17.491 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.986 + +Slack : 17.491 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.986 + +Slack : 17.522 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.955 + +Slack : 17.522 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.955 + +Slack : 17.522 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.955 + +Slack : 17.540 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 2.976 + +Slack : 17.540 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.330 +Data Delay : 2.976 + +Slack : 17.575 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.902 + +Slack : 17.575 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.902 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.872 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.872 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.872 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.872 + +Slack : 17.636 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.841 + +Slack : 17.636 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.841 + +Slack : 17.636 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.841 + +Slack : 17.640 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.837 + +Slack : 17.640 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.837 + +Slack : 17.689 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.788 + +Slack : 17.689 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.788 + +Slack : 17.702 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.775 + +Slack : 17.702 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.775 + +Slack : 17.702 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.775 + +Slack : 17.702 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.775 + +Slack : 17.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.744 + +Slack : 17.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.744 + +Slack : 17.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.744 + +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.723 + +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.723 + +Slack : 17.786 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.691 + +Slack : 17.786 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.691 + +Slack : 17.851 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.626 + +Slack : 17.851 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.626 + +Slack : 17.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.032 +Data Delay : 2.850 + +Slack : 17.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.032 +Data Delay : 2.850 + +Slack : 17.987 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.014 +Data Delay : 2.845 + +Slack : 17.987 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.014 +Data Delay : 2.845 + +Slack : 17.987 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.014 +Data Delay : 2.845 + +Slack : 17.987 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.014 +Data Delay : 2.845 + +Slack : 17.987 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.014 +Data Delay : 2.845 + +Slack : 18.061 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.071 +Data Delay : 2.714 + +Slack : 18.061 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.071 +Data Delay : 2.714 + +Slack : 18.070 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.407 + +Slack : 18.070 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.407 + +Slack : 18.070 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.407 + +Slack : 18.070 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.407 + +Slack : 18.084 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.709 + +Slack : 18.084 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.709 + +Slack : 18.084 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.709 + +Slack : 18.084 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.709 + +Slack : 18.084 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.709 + +Slack : 18.097 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.331 +Data Delay : 2.418 + +Slack : 18.097 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.331 +Data Delay : 2.418 + +Slack : 18.097 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.331 +Data Delay : 2.418 + +Slack : 18.101 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.376 + +Slack : 18.101 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.376 + +Slack : 18.101 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.376 + +Slack : 18.154 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.323 + +Slack : 18.154 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.323 + +Slack : 18.164 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.313 + +Slack : 18.164 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.313 + +Slack : 18.164 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.313 + +Slack : 18.164 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.313 + +Slack : 18.175 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.071 +Data Delay : 2.600 + +Slack : 18.175 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.071 +Data Delay : 2.600 + +Slack : 18.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.282 + +Slack : 18.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.282 + +Slack : 18.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.282 + +Slack : 18.195 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.282 + +Slack : 18.195 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.282 + +Slack : 18.195 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.282 + +Slack : 18.198 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.358 +Data Delay : 2.200 + +Slack : 18.198 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.595 + +Slack : 18.198 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.595 + +Slack : 18.198 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.595 + +Slack : 18.198 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.595 + +Slack : 18.198 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.595 + +Slack : 18.219 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.258 + +Slack : 18.219 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.258 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : -2.785 +From Node : SW[2] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.423 +Clock Skew : 0.254 +Data Delay : 1.417 + +Slack : 70.539 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.069 +Data Delay : 0.876 + +Slack : 70.832 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.069 +Data Delay : 0.583 + +Slack : 70.832 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.069 +Data Delay : 0.583 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 3.262 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 6.269 + +Slack : 3.437 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 6.092 + +Slack : 3.567 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.964 + +Slack : 3.581 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.385 +Data Delay : 5.939 + +Slack : 3.583 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.948 + +Slack : 3.590 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.941 + +Slack : 3.619 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.384 +Data Delay : 5.902 + +Slack : 3.656 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.371 +Data Delay : 5.876 + +Slack : 3.677 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.851 + +Slack : 3.690 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.838 + +Slack : 3.742 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 5.787 + +Slack : 3.758 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 5.771 + +Slack : 3.765 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 5.764 + +Slack : 3.812 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.719 + +Slack : 3.836 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.692 + +Slack : 3.886 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.385 +Data Delay : 5.634 + +Slack : 3.902 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.628 + +Slack : 3.902 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.628 + +Slack : 3.902 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.385 +Data Delay : 5.618 + +Slack : 3.909 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.385 +Data Delay : 5.611 + +Slack : 3.918 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.087 +Data Delay : 5.900 + +Slack : 3.924 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.384 +Data Delay : 5.597 + +Slack : 3.938 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.881 + +Slack : 3.940 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.384 +Data Delay : 5.581 + +Slack : 3.947 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.384 +Data Delay : 5.574 + +Slack : 3.961 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.371 +Data Delay : 5.571 + +Slack : 3.972 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.556 + +Slack : 3.977 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.371 +Data Delay : 5.555 + +Slack : 3.984 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.371 +Data Delay : 5.548 + +Slack : 3.985 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.543 + +Slack : 4.020 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.508 + +Slack : 4.027 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.501 + +Slack : 4.035 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.493 + +Slack : 4.042 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.486 + +Slack : 4.082 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.449 + +Slack : 4.104 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.389 +Data Delay : 5.412 + +Slack : 4.117 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.414 + +Slack : 4.132 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.381 + +Slack : 4.133 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.398 + +Slack : 4.135 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.378 + +Slack : 4.140 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.391 + +Slack : 4.141 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.387 + +Slack : 4.157 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.371 + +Slack : 4.159 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 5.670 + +Slack : 4.164 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.364 + +Slack : 4.166 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.387 +Data Delay : 5.352 + +Slack : 4.178 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.648 + +Slack : 4.187 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.076 +Data Delay : 5.640 + +Slack : 4.207 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.323 + +Slack : 4.207 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.323 + +Slack : 4.223 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.307 + +Slack : 4.223 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.307 + +Slack : 4.226 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.602 + +Slack : 4.226 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.602 + +Slack : 4.230 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.300 + +Slack : 4.230 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.373 +Data Delay : 5.300 + +Slack : 4.248 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 5.281 + +Slack : 4.285 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.087 +Data Delay : 5.533 + +Slack : 4.306 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.513 + +Slack : 4.311 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 5.218 + +Slack : 4.316 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 5.215 + +Slack : 4.357 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.076 +Data Delay : 5.470 + +Slack : 4.387 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.385 +Data Delay : 5.133 + +Slack : 4.392 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.440 + +Slack : 4.399 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.389 +Data Delay : 5.117 + +Slack : 4.401 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.384 +Data Delay : 5.120 + +Slack : 4.407 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.384 +Data Delay : 5.114 + +Slack : 4.420 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.412 + +Slack : 4.425 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.407 + +Slack : 4.427 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.086 + +Slack : 4.427 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.405 + +Slack : 4.430 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.083 + +Slack : 4.437 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.076 + +Slack : 4.440 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.084 +Data Delay : 5.381 + +Slack : 4.452 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.076 + +Slack : 4.453 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.060 + +Slack : 4.456 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.389 +Data Delay : 5.060 + +Slack : 4.459 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.389 +Data Delay : 5.057 + +Slack : 4.460 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.053 + +Slack : 4.461 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.387 +Data Delay : 5.057 + +Slack : 4.462 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.371 +Data Delay : 5.070 + +Slack : 4.463 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 5.366 + +Slack : 4.465 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.375 +Data Delay : 5.063 + +Slack : 4.477 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.036 + +Slack : 4.478 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.083 +Data Delay : 5.344 + +Slack : 4.484 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.392 +Data Delay : 5.029 + +Slack : 4.486 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.346 + +Slack : 4.516 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 5.313 + +Slack : 4.518 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.387 +Data Delay : 5.000 + +Slack : 4.519 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.353 +Data Delay : 5.123 + +Slack : 4.521 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.387 +Data Delay : 4.997 + +Slack : 4.540 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.286 + +Slack : 4.560 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.272 + +Slack : 4.567 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.076 +Data Delay : 5.260 + +Slack : 4.569 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.261 + +Slack : 4.594 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.234 + +Slack : 4.594 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.234 + +Slack : 4.611 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.221 + +Slack : 4.616 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.374 +Data Delay : 4.913 + +Slack : 4.621 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.372 +Data Delay : 4.910 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.059 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.327 +Data Delay : 2.659 + +Slack : 0.194 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.327 +Data Delay : 2.794 + +Slack : 0.473 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.672 + +Slack : 0.563 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.333 +Data Delay : 3.169 + +Slack : 0.624 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.327 +Data Delay : 3.224 + +Slack : 0.973 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.489 + +Slack : 0.995 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.075 +Data Delay : 3.343 + +Slack : 0.998 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 3.517 + +Slack : 1.008 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.521 + +Slack : 1.020 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.528 + +Slack : 1.025 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.528 + +Slack : 1.030 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.546 + +Slack : 1.040 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.553 + +Slack : 1.045 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.554 + +Slack : 1.054 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.557 + +Slack : 1.061 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.573 + +Slack : 1.064 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.567 + +Slack : 1.064 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.580 + +Slack : 1.064 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.577 + +Slack : 1.064 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.075 +Data Delay : 3.412 + +Slack : 1.066 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.579 + +Slack : 1.068 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.576 + +Slack : 1.068 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.582 + +Slack : 1.069 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 3.588 + +Slack : 1.071 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.226 +Data Delay : 3.570 + +Slack : 1.075 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.584 + +Slack : 1.084 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.594 + +Slack : 1.089 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.601 + +Slack : 1.090 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 3.609 + +Slack : 1.091 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.226 +Data Delay : 3.590 + +Slack : 1.092 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.327 +Data Delay : 3.692 + +Slack : 1.101 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.077 +Data Delay : 3.451 + +Slack : 1.105 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.228 +Data Delay : 3.606 + +Slack : 1.108 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.620 + +Slack : 1.111 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.624 + +Slack : 1.112 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.625 + +Slack : 1.112 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.615 + +Slack : 1.113 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.625 + +Slack : 1.115 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.069 +Data Delay : 3.457 + +Slack : 1.115 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.226 +Data Delay : 3.614 + +Slack : 1.116 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.618 + +Slack : 1.118 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.634 + +Slack : 1.119 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.231 +Data Delay : 3.623 + +Slack : 1.120 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.633 + +Slack : 1.120 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.228 +Data Delay : 3.621 + +Slack : 1.120 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.634 + +Slack : 1.121 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.630 + +Slack : 1.122 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.635 + +Slack : 1.122 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.241 +Data Delay : 3.636 + +Slack : 1.122 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.624 + +Slack : 1.123 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.636 + +Slack : 1.129 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.639 + +Slack : 1.129 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.640 + +Slack : 1.131 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 3.650 + +Slack : 1.133 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.635 + +Slack : 1.133 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.635 + +Slack : 1.135 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.231 +Data Delay : 3.639 + +Slack : 1.136 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.639 + +Slack : 1.138 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.075 +Data Delay : 3.486 + +Slack : 1.139 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.652 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.649 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.650 + +Slack : 1.141 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.661 + +Slack : 1.144 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.653 + +Slack : 1.145 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.647 + +Slack : 1.146 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.658 + +Slack : 1.146 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.648 + +Slack : 1.148 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.656 + +Slack : 1.148 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.228 +Data Delay : 3.649 + +Slack : 1.150 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.660 + +Slack : 1.152 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.665 + +Slack : 1.153 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.665 + +Slack : 1.154 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.227 +Data Delay : 3.654 + +Slack : 1.154 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.657 + +Slack : 1.154 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.667 + +Slack : 1.155 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.227 +Data Delay : 3.655 + +Slack : 1.159 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.661 + +Slack : 1.160 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.680 + +Slack : 1.162 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.228 +Data Delay : 3.663 + +Slack : 1.162 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.664 + +Slack : 1.162 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.665 + +Slack : 1.162 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.675 + +Slack : 1.164 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.674 + +Slack : 1.165 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.231 +Data Delay : 3.669 + +Slack : 1.166 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.669 + +Slack : 1.167 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.071 +Data Delay : 3.511 + +Slack : 1.167 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.677 + +Slack : 1.172 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.685 + +Slack : 1.174 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.687 + +Slack : 1.177 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.229 +Data Delay : 3.679 + +Slack : 1.177 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.690 + +Slack : 1.177 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.687 + +Slack : 1.178 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.694 + +Slack : 1.184 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.227 +Data Delay : 3.684 + +Slack : 1.187 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.227 +Data Delay : 3.687 + +Slack : 1.187 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 3.706 + +Slack : 1.188 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.691 + +Slack : 1.190 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.315 +Data Delay : 3.778 + +Slack : 1.192 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.226 +Data Delay : 3.691 + +Slack : 1.193 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.704 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.298 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vga_vc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.495 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.708 + +Slack : 0.496 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.696 + +Slack : 0.498 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.698 + +Slack : 0.504 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 0.705 + +Slack : 0.604 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.803 + +Slack : 0.727 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 0.928 + +Slack : 0.741 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.941 + +Slack : 0.783 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.983 + +Slack : 0.783 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.988 + +Slack : 0.805 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 1.019 + +Slack : 0.889 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.095 + +Slack : 0.901 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.104 + +Slack : 0.917 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.123 + +Slack : 0.980 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.181 + +Slack : 0.989 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 0.903 + +Slack : 0.989 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.190 + +Slack : 0.999 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 0.913 + +Slack : 1.002 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.203 + +Slack : 1.013 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.213 + +Slack : 1.018 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 0.932 + +Slack : 1.048 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.253 + +Slack : 1.049 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 0.936 + +Slack : 1.062 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.259 +Data Delay : 0.947 + +Slack : 1.069 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.259 +Data Delay : 0.954 + +Slack : 1.096 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.296 + +Slack : 1.112 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 1.316 + +Slack : 1.113 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.318 + +Slack : 1.114 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.319 + +Slack : 1.117 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 1.031 + +Slack : 1.127 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.332 + +Slack : 1.133 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.661 + +Slack : 1.139 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 1.053 + +Slack : 1.139 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.345 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.346 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.668 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.346 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.346 + +Slack : 1.152 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 1.066 + +Slack : 1.160 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 1.047 + +Slack : 1.160 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.366 + +Slack : 1.162 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 1.049 + +Slack : 1.166 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.372 + +Slack : 1.168 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 1.055 + +Slack : 1.170 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 1.057 + +Slack : 1.185 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 1.072 + +Slack : 1.185 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.386 + +Slack : 1.210 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.416 + +Slack : 1.211 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.417 + +Slack : 1.214 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.230 +Data Delay : 1.128 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.424 + +Slack : 1.225 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.431 + +Slack : 1.226 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.431 + +Slack : 1.229 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.432 + +Slack : 1.236 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.442 + +Slack : 1.239 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.445 + +Slack : 1.244 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.450 + +Slack : 1.251 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.457 + +Slack : 1.261 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.467 + +Slack : 1.269 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.475 + +Slack : 1.274 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.480 + +Slack : 1.276 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.482 + +Slack : 1.287 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.815 + +Slack : 1.293 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.499 + +Slack : 1.294 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.822 + +Slack : 1.295 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.501 + +Slack : 1.309 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.514 + +Slack : 1.321 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.527 + +Slack : 1.339 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.544 + +Slack : 1.340 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.546 + +Slack : 1.360 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.888 + +Slack : 1.365 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.571 + +Slack : 1.368 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.258 +Data Delay : 1.254 + +Slack : 1.374 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 1.578 + +Slack : 1.375 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.258 +Data Delay : 1.261 + +Slack : 1.375 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.578 + +Slack : 1.378 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.578 + +Slack : 1.382 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.585 + +Slack : 1.400 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.257 +Data Delay : 1.287 + +Slack : 1.412 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.618 + +Slack : 1.416 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.617 + +Slack : 1.420 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.626 + +Slack : 1.421 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.627 + +Slack : 1.423 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.623 + +Slack : 1.424 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.259 +Data Delay : 1.309 + +Slack : 1.429 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.629 + +Slack : 1.435 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.641 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.298 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.306 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.519 + +Slack : 0.518 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.731 + +Slack : 1.248 +From Node : SW[2] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : -0.017 +Clock Skew : 0.626 +Data Delay : 1.091 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.299 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.511 + +Slack : 0.299 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.511 + +Slack : 0.306 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.519 + +Slack : 0.306 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.519 + +Slack : 0.307 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.519 + +Slack : 0.308 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.519 + +Slack : 0.311 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.319 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.519 + +Slack : 0.320 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + +Slack : 0.323 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.536 + +Slack : 0.324 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.537 + +Slack : 0.324 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.537 + +Slack : 0.325 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.538 + +Slack : 0.325 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.538 + +Slack : 0.326 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.539 + +Slack : 0.326 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.539 + +Slack : 0.326 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.539 + +Slack : 0.327 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.540 + +Slack : 0.336 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.548 + +Slack : 0.340 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.340 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.353 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.566 + +Slack : 0.360 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.559 + +Slack : 0.432 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.631 + +Slack : 0.480 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.693 + +Slack : 0.481 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.694 + +Slack : 0.483 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.696 + +Slack : 0.483 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.696 + +Slack : 0.485 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.698 + +Slack : 0.488 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.701 + +Slack : 0.488 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.701 + +Slack : 0.490 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.689 + +Slack : 0.490 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.703 + +Slack : 0.498 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.711 + +Slack : 0.503 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.703 + +Slack : 0.504 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.704 + +Slack : 0.509 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.709 + +Slack : 0.510 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.694 + +Slack : 0.512 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.712 + +Slack : 0.513 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.726 + +Slack : 0.516 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.716 + +Slack : 0.516 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.729 + +Slack : 0.521 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.721 + +Slack : 0.526 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.739 + +Slack : 0.531 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.744 + +Slack : 0.532 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.745 + +Slack : 0.533 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.732 + +Slack : 0.537 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.737 + +Slack : 0.542 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.742 + +Slack : 0.546 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.057 + +Slack : 0.549 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.762 + +Slack : 0.554 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.753 + +Slack : 0.554 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.767 + +Slack : 0.556 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.755 + +Slack : 0.596 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.795 + +Slack : 0.602 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.786 + +Slack : 0.619 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.803 + +Slack : 0.630 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.829 + +Slack : 0.630 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.106 +Data Delay : 0.880 + +Slack : 0.645 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.858 + +Slack : 0.667 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.866 + +Slack : 0.668 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.867 + +Slack : 0.698 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.396 +Data Delay : 1.238 + +Slack : 0.700 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.899 + +Slack : 0.718 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.229 + +Slack : 0.724 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.912 + +Slack : 0.732 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.945 + +Slack : 0.735 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.948 + +Slack : 0.737 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.950 + +Slack : 0.744 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.957 + +Slack : 0.745 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.958 + +Slack : 0.747 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.947 + +Slack : 0.748 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.948 + +Slack : 0.751 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.963 + +Slack : 0.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.954 + +Slack : 0.754 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.954 + +Slack : 0.757 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.969 + +Slack : 0.758 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.971 + +Slack : 0.759 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.959 + +Slack : 0.759 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.959 + +Slack : 0.759 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.959 + +Slack : 0.759 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.959 + +Slack : 0.759 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.972 + +Slack : 0.761 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.961 + +Slack : 0.763 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.963 + +Slack : 0.763 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.963 + +Slack : 0.771 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.984 + +Slack : 0.772 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.972 + +Slack : 0.780 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.980 + +Slack : 0.781 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.994 + +Slack : 0.781 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.994 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.312 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.320 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + +Slack : 0.321 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.519 + +Slack : 0.336 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.535 + +Slack : 0.374 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.573 + +Slack : 0.446 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.645 + +Slack : 0.500 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.699 + +Slack : 0.500 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.699 + +Slack : 0.501 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.699 + +Slack : 0.501 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.699 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.503 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.504 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + +Slack : 0.504 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.702 + +Slack : 0.505 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.704 + +Slack : 0.505 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.703 + +Slack : 0.507 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.706 + +Slack : 0.512 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.710 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.711 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.711 + +Slack : 0.514 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.712 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.714 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.714 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.714 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.716 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.716 + +Slack : 0.519 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.718 + +Slack : 0.627 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.825 + +Slack : 0.744 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.943 + +Slack : 0.745 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.944 + +Slack : 0.746 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.945 + +Slack : 0.747 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.945 + +Slack : 0.748 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.946 + +Slack : 0.748 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.751 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.949 + +Slack : 0.751 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.752 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.753 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + +Slack : 0.754 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.756 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.955 + +Slack : 0.757 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.955 + +Slack : 0.758 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.956 + +Slack : 0.758 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.759 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.957 + +Slack : 0.759 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.958 + +Slack : 0.760 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.959 + +Slack : 0.761 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.959 + +Slack : 0.761 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.959 + +Slack : 0.761 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.763 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.961 + +Slack : 0.763 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.961 + +Slack : 0.764 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.963 + +Slack : 0.767 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.965 + +Slack : 0.767 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.965 + +Slack : 0.769 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.967 + +Slack : 0.770 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.968 + +Slack : 0.770 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.968 + +Slack : 0.774 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.972 + +Slack : 0.774 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.972 + +Slack : 0.805 +From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.003 + +Slack : 0.833 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.032 + +Slack : 0.834 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.033 + +Slack : 0.835 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.034 + +Slack : 0.837 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.035 + +Slack : 0.837 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.036 + +Slack : 0.840 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.039 + +Slack : 0.841 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.040 + +Slack : 0.842 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.041 + +Slack : 0.844 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.042 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.044 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.046 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.047 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.047 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.048 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.048 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.048 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.049 + +Slack : 0.853 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.051 + +Slack : 0.855 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.053 + +Slack : 0.855 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.054 + +Slack : 0.856 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.055 + +Slack : 0.857 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.055 + +Slack : 0.857 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.055 + +Slack : 0.857 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.056 + +Slack : 0.858 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.056 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.057 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.057 + +Slack : 0.863 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.061 + +Slack : 0.863 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.061 + +Slack : 0.865 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.063 + +Slack : 0.866 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.064 + +Slack : 0.866 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.064 + +Slack : 0.870 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.068 + +Slack : 0.870 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.068 + +Slack : 0.899 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.096 + +Slack : 0.902 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.101 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -5.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.941 + +Slack : -5.744 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.943 + +Slack : -5.744 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.090 +Data Delay : 3.941 + +Slack : -5.744 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.091 +Data Delay : 3.940 + +Slack : -5.743 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.092 +Data Delay : 3.938 + +Slack : -5.507 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.115 +Data Delay : 3.681 + +Slack : -5.494 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.116 +Data Delay : 3.667 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.082 +Data Delay : 3.554 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.082 +Data Delay : 3.554 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.082 +Data Delay : 3.554 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.070 +Data Delay : 3.566 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.548 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.082 +Data Delay : 3.554 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.082 +Data Delay : 3.554 + +Slack : -5.257 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.082 +Data Delay : 3.554 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.547 + +Slack : -4.996 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.176 +Data Delay : 3.548 + +Slack : -4.971 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.204 +Data Delay : 3.554 + +Slack : -4.967 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.214 +Data Delay : 3.560 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.211 +Data Delay : 3.549 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.211 +Data Delay : 3.549 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.548 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.548 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.548 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.548 + +Slack : -4.959 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.548 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.233 +Data Delay : 3.555 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.224 +Data Delay : 3.546 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.224 +Data Delay : 3.546 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.223 +Data Delay : 3.545 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.943 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.554 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.548 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.548 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.548 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.548 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.548 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.239 +Data Delay : 3.549 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.239 +Data Delay : 3.549 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.239 +Data Delay : 3.549 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.239 +Data Delay : 3.549 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.611 +Data Delay : 3.208 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.611 +Data Delay : 3.208 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.611 +Data Delay : 3.208 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.611 +Data Delay : 3.208 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.601 +Data Delay : 3.208 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.601 +Data Delay : 3.208 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.601 +Data Delay : 3.208 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.601 +Data Delay : 3.208 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.601 +Data Delay : 3.208 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.595 +Data Delay : 3.204 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.595 +Data Delay : 3.204 + +Slack : 3.381 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.203 + +Slack : 3.382 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.204 + +Slack : 3.382 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.204 + +Slack : 3.382 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.594 +Data Delay : 3.204 + +Slack : 3.384 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.605 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.385 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.217 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.206 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.206 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.206 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.206 + +Slack : 3.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.206 + +Slack : 3.398 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.582 +Data Delay : 3.208 + +Slack : 3.398 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.582 +Data Delay : 3.208 + +Slack : 3.409 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.585 +Data Delay : 3.222 + +Slack : 3.413 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.575 +Data Delay : 3.216 + +Slack : 3.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.545 +Data Delay : 3.206 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.206 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.205 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.205 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.205 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.205 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.205 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.208 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.277 +Data Delay : 3.216 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.277 +Data Delay : 3.216 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.277 +Data Delay : 3.216 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.289 +Data Delay : 3.228 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.277 +Data Delay : 3.216 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.277 +Data Delay : 3.216 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.277 +Data Delay : 3.216 + +Slack : 3.895 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.226 +Data Delay : 3.294 + +Slack : 3.909 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.227 +Data Delay : 3.309 + +Slack : 4.117 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.254 +Data Delay : 3.541 + +Slack : 4.117 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.252 +Data Delay : 3.539 + +Slack : 4.117 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.251 +Data Delay : 3.538 + +Slack : 4.117 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.250 +Data Delay : 3.537 + +Slack : 4.120 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.250 +Data Delay : 3.540 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.746 +Actual Width : 4.962 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.746 +Actual Width : 4.962 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.746 +Actual Width : 4.962 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.746 +Actual Width : 4.962 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.746 +Actual Width : 4.962 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[7] + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[0] + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[1] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[2] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[3] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[6] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[0] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.849 +Actual Width : 4.999 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.849 +Actual Width : 4.999 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.851 +Actual Width : 5.001 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 9.487 +Actual Width : 9.717 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : 9.496 +Actual Width : 9.726 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : 9.497 +Actual Width : 9.727 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[0] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[1] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[2] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[3] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[4] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[5] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[6] + +Slack : 19.597 +Actual Width : 19.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[7] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[0] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[1] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[2] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[3] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[4] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[5] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[6] + +Slack : 19.604 +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[7] + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[2] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[5] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[6] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[4] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[5] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[6] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[7] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[8] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[9] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_vc[6] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_vc[9] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[11] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[12] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[3] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[5] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[6] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[7] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[8] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[9] + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.606 +Actual Width : 19.822 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 + +Slack : 19.606 +Actual Width : 19.822 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[0] + +Slack : 19.606 +Actual Width : 19.822 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[1] + +Slack : 19.606 +Actual Width : 19.822 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[3] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 20.589 +Actual Width : 20.805 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] + +Slack : 20.589 +Actual Width : 20.805 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.593 +Actual Width : 20.809 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.602 +Actual Width : 20.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] + +Slack : 20.623 +Actual Width : 20.807 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] + +Slack : 20.633 +Actual Width : 20.817 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] + +Slack : 20.633 +Actual Width : 20.817 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] + +Slack : 20.633 +Actual Width : 20.817 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] + +Slack : 20.633 +Actual Width : 20.817 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] + +Slack : 20.633 +Actual Width : 20.817 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] + +Slack : 20.667 +Actual Width : 20.883 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] + +Slack : 20.667 +Actual Width : 20.883 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] + +Slack : 20.667 +Actual Width : 20.883 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] + +Slack : 20.667 +Actual Width : 20.883 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] + +Slack : 20.667 +Actual Width : 20.883 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] + +Slack : 20.676 +Actual Width : 20.892 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] + +Slack : 20.695 +Actual Width : 20.845 +Required Width : 0.150 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out + +Slack : 20.696 +Actual Width : 20.846 +Required Width : 0.150 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out + +Slack : 20.697 +Actual Width : 20.852 +Required Width : 0.155 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r + +Slack : 20.698 +Actual Width : 20.853 +Required Width : 0.155 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r + +Slack : 20.698 +Actual Width : 20.853 +Required Width : 0.155 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 + +Slack : 20.698 +Actual Width : 20.853 +Required Width : 0.155 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r + +Slack : 20.698 +Actual Width : 20.853 +Required Width : 0.155 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.699 +Actual Width : 20.849 +Required Width : 0.150 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r + +Slack : 20.699 +Actual Width : 20.849 +Required Width : 0.150 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r + +Slack : 20.699 +Actual Width : 20.849 +Required Width : 0.150 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 + +Slack : 20.699 +Actual Width : 20.849 +Required Width : 0.150 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.699 +Actual Width : 20.883 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 35.491 +Actual Width : 35.707 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.491 +Actual Width : 35.707 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] + +Slack : 35.597 +Actual Width : 35.781 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.597 +Actual Width : 35.781 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] + +Slack : 35.725 +Actual Width : 35.725 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] + +Slack : 35.725 +Actual Width : 35.725 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk + +Slack : 35.731 +Actual Width : 35.731 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.731 +Actual Width : 35.731 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.757 +Actual Width : 35.757 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.757 +Actual Width : 35.757 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.763 +Actual Width : 35.763 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] + +Slack : 35.763 +Actual Width : 35.763 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk + +Slack : 69.489 +Actual Width : 71.489 +Required Width : 2.000 +Type : Min Period +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 69.489 +Actual Width : 71.489 +Required Width : 2.000 +Type : Min Period +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Setup Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.472 +Fall : 1.660 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 2.972 +Fall : 3.141 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : 0.869 +Fall : 1.148 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : 0.869 +Fall : 1.148 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : 1.123 +Fall : 1.331 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.505 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Hold Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.067 +Fall : -1.233 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -2.115 +Fall : -2.290 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : -0.321 +Fall : -0.592 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : -0.321 +Fall : -0.592 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : -0.571 +Fall : -0.775 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : -0.856 +Fall : -1.078 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 9.763 +Fall : 9.640 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 8.930 +Fall : 8.821 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 9.018 +Fall : 8.987 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 8.648 +Fall : 8.561 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 9.083 +Fall : 9.048 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 9.570 +Fall : 9.500 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 9.433 +Fall : 9.450 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 9.653 +Fall : 9.560 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 9.763 +Fall : 9.640 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 9.550 +Fall : 9.453 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 9.034 +Fall : 8.934 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 9.034 +Fall : 8.981 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 8.877 +Fall : 8.809 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 8.846 +Fall : 8.778 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 9.369 +Fall : 9.285 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 9.081 +Fall : 9.045 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 9.550 +Fall : 9.453 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 9.133 +Fall : 8.974 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.991 +Fall : 2.916 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.991 +Fall : 2.916 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.992 +Fall : 2.917 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 2.989 +Fall : 2.914 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 2.974 +Fall : 2.902 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 3.050 +Fall : 2.956 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.053 +Fall : 2.959 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 2.972 +Fall : 2.900 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 2.989 +Fall : 2.914 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.050 +Fall : 2.956 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.765 +Fall : 5.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.237 +Fall : 5.209 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.604 +Fall : 5.575 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.442 +Fall : 5.371 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.592 +Fall : 5.600 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.580 +Fall : 5.546 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.588 +Fall : 5.509 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.504 +Fall : 5.454 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.634 +Fall : 5.552 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 5.765 +Fall : 5.797 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 5.763 +Fall : 5.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 5.382 +Fall : 5.398 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 5.382 +Fall : 5.398 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 5.685 +Fall : 5.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 5.395 +Fall : 5.405 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 5.395 +Fall : 5.405 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 5.355 +Fall : 5.389 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.050 +Fall : 2.956 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.057 +Fall : 2.963 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.468 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.400 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 7.517 +Fall : 7.486 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 7.311 +Fall : 7.273 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.043 +Fall : 7.020 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 6.657 +Fall : 6.591 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.277 +Fall : 7.239 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.944 +Fall : 6.961 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 7.318 +Fall : 7.306 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 7.392 +Fall : 7.362 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 7.517 +Fall : 7.486 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.415 +Fall : 7.386 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.415 +Fall : 7.386 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.059 +Fall : 7.014 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 6.886 +Fall : 6.839 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.040 +Fall : 6.969 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 6.743 +Fall : 6.746 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 6.966 +Fall : 6.901 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.289 +Fall : 7.255 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 6.887 +Fall : 6.820 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 7.256 +Fall : 6.934 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 7.256 +Fall : 6.934 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 5.723 +Fall : 5.600 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 5.856 +Fall : 5.845 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 6.038 +Fall : 6.088 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 6.121 +Fall : 6.026 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 6.121 +Fall : 6.026 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 6.117 +Fall : 6.009 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 6.037 +Fall : 5.922 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 6.022 +Fall : 5.909 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 2.597 +Fall : 2.522 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 6.166 +Fall : 6.135 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 6.092 +Fall : 6.135 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 6.166 +Fall : 6.053 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 5.733 +Fall : 5.754 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 6.077 +Fall : 6.107 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 2.595 +Fall : 2.520 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 2.592 +Fall : 2.517 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 2.592 +Fall : 2.517 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 2.596 +Fall : 2.521 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 4.361 +Fall : 3.948 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 2.594 +Fall : 2.519 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 2.647 +Fall : 2.553 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.648 +Fall : 2.554 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 7.264 +Fall : 7.210 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 7.290 +Fall : 7.210 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.408 +Fall : 7.342 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 7.326 +Fall : 7.234 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.659 +Fall : 7.654 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 7.264 +Fall : 7.229 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 8.016 +Fall : 8.020 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 7.890 +Fall : 7.849 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 8.166 +Fall : 8.046 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.067 +Fall : 7.021 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.391 +Fall : 7.318 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.423 +Fall : 7.336 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 7.548 +Fall : 7.476 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.435 +Fall : 7.397 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.067 +Fall : 7.021 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 7.710 +Fall : 7.667 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.790 +Fall : 7.745 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 7.562 +Fall : 7.409 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 2.600 +Fall : 2.528 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 2.686 +Fall : 2.592 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.620 +Fall : 2.544 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.620 +Fall : 2.544 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 2.619 +Fall : 2.543 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.621 +Fall : 2.545 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 2.618 +Fall : 2.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 2.619 +Fall : 2.543 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 2.602 +Fall : 2.530 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 2.686 +Fall : 2.592 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 2.678 +Fall : 2.584 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 2.681 +Fall : 2.587 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 2.600 +Fall : 2.528 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 2.618 +Fall : 2.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 2.618 +Fall : 2.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 2.620 +Fall : 2.544 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 2.678 +Fall : 2.584 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.286 +Fall : 4.349 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.700 +Fall : 4.672 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.053 +Fall : 5.022 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.897 +Fall : 4.828 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.041 +Fall : 5.044 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.032 +Fall : 4.997 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.038 +Fall : 4.958 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.903 +Fall : 4.849 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.081 +Fall : 5.001 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 4.678 +Fall : 4.739 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 4.677 +Fall : 4.752 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 4.311 +Fall : 4.357 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 4.311 +Fall : 4.357 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 4.602 +Fall : 4.681 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 4.323 +Fall : 4.363 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 4.323 +Fall : 4.363 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 4.286 +Fall : 4.349 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 2.678 +Fall : 2.584 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 2.685 +Fall : 2.591 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.091 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.022 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.403 +Fall : 5.370 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.348 +Fall : 6.243 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.036 +Fall : 5.999 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.828 +Fall : 5.775 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.403 +Fall : 5.370 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.103 +Fall : 6.053 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.223 +Fall : 6.211 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.718 +Fall : 5.699 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.300 +Fall : 6.260 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 5.179 +Fall : 5.113 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 6.449 +Fall : 6.351 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 6.051 +Fall : 5.993 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 6.050 +Fall : 6.017 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 5.179 +Fall : 5.113 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 5.906 +Fall : 5.845 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 5.917 +Fall : 5.858 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 5.618 +Fall : 5.595 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 5.696 +Fall : 5.623 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 3.588 +Fall : 3.435 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 5.218 +Fall : 4.734 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 3.588 +Fall : 3.435 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 3.803 +Fall : 3.631 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 3.978 +Fall : 3.865 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 3.686 +Fall : 3.540 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 3.781 +Fall : 3.652 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 3.779 +Fall : 3.634 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 3.700 +Fall : 3.552 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 3.686 +Fall : 3.540 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 2.241 +Fall : 2.165 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 3.668 +Fall : 3.530 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 4.012 +Fall : 3.895 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 4.141 +Fall : 4.046 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 3.668 +Fall : 3.530 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 3.998 +Fall : 3.868 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 2.240 +Fall : 2.164 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 2.237 +Fall : 2.161 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 2.236 +Fall : 2.160 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 2.240 +Fall : 2.164 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 4.005 +Fall : 3.591 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 2.238 +Fall : 2.162 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 2.290 +Fall : 2.196 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.291 +Fall : 2.197 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 4.171 +RF : +FR : +FF : 4.298 + +Input Port : SW[2] +Output Port : LED[2] +RR : 3.640 +RF : +FR : +FF : 3.830 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.345 +RF : +FR : +FF : 6.446 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.209 +RF : +FR : +FF : 6.310 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 3.926 +RF : +FR : +FF : 4.080 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 4.036 +RF : +FR : +FF : 4.165 + +Input Port : SW[2] +Output Port : LED[2] +RR : 3.527 +RF : +FR : +FF : 3.715 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.118 +RF : +FR : +FF : 6.226 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 5.986 +RF : +FR : +FF : 6.095 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 3.795 +RF : +FR : +FF : 3.951 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.370 +Fall : 5.228 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.483 +Fall : 5.341 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.483 +Fall : 5.341 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.382 +Fall : 5.257 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.574 +Fall : 5.463 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.374 +Fall : 5.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.370 +Fall : 5.228 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.370 +Fall : 5.228 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.378 +Fall : 5.253 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.319 +Fall : 4.194 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.453 +Fall : 4.311 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.453 +Fall : 4.311 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.323 +Fall : 4.198 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.536 +Fall : 4.425 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.347 +Fall : 4.205 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.343 +Fall : 4.201 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.343 +Fall : 4.201 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.319 +Fall : 4.194 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.282 +1 to Hi-Z : 5.424 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.380 +1 to Hi-Z : 5.522 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.380 +1 to Hi-Z : 5.522 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.325 +1 to Hi-Z : 5.450 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.550 +1 to Hi-Z : 5.661 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.295 +1 to Hi-Z : 5.437 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.282 +1 to Hi-Z : 5.424 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.282 +1 to Hi-Z : 5.424 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.315 +1 to Hi-Z : 5.440 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.226 +1 to Hi-Z : 4.352 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.321 +1 to Hi-Z : 4.463 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.321 +1 to Hi-Z : 4.463 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.236 +1 to Hi-Z : 4.361 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.482 +1 to Hi-Z : 4.593 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.239 +1 to Hi-Z : 4.381 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.226 +1 to Hi-Z : 4.368 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.226 +1 to Hi-Z : 4.368 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.227 +1 to Hi-Z : 4.352 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++--------------------------------------------------------------------------------+ +Clock : CLOCK_50 +Slack : -14.929 +End Point TNS : -634.264 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : -4.459 +End Point TNS : -174.631 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -3.773 +End Point TNS : -34.191 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : -2.784 +End Point TNS : -2.784 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 5.613 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++--------------------------------------------------------------------------------+ +Clock : CLOCK_50 +Slack : -0.217 +End Point TNS : -0.350 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 0.177 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.178 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 0.178 +End Point TNS : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.186 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery Summary ; ++--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : -4.694 +End Point TNS : -356.359 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal Summary ; ++--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 2.518 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++--------------------------------------------------------------------------------+ +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.784 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 9.208 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 19.609 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 20.600 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 35.535 +End Point TNS : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : -14.929 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.977 + +Slack : -14.904 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.952 + +Slack : -14.859 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.752 + +Slack : -14.844 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.904 + +Slack : -14.835 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.881 + +Slack : -14.831 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.879 + +Slack : -14.807 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.867 + +Slack : -14.791 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.851 + +Slack : -14.781 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.827 + +Slack : -14.775 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.823 + +Slack : -14.766 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.662 + +Slack : -14.764 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.657 + +Slack : -14.755 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.658 + +Slack : -14.751 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.811 + +Slack : -14.739 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.030 +Data Delay : 4.783 + +Slack : -14.736 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.631 + +Slack : -14.728 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.027 +Data Delay : 4.775 + +Slack : -14.725 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.615 + +Slack : -14.717 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.777 + +Slack : -14.716 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.613 + +Slack : -14.712 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.760 + +Slack : -14.708 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.027 +Data Delay : 4.755 + +Slack : -14.707 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.755 + +Slack : -14.706 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.596 + +Slack : -14.701 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.749 + +Slack : -14.697 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.757 + +Slack : -14.695 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.755 + +Slack : -14.689 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.585 + +Slack : -14.682 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.742 + +Slack : -14.681 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.727 + +Slack : -14.676 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.186 +Data Delay : 4.564 + +Slack : -14.675 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.030 +Data Delay : 4.719 + +Slack : -14.665 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.030 +Data Delay : 4.709 + +Slack : -14.660 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.563 + +Slack : -14.658 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.704 + +Slack : -14.657 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.553 + +Slack : -14.656 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.716 + +Slack : -14.656 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.716 + +Slack : -14.641 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.687 + +Slack : -14.640 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.688 + +Slack : -14.633 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.522 + +Slack : -14.625 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.671 + +Slack : -14.621 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.518 + +Slack : -14.616 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.506 + +Slack : -14.608 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.497 + +Slack : -14.602 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.662 + +Slack : -14.594 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.490 + +Slack : -14.593 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.638 + +Slack : -14.592 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.487 + +Slack : -14.585 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.482 + +Slack : -14.579 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.468 + +Slack : -14.578 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.471 + +Slack : -14.573 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.633 + +Slack : -14.557 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.030 +Data Delay : 4.601 + +Slack : -14.557 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.448 + +Slack : -14.552 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.612 + +Slack : -14.550 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.443 + +Slack : -14.534 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.594 + +Slack : -14.533 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.593 + +Slack : -14.532 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.186 +Data Delay : 4.420 + +Slack : -14.525 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.416 + +Slack : -14.506 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.552 + +Slack : -14.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.388 + +Slack : -14.491 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.381 + +Slack : -14.491 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.176 +Data Delay : 4.389 + +Slack : -14.485 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.531 + +Slack : -14.471 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.531 + +Slack : -14.470 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.360 + +Slack : -14.469 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.362 + +Slack : -14.468 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.514 + +Slack : -14.467 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.513 + +Slack : -14.459 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.519 + +Slack : -14.450 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.510 + +Slack : -14.441 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.501 + +Slack : -14.440 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.336 + +Slack : -14.434 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.170 +Data Delay : 4.338 + +Slack : -14.432 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.492 + +Slack : -14.428 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.488 + +Slack : -14.428 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.488 + +Slack : -14.409 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.309 + +Slack : -14.406 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.299 + +Slack : -14.402 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.295 + +Slack : -14.395 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.292 + +Slack : -14.394 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.454 + +Slack : -14.393 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.293 + +Slack : -14.391 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.451 + +Slack : -14.389 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.284 + +Slack : -14.381 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.272 + +Slack : -14.375 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.275 + +Slack : -14.373 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.268 + +Slack : -14.371 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.266 + +Slack : -14.361 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.258 + +Slack : -14.360 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.027 +Data Delay : 4.407 + +Slack : -14.352 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.176 +Data Delay : 4.250 + +Slack : -14.348 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.243 + +Slack : -14.345 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.405 + +Slack : -14.342 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.173 +Data Delay : 4.243 + +Slack : -14.333 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.224 + +Slack : -14.330 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.225 + +Slack : -14.314 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.360 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.459 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.047 +Data Delay : 2.501 + +Slack : -4.436 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.386 +Data Delay : 3.139 + +Slack : -4.407 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 3.121 + +Slack : -4.374 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.201 +Data Delay : 3.262 + +Slack : -4.337 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.048 +Data Delay : 2.378 + +Slack : -4.336 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 3.050 + +Slack : -4.334 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.376 +Data Delay : 3.047 + +Slack : -4.332 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 3.046 + +Slack : -4.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.372 +Data Delay : 3.041 + +Slack : -4.319 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 3.039 + +Slack : -4.300 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 3.014 + +Slack : -4.282 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.054 +Data Delay : 2.317 + +Slack : -4.275 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.372 +Data Delay : 2.992 + +Slack : -4.271 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.051 +Data Delay : 2.309 + +Slack : -4.264 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.973 + +Slack : -4.263 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 +Data Delay : 2.969 + +Slack : -4.259 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.974 + +Slack : -4.235 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.955 + +Slack : -4.234 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.372 +Data Delay : 2.951 + +Slack : -4.231 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.381 +Data Delay : 2.939 + +Slack : -4.211 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.944 + +Slack : -4.208 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.382 +Data Delay : 2.915 + +Slack : -4.202 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.370 +Data Delay : 2.921 + +Slack : -4.202 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.385 +Data Delay : 2.906 + +Slack : -4.202 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.195 +Data Delay : 3.096 + +Slack : -4.201 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.198 +Data Delay : 3.092 + +Slack : -4.195 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.358 +Data Delay : 2.926 + +Slack : -4.169 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.196 +Data Delay : 3.062 + +Slack : -4.142 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.863 + +Slack : -4.141 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.362 +Data Delay : 2.868 + +Slack : -4.137 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.366 +Data Delay : 2.860 + +Slack : -4.127 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.360 +Data Delay : 2.856 + +Slack : -4.126 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.865 + +Slack : -4.125 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.364 +Data Delay : 2.850 + +Slack : -4.123 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.391 +Data Delay : 2.821 + +Slack : -4.111 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.365 +Data Delay : 2.835 + +Slack : -4.105 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.826 + +Slack : -4.100 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.841 + +Slack : -4.095 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.815 + +Slack : -4.081 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.337 +Data Delay : 2.833 + +Slack : -4.079 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.830 + +Slack : -4.077 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.337 +Data Delay : 2.829 + +Slack : -4.069 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.790 + +Slack : -4.066 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.806 + +Slack : -4.058 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.362 +Data Delay : 2.785 + +Slack : -4.049 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.363 +Data Delay : 2.775 + +Slack : -4.045 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.337 +Data Delay : 2.797 + +Slack : -4.043 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 2.765 + +Slack : -4.041 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.762 + +Slack : -4.039 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 2.761 + +Slack : -4.031 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.353 +Data Delay : 2.767 + +Slack : -4.026 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.741 + +Slack : -4.014 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.359 +Data Delay : 2.744 + +Slack : -4.013 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.753 + +Slack : -4.007 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 2.729 + +Slack : -4.005 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.717 + +Slack : -4.005 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.352 +Data Delay : 2.742 + +Slack : -4.000 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.715 + +Slack : -3.997 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.741 + +Slack : -3.985 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.725 + +Slack : -3.983 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.695 + +Slack : -3.981 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.723 + +Slack : -3.980 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.346 +Data Delay : 2.723 + +Slack : -3.978 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.718 + +Slack : -3.966 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 2.680 + +Slack : -3.961 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.359 +Data Delay : 2.691 + +Slack : -3.955 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.670 + +Slack : -3.945 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.357 +Data Delay : 2.677 + +Slack : -3.942 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.690 + +Slack : -3.940 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.342 +Data Delay : 2.687 + +Slack : -3.938 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.686 + +Slack : -3.936 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.363 +Data Delay : 2.662 + +Slack : -3.936 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.362 +Data Delay : 2.663 + +Slack : -3.935 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.358 +Data Delay : 2.666 + +Slack : -3.929 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.352 +Data Delay : 2.666 + +Slack : -3.928 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.662 + +Slack : -3.923 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.657 + +Slack : -3.917 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.354 +Data Delay : 2.652 + +Slack : -3.912 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.352 +Data Delay : 2.649 + +Slack : -3.906 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.654 + +Slack : -3.895 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.600 + +Slack : -3.894 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.343 +Data Delay : 2.640 + +Slack : -3.893 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.346 +Data Delay : 2.636 + +Slack : -3.881 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.601 + +Slack : -3.879 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.627 + +Slack : -3.873 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.344 +Data Delay : 2.618 + +Slack : -3.870 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.366 +Data Delay : 2.593 + +Slack : -3.861 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.344 +Data Delay : 2.606 + +Slack : -3.854 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.386 +Data Delay : 2.557 + +Slack : -3.837 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.542 + +Slack : -3.826 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 +Data Delay : 2.532 + +Slack : -3.823 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.539 + +Slack : -3.818 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.371 +Data Delay : 2.536 + +Slack : -3.817 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.342 +Data Delay : 2.564 + +Slack : -3.816 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.554 + +Slack : -3.816 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.364 +Data Delay : 2.541 + +Slack : -3.816 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.554 + +Slack : -3.812 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.357 +Data Delay : 2.544 + +Slack : -3.811 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.553 + +Slack : -3.803 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.547 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -3.773 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.248 +Data Delay : 1.849 + +Slack : -3.543 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.047 +Data Delay : 1.867 + +Slack : -3.543 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.047 +Data Delay : 1.867 + +Slack : -3.443 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.775 + +Slack : -3.443 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.775 + +Slack : -3.443 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.775 + +Slack : -3.443 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.775 + +Slack : -3.443 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.775 + +Slack : -3.164 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.031 +Data Delay : 1.504 + +Slack : -2.953 +From Node : AUD_ADCDAT +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.285 + +Slack : 18.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.250 +Data Delay : 1.915 + +Slack : 18.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.250 +Data Delay : 1.915 + +Slack : 18.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.250 +Data Delay : 1.915 + +Slack : 18.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.250 +Data Delay : 1.915 + +Slack : 18.681 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.249 +Data Delay : 1.908 + +Slack : 18.681 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.249 +Data Delay : 1.908 + +Slack : 18.681 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.249 +Data Delay : 1.908 + +Slack : 18.720 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.250 +Data Delay : 1.868 + +Slack : 18.720 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.250 +Data Delay : 1.868 + +Slack : 18.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.828 + +Slack : 18.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.828 + +Slack : 18.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.828 + +Slack : 18.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.828 + +Slack : 18.753 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.810 + +Slack : 18.753 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.810 + +Slack : 18.753 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.810 + +Slack : 18.757 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.249 +Data Delay : 1.832 + +Slack : 18.757 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.249 +Data Delay : 1.832 + +Slack : 18.781 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.781 + +Slack : 18.781 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.781 + +Slack : 18.797 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.765 + +Slack : 18.797 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.765 + +Slack : 18.797 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.765 + +Slack : 18.797 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.765 + +Slack : 18.818 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.745 + +Slack : 18.818 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.745 + +Slack : 18.830 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.733 + +Slack : 18.830 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.733 + +Slack : 18.830 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.733 + +Slack : 18.844 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.718 + +Slack : 18.844 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.718 + +Slack : 18.861 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.701 + +Slack : 18.861 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.701 + +Slack : 18.861 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.701 + +Slack : 18.861 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.701 + +Slack : 18.881 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.682 + +Slack : 18.881 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.682 + +Slack : 18.894 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.669 + +Slack : 18.894 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.669 + +Slack : 18.894 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.669 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.654 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.654 + +Slack : 18.945 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.618 + +Slack : 18.945 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.618 + +Slack : 19.041 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.070 +Data Delay : 1.727 + +Slack : 19.041 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.070 +Data Delay : 1.727 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.062 +Data Delay : 1.724 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.062 +Data Delay : 1.724 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.062 +Data Delay : 1.724 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.062 +Data Delay : 1.724 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.062 +Data Delay : 1.724 + +Slack : 19.112 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 1.630 + +Slack : 19.112 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 1.630 + +Slack : 19.113 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.449 + +Slack : 19.113 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.449 + +Slack : 19.113 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.449 + +Slack : 19.113 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.449 + +Slack : 19.117 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.446 + +Slack : 19.117 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.446 + +Slack : 19.117 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.446 + +Slack : 19.118 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.252 +Data Delay : 1.468 + +Slack : 19.118 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.252 +Data Delay : 1.468 + +Slack : 19.118 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.252 +Data Delay : 1.468 + +Slack : 19.124 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.626 + +Slack : 19.124 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.626 + +Slack : 19.124 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.626 + +Slack : 19.124 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.626 + +Slack : 19.124 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.626 + +Slack : 19.160 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.402 + +Slack : 19.160 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.402 + +Slack : 19.165 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.271 +Data Delay : 1.355 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.394 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.394 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.394 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.393 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.393 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.393 + +Slack : 19.169 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.393 + +Slack : 19.172 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.252 +Data Delay : 1.414 + +Slack : 19.175 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 1.567 + +Slack : 19.175 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.096 +Data Delay : 1.567 + +Slack : 19.178 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.252 +Data Delay : 1.408 + +Slack : 19.180 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.380 + +Slack : 19.180 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.380 + +Slack : 19.180 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.380 + +Slack : 19.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.252 +Data Delay : 1.400 + +Slack : 19.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.563 + +Slack : 19.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.563 + +Slack : 19.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.563 + +Slack : 19.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.563 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : -2.784 +From Node : SW[2] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.423 +Clock Skew : -0.021 +Data Delay : 1.133 + +Slack : 70.890 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.046 +Data Delay : 0.540 + +Slack : 71.071 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.046 +Data Delay : 0.359 + +Slack : 71.071 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 +Clock Skew : -0.046 +Data Delay : 0.359 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 5.613 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 4.094 + +Slack : 5.705 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 4.001 + +Slack : 5.819 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.888 + +Slack : 5.826 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.242 +Data Delay : 3.872 + +Slack : 5.827 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.880 + +Slack : 5.831 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.876 + +Slack : 5.851 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.241 +Data Delay : 3.848 + +Slack : 5.911 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.795 + +Slack : 5.919 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.787 + +Slack : 5.923 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.783 + +Slack : 5.928 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.231 +Data Delay : 3.780 + +Slack : 5.987 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.720 + +Slack : 6.003 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.701 + +Slack : 6.027 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.677 + +Slack : 6.032 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.242 +Data Delay : 3.666 + +Slack : 6.034 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.670 + +Slack : 6.040 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.242 +Data Delay : 3.658 + +Slack : 6.044 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.242 +Data Delay : 3.654 + +Slack : 6.048 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.658 + +Slack : 6.048 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.658 + +Slack : 6.057 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.241 +Data Delay : 3.642 + +Slack : 6.065 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.241 +Data Delay : 3.634 + +Slack : 6.069 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.241 +Data Delay : 3.630 + +Slack : 6.072 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.813 + +Slack : 6.105 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.062 +Data Delay : 3.773 + +Slack : 6.123 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.756 + +Slack : 6.134 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.231 +Data Delay : 3.574 + +Slack : 6.142 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.231 +Data Delay : 3.566 + +Slack : 6.146 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.231 +Data Delay : 3.562 + +Slack : 6.152 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.555 + +Slack : 6.178 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.514 + +Slack : 6.193 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.514 + +Slack : 6.195 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.690 + +Slack : 6.201 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.506 + +Slack : 6.205 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.502 + +Slack : 6.209 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.495 + +Slack : 6.217 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.487 + +Slack : 6.221 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.483 + +Slack : 6.233 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.471 + +Slack : 6.240 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.464 + +Slack : 6.240 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.647 + +Slack : 6.241 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.463 + +Slack : 6.244 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.462 + +Slack : 6.245 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.459 + +Slack : 6.248 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.456 + +Slack : 6.252 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.452 + +Slack : 6.254 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.452 + +Slack : 6.254 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.452 + +Slack : 6.254 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.630 + +Slack : 6.262 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.444 + +Slack : 6.262 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.444 + +Slack : 6.265 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.246 +Data Delay : 3.429 + +Slack : 6.266 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.440 + +Slack : 6.266 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.440 + +Slack : 6.291 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.595 + +Slack : 6.291 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.595 + +Slack : 6.317 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.375 + +Slack : 6.319 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.244 +Data Delay : 3.377 + +Slack : 6.346 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.062 +Data Delay : 3.532 + +Slack : 6.355 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.530 + +Slack : 6.364 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.515 + +Slack : 6.365 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.242 +Data Delay : 3.333 + +Slack : 6.366 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.233 +Data Delay : 3.340 + +Slack : 6.371 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.234 +Data Delay : 3.334 + +Slack : 6.384 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.308 + +Slack : 6.390 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.241 +Data Delay : 3.309 + +Slack : 6.392 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.300 + +Slack : 6.396 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.296 + +Slack : 6.420 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.241 +Data Delay : 3.279 + +Slack : 6.428 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.462 + +Slack : 6.428 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.462 + +Slack : 6.433 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.454 + +Slack : 6.437 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.453 + +Slack : 6.447 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.059 +Data Delay : 3.434 + +Slack : 6.461 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.429 + +Slack : 6.467 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.231 +Data Delay : 3.241 + +Slack : 6.471 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.246 +Data Delay : 3.223 + +Slack : 6.472 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 3.410 + +Slack : 6.479 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.246 +Data Delay : 3.215 + +Slack : 6.481 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.406 + +Slack : 6.481 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.409 + +Slack : 6.483 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.246 +Data Delay : 3.211 + +Slack : 6.495 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.389 + +Slack : 6.505 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 3.384 + +Slack : 6.507 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.185 + +Slack : 6.515 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.375 + +Slack : 6.520 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.172 + +Slack : 6.523 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.181 + +Slack : 6.525 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.244 +Data Delay : 3.171 + +Slack : 6.526 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.232 +Data Delay : 3.181 + +Slack : 6.531 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.173 + +Slack : 6.532 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.217 +Data Delay : 3.238 + +Slack : 6.532 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.354 + +Slack : 6.532 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.354 + +Slack : 6.533 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.244 +Data Delay : 3.163 + +Slack : 6.537 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.244 +Data Delay : 3.159 + +Slack : 6.539 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.347 + +Slack : 6.542 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.235 +Data Delay : 3.162 + +Slack : 6.543 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 3.346 + +Slack : 6.548 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.248 +Data Delay : 3.144 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : -0.217 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.574 +Data Delay : 1.565 + +Slack : -0.133 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.576 +Data Delay : 1.651 + +Slack : 0.086 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.580 +Data Delay : 1.874 + +Slack : 0.119 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.577 +Data Delay : 1.904 + +Slack : 0.268 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.388 + +Slack : 0.376 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.412 +Data Delay : 1.996 + +Slack : 0.395 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.574 +Data Delay : 2.177 + +Slack : 0.410 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.134 + +Slack : 0.421 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.148 + +Slack : 0.430 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.414 +Data Delay : 2.052 + +Slack : 0.435 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.156 + +Slack : 0.443 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.156 + +Slack : 0.444 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.161 + +Slack : 0.444 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.171 + +Slack : 0.445 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.169 + +Slack : 0.448 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.414 +Data Delay : 2.070 + +Slack : 0.452 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.165 + +Slack : 0.453 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.177 + +Slack : 0.455 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.178 + +Slack : 0.456 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.174 + +Slack : 0.460 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.184 + +Slack : 0.460 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.183 + +Slack : 0.460 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.414 +Data Delay : 2.082 + +Slack : 0.462 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.408 +Data Delay : 2.078 + +Slack : 0.463 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.184 + +Slack : 0.465 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.182 + +Slack : 0.465 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.176 + +Slack : 0.466 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.193 + +Slack : 0.466 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.572 +Data Delay : 2.246 + +Slack : 0.477 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.199 + +Slack : 0.478 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.196 + +Slack : 0.479 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.202 + +Slack : 0.479 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.202 + +Slack : 0.479 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.576 +Data Delay : 2.263 + +Slack : 0.480 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.566 +Data Delay : 2.254 + +Slack : 0.482 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.206 + +Slack : 0.483 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.410 +Data Delay : 2.101 + +Slack : 0.483 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.206 + +Slack : 0.483 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.196 + +Slack : 0.484 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.502 +Data Delay : 2.194 + +Slack : 0.484 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.202 + +Slack : 0.485 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.502 +Data Delay : 2.195 + +Slack : 0.485 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.210 + +Slack : 0.486 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.209 + +Slack : 0.486 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.210 + +Slack : 0.487 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.565 +Data Delay : 2.260 + +Slack : 0.488 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.572 +Data Delay : 2.268 + +Slack : 0.489 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.200 + +Slack : 0.490 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.214 + +Slack : 0.493 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.504 +Data Delay : 2.205 + +Slack : 0.494 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.217 + +Slack : 0.494 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.502 +Data Delay : 2.204 + +Slack : 0.495 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.222 + +Slack : 0.497 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.564 +Data Delay : 2.269 + +Slack : 0.497 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.211 + +Slack : 0.497 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.221 + +Slack : 0.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.411 +Data Delay : 2.118 + +Slack : 0.499 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.218 + +Slack : 0.500 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.224 + +Slack : 0.500 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.223 + +Slack : 0.500 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.221 + +Slack : 0.500 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.408 +Data Delay : 2.116 + +Slack : 0.502 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.220 + +Slack : 0.502 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.227 + +Slack : 0.502 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.566 +Data Delay : 2.276 + +Slack : 0.505 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.504 +Data Delay : 2.217 + +Slack : 0.505 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.218 + +Slack : 0.505 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.218 + +Slack : 0.505 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.218 + +Slack : 0.505 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.564 +Data Delay : 2.277 + +Slack : 0.506 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.217 + +Slack : 0.506 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.520 +Data Delay : 2.234 + +Slack : 0.507 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.504 +Data Delay : 2.219 + +Slack : 0.507 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.410 +Data Delay : 2.125 + +Slack : 0.508 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.504 +Data Delay : 2.220 + +Slack : 0.508 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.504 +Data Delay : 2.220 + +Slack : 0.508 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.227 + +Slack : 0.511 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.411 +Data Delay : 2.130 + +Slack : 0.512 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.235 + +Slack : 0.513 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.224 + +Slack : 0.514 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.416 +Data Delay : 2.138 + +Slack : 0.515 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.233 + +Slack : 0.516 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.234 + +Slack : 0.517 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.240 + +Slack : 0.518 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.231 + +Slack : 0.518 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.232 + +Slack : 0.519 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.520 +Data Delay : 2.247 + +Slack : 0.519 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.420 +Data Delay : 2.147 + +Slack : 0.520 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.422 +Data Delay : 2.150 + +Slack : 0.520 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.233 + +Slack : 0.521 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.242 + +Slack : 0.522 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.249 + +Slack : 0.523 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.236 + +Slack : 0.525 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.248 + +Slack : 0.526 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.237 + +Slack : 0.526 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.240 + +Slack : 0.527 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.238 + +Slack : 0.528 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.411 +Data Delay : 2.147 + +Slack : 0.529 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.242 + +Slack : 0.530 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.244 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.177 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.307 + +Slack : 0.184 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.314 + +Slack : 0.306 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.436 + +Slack : 1.186 +From Node : SW[2] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : -0.017 +Clock Skew : 0.233 +Data Delay : 0.576 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.178 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vga_vc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.282 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.404 + +Slack : 0.292 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.421 + +Slack : 0.294 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.415 + +Slack : 0.295 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.416 + +Slack : 0.336 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.457 + +Slack : 0.408 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.530 + +Slack : 0.443 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.564 + +Slack : 0.460 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.581 + +Slack : 0.460 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.585 + +Slack : 0.461 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.591 + +Slack : 0.514 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.641 + +Slack : 0.527 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.653 + +Slack : 0.531 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.655 + +Slack : 0.566 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.688 + +Slack : 0.577 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.526 + +Slack : 0.580 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.702 + +Slack : 0.583 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.705 + +Slack : 0.584 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.533 + +Slack : 0.591 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.540 + +Slack : 0.606 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.731 + +Slack : 0.606 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.727 + +Slack : 0.616 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.150 +Data Delay : 0.550 + +Slack : 0.642 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.152 +Data Delay : 0.574 + +Slack : 0.645 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.769 + +Slack : 0.645 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.152 +Data Delay : 0.577 + +Slack : 0.648 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.773 + +Slack : 0.649 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.774 + +Slack : 0.649 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.968 + +Slack : 0.654 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.779 + +Slack : 0.659 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.608 + +Slack : 0.659 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.780 + +Slack : 0.663 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.790 + +Slack : 0.665 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.614 + +Slack : 0.665 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.792 + +Slack : 0.669 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.618 + +Slack : 0.673 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.150 +Data Delay : 0.607 + +Slack : 0.673 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.800 + +Slack : 0.673 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.800 + +Slack : 0.676 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.803 + +Slack : 0.677 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.151 +Data Delay : 0.610 + +Slack : 0.678 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.150 +Data Delay : 0.612 + +Slack : 0.679 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.806 + +Slack : 0.683 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.150 +Data Delay : 0.617 + +Slack : 0.684 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.806 + +Slack : 0.687 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.151 +Data Delay : 0.620 + +Slack : 0.701 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.828 + +Slack : 0.701 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.828 + +Slack : 0.704 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.236 +Data Delay : 1.024 + +Slack : 0.707 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.830 + +Slack : 0.711 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.135 +Data Delay : 0.660 + +Slack : 0.727 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.853 + +Slack : 0.729 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.853 + +Slack : 0.738 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.865 + +Slack : 0.739 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.866 + +Slack : 0.740 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.865 + +Slack : 0.741 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.868 + +Slack : 0.742 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.868 + +Slack : 0.745 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.872 + +Slack : 0.750 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.236 +Data Delay : 1.070 + +Slack : 0.751 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.878 + +Slack : 0.755 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.236 +Data Delay : 1.075 + +Slack : 0.755 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.882 + +Slack : 0.756 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.883 + +Slack : 0.759 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.886 + +Slack : 0.761 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.888 + +Slack : 0.764 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.891 + +Slack : 0.790 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.914 + +Slack : 0.791 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.236 +Data Delay : 1.111 + +Slack : 0.802 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.151 +Data Delay : 0.735 + +Slack : 0.804 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.931 + +Slack : 0.808 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.929 + +Slack : 0.808 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.932 + +Slack : 0.809 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.934 + +Slack : 0.810 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.151 +Data Delay : 0.743 + +Slack : 0.813 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.151 +Data Delay : 0.746 + +Slack : 0.813 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.040 +Data Delay : 0.937 + +Slack : 0.816 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.937 + +Slack : 0.821 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.942 + +Slack : 0.822 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.949 + +Slack : 0.827 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.954 + +Slack : 0.832 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.958 + +Slack : 0.832 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.958 + +Slack : 0.832 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.959 + +Slack : 0.832 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.959 + +Slack : 0.835 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.957 + +Slack : 0.842 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.043 +Data Delay : 0.969 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.178 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.307 + +Slack : 0.178 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.307 + +Slack : 0.179 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.307 + +Slack : 0.184 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.313 + +Slack : 0.184 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.313 + +Slack : 0.184 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.314 + +Slack : 0.185 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.185 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.185 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.185 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.185 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.185 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.315 + +Slack : 0.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.314 + +Slack : 0.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.317 + +Slack : 0.187 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.316 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.193 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.314 + +Slack : 0.199 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.327 + +Slack : 0.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.333 + +Slack : 0.217 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.337 + +Slack : 0.254 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.375 + +Slack : 0.277 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.397 + +Slack : 0.281 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.394 + +Slack : 0.284 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.413 + +Slack : 0.285 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.414 + +Slack : 0.287 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.416 + +Slack : 0.288 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.417 + +Slack : 0.288 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.417 + +Slack : 0.288 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.419 + +Slack : 0.288 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.419 + +Slack : 0.289 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.420 + +Slack : 0.296 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.425 + +Slack : 0.298 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.300 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.421 + +Slack : 0.305 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.306 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.427 + +Slack : 0.307 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.435 + +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.428 + +Slack : 0.308 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.437 + +Slack : 0.310 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.431 + +Slack : 0.310 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.226 +Data Delay : 0.620 + +Slack : 0.316 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.444 + +Slack : 0.317 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.437 + +Slack : 0.319 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.447 + +Slack : 0.321 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.441 + +Slack : 0.323 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.451 + +Slack : 0.325 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.446 + +Slack : 0.327 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.448 + +Slack : 0.332 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.452 + +Slack : 0.333 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.461 + +Slack : 0.334 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.455 + +Slack : 0.340 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.469 + +Slack : 0.354 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.072 +Data Delay : 0.510 + +Slack : 0.362 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.482 + +Slack : 0.367 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.498 + +Slack : 0.368 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.028 +Data Delay : 0.480 + +Slack : 0.379 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.500 + +Slack : 0.382 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.028 +Data Delay : 0.494 + +Slack : 0.391 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.511 + +Slack : 0.396 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.243 +Data Delay : 0.723 + +Slack : 0.408 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.528 + +Slack : 0.410 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.226 +Data Delay : 0.720 + +Slack : 0.429 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.542 + +Slack : 0.437 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.568 + +Slack : 0.438 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.569 + +Slack : 0.440 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.563 + +Slack : 0.442 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.563 + +Slack : 0.444 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.573 + +Slack : 0.444 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.567 + +Slack : 0.444 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.573 + +Slack : 0.446 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.577 + +Slack : 0.447 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + +Slack : 0.448 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.571 + +Slack : 0.448 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.569 + +Slack : 0.448 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.577 + +Slack : 0.449 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.580 + +Slack : 0.450 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.579 + +Slack : 0.450 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.573 + +Slack : 0.450 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.573 + +Slack : 0.454 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.577 + +Slack : 0.454 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.454 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.456 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.584 + +Slack : 0.457 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.460 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.589 + +Slack : 0.460 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.581 + +Slack : 0.465 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.593 + +Slack : 0.466 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.152 +Data Delay : 0.398 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.186 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.193 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.197 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.318 + +Slack : 0.227 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.348 + +Slack : 0.270 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.391 + +Slack : 0.295 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.416 + +Slack : 0.297 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.297 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.297 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.298 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.298 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.298 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.300 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.421 + +Slack : 0.304 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.304 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.304 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.306 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.427 + +Slack : 0.306 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.427 + +Slack : 0.307 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.428 + +Slack : 0.308 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.429 + +Slack : 0.357 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.478 + +Slack : 0.445 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.566 + +Slack : 0.446 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + +Slack : 0.446 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + +Slack : 0.446 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + +Slack : 0.447 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + +Slack : 0.447 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + +Slack : 0.448 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.569 + +Slack : 0.453 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.574 + +Slack : 0.454 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.454 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.455 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.576 + +Slack : 0.455 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.576 + +Slack : 0.456 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.577 + +Slack : 0.456 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.577 + +Slack : 0.457 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.457 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.458 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.579 + +Slack : 0.458 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.579 + +Slack : 0.459 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.580 + +Slack : 0.459 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.580 + +Slack : 0.460 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.581 + +Slack : 0.461 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.582 + +Slack : 0.463 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.584 + +Slack : 0.463 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.584 + +Slack : 0.464 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.585 + +Slack : 0.464 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.585 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.467 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.588 + +Slack : 0.467 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.588 + +Slack : 0.475 +From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.596 + +Slack : 0.508 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.629 + +Slack : 0.509 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.630 + +Slack : 0.509 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.630 + +Slack : 0.510 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.631 + +Slack : 0.510 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.631 + +Slack : 0.511 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.632 + +Slack : 0.512 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.633 + +Slack : 0.512 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.633 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.634 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.634 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.637 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.637 + +Slack : 0.517 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.638 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.639 + +Slack : 0.519 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.640 + +Slack : 0.520 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.520 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.521 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.642 + +Slack : 0.521 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.642 + +Slack : 0.522 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.643 + +Slack : 0.523 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.644 + +Slack : 0.524 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.645 + +Slack : 0.524 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.645 + +Slack : 0.526 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.647 + +Slack : 0.527 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.648 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.530 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.651 + +Slack : 0.530 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.651 + +Slack : 0.531 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.652 + +Slack : 0.531 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.652 + +Slack : 0.532 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.653 + +Slack : 0.532 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.653 + +Slack : 0.532 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.653 + +Slack : 0.533 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.654 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : -4.694 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.228 +Data Delay : 2.789 + +Slack : -4.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.225 +Data Delay : 2.791 + +Slack : -4.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.789 + +Slack : -4.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.230 +Data Delay : 2.786 + +Slack : -4.692 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.789 + +Slack : -4.583 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.248 +Data Delay : 2.659 + +Slack : -4.575 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.251 +Data Delay : 2.648 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.580 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.580 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.580 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.213 +Data Delay : 2.588 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.572 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.574 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.574 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.574 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.574 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.574 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.574 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.580 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.580 + +Slack : -4.430 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.580 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.574 + +Slack : -4.429 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.571 + +Slack : -4.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.047 +Data Delay : 2.580 + +Slack : -4.254 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.586 + +Slack : -4.250 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.047 +Data Delay : 2.574 + +Slack : -4.250 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.047 +Data Delay : 2.574 + +Slack : -4.242 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.574 + +Slack : -4.242 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.574 + +Slack : -4.242 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.574 + +Slack : -4.242 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.574 + +Slack : -4.242 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.574 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.031 +Data Delay : 2.581 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.038 +Data Delay : 2.574 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.573 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.038 +Data Delay : 2.574 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.038 +Data Delay : 2.574 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.573 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.573 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.573 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.241 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.032 +Data Delay : 2.580 + +Slack : -4.240 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.037 +Data Delay : 2.574 + +Slack : -4.240 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.037 +Data Delay : 2.574 + +Slack : -4.234 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.031 +Data Delay : 2.574 + +Slack : -4.234 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.031 +Data Delay : 2.574 + +Slack : -4.234 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.031 +Data Delay : 2.574 + +Slack : -4.234 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.031 +Data Delay : 2.574 + +Slack : -4.227 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : -0.023 +Data Delay : 2.572 + +Slack : -4.202 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.002 +Data Delay : 2.572 + +Slack : -4.202 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.002 +Data Delay : 2.572 + +Slack : -4.202 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.002 +Data Delay : 2.572 + +Slack : -4.202 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.002 +Data Delay : 2.572 + +Slack : -4.202 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.002 +Data Delay : 2.572 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 2.518 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.257 +Data Delay : 1.946 + +Slack : 2.518 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.257 +Data Delay : 1.946 + +Slack : 2.518 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.257 +Data Delay : 1.946 + +Slack : 2.518 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.257 +Data Delay : 1.946 + +Slack : 2.518 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.257 +Data Delay : 1.946 + +Slack : 2.544 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.231 +Data Delay : 1.946 + +Slack : 2.557 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 1.947 + +Slack : 2.557 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 1.947 + +Slack : 2.557 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 1.947 + +Slack : 2.557 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 1.947 + +Slack : 2.563 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.214 +Data Delay : 1.945 + +Slack : 2.563 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.214 +Data Delay : 1.945 + +Slack : 2.563 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.214 +Data Delay : 1.945 + +Slack : 2.563 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.214 +Data Delay : 1.945 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.215 +Data Delay : 1.947 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.215 +Data Delay : 1.947 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.215 +Data Delay : 1.947 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.215 +Data Delay : 1.947 + +Slack : 2.564 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.215 +Data Delay : 1.947 + +Slack : 2.566 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.947 + +Slack : 2.566 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.947 + +Slack : 2.566 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.947 + +Slack : 2.566 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.947 + +Slack : 2.566 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.947 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 1.957 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.567 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.221 +Data Delay : 1.956 + +Slack : 2.574 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.205 +Data Delay : 1.947 + +Slack : 2.574 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.205 +Data Delay : 1.947 + +Slack : 2.579 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.214 +Data Delay : 1.961 + +Slack : 2.582 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.205 +Data Delay : 1.955 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.761 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.947 + +Slack : 2.762 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.024 +Data Delay : 1.955 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.024 +Data Delay : 1.955 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.024 +Data Delay : 1.955 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.032 +Data Delay : 1.963 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.946 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.024 +Data Delay : 1.955 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.024 +Data Delay : 1.955 + +Slack : 2.763 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.024 +Data Delay : 1.955 + +Slack : 2.897 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : -0.019 +Data Delay : 2.020 + +Slack : 2.902 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : -0.016 +Data Delay : 2.028 + +Slack : 3.008 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.009 +Data Delay : 2.157 + +Slack : 3.008 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.007 +Data Delay : 2.155 + +Slack : 3.008 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.007 +Data Delay : 2.155 + +Slack : 3.008 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.004 +Data Delay : 2.152 + +Slack : 3.011 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.005 +Data Delay : 2.156 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.796 +Actual Width : 4.980 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.796 +Actual Width : 4.980 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.796 +Actual Width : 4.980 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.796 +Actual Width : 4.980 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.796 +Actual Width : 4.980 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.801 +Actual Width : 5.017 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.801 +Actual Width : 5.017 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.801 +Actual Width : 5.017 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.801 +Actual Width : 5.017 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.801 +Actual Width : 5.017 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[3] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[6] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[0] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 20.600 +Actual Width : 20.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] + +Slack : 20.600 +Actual Width : 20.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] + +Slack : 20.600 +Actual Width : 20.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] + +Slack : 20.600 +Actual Width : 20.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] + +Slack : 20.600 +Actual Width : 20.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] + +Slack : 20.610 +Actual Width : 20.826 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Fall +Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.643 +Actual Width : 20.827 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.643 +Actual Width : 20.827 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.643 +Actual Width : 20.827 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.644 +Actual Width : 20.828 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.644 +Actual Width : 20.828 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.644 +Actual Width : 20.828 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.644 +Actual Width : 20.828 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.648 +Actual Width : 20.832 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.649 +Actual Width : 20.865 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] + +Slack : 20.649 +Actual Width : 20.865 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] + +Slack : 20.650 +Actual Width : 20.866 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.650 +Actual Width : 20.834 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] + +Slack : 20.651 +Actual Width : 20.835 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.656 +Actual Width : 20.872 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 35.535 +Actual Width : 35.719 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.535 +Actual Width : 35.719 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] + +Slack : 35.552 +Actual Width : 35.768 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.552 +Actual Width : 35.768 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] + +Slack : 35.715 +Actual Width : 35.715 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.715 +Actual Width : 35.715 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.739 +Actual Width : 35.739 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] + +Slack : 35.739 +Actual Width : 35.739 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk + +Slack : 35.749 +Actual Width : 35.749 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] + +Slack : 35.749 +Actual Width : 35.749 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk + +Slack : 35.774 +Actual Width : 35.774 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.774 +Actual Width : 35.774 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 69.489 +Actual Width : 71.489 +Required Width : 2.000 +Type : Min Period +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 69.489 +Actual Width : 71.489 +Required Width : 2.000 +Type : Min Period +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Setup Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 0.740 +Fall : 1.482 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.804 +Fall : 2.519 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : 0.623 +Fall : 1.147 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : 0.623 +Fall : 1.147 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : 0.719 +Fall : 1.317 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 1.573 +Fall : 2.137 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Hold Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -0.493 +Fall : -1.222 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.255 +Fall : -1.937 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : -0.259 +Fall : -0.787 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : -0.259 +Fall : -0.787 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : -0.358 +Fall : -0.948 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : -0.536 +Fall : -1.090 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.313 +Fall : 6.460 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.793 +Fall : 5.876 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.759 +Fall : 6.041 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.594 +Fall : 5.678 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.806 +Fall : 5.971 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.201 +Fall : 6.318 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.089 +Fall : 6.240 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.227 +Fall : 6.385 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.313 +Fall : 6.460 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 6.125 +Fall : 6.276 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 5.865 +Fall : 5.971 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 5.734 +Fall : 6.023 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 5.802 +Fall : 5.888 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 5.700 +Fall : 5.827 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 6.047 +Fall : 6.179 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 5.913 +Fall : 6.016 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 6.125 +Fall : 6.276 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 5.968 +Fall : 6.044 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 2.060 +Fall : 1.988 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 2.060 +Fall : 1.988 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.000 +Fall : 1.945 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.000 +Fall : 1.945 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.001 +Fall : 1.946 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 1.979 +Fall : 1.928 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 2.060 +Fall : 1.988 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 2.052 +Fall : 1.980 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 2.055 +Fall : 1.983 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 1.977 +Fall : 1.926 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 1.998 +Fall : 1.943 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 2.053 +Fall : 1.981 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.820 +Fall : 3.760 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.349 +Fall : 3.460 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.570 +Fall : 3.712 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.422 +Fall : 3.554 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.576 +Fall : 3.760 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.576 +Fall : 3.720 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.545 +Fall : 3.681 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.508 +Fall : 3.637 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.578 +Fall : 3.734 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 3.818 +Fall : 3.711 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 3.820 +Fall : 3.713 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 3.557 +Fall : 3.474 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 3.557 +Fall : 3.474 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 3.745 +Fall : 3.658 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 3.565 +Fall : 3.478 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 3.565 +Fall : 3.478 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 3.554 +Fall : 3.493 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 2.053 +Fall : 1.981 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 2.057 +Fall : 1.985 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 3.958 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 3.905 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.782 +Fall : 4.918 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.665 +Fall : 4.838 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.507 +Fall : 4.626 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.218 +Fall : 4.314 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.638 +Fall : 4.810 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.496 +Fall : 4.607 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.646 +Fall : 4.769 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.693 +Fall : 4.865 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.782 +Fall : 4.918 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 4.737 +Fall : 4.933 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.737 +Fall : 4.933 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.482 +Fall : 4.608 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.426 +Fall : 4.524 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.532 +Fall : 4.666 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.342 +Fall : 4.468 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.470 +Fall : 4.545 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 4.591 +Fall : 4.756 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 4.437 +Fall : 4.502 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 5.003 +Fall : 4.766 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 5.003 +Fall : 4.766 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 3.568 +Fall : 3.592 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 3.684 +Fall : 3.701 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 3.827 +Fall : 3.886 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 3.834 +Fall : 3.845 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 3.832 +Fall : 3.845 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 3.834 +Fall : 3.845 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 3.780 +Fall : 3.775 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 3.773 +Fall : 3.767 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 1.713 +Fall : 1.658 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 3.857 +Fall : 3.939 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 3.857 +Fall : 3.939 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 3.847 +Fall : 3.908 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 3.617 +Fall : 3.642 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 3.834 +Fall : 3.914 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 1.712 +Fall : 1.657 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 1.709 +Fall : 1.654 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 1.708 +Fall : 1.653 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 1.713 +Fall : 1.658 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 3.245 +Fall : 2.951 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 1.711 +Fall : 1.656 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 1.755 +Fall : 1.683 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 1.758 +Fall : 1.686 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.636 +Fall : 4.726 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.640 +Fall : 4.735 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.729 +Fall : 4.863 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.651 +Fall : 4.726 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.847 +Fall : 5.000 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.636 +Fall : 4.761 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.103 +Fall : 5.241 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.028 +Fall : 5.231 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.163 +Fall : 5.298 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 4.485 +Fall : 4.625 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.709 +Fall : 4.827 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.704 +Fall : 4.844 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.854 +Fall : 4.932 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.750 +Fall : 4.865 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.485 +Fall : 4.625 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.955 +Fall : 5.045 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 4.927 +Fall : 5.124 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 4.836 +Fall : 4.901 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 1.748 +Fall : 1.693 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 1.726 +Fall : 1.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 1.802 +Fall : 1.731 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 2.853 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.001 +Fall : 3.106 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.215 +Fall : 3.348 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.066 +Fall : 3.192 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.216 +Fall : 3.391 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.218 +Fall : 3.357 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.190 +Fall : 3.318 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.119 +Fall : 3.241 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.217 +Fall : 3.365 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 3.104 +Fall : 3.018 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 3.106 +Fall : 3.020 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 2.853 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 2.853 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 3.034 +Fall : 2.967 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 2.861 +Fall : 2.794 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 2.861 +Fall : 2.794 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 2.854 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 1.804 +Fall : 1.733 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 3.708 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 3.654 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.332 +Fall : 3.501 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.950 +Fall : 4.038 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.771 +Fall : 3.883 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.594 +Fall : 3.709 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.332 +Fall : 3.501 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.790 +Fall : 3.904 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.836 +Fall : 3.962 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.571 +Fall : 3.727 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.884 +Fall : 4.010 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 3.235 +Fall : 3.366 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.019 +Fall : 4.130 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 3.746 +Fall : 3.864 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 3.797 +Fall : 3.915 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 3.235 +Fall : 3.366 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 3.639 +Fall : 3.768 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 3.688 +Fall : 3.766 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 3.470 +Fall : 3.620 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 3.557 +Fall : 3.613 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 2.226 +Fall : 2.220 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 3.678 +Fall : 3.431 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 2.226 +Fall : 2.220 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 2.350 +Fall : 2.357 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 2.488 +Fall : 2.534 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 2.288 +Fall : 2.300 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 2.344 +Fall : 2.375 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 2.347 +Fall : 2.375 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 2.295 +Fall : 2.308 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 2.288 +Fall : 2.300 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 1.471 +Fall : 1.416 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 2.270 +Fall : 2.287 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 2.500 +Fall : 2.572 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 2.589 +Fall : 2.650 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 2.270 +Fall : 2.287 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 2.479 +Fall : 2.548 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 1.469 +Fall : 1.414 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 1.467 +Fall : 1.412 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 1.465 +Fall : 1.410 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 1.470 +Fall : 1.415 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 3.002 +Fall : 2.708 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 1.469 +Fall : 1.414 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 1.513 +Fall : 1.442 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 1.516 +Fall : 1.445 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 2.818 +RF : +FR : +FF : 3.181 + +Input Port : SW[2] +Output Port : LED[2] +RR : 2.437 +RF : +FR : +FF : 2.866 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 4.009 +RF : +FR : +FF : 4.744 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 3.890 +RF : +FR : +FF : 4.614 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 2.537 +RF : +FR : +FF : 3.122 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 2.732 +RF : +FR : +FF : 3.100 + +Input Port : SW[2] +Output Port : LED[2] +RR : 2.366 +RF : +FR : +FF : 2.798 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 3.874 +RF : +FR : +FF : 4.602 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 3.757 +RF : +FR : +FF : 4.474 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 2.458 +RF : +FR : +FF : 3.039 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.442 +Fall : 3.368 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.544 +Fall : 3.451 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.544 +Fall : 3.451 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.443 +Fall : 3.369 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.578 +Fall : 3.513 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.486 +Fall : 3.393 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.475 +Fall : 3.382 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.475 +Fall : 3.382 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.442 +Fall : 3.368 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 2.757 +Fall : 2.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 2.865 +Fall : 2.772 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 2.865 +Fall : 2.772 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 2.759 +Fall : 2.685 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 2.895 +Fall : 2.830 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 2.809 +Fall : 2.716 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 2.799 +Fall : 2.706 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 2.799 +Fall : 2.706 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 2.757 +Fall : 2.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.504 +1 to Hi-Z : 3.578 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.584 +1 to Hi-Z : 3.677 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.584 +1 to Hi-Z : 3.677 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.508 +1 to Hi-Z : 3.582 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.677 +1 to Hi-Z : 3.742 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.520 +1 to Hi-Z : 3.613 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.515 +1 to Hi-Z : 3.608 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.515 +1 to Hi-Z : 3.608 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.504 +1 to Hi-Z : 3.578 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.800 +1 to Hi-Z : 2.874 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.885 +1 to Hi-Z : 2.978 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.885 +1 to Hi-Z : 2.978 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.804 +1 to Hi-Z : 2.878 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.973 +1 to Hi-Z : 3.038 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.824 +1 to Hi-Z : 2.917 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.819 +1 to Hi-Z : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.819 +1 to Hi-Z : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.800 +1 to Hi-Z : 2.874 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++--------------------------------------------------------------------------------+ +Clock : Worst-case Slack +Setup : -18.257 +Hold : -0.217 +Recovery : -6.225 +Removal : 2.518 +Minimum Pulse Width : 4.746 + +Clock : CLOCK_50 +Setup : -18.257 +Hold : -0.217 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 9.208 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Setup : 2.500 +Hold : 0.186 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 4.746 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Setup : -7.550 +Hold : 0.178 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 19.597 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Setup : -2.914 +Hold : 0.177 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 35.491 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Setup : -4.737 +Hold : 0.178 +Recovery : -6.225 +Removal : 2.518 +Minimum Pulse Width : 20.589 + +Clock : Design-wide TNS +Setup : -1145.21 +Hold : -0.35 +Recovery : -455.695 +Removal : 0.0 +Minimum Pulse Width : 0.0 + +Clock : CLOCK_50 +Setup : -809.639 +Hold : -0.350 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Setup : 0.000 +Hold : 0.000 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Setup : -292.429 +Hold : 0.000 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Setup : -2.914 +Hold : 0.000 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Setup : -40.228 +Hold : 0.000 +Recovery : -455.695 +Removal : 0.000 +Minimum Pulse Width : 0.000 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Setup Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 1.512 +Fall : 1.781 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 3.245 +Fall : 3.515 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : 1.011 +Fall : 1.277 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : 1.011 +Fall : 1.277 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : 1.263 +Fall : 1.501 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.820 +Fall : 3.101 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Hold Times ; ++--------------------------------------------------------------------------------+ +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -0.493 +Fall : -1.222 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -1.255 +Fall : -1.937 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : SW[*] +Clock Port : CLOCK_50 +Rise : -0.259 +Fall : -0.592 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : SW[2] +Clock Port : CLOCK_50 +Rise : -0.259 +Fall : -0.592 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + +Data Port : AUD_ADCDAT +Clock Port : CLOCK_50 +Rise : -0.358 +Fall : -0.775 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : -0.536 +Fall : -1.078 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 10.793 +Fall : 10.789 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 9.931 +Fall : 9.913 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 9.959 +Fall : 10.101 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 9.579 +Fall : 9.547 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 10.004 +Fall : 10.080 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 10.661 +Fall : 10.706 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 10.516 +Fall : 10.623 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 10.720 +Fall : 10.719 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 10.793 +Fall : 10.789 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 10.560 +Fall : 10.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 10.028 +Fall : 10.042 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 9.968 +Fall : 10.109 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 9.866 +Fall : 9.872 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 9.785 +Fall : 9.851 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 10.384 +Fall : 10.396 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 10.128 +Fall : 10.166 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 10.560 +Fall : 10.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 10.152 +Fall : 10.092 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 3.321 +Fall : 3.234 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 3.296 +Fall : 3.214 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 3.416 +Fall : 3.331 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.419 +Fall : 3.334 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 3.294 +Fall : 3.212 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.417 +Fall : 3.332 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.411 +Fall : 6.384 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.780 +Fall : 5.845 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.176 +Fall : 6.240 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.956 +Fall : 5.950 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 6.111 +Fall : 6.220 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.151 +Fall : 6.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.145 +Fall : 6.180 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.074 +Fall : 6.119 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.150 +Fall : 6.186 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 6.401 +Fall : 6.369 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 6.411 +Fall : 6.384 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 5.985 +Fall : 5.938 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 5.985 +Fall : 5.938 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 6.305 +Fall : 6.309 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 5.992 +Fall : 5.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 5.992 +Fall : 5.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 6.005 +Fall : 5.971 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.417 +Fall : 3.332 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.423 +Fall : 3.338 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.576 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.505 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 8.268 +Fall : 8.331 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 8.040 +Fall : 8.140 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.800 +Fall : 7.856 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 7.312 +Fall : 7.306 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.984 +Fall : 8.035 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 7.683 +Fall : 7.767 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 8.090 +Fall : 8.178 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 8.141 +Fall : 8.187 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 8.268 +Fall : 8.331 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 8.137 +Fall : 8.269 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 8.137 +Fall : 8.269 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.809 +Fall : 7.864 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 7.599 +Fall : 7.631 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.765 +Fall : 7.806 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.406 +Fall : 7.457 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 7.702 +Fall : 7.721 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.981 +Fall : 8.036 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 7.627 +Fall : 7.634 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 8.089 +Fall : 7.827 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 8.089 +Fall : 7.827 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 6.289 +Fall : 6.217 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 6.465 +Fall : 6.464 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 6.666 +Fall : 6.710 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 6.731 +Fall : 6.659 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 6.731 +Fall : 6.656 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 6.730 +Fall : 6.659 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 6.646 +Fall : 6.554 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 6.632 +Fall : 6.539 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 2.863 +Fall : 2.776 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 6.755 +Fall : 6.797 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 6.714 +Fall : 6.797 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 6.755 +Fall : 6.698 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 6.322 +Fall : 6.341 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 6.698 +Fall : 6.778 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 2.861 +Fall : 2.774 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 2.859 +Fall : 2.772 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 2.858 +Fall : 2.771 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 2.862 +Fall : 2.775 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 4.881 +Fall : 4.517 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 2.860 +Fall : 2.773 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 2.951 +Fall : 2.866 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 2.953 +Fall : 2.868 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.636 +Fall : 4.726 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.640 +Fall : 4.735 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.729 +Fall : 4.863 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.651 +Fall : 4.726 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.847 +Fall : 5.000 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.636 +Fall : 4.761 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.103 +Fall : 5.241 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.028 +Fall : 5.231 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.163 +Fall : 5.298 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 4.485 +Fall : 4.625 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.709 +Fall : 4.827 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.704 +Fall : 4.844 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.854 +Fall : 4.932 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.750 +Fall : 4.865 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.485 +Fall : 4.625 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.955 +Fall : 5.045 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 4.927 +Fall : 5.124 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 4.836 +Fall : 4.901 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 1.748 +Fall : 1.693 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 1.726 +Fall : 1.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 1.802 +Fall : 1.731 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 2.853 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.001 +Fall : 3.106 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.215 +Fall : 3.348 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.066 +Fall : 3.192 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.216 +Fall : 3.391 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.218 +Fall : 3.357 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.190 +Fall : 3.318 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.119 +Fall : 3.241 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.217 +Fall : 3.365 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 3.104 +Fall : 3.018 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 3.106 +Fall : 3.020 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 2.853 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 2.853 +Fall : 2.790 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 3.034 +Fall : 2.967 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 2.861 +Fall : 2.794 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 2.861 +Fall : 2.794 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 2.854 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 1.804 +Fall : 1.733 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 3.708 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 3.654 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.332 +Fall : 3.501 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.950 +Fall : 4.038 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.771 +Fall : 3.883 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.594 +Fall : 3.709 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.332 +Fall : 3.501 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.790 +Fall : 3.904 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.836 +Fall : 3.962 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.571 +Fall : 3.727 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.884 +Fall : 4.010 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 3.235 +Fall : 3.366 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.019 +Fall : 4.130 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 3.746 +Fall : 3.864 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 3.797 +Fall : 3.915 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 3.235 +Fall : 3.366 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 3.639 +Fall : 3.768 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 3.688 +Fall : 3.766 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 3.470 +Fall : 3.620 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 3.557 +Fall : 3.613 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[*] +Clock Port : CLOCK_50 +Rise : 2.226 +Fall : 2.220 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[0] +Clock Port : CLOCK_50 +Rise : 3.678 +Fall : 3.431 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[1] +Clock Port : CLOCK_50 +Rise : 2.226 +Fall : 2.220 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[2] +Clock Port : CLOCK_50 +Rise : 2.350 +Fall : 2.357 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_B[3] +Clock Port : CLOCK_50 +Rise : 2.488 +Fall : 2.534 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[*] +Clock Port : CLOCK_50 +Rise : 2.288 +Fall : 2.300 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[0] +Clock Port : CLOCK_50 +Rise : 2.344 +Fall : 2.375 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[1] +Clock Port : CLOCK_50 +Rise : 2.347 +Fall : 2.375 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[2] +Clock Port : CLOCK_50 +Rise : 2.295 +Fall : 2.308 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_G[3] +Clock Port : CLOCK_50 +Rise : 2.288 +Fall : 2.300 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_HS +Clock Port : CLOCK_50 +Rise : 1.471 +Fall : 1.416 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[*] +Clock Port : CLOCK_50 +Rise : 2.270 +Fall : 2.287 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[0] +Clock Port : CLOCK_50 +Rise : 2.500 +Fall : 2.572 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[1] +Clock Port : CLOCK_50 +Rise : 2.589 +Fall : 2.650 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[2] +Clock Port : CLOCK_50 +Rise : 2.270 +Fall : 2.287 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_R[3] +Clock Port : CLOCK_50 +Rise : 2.479 +Fall : 2.548 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : VGA_VS +Clock Port : CLOCK_50 +Rise : 1.469 +Fall : 1.414 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : AUD_ADCLRCK +Clock Port : CLOCK_50 +Rise : 1.467 +Fall : 1.412 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_BCLK +Clock Port : CLOCK_50 +Rise : 1.465 +Fall : 1.410 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACDAT +Clock Port : CLOCK_50 +Rise : 1.470 +Fall : 1.415 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_DACLRCK +Clock Port : CLOCK_50 +Rise : 3.002 +Fall : 2.708 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : AUD_XCK +Clock Port : CLOCK_50 +Rise : 1.469 +Fall : 1.414 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SCLK +Clock Port : CLOCK_50 +Rise : 1.513 +Fall : 1.442 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + +Data Port : I2C_SDAT +Clock Port : CLOCK_50 +Rise : 1.516 +Fall : 1.445 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 4.628 +RF : +FR : +FF : 4.693 + +Input Port : SW[2] +Output Port : LED[2] +RR : 4.044 +RF : +FR : +FF : 4.195 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.977 +RF : +FR : +FF : 7.192 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.783 +RF : +FR : +FF : 7.007 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 4.317 +RF : +FR : +FF : 4.516 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Propagation Delay ; ++--------------------------------------------------------------------------------+ +Input Port : SW[1] +Output Port : LED[0] +RR : 2.732 +RF : +FR : +FF : 3.100 + +Input Port : SW[2] +Output Port : LED[2] +RR : 2.366 +RF : +FR : +FF : 2.798 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 3.874 +RF : +FR : +FF : 4.602 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 3.757 +RF : +FR : +FF : 4.474 + +Input Port : raw_loader_in +Output Port : LED[3] +RR : 2.458 +RF : +FR : +FF : 3.039 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------------------------------------------------------------------------+ +Pin : LED[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : LED[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : AUD_XCK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : AUD_ADCLRCK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : AUD_DACLRCK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : AUD_BCLK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : AUD_DACDAT +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_R[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_R[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_R[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_R[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_G[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_G[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_G[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_G[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_B[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_B[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_B[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_B[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_HS +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : VGA_VS +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[8] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[9] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[10] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[11] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[12] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[13] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[14] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[15] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[16] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[17] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[18] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[19] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[20] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[21] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[22] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[23] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[24] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[25] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[26] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[27] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[28] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[29] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[30] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[31] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[32] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : GPIO_1[33] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : buzzer_out +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : I2C_SCLK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : I2C_SDAT +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : ~ALTERA_DCLK~ +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : ~ALTERA_nCEO~ +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Input Transition Times ; ++--------------------------------------------------------------------------------+ +Pin : SW[0] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : SW[3] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : I2C_SCLK +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : I2C_SDAT +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : SW[1] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : SW[2] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : raw_loader_in +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : KEY[0] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : CLOCK_50 +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : PS2_DAT +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : KEY[1] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : PS2_CLK +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : AUD_ADCDAT +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : ~ALTERA_ASDO_DATA1~ +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : ~ALTERA_FLASH_nCE_nCSO~ +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : ~ALTERA_DATA0~ +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------------------------------------------------------------------------+ +Pin : LED[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0119 V +Ringback Voltage on Rise at FPGA Pin : 0.277 V +Ringback Voltage on Fall at FPGA Pin : 0.297 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0119 V +Ringback Voltage on Rise at Far-end : 0.277 V +Ringback Voltage on Fall at Far-end : 0.297 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0119 V +Ringback Voltage on Rise at FPGA Pin : 0.277 V +Ringback Voltage on Fall at FPGA Pin : 0.297 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0119 V +Ringback Voltage on Rise at Far-end : 0.277 V +Ringback Voltage on Fall at Far-end : 0.297 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_XCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_ADCLRCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_DACLRCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_BCLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_DACDAT +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_HS +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_VS +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[16] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[17] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[18] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[19] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[20] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[21] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[22] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[23] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[24] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[25] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[26] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0119 V +Ringback Voltage on Rise at FPGA Pin : 0.277 V +Ringback Voltage on Fall at FPGA Pin : 0.297 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0119 V +Ringback Voltage on Rise at Far-end : 0.277 V +Ringback Voltage on Fall at Far-end : 0.297 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[27] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[28] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[29] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[30] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[31] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[32] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[33] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : buzzer_out +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : I2C_SCLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : I2C_SDAT +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : ~ALTERA_DCLK~ +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 8.05e-09 V +Voh Max at FPGA Pin : 3.21 V +Vol Min at FPGA Pin : -0.181 V +Ringback Voltage on Rise at FPGA Pin : 0.16 V +Ringback Voltage on Fall at FPGA Pin : 0.253 V +10-90 Rise Time at FPGA Pin : 2.77e-10 s +90-10 Fall Time at FPGA Pin : 2.32e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : Yes +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 8.05e-09 V +Voh Max at Far-end : 3.21 V +Vol Min at Far-end : -0.181 V +Ringback Voltage on Rise at Far-end : 0.16 V +Ringback Voltage on Fall at Far-end : 0.253 V +10-90 Rise Time at Far-end : 2.77e-10 s +90-10 Fall Time at Far-end : 2.32e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : Yes + +Pin : ~ALTERA_nCEO~ +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------------------------------------------------------------------------+ +Pin : LED[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00666 V +Ringback Voltage on Rise at FPGA Pin : 0.298 V +Ringback Voltage on Fall at FPGA Pin : 0.277 V +10-90 Rise Time at FPGA Pin : 5.29e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00666 V +Ringback Voltage on Rise at Far-end : 0.298 V +Ringback Voltage on Fall at Far-end : 0.277 V +10-90 Rise Time at Far-end : 5.29e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : LED[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00666 V +Ringback Voltage on Rise at FPGA Pin : 0.298 V +Ringback Voltage on Fall at FPGA Pin : 0.277 V +10-90 Rise Time at FPGA Pin : 5.29e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00666 V +Ringback Voltage on Rise at Far-end : 0.298 V +Ringback Voltage on Fall at Far-end : 0.277 V +10-90 Rise Time at Far-end : 5.29e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : AUD_XCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : AUD_ADCLRCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : AUD_DACLRCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : AUD_BCLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : AUD_DACDAT +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_R[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_R[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_R[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_R[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_G[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_G[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_G[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_G[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_B[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_B[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_B[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_B[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_HS +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : VGA_VS +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[16] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[17] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[18] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[19] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[20] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[21] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[22] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[23] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[24] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[25] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[26] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00666 V +Ringback Voltage on Rise at FPGA Pin : 0.298 V +Ringback Voltage on Fall at FPGA Pin : 0.277 V +10-90 Rise Time at FPGA Pin : 5.29e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00666 V +Ringback Voltage on Rise at Far-end : 0.298 V +Ringback Voltage on Fall at Far-end : 0.277 V +10-90 Rise Time at Far-end : 5.29e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[27] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[28] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[29] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[30] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[31] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[32] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : GPIO_1[33] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : buzzer_out +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : I2C_SCLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : I2C_SDAT +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : ~ALTERA_DCLK~ +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.02e-06 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.124 V +Ringback Voltage on Rise at FPGA Pin : 0.134 V +Ringback Voltage on Fall at FPGA Pin : 0.323 V +10-90 Rise Time at FPGA Pin : 3.02e-10 s +90-10 Fall Time at FPGA Pin : 2.85e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.02e-06 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.124 V +Ringback Voltage on Rise at Far-end : 0.134 V +Ringback Voltage on Fall at Far-end : 0.323 V +10-90 Rise Time at Far-end : 3.02e-10 s +90-10 Fall Time at Far-end : 2.85e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : ~ALTERA_nCEO~ +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------------------------------------------------------------------------+ +Pin : LED[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0162 V +Ringback Voltage on Rise at FPGA Pin : 0.354 V +Ringback Voltage on Fall at FPGA Pin : 0.317 V +10-90 Rise Time at FPGA Pin : 3.88e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0162 V +Ringback Voltage on Rise at Far-end : 0.354 V +Ringback Voltage on Fall at Far-end : 0.317 V +10-90 Rise Time at Far-end : 3.88e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : LED[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0162 V +Ringback Voltage on Rise at FPGA Pin : 0.354 V +Ringback Voltage on Fall at FPGA Pin : 0.317 V +10-90 Rise Time at FPGA Pin : 3.88e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0162 V +Ringback Voltage on Rise at Far-end : 0.354 V +Ringback Voltage on Fall at Far-end : 0.317 V +10-90 Rise Time at Far-end : 3.88e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_XCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_ADCLRCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_DACLRCK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_BCLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : AUD_DACDAT +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_R[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_G[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_B[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_HS +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : VGA_VS +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[16] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[17] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[18] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[19] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[20] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[21] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[22] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[23] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[24] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[25] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[26] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0162 V +Ringback Voltage on Rise at FPGA Pin : 0.354 V +Ringback Voltage on Fall at FPGA Pin : 0.317 V +10-90 Rise Time at FPGA Pin : 3.88e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0162 V +Ringback Voltage on Rise at Far-end : 0.354 V +Ringback Voltage on Fall at Far-end : 0.317 V +10-90 Rise Time at Far-end : 3.88e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[27] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[28] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[29] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[30] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[31] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[32] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : GPIO_1[33] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : buzzer_out +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : I2C_SCLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : I2C_SDAT +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : ~ALTERA_DCLK~ +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 6.54e-08 V +Voh Max at FPGA Pin : 3.66 V +Vol Min at FPGA Pin : -0.258 V +Ringback Voltage on Rise at FPGA Pin : 0.41 V +Ringback Voltage on Fall at FPGA Pin : 0.318 V +10-90 Rise Time at FPGA Pin : 1.57e-10 s +90-10 Fall Time at FPGA Pin : 2.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : Yes +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 6.54e-08 V +Voh Max at Far-end : 3.66 V +Vol Min at Far-end : -0.258 V +Ringback Voltage on Rise at Far-end : 0.41 V +Ringback Voltage on Fall at Far-end : 0.318 V +10-90 Rise Time at Far-end : 1.57e-10 s +90-10 Fall Time at Far-end : 2.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : Yes + +Pin : ~ALTERA_nCEO~ +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Setup Transfers ; ++--------------------------------------------------------------------------------+ +From Clock : CLOCK_50 +To Clock : beep +RR Paths : false path +FR Paths : 0 +RF Paths : false path +FF Paths : 0 + +From Clock : beep +To Clock : CLOCK_50 +RR Paths : false path +FR Paths : false path +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : CLOCK_50 +RR Paths : 276 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : CLOCK_50 +RR Paths : 108 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] +To Clock : CLOCK_50 +RR Paths : 1 +FR Paths : 1 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +To Clock : CLOCK_50 +RR Paths : 1181 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +To Clock : CLOCK_50 +RR Paths : 7 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 1940 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 248 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 1050 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +RR Paths : 1 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +RR Paths : 3 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +RR Paths : 12 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +RR Paths : 1437 +FR Paths : 180 +RF Paths : 0 +FF Paths : 21 ++--------------------------------------------------------------------------------+ + +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------+ +; Hold Transfers ; ++--------------------------------------------------------------------------------+ +From Clock : CLOCK_50 +To Clock : beep +RR Paths : false path +FR Paths : 0 +RF Paths : false path +FF Paths : 0 + +From Clock : beep +To Clock : CLOCK_50 +RR Paths : false path +FR Paths : false path +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : CLOCK_50 +RR Paths : 276 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : CLOCK_50 +RR Paths : 108 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] +To Clock : CLOCK_50 +RR Paths : 1 +FR Paths : 1 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +To Clock : CLOCK_50 +RR Paths : 1181 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +To Clock : CLOCK_50 +RR Paths : 7 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 1940 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 248 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 1050 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +RR Paths : 1 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +RR Paths : 3 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +RR Paths : 12 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +RR Paths : 1437 +FR Paths : 180 +RF Paths : 0 +FF Paths : 21 ++--------------------------------------------------------------------------------+ + +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------+ +; Recovery Transfers ; ++--------------------------------------------------------------------------------+ +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +RR Paths : 76 +FR Paths : 0 +RF Paths : 6 +FF Paths : 0 ++--------------------------------------------------------------------------------+ + +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------+ +; Removal Transfers ; ++--------------------------------------------------------------------------------+ +From Clock : CLOCK_50 +To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +RR Paths : 76 +FR Paths : 0 +RF Paths : 6 +FF Paths : 0 ++--------------------------------------------------------------------------------+ + +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++--------------------------------------------------------------------------------+ +; Unconstrained Paths ; ++--------------------------------------------------------------------------------+ +Property : Illegal Clocks +Setup : 0 +Hold : 0 + +Property : Unconstrained Clocks +Setup : 2 +Hold : 2 + +Property : Unconstrained Input Ports +Setup : 0 +Hold : 0 + +Property : Unconstrained Input Port Paths +Setup : 0 +Hold : 0 + +Property : Unconstrained Output Ports +Setup : 0 +Hold : 0 + +Property : Unconstrained Output Port Paths +Setup : 0 +Hold : 0 ++--------------------------------------------------------------------------------+ + + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit TimeQuest Timing Analyzer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Sat Apr 2 16:35:55 2022 +Info: Command: quartus_sta spectrum -c spectrum +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332104): Reading SDC File: 'spectrum.sdc' +Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port +Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument is an empty collection + Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}] +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} + Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} +Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin +Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection + Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}] +Info (332151): Clock uncertainty is not calculated until you update the timing netlist. +Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock +Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock +Warning (332125): Found combinational loop of 509 nodes + Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~8|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~9|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~9|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|dataa" + Warning (332126): Node "z80_|alu_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~10|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~14|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~27|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~27|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~21|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~23|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~1|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa" + Warning (332126): Node "z80_|alu_|db[6]~21|datac" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datad" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|datad" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|dataa" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~20|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~10|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~26|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|dataa" + Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~33|datac" + Warning (332126): Node "z80_|alu_control_|db[4]~33|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datad" + Warning (332126): Node "z80_|alu_|db[4]~8|datab" + Warning (332126): Node "z80_|alu_|db[4]~8|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datac" + Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~14|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datac" + Warning (332126): Node "z80_|alu_|db[1]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|dataa" + Warning (332126): Node "z80_|alu_control_|db[1]~27|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~2|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" + Warning (332126): Node "z80_|alu_|db[1]~15|datab" + Warning (332126): Node "z80_|alu_|db[1]~15|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|datad" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~6|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~7|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datac" + Warning (332126): Node "z80_|alu_|db[2]~12|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~30|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~37|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datac" + Warning (332126): Node "z80_|alu_|db[2]~11|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datad" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|datad" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~16|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~7|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~0|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~0|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~1|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~1|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|datac" + Warning (332126): Node "z80_|alu_|db[3]~13|combout" + Warning (332126): Node "z80_|alu_|db[3]~14|datab" + Warning (332126): Node "z80_|alu_|db[3]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~36|combout" + Warning (332126): Node "z80_|bus_control_|db[3]~21|dataa" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~14|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|datac" + Warning (332126): Node "z80_|alu_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datac" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|datac" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~14|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~14|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~17|dataa" + Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~10|dataa" + Warning (332126): Node "z80_|alu_control_|db[0]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datac" + Warning (332126): Node "z80_|alu_|db[0]~18|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" + Warning (332126): Node "z80_|alu_|db[0]~17|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datad" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datad" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|datac" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datad" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~36|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datac" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|alu_|db[3]~14|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~6|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~1|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~15|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~33|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac" + Warning (332126): Node "z80_|alu_|db[4]~8|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~0|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|datac" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datad" + Warning (332126): Node "z80_|alu_control_|db[5]~17|datad" + Warning (332126): Node "z80_|alu_control_|db[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~17|datac" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|bus_control_|db[5]~15|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datac" + Warning (332126): Node "z80_|alu_|db[7]~19|datac" + Warning (332126): Node "z80_|alu_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|datad" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~20|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datad" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|datac" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~16|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" +Critical Warning (332081): Design contains combinational loop of 509 nodes. Estimating the delays through the loop. +Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -18.257 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -18.257 -809.639 CLOCK_50 + Info (332119): -7.550 -292.429 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.737 -40.228 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.914 -2.914 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 2.500 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is -0.026 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.026 -0.026 CLOCK_50 + Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.343 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.358 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case recovery slack is -6.225 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -6.225 -455.695 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.696 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.696 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 4.752 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 4.752 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.489 0.000 CLOCK_50 + Info (332119): 19.601 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 20.596 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -17.443 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -17.443 -768.889 CLOCK_50 + Info (332119): -6.729 -260.267 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.426 -37.694 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.785 -2.785 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 3.262 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.059 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.059 0.000 CLOCK_50 + Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.312 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case recovery slack is -5.745 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -5.745 -420.318 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.369 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.369 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 4.746 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 4.746 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.487 0.000 CLOCK_50 + Info (332119): 19.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 20.589 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info: Analyzing Fast 1200mV 0C Model +Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -14.929 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -14.929 -634.264 CLOCK_50 + Info (332119): -4.459 -174.631 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -3.773 -34.191 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 5.613 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is -0.217 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.217 -0.350 CLOCK_50 + Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.186 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case recovery slack is -4.694 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -4.694 -356.359 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 2.518 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 2.518 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 4.784 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 4.784 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.208 0.000 CLOCK_50 + Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 530 warnings + Info: Peak virtual memory: 445 megabytes + Info: Processing ended: Sat Apr 2 16:35:59 2022 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 + + diff --git a/output_files.old/spectrum.sta.summary b/output_files.old/spectrum.sta.summary new file mode 100644 index 0000000..5b55ae2 --- /dev/null +++ b/output_files.old/spectrum.sta.summary @@ -0,0 +1,209 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'CLOCK_50' +Slack : -18.257 +TNS : -809.639 + +Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : -7.550 +TNS : -292.429 + +Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -4.737 +TNS : -40.228 + +Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : -2.914 +TNS : -2.914 + +Type : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.500 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'CLOCK_50' +Slack : -0.026 +TNS : -0.026 + +Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.342 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.342 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.343 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.358 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -6.225 +TNS : -455.695 + +Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 3.696 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.752 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' +Slack : 9.489 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : 19.601 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 20.596 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 35.503 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'CLOCK_50' +Slack : -17.443 +TNS : -768.889 + +Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : -6.729 +TNS : -260.267 + +Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -4.426 +TNS : -37.694 + +Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : -2.785 +TNS : -2.785 + +Type : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 3.262 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'CLOCK_50' +Slack : 0.059 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.298 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.298 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.298 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.312 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -5.745 +TNS : -420.318 + +Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 3.369 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.746 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' +Slack : 9.487 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : 19.597 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 20.589 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 35.491 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'CLOCK_50' +Slack : -14.929 +TNS : -634.264 + +Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : -4.459 +TNS : -174.631 + +Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -3.773 +TNS : -34.191 + +Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : -2.784 +TNS : -2.784 + +Type : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 5.613 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'CLOCK_50' +Slack : -0.217 +TNS : -0.350 + +Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.177 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.178 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.178 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.186 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : -4.694 +TNS : -356.359 + +Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 2.518 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.784 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' +Slack : 9.208 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' +Slack : 19.609 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 20.600 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 35.535 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/output_files/sdram_simple.vhd b/output_files/sdram_simple.vhd new file mode 100644 index 0000000..8ba8bee --- /dev/null +++ b/output_files/sdram_simple.vhd @@ -0,0 +1,738 @@ +------------------------------------------------------ +-- FSM for a SDRAM controller +-- +-- Version 0.1 - Ready to simulate +-- +-- Author: Mike Field (hamster@snap.net.nz) +-- +-- Feel free to use it however you would like, but +-- just drop me an email to say thanks. +------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +-- library unisim; +-- use unisim.vcomponents.all; + +entity sdram_controller2 is + generic ( + HIGH_BIT: integer := 24; + MHZ: integer := 96; + REFRESH_CYCLES: integer := 4096; + ADDRESS_BITS: integer := 12 + ); + PORT ( + clock_100: in std_logic; + clock_100_delayed_3ns: in std_logic; + rst: in std_logic; + + -- Signals to/from the SDRAM chip + DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0); + DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); + DRAM_CAS_N : OUT STD_LOGIC; + DRAM_CKE : OUT STD_LOGIC; + DRAM_CLK : OUT STD_LOGIC; + DRAM_CS_N : OUT STD_LOGIC; + DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); + DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); + DRAM_RAS_N : OUT STD_LOGIC; + DRAM_WE_N : OUT STD_LOGIC; + + pending: out std_logic; + + --- Inputs from rest of the system + address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2); + req_read : IN STD_LOGIC; + req_write : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (31 downto 0); + data_out_valid : OUT STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 downto 0); + data_mask : IN STD_LOGIC_VECTOR (3 downto 0) + ); +end entity; + + +architecture rtl of sdram_controller2 is + + type reg is record + address : std_logic_vector(ADDRESS_BITS-1 downto 0); + bank : std_logic_vector( 1 downto 0); + init_counter : std_logic_vector(14 downto 0); + rf_counter : integer; + rf_pending : std_logic; + rd_pending : std_logic; + wr_pending : std_logic; + act_row : std_logic_vector(ADDRESS_BITS-1 downto 0); + act_ba : std_logic_vector(1 downto 0); + data_out_low : std_logic_vector(15 downto 0); + req_addr_q : std_logic_vector(HIGH_BIT downto 2); + req_data_write: std_logic_vector(31 downto 0); + req_mask : std_logic_vector(3 downto 0); + data_out_valid: std_logic; + dq_masks : std_logic_vector(1 downto 0); + tristate : std_logic; + end record; + + signal r : reg; + signal n : reg; + + signal rstate : std_logic_vector(8 downto 0); + signal nstate : std_logic_vector(8 downto 0); + signal rdata_write : std_logic_vector(15 downto 0); + signal ndata_write : std_logic_vector(15 downto 0); + + + -- Vectors for each SDRAM 'command' + --- CS_N, RAS_N, CAS_N, WE_N + constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; + constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. + constant cmd_write : std_logic_vector(3 downto 0) := "0100"; + constant cmd_act : std_logic_vector(3 downto 0) := "0011"; + constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. + constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; + constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set + + -- State assignments + constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000"; + + constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop; + constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre; + constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref; + constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs; + + constant s_idle_id: std_logic_vector(4 downto 0) := "00001"; + constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop; + + constant s_rf0_id: std_logic_vector(4 downto 0) := "00010"; + constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref; + + constant s_rf1_id: std_logic_vector(4 downto 0) := "00011"; + constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; + + constant s_rf2_id: std_logic_vector(4 downto 0) := "00100"; + constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; + + constant s_rf3_id: std_logic_vector(4 downto 0) := "00101"; + constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; + + constant s_rf4_id: std_logic_vector(4 downto 0) := "00110"; + constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; + + constant s_rf5_id: std_logic_vector(4 downto 0) := "00111"; + constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; + + + constant s_ra0_id: std_logic_vector(4 downto 0) := "01000"; + constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; + + constant s_ra1_id: std_logic_vector(4 downto 0) := "01001"; + constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; + + constant s_ra2_id: std_logic_vector(4 downto 0) := "01010"; + constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; + + + constant s_dr0_id: std_logic_vector(4 downto 0) := "01011"; + constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; + + constant s_dr1_id: std_logic_vector(4 downto 0) := "01100"; + constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; + + constant s_wr0_id: std_logic_vector(4 downto 0) := "01101"; + constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; + + constant s_wr1_id: std_logic_vector(4 downto 0) := "01110"; + constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; + + constant s_wr2_id: std_logic_vector(4 downto 0) := "01111"; + constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; + + constant s_wr3_id: std_logic_vector(4 downto 0) := "10000"; + constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write; + + + constant s_rd0_id: std_logic_vector(4 downto 0) := "10001"; + constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; + + constant s_rd1_id: std_logic_vector(4 downto 0) := "10010"; + constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read; + + constant s_rd2_id: std_logic_vector(4 downto 0) := "10011"; + constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; + + constant s_rd3_id: std_logic_vector(4 downto 0) := "10100"; + constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read; + + constant s_rd4_id: std_logic_vector(4 downto 0) := "10101"; + constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; + + constant s_rd5_id: std_logic_vector(4 downto 0) := "10110"; + constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read; + + constant s_rd6_id: std_logic_vector(4 downto 0) := "10111"; + constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; + + constant s_rd7_id: std_logic_vector(4 downto 0) := "11000"; + constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; + + constant s_rd8_id: std_logic_vector(4 downto 0) := "11001"; + constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; + + constant s_rd9_id: std_logic_vector(4 downto 0) := "11011"; + constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; + + + constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101"; + constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; + + constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110"; + constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; + + constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111"; + constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; + + signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0); + signal addr_bank: std_logic_vector(1 downto 0); + + constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width + + + signal addr_col : std_logic_vector(7 downto 0); + signal captured : std_logic_vector(15 downto 0); + signal busy: std_logic; + + constant tOPD: time := 2.1 ns; + constant tHZ: time := 8 ns; + + signal dram_dq_dly : std_logic_vector(15 downto 0); + + -- Debug only + signal debug_cmd: std_logic_vector(3 downto 0); + + signal not_clock_100_delayed_3ns: std_logic; + + constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10; + + attribute IOB: string; + + signal i_DRAM_CS_N: std_logic; + attribute IOB of i_DRAM_CS_N: signal is "true"; + + signal i_DRAM_RAS_N: std_logic; + attribute IOB of i_DRAM_RAS_N: signal is "true"; + + signal i_DRAM_CAS_N: std_logic; + attribute IOB of i_DRAM_CAS_N: signal is "true"; + + signal i_DRAM_WE_N: std_logic; + attribute IOB of i_DRAM_WE_N: signal is "true"; + + signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0); + attribute IOB of i_DRAM_ADDR: signal is "true"; + + signal i_DRAM_BA: std_logic_vector(1 downto 0); + attribute IOB of i_DRAM_BA: signal is "true"; + + signal i_DRAM_DQM: std_logic_vector(1 downto 0); + attribute IOB of i_DRAM_DQM: signal is "true"; + + attribute IOB of rdata_write: signal is "true"; + attribute IOB of captured: signal is "true"; + + signal i_DRAM_CLK: std_logic; + + attribute fsm_encoding: string; + attribute fsm_encoding of nstate: signal is "user"; + attribute fsm_encoding of rstate: signal is "user"; + +begin + + debug_cmd <= rstate(3 downto 0); + + -- Addressing is in 32 bit words - twice that of the DRAM width, + -- so each burst of four access two system words. + --addr_row <= address(23 downto 11); + --addr_bank <= address(10 downto 9); + process(r.req_addr_q) + begin + addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1); + -- (24-2) downto (24-2 - 2 - 13 - 1) + -- 22 downto 6 + addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2); + r.req_addr_q(ADDRESS_BITS-1+9 downto 9); + addr_col <= (others => '0'); + + addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0"; + r.req_addr_q(8 downto 2) & "0"; + end process; + + not_clock_100_delayed_3ns <= not clock_100_delayed_3ns; + + clock: ODDR2 + generic map ( + DDR_ALIGNMENT => "NONE", + INIT => '0', + SRTYPE => "ASYNC") + port map ( + D0 => '1', + D1 => '0', + Q => i_DRAM_CLK, + C0 => clock_100_delayed_3ns, + C1 => not_clock_100_delayed_3ns, + CE => '1', + R => '0', + S => '0' + ); + + DRAM_CKE <= '1'; + + DRAM_CLK <= transport i_DRAM_CLK after tOPD; + + i_DRAM_CS_N <= transport rstate(3) after tOPD; + DRAM_CS_N <= i_DRAM_CS_N; + + i_DRAM_RAS_N <= transport rstate(2) after tOPD; + DRAM_RAS_N <= i_DRAM_RAS_N; + + i_DRAM_CAS_N <= transport rstate(1) after tOPD; + DRAM_CAS_N <= i_DRAM_CAS_N; + + i_DRAM_WE_N <= transport rstate(0) after tOPD; + DRAM_WE_N <= i_DRAM_WE_N; + + i_DRAM_ADDR <= transport r.address after tOPD; + DRAM_ADDR <= i_DRAM_ADDR; + + i_DRAM_BA <= transport r.bank after tOPD; + DRAM_BA <= i_DRAM_BA; + + i_DRAM_DQM <= transport r.dq_masks after tOPD; + DRAM_DQM <= i_DRAM_DQM; + + DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured; + data_out_valid <= r.data_out_valid; + + DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write; + + pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0'; + + process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured) + begin + -- copy the existing values + n <= r; + nstate <= rstate; + ndata_write <= rdata_write; + + if req_read = '1' then + n.rd_pending <= '1'; + if r.rd_pending='0' then + n.req_addr_q <= address; + end if; + end if; + + if req_write = '1' then + n.wr_pending <= '1'; + if r.wr_pending='0' then + n.req_addr_q <= address; + -- Queue data here + n.req_data_write <= data_in; + n.req_mask <= data_mask; + end if; + end if; + + n.dq_masks <= "11"; + + -- first off, do we need to perform a refresh cycle ASAP? + if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns + n.rf_counter <= 0; + n.rf_pending <= '1'; + else + -- only start looking for refreshes outside of the initialisation state. + if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then + n.rf_counter <= r.rf_counter + 1; + end if; + end if; + + -- Set the data bus into HIZ, high and low bytes masked + --DRAM_DQ <= (others => 'Z'); + n.tristate <= '0'; + + n.init_counter <= r.init_counter-1; + + --ndata_write <= (others => DontCareValue); + + n.data_out_valid <= '0'; -- alvie- here, no ? + + -- Process the FSM + case rstate(8 downto 4) is + when s_init_nop_id => --s_init_nop(8 downto 4) => + nstate <= s_init_nop; + n.address <= (others => '0'); + n.bank <= (others => '0'); + n.act_ba <= (others => '0'); + n.rf_counter <= 0; + -- n.data_out_valid <= '1'; -- alvie- not here + + -- T-130, precharge all banks. + if r.init_counter = "000000010000010" then + nstate <= s_init_pre; + n.address(10) <= '1'; + end if; + + -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes + + if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then + nstate <= s_init_ref; + end if; + + -- T-3, the load mode register + if r.init_counter = 3 then + nstate <= s_init_mrs; + -- Mode register is as follows: + -- resvd wr_b OpMd CAS=3 Seq bust=1 + n.address <= "00" & "0" & "00" & "011" & "0" & "000"; + -- resvd + n.bank <= "00"; + end if; + + -- T-1 The switch to the FSM (first command will be a NOP + if r.init_counter = 1 then + nstate <= s_idle; + end if; + + ------------------------------ + -- The Idle section + ------------------------------ + when s_idle_id => + nstate <= s_idle; + + -- do we have to activate a row? + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + -- refreshes take priority over everything + if r.rf_pending = '1' then + nstate <= s_rf0; + n.rf_pending <= '0'; + end if; + ------------------------------ + -- Row activation + -- s_ra2 is also the "idle with active row" state and provides + -- a resting point between operations on the same row + ------------------------------ + when s_ra0_id => + nstate <= s_ra1; + when s_ra1_id => + nstate <= s_ra2; + + + when s_ra2_id=> + -- we can stay in this state until we have something to do + nstate <= s_ra2; + n.tristate<='0'; + + if r.rf_pending = '1' then + nstate <= s_dr0; + n.address(10) <= '1'; + else + + -- If there is a read pending, deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_dr0; + n.address(10) <= '1'; + end if; + + -- unless we have a read to perform on the same row? do that instead + if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then + nstate <= s_rd0; + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + --n.tristate<='1'; + end if; + + -- unless we have a write on the same row? writes take priroty over reads + if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then + nstate <= s_wr0; + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + ndata_write <= r.req_data_write(31 downto 16); + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= not r.req_mask(3 downto 2); + n.wr_pending <= '0'; + --n.tristate <= '0'; + end if; + + + end if; + -- nstate <= s_dr0; + -- n.address(10) <= '1'; + -- n.rd_pending <= r.rd_pending; + -- n.wr_pending <= r.wr_pending; + --n.tristate <= '0'; + --end if; + + ------------------------------------------------------ + -- Deactivate the current row and return to idle state + ------------------------------------------------------ + when s_dr0_id => + nstate <= s_dr1; + when s_dr1_id => + nstate <= s_idle; + + ------------------------------ + -- The Refresh section + ------------------------------ + when s_rf0_id => + nstate <= s_rf1; + when s_rf1_id => + nstate <= s_rf2; + when s_rf2_id => + nstate <= s_rf3; + when s_rf3_id => + nstate <= s_rf4; + when s_rf4_id => + nstate <= s_rf5; + when s_rf5_id => + nstate <= s_idle; + ------------------------------ + -- The Write section + ------------------------------ + when s_wr0_id => + nstate <= s_wr3; + n.bank <= addr_bank; + n.address(0) <= '1'; + ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16); + --DRAM_DQ <= rdata_write; + n.dq_masks<= not r.req_mask(1 downto 0); + n.tristate <= '0'; + + when s_wr1_id => null; + when s_wr2_id => + nstate <= s_dr0; + n.address(10) <= '1'; + + + when s_wr3_id => + -- Default to the idle+row active state + nstate <= s_ra2; + --DRAM_DQ <= rdata_write; + n.data_out_valid<='1'; -- alvie- ack write + n.tristate <= '0'; + n.dq_masks<= "11"; + + -- If there is a read or write then deactivate the row + --if r.rd_pending = '1' or r.wr_pending = '1' then + -- nstate <= s_dr0; + -- n.address(10) <= '1'; + --end if; + + -- But if there is a read pending in the same row, do that + --if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then + -- nstate <= s_rd0; + -- n.address <= (others => '0'); + -- n.address(addr_col'HIGH downto 0) <= addr_col; + -- n.bank <= addr_bank; + -- --n.act_ba <= addr_bank; + -- n.dq_masks <= "00"; + -- n.rd_pending <= '0'; + --end if; + + -- unless there is a write pending in the same row, do that + --if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then + -- nstate <= s_wr0; + -- n.address <= (others => '0'); + -- n.address(addr_col'HIGH downto 0) <= addr_col; + -- n.bank <= addr_bank; + --n.act_ba <= addr_bank; + -- n.dq_masks<= "00"; + -- n.wr_pending <= '0'; + --end if; + + -- But always try and refresh if one is pending! + if r.rf_pending = '1' then + nstate <= s_wr2; --dr0; + --n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Read section + ------------------------------ + when s_rd0_id => -- 10001 + nstate <= s_rd1; + n.tristate<='1'; + n.dq_masks <= "00"; + n.address(0)<='1'; + + when s_rd1_id => -- 10010 + nstate <= s_rd2; + n.dq_masks <= "00"; + n.tristate<='1'; + if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then + + nstate <= s_rd3; -- Another request came, and we can pipeline - + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= "00"; + n.rd_pending <= '0'; + + end if; + + when s_rd2_id => -- 10011 + nstate <= s_rd7; + n.dq_masks <= "00"; + n.tristate<='1'; + + + when s_rd3_id => -- 10100 + + nstate <= s_rd4; + n.dq_masks <= "00"; + n.address(0) <= '1'; + n.tristate<='1'; + + + -- Data is still not ready... + + when s_rd4_id => -- 10101 + nstate <= s_rd5; + n.dq_masks <= "00"; + --n.address(0)<='1'; + n.tristate<='1'; + + if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then + nstate <= s_rd5; -- Another request came, and we can pipeline - + + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= "00"; + n.rd_pending <= '0'; + + else + nstate <= s_rd6; -- NOTE: not correct + end if; + + --if r.rf_pending = '1' then + -- nstate <= s_drdr0; + -- n.address(10) <= '1'; + -- n.rd_pending <= r.rd_pending; -- Keep request + --end if; + + + n.data_out_low <= captured; + n.data_out_valid <= '1'; + + + when s_rd5_id => + -- If a refresh is pending then always deactivate the row + --if r.rf_pending = '1' then + -- nstate <= s_drdr0; + -- n.address(10) <= '1'; + --end if; + + n.address(0) <= '1'; + nstate <= s_rd4; -- Another request came, and we can pipeline - + n.dq_masks <= "00"; + n.tristate<='1'; + + when s_rd6_id => + nstate <= s_rd7; + n.dq_masks<= "00"; + n.tristate<='1'; + + when s_rd7_id => + nstate <= s_ra2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + n.tristate<='1'; + + when s_rd8_id => null; + + when s_rd9_id => null; + + -- The Deactivate row during read section + ------------------------------ + when s_drdr0_id => + nstate <= s_drdr1; + when s_drdr1_id => + nstate <= s_drdr2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_drdr2_id => + nstate <= s_idle; + + if r.rf_pending = '1' then + nstate <= s_rf0; + end if; + + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + when others => + nstate <= s_init_nop; + end case; + end process; + + --- The clock driven logic + process (clock_100, n) + begin + if clock_100'event and clock_100 = '1' then + if rst='1' then + rstate <= (others => '0'); + r.address <= (others => '0'); + r.bank <= (others => '0'); + r.init_counter <= "100000000000000"; + -- synopsys translate_off + r.init_counter <= "000000100000000"; + -- synopsys translate_on + r.rf_counter <= 0; + r.rf_pending <= '0'; + r.rd_pending <= '0'; + r.wr_pending <= '0'; + r.act_row <= (others => '0'); + r.data_out_low <= (others => '0'); + r.data_out_valid <= '0'; + r.dq_masks <= "11"; + r.tristate<='1'; + else + r <= n; + rstate <= nstate; + rdata_write <= ndata_write; + end if; + end if; + end process; + + dram_dq_dly <= transport dram_dq after 1.9 ns; + +-- process (clock_100_delayed_3ns, dram_dq_dly) +-- begin +-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then +-- captured <= dram_dq_dly; +-- end if; +-- end process; + + process (clock_100) + begin + if falling_edge(clock_100) then + captured <= dram_dq_dly; + end if; + end process; + +end rtl; \ No newline at end of file diff --git a/output_files/sdram_simple.vhd.bak b/output_files/sdram_simple.vhd.bak new file mode 100644 index 0000000..95044bf --- /dev/null +++ b/output_files/sdram_simple.vhd.bak @@ -0,0 +1,738 @@ +------------------------------------------------------ +-- FSM for a SDRAM controller +-- +-- Version 0.1 - Ready to simulate +-- +-- Author: Mike Field (hamster@snap.net.nz) +-- +-- Feel free to use it however you would like, but +-- just drop me an email to say thanks. +------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +entity sdram_controller is + generic ( + HIGH_BIT: integer := 24; + MHZ: integer := 96; + REFRESH_CYCLES: integer := 4096; + ADDRESS_BITS: integer := 12 + ); + PORT ( + clock_100: in std_logic; + clock_100_delayed_3ns: in std_logic; + rst: in std_logic; + + -- Signals to/from the SDRAM chip + DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0); + DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); + DRAM_CAS_N : OUT STD_LOGIC; + DRAM_CKE : OUT STD_LOGIC; + DRAM_CLK : OUT STD_LOGIC; + DRAM_CS_N : OUT STD_LOGIC; + DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); + DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); + DRAM_RAS_N : OUT STD_LOGIC; + DRAM_WE_N : OUT STD_LOGIC; + + pending: out std_logic; + + --- Inputs from rest of the system + address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2); + req_read : IN STD_LOGIC; + req_write : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (31 downto 0); + data_out_valid : OUT STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 downto 0); + data_mask : IN STD_LOGIC_VECTOR (3 downto 0) + ); +end entity; + + +architecture rtl of sdram_controller is + + type reg is record + address : std_logic_vector(ADDRESS_BITS-1 downto 0); + bank : std_logic_vector( 1 downto 0); + init_counter : std_logic_vector(14 downto 0); + rf_counter : integer; + rf_pending : std_logic; + rd_pending : std_logic; + wr_pending : std_logic; + act_row : std_logic_vector(ADDRESS_BITS-1 downto 0); + act_ba : std_logic_vector(1 downto 0); + data_out_low : std_logic_vector(15 downto 0); + req_addr_q : std_logic_vector(HIGH_BIT downto 2); + req_data_write: std_logic_vector(31 downto 0); + req_mask : std_logic_vector(3 downto 0); + data_out_valid: std_logic; + dq_masks : std_logic_vector(1 downto 0); + tristate : std_logic; + end record; + + signal r : reg; + signal n : reg; + + signal rstate : std_logic_vector(8 downto 0); + signal nstate : std_logic_vector(8 downto 0); + signal rdata_write : std_logic_vector(15 downto 0); + signal ndata_write : std_logic_vector(15 downto 0); + + + -- Vectors for each SDRAM 'command' + --- CS_N, RAS_N, CAS_N, WE_N + constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; + constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. + constant cmd_write : std_logic_vector(3 downto 0) := "0100"; + constant cmd_act : std_logic_vector(3 downto 0) := "0011"; + constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. + constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; + constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set + + -- State assignments + constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000"; + + constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop; + constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre; + constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref; + constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs; + + constant s_idle_id: std_logic_vector(4 downto 0) := "00001"; + constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop; + + constant s_rf0_id: std_logic_vector(4 downto 0) := "00010"; + constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref; + + constant s_rf1_id: std_logic_vector(4 downto 0) := "00011"; + constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; + + constant s_rf2_id: std_logic_vector(4 downto 0) := "00100"; + constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; + + constant s_rf3_id: std_logic_vector(4 downto 0) := "00101"; + constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; + + constant s_rf4_id: std_logic_vector(4 downto 0) := "00110"; + constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; + + constant s_rf5_id: std_logic_vector(4 downto 0) := "00111"; + constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; + + + constant s_ra0_id: std_logic_vector(4 downto 0) := "01000"; + constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; + + constant s_ra1_id: std_logic_vector(4 downto 0) := "01001"; + constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; + + constant s_ra2_id: std_logic_vector(4 downto 0) := "01010"; + constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; + + + constant s_dr0_id: std_logic_vector(4 downto 0) := "01011"; + constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; + + constant s_dr1_id: std_logic_vector(4 downto 0) := "01100"; + constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; + + constant s_wr0_id: std_logic_vector(4 downto 0) := "01101"; + constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; + + constant s_wr1_id: std_logic_vector(4 downto 0) := "01110"; + constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; + + constant s_wr2_id: std_logic_vector(4 downto 0) := "01111"; + constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; + + constant s_wr3_id: std_logic_vector(4 downto 0) := "10000"; + constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write; + + + constant s_rd0_id: std_logic_vector(4 downto 0) := "10001"; + constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; + + constant s_rd1_id: std_logic_vector(4 downto 0) := "10010"; + constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read; + + constant s_rd2_id: std_logic_vector(4 downto 0) := "10011"; + constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; + + constant s_rd3_id: std_logic_vector(4 downto 0) := "10100"; + constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read; + + constant s_rd4_id: std_logic_vector(4 downto 0) := "10101"; + constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; + + constant s_rd5_id: std_logic_vector(4 downto 0) := "10110"; + constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read; + + constant s_rd6_id: std_logic_vector(4 downto 0) := "10111"; + constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; + + constant s_rd7_id: std_logic_vector(4 downto 0) := "11000"; + constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; + + constant s_rd8_id: std_logic_vector(4 downto 0) := "11001"; + constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; + + constant s_rd9_id: std_logic_vector(4 downto 0) := "11011"; + constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; + + + constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101"; + constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; + + constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110"; + constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; + + constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111"; + constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; + + signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0); + signal addr_bank: std_logic_vector(1 downto 0); + + constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width + + + signal addr_col : std_logic_vector(7 downto 0); + signal captured : std_logic_vector(15 downto 0); + signal busy: std_logic; + + constant tOPD: time := 2.1 ns; + constant tHZ: time := 8 ns; + + signal dram_dq_dly : std_logic_vector(15 downto 0); + + -- Debug only + signal debug_cmd: std_logic_vector(3 downto 0); + + signal not_clock_100_delayed_3ns: std_logic; + + constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10; + + attribute IOB: string; + + signal i_DRAM_CS_N: std_logic; + attribute IOB of i_DRAM_CS_N: signal is "true"; + + signal i_DRAM_RAS_N: std_logic; + attribute IOB of i_DRAM_RAS_N: signal is "true"; + + signal i_DRAM_CAS_N: std_logic; + attribute IOB of i_DRAM_CAS_N: signal is "true"; + + signal i_DRAM_WE_N: std_logic; + attribute IOB of i_DRAM_WE_N: signal is "true"; + + signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0); + attribute IOB of i_DRAM_ADDR: signal is "true"; + + signal i_DRAM_BA: std_logic_vector(1 downto 0); + attribute IOB of i_DRAM_BA: signal is "true"; + + signal i_DRAM_DQM: std_logic_vector(1 downto 0); + attribute IOB of i_DRAM_DQM: signal is "true"; + + attribute IOB of rdata_write: signal is "true"; + attribute IOB of captured: signal is "true"; + + signal i_DRAM_CLK: std_logic; + + attribute fsm_encoding: string; + attribute fsm_encoding of nstate: signal is "user"; + attribute fsm_encoding of rstate: signal is "user"; + +begin + + debug_cmd <= rstate(3 downto 0); + + -- Addressing is in 32 bit words - twice that of the DRAM width, + -- so each burst of four access two system words. + --addr_row <= address(23 downto 11); + --addr_bank <= address(10 downto 9); + process(r.req_addr_q) + begin + addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1); + -- (24-2) downto (24-2 - 2 - 13 - 1) + -- 22 downto 6 + addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2); + r.req_addr_q(ADDRESS_BITS-1+9 downto 9); + addr_col <= (others => '0'); + + addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0"; + r.req_addr_q(8 downto 2) & "0"; + end process; + + not_clock_100_delayed_3ns <= not clock_100_delayed_3ns; + + clock: ODDR2 + generic map ( + DDR_ALIGNMENT => "NONE", + INIT => '0', + SRTYPE => "ASYNC") + port map ( + D0 => '1', + D1 => '0', + Q => i_DRAM_CLK, + C0 => clock_100_delayed_3ns, + C1 => not_clock_100_delayed_3ns, + CE => '1', + R => '0', + S => '0' + ); + + DRAM_CKE <= '1'; + + DRAM_CLK <= transport i_DRAM_CLK after tOPD; + + i_DRAM_CS_N <= transport rstate(3) after tOPD; + DRAM_CS_N <= i_DRAM_CS_N; + + i_DRAM_RAS_N <= transport rstate(2) after tOPD; + DRAM_RAS_N <= i_DRAM_RAS_N; + + i_DRAM_CAS_N <= transport rstate(1) after tOPD; + DRAM_CAS_N <= i_DRAM_CAS_N; + + i_DRAM_WE_N <= transport rstate(0) after tOPD; + DRAM_WE_N <= i_DRAM_WE_N; + + i_DRAM_ADDR <= transport r.address after tOPD; + DRAM_ADDR <= i_DRAM_ADDR; + + i_DRAM_BA <= transport r.bank after tOPD; + DRAM_BA <= i_DRAM_BA; + + i_DRAM_DQM <= transport r.dq_masks after tOPD; + DRAM_DQM <= i_DRAM_DQM; + + DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured; + data_out_valid <= r.data_out_valid; + + DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write; + + pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0'; + + process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured) + begin + -- copy the existing values + n <= r; + nstate <= rstate; + ndata_write <= rdata_write; + + if req_read = '1' then + n.rd_pending <= '1'; + if r.rd_pending='0' then + n.req_addr_q <= address; + end if; + end if; + + if req_write = '1' then + n.wr_pending <= '1'; + if r.wr_pending='0' then + n.req_addr_q <= address; + -- Queue data here + n.req_data_write <= data_in; + n.req_mask <= data_mask; + end if; + end if; + + n.dq_masks <= "11"; + + -- first off, do we need to perform a refresh cycle ASAP? + if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns + n.rf_counter <= 0; + n.rf_pending <= '1'; + else + -- only start looking for refreshes outside of the initialisation state. + if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then + n.rf_counter <= r.rf_counter + 1; + end if; + end if; + + -- Set the data bus into HIZ, high and low bytes masked + --DRAM_DQ <= (others => 'Z'); + n.tristate <= '0'; + + n.init_counter <= r.init_counter-1; + + --ndata_write <= (others => DontCareValue); + + n.data_out_valid <= '0'; -- alvie- here, no ? + + -- Process the FSM + case rstate(8 downto 4) is + when s_init_nop_id => --s_init_nop(8 downto 4) => + nstate <= s_init_nop; + n.address <= (others => '0'); + n.bank <= (others => '0'); + n.act_ba <= (others => '0'); + n.rf_counter <= 0; + -- n.data_out_valid <= '1'; -- alvie- not here + + -- T-130, precharge all banks. + if r.init_counter = "000000010000010" then + nstate <= s_init_pre; + n.address(10) <= '1'; + end if; + + -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes + + if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then + nstate <= s_init_ref; + end if; + + -- T-3, the load mode register + if r.init_counter = 3 then + nstate <= s_init_mrs; + -- Mode register is as follows: + -- resvd wr_b OpMd CAS=3 Seq bust=1 + n.address <= "00" & "0" & "00" & "011" & "0" & "000"; + -- resvd + n.bank <= "00"; + end if; + + -- T-1 The switch to the FSM (first command will be a NOP + if r.init_counter = 1 then + nstate <= s_idle; + end if; + + ------------------------------ + -- The Idle section + ------------------------------ + when s_idle_id => + nstate <= s_idle; + + -- do we have to activate a row? + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + -- refreshes take priority over everything + if r.rf_pending = '1' then + nstate <= s_rf0; + n.rf_pending <= '0'; + end if; + ------------------------------ + -- Row activation + -- s_ra2 is also the "idle with active row" state and provides + -- a resting point between operations on the same row + ------------------------------ + when s_ra0_id => + nstate <= s_ra1; + when s_ra1_id => + nstate <= s_ra2; + + + when s_ra2_id=> + -- we can stay in this state until we have something to do + nstate <= s_ra2; + n.tristate<='0'; + + if r.rf_pending = '1' then + nstate <= s_dr0; + n.address(10) <= '1'; + else + + -- If there is a read pending, deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_dr0; + n.address(10) <= '1'; + end if; + + -- unless we have a read to perform on the same row? do that instead + if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then + nstate <= s_rd0; + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + --n.tristate<='1'; + end if; + + -- unless we have a write on the same row? writes take priroty over reads + if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then + nstate <= s_wr0; + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + ndata_write <= r.req_data_write(31 downto 16); + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= not r.req_mask(3 downto 2); + n.wr_pending <= '0'; + --n.tristate <= '0'; + end if; + + + end if; + -- nstate <= s_dr0; + -- n.address(10) <= '1'; + -- n.rd_pending <= r.rd_pending; + -- n.wr_pending <= r.wr_pending; + --n.tristate <= '0'; + --end if; + + ------------------------------------------------------ + -- Deactivate the current row and return to idle state + ------------------------------------------------------ + when s_dr0_id => + nstate <= s_dr1; + when s_dr1_id => + nstate <= s_idle; + + ------------------------------ + -- The Refresh section + ------------------------------ + when s_rf0_id => + nstate <= s_rf1; + when s_rf1_id => + nstate <= s_rf2; + when s_rf2_id => + nstate <= s_rf3; + when s_rf3_id => + nstate <= s_rf4; + when s_rf4_id => + nstate <= s_rf5; + when s_rf5_id => + nstate <= s_idle; + ------------------------------ + -- The Write section + ------------------------------ + when s_wr0_id => + nstate <= s_wr3; + n.bank <= addr_bank; + n.address(0) <= '1'; + ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16); + --DRAM_DQ <= rdata_write; + n.dq_masks<= not r.req_mask(1 downto 0); + n.tristate <= '0'; + + when s_wr1_id => null; + when s_wr2_id => + nstate <= s_dr0; + n.address(10) <= '1'; + + + when s_wr3_id => + -- Default to the idle+row active state + nstate <= s_ra2; + --DRAM_DQ <= rdata_write; + n.data_out_valid<='1'; -- alvie- ack write + n.tristate <= '0'; + n.dq_masks<= "11"; + + -- If there is a read or write then deactivate the row + --if r.rd_pending = '1' or r.wr_pending = '1' then + -- nstate <= s_dr0; + -- n.address(10) <= '1'; + --end if; + + -- But if there is a read pending in the same row, do that + --if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then + -- nstate <= s_rd0; + -- n.address <= (others => '0'); + -- n.address(addr_col'HIGH downto 0) <= addr_col; + -- n.bank <= addr_bank; + -- --n.act_ba <= addr_bank; + -- n.dq_masks <= "00"; + -- n.rd_pending <= '0'; + --end if; + + -- unless there is a write pending in the same row, do that + --if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then + -- nstate <= s_wr0; + -- n.address <= (others => '0'); + -- n.address(addr_col'HIGH downto 0) <= addr_col; + -- n.bank <= addr_bank; + --n.act_ba <= addr_bank; + -- n.dq_masks<= "00"; + -- n.wr_pending <= '0'; + --end if; + + -- But always try and refresh if one is pending! + if r.rf_pending = '1' then + nstate <= s_wr2; --dr0; + --n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Read section + ------------------------------ + when s_rd0_id => -- 10001 + nstate <= s_rd1; + n.tristate<='1'; + n.dq_masks <= "00"; + n.address(0)<='1'; + + when s_rd1_id => -- 10010 + nstate <= s_rd2; + n.dq_masks <= "00"; + n.tristate<='1'; + if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then + + nstate <= s_rd3; -- Another request came, and we can pipeline - + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= "00"; + n.rd_pending <= '0'; + + end if; + + when s_rd2_id => -- 10011 + nstate <= s_rd7; + n.dq_masks <= "00"; + n.tristate<='1'; + + + when s_rd3_id => -- 10100 + + nstate <= s_rd4; + n.dq_masks <= "00"; + n.address(0) <= '1'; + n.tristate<='1'; + + + -- Data is still not ready... + + when s_rd4_id => -- 10101 + nstate <= s_rd5; + n.dq_masks <= "00"; + --n.address(0)<='1'; + n.tristate<='1'; + + if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then + nstate <= s_rd5; -- Another request came, and we can pipeline - + + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= "00"; + n.rd_pending <= '0'; + + else + nstate <= s_rd6; -- NOTE: not correct + end if; + + --if r.rf_pending = '1' then + -- nstate <= s_drdr0; + -- n.address(10) <= '1'; + -- n.rd_pending <= r.rd_pending; -- Keep request + --end if; + + + n.data_out_low <= captured; + n.data_out_valid <= '1'; + + + when s_rd5_id => + -- If a refresh is pending then always deactivate the row + --if r.rf_pending = '1' then + -- nstate <= s_drdr0; + -- n.address(10) <= '1'; + --end if; + + n.address(0) <= '1'; + nstate <= s_rd4; -- Another request came, and we can pipeline - + n.dq_masks <= "00"; + n.tristate<='1'; + + when s_rd6_id => + nstate <= s_rd7; + n.dq_masks<= "00"; + n.tristate<='1'; + + when s_rd7_id => + nstate <= s_ra2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + n.tristate<='1'; + + when s_rd8_id => null; + + when s_rd9_id => null; + + -- The Deactivate row during read section + ------------------------------ + when s_drdr0_id => + nstate <= s_drdr1; + when s_drdr1_id => + nstate <= s_drdr2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_drdr2_id => + nstate <= s_idle; + + if r.rf_pending = '1' then + nstate <= s_rf0; + end if; + + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + when others => + nstate <= s_init_nop; + end case; + end process; + + --- The clock driven logic + process (clock_100, n) + begin + if clock_100'event and clock_100 = '1' then + if rst='1' then + rstate <= (others => '0'); + r.address <= (others => '0'); + r.bank <= (others => '0'); + r.init_counter <= "100000000000000"; + -- synopsys translate_off + r.init_counter <= "000000100000000"; + -- synopsys translate_on + r.rf_counter <= 0; + r.rf_pending <= '0'; + r.rd_pending <= '0'; + r.wr_pending <= '0'; + r.act_row <= (others => '0'); + r.data_out_low <= (others => '0'); + r.data_out_valid <= '0'; + r.dq_masks <= "11"; + r.tristate<='1'; + else + r <= n; + rstate <= nstate; + rdata_write <= ndata_write; + end if; + end if; + end process; + + dram_dq_dly <= transport dram_dq after 1.9 ns; + +-- process (clock_100_delayed_3ns, dram_dq_dly) +-- begin +-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then +-- captured <= dram_dq_dly; +-- end if; +-- end process; + + process (clock_100) + begin + if falling_edge(clock_100) then + captured <= dram_dq_dly; + end if; + end process; + +end rtl; \ No newline at end of file diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index 44a85f8..90653ed 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Sat Apr 2 14:51:11 2022 +Wed Apr 6 13:58:19 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sat Apr 2 14:51:11 2022 ; +; Assembler Status ; Successful - Wed Apr 6 13:58:19 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x0058B9EB ; -; Checksum ; 0x0058B9EB ; +; JTAG usercode ; 0x0059A13C ; +; Checksum ; 0x0059A13C ; +----------------+-----------------------+ @@ -173,13 +173,13 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Sat Apr 2 14:51:09 2022 + Info: Processing started: Wed Apr 6 13:58:17 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 383 megabytes - Info: Processing ended: Sat Apr 2 14:51:11 2022 + Info: Peak virtual memory: 387 megabytes + Info: Processing ended: Wed Apr 6 13:58:19 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index b81c623..2d48427 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Sat Apr 2 14:51:22 2022 +Wed Apr 6 13:58:30 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index c7835b6..fd107dc 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Sat Apr 2 14:51:22 2022 +Wed Apr 6 13:58:30 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Sat Apr 2 14:51:22 2022 ; +; EDA Netlist Writer Status ; Successful - Wed Apr 6 13:58:30 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Sat Apr 2 14:51:19 2022 + Info: Processing started: Wed Apr 6 13:58:26 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool @@ -99,9 +99,9 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 379 megabytes - Info: Processing ended: Sat Apr 2 14:51:22 2022 - Info: Elapsed time: 00:00:03 + Info: Peak virtual memory: 380 megabytes + Info: Processing ended: Wed Apr 6 13:58:30 2022 + Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:03 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index c20f174..be6e7a4 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Sat Apr 2 14:51:07 2022 +Wed Apr 6 13:58:15 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -34,8 +34,8 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 26. Global & Other Fast Signals 27. Non-Global High Fan-Out Signals 28. Fitter RAM Summary - 29. |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM - 30. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM + 29. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM + 30. |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM 31. |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM 32. Routing Usage Summary 33. LAB Logic Elements @@ -77,18 +77,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Sat Apr 2 14:51:07 2022 ; +; Fitter Status ; Successful - Wed Apr 6 13:58:15 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,609 / 22,320 ( 12 % ) ; -; Total combinational functions ; 2,490 / 22,320 ( 11 % ) ; -; Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; -; Total registers ; 664 ; -; Total pins ; 114 / 154 ( 74 % ) ; +; Total logic elements ; 2,743 / 22,320 ( 12 % ) ; +; Total combinational functions ; 2,624 / 22,320 ( 12 % ) ; +; Dedicated logic registers ; 700 / 22,320 ( 3 % ) ; +; Total registers ; 729 ; +; Total pins ; 120 / 154 ( 78 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; @@ -385,8 +385,6 @@ Parallel compilation was disabled, but you have multiple processors available. E ; GPIO_1[29] ; Missing drive strength ; ; GPIO_1[30] ; Missing drive strength ; ; GPIO_1[31] ; Missing drive strength ; -; GPIO_1[32] ; Missing drive strength ; -; GPIO_1[33] ; Missing drive strength ; ; buzzer_out ; Missing drive strength ; ; DRAM_BA[0] ; Missing drive strength ; ; DRAM_BA[1] ; Missing drive strength ; @@ -411,6 +409,7 @@ Parallel compilation was disabled, but you have multiple processors available. E ; DRAM_ADDR[10] ; Missing drive strength ; ; DRAM_ADDR[11] ; Missing drive strength ; ; DRAM_ADDR[12] ; Missing drive strength ; +; kempston_gnd ; Missing drive strength ; ; I2C_SCLK ; Missing drive strength ; ; I2C_SDAT ; Missing drive strength ; ; DRAM_DQ[0] ; Missing drive strength ; @@ -1055,48 +1054,6 @@ Ignored To : GPIO_0[3] Ignored Value : PIN_A3 Ignored Source : QSF Assignment -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[4] -Ignored Value : PIN_B3 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[5] -Ignored Value : PIN_B4 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[6] -Ignored Value : PIN_A4 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[7] -Ignored Value : PIN_B5 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[8] -Ignored Value : PIN_A5 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : GPIO_0[9] -Ignored Value : PIN_D5 -Ignored Source : QSF Assignment - Name : Location Ignored Entity : Ignored From : @@ -1335,48 +1292,6 @@ Ignored To : GPIO_0[3] Ignored Value : 3.3-V LVTTL Ignored Source : QSF Assignment -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[4] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[5] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[6] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[7] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[8] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : GPIO_0[9] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - Name : I/O Standard Ignored Entity : spectrum Ignored From : @@ -1543,14 +1458,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 3462 ) -From Design Partitions [A] : 0.00 % ( 0 / 3462 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3462 ) +Total [A + B] : 0.00 % ( 0 / 3673 ) +From Design Partitions [A] : 0.00 % ( 0 / 3673 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3673 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 3462 ) -From Design Partitions [A] : 0.00 % ( 0 / 3462 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3462 ) +Total [A + B] : 0.00 % ( 0 / 3673 ) +From Design Partitions [A] : 0.00 % ( 0 / 3673 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3673 ) Type : Total [A + B] : @@ -1601,7 +1516,7 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 3445 ) +Preservation Achieved : 0.00 % ( 0 / 3656 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -1628,28 +1543,28 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe +---------------------------------------------+----------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------+ -; Total logic elements ; 2,609 / 22,320 ( 12 % ) ; -; -- Combinational with no register ; 1974 ; +; Total logic elements ; 2,743 / 22,320 ( 12 % ) ; +; -- Combinational with no register ; 2043 ; ; -- Register only ; 119 ; -; -- Combinational with a register ; 516 ; +; -- Combinational with a register ; 581 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1776 ; -; -- 3 input functions ; 423 ; -; -- <=2 input functions ; 291 ; +; -- 4 input functions ; 1835 ; +; -- 3 input functions ; 428 ; +; -- <=2 input functions ; 361 ; ; -- Register only ; 119 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2414 ; -; -- arithmetic mode ; 76 ; +; -- normal mode ; 2492 ; +; -- arithmetic mode ; 132 ; ; ; ; -; Total registers* ; 664 / 23,018 ( 3 % ) ; -; -- Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; +; Total registers* ; 729 / 23,018 ( 3 % ) ; +; -- Dedicated logic registers ; 700 / 22,320 ( 3 % ) ; ; -- I/O registers ; 29 / 698 ( 4 % ) ; ; ; ; -; Total LABs: partially or completely used ; 204 / 1,395 ( 15 % ) ; +; Total LABs: partially or completely used ; 216 / 1,395 ( 15 % ) ; ; Virtual pins ; 0 ; -; I/O pins ; 114 / 154 ( 74 % ) ; +; I/O pins ; 120 / 154 ( 78 % ) ; ; -- Clock pins ; 5 / 7 ( 71 % ) ; ; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; ; ; ; @@ -1664,12 +1579,12 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe ; CRC blocks ; 0 / 1 ( 0 % ) ; ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 5% / 5% / 6% ; -; Peak interconnect usage (total/H/V) ; 20% / 16% / 25% ; -; Maximum fan-out ; 435 ; -; Highest non-global fan-out ; 78 ; -; Total fan-out ; 12653 ; -; Average fan-out ; 3.56 ; +; Average interconnect usage (total/H/V) ; 6% / 6% / 7% ; +; Peak interconnect usage (total/H/V) ; 30% / 25% / 36% ; +; Maximum fan-out ; 454 ; +; Highest non-global fan-out ; 73 ; +; Total fan-out ; 13241 ; +; Average fan-out ; 3.52 ; +---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -1687,11 +1602,11 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 2609 / 22320 ( 12 % ) +Top : 2743 / 22320 ( 12 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 1974 +Top : 2043 hard_block:auto_generated_inst : 0 Statistic : -- Register only @@ -1699,7 +1614,7 @@ Top : 119 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 516 +Top : 581 hard_block:auto_generated_inst : 0 Statistic : @@ -1711,15 +1626,15 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 1776 +Top : 1835 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions -Top : 423 +Top : 428 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 291 +Top : 361 hard_block:auto_generated_inst : 0 Statistic : -- Register only @@ -1735,11 +1650,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 2414 +Top : 2492 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode -Top : 76 +Top : 132 hard_block:auto_generated_inst : 0 Statistic : @@ -1747,11 +1662,11 @@ Top : hard_block:auto_generated_inst : Statistic : Total registers -Top : 664 +Top : 729 hard_block:auto_generated_inst : 0 Statistic : -- Dedicated logic registers -Top : 635 / 22320 ( 3 % ) +Top : 700 / 22320 ( 3 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- I/O registers @@ -1763,7 +1678,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 204 / 1395 ( 15 % ) +Top : 216 / 1395 ( 15 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -1775,7 +1690,7 @@ Top : 0 hard_block:auto_generated_inst : 0 Statistic : I/O pins -Top : 114 +Top : 120 hard_block:auto_generated_inst : 0 Statistic : Embedded Multiplier 9-bit elements @@ -1839,11 +1754,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 12657 +Top : 13245 hard_block:auto_generated_inst : 274 Statistic : -- Registered Connections -Top : 3469 +Top : 3734 hard_block:auto_generated_inst : 0 Statistic : @@ -1871,11 +1786,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Input Ports -Top : 11 +Top : 18 hard_block:auto_generated_inst : 2 Statistic : -- Output Ports -Top : 85 +Top : 84 hard_block:auto_generated_inst : 6 Statistic : -- Bidir Ports @@ -1968,7 +1883,7 @@ I/O Bank : 3 X coordinate : 27 Y coordinate : 0 Z coordinate : 21 -Combinational Fan-Out : 52 +Combinational Fan-Out : 96 Registered Fan-Out : 0 Global : yes Input Register : no @@ -2094,7 +2009,7 @@ I/O Bank : 7 X coordinate : 25 Y coordinate : 34 Z coordinate : 7 -Combinational Fan-Out : 2 +Combinational Fan-Out : 0 Registered Fan-Out : 0 Global : no Input Register : no @@ -2124,6 +2039,114 @@ I/O Standard : 3.3-V LVTTL Termination Control Block : -- Location assigned by : User +Name : kempston[0] +Pin # : B4 +I/O Bank : 8 +X coordinate : 7 +Y coordinate : 34 +Z coordinate : 0 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : kempston[1] +Pin # : A4 +I/O Bank : 8 +X coordinate : 9 +Y coordinate : 34 +Z coordinate : 21 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : kempston[2] +Pin # : B5 +I/O Bank : 8 +X coordinate : 11 +Y coordinate : 34 +Z coordinate : 0 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : kempston[3] +Pin # : A5 +I/O Bank : 8 +X coordinate : 14 +Y coordinate : 34 +Z coordinate : 21 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : kempston[4] +Pin # : D5 +I/O Bank : 8 +X coordinate : 5 +Y coordinate : 34 +Z coordinate : 14 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + +Name : kempston_autofire_button +Pin # : J14 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 15 +Z coordinate : 7 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User + Name : raw_loader_in Pin # : B6 I/O Bank : 8 @@ -2141,6 +2164,24 @@ Weak Pull Up : Off I/O Standard : 3.3-V LVTTL Termination Control Block : -- Location assigned by : User + +Name : turbo_button +Pin # : J13 +I/O Bank : 5 +X coordinate : 53 +Y coordinate : 16 +Z coordinate : 7 +Combinational Fan-Out : 2 +Registered Fan-Out : 0 +Global : no +Input Register : no +Power Up High : no +PCI I/O Enabled : yes +Bus Hold : no +Weak Pull Up : On +I/O Standard : 3.3-V LVTTL +Termination Control Block : -- +Location assigned by : User +--------------------------------------------------------------------------------+ @@ -3473,56 +3514,6 @@ Location assigned by : User Output Enable Source : - Output Enable Group : - -Name : GPIO_1[32] -Pin # : J13 -I/O Bank : 5 -X coordinate : 53 -Y coordinate : 16 -Z coordinate : 7 -Output Register : no -Output Enable Register : no -Power Up High : no -Slew Rate : 2 -PCI I/O Enabled : no -Open Drain : no -TRI Primitive : no -Bus Hold : no -Weak Pull Up : Off -I/O Standard : 3.3-V LVTTL -Current Strength : 8mA -Termination : Off -Termination Control Block : -- -Output Buffer Pre-emphasis : no -Voltage Output Differential : no -Location assigned by : User -Output Enable Source : - -Output Enable Group : - - -Name : GPIO_1[33] -Pin # : J14 -I/O Bank : 5 -X coordinate : 53 -Y coordinate : 15 -Z coordinate : 7 -Output Register : no -Output Enable Register : no -Power Up High : no -Slew Rate : 2 -PCI I/O Enabled : no -Open Drain : no -TRI Primitive : no -Bus Hold : no -Weak Pull Up : Off -I/O Standard : 3.3-V LVTTL -Current Strength : 8mA -Termination : Off -Termination Control Block : -- -Output Buffer Pre-emphasis : no -Voltage Output Differential : no -Location assigned by : User -Output Enable Source : - -Output Enable Group : - - Name : GPIO_1[3] Pin # : T13 I/O Bank : 4 @@ -4272,6 +4263,31 @@ Voltage Output Differential : no Location assigned by : User Output Enable Source : - Output Enable Group : - + +Name : kempston_gnd +Pin # : B3 +I/O Bank : 8 +X coordinate : 3 +Y coordinate : 34 +Z coordinate : 0 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - +--------------------------------------------------------------------------------+ @@ -4951,11 +4967,41 @@ Reserved As : Use as regular IO User Signal Name : AUD_BCLK Pin Type : Dual Purpose Pin +Location : A5 +Pin Name : DIFFIO_T5n, DATA7 +Reserved As : Use as regular IO +User Signal Name : kempston[3] +Pin Type : Dual Purpose Pin + +Location : B5 +Pin Name : DIFFIO_T5p, DATA8 +Reserved As : Use as regular IO +User Signal Name : kempston[2] +Pin Type : Dual Purpose Pin + Location : D6 Pin Name : DIFFIO_T4n, DATA9 Reserved As : Use as regular IO User Signal Name : PS2_CLK Pin Type : Dual Purpose Pin + +Location : A4 +Pin Name : DIFFIO_T3n, DATA10 +Reserved As : Use as regular IO +User Signal Name : kempston[1] +Pin Type : Dual Purpose Pin + +Location : B4 +Pin Name : DIFFIO_T3p, DATA11 +Reserved As : Use as regular IO +User Signal Name : kempston[0] +Pin Type : Dual Purpose Pin + +Location : B3 +Pin Name : DATA12, DQS1T/CQ1T#,CDPCLK7 +Reserved As : Use as regular IO +User Signal Name : kempston_gnd +Pin Type : Dual Purpose Pin +--------------------------------------------------------------------------------+ @@ -4999,7 +5045,7 @@ VCCIO Voltage : 3.3V VREF Voltage : -- I/O Bank : 8 -Usage : 12 / 24 ( 50 % ) +Usage : 18 / 24 ( 75 % ) VCCIO Voltage : 3.3V VREF Voltage : -- +--------------------------------------------------------------------------------+ @@ -5048,24 +5094,24 @@ Weak Pull Up : On Location : A4 Pad Number : 236 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : kempston[1] +Dir. : input +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no Weak Pull Up : On Location : A5 Pad Number : 232 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : kempston[3] +Dir. : input +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no Weak Pull Up : On @@ -5228,36 +5274,36 @@ Weak Pull Up : -- Location : B3 Pad Number : 242 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : kempston_gnd +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : B4 Pad Number : 237 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : kempston[0] +Dir. : input +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no Weak Pull Up : On Location : B5 Pad Number : 233 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : kempston[2] +Dir. : input +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no Weak Pull Up : On @@ -5636,12 +5682,12 @@ Weak Pull Up : -- Location : D5 Pad Number : 241 I/O Bank : 8 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : kempston[4] +Dir. : input +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no Weak Pull Up : On @@ -6704,26 +6750,26 @@ Weak Pull Up : -- Location : J13 Pad Number : 146 I/O Bank : 5 -Pin Name/Usage : GPIO_1[32] -Dir. : output +Pin Name/Usage : turbo_button +Dir. : input I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O User Assignment : Y Bus Hold : no -Weak Pull Up : Off +Weak Pull Up : On Location : J14 Pad Number : 144 I/O Bank : 5 -Pin Name/Usage : GPIO_1[33] -Dir. : output +Pin Name/Usage : kempston_autofire_button +Dir. : input I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O User Assignment : Y Bus Hold : no -Weak Pull Up : Off +Weak Pull Up : On Location : J15 Pad Number : 143 @@ -8325,22 +8371,56 @@ SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 2609 (106) -Dedicated Logic Registers : 635 (0) +Logic Cells : 2743 (121) +Dedicated Logic Registers : 700 (21) I/O Registers : 29 (29) Memory Bits : 524288 M9Ks : 64 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 114 +Pins : 120 Virtual Pins : 0 -LUT-Only LCs : 1974 (105) +LUT-Only LCs : 2043 (100) Register-Only LCs : 119 (0) -LUT/Register LCs : 516 (3) +LUT/Register LCs : 581 (24) Full Hierarchy Name : |spectrum Library Name : work +Compilation Hierarchy Node : |debouncer:debounce_autofire| +Logic Cells : 34 (34) +Dedicated Logic Registers : 22 (22) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 12 (12) +Register-Only LCs : 0 (0) +LUT/Register LCs : 22 (22) +Full Hierarchy Name : |spectrum|debouncer:debounce_autofire +Library Name : work + +Compilation Hierarchy Node : |debouncer:debounce_turbo| +Logic Cells : 34 (34) +Dedicated Logic Registers : 22 (22) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 12 (12) +Register-Only LCs : 0 (0) +LUT/Register LCs : 22 (22) +Full Hierarchy Name : |spectrum|debouncer:debounce_turbo +Library Name : work + Compilation Hierarchy Node : |ram16:ram0| Logic Cells : 4 (0) Dedicated Logic Registers : 2 (0) @@ -8353,8 +8433,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 2 (0) -LUT/Register LCs : 0 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 1 (0) Full Hierarchy Name : |spectrum|ram16:ram0 Library Name : work @@ -8370,8 +8450,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 2 (0) -LUT/Register LCs : 0 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 1 (0) Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component Library Name : work @@ -8387,8 +8467,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 2 (2) -LUT/Register LCs : 0 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated Library Name : work @@ -8410,7 +8490,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -Logic Cells : 16 (0) +Logic Cells : 25 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -8420,14 +8500,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 12 (0) -Register-Only LCs : 1 (0) -LUT/Register LCs : 3 (0) +LUT-Only LCs : 21 (0) +Register-Only LCs : 2 (0) +LUT/Register LCs : 2 (0) Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -Logic Cells : 16 (0) +Logic Cells : 25 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -8437,14 +8517,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 12 (0) -Register-Only LCs : 1 (0) -LUT/Register LCs : 3 (0) +LUT-Only LCs : 21 (0) +Register-Only LCs : 2 (0) +LUT/Register LCs : 2 (0) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -Logic Cells : 16 (4) +Logic Cells : 25 (4) Dedicated Logic Registers : 4 (4) I/O Registers : 0 (0) Memory Bits : 262144 @@ -8454,9 +8534,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 12 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 3 (3) +LUT-Only LCs : 21 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 2 (1) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated Library Name : work @@ -8488,14 +8568,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) +LUT-Only LCs : 6 (6) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3 Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -Logic Cells : 4 (4) +Logic Cells : 14 (14) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8505,7 +8585,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) +LUT-Only LCs : 14 (14) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 @@ -8563,7 +8643,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |sdram_controller:sdram_| -Logic Cells : 229 (229) +Logic Cells : 237 (237) Dedicated Logic Registers : 44 (44) I/O Registers : 0 (0) Memory Bits : 0 @@ -8573,7 +8653,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 185 (185) +LUT-Only LCs : 193 (193) Register-Only LCs : 4 (4) LUT/Register LCs : 40 (40) Full Hierarchy Name : |spectrum|sdram_controller:sdram_ @@ -8631,7 +8711,7 @@ Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdr Library Name : work Compilation Hierarchy Node : |ula:ula_| -Logic Cells : 456 (9) +Logic Cells : 466 (8) Dedicated Logic Registers : 223 (7) I/O Registers : 0 (0) Memory Bits : 0 @@ -8641,9 +8721,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 233 (2) -Register-Only LCs : 37 (5) -LUT/Register LCs : 186 (2) +LUT-Only LCs : 243 (2) +Register-Only LCs : 28 (3) +LUT/Register LCs : 195 (3) Full Hierarchy Name : |spectrum|ula:ula_ Library Name : work @@ -8682,7 +8762,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_ Library Name : work Compilation Hierarchy Node : |i2s_intf:i2s_intf_| -Logic Cells : 69 (69) +Logic Cells : 67 (67) Dedicated Logic Registers : 41 (41) I/O Registers : 0 (0) Memory Bits : 0 @@ -8692,9 +8772,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 28 (28) -Register-Only LCs : 1 (1) -LUT/Register LCs : 40 (40) +LUT-Only LCs : 25 (25) +Register-Only LCs : 0 (0) +LUT/Register LCs : 42 (42) Full Hierarchy Name : |spectrum|ula:ula_|i2s_intf:i2s_intf_ Library Name : work @@ -8750,7 +8830,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_|altpll:altpll_component Library Name : work Compilation Hierarchy Node : |ps2_keyboard:ps2_keyboard_| -Logic Cells : 30 (30) +Logic Cells : 31 (31) Dedicated Logic Registers : 24 (24) I/O Registers : 0 (0) Memory Bits : 0 @@ -8760,14 +8840,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 6 (6) -Register-Only LCs : 8 (8) -LUT/Register LCs : 16 (16) +LUT-Only LCs : 7 (7) +Register-Only LCs : 9 (9) +LUT/Register LCs : 15 (15) Full Hierarchy Name : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_ Library Name : work Compilation Hierarchy Node : |video:video_| -Logic Cells : 122 (122) +Logic Cells : 115 (115) Dedicated Logic Registers : 72 (72) I/O Registers : 0 (0) Memory Bits : 0 @@ -8777,14 +8857,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 50 (50) -Register-Only LCs : 23 (23) -LUT/Register LCs : 49 (49) +LUT-Only LCs : 43 (43) +Register-Only LCs : 16 (16) +LUT/Register LCs : 56 (56) Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -Logic Cells : 148 (148) +Logic Cells : 167 (167) Dedicated Logic Registers : 43 (43) I/O Registers : 0 (0) Memory Bits : 0 @@ -8794,14 +8874,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 99 (99) +LUT-Only LCs : 118 (118) Register-Only LCs : 0 (0) LUT/Register LCs : 49 (49) Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -Logic Cells : 1800 (2) +Logic Cells : 1822 (2) Dedicated Logic Registers : 362 (1) I/O Registers : 0 (0) Memory Bits : 0 @@ -8811,14 +8891,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1437 (1) -Register-Only LCs : 75 (0) -LUT/Register LCs : 288 (2) +LUT-Only LCs : 1460 (1) +Register-Only LCs : 84 (0) +LUT/Register LCs : 278 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -Logic Cells : 47 (18) +Logic Cells : 49 (17) Dedicated Logic Registers : 16 (16) I/O Registers : 0 (0) Memory Bits : 0 @@ -8828,14 +8908,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 29 (0) -Register-Only LCs : 2 (2) -LUT/Register LCs : 16 (16) +LUT-Only LCs : 33 (2) +Register-Only LCs : 1 (1) +LUT/Register LCs : 15 (14) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_ Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -Logic Cells : 29 (12) +Logic Cells : 32 (15) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8845,9 +8925,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 29 (12) +LUT-Only LCs : 31 (14) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec Library Name : work @@ -8964,14 +9044,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (15) +LUT-Only LCs : 16 (16) Register-Only LCs : 0 (0) -LUT/Register LCs : 17 (17) +LUT/Register LCs : 16 (16) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_ Library Name : work Compilation Hierarchy Node : |alu:alu_| -Logic Cells : 128 (91) +Logic Cells : 131 (95) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -8981,9 +9061,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 107 (70) -Register-Only LCs : 0 (0) -LUT/Register LCs : 21 (5) +LUT-Only LCs : 110 (74) +Register-Only LCs : 1 (1) +LUT/Register LCs : 20 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_ Library Name : work @@ -9005,7 +9085,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se Library Name : work Compilation Hierarchy Node : |alu_core:b2v_core| -Logic Cells : 20 (0) +Logic Cells : 21 (0) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9015,9 +9095,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 20 (0) +LUT-Only LCs : 19 (0) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 2 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core Library Name : work @@ -9039,7 +9119,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| -Logic Cells : 5 (5) +Logic Cells : 4 (4) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9049,7 +9129,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 5 (5) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1 @@ -9066,14 +9146,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) +LUT-Only LCs : 6 (6) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2 Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| -Logic Cells : 3 (3) +Logic Cells : 5 (5) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9083,9 +9163,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 3 (3) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3 Library Name : work @@ -9168,9 +9248,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 38 (33) +LUT-Only LCs : 39 (34) Register-Only LCs : 0 (0) -LUT/Register LCs : 3 (3) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_ Library Name : work @@ -9209,7 +9289,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -Logic Cells : 61 (61) +Logic Cells : 59 (59) Dedicated Logic Registers : 10 (10) I/O Registers : 0 (0) Memory Bits : 0 @@ -9219,7 +9299,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 51 (51) +LUT-Only LCs : 49 (49) Register-Only LCs : 0 (0) LUT/Register LCs : 10 (10) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_ @@ -9236,14 +9316,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 12 (12) +LUT-Only LCs : 16 (16) Register-Only LCs : 0 (0) -LUT/Register LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|bus_control:bus_control_ Library Name : work Compilation Hierarchy Node : |clk_delay:clk_delay_| -Logic Cells : 3 (3) +Logic Cells : 2 (2) Dedicated Logic Registers : 2 (2) I/O Registers : 0 (0) Memory Bits : 0 @@ -9253,27 +9333,10 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1 (1) -Register-Only LCs : 1 (1) -LUT/Register LCs : 1 (1) -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ -Library Name : work - -Compilation Hierarchy Node : |control_pins_n:control_pins_| -Logic Cells : 1 (1) -Dedicated Logic Registers : 0 (0) -I/O Registers : 0 (0) -Memory Bits : 0 -M9Ks : 0 -DSP Elements : 0 -DSP 9x9 : 0 -DSP 18x18 : 0 -Pins : 0 -Virtual Pins : 0 -LUT-Only LCs : 1 (1) +LUT-Only LCs : 0 (0) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_ +LUT/Register LCs : 2 (2) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ Library Name : work Compilation Hierarchy Node : |data_pins:data_pins_| @@ -9293,8 +9356,8 @@ LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_ Library Name : work -Compilation Hierarchy Node : |data_switch:sw2_| -Logic Cells : 1 (1) +Compilation Hierarchy Node : |data_switch_mask:sw1_| +Logic Cells : 5 (5) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9304,31 +9367,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1 (1) +LUT-Only LCs : 5 (5) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ -Library Name : work - -Compilation Hierarchy Node : |data_switch_mask:sw1_| -Logic Cells : 4 (4) -Dedicated Logic Registers : 0 (0) -I/O Registers : 0 (0) -Memory Bits : 0 -M9Ks : 0 -DSP Elements : 0 -DSP 9x9 : 0 -DSP 18x18 : 0 -Pins : 0 -Virtual Pins : 0 -LUT-Only LCs : 3 (3) -Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_ Library Name : work Compilation Hierarchy Node : |decode_state:decode_state_| -Logic Cells : 14 (14) +Logic Cells : 15 (15) Dedicated Logic Registers : 6 (6) I/O Registers : 0 (0) Memory Bits : 0 @@ -9340,12 +9386,12 @@ Pins : 0 Virtual Pins : 0 LUT-Only LCs : 8 (8) Register-Only LCs : 0 (0) -LUT/Register LCs : 6 (6) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode_state_ Library Name : work Compilation Hierarchy Node : |execute:execute_| -Logic Cells : 926 (926) +Logic Cells : 934 (934) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9355,14 +9401,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 917 (917) +LUT-Only LCs : 924 (924) Register-Only LCs : 0 (0) -LUT/Register LCs : 9 (9) +LUT/Register LCs : 10 (10) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_ Library Name : work Compilation Hierarchy Node : |interrupts:interrupts_| -Logic Cells : 14 (14) +Logic Cells : 16 (16) Dedicated Logic Registers : 8 (8) I/O Registers : 0 (0) Memory Bits : 0 @@ -9372,9 +9418,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 6 (6) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +LUT-Only LCs : 8 (8) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|interrupts:interrupts_ Library Name : work @@ -9390,13 +9436,13 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|ir:ir_ Library Name : work Compilation Hierarchy Node : |memory_ifc:memory_ifc_| -Logic Cells : 26 (26) +Logic Cells : 25 (25) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -9406,9 +9452,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 6 (6) -Register-Only LCs : 9 (9) -LUT/Register LCs : 11 (11) +LUT-Only LCs : 5 (5) +Register-Only LCs : 7 (7) +LUT/Register LCs : 13 (13) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_ Library Name : work @@ -9430,7 +9476,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_con Library Name : work Compilation Hierarchy Node : |pla_decode:pla_decode_| -Logic Cells : 74 (74) +Logic Cells : 71 (71) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9440,14 +9486,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 73 (73) +LUT-Only LCs : 70 (70) Register-Only LCs : 0 (0) LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_decode_ Library Name : work Compilation Hierarchy Node : |reg_control:reg_control_| -Logic Cells : 30 (30) +Logic Cells : 29 (29) Dedicated Logic Registers : 4 (4) I/O Registers : 0 (0) Memory Bits : 0 @@ -9457,14 +9503,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 26 (26) +LUT-Only LCs : 25 (25) Register-Only LCs : 0 (0) LUT/Register LCs : 4 (4) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_control_ Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -Logic Cells : 344 (124) +Logic Cells : 353 (129) Dedicated Logic Registers : 224 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -9474,9 +9520,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 120 (120) -Register-Only LCs : 61 (0) -LUT/Register LCs : 163 (150) +LUT-Only LCs : 129 (129) +Register-Only LCs : 67 (0) +LUT/Register LCs : 157 (148) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_ Library Name : work @@ -9526,8 +9572,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_hi Library Name : work @@ -9543,8 +9589,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 7 (7) -LUT/Register LCs : 1 (1) +Register-Only LCs : 8 (8) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo Library Name : work @@ -9560,8 +9606,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 8 (8) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_hi Library Name : work @@ -9594,8 +9640,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 7 (7) -LUT/Register LCs : 1 (1) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_hi Library Name : work @@ -9611,8 +9657,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 3 (3) -LUT/Register LCs : 5 (5) +Register-Only LCs : 5 (5) +LUT/Register LCs : 3 (3) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_lo Library Name : work @@ -9662,8 +9708,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 8 (8) -LUT/Register LCs : 0 (0) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_hi Library Name : work @@ -9679,8 +9725,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 5 (5) +LUT/Register LCs : 3 (3) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_lo Library Name : work @@ -9747,8 +9793,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 5 (5) -LUT/Register LCs : 3 (3) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo Library Name : work @@ -9798,8 +9844,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 8 (8) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_hi Library Name : work @@ -9815,8 +9861,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 2 (2) -LUT/Register LCs : 6 (6) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_lo Library Name : work @@ -9832,8 +9878,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_hi Library Name : work @@ -9849,8 +9895,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 3 (3) -LUT/Register LCs : 5 (5) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo Library Name : work @@ -9934,8 +9980,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi Library Name : work @@ -10221,6 +10267,14 @@ Pad to Input Register : -- TCO : -- TCOE : -- +Name : SW[2] +Pin Type : Input +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + Name : SW[3] Pin Type : Input Pad to Core 0 : -- @@ -10485,22 +10539,6 @@ Pad to Input Register : -- TCO : -- TCOE : -- -Name : GPIO_1[32] -Pin Type : Output -Pad to Core 0 : -- -Pad to Core 1 : -- -Pad to Input Register : -- -TCO : -- -TCOE : -- - -Name : GPIO_1[33] -Pin Type : Output -Pad to Core 0 : -- -Pad to Core 1 : -- -Pad to Input Register : -- -TCO : -- -TCOE : -- - Name : buzzer_out Pin Type : Output Pad to Core 0 : -- @@ -10693,6 +10731,14 @@ Pad to Input Register : -- TCO : (0) 0 ps TCOE : -- +Name : kempston_gnd +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + Name : I2C_SCLK Pin Type : Bidir Pad to Core 0 : -- @@ -10845,7 +10891,39 @@ Pad to Input Register : -- TCO : -- TCOE : -- -Name : SW[2] +Name : raw_loader_in +Pin Type : Input +Pad to Core 0 : (6) 1314 ps +Pad to Core 1 : (0) 0 ps +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : kempston[0] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : (0) 0 ps +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : kempston[1] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : (0) 0 ps +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : kempston[2] +Pin Type : Input +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : (0) 0 ps +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : kempston[3] Pin Type : Input Pad to Core 0 : (0) 0 ps Pad to Core 1 : -- @@ -10853,9 +10931,9 @@ Pad to Input Register : -- TCO : -- TCOE : -- -Name : raw_loader_in +Name : kempston[4] Pin Type : Input -Pad to Core 0 : (6) 1314 ps +Pad to Core 0 : (0) 0 ps Pad to Core 1 : (0) 0 ps Pad to Input Register : -- TCO : -- @@ -10877,7 +10955,7 @@ Pad to Input Register : -- TCO : -- TCOE : -- -Name : PS2_DAT +Name : turbo_button Pin Type : Input Pad to Core 0 : -- Pad to Core 1 : (6) 1314 ps @@ -10885,6 +10963,22 @@ Pad to Input Register : -- TCO : -- TCOE : -- +Name : kempston_autofire_button +Pin Type : Input +Pad to Core 0 : (6) 1314 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : PS2_DAT +Pin Type : Input +Pad to Core 0 : (6) 1314 ps +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + Name : KEY[1] Pin Type : Input Pad to Core 0 : (0) 0 ps @@ -10919,6 +11013,10 @@ Source Pin / Fanout : SW[0] Pad To Core Index : Setting : +Source Pin / Fanout : SW[2] +Pad To Core Index : +Setting : + Source Pin / Fanout : SW[3] Pad To Core Index : Setting : @@ -10936,11 +11034,11 @@ Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~1 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 0 -Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[1]~5 -Pad To Core Index : 1 +Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~5 +Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : DRAM_DQ[0] @@ -11011,15 +11109,11 @@ Source Pin / Fanout : SW[1] Pad To Core Index : Setting : -Source Pin / Fanout : SW[2] -Pad To Core Index : -Setting : - Source Pin / Fanout : raw_loader_in Pad To Core Index : Setting : -Source Pin / Fanout : - D[6]~99 +Source Pin / Fanout : - D[6]~28 Pad To Core Index : 1 Setting : 0 @@ -11027,10 +11121,70 @@ Source Pin / Fanout : - ula:ula_|beep~0 Pad To Core Index : 0 Setting : 6 +Source Pin / Fanout : - LED[1]~output +Pad To Core Index : 1 +Setting : 0 + +Source Pin / Fanout : kempston[0] +Pad To Core Index : +Setting : + +Source Pin / Fanout : - Selector8~4 +Pad To Core Index : 0 +Setting : 0 + Source Pin / Fanout : - LED[3]~output Pad To Core Index : 1 Setting : 0 +Source Pin / Fanout : kempston[1] +Pad To Core Index : +Setting : + +Source Pin / Fanout : - Selector10~2 +Pad To Core Index : 1 +Setting : 0 + +Source Pin / Fanout : - LED[4]~output +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : kempston[2] +Pad To Core Index : +Setting : + +Source Pin / Fanout : - Selector12~4 +Pad To Core Index : 1 +Setting : 0 + +Source Pin / Fanout : - LED[5]~output +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : kempston[3] +Pad To Core Index : +Setting : + +Source Pin / Fanout : - Selector14~8 +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : - LED[6]~output +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : kempston[4] +Pad To Core Index : +Setting : + +Source Pin / Fanout : - LED~0 +Pad To Core Index : 0 +Setting : 0 + +Source Pin / Fanout : - Selector6~6 +Pad To Core Index : 1 +Setting : 0 + Source Pin / Fanout : KEY[0] Pad To Core Index : Setting : @@ -11043,20 +11197,44 @@ Source Pin / Fanout : CLOCK_50 Pad To Core Index : Setting : +Source Pin / Fanout : turbo_button +Pad To Core Index : +Setting : + +Source Pin / Fanout : - debouncer:debounce_turbo|r_State~6 +Pad To Core Index : 1 +Setting : 6 + +Source Pin / Fanout : - debouncer:debounce_turbo|always0~2 +Pad To Core Index : 1 +Setting : 6 + +Source Pin / Fanout : kempston_autofire_button +Pad To Core Index : +Setting : + +Source Pin / Fanout : - debouncer:debounce_autofire|r_State~6 +Pad To Core Index : 0 +Setting : 6 + +Source Pin / Fanout : - debouncer:debounce_autofire|always0~2 +Pad To Core Index : 0 +Setting : 6 + Source Pin / Fanout : PS2_DAT Pad To Core Index : Setting : Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|always1~0 -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 6 Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 6 Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready~0 -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 6 Source Pin / Fanout : KEY[1] @@ -11075,7 +11253,7 @@ Source Pin / Fanout : AUD_ADCDAT Pad To Core Index : Setting : -Source Pin / Fanout : - ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]~20 +Source Pin / Fanout : - ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]~19 Pad To Core Index : 0 Setting : 0 +--------------------------------------------------------------------------------+ @@ -11087,25 +11265,25 @@ Setting : 0 +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 3 -Usage : Clock -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : CLOCK_50 -Location : PIN_R8 -Fan-Out : 34 +Fan-Out : 76 Usage : Clock Global : yes Global Resource Used : Global Clock Global Line Name : GCLK15 Enable Signal Source Name : -- -Name : D[0]~121 -Location : LCCOMB_X25_Y17_N24 -Fan-Out : 8 +Name : CLOCK_50 +Location : PIN_R8 +Fan-Out : 5 +Usage : Clock +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : D[0]~49 +Location : LCCOMB_X23_Y17_N30 +Fan-Out : 12 Usage : Output enable Global : no Global Resource Used : -- @@ -11121,8 +11299,53 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 -Location : LCCOMB_X21_Y13_N24 +Name : debouncer:debounce_autofire|always0~2 +Location : LCCOMB_X19_Y14_N22 +Fan-Out : 21 +Usage : Sync. clear +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : debouncer:debounce_autofire|r_State +Location : FF_X18_Y14_N19 +Fan-Out : 3 +Usage : Clock +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : debouncer:debounce_turbo|always0~2 +Location : LCCOMB_X25_Y27_N0 +Fan-Out : 21 +Usage : Sync. clear +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : debouncer:debounce_turbo|r_State +Location : FF_X25_Y27_N5 +Fan-Out : 3 +Usage : Clock +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : kempston_autofire_enabled +Location : FF_X18_Y14_N31 +Fan-Out : 20 +Usage : Clock enable, Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~1 +Location : LCCOMB_X23_Y17_N12 Fan-Out : 8 Usage : Write enable Global : no @@ -11130,8 +11353,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 -Location : LCCOMB_X23_Y18_N0 +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~0 +Location : LCCOMB_X24_Y15_N28 Fan-Out : 8 Usage : Write enable Global : no @@ -11140,7 +11363,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 -Location : LCCOMB_X25_Y8_N4 +Location : LCCOMB_X24_Y16_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -11149,7 +11372,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] -Location : LCCOMB_X23_Y15_N22 +Location : LCCOMB_X24_Y16_N26 Fan-Out : 8 Usage : Write enable Global : no @@ -11158,7 +11381,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 -Location : LCCOMB_X25_Y8_N10 +Location : LCCOMB_X29_Y12_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -11167,7 +11390,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] -Location : LCCOMB_X21_Y13_N0 +Location : LCCOMB_X23_Y17_N22 Fan-Out : 8 Usage : Write enable Global : no @@ -11176,7 +11399,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] -Location : LCCOMB_X21_Y13_N6 +Location : LCCOMB_X23_Y17_N20 Fan-Out : 8 Usage : Write enable Global : no @@ -11185,7 +11408,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 -Location : LCCOMB_X25_Y8_N0 +Location : LCCOMB_X24_Y16_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -11194,7 +11417,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] -Location : LCCOMB_X21_Y13_N14 +Location : LCCOMB_X23_Y17_N14 Fan-Out : 8 Usage : Write enable Global : no @@ -11203,7 +11426,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 -Location : LCCOMB_X25_Y8_N22 +Location : LCCOMB_X21_Y15_N2 Fan-Out : 8 Usage : Clock enable Global : no @@ -11212,16 +11435,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y14_N12 +Location : LCCOMB_X52_Y14_N4 Fan-Out : 149 Usage : Async. clear, Async. load Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK9 +Global Line Name : GCLK8 Enable Signal Source Name : -- Name : sdram_controller:sdram_|Mux13~5 -Location : LCCOMB_X20_Y7_N2 +Location : LCCOMB_X21_Y16_N20 Fan-Out : 7 Usage : Clock enable Global : no @@ -11230,7 +11453,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : sdram_controller:sdram_|Mux19~0 -Location : LCCOMB_X21_Y11_N2 +Location : LCCOMB_X21_Y16_N30 Fan-Out : 6 Usage : Clock enable Global : no @@ -11239,7 +11462,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : sdram_controller:sdram_|Mux84~1 -Location : LCCOMB_X19_Y15_N2 +Location : LCCOMB_X23_Y19_N28 Fan-Out : 16 Usage : Output enable Global : no @@ -11247,8 +11470,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : sdram_controller:sdram_|r.act_row[1]~1 -Location : LCCOMB_X21_Y12_N0 +Name : sdram_controller:sdram_|r.act_row[2]~1 +Location : LCCOMB_X21_Y14_N26 Fan-Out : 5 Usage : Clock enable Global : no @@ -11256,8 +11479,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : sdram_controller:sdram_|r.address[3]~17 -Location : LCCOMB_X19_Y8_N26 +Name : sdram_controller:sdram_|r.address[3]~20 +Location : LCCOMB_X19_Y13_N18 Fan-Out : 6 Usage : Clock enable Global : no @@ -11265,8 +11488,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : sdram_controller:sdram_|r.bank[0]~9 -Location : LCCOMB_X19_Y8_N2 +Name : sdram_controller:sdram_|r.bank[0]~11 +Location : LCCOMB_X19_Y13_N26 Fan-Out : 2 Usage : Clock enable Global : no @@ -11274,8 +11497,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : sdram_controller:sdram_|r.rf_counter[3]~32 -Location : LCCOMB_X20_Y13_N26 +Name : sdram_controller:sdram_|r.rf_counter[8]~32 +Location : LCCOMB_X20_Y13_N30 Fan-Out : 10 Usage : Sync. clear Global : no @@ -11284,8 +11507,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : sdram_controller:sdram_|r.state[7] -Location : FF_X19_Y15_N21 -Fan-Out : 45 +Location : FF_X23_Y19_N11 +Fan-Out : 53 Usage : Sync. load Global : no Global Resource Used : -- @@ -11302,7 +11525,7 @@ Global Line Name : GCLK4 Enable Signal Source Name : -- Name : ula:ula_|always0~3 -Location : LCCOMB_X23_Y19_N2 +Location : LCCOMB_X23_Y17_N24 Fan-Out : 7 Usage : Clock enable Global : no @@ -11311,16 +11534,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu -Location : FF_X25_Y33_N5 -Fan-Out : 435 +Location : FF_X25_Y33_N1 +Fan-Out : 454 Usage : Clock Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK14 +Global Line Name : GCLK12 Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|WideAnd0 -Location : LCCOMB_X1_Y24_N30 +Location : LCCOMB_X3_Y24_N4 Fan-Out : 17 Usage : Clock enable Global : no @@ -11328,8 +11551,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~3 -Location : LCCOMB_X2_Y23_N26 +Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 +Location : LCCOMB_X1_Y23_N8 Fan-Out : 3 Usage : Clock enable Global : no @@ -11338,7 +11561,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 -Location : LCCOMB_X1_Y23_N20 +Location : LCCOMB_X2_Y23_N8 Fan-Out : 2 Usage : Clock enable Global : no @@ -11347,16 +11570,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Location : FF_X2_Y24_N9 -Fan-Out : 22 +Location : FF_X1_Y23_N29 +Fan-Out : 23 Usage : Sync. load Global : no Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 -Location : LCCOMB_X2_Y24_N0 +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~28 +Location : LCCOMB_X1_Y23_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -11364,8 +11587,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~12 -Location : LCCOMB_X2_Y24_N14 +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 +Location : LCCOMB_X2_Y23_N6 Fan-Out : 6 Usage : Clock enable Global : no @@ -11374,7 +11597,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|state.Start -Location : FF_X2_Y24_N31 +Location : FF_X2_Y22_N29 Fan-Out : 20 Usage : Sync. clear, Sync. load Global : no @@ -11392,7 +11615,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|Equal0~2 -Location : LCCOMB_X20_Y31_N2 +Location : LCCOMB_X25_Y30_N26 Fan-Out : 37 Usage : Sync. load Global : no @@ -11400,8 +11623,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 -Location : LCCOMB_X24_Y32_N28 +Name : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~9 +Location : LCCOMB_X24_Y23_N8 Fan-Out : 5 Usage : Clock enable Global : no @@ -11409,8 +11632,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~2 -Location : LCCOMB_X24_Y32_N10 +Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]~1 +Location : LCCOMB_X24_Y23_N2 Fan-Out : 17 Usage : Clock enable Global : no @@ -11446,7 +11669,7 @@ Global Line Name : GCLK19 Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge -Location : FF_X17_Y27_N17 +Location : FF_X14_Y29_N1 Fan-Out : 6 Usage : Clock enable Global : no @@ -11455,8 +11678,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready -Location : FF_X18_Y12_N25 -Fan-Out : 8 +Location : FF_X18_Y21_N9 +Fan-Out : 7 Usage : Clock enable Global : no Global Resource Used : -- @@ -11464,7 +11687,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 -Location : LCCOMB_X18_Y12_N6 +Location : LCCOMB_X18_Y21_N30 Fan-Out : 9 Usage : Clock enable Global : no @@ -11473,7 +11696,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~0 -Location : LCCOMB_X30_Y29_N10 +Location : LCCOMB_X29_Y31_N14 Fan-Out : 16 Usage : Clock enable Global : no @@ -11482,7 +11705,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~1 -Location : LCCOMB_X30_Y29_N20 +Location : LCCOMB_X30_Y31_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -11491,7 +11714,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~2 -Location : LCCOMB_X30_Y29_N14 +Location : LCCOMB_X30_Y31_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -11500,7 +11723,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Equal3~1 -Location : LCCOMB_X32_Y30_N16 +Location : LCCOMB_X31_Y31_N4 Fan-Out : 16 Usage : Clock enable Global : no @@ -11508,8 +11731,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|video:video_|vram_address[8]~1 -Location : LCCOMB_X30_Y29_N2 +Name : ula:ula_|video:video_|vram_address[9]~1 +Location : LCCOMB_X30_Y31_N0 Fan-Out : 4 Usage : Clock enable Global : no @@ -11518,7 +11741,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|vram_address~0 -Location : LCCOMB_X30_Y29_N8 +Location : LCCOMB_X30_Y31_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -11526,9 +11749,9 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~23 -Location : LCCOMB_X23_Y9_N30 -Fan-Out : 47 +Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 +Location : LCCOMB_X29_Y12_N30 +Fan-Out : 48 Usage : Clock enable Global : no Global Resource Used : -- @@ -11536,7 +11759,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 -Location : LCCOMB_X28_Y10_N28 +Location : LCCOMB_X24_Y11_N20 Fan-Out : 4 Usage : Clock enable Global : no @@ -11545,7 +11768,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena -Location : LCCOMB_X28_Y10_N0 +Location : LCCOMB_X24_Y11_N30 Fan-Out : 4 Usage : Clock enable Global : no @@ -11554,7 +11777,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena -Location : LCCOMB_X26_Y9_N22 +Location : LCCOMB_X23_Y12_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -11563,7 +11786,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq -Location : LCCOMB_X39_Y14_N4 +Location : LCCOMB_X30_Y11_N14 Fan-Out : 24 Usage : Clock enable Global : no @@ -11572,7 +11795,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 -Location : LCCOMB_X28_Y12_N16 +Location : LCCOMB_X26_Y16_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -11580,8 +11803,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 -Location : LCCOMB_X36_Y12_N8 +Name : z80_top_direct_n:z80_|execute:execute_|ctl_al_we~10 +Location : LCCOMB_X36_Y11_N16 Fan-Out : 16 Usage : Clock enable Global : no @@ -11590,7 +11813,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low -Location : LCCOMB_X29_Y7_N4 +Location : LCCOMB_X27_Y14_N6 Fan-Out : 17 Usage : Clock enable Global : no @@ -11599,7 +11822,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 -Location : LCCOMB_X30_Y12_N6 +Location : LCCOMB_X30_Y11_N24 Fan-Out : 16 Usage : Sync. load Global : no @@ -11608,7 +11831,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 -Location : LCCOMB_X29_Y10_N0 +Location : LCCOMB_X26_Y13_N16 Fan-Out : 2 Usage : Clock enable Global : no @@ -11617,7 +11840,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 -Location : LCCOMB_X29_Y10_N20 +Location : LCCOMB_X27_Y11_N18 Fan-Out : 2 Usage : Clock enable Global : no @@ -11626,7 +11849,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_im_we -Location : LCCOMB_X30_Y12_N16 +Location : LCCOMB_X32_Y14_N28 Fan-Out : 3 Usage : Clock enable Global : no @@ -11634,8 +11857,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 -Location : LCCOMB_X37_Y9_N10 +Name : z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~17 +Location : LCCOMB_X29_Y17_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -11644,7 +11867,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 -Location : LCCOMB_X37_Y7_N14 +Location : LCCOMB_X31_Y17_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -11653,7 +11876,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 -Location : LCCOMB_X37_Y7_N16 +Location : LCCOMB_X29_Y18_N28 Fan-Out : 2 Usage : Clock enable Global : no @@ -11662,16 +11885,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|fpga_reset -Location : FF_X26_Y32_N9 -Fan-Out : 2 -Usage : Async. clear -Global : yes -Global Resource Used : Global Clock -Global Line Name : GCLK10 -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X30_Y11_N4 +Location : FF_X27_Y1_N29 Fan-Out : 2 Usage : Async. clear Global : yes @@ -11679,8 +11893,17 @@ Global Resource Used : Global Clock Global Line Name : GCLK16 Enable Signal Source Name : -- +Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 +Location : LCCOMB_X30_Y12_N16 +Fan-Out : 2 +Usage : Async. clear +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK7 +Enable Signal Source Name : -- + Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_15 -Location : LCCOMB_X30_Y11_N24 +Location : LCCOMB_X30_Y11_N12 Fan-Out : 1 Usage : Async. clear Global : no @@ -11689,7 +11912,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_9 -Location : LCCOMB_X30_Y11_N30 +Location : LCCOMB_X23_Y11_N14 Fan-Out : 1 Usage : Async. clear Global : no @@ -11697,8 +11920,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 -Location : LCCOMB_X30_Y12_N30 +Name : z80_top_direct_n:z80_|interrupts:interrupts_|test1~4 +Location : LCCOMB_X30_Y11_N28 Fan-Out : 2 Usage : Clock enable Global : no @@ -11707,7 +11930,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 -Location : LCCOMB_X32_Y12_N12 +Location : LCCOMB_X27_Y15_N30 Fan-Out : 16 Usage : Clock enable Global : no @@ -11716,7 +11939,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 -Location : LCCOMB_X26_Y13_N2 +Location : LCCOMB_X30_Y9_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -11725,7 +11948,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 -Location : LCCOMB_X27_Y17_N6 +Location : LCCOMB_X30_Y9_N2 Fan-Out : 8 Usage : Clock enable Global : no @@ -11734,7 +11957,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 -Location : LCCOMB_X26_Y13_N28 +Location : LCCOMB_X30_Y9_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -11743,7 +11966,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 -Location : LCCOMB_X29_Y14_N22 +Location : LCCOMB_X30_Y9_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -11752,7 +11975,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 -Location : LCCOMB_X28_Y14_N18 +Location : LCCOMB_X29_Y7_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -11761,7 +11984,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 -Location : LCCOMB_X30_Y13_N6 +Location : LCCOMB_X30_Y9_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -11770,7 +11993,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 -Location : LCCOMB_X28_Y14_N12 +Location : LCCOMB_X29_Y7_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -11779,7 +12002,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 -Location : LCCOMB_X29_Y14_N30 +Location : LCCOMB_X30_Y9_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -11788,7 +12011,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 -Location : LCCOMB_X27_Y17_N22 +Location : LCCOMB_X27_Y7_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -11797,7 +12020,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 -Location : LCCOMB_X27_Y17_N24 +Location : LCCOMB_X30_Y7_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -11806,7 +12029,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 -Location : LCCOMB_X27_Y17_N8 +Location : LCCOMB_X27_Y7_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -11815,7 +12038,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 -Location : LCCOMB_X27_Y17_N18 +Location : LCCOMB_X30_Y7_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -11824,7 +12047,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 -Location : LCCOMB_X27_Y17_N26 +Location : LCCOMB_X31_Y10_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -11833,7 +12056,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 -Location : LCCOMB_X30_Y13_N24 +Location : LCCOMB_X31_Y10_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -11842,7 +12065,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 -Location : LCCOMB_X27_Y17_N12 +Location : LCCOMB_X31_Y10_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -11851,7 +12074,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 -Location : LCCOMB_X28_Y15_N10 +Location : LCCOMB_X31_Y10_N14 Fan-Out : 8 Usage : Clock enable Global : no @@ -11860,7 +12083,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 -Location : LCCOMB_X30_Y16_N0 +Location : LCCOMB_X35_Y10_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -11869,7 +12092,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 -Location : LCCOMB_X30_Y16_N12 +Location : LCCOMB_X35_Y10_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -11878,7 +12101,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 -Location : LCCOMB_X28_Y14_N0 +Location : LCCOMB_X29_Y7_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -11887,7 +12110,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 -Location : LCCOMB_X28_Y14_N14 +Location : LCCOMB_X30_Y9_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -11896,7 +12119,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 -Location : LCCOMB_X27_Y14_N26 +Location : LCCOMB_X31_Y10_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -11905,7 +12128,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 -Location : LCCOMB_X27_Y14_N0 +Location : LCCOMB_X31_Y10_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -11914,7 +12137,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 -Location : LCCOMB_X30_Y16_N2 +Location : LCCOMB_X35_Y10_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -11923,7 +12146,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 -Location : LCCOMB_X30_Y16_N30 +Location : LCCOMB_X35_Y10_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -11932,7 +12155,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 -Location : LCCOMB_X28_Y14_N26 +Location : LCCOMB_X29_Y7_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -11941,7 +12164,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 -Location : LCCOMB_X29_Y15_N30 +Location : LCCOMB_X30_Y9_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -11950,7 +12173,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 -Location : LCCOMB_X30_Y16_N18 +Location : LCCOMB_X35_Y10_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -11959,7 +12182,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 -Location : LCCOMB_X30_Y16_N28 +Location : LCCOMB_X35_Y10_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -11968,8 +12191,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X31_Y14_N1 -Fan-Out : 79 +Location : FF_X27_Y15_N17 +Fan-Out : 73 Usage : Output enable Global : no Global Resource Used : -- @@ -11977,12 +12200,12 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X31_Y14_N1 +Location : FF_X27_Y15_N17 Fan-Out : 72 Usage : Async. clear Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK7 +Global Line Name : GCLK9 Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ @@ -11993,18 +12216,18 @@ Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 34 +Fan-Out : 76 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock Global Line Name : GCLK15 Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y14_N12 +Location : LCCOMB_X52_Y14_N4 Fan-Out : 149 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK9 +Global Line Name : GCLK8 Enable Signal Source Name : -- Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] @@ -12016,17 +12239,17 @@ Global Line Name : GCLK4 Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu -Location : FF_X25_Y33_N5 -Fan-Out : 435 +Location : FF_X25_Y33_N1 +Fan-Out : 454 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK14 +Global Line Name : GCLK12 Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Location : PLL_4 Fan-Out : 110 -Fan-Out Using Intentional Clock Skew : 18 +Fan-Out Using Intentional Clock Skew : 16 Global Resource Used : Global Clock Global Line Name : GCLK18 Enable Signal Source Name : -- @@ -12034,7 +12257,7 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] Location : PLL_4 Fan-Out : 2 -Fan-Out Using Intentional Clock Skew : 2 +Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock Global Line Name : GCLK17 Enable Signal Source Name : -- @@ -12042,1044 +12265,1044 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] Location : PLL_4 Fan-Out : 82 -Fan-Out Using Intentional Clock Skew : 26 +Fan-Out Using Intentional Clock Skew : 27 Global Resource Used : Global Clock Global Line Name : GCLK19 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|fpga_reset -Location : FF_X26_Y32_N9 -Fan-Out : 2 -Fan-Out Using Intentional Clock Skew : 0 -Global Resource Used : Global Clock -Global Line Name : GCLK10 -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X30_Y11_N4 +Location : FF_X27_Y1_N29 Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock Global Line Name : GCLK16 Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X31_Y14_N1 -Fan-Out : 72 +Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 +Location : LCCOMB_X30_Y12_N16 +Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock Global Line Name : GCLK7 Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Location : FF_X27_Y15_N17 +Fan-Out : 72 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK9 +Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+---------------------------------------------------------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+---------------------------------------------------------------------------------------------------------------------------------+---------+ -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 78 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 73 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~24 ; 71 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~17 ; 69 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~20 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~16 ; 68 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[4]~28 ; 66 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~27 ; 66 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~26 ; 65 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~25 ; 65 ; -; sdram_controller:sdram_|r.state[4] ; 65 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]~31 ; 64 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]~30 ; 64 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]~29 ; 64 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 62 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 58 ; -; sdram_controller:sdram_|r.state[8] ; 57 ; -; sdram_controller:sdram_|r.state[6] ; 55 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 55 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 52 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 52 ; -; z80_top_direct_n:z80_|nM1_int~2 ; 48 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~23 ; 47 ; -; sdram_controller:sdram_|r.state[7] ; 45 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 42 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~8 ; 41 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 41 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 41 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 40 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 39 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 39 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~2 ; 39 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 38 ; -; ula:ula_|zx_keyboard:zx_keyboard_|released ; 38 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 38 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 37 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 37 ; -; ula:ula_|i2s_intf:i2s_intf_|Equal0~2 ; 37 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 36 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 34 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 34 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 34 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 33 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 33 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 33 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 33 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~14 ; 33 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 32 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~16 ; 31 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 31 ; -; sdram_controller:sdram_|r.state[5] ; 29 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 29 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 29 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 29 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 28 ; -; Equal2~1 ; 28 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 27 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~34 ; 26 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 26 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 25 ; -; ~GND ; 24 ; -; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq ; 24 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 24 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~46 ; 23 ; -; sdram_controller:sdram_|r.rd_pending ; 23 ; -; sdram_controller:sdram_|r.wr_pending ; 23 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 23 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~22 ; 23 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~21 ; 23 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Data ; 23 ; -; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 22 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~14 ; 22 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~1 ; 22 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~3 ; 22 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~35 ; 21 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~31 ; 21 ; -; sdram_controller:sdram_|Equal7~2 ; 21 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 21 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Start ; 20 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 20 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 20 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 19 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 19 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 19 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~6 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~38 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_we~7 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 18 ; -; sdram_controller:sdram_|r.rf_pending ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 18 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 18 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~17 ; 17 ; -; ula:ula_|i2c_loader:i2c_loader_|WideAnd0 ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 17 ; -; ula:ula_|video:video_|vram_address[10] ; 17 ; -; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 17 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 17 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 17 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~2 ; 17 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 ; 16 ; -; sdram_controller:sdram_|Mux84~1 ; 16 ; -; ula:ula_|video:video_|vram_address[12] ; 16 ; -; ula:ula_|video:video_|vram_address[11] ; 16 ; -; ula:ula_|video:video_|vram_address[9] ; 16 ; -; ula:ula_|video:video_|vram_address[8] ; 16 ; -; ula:ula_|video:video_|vram_address[7] ; 16 ; -; ula:ula_|video:video_|vram_address[6] ; 16 ; -; ula:ula_|video:video_|vram_address[5] ; 16 ; -; ula:ula_|video:video_|vram_address[4] ; 16 ; -; ula:ula_|video:video_|vram_address[3] ; 16 ; -; ula:ula_|video:video_|vram_address[2] ; 16 ; -; ula:ula_|video:video_|vram_address[1] ; 16 ; -; ula:ula_|video:video_|vram_address[0] ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; -; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~53 ; 16 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 16 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 16 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 16 ; -; ula:ula_|video:video_|Decoder0~0 ; 16 ; -; ula:ula_|video:video_|Equal3~1 ; 16 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_exx ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 15 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~2 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 15 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~7 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 15 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 15 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 15 ; -; ula:ula_|video:video_|Equal1~0 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~15 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~90 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~80 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]~71 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]~61 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]~51 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]~41 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[1]~32 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~84 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~75 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~66 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~57 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~48 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~39 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~30 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~21 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~22 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~9 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 14 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 14 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 14 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|in_halt ; 14 ; -; ula:ula_|video:video_|vga_hc[2] ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~7 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~8 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~5 ; 13 ; -; Equal2~0 ; 13 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 13 ; -; ula:ula_|video:video_|vga_hc[1] ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~14 ; 12 ; -; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 12 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 12 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 12 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 12 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] ; 12 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 12 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 11 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 11 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~15 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~14 ; 11 ; -; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~11 ; 11 ; -; sdram_controller:sdram_|process_0~2 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~2 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~2 ; 11 ; -; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] ; 11 ; -; sdram_controller:sdram_|r.rf_counter[3]~32 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~2 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~4 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~6 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 10 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 10 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_48 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_44 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_34 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_30 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_50 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_46 ; 9 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Idle ; 9 ; -; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 9 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Ack ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_zero ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_lq ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~14 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~7 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_80 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_76~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~11 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_64~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_40~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_36~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~8 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_38~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~2 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~7 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_oe~1 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_oe~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_72 ; 9 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sw_4d_hi~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_60 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 9 ; -; sdram_controller:sdram_|r.init_counter[0] ; 9 ; -; D[4]~111 ; 9 ; -; D[3]~109 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~18 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~3 ; 9 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 9 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; -; ula:ula_|video:video_|vga_hc[3] ; 9 ; -; ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 8 ; -; D[0]~121 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; -; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena ; 8 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~9 ; 8 ; -; ula:ula_|video:video_|vram_address~0 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~20 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~21 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus ; 8 ; -; D[7]~117 ; 8 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 ; 8 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re ; 8 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~6 ; 8 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~4 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] ; 8 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 ; 8 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 ; 8 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~11 ; 8 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~2 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~25 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~29 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~20 ; 8 ; -; ula:ula_|video:video_|Decoder0~2 ; 8 ; -; ula:ula_|video:video_|Decoder0~1 ; 8 ; -; sdram_controller:sdram_|r.init_counter[1] ; 8 ; -; sdram_controller:sdram_|r.init_counter[7] ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal48~0 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~1 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~9 ; 8 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~3 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal37~0 ; 8 ; -; D[0]~65 ; 8 ; -; D[2]~53 ; 8 ; -; D[1]~41 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~0 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~2 ; 8 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 8 ; -; ula:ula_|video:video_|vga_hc[0] ; 8 ; -; ula:ula_|video:video_|vga_hc[6] ; 8 ; -; ula:ula_|video:video_|vga_vc[5] ; 8 ; -; ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] ; 8 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 7 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal38~2 ; 7 ; -; ula:ula_|always0~3 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 7 ; -; ula:ula_|i2c_loader:i2c_loader_|nbyte[0] ; 7 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 7 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~13 ; 7 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~7 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~19 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~7 ; 7 ; -; D[6]~115 ; 7 ; -; D[5]~113 ; 7 ; -; ExtRamWE~0 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~33 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 7 ; -; sdram_controller:sdram_|r.address[3]~8 ; 7 ; -; sdram_controller:sdram_|Mux13~5 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 7 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 7 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 7 ; -; ula:ula_|video:video_|vga_hc[8] ; 7 ; -; ula:ula_|video:video_|vga_hc[7] ; 7 ; -; ula:ula_|video:video_|vga_vc[9] ; 7 ; -; ula:ula_|video:video_|vga_vc[1] ; 7 ; -; ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] ; 7 ; -; ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] ; 7 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~13 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~9 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~33 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~47 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 6 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~12 ; 6 ; -; ula:ula_|i2c_loader:i2c_loader_|nbyte[1] ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~20 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[0]~18 ; 6 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] ; 6 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] ; 6 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[2] ; 6 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~6 ; 6 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|rsel3 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[1]~19 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 6 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla82M1T1_16 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~24 ; 6 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~19 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 6 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~1 ; 6 ; -; sdram_controller:sdram_|r.address[3]~17 ; 6 ; -; sdram_controller:sdram_|Mux19~0 ; 6 ; -; sdram_controller:sdram_|Equal2~2 ; 6 ; -; sdram_controller:sdram_|r.address[3]~6 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~10 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 6 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 6 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_39 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~8 ; 6 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 6 ; -; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; -; ula:ula_|video:video_|screen_en~1 ; 6 ; -; ula:ula_|video:video_|vga_hc[9] ; 6 ; -; ula:ula_|video:video_|vga_vc[8] ; 6 ; -; ula:ula_|video:video_|vga_vc[7] ; 6 ; -; ula:ula_|video:video_|vga_vc[4] ; 6 ; -; ula:ula_|video:video_|vga_vc[6] ; 6 ; -; ula:ula_|video:video_|vga_vc[3] ; 6 ; -; ula:ula_|video:video_|vga_vc[2] ; 6 ; -; ula:ula_|video:video_|vga_vc[0] ; 6 ; -; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla89M1T2_3 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[0]~27 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~26 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~16 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 ; 5 ; -; ula:ula_|i2c_loader:i2c_loader_|nbit[0] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[5]~24 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[6]~22 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[1]~16 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_low ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[3]~14 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[2]~12 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[4]~10 ; 5 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~33 ; 5 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_mask543_en~0 ; 5 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 5 ; -; sdram_controller:sdram_|r.act_row[1]~1 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[0]~25 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[2]~13 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[1] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~30 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[1]~20 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~14 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~1 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~38 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[13] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_ir~1 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 5 ; -; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 ; 5 ; -; sdram_controller:sdram_|Mux24~2 ; 5 ; -; sdram_controller:sdram_|n~3 ; 5 ; -; sdram_controller:sdram_|n~2 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~8 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~7 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal29~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMWrite~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~0 ; 5 ; -; z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ~1 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~2 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~15 ; 5 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~1 ; 5 ; -; ula:ula_|i2s_intf:i2s_intf_|Equal1~0 ; 5 ; -; ula:ula_|video:video_|vga_hc[5] ; 5 ; -; ula:ula_|video:video_|vga_hc[4] ; 5 ; -; ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 ; 5 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~41 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~3 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~37 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_iy~2 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~40 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf2_we ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~8 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~14 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla57M1T4_4 ; 4 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Pause ; 4 ; -; ula:ula_|i2c_loader:i2c_loader_|nbit[1] ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69~2 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71~2 ; 4 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Stop ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~36 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~30 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~27 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~23 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~17 ; 4 ; -; ula:ula_|video:video_|vram_address[8]~1 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af2~0 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~14 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~40 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~3 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~2 ; 4 ; -; sdram_controller:sdram_|Mux4~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 4 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_cf ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla66npla53M1T1_15 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 4 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~9 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~10 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~1 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]~24 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[6]~21 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[5]~18 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[4]~15 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[3]~12 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]~9 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]~6 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~73 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~2 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~44 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~39 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~24 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~21 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~18 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~28 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~15 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[12] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~21 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~20 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~12 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~9 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[10] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~6 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~3 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[8] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[6] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[3] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[5] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~24 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~21 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~20 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~17 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~34 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~20 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~11 ; 4 ; -; sdram_controller:sdram_|Mux23~0 ; 4 ; -; sdram_controller:sdram_|process_0~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~14 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~2 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla42M3T3_6 ; 4 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~4 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~2 ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] ; 4 ; -; D[5]~97 ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[5] ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 4 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~4 ; 4 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 4 ; -; ula:ula_|i2s_intf:i2s_intf_|Equal1~1 ; 4 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_16 ; 4 ; -; ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 ; 4 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 4 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 4 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] ; 4 ; -; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; -; sdram_controller:sdram_|r.address[0]~_Duplicate_1 ; 4 ; -; PS2_DAT~input ; 3 ; -; raw_loader_in~input ; 3 ; -; I2C_SDAT~input ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_use_cf2~13 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~99 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~12 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~39 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~18 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_im_we ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~21 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~34 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~21 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~94 ; 3 ; -; sdram_controller:sdram_|n~5 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~35 ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~3 ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|state~24 ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|nbit[2] ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg~4 ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|divider[0] ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|scl_out~0 ; 3 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_instIFF2 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf~0 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~17 ; 3 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~2 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~5 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|rsel0 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~26 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~12 ; 3 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_pf ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~11 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|result~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~1 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[0] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~14 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~15 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~35 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~28 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_sf ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_nop3pla68M3T1_20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~12 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~12 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[0] ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~25 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~28 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~9 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~0 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~59 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~48 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~43 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~13 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~11 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~9 ; 3 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~7 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~1 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~32 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|carry_borrow_out~0 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~15 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|carry_borrow_out~0 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|carry_borrow_out~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~36 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~23 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~21 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~93 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~81 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~61 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~52 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~15 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~35 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~7 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~50 ; 3 ; -; sdram_controller:sdram_|Mux13~6 ; 3 ; -; sdram_controller:sdram_|Mux23~7 ; 3 ; -; sdram_controller:sdram_|r.init_counter[4] ; 3 ; -; sdram_controller:sdram_|r.init_counter[5] ; 3 ; -; sdram_controller:sdram_|r.init_counter[6] ; 3 ; -; sdram_controller:sdram_|r.init_counter[3] ; 3 ; -; sdram_controller:sdram_|r.init_counter[2] ; 3 ; -; sdram_controller:sdram_|r.init_counter[8] ; 3 ; -; sdram_controller:sdram_|r.init_counter[9] ; 3 ; -; sdram_controller:sdram_|r.init_counter[10] ; 3 ; -; sdram_controller:sdram_|Mux71~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~49 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~47 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~46 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~41 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal4~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~37 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~30 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~2 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~2 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal79~0 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~2 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc~2 ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[7] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~8 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal46~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~28 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~44 ; 3 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fIORead~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fIOWrite~0 ; 3 ; -; ula:ula_|i2s_intf:i2s_intf_|LessThan0~0 ; 3 ; -; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~0 ; 3 ; -; ula:ula_|video:video_|VGA_B[0]~1 ; 3 ; -; ula:ula_|video:video_|VGA_G[0]~0 ; 3 ; -; ula:ula_|video:video_|VGA_B[1]~0 ; 3 ; -; ula:ula_|video:video_|VGA_R[0]~0 ; 3 ; -; ula:ula_|video:video_|cindex[2]~0 ; 3 ; -; ula:ula_|video:video_|disp_enable~1 ; 3 ; -; ula:ula_|video:video_|Equal2~0 ; 3 ; -; ula:ula_|video:video_|LessThan6~0 ; 3 ; -; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 ; 3 ; -; sdram_controller:sdram_|r.address[11]~5 ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[7] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[3] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] ; 3 ; -; sdram_controller:sdram_|r.address[10]~_Duplicate_1 ; 3 ; -; sdram_controller:sdram_|r.address[5]~_Duplicate_1 ; 3 ; -; sdram_controller:sdram_|r.address[4]~_Duplicate_1 ; 3 ; -; CLOCK_50~input ; 2 ; -; SW[2]~input ; 2 ; -; SW[1]~input ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~36 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~51 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~97 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~96 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~53 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~52 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~12 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~46 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~19 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~2 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~127 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 ; 2 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~22 ; 2 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~50 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~49 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla9M1T5_2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~35 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla12M3T1_2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~19 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~20 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 2 ; -; sdram_controller:sdram_|Mux10~11 ; 2 ; -; sdram_controller:sdram_|r.bank[0]~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~56 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~38 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla6M1T4_4 ; 2 ; -; D[6]~127 ; 2 ; -; D[4]~125 ; 2 ; -; D[3]~122 ; 2 ; -; D[0]~120 ; 2 ; -; D[2]~119 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~45 ; 2 ; -; D[1]~118 ; 2 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg~15 ; 2 ; -; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 2 ; -; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|Mux35~0 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Pause~1 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Pause~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|Equal0~1 ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[1] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[2] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[3] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[4] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[5] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[6] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|sda_out~4 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|sda_out~1 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|scl_out~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_parity_out ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~24 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf2 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~0 ; 2 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~9 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~12 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~39 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~6 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~37 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~35 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~33 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~31 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~23 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~27 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~22 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~25 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 ; 2 ; -; sdram_controller:sdram_|Equal0~2 ; 2 ; -; sdram_controller:sdram_|Mux39~1 ; 2 ; -; sdram_controller:sdram_|Mux9~9 ; 2 ; -; sdram_controller:sdram_|Mux9~8 ; 2 ; -; sdram_controller:sdram_|Mux13~7 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|sel[1]~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~7 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[1] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|alu_core_cf_in~0 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_hf ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_nf_we~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~16 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[2] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~29 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~12 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[3] ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux|out~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[1] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[2] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~2 ; 2 ; -+---------------------------------------------------------------------------------------------------------------------------------+---------+ ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++--------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++--------------------------------------------------------------------------------------------------------------------------------+---------+ +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~18 ; 73 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~21 ; 72 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 72 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~19 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~17 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~16 ; 69 ; +; sdram_controller:sdram_|r.state[4] ; 68 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[4]~30 ; 66 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~29 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~28 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~27 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]~26 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]~25 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]~31 ; 64 ; +; sdram_controller:sdram_|r.state[6] ; 64 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 64 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~24 ; 64 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 63 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 63 ; +; sdram_controller:sdram_|r.state[8] ; 60 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 60 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ; +; sdram_controller:sdram_|r.state[7] ; 53 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 53 ; +; z80_top_direct_n:z80_|nM1_int~2 ; 51 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 ; 48 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~3 ; 46 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 44 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 44 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 42 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 42 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~7 ; 41 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 41 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 39 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 39 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 38 ; +; ula:ula_|zx_keyboard:zx_keyboard_|released ; 38 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 38 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~2 ; 37 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 37 ; +; ula:ula_|i2s_intf:i2s_intf_|Equal0~2 ; 37 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 36 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 35 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 35 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 35 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~4 ; 35 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 34 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~8 ; 34 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 33 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 33 ; +; sdram_controller:sdram_|r.state[5] ; 32 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 31 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 31 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~8 ; 30 ; +; sdram_controller:sdram_|r.rd_pending ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~34 ; 28 ; +; sdram_controller:sdram_|r.wr_pending ; 27 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 27 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 27 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 27 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 27 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 26 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~22 ; 26 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 25 ; +; ~GND ; 24 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~33 ; 24 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 24 ; +; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq ; 24 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 24 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 24 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 24 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Data ; 24 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 23 ; +; sdram_controller:sdram_|Equal7~2 ; 23 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~1 ; 23 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~3 ; 22 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 22 ; +; debouncer:debounce_autofire|always0~2 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~36 ; 21 ; +; debouncer:debounce_turbo|always0~2 ; 21 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~16 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~18 ; 21 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 21 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] ; 21 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Start ; 20 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~40 ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 20 ; +; Equal5~1 ; 20 ; +; Equal5~0 ; 20 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~23 ; 20 ; +; kempston_autofire_enabled ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 19 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 19 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~19 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~6 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_we~8 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~33 ; 18 ; +; sdram_controller:sdram_|r.rf_pending ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~16 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 18 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 18 ; +; ula:ula_|i2c_loader:i2c_loader_|WideAnd0 ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~45 ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 17 ; +; ula:ula_|video:video_|vram_address[10] ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~15 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 17 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]~1 ; 17 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~10 ; 16 ; +; sdram_controller:sdram_|Mux84~1 ; 16 ; +; ula:ula_|video:video_|vram_address[12] ; 16 ; +; ula:ula_|video:video_|vram_address[11] ; 16 ; +; ula:ula_|video:video_|vram_address[9] ; 16 ; +; ula:ula_|video:video_|vram_address[8] ; 16 ; +; ula:ula_|video:video_|vram_address[7] ; 16 ; +; ula:ula_|video:video_|vram_address[6] ; 16 ; +; ula:ula_|video:video_|vram_address[5] ; 16 ; +; ula:ula_|video:video_|vram_address[4] ; 16 ; +; ula:ula_|video:video_|vram_address[3] ; 16 ; +; ula:ula_|video:video_|vram_address[2] ; 16 ; +; ula:ula_|video:video_|vram_address[1] ; 16 ; +; ula:ula_|video:video_|vram_address[0] ; 16 ; +; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; +; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~55 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 16 ; +; ula:ula_|video:video_|Decoder0~0 ; 16 ; +; ula:ula_|video:video_|Equal3~1 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 15 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_exx ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~2 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 15 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 15 ; +; ula:ula_|video:video_|Equal1~0 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~18 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~92 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~82 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]~73 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]~63 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]~53 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]~43 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[1]~33 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~23 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~84 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~75 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~66 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~57 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~48 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~39 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~30 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~21 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 14 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 14 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~4 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~3 ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 14 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|in_halt ; 14 ; +; ula:ula_|video:video_|vga_hc[2] ; 14 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~14 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 13 ; +; ula:ula_|video:video_|vga_hc[1] ; 13 ; +; D[0]~49 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~18 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~14 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~9 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~2 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~2 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~1 ; 12 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~4 ; 11 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~16 ; 11 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~15 ; 11 ; +; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 11 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 11 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] ; 11 ; +; sdram_controller:sdram_|r.rf_counter[8]~32 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 10 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~20 ; 10 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~18 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~2 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~2 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~8 ; 10 ; +; sdram_controller:sdram_|process_0~4 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~4 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~12 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 10 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 10 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 10 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_34 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_30 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_50 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_46 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_48 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Idle ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Ack ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_zero ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~8 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_lq ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~15 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~5 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~8 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_38~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~8 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~2 ; 9 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_76~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_80 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~15 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_64~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_36~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_40~0 ; 9 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~1 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_oe~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~45 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~13 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~29 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_72 ; 9 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sw_4d_hi~0 ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_60 ; 9 ; +; D[4]~39 ; 9 ; +; D[3]~38 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~1 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~11 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~6 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~8 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~0 ; 9 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 9 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; +; ula:ula_|video:video_|vga_hc[3] ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] ; 9 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~9 ; 8 ; +; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~9 ; 8 ; +; ula:ula_|video:video_|vram_address~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~22 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~11 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~3 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~20 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~32 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_oe~2 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus ; 8 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 ; 8 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~1 ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~5 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~17 ; 8 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~13 ; 8 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~3 ; 8 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 8 ; +; ula:ula_|video:video_|Decoder0~2 ; 8 ; +; ula:ula_|video:video_|Decoder0~1 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~13 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~5 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal37~0 ; 8 ; +; D[0]~14 ; 8 ; +; D[2]~13 ; 8 ; +; D[1]~12 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~0 ; 8 ; +; ula:ula_|video:video_|vga_hc[0] ; 8 ; +; ula:ula_|video:video_|vga_hc[6] ; 8 ; +; ula:ula_|video:video_|vga_vc[5] ; 8 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~9 ; 7 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_44 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal38~2 ; 7 ; +; ula:ula_|always0~3 ; 7 ; +; ula:ula_|i2c_loader:i2c_loader_|nbyte[0] ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~7 ; 7 ; +; D[7]~48 ; 7 ; +; D[6]~47 ; 7 ; +; D[5]~40 ; 7 ; +; ExtRamWE~0 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~32 ; 7 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~3 ; 7 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~21 ; 7 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~23 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~29 ; 7 ; +; sdram_controller:sdram_|r.address[3]~11 ; 7 ; +; sdram_controller:sdram_|Mux13~5 ; 7 ; +; sdram_controller:sdram_|n~4 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~10 ; 7 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~3 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 7 ; +; ula:ula_|video:video_|vga_hc[8] ; 7 ; +; ula:ula_|video:video_|vga_hc[7] ; 7 ; +; ula:ula_|video:video_|vga_vc[9] ; 7 ; +; ula:ula_|video:video_|vga_vc[1] ; 7 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] ; 7 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] ; 7 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~9 ; 6 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~16 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~46 ; 6 ; +; Selector14~18 ; 6 ; +; Selector14~17 ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|nbyte[1] ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~20 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[0]~18 ; 6 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[2] ; 6 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~6 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[1]~19 ; 6 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~25 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~5 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~41 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla82M1T1_16 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~3 ; 6 ; +; sdram_controller:sdram_|r.address[3]~20 ; 6 ; +; sdram_controller:sdram_|Mux19~0 ; 6 ; +; sdram_controller:sdram_|r.init_counter[0] ; 6 ; +; sdram_controller:sdram_|r.address[3]~6 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 6 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_39 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|fMWrite~2 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 6 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 6 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 6 ; +; ula:ula_|i2s_intf:i2s_intf_|Equal1~1 ; 6 ; +; ula:ula_|i2s_intf:i2s_intf_|LessThan0~1 ; 6 ; +; ula:ula_|video:video_|screen_en~1 ; 6 ; +; ula:ula_|video:video_|vga_hc[9] ; 6 ; +; ula:ula_|video:video_|vga_vc[8] ; 6 ; +; ula:ula_|video:video_|vga_vc[7] ; 6 ; +; ula:ula_|video:video_|vga_vc[4] ; 6 ; +; ula:ula_|video:video_|vga_vc[6] ; 6 ; +; ula:ula_|video:video_|vga_vc[3] ; 6 ; +; ula:ula_|video:video_|vga_vc[2] ; 6 ; +; ula:ula_|video:video_|vga_vc[0] ; 6 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 6 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla89M1T2_3 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 5 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[0] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[5]~24 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[6]~22 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|cy_out~0 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[1]~16 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_low ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[3]~14 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[2]~12 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[4]~10 ; 5 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~31 ; 5 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~26 ; 5 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 5 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 5 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|rsel3 ; 5 ; +; sdram_controller:sdram_|r.act_row[2]~1 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[0]~25 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[2]~13 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla66npla53M1T1_15 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[1] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~15 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~23 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~11 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal48~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~16 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~8 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_ir~1 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~2 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~9 ; 5 ; +; sdram_controller:sdram_|Equal5~1 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~16 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~8 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~19 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~7 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal29~0 ; 5 ; +; Selector14~8 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~9 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal46~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~0 ; 5 ; +; Selector12~4 ; 5 ; +; Equal3~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~6 ; 5 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nIORQ_out~0 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 5 ; +; ula:ula_|video:video_|vga_hc[5] ; 5 ; +; ula:ula_|video:video_|vga_hc[4] ; 5 ; +; sdram_controller:sdram_|r.init_counter[7] ; 5 ; +; sdram_controller:sdram_|r.init_counter[1] ; 5 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[3] ; 5 ; +; CLOCK_50~input ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~3 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_iy~2 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~6 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~5 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal71~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf2_we ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla42M3T3_6 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal5~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 4 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Pause ; 4 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[1] ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71~2 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69~2 ; 4 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Stop ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena ; 4 ; +; ula:ula_|video:video_|vram_address[9]~1 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~35 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~28 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~25 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~22 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~18 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~15 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~12 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af2~0 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~23 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~13 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~5 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 4 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_cf ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~29 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 4 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~3 ; 4 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[1]~17 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~8 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~1 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~2 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]~24 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[6]~21 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[4]~18 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[3]~15 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[5]~12 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]~9 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]~6 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~12 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_ff_oe~1 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~25 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~22 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~34 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~30 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~19 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~16 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[12] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[13] ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~23 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~13 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~10 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|carry_borrow_out~0 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[10] ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~17 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~18 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~4 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[8] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[6] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~28 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~23 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~20 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[3] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[5] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~1 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~30 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~19 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~17 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 4 ; +; sdram_controller:sdram_|Mux23~0 ; 4 ; +; sdram_controller:sdram_|n~2 ; 4 ; +; sdram_controller:sdram_|process_0~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~48 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~39 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~16 ; 4 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~2 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~9 ; 4 ; +; ula:ula_|i2s_intf:i2s_intf_|Equal1~0 ; 4 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_16 ; 4 ; +; ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 ; 4 ; +; ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] ; 4 ; +; sdram_controller:sdram_|r.address[0]~_Duplicate_1 ; 4 ; +; PS2_DAT~input ; 3 ; +; raw_loader_in~input ; 3 ; +; I2C_SDAT~input ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_use_cf2~13 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla26M1T4_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_zero_oe~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_im_we ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~16 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~78 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~11 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~28 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla57M1T4_4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~77 ; 3 ; +; sdram_controller:sdram_|n~6 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~58 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~32 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~27 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|state~24 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[2] ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg~6 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|divider[0] ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|scl_out~0 ; 3 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_instIFF2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 3 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~2 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~35 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~15 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|rsel0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~22 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; +; sdram_controller:sdram_|Mux8~1 ; 3 ; +; sdram_controller:sdram_|Mux4~1 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_pf ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~2 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|cy_out~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op2_high[0] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~30 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~1 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_sf ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_nop3pla68M3T1_20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~26 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~9 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op2_low[0] ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~24 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~12 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~76 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~49 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~45 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~14 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~12 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~10 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~8 ; 3 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~7 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~41 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~2 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~22 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~35 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~23 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|carry_borrow_out~0 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~44 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~25 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~11 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~18 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~34 ; 3 ; +; debouncer:debounce_autofire|r_State ; 3 ; +; sdram_controller:sdram_|Mux13~6 ; 3 ; +; sdram_controller:sdram_|Mux23~1 ; 3 ; +; sdram_controller:sdram_|Equal2~3 ; 3 ; +; sdram_controller:sdram_|r.act_row[4] ; 3 ; +; sdram_controller:sdram_|Equal7~1 ; 3 ; +; sdram_controller:sdram_|Equal7~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~51 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~7 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~43 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal4~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~32 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|comb~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~3 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~2 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~2 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal79~0 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc~1 ; 3 ; +; D[7]~37 ; 3 ; +; D[5]~27 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~7 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~15 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~14 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~29 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIORead~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fIOWrite~0 ; 3 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~0 ; 3 ; +; kempston_auto_fire_counter[0] ; 3 ; +; debouncer:debounce_turbo|r_State ; 3 ; +; ula:ula_|video:video_|VGA_B[0]~1 ; 3 ; +; ula:ula_|video:video_|VGA_G[0]~0 ; 3 ; +; ula:ula_|video:video_|VGA_B[1]~0 ; 3 ; +; ula:ula_|video:video_|VGA_R[0]~0 ; 3 ; +; ula:ula_|video:video_|cindex[1]~0 ; 3 ; +; ula:ula_|video:video_|disp_enable~1 ; 3 ; +; ula:ula_|video:video_|Equal2~0 ; 3 ; +; ula:ula_|video:video_|LessThan6~0 ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 ; 3 ; +; turbo ; 3 ; +; debouncer:debounce_autofire|r_Count[10] ; 3 ; +; debouncer:debounce_autofire|r_Count[9] ; 3 ; +; debouncer:debounce_autofire|r_Count[8] ; 3 ; +; debouncer:debounce_autofire|r_Count[20] ; 3 ; +; debouncer:debounce_autofire|r_Count[7] ; 3 ; +; debouncer:debounce_autofire|r_Count[6] ; 3 ; +; debouncer:debounce_autofire|r_Count[5] ; 3 ; +; debouncer:debounce_autofire|r_Count[11] ; 3 ; +; debouncer:debounce_autofire|r_Count[13] ; 3 ; +; debouncer:debounce_autofire|r_Count[12] ; 3 ; +; debouncer:debounce_autofire|r_Count[15] ; 3 ; +; debouncer:debounce_autofire|r_Count[14] ; 3 ; +; debouncer:debounce_turbo|r_Count[10] ; 3 ; +; debouncer:debounce_turbo|r_Count[9] ; 3 ; +; debouncer:debounce_turbo|r_Count[8] ; 3 ; +; debouncer:debounce_turbo|r_Count[20] ; 3 ; +; debouncer:debounce_turbo|r_Count[7] ; 3 ; +; debouncer:debounce_turbo|r_Count[6] ; 3 ; +; debouncer:debounce_turbo|r_Count[5] ; 3 ; +; debouncer:debounce_turbo|r_Count[11] ; 3 ; +; debouncer:debounce_turbo|r_Count[13] ; 3 ; +; debouncer:debounce_turbo|r_Count[12] ; 3 ; +; debouncer:debounce_turbo|r_Count[15] ; 3 ; +; debouncer:debounce_turbo|r_Count[14] ; 3 ; +; sdram_controller:sdram_|r.address[11]~5 ; 3 ; +; sdram_controller:sdram_|r.init_counter[6] ; 3 ; +; sdram_controller:sdram_|r.init_counter[2] ; 3 ; +; sdram_controller:sdram_|r.init_counter[3] ; 3 ; +; sdram_controller:sdram_|r.init_counter[14] ; 3 ; +; sdram_controller:sdram_|r.init_counter[13] ; 3 ; +; sdram_controller:sdram_|r.init_counter[12] ; 3 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 ; 3 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[7] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[4] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[2] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[1] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] ; 3 ; +; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 3 ; +; sdram_controller:sdram_|r.address[10]~_Duplicate_1 ; 3 ; +; sdram_controller:sdram_|r.address[5]~_Duplicate_1 ; 3 ; +; sdram_controller:sdram_|r.address[4]~_Duplicate_1 ; 3 ; +; kempston_auto_fire ; 3 ; +; kempston_autofire_button~input ; 2 ; +; turbo_button~input ; 2 ; +; kempston[4]~input ; 2 ; +; kempston[3]~input ; 2 ; +; kempston[2]~input ; 2 ; +; kempston[1]~input ; 2 ; +; kempston[0]~input ; 2 ; +; SW[1]~input ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~28 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~38 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~38 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~79 ; 2 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ; 2 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~50 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~23 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~2 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~8 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~128 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 ; 2 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re~2 ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d0_out ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~46 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~22 ; 2 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|test1~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~21 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~36 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla9M1T5_2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~23 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla12M3T1_2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~34 ; 2 ; +; sdram_controller:sdram_|Mux20~10 ; 2 ; +; Selector8~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~35 ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg~14 ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 2 ; +; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|Mux35~0 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Pause~1 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Pause~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|Equal0~1 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[1] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[2] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[3] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[4] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[5] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[6] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[7] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|sda_out~4 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|sda_out~1 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|scl_out~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_parity_out ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~8 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~19 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~11 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~35 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~34 ; 2 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~25 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~14 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~39 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~37 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~6 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~31 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~29 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~27 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~5 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~26 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~6 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~14 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~16 ; 2 ; +; debouncer:debounce_autofire|always0~0 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 ; 2 ; +; sdram_controller:sdram_|Equal0~2 ; 2 ; +; sdram_controller:sdram_|Mux39~1 ; 2 ; +; sdram_controller:sdram_|Mux9~5 ; 2 ; +; sdram_controller:sdram_|Mux9~4 ; 2 ; +; sdram_controller:sdram_|Mux13~7 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|sel[1]~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~7 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|alu_core_cf_in~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~16 ; 2 ; ++--------------------------------------------------------------------------------------------------------------------------------+---------+ +--------------------------------------------------------------------------------+ @@ -13105,7 +13328,7 @@ Implementation Port B Width : 8 Implementation Bits : 131072 M9Ks : 16 MIF : ula/test_scr.hex -Location : M9K_X33_Y28_N0, M9K_X22_Y28_N0, M9K_X22_Y27_N0, M9K_X22_Y23_N0, M9K_X33_Y29_N0, M9K_X22_Y29_N0, M9K_X33_Y23_N0, M9K_X33_Y26_N0, M9K_X22_Y22_N0, M9K_X22_Y21_N0, M9K_X33_Y24_N0, M9K_X22_Y24_N0, M9K_X22_Y26_N0, M9K_X22_Y25_N0, M9K_X33_Y25_N0, M9K_X33_Y21_N0 +Location : M9K_X33_Y25_N0, M9K_X22_Y23_N0, M9K_X22_Y27_N0, M9K_X22_Y30_N0, M9K_X22_Y25_N0, M9K_X22_Y24_N0, M9K_X22_Y28_N0, M9K_X33_Y28_N0, M9K_X33_Y27_N0, M9K_X33_Y30_N0, M9K_X33_Y23_N0, M9K_X33_Y26_N0, M9K_X22_Y29_N0, M9K_X22_Y26_N0, M9K_X33_Y29_N0, M9K_X33_Y24_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -13131,7 +13354,7 @@ Implementation Port B Width : -- Implementation Bits : 262144 M9Ks : 32 MIF : led_patterns.mif -Location : M9K_X33_Y15_N0, M9K_X33_Y7_N0, M9K_X22_Y7_N0, M9K_X22_Y11_N0, M9K_X33_Y19_N0, M9K_X33_Y8_N0, M9K_X22_Y5_N0, M9K_X22_Y3_N0, M9K_X22_Y14_N0, M9K_X33_Y9_N0, M9K_X22_Y9_N0, M9K_X22_Y12_N0, M9K_X22_Y13_N0, M9K_X33_Y14_N0, M9K_X33_Y13_N0, M9K_X22_Y15_N0, M9K_X22_Y18_N0, M9K_X22_Y16_N0, M9K_X22_Y10_N0, M9K_X22_Y20_N0, M9K_X33_Y5_N0, M9K_X33_Y10_N0, M9K_X33_Y18_N0, M9K_X22_Y2_N0, M9K_X22_Y8_N0, M9K_X22_Y17_N0, M9K_X22_Y6_N0, M9K_X22_Y19_N0, M9K_X22_Y4_N0, M9K_X33_Y17_N0, M9K_X33_Y16_N0, M9K_X22_Y1_N0 +Location : M9K_X33_Y19_N0, M9K_X22_Y21_N0, M9K_X33_Y13_N0, M9K_X22_Y19_N0, M9K_X22_Y9_N0, M9K_X22_Y10_N0, M9K_X33_Y12_N0, M9K_X22_Y8_N0, M9K_X22_Y18_N0, M9K_X22_Y16_N0, M9K_X22_Y20_N0, M9K_X22_Y17_N0, M9K_X33_Y7_N0, M9K_X33_Y9_N0, M9K_X22_Y11_N0, M9K_X22_Y4_N0, M9K_X22_Y22_N0, M9K_X33_Y11_N0, M9K_X22_Y6_N0, M9K_X33_Y20_N0, M9K_X33_Y15_N0, M9K_X33_Y17_N0, M9K_X33_Y18_N0, M9K_X33_Y21_N0, M9K_X22_Y15_N0, M9K_X22_Y12_N0, M9K_X22_Y13_N0, M9K_X22_Y14_N0, M9K_X33_Y10_N0, M9K_X33_Y16_N0, M9K_X22_Y5_N0, M9K_X22_Y2_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -13157,7 +13380,7 @@ Implementation Port B Width : -- Implementation Bits : 131072 M9Ks : 16 MIF : ./rom/gw03.hex -Location : M9K_X22_Y31_N0, M9K_X33_Y2_N0, M9K_X33_Y20_N0, M9K_X33_Y32_N0, M9K_X33_Y4_N0, M9K_X33_Y11_N0, M9K_X22_Y32_N0, M9K_X33_Y12_N0, M9K_X22_Y33_N0, M9K_X33_Y30_N0, M9K_X33_Y33_N0, M9K_X33_Y6_N0, M9K_X22_Y30_N0, M9K_X33_Y22_N0, M9K_X33_Y3_N0, M9K_X33_Y27_N0 +Location : M9K_X33_Y32_N0, M9K_X22_Y32_N0, M9K_X33_Y2_N0, M9K_X33_Y5_N0, M9K_X33_Y14_N0, M9K_X22_Y3_N0, M9K_X33_Y31_N0, M9K_X33_Y4_N0, M9K_X22_Y33_N0, M9K_X33_Y22_N0, M9K_X33_Y6_N0, M9K_X33_Y33_N0, M9K_X22_Y31_N0, M9K_X22_Y7_N0, M9K_X33_Y3_N0, M9K_X33_Y8_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -13167,2062 +13390,6 @@ Fits in MLABs : No - Unknown Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;8;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;16;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;24;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;32;(11000001) (301) (193) (C1) ;(11000001) (301) (193) (C1) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ; -;40;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ; -;48;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000000) (200) (128) (80) ; -;56;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000011) (203) (131) (83) ;(10000011) (203) (131) (83) ; -;64;(11000001) (301) (193) (C1) ;(10000001) (201) (129) (81) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;72;(00000011) (3) (3) (03) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111110) (376) (254) (FE) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;80;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; -;88;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000001) (201) (129) (81) ;(11000011) (303) (195) (C3) ; -;96;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ; -;104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ; -;112;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;120;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;128;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000010) (102) (66) (42) ;(10000111) (207) (135) (87) ;(01111111) (177) (127) (7F) ; -;136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(11101110) (356) (238) (EE) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; -;144;(11110001) (361) (241) (F1) ;(11111111) (377) (255) (FF) ;(11100001) (341) (225) (E1) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000001) (201) (129) (81) ;(11111110) (376) (254) (FE) ;(00001111) (17) (15) (0F) ; -;152;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;160;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011110) (36) (30) (1E) ; -;168;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(10000000) (200) (128) (80) ;(00100100) (44) (36) (24) ;(00001111) (17) (15) (0F) ;(11111100) (374) (252) (FC) ;(00000000) (0) (0) (00) ; -;176;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;192;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111111) (77) (63) (3F) ; -;200;(01111100) (174) (124) (7C) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(11111000) (370) (248) (F8) ; -;208;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01100011) (143) (99) (63) ;(00001100) (14) (12) (0C) ;(00110001) (61) (49) (31) ;(10101110) (256) (174) (AE) ;(11000011) (303) (195) (C3) ;(11001111) (317) (207) (CF) ; -;216;(01100011) (143) (99) (63) ;(10011111) (237) (159) (9F) ;(11111111) (377) (255) (FF) ;(00001111) (17) (15) (0F) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;224;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ; -;232;(11111111) (377) (255) (FF) ;(11111000) (370) (248) (F8) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000001) (1) (1) (01) ;(11111111) (377) (255) (FF) ; -;240;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ;(11111110) (376) (254) (FE) ;(01100100) (144) (100) (64) ;(01111001) (171) (121) (79) ;(00011100) (34) (28) (1C) ;(10000111) (207) (135) (87) ; -;248;(00011001) (31) (25) (19) ;(10011000) (230) (152) (98) ;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;256;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;264;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;272;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;280;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;288;(11000011) (303) (195) (C3) ;(10000110) (206) (134) (86) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ; -;296;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ; -;304;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ;(01100000) (140) (96) (60) ; -;312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ;(01100001) (141) (97) (61) ;(11000011) (303) (195) (C3) ; -;320;(11000111) (307) (199) (C7) ;(01100011) (143) (99) (63) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ; -;328;(00011111) (37) (31) (1F) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111000) (370) (248) (F8) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;336;(11111000) (370) (248) (F8) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111000) (370) (248) (F8) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(00000000) (0) (0) (00) ; -;344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(11000110) (306) (198) (C6) ;(11100011) (343) (227) (E3) ; -;352;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00000100) (4) (4) (04) ;(10100000) (240) (160) (A0) ; -;360;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111111) (177) (127) (7F) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11110111) (367) (247) (F7) ; -;368;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11110000) (360) (240) (F0) ;(01111000) (170) (120) (78) ;(00000000) (0) (0) (00) ; -;376;(10111111) (277) (191) (BF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;384;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(01010001) (121) (81) (51) ;(00000001) (1) (1) (01) ;(11111110) (376) (254) (FE) ; -;392;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(11111100) (374) (252) (FC) ;(01011110) (136) (94) (5E) ;(00000000) (0) (0) (00) ;(01111111) (177) (127) (7F) ;(11111000) (370) (248) (F8) ;(00000000) (0) (0) (00) ; -;400;(11111100) (374) (252) (FC) ;(00111111) (77) (63) (3F) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(01111000) (170) (120) (78) ;(00000111) (7) (7) (07) ; -;408;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; -;416;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011110) (36) (30) (1E) ; -;424;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00000111) (7) (7) (07) ;(11111110) (376) (254) (FE) ;(00000000) (0) (0) (00) ; -;432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;440;(00000000) (0) (0) (00) ;(00001111) (17) (15) (0F) ;(00000000) (0) (0) (00) ;(01111111) (177) (127) (7F) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; 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-;16368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; - - RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM ; @@ -17279,6 +15446,2062 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci ;16376;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(10011001) (231) (153) (99) ;(10100001) (241) (161) (A1) ;(10100001) (241) (161) (A1) ;(10011001) (231) (153) (99) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ; +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; 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+;16288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; + + RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM ; @@ -21388,164 +21611,171 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci +-----------------------+------------------------+ ; Routing Resource Type ; Usage ; +-----------------------+------------------------+ -; Block interconnects ; 5,364 / 71,559 ( 7 % ) ; -; C16 interconnects ; 115 / 2,597 ( 4 % ) ; -; C4 interconnects ; 2,916 / 46,848 ( 6 % ) ; -; Direct links ; 467 / 71,559 ( < 1 % ) ; +; Block interconnects ; 5,515 / 71,559 ( 8 % ) ; +; C16 interconnects ; 141 / 2,597 ( 5 % ) ; +; C4 interconnects ; 3,156 / 46,848 ( 7 % ) ; +; Direct links ; 445 / 71,559 ( < 1 % ) ; ; Global clocks ; 10 / 20 ( 50 % ) ; -; Local interconnects ; 1,335 / 24,624 ( 5 % ) ; -; R24 interconnects ; 123 / 2,496 ( 5 % ) ; -; R4 interconnects ; 3,116 / 62,424 ( 5 % ) ; +; Local interconnects ; 1,448 / 24,624 ( 6 % ) ; +; R24 interconnects ; 158 / 2,496 ( 6 % ) ; +; R4 interconnects ; 3,388 / 62,424 ( 5 % ) ; +-----------------------+------------------------+ +-----------------------------------------------------------------------------+ ; LAB Logic Elements ; +---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 12.79) ; Number of LABs (Total = 204) ; +; Number of Logic Elements (Average = 12.70) ; Number of LABs (Total = 216) ; +---------------------------------------------+-------------------------------+ -; 1 ; 16 ; -; 2 ; 7 ; -; 3 ; 3 ; -; 4 ; 3 ; -; 5 ; 4 ; -; 6 ; 2 ; +; 1 ; 23 ; +; 2 ; 3 ; +; 3 ; 4 ; +; 4 ; 5 ; +; 5 ; 0 ; +; 6 ; 5 ; ; 7 ; 1 ; -; 8 ; 4 ; -; 9 ; 3 ; -; 10 ; 1 ; +; 8 ; 2 ; +; 9 ; 2 ; +; 10 ; 0 ; ; 11 ; 2 ; -; 12 ; 8 ; -; 13 ; 11 ; -; 14 ; 7 ; -; 15 ; 21 ; -; 16 ; 111 ; +; 12 ; 5 ; +; 13 ; 9 ; +; 14 ; 18 ; +; 15 ; 32 ; +; 16 ; 105 ; +---------------------------------------------+-------------------------------+ +--------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 1.16) ; Number of LABs (Total = 204) ; +; LAB-wide Signals (Average = 1.14) ; Number of LABs (Total = 216) ; +------------------------------------+-------------------------------+ -; 1 Async. clear ; 50 ; -; 1 Clock ; 111 ; -; 1 Clock enable ; 43 ; -; 1 Sync. clear ; 1 ; -; 1 Sync. load ; 8 ; -; 2 Async. clears ; 2 ; -; 2 Clock enables ; 19 ; -; 2 Clocks ; 2 ; +; 1 Async. clear ; 47 ; +; 1 Clock ; 119 ; +; 1 Clock enable ; 36 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 7 ; +; 2 Async. clears ; 3 ; +; 2 Clock enables ; 27 ; +; 2 Clocks ; 4 ; +------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 15.63) ; Number of LABs (Total = 204) ; +; Number of Signals Sourced (Average = 15.68) ; Number of LABs (Total = 216) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 11 ; -; 2 ; 7 ; -; 3 ; 5 ; -; 4 ; 3 ; -; 5 ; 2 ; +; 1 ; 14 ; +; 2 ; 10 ; +; 3 ; 2 ; +; 4 ; 5 ; +; 5 ; 3 ; ; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 5 ; -; 9 ; 2 ; -; 10 ; 3 ; -; 11 ; 3 ; -; 12 ; 3 ; -; 13 ; 3 ; -; 14 ; 9 ; -; 15 ; 15 ; -; 16 ; 53 ; -; 17 ; 10 ; -; 18 ; 10 ; -; 19 ; 6 ; -; 20 ; 12 ; -; 21 ; 7 ; -; 22 ; 3 ; -; 23 ; 1 ; -; 24 ; 7 ; -; 25 ; 2 ; -; 26 ; 4 ; -; 27 ; 6 ; -; 28 ; 4 ; +; 8 ; 1 ; +; 9 ; 4 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 4 ; +; 13 ; 6 ; +; 14 ; 10 ; +; 15 ; 21 ; +; 16 ; 49 ; +; 17 ; 8 ; +; 18 ; 9 ; +; 19 ; 7 ; +; 20 ; 8 ; +; 21 ; 10 ; +; 22 ; 7 ; +; 23 ; 6 ; +; 24 ; 3 ; +; 25 ; 7 ; +; 26 ; 8 ; +; 27 ; 4 ; +; 28 ; 3 ; ; 29 ; 2 ; ; 30 ; 1 ; ; 31 ; 1 ; -; 32 ; 2 ; +; 32 ; 1 ; +----------------------------------------------+-------------------------------+ +---------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 8.04) ; Number of LABs (Total = 204) ; +; Number of Signals Sourced Out (Average = 7.87) ; Number of LABs (Total = 216) ; +-------------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 22 ; +; 1 ; 31 ; ; 2 ; 10 ; -; 3 ; 7 ; -; 4 ; 8 ; -; 5 ; 11 ; -; 6 ; 13 ; -; 7 ; 14 ; -; 8 ; 23 ; -; 9 ; 18 ; -; 10 ; 21 ; -; 11 ; 16 ; -; 12 ; 8 ; -; 13 ; 7 ; -; 14 ; 10 ; -; 15 ; 5 ; -; 16 ; 8 ; -; 17 ; 2 ; -; 18 ; 1 ; +; 3 ; 6 ; +; 4 ; 7 ; +; 5 ; 13 ; +; 6 ; 17 ; +; 7 ; 12 ; +; 8 ; 20 ; +; 9 ; 13 ; +; 10 ; 26 ; +; 11 ; 8 ; +; 12 ; 18 ; +; 13 ; 12 ; +; 14 ; 8 ; +; 15 ; 9 ; +; 16 ; 4 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 1 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 1 ; +-------------------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 18.75) ; Number of LABs (Total = 204) ; +; Number of Distinct Inputs (Average = 18.51) ; Number of LABs (Total = 216) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 5 ; -; 3 ; 9 ; -; 4 ; 10 ; -; 5 ; 3 ; +; 1 ; 2 ; +; 2 ; 9 ; +; 3 ; 7 ; +; 4 ; 8 ; +; 5 ; 6 ; ; 6 ; 3 ; ; 7 ; 3 ; -; 8 ; 4 ; +; 8 ; 7 ; ; 9 ; 5 ; -; 10 ; 4 ; -; 11 ; 8 ; -; 12 ; 7 ; -; 13 ; 11 ; -; 14 ; 5 ; -; 15 ; 6 ; -; 16 ; 4 ; -; 17 ; 6 ; -; 18 ; 8 ; -; 19 ; 4 ; -; 20 ; 8 ; -; 21 ; 2 ; -; 22 ; 6 ; +; 10 ; 7 ; +; 11 ; 6 ; +; 12 ; 9 ; +; 13 ; 7 ; +; 14 ; 2 ; +; 15 ; 8 ; +; 16 ; 6 ; +; 17 ; 4 ; +; 18 ; 3 ; +; 19 ; 6 ; +; 20 ; 6 ; +; 21 ; 4 ; +; 22 ; 4 ; ; 23 ; 4 ; -; 24 ; 4 ; -; 25 ; 7 ; -; 26 ; 2 ; +; 24 ; 9 ; +; 25 ; 10 ; +; 26 ; 5 ; ; 27 ; 6 ; -; 28 ; 7 ; +; 28 ; 13 ; ; 29 ; 8 ; -; 30 ; 12 ; -; 31 ; 11 ; -; 32 ; 19 ; -; 33 ; 2 ; +; 30 ; 5 ; +; 31 ; 14 ; +; 32 ; 12 ; +; 33 ; 4 ; +; 34 ; 3 ; +----------------------------------------------+-------------------------------+ @@ -21555,10 +21785,10 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci ; I/O Rules Statistic ; Total ; +----------------------------------+-------+ ; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 11 ; +; Number of I/O Rules Passed ; 13 ; ; Number of I/O Rules Failed ; 0 ; ; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 19 ; +; Number of I/O Rules Inapplicable ; 17 ; +----------------------------------+-------+ @@ -21682,12 +21912,12 @@ Information : No Enable Bus-Hold Circuitry assignments found. Area : I/O Extra Information : -Status : Inapplicable +Status : Pass ID : IO_000014 Category : I/O Properties Checks for One I/O Rule Description : The location should support the requested Weak Pull Up value. Severity : Critical -Information : No Weak Pull-Up Resistor assignments found. +Information : 0 such failures found. Area : I/O Extra Information : @@ -21727,12 +21957,12 @@ Information : 0 such failures found. Area : I/O Extra Information : -Status : Inapplicable +Status : Pass ID : IO_000021 Category : I/O Properties Checks for One I/O Rule Description : The I/O standard should support the requested Weak Pull Up value. Severity : Critical -Information : No Weak Pull-Up Resistor assignments found. +Information : 0 such failures found. Area : I/O Extra Information : @@ -21777,7 +22007,7 @@ ID : IO_000027 Category : I/O Properties Checks for One I/O Rule Description : Weak Pull Up and Bus Hold should not be used at the same time. Severity : Critical -Information : No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. +Information : No Enable Bus-Hold Circuitry assignments found. Area : I/O Extra Information : @@ -21842,25 +22072,25 @@ Extra Information : ; I/O Rules Matrix ; +--------------------------------------------------------------------------------+ Pin/Rules : Total Pass -IO_000001 : 114 +IO_000001 : 120 IO_000002 : 29 -IO_000003 : 114 +IO_000003 : 120 IO_000004 : 0 IO_000005 : 0 -IO_000006 : 114 -IO_000007 : 114 +IO_000006 : 120 +IO_000007 : 120 IO_000008 : 0 -IO_000009 : 114 -IO_000010 : 114 +IO_000009 : 120 +IO_000010 : 120 IO_000011 : 0 IO_000012 : 0 IO_000013 : 0 -IO_000014 : 0 -IO_000015 : 57 +IO_000014 : 7 +IO_000015 : 64 IO_000018 : 0 IO_000019 : 0 -IO_000020 : 57 -IO_000021 : 0 +IO_000020 : 64 +IO_000021 : 7 IO_000022 : 0 IO_000023 : 10 IO_000024 : 0 @@ -21869,7 +22099,7 @@ IO_000027 : 0 IO_000045 : 0 IO_000046 : 0 IO_000047 : 0 -IO_000033 : 114 +IO_000033 : 120 IO_000034 : 0 IO_000042 : 0 @@ -21907,35 +22137,35 @@ IO_000042 : 0 Pin/Rules : Total Inapplicable IO_000001 : 0 -IO_000002 : 85 +IO_000002 : 91 IO_000003 : 0 -IO_000004 : 114 -IO_000005 : 114 +IO_000004 : 120 +IO_000005 : 120 IO_000006 : 0 IO_000007 : 0 -IO_000008 : 114 +IO_000008 : 120 IO_000009 : 0 IO_000010 : 0 -IO_000011 : 114 -IO_000012 : 114 -IO_000013 : 114 -IO_000014 : 114 -IO_000015 : 57 -IO_000018 : 114 -IO_000019 : 114 -IO_000020 : 57 -IO_000021 : 114 -IO_000022 : 114 -IO_000023 : 104 -IO_000024 : 114 -IO_000026 : 114 -IO_000027 : 114 -IO_000045 : 114 -IO_000046 : 114 -IO_000047 : 114 +IO_000011 : 120 +IO_000012 : 120 +IO_000013 : 120 +IO_000014 : 113 +IO_000015 : 56 +IO_000018 : 120 +IO_000019 : 120 +IO_000020 : 56 +IO_000021 : 113 +IO_000022 : 120 +IO_000023 : 110 +IO_000024 : 120 +IO_000026 : 120 +IO_000027 : 120 +IO_000045 : 120 +IO_000046 : 120 +IO_000047 : 120 IO_000033 : 0 -IO_000034 : 114 -IO_000042 : 114 +IO_000034 : 120 +IO_000042 : 120 Pin/Rules : Total Fail IO_000001 : 0 @@ -22865,6 +23095,38 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable +Pin/Rules : SW[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + Pin/Rules : SW[3] IO_000001 : Pass IO_000002 : Inapplicable @@ -23921,70 +24183,6 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable -Pin/Rules : GPIO_1[32] -IO_000001 : Pass -IO_000002 : Inapplicable -IO_000003 : Pass -IO_000004 : Inapplicable -IO_000005 : Inapplicable -IO_000006 : Pass -IO_000007 : Pass -IO_000008 : Inapplicable -IO_000009 : Pass -IO_000010 : Pass -IO_000011 : Inapplicable -IO_000012 : Inapplicable -IO_000013 : Inapplicable -IO_000014 : Inapplicable -IO_000015 : Inapplicable -IO_000018 : Inapplicable -IO_000019 : Inapplicable -IO_000020 : Inapplicable -IO_000021 : Inapplicable -IO_000022 : Inapplicable -IO_000023 : Inapplicable -IO_000024 : Inapplicable -IO_000026 : Inapplicable -IO_000027 : Inapplicable -IO_000045 : Inapplicable -IO_000046 : Inapplicable -IO_000047 : Inapplicable -IO_000033 : Pass -IO_000034 : Inapplicable -IO_000042 : Inapplicable - -Pin/Rules : GPIO_1[33] -IO_000001 : Pass -IO_000002 : Inapplicable -IO_000003 : Pass -IO_000004 : Inapplicable -IO_000005 : Inapplicable -IO_000006 : Pass -IO_000007 : Pass -IO_000008 : Inapplicable -IO_000009 : Pass -IO_000010 : Pass -IO_000011 : Inapplicable -IO_000012 : Inapplicable -IO_000013 : Inapplicable -IO_000014 : Inapplicable -IO_000015 : Inapplicable -IO_000018 : Inapplicable -IO_000019 : Inapplicable -IO_000020 : Inapplicable -IO_000021 : Inapplicable -IO_000022 : Inapplicable -IO_000023 : Inapplicable -IO_000024 : Inapplicable -IO_000026 : Inapplicable -IO_000027 : Inapplicable -IO_000045 : Inapplicable -IO_000046 : Inapplicable -IO_000047 : Inapplicable -IO_000033 : Pass -IO_000034 : Inapplicable -IO_000042 : Inapplicable - Pin/Rules : buzzer_out IO_000001 : Pass IO_000002 : Inapplicable @@ -24753,6 +24951,38 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable +Pin/Rules : kempston_gnd +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + Pin/Rules : I2C_SCLK IO_000001 : Pass IO_000002 : Pass @@ -25361,7 +25591,7 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable -Pin/Rules : SW[2] +Pin/Rules : raw_loader_in IO_000001 : Pass IO_000002 : Inapplicable IO_000003 : Pass @@ -25393,7 +25623,7 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable -Pin/Rules : raw_loader_in +Pin/Rules : kempston[0] IO_000001 : Pass IO_000002 : Inapplicable IO_000003 : Pass @@ -25407,12 +25637,140 @@ IO_000010 : Pass IO_000011 : Inapplicable IO_000012 : Inapplicable IO_000013 : Inapplicable -IO_000014 : Inapplicable +IO_000014 : Pass IO_000015 : Pass IO_000018 : Inapplicable IO_000019 : Inapplicable IO_000020 : Pass -IO_000021 : Inapplicable +IO_000021 : Pass +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : kempston[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Pass +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Pass +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : kempston[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Pass +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Pass +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : kempston[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Pass +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Pass +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : kempston[4] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Pass +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Pass IO_000022 : Inapplicable IO_000023 : Inapplicable IO_000024 : Inapplicable @@ -25489,6 +25847,70 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable +Pin/Rules : turbo_button +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Pass +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Pass +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : kempston_autofire_button +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Pass +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Pass +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + Pin/Rules : PS2_DAT IO_000001 : Pass IO_000002 : Inapplicable @@ -25662,11 +26084,11 @@ IO_000042 : Inapplicable +--------------------------------------------------------------------------------+ Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50 -Delay Added in ns : 662.4 +Delay Added in ns : 611.2 Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50,ula_|pll_|altpll_component|auto_generated|pll1|clk[0],I/O -Delay Added in ns : 29.2 +Delay Added in ns : 38.3 +--------------------------------------------------------------------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. @@ -25676,405 +26098,405 @@ This will disable optimization of problematic paths and expose them for further +--------------------------------------------------------------------------------+ ; Estimated Delay Added for Hold Timing Details ; +--------------------------------------------------------------------------------+ -Source Register : ula:ula_|video:video_|vram_address[9] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.698 - -Source Register : ula:ula_|video:video_|vram_address[12] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.698 - -Source Register : ula:ula_|video:video_|vram_address[8] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.695 - -Source Register : ula:ula_|video:video_|vram_address[11] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.695 - -Source Register : ula:ula_|video:video_|vram_address[10] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.688 - -Source Register : ula:ula_|video:video_|vram_address[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.647 - -Source Register : ula:ula_|video:video_|vram_address[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.646 - -Source Register : ula:ula_|video:video_|vram_address[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.641 - -Source Register : ula:ula_|video:video_|vram_address[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.641 - -Source Register : ula:ula_|video:video_|vram_address[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.638 - Source Register : ula:ula_|video:video_|vram_address[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.638 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Delay Added in ns : 3.461 Source Register : ula:ula_|video:video_|vram_address[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.638 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Delay Added in ns : 3.461 + +Source Register : ula:ula_|video:video_|vram_address[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.416 + +Source Register : ula:ula_|video:video_|vram_address[12] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.416 Source Register : ula:ula_|video:video_|vram_address[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Delay Added in ns : 3.615 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.210 + +Source Register : ula:ula_|video:video_|vram_address[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Delay Added in ns : 3.209 + +Source Register : ula:ula_|video:video_|vram_address[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.207 + +Source Register : ula:ula_|video:video_|vram_address[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.206 + +Source Register : ula:ula_|video:video_|vram_address[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Delay Added in ns : 3.202 + +Source Register : ula:ula_|video:video_|vram_address[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Delay Added in ns : 3.202 + +Source Register : ula:ula_|video:video_|vram_address[8] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Delay Added in ns : 3.147 + +Source Register : ula:ula_|video:video_|vram_address[11] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Delay Added in ns : 3.147 + +Source Register : ula:ula_|video:video_|vram_address[10] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Delay Added in ns : 3.145 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 1.924 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 1.982 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.919 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 1.037 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.918 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.881 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.865 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.761 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -Destination Register : DRAM_DQ[6] -Delay Added in ns : 0.728 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Delay Added in ns : 0.708 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.693 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.686 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.686 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -Destination Register : DRAM_DQ[6] -Delay Added in ns : 0.639 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Delay Added in ns : 0.633 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.605 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Delay Added in ns : 0.603 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.577 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 0.577 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 1.893 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.563 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.530 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.519 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|in_halt -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|M5 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Delay Added in ns : 0.481 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.479 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -Destination Register : DRAM_DQ[6] -Delay Added in ns : 0.457 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.450 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 0.448 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.444 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.444 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.443 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.414 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 1.299 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.400 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 1.132 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.399 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 1.067 -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.380 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.993 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.380 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.960 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.380 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Delay Added in ns : 0.891 -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.380 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Delay Added in ns : 0.852 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.366 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.826 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.366 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.811 -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.366 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.805 -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.354 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.802 -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Delay Added in ns : 0.350 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.750 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.314 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.694 -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Delay Added in ns : 0.314 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Delay Added in ns : 0.647 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.312 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.636 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Delay Added in ns : 0.312 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.628 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : raw_loader_in +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.606 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.595 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[6][0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : kempston[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Delay Added in ns : 0.590 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Delay Added in ns : 0.583 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.505 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.489 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.489 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.489 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.489 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.489 + +Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.457 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.457 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|M5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.457 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.457 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Delay Added in ns : 0.457 +--------------------------------------------------------------------------------+ Note: This table only shows the top 100 path(s) that have the largest delay added for hold. @@ -26157,89 +26579,8 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 513 nodes - Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~33|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~33|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datab" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datac" - Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~33|datad" - Warning (332126): Node "z80_|alu_|db[4]~8|datab" - Warning (332126): Node "z80_|alu_|db[4]~8|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|dataa" - Warning (332126): Node "z80_|alu_|db[4]~10|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datab" - Warning (332126): Node "z80_|alu_|db[4]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~16|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|datab" - Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~17|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~16|datac" - Warning (332126): Node "z80_|alu_control_|db[5]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab" - Warning (332126): Node "z80_|alu_|db[5]~23|datab" - Warning (332126): Node "z80_|alu_|db[5]~23|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|dataa" - Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" - Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa" +Warning (332125): Found combinational loop of 518 nodes + Warning (332126): Node "z80_|bus_control_|db[5]~16|combout" Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" @@ -26251,137 +26592,238 @@ Warning (332125): Found combinational loop of 513 nodes Warning (332126): Node "z80_|alu_|db_high[3]~3|datab" Warning (332126): Node "z80_|alu_|db_high[3]~3|combout" Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~8|combout" Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~10|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datab" Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" Warning (332126): Node "z80_|alu_|db[6]~22|datab" Warning (332126): Node "z80_|alu_|db[6]~22|combout" Warning (332126): Node "z80_|alu_|db_high[3]~2|datab" Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" Warning (332126): Node "z80_|alu_|db_high[3]~3|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~10|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~23|datac" - Warning (332126): Node "z80_|alu_control_|db[6]~23|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" - Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" - Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" - Warning (332126): Node "z80_|sw1_|db_down[6]~1|dataa" - Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~23|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~23|datab" - Warning (332126): Node "z80_|alu_|db[6]~21|dataa" - Warning (332126): Node "z80_|alu_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datab" - Warning (332126): Node "z80_|alu_|db[6]~21|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~16|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|dataa" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~16|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datab" + Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~0|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~0|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~1|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~1|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|combout" + Warning (332126): Node "z80_|alu_|db[3]~14|dataa" + Warning (332126): Node "z80_|alu_|db[3]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~57|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~57|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~58|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~58|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~61|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~61|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~62|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|datab" + Warning (332126): Node "z80_|alu_|db[3]~14|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~20|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~20|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~33|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~33|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~20|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~27|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~27|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datab" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datac" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~3|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~3|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~19|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~19|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~7|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" Warning (332126): Node "z80_|alu_|db[0]~17|datab" Warning (332126): Node "z80_|alu_|db[0]~17|combout" Warning (332126): Node "z80_|alu_|db[0]~18|dataa" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa" - Warning (332126): Node "z80_|alu_control_|db[0]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~14|dataa" - Warning (332126): Node "z80_|alu_control_|db[0]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~23|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~23|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~25|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~25|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~11|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~11|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~12|dataa" + Warning (332126): Node "z80_|bus_control_|db[0]~12|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[0]|dataa" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[0]|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~24|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~24|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~25|datac" + Warning (332126): Node "z80_|alu_|db[0]~17|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~16|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~16|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~11|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~18|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[0]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[0]~4|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~25|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~10|datab" - Warning (332126): Node "z80_|alu_control_|db[0]~10|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~11|datab" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" - Warning (332126): Node "z80_|alu_|db[0]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~18|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~19|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~19|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~20|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~20|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~13|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" Warning (332126): Node "z80_|alu_|db[1]~16|datab" Warning (332126): Node "z80_|alu_|db[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~10|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datab" + Warning (332126): Node "z80_|alu_|db[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~0|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~27|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~14|dataa" + Warning (332126): Node "z80_|bus_control_|db[2]~14|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[2]|dataa" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[2]|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~5|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~27|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout" + Warning (332126): Node "z80_|alu_|db[2]~11|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~13|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" @@ -26393,286 +26835,273 @@ Warning (332125): Found combinational loop of 513 nodes Warning (332126): Node "z80_|alu_|db[1]~15|datab" Warning (332126): Node "z80_|alu_|db[1]~15|combout" Warning (332126): Node "z80_|alu_|db[1]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~2|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~2|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~4|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~10|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|datab" - Warning (332126): Node "z80_|alu_|db[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~18|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datab" - Warning (332126): Node "z80_|alu_|db[2]~11|datab" - Warning (332126): Node "z80_|alu_|db[2]~11|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~4|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~5|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~26|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~26|combout" - Warning (332126): Node "z80_|alu_|db[3]~13|datab" - Warning (332126): Node "z80_|alu_|db[3]~13|combout" - Warning (332126): Node "z80_|alu_|db[3]~14|dataa" - Warning (332126): Node "z80_|alu_|db[3]~14|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~22|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datab" - Warning (332126): Node "z80_|alu_|db[3]~13|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~5|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~36|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~36|combout" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~25|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~25|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~27|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~20|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" - Warning (332126): Node "z80_|sw1_|db_down[3]~3|dataa" - Warning (332126): Node "z80_|sw1_|db_down[3]~3|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~13|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~14|datac" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" - Warning (332126): Node "z80_|alu_|db[3]~14|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~9|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~10|datab" - Warning (332126): Node "z80_|alu_control_|db[2]~28|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~30|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~30|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" - Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" - Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~30|datad" - Warning (332126): Node "z80_|alu_|db[2]~11|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~19|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~27|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~27|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~13|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~21|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~22|dataa" + Warning (332126): Node "z80_|alu_control_|db[1]~22|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~9|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~9|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|dataa" Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" - Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" - Warning (332126): Node "z80_|sw1_|db_down[1]~2|dataa" - Warning (332126): Node "z80_|sw1_|db_down[1]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~27|dataa" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[1]|dataa" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[1]|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~22|datab" Warning (332126): Node "z80_|alu_|db[1]~15|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~3|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~19|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~20|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~37|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~37|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" - Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~3|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~3|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~4|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~7|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~8|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~8|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~9|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~1|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~29|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~29|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~30|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|bus_control_|db[4]~18|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~20|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~14|datac" + Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~65|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~72|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~72|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~16|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~29|datac" + Warning (332126): Node "z80_|alu_|db[4]~8|datab" + Warning (332126): Node "z80_|alu_|db[4]~8|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" + Warning (332126): Node "z80_|alu_|db[4]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~19|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~12|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~12|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~47|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~48|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~51|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~51|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~52|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~52|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[5]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~9|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~9|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~10|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|datab" + Warning (332126): Node "z80_|bus_control_|db[5]~16|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~17|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~18|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~18|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~7|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~7|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[0]|dataa" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[0]|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~18|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~2|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~82|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~83|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~25|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~25|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~14|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~15|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~15|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~4|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~4|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~6|dataa" + Warning (332126): Node "z80_|bus_control_|db[7]~6|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[1]|dataa" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[1]|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~15|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datab" - Warning (332126): Node "z80_|alu_control_|db[7]~19|datab" - Warning (332126): Node "z80_|alu_|db[7]~19|dataa" - Warning (332126): Node "z80_|alu_|db[7]~19|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|datab" - Warning (332126): Node "z80_|alu_|db[7]~19|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~13|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~8|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~22|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|combout" - Warning (332126): Node "z80_|alu_|db[5]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~4|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~14|datac" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" -Critical Warning (332081): Design contains combinational loop of 513 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~9|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~7|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~3|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" +Critical Warning (332081): Design contains combinational loop of 518 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements @@ -26688,6 +27117,9 @@ Info (332111): Found 7 clocks Info (332111): 41.702 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node debouncer:debounce_turbo|r_State + Info (176357): Destination node debouncer:debounce_autofire|r_State Info (176353): Automatically promoted node sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_1) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 Info (176353): Automatically promoted node sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C0 of PLL_1) @@ -26741,12 +27173,6 @@ Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0_IN[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0_IN[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1_IN[0]" is assigned to location or region, but does not exist in design @@ -26769,28 +27195,29 @@ Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 Info (170193): Fitter routing operations beginning -Info (170089): 7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. +Info (170089): 7e+02 ns of routing delay (approximately 1.4% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. Info (170195): Router estimated average interconnect usage is 5% of the available device resources - Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:06 + Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:07 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 1.84 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 2.06 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning (169177): 57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. +Warning (169177): 64 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at M1 + Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at B9 Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at M15 Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at F13 Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at T15 @@ -26839,20 +27266,26 @@ Warning (169177): 57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5- Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at N3 Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at K1 Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at T8 - Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at B9 Info (169178): Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6 + Info (169178): Pin kempston[0] uses I/O standard 3.3-V LVTTL at B4 + Info (169178): Pin kempston[1] uses I/O standard 3.3-V LVTTL at A4 + Info (169178): Pin kempston[2] uses I/O standard 3.3-V LVTTL at B5 + Info (169178): Pin kempston[3] uses I/O standard 3.3-V LVTTL at A5 + Info (169178): Pin kempston[4] uses I/O standard 3.3-V LVTTL at D5 Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at J15 Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 + Info (169178): Pin turbo_button uses I/O standard 3.3-V LVTTL at J13 + Info (169178): Pin kempston_autofire_button uses I/O standard 3.3-V LVTTL at J14 Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7 Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at E1 Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6 Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 574 warnings - Info: Peak virtual memory: 641 megabytes - Info: Processing ended: Sat Apr 2 14:51:08 2022 - Info: Elapsed time: 00:00:22 - Info: Total CPU time (on all processors): 00:00:22 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 575 warnings + Info: Peak virtual memory: 645 megabytes + Info: Processing ended: Wed Apr 6 13:58:16 2022 + Info: Elapsed time: 00:00:24 + Info: Total CPU time (on all processors): 00:00:24 +----------------------------+ diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index 1bed494..3da2c62 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,15 +1,15 @@ -Fitter Status : Successful - Sat Apr 2 14:51:07 2022 +Fitter Status : Successful - Wed Apr 6 13:58:15 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 2,609 / 22,320 ( 12 % ) - Total combinational functions : 2,490 / 22,320 ( 11 % ) - Dedicated logic registers : 635 / 22,320 ( 3 % ) -Total registers : 664 -Total pins : 114 / 154 ( 74 % ) +Total logic elements : 2,743 / 22,320 ( 12 % ) + Total combinational functions : 2,624 / 22,320 ( 12 % ) + Dedicated logic registers : 700 / 22,320 ( 3 % ) +Total registers : 729 +Total pins : 120 / 154 ( 78 % ) Total virtual pins : 0 Total memory bits : 524,288 / 608,256 ( 86 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index d85d42d..6083ccf 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Sat Apr 2 14:51:22 2022 +Wed Apr 6 13:58:30 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,18 +40,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Sat Apr 2 14:51:22 2022 ; +; Flow Status ; Successful - Wed Apr 6 13:58:30 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,609 / 22,320 ( 12 % ) ; -; Total combinational functions ; 2,490 / 22,320 ( 11 % ) ; -; Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; -; Total registers ; 664 ; -; Total pins ; 114 / 154 ( 74 % ) ; +; Total logic elements ; 2,743 / 22,320 ( 12 % ) ; +; Total combinational functions ; 2,624 / 22,320 ( 12 % ) ; +; Dedicated logic registers ; 700 / 22,320 ( 3 % ) ; +; Total registers ; 729 ; +; Total pins ; 120 / 154 ( 78 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/02/2022 14:50:31 ; +; Start date & time ; 04/06/2022 13:57:37 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164890023113286 +Value : 0.164924265739740 Default Value : -- Entity Name : -- Section Id : -- @@ -91,6 +91,18 @@ Default Value : Entity Name : -- Section Id : -- +Assignment Name : ENABLE_LOGIC_ANALYZER_INTERFACE +Value : Off +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : ENABLE_SIGNALTAP +Value : Off +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : IP_TOOL_NAME Value : ROM: 1-PORT Default Value : -- @@ -139,6 +151,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_NAME +Value : ALTPLL +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : IP_TOOL_VERSION Value : 13.1 Default Value : -- @@ -187,6 +205,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : MAX_CORE_JUNCTION_TEMP Value : 85 Default Value : -- @@ -265,6 +289,18 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : MISC_FILE +Value : pll_sdram_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : pll_sdram.ppf +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Value : 1.2V Default Value : -- @@ -289,11 +325,29 @@ Default Value : -- Entity Name : -- Section Id : Top +Assignment Name : POWER_BOARD_THERMAL_MODEL +Value : None (CONSERVATIVE) +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : POWER_PRESET_COOLING_SOLUTION +Value : 23 MM HEAT SINK WITH 200 LFPM AIRFLOW +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : PROJECT_OUTPUT_DIRECTORY Value : output_files Default Value : -- Entity Name : -- Section Id : -- + +Assignment Name : USE_SIGNALTAP_FILE +Value : output_files/stp1.stp +Default Value : -- +Entity Name : -- +Section Id : -- +--------------------------------------------------------------------------------+ @@ -302,40 +356,40 @@ Section Id : -- ; Flow Elapsed Time ; +--------------------------------------------------------------------------------+ Module Name : Analysis & Synthesis -Elapsed Time : 00:00:14 +Elapsed Time : 00:00:15 Average Processors Used : 1.0 Peak Virtual Memory : 446 MB Total CPU Time (on all processors) : 00:00:14 Module Name : Fitter -Elapsed Time : 00:00:21 +Elapsed Time : 00:00:23 Average Processors Used : 1.0 -Peak Virtual Memory : 641 MB -Total CPU Time (on all processors) : 00:00:21 +Peak Virtual Memory : 645 MB +Total CPU Time (on all processors) : 00:00:23 Module Name : Assembler Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 383 MB +Peak Virtual Memory : 387 MB Total CPU Time (on all processors) : 00:00:02 Module Name : TimeQuest Timing Analyzer -Elapsed Time : 00:00:03 +Elapsed Time : 00:00:04 Average Processors Used : 1.0 -Peak Virtual Memory : 445 MB +Peak Virtual Memory : 441 MB Total CPU Time (on all processors) : 00:00:04 Module Name : EDA Netlist Writer -Elapsed Time : 00:00:03 +Elapsed Time : 00:00:04 Average Processors Used : 1.0 -Peak Virtual Memory : 371 MB +Peak Virtual Memory : 368 MB Total CPU Time (on all processors) : 00:00:03 Module Name : Total -Elapsed Time : 00:00:43 +Elapsed Time : 00:00:48 Average Processors Used : -- Peak Virtual Memory : -- -Total CPU Time (on all processors) : 00:00:44 +Total CPU Time (on all processors) : 00:00:46 +--------------------------------------------------------------------------------+ diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index 846186e..1d49a93 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index 102053a..4b49d7d 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Sat Apr 2 14:50:45 2022 +Wed Apr 6 13:57:51 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -24,29 +24,31 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 16. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated 17. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated 18. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated - 19. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component - 20. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component - 21. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component - 22. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component - 23. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component - 24. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_ - 25. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_ - 26. altsyncram Parameter Settings by Entity Instance - 27. altpll Parameter Settings by Entity Instance - 28. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_" - 29. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2" - 30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux" - 31. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_" - 32. Port Connectivity Checks: "z80_top_direct_n:z80_" - 33. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_" - 34. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_" - 35. Port Connectivity Checks: "ula:ula_" - 36. Port Connectivity Checks: "sdram_controller:sdram_" - 37. Port Connectivity Checks: "ram16:ram0" - 38. Port Connectivity Checks: "rom0:rom" - 39. Elapsed Time Per Partition - 40. Analysis & Synthesis Messages - 41. Analysis & Synthesis Suppressed Messages + 19. Parameter Settings for User Entity Instance: debouncer:debounce_turbo + 20. Parameter Settings for User Entity Instance: debouncer:debounce_autofire + 21. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component + 22. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component + 23. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component + 24. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component + 25. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component + 26. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_ + 27. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_ + 28. altsyncram Parameter Settings by Entity Instance + 29. altpll Parameter Settings by Entity Instance + 30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_" + 31. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2" + 32. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux" + 33. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_" + 34. Port Connectivity Checks: "z80_top_direct_n:z80_" + 35. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_" + 36. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_" + 37. Port Connectivity Checks: "ula:ula_" + 38. Port Connectivity Checks: "sdram_controller:sdram_" + 39. Port Connectivity Checks: "ram16:ram0" + 40. Port Connectivity Checks: "rom0:rom" + 41. Elapsed Time Per Partition + 42. Analysis & Synthesis Messages + 43. Analysis & Synthesis Suppressed Messages @@ -72,16 +74,16 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sat Apr 2 14:50:45 2022 ; +; Analysis & Synthesis Status ; Successful - Wed Apr 6 13:57:51 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 2,751 ; -; Total combinational functions ; 2,480 ; -; Dedicated logic registers ; 649 ; -; Total registers ; 649 ; -; Total pins ; 114 ; +; Total logic elements ; 2,885 ; +; Total combinational functions ; 2,614 ; +; Dedicated logic registers ; 714 ; +; Total registers ; 714 ; +; Total pins ; 120 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 ; ; Embedded Multiplier 9-bit elements ; 0 ; @@ -749,6 +751,12 @@ File Type : User Wizard-Generated File File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram_clk_gen.v Library : +File Name with User-Entered Path : debouncer.v +Used in Netlist : yes +File Type : User Verilog HDL File +File Name with Absolute Path : /home/benny/work/fpga/spectrum/debouncer.v +Library : + File Name with User-Entered Path : cpu/toplevel/globals.vh Used in Netlist : yes File Type : Auto-Found Unspecified File @@ -955,32 +963,32 @@ Library : +---------------------------------------------+---------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------+ -; Estimated Total logic elements ; 2,751 ; +; Estimated Total logic elements ; 2,885 ; ; ; ; -; Total combinational functions ; 2480 ; +; Total combinational functions ; 2614 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1776 ; -; -- 3 input functions ; 416 ; -; -- <=2 input functions ; 288 ; +; -- 4 input functions ; 1835 ; +; -- 3 input functions ; 421 ; +; -- <=2 input functions ; 358 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2404 ; -; -- arithmetic mode ; 76 ; +; -- normal mode ; 2482 ; +; -- arithmetic mode ; 132 ; ; ; ; -; Total registers ; 649 ; -; -- Dedicated logic registers ; 649 ; +; Total registers ; 714 ; +; -- Dedicated logic registers ; 714 ; ; -- I/O registers ; 0 ; ; ; ; -; I/O pins ; 114 ; +; I/O pins ; 120 ; ; Total memory bits ; 524288 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 2 ; ; -- PLLs ; 2 ; ; ; ; ; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ; -; Maximum fan-out ; 436 ; -; Total fan-out ; 12502 ; -; Average fan-out ; 3.63 ; +; Maximum fan-out ; 455 ; +; Total fan-out ; 13090 ; +; Average fan-out ; 3.58 ; +---------------------------------------------+---------------------------------+ @@ -988,17 +996,41 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 2480 (108) -LC Registers : 649 (0) +LC Combinationals : 2614 (124) +LC Registers : 714 (21) Memory Bits : 524288 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 114 +Pins : 120 Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work +Compilation Hierarchy Node : |debouncer:debounce_autofire| +LC Combinationals : 34 (34) +LC Registers : 22 (22) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|debouncer:debounce_autofire +Library Name : work + +Compilation Hierarchy Node : |debouncer:debounce_turbo| +LC Combinationals : 34 (34) +LC Registers : 22 (22) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|debouncer:debounce_turbo +Library Name : work + Compilation Hierarchy Node : |ram16:ram0| LC Combinationals : 2 (0) LC Registers : 2 (0) @@ -1048,7 +1080,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -LC Combinationals : 12 (0) +LC Combinationals : 22 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1060,7 +1092,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 12 (0) +LC Combinationals : 22 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1072,7 +1104,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -LC Combinationals : 12 (0) +LC Combinationals : 22 (0) LC Registers : 4 (4) Memory Bits : 262144 DSP Elements : 0 @@ -1108,7 +1140,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -LC Combinationals : 4 (4) +LC Combinationals : 14 (14) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1156,7 +1188,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |sdram_controller:sdram_| -LC Combinationals : 217 (217) +LC Combinationals : 226 (226) LC Registers : 57 (57) Memory Bits : 0 DSP Elements : 0 @@ -1204,7 +1236,7 @@ Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdr Library Name : work Compilation Hierarchy Node : |ula:ula_| -LC Combinationals : 418 (4) +LC Combinationals : 436 (4) LC Registers : 224 (7) Memory Bits : 0 DSP Elements : 0 @@ -1240,7 +1272,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_ Library Name : work Compilation Hierarchy Node : |i2s_intf:i2s_intf_| -LC Combinationals : 68 (68) +LC Combinationals : 67 (67) LC Registers : 42 (42) Memory Bits : 0 DSP Elements : 0 @@ -1312,7 +1344,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -LC Combinationals : 148 (148) +LC Combinationals : 167 (167) LC Registers : 43 (43) Memory Bits : 0 DSP Elements : 0 @@ -1324,7 +1356,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -LC Combinationals : 1723 (2) +LC Combinationals : 1736 (2) LC Registers : 362 (1) Memory Bits : 0 DSP Elements : 0 @@ -1336,7 +1368,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -LC Combinationals : 45 (16) +LC Combinationals : 48 (16) LC Registers : 16 (16) Memory Bits : 0 DSP Elements : 0 @@ -1348,7 +1380,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -LC Combinationals : 29 (12) +LC Combinationals : 32 (15) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1444,7 +1476,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres Library Name : work Compilation Hierarchy Node : |alu:alu_| -LC Combinationals : 128 (75) +LC Combinationals : 130 (76) LC Registers : 20 (20) Memory Bits : 0 DSP Elements : 0 @@ -1468,7 +1500,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se Library Name : work Compilation Hierarchy Node : |alu_core:b2v_core| -LC Combinationals : 20 (0) +LC Combinationals : 21 (0) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1492,7 +1524,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| -LC Combinationals : 5 (5) +LC Combinationals : 4 (4) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1516,7 +1548,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| -LC Combinationals : 3 (3) +LC Combinationals : 5 (5) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1612,7 +1644,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -LC Combinationals : 61 (61) +LC Combinationals : 59 (59) LC Registers : 10 (10) Memory Bits : 0 DSP Elements : 0 @@ -1647,18 +1679,6 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ Library Name : work -Compilation Hierarchy Node : |control_pins_n:control_pins_| -LC Combinationals : 1 (1) -LC Registers : 0 (0) -Memory Bits : 0 -DSP Elements : 0 -DSP 9x9 : 0 -DSP 18x18 : 0 -Pins : 0 -Virtual Pins : 0 -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_ -Library Name : work - Compilation Hierarchy Node : |data_pins:data_pins_| LC Combinationals : 9 (9) LC Registers : 8 (8) @@ -1671,20 +1691,8 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_ Library Name : work -Compilation Hierarchy Node : |data_switch:sw2_| -LC Combinationals : 1 (1) -LC Registers : 0 (0) -Memory Bits : 0 -DSP Elements : 0 -DSP 9x9 : 0 -DSP 18x18 : 0 -Pins : 0 -Virtual Pins : 0 -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ -Library Name : work - Compilation Hierarchy Node : |data_switch_mask:sw1_| -LC Combinationals : 4 (4) +LC Combinationals : 5 (5) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1696,7 +1704,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw Library Name : work Compilation Hierarchy Node : |decode_state:decode_state_| -LC Combinationals : 11 (11) +LC Combinationals : 12 (12) LC Registers : 6 (6) Memory Bits : 0 DSP Elements : 0 @@ -1708,7 +1716,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode Library Name : work Compilation Hierarchy Node : |execute:execute_| -LC Combinationals : 926 (926) +LC Combinationals : 934 (934) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1720,7 +1728,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_ Library Name : work Compilation Hierarchy Node : |interrupts:interrupts_| -LC Combinationals : 10 (10) +LC Combinationals : 11 (11) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1768,7 +1776,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_con Library Name : work Compilation Hierarchy Node : |pla_decode:pla_decode_| -LC Combinationals : 74 (74) +LC Combinationals : 71 (71) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1780,7 +1788,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_deco Library Name : work Compilation Hierarchy Node : |reg_control:reg_control_| -LC Combinationals : 30 (30) +LC Combinationals : 29 (29) LC Registers : 4 (4) Memory Bits : 0 DSP Elements : 0 @@ -1792,7 +1800,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -LC Combinationals : 281 (270) +LC Combinationals : 286 (277) LC Registers : 224 (0) Memory Bits : 0 DSP Elements : 0 @@ -1828,7 +1836,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi| -LC Combinationals : 8 (8) +LC Combinationals : 6 (6) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1900,7 +1908,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_hi| -LC Combinationals : 0 (0) +LC Combinationals : 2 (2) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1984,7 +1992,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_lo| -LC Combinationals : 1 (1) +LC Combinationals : 0 (0) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2128,7 +2136,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo| -LC Combinationals : 2 (2) +LC Combinationals : 1 (1) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2365,12 +2373,12 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 649 ; -; Number of registers using Synchronous Clear ; 13 ; -; Number of registers using Synchronous Load ; 34 ; +; Total registers ; 714 ; +; Number of registers using Synchronous Clear ; 55 ; +; Number of registers using Synchronous Load ; 35 ; ; Number of registers using Asynchronous Clear ; 221 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 464 ; +; Number of registers using Clock Enable ; 481 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -2380,16 +2388,16 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak +----------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------------------------+---------+ -; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 150 ; +; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 3 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 144 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] ; 2 ; -; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; +; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[4] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] ; 2 ; @@ -2397,22 +2405,22 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ; @@ -2425,24 +2433,23 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 64 ; ; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ; ; z80_top_direct_n:z80_|fpga_reset ; 2 ; -; sdram_controller:sdram_|r.init_counter[3] ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out ; 3 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; -; Total number of inverted registers = 62 ; ; +; Total number of inverted registers = 61 ; ; +----------------------------------------------------------+---------+ @@ -2455,7 +2462,7 @@ Baseline Area : 20 LEs Area if Restructured : 10 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[5] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[8] Multiplexer Inputs : 3:1 Bus Width : 4 bits @@ -2463,7 +2470,7 @@ Baseline Area : 8 LEs Area if Restructured : 4 LEs Saving if Restructured : 4 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] +Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] Multiplexer Inputs : 4:1 Bus Width : 2 bits @@ -2479,7 +2486,7 @@ Baseline Area : 20 LEs Area if Restructured : 10 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[3] +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[8] Multiplexer Inputs : 6:1 Bus Width : 5 bits @@ -2487,7 +2494,7 @@ Baseline Area : 20 LEs Area if Restructured : 5 LEs Saving if Restructured : 15 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Multiplexer Inputs : 5:1 Bus Width : 3 bits @@ -2503,7 +2510,7 @@ Baseline Area : 42 LEs Area if Restructured : 14 LEs Saving if Restructured : 28 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Multiplexer Inputs : 5:1 Bus Width : 3 bits @@ -2511,7 +2518,7 @@ Baseline Area : 9 LEs Area if Restructured : 3 LEs Saving if Restructured : 6 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Multiplexer Inputs : 10:1 Bus Width : 2 bits @@ -2519,7 +2526,7 @@ Baseline Area : 12 LEs Area if Restructured : 2 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[11] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[12] Multiplexer Inputs : 10:1 Bus Width : 2 bits @@ -2527,7 +2534,7 @@ Baseline Area : 12 LEs Area if Restructured : 2 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[8] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[9] Multiplexer Inputs : 32:1 Bus Width : 5 bits @@ -2535,7 +2542,7 @@ Baseline Area : 105 LEs Area if Restructured : 0 LEs Saving if Restructured : 105 LEs Registered : Yes -Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[1] +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[2] Multiplexer Inputs : 8:1 Bus Width : 2 bits @@ -2543,7 +2550,7 @@ Baseline Area : 10 LEs Area if Restructured : 4 LEs Saving if Restructured : 6 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Multiplexer Inputs : 32:1 Bus Width : 2 bits @@ -2559,7 +2566,7 @@ Baseline Area : 80 LEs Area if Restructured : 4 LEs Saving if Restructured : 76 LEs Registered : Yes -Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[8] +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[9] Multiplexer Inputs : 31:1 Bus Width : 2 bits @@ -2575,7 +2582,7 @@ Baseline Area : 12 LEs Area if Restructured : 4 LEs Saving if Restructured : 8 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Multiplexer Inputs : 9:1 Bus Width : 3 bits @@ -2583,7 +2590,7 @@ Baseline Area : 18 LEs Area if Restructured : 3 LEs Saving if Restructured : 15 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[0] Multiplexer Inputs : 27:1 Bus Width : 4 bits @@ -2591,7 +2598,7 @@ Baseline Area : 72 LEs Area if Restructured : 52 LEs Saving if Restructured : 20 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Multiplexer Inputs : 3:1 Bus Width : 16 bits @@ -2623,15 +2630,7 @@ Baseline Area : 9 LEs Area if Restructured : 6 LEs Saving if Restructured : 3 LEs Registered : No -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[2] - -Multiplexer Inputs : 6:1 -Bus Width : 2 bits -Baseline Area : 8 LEs -Area if Restructured : 6 LEs -Saving if Restructured : 2 LEs -Registered : No -Example Multiplexer Output : |spectrum|Mux0 +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[1] Multiplexer Inputs : 4:1 Bus Width : 8 bits @@ -2641,13 +2640,21 @@ Saving if Restructured : 8 LEs Registered : No Example Multiplexer Output : |spectrum|sdram_controller:sdram_|Mux74 -Multiplexer Inputs : 8:1 -Bus Width : 6 bits -Baseline Area : 30 LEs -Area if Restructured : 24 LEs -Saving if Restructured : 6 LEs +Multiplexer Inputs : 7:1 +Bus Width : 2 bits +Baseline Area : 8 LEs +Area if Restructured : 8 LEs +Saving if Restructured : 0 LEs Registered : No -Example Multiplexer Output : |spectrum|Selector0 +Example Multiplexer Output : |spectrum|Selector4 + +Multiplexer Inputs : 9:1 +Bus Width : 5 bits +Baseline Area : 30 LEs +Area if Restructured : 20 LEs +Saving if Restructured : 10 LEs +Registered : No +Example Multiplexer Output : |spectrum|Selector14 Multiplexer Inputs : 9:1 Bus Width : 2 bits @@ -2701,6 +2708,28 @@ To : - ++--------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: debouncer:debounce_turbo ; ++--------------------------------------------------------------------------------+ +Parameter Name : c_DEBOUNCE_LIMIT +Value : 1100000 +Type : Signed Integer ++--------------------------------------------------------------------------------+ + +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: debouncer:debounce_autofire ; ++--------------------------------------------------------------------------------+ +Parameter Name : c_DEBOUNCE_LIMIT +Value : 1100000 +Type : Signed Integer ++--------------------------------------------------------------------------------+ + +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + +--------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ; +--------------------------------------------------------------------------------+ @@ -6580,7 +6609,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:11 ; +; Top ; 00:00:12 ; +----------------+--------------+ @@ -6590,7 +6619,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Sat Apr 2 14:50:31 2022 + Info: Processing started: Wed Apr 6 13:57:36 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv @@ -6708,10 +6737,31 @@ Info (12021): Found 2 design units, including 1 entities, in source file sdram.v Info (12023): Found entity 1: sdram_controller Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v Info (12023): Found entity 1: sdram_clk_gen +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126) +Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128) +Info (12021): Found 1 design units, including 1 entities, in source file sdram.v + Info (12023): Found entity 1: sdram +Info (12021): Found 1 design units, including 1 entities, in source file sdram_ctrl.v + Info (12023): Found entity 1: SDRAM_ctrl +Info (12021): Found 1 design units, including 1 entities, in source file sdram_controller.v + Info (12023): Found entity 1: sdram_controller_new +Info (12021): Found 1 design units, including 1 entities, in source file pll_sdram.v + Info (12023): Found entity 1: pll_sdram +Info (12021): Found 1 design units, including 1 entities, in source file debouncer.v + Info (12023): Found entity 1: debouncer Info (12127): Elaborating entity "spectrum" for the top level hierarchy -Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver -Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver -Warning (10034): Output port "GPIO_1[33..32]" at spectrum.sv(20) has no driver +Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(114): object "is_io_read_requested" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(115): object "is_io_write_requested" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(118): object "is_rom_address" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(133): object "kempston_last_fire_state" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(231): object "sdram_write_request" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at spectrum.sv(141): truncated value with size 32 to match size of target (18) +Info (12128): Elaborating entity "debouncer" for hierarchy "debouncer:debounce_turbo" +Warning (10230): Verilog HDL assignment warning at debouncer.v(13): truncated value with size 32 to match size of target (21) Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" @@ -7006,10 +7056,10 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]" to the node "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "RamWE" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "sdram_read_request" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nWR" to the node "RamWE" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal1" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal1" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal5" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal5" into an OR gate Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[0]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[0]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[7]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[7]" into an OR gate @@ -7086,35 +7136,30 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "LED[1]" is stuck at GND - Warning (13410): Pin "LED[4]" is stuck at GND - Warning (13410): Pin "LED[5]" is stuck at GND - Warning (13410): Pin "LED[6]" is stuck at GND - Warning (13410): Pin "LED[7]" is stuck at GND Warning (13410): Pin "GPIO_1[24]" is stuck at VCC - Warning (13410): Pin "GPIO_1[32]" is stuck at GND - Warning (13410): Pin "GPIO_1[33]" is stuck at GND Warning (13410): Pin "DRAM_CKE" is stuck at VCC Warning (13410): Pin "DRAM_CS_N" is stuck at GND + Warning (13410): Pin "kempston_gnd" is stuck at GND Info (286030): Timing-Driven Synthesis is running Info (17049): 2 registers lost all their fanouts during netlist optimizations. Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL -Warning (21074): Design contains 2 input pin(s) that do not drive logic +Warning (21074): Design contains 3 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "SW[0]" + Warning (15610): No output dependent on input pin "SW[2]" Warning (15610): No output dependent on input pin "SW[3]" -Info (21057): Implemented 3006 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 11 input pins - Info (21059): Implemented 85 output pins +Info (21057): Implemented 3146 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 18 input pins + Info (21059): Implemented 84 output pins Info (21060): Implemented 18 bidirectional pins - Info (21061): Implemented 2826 logic cells + Info (21061): Implemented 2960 logic cells Info (21064): Implemented 64 RAM segments Info (21065): Implemented 2 PLLs -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 117 warnings Info: Peak virtual memory: 446 megabytes - Info: Processing ended: Sat Apr 2 14:50:45 2022 - Info: Elapsed time: 00:00:14 + Info: Processing ended: Wed Apr 6 13:57:51 2022 + Info: Elapsed time: 00:00:15 Info: Total CPU time (on all processors): 00:00:15 diff --git a/output_files/spectrum.map.smsg b/output_files/spectrum.map.smsg index c246cc5..dbea507 100644 --- a/output_files/spectrum.map.smsg +++ b/output_files/spectrum.map.smsg @@ -1,2 +1,3 @@ Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(19): object "nRESET" differs only in case from object "nreset" in the same scope Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(22): object "CLK" differs only in case from object "clk" in the same scope +Warning (10273): Verilog HDL warning at sdram_controller.v(166): extended using "x" or "z" diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 547a1c8..35dce1f 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,13 +1,13 @@ -Analysis & Synthesis Status : Successful - Sat Apr 2 14:50:45 2022 +Analysis & Synthesis Status : Successful - Wed Apr 6 13:57:51 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 2,751 - Total combinational functions : 2,480 - Dedicated logic registers : 649 -Total registers : 649 -Total pins : 114 +Total logic elements : 2,885 + Total combinational functions : 2,614 + Dedicated logic registers : 714 +Total registers : 714 +Total pins : 120 Total virtual pins : 0 Total memory bits : 524,288 Embedded Multiplier 9-bit elements : 0 diff --git a/output_files/spectrum.pin b/output_files/spectrum.pin index 23d60f8..ae16767 100644 --- a/output_files/spectrum.pin +++ b/output_files/spectrum.pin @@ -71,8 +71,8 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage VCCIO8 : A1 : power : : 3.3V : 8 : RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +kempston[1] : A4 : input : 3.3-V LVTTL : : 8 : Y +kempston[3] : A5 : input : 3.3-V LVTTL : : 8 : Y buzzer_out : A6 : output : 3.3-V LVTTL : : 8 : Y AUD_XCK : A7 : output : 3.3-V LVTTL : : 8 : Y GND+ : A8 : : : : 8 : @@ -86,9 +86,9 @@ LED[0] : A15 : output : 3.3-V LVTTL : VCCIO7 : A16 : power : : 3.3V : 7 : LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y GND : B2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +kempston_gnd : B3 : output : 3.3-V LVTTL : : 8 : Y +kempston[0] : B4 : input : 3.3-V LVTTL : : 8 : Y +kempston[2] : B5 : input : 3.3-V LVTTL : : 8 : Y raw_loader_in : B6 : input : 3.3-V LVTTL : : 8 : Y PS2_DAT : B7 : input : 3.3-V LVTTL : : 8 : Y GND+ : B8 : : : : 8 : @@ -120,7 +120,7 @@ LED[4] : D1 : output : 3.3-V LVTTL : ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : VCCD_PLL3 : D4 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +kempston[4] : D5 : input : 3.3-V LVTTL : : 8 : Y PS2_CLK : D6 : input : 3.3-V LVTTL : : 8 : Y GND : D7 : gnd : : : : AUD_ADCDAT : D8 : input : 3.3-V LVTTL : : 8 : Y @@ -208,8 +208,8 @@ GND : J9 : gnd : : GND : J10 : gnd : : : : GND : J11 : gnd : : : : VCCINT : J12 : power : : 1.2V : : -GPIO_1[32] : J13 : output : 3.3-V LVTTL : : 5 : Y -GPIO_1[33] : J14 : output : 3.3-V LVTTL : : 5 : Y +turbo_button : J13 : input : 3.3-V LVTTL : : 5 : Y +kempston_autofire_button : J14 : input : 3.3-V LVTTL : : 5 : Y KEY[0] : J15 : input : 3.3-V LVTTL : : 5 : Y GPIO_1[30] : J16 : output : 3.3-V LVTTL : : 5 : Y DRAM_DQ[15] : K1 : bidir : 3.3-V LVTTL : : 2 : Y diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 89c7aaf..e1976de 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index 2fe65db..b5d148c 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Sat Apr 2 14:51:17 2022 +Wed Apr 6 13:58:24 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -21,11 +21,11 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 13. Slow 1200mV 85C Model Setup: 'CLOCK_50' 14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 17. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' - 18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 16. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 17. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' 21. Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' 22. Slow 1200mV 85C Model Hold: 'CLOCK_50' 23. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' @@ -55,12 +55,12 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 47. Slow 1200mV 0C Model Setup: 'CLOCK_50' 48. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 49. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 50. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 51. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' - 52. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 54. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 55. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 50. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 51. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 52. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 54. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 55. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' 56. Slow 1200mV 0C Model Hold: 'CLOCK_50' 57. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 58. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' @@ -88,13 +88,13 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 80. Fast 1200mV 0C Model Setup: 'CLOCK_50' 81. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 82. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 83. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 84. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' - 85. Fast 1200mV 0C Model Hold: 'CLOCK_50' - 86. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 88. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' - 89. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 83. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 84. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 85. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 86. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 88. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 89. Fast 1200mV 0C Model Hold: 'CLOCK_50' 90. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 91. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 92. Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' @@ -184,7 +184,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +--------------------------------------------------------------------------------+ SDC File Path : spectrum.sdc Status : OK -Read at : Sat Apr 2 14:51:14 2022 +Read at : Wed Apr 6 13:58:21 2022 +--------------------------------------------------------------------------------+ @@ -324,27 +324,27 @@ Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 48.03 MHz -Restricted Fmax : 48.03 MHz +Fmax : 48.81 MHz +Restricted Fmax : 48.81 MHz Clock Name : CLOCK_50 Note : -Fmax : 118.6 MHz -Restricted Fmax : 118.6 MHz +Fmax : 127.71 MHz +Restricted Fmax : 127.71 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 153.92 MHz -Restricted Fmax : 153.92 MHz +Fmax : 148.39 MHz +Restricted Fmax : 148.39 MHz Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 163.48 MHz -Restricted Fmax : 163.48 MHz +Fmax : 172.89 MHz +Restricted Fmax : 172.89 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 940.73 MHz +Fmax : 840.34 MHz Restricted Fmax : 500.0 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Note : limit due to minimum period restriction (tmin) @@ -363,23 +363,23 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -18.571 -End Point TNS : -821.372 +Slack : -18.476 +End Point TNS : -808.800 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -7.747 -End Point TNS : -287.138 +Slack : -7.513 +End Point TNS : -282.972 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.731 -End Point TNS : -41.432 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.915 -End Point TNS : -2.915 +Slack : -4.734 +End Point TNS : -42.279 Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Slack : 3.503 +Slack : 3.261 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 70.299 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -388,24 +388,24 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : 0.342 -End Point TNS : 0.000 - Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.342 +Slack : 0.344 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Slack : 0.357 End Point TNS : 0.000 +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 0.357 +End Point TNS : 0.000 + Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Slack : 0.359 +Slack : 0.358 End Point TNS : 0.000 Clock : CLOCK_50 -Slack : 0.373 +Slack : 0.382 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -415,8 +415,8 @@ End Point TNS : 0.000 ; Slow 1200mV 85C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -6.212 -End Point TNS : -460.730 +Slack : -6.210 +End Point TNS : -460.961 +--------------------------------------------------------------------------------+ @@ -425,7 +425,7 @@ End Point TNS : -460.730 ; Slow 1200mV 85C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.666 +Slack : 3.689 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -447,11 +447,11 @@ Slack : 19.602 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 20.597 +Slack : 20.593 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : 35.503 +Slack : 35.490 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -460,905 +460,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -18.571 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.393 - -Slack : -18.455 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.277 - -Slack : -18.451 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 8.292 - -Slack : -18.439 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.261 - -Slack : -18.432 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.505 -Data Delay : 8.001 - -Slack : -18.426 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 8.267 - -Slack : -18.398 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.956 - -Slack : -18.391 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.950 - -Slack : -18.389 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 7.954 - -Slack : -18.372 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.194 - -Slack : -18.364 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.186 - -Slack : -18.356 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.178 - -Slack : -18.353 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 8.194 - -Slack : -18.347 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.169 - -Slack : -18.345 -From Node : ula:ula_|video:video_|frame[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.249 -Data Delay : 8.170 - -Slack : -18.344 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.166 - -Slack : -18.335 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.157 - -Slack : -18.314 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.136 - -Slack : -18.303 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 8.144 - -Slack : -18.300 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.122 - -Slack : -18.275 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.833 - -Slack : -18.250 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.808 - -Slack : -18.211 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.033 - -Slack : -18.206 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.028 - -Slack : -18.202 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.024 - -Slack : -18.186 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.505 -Data Delay : 7.755 - -Slack : -18.180 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.002 - -Slack : -18.178 -From Node : ula:ula_|video:video_|bits[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 8.000 - -Slack : -18.177 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 8.018 - -Slack : -18.155 +Slack : -18.476 From Node : ula:ula_|video:video_|vga_vc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.977 +Clock Skew : -0.253 +Data Delay : 8.297 -Slack : -18.153 -From Node : ula:ula_|video:video_|bits[1] +Slack : -18.463 +From Node : ula:ula_|video:video_|vga_vc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.975 +Clock Skew : -0.253 +Data Delay : 8.284 -Slack : -18.147 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.707 - -Slack : -18.145 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.704 - -Slack : -18.143 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 7.708 - -Slack : -18.107 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.948 - -Slack : -18.102 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 7.667 - -Slack : -18.073 -From Node : ula:ula_|video:video_|vga_vc[5] +Slack : -18.424 +From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.895 +Clock Skew : -0.244 +Data Delay : 8.254 -Slack : -18.071 +Slack : -18.421 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 8.251 + +Slack : -18.405 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 8.235 + +Slack : -18.370 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 8.191 + +Slack : -18.327 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 8.148 + +Slack : -18.296 From Node : ula:ula_|video:video_|vga_vc[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.893 +Clock Skew : -0.253 +Data Delay : 8.117 -Slack : -18.024 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] +Slack : -18.259 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.584 +Clock Skew : -0.253 +Data Delay : 8.080 -Slack : -18.018 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : DRAM_DQ[2] +Slack : -18.230 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.578 +Clock Skew : -0.253 +Data Delay : 8.051 -Slack : -18.010 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : DRAM_DQ[5] +Slack : -18.227 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 7.566 +Clock Skew : -0.253 +Data Delay : 8.048 -Slack : -18.004 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] +Slack : -18.205 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.562 +Clock Skew : -0.253 +Data Delay : 8.026 -Slack : -18.001 +Slack : -18.178 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 8.008 + +Slack : -18.166 From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.823 +Clock Skew : -0.244 +Data Delay : 7.996 -Slack : -17.982 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : DRAM_DQ[2] +Slack : -18.079 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.542 +Clock Skew : -0.253 +Data Delay : 7.900 -Slack : -17.978 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[2] +Slack : -18.056 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.877 + +Slack : -18.035 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.819 +Data Delay : 7.876 -Slack : -17.976 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] +Slack : -18.016 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 7.541 +Clock Skew : -0.233 +Data Delay : 7.857 -Slack : -17.956 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.516 - -Slack : -17.947 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.507 - -Slack : -17.932 +Slack : -18.002 From Node : ula:ula_|video:video_|vga_hc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.754 +Clock Skew : -0.244 +Data Delay : 7.832 -Slack : -17.932 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.492 - -Slack : -17.925 -From Node : ula:ula_|video:video_|bits[2] +Slack : -17.989 +From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.747 +Clock Skew : -0.253 +Data Delay : 7.810 -Slack : -17.903 +Slack : -17.982 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.744 - -Slack : -17.890 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.712 - -Slack : -17.876 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.520 -Data Delay : 7.430 - -Slack : -17.873 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.423 - -Slack : -17.872 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.431 - -Slack : -17.864 -From Node : ula:ula_|video:video_|attr[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.686 - -Slack : -17.859 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.681 - -Slack : -17.850 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.400 - -Slack : -17.841 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.682 +Data Delay : 7.823 -Slack : -17.827 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[5] +Slack : -17.978 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.668 +Clock Skew : -0.509 +Data Delay : 7.543 -Slack : -17.807 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.366 - -Slack : -17.805 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 7.366 - -Slack : -17.804 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.645 - -Slack : -17.794 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.344 - -Slack : -17.788 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.338 - -Slack : -17.757 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.316 - -Slack : -17.746 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.305 - -Slack : -17.732 +Slack : -17.955 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.282 +Clock Skew : -0.523 +Data Delay : 7.506 -Slack : -17.731 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[7] +Slack : -17.928 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.572 +Clock Skew : -0.520 +Data Delay : 7.482 -Slack : -17.706 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[5] +Slack : -17.924 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.547 +Clock Skew : -0.253 +Data Delay : 7.745 -Slack : -17.698 +Slack : -17.923 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.744 + +Slack : -17.920 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.741 + +Slack : -17.910 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.731 + +Slack : -17.889 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 7.456 + +Slack : -17.880 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.701 + +Slack : -17.880 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 7.442 + +Slack : -17.875 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.539 +Data Delay : 7.716 -Slack : -17.680 +Slack : -17.866 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.687 + +Slack : -17.855 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 7.420 + +Slack : -17.854 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.675 + +Slack : -17.852 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 7.404 + +Slack : -17.832 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.244 +Data Delay : 7.662 + +Slack : -17.816 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.657 + +Slack : -17.807 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 7.358 + +Slack : -17.780 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.621 + +Slack : -17.747 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.568 + +Slack : -17.746 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.505 +Data Delay : 7.315 + +Slack : -17.688 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.521 +Data Delay : 7.529 -Slack : -17.670 +Slack : -17.665 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.215 + +Slack : -17.638 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.479 + +Slack : -17.624 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.185 + +Slack : -17.623 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.173 + +Slack : -17.587 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.428 + +Slack : -17.584 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.425 + +Slack : -17.575 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.416 + +Slack : -17.572 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.393 + +Slack : -17.571 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.412 + +Slack : -17.542 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.103 + +Slack : -17.518 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 7.070 + +Slack : -17.517 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.358 + +Slack : -17.515 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.524 -Data Delay : 7.220 +Data Delay : 7.065 -Slack : -17.660 +Slack : -17.513 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 7.223 - -Slack : -17.659 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.500 - -Slack : -17.636 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.477 +Clock Skew : -0.509 +Data Delay : 7.078 -Slack : -17.620 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +Slack : -17.507 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.180 - -Slack : -17.610 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 7.173 - -Slack : -17.600 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : DRAM_DQ[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.159 - -Slack : -17.593 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 7.156 - -Slack : -17.587 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.146 - -Slack : -17.580 -From Node : ula:ula_|video:video_|bits[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.252 -Data Delay : 7.402 - -Slack : -17.569 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 7.125 - -Slack : -17.563 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 7.114 - -Slack : -17.546 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.387 - -Slack : -17.538 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.088 - -Slack : -17.528 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -To Node : DRAM_DQ[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.513 -Data Delay : 7.089 +Data Delay : 7.068 -Slack : -17.490 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : DRAM_DQ[1] +Slack : -17.506 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.507 -Data Delay : 7.057 +Clock Skew : -0.511 +Data Delay : 7.069 -Slack : -17.487 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.045 - -Slack : -17.486 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.233 -Data Delay : 7.327 - -Slack : -17.477 +Slack : -17.484 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.318 +Data Delay : 7.325 + +Slack : -17.472 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.022 + +Slack : -17.462 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.012 Slack : -17.452 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[0] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 Data Delay : 7.293 -Slack : -17.450 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] +Slack : -17.442 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.000 + +Slack : -17.436 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 6.999 + +Slack : -17.434 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.253 +Data Delay : 7.255 + +Slack : -17.428 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.984 + +Slack : -17.426 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.515 -Data Delay : 7.009 +Data Delay : 6.985 -Slack : -17.443 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[1] +Slack : -17.426 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.284 +Data Delay : 7.267 -Slack : -17.435 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Slack : -17.424 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.520 -Data Delay : 6.989 +Clock Skew : -0.524 +Data Delay : 6.974 -Slack : -17.430 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : GPIO_1[19] +Slack : -17.424 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 6.991 + +Slack : -17.417 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.515 -Data Delay : 6.989 +Data Delay : 6.976 -Slack : -17.401 +Slack : -17.414 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.973 + +Slack : -17.414 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.255 + +Slack : -17.412 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.972 + +Slack : -17.410 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.251 + +Slack : -17.402 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.952 + +Slack : -17.389 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.948 + +Slack : -17.387 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.939 + +Slack : -17.379 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.951 +Clock Skew : -0.511 +Data Delay : 6.942 -Slack : -17.399 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] +Slack : -17.367 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 6.962 +Clock Skew : -0.518 +Data Delay : 6.923 -Slack : -17.396 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] +Slack : -17.365 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.923 + +Slack : -17.364 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.922 + +Slack : -17.359 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.233 -Data Delay : 7.237 +Data Delay : 7.200 + +Slack : -17.353 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.912 + +Slack : -17.346 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.187 + +Slack : -17.340 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.181 + +Slack : -17.316 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.157 + +Slack : -17.310 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.151 + +Slack : -17.281 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.505 +Data Delay : 6.850 + +Slack : -17.277 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.829 + +Slack : -17.274 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.824 + +Slack : -17.273 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.833 + +Slack : -17.270 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.831 + +Slack : -17.255 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.096 + +Slack : -17.252 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 6.806 + +Slack : -17.229 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.787 + +Slack : -17.221 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.771 + +Slack : -17.208 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.767 + +Slack : -17.204 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.766 +--------------------------------------------------------------------------------+ @@ -1366,473 +1366,140 @@ Data Delay : 7.237 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -7.747 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 5.558 - -Slack : -7.745 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.302 -Data Delay : 5.551 - -Slack : -7.636 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.249 -Data Delay : 5.495 - -Slack : -7.634 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 5.488 - -Slack : -7.563 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.298 -Data Delay : 5.373 - -Slack : -7.492 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 5.303 - -Slack : -7.475 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.287 -Data Delay : 5.296 - -Slack : -7.464 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.305 -Data Delay : 5.267 - -Slack : -7.437 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 5.246 - -Slack : -7.436 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.279 -Data Delay : 5.265 - -Slack : -7.401 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.291 -Data Delay : 5.218 - -Slack : -7.381 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 5.208 - -Slack : -7.356 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.249 -Data Delay : 5.215 - -Slack : -7.345 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.302 -Data Delay : 5.151 - -Slack : -7.333 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.291 -Data Delay : 5.150 - -Slack : -7.320 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.302 -Data Delay : 5.126 - -Slack : -7.316 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 5.125 - -Slack : -7.296 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 5.109 - -Slack : -7.289 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.113 - -Slack : -7.233 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.289 -Data Delay : 5.052 - -Slack : -7.232 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 5.097 - -Slack : -7.222 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 5.087 - -Slack : -7.177 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 5.040 - -Slack : -7.165 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.305 -Data Delay : 4.968 - -Slack : -7.163 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.263 -Data Delay : 5.008 - -Slack : -7.159 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.974 - -Slack : -7.148 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.959 - -Slack : -7.147 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -7.513 +From Node : kempston[2] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.972 +Clock Skew : 0.158 +Data Delay : 5.779 -Slack : -7.143 +Slack : -7.251 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.150 +Data Delay : 5.509 + +Slack : -7.249 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.148 +Data Delay : 5.505 + +Slack : -7.223 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.287 +Data Delay : 5.044 + +Slack : -7.220 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.149 +Data Delay : 5.477 + +Slack : -7.144 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.268 +Data Delay : 4.984 + +Slack : -7.116 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.264 +Data Delay : 4.960 + +Slack : -7.112 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.260 +Data Delay : 4.960 + +Slack : -7.092 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.149 +Data Delay : 5.349 + +Slack : -7.056 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.880 + +Slack : -7.026 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.880 + +Slack : -7.025 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.261 +Data Delay : 4.872 + +Slack : -7.003 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.299 +Data Delay : 4.812 + +Slack : -6.994 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.255 +Data Delay : 4.847 + +Slack : -6.970 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.302 -Data Delay : 4.949 - -Slack : -7.136 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.951 - -Slack : -7.117 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.933 - -Slack : -7.103 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.275 -Data Delay : 4.936 - -Slack : -7.093 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.947 - -Slack : -7.091 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.290 -Data Delay : 4.909 - -Slack : -7.085 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.248 -Data Delay : 4.945 - -Slack : -7.072 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.290 -Data Delay : 4.890 - -Slack : -7.066 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.882 - -Slack : -7.062 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.247 -Data Delay : 4.923 - -Slack : -7.059 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.874 - -Slack : -7.038 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.247 -Data Delay : 4.899 - -Slack : -7.037 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.300 -Data Delay : 4.845 - -Slack : -7.020 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -2.296 -Data Delay : 4.832 - -Slack : -7.018 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 4.827 - -Slack : -7.015 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.288 -Data Delay : 4.835 - -Slack : -7.006 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.872 - -Slack : -6.994 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.296 -Data Delay : 4.806 - -Slack : -6.987 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.291 -Data Delay : 4.804 - -Slack : -6.984 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.271 -Data Delay : 4.821 - -Slack : -6.978 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.805 - -Slack : -6.978 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.260 -Data Delay : 4.826 - -Slack : -6.960 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.294 -Data Delay : 4.774 - -Slack : -6.960 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.300 -Data Delay : 4.768 +Data Delay : 4.782 Slack : -6.959 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 @@ -1840,350 +1507,332 @@ To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_g Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.256 -Data Delay : 4.811 +Clock Skew : -2.251 +Data Delay : 4.816 -Slack : -6.955 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Slack : -6.958 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.819 +Clock Skew : -2.300 +Data Delay : 4.766 -Slack : -6.953 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -6.935 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.807 +Clock Skew : -2.293 +Data Delay : 4.750 -Slack : -6.953 +Slack : -6.929 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.150 +Data Delay : 5.187 + +Slack : -6.927 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.159 +Data Delay : 5.194 + +Slack : -6.926 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.755 + +Slack : -6.915 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.287 +Data Delay : 4.736 + +Slack : -6.914 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.739 + +Slack : -6.911 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 4.729 + +Slack : -6.908 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.282 +Data Delay : 4.734 + +Slack : -6.906 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.264 +Data Delay : 4.750 + +Slack : -6.900 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.260 +Data Delay : 4.748 + +Slack : -6.879 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.694 + +Slack : -6.875 +From Node : kempston[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.151 +Data Delay : 5.134 + +Slack : -6.874 +From Node : kempston[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.150 +Data Delay : 5.132 + +Slack : -6.867 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.297 +Data Delay : 4.678 + +Slack : -6.867 +From Node : kempston[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.151 +Data Delay : 5.126 + +Slack : -6.857 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 4.674 + +Slack : -6.856 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.721 + +Slack : -6.845 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 4.658 + +Slack : -6.809 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.660 + +Slack : -6.804 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.260 +Data Delay : 4.652 + +Slack : -6.800 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.263 +Data Delay : 4.645 + +Slack : -6.788 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.604 + +Slack : -6.787 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.255 +Data Delay : 4.640 + +Slack : -6.768 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.150 +Data Delay : 5.026 + +Slack : -6.765 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.589 + +Slack : -6.760 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.575 + +Slack : -6.738 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.260 +Data Delay : 4.586 + +Slack : -6.737 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.565 + +Slack : -6.732 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.289 -Data Delay : 4.772 +Data Delay : 4.551 -Slack : -6.945 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 5.049 - -Slack : -6.929 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.793 - -Slack : -6.919 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.252 -Data Delay : 4.775 - -Slack : -6.917 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.732 - -Slack : -6.914 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.262 -Data Delay : 4.760 - -Slack : -6.910 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.775 - -Slack : -6.909 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.251 -Data Delay : 4.766 - -Slack : -6.899 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.239 -Data Delay : 4.768 - -Slack : -6.895 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.290 -Data Delay : 4.713 - -Slack : -6.893 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.268 -Data Delay : 4.733 - -Slack : -6.886 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.709 - -Slack : -6.860 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 4.684 - -Slack : -6.856 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.252 -Data Delay : 4.712 - -Slack : -6.854 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.257 -Data Delay : 4.705 - -Slack : -6.852 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.716 - -Slack : -6.852 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.294 -Data Delay : 4.666 - -Slack : -6.851 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 4.714 - -Slack : -6.836 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 4.660 - -Slack : -6.829 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.695 - -Slack : -6.825 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.234 -Data Delay : 4.699 - -Slack : -6.824 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.640 - -Slack : -6.824 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.259 -Data Delay : 4.673 - -Slack : -6.822 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.633 - -Slack : -6.807 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.635 - -Slack : -6.783 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.611 - -Slack : -6.779 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.266 -Data Delay : 4.621 - -Slack : -6.770 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.236 -Data Delay : 4.642 - -Slack : -6.757 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Slack : -6.729 +From Node : kempston[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.572 +Clock Skew : 0.151 +Data Delay : 4.988 -Slack : -6.723 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Slack : -6.720 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.252 -Data Delay : 4.579 +Clock Skew : -2.267 +Data Delay : 4.561 -Slack : -6.709 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Slack : -6.695 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.257 -Data Delay : 4.560 +Clock Skew : -2.299 +Data Delay : 4.504 -Slack : -6.707 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.522 - -Slack : -6.705 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +Slack : -6.691 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.255 -Data Delay : 4.558 +Clock Skew : -2.302 +Data Delay : 4.497 -Slack : -6.704 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Slack : -6.676 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.289 -Data Delay : 4.523 +Clock Skew : -2.250 +Data Delay : 4.534 -Slack : -6.703 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Slack : -6.664 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.264 -Data Delay : 4.547 - -Slack : -6.678 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.239 -Data Delay : 4.547 +Clock Skew : -2.293 +Data Delay : 4.479 Slack : -6.655 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 @@ -2191,80 +1840,431 @@ To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_g Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.520 +Clock Skew : -2.244 +Data Delay : 4.519 -Slack : -6.649 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.472 - -Slack : -6.642 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.251 -Data Delay : 4.499 - -Slack : -6.642 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.470 - -Slack : -6.633 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.255 -Data Delay : 4.486 - -Slack : -6.617 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.433 - -Slack : -6.608 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.473 - -Slack : -6.605 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Slack : -6.651 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.471 +Clock Skew : -2.251 +Data Delay : 4.508 -Slack : -6.597 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Slack : -6.649 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 4.763 + +Slack : -6.647 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.501 + +Slack : -6.646 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.277 +Data Delay : 4.477 + +Slack : -6.645 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.460 + +Slack : -6.644 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.509 + +Slack : -6.643 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.507 + +Slack : -6.641 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.286 +Data Delay : 4.463 + +Slack : -6.640 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 4.453 + +Slack : -6.636 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.501 + +Slack : -6.635 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.450 + +Slack : -6.629 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.264 +Data Delay : 4.473 + +Slack : -6.618 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.270 +Data Delay : 4.456 + +Slack : -6.615 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.452 + +Slack : -6.613 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.233 +Data Delay : 4.488 + +Slack : -6.610 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.438 + +Slack : -6.607 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.453 + +Slack : -6.603 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.418 + +Slack : -6.596 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.425 + +Slack : -6.595 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.423 + +Slack : -6.590 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 4.447 + +Slack : -6.588 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.417 + +Slack : -6.582 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.155 +Data Delay : 4.845 + +Slack : -6.565 +From Node : kempston[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.150 +Data Delay : 4.823 + +Slack : -6.553 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.369 + +Slack : -6.529 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.288 +Data Delay : 4.349 + +Slack : -6.529 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.633 + +Slack : -6.514 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.302 +Data Delay : 4.320 + +Slack : -6.473 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.319 + +Slack : -6.472 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.279 +Data Delay : 4.301 + +Slack : -6.470 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.295 + +Slack : -6.462 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.145 +Data Delay : 4.715 + +Slack : -6.442 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 Clock Skew : -2.265 -Data Delay : 4.440 +Data Delay : 4.285 + +Slack : -6.433 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.249 + +Slack : -6.431 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.294 +Data Delay : 4.245 + +Slack : -6.421 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.151 +Data Delay : 4.680 + +Slack : -6.419 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.275 + +Slack : -6.417 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.148 +Data Delay : 4.673 + +Slack : -6.409 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.298 +Data Delay : 4.219 + +Slack : -6.402 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.217 + +Slack : -6.391 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.251 + +Slack : -6.386 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.140 +Data Delay : 4.634 + +Slack : -6.356 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.238 +Data Delay : 4.226 + +Slack : -6.355 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 4.173 + +Slack : -6.355 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.239 +Data Delay : 4.224 + +Slack : -6.349 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.165 + +Slack : -6.348 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.238 +Data Delay : 4.218 +--------------------------------------------------------------------------------+ @@ -2272,947 +2272,905 @@ Data Delay : 4.440 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.731 +Slack : -4.734 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.952 + +Slack : -4.734 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.952 + +Slack : -4.725 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.193 -Data Delay : 2.822 +Data Delay : 2.816 -Slack : -4.573 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.791 - -Slack : -4.573 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.791 - -Slack : -4.102 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.671 - -Slack : -4.102 +Slack : -4.269 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.671 +Clock Skew : 0.169 +Data Delay : 2.817 -Slack : -4.102 +Slack : -4.269 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.671 +Clock Skew : 0.169 +Data Delay : 2.817 -Slack : -4.102 +Slack : -4.269 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.671 +Clock Skew : 0.169 +Data Delay : 2.817 -Slack : -4.102 +Slack : -4.269 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 2.671 +Clock Skew : 0.169 +Data Delay : 2.817 -Slack : -3.948 +Slack : -4.269 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.169 +Data Delay : 2.817 + +Slack : -3.587 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.166 +Clock Skew : 0.194 +Data Delay : 2.160 -Slack : -3.097 +Slack : -3.154 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.199 -Data Delay : 1.675 +Clock Skew : 0.161 +Data Delay : 1.694 -Slack : 16.635 +Slack : 16.936 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.779 +Clock Skew : -0.431 +Data Delay : 3.479 -Slack : 16.649 +Slack : 16.937 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.765 +Clock Skew : -0.431 +Data Delay : 3.478 -Slack : 16.792 +Slack : 16.963 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.452 + +Slack : 16.963 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.452 + +Slack : 16.963 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.452 + +Slack : 16.963 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.452 + +Slack : 16.963 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.452 + +Slack : 16.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.451 + +Slack : 16.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.451 + +Slack : 16.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.451 + +Slack : 16.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.451 + +Slack : 16.964 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.451 + +Slack : 17.071 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.622 +Clock Skew : -0.431 +Data Delay : 3.344 -Slack : 16.818 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.600 - -Slack : 16.818 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.600 - -Slack : 16.832 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.586 - -Slack : 16.832 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.586 - -Slack : 16.842 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 17.098 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.572 +Clock Skew : -0.431 +Data Delay : 3.317 -Slack : 16.842 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 17.098 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.572 +Clock Skew : -0.431 +Data Delay : 3.317 -Slack : 16.842 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 17.098 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.572 +Clock Skew : -0.431 +Data Delay : 3.317 -Slack : 16.842 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 17.098 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.572 +Clock Skew : -0.431 +Data Delay : 3.317 -Slack : 16.842 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 17.098 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.572 +Clock Skew : -0.431 +Data Delay : 3.317 -Slack : 16.851 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.563 - -Slack : 16.851 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.563 - -Slack : 16.856 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.558 - -Slack : 16.856 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.558 - -Slack : 16.856 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.558 - -Slack : 16.856 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.558 - -Slack : 16.856 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.558 - -Slack : 16.865 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.549 - -Slack : 16.865 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.549 - -Slack : 16.889 +Slack : 17.177 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.525 +Clock Skew : -0.431 +Data Delay : 3.238 -Slack : 16.975 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.443 - -Slack : 16.975 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.443 - -Slack : 16.999 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.415 - -Slack : 16.999 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.415 - -Slack : 16.999 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.415 - -Slack : 16.999 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.415 - -Slack : 16.999 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.415 - -Slack : 17.004 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.410 - -Slack : 17.004 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.410 - -Slack : 17.072 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.346 - -Slack : 17.072 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 3.346 - -Slack : 17.096 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.318 - -Slack : 17.096 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.318 - -Slack : 17.096 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.318 - -Slack : 17.096 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.318 - -Slack : 17.096 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.318 - -Slack : 17.105 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.309 - -Slack : 17.105 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.309 - -Slack : 17.223 +Slack : 17.190 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.073 -Data Delay : 3.550 +Clock Skew : -0.431 +Data Delay : 3.225 -Slack : 17.237 +Slack : 17.190 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.225 + +Slack : 17.191 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.073 -Data Delay : 3.536 +Clock Skew : -0.431 +Data Delay : 3.224 -Slack : 17.246 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 17.191 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.170 +Clock Skew : -0.431 +Data Delay : 3.224 -Slack : 17.246 +Slack : 17.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.211 + +Slack : 17.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.211 + +Slack : 17.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.211 + +Slack : 17.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.211 + +Slack : 17.204 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.211 + +Slack : 17.206 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.209 + +Slack : 17.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.182 + +Slack : 17.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.182 + +Slack : 17.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.182 + +Slack : 17.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.182 + +Slack : 17.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.182 + +Slack : 17.325 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.090 + +Slack : 17.325 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.090 + +Slack : 17.363 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.170 +Clock Skew : -0.429 +Data Delay : 3.054 -Slack : 17.260 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 17.363 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.156 +Clock Skew : -0.429 +Data Delay : 3.054 -Slack : 17.260 +Slack : 17.364 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.156 +Clock Skew : -0.429 +Data Delay : 3.053 -Slack : 17.297 +Slack : 17.364 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 3.053 + +Slack : 17.382 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.117 +Clock Skew : -0.431 +Data Delay : 3.033 -Slack : 17.377 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.073 -Data Delay : 3.396 - -Slack : 17.399 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 3.015 - -Slack : 17.403 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.013 - -Slack : 17.403 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 3.013 - -Slack : 17.477 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.073 -Data Delay : 3.296 - -Slack : 17.480 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 2.938 - -Slack : 17.480 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 2.938 - -Slack : 17.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.916 - -Slack : 17.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.430 -Data Delay : 2.916 - -Slack : 17.504 +Slack : 17.409 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.910 +Clock Skew : -0.431 +Data Delay : 3.006 -Slack : 17.504 +Slack : 17.409 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.910 +Clock Skew : -0.431 +Data Delay : 3.006 -Slack : 17.504 +Slack : 17.409 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.910 +Clock Skew : -0.431 +Data Delay : 3.006 -Slack : 17.504 +Slack : 17.409 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.910 +Clock Skew : -0.431 +Data Delay : 3.006 -Slack : 17.504 +Slack : 17.409 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.910 +Clock Skew : -0.431 +Data Delay : 3.006 -Slack : 17.513 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.901 - -Slack : 17.513 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.901 - -Slack : 17.559 +Slack : 17.425 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.855 +Clock Skew : -0.429 +Data Delay : 2.992 -Slack : 17.559 +Slack : 17.425 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.855 - -Slack : 17.559 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.855 - -Slack : 17.559 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.855 - -Slack : 17.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.841 - -Slack : 17.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.841 - -Slack : 17.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.841 - -Slack : 17.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.841 - -Slack : 17.582 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 2.836 +Clock Skew : -0.429 +Data Delay : 2.992 -Slack : 17.582 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.425 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.428 -Data Delay : 2.836 +Clock Skew : -0.429 +Data Delay : 2.992 -Slack : 17.606 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.808 +Clock Skew : -0.429 +Data Delay : 2.991 -Slack : 17.606 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.808 +Clock Skew : -0.429 +Data Delay : 2.991 -Slack : 17.606 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Slack : 17.426 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.808 +Clock Skew : -0.429 +Data Delay : 2.991 -Slack : 17.606 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Slack : 17.431 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.808 +Clock Skew : -0.431 +Data Delay : 2.984 -Slack : 17.606 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Slack : 17.431 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.808 +Clock Skew : -0.431 +Data Delay : 2.984 -Slack : 17.615 +Slack : 17.460 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.799 +Clock Skew : -0.431 +Data Delay : 2.955 -Slack : 17.615 +Slack : 17.460 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.432 -Data Delay : 2.799 +Clock Skew : -0.431 +Data Delay : 2.955 -Slack : 17.623 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Slack : 17.498 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.144 +Clock Skew : -0.429 +Data Delay : 2.919 -Slack : 17.623 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Slack : 17.498 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.144 +Clock Skew : -0.429 +Data Delay : 2.919 -Slack : 17.623 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 17.560 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.144 +Clock Skew : -0.429 +Data Delay : 2.857 -Slack : 17.623 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 17.560 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.144 +Clock Skew : -0.429 +Data Delay : 2.857 -Slack : 17.623 +Slack : 17.560 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.857 + +Slack : 17.599 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.144 +Clock Skew : -0.099 +Data Delay : 3.148 -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.130 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 17.599 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.130 +Clock Skew : -0.099 +Data Delay : 3.148 -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 17.599 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.130 +Clock Skew : -0.099 +Data Delay : 3.148 -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 17.599 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.130 +Clock Skew : -0.099 +Data Delay : 3.148 -Slack : 17.637 +Slack : 17.599 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.148 + +Slack : 17.600 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.079 -Data Delay : 3.130 -+--------------------------------------------------------------------------------+ +Clock Skew : -0.099 +Data Delay : 3.147 +Slack : 17.600 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.147 +Slack : 17.600 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.147 -+--------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; -+--------------------------------------------------------------------------------+ -Slack : -2.915 -From Node : SW[2] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.423 -Clock Skew : 0.216 -Data Delay : 1.509 +Slack : 17.600 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.147 -Slack : 70.426 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.078 -Data Delay : 0.980 +Slack : 17.600 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.147 -Slack : 70.747 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|counter[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.078 -Data Delay : 0.659 +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.813 -Slack : 70.747 -From Node : ula:ula_|clocks:clocks_|clk_cpu -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.078 -Data Delay : 0.659 +Slack : 17.604 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.813 + +Slack : 17.633 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.784 + +Slack : 17.633 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.784 + +Slack : 17.636 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.779 + +Slack : 17.636 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.779 + +Slack : 17.666 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.751 + +Slack : 17.666 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.751 + +Slack : 17.666 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.751 + +Slack : 17.695 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.722 + +Slack : 17.695 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.722 + +Slack : 17.695 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.722 + +Slack : 17.695 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.722 + +Slack : 17.695 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.722 + +Slack : 17.696 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.721 + +Slack : 17.696 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.429 +Data Delay : 2.721 + +Slack : 17.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.013 + +Slack : 17.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.013 + +Slack : 17.734 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.099 +Data Delay : 3.013 +--------------------------------------------------------------------------------+ @@ -3220,947 +3178,938 @@ Data Delay : 0.659 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 3.503 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 6.345 - -Slack : 3.528 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 6.320 - -Slack : 3.604 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.234 - -Slack : 3.637 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 6.211 - -Slack : 3.639 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.199 - -Slack : 3.658 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.180 - -Slack : 3.662 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 6.186 - -Slack : 3.687 +Slack : 3.261 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 6.153 - -Slack : 3.712 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 Clock Skew : -0.050 -Data Delay : 6.136 +Data Delay : 6.587 -Slack : 3.722 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 6.118 - -Slack : 3.741 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 6.099 - -Slack : 3.768 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.070 - -Slack : 3.768 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.070 - -Slack : 3.785 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.053 - -Slack : 3.804 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 6.034 - -Slack : 3.851 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.989 - -Slack : 3.851 +Slack : 3.412 From Node : sdram_controller:sdram_|r.init_counter[11] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.989 +Clock Skew : -0.050 +Data Delay : 6.436 -Slack : 3.868 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.972 - -Slack : 3.887 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.953 - -Slack : 3.892 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.946 - -Slack : 3.936 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.902 - -Slack : 3.975 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.865 - -Slack : 3.988 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.853 - -Slack : 4.000 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.070 -Data Delay : 5.830 - -Slack : 4.007 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.831 - -Slack : 4.019 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.821 - -Slack : 4.023 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.818 - -Slack : 4.041 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.797 - -Slack : 4.042 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.799 - -Slack : 4.052 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.070 -Data Delay : 5.778 - -Slack : 4.055 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.790 - -Slack : 4.068 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.747 - -Slack : 4.080 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.765 - -Slack : 4.090 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.750 - -Slack : 4.103 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.712 - -Slack : 4.107 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.070 -Data Delay : 5.723 - -Slack : 4.122 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.693 - -Slack : 4.124 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.716 - -Slack : 4.130 -From Node : sdram_controller:sdram_|r.wr_pending -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 5.720 - -Slack : 4.142 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.703 - -Slack : 4.152 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.689 - -Slack : 4.152 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.689 - -Slack : 4.164 -From Node : sdram_controller:sdram_|r.state[4] +Slack : 3.574 +From Node : sdram_controller:sdram_|r.state[5] To Node : sdram_controller:sdram_|r.address[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.679 +Clock Skew : -0.079 +Data Delay : 6.245 -Slack : 4.167 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[0] +Slack : 3.580 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.070 -Data Delay : 5.663 +Clock Skew : -0.050 +Data Delay : 6.268 -Slack : 4.167 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.678 - -Slack : 4.169 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.672 - -Slack : 4.176 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.078 -Data Delay : 5.646 - -Slack : 4.188 +Slack : 3.583 From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[4] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.653 +Clock Skew : -0.050 +Data Delay : 6.265 -Slack : 4.189 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.656 - -Slack : 4.196 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.070 -Data Delay : 5.634 - -Slack : 4.214 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.631 - -Slack : 4.232 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.583 - -Slack : 4.232 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.583 - -Slack : 4.236 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.078 -Data Delay : 5.586 - -Slack : 4.241 -From Node : sdram_controller:sdram_|r.rd_pending -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 5.609 - -Slack : 4.243 +Slack : 3.618 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.563 +Clock Skew : -0.086 +Data Delay : 6.196 -Slack : 4.249 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.566 - -Slack : 4.258 -From Node : sdram_controller:sdram_|r.init_counter[6] +Slack : 3.682 +From Node : sdram_controller:sdram_|r.init_counter[13] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.548 +Clock Skew : -0.086 +Data Delay : 6.132 -Slack : 4.262 +Slack : 3.686 From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.162 + +Slack : 3.695 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 6.124 + +Slack : 3.754 +From Node : sdram_controller:sdram_|r.init_counter[4] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.544 +Clock Skew : -0.086 +Data Delay : 6.060 -Slack : 4.264 -From Node : sdram_controller:sdram_|r.act_row[4] +Slack : 3.760 +From Node : sdram_controller:sdram_|r.state[4] To Node : sdram_controller:sdram_|r.address[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.581 +Clock Skew : -0.081 +Data Delay : 6.057 -Slack : 4.268 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.547 - -Slack : 4.276 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.565 - -Slack : 4.276 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.569 - -Slack : 4.283 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.078 -Data Delay : 5.539 - -Slack : 4.301 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.544 - -Slack : 4.320 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.052 -Data Delay : 5.526 - -Slack : 4.320 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.521 - -Slack : 4.343 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.078 -Data Delay : 5.479 - -Slack : 4.345 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.461 - -Slack : 4.345 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.052 -Data Delay : 5.501 - -Slack : 4.351 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 5.494 - -Slack : 4.353 +Slack : 3.761 From Node : sdram_controller:sdram_|r.init_counter[11] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.453 +Clock Skew : -0.086 +Data Delay : 6.053 -Slack : 4.356 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[10] +Slack : 3.769 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.459 +Clock Skew : -0.050 +Data Delay : 6.079 -Slack : 4.361 -From Node : sdram_controller:sdram_|r.state[4] +Slack : 3.769 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 6.048 + +Slack : 3.792 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 6.010 + +Slack : 3.827 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.021 + +Slack : 3.834 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.987 + +Slack : 3.855 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.992 + +Slack : 3.860 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 5.957 + +Slack : 3.862 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.959 + +Slack : 3.865 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 5.953 + +Slack : 3.874 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.940 + +Slack : 3.883 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.964 + +Slack : 3.895 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.949 + +Slack : 3.920 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.926 + +Slack : 3.920 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 5.896 + +Slack : 3.921 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.893 + +Slack : 3.923 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.921 + +Slack : 3.925 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.889 + +Slack : 3.926 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.922 + +Slack : 3.931 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.917 + +Slack : 3.935 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.886 + +Slack : 3.956 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.891 + +Slack : 3.956 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 5.862 + +Slack : 3.959 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.862 + +Slack : 3.964 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.884 + +Slack : 3.969 +From Node : sdram_controller:sdram_|r.state[5] To Node : sdram_controller:sdram_|r.address[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.056 -Data Delay : 5.481 +Clock Skew : -0.080 +Data Delay : 5.849 -Slack : 4.361 +Slack : 3.980 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.867 + +Slack : 3.983 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.863 + +Slack : 3.996 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.848 + +Slack : 4.002 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.812 + +Slack : 4.015 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 5.802 + +Slack : 4.020 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.824 + +Slack : 4.021 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.793 + +Slack : 4.023 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.099 +Data Delay : 5.778 + +Slack : 4.031 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.817 + +Slack : 4.037 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.809 + +Slack : 4.044 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.777 + +Slack : 4.050 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.795 + +Slack : 4.091 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.723 + +Slack : 4.096 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.750 + +Slack : 4.106 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.741 + +Slack : 4.107 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.714 + +Slack : 4.111 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 5.707 + +Slack : 4.150 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.698 + +Slack : 4.154 From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.665 + +Slack : 4.161 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.660 + +Slack : 4.168 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.651 + +Slack : 4.176 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.669 + +Slack : 4.180 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.634 + +Slack : 4.189 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.625 + +Slack : 4.195 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.624 + +Slack : 4.219 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 5.583 + +Slack : 4.220 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.601 + +Slack : 4.228 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 5.574 + +Slack : 4.234 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.585 + +Slack : 4.271 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.552 + +Slack : 4.287 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.561 + +Slack : 4.289 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.557 + +Slack : 4.294 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.078 +Data Delay : 5.526 + +Slack : 4.301 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.522 + +Slack : 4.312 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.502 + +Slack : 4.316 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.527 + +Slack : 4.320 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.499 + +Slack : 4.339 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.081 +Data Delay : 5.478 + +Slack : 4.341 +From Node : sdram_controller:sdram_|r.state[5] To Node : sdram_controller:sdram_|r.address[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.056 -Data Delay : 5.481 +Clock Skew : -0.080 +Data Delay : 5.477 -Slack : 4.361 +Slack : 4.346 +From Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.056 +Data Delay : 5.496 + +Slack : 4.362 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 5.487 + +Slack : 4.362 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.461 + +Slack : 4.375 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 5.441 + +Slack : 4.379 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.101 +Data Delay : 5.420 + +Slack : 4.394 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.454 + +Slack : 4.401 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.079 +Data Delay : 5.420 + +Slack : 4.407 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.080 +Data Delay : 5.413 + +Slack : 4.422 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.425 + +Slack : 4.422 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.077 +Data Delay : 5.401 + +Slack : 4.424 From Node : sdram_controller:sdram_|r.state[4] To Node : sdram_controller:sdram_|r.address[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 5.479 - -Slack : 4.372 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.078 -Data Delay : 5.450 - -Slack : 4.389 -From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[2] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.068 -Data Delay : 5.443 - -Slack : 4.391 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.450 - -Slack : 4.400 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.415 - -Slack : 4.406 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.400 - -Slack : 4.423 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.070 -Data Delay : 5.407 - -Slack : 4.425 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.416 - -Slack : 4.426 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.052 -Data Delay : 5.420 - -Slack : 4.430 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.376 - -Slack : 4.454 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.052 +Clock Skew : -0.082 Data Delay : 5.392 -Slack : 4.471 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.344 - -Slack : 4.479 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.052 -Data Delay : 5.367 - -Slack : 4.480 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.361 - -Slack : 4.502 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.336 - -Slack : 4.505 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.085 -Data Delay : 5.310 - -Slack : 4.507 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.299 - -Slack : 4.509 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.074 -Data Delay : 5.317 - -Slack : 4.512 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.094 -Data Delay : 5.294 - -Slack : 4.529 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.052 -Data Delay : 5.317 - -Slack : 4.535 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.309 - -Slack : 4.546 +Slack : 4.425 From Node : sdram_controller:sdram_|r.state[4] To Node : sdram_controller:sdram_|r.address[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 5.279 +Clock Skew : -0.099 +Data Delay : 5.376 -Slack : 4.573 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.state[0] +Slack : 4.425 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.087 -Data Delay : 5.240 +Clock Skew : -0.098 +Data Delay : 5.377 -Slack : 4.583 -From Node : sdram_controller:sdram_|r.rd_pending -To Node : sdram_controller:sdram_|r.address[5] +Slack : 4.429 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.dq_masks[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.051 -Data Delay : 5.264 +Clock Skew : -0.082 +Data Delay : 5.387 -Slack : 4.585 -From Node : sdram_controller:sdram_|r.init_counter[2] +Slack : 4.429 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 5.387 + +Slack : 4.431 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.101 +Data Delay : 5.368 + +Slack : 4.435 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.099 +Data Delay : 5.366 + +Slack : 4.436 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.104 +Data Delay : 5.360 + +Slack : 4.437 +From Node : sdram_controller:sdram_|r.act_row[4] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.409 + +Slack : 4.438 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 5.364 + +Slack : 4.438 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.098 +Data Delay : 5.364 + +Slack : 4.440 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.071 +Data Delay : 5.389 + +Slack : 4.440 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.406 + +Slack : 4.441 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.072 +Data Delay : 5.387 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 70.299 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 71.489 Clock Skew : -0.058 -Data Delay : 5.255 -+--------------------------------------------------------------------------------+ +Data Delay : 1.127 - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; -+--------------------------------------------------------------------------------+ -Slack : 0.342 +Slack : 70.762 From Node : ula:ula_|clocks:clocks_|clk_cpu To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.577 +Relationship : 71.489 +Clock Skew : -0.063 +Data Delay : 0.659 -Slack : 0.345 +Slack : 70.763 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|counter[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.580 - -Slack : 0.575 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.810 - -Slack : 1.322 -From Node : SW[2] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : -0.017 -Clock Skew : 0.636 -Data Delay : 1.188 +Relationship : 71.489 +Clock Skew : -0.062 +Data Delay : 0.659 +--------------------------------------------------------------------------------+ @@ -4168,42 +4117,15 @@ Data Delay : 1.188 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.342 +Slack : 0.344 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 +Clock Skew : 0.076 Data Delay : 0.577 -Slack : 0.342 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.577 - -Slack : 0.342 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.577 - -Slack : 0.345 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.580 - Slack : 0.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] @@ -4214,23 +4136,14 @@ Clock Skew : 0.078 Data Delay : 0.580 Slack : 0.346 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.580 -Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - Slack : 0.358 From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] @@ -4249,6 +4162,15 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data @@ -4267,6 +4189,15 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] @@ -4277,8 +4208,8 @@ Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4303,6 +4234,51 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.580 + +Slack : 0.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.580 + Slack : 0.361 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] @@ -4330,72 +4306,36 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.597 -Slack : 0.371 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Slack : 0.373 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.591 - -Slack : 0.372 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.592 - -Slack : 0.372 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.592 Slack : 0.373 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.593 +Clock Skew : 0.062 +Data Delay : 0.592 Slack : 0.373 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.593 - -Slack : 0.373 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.593 - -Slack : 0.373 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.593 +Clock Skew : 0.062 +Data Delay : 0.592 Slack : 0.374 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4403,8 +4343,35 @@ Clock Skew : 0.062 Data Delay : 0.593 Slack : 0.374 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.593 + +Slack : 0.374 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.593 + +Slack : 0.374 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.593 + +Slack : 0.374 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4412,85 +4379,148 @@ Clock Skew : 0.062 Data Delay : 0.593 Slack : 0.375 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.594 + +Slack : 0.375 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.594 + +Slack : 0.375 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.594 + +Slack : 0.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.622 + +Slack : 0.404 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.623 + +Slack : 0.412 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.645 + +Slack : 0.425 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.644 + +Slack : 0.430 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.649 + +Slack : 0.436 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.655 + +Slack : 0.479 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.698 + +Slack : 0.481 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.595 +Clock Skew : 0.062 +Data Delay : 0.700 -Slack : 0.376 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Slack : 0.481 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.595 +Data Delay : 0.700 -Slack : 0.386 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 0.482 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.605 +Data Delay : 0.701 -Slack : 0.386 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Slack : 0.506 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.605 +Data Delay : 0.725 -Slack : 0.439 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Slack : 0.524 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.425 -Data Delay : 1.021 +Clock Skew : 0.432 +Data Delay : 1.113 -Slack : 0.460 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 0.541 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.436 -Data Delay : 1.053 - -Slack : 0.510 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.729 - -Slack : 0.534 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.753 - -Slack : 0.542 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.762 +Clock Skew : 0.432 +Data Delay : 1.130 Slack : 0.542 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -4519,80 +4549,8 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.780 -Slack : 0.550 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.769 - -Slack : 0.551 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.771 - -Slack : 0.552 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.772 - -Slack : 0.552 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.772 - -Slack : 0.553 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.773 - -Slack : 0.553 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.773 - -Slack : 0.553 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.772 - -Slack : 0.554 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.773 - Slack : 0.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4600,18 +4558,18 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.790 -Slack : 0.558 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Slack : 0.557 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.777 +Data Delay : 0.776 Slack : 0.561 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4627,41 +4585,95 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.781 -Slack : 0.570 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.790 - -Slack : 0.574 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.793 - -Slack : 0.575 +Slack : 0.563 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.794 +Data Delay : 0.782 -Slack : 0.582 +Slack : 0.567 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.786 + +Slack : 0.568 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.801 +Data Delay : 0.787 + +Slack : 0.569 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.158 + +Slack : 0.573 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.792 + +Slack : 0.576 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.795 + +Slack : 0.576 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 0.793 + +Slack : 0.579 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.812 + +Slack : 0.579 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.076 +Data Delay : 0.812 + +Slack : 0.582 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.169 Slack : 0.583 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] @@ -4672,257 +4684,212 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.802 -Slack : 0.585 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.819 - -Slack : 0.588 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.822 - -Slack : 0.589 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.823 - Slack : 0.590 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.459 -Data Delay : 1.206 - -Slack : 0.591 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.825 - -Slack : 0.607 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.826 - -Slack : 0.610 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.844 - -Slack : 0.697 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.457 -Data Delay : 1.311 - -Slack : 0.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.920 - -Slack : 0.703 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.922 - -Slack : 0.704 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.923 - -Slack : 0.704 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.939 - -Slack : 0.708 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.943 - -Slack : 0.708 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.927 +Data Delay : 0.809 -Slack : 0.710 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Slack : 0.596 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.929 +Clock Skew : 0.076 +Data Delay : 0.829 -Slack : 0.712 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Slack : 0.631 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.931 +Clock Skew : 0.076 +Data Delay : 0.864 -Slack : 0.722 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Slack : 0.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : -0.285 -Data Delay : 0.594 +Clock Skew : 0.430 +Data Delay : 1.260 -Slack : 0.733 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.952 - -Slack : 0.734 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.953 - -Slack : 0.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.457 -Data Delay : 1.354 - -Slack : 0.753 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 0.693 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 0.973 +Data Delay : 0.913 -Slack : 0.755 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Slack : 0.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.974 +Clock Skew : 0.078 +Data Delay : 0.936 -Slack : 0.769 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 0.977 - -Slack : 0.774 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.993 - -Slack : 0.789 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.008 - -Slack : 0.807 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.051 -Data Delay : 1.015 - -Slack : 0.809 +Slack : 0.705 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.028 +Data Delay : 0.924 -Slack : 0.816 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.721 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.035 +Data Delay : 0.940 + +Slack : 0.753 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.342 + +Slack : 0.761 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.406 +Data Delay : 1.324 + +Slack : 0.761 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.406 +Data Delay : 1.324 + +Slack : 0.761 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.406 +Data Delay : 1.324 + +Slack : 0.761 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.406 +Data Delay : 1.324 + +Slack : 0.761 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.406 +Data Delay : 1.324 + +Slack : 0.763 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.997 + +Slack : 0.765 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 0.629 + +Slack : 0.766 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.353 + +Slack : 0.780 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 0.997 + +Slack : 0.784 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.003 + +Slack : 0.785 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.060 +Data Delay : 1.002 + +Slack : 0.787 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.006 + +Slack : 0.787 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.006 + +Slack : 0.802 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.260 +Data Delay : 0.699 Slack : 0.817 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -4942,23 +4909,32 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.054 -Slack : 0.820 +Slack : 0.822 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.039 +Data Delay : 1.041 -Slack : 0.830 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Slack : 0.829 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.049 +Clock Skew : 0.067 +Data Delay : 1.053 + +Slack : 0.829 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.430 +Data Delay : 1.416 Slack : 0.832 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -4970,7 +4946,7 @@ Clock Skew : 0.078 Data Delay : 1.067 Slack : 0.833 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -5006,7 +4982,16 @@ Clock Skew : 0.062 Data Delay : 1.054 Slack : 0.835 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.054 + +Slack : 0.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -5014,58 +4999,22 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.070 -Slack : 0.840 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Slack : 0.851 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.059 +Data Delay : 1.070 -Slack : 0.841 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.854 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.060 - -Slack : 0.844 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.063 - -Slack : 0.847 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.066 - -Slack : 0.850 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.069 - -Slack : 0.852 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.064 Data Delay : 1.073 +--------------------------------------------------------------------------------+ @@ -5074,15 +5023,6 @@ Data Delay : 1.073 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 0.357 -From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - Slack : 0.357 From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 @@ -5101,104 +5041,113 @@ Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.357 +Slack : 0.358 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 From Node : ula:ula_|video:video_|vga_vc[9] To Node : ula:ula_|video:video_|vga_vc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 +Slack : 0.358 From Node : ula:ula_|video:video_|vga_vc[6] To Node : ula:ula_|video:video_|vga_vc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.357 +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 From Node : ula:ula_|video:video_|vga_vc[8] To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.551 +Slack : 0.552 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 0.771 +Data Delay : 0.772 Slack : 0.553 From Node : ula:ula_|video:video_|frame[3] @@ -5209,770 +5158,803 @@ Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.773 -Slack : 0.587 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.807 - -Slack : 0.702 +Slack : 0.562 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 0.922 +Data Delay : 0.782 -Slack : 0.804 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.076 -Data Delay : 1.037 - -Slack : 0.825 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.045 - -Slack : 0.877 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.095 - -Slack : 0.886 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.105 - -Slack : 0.897 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 0.790 - -Slack : 0.937 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.155 - -Slack : 0.976 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.196 - -Slack : 0.978 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.198 - -Slack : 1.003 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.221 - -Slack : 1.010 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.228 - -Slack : 1.014 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.232 - -Slack : 1.103 +Slack : 0.674 From Node : ula:ula_|video:video_|frame[4] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.323 +Data Delay : 0.894 -Slack : 1.108 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] +Slack : 0.776 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.000 +Clock Skew : 0.087 +Data Delay : 1.020 -Slack : 1.110 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] +Slack : 0.812 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.002 +Clock Skew : 0.063 +Data Delay : 1.032 -Slack : 1.115 -From Node : ula:ula_|video:video_|bits_prefetch[5] -To Node : ula:ula_|video:video_|bits[5] +Slack : 0.826 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.007 +Clock Skew : 0.063 +Data Delay : 1.046 -Slack : 1.141 +Slack : 0.828 From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] +To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.359 +Clock Skew : 0.087 +Data Delay : 1.072 -Slack : 1.148 +Slack : 0.828 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.366 +Clock Skew : 0.087 +Data Delay : 1.072 -Slack : 1.157 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.375 +Clock Skew : 0.087 +Data Delay : 1.073 -Slack : 1.175 -From Node : ula:ula_|video:video_|frame[0] +Slack : 0.840 +From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.068 +Clock Skew : 0.063 +Data Delay : 1.060 -Slack : 1.177 -From Node : ula:ula_|video:video_|frame[0] +Slack : 0.842 +From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.070 - -Slack : 1.195 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.413 - -Slack : 1.203 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.422 - -Slack : 1.222 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.441 - -Slack : 1.229 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.448 - -Slack : 1.231 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.449 - -Slack : 1.232 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.450 - -Slack : 1.237 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.455 - -Slack : 1.239 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.458 - -Slack : 1.240 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.132 - -Slack : 1.256 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.475 - -Slack : 1.258 -From Node : ula:ula_|video:video_|bits_prefetch[7] -To Node : ula:ula_|video:video_|bits[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.150 - -Slack : 1.258 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.476 - -Slack : 1.258 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.477 - -Slack : 1.266 -From Node : ula:ula_|video:video_|attr_prefetch[6] -To Node : ula:ula_|video:video_|attr[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.130 - -Slack : 1.268 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.132 - -Slack : 1.270 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.134 - -Slack : 1.292 -From Node : ula:ula_|video:video_|attr_prefetch[1] -To Node : ula:ula_|video:video_|attr[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.156 - -Slack : 1.294 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.158 - -Slack : 1.294 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.513 - -Slack : 1.295 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.514 - -Slack : 1.304 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.168 - -Slack : 1.322 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.541 - -Slack : 1.324 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.543 - -Slack : 1.326 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.545 - -Slack : 1.332 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.551 - -Slack : 1.356 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.576 +Data Delay : 1.062 -Slack : 1.356 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.576 - -Slack : 1.364 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Slack : 0.856 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.582 +Data Delay : 1.074 -Slack : 1.368 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.587 - -Slack : 1.404 +Slack : 0.934 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.624 +Data Delay : 1.154 -Slack : 1.414 -From Node : ula:ula_|video:video_|bits_prefetch[3] -To Node : ula:ula_|video:video_|bits[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.306 - -Slack : 1.414 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.936 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.633 +Data Delay : 1.155 -Slack : 1.416 +Slack : 0.947 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.065 +Data Delay : 1.169 + +Slack : 0.995 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.087 +Data Delay : 1.239 + +Slack : 1.042 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.268 + +Slack : 1.046 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 1.272 + +Slack : 1.099 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.272 +Data Delay : 0.984 + +Slack : 1.134 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.636 +Data Delay : 1.354 -Slack : 1.416 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.154 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.635 +Data Delay : 1.373 -Slack : 1.431 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] +Slack : 1.166 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 1.295 +Clock Skew : 0.071 +Data Delay : 1.394 -Slack : 1.436 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.204 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.655 +Clock Skew : 0.087 +Data Delay : 1.448 -Slack : 1.486 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] +Slack : 1.226 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.705 +Clock Skew : -0.244 +Data Delay : 1.139 -Slack : 1.496 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.228 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.715 +Clock Skew : -0.272 +Data Delay : 1.113 -Slack : 1.505 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.724 - -Slack : 1.511 +Slack : 1.230 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.731 +Data Delay : 1.450 -Slack : 1.518 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.237 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.737 +Clock Skew : 0.069 +Data Delay : 1.463 -Slack : 1.526 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.245 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.745 +Clock Skew : 0.070 +Data Delay : 1.472 -Slack : 1.532 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[7] +Slack : 1.246 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.752 +Data Delay : 1.466 -Slack : 1.533 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[8] +Slack : 1.276 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.753 +Clock Skew : 0.069 +Data Delay : 1.502 -Slack : 1.558 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.776 - -Slack : 1.562 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.782 - -Slack : 1.575 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 1.467 - -Slack : 1.582 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.800 - -Slack : 1.584 +Slack : 1.285 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.804 +Data Delay : 1.505 -Slack : 1.584 +Slack : 1.285 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.804 +Data Delay : 1.505 -Slack : 1.584 +Slack : 1.285 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.804 +Data Delay : 1.505 -Slack : 1.584 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.804 - -Slack : 1.584 +Slack : 1.285 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.804 +Data Delay : 1.505 -Slack : 1.588 +Slack : 1.288 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.508 + +Slack : 1.288 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.087 +Data Delay : 1.532 + +Slack : 1.324 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 1.551 + +Slack : 1.332 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.087 +Data Delay : 1.576 + +Slack : 1.343 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.087 +Data Delay : 1.587 + +Slack : 1.351 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.272 +Data Delay : 1.236 + +Slack : 1.360 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.578 + +Slack : 1.361 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 1.588 + +Slack : 1.368 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.244 +Data Delay : 1.281 + +Slack : 1.369 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 +Data Delay : 1.589 + +Slack : 1.373 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.591 + +Slack : 1.374 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.244 +Data Delay : 1.287 + +Slack : 1.380 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.605 + +Slack : 1.382 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.607 + +Slack : 1.420 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.639 + +Slack : 1.438 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.087 +Data Delay : 1.682 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.415 +Data Delay : 2.021 + +Slack : 1.454 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.272 +Data Delay : 1.339 + +Slack : 1.455 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.680 + +Slack : 1.543 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.763 + +Slack : 1.555 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.774 + +Slack : 1.562 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.782 + +Slack : 1.564 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.784 + +Slack : 1.564 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.789 + +Slack : 1.571 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.087 +Data Delay : 1.815 + +Slack : 1.580 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.798 + +Slack : 1.581 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.800 + +Slack : 1.587 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.805 + +Slack : 1.588 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 Data Delay : 1.808 -Slack : 1.596 -From Node : ula:ula_|video:video_|vga_vc[4] +Slack : 1.588 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.808 + +Slack : 1.588 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.808 + +Slack : 1.588 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.808 + +Slack : 1.588 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.808 + +Slack : 1.605 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.824 + +Slack : 1.615 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.834 + +Slack : 1.617 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.244 +Data Delay : 1.530 + +Slack : 1.620 +From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.815 +Clock Skew : 0.070 +Data Delay : 1.847 -Slack : 1.610 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[10] +Slack : 1.620 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 1.847 + +Slack : 1.620 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 1.847 + +Slack : 1.620 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 1.847 + +Slack : 1.639 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 1.864 + +Slack : 1.646 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.829 +Data Delay : 1.865 -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] +Slack : 1.654 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 +Clock Skew : 0.087 +Data Delay : 1.898 -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] +Slack : 1.675 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vga_hc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 +Clock Skew : 0.062 +Data Delay : 1.894 -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] +Slack : 1.683 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 +Clock Skew : 0.070 +Data Delay : 1.910 ++--------------------------------------------------------------------------------+ -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.357 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 +Clock Skew : 0.063 +Data Delay : 0.577 -Slack : 1.613 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.361 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 -Clock Skew : 0.435 -Data Delay : 2.205 +Clock Skew : 0.062 +Data Delay : 0.580 + +Slack : 0.779 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 1.003 +--------------------------------------------------------------------------------+ @@ -5980,36 +5962,36 @@ Data Delay : 2.205 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 0.359 -From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.577 - -Slack : 0.359 -From Node : sdram_controller:sdram_|r.wr_pending -To Node : sdram_controller:sdram_|r.wr_pending -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.577 - -Slack : 0.359 +Slack : 0.358 From Node : sdram_controller:sdram_|r.rd_pending To Node : sdram_controller:sdram_|r.rd_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.359 -From Node : sdram_controller:sdram_|r.state[8] -To Node : sdram_controller:sdram_|r.state[8] +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6034,27 +6016,9 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 0.580 -Slack : 0.379 -From Node : sdram_controller:sdram_|r.rf_counter[9] -To Node : sdram_controller:sdram_|r.rf_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.597 - -Slack : 0.521 -From Node : sdram_controller:sdram_|r.state[8] -To Node : sdram_controller:sdram_|r.state[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.739 - Slack : 0.557 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[3] +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6062,17 +6026,8 @@ Clock Skew : 0.061 Data Delay : 0.775 Slack : 0.558 -From Node : sdram_controller:sdram_|r.rf_counter[1] -To Node : sdram_controller:sdram_|r.rf_counter[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.776 - -Slack : 0.558 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[12] +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6080,17 +6035,8 @@ Clock Skew : 0.061 Data Delay : 0.776 Slack : 0.559 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.777 - -Slack : 0.559 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.init_counter[14] +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6098,31 +6044,40 @@ Clock Skew : 0.061 Data Delay : 0.777 Slack : 0.560 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[6] +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 Data Delay : 0.778 -Slack : 0.561 +Slack : 0.560 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.778 + +Slack : 0.562 From Node : sdram_controller:sdram_|r.rf_counter[2] To Node : sdram_controller:sdram_|r.rf_counter[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 0.779 +Data Delay : 0.780 -Slack : 0.561 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.init_counter[13] +Slack : 0.562 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 0.779 +Data Delay : 0.780 Slack : 0.562 From Node : sdram_controller:sdram_|r.rf_counter[7] @@ -6143,8 +6098,17 @@ Clock Skew : 0.061 Data Delay : 0.780 Slack : 0.563 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[4] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.781 + +Slack : 0.563 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6160,6 +6124,15 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 0.782 +Slack : 0.570 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.788 + Slack : 0.570 From Node : sdram_controller:sdram_|r.init_counter[2] To Node : sdram_controller:sdram_|r.init_counter[2] @@ -6170,8 +6143,8 @@ Clock Skew : 0.061 Data Delay : 0.788 Slack : 0.571 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[10] +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6214,95 +6187,104 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 0.791 -Slack : 0.575 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.793 - -Slack : 0.580 -From Node : sdram_controller:sdram_|r.rf_counter[0] -To Node : sdram_controller:sdram_|r.rf_counter[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.798 - -Slack : 0.592 +Slack : 0.573 From Node : sdram_controller:sdram_|r.init_counter[1] To Node : sdram_controller:sdram_|r.init_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 0.810 +Data Delay : 0.791 -Slack : 0.594 +Slack : 0.574 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.792 + +Slack : 0.575 From Node : sdram_controller:sdram_|r.init_counter[7] To Node : sdram_controller:sdram_|r.init_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 0.812 +Data Delay : 0.793 -Slack : 0.608 -From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[7] +Slack : 0.575 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 0.826 +Data Delay : 0.793 -Slack : 0.612 +Slack : 0.581 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.799 + +Slack : 0.593 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.812 + +Slack : 0.594 From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.state[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.830 +Clock Skew : 0.062 +Data Delay : 0.813 -Slack : 0.612 +Slack : 0.613 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.832 + +Slack : 0.617 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.836 + +Slack : 0.704 From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.830 - -Slack : 0.818 -From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.037 +Data Delay : 0.923 -Slack : 0.822 -From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.041 - -Slack : 0.829 -From Node : sdram_controller:sdram_|r.state[7] -To Node : sdram_controller:sdram_|r.state[7] +Slack : 0.814 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.047 +Data Delay : 1.032 Slack : 0.832 From Node : sdram_controller:sdram_|r.rf_counter[1] @@ -6313,23 +6295,14 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.050 -Slack : 0.832 +Slack : 0.834 From Node : sdram_controller:sdram_|r.rf_counter[3] To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.050 - -Slack : 0.833 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.051 +Data Delay : 1.052 Slack : 0.834 From Node : sdram_controller:sdram_|r.init_counter[11] @@ -6340,14 +6313,23 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.052 -Slack : 0.834 +Slack : 0.835 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.053 + +Slack : 0.836 From Node : sdram_controller:sdram_|r.rf_counter[5] To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.052 +Data Delay : 1.054 Slack : 0.836 From Node : sdram_controller:sdram_|r.rf_counter[7] @@ -6358,6 +6340,24 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.054 +Slack : 0.845 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.063 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.064 + Slack : 0.846 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[6] @@ -6368,8 +6368,8 @@ Clock Skew : 0.061 Data Delay : 1.064 Slack : 0.847 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[10] +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6377,71 +6377,62 @@ Clock Skew : 0.061 Data Delay : 1.065 Slack : 0.847 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.848 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.065 - -Slack : 0.847 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[13] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.065 - -Slack : 0.848 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[3] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 Data Delay : 1.066 Slack : 0.848 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.066 - -Slack : 0.849 -From Node : sdram_controller:sdram_|r.rf_counter[0] -To Node : sdram_controller:sdram_|r.rf_counter[2] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.067 - -Slack : 0.849 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.067 - -Slack : 0.850 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.068 +Data Delay : 1.066 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 Slack : 0.850 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[4] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6449,8 +6440,17 @@ Clock Skew : 0.061 Data Delay : 1.068 Slack : 0.850 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[8] +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6466,23 +6466,41 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.069 +Slack : 0.851 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.069 + Slack : 0.852 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[6] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.070 -Slack : 0.860 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[11] +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.078 +Data Delay : 1.077 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.077 Slack : 0.860 From Node : sdram_controller:sdram_|r.init_counter[4] @@ -6493,6 +6511,15 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.078 +Slack : 0.861 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.079 + Slack : 0.861 From Node : sdram_controller:sdram_|r.init_counter[2] To Node : sdram_controller:sdram_|r.init_counter[4] @@ -6520,15 +6547,6 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.080 -Slack : 0.862 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.080 - Slack : 0.862 From Node : sdram_controller:sdram_|r.init_counter[4] To Node : sdram_controller:sdram_|r.init_counter[6] @@ -6539,8 +6557,8 @@ Clock Skew : 0.061 Data Delay : 1.080 Slack : 0.864 -From Node : sdram_controller:sdram_|r.init_counter[1] -To Node : sdram_controller:sdram_|r.init_counter[2] +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6556,50 +6574,23 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.082 -Slack : 0.864 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.init_counter[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.082 - -Slack : 0.866 -From Node : sdram_controller:sdram_|r.init_counter[7] -To Node : sdram_controller:sdram_|r.init_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.084 - -Slack : 0.894 +Slack : 0.879 From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.112 +Clock Skew : 0.062 +Data Delay : 1.098 -Slack : 0.909 -From Node : sdram_controller:sdram_|r.rf_counter[9] -To Node : sdram_controller:sdram_|r.rf_pending -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.127 - -Slack : 0.909 +Slack : 0.886 From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.127 +Clock Skew : 0.062 +Data Delay : 1.105 Slack : 0.942 From Node : sdram_controller:sdram_|r.rf_counter[1] @@ -6610,31 +6601,13 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.160 -Slack : 0.942 +Slack : 0.944 From Node : sdram_controller:sdram_|r.rf_counter[3] To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.160 - -Slack : 0.944 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[13] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.162 - -Slack : 0.944 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 Data Delay : 1.162 Slack : 0.944 @@ -6647,17 +6620,26 @@ Clock Skew : 0.061 Data Delay : 1.162 Slack : 0.944 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[6] +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.162 +Slack : 0.945 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.163 + Slack : 0.946 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[14] +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6665,8 +6647,8 @@ Clock Skew : 0.061 Data Delay : 1.164 Slack : 0.946 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[8] +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6682,6 +6664,51 @@ Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.164 +Slack : 0.946 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.164 + +Slack : 0.947 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.165 + +Slack : 0.948 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.166 + +Slack : 0.955 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.173 + +Slack : 0.956 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.174 + Slack : 0.956 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[7] @@ -6692,8 +6719,26 @@ Clock Skew : 0.061 Data Delay : 1.174 Slack : 0.957 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[11] +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.175 + +Slack : 0.957 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.175 + +Slack : 0.957 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6710,8 +6755,8 @@ Clock Skew : 0.061 Data Delay : 1.176 Slack : 0.959 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[12] +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6719,8 +6764,17 @@ Clock Skew : 0.061 Data Delay : 1.177 Slack : 0.959 -From Node : sdram_controller:sdram_|r.rf_counter[0] -To Node : sdram_controller:sdram_|r.rf_counter[3] +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.177 + +Slack : 0.959 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6728,8 +6782,8 @@ Clock Skew : 0.061 Data Delay : 1.177 Slack : 0.960 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[5] +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6737,8 +6791,8 @@ Clock Skew : 0.061 Data Delay : 1.178 Slack : 0.960 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[9] +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6746,8 +6800,17 @@ Clock Skew : 0.061 Data Delay : 1.178 Slack : 0.961 -From Node : sdram_controller:sdram_|r.rf_counter[0] -To Node : sdram_controller:sdram_|r.rf_counter[4] +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.179 + +Slack : 0.961 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6755,8 +6818,8 @@ Clock Skew : 0.061 Data Delay : 1.179 Slack : 0.962 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[7] +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -6764,31 +6827,31 @@ Clock Skew : 0.061 Data Delay : 1.180 Slack : 0.962 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[6] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.180 -Slack : 0.964 +Slack : 0.962 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 -Data Delay : 1.182 +Data Delay : 1.180 -Slack : 0.970 -From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 -To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Slack : 0.963 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.189 +Clock Skew : 0.061 +Data Delay : 1.181 Slack : 0.971 From Node : sdram_controller:sdram_|r.init_counter[2] @@ -6798,87 +6861,6 @@ Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.061 Data Delay : 1.189 - -Slack : 0.972 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[13] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.190 - -Slack : 0.972 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.init_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.190 - -Slack : 0.973 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.init_counter[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.191 - -Slack : 0.974 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.192 - -Slack : 0.974 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.192 - -Slack : 0.974 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.init_counter[11] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.192 - -Slack : 0.974 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.init_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.192 - -Slack : 0.976 -From Node : sdram_controller:sdram_|r.init_counter[1] -To Node : sdram_controller:sdram_|r.init_counter[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.194 - -Slack : 0.976 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.init_counter[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.194 +--------------------------------------------------------------------------------+ @@ -6886,905 +6868,905 @@ Data Delay : 1.194 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.373 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Slack : 0.382 +From Node : debouncer:debounce_autofire|r_State +To Node : debouncer:debounce_autofire|r_State +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.577 + +Slack : 0.382 +From Node : debouncer:debounce_turbo|r_State +To Node : debouncer:debounce_turbo|r_State +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.577 + +Slack : 0.391 +From Node : debouncer:debounce_turbo|r_Count[20] +To Node : debouncer:debounce_turbo|r_Count[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.592 +Data Delay : 0.610 + +Slack : 0.391 +From Node : debouncer:debounce_autofire|r_Count[20] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.610 + +Slack : 0.559 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.778 + +Slack : 0.559 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.778 + +Slack : 0.560 +From Node : debouncer:debounce_turbo|r_Count[1] +To Node : debouncer:debounce_turbo|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.779 + +Slack : 0.560 +From Node : debouncer:debounce_turbo|r_Count[3] +To Node : debouncer:debounce_turbo|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.779 + +Slack : 0.560 +From Node : debouncer:debounce_autofire|r_Count[3] +To Node : debouncer:debounce_autofire|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.778 + +Slack : 0.560 +From Node : debouncer:debounce_autofire|r_Count[19] +To Node : debouncer:debounce_autofire|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.779 + +Slack : 0.561 +From Node : debouncer:debounce_turbo|r_Count[19] +To Node : debouncer:debounce_turbo|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : debouncer:debounce_turbo|r_Count[17] +To Node : debouncer:debounce_turbo|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : debouncer:debounce_autofire|r_Count[1] +To Node : debouncer:debounce_autofire|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.779 + +Slack : 0.561 +From Node : debouncer:debounce_autofire|r_Count[17] +To Node : debouncer:debounce_autofire|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.562 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.781 + +Slack : 0.562 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.781 + +Slack : 0.562 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.780 + +Slack : 0.563 +From Node : debouncer:debounce_turbo|r_Count[13] +To Node : debouncer:debounce_turbo|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.782 + +Slack : 0.563 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.781 + +Slack : 0.563 +From Node : debouncer:debounce_autofire|r_Count[13] +To Node : debouncer:debounce_autofire|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.782 + +Slack : 0.563 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.782 + +Slack : 0.565 +From Node : debouncer:debounce_turbo|r_Count[9] +To Node : debouncer:debounce_turbo|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.784 + +Slack : 0.565 +From Node : debouncer:debounce_turbo|r_Count[15] +To Node : debouncer:debounce_turbo|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.784 + +Slack : 0.565 +From Node : debouncer:debounce_autofire|r_Count[15] +To Node : debouncer:debounce_autofire|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.784 + +Slack : 0.565 +From Node : debouncer:debounce_autofire|r_Count[5] +To Node : debouncer:debounce_autofire|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.783 + +Slack : 0.565 +From Node : debouncer:debounce_autofire|r_Count[7] +To Node : debouncer:debounce_autofire|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.783 + +Slack : 0.565 +From Node : debouncer:debounce_autofire|r_Count[9] +To Node : debouncer:debounce_autofire|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.783 + +Slack : 0.567 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.786 + +Slack : 0.568 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.787 + +Slack : 0.568 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.786 + +Slack : 0.568 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.787 + +Slack : 0.569 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.788 + +Slack : 0.569 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.787 + +Slack : 0.569 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.788 + +Slack : 0.572 +From Node : debouncer:debounce_turbo|r_Count[10] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.572 +From Node : debouncer:debounce_autofire|r_Count[10] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.576 +From Node : debouncer:debounce_turbo|r_Count[7] +To Node : debouncer:debounce_turbo|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.795 Slack : 0.577 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.637 -Data Delay : 3.505 - -Slack : 0.605 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.640 -Data Delay : 3.536 - -Slack : 0.812 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.636 -Data Delay : 3.739 - -Slack : 0.837 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.637 -Data Delay : 3.765 - -Slack : 1.263 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.357 -Data Delay : 3.911 - -Slack : 1.267 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.643 -Data Delay : 4.201 - -Slack : 1.304 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.648 -Data Delay : 4.243 - -Slack : 1.329 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.181 - -Slack : 1.335 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.645 -Data Delay : 4.271 - -Slack : 1.345 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.654 -Data Delay : 4.290 - -Slack : 1.345 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.641 -Data Delay : 4.277 - -Slack : 1.346 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.348 -Data Delay : 3.985 - -Slack : 1.356 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.646 -Data Delay : 4.293 - -Slack : 1.359 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.348 -Data Delay : 3.998 - -Slack : 1.360 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.208 - -Slack : 1.372 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.643 -Data Delay : 4.306 - -Slack : 1.378 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.351 -Data Delay : 4.020 - -Slack : 1.379 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.641 -Data Delay : 4.311 - -Slack : 1.381 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.645 -Data Delay : 4.317 - -Slack : 1.385 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.237 - -Slack : 1.402 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.646 -Data Delay : 4.339 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.573 -Data Delay : 4.269 - -Slack : 1.407 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.363 -Data Delay : 4.061 - -Slack : 1.409 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.648 -Data Delay : 4.348 - -Slack : 1.411 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.636 -Data Delay : 4.338 - -Slack : 1.413 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.361 -Data Delay : 4.065 - -Slack : 1.415 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 4.276 - -Slack : 1.415 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.356 -Data Delay : 4.062 - -Slack : 1.421 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.276 - -Slack : 1.423 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.271 - -Slack : 1.426 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 4.287 - -Slack : 1.428 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.632 -Data Delay : 4.351 - -Slack : 1.428 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.364 -Data Delay : 4.083 - -Slack : 1.429 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 4.279 - -Slack : 1.429 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.352 -Data Delay : 4.072 - -Slack : 1.431 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.556 -Data Delay : 4.278 - -Slack : 1.433 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 4.294 - -Slack : 1.434 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.362 -Data Delay : 4.087 - -Slack : 1.436 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.637 -Data Delay : 4.364 - -Slack : 1.438 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.573 -Data Delay : 4.302 - -Slack : 1.438 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.286 - -Slack : 1.442 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.339 -Data Delay : 4.072 - -Slack : 1.443 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.573 -Data Delay : 4.307 - -Slack : 1.443 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.298 - -Slack : 1.444 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.548 -Data Delay : 4.283 - -Slack : 1.447 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.570 -Data Delay : 4.308 - -Slack : 1.448 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.292 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.298 - -Slack : 1.450 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.353 -Data Delay : 4.094 - -Slack : 1.453 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.552 -Data Delay : 4.296 - -Slack : 1.457 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.573 -Data Delay : 4.321 - -Slack : 1.458 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 4.308 - -Slack : 1.459 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.314 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.312 - -Slack : 1.462 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.315 - -Slack : 1.462 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.632 -Data Delay : 4.385 - -Slack : 1.463 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.315 - -Slack : 1.464 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.319 - -Slack : 1.465 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.654 -Data Delay : 4.410 - -Slack : 1.468 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.645 -Data Delay : 4.404 - -Slack : 1.474 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.318 - -Slack : 1.477 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.634 -Data Delay : 4.402 - -Slack : 1.477 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.548 -Data Delay : 4.316 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.334 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.320 - -Slack : 1.487 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 4.337 - -Slack : 1.489 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.344 - -Slack : 1.494 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.548 -Data Delay : 4.333 - -Slack : 1.497 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.341 -Data Delay : 4.129 - -Slack : 1.500 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.352 - -Slack : 1.504 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.356 - -Slack : 1.506 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.573 -Data Delay : 4.370 - -Slack : 1.508 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.361 - -Slack : 1.508 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.354 -Data Delay : 4.153 - -Slack : 1.510 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.362 - -Slack : 1.510 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.354 - -Slack : 1.513 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.368 - -Slack : 1.513 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.552 -Data Delay : 4.356 - -Slack : 1.518 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.362 - -Slack : 1.519 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 4.369 - -Slack : 1.519 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.363 - -Slack : 1.519 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.360 - -Slack : 1.520 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.643 -Data Delay : 4.454 - -Slack : 1.521 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.351 -Data Delay : 4.163 - -Slack : 1.523 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.559 -Data Delay : 4.373 - -Slack : 1.523 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.367 - -Slack : 1.523 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.352 -Data Delay : 4.166 - -Slack : 1.524 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.548 -Data Delay : 4.363 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.373 - -Slack : 1.526 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.548 -Data Delay : 4.365 - -Slack : 1.527 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.379 - -Slack : 1.527 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.371 - -Slack : 1.527 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.564 -Data Delay : 4.382 - -Slack : 1.527 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.379 - -Slack : 1.529 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.556 -Data Delay : 4.376 - -Slack : 1.530 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.371 - -Slack : 1.531 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.377 -Data Delay : 4.199 - -Slack : 1.534 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.556 -Data Delay : 4.381 - -Slack : 1.534 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.375 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.796 + +Slack : 0.577 +From Node : debouncer:debounce_turbo|r_Count[5] +To Node : debouncer:debounce_turbo|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.796 + +Slack : 0.577 +From Node : debouncer:debounce_turbo|r_Count[11] +To Node : debouncer:debounce_turbo|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.796 + +Slack : 0.577 +From Node : debouncer:debounce_autofire|r_Count[11] +To Node : debouncer:debounce_autofire|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.796 + +Slack : 0.577 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.795 + +Slack : 0.580 +From Node : debouncer:debounce_turbo|r_Count[6] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.799 + +Slack : 0.834 +From Node : debouncer:debounce_turbo|r_Count[1] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.053 + +Slack : 0.834 +From Node : debouncer:debounce_turbo|r_Count[3] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.053 + +Slack : 0.834 +From Node : debouncer:debounce_autofire|r_Count[19] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.053 + +Slack : 0.834 +From Node : debouncer:debounce_autofire|r_Count[3] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.052 + +Slack : 0.835 +From Node : debouncer:debounce_turbo|r_Count[19] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.054 + +Slack : 0.835 +From Node : debouncer:debounce_turbo|r_Count[17] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.054 + +Slack : 0.835 +From Node : debouncer:debounce_autofire|r_Count[1] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.053 + +Slack : 0.835 +From Node : debouncer:debounce_autofire|r_Count[17] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.054 + +Slack : 0.838 +From Node : debouncer:debounce_turbo|r_Count[13] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.057 + +Slack : 0.838 +From Node : debouncer:debounce_autofire|r_Count[13] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.057 + +Slack : 0.840 +From Node : debouncer:debounce_turbo|r_Count[15] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.059 + +Slack : 0.840 +From Node : debouncer:debounce_autofire|r_Count[15] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.059 + +Slack : 0.840 +From Node : debouncer:debounce_autofire|r_Count[5] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.058 + +Slack : 0.840 +From Node : debouncer:debounce_autofire|r_Count[7] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.058 + +Slack : 0.840 +From Node : debouncer:debounce_autofire|r_Count[9] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.058 + +Slack : 0.843 +From Node : debouncer:debounce_turbo|r_Count[9] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.059 + +Slack : 0.847 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.066 + +Slack : 0.847 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.066 + +Slack : 0.847 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.847 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.066 + +Slack : 0.848 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.067 + +Slack : 0.849 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.849 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.849 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.849 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.849 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.849 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.849 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.850 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.069 + +Slack : 0.850 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.850 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.069 + +Slack : 0.851 +From Node : debouncer:debounce_turbo|r_Count[7] +To Node : debouncer:debounce_turbo|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.070 + +Slack : 0.851 +From Node : debouncer:debounce_turbo|r_Count[11] +To Node : debouncer:debounce_turbo|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.070 + +Slack : 0.851 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.070 + +Slack : 0.851 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.070 + +Slack : 0.851 +From Node : debouncer:debounce_autofire|r_Count[11] +To Node : debouncer:debounce_autofire|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.070 + +Slack : 0.851 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.069 + +Slack : 0.852 +From Node : debouncer:debounce_turbo|r_Count[5] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.071 + +Slack : 0.852 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.071 + +Slack : 0.852 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.070 + +Slack : 0.854 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.073 + +Slack : 0.855 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.074 + +Slack : 0.855 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.074 + +Slack : 0.855 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.073 + +Slack : 0.856 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.075 + +Slack : 0.856 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.075 + +Slack : 0.856 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.074 + +Slack : 0.857 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.076 + +Slack : 0.857 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.076 + +Slack : 0.857 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.075 + +Slack : 0.858 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.077 + +Slack : 0.858 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.077 + +Slack : 0.858 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.076 + +Slack : 0.859 +From Node : debouncer:debounce_turbo|r_Count[10] +To Node : debouncer:debounce_turbo|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.078 + +Slack : 0.859 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.059 +Data Delay : 1.075 + +Slack : 0.859 +From Node : debouncer:debounce_autofire|r_Count[10] +To Node : debouncer:debounce_autofire|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.078 +--------------------------------------------------------------------------------+ @@ -7792,743 +7774,743 @@ Data Delay : 4.375 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -6.212 +Slack : -6.210 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 4.333 +Data Delay : 4.331 -Slack : -6.212 +Slack : -6.210 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 4.331 +Data Delay : 4.329 -Slack : -6.212 +Slack : -6.210 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.330 +Data Delay : 4.328 -Slack : -6.212 +Slack : -6.210 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.165 -Data Delay : 4.329 +Data Delay : 4.327 -Slack : -6.211 +Slack : -6.209 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.329 +Data Delay : 4.327 -Slack : -5.960 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.195 -Data Delay : 4.049 - -Slack : -5.959 +Slack : -5.969 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.193 -Data Delay : 4.050 +Data Delay : 4.060 -Slack : -5.696 +Slack : -5.958 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.195 +Data Delay : 4.047 + +Slack : -5.705 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.923 + +Slack : -5.705 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.912 +Clock Skew : -0.161 +Data Delay : 3.923 -Slack : -5.695 +Slack : -5.705 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.913 +Data Delay : 3.923 -Slack : -5.695 +Slack : -5.705 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.923 + +Slack : -5.705 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.923 + +Slack : -5.705 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.913 +Data Delay : 3.923 -Slack : -5.695 +Slack : -5.705 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.913 +Data Delay : 3.923 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 +Clock Skew : -0.176 +Data Delay : 3.907 -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 +Clock Skew : -0.176 +Data Delay : 3.907 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 +Clock Skew : -0.176 +Data Delay : 3.907 -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 +Clock Skew : -0.176 +Data Delay : 3.907 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 +Clock Skew : -0.176 +Data Delay : 3.907 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 +Clock Skew : -0.176 +Data Delay : 3.907 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.176 +Data Delay : 3.907 + +Slack : -5.704 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.176 +Data Delay : 3.907 + +Slack : -5.704 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.176 +Data Delay : 3.907 + +Slack : -5.704 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.176 +Data Delay : 3.907 + +Slack : -5.704 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.159 -Data Delay : 3.915 +Data Delay : 3.924 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.159 -Data Delay : 3.915 +Data Delay : 3.924 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 +Clock Skew : -0.159 +Data Delay : 3.924 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 +Clock Skew : -0.159 +Data Delay : 3.924 -Slack : -5.695 +Slack : -5.704 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 +Clock Skew : -0.159 +Data Delay : 3.924 -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.911 - -Slack : -5.695 +Slack : -5.694 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.911 +Data Delay : 3.910 -Slack : -5.695 +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.171 +Data Delay : 3.901 + +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.909 + +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.909 + +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.909 + +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.909 + +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.909 + +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.911 +Data Delay : 3.909 -Slack : -5.695 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.911 +Data Delay : 3.909 -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.913 - -Slack : -5.695 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 +Clock Skew : -0.171 +Data Delay : 3.901 -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.160 -Data Delay : 3.914 - -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.686 +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.171 +Data Delay : 3.901 + +Slack : -5.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.171 +Data Delay : 3.901 + +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 - -Slack : -5.686 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 - -Slack : -5.686 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.149 -Data Delay : 3.916 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 +Clock Skew : -0.161 Data Delay : 3.911 -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 -Data Delay : 3.911 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 -Data Delay : 3.911 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 -Data Delay : 3.911 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.912 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.912 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.912 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.912 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.912 - -Slack : -5.345 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.191 -Data Delay : 3.912 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.913 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.913 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.913 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.913 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.190 -Data Delay : 3.913 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 -Data Delay : 3.910 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 -Data Delay : 3.910 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.187 -Data Delay : 3.910 - -Slack : -5.344 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.186 -Data Delay : 3.909 - -Slack : -5.340 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.196 -Data Delay : 3.915 - -Slack : -5.338 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.199 -Data Delay : 3.916 - -Slack : -5.335 +Slack : -5.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.199 -Data Delay : 3.913 +Clock Skew : -0.161 +Data Delay : 3.911 -Slack : -5.320 +Slack : -5.374 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.169 +Data Delay : 3.922 + +Slack : -5.374 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.169 +Data Delay : 3.922 + +Slack : -5.374 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.169 +Data Delay : 3.922 + +Slack : -5.374 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.169 +Data Delay : 3.922 + +Slack : -5.374 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.169 +Data Delay : 3.922 + +Slack : -5.371 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.161 +Data Delay : 3.911 + +Slack : -5.353 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.177 +Data Delay : 3.909 + +Slack : -5.350 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.194 +Data Delay : 3.923 + +Slack : -5.350 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.194 +Data Delay : 3.923 + +Slack : -5.350 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.194 +Data Delay : 3.923 + +Slack : -5.343 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.212 -Data Delay : 3.911 +Clock Skew : 0.188 +Data Delay : 3.910 -Slack : -5.320 +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.912 + +Slack : -5.343 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.212 +Clock Skew : 0.190 +Data Delay : 3.912 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.912 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.912 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.912 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.912 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.909 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.909 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.909 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.909 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.909 + +Slack : -5.343 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.190 +Data Delay : 3.909 + +Slack : -5.342 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 Data Delay : 3.911 -Slack : -5.316 +Slack : -5.342 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.218 -Data Delay : 3.913 +Clock Skew : 0.190 +Data Delay : 3.911 -Slack : -5.316 +Slack : -5.342 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.218 -Data Delay : 3.913 +Clock Skew : 0.190 +Data Delay : 3.911 + +Slack : -5.342 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.178 +Data Delay : 3.899 +--------------------------------------------------------------------------------+ @@ -8536,68 +8518,14 @@ Data Delay : 3.913 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.666 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.638 -Data Delay : 3.545 - -Slack : 3.666 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.638 -Data Delay : 3.545 - -Slack : 3.668 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.632 -Data Delay : 3.541 - -Slack : 3.668 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.632 -Data Delay : 3.541 - -Slack : 3.684 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.543 - -Slack : 3.687 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.619 -Data Delay : 3.547 - Slack : 3.689 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.543 +Clock Skew : 0.609 +Data Delay : 3.542 Slack : 3.689 From Node : KEY[0] @@ -8605,8 +8533,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.543 +Clock Skew : 0.609 +Data Delay : 3.542 Slack : 3.689 From Node : KEY[0] @@ -8614,8 +8542,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.543 +Clock Skew : 0.609 +Data Delay : 3.542 Slack : 3.689 From Node : KEY[0] @@ -8623,8 +8551,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.543 +Clock Skew : 0.609 +Data Delay : 3.542 Slack : 3.689 From Node : KEY[0] @@ -8632,8 +8560,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.543 +Clock Skew : 0.609 +Data Delay : 3.542 Slack : 3.689 From Node : KEY[0] @@ -8641,17 +8569,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.610 -Data Delay : 3.543 - -Slack : 3.690 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.615 -Data Delay : 3.546 +Clock Skew : 0.609 +Data Delay : 3.542 Slack : 3.693 From Node : KEY[0] @@ -8659,8 +8578,26 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.540 +Clock Skew : 0.609 +Data Delay : 3.543 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.543 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.543 Slack : 3.693 From Node : KEY[0] @@ -8668,8 +8605,35 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.540 +Clock Skew : 0.609 +Data Delay : 3.543 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.543 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.543 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.543 Slack : 3.693 From Node : KEY[0] @@ -8677,372 +8641,264 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.540 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 Clock Skew : 0.609 -Data Delay : 3.544 +Data Delay : 3.543 -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.544 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.544 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.544 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.609 -Data Delay : 3.544 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.541 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.541 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.541 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.541 - -Slack : 3.694 +Slack : 3.693 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.604 -Data Delay : 3.539 +Clock Skew : 0.609 +Data Delay : 3.543 -Slack : 4.050 +Slack : 3.694 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 +Clock Skew : 0.607 +Data Delay : 3.542 -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.050 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 +Clock Skew : 0.597 +Data Delay : 3.533 -Slack : 4.050 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.256 -Data Delay : 3.547 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.059 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.244 -Data Delay : 3.544 - -Slack : 4.060 +Slack : 3.703 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 +Clock Skew : 0.613 +Data Delay : 3.557 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.613 +Data Delay : 3.557 + +Slack : 3.703 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.613 +Data Delay : 3.557 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.595 +Data Delay : 3.543 + +Slack : 3.723 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.579 +Data Delay : 3.543 + +Slack : 3.728 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.587 +Data Delay : 3.556 + +Slack : 3.728 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.587 +Data Delay : 3.556 + +Slack : 3.728 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.587 +Data Delay : 3.556 + +Slack : 3.728 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.587 +Data Delay : 3.556 + +Slack : 3.728 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.587 +Data Delay : 3.556 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 Slack : 4.060 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.233 +Data Delay : 3.534 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -9051,112 +8907,49 @@ Data Delay : 3.542 Slack : 4.060 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.242 Data Delay : 3.543 -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.245 -Data Delay : 3.546 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.245 -Data Delay : 3.546 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - -Slack : 4.060 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.542 - Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] @@ -9175,50 +8968,230 @@ Relationship : -0.006 Clock Skew : 0.241 Data Delay : 3.542 -Slack : 4.061 +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.233 +Data Delay : 3.534 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.233 +Data Delay : 3.534 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.233 +Data Delay : 3.534 + +Slack : 4.071 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.557 + +Slack : 4.071 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.557 + +Slack : 4.071 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.557 + +Slack : 4.071 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.557 + +Slack : 4.071 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.557 + +Slack : 4.072 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.545 +Data Delay : 3.556 -Slack : 4.061 +Slack : 4.072 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.556 + +Slack : 4.072 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.556 + +Slack : 4.072 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.545 +Data Delay : 3.556 -Slack : 4.061 +Slack : 4.072 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.545 +Data Delay : 3.556 -Slack : 4.061 +Slack : 4.073 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.228 +Data Delay : 3.542 + +Slack : 4.073 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.545 +Data Delay : 3.557 -Slack : 4.280 +Slack : 4.073 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.192 -Data Delay : 3.657 +Clock Skew : 0.243 +Data Delay : 3.557 Slack : 4.280 From Node : KEY[0] @@ -9229,6 +9202,15 @@ Relationship : -0.006 Clock Skew : 0.190 Data Delay : 3.655 +Slack : 4.292 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.192 +Data Delay : 3.669 + Slack : 4.505 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r @@ -9320,6 +9302,54 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.act_row[4] +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + Slack : 4.752 Actual Width : 4.968 Required Width : 0.216 @@ -9376,6 +9406,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[2] +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + Slack : 4.752 Actual Width : 4.968 Required Width : 0.216 @@ -9472,14 +9510,6 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 -Slack : 4.753 -Actual Width : 4.969 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[3] - Slack : 4.753 Actual Width : 4.969 Required Width : 0.216 @@ -9584,78 +9614,6 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.wr_pending -Slack : 4.755 -Actual Width : 4.971 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[0] - -Slack : 4.758 -Actual Width : 4.974 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 - -Slack : 4.758 -Actual Width : 4.974 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 - -Slack : 4.759 -Actual Width : 4.975 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 - -Slack : 4.759 -Actual Width : 4.975 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 - -Slack : 4.759 -Actual Width : 4.975 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 - -Slack : 4.830 -Actual Width : 4.985 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[1] - -Slack : 4.830 -Actual Width : 4.985 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[2] - -Slack : 4.833 -Actual Width : 4.988 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11] - Slack : 4.836 Actual Width : 4.991 Required Width : 0.155 @@ -9672,6 +9630,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.address[10] +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + Slack : 4.836 Actual Width : 4.991 Required Width : 0.155 @@ -9728,6 +9694,22 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.state[0] +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + Slack : 4.837 Actual Width : 4.992 Required Width : 0.155 @@ -9792,70 +9774,6 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.dq_masks[1] -Slack : 4.840 -Actual Width : 5.024 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 - -Slack : 4.840 -Actual Width : 5.024 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 - -Slack : 4.840 -Actual Width : 5.024 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 - -Slack : 4.840 -Actual Width : 5.024 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 - -Slack : 4.840 -Actual Width : 5.024 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 - -Slack : 4.843 -Actual Width : 5.027 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[0] - -Slack : 4.845 -Actual Width : 5.029 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.rd_pending - -Slack : 4.845 -Actual Width : 5.029 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.wr_pending - Slack : 4.846 Actual Width : 5.030 Required Width : 0.184 @@ -9902,7 +9820,15 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] Slack : 4.846 Actual Width : 5.030 @@ -9960,6 +9886,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[2] +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + Slack : 4.846 Actual Width : 5.030 Required Width : 0.184 @@ -10079,6 +10013,54 @@ Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +--------------------------------------------------------------------------------+ @@ -10092,7 +10074,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.488 Actual Width : 9.718 @@ -10100,7 +10082,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : 9.488 Actual Width : 9.718 @@ -10108,7 +10090,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg Slack : 9.488 Actual Width : 9.718 @@ -10116,72 +10098,48 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 -Slack : 9.488 -Actual Width : 9.718 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Slack : 9.488 -Actual Width : 9.718 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg - Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -10278,30 +10236,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg - Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -10332,7 +10266,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -10340,7 +10274,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 Slack : 9.489 Actual Width : 9.719 @@ -10348,31 +10282,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -10398,38 +10308,70 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -10454,6 +10396,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -10484,15 +10434,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -10502,13 +10444,21 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -Slack : 9.491 -Actual Width : 9.721 +Slack : 9.490 +Actual Width : 9.720 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -10516,7 +10466,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -10524,7 +10474,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -10532,7 +10482,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -10540,7 +10490,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -10548,7 +10498,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -10556,7 +10506,55 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -10580,32 +10578,24 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 - -Slack : 9.494 -Actual Width : 9.724 +Slack : 9.493 +Actual Width : 9.723 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 @@ -10638,6 +10628,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 @@ -10660,15 +10658,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : 9.494 Actual Width : 9.724 @@ -10678,13 +10668,21 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -Slack : 9.495 -Actual Width : 9.725 +Slack : 9.494 +Actual Width : 9.724 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 Slack : 9.495 Actual Width : 9.725 @@ -10708,23 +10706,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : 9.498 Actual Width : 9.728 @@ -10732,7 +10714,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 Slack : 9.498 Actual Width : 9.728 @@ -10740,24 +10722,24 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 - Slack : 9.499 Actual Width : 9.729 Required Width : 0.230 @@ -10774,6 +10756,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + Slack : 9.499 Actual Width : 9.729 Required Width : 0.230 @@ -10790,14 +10780,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 - Slack : 9.499 Actual Width : 9.729 Required Width : 0.230 @@ -10812,15 +10794,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 Slack : 9.499 Actual Width : 9.729 @@ -10836,7 +10810,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 Slack : 9.500 Actual Width : 9.730 @@ -10860,7 +10834,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 Slack : 9.500 Actual Width : 9.730 @@ -10870,21 +10844,29 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 -Slack : 9.500 -Actual Width : 9.730 +Slack : 9.501 +Actual Width : 9.731 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Slack : 9.500 -Actual Width : 9.730 +Slack : 9.501 +Actual Width : 9.731 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +--------------------------------------------------------------------------------+ @@ -10892,6 +10874,78 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg + Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -10916,54 +10970,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg - Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -10988,54 +10994,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg - Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -11060,6 +11018,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg + Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -11108,54 +11090,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg - Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -11180,30 +11114,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg - Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -11228,6 +11138,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -11276,6 +11210,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg + Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -11348,30 +11330,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg - Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -11402,7 +11360,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11410,7 +11368,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11418,7 +11376,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -11426,7 +11384,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11434,7 +11392,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11442,7 +11400,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -11468,6 +11426,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -11492,6 +11474,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -11546,7 +11552,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11554,7 +11560,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11562,7 +11568,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -11570,7 +11576,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11578,7 +11584,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11586,7 +11592,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -11594,7 +11600,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11602,7 +11608,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -11610,55 +11616,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg Slack : 19.603 Actual Width : 19.819 @@ -11666,7 +11624,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] +Target : ula:ula_|video:video_|bits_prefetch[0] Slack : 19.603 Actual Width : 19.819 @@ -11674,7 +11632,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] +Target : ula:ula_|video:video_|bits_prefetch[1] Slack : 19.603 Actual Width : 19.819 @@ -11682,7 +11640,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] +Target : ula:ula_|video:video_|bits_prefetch[2] Slack : 19.603 Actual Width : 19.819 @@ -11690,7 +11648,31 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] +Target : ula:ula_|video:video_|bits_prefetch[3] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[4] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[5] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[6] +--------------------------------------------------------------------------------+ @@ -11698,13 +11680,13 @@ Target : ula:ula_|video:video_|attr[5] +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 20.597 -Actual Width : 20.813 +Slack : 20.593 +Actual Width : 20.809 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Slack : 20.597 Actual Width : 20.813 @@ -11712,7 +11694,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Slack : 20.597 Actual Width : 20.813 @@ -11720,7 +11702,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Slack : 20.597 Actual Width : 20.813 @@ -11728,7 +11710,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Slack : 20.597 Actual Width : 20.813 @@ -11736,7 +11718,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Slack : 20.597 Actual Width : 20.813 @@ -11744,7 +11726,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Slack : 20.597 Actual Width : 20.813 @@ -11752,7 +11734,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Slack : 20.597 Actual Width : 20.813 @@ -11760,7 +11742,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Slack : 20.597 Actual Width : 20.813 @@ -11768,7 +11750,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Slack : 20.597 Actual Width : 20.813 @@ -11776,7 +11758,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Slack : 20.597 Actual Width : 20.813 @@ -11784,7 +11766,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Slack : 20.597 Actual Width : 20.813 @@ -11792,7 +11774,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Slack : 20.597 Actual Width : 20.813 @@ -11800,7 +11782,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Slack : 20.597 Actual Width : 20.813 @@ -11808,7 +11790,15 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.598 Actual Width : 20.814 @@ -11816,80 +11806,104 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Slack : 20.598 -Actual Width : 20.814 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] - Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -11928,7 +11942,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Slack : 20.599 Actual Width : 20.815 @@ -11936,7 +11950,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Slack : 20.599 Actual Width : 20.815 @@ -11944,7 +11958,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Data +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Slack : 20.599 Actual Width : 20.815 @@ -11952,7 +11966,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Slack : 20.599 Actual Width : 20.815 @@ -11960,7 +11974,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Slack : 20.599 Actual Width : 20.815 @@ -11968,175 +11982,135 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Start +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Slack : 20.601 -Actual Width : 20.817 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.601 -Actual Width : 20.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.601 -Actual Width : 20.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.601 -Actual Width : 20.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.601 -Actual Width : 20.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.604 -Actual Width : 20.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Slack : 20.605 Actual Width : 20.821 @@ -12144,224 +12118,216 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.605 +Actual Width : 20.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.605 +Actual Width : 20.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack - -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop - -Slack : 20.608 -Actual Width : 20.824 +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Slack : 20.608 -Actual Width : 20.824 +Slack : 20.606 +Actual Width : 20.822 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.606 +Actual Width : 20.822 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Slack : 20.608 -Actual Width : 20.824 +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Slack : 20.608 -Actual Width : 20.824 +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.609 -Actual Width : 20.825 +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.610 -Actual Width : 20.826 +Slack : 20.606 +Actual Width : 20.822 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.610 -Actual Width : 20.826 +Slack : 20.607 +Actual Width : 20.823 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.608 +Actual Width : 20.824 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.608 +Actual Width : 20.824 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Slack : 20.647 -Actual Width : 20.863 +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.650 +Actual Width : 20.834 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.650 +Actual Width : 20.834 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.650 +Actual Width : 20.834 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.650 +Actual Width : 20.834 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.650 +Actual Width : 20.834 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.650 +Actual Width : 20.834 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Slack : 20.690 -Actual Width : 20.874 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.690 -Actual Width : 20.874 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - Slack : 20.691 Actual Width : 20.846 Required Width : 0.155 @@ -12378,14 +12344,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out -Slack : 20.691 -Actual Width : 20.875 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -12410,6 +12368,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Slack : 20.692 +Actual Width : 20.876 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -12418,22 +12384,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop - Slack : 20.693 Actual Width : 20.848 Required Width : 0.155 @@ -12448,39 +12398,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Slack : 20.694 Actual Width : 20.878 @@ -12488,15 +12406,79 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.694 -Actual Width : 20.878 +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.695 +Actual Width : 20.879 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.695 +Actual Width : 20.879 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +--------------------------------------------------------------------------------+ @@ -12504,32 +12486,32 @@ Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : 35.503 -Actual Width : 35.719 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula:ula_|clocks:clocks_|clk_cpu - -Slack : 35.503 -Actual Width : 35.719 +Slack : 35.490 +Actual Width : 35.706 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula:ula_|clocks:clocks_|counter[0] -Slack : 35.584 -Actual Width : 35.768 +Slack : 35.491 +Actual Width : 35.707 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.597 +Actual Width : 35.781 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula:ula_|clocks:clocks_|clk_cpu -Slack : 35.584 -Actual Width : 35.768 +Slack : 35.597 +Actual Width : 35.781 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] @@ -12552,32 +12534,32 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk -Slack : 35.743 -Actual Width : 35.743 +Slack : 35.730 +Actual Width : 35.730 Required Width : 0.000 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|clocks_|clk_cpu|clk -Slack : 35.743 -Actual Width : 35.743 +Slack : 35.730 +Actual Width : 35.730 Required Width : 0.000 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|clocks_|counter[0]|clk -Slack : 35.746 -Actual Width : 35.746 +Slack : 35.758 +Actual Width : 35.758 Required Width : 0.000 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|clocks_|clk_cpu|clk -Slack : 35.746 -Actual Width : 35.746 +Slack : 35.759 +Actual Width : 35.759 Required Width : 0.000 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] @@ -12622,45 +12604,129 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : 1.548 -Fall : 1.931 +Rise : 2.982 +Fall : 3.302 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : 2.346 +Fall : 2.671 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : 2.083 +Fall : 2.452 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 2.910 +Fall : 3.266 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 2.982 +Fall : 3.302 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 2.249 +Fall : 2.595 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : 3.159 +Fall : 3.711 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.846 -Fall : 4.271 +Rise : 3.214 +Fall : 3.753 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : 3.437 +Fall : 4.028 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : 5.217 +Fall : 5.573 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : 1.010 -Fall : 1.278 +Rise : 4.464 +Fall : 4.789 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : 1.010 -Fall : 1.278 +Rise : 4.077 +Fall : 4.446 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 5.217 +Fall : 5.573 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 4.615 +Fall : 4.935 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 4.296 +Fall : 4.642 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 4.842 +Fall : 5.311 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.221 -Fall : 1.461 +Rise : 1.275 +Fall : 1.518 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.814 -Fall : 3.095 +Rise : 2.868 +Fall : 3.098 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -12670,45 +12736,129 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : -1.154 -Fall : -1.552 +Rise : -1.367 +Fall : -1.724 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : -1.480 +Fall : -1.794 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : -1.367 +Fall : -1.724 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -1.610 +Fall : -1.927 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -2.297 +Fall : -2.537 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -1.553 +Fall : -1.892 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : -1.675 +Fall : -2.234 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -2.539 -Fall : -2.918 +Rise : -2.655 +Fall : -3.175 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : -1.937 +Fall : -2.527 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : -2.942 +Fall : -3.255 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : -0.395 -Fall : -0.661 +Rise : -3.082 +Fall : -3.396 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : -0.395 -Fall : -0.661 +Rise : -3.216 +Fall : -3.573 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -2.942 +Fall : -3.255 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -3.369 +Fall : -3.649 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -3.039 +Fall : -3.374 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -3.799 +Fall : -4.258 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.602 -Fall : -0.833 +Rise : -0.657 +Fall : -0.891 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -1.346 -Fall : -1.585 +Rise : -0.973 +Fall : -1.211 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -12720,134 +12870,134 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 10.801 -Fall : 10.789 +Rise : 10.228 +Fall : 10.241 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 10.164 -Fall : 10.160 +Rise : 9.909 +Fall : 10.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 10.350 -Fall : 10.351 +Rise : 9.954 +Fall : 10.011 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 10.114 -Fall : 10.074 +Rise : 10.123 +Fall : 10.126 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 10.072 -Fall : 10.237 +Rise : 9.672 +Fall : 9.707 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 10.376 -Fall : 10.386 +Rise : 10.228 +Fall : 10.241 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 10.482 -Fall : 10.574 +Rise : 9.897 +Fall : 9.931 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 10.801 -Fall : 10.789 +Rise : 9.384 +Fall : 9.506 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 10.294 -Fall : 10.222 +Rise : 9.974 +Fall : 9.978 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 10.527 -Fall : 10.543 +Rise : 9.944 +Fall : 9.917 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 10.022 -Fall : 10.010 +Rise : 9.782 +Fall : 9.780 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 10.153 -Fall : 10.157 +Rise : 9.280 +Fall : 9.386 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 10.039 -Fall : 10.024 +Rise : 9.654 +Fall : 9.659 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 9.790 -Fall : 9.910 +Rise : 9.391 +Fall : 9.410 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 10.258 -Fall : 10.260 +Rise : 9.589 +Fall : 9.640 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 10.080 -Fall : 10.129 +Rise : 9.681 +Fall : 9.690 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 10.527 -Fall : 10.543 +Rise : 9.944 +Fall : 9.917 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 9.684 -Fall : 9.676 +Rise : 9.894 +Fall : 9.917 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_ADDR[*] Clock Port : CLOCK_50 -Rise : 3.430 -Fall : 3.345 +Rise : 3.425 +Fall : 3.340 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -12930,8 +13080,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 3.430 -Fall : 3.345 +Rise : 3.419 +Fall : 3.334 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -12965,127 +13115,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 3.426 -Fall : 3.341 +Rise : 3.417 +Fall : 3.332 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 6.248 -Fall : 6.300 +Rise : 6.004 +Fall : 6.086 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 5.552 -Fall : 5.647 +Rise : 5.305 +Fall : 5.354 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.839 -Fall : 5.898 +Rise : 5.578 +Fall : 5.696 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 5.545 -Fall : 5.576 +Rise : 5.445 +Fall : 5.512 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 5.269 -Fall : 5.330 +Rise : 5.941 +Fall : 6.086 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 5.626 -Fall : 5.683 +Rise : 5.645 +Fall : 5.775 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 5.718 -Fall : 5.830 +Rise : 6.004 +Fall : 6.051 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 5.584 -Fall : 5.653 +Rise : 4.996 +Fall : 5.088 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 5.733 -Fall : 5.777 +Rise : 5.954 +Fall : 6.010 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 6.248 -Fall : 6.299 +Rise : 5.903 +Fall : 5.918 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 6.038 -Fall : 6.073 +Rise : 5.870 +Fall : 5.876 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 6.021 -Fall : 6.053 +Rise : 5.883 +Fall : 5.889 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 6.021 -Fall : 6.053 +Rise : 5.883 +Fall : 5.889 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 6.215 -Fall : 6.300 +Rise : 5.873 +Fall : 5.891 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 6.241 -Fall : 6.286 +Rise : 5.904 +Fall : 5.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 6.241 -Fall : 6.286 +Rise : 5.904 +Fall : 5.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 5.859 -Fall : 5.918 +Rise : 5.941 +Fall : 5.965 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -13112,8 +13262,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 3.426 -Fall : 3.341 +Rise : 3.417 +Fall : 3.332 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -13140,197 +13290,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 8.525 -Fall : 8.506 +Rise : 8.091 +Fall : 8.109 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 7.614 -Fall : 7.674 +Rise : 7.500 +Fall : 7.498 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 7.796 -Fall : 7.806 +Rise : 7.943 +Fall : 8.029 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 8.092 -Fall : 8.080 +Rise : 8.038 +Fall : 8.056 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 7.910 -Fall : 8.021 +Rise : 7.578 +Fall : 7.658 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 8.495 -Fall : 8.500 +Rise : 8.091 +Fall : 8.109 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 8.018 -Fall : 8.084 +Rise : 7.839 +Fall : 7.890 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 8.525 -Fall : 8.506 +Rise : 7.255 +Fall : 7.347 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.947 -Fall : 7.936 +Rise : 7.712 +Fall : 7.706 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 8.377 -Fall : 8.374 +Rise : 7.632 +Fall : 7.649 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.472 -Fall : 7.524 +Rise : 7.222 +Fall : 7.219 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.599 -Fall : 7.612 +Rise : 7.315 +Fall : 7.384 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 8.017 -Fall : 8.030 +Rise : 7.565 +Fall : 7.591 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.628 -Fall : 7.694 +Rise : 7.471 +Fall : 7.581 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.377 -Fall : 8.374 +Rise : 7.421 +Fall : 7.433 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.619 -Fall : 7.643 +Rise : 7.623 +Fall : 7.649 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 8.251 -Fall : 8.260 +Rise : 7.465 +Fall : 7.500 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.224 -Fall : 7.248 +Rise : 7.632 +Fall : 7.645 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.645 -Fall : 8.352 +Rise : 8.550 +Fall : 8.202 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.645 -Fall : 8.352 +Rise : 8.550 +Fall : 8.202 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 7.356 -Fall : 7.355 +Rise : 6.928 +Fall : 6.937 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.643 -Fall : 6.643 +Rise : 6.512 +Fall : 6.445 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.647 -Fall : 6.639 +Rise : 6.524 +Fall : 6.454 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.988 -Fall : 6.893 +Rise : 7.146 +Fall : 7.041 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.282 -Fall : 6.183 +Rise : 6.553 +Fall : 6.432 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.690 -Fall : 6.712 +Rise : 6.279 +Fall : 6.217 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.988 -Fall : 6.893 +Rise : 7.146 +Fall : 7.041 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.988 -Fall : 6.893 +Rise : 7.146 +Fall : 7.041 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -13343,36 +13493,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 7.297 -Fall : 7.345 +Rise : 6.725 +Fall : 6.676 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.937 -Fall : 6.925 +Rise : 6.725 +Fall : 6.676 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 7.297 -Fall : 7.345 +Rise : 6.651 +Fall : 6.615 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.690 +Rise : 6.698 Fall : 6.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.641 -Fall : 6.567 +Rise : 6.230 +Fall : 6.171 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -13440,127 +13590,127 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 7.830 -Fall : 7.818 +Rise : 7.418 +Fall : 7.417 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 8.061 -Fall : 8.083 +Rise : 8.698 +Fall : 8.650 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 8.174 -Fall : 8.205 +Rise : 8.740 +Fall : 8.736 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 7.830 -Fall : 7.818 +Rise : 8.821 +Fall : 8.816 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 8.228 -Fall : 8.280 +Rise : 7.612 +Fall : 7.634 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 8.428 -Fall : 8.466 +Rise : 8.738 +Fall : 8.739 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 8.693 -Fall : 8.718 +Rise : 8.874 +Fall : 8.896 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 8.284 -Fall : 8.302 +Rise : 7.418 +Fall : 7.417 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 8.683 -Fall : 8.600 +Rise : 8.389 +Fall : 8.422 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.760 -Fall : 7.774 +Rise : 7.341 +Fall : 7.353 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.924 -Fall : 7.938 +Rise : 8.307 +Fall : 8.297 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.985 -Fall : 8.020 +Rise : 8.049 +Fall : 8.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.760 -Fall : 7.774 +Rise : 8.374 +Fall : 8.371 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.962 -Fall : 7.971 +Rise : 7.341 +Fall : 7.353 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.306 -Fall : 8.338 +Rise : 8.108 +Fall : 8.143 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 8.306 -Fall : 8.291 +Rise : 8.668 +Fall : 8.665 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 8.017 -Fall : 8.062 +Rise : 7.481 +Fall : 7.480 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 8.101 -Fall : 8.081 +Rise : 8.315 +Fall : 8.367 Clock Edge : Rise Clock Reference : CLOCK_50 @@ -13650,8 +13800,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 3.009 -Fall : 2.924 +Rise : 2.998 +Fall : 2.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -13685,127 +13835,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 3.006 -Fall : 2.921 +Rise : 2.996 +Fall : 2.911 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.562 -Fall : 4.614 +Rise : 4.438 +Fall : 4.524 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.973 -Fall : 5.061 +Rise : 4.691 +Fall : 4.745 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.248 -Fall : 5.301 +Rise : 4.949 +Fall : 5.047 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.963 -Fall : 4.991 +Rise : 4.820 +Fall : 4.867 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.700 -Fall : 4.753 +Rise : 5.294 +Fall : 5.421 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 5.044 -Fall : 5.095 +Rise : 5.013 +Fall : 5.123 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 5.134 -Fall : 5.235 +Rise : 5.406 +Fall : 5.449 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.945 -Fall : 5.002 +Rise : 4.438 +Fall : 4.524 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 5.145 -Fall : 5.183 +Rise : 5.293 +Fall : 5.342 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 4.931 -Fall : 4.977 +Rise : 4.880 +Fall : 4.891 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 4.730 -Fall : 4.760 +Rise : 4.848 +Fall : 4.850 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 4.713 -Fall : 4.741 +Rise : 4.860 +Fall : 4.863 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 4.713 -Fall : 4.741 +Rise : 4.860 +Fall : 4.863 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 4.900 -Fall : 4.977 +Rise : 4.850 +Fall : 4.865 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 4.924 -Fall : 4.965 +Rise : 4.880 +Fall : 4.886 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 4.924 -Fall : 4.965 +Rise : 4.880 +Fall : 4.886 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 4.562 -Fall : 4.614 +Rise : 4.919 +Fall : 4.939 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -13832,8 +13982,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 3.006 -Fall : 2.921 +Rise : 2.996 +Fall : 2.911 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -13860,197 +14010,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 6.189 -Fall : 6.209 +Rise : 6.436 +Fall : 6.455 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 6.676 -Fall : 6.693 +Rise : 6.457 +Fall : 6.534 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 6.674 -Fall : 6.676 +Rise : 6.813 +Fall : 6.750 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 7.005 -Fall : 6.988 +Rise : 7.010 +Fall : 7.107 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 6.630 -Fall : 6.784 +Rise : 6.622 +Fall : 6.673 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 6.357 -Fall : 6.415 +Rise : 7.079 +Fall : 7.091 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 6.848 -Fall : 6.958 +Rise : 6.774 +Fall : 6.865 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 6.189 -Fall : 6.209 +Rise : 6.436 +Fall : 6.455 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.027 -Fall : 7.015 +Rise : 6.759 +Fall : 6.790 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.922 -Fall : 5.969 +Rise : 5.164 +Fall : 5.193 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.539 -Fall : 6.548 +Rise : 6.115 +Fall : 6.099 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 6.485 -Fall : 6.491 +Rise : 5.874 +Fall : 5.919 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.935 -Fall : 6.944 +Rise : 6.560 +Fall : 6.663 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 6.364 -Fall : 6.475 +Rise : 5.164 +Fall : 5.193 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 6.235 -Fall : 6.287 +Rise : 6.430 +Fall : 6.437 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.464 -Fall : 6.535 +Rise : 6.568 +Fall : 6.634 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 5.922 -Fall : 5.969 +Rise : 5.515 +Fall : 5.513 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.372 -Fall : 6.397 +Rise : 6.685 +Fall : 6.735 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 4.408 -Fall : 4.397 +Rise : 4.248 +Fall : 4.209 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 6.411 -Fall : 6.112 +Rise : 6.286 +Fall : 5.965 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 4.636 -Fall : 4.572 +Rise : 4.306 +Fall : 4.277 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 4.408 -Fall : 4.401 +Rise : 4.248 +Fall : 4.209 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.413 -Fall : 4.397 +Rise : 4.260 +Fall : 4.217 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.788 -Fall : 3.713 +Rise : 3.998 +Fall : 3.874 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.811 -Fall : 3.715 +Rise : 4.353 +Fall : 4.239 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.788 -Fall : 3.713 +Rise : 3.998 +Fall : 3.874 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 4.488 -Fall : 4.397 +Rise : 4.923 +Fall : 4.823 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 4.488 -Fall : 4.397 +Rise : 4.923 +Fall : 4.823 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -14063,36 +14213,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 4.158 -Fall : 4.085 +Rise : 3.838 +Fall : 3.798 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.442 -Fall : 4.429 +Rise : 4.312 +Fall : 4.282 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.462 -Fall : 4.423 +Rise : 4.256 +Fall : 4.155 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 4.205 -Fall : 4.147 +Rise : 4.287 +Fall : 4.239 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 4.158 -Fall : 4.085 +Rise : 3.838 +Fall : 3.798 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -14160,38 +14310,136 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.629 +RR : 4.760 RF : FR : -FF : 4.693 +FF : 4.845 -Input Port : SW[2] -Output Port : LED[2] -RR : 4.045 -RF : -FR : -FF : 4.195 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 6.879 +RF : 6.888 +FR : 7.195 +FF : 7.213 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 6.687 +RF : 6.671 +FR : 7.003 +FF : 6.996 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 4.492 +FR : 4.693 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 7.200 +RF : 7.173 +FR : 7.560 +FF : 7.542 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 7.015 +RF : 6.950 +FR : 7.322 +FF : 7.358 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 4.319 +FR : 4.499 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 8.089 +RF : 8.112 +FR : 8.436 +FF : 8.468 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 6.945 +RF : 6.980 +FR : 7.315 +FF : 7.315 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 6.211 +FR : 6.117 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 7.927 +RF : 7.949 +FR : 8.239 +FF : 8.269 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 7.621 +RF : 7.586 +FR : 7.940 +FF : 7.914 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 4.174 +FR : 4.361 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 7.468 +RF : 7.451 +FR : 7.805 +FF : 7.797 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 7.041 +RF : 7.069 +FR : 7.371 +FF : 7.371 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 6.462 +FR : 7.117 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 6.893 +RR : 7.844 RF : FR : -FF : 7.253 +FF : 8.324 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 7.004 +RR : 6.881 RF : FR : -FF : 7.359 +FF : 7.298 Input Port : raw_loader_in -Output Port : LED[3] -RR : 4.487 +Output Port : LED[1] +RR : 5.229 RF : FR : -FF : 4.751 +FF : 5.518 +--------------------------------------------------------------------------------+ @@ -14201,38 +14449,136 @@ FF : 4.751 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.491 +RR : 4.617 RF : FR : -FF : 4.560 +FF : 4.706 -Input Port : SW[2] -Output Port : LED[2] -RR : 3.931 -RF : -FR : -FF : 4.082 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 6.643 +RF : 6.647 +FR : 6.957 +FF : 6.970 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 6.462 +RF : 6.443 +FR : 6.777 +FF : 6.767 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 4.352 +FR : 4.553 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 6.951 +RF : 6.921 +FR : 7.308 +FF : 7.287 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 6.777 +RF : 6.675 +FR : 7.034 +FF : 7.114 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 4.189 +FR : 4.370 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 7.617 +RF : 7.013 +FR : 7.365 +FF : 7.976 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 6.711 +RF : 6.740 +FR : 7.074 +FF : 7.073 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 6.081 +FR : 5.988 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 7.547 +RF : 7.445 +FR : 7.749 +FF : 7.858 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 7.360 +RF : 7.322 +FR : 7.677 +FF : 7.648 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 4.045 +FR : 4.232 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 7.212 +RF : 7.191 +FR : 7.547 +FF : 7.535 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 6.796 +RF : 6.734 +FR : 7.075 +FF : 7.121 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 6.308 +FR : 6.961 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 6.662 +RR : 7.572 RF : FR : -FF : 7.012 +FF : 8.037 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.765 +RR : 6.609 RF : FR : -FF : 7.110 +FF : 7.014 Input Port : raw_loader_in -Output Port : LED[3] -RR : 4.348 +Output Port : LED[1] +RR : 5.060 RF : FR : -FF : 4.609 +FF : 5.344 +--------------------------------------------------------------------------------+ @@ -14242,64 +14588,64 @@ FF : 4.609 +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 5.921 -Fall : 5.799 +Rise : 5.697 +Fall : 5.575 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 6.438 -Fall : 6.316 +Rise : 5.873 +Fall : 5.751 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 6.438 -Fall : 6.316 +Rise : 5.873 +Fall : 5.751 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 6.070 -Fall : 5.937 +Rise : 5.822 +Fall : 5.689 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 6.069 -Fall : 5.949 +Rise : 5.934 +Fall : 5.814 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 5.921 -Fall : 5.799 +Rise : 5.968 +Fall : 5.846 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 6.085 -Fall : 5.963 +Rise : 5.697 +Fall : 5.575 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 6.085 -Fall : 5.963 +Rise : 5.697 +Fall : 5.575 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 6.061 -Fall : 5.928 +Rise : 5.988 +Fall : 5.855 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -14311,64 +14657,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.617 -Fall : 4.495 +Rise : 4.681 +Fall : 4.559 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 5.113 -Fall : 4.991 +Rise : 4.851 +Fall : 4.729 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.113 -Fall : 4.991 +Rise : 4.851 +Fall : 4.729 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.732 -Fall : 4.599 +Rise : 4.774 +Fall : 4.641 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.754 -Fall : 4.634 +Rise : 4.904 +Fall : 4.784 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.617 -Fall : 4.495 +Rise : 4.942 +Fall : 4.820 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.775 -Fall : 4.653 +Rise : 4.681 +Fall : 4.559 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.775 -Fall : 4.653 +Rise : 4.681 +Fall : 4.559 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.723 -Fall : 4.590 +Rise : 4.933 +Fall : 4.800 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -14380,64 +14726,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -0 to Hi-Z : 5.820 -1 to Hi-Z : 5.942 +0 to Hi-Z : 5.619 +1 to Hi-Z : 5.741 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -0 to Hi-Z : 6.366 -1 to Hi-Z : 6.488 +0 to Hi-Z : 5.773 +1 to Hi-Z : 5.895 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -0 to Hi-Z : 6.366 -1 to Hi-Z : 6.488 +0 to Hi-Z : 5.773 +1 to Hi-Z : 5.895 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -0 to Hi-Z : 5.976 -1 to Hi-Z : 6.109 +0 to Hi-Z : 5.703 +1 to Hi-Z : 5.836 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -0 to Hi-Z : 6.042 -1 to Hi-Z : 6.162 +0 to Hi-Z : 5.921 +1 to Hi-Z : 6.041 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -0 to Hi-Z : 5.820 -1 to Hi-Z : 5.942 +0 to Hi-Z : 5.902 +1 to Hi-Z : 6.024 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -0 to Hi-Z : 5.919 -1 to Hi-Z : 6.041 +0 to Hi-Z : 5.619 +1 to Hi-Z : 5.741 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -0 to Hi-Z : 5.919 -1 to Hi-Z : 6.041 +0 to Hi-Z : 5.619 +1 to Hi-Z : 5.741 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -0 to Hi-Z : 5.948 -1 to Hi-Z : 6.081 +0 to Hi-Z : 5.942 +1 to Hi-Z : 6.075 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -14449,64 +14795,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -0 to Hi-Z : 4.523 -1 to Hi-Z : 4.645 +0 to Hi-Z : 4.609 +1 to Hi-Z : 4.731 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -0 to Hi-Z : 5.047 -1 to Hi-Z : 5.169 +0 to Hi-Z : 4.756 +1 to Hi-Z : 4.878 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -0 to Hi-Z : 5.047 -1 to Hi-Z : 5.169 +0 to Hi-Z : 4.756 +1 to Hi-Z : 4.878 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -0 to Hi-Z : 4.644 -1 to Hi-Z : 4.777 +0 to Hi-Z : 4.660 +1 to Hi-Z : 4.793 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -0 to Hi-Z : 4.731 -1 to Hi-Z : 4.851 +0 to Hi-Z : 4.893 +1 to Hi-Z : 5.013 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -0 to Hi-Z : 4.523 -1 to Hi-Z : 4.645 +0 to Hi-Z : 4.880 +1 to Hi-Z : 5.002 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -0 to Hi-Z : 4.617 -1 to Hi-Z : 4.739 +0 to Hi-Z : 4.609 +1 to Hi-Z : 4.731 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -0 to Hi-Z : 4.617 -1 to Hi-Z : 4.739 +0 to Hi-Z : 4.609 +1 to Hi-Z : 4.731 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -0 to Hi-Z : 4.617 -1 to Hi-Z : 4.750 +0 to Hi-Z : 4.890 +1 to Hi-Z : 5.023 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -14522,27 +14868,27 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 50.7 MHz -Restricted Fmax : 50.7 MHz +Fmax : 50.81 MHz +Restricted Fmax : 50.81 MHz Clock Name : CLOCK_50 Note : -Fmax : 132.1 MHz -Restricted Fmax : 132.1 MHz +Fmax : 141.8 MHz +Restricted Fmax : 141.8 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 170.88 MHz -Restricted Fmax : 170.88 MHz +Fmax : 165.32 MHz +Restricted Fmax : 165.32 MHz Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 180.38 MHz -Restricted Fmax : 180.38 MHz +Fmax : 190.88 MHz +Restricted Fmax : 190.88 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 1054.85 MHz +Fmax : 951.47 MHz Restricted Fmax : 500.0 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Note : limit due to minimum period restriction (tmin) @@ -14555,23 +14901,23 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -17.727 -End Point TNS : -781.205 +Slack : -17.646 +End Point TNS : -768.789 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -6.896 -End Point TNS : -255.894 +Slack : -6.953 +End Point TNS : -254.832 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.422 -End Point TNS : -38.759 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.786 -End Point TNS : -2.786 +Slack : -4.416 +End Point TNS : -39.535 Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Slack : 4.148 +Slack : 3.951 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 70.438 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -14580,12 +14926,8 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : 0.298 -End Point TNS : 0.000 - Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.298 +Slack : 0.300 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -14596,8 +14938,12 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Slack : 0.312 End Point TNS : 0.000 +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 0.312 +End Point TNS : 0.000 + Clock : CLOCK_50 -Slack : 0.339 +Slack : 0.333 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -14607,8 +14953,8 @@ End Point TNS : 0.000 ; Slow 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -5.735 -End Point TNS : -424.927 +Slack : -5.734 +End Point TNS : -425.150 +--------------------------------------------------------------------------------+ @@ -14617,7 +14963,7 @@ End Point TNS : -424.927 ; Slow 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.339 +Slack : 3.370 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -14631,19 +14977,19 @@ Slack : 4.748 End Point TNS : 0.000 Clock : CLOCK_50 -Slack : 9.489 +Slack : 9.488 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 19.596 +Slack : 19.598 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 20.591 +Slack : 20.589 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : 35.491 +Slack : 35.487 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -14652,905 +14998,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -17.727 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.520 - -Slack : -17.668 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.479 - -Slack : -17.643 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.436 - -Slack : -17.634 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.192 - -Slack : -17.631 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.504 -Data Delay : 7.201 - -Slack : -17.617 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.428 - -Slack : -17.598 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.391 - -Slack : -17.595 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.153 - -Slack : -17.581 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 7.145 - -Slack : -17.546 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.338 - -Slack : -17.546 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.357 - -Slack : -17.544 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.337 - -Slack : -17.540 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.332 - -Slack : -17.535 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.346 - -Slack : -17.533 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.325 - -Slack : -17.529 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.322 - -Slack : -17.521 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.314 - -Slack : -17.521 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.313 - -Slack : -17.513 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.071 - -Slack : -17.502 -From Node : ula:ula_|video:video_|frame[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.278 -Data Delay : 7.298 - -Slack : -17.481 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.274 - -Slack : -17.452 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.010 - -Slack : -17.448 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.259 - -Slack : -17.426 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.219 - -Slack : -17.414 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.972 - -Slack : -17.411 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.504 -Data Delay : 6.981 - -Slack : -17.406 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.198 - -Slack : -17.384 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.177 - -Slack : -17.380 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.939 - -Slack : -17.371 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.164 - -Slack : -17.363 -From Node : ula:ula_|video:video_|bits[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.156 - -Slack : -17.361 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 6.925 - -Slack : -17.361 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 6.925 - -Slack : -17.359 +Slack : -17.646 From Node : ula:ula_|video:video_|vga_vc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.152 +Clock Skew : -0.283 +Data Delay : 7.437 -Slack : -17.343 -From Node : ula:ula_|video:video_|bits[1] +Slack : -17.634 +From Node : ula:ula_|video:video_|vga_vc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.136 +Clock Skew : -0.283 +Data Delay : 7.425 -Slack : -17.326 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.137 - -Slack : -17.298 -From Node : ula:ula_|video:video_|vga_vc[5] +Slack : -17.578 +From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.091 +Clock Skew : -0.274 +Data Delay : 7.378 -Slack : -17.298 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] +Slack : -17.577 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.857 +Clock Skew : -0.274 +Data Delay : 7.377 -Slack : -17.289 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : DRAM_DQ[2] +Slack : -17.565 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.848 +Clock Skew : -0.274 +Data Delay : 7.365 -Slack : -17.281 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[2] +Slack : -17.539 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 7.092 +Clock Skew : -0.283 +Data Delay : 7.330 -Slack : -17.279 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] +Slack : -17.522 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 6.843 +Clock Skew : -0.283 +Data Delay : 7.313 -Slack : -17.279 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.512 -Data Delay : 6.841 - -Slack : -17.275 +Slack : -17.473 From Node : ula:ula_|video:video_|vga_vc[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 7.068 +Clock Skew : -0.283 +Data Delay : 7.264 -Slack : -17.236 +Slack : -17.427 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 7.218 + +Slack : -17.407 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 7.198 + +Slack : -17.401 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 7.192 + +Slack : -17.396 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 7.187 + +Slack : -17.363 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 7.163 + +Slack : -17.336 From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 7.028 +Clock Skew : -0.274 +Data Delay : 7.136 -Slack : -17.232 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.790 - -Slack : -17.227 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 6.783 - -Slack : -17.181 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.731 - -Slack : -17.178 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.737 - -Slack : -17.170 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] +Slack : -17.284 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.263 -Data Delay : 6.981 +Data Delay : 7.095 -Slack : -17.168 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] +Slack : -17.283 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.512 -Data Delay : 6.730 +Clock Skew : -0.283 +Data Delay : 7.074 -Slack : -17.162 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : DRAM_DQ[3] +Slack : -17.257 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.721 +Clock Skew : -0.510 +Data Delay : 6.821 -Slack : -17.152 +Slack : -17.241 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 7.032 + +Slack : -17.240 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.050 + +Slack : -17.219 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 7.029 + +Slack : -17.198 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.989 + +Slack : -17.197 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.748 + +Slack : -17.196 From Node : ula:ula_|video:video_|vga_hc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.282 -Data Delay : 6.944 +Clock Skew : -0.274 +Data Delay : 6.996 -Slack : -17.134 +Slack : -17.189 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.742 + +Slack : -17.173 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.725 + +Slack : -17.153 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.964 + +Slack : -17.145 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.936 + +Slack : -17.140 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.684 +Clock Skew : -0.508 +Data Delay : 6.706 -Slack : -17.131 +Slack : -17.126 From Node : ula:ula_|video:video_|bits[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 6.924 +Clock Skew : -0.283 +Data Delay : 6.917 -Slack : -17.128 +Slack : -17.124 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.915 + +Slack : -17.117 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.681 + +Slack : -17.110 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.901 + +Slack : -17.103 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.665 + +Slack : -17.095 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.886 + +Slack : -17.088 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.879 + +Slack : -17.068 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.859 + +Slack : -17.047 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.858 + +Slack : -17.045 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.274 +Data Delay : 6.845 + +Slack : -17.029 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.580 + +Slack : -17.015 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.825 + +Slack : -16.977 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.504 +Data Delay : 6.547 + +Slack : -16.972 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.763 + +Slack : -16.968 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.779 + +Slack : -16.952 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.763 + +Slack : -16.907 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.457 + +Slack : -16.877 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.427 + +Slack : -16.872 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.432 + +Slack : -16.856 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.667 + +Slack : -16.829 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.640 + +Slack : -16.825 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.524 -Data Delay : 6.678 +Data Delay : 6.375 -Slack : -17.124 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.935 - -Slack : -17.107 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 6.900 - -Slack : -17.106 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.521 -Data Delay : 6.659 - -Slack : -17.104 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.662 - -Slack : -17.077 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.635 - -Slack : -17.075 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 6.868 - -Slack : -17.075 -From Node : ula:ula_|video:video_|attr[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 6.868 - -Slack : -17.073 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 6.633 - -Slack : -17.054 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.865 - -Slack : -17.045 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.856 - -Slack : -17.023 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.573 - -Slack : -17.022 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.580 - -Slack : -17.014 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.825 - -Slack : -16.999 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.810 - -Slack : -16.991 +Slack : -16.814 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.549 +Clock Skew : -0.514 +Data Delay : 6.374 -Slack : -16.989 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : DRAM_DQ[2] +Slack : -16.814 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.605 + +Slack : -16.814 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.513 -Data Delay : 6.550 +Data Delay : 6.375 -Slack : -16.987 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.537 - -Slack : -16.979 +Slack : -16.807 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.790 +Clock Skew : -0.264 +Data Delay : 6.617 -Slack : -16.941 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.752 - -Slack : -16.938 +Slack : -16.806 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.263 -Data Delay : 6.749 +Data Delay : 6.617 -Slack : -16.920 +Slack : -16.801 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.611 + +Slack : -16.779 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.343 + +Slack : -16.755 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.305 + +Slack : -16.751 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.309 + +Slack : -16.749 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.305 + +Slack : -16.748 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.306 + +Slack : -16.741 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.551 + +Slack : -16.740 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.300 + +Slack : -16.732 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.543 + +Slack : -16.732 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.524 -Data Delay : 6.470 +Data Delay : 6.282 -Slack : -16.903 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[18] +Slack : -16.729 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.714 +Clock Skew : -0.524 +Data Delay : 6.279 -Slack : -16.878 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.439 - -Slack : -16.876 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.435 - -Slack : -16.854 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 6.410 - -Slack : -16.847 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : DRAM_DQ[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.405 - -Slack : -16.844 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.405 - -Slack : -16.832 +Slack : -16.727 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.383 +Clock Skew : -0.516 +Data Delay : 6.285 -Slack : -16.823 -From Node : ula:ula_|video:video_|bits[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.281 -Data Delay : 6.616 - -Slack : -16.817 +Slack : -16.722 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[0] +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.628 +Clock Skew : -0.264 +Data Delay : 6.532 -Slack : -16.814 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : DRAM_DQ[5] +Slack : -16.718 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.372 +Clock Skew : -0.513 +Data Delay : 6.279 -Slack : -16.809 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.367 - -Slack : -16.805 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.508 -Data Delay : 6.371 - -Slack : -16.794 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.344 - -Slack : -16.780 +Slack : -16.717 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 6.340 +Clock Skew : -0.515 +Data Delay : 6.276 -Slack : -16.748 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.559 - -Slack : -16.733 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.521 -Data Delay : 6.286 - -Slack : -16.722 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Slack : -16.716 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.533 +Clock Skew : -0.516 +Data Delay : 6.274 -Slack : -16.718 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] +Slack : -16.713 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.265 + +Slack : -16.705 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.515 + +Slack : -16.703 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 6.276 +Data Delay : 6.261 -Slack : -16.715 +Slack : -16.695 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.247 + +Slack : -16.689 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.500 + +Slack : -16.686 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.283 +Data Delay : 6.477 + +Slack : -16.675 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.486 + +Slack : -16.662 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.228 + +Slack : -16.659 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.209 + +Slack : -16.653 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.209 + +Slack : -16.645 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.455 + +Slack : -16.635 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.265 +Clock Skew : -0.513 +Data Delay : 6.196 -Slack : -16.713 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.524 - -Slack : -16.712 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.523 - -Slack : -16.705 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +Slack : -16.633 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 6.263 +Data Delay : 6.191 -Slack : -16.688 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] +Slack : -16.607 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.499 +Clock Skew : -0.516 +Data Delay : 6.165 -Slack : -16.672 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Slack : -16.605 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.163 + +Slack : -16.594 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.147 + +Slack : -16.589 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.263 -Data Delay : 6.483 +Clock Skew : -0.264 +Data Delay : 6.399 + +Slack : -16.583 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.393 + +Slack : -16.560 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.370 + +Slack : -16.544 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.102 + +Slack : -16.537 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.087 + +Slack : -16.534 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.093 + +Slack : -16.522 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.086 + +Slack : -16.514 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.064 + +Slack : -16.508 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.070 + +Slack : -16.505 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.063 + +Slack : -16.502 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.061 + +Slack : -16.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.504 +Data Delay : 6.069 + +Slack : -16.495 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 6.047 +--------------------------------------------------------------------------------+ @@ -15558,905 +15904,905 @@ Data Delay : 6.483 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -6.896 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Slack : -6.953 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.023 -Data Delay : 4.973 +Clock Skew : 0.193 +Data Delay : 5.246 -Slack : -6.891 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Slack : -6.701 +From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.017 -Data Delay : 4.974 +Clock Skew : 0.186 +Data Delay : 4.987 -Slack : -6.815 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Slack : -6.683 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.976 -Data Delay : 4.939 +Clock Skew : 0.184 +Data Delay : 4.967 -Slack : -6.810 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Slack : -6.671 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.940 +Clock Skew : 0.185 +Data Delay : 4.956 -Slack : -6.744 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Slack : -6.576 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.825 +Clock Skew : 0.184 +Data Delay : 4.860 -Slack : -6.718 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.025 -Data Delay : 4.793 - -Slack : -6.681 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.765 - -Slack : -6.673 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Slack : -6.431 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.008 -Data Delay : 4.765 +Data Delay : 4.523 -Slack : -6.636 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Slack : -6.424 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.019 +Clock Skew : 0.193 Data Delay : 4.717 -Slack : -6.634 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Slack : -6.392 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.999 -Data Delay : 4.735 +Clock Skew : 0.186 +Data Delay : 4.678 -Slack : -6.589 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.687 - -Slack : -6.588 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.676 - -Slack : -6.564 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.011 -Data Delay : 4.653 - -Slack : -6.561 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.025 -Data Delay : 4.636 - -Slack : -6.556 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.971 -Data Delay : 4.685 - -Slack : -6.555 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.021 -Data Delay : 4.634 - -Slack : -6.518 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.599 - -Slack : -6.511 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.607 - -Slack : -6.503 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -6.381 +From Node : kempston[3] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.015 -Data Delay : 4.588 - -Slack : -6.483 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.619 - -Slack : -6.444 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.581 - -Slack : -6.437 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.010 -Data Delay : 4.527 - -Slack : -6.417 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.504 - -Slack : -6.405 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.501 - -Slack : -6.399 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.966 -Data Delay : 4.533 - -Slack : -6.395 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.982 -Data Delay : 4.513 - -Slack : -6.389 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.024 -Data Delay : 4.465 - -Slack : -6.385 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.472 - -Slack : -6.378 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.017 -Data Delay : 4.461 +Clock Skew : 0.186 +Data Delay : 4.667 Slack : -6.374 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +From Node : kempston[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.022 -Data Delay : 4.452 +Clock Skew : 0.185 +Data Delay : 4.659 -Slack : -6.370 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.996 -Data Delay : 4.474 - -Slack : -6.359 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.440 - -Slack : -6.351 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.438 - -Slack : -6.342 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.429 - -Slack : -6.325 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.406 - -Slack : -6.323 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Slack : -6.368 +From Node : kempston[3] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.974 -Data Delay : 4.449 +Clock Skew : 0.186 +Data Delay : 4.654 -Slack : -6.315 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.010 -Data Delay : 4.405 - -Slack : -6.313 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.968 -Data Delay : 4.445 - -Slack : -6.307 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.968 -Data Delay : 4.439 - -Slack : -6.301 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.011 -Data Delay : 4.390 - -Slack : -6.289 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.967 -Data Delay : 4.422 - -Slack : -6.286 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.422 - -Slack : -6.282 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.368 - -Slack : -6.264 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.974 -Data Delay : 4.390 - -Slack : -6.256 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.020 -Data Delay : 4.336 - -Slack : -6.254 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.352 - -Slack : -6.253 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.015 -Data Delay : 4.338 - -Slack : -6.252 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.344 - -Slack : -6.252 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.015 -Data Delay : 4.337 - -Slack : -6.240 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.972 -Data Delay : 4.368 - -Slack : -6.229 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.316 - -Slack : -6.226 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.337 - -Slack : -6.220 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.356 - -Slack : -6.213 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.976 -Data Delay : 4.337 - -Slack : -6.198 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.011 -Data Delay : 4.287 - -Slack : -6.197 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.965 -Data Delay : 4.332 - -Slack : -6.192 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.755 -Data Delay : 4.537 - -Slack : -6.188 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.981 -Data Delay : 4.307 - -Slack : -6.180 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.960 -Data Delay : 4.320 - -Slack : -6.174 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 4.265 - -Slack : -6.170 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.258 - -Slack : -6.163 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.965 -Data Delay : 4.298 - -Slack : -6.155 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.010 -Data Delay : 4.245 - -Slack : -6.154 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.006 -Data Delay : 4.248 - -Slack : -6.154 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.981 -Data Delay : 4.273 - -Slack : -6.134 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.972 -Data Delay : 4.262 - -Slack : -6.129 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.018 -Data Delay : 4.211 - -Slack : -6.129 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.988 -Data Delay : 4.241 - -Slack : -6.128 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.223 - -Slack : -6.126 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.007 -Data Delay : 4.219 - -Slack : -6.124 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.212 - -Slack : -6.114 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.251 - -Slack : -6.112 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.199 - -Slack : -6.099 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.961 -Data Delay : 4.238 - -Slack : -6.098 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.979 -Data Delay : 4.219 - -Slack : -6.094 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.966 -Data Delay : 4.228 - -Slack : -6.093 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.973 -Data Delay : 4.220 - -Slack : -6.076 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.001 -Data Delay : 4.175 - -Slack : -6.072 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.979 -Data Delay : 4.193 - -Slack : -6.058 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 4.158 - -Slack : -6.049 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.955 -Data Delay : 4.194 - -Slack : -6.038 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.984 -Data Delay : 4.154 - -Slack : -6.027 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.113 - -Slack : -6.012 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.958 -Data Delay : 4.154 - -Slack : -6.002 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.973 -Data Delay : 4.129 - -Slack : -5.982 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 4.073 - -Slack : -5.975 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.982 -Data Delay : 4.093 - -Slack : -5.974 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.975 -Data Delay : 4.099 - -Slack : -5.966 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.976 -Data Delay : 4.090 - -Slack : -5.952 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.038 - -Slack : -5.951 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.087 - -Slack : -5.949 +Slack : -6.365 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.085 +Clock Skew : -1.985 +Data Delay : 4.480 -Slack : -5.945 +Slack : -6.342 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 4.460 + +Slack : -6.310 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.006 +Data Delay : 4.404 + +Slack : -6.307 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.981 +Data Delay : 4.426 + +Slack : -6.304 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 4.431 + +Slack : -6.278 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.186 +Data Delay : 4.564 + +Slack : -6.272 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 4.398 + +Slack : -6.271 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.980 +Data Delay : 4.391 + +Slack : -6.228 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.186 +Data Delay : 4.514 + +Slack : -6.213 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 4.299 + +Slack : -6.198 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.019 +Data Delay : 4.279 + +Slack : -6.196 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.020 +Data Delay : 4.276 + +Slack : -6.185 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 4.284 + +Slack : -6.180 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 4.272 + +Slack : -6.177 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.022 +Data Delay : 4.255 + +Slack : -6.166 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.282 + +Slack : -6.155 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 4.283 + +Slack : -6.153 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 4.252 + +Slack : -6.146 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 4.264 + +Slack : -6.143 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.233 + +Slack : -6.143 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.191 +Data Delay : 4.434 + +Slack : -6.132 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.228 + +Slack : -6.119 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.014 -Data Delay : 4.031 +Data Delay : 4.205 -Slack : -5.938 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Slack : -6.114 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.033 +Clock Skew : -2.013 +Data Delay : 4.201 -Slack : -5.936 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.960 -Data Delay : 4.076 - -Slack : -5.925 +Slack : -6.101 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.974 -Data Delay : 4.051 +Clock Skew : -1.964 +Data Delay : 4.237 -Slack : -5.903 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Slack : -6.098 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.017 +Data Delay : 4.181 + +Slack : -6.093 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.016 +Data Delay : 4.177 + +Slack : -6.081 +From Node : kempston[3] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.974 -Data Delay : 4.029 +Clock Skew : 0.186 +Data Delay : 4.367 -Slack : -5.892 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Slack : -6.067 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.001 -Data Delay : 3.991 +Clock Skew : -1.977 +Data Delay : 4.190 -Slack : -5.883 +Slack : -6.062 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.979 +Data Delay : 4.183 + +Slack : -6.062 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 4.186 + +Slack : -6.047 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 4.135 + +Slack : -6.045 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.961 -Data Delay : 4.022 +Clock Skew : -1.981 +Data Delay : 4.164 -Slack : -5.875 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Slack : -6.022 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 4.121 + +Slack : -6.019 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.983 +Data Delay : 4.136 + +Slack : -6.004 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.180 +Data Delay : 4.284 + +Slack : -5.999 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.998 +Data Delay : 4.101 + +Slack : -5.992 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.186 +Data Delay : 4.278 + +Slack : -5.978 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 4.066 + +Slack : -5.976 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.969 -Data Delay : 4.006 +Clock Skew : -1.744 +Data Delay : 4.332 + +Slack : -5.970 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.057 + +Slack : -5.963 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 +Data Delay : 4.048 + +Slack : -5.960 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.047 + +Slack : -5.960 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.095 + +Slack : -5.953 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.044 + +Slack : -5.952 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.184 +Data Delay : 4.236 + +Slack : -5.950 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 4.062 + +Slack : -5.935 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 +Data Delay : 4.020 + +Slack : -5.934 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.020 +Data Delay : 4.014 + +Slack : -5.934 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.996 +Data Delay : 4.038 + +Slack : -5.929 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.990 +Data Delay : 4.039 + +Slack : -5.926 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.174 +Data Delay : 4.200 + +Slack : -5.924 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.990 +Data Delay : 4.034 + +Slack : -5.922 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.009 + +Slack : -5.912 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 4.040 + +Slack : -5.910 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.971 +Data Delay : 4.039 + +Slack : -5.908 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.022 +Data Delay : 3.986 + +Slack : -5.905 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.041 + +Slack : -5.905 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 4.035 + +Slack : -5.898 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.033 + +Slack : -5.894 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.007 +Data Delay : 3.987 + +Slack : -5.892 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.028 + +Slack : -5.886 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 3.985 + +Slack : -5.881 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.192 +Data Delay : 4.173 + +Slack : -5.879 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 3.977 + +Slack : -5.873 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 3.972 + +Slack : -5.872 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 3.998 + +Slack : -5.871 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.983 +Data Delay : 3.988 + +Slack : -5.869 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.953 +Data Delay : 4.016 + +Slack : -5.866 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 3.984 + +Slack : -5.858 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 3.957 + +Slack : -5.847 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.179 +Data Delay : 4.126 + +Slack : -5.842 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.180 +Data Delay : 4.122 + +Slack : -5.838 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.011 +Data Delay : 3.927 + +Slack : -5.838 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.023 +Data Delay : 3.915 + +Slack : -5.838 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.755 +Data Delay : 4.183 + +Slack : -5.823 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 3.915 + +Slack : -5.795 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.006 +Data Delay : 3.889 + +Slack : -5.791 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.999 +Data Delay : 3.892 + +Slack : -5.774 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 3.892 + +Slack : -5.767 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.193 +Data Delay : 4.060 + +Slack : -5.754 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.971 +Data Delay : 3.883 + +Slack : -5.731 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.968 +Data Delay : 3.863 + +Slack : -5.722 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 3.810 + +Slack : -5.714 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 3.830 + +Slack : -5.707 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 3.813 + +Slack : -5.704 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 3.790 + +Slack : -5.698 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 3.784 + +Slack : -5.692 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 3.779 +--------------------------------------------------------------------------------+ @@ -16464,947 +16810,905 @@ Data Delay : 4.006 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.422 +Slack : -4.416 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 2.596 +Data Delay : 2.590 -Slack : -4.259 +Slack : -4.401 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.551 +Data Delay : 2.693 -Slack : -4.259 +Slack : -4.401 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.551 +Data Delay : 2.693 -Slack : -3.838 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.446 - -Slack : -3.838 +Slack : -3.992 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.446 +Clock Skew : 0.209 +Data Delay : 2.580 -Slack : -3.838 +Slack : -3.992 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.446 +Clock Skew : 0.209 +Data Delay : 2.580 -Slack : -3.838 +Slack : -3.992 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.446 +Clock Skew : 0.209 +Data Delay : 2.580 -Slack : -3.838 +Slack : -3.992 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 2.446 +Clock Skew : 0.209 +Data Delay : 2.580 -Slack : -3.705 +Slack : -3.992 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.209 +Data Delay : 2.580 + +Slack : -3.380 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 1.997 +Clock Skew : 0.232 +Data Delay : 1.991 -Slack : -2.924 +Slack : -2.977 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 1.538 +Clock Skew : 0.201 +Data Delay : 1.557 -Slack : 17.066 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.410 - -Slack : 17.078 +Slack : 17.325 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.398 +Clock Skew : -0.368 +Data Delay : 3.153 -Slack : 17.200 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 17.325 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.276 +Clock Skew : -0.368 +Data Delay : 3.153 -Slack : 17.223 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.258 - -Slack : 17.223 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.258 - -Slack : 17.235 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.246 - -Slack : 17.235 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.246 - -Slack : 17.246 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.230 - -Slack : 17.246 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.230 - -Slack : 17.246 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.230 - -Slack : 17.246 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.230 - -Slack : 17.246 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.230 - -Slack : 17.255 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.221 - -Slack : 17.255 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.221 - -Slack : 17.258 +Slack : 17.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.218 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.258 +Slack : 17.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.218 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.258 +Slack : 17.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.218 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.258 +Slack : 17.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.218 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.258 +Slack : 17.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.218 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.267 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Slack : 17.345 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.209 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.267 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 17.345 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.209 +Clock Skew : -0.369 +Data Delay : 3.132 -Slack : 17.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 17.345 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 3.132 + +Slack : 17.345 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 3.132 + +Slack : 17.345 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 3.132 + +Slack : 17.439 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.187 +Clock Skew : -0.368 +Data Delay : 3.039 -Slack : 17.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.124 - -Slack : 17.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.124 - -Slack : 17.380 +Slack : 17.459 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.096 +Clock Skew : -0.369 +Data Delay : 3.018 -Slack : 17.380 +Slack : 17.459 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.096 +Clock Skew : -0.369 +Data Delay : 3.018 -Slack : 17.380 +Slack : 17.459 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.096 +Clock Skew : -0.369 +Data Delay : 3.018 -Slack : 17.380 +Slack : 17.459 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.096 +Clock Skew : -0.369 +Data Delay : 3.018 -Slack : 17.380 +Slack : 17.459 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.096 +Clock Skew : -0.369 +Data Delay : 3.018 -Slack : 17.389 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 17.536 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.942 + +Slack : 17.552 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.087 +Clock Skew : -0.369 +Data Delay : 2.925 -Slack : 17.389 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 17.552 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.087 +Clock Skew : -0.369 +Data Delay : 2.925 -Slack : 17.446 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Slack : 17.552 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.035 +Clock Skew : -0.369 +Data Delay : 2.925 -Slack : 17.446 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 17.552 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 3.035 +Clock Skew : -0.369 +Data Delay : 2.925 -Slack : 17.469 +Slack : 17.556 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.007 +Clock Skew : -0.369 +Data Delay : 2.921 -Slack : 17.469 +Slack : 17.556 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.007 +Clock Skew : -0.369 +Data Delay : 2.921 -Slack : 17.469 +Slack : 17.556 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.007 +Clock Skew : -0.369 +Data Delay : 2.921 -Slack : 17.469 +Slack : 17.556 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.007 +Clock Skew : -0.369 +Data Delay : 2.921 -Slack : 17.469 +Slack : 17.556 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 3.007 - -Slack : 17.478 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.998 - -Slack : 17.478 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.998 - -Slack : 17.585 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.046 -Data Delay : 3.215 - -Slack : 17.597 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.046 -Data Delay : 3.203 - -Slack : 17.613 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 Clock Skew : -0.369 -Data Delay : 2.864 +Data Delay : 2.921 -Slack : 17.613 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.864 - -Slack : 17.625 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.852 - -Slack : 17.625 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.852 - -Slack : 17.658 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.818 - -Slack : 17.719 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.046 -Data Delay : 3.081 - -Slack : 17.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.730 - -Slack : 17.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.730 - -Slack : 17.752 +Slack : 17.572 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 +Clock Skew : -0.368 +Data Delay : 2.906 + +Slack : 17.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.885 + +Slack : 17.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.885 + +Slack : 17.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.885 + +Slack : 17.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.885 + +Slack : 17.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.885 + +Slack : 17.666 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.811 + +Slack : 17.666 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.811 + +Slack : 17.698 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.780 + +Slack : 17.698 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.780 + +Slack : 17.698 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.780 + +Slack : 17.698 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.780 + +Slack : 17.723 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.755 + +Slack : 17.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.734 + +Slack : 17.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.734 + +Slack : 17.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.734 + +Slack : 17.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.734 + +Slack : 17.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.734 + +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 Data Delay : 2.724 -Slack : 17.808 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.046 -Data Delay : 2.992 - -Slack : 17.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 2.666 +Clock Skew : -0.368 +Data Delay : 2.724 -Slack : 17.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 2.666 +Clock Skew : -0.368 +Data Delay : 2.724 -Slack : 17.836 +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.724 + +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.724 + +Slack : 17.754 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.724 + +Slack : 17.763 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.369 -Data Delay : 2.641 +Data Delay : 2.714 -Slack : 17.836 +Slack : 17.763 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.714 + +Slack : 17.799 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.678 + +Slack : 17.799 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.678 + +Slack : 17.812 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.666 + +Slack : 17.812 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.666 + +Slack : 17.868 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.610 + +Slack : 17.868 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.610 + +Slack : 17.868 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.610 + +Slack : 17.909 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.641 +Clock Skew : -0.368 +Data Delay : 2.569 -Slack : 17.838 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Slack : 17.909 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.638 +Clock Skew : -0.368 +Data Delay : 2.569 -Slack : 17.838 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.638 +Clock Skew : -0.072 +Data Delay : 2.864 -Slack : 17.838 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.638 +Clock Skew : -0.072 +Data Delay : 2.864 -Slack : 17.838 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.638 +Clock Skew : -0.072 +Data Delay : 2.864 -Slack : 17.838 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.638 +Clock Skew : -0.072 +Data Delay : 2.864 -Slack : 17.847 +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.072 +Data Delay : 2.864 + +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.072 +Data Delay : 2.864 + +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.072 +Data Delay : 2.864 + +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.072 +Data Delay : 2.864 + +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.072 +Data Delay : 2.864 + +Slack : 17.910 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.072 +Data Delay : 2.864 + +Slack : 17.945 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.533 + +Slack : 17.945 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.533 + +Slack : 17.950 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.629 +Clock Skew : -0.369 +Data Delay : 2.527 -Slack : 17.847 +Slack : 17.950 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.629 +Clock Skew : -0.369 +Data Delay : 2.527 -Slack : 17.894 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 17.965 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.582 +Clock Skew : -0.368 +Data Delay : 2.513 -Slack : 17.894 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Slack : 17.965 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.582 +Clock Skew : -0.368 +Data Delay : 2.513 -Slack : 17.894 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Slack : 17.965 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.582 +Clock Skew : -0.368 +Data Delay : 2.513 -Slack : 17.894 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.582 - -Slack : 17.906 +Slack : 17.983 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.570 +Clock Skew : -0.368 +Data Delay : 2.495 -Slack : 17.906 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.570 - -Slack : 17.906 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.570 - -Slack : 17.906 +Slack : 17.983 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.570 +Clock Skew : -0.368 +Data Delay : 2.495 -Slack : 17.909 +Slack : 17.983 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.495 + +Slack : 17.983 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.495 + +Slack : 18.001 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.368 +Data Delay : 2.477 + +Slack : 18.001 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 2.572 +Clock Skew : -0.368 +Data Delay : 2.477 -Slack : 17.909 +Slack : 18.001 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.365 -Data Delay : 2.572 +Clock Skew : -0.368 +Data Delay : 2.477 -Slack : 17.932 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.544 - -Slack : 17.932 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.544 - -Slack : 17.932 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.544 - -Slack : 17.932 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.544 - -Slack : 17.932 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.544 - -Slack : 17.941 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.535 - -Slack : 17.941 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.370 -Data Delay : 2.535 - -Slack : 17.949 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.844 - -Slack : 17.949 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.844 - -Slack : 17.949 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.844 - -Slack : 17.949 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.844 - -Slack : 17.949 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 18.024 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.844 +Clock Skew : -0.072 +Data Delay : 2.750 -Slack : 17.961 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.832 - -Slack : 17.961 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 18.024 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.832 +Clock Skew : -0.072 +Data Delay : 2.750 -Slack : 17.961 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 18.024 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.832 - -Slack : 17.961 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.832 - -Slack : 17.961 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.053 -Data Delay : 2.832 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; -+--------------------------------------------------------------------------------+ -Slack : -2.786 -From Node : SW[2] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.423 -Clock Skew : 0.254 -Data Delay : 1.418 - -Slack : 70.541 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.069 -Data Delay : 0.874 - -Slack : 70.832 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|counter[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.069 -Data Delay : 0.583 - -Slack : 70.832 -From Node : ula:ula_|clocks:clocks_|clk_cpu -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.069 -Data Delay : 0.583 +Clock Skew : -0.072 +Data Delay : 2.750 +--------------------------------------------------------------------------------+ @@ -17412,947 +17716,938 @@ Data Delay : 0.583 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 4.148 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.047 -Data Delay : 5.708 - -Slack : 4.171 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.047 -Data Delay : 5.685 - -Slack : 4.243 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.047 -Data Delay : 5.613 - -Slack : 4.282 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.564 - -Slack : 4.293 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.047 -Data Delay : 5.563 - -Slack : 4.315 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.531 - -Slack : 4.332 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.047 -Data Delay : 5.524 - -Slack : 4.335 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.511 - -Slack : 4.351 +Slack : 3.951 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.497 +Clock Skew : -0.046 +Data Delay : 5.906 -Slack : 4.384 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.464 - -Slack : 4.404 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.444 - -Slack : 4.444 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.402 - -Slack : 4.446 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.400 - -Slack : 4.446 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.400 - -Slack : 4.463 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.383 - -Slack : 4.513 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.335 - -Slack : 4.515 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.333 - -Slack : 4.515 +Slack : 4.102 From Node : sdram_controller:sdram_|r.init_counter[11] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.333 +Clock Skew : -0.046 +Data Delay : 5.755 -Slack : 4.532 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.316 - -Slack : 4.541 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.305 - -Slack : 4.571 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.274 - -Slack : 4.595 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.251 - -Slack : 4.610 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.238 - -Slack : 4.617 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.232 - -Slack : 4.628 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.217 - -Slack : 4.650 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.199 - -Slack : 4.661 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.192 - -Slack : 4.662 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.186 - -Slack : 4.664 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.056 -Data Delay : 5.183 - -Slack : 4.664 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.181 - -Slack : 4.670 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.179 - -Slack : 4.679 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.174 - -Slack : 4.684 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.169 - -Slack : 4.690 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 5.140 - -Slack : 4.691 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 5.155 - -Slack : 4.701 -From Node : sdram_controller:sdram_|r.state[4] +Slack : 4.191 +From Node : sdram_controller:sdram_|r.state[5] To Node : sdram_controller:sdram_|r.address[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.152 +Clock Skew : -0.073 +Data Delay : 5.639 -Slack : 4.712 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.141 - -Slack : 4.721 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.124 - -Slack : 4.723 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 5.107 - -Slack : 4.727 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.068 -Data Delay : 5.110 - -Slack : 4.728 -From Node : sdram_controller:sdram_|r.wr_pending -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.045 -Data Delay : 5.130 - -Slack : 4.733 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.116 - -Slack : 4.743 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 5.087 - -Slack : 4.753 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.060 -Data Delay : 5.092 - -Slack : 4.756 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 5.092 - -Slack : 4.772 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.081 - -Slack : 4.772 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.077 - -Slack : 4.780 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.069 - -Slack : 4.781 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.068 - -Slack : 4.783 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.070 - -Slack : 4.784 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.068 -Data Delay : 5.053 - -Slack : 4.798 +Slack : 4.234 From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[4] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 5.051 +Clock Skew : -0.046 +Data Delay : 5.623 -Slack : 4.806 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.047 - -Slack : 4.820 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.068 -Data Delay : 5.017 - -Slack : 4.822 -From Node : sdram_controller:sdram_|r.rd_pending -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.045 -Data Delay : 5.036 - -Slack : 4.825 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 5.030 - -Slack : 4.829 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.024 - -Slack : 4.848 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 5.007 - -Slack : 4.850 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.980 - -Slack : 4.852 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 5.001 - -Slack : 4.854 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.976 - -Slack : 4.854 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.976 - -Slack : 4.858 +Slack : 4.246 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.965 +Clock Skew : -0.073 +Data Delay : 5.586 -Slack : 4.861 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[5] +Slack : 4.252 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 4.992 +Clock Skew : -0.046 +Data Delay : 5.605 -Slack : 4.871 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.959 - -Slack : 4.871 -From Node : sdram_controller:sdram_|r.init_counter[6] +Slack : 4.305 +From Node : sdram_controller:sdram_|r.init_counter[13] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.952 +Clock Skew : -0.073 +Data Delay : 5.527 -Slack : 4.873 +Slack : 4.348 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.509 + +Slack : 4.352 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.468 + +Slack : 4.355 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.473 + +Slack : 4.372 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.460 + +Slack : 4.376 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.456 + +Slack : 4.381 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.449 + +Slack : 4.382 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.446 + +Slack : 4.412 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.445 + +Slack : 4.440 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.390 + +Slack : 4.443 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.385 + +Slack : 4.461 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.396 + +Slack : 4.469 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.363 + +Slack : 4.471 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.076 +Data Delay : 5.356 + +Slack : 4.472 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.364 + +Slack : 4.498 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.338 + +Slack : 4.505 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.327 + +Slack : 4.509 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.346 + +Slack : 4.512 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 5.342 + +Slack : 4.522 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.310 + +Slack : 4.526 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.326 + +Slack : 4.528 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.302 + +Slack : 4.535 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.320 + +Slack : 4.549 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.308 + +Slack : 4.551 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.277 + +Slack : 4.552 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.300 + +Slack : 4.554 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.303 + +Slack : 4.558 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.278 + +Slack : 4.569 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 5.250 + +Slack : 4.570 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 5.259 + +Slack : 4.572 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 5.282 + +Slack : 4.580 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.256 + +Slack : 4.583 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.274 + +Slack : 4.585 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.247 + +Slack : 4.595 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.260 + +Slack : 4.600 From Node : sdram_controller:sdram_|r.init_counter[9] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.950 +Clock Skew : -0.073 +Data Delay : 5.232 -Slack : 4.876 -From Node : sdram_controller:sdram_|r.init_counter[10] +Slack : 4.612 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.240 + +Slack : 4.617 +From Node : sdram_controller:sdram_|r.act_row[2] To Node : sdram_controller:sdram_|r.address[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 4.973 +Clock Skew : -0.048 +Data Delay : 5.238 -Slack : 4.877 +Slack : 4.618 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 5.236 + +Slack : 4.634 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.218 + +Slack : 4.636 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.194 + +Slack : 4.647 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.210 + +Slack : 4.653 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.183 + +Slack : 4.660 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 5.194 + +Slack : 4.663 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.169 + +Slack : 4.668 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.187 + +Slack : 4.713 From Node : sdram_controller:sdram_|r.act_row[1] To Node : sdram_controller:sdram_|r.address[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.068 -Data Delay : 4.960 +Clock Skew : -0.069 +Data Delay : 5.123 -Slack : 4.888 +Slack : 4.713 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.117 + +Slack : 4.718 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.112 + +Slack : 4.726 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.131 + +Slack : 4.746 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.086 + +Slack : 4.749 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 5.108 + +Slack : 4.759 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.077 + +Slack : 4.765 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.090 + +Slack : 4.771 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.061 + +Slack : 4.778 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.052 + +Slack : 4.787 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.033 + +Slack : 4.801 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.019 + +Slack : 4.811 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 5.019 + +Slack : 4.815 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 5.021 + +Slack : 4.840 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 4.990 + +Slack : 4.860 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.072 +Data Delay : 4.971 + +Slack : 4.861 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 4.968 + +Slack : 4.865 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.066 +Data Delay : 4.974 + +Slack : 4.870 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 4.985 + +Slack : 4.871 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 4.986 + +Slack : 4.872 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.045 +Data Delay : 4.986 + +Slack : 4.875 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.073 +Data Delay : 4.957 + +Slack : 4.902 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.066 +Data Delay : 4.937 + +Slack : 4.904 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 4.949 + +Slack : 4.911 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.076 +Data Delay : 4.916 + +Slack : 4.933 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.895 + +Slack : 4.935 +From Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 4.917 + +Slack : 4.937 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 4.900 + +Slack : 4.943 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.066 +Data Delay : 4.896 + +Slack : 4.966 From Node : sdram_controller:sdram_|r.state[4] To Node : sdram_controller:sdram_|r.address[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 4.962 +Clock Skew : -0.076 +Data Delay : 4.861 -Slack : 4.892 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[3] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.051 -Data Delay : 4.960 - -Slack : 4.892 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.051 -Data Delay : 4.960 - -Slack : 4.909 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.068 -Data Delay : 4.928 - -Slack : 4.913 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 4.936 - -Slack : 4.925 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.898 - -Slack : 4.933 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.890 - -Slack : 4.947 +Slack : 4.972 From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 4.908 - -Slack : 4.949 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.881 - -Slack : 4.953 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.046 -Data Delay : 4.904 - -Slack : 4.961 -From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[2] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 4.886 - -Slack : 4.970 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 4.885 - -Slack : 4.991 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.839 - -Slack : 4.994 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.829 - -Slack : 4.999 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.053 -Data Delay : 4.851 - -Slack : 5.007 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.058 -Data Delay : 4.840 - -Slack : 5.007 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 4.842 - -Slack : 5.015 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.808 - -Slack : 5.016 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 4.839 - -Slack : 5.034 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.062 -Data Delay : 4.809 - -Slack : 5.059 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[5] +To Node : sdram_controller:sdram_|r.address[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.052 -Data Delay : 4.792 +Data Delay : 4.879 -Slack : 5.066 +Slack : 4.976 From Node : sdram_controller:sdram_|r.state[4] To Node : sdram_controller:sdram_|r.address[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.063 -Data Delay : 4.776 +Clock Skew : -0.086 +Data Delay : 4.843 -Slack : 5.066 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.757 - -Slack : 5.072 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.074 -Data Delay : 4.759 - -Slack : 5.083 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.057 -Data Delay : 4.763 - -Slack : 5.085 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.075 -Data Delay : 4.745 - -Slack : 5.087 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.082 -Data Delay : 4.736 - -Slack : 5.106 +Slack : 4.976 From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 4.844 + +Slack : 4.977 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 4.880 + +Slack : 4.978 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.069 +Data Delay : 4.858 + +Slack : 4.982 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.062 +Data Delay : 4.861 + +Slack : 4.982 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 4.862 + +Slack : 4.985 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 4.835 + +Slack : 4.986 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.049 -Data Delay : 4.748 +Data Delay : 4.868 -Slack : 5.118 -From Node : sdram_controller:sdram_|r.state[6] +Slack : 4.986 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 4.834 + +Slack : 4.986 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.086 +Data Delay : 4.833 + +Slack : 4.992 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.088 +Data Delay : 4.825 + +Slack : 4.998 +From Node : sdram_controller:sdram_|r.init_counter[11] To Node : sdram_controller:sdram_|r.address[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.045 -Data Delay : 4.740 +Data Delay : 4.860 -Slack : 5.126 -From Node : sdram_controller:sdram_|r.rd_pending -To Node : sdram_controller:sdram_|r.state[4] +Slack : 4.998 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.dq_masks[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.050 -Data Delay : 4.819 +Clock Skew : -0.076 +Data Delay : 4.829 -Slack : 5.139 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.state[4] +Slack : 4.998 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.dq_masks[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.059 -Data Delay : 4.797 +Clock Skew : -0.076 +Data Delay : 4.829 + +Slack : 5.015 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 4.840 + +Slack : 5.016 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.066 +Data Delay : 4.823 + +Slack : 5.016 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 4.813 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : 0.298 -From Node : ula:ula_|clocks:clocks_|clk_cpu +Slack : 70.438 +From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.511 +Relationship : 71.489 +Clock Skew : -0.049 +Data Delay : 0.997 -Slack : 0.306 +Slack : 70.846 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|counter[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.519 +Relationship : 71.489 +Clock Skew : -0.055 +Data Delay : 0.583 -Slack : 0.517 -From Node : ula:ula_|clocks:clocks_|counter[0] +Slack : 70.846 +From Node : ula:ula_|clocks:clocks_|clk_cpu To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.730 - -Slack : 1.246 -From Node : SW[2] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : -0.017 -Clock Skew : 0.626 -Data Delay : 1.089 +Relationship : 71.489 +Clock Skew : -0.055 +Data Delay : 0.583 +--------------------------------------------------------------------------------+ @@ -18360,51 +18655,15 @@ Data Delay : 1.089 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.298 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.511 - -Slack : 0.298 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.511 - -Slack : 0.299 +Slack : 0.300 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 +Clock Skew : 0.067 Data Delay : 0.511 -Slack : 0.306 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.519 - -Slack : 0.306 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.519 - Slack : 0.306 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] @@ -18414,36 +18673,18 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.519 -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 +Clock Skew : 0.068 +Data Delay : 0.519 Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -18469,8 +18710,26 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -18487,8 +18746,53 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -18504,6 +18808,24 @@ Relationship : 0.000 Clock Skew : 0.056 Data Delay : 0.519 +Slack : 0.320 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + +Slack : 0.320 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + Slack : 0.320 From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] @@ -18513,158 +18835,230 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.519 -Slack : 0.323 +Slack : 0.322 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.536 - -Slack : 0.337 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.537 +Data Delay : 0.535 Slack : 0.338 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.538 - -Slack : 0.338 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.538 - -Slack : 0.338 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.538 - -Slack : 0.339 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.539 - -Slack : 0.339 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.539 - -Slack : 0.339 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.539 - -Slack : 0.339 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.538 - -Slack : 0.340 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.540 - -Slack : 0.340 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.539 - -Slack : 0.341 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.540 +Clock Skew : 0.056 +Data Delay : 0.538 -Slack : 0.344 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Slack : 0.338 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.538 + +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.543 +Data Delay : 0.538 -Slack : 0.345 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.544 +Data Delay : 0.538 -Slack : 0.414 +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.538 + +Slack : 0.339 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.359 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.558 + +Slack : 0.360 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.559 + +Slack : 0.368 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.579 + +Slack : 0.381 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.581 + +Slack : 0.384 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.583 + +Slack : 0.384 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 0.951 - -Slack : 0.415 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.380 -Data Delay : 0.939 - -Slack : 0.473 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.672 +Data Delay : 0.583 + +Slack : 0.432 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.631 + +Slack : 0.434 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.633 + +Slack : 0.435 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.634 + +Slack : 0.435 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.634 + +Slack : 0.450 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.649 + +Slack : 0.476 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 1.008 + +Slack : 0.484 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 1.016 Slack : 0.487 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -18693,428 +19087,347 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.703 -Slack : 0.491 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.690 - -Slack : 0.492 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.692 - -Slack : 0.494 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.694 - -Slack : 0.495 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.695 - -Slack : 0.496 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.696 - -Slack : 0.497 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.697 - -Slack : 0.497 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.696 - -Slack : 0.497 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.696 - -Slack : 0.497 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.697 - -Slack : 0.498 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.698 - -Slack : 0.501 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.714 - -Slack : 0.502 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.702 - -Slack : 0.505 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.705 - -Slack : 0.506 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.706 - -Slack : 0.511 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.711 - -Slack : 0.511 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.711 - -Slack : 0.516 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.716 - -Slack : 0.520 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.732 - -Slack : 0.521 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.721 - -Slack : 0.521 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.721 - -Slack : 0.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.740 - -Slack : 0.529 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.741 - -Slack : 0.532 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.744 - -Slack : 0.544 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.743 - -Slack : 0.546 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.758 - -Slack : 0.550 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.413 -Data Delay : 1.107 - -Slack : 0.625 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.824 - -Slack : 0.627 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.412 -Data Delay : 1.183 - -Slack : 0.627 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.500 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.826 +Clock Skew : 0.056 +Data Delay : 0.700 -Slack : 0.628 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.827 - -Slack : 0.632 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.831 - -Slack : 0.638 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.837 - -Slack : 0.642 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.841 - -Slack : 0.644 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.857 - -Slack : 0.648 +Slack : 0.500 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.861 +Data Delay : 0.713 -Slack : 0.651 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.255 -Data Delay : 0.540 - -Slack : 0.669 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.412 -Data Delay : 1.225 - -Slack : 0.670 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.870 - -Slack : 0.671 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.870 - -Slack : 0.684 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.883 - -Slack : 0.690 +Slack : 0.501 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.890 +Clock Skew : 0.388 +Data Delay : 1.033 -Slack : 0.694 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Slack : 0.504 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.885 +Clock Skew : 0.055 +Data Delay : 0.703 -Slack : 0.697 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Slack : 0.505 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.896 +Data Delay : 0.704 -Slack : 0.707 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.506 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.705 + +Slack : 0.507 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.706 + +Slack : 0.509 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.708 + +Slack : 0.515 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.714 + +Slack : 0.517 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.713 + +Slack : 0.520 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.719 + +Slack : 0.521 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.732 + +Slack : 0.521 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.732 + +Slack : 0.522 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.721 + +Slack : 0.526 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.737 + +Slack : 0.528 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.907 +Data Delay : 0.728 -Slack : 0.724 +Slack : 0.533 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.062 + +Slack : 0.559 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.770 + +Slack : 0.618 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.147 + +Slack : 0.632 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.832 + +Slack : 0.633 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.924 +Clock Skew : 0.055 +Data Delay : 0.832 -Slack : 0.727 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Slack : 0.645 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.047 -Data Delay : 0.918 +Clock Skew : 0.069 +Data Delay : 0.858 -Slack : 0.730 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.658 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.929 +Data Delay : 0.857 + +Slack : 0.677 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 1.209 + +Slack : 0.682 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.211 + +Slack : 0.686 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.263 +Data Delay : 0.567 + +Slack : 0.690 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.903 + +Slack : 0.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.897 + +Slack : 0.705 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.363 +Data Delay : 1.212 + +Slack : 0.705 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.363 +Data Delay : 1.212 + +Slack : 0.705 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.363 +Data Delay : 1.212 + +Slack : 0.705 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.363 +Data Delay : 1.212 + +Slack : 0.705 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.363 +Data Delay : 1.212 + +Slack : 0.705 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.901 + +Slack : 0.706 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.905 + +Slack : 0.713 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.912 + +Slack : 0.718 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.917 + +Slack : 0.720 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.231 +Data Delay : 0.633 Slack : 0.731 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -19134,14 +19447,14 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.948 -Slack : 0.738 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Slack : 0.736 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.937 +Clock Skew : 0.385 +Data Delay : 1.265 Slack : 0.738 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -19153,22 +19466,22 @@ Clock Skew : 0.069 Data Delay : 0.951 Slack : 0.739 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.939 - -Slack : 0.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.953 +Data Delay : 0.952 + +Slack : 0.744 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.943 Slack : 0.745 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -19179,86 +19492,68 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.958 -Slack : 0.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 0.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.960 +Data Delay : 0.959 Slack : 0.748 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.948 - -Slack : 0.748 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.948 - -Slack : 0.752 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.951 - -Slack : 0.753 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.061 Data Delay : 0.953 -Slack : 0.755 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.954 - -Slack : 0.759 +Slack : 0.748 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.959 +Clock Skew : 0.055 +Data Delay : 0.947 -Slack : 0.760 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.960 - -Slack : 0.761 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Slack : 0.749 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.960 +Data Delay : 0.948 + +Slack : 0.749 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.948 + +Slack : 0.765 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.976 + +Slack : 0.765 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.067 +Data Delay : 0.976 +--------------------------------------------------------------------------------+ @@ -19267,8 +19562,8 @@ Data Delay : 0.960 ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ Slack : 0.311 -From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -19276,17 +19571,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -19312,8 +19598,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -19321,8 +19607,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vga_vc[3] +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -19338,6 +19624,42 @@ Relationship : 0.000 Clock Skew : 0.056 Data Delay : 0.511 +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + Slack : 0.312 From Node : ula:ula_|video:video_|vram_address[10] To Node : ula:ula_|video:video_|vram_address[10] @@ -19348,35 +19670,8 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -19401,32 +19696,41 @@ Relationship : 0.000 Clock Skew : 0.056 Data Delay : 0.698 -Slack : 0.528 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.728 - -Slack : 0.640 +Slack : 0.508 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.840 +Data Delay : 0.708 -Slack : 0.727 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +Slack : 0.604 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.067 -Data Delay : 0.938 +Clock Skew : 0.056 +Data Delay : 0.804 + +Slack : 0.720 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.919 + +Slack : 0.720 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.941 Slack : 0.741 From Node : ula:ula_|video:video_|frame[2] @@ -19437,734 +19741,725 @@ Relationship : 0.000 Clock Skew : 0.056 Data Delay : 0.941 -Slack : 0.808 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.005 - -Slack : 0.808 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 0.715 - -Slack : 0.813 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.012 - -Slack : 0.859 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.056 - -Slack : 0.875 +Slack : 0.747 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.075 +Data Delay : 0.947 -Slack : 0.882 +Slack : 0.754 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.082 +Data Delay : 0.954 -Slack : 0.922 -From Node : ula:ula_|video:video_|vga_hc[8] +Slack : 0.754 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.119 +Clock Skew : 0.077 +Data Delay : 0.975 -Slack : 0.925 -From Node : ula:ula_|video:video_|vga_hc[7] +Slack : 0.755 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.122 +Clock Skew : 0.077 +Data Delay : 0.976 -Slack : 0.925 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.122 - -Slack : 1.003 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.203 - -Slack : 1.008 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 0.915 - -Slack : 1.015 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 0.922 - -Slack : 1.018 -From Node : ula:ula_|video:video_|bits_prefetch[5] -To Node : ula:ula_|video:video_|bits[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 0.925 - -Slack : 1.030 +Slack : 0.756 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.227 +Clock Skew : 0.077 +Data Delay : 0.977 -Slack : 1.035 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.232 - -Slack : 1.047 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 0.954 - -Slack : 1.052 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.249 - -Slack : 1.054 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 0.961 - -Slack : 1.096 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.293 - -Slack : 1.104 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[1] +Slack : 0.777 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.303 +Data Delay : 0.976 -Slack : 1.115 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.313 - -Slack : 1.118 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.315 - -Slack : 1.119 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.316 - -Slack : 1.124 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 1.031 - -Slack : 1.124 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.321 - -Slack : 1.124 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.322 - -Slack : 1.126 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.323 - -Slack : 1.134 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.332 - -Slack : 1.140 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.337 - -Slack : 1.141 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.339 - -Slack : 1.151 -From Node : ula:ula_|video:video_|bits_prefetch[7] -To Node : ula:ula_|video:video_|bits[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 1.058 - -Slack : 1.155 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.263 -Data Delay : 1.036 - -Slack : 1.156 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.036 - -Slack : 1.157 -From Node : ula:ula_|video:video_|attr_prefetch[6] -To Node : ula:ula_|video:video_|attr[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.037 - -Slack : 1.178 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.058 - -Slack : 1.180 -From Node : ula:ula_|video:video_|attr_prefetch[1] -To Node : ula:ula_|video:video_|attr[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.263 -Data Delay : 1.061 - -Slack : 1.182 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.380 - -Slack : 1.183 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.380 - -Slack : 1.183 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.380 - -Slack : 1.186 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.066 - -Slack : 1.202 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.400 - -Slack : 1.208 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.406 - -Slack : 1.221 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.419 - -Slack : 1.228 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.426 - -Slack : 1.230 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.428 - -Slack : 1.233 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.432 - -Slack : 1.233 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.432 - -Slack : 1.257 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.455 - -Slack : 1.267 +Slack : 0.839 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.466 +Data Delay : 1.038 -Slack : 1.268 +Slack : 0.858 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.057 + +Slack : 0.868 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.057 +Data Delay : 1.069 + +Slack : 0.913 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.134 + +Slack : 0.952 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.157 + +Slack : 0.961 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.166 + +Slack : 0.994 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.242 +Data Delay : 0.896 + +Slack : 1.014 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.468 +Data Delay : 1.214 -Slack : 1.278 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.048 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.476 +Clock Skew : 0.055 +Data Delay : 1.247 -Slack : 1.280 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.079 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.478 +Clock Skew : 0.063 +Data Delay : 1.286 -Slack : 1.298 -From Node : ula:ula_|video:video_|bits_prefetch[3] -To Node : ula:ula_|video:video_|bits[3] +Slack : 1.096 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 1.205 +Clock Skew : 0.077 +Data Delay : 1.317 -Slack : 1.316 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.264 -Data Delay : 1.196 - -Slack : 1.351 +Slack : 1.097 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.551 +Data Delay : 1.297 -Slack : 1.353 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] +Slack : 1.108 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.215 +Data Delay : 1.037 + +Slack : 1.110 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.553 +Data Delay : 1.310 -Slack : 1.353 -From Node : ula:ula_|video:video_|vga_vc[1] +Slack : 1.117 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.322 + +Slack : 1.119 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.242 +Data Delay : 1.021 + +Slack : 1.137 +From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.551 +Clock Skew : 0.061 +Data Delay : 1.342 -Slack : 1.353 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.551 - -Slack : 1.370 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.568 - -Slack : 1.373 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.571 - -Slack : 1.382 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.582 - -Slack : 1.385 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.585 - -Slack : 1.413 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.611 - -Slack : 1.413 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.053 -Data Delay : 1.610 - -Slack : 1.414 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.612 - -Slack : 1.421 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.620 - -Slack : 1.426 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.626 - -Slack : 1.437 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.237 -Data Delay : 1.344 - -Slack : 1.446 +Slack : 1.164 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.645 +Data Delay : 1.363 -Slack : 1.446 +Slack : 1.164 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.645 +Data Delay : 1.363 -Slack : 1.446 +Slack : 1.164 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.645 +Data Delay : 1.363 -Slack : 1.446 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.645 - -Slack : 1.446 +Slack : 1.164 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.645 +Data Delay : 1.363 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] +Slack : 1.170 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.077 +Data Delay : 1.391 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] +Slack : 1.171 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.061 +Data Delay : 1.376 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] +Slack : 1.172 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.056 +Data Delay : 1.372 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] +Slack : 1.197 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vga_hc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.061 +Data Delay : 1.402 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] +Slack : 1.212 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : -0.242 +Data Delay : 1.114 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] +Slack : 1.214 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.077 +Data Delay : 1.435 -Slack : 1.463 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[0] +Slack : 1.222 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.055 +Data Delay : 1.421 -Slack : 1.463 +Slack : 1.225 From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.390 -Data Delay : 1.997 +Clock Skew : 0.055 +Data Delay : 1.424 + +Slack : 1.225 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.446 + +Slack : 1.230 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.435 + +Slack : 1.242 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.441 + +Slack : 1.248 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.215 +Data Delay : 1.177 + +Slack : 1.249 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.454 + +Slack : 1.252 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.457 + +Slack : 1.256 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.215 +Data Delay : 1.185 + +Slack : 1.295 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.494 + +Slack : 1.303 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.524 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.367 +Data Delay : 1.815 + +Slack : 1.322 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.242 +Data Delay : 1.224 + +Slack : 1.338 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.543 + +Slack : 1.388 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.588 + +Slack : 1.399 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.598 + +Slack : 1.403 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.603 + +Slack : 1.408 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.607 + +Slack : 1.415 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.614 + +Slack : 1.427 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.627 + +Slack : 1.427 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.627 + +Slack : 1.427 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.627 + +Slack : 1.427 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.627 + +Slack : 1.427 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.627 + +Slack : 1.432 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.653 + +Slack : 1.434 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.639 + +Slack : 1.437 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.637 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.648 + +Slack : 1.469 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.674 + +Slack : 1.469 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.674 + +Slack : 1.469 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.674 + +Slack : 1.469 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.674 + +Slack : 1.470 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.669 + +Slack : 1.471 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.215 +Data Delay : 1.400 + +Slack : 1.478 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.677 + +Slack : 1.497 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.702 + +Slack : 1.498 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.697 + +Slack : 1.514 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.735 + +Slack : 1.517 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.716 + +Slack : 1.522 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.721 +--------------------------------------------------------------------------------+ @@ -20173,8 +20468,8 @@ Data Delay : 1.997 ; Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ Slack : 0.312 -From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -20190,13 +20485,13 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 -Slack : 0.313 -From Node : sdram_controller:sdram_|r.wr_pending -To Node : sdram_controller:sdram_|r.wr_pending +Slack : 0.312 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 +Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.313 @@ -20209,8 +20504,8 @@ Clock Skew : 0.054 Data Delay : 0.511 Slack : 0.313 -From Node : sdram_controller:sdram_|r.state[8] -To Node : sdram_controller:sdram_|r.state[8] +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -20226,81 +20521,45 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.519 -Slack : 0.337 -From Node : sdram_controller:sdram_|r.rf_counter[9] -To Node : sdram_controller:sdram_|r.rf_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.536 - -Slack : 0.470 -From Node : sdram_controller:sdram_|r.state[8] -To Node : sdram_controller:sdram_|r.state[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.668 - -Slack : 0.500 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[3] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.699 - -Slack : 0.500 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.698 - -Slack : 0.501 +Slack : 0.499 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 +Data Delay : 0.698 + +Slack : 0.501 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.700 -Slack : 0.502 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.701 - -Slack : 0.502 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.701 - -Slack : 0.502 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.init_counter[14] +Slack : 0.501 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 -Data Delay : 0.700 +Data Delay : 0.699 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 Slack : 0.503 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[2] +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -20316,24 +20575,33 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.702 +Slack : 0.504 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + +Slack : 0.504 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + Slack : 0.505 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[4] +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.704 -Slack : 0.505 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.init_counter[13] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.703 - Slack : 0.505 From Node : sdram_controller:sdram_|r.init_counter[11] To Node : sdram_controller:sdram_|r.init_counter[11] @@ -20344,14 +20612,32 @@ Clock Skew : 0.054 Data Delay : 0.703 Slack : 0.506 -From Node : sdram_controller:sdram_|r.rf_counter[8] -To Node : sdram_controller:sdram_|r.rf_counter[8] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.705 +Slack : 0.507 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.705 + +Slack : 0.512 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.710 + Slack : 0.512 From Node : sdram_controller:sdram_|r.init_counter[2] To Node : sdram_controller:sdram_|r.init_counter[2] @@ -20362,8 +20648,8 @@ Clock Skew : 0.054 Data Delay : 0.710 Slack : 0.513 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[10] +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -20406,114 +20692,123 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.714 -Slack : 0.518 -From Node : sdram_controller:sdram_|r.rf_counter[0] -To Node : sdram_controller:sdram_|r.rf_counter[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.717 - -Slack : 0.518 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.716 - -Slack : 0.533 +Slack : 0.516 From Node : sdram_controller:sdram_|r.init_counter[1] To Node : sdram_controller:sdram_|r.init_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 -Data Delay : 0.731 +Data Delay : 0.714 -Slack : 0.535 +Slack : 0.517 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.715 + +Slack : 0.517 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.715 + +Slack : 0.518 From Node : sdram_controller:sdram_|r.init_counter[7] To Node : sdram_controller:sdram_|r.init_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 -Data Delay : 0.733 +Data Delay : 0.716 -Slack : 0.544 -From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[7] +Slack : 0.519 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.742 +Clock Skew : 0.055 +Data Delay : 0.718 -Slack : 0.547 +Slack : 0.534 From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.state[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 +Clock Skew : 0.055 +Data Delay : 0.733 + +Slack : 0.534 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.733 + +Slack : 0.546 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.745 -Slack : 0.548 +Slack : 0.551 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.750 + +Slack : 0.634 From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.746 +Clock Skew : 0.055 +Data Delay : 0.833 -Slack : 0.744 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[4] +Slack : 0.730 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.943 +Data Delay : 0.929 -Slack : 0.746 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.945 - -Slack : 0.746 +Slack : 0.743 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 +Data Delay : 0.942 + +Slack : 0.746 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.945 -Slack : 0.748 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.946 - -Slack : 0.748 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.946 - Slack : 0.748 From Node : sdram_controller:sdram_|r.rf_counter[7] To Node : sdram_controller:sdram_|r.rf_counter[8] @@ -20523,27 +20818,27 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.947 -Slack : 0.749 -From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Slack : 0.748 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 -Data Delay : 0.947 +Data Delay : 0.946 Slack : 0.749 -From Node : sdram_controller:sdram_|r.state[7] -To Node : sdram_controller:sdram_|r.state[7] +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.947 +Clock Skew : 0.055 +Data Delay : 0.948 Slack : 0.750 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[13] +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -20551,35 +20846,44 @@ Clock Skew : 0.054 Data Delay : 0.948 Slack : 0.751 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.949 + +Slack : 0.752 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.950 - -Slack : 0.751 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.950 +Data Delay : 0.951 Slack : 0.752 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[3] +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.951 +Slack : 0.753 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + Slack : 0.754 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[5] +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -20587,23 +20891,14 @@ Clock Skew : 0.055 Data Delay : 0.953 Slack : 0.755 -From Node : sdram_controller:sdram_|r.rf_counter[8] -To Node : sdram_controller:sdram_|r.rf_counter[9] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.954 -Slack : 0.757 -From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.955 - Slack : 0.757 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[6] @@ -20613,67 +20908,103 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.955 -Slack : 0.757 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[14] +Slack : 0.758 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 -Data Delay : 0.955 +Data Delay : 0.956 -Slack : 0.758 +Slack : 0.759 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.957 + +Slack : 0.759 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.957 - -Slack : 0.758 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.957 - -Slack : 0.759 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 Data Delay : 0.958 -Slack : 0.761 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.959 - -Slack : 0.761 +Slack : 0.759 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.960 +Data Delay : 0.958 -Slack : 0.763 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[11] +Slack : 0.760 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 +Data Delay : 0.958 + +Slack : 0.760 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.958 + +Slack : 0.760 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.959 + +Slack : 0.761 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.959 + +Slack : 0.762 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.960 + +Slack : 0.762 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.960 + +Slack : 0.762 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.961 Slack : 0.763 @@ -20703,6 +21034,15 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.965 +Slack : 0.769 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.967 + Slack : 0.769 From Node : sdram_controller:sdram_|r.init_counter[2] To Node : sdram_controller:sdram_|r.init_counter[4] @@ -20712,15 +21052,6 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.967 -Slack : 0.770 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.968 - Slack : 0.770 From Node : sdram_controller:sdram_|r.init_counter[4] To Node : sdram_controller:sdram_|r.init_counter[6] @@ -20730,15 +21061,6 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.968 -Slack : 0.774 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.init_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.972 - Slack : 0.774 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.init_counter[10] @@ -20748,86 +21070,50 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 0.972 -Slack : 0.776 -From Node : sdram_controller:sdram_|r.init_counter[1] -To Node : sdram_controller:sdram_|r.init_counter[2] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.974 - -Slack : 0.778 -From Node : sdram_controller:sdram_|r.init_counter[7] +Slack : 0.774 +From Node : sdram_controller:sdram_|r.init_counter[6] To Node : sdram_controller:sdram_|r.init_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.054 -Data Delay : 0.976 +Data Delay : 0.972 -Slack : 0.808 +Slack : 0.788 From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.006 - -Slack : 0.813 -From Node : sdram_controller:sdram_|r.rf_counter[9] -To Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.012 +Data Delay : 0.987 -Slack : 0.818 +Slack : 0.793 From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.state[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.016 - -Slack : 0.833 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.032 +Data Delay : 0.992 -Slack : 0.835 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.034 - -Slack : 0.835 +Slack : 0.832 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.034 +Data Delay : 1.031 -Slack : 0.837 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[13] +Slack : 0.835 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.035 +Clock Skew : 0.055 +Data Delay : 1.034 Slack : 0.837 From Node : sdram_controller:sdram_|r.rf_counter[7] @@ -20838,31 +21124,49 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 1.036 -Slack : 0.840 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[6] +Slack : 0.837 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.039 +Clock Skew : 0.054 +Data Delay : 1.035 -Slack : 0.842 +Slack : 0.838 From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.041 +Data Delay : 1.037 -Slack : 0.842 +Slack : 0.839 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.037 + +Slack : 0.839 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 +Data Delay : 1.038 + +Slack : 0.842 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 1.041 Slack : 0.844 @@ -20874,6 +21178,24 @@ Relationship : 0.000 Clock Skew : 0.054 Data Delay : 1.042 +Slack : 0.845 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.044 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.044 + Slack : 0.846 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[7] @@ -20884,49 +21206,76 @@ Clock Skew : 0.054 Data Delay : 1.044 Slack : 0.847 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.045 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.046 + +Slack : 0.848 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.046 - -Slack : 0.847 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.046 - -Slack : 0.848 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 Data Delay : 1.047 -Slack : 0.850 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[11] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.048 - -Slack : 0.850 +Slack : 0.848 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.049 +Data Delay : 1.047 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.047 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.048 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.048 + +Slack : 0.851 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.050 Slack : 0.853 From Node : sdram_controller:sdram_|r.init_counter[5] @@ -20938,40 +21287,67 @@ Clock Skew : 0.054 Data Delay : 1.051 Slack : 0.854 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.052 + +Slack : 0.855 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.053 + +Slack : 0.855 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.053 - -Slack : 0.855 -From Node : sdram_controller:sdram_|r.rf_counter[2] -To Node : sdram_controller:sdram_|r.rf_counter[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 Data Delay : 1.054 -Slack : 0.857 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.055 - -Slack : 0.857 +Slack : 0.855 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.056 +Data Delay : 1.054 + +Slack : 0.856 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.054 + +Slack : 0.856 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.055 + +Slack : 0.857 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.055 Slack : 0.858 From Node : sdram_controller:sdram_|r.init_counter[2] @@ -20983,94 +21359,46 @@ Clock Skew : 0.054 Data Delay : 1.056 Slack : 0.859 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[13] +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.057 +Clock Skew : 0.055 +Data Delay : 1.058 ++--------------------------------------------------------------------------------+ -Slack : 0.859 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.init_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.057 -Slack : 0.863 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.061 -Slack : 0.863 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.init_counter[11] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.312 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.061 +Clock Skew : 0.055 +Data Delay : 0.511 -Slack : 0.865 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.init_counter[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.320 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.063 +Clock Skew : 0.055 +Data Delay : 0.519 -Slack : 0.866 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.710 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.064 - -Slack : 0.866 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.init_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.064 - -Slack : 0.867 -From Node : sdram_controller:sdram_|r.init_counter[7] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.065 - -Slack : 0.870 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.init_counter[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.068 - -Slack : 0.870 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 1.068 +Clock Skew : 0.061 +Data Delay : 0.915 +--------------------------------------------------------------------------------+ @@ -21078,905 +21406,905 @@ Data Delay : 1.068 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.339 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Slack : 0.333 +From Node : debouncer:debounce_autofire|r_State +To Node : debouncer:debounce_autofire|r_State +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.034 +Data Delay : 0.511 + +Slack : 0.333 +From Node : debouncer:debounce_turbo|r_State +To Node : debouncer:debounce_turbo|r_State +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.034 +Data Delay : 0.511 + +Slack : 0.348 +From Node : debouncer:debounce_turbo|r_Count[20] +To Node : debouncer:debounce_turbo|r_Count[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.538 - -Slack : 0.616 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.314 -Data Delay : 3.203 - -Slack : 0.649 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.317 -Data Delay : 3.239 - -Slack : 0.837 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.313 -Data Delay : 3.423 - -Slack : 0.859 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.315 -Data Delay : 3.447 - -Slack : 1.264 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.318 -Data Delay : 3.855 - -Slack : 1.268 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.070 -Data Delay : 3.611 - -Slack : 1.292 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.807 - -Slack : 1.306 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.325 -Data Delay : 3.904 - -Slack : 1.317 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.318 -Data Delay : 3.908 - -Slack : 1.319 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.322 -Data Delay : 3.914 - -Slack : 1.324 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.835 - -Slack : 1.328 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.062 -Data Delay : 3.663 - -Slack : 1.331 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.855 - -Slack : 1.332 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.331 -Data Delay : 3.936 - -Slack : 1.335 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.323 -Data Delay : 3.931 - -Slack : 1.337 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.855 - -Slack : 1.339 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.850 - -Slack : 1.342 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.062 -Data Delay : 3.677 - -Slack : 1.348 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.866 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.864 - -Slack : 1.356 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.062 -Data Delay : 3.691 - -Slack : 1.358 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.882 - -Slack : 1.358 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.869 - -Slack : 1.360 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.318 -Data Delay : 3.951 - -Slack : 1.364 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.889 - -Slack : 1.365 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.890 - -Slack : 1.375 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.066 -Data Delay : 3.714 - -Slack : 1.375 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.322 -Data Delay : 3.970 - -Slack : 1.376 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.076 -Data Delay : 3.725 - -Slack : 1.381 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.905 - -Slack : 1.383 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.894 - -Slack : 1.383 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.318 -Data Delay : 3.974 - -Slack : 1.384 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.074 -Data Delay : 3.731 - -Slack : 1.385 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.910 - -Slack : 1.385 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.310 -Data Delay : 3.968 - -Slack : 1.386 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.902 - -Slack : 1.391 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.067 -Data Delay : 3.731 - -Slack : 1.391 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.323 -Data Delay : 3.987 - -Slack : 1.392 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.077 -Data Delay : 3.742 - -Slack : 1.395 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.313 -Data Delay : 3.981 - -Slack : 1.396 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.054 -Data Delay : 3.723 - -Slack : 1.397 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.055 -Data Delay : 3.725 - -Slack : 1.398 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.069 -Data Delay : 3.740 - -Slack : 1.400 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.075 -Data Delay : 3.748 - -Slack : 1.401 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.916 - -Slack : 1.402 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.325 -Data Delay : 4.000 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 3.922 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.908 - -Slack : 1.408 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.933 - -Slack : 1.408 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 3.925 - -Slack : 1.411 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.926 - -Slack : 1.419 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.930 - -Slack : 1.421 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.315 -Data Delay : 4.009 - -Slack : 1.423 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.933 - -Slack : 1.427 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.951 - -Slack : 1.427 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.310 -Data Delay : 4.010 - -Slack : 1.430 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.941 - -Slack : 1.432 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.939 - -Slack : 1.434 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.937 - -Slack : 1.436 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.331 -Data Delay : 4.040 - -Slack : 1.438 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.953 - -Slack : 1.442 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.967 - -Slack : 1.442 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.960 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.952 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.955 - -Slack : 1.450 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.322 -Data Delay : 4.045 - -Slack : 1.451 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.969 - -Slack : 1.451 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.310 -Data Delay : 4.034 - -Slack : 1.451 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.065 -Data Delay : 3.789 - -Slack : 1.454 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 3.971 - -Slack : 1.456 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.962 - -Slack : 1.456 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.971 - -Slack : 1.458 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.971 - -Slack : 1.459 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.975 - -Slack : 1.461 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.972 - -Slack : 1.462 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.977 - -Slack : 1.466 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.982 - -Slack : 1.468 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.971 - -Slack : 1.469 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.235 -Data Delay : 3.977 - -Slack : 1.470 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.066 -Data Delay : 3.809 - -Slack : 1.471 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.974 - -Slack : 1.474 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.985 - -Slack : 1.475 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.235 -Data Delay : 3.983 - -Slack : 1.477 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.992 - -Slack : 1.481 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.244 -Data Delay : 3.998 - -Slack : 1.481 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.988 - -Slack : 1.481 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.235 -Data Delay : 3.989 - -Slack : 1.481 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.996 - -Slack : 1.484 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.235 -Data Delay : 3.992 - -Slack : 1.486 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.001 - -Slack : 1.486 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.067 -Data Delay : 3.826 - -Slack : 1.487 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.084 -Data Delay : 3.844 - -Slack : 1.487 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.065 -Data Delay : 3.825 - -Slack : 1.487 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.990 - -Slack : 1.487 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.002 - -Slack : 1.488 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.998 - -Slack : 1.488 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.999 - -Slack : 1.488 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.994 - -Slack : 1.488 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.063 -Data Delay : 3.824 +Data Delay : 0.547 + +Slack : 0.349 +From Node : debouncer:debounce_autofire|r_Count[20] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.547 + +Slack : 0.502 +From Node : debouncer:debounce_turbo|r_Count[3] +To Node : debouncer:debounce_turbo|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.503 +From Node : debouncer:debounce_turbo|r_Count[19] +To Node : debouncer:debounce_turbo|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : debouncer:debounce_turbo|r_Count[1] +To Node : debouncer:debounce_turbo|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : debouncer:debounce_autofire|r_Count[1] +To Node : debouncer:debounce_autofire|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : debouncer:debounce_autofire|r_Count[3] +To Node : debouncer:debounce_autofire|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.504 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + +Slack : 0.504 +From Node : debouncer:debounce_turbo|r_Count[17] +To Node : debouncer:debounce_turbo|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + +Slack : 0.504 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.703 + +Slack : 0.504 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.702 + +Slack : 0.505 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.704 + +Slack : 0.505 +From Node : debouncer:debounce_turbo|r_Count[9] +To Node : debouncer:debounce_turbo|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.704 + +Slack : 0.505 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.704 + +Slack : 0.505 +From Node : debouncer:debounce_autofire|r_Count[5] +To Node : debouncer:debounce_autofire|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.704 + +Slack : 0.505 +From Node : debouncer:debounce_autofire|r_Count[19] +To Node : debouncer:debounce_autofire|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.703 + +Slack : 0.505 +From Node : debouncer:debounce_autofire|r_Count[17] +To Node : debouncer:debounce_autofire|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.703 + +Slack : 0.506 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.705 + +Slack : 0.506 +From Node : debouncer:debounce_turbo|r_Count[13] +To Node : debouncer:debounce_turbo|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.705 + +Slack : 0.506 +From Node : debouncer:debounce_autofire|r_Count[9] +To Node : debouncer:debounce_autofire|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.705 + +Slack : 0.506 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.704 + +Slack : 0.507 +From Node : debouncer:debounce_autofire|r_Count[7] +To Node : debouncer:debounce_autofire|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.706 + +Slack : 0.507 +From Node : debouncer:debounce_autofire|r_Count[13] +To Node : debouncer:debounce_autofire|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.705 + +Slack : 0.508 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.707 + +Slack : 0.508 +From Node : debouncer:debounce_turbo|r_Count[15] +To Node : debouncer:debounce_turbo|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.707 + +Slack : 0.509 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.708 + +Slack : 0.509 +From Node : debouncer:debounce_autofire|r_Count[15] +To Node : debouncer:debounce_autofire|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.707 + +Slack : 0.509 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.708 + +Slack : 0.510 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.709 + +Slack : 0.510 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.709 + +Slack : 0.510 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.708 + +Slack : 0.510 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.708 + +Slack : 0.514 +From Node : debouncer:debounce_turbo|r_Count[10] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.713 + +Slack : 0.515 +From Node : debouncer:debounce_autofire|r_Count[10] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.713 + +Slack : 0.517 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.716 + +Slack : 0.517 +From Node : debouncer:debounce_turbo|r_Count[5] +To Node : debouncer:debounce_turbo|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.716 + +Slack : 0.517 +From Node : debouncer:debounce_turbo|r_Count[7] +To Node : debouncer:debounce_turbo|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.716 + +Slack : 0.517 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.716 + +Slack : 0.519 +From Node : debouncer:debounce_turbo|r_Count[11] +To Node : debouncer:debounce_turbo|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.718 + +Slack : 0.519 +From Node : debouncer:debounce_autofire|r_Count[11] +To Node : debouncer:debounce_autofire|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.717 + +Slack : 0.522 +From Node : debouncer:debounce_turbo|r_Count[6] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.721 + +Slack : 0.747 +From Node : debouncer:debounce_turbo|r_Count[3] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.946 + +Slack : 0.748 +From Node : debouncer:debounce_turbo|r_Count[19] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.748 +From Node : debouncer:debounce_turbo|r_Count[1] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.748 +From Node : debouncer:debounce_autofire|r_Count[1] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.748 +From Node : debouncer:debounce_autofire|r_Count[3] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.749 +From Node : debouncer:debounce_turbo|r_Count[17] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.948 + +Slack : 0.749 +From Node : debouncer:debounce_autofire|r_Count[5] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.948 + +Slack : 0.750 +From Node : debouncer:debounce_turbo|r_Count[13] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.949 + +Slack : 0.750 +From Node : debouncer:debounce_autofire|r_Count[19] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.948 + +Slack : 0.750 +From Node : debouncer:debounce_autofire|r_Count[17] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.948 + +Slack : 0.750 +From Node : debouncer:debounce_autofire|r_Count[9] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.949 + +Slack : 0.751 +From Node : debouncer:debounce_turbo|r_Count[9] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 0.948 + +Slack : 0.751 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.751 +From Node : debouncer:debounce_autofire|r_Count[7] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.751 +From Node : debouncer:debounce_autofire|r_Count[13] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.949 + +Slack : 0.751 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.752 +From Node : debouncer:debounce_turbo|r_Count[15] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.752 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.753 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + +Slack : 0.753 +From Node : debouncer:debounce_autofire|r_Count[15] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.951 + +Slack : 0.753 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + +Slack : 0.753 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.951 + +Slack : 0.754 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.754 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.755 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.954 + +Slack : 0.755 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.953 + +Slack : 0.757 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.956 + +Slack : 0.758 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.758 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.758 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.758 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.759 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.958 + +Slack : 0.759 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.958 + +Slack : 0.759 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.958 + +Slack : 0.759 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.957 + +Slack : 0.759 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.957 + +Slack : 0.760 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.959 + +Slack : 0.760 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.959 + +Slack : 0.760 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.958 + +Slack : 0.761 +From Node : debouncer:debounce_turbo|r_Count[7] +To Node : debouncer:debounce_turbo|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.761 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.761 +From Node : debouncer:debounce_turbo|r_Count[5] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.761 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.762 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.961 + +Slack : 0.762 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.960 + +Slack : 0.763 +From Node : debouncer:debounce_turbo|r_Count[10] +To Node : debouncer:debounce_turbo|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.962 + +Slack : 0.764 +From Node : debouncer:debounce_turbo|r_Count[11] +To Node : debouncer:debounce_turbo|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.963 + +Slack : 0.764 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.963 + +Slack : 0.764 +From Node : debouncer:debounce_autofire|r_Count[11] +To Node : debouncer:debounce_autofire|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.962 + +Slack : 0.764 +From Node : debouncer:debounce_autofire|r_Count[10] +To Node : debouncer:debounce_autofire|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.962 + +Slack : 0.765 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.964 + +Slack : 0.765 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.964 + +Slack : 0.766 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.965 + +Slack : 0.766 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.964 + +Slack : 0.766 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.964 + +Slack : 0.768 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 0.965 +--------------------------------------------------------------------------------+ @@ -21984,275 +22312,266 @@ Data Delay : 3.824 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -5.735 +Slack : -5.734 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.934 +Data Delay : 3.933 -Slack : -5.735 +Slack : -5.734 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.090 -Data Delay : 3.932 +Data Delay : 3.931 -Slack : -5.735 +Slack : -5.734 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.931 +Data Delay : 3.930 -Slack : -5.734 +Slack : -5.733 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.930 +Data Delay : 3.929 -Slack : -5.734 +Slack : -5.733 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.092 -Data Delay : 3.929 +Data Delay : 3.928 -Slack : -5.485 +Slack : -5.494 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 3.659 +Data Delay : 3.668 -Slack : -5.485 +Slack : -5.484 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.116 -Data Delay : 3.658 +Data Delay : 3.657 -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.540 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.540 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.540 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.543 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.543 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.543 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.543 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.543 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.543 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.539 - -Slack : -5.248 +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.539 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.539 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.539 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.539 - -Slack : -5.248 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.540 +Data Delay : 3.549 -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.247 +Slack : -5.257 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.539 +Data Delay : 3.549 -Slack : -5.247 +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.101 +Data Delay : 3.534 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.083 -Data Delay : 3.543 +Clock Skew : -0.087 +Data Delay : 3.548 -Slack : -5.247 +Slack : -5.256 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.083 -Data Delay : 3.543 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.256 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.548 + +Slack : -5.255 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.550 + +Slack : -5.255 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.550 + +Slack : -5.255 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.550 + +Slack : -5.255 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.550 + +Slack : -5.255 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.550 Slack : -5.247 From Node : KEY[0] @@ -22299,15 +22618,6 @@ Relationship : 0.424 Clock Skew : -0.088 Data Delay : 3.538 -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.538 - Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] @@ -22326,401 +22636,419 @@ Relationship : 0.424 Clock Skew : -0.088 Data Delay : 3.538 -Slack : -5.247 +Slack : -5.246 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.095 +Data Delay : 3.530 + +Slack : -5.246 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.538 + +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 +Clock Skew : -0.095 +Data Delay : 3.530 -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.247 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.084 -Data Delay : 3.542 - -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 +Slack : -5.246 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.095 +Data Delay : 3.530 + +Slack : -5.246 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.095 +Data Delay : 3.530 + +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -5.242 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 - -Slack : -5.242 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.076 -Data Delay : 3.545 - -Slack : -4.950 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.539 - -Slack : -4.950 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.539 - -Slack : -4.950 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.539 - -Slack : -4.950 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.539 - -Slack : -4.950 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.539 - -Slack : -4.950 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.213 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.226 -Data Delay : 3.539 - -Slack : -4.934 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.224 -Data Delay : 3.537 - -Slack : -4.931 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.539 - -Slack : -4.931 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.539 - -Slack : -4.931 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.539 - -Slack : -4.931 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.539 - -Slack : -4.931 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.229 -Data Delay : 3.539 - -Slack : -4.931 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.545 - -Slack : -4.928 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.236 -Data Delay : 3.543 - -Slack : -4.927 +Slack : -5.246 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.541 +Clock Skew : -0.085 +Data Delay : 3.540 -Slack : -4.910 +Slack : -4.960 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.209 +Data Delay : 3.548 + +Slack : -4.960 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.209 +Data Delay : 3.548 + +Slack : -4.960 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.209 +Data Delay : 3.548 + +Slack : -4.960 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.209 +Data Delay : 3.548 + +Slack : -4.960 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.209 +Data Delay : 3.548 + +Slack : -4.960 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.201 +Data Delay : 3.540 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.537 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.537 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.537 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.537 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.537 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.212 +Data Delay : 3.537 + +Slack : -4.942 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.215 +Data Delay : 3.536 + +Slack : -4.938 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.549 + +Slack : -4.938 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.549 + +Slack : -4.938 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.549 + +Slack : -4.933 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.250 +Clock Skew : 0.227 Data Delay : 3.539 -Slack : -4.910 +Slack : -4.933 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.933 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.933 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.250 -Data Delay : 3.539 +Clock Skew : 0.228 +Data Delay : 3.540 -Slack : -4.904 +Slack : -4.933 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.256 -Data Delay : 3.539 +Clock Skew : 0.228 +Data Delay : 3.540 -Slack : -4.904 +Slack : -4.933 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.256 -Data Delay : 3.539 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.933 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.933 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.933 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.933 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.228 +Data Delay : 3.540 + +Slack : -4.932 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.217 +Data Delay : 3.528 +--------------------------------------------------------------------------------+ @@ -22728,545 +23056,248 @@ Data Delay : 3.539 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.339 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.628 -Data Delay : 3.195 - -Slack : 3.339 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.628 -Data Delay : 3.195 - -Slack : 3.344 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.622 -Data Delay : 3.194 - -Slack : 3.344 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.622 -Data Delay : 3.194 - -Slack : 3.361 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 +Clock Skew : 0.598 Data Delay : 3.196 -Slack : 3.362 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.608 -Data Delay : 3.198 - -Slack : 3.365 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.199 - -Slack : 3.367 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.195 - -Slack : 3.367 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.195 - -Slack : 3.367 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.195 - -Slack : 3.367 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.195 - -Slack : 3.367 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.600 -Data Delay : 3.195 - -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.599 +Data Delay : 3.197 -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.600 +Data Delay : 3.198 -Slack : 3.369 +Slack : 3.370 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.198 + +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.599 +Data Delay : 3.197 -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.600 +Data Delay : 3.198 -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.600 +Data Delay : 3.198 -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.600 +Data Delay : 3.198 -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.597 -Data Delay : 3.194 +Clock Skew : 0.599 +Data Delay : 3.197 -Slack : 3.369 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.596 -Data Delay : 3.193 +Clock Skew : 0.600 +Data Delay : 3.198 -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.193 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.193 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.193 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.193 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.193 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.584 -Data Delay : 3.193 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.688 +Slack : 3.370 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 +Clock Skew : 0.588 +Data Delay : 3.186 -Slack : 3.688 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.283 -Data Delay : 3.199 - -Slack : 3.694 +Slack : 3.377 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.193 +Clock Skew : 0.604 +Data Delay : 3.209 -Slack : 3.694 +Slack : 3.377 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.193 +Clock Skew : 0.604 +Data Delay : 3.209 -Slack : 3.694 +Slack : 3.377 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.193 +Clock Skew : 0.604 +Data Delay : 3.209 -Slack : 3.694 +Slack : 3.380 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.194 + +Slack : 3.380 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.194 + +Slack : 3.380 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.194 + +Slack : 3.380 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.194 + +Slack : 3.380 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.194 + +Slack : 3.380 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.583 +Data Delay : 3.194 + +Slack : 3.384 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.193 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.193 - -Slack : 3.694 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.193 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 +Clock Skew : 0.586 Data Delay : 3.198 -Slack : 3.695 +Slack : 3.398 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.274 +Clock Skew : 0.571 Data Delay : 3.197 -Slack : 3.695 +Slack : 3.402 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.579 +Data Delay : 3.209 -Slack : 3.695 +Slack : 3.402 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.579 +Data Delay : 3.209 -Slack : 3.695 +Slack : 3.402 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.579 +Data Delay : 3.209 -Slack : 3.695 +Slack : 3.402 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.579 +Data Delay : 3.209 -Slack : 3.695 +Slack : 3.402 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 - -Slack : 3.695 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.275 -Data Delay : 3.198 +Clock Skew : 0.579 +Data Delay : 3.209 Slack : 3.695 From Node : KEY[0] @@ -23274,8 +23305,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23283,8 +23314,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23292,8 +23323,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23301,8 +23332,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23310,8 +23341,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23319,8 +23350,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23328,8 +23359,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 Slack : 3.695 From Node : KEY[0] @@ -23337,134 +23368,431 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.193 +Clock Skew : 0.271 +Data Delay : 3.194 -Slack : 3.695 +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.696 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.273 +Data Delay : 3.197 + +Slack : 3.697 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.263 +Data Delay : 3.188 + +Slack : 3.697 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.263 +Data Delay : 3.188 -Slack : 3.695 +Slack : 3.697 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.263 +Data Delay : 3.188 -Slack : 3.695 +Slack : 3.697 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.274 -Data Delay : 3.197 +Clock Skew : 0.263 +Data Delay : 3.188 -Slack : 3.696 +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.209 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.209 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.211 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.211 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.211 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.211 + +Slack : 3.709 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.211 + +Slack : 3.710 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.196 +Clock Skew : 0.271 +Data Delay : 3.209 -Slack : 3.696 +Slack : 3.710 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.209 + +Slack : 3.710 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.209 + +Slack : 3.710 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.196 +Clock Skew : 0.271 +Data Delay : 3.209 -Slack : 3.696 +Slack : 3.710 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.196 +Clock Skew : 0.271 +Data Delay : 3.209 -Slack : 3.696 +Slack : 3.711 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 +Clock Skew : 0.257 Data Delay : 3.196 -Slack : 3.883 +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.711 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.257 +Data Delay : 3.196 + +Slack : 3.884 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.226 -Data Delay : 3.282 +Data Delay : 3.283 -Slack : 3.884 +Slack : 3.898 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.227 -Data Delay : 3.284 +Data Delay : 3.298 -Slack : 4.105 +Slack : 4.106 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.254 -Data Delay : 3.529 +Data Delay : 3.530 -Slack : 4.105 +Slack : 4.106 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.252 -Data Delay : 3.527 +Data Delay : 3.528 -Slack : 4.105 +Slack : 4.106 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.250 -Data Delay : 3.525 +Data Delay : 3.526 -Slack : 4.105 +Slack : 4.106 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.251 -Data Delay : 3.526 +Data Delay : 3.527 -Slack : 4.105 +Slack : 4.106 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.250 -Data Delay : 3.525 +Data Delay : 3.526 +--------------------------------------------------------------------------------+ @@ -23518,7 +23846,31 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 Slack : 4.748 Actual Width : 4.964 @@ -23608,6 +23960,22 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.rf_pending +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + Slack : 4.749 Actual Width : 4.965 Required Width : 0.216 @@ -23728,6 +24096,46 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.rd_pending +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + Slack : 4.749 Actual Width : 4.965 Required Width : 0.216 @@ -23742,88 +24150,8 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[4] - -Slack : 4.750 -Actual Width : 4.966 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[5] - -Slack : 4.750 -Actual Width : 4.966 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[6] - -Slack : 4.750 -Actual Width : 4.966 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[7] - -Slack : 4.750 -Actual Width : 4.966 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[8] - -Slack : 4.751 -Actual Width : 4.967 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[0] -Slack : 4.752 -Actual Width : 4.968 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 - -Slack : 4.752 -Actual Width : 4.968 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 - -Slack : 4.752 -Actual Width : 4.968 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 - -Slack : 4.752 -Actual Width : 4.968 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 - -Slack : 4.752 -Actual Width : 4.968 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 - Slack : 4.841 Actual Width : 4.996 Required Width : 0.155 @@ -23912,62 +24240,46 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.bank[0] -Slack : 4.843 -Actual Width : 4.998 +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.846 +Actual Width : 5.001 Required Width : 0.155 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.state[1] -Slack : 4.843 -Actual Width : 4.998 +Slack : 4.846 +Actual Width : 5.001 Required Width : 0.155 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.state[2] -Slack : 4.844 -Actual Width : 4.999 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11] - -Slack : 4.846 -Actual Width : 5.001 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0] - -Slack : 4.846 -Actual Width : 5.001 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[8] - -Slack : 4.846 -Actual Width : 5.001 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[9] - -Slack : 4.847 -Actual Width : 5.031 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 - Slack : 4.847 Actual Width : 5.002 Required Width : 0.155 @@ -23977,108 +24289,132 @@ Clock Edge : Rise Target : sdram_controller:sdram_|r.address[10] Slack : 4.847 -Actual Width : 5.031 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.849 +Actual Width : 4.999 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.849 +Actual Width : 4.999 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.850 +Actual Width : 5.034 Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 -Slack : 4.847 -Actual Width : 4.997 -Required Width : 0.150 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 - -Slack : 4.847 -Actual Width : 5.002 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 - -Slack : 4.847 -Actual Width : 5.031 +Slack : 4.850 +Actual Width : 5.034 Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 -Slack : 4.847 -Actual Width : 5.031 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 - -Slack : 4.847 -Actual Width : 4.997 -Required Width : 0.150 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[0] - -Slack : 4.847 -Actual Width : 5.002 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[0] - -Slack : 4.848 -Actual Width : 4.998 -Required Width : 0.150 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[10] - -Slack : 4.848 -Actual Width : 5.032 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 - -Slack : 4.848 -Actual Width : 4.998 -Required Width : 0.150 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[8] - -Slack : 4.848 -Actual Width : 5.032 +Slack : 4.850 +Actual Width : 5.034 Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[0] -Slack : 4.849 -Actual Width : 4.999 -Required Width : 0.150 -Type : High Pulse Width +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0] - -Slack : 4.849 -Actual Width : 4.999 -Required Width : 0.150 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[9] +Target : sdram_controller:sdram_|r.rd_pending Slack : 4.850 Actual Width : 5.034 @@ -24086,47 +24422,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[3] - -Slack : 4.850 -Actual Width : 5.034 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[4] - -Slack : 4.850 -Actual Width : 5.034 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[5] - -Slack : 4.850 -Actual Width : 5.034 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[6] - -Slack : 4.850 -Actual Width : 5.034 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[7] - -Slack : 4.850 -Actual Width : 5.034 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[8] +Target : sdram_controller:sdram_|r.wr_pending Slack : 4.851 Actual Width : 5.035 @@ -24134,55 +24430,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[0] - -Slack : 4.851 -Actual Width : 5.035 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[1] - -Slack : 4.851 -Actual Width : 5.035 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[2] - -Slack : 4.851 -Actual Width : 5.035 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[3] - -Slack : 4.851 -Actual Width : 5.035 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[4] - -Slack : 4.851 -Actual Width : 5.001 -Required Width : 0.150 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11] - -Slack : 4.851 -Actual Width : 5.035 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 Slack : 4.851 Actual Width : 5.001 @@ -24248,6 +24496,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[2] +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + Slack : 4.851 Actual Width : 5.035 Required Width : 0.184 @@ -24271,6 +24527,78 @@ Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] +--------------------------------------------------------------------------------+ @@ -24278,13 +24606,13 @@ Target : sdram_controller:sdram_|r.init_counter[6] +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 9.489 -Actual Width : 9.719 +Slack : 9.488 +Actual Width : 9.718 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -24292,7 +24620,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -24300,15 +24628,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -24332,7 +24652,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -24340,7 +24660,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -24348,7 +24668,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -24356,7 +24676,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -24364,7 +24684,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -24388,7 +24716,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -24396,7 +24724,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -24436,7 +24780,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -24444,23 +24788,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -24516,7 +24844,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -24532,7 +24876,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -24548,7 +24892,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -24556,7 +24900,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -24564,7 +24908,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -24582,6 +24926,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 + Slack : 9.491 Actual Width : 9.721 Required Width : 0.230 @@ -24596,7 +24948,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -24604,39 +24956,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -24654,6 +24974,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + Slack : 9.491 Actual Width : 9.721 Required Width : 0.230 @@ -24670,22 +25006,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - Slack : 9.491 Actual Width : 9.721 Required Width : 0.230 @@ -24708,7 +25028,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -24732,15 +25060,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -24772,7 +25092,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : 9.493 +Actual Width : 9.723 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.493 Actual Width : 9.723 @@ -24788,7 +25132,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : 9.493 Actual Width : 9.723 @@ -24796,7 +25140,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : 9.494 Actual Width : 9.724 @@ -24804,15 +25148,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : 9.494 Actual Width : 9.724 @@ -24822,6 +25158,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 @@ -24836,7 +25180,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 Slack : 9.495 Actual Width : 9.725 @@ -24844,15 +25188,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : 9.495 Actual Width : 9.725 @@ -24870,6 +25206,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + Slack : 9.495 Actual Width : 9.725 Required Width : 0.230 @@ -24886,22 +25230,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - Slack : 9.495 Actual Width : 9.725 Required Width : 0.230 @@ -24916,7 +25244,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : 9.497 Actual Width : 9.727 @@ -24924,15 +25252,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 - -Slack : 9.497 -Actual Width : 9.727 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 Slack : 9.497 Actual Width : 9.727 @@ -24948,7 +25268,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 Slack : 9.497 Actual Width : 9.727 @@ -24956,7 +25276,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 Slack : 9.498 Actual Width : 9.728 @@ -24972,7 +25292,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 Slack : 9.498 Actual Width : 9.728 @@ -24980,23 +25300,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 - -Slack : 9.498 -Actual Width : 9.728 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 - -Slack : 9.498 -Actual Width : 9.728 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 Slack : 9.498 Actual Width : 9.728 @@ -25014,6 +25318,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 + Slack : 9.498 Actual Width : 9.728 Required Width : 0.230 @@ -25036,7 +25356,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 Slack : 9.498 Actual Width : 9.728 @@ -25044,7 +25364,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -25052,7 +25372,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -25069,14 +25405,6 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 - -Slack : 9.498 -Actual Width : 9.728 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +--------------------------------------------------------------------------------+ @@ -25084,77 +25412,77 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.596 -Actual Width : 19.812 +Slack : 19.598 +Actual Width : 19.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[0] -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[1] - -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] - -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[3] - -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[4] - -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] - -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] - -Slack : 19.596 -Actual Width : 19.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] - Slack : 19.598 Actual Width : 19.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|frame[0] +Target : ula:ula_|video:video_|bits_prefetch[1] + +Slack : 19.598 +Actual Width : 19.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[2] + +Slack : 19.598 +Actual Width : 19.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[3] + +Slack : 19.598 +Actual Width : 19.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[4] + +Slack : 19.598 +Actual Width : 19.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[5] + +Slack : 19.598 +Actual Width : 19.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[6] + +Slack : 19.598 +Actual Width : 19.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[7] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] Slack : 19.601 Actual Width : 19.817 @@ -25180,6 +25508,38 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[1] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[2] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[3] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[4] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[5] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -25188,6 +25548,86 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[6] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[7] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[0] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[1] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[2] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[3] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[4] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[5] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[6] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[7] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|frame[0] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -25220,6 +25660,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|frame[4] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[1] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -25228,54 +25676,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_hc[2] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -25356,30 +25756,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_vc[9] -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] - Slack : 19.602 Actual Width : 19.818 Required Width : 0.216 @@ -25388,110 +25764,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[7] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[0] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[1] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[2] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[3] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[4] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[5] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[6] - -Slack : 19.602 -Actual Width : 19.818 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[7] - Slack : 19.602 Actual Width : 19.818 Required Width : 0.216 @@ -25506,7 +25778,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[1] +Target : ula:ula_|video:video_|vga_hc[3] Slack : 19.602 Actual Width : 19.818 @@ -25514,7 +25786,47 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[3] +Target : ula:ula_|video:video_|vga_hc[4] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[5] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[6] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[7] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[8] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[9] Slack : 19.602 Actual Width : 19.818 @@ -25621,12 +25933,28 @@ Clock Edge : Rise Target : ula:ula_|video:video_|vram_address[9] Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Slack : 19.603 Actual Width : 19.833 @@ -25634,23 +25962,55 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg -Slack : 19.604 -Actual Width : 19.834 +Slack : 19.605 +Actual Width : 19.835 Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 Slack : 19.605 Actual Width : 19.835 @@ -25658,55 +26018,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -25730,7 +26042,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 Slack : 19.605 Actual Width : 19.835 @@ -25738,7 +26050,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -25746,31 +26058,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Slack : 19.605 Actual Width : 19.835 @@ -25804,6 +26092,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + Slack : 19.605 Actual Width : 19.835 Required Width : 0.230 @@ -25820,69 +26124,93 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 -Slack : 19.605 -Actual Width : 19.821 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.606 +Actual Width : 19.836 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 +--------------------------------------------------------------------------------+ @@ -25890,53 +26218,53 @@ Target : ula:ula_|video:video_|attr_prefetch[7] +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 20.591 -Actual Width : 20.807 +Slack : 20.589 +Actual Width : 20.805 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.591 -Actual Width : 20.807 +Slack : 20.589 +Actual Width : 20.805 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.591 -Actual Width : 20.807 +Slack : 20.589 +Actual Width : 20.805 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Slack : 20.591 -Actual Width : 20.807 +Slack : 20.589 +Actual Width : 20.805 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Slack : 20.591 -Actual Width : 20.807 +Slack : 20.589 +Actual Width : 20.805 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Slack : 20.592 -Actual Width : 20.808 +Slack : 20.589 +Actual Width : 20.805 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Slack : 20.594 Actual Width : 20.810 @@ -25944,7 +26272,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Slack : 20.594 Actual Width : 20.810 @@ -25952,23 +26280,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Slack : 20.594 Actual Width : 20.810 @@ -26040,128 +26352,64 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Data -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle - -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Start -Slack : 20.594 -Actual Width : 20.810 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] - -Slack : 20.594 -Actual Width : 20.810 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -26178,14 +26426,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -26194,30 +26434,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -26226,13 +26442,237 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.598 -Actual Width : 20.814 +Slack : 20.595 +Actual Width : 20.811 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Slack : 20.598 Actual Width : 20.814 @@ -26240,7 +26680,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Slack : 20.598 Actual Width : 20.814 @@ -26248,7 +26688,31 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Slack : 20.598 Actual Width : 20.814 @@ -26258,190 +26722,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] - -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.598 +Actual Width : 20.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Slack : 20.600 -Actual Width : 20.816 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.600 -Actual Width : 20.816 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Slack : 20.600 -Actual Width : 20.816 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.600 -Actual Width : 20.816 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Slack : 20.600 -Actual Width : 20.816 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.600 -Actual Width : 20.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.601 -Actual Width : 20.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] - -Slack : 20.603 -Actual Width : 20.819 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - Slack : 20.633 Actual Width : 20.817 Required Width : 0.184 @@ -26490,48 +26818,48 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Slack : 20.667 -Actual Width : 20.883 +Slack : 20.668 +Actual Width : 20.884 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Slack : 20.667 -Actual Width : 20.883 +Slack : 20.668 +Actual Width : 20.884 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Slack : 20.667 -Actual Width : 20.883 +Slack : 20.668 +Actual Width : 20.884 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Slack : 20.667 -Actual Width : 20.883 +Slack : 20.668 +Actual Width : 20.884 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Slack : 20.667 -Actual Width : 20.883 +Slack : 20.668 +Actual Width : 20.884 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Slack : 20.667 -Actual Width : 20.883 +Slack : 20.668 +Actual Width : 20.884 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -26586,14 +26914,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r -Slack : 20.698 -Actual Width : 20.882 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - Slack : 20.698 Actual Width : 20.853 Required Width : 0.155 @@ -26650,45 +26970,53 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out -Slack : 20.701 -Actual Width : 20.885 -Required Width : 0.184 +Slack : 20.702 +Actual Width : 20.857 +Required Width : 0.155 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out -Slack : 20.701 -Actual Width : 20.885 +Slack : 20.702 +Actual Width : 20.886 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Slack : 20.701 -Actual Width : 20.885 +Slack : 20.703 +Actual Width : 20.887 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.701 -Actual Width : 20.885 +Slack : 20.703 +Actual Width : 20.887 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Slack : 20.701 -Actual Width : 20.885 +Slack : 20.703 +Actual Width : 20.887 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.703 +Actual Width : 20.887 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +--------------------------------------------------------------------------------+ @@ -26696,38 +27024,38 @@ Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : 35.491 -Actual Width : 35.707 +Slack : 35.487 +Actual Width : 35.703 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula:ula_|clocks:clocks_|clk_cpu -Slack : 35.491 -Actual Width : 35.707 +Slack : 35.489 +Actual Width : 35.705 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula:ula_|clocks:clocks_|counter[0] -Slack : 35.597 -Actual Width : 35.781 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula:ula_|clocks:clocks_|clk_cpu - -Slack : 35.597 -Actual Width : 35.781 +Slack : 35.600 +Actual Width : 35.784 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula:ula_|clocks:clocks_|counter[0] +Slack : 35.601 +Actual Width : 35.785 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|clk_cpu + Slack : 35.725 Actual Width : 35.725 Required Width : 0.000 @@ -26744,38 +27072,38 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk -Slack : 35.731 -Actual Width : 35.731 +Slack : 35.727 +Actual Width : 35.727 Required Width : 0.000 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|clocks_|clk_cpu|clk -Slack : 35.731 -Actual Width : 35.731 +Slack : 35.729 +Actual Width : 35.729 Required Width : 0.000 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|clocks_|counter[0]|clk -Slack : 35.757 -Actual Width : 35.757 -Required Width : 0.000 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula_|clocks_|clk_cpu|clk - -Slack : 35.757 -Actual Width : 35.757 +Slack : 35.760 +Actual Width : 35.760 Required Width : 0.000 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|clocks_|counter[0]|clk +Slack : 35.761 +Actual Width : 35.761 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + Slack : 35.763 Actual Width : 35.763 Required Width : 0.000 @@ -26814,45 +27142,129 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : 1.514 -Fall : 1.791 +Rise : 2.750 +Fall : 2.995 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : 2.161 +Fall : 2.433 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : 1.949 +Fall : 2.264 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 2.688 +Fall : 2.988 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 2.750 +Fall : 2.995 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 2.083 +Fall : 2.380 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : 2.794 +Fall : 3.243 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.526 -Fall : 3.809 +Rise : 3.036 +Fall : 3.389 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : 3.044 +Fall : 3.515 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : 4.708 +Fall : 5.013 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : 0.868 -Fall : 1.149 +Rise : 4.016 +Fall : 4.288 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : 0.868 -Fall : 1.149 +Rise : 3.671 +Fall : 3.986 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 4.708 +Fall : 5.013 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 4.196 +Fall : 4.441 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 3.914 +Fall : 4.203 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 4.436 +Fall : 4.761 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.088 -Fall : 1.288 +Rise : 1.138 +Fall : 1.341 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.501 -Fall : 2.786 +Rise : 2.589 +Fall : 2.780 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -26862,45 +27274,129 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : -1.142 -Fall : -1.415 +Rise : -1.329 +Fall : -1.636 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : -1.427 +Fall : -1.697 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : -1.329 +Fall : -1.636 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -1.526 +Fall : -1.822 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -2.137 +Fall : -2.367 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -1.483 +Fall : -1.777 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : -1.419 +Fall : -1.876 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -2.326 -Fall : -2.595 +Rise : -2.529 +Fall : -2.866 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : -1.649 +Fall : -2.117 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : -2.653 +Fall : -2.952 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : -0.319 -Fall : -0.593 +Rise : -2.798 +Fall : -3.068 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : -0.319 -Fall : -0.593 +Rise : -2.941 +Fall : -3.248 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -2.653 +Fall : -2.952 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -3.046 +Fall : -3.299 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -2.752 +Fall : -3.046 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -3.483 +Fall : -3.797 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.536 -Fall : -0.733 +Rise : -0.586 +Fall : -0.786 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -1.185 -Fall : -1.411 +Rise : -0.849 +Fall : -1.071 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -26912,134 +27408,134 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 9.704 -Fall : 9.567 +Rise : 9.235 +Fall : 9.132 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 9.147 -Fall : 9.032 +Rise : 8.964 +Fall : 8.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 9.316 -Fall : 9.197 +Rise : 9.034 +Fall : 8.888 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 9.155 -Fall : 9.002 +Rise : 9.159 +Fall : 9.077 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 9.152 -Fall : 9.158 +Rise : 8.739 +Fall : 8.696 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 9.351 -Fall : 9.246 +Rise : 9.235 +Fall : 9.132 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 9.507 -Fall : 9.411 +Rise : 8.940 +Fall : 8.877 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 9.704 -Fall : 9.567 +Rise : 8.481 +Fall : 8.437 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 9.309 -Fall : 9.150 +Rise : 9.014 +Fall : 8.932 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 9.484 -Fall : 9.425 +Rise : 8.962 +Fall : 8.871 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 9.018 -Fall : 8.912 +Rise : 8.800 +Fall : 8.713 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 9.123 -Fall : 9.045 +Rise : 8.400 +Fall : 8.326 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 9.044 -Fall : 8.917 +Rise : 8.685 +Fall : 8.594 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 8.866 -Fall : 8.821 +Rise : 8.445 +Fall : 8.392 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 9.269 -Fall : 9.179 +Rise : 8.664 +Fall : 8.649 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 9.131 -Fall : 9.026 +Rise : 8.722 +Fall : 8.655 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 9.484 -Fall : 9.425 +Rise : 8.962 +Fall : 8.871 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 8.703 -Fall : 8.604 +Rise : 8.918 +Fall : 8.805 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_ADDR[*] Clock Port : CLOCK_50 -Rise : 3.063 -Fall : 2.969 +Rise : 3.059 +Fall : 2.965 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -27122,8 +27618,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 3.063 -Fall : 2.969 +Rise : 3.053 +Fall : 2.959 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -27157,127 +27653,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 3.059 -Fall : 2.965 +Rise : 3.050 +Fall : 2.956 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 5.612 -Fall : 5.736 +Rise : 5.461 +Fall : 5.467 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 5.021 -Fall : 5.022 +Rise : 4.788 +Fall : 4.759 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.298 -Fall : 5.247 +Rise : 5.047 +Fall : 5.081 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 5.067 -Fall : 5.018 +Rise : 4.960 +Fall : 4.974 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.792 -Fall : 4.786 +Rise : 5.428 +Fall : 5.467 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 Rise : 5.108 -Fall : 5.074 +Fall : 5.147 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 5.184 -Fall : 5.190 +Rise : 5.461 +Fall : 5.392 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 5.057 -Fall : 5.041 +Rise : 4.510 +Fall : 4.536 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 5.242 -Fall : 5.220 +Rise : 5.431 +Fall : 5.403 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 5.612 -Fall : 5.736 +Rise : 5.319 +Fall : 5.394 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 5.433 -Fall : 5.528 +Rise : 5.290 +Fall : 5.351 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 5.415 -Fall : 5.507 +Rise : 5.301 +Fall : 5.365 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 5.415 -Fall : 5.507 +Rise : 5.301 +Fall : 5.365 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 5.584 -Fall : 5.735 +Rise : 5.290 +Fall : 5.366 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 5.606 -Fall : 5.727 +Rise : 5.319 +Fall : 5.388 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 5.606 -Fall : 5.727 +Rise : 5.319 +Fall : 5.388 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 5.216 -Fall : 5.338 +Rise : 5.293 +Fall : 5.397 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -27304,8 +27800,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 3.059 -Fall : 2.965 +Rise : 3.050 +Fall : 2.956 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -27332,197 +27828,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 7.742 -Fall : 7.609 +Rise : 7.358 +Fall : 7.270 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 6.921 -Fall : 6.836 +Rise : 6.806 +Fall : 6.701 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 7.061 -Fall : 6.953 +Rise : 7.271 +Fall : 7.200 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 7.363 -Fall : 7.240 +Rise : 7.331 +Fall : 7.270 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 7.236 -Fall : 7.218 +Rise : 6.888 +Fall : 6.877 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 7.691 -Fall : 7.577 +Rise : 7.358 +Fall : 7.256 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 7.301 -Fall : 7.220 +Rise : 7.121 +Fall : 7.071 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 7.742 -Fall : 7.609 +Rise : 6.608 +Fall : 6.556 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.255 -Fall : 7.167 +Rise : 7.026 +Fall : 6.959 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.609 -Fall : 7.510 +Rise : 6.930 +Fall : 6.849 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.792 -Fall : 6.716 +Rise : 6.562 +Fall : 6.475 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 6.868 -Fall : 6.801 +Rise : 6.634 +Fall : 6.601 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.252 -Fall : 7.155 +Rise : 6.853 +Fall : 6.788 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 6.950 -Fall : 6.881 +Rise : 6.814 +Fall : 6.745 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.609 -Fall : 7.510 +Rise : 6.763 +Fall : 6.706 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.928 -Fall : 6.839 +Rise : 6.903 +Fall : 6.849 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.522 -Fall : 7.467 +Rise : 6.825 +Fall : 6.761 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.553 -Fall : 6.501 +Rise : 6.930 +Fall : 6.832 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 7.801 -Fall : 7.387 +Rise : 7.720 +Fall : 7.262 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 7.801 -Fall : 7.387 +Rise : 7.720 +Fall : 7.262 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.721 -Fall : 6.643 +Rise : 6.306 +Fall : 6.242 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.058 -Fall : 5.994 +Rise : 5.935 +Fall : 5.822 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.058 -Fall : 5.988 +Rise : 5.947 +Fall : 5.831 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.378 -Fall : 6.216 +Rise : 6.517 +Fall : 6.349 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 5.722 -Fall : 5.601 +Rise : 5.965 +Fall : 5.799 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.100 -Fall : 6.052 +Rise : 5.705 +Fall : 5.626 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.378 -Fall : 6.216 +Rise : 6.517 +Fall : 6.349 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.378 -Fall : 6.216 +Rise : 6.517 +Fall : 6.349 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -27535,36 +28031,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.652 -Fall : 6.631 +Rise : 6.139 +Fall : 6.025 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.325 -Fall : 6.242 +Rise : 6.139 +Fall : 6.025 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 6.652 -Fall : 6.631 +Rise : 6.055 +Fall : 5.987 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.096 -Fall : 5.995 +Rise : 6.107 +Fall : 5.976 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.056 -Fall : 5.943 +Rise : 5.673 +Fall : 5.574 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -27632,127 +28128,127 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 7.096 -Fall : 6.975 +Rise : 6.675 +Fall : 6.568 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 7.264 -Fall : 7.182 +Rise : 7.814 +Fall : 7.700 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 7.371 -Fall : 7.296 +Rise : 7.914 +Fall : 7.793 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 7.096 -Fall : 6.975 +Rise : 8.007 +Fall : 7.916 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 7.441 -Fall : 7.404 +Rise : 6.884 +Fall : 6.830 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 7.615 -Fall : 7.537 +Rise : 7.900 +Fall : 7.785 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 7.847 -Fall : 7.749 +Rise : 8.017 +Fall : 7.947 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 7.468 -Fall : 7.367 +Rise : 6.675 +Fall : 6.568 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.876 -Fall : 7.722 +Rise : 7.590 +Fall : 7.547 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 6.991 -Fall : 6.894 +Rise : 6.601 +Fall : 6.539 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.141 -Fall : 7.067 +Rise : 7.487 +Fall : 7.400 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.186 -Fall : 7.151 +Rise : 7.249 +Fall : 7.157 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.991 -Fall : 6.894 +Rise : 7.554 +Fall : 7.455 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.168 -Fall : 7.083 +Rise : 6.601 +Fall : 6.539 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.533 -Fall : 7.468 +Rise : 7.339 +Fall : 7.308 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.485 -Fall : 7.379 +Rise : 7.808 +Fall : 7.734 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.255 -Fall : 7.231 +Rise : 6.758 +Fall : 6.696 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.296 -Fall : 7.199 +Rise : 7.500 +Fall : 7.427 Clock Edge : Rise Clock Reference : CLOCK_50 @@ -27842,8 +28338,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 2.690 -Fall : 2.596 +Rise : 2.681 +Fall : 2.587 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -27877,127 +28373,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 2.686 -Fall : 2.592 +Rise : 2.678 +Fall : 2.584 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.046 -Fall : 4.162 +Rise : 4.002 +Fall : 4.024 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.494 -Fall : 4.492 +Rise : 4.228 +Fall : 4.206 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.759 -Fall : 4.708 +Rise : 4.477 +Fall : 4.495 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.536 -Fall : 4.486 +Rise : 4.394 +Fall : 4.390 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.273 -Fall : 4.266 +Rise : 4.841 +Fall : 4.865 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.576 -Fall : 4.543 +Rise : 4.536 +Fall : 4.558 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.651 -Fall : 4.654 +Rise : 4.916 +Fall : 4.847 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.474 -Fall : 4.453 +Rise : 4.002 +Fall : 4.024 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.705 -Fall : 4.681 +Rise : 4.829 +Fall : 4.797 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 4.425 -Fall : 4.542 +Rise : 4.397 +Fall : 4.467 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 4.254 -Fall : 4.343 +Rise : 4.369 +Fall : 4.426 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 4.236 -Fall : 4.323 +Rise : 4.379 +Fall : 4.439 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 4.236 -Fall : 4.323 +Rise : 4.379 +Fall : 4.439 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 4.398 -Fall : 4.541 +Rise : 4.369 +Fall : 4.440 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 4.419 -Fall : 4.534 +Rise : 4.397 +Fall : 4.462 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 4.419 -Fall : 4.534 +Rise : 4.397 +Fall : 4.462 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 4.046 -Fall : 4.162 +Rise : 4.373 +Fall : 4.471 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -28024,8 +28520,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 2.686 -Fall : 2.592 +Rise : 2.678 +Fall : 2.584 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -28052,197 +28548,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 5.643 -Fall : 5.545 +Rise : 5.885 +Fall : 5.812 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 6.051 -Fall : 5.942 +Rise : 5.887 +Fall : 5.848 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 6.097 -Fall : 5.993 +Rise : 6.220 +Fall : 6.049 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 6.444 -Fall : 6.297 +Rise : 6.425 +Fall : 6.385 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 6.074 -Fall : 6.074 +Rise : 6.051 +Fall : 6.022 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 5.795 -Fall : 5.719 +Rise : 6.464 +Fall : 6.364 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 6.263 -Fall : 6.207 +Rise : 6.162 +Fall : 6.130 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 5.643 -Fall : 5.545 +Rise : 5.885 +Fall : 5.812 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 6.436 -Fall : 6.340 +Rise : 6.182 +Fall : 6.136 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.430 -Fall : 5.409 +Rise : 4.696 +Fall : 4.646 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 5.928 -Fall : 5.827 +Rise : 5.570 +Fall : 5.466 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.912 -Fall : 5.848 +Rise : 5.352 +Fall : 5.306 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.339 -Fall : 6.216 +Rise : 5.968 +Fall : 5.926 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.801 -Fall : 5.753 +Rise : 4.696 +Fall : 4.646 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.713 -Fall : 5.650 +Rise : 5.890 +Fall : 5.834 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.904 -Fall : 5.840 +Rise : 5.953 +Fall : 5.917 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 5.430 -Fall : 5.409 +Rise : 5.046 +Fall : 4.982 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.794 -Fall : 5.736 +Rise : 6.092 +Fall : 6.016 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 4.034 -Fall : 3.964 +Rise : 3.879 +Fall : 3.818 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.778 -Fall : 5.365 +Rise : 5.663 +Fall : 5.258 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 4.250 -Fall : 4.133 +Rise : 3.932 +Fall : 3.854 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 4.034 -Fall : 3.970 +Rise : 3.879 +Fall : 3.818 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.034 -Fall : 3.964 +Rise : 3.890 +Fall : 3.827 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.467 -Fall : 3.356 +Rise : 3.661 +Fall : 3.500 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.489 -Fall : 3.376 +Rise : 3.989 +Fall : 3.866 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.467 -Fall : 3.356 +Rise : 3.661 +Fall : 3.500 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 4.119 -Fall : 3.966 +Rise : 4.518 +Fall : 4.393 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 4.119 -Fall : 3.966 +Rise : 4.518 +Fall : 4.393 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -28255,36 +28751,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.812 -Fall : 3.704 +Rise : 3.499 +Fall : 3.444 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.071 -Fall : 3.991 +Rise : 3.947 +Fall : 3.877 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.084 -Fall : 4.001 +Rise : 3.907 +Fall : 3.758 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.851 -Fall : 3.754 +Rise : 3.915 +Fall : 3.830 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 3.812 -Fall : 3.704 +Rise : 3.499 +Fall : 3.444 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -28352,38 +28848,136 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.172 +RR : 4.281 RF : FR : -FF : 4.298 +FF : 4.438 -Input Port : SW[2] -Output Port : LED[2] -RR : 3.641 -RF : -FR : -FF : 3.830 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 6.287 +RF : 6.221 +FR : 6.551 +FF : 6.493 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 6.070 +RF : 5.980 +FR : 6.334 +FF : 6.252 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 4.092 +FR : 4.238 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 6.588 +RF : 6.490 +FR : 6.895 +FF : 6.805 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 6.362 +RF : 6.225 +FR : 6.629 +FF : 6.576 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 3.897 +FR : 4.014 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 7.364 +RF : 7.269 +FR : 7.661 +FF : 7.574 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 6.313 +RF : 6.258 +FR : 6.620 +FF : 6.534 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 5.571 +FR : 5.363 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 7.218 +RF : 7.124 +FR : 7.455 +FF : 7.369 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 6.929 +RF : 6.814 +FR : 7.198 +FF : 7.091 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 3.795 +FR : 3.949 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 6.803 +RF : 6.673 +FR : 7.092 +FF : 6.970 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 6.424 +RF : 6.383 +FR : 6.706 +FF : 6.647 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 5.697 +FR : 6.366 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 6.274 +RR : 7.137 RF : FR : -FF : 6.463 +FF : 7.416 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.413 +RR : 6.286 RF : FR : -FF : 6.634 +FF : 6.563 Input Port : raw_loader_in -Output Port : LED[3] -RR : 4.080 +Output Port : LED[1] +RR : 4.774 RF : FR : -FF : 4.294 +FF : 4.979 +--------------------------------------------------------------------------------+ @@ -28393,38 +28987,136 @@ FF : 4.294 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.037 +RR : 4.142 RF : FR : -FF : 4.165 +FF : 4.299 -Input Port : SW[2] -Output Port : LED[2] -RR : 3.527 -RF : -FR : -FF : 3.716 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 6.059 +RF : 5.996 +FR : 6.323 +FF : 6.266 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 5.855 +RF : 5.766 +FR : 6.119 +FF : 6.036 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 3.955 +FR : 4.103 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 6.349 +RF : 6.252 +FR : 6.656 +FF : 6.565 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 6.135 +RF : 5.966 +FR : 6.357 +FF : 6.348 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 3.770 +FR : 3.888 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 6.936 +RF : 6.273 +FR : 6.676 +FF : 7.110 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 6.089 +RF : 6.032 +FR : 6.391 +FF : 6.307 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 5.444 +FR : 5.238 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 6.862 +RF : 6.658 +FR : 7.001 +FF : 6.992 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 6.679 +RF : 6.566 +FR : 6.950 +FF : 6.843 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 3.668 +FR : 3.824 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 6.558 +RF : 6.431 +FR : 6.846 +FF : 6.725 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 6.192 +RF : 6.075 +FR : 6.428 +FF : 6.413 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 5.547 +FR : 6.219 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 6.051 +RR : 6.875 RF : FR : -FF : 6.240 +FF : 7.154 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.182 +RR : 6.030 RF : FR : -FF : 6.405 +FF : 6.299 Input Port : raw_loader_in -Output Port : LED[3] -RR : 3.944 +Output Port : LED[1] +RR : 4.610 RF : FR : -FF : 4.156 +FF : 4.813 +--------------------------------------------------------------------------------+ @@ -28434,64 +29126,64 @@ FF : 4.156 +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 5.323 -Fall : 5.181 +Rise : 5.133 +Fall : 4.991 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 5.805 -Fall : 5.663 +Rise : 5.292 +Fall : 5.150 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.805 -Fall : 5.663 +Rise : 5.292 +Fall : 5.150 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 5.488 -Fall : 5.363 +Rise : 5.281 +Fall : 5.156 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 5.500 -Fall : 5.389 +Rise : 5.377 +Fall : 5.266 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 5.323 -Fall : 5.181 +Rise : 5.382 +Fall : 5.240 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 5.512 -Fall : 5.370 +Rise : 5.133 +Fall : 4.991 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 5.512 -Fall : 5.370 +Rise : 5.133 +Fall : 4.991 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 5.495 -Fall : 5.370 +Rise : 5.433 +Fall : 5.308 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -28503,64 +29195,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.160 -Fall : 4.018 +Rise : 4.230 +Fall : 4.088 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.623 -Fall : 4.481 +Rise : 4.383 +Fall : 4.241 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.623 -Fall : 4.481 +Rise : 4.383 +Fall : 4.241 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.286 -Fall : 4.161 +Rise : 4.340 +Fall : 4.215 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.326 -Fall : 4.215 +Rise : 4.461 +Fall : 4.350 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.160 -Fall : 4.018 +Rise : 4.469 +Fall : 4.327 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.341 -Fall : 4.199 +Rise : 4.230 +Fall : 4.088 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.341 -Fall : 4.199 +Rise : 4.230 +Fall : 4.088 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.293 -Fall : 4.168 +Rise : 4.486 +Fall : 4.361 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -28572,64 +29264,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -0 to Hi-Z : 5.156 -1 to Hi-Z : 5.298 +0 to Hi-Z : 4.987 +1 to Hi-Z : 5.129 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -0 to Hi-Z : 5.644 -1 to Hi-Z : 5.786 +0 to Hi-Z : 5.112 +1 to Hi-Z : 5.254 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -0 to Hi-Z : 5.644 -1 to Hi-Z : 5.786 +0 to Hi-Z : 5.112 +1 to Hi-Z : 5.254 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -0 to Hi-Z : 5.349 -1 to Hi-Z : 5.474 +0 to Hi-Z : 5.135 +1 to Hi-Z : 5.260 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -0 to Hi-Z : 5.397 -1 to Hi-Z : 5.508 +0 to Hi-Z : 5.317 +1 to Hi-Z : 5.428 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -0 to Hi-Z : 5.156 -1 to Hi-Z : 5.298 +0 to Hi-Z : 5.233 +1 to Hi-Z : 5.375 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -0 to Hi-Z : 5.257 -1 to Hi-Z : 5.399 +0 to Hi-Z : 4.987 +1 to Hi-Z : 5.129 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -0 to Hi-Z : 5.257 -1 to Hi-Z : 5.399 +0 to Hi-Z : 4.987 +1 to Hi-Z : 5.129 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -0 to Hi-Z : 5.335 -1 to Hi-Z : 5.460 +0 to Hi-Z : 5.329 +1 to Hi-Z : 5.454 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -28641,64 +29333,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -0 to Hi-Z : 3.999 -1 to Hi-Z : 4.141 +0 to Hi-Z : 4.089 +1 to Hi-Z : 4.231 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -0 to Hi-Z : 4.467 -1 to Hi-Z : 4.609 +0 to Hi-Z : 4.210 +1 to Hi-Z : 4.352 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -0 to Hi-Z : 4.467 -1 to Hi-Z : 4.609 +0 to Hi-Z : 4.210 +1 to Hi-Z : 4.352 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -0 to Hi-Z : 4.153 -1 to Hi-Z : 4.278 +0 to Hi-Z : 4.201 +1 to Hi-Z : 4.326 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -0 to Hi-Z : 4.229 -1 to Hi-Z : 4.340 +0 to Hi-Z : 4.404 +1 to Hi-Z : 4.515 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -0 to Hi-Z : 3.999 -1 to Hi-Z : 4.141 +0 to Hi-Z : 4.326 +1 to Hi-Z : 4.468 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -0 to Hi-Z : 4.096 -1 to Hi-Z : 4.238 +0 to Hi-Z : 4.089 +1 to Hi-Z : 4.231 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -0 to Hi-Z : 4.096 -1 to Hi-Z : 4.238 +0 to Hi-Z : 4.089 +1 to Hi-Z : 4.231 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -0 to Hi-Z : 4.139 -1 to Hi-Z : 4.264 +0 to Hi-Z : 4.386 +1 to Hi-Z : 4.511 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -28715,23 +29407,23 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -15.243 -End Point TNS : -641.328 +Slack : -15.170 +End Point TNS : -635.207 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -4.921 -End Point TNS : -171.346 +Slack : -5.647 +End Point TNS : -193.116 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -3.770 -End Point TNS : -34.841 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.784 -End Point TNS : -2.784 +Slack : -3.810 +End Point TNS : -35.303 Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Slack : 6.261 +Slack : 6.131 +End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 70.800 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -28740,16 +29432,8 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ -Clock : CLOCK_50 -Slack : 0.098 -End Point TNS : 0.000 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : 0.177 -End Point TNS : 0.000 - Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.177 +Slack : 0.179 End Point TNS : 0.000 Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -28759,6 +29443,14 @@ End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Slack : 0.186 End Point TNS : 0.000 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Slack : 0.186 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 0.201 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -28768,7 +29460,7 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Slack : -4.684 -End Point TNS : -358.844 +End Point TNS : -359.024 +--------------------------------------------------------------------------------+ @@ -28787,7 +29479,7 @@ End Point TNS : 0.000 ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Slack : 4.783 +Slack : 4.784 End Point TNS : 0.000 Clock : CLOCK_50 @@ -28803,7 +29495,7 @@ Slack : 20.600 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : 35.535 +Slack : 35.525 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -28812,905 +29504,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -15.243 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.289 - -Slack : -15.162 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.208 - -Slack : -15.156 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.202 - -Slack : -15.144 -From Node : ula:ula_|video:video_|frame[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 5.194 - -Slack : -15.131 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.177 - -Slack : -15.128 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.174 - -Slack : -15.126 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.172 - -Slack : -15.110 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.156 - -Slack : -15.104 +Slack : -15.170 From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.150 +Clock Skew : -0.023 +Data Delay : 5.221 -Slack : -15.097 -From Node : ula:ula_|video:video_|vga_vc[6] +Slack : -15.168 +From Node : ula:ula_|video:video_|vga_hc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.143 +Clock Skew : -0.023 +Data Delay : 5.219 -Slack : -15.090 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.136 - -Slack : -15.069 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.115 - -Slack : -15.047 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.093 - -Slack : -15.044 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.090 - -Slack : -15.028 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.074 - -Slack : -15.022 -From Node : ula:ula_|video:video_|bits[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.068 - -Slack : -15.021 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.067 - -Slack : -15.008 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.054 - -Slack : -15.005 +Slack : -15.161 From Node : ula:ula_|video:video_|vga_vc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.051 +Clock Skew : -0.029 +Data Delay : 5.206 -Slack : -14.970 +Slack : -15.156 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.201 + +Slack : -15.151 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.023 +Data Delay : 5.202 + +Slack : -15.132 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.177 + +Slack : -15.086 From Node : ula:ula_|video:video_|vga_vc[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 5.016 +Clock Skew : -0.029 +Data Delay : 5.131 -Slack : -14.969 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 5.030 - -Slack : -14.959 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.859 - -Slack : -14.952 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.169 -Data Delay : 4.857 - -Slack : -14.952 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.848 - -Slack : -14.948 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.994 - -Slack : -14.919 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.980 - -Slack : -14.911 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.807 - -Slack : -14.908 +Slack : -15.069 From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.954 +Clock Skew : -0.023 +Data Delay : 5.120 -Slack : -14.900 +Slack : -15.068 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.113 + +Slack : -15.060 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.105 + +Slack : -15.046 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.091 + +Slack : -15.040 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.085 + +Slack : -15.026 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.023 +Data Delay : 5.077 + +Slack : -15.005 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.050 + +Slack : -14.983 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.028 + +Slack : -14.973 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 5.018 + +Slack : -14.970 From Node : ula:ula_|video:video_|vga_hc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.946 +Clock Skew : -0.023 +Data Delay : 5.021 -Slack : -14.886 +Slack : -14.908 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.953 + +Slack : -14.884 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.929 + +Slack : -14.876 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.921 + +Slack : -14.875 From Node : ula:ula_|video:video_|bits[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.932 +Clock Skew : -0.029 +Data Delay : 4.920 -Slack : -14.886 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.947 - -Slack : -14.874 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : DRAM_DQ[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.770 - -Slack : -14.869 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.930 - -Slack : -14.866 -From Node : ula:ula_|video:video_|bits[3] +Slack : -14.871 +From Node : ula:ula_|video:video_|vga_vc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.912 +Clock Skew : -0.029 +Data Delay : 4.916 Slack : -14.859 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.759 +Clock Skew : -0.029 +Data Delay : 4.904 Slack : -14.853 -From Node : ula:ula_|video:video_|attr[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.899 - -Slack : -14.852 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.898 - -Slack : -14.852 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.169 -Data Delay : 4.757 - -Slack : -14.852 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.748 - -Slack : -14.846 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.907 - -Slack : -14.838 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.734 - -Slack : -14.800 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.700 - -Slack : -14.786 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.847 - -Slack : -14.774 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.670 - -Slack : -14.769 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 4.666 - -Slack : -14.749 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.644 - -Slack : -14.733 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.633 - -Slack : -14.729 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.625 - -Slack : -14.727 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.627 - -Slack : -14.700 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.181 -Data Delay : 4.593 - -Slack : -14.697 -From Node : ula:ula_|video:video_|bits[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.743 - -Slack : -14.696 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 4.593 - -Slack : -14.689 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.589 - -Slack : -14.685 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.581 - -Slack : -14.681 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.742 - -Slack : -14.644 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.705 - -Slack : -14.637 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.698 - -Slack : -14.636 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.531 - -Slack : -14.632 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.185 -Data Delay : 4.521 - -Slack : -14.625 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.521 - -Slack : -14.614 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : DRAM_DQ[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.509 - -Slack : -14.611 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.672 - -Slack : -14.607 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 4.504 - -Slack : -14.582 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.473 - -Slack : -14.567 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.457 - -Slack : -14.544 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.605 - -Slack : -14.542 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.603 - -Slack : -14.541 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.436 - -Slack : -14.541 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.602 - -Slack : -14.538 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.429 - -Slack : -14.536 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : DRAM_DQ[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.176 -Data Delay : 4.434 - -Slack : -14.535 From Node : ula:ula_|video:video_|vga_hc[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.581 +Clock Skew : -0.023 +Data Delay : 4.904 -Slack : -14.517 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.578 - -Slack : -14.504 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.399 - -Slack : -14.502 -From Node : ula:ula_|video:video_|attr[0] +Slack : -14.852 +From Node : ula:ula_|video:video_|bits[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.548 +Clock Skew : -0.029 +Data Delay : 4.897 -Slack : -14.499 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : DRAM_DQ[5] +Slack : -14.850 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.389 +Clock Skew : -0.029 +Data Delay : 4.895 -Slack : -14.499 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Slack : -14.792 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.851 + +Slack : -14.778 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.823 + +Slack : -14.745 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.560 +Clock Skew : -0.015 +Data Delay : 4.804 -Slack : -14.492 +Slack : -14.740 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.800 + +Slack : -14.724 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.176 -Data Delay : 4.390 +Clock Skew : -0.174 +Data Delay : 4.624 -Slack : -14.488 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : DRAM_DQ[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.383 - -Slack : -14.472 +Slack : -14.697 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.185 -Data Delay : 4.361 - -Slack : -14.462 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.357 - -Slack : -14.455 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.516 - -Slack : -14.439 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : DRAM_DQ[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.184 -Data Delay : 4.329 +Data Delay : 4.587 -Slack : -14.438 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] +Slack : -14.696 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.334 +Clock Skew : -0.181 +Data Delay : 4.589 -Slack : -14.438 +Slack : -14.682 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.727 + +Slack : -14.676 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.579 + +Slack : -14.644 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.544 + +Slack : -14.644 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.535 + +Slack : -14.642 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.701 + +Slack : -14.636 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.696 + +Slack : -14.628 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.528 + +Slack : -14.618 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.509 + +Slack : -14.607 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.652 + +Slack : -14.599 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.659 + +Slack : -14.599 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.169 +Data Delay : 4.504 + +Slack : -14.564 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.499 +Clock Skew : -0.014 +Data Delay : 4.624 -Slack : -14.415 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : DRAM_DQ[0] +Slack : -14.505 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.310 +Clock Skew : -0.183 +Data Delay : 4.396 -Slack : -14.413 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.181 -Data Delay : 4.306 - -Slack : -14.401 +Slack : -14.492 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.176 -Data Delay : 4.299 +Data Delay : 4.390 -Slack : -14.389 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] +Slack : -14.484 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.544 + +Slack : -14.477 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.536 + +Slack : -14.468 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.358 + +Slack : -14.464 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.361 + +Slack : -14.461 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.521 + +Slack : -14.455 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.515 + +Slack : -14.454 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.514 + +Slack : -14.433 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.492 + +Slack : -14.430 +From Node : ula:ula_|video:video_|attr[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.029 +Data Delay : 4.475 + +Slack : -14.427 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.324 + +Slack : -14.412 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.312 + +Slack : -14.411 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.176 +Data Delay : 4.309 + +Slack : -14.395 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.454 + +Slack : -14.395 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.454 + +Slack : -14.390 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.185 -Data Delay : 4.278 +Data Delay : 4.279 -Slack : -14.387 +Slack : -14.390 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.287 + +Slack : -14.388 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.176 +Data Delay : 4.286 + +Slack : -14.384 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.443 + +Slack : -14.381 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.276 + +Slack : -14.380 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.182 +Data Delay : 4.272 + +Slack : -14.371 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.261 + +Slack : -14.370 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.265 + +Slack : -14.364 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.259 + +Slack : -14.364 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.267 + +Slack : -14.363 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.259 + +Slack : -14.361 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.420 + +Slack : -14.358 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.253 + +Slack : -14.351 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.411 + +Slack : -14.351 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.240 + +Slack : -14.347 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.242 + +Slack : -14.345 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.242 + +Slack : -14.343 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.403 + +Slack : -14.337 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.177 -Data Delay : 4.284 +Data Delay : 4.234 -Slack : -14.382 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 4.279 - -Slack : -14.380 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : DRAM_DQ[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.171 -Data Delay : 4.283 - -Slack : -14.374 +Slack : -14.333 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : DRAM_DQ[0] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.435 +Clock Skew : -0.015 +Data Delay : 4.392 -Slack : -14.357 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Slack : -14.332 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.223 + +Slack : -14.328 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.217 + +Slack : -14.327 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.418 +Clock Skew : -0.177 +Data Delay : 4.224 -Slack : -14.355 +Slack : -14.324 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.416 +Clock Skew : -0.014 +Data Delay : 4.384 -Slack : -14.350 +Slack : -14.324 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.214 + +Slack : -14.323 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.240 +Clock Skew : -0.176 +Data Delay : 4.221 -Slack : -14.346 +Slack : -14.312 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.371 + +Slack : -14.310 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] +To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.179 -Data Delay : 4.241 +Data Delay : 4.205 -Slack : -14.330 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] +Slack : -14.299 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.013 -Data Delay : 4.391 +Clock Skew : -0.181 +Data Delay : 4.192 -Slack : -14.328 -From Node : ula:ula_|video:video_|attr[3] -To Node : VGA_B[0] +Slack : -14.290 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.028 -Data Delay : 4.374 +Clock Skew : -0.178 +Data Delay : 4.186 -Slack : -14.325 +Slack : -14.287 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.169 +Data Delay : 4.192 + +Slack : -14.279 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.338 + +Slack : -14.276 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.015 +Data Delay : 4.335 + +Slack : -14.273 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.169 + +Slack : -14.266 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.163 + +Slack : -14.259 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.171 -Data Delay : 4.228 +Clock Skew : -0.178 +Data Delay : 4.155 + +Slack : -14.254 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.144 + +Slack : -14.253 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.313 + +Slack : -14.247 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.147 +--------------------------------------------------------------------------------+ @@ -29718,905 +30410,905 @@ Data Delay : 4.228 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -4.921 +Slack : -5.647 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.048 +Data Delay : 3.688 + +Slack : -5.505 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -0.058 -Data Delay : 2.952 - -Slack : -4.920 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -0.062 -Data Delay : 2.947 - -Slack : -4.682 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -0.053 -Data Delay : 2.718 +Data Delay : 3.541 -Slack : -4.553 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.381 -Data Delay : 3.261 - -Slack : -4.552 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.385 -Data Delay : 3.256 - -Slack : -4.500 +Slack : -5.496 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -0.054 -Data Delay : 2.535 +Data Delay : 3.531 -Slack : -4.470 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Slack : -5.487 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 3.176 +Clock Skew : -0.053 +Data Delay : 3.523 -Slack : -4.454 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Slack : -5.388 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.387 -Data Delay : 3.156 +Clock Skew : -0.055 +Data Delay : 3.422 -Slack : -4.454 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 3.198 - -Slack : -4.453 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 3.158 - -Slack : -4.453 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Slack : -5.297 +From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.349 -Data Delay : 3.193 +Clock Skew : -0.052 +Data Delay : 3.334 -Slack : -4.451 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 3.156 - -Slack : -4.427 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.367 -Data Delay : 3.149 - -Slack : -4.427 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 3.142 - -Slack : -4.408 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 3.129 - -Slack : -4.386 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.385 -Data Delay : 3.090 - -Slack : -4.363 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -5.269 +From Node : kempston[2] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 3.073 +Clock Skew : -0.048 +Data Delay : 3.310 -Slack : -4.346 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.388 -Data Delay : 3.047 - -Slack : -4.343 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 3.063 - -Slack : -4.320 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 3.029 - -Slack : -4.320 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.385 -Data Delay : 3.024 - -Slack : -4.314 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.376 -Data Delay : 3.027 - -Slack : -4.312 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.346 -Data Delay : 3.055 - -Slack : -4.292 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.375 -Data Delay : 3.006 - -Slack : -4.280 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.339 -Data Delay : 3.030 - -Slack : -4.269 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.978 - -Slack : -4.265 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.357 -Data Delay : 2.997 - -Slack : -4.261 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 3.010 - -Slack : -4.249 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.381 -Data Delay : 2.957 - -Slack : -4.233 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.387 -Data Delay : 2.935 - -Slack : -4.226 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.364 -Data Delay : 2.951 - -Slack : -4.221 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 2.926 - -Slack : -4.215 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.964 - -Slack : -4.205 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.372 -Data Delay : 2.922 - -Slack : -4.200 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.381 -Data Delay : 2.908 - -Slack : -4.199 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.910 - -Slack : -4.196 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.944 - -Slack : -4.178 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.375 -Data Delay : 2.892 - -Slack : -4.177 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -5.262 +From Node : kempston[3] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 2.892 +Clock Skew : -0.054 +Data Delay : 3.297 -Slack : -4.173 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.382 -Data Delay : 2.880 - -Slack : -4.172 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 2.882 - -Slack : -4.168 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.351 -Data Delay : 2.906 - -Slack : -4.164 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.377 -Data Delay : 2.876 - -Slack : -4.163 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.344 -Data Delay : 2.908 - -Slack : -4.162 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.377 -Data Delay : 2.874 - -Slack : -4.159 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.875 - -Slack : -4.158 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Slack : -5.257 +From Node : kempston[3] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.363 -Data Delay : 2.884 +Clock Skew : -0.053 +Data Delay : 3.293 -Slack : -4.158 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -5.252 +From Node : kempston[3] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.355 -Data Delay : 2.892 +Clock Skew : -0.053 +Data Delay : 3.288 -Slack : -4.155 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -5.240 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.347 -Data Delay : 2.897 +Clock Skew : -0.054 +Data Delay : 3.275 -Slack : -4.146 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Slack : -5.173 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.343 -Data Delay : 2.892 +Clock Skew : -0.051 +Data Delay : 3.211 -Slack : -4.143 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Slack : -5.171 +From Node : kempston[2] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.375 -Data Delay : 2.857 +Clock Skew : -0.054 +Data Delay : 3.206 -Slack : -4.136 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Slack : -5.075 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 2.880 +Clock Skew : -0.058 +Data Delay : 3.106 -Slack : -4.134 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Slack : -5.071 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.855 +Clock Skew : -0.054 +Data Delay : 3.106 -Slack : -4.133 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.839 - -Slack : -4.132 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.841 - -Slack : -4.132 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.377 -Data Delay : 2.844 - -Slack : -4.132 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -5.054 +From Node : kempston[3] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.848 +Clock Skew : -0.052 +Data Delay : 3.091 -Slack : -4.129 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Slack : -5.041 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.381 -Data Delay : 2.837 +Clock Skew : -0.062 +Data Delay : 3.068 -Slack : -4.115 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Slack : -5.037 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.054 +Data Delay : 3.072 + +Slack : -5.003 +From Node : kempston[1] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.342 -Data Delay : 2.862 +Clock Skew : -0.049 +Data Delay : 3.043 -Slack : -4.115 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Slack : -4.988 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.361 -Data Delay : 2.843 +Clock Skew : -0.060 +Data Delay : 3.017 -Slack : -4.095 +Slack : -4.980 +From Node : kempston[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.058 +Data Delay : 3.011 + +Slack : -4.888 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.049 +Data Delay : 2.928 + +Slack : -4.841 +From Node : kempston[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.056 +Data Delay : 2.874 + +Slack : -4.818 +From Node : kempston[4] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.057 +Data Delay : 2.850 + +Slack : -4.296 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 3.011 + +Slack : -4.234 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.968 + +Slack : -4.218 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.359 +Data Delay : 2.948 + +Slack : -4.203 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.936 + +Slack : -4.179 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.919 + +Slack : -4.171 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.887 + +Slack : -4.150 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.884 + +Slack : -4.146 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.885 + +Slack : -4.141 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.846 + +Slack : -4.141 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 2.851 + +Slack : -4.131 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.840 + +Slack : -4.130 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 +Data Delay : 2.836 + +Slack : -4.127 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.842 + +Slack : -4.094 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.349 -Data Delay : 2.835 +Data Delay : 2.834 -Slack : -4.079 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Slack : -4.093 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.336 -Data Delay : 2.832 +Clock Skew : -1.374 +Data Delay : 2.808 -Slack : -4.065 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -4.093 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.349 -Data Delay : 2.805 +Clock Skew : -1.367 +Data Delay : 2.815 -Slack : -4.061 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Slack : -4.092 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.357 -Data Delay : 2.793 +Clock Skew : -1.370 +Data Delay : 2.811 -Slack : -4.058 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Slack : -4.090 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.811 + +Slack : -4.088 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.822 + +Slack : -4.081 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.807 +Clock Skew : -1.356 +Data Delay : 2.814 -Slack : -4.058 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Slack : -4.078 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.377 -Data Delay : 2.770 +Clock Skew : -1.378 +Data Delay : 2.789 -Slack : -4.057 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.773 - -Slack : -4.052 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.372 -Data Delay : 2.769 - -Slack : -4.051 +Slack : -4.077 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.381 +Data Delay : 2.785 + +Slack : -4.070 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.376 -Data Delay : 2.764 +Data Delay : 2.783 -Slack : -4.046 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.333 -Data Delay : 2.802 - -Slack : -4.043 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.784 - -Slack : -4.042 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.352 -Data Delay : 2.779 - -Slack : -4.040 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.372 -Data Delay : 2.757 - -Slack : -4.039 +Slack : -4.069 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.755 - -Slack : -4.036 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.208 -Data Delay : 2.917 - -Slack : -4.033 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.781 - -Slack : -4.031 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.779 - -Slack : -4.027 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.334 -Data Delay : 2.782 - -Slack : -4.022 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.355 -Data Delay : 2.756 - -Slack : -4.021 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.375 -Data Delay : 2.735 - -Slack : -4.020 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 2.730 - -Slack : -4.015 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.357 -Data Delay : 2.747 - -Slack : -4.002 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.750 +Clock Skew : -1.379 +Data Delay : 2.779 -Slack : -4.000 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.741 - -Slack : -3.996 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Slack : -4.065 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.717 +Clock Skew : -1.355 +Data Delay : 2.799 -Slack : -3.991 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Slack : -4.050 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.342 -Data Delay : 2.738 +Data Delay : 2.797 -Slack : -3.990 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Slack : -4.046 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.338 -Data Delay : 2.741 +Clock Skew : -1.355 +Data Delay : 2.780 -Slack : -3.989 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Slack : -4.035 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.700 +Clock Skew : -1.353 +Data Delay : 2.771 + +Slack : -4.031 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.765 + +Slack : -4.027 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.765 + +Slack : -3.992 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 2.706 Slack : -3.979 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.700 - -Slack : -3.979 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -1.367 Data Delay : 2.701 -Slack : -3.970 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Slack : -3.972 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.703 +Clock Skew : -1.384 +Data Delay : 2.677 + +Slack : -3.971 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.683 + +Slack : -3.964 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.364 +Data Delay : 2.689 Slack : -3.963 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.682 +Clock Skew : -1.360 +Data Delay : 2.692 Slack : -3.962 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.335 -Data Delay : 2.716 +Clock Skew : -1.341 +Data Delay : 2.710 Slack : -3.956 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.705 +Clock Skew : -1.374 +Data Delay : 2.671 -Slack : -3.945 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Slack : -3.956 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.656 +Clock Skew : -1.202 +Data Delay : 2.843 -Slack : -3.937 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Slack : -3.948 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.676 +Clock Skew : -1.362 +Data Delay : 2.675 -Slack : -3.929 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +Slack : -3.938 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.670 +Clock Skew : -1.384 +Data Delay : 2.643 -Slack : -3.928 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Slack : -3.933 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.644 +Clock Skew : -1.379 +Data Delay : 2.643 -Slack : -3.924 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Slack : -3.931 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.357 -Data Delay : 2.656 +Clock Skew : -1.382 +Data Delay : 2.638 -Slack : -3.918 +Slack : -3.926 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.351 -Data Delay : 2.656 +Clock Skew : -1.341 +Data Delay : 2.674 + +Slack : -3.925 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.665 + +Slack : -3.925 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.667 + +Slack : -3.924 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.633 + +Slack : -3.921 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.670 + +Slack : -3.916 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.665 + +Slack : -3.912 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.621 + +Slack : -3.911 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 2.631 + +Slack : -3.911 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.363 +Data Delay : 2.637 + +Slack : -3.910 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.358 +Data Delay : 2.641 + +Slack : -3.907 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.358 +Data Delay : 2.638 + +Slack : -3.906 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.627 + +Slack : -3.903 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.619 + +Slack : -3.902 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.635 + +Slack : -3.901 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.622 + +Slack : -3.899 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.620 + +Slack : -3.897 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.376 +Data Delay : 2.610 + +Slack : -3.894 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.636 + +Slack : -3.892 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.601 + +Slack : -3.891 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.631 + +Slack : -3.887 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.333 +Data Delay : 2.643 + +Slack : -3.882 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.594 + +Slack : -3.882 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.386 +Data Delay : 2.585 + +Slack : -3.858 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.209 +Data Delay : 2.738 + +Slack : -3.835 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.357 +Data Delay : 2.567 + +Slack : -3.828 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.539 + +Slack : -3.824 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.558 + +Slack : -3.819 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 2.529 + +Slack : -3.810 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.521 + +Slack : -3.805 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.366 +Data Delay : 2.528 + +Slack : -3.793 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.509 + +Slack : -3.792 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.344 +Data Delay : 2.537 + +Slack : -3.784 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.489 +--------------------------------------------------------------------------------+ @@ -30624,947 +31316,905 @@ Data Delay : 2.656 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -3.770 +Slack : -3.810 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 1.955 + +Slack : -3.810 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 1.955 + +Slack : -3.765 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 1.846 +Data Delay : 1.841 -Slack : -3.712 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.857 - -Slack : -3.712 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.857 - -Slack : -3.473 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.805 - -Slack : -3.473 +Slack : -3.559 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.805 +Clock Skew : -0.049 +Data Delay : 1.881 -Slack : -3.473 +Slack : -3.559 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.805 +Clock Skew : -0.049 +Data Delay : 1.881 -Slack : -3.473 +Slack : -3.559 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.805 +Clock Skew : -0.049 +Data Delay : 1.881 -Slack : -3.473 +Slack : -3.559 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 1.805 +Clock Skew : -0.049 +Data Delay : 1.881 -Slack : -3.355 +Slack : -3.559 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.049 +Data Delay : 1.881 + +Slack : -3.160 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.500 +Clock Skew : -0.036 +Data Delay : 1.495 -Slack : -2.927 +Slack : -2.963 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 1.269 +Clock Skew : -0.049 +Data Delay : 1.285 -Slack : 18.452 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 2.108 - -Slack : 18.460 +Slack : 18.646 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 2.100 - -Slack : 18.530 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 2.030 - -Slack : 18.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 2.002 - -Slack : 18.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 2.002 - -Slack : 18.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.997 - -Slack : 18.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.997 - -Slack : 18.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.995 - -Slack : 18.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.995 - -Slack : 18.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.995 - -Slack : 18.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.995 - -Slack : 18.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.995 - -Slack : 18.571 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.994 - -Slack : 18.571 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.994 - -Slack : 18.571 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.989 - -Slack : 18.571 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.989 - -Slack : 18.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.987 - -Slack : 18.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.987 - -Slack : 18.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.987 - -Slack : 18.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.987 - -Slack : 18.573 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.987 - -Slack : 18.588 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.972 - -Slack : 18.641 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.919 - -Slack : 18.641 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.919 - -Slack : 18.643 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.917 - -Slack : 18.643 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.917 - -Slack : 18.643 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.917 - -Slack : 18.643 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.917 - -Slack : 18.643 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.917 - -Slack : 18.651 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 Data Delay : 1.914 -Slack : 18.651 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 18.646 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.273 +Clock Skew : -0.278 Data Delay : 1.914 -Slack : 18.699 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.861 - -Slack : 18.699 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.861 - -Slack : 18.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.859 +Data Delay : 1.901 -Slack : 18.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.859 +Data Delay : 1.901 -Slack : 18.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.859 +Data Delay : 1.901 -Slack : 18.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.859 +Data Delay : 1.901 -Slack : 18.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.859 +Data Delay : 1.901 -Slack : 18.709 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.856 - -Slack : 18.709 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.856 - -Slack : 18.780 +Slack : 18.659 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.083 -Data Delay : 1.975 +Clock Skew : -0.278 +Data Delay : 1.901 + +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.901 + +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.901 + +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.901 + +Slack : 18.659 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.901 + +Slack : 18.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.827 + +Slack : 18.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.814 + +Slack : 18.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.814 + +Slack : 18.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.814 + +Slack : 18.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.814 + +Slack : 18.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.814 + +Slack : 18.783 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.777 Slack : 18.788 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.083 -Data Delay : 1.967 - -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.815 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.748 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.740 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.740 - -Slack : 18.839 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.721 +Data Delay : 1.772 -Slack : 18.858 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.083 -Data Delay : 1.897 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.893 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.670 - -Slack : 18.898 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.662 - -Slack : 18.916 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.083 -Data Delay : 1.839 - -Slack : 18.936 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.629 - -Slack : 18.936 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.629 - -Slack : 18.950 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 18.789 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.610 +Data Delay : 1.771 -Slack : 18.950 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 18.789 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.610 +Data Delay : 1.771 -Slack : 18.951 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.612 - -Slack : 18.951 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.275 -Data Delay : 1.612 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.608 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.608 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.608 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.608 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.608 - -Slack : 18.970 +Slack : 18.789 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.590 - -Slack : 18.970 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.590 - -Slack : 18.970 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.590 - -Slack : 18.970 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.590 - -Slack : 18.978 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.582 - -Slack : 18.978 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.582 - -Slack : 18.978 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.582 - -Slack : 18.978 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.278 -Data Delay : 1.582 - -Slack : 18.988 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.577 - -Slack : 18.988 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.273 -Data Delay : 1.577 - -Slack : 19.006 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.744 - -Slack : 19.006 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.744 - -Slack : 19.006 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.744 - -Slack : 19.006 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.744 - -Slack : 19.006 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.744 - -Slack : 19.009 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.551 +Data Delay : 1.771 -Slack : 19.009 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 18.789 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.551 +Data Delay : 1.771 -Slack : 19.011 +Slack : 18.796 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.549 +Data Delay : 1.764 -Slack : 19.011 +Slack : 18.796 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.549 +Data Delay : 1.764 -Slack : 19.011 +Slack : 18.796 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.549 +Data Delay : 1.764 -Slack : 19.011 +Slack : 18.796 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.549 +Data Delay : 1.764 -Slack : 19.011 +Slack : 18.796 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.278 -Data Delay : 1.549 +Data Delay : 1.764 -Slack : 19.014 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Slack : 18.801 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.736 +Clock Skew : -0.278 +Data Delay : 1.759 -Slack : 19.014 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Slack : 18.801 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.736 +Clock Skew : -0.278 +Data Delay : 1.759 -Slack : 19.014 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 18.801 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.736 +Clock Skew : -0.278 +Data Delay : 1.759 -Slack : 19.014 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 18.801 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.736 +Clock Skew : -0.278 +Data Delay : 1.759 -Slack : 19.014 +Slack : 18.801 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.759 + +Slack : 18.853 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.707 + +Slack : 18.853 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.707 + +Slack : 18.895 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.665 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.652 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.652 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.652 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.652 + +Slack : 18.908 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.652 + +Slack : 18.911 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.652 + +Slack : 18.911 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.652 + +Slack : 18.912 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.651 + +Slack : 18.912 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.651 + +Slack : 18.917 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.646 + +Slack : 18.917 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.646 + +Slack : 18.917 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.646 + +Slack : 18.918 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.642 + +Slack : 18.918 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.642 + +Slack : 18.918 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.645 + +Slack : 18.918 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.645 + +Slack : 18.918 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.645 + +Slack : 18.926 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.634 + +Slack : 18.926 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.634 + +Slack : 18.974 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.589 + +Slack : 18.974 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.589 + +Slack : 18.980 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.583 + +Slack : 18.980 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.583 + +Slack : 18.980 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.583 + +Slack : 19.022 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.088 -Data Delay : 1.736 -+--------------------------------------------------------------------------------+ +Clock Skew : -0.098 +Data Delay : 1.718 +Slack : 19.022 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.718 +Slack : 19.022 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.718 -+--------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; -+--------------------------------------------------------------------------------+ -Slack : -2.784 -From Node : SW[2] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.423 -Clock Skew : -0.021 -Data Delay : 1.133 +Slack : 19.022 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.718 -Slack : 70.891 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.046 -Data Delay : 0.539 +Slack : 19.022 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.718 -Slack : 71.071 -From Node : ula:ula_|clocks:clocks_|counter[0] -To Node : ula:ula_|clocks:clocks_|counter[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.046 -Data Delay : 0.359 +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.717 -Slack : 71.071 -From Node : ula:ula_|clocks:clocks_|clk_cpu -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 71.489 -Clock Skew : -0.046 -Data Delay : 0.359 +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.717 + +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.717 + +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.717 + +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.717 + +Slack : 19.031 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.529 + +Slack : 19.031 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.529 + +Slack : 19.039 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.524 + +Slack : 19.039 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.524 + +Slack : 19.045 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.518 + +Slack : 19.045 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.518 + +Slack : 19.045 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.518 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.511 + +Slack : 19.052 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.511 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.076 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.487 + +Slack : 19.076 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.487 + +Slack : 19.077 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.486 + +Slack : 19.077 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.486 + +Slack : 19.085 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.655 + +Slack : 19.085 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.655 + +Slack : 19.085 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.098 +Data Delay : 1.655 +--------------------------------------------------------------------------------+ @@ -31572,1853 +32222,938 @@ Data Delay : 0.359 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 6.261 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[4] +Slack : 6.131 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.031 -Data Delay : 3.647 +Data Delay : 3.777 -Slack : 6.273 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[4] +Slack : 6.191 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 3.697 + +Slack : 6.206 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.031 -Data Delay : 3.635 +Data Delay : 3.702 -Slack : 6.330 +Slack : 6.293 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.615 + +Slack : 6.314 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 3.574 + +Slack : 6.322 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.586 + +Slack : 6.340 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.546 + +Slack : 6.351 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.557 + +Slack : 6.353 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.534 + +Slack : 6.369 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 3.511 + +Slack : 6.395 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.492 + +Slack : 6.395 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.491 + +Slack : 6.408 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.479 + +Slack : 6.419 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.489 + +Slack : 6.421 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.466 + +Slack : 6.422 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.463 + +Slack : 6.433 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.458 + +Slack : 6.444 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.464 + +Slack : 6.448 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.443 + +Slack : 6.454 From Node : sdram_controller:sdram_|r.act_row[0] To Node : sdram_controller:sdram_|r.address[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.031 -Data Delay : 3.578 +Clock Skew : -0.032 +Data Delay : 3.453 -Slack : 6.342 +Slack : 6.462 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.425 + +Slack : 6.463 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.424 + +Slack : 6.469 From Node : sdram_controller:sdram_|r.act_row[1] To Node : sdram_controller:sdram_|r.address[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.031 -Data Delay : 3.566 +Clock Skew : -0.032 +Data Delay : 3.438 -Slack : 6.363 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[5] +Slack : 6.470 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.536 - -Slack : 6.366 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.031 -Data Delay : 3.542 - -Slack : 6.378 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.521 - -Slack : 6.388 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.511 - -Slack : 6.390 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.510 - -Slack : 6.405 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.495 - -Slack : 6.415 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.485 - -Slack : 6.437 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.462 - -Slack : 6.438 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.461 - -Slack : 6.456 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.443 - -Slack : 6.464 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.435 - -Slack : 6.464 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.436 - -Slack : 6.465 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.435 - -Slack : 6.483 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 +Clock Skew : -0.052 Data Delay : 3.417 -Slack : 6.491 -From Node : sdram_controller:sdram_|r.init_counter[4] +Slack : 6.482 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.405 + +Slack : 6.490 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.396 + +Slack : 6.494 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.397 + +Slack : 6.500 +From Node : sdram_controller:sdram_|r.init_counter[7] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.409 +Clock Skew : -0.031 +Data Delay : 3.408 -Slack : 6.513 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[5] +Slack : 6.500 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.386 +Clock Skew : -0.060 +Data Delay : 3.380 -Slack : 6.524 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[5] +Slack : 6.504 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.040 +Clock Skew : -0.061 Data Delay : 3.375 -Slack : 6.540 -From Node : sdram_controller:sdram_|r.init_counter[10] +Slack : 6.505 +From Node : sdram_controller:sdram_|r.init_counter[2] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.360 +Clock Skew : -0.031 +Data Delay : 3.403 -Slack : 6.551 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.349 - -Slack : 6.561 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.340 - -Slack : 6.566 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.334 - -Slack : 6.576 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.325 - -Slack : 6.578 +Slack : 6.506 From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[0] +To Node : sdram_controller:sdram_|r.state[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.321 +Clock Skew : -0.049 +Data Delay : 3.385 -Slack : 6.581 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.318 - -Slack : 6.586 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.315 - -Slack : 6.590 +Slack : 6.515 From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[0] +To Node : sdram_controller:sdram_|r.address[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.309 +Clock Skew : -0.032 +Data Delay : 3.392 -Slack : 6.593 -From Node : sdram_controller:sdram_|r.init_counter[3] +Slack : 6.516 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.389 + +Slack : 6.527 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.032 +Data Delay : 3.380 + +Slack : 6.529 +From Node : sdram_controller:sdram_|r.init_counter[13] To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.308 +Clock Skew : -0.031 +Data Delay : 3.379 -Slack : 6.606 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.address[10] +Slack : 6.531 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.279 +Clock Skew : -0.034 +Data Delay : 3.374 -Slack : 6.608 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[5] +Slack : 6.539 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.348 + +Slack : 6.544 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 3.344 + +Slack : 6.547 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.033 -Data Delay : 3.298 +Data Delay : 3.359 -Slack : 6.608 -From Node : sdram_controller:sdram_|r.init_counter[13] +Slack : 6.552 +From Node : sdram_controller:sdram_|r.wr_pending To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.292 +Clock Skew : -0.033 +Data Delay : 3.354 -Slack : 6.614 +Slack : 6.553 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.332 + +Slack : 6.558 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.329 + +Slack : 6.559 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.349 + +Slack : 6.561 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.326 + +Slack : 6.564 From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 3.316 + +Slack : 6.570 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 3.318 + +Slack : 6.572 +From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.address[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.036 -Data Delay : 3.289 +Clock Skew : -0.051 +Data Delay : 3.316 -Slack : 6.615 -From Node : sdram_controller:sdram_|r.wr_pending -To Node : sdram_controller:sdram_|r.address[4] +Slack : 6.577 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.029 +Clock Skew : -0.034 +Data Delay : 3.328 + +Slack : 6.578 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.309 + +Slack : 6.579 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.327 + +Slack : 6.583 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.032 +Data Delay : 3.324 + +Slack : 6.589 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.316 + +Slack : 6.593 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 Data Delay : 3.295 -Slack : 6.620 +Slack : 6.609 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.278 + +Slack : 6.614 From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.292 + +Slack : 6.620 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.033 Data Delay : 3.286 -Slack : 6.621 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.address[10] +Slack : 6.630 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.264 +Clock Skew : -0.031 +Data Delay : 3.278 Slack : 6.631 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.254 - -Slack : 6.635 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.266 - -Slack : 6.636 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.265 - -Slack : 6.647 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.252 - -Slack : 6.654 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.247 - -Slack : 6.659 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.240 - -Slack : 6.662 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.239 - -Slack : 6.671 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.034 -Data Delay : 3.234 - -Slack : 6.677 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.229 - -Slack : 6.680 -From Node : sdram_controller:sdram_|r.rd_pending -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.029 -Data Delay : 3.230 - -Slack : 6.680 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.205 - -Slack : 6.681 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.204 - -Slack : 6.682 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.224 - -Slack : 6.683 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.216 - -Slack : 6.683 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.034 -Data Delay : 3.222 - -Slack : 6.688 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.039 -Data Delay : 3.212 - -Slack : 6.689 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.217 - -Slack : 6.699 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.186 - -Slack : 6.707 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.178 - -Slack : 6.711 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.190 - -Slack : 6.713 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.193 - -Slack : 6.714 -From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[2] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.043 -Data Delay : 3.183 - -Slack : 6.722 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.179 - -Slack : 6.732 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.061 -Data Delay : 3.147 - -Slack : 6.737 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.061 -Data Delay : 3.142 - -Slack : 6.738 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[3] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.037 -Data Delay : 3.164 - -Slack : 6.738 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.037 -Data Delay : 3.164 - -Slack : 6.739 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.address[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.160 - -Slack : 6.740 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.034 -Data Delay : 3.165 - -Slack : 6.741 From Node : sdram_controller:sdram_|r.init_counter[9] To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.061 -Data Delay : 3.138 +Clock Skew : -0.053 +Data Delay : 3.256 -Slack : 6.750 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 3.142 - -Slack : 6.752 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.034 -Data Delay : 3.153 - -Slack : 6.756 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.129 - -Slack : 6.762 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 3.130 - -Slack : 6.764 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.037 -Data Delay : 3.138 - -Slack : 6.767 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.118 - -Slack : 6.768 -From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.138 - -Slack : 6.776 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.035 -Data Delay : 3.128 - -Slack : 6.776 -From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.bank[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.034 -Data Delay : 3.129 - -Slack : 6.779 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.038 -Data Delay : 3.122 - -Slack : 6.780 -From Node : sdram_controller:sdram_|r.act_row[3] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.126 - -Slack : 6.799 -From Node : sdram_controller:sdram_|r.state[4] -To Node : sdram_controller:sdram_|r.address[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.037 -Data Delay : 3.103 - -Slack : 6.804 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.061 -Data Delay : 3.075 - -Slack : 6.809 -From Node : sdram_controller:sdram_|r.init_counter[3] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.054 -Data Delay : 3.077 - -Slack : 6.812 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.061 -Data Delay : 3.067 - -Slack : 6.814 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 3.078 - -Slack : 6.824 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.address[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.055 -Data Delay : 3.061 - -Slack : 6.825 -From Node : sdram_controller:sdram_|r.state[4] +Slack : 6.631 +From Node : sdram_controller:sdram_|r.state[8] To Node : sdram_controller:sdram_|r.address[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.045 -Data Delay : 3.070 +Clock Skew : -0.060 +Data Delay : 3.249 -Slack : 6.829 -From Node : sdram_controller:sdram_|r.init_counter[5] -To Node : sdram_controller:sdram_|r.state[0] +Slack : 6.635 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.address[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.061 -Data Delay : 3.050 +Data Delay : 3.244 -Slack : 6.831 +Slack : 6.638 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 3.242 + +Slack : 6.643 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.263 + +Slack : 6.653 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 3.235 + +Slack : 6.658 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.233 + +Slack : 6.661 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 3.228 + +Slack : 6.665 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.222 + +Slack : 6.669 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.065 +Data Delay : 3.206 + +Slack : 6.678 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.063 +Data Delay : 3.199 + +Slack : 6.684 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.201 + +Slack : 6.690 From Node : sdram_controller:sdram_|r.act_row[1] To Node : sdram_controller:sdram_|r.address[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 3.061 +Clock Skew : -0.049 +Data Delay : 3.201 -Slack : 6.837 -From Node : sdram_controller:sdram_|r.act_row[0] -To Node : sdram_controller:sdram_|r.bank[1] +Slack : 6.690 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.069 +Clock Skew : -0.063 +Data Delay : 3.187 -Slack : 6.842 +Slack : 6.691 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.194 + +Slack : 6.693 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.194 + +Slack : 6.699 +From Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.036 +Data Delay : 3.204 + +Slack : 6.702 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.206 + +Slack : 6.707 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.180 + +Slack : 6.709 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 3.178 + +Slack : 6.720 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 3.167 + +Slack : 6.725 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.166 + +Slack : 6.742 From Node : sdram_controller:sdram_|r.state[4] To Node : sdram_controller:sdram_|r.address[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.046 -Data Delay : 3.052 - -Slack : 6.842 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.state[0] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 Clock Skew : -0.061 -Data Delay : 3.037 +Data Delay : 3.137 -Slack : 6.849 +Slack : 6.748 From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.address[10] +To Node : sdram_controller:sdram_|r.state[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.048 -Data Delay : 3.043 +Clock Skew : -0.049 +Data Delay : 3.143 -Slack : 6.849 -From Node : sdram_controller:sdram_|r.act_row[1] -To Node : sdram_controller:sdram_|r.bank[1] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.057 - -Slack : 6.850 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.state[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.097 - -Slack : 6.852 -From Node : sdram_controller:sdram_|r.init_counter[2] +Slack : 6.748 +From Node : sdram_controller:sdram_|r.wr_pending To Node : sdram_controller:sdram_|r.address[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.047 +Clock Skew : -0.034 +Data Delay : 3.157 -Slack : 6.863 -From Node : sdram_controller:sdram_|r.state[8] -To Node : sdram_controller:sdram_|r.address[0] +Slack : 6.748 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.041 -Data Delay : 3.036 +Clock Skew : -0.060 +Data Delay : 3.132 -Slack : 6.865 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.state[4] +Slack : 6.749 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.address[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.082 +Clock Skew : -0.031 +Data Delay : 3.159 -Slack : 6.867 +Slack : 6.754 From Node : sdram_controller:sdram_|r.act_row[2] -To Node : sdram_controller:sdram_|r.state[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 3.137 + +Slack : 6.754 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 Clock Skew : -0.054 -Data Delay : 3.019 +Data Delay : 3.131 -Slack : 6.873 +Slack : 6.760 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 3.133 + +Slack : 6.764 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.dq_masks[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.121 + +Slack : 6.764 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.dq_masks[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.121 + +Slack : 6.766 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.113 + +Slack : 6.769 From Node : sdram_controller:sdram_|r.act_row[4] -To Node : sdram_controller:sdram_|r.bank[1] +To Node : sdram_controller:sdram_|r.address[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.033 -Data Delay : 3.033 +Clock Skew : -0.032 +Data Delay : 3.138 -Slack : 6.875 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.state[4] +Slack : 6.771 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.state[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 10.000 -Clock Skew : -0.040 -Data Delay : 3.072 +Clock Skew : -0.053 +Data Delay : 3.116 + +Slack : 6.773 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.106 + +Slack : 6.774 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.032 +Data Delay : 3.133 + +Slack : 6.778 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 3.115 + +Slack : 6.781 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.043 +Data Delay : 3.116 + +Slack : 6.787 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.042 +Data Delay : 3.111 + +Slack : 6.787 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.030 +Data Delay : 3.122 + +Slack : 6.793 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.036 +Data Delay : 3.110 +--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : 0.098 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.563 -Data Delay : 1.869 - -Slack : 0.136 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.566 -Data Delay : 1.910 - -Slack : 0.194 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.314 - -Slack : 0.237 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.562 -Data Delay : 2.007 - -Slack : 0.244 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.564 -Data Delay : 2.016 - -Slack : 0.537 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.572 -Data Delay : 2.317 - -Slack : 0.538 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.566 -Data Delay : 2.312 - -Slack : 0.544 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.158 - -Slack : 0.545 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.569 -Data Delay : 2.322 - -Slack : 0.551 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.577 -Data Delay : 2.336 - -Slack : 0.556 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.564 -Data Delay : 2.328 - -Slack : 0.567 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.401 -Data Delay : 2.176 - -Slack : 0.568 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.569 -Data Delay : 2.345 - -Slack : 0.574 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.570 -Data Delay : 2.352 - -Slack : 0.577 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.562 -Data Delay : 2.347 - -Slack : 0.584 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.564 -Data Delay : 2.356 - -Slack : 0.591 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.561 -Data Delay : 2.360 - -Slack : 0.593 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.400 -Data Delay : 2.201 - -Slack : 0.596 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.564 -Data Delay : 2.368 - -Slack : 0.597 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.570 -Data Delay : 2.375 - -Slack : 0.599 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.572 -Data Delay : 2.379 - -Slack : 0.599 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.408 -Data Delay : 2.215 - -Slack : 0.600 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.566 -Data Delay : 2.374 - -Slack : 0.600 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.402 -Data Delay : 2.210 - -Slack : 0.605 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.558 -Data Delay : 2.371 - -Slack : 0.609 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.398 -Data Delay : 2.215 - -Slack : 0.610 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.224 - -Slack : 0.613 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.335 - -Slack : 0.616 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.395 -Data Delay : 2.219 - -Slack : 0.627 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.352 - -Slack : 0.628 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.412 -Data Delay : 2.248 - -Slack : 0.631 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.348 - -Slack : 0.632 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.349 - -Slack : 0.633 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.577 -Data Delay : 2.418 - -Slack : 0.637 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.366 - -Slack : 0.639 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.369 - -Slack : 0.639 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.407 -Data Delay : 2.254 - -Slack : 0.640 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.359 - -Slack : 0.642 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.571 -Data Delay : 2.421 - -Slack : 0.642 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.569 -Data Delay : 2.419 - -Slack : 0.645 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.558 -Data Delay : 2.411 - -Slack : 0.646 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.579 -Data Delay : 2.433 - -Slack : 0.647 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.368 - -Slack : 0.649 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.410 -Data Delay : 2.267 - -Slack : 0.650 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.382 - -Slack : 0.655 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 2.378 - -Slack : 0.657 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.523 -Data Delay : 2.388 - -Slack : 0.657 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.413 -Data Delay : 2.278 - -Slack : 0.660 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.274 - -Slack : 0.661 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.275 - -Slack : 0.666 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.405 -Data Delay : 2.279 - -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.393 - -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.385 - -Slack : 0.671 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.392 - -Slack : 0.678 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.411 -Data Delay : 2.297 - -Slack : 0.679 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.390 - -Slack : 0.682 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.421 -Data Delay : 2.311 - -Slack : 0.685 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.417 - -Slack : 0.685 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.426 -Data Delay : 2.319 - -Slack : 0.686 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.510 -Data Delay : 2.404 - -Slack : 0.687 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.416 - -Slack : 0.687 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 2.413 - -Slack : 0.687 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.561 -Data Delay : 2.456 - -Slack : 0.688 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.523 -Data Delay : 2.419 - -Slack : 0.688 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.409 -Data Delay : 2.305 - -Slack : 0.688 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.420 -Data Delay : 2.316 - -Slack : 0.689 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.403 -Data Delay : 2.300 - -Slack : 0.690 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.579 -Data Delay : 2.477 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.421 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.415 - -Slack : 0.693 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.404 -Data Delay : 2.305 - -Slack : 0.694 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.518 -Data Delay : 2.420 - -Slack : 0.694 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.409 - -Slack : 0.694 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.410 - -Slack : 0.695 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.309 - -Slack : 0.696 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.573 -Data Delay : 2.477 - -Slack : 0.697 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.502 -Data Delay : 2.407 - -Slack : 0.698 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.422 -Data Delay : 2.328 - -Slack : 0.700 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.314 - -Slack : 0.701 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.403 -Data Delay : 2.312 - -Slack : 0.703 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.422 -Data Delay : 2.333 - -Slack : 0.705 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.426 - -Slack : 0.706 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.438 - -Slack : 0.708 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.433 - -Slack : 0.708 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.405 -Data Delay : 2.321 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.433 - -Slack : 0.710 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 2.433 - -Slack : 0.711 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.436 - -Slack : 0.711 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.510 -Data Delay : 2.429 - -Slack : 0.712 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.414 -Data Delay : 2.334 - -Slack : 0.713 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.427 - -Slack : 0.714 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.444 - -Slack : 0.716 -From Node : ula:ula_|video:video_|vram_address[9] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.438 - -Slack : 0.717 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.413 -Data Delay : 2.338 - -Slack : 0.718 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.442 - -Slack : 0.718 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.442 - -Slack : 0.719 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.448 - -Slack : 0.719 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.444 - -Slack : 0.719 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.428 -Data Delay : 2.355 - -Slack : 0.721 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.437 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; -+--------------------------------------------------------------------------------+ -Slack : 0.177 -From Node : ula:ula_|clocks:clocks_|clk_cpu +Slack : 70.800 +From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.307 +Relationship : 71.489 +Clock Skew : -0.032 +Data Delay : 0.644 -Slack : 0.184 +Slack : 71.080 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|counter[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.314 +Relationship : 71.489 +Clock Skew : -0.037 +Data Delay : 0.359 -Slack : 0.306 -From Node : ula:ula_|clocks:clocks_|counter[0] +Slack : 71.080 +From Node : ula:ula_|clocks:clocks_|clk_cpu To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.436 - -Slack : 1.186 -From Node : SW[2] -To Node : ula:ula_|clocks:clocks_|clk_cpu -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Relationship : -0.017 -Clock Skew : 0.233 -Data Delay : 0.576 +Relationship : 71.489 +Clock Skew : -0.037 +Data Delay : 0.359 +--------------------------------------------------------------------------------+ @@ -33426,31 +33161,13 @@ Data Delay : 0.576 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.177 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.307 - -Slack : 0.177 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.307 - -Slack : 0.178 +Slack : 0.179 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.044 Data Delay : 0.307 Slack : 0.183 @@ -33462,24 +33179,6 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.314 -Slack : 0.184 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.314 - -Slack : 0.185 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.314 - Slack : 0.186 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data @@ -33499,17 +33198,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -33526,14 +33216,23 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.314 + Slack : 0.186 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] @@ -33561,6 +33260,33 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 +Slack : 0.187 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + Slack : 0.187 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] @@ -33570,18 +33296,27 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 -Slack : 0.192 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.313 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -33589,8 +33324,8 @@ Clock Skew : 0.037 Data Delay : 0.314 Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -33598,40 +33333,40 @@ Clock Skew : 0.037 Data Delay : 0.314 Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 -Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.314 +Data Delay : 0.315 -Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.314 +Data Delay : 0.315 -Slack : 0.193 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.314 +Data Delay : 0.315 Slack : 0.194 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] @@ -33643,8 +33378,26 @@ Clock Skew : 0.037 Data Delay : 0.315 Slack : 0.194 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -33652,8 +33405,17 @@ Clock Skew : 0.036 Data Delay : 0.314 Slack : 0.194 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.314 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -33669,86 +33431,131 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.314 -Slack : 0.196 +Slack : 0.195 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.316 + +Slack : 0.195 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.316 + +Slack : 0.211 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.331 + +Slack : 0.213 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.333 + +Slack : 0.216 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.344 + +Slack : 0.221 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.342 + +Slack : 0.227 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.347 + +Slack : 0.230 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.350 + +Slack : 0.251 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.372 + +Slack : 0.252 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.373 + +Slack : 0.253 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.317 +Data Delay : 0.374 -Slack : 0.197 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.317 - -Slack : 0.203 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.323 - -Slack : 0.203 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.323 - -Slack : 0.226 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.231 -Data Delay : 0.541 - -Slack : 0.243 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.240 -Data Delay : 0.567 - -Slack : 0.261 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.381 - -Slack : 0.271 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.391 - -Slack : 0.278 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 0.254 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.399 +Data Delay : 0.375 + +Slack : 0.273 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.393 + +Slack : 0.281 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.599 Slack : 0.287 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -33759,15 +33566,6 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.418 -Slack : 0.288 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.409 - Slack : 0.288 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -33778,13 +33576,13 @@ Clock Skew : 0.047 Data Delay : 0.419 Slack : 0.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.410 +Clock Skew : 0.234 +Data Delay : 0.607 Slack : 0.289 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -33795,53 +33593,8 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.420 -Slack : 0.293 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.294 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - -Slack : 0.294 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - -Slack : 0.294 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - -Slack : 0.294 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - Slack : 0.295 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -33850,355 +33603,328 @@ Clock Skew : 0.047 Data Delay : 0.426 Slack : 0.296 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.416 +Clock Skew : 0.037 +Data Delay : 0.417 -Slack : 0.296 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.416 - -Slack : 0.299 +Slack : 0.300 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.420 -Slack : 0.299 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.304 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.425 - -Slack : 0.306 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.249 -Data Delay : 0.639 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.428 - -Slack : 0.307 +Slack : 0.301 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.428 +Clock Skew : 0.036 +Data Delay : 0.421 -Slack : 0.310 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Slack : 0.301 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.431 +Clock Skew : 0.036 +Data Delay : 0.421 -Slack : 0.311 +Slack : 0.302 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.432 +Data Delay : 0.423 -Slack : 0.315 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 0.303 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.443 +Clock Skew : 0.036 +Data Delay : 0.423 -Slack : 0.319 +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.427 + +Slack : 0.307 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.426 + +Slack : 0.308 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.428 + +Slack : 0.310 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.044 -Data Delay : 0.447 +Data Delay : 0.438 -Slack : 0.320 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Slack : 0.311 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.431 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.630 + +Slack : 0.314 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.044 -Data Delay : 0.448 +Data Delay : 0.442 -Slack : 0.321 +Slack : 0.315 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.436 + +Slack : 0.316 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.233 +Data Delay : 0.633 + +Slack : 0.320 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.044 -Data Delay : 0.449 +Data Delay : 0.448 -Slack : 0.325 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.446 - -Slack : 0.328 +Slack : 0.341 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.044 -Data Delay : 0.456 +Data Delay : 0.469 -Slack : 0.369 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 0.364 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.485 + +Slack : 0.367 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.047 -Data Delay : 0.500 - -Slack : 0.371 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.491 - -Slack : 0.372 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.502 - -Slack : 0.374 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.494 - -Slack : 0.375 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.246 -Data Delay : 0.705 - -Slack : 0.375 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.495 - -Slack : 0.375 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.495 - -Slack : 0.378 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 Data Delay : 0.498 -Slack : 0.380 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.500 - -Slack : 0.381 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.149 -Data Delay : 0.316 - -Slack : 0.386 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.506 - -Slack : 0.388 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.508 - -Slack : 0.395 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.516 - -Slack : 0.396 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.246 -Data Delay : 0.726 - -Slack : 0.401 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.521 - -Slack : 0.402 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.030 -Data Delay : 0.516 - -Slack : 0.412 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.532 - -Slack : 0.424 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.030 -Data Delay : 0.538 - -Slack : 0.426 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.547 - -Slack : 0.427 +Slack : 0.370 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.548 +Data Delay : 0.491 -Slack : 0.435 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Slack : 0.371 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.233 +Data Delay : 0.688 + +Slack : 0.376 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.497 + +Slack : 0.401 +From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.529 + +Slack : 0.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.708 + +Slack : 0.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.708 + +Slack : 0.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.708 + +Slack : 0.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.708 + +Slack : 0.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.221 +Data Delay : 0.708 + +Slack : 0.404 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.154 +Data Delay : 0.334 + +Slack : 0.413 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.555 +Data Delay : 0.533 -Slack : 0.435 +Slack : 0.413 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.731 + +Slack : 0.416 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.535 + +Slack : 0.417 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.537 + +Slack : 0.419 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.538 + +Slack : 0.424 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.556 +Data Delay : 0.545 -Slack : 0.436 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.426 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.556 +Clock Skew : -0.137 +Data Delay : 0.373 Slack : 0.436 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -34209,6 +33935,15 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.567 +Slack : 0.437 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.557 + Slack : 0.437 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] @@ -34218,41 +33953,14 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.568 -Slack : 0.443 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 0.446 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.566 - -Slack : 0.444 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.567 - -Slack : 0.447 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.568 - -Slack : 0.447 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.568 +Clock Skew : 0.041 +Data Delay : 0.571 Slack : 0.447 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] @@ -34264,7 +33972,25 @@ Clock Skew : 0.047 Data Delay : 0.578 Slack : 0.448 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.448 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.448 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -34272,6 +33998,15 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.579 +Slack : 0.449 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.569 + Slack : 0.450 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] @@ -34282,16 +34017,7 @@ Clock Skew : 0.047 Data Delay : 0.581 Slack : 0.451 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.571 - -Slack : 0.451 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -34299,32 +34025,41 @@ Relationship : 0.000 Clock Skew : 0.047 Data Delay : 0.582 -Slack : 0.453 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.452 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.573 +Clock Skew : 0.233 +Data Delay : 0.769 -Slack : 0.455 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Slack : 0.459 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.575 +Clock Skew : 0.044 +Data Delay : 0.587 -Slack : 0.455 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Slack : 0.463 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.576 +Clock Skew : 0.035 +Data Delay : 0.582 + +Slack : 0.463 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.591 +--------------------------------------------------------------------------------+ @@ -34333,8 +34068,26 @@ Data Delay : 0.576 ; Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ Slack : 0.186 -From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -34350,24 +34103,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.187 -From Node : sdram_controller:sdram_|r.wr_pending -To Node : sdram_controller:sdram_|r.wr_pending -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 - -Slack : 0.187 -From Node : sdram_controller:sdram_|r.rd_pending -To Node : sdram_controller:sdram_|r.rd_pending -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 - Slack : 0.187 From Node : sdram_controller:sdram_|r.rf_pending To Node : sdram_controller:sdram_|r.rf_pending @@ -34386,42 +34121,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 -Slack : 0.198 -From Node : sdram_controller:sdram_|r.rf_counter[9] -To Node : sdram_controller:sdram_|r.rf_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.318 - -Slack : 0.276 -From Node : sdram_controller:sdram_|r.state[8] -To Node : sdram_controller:sdram_|r.state[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.397 - -Slack : 0.296 -From Node : sdram_controller:sdram_|r.init_counter[14] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.417 - -Slack : 0.296 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.417 - Slack : 0.297 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[1] @@ -34432,8 +34131,8 @@ Clock Skew : 0.036 Data Delay : 0.417 Slack : 0.298 -From Node : sdram_controller:sdram_|r.rf_counter[3] -To Node : sdram_controller:sdram_|r.rf_counter[3] +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -34441,48 +34140,30 @@ Clock Skew : 0.036 Data Delay : 0.418 Slack : 0.298 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.init_counter[13] +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.419 +Clock Skew : 0.036 +Data Delay : 0.418 Slack : 0.299 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[5] +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.419 -Slack : 0.299 +Slack : 0.300 From Node : sdram_controller:sdram_|r.rf_counter[6] To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.419 - -Slack : 0.299 -From Node : sdram_controller:sdram_|r.rf_counter[7] -To Node : sdram_controller:sdram_|r.rf_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.419 - -Slack : 0.299 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[11] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 Data Delay : 0.420 Slack : 0.300 @@ -34494,14 +34175,50 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.420 -Slack : 0.301 +Slack : 0.300 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.421 +Data Delay : 0.420 + +Slack : 0.300 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 Slack : 0.301 From Node : sdram_controller:sdram_|r.rf_counter[8] @@ -34513,158 +34230,167 @@ Clock Skew : 0.036 Data Delay : 0.421 Slack : 0.304 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[10] +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 +Data Delay : 0.424 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 Data Delay : 0.425 -Slack : 0.304 +Slack : 0.305 From Node : sdram_controller:sdram_|r.init_counter[4] To Node : sdram_controller:sdram_|r.init_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.425 -Slack : 0.304 +Slack : 0.305 From Node : sdram_controller:sdram_|r.init_counter[2] To Node : sdram_controller:sdram_|r.init_counter[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.425 -Slack : 0.305 +Slack : 0.306 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.init_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.426 -Slack : 0.305 +Slack : 0.306 From Node : sdram_controller:sdram_|r.init_counter[6] To Node : sdram_controller:sdram_|r.init_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.426 -Slack : 0.305 +Slack : 0.306 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.426 Slack : 0.307 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[9] +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.428 +Clock Skew : 0.036 +Data Delay : 0.427 -Slack : 0.309 +Slack : 0.307 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.427 + +Slack : 0.307 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.427 + +Slack : 0.307 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.427 + +Slack : 0.311 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[0] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.429 +Data Delay : 0.431 Slack : 0.317 -From Node : sdram_controller:sdram_|r.init_counter[1] -To Node : sdram_controller:sdram_|r.init_counter[1] +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.438 -Slack : 0.318 -From Node : sdram_controller:sdram_|r.init_counter[7] -To Node : sdram_controller:sdram_|r.init_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.439 - -Slack : 0.324 -From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.445 - -Slack : 0.328 +Slack : 0.320 From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.state[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.449 +Data Delay : 0.441 -Slack : 0.328 +Slack : 0.326 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.447 + +Slack : 0.330 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.451 + +Slack : 0.372 From Node : sdram_controller:sdram_|r.state[7] To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.449 +Data Delay : 0.493 -Slack : 0.424 -From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Slack : 0.441 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.545 - -Slack : 0.427 -From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 -To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.548 - -Slack : 0.440 -From Node : sdram_controller:sdram_|r.state[7] -To Node : sdram_controller:sdram_|r.state[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.561 -Slack : 0.446 -From Node : sdram_controller:sdram_|r.init_counter[13] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.567 - Slack : 0.446 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[2] @@ -34674,86 +34400,113 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.566 -Slack : 0.447 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[12] +Slack : 0.448 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.568 -Slack : 0.447 +Slack : 0.448 From Node : sdram_controller:sdram_|r.rf_counter[3] To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.567 +Data Delay : 0.568 Slack : 0.448 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.449 From Node : sdram_controller:sdram_|r.rf_counter[5] To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.568 +Data Delay : 0.569 -Slack : 0.448 +Slack : 0.449 From Node : sdram_controller:sdram_|r.rf_counter[7] To Node : sdram_controller:sdram_|r.rf_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.568 +Data Delay : 0.569 -Slack : 0.453 +Slack : 0.454 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.574 Slack : 0.455 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[13] +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.576 +Clock Skew : 0.036 +Data Delay : 0.575 Slack : 0.455 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[10] +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.576 +Clock Skew : 0.036 +Data Delay : 0.575 -Slack : 0.456 +Slack : 0.455 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.575 + +Slack : 0.455 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.575 + +Slack : 0.457 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.577 + +Slack : 0.458 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[1] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.576 - -Slack : 0.457 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.577 +Data Delay : 0.578 Slack : 0.458 From Node : sdram_controller:sdram_|r.rf_counter[2] @@ -34765,13 +34518,22 @@ Clock Skew : 0.036 Data Delay : 0.578 Slack : 0.458 -From Node : sdram_controller:sdram_|r.init_counter[12] -To Node : sdram_controller:sdram_|r.init_counter[14] +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.579 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 Slack : 0.459 From Node : sdram_controller:sdram_|r.rf_counter[8] @@ -34782,32 +34544,23 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.579 -Slack : 0.459 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[5] +Slack : 0.460 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.579 +Data Delay : 0.580 -Slack : 0.459 +Slack : 0.461 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[2] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.579 - -Slack : 0.460 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.580 +Data Delay : 0.581 Slack : 0.461 From Node : sdram_controller:sdram_|r.rf_counter[2] @@ -34818,141 +34571,132 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.581 -Slack : 0.462 +Slack : 0.461 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.582 +Data Delay : 0.581 -Slack : 0.463 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[11] +Slack : 0.461 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.584 +Clock Skew : 0.036 +Data Delay : 0.581 -Slack : 0.463 +Slack : 0.464 From Node : sdram_controller:sdram_|r.init_counter[4] To Node : sdram_controller:sdram_|r.init_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.584 Slack : 0.464 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.584 + +Slack : 0.464 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.584 + +Slack : 0.465 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.init_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.585 -Slack : 0.464 +Slack : 0.465 From Node : sdram_controller:sdram_|r.init_counter[6] To Node : sdram_controller:sdram_|r.init_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.585 -Slack : 0.465 -From Node : sdram_controller:sdram_|r.init_counter[1] -To Node : sdram_controller:sdram_|r.init_counter[2] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.586 - -Slack : 0.466 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.init_counter[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.587 - -Slack : 0.466 -From Node : sdram_controller:sdram_|r.init_counter[7] -To Node : sdram_controller:sdram_|r.init_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.587 - -Slack : 0.466 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[12] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.587 - -Slack : 0.466 +Slack : 0.467 From Node : sdram_controller:sdram_|r.init_counter[4] To Node : sdram_controller:sdram_|r.init_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.587 Slack : 0.467 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.587 + +Slack : 0.467 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.587 + +Slack : 0.468 From Node : sdram_controller:sdram_|r.init_counter[8] To Node : sdram_controller:sdram_|r.init_counter[10] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.588 -Slack : 0.467 +Slack : 0.468 From Node : sdram_controller:sdram_|r.init_counter[6] To Node : sdram_controller:sdram_|r.init_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.588 -Slack : 0.473 +Slack : 0.469 From Node : sdram_controller:sdram_|r.state[5] -To Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.590 + +Slack : 0.473 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.594 -Slack : 0.483 -From Node : sdram_controller:sdram_|r.state[6] -To Node : sdram_controller:sdram_|r.state[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.604 - -Slack : 0.497 -From Node : sdram_controller:sdram_|r.rf_counter[9] -To Node : sdram_controller:sdram_|r.rf_pending -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.617 - Slack : 0.509 From Node : sdram_controller:sdram_|r.rf_counter[1] To Node : sdram_controller:sdram_|r.rf_counter[3] @@ -34962,41 +34706,50 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.629 -Slack : 0.510 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[13] +Slack : 0.511 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.631 -Slack : 0.510 +Slack : 0.511 From Node : sdram_controller:sdram_|r.rf_counter[3] To Node : sdram_controller:sdram_|r.rf_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.630 +Data Delay : 0.631 Slack : 0.511 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.631 + +Slack : 0.512 From Node : sdram_controller:sdram_|r.rf_counter[5] To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.631 +Data Delay : 0.632 -Slack : 0.511 +Slack : 0.512 From Node : sdram_controller:sdram_|r.rf_counter[7] To Node : sdram_controller:sdram_|r.rf_counter[9] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.631 +Data Delay : 0.632 Slack : 0.512 From Node : sdram_controller:sdram_|r.rf_counter[1] @@ -35007,95 +34760,149 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.632 -Slack : 0.513 -From Node : sdram_controller:sdram_|r.init_counter[11] -To Node : sdram_controller:sdram_|r.init_counter[14] +Slack : 0.514 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.634 -Slack : 0.513 +Slack : 0.514 From Node : sdram_controller:sdram_|r.rf_counter[3] To Node : sdram_controller:sdram_|r.rf_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.633 +Data Delay : 0.634 Slack : 0.514 -From Node : sdram_controller:sdram_|r.rf_counter[5] -To Node : sdram_controller:sdram_|r.rf_counter[8] +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.634 +Slack : 0.515 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.635 + Slack : 0.516 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.636 + +Slack : 0.517 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.637 Slack : 0.518 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[11] +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[5] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.639 +Clock Skew : 0.036 +Data Delay : 0.638 -Slack : 0.519 +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.638 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.638 + +Slack : 0.520 From Node : sdram_controller:sdram_|r.init_counter[5] To Node : sdram_controller:sdram_|r.init_counter[8] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.640 Slack : 0.521 -From Node : sdram_controller:sdram_|r.init_counter[9] -To Node : sdram_controller:sdram_|r.init_counter[12] +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_pending Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.642 +Clock Skew : 0.036 +Data Delay : 0.641 -Slack : 0.522 -From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 -To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Slack : 0.521 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.init_counter[6] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 +Data Delay : 0.641 + +Slack : 0.521 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.641 + +Slack : 0.521 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.641 + +Slack : 0.523 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 Data Delay : 0.643 -Slack : 0.522 +Slack : 0.524 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[3] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.642 - -Slack : 0.523 -From Node : sdram_controller:sdram_|r.rf_counter[6] -To Node : sdram_controller:sdram_|r.rf_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.643 +Data Delay : 0.644 Slack : 0.524 From Node : sdram_controller:sdram_|r.rf_counter[2] @@ -35106,23 +34913,50 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.644 -Slack : 0.525 +Slack : 0.524 From Node : sdram_controller:sdram_|r.rf_counter[4] To Node : sdram_controller:sdram_|r.rf_counter[7] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.645 +Data Delay : 0.644 + +Slack : 0.524 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.644 Slack : 0.525 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.646 + +Slack : 0.526 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.646 + +Slack : 0.527 From Node : sdram_controller:sdram_|r.rf_counter[0] To Node : sdram_controller:sdram_|r.rf_counter[4] Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.645 +Data Delay : 0.647 Slack : 0.527 From Node : sdram_controller:sdram_|r.rf_counter[2] @@ -35132,105 +34966,6 @@ Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.647 - -Slack : 0.528 -From Node : sdram_controller:sdram_|r.rf_counter[4] -To Node : sdram_controller:sdram_|r.rf_counter[8] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.648 - -Slack : 0.529 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.init_counter[5] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.650 - -Slack : 0.529 -From Node : sdram_controller:sdram_|r.init_counter[7] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.650 - -Slack : 0.529 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[13] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.650 - -Slack : 0.529 -From Node : sdram_controller:sdram_|r.init_counter[4] -To Node : sdram_controller:sdram_|r.init_counter[7] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.650 - -Slack : 0.530 -From Node : sdram_controller:sdram_|r.init_counter[8] -To Node : sdram_controller:sdram_|r.init_counter[11] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.651 - -Slack : 0.530 -From Node : sdram_controller:sdram_|r.init_counter[6] -To Node : sdram_controller:sdram_|r.init_counter[9] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.651 - -Slack : 0.531 -From Node : sdram_controller:sdram_|r.init_counter[1] -To Node : sdram_controller:sdram_|r.init_counter[4] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.652 - -Slack : 0.532 -From Node : sdram_controller:sdram_|r.init_counter[2] -To Node : sdram_controller:sdram_|r.init_counter[6] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.653 - -Slack : 0.532 -From Node : sdram_controller:sdram_|r.init_counter[7] -To Node : sdram_controller:sdram_|r.init_counter[10] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.653 - -Slack : 0.532 -From Node : sdram_controller:sdram_|r.init_counter[10] -To Node : sdram_controller:sdram_|r.init_counter[14] -Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.653 +--------------------------------------------------------------------------------+ @@ -35265,6 +35000,15 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 +Slack : 0.186 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + Slack : 0.186 From Node : ula:ula_|video:video_|vga_vc[9] To Node : ula:ula_|video:video_|vga_vc[9] @@ -35275,8 +35019,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -35301,15 +35045,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - Slack : 0.186 From Node : ula:ula_|video:video_|vga_vc[3] To Node : ula:ula_|video:video_|vga_vc[3] @@ -35320,8 +35055,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -35338,8 +35073,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[6] +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -35373,32 +35108,41 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.416 -Slack : 0.319 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.440 - -Slack : 0.368 +Slack : 0.300 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.489 +Data Delay : 0.421 -Slack : 0.418 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +Slack : 0.353 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.547 +Clock Skew : 0.037 +Data Delay : 0.474 + +Slack : 0.415 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.551 + +Slack : 0.418 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.539 Slack : 0.443 From Node : ula:ula_|video:video_|frame[2] @@ -35409,734 +35153,1664 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.564 -Slack : 0.457 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.577 - -Slack : 0.465 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.585 - -Slack : 0.481 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.425 - -Slack : 0.494 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.614 - -Slack : 0.520 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.641 - -Slack : 0.523 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.644 - -Slack : 0.531 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.651 - -Slack : 0.535 -From Node : ula:ula_|video:video_|vga_hc[8] +Slack : 0.447 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.655 +Clock Skew : 0.052 +Data Delay : 0.583 -Slack : 0.535 -From Node : ula:ula_|video:video_|vga_hc[7] +Slack : 0.447 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.655 +Clock Skew : 0.052 +Data Delay : 0.583 -Slack : 0.567 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.688 - -Slack : 0.593 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.537 - -Slack : 0.594 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.538 - -Slack : 0.594 -From Node : ula:ula_|video:video_|bits_prefetch[5] -To Node : ula:ula_|video:video_|bits[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.538 - -Slack : 0.603 +Slack : 0.451 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.723 +Clock Skew : 0.052 +Data Delay : 0.587 -Slack : 0.608 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.728 - -Slack : 0.613 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.732 - -Slack : 0.626 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vga_hc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.747 - -Slack : 0.634 -From Node : ula:ula_|video:video_|frame[0] +Slack : 0.453 +From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.578 +Clock Skew : 0.037 +Data Delay : 0.574 -Slack : 0.637 -From Node : ula:ula_|video:video_|frame[0] +Slack : 0.456 +From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.581 +Clock Skew : 0.037 +Data Delay : 0.577 -Slack : 0.637 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] +Slack : 0.459 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.580 + +Slack : 0.493 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.616 + +Slack : 0.506 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.757 +Data Delay : 0.626 -Slack : 0.648 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.511 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.767 +Clock Skew : 0.037 +Data Delay : 0.632 -Slack : 0.656 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.775 - -Slack : 0.656 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.775 - -Slack : 0.656 -From Node : ula:ula_|video:video_|vga_hc[6] +Slack : 0.545 +From Node : ula:ula_|video:video_|vga_hc[8] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.776 +Clock Skew : 0.052 +Data Delay : 0.681 -Slack : 0.659 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.778 - -Slack : 0.662 +Slack : 0.550 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vram_address[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.781 +Clock Skew : 0.041 +Data Delay : 0.675 -Slack : 0.664 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.608 - -Slack : 0.669 -From Node : ula:ula_|video:video_|bits_prefetch[7] -To Node : ula:ula_|video:video_|bits[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.613 - -Slack : 0.669 +Slack : 0.554 From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.788 - -Slack : 0.674 -From Node : ula:ula_|video:video_|attr_prefetch[6] -To Node : ula:ula_|video:video_|attr[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.604 - -Slack : 0.676 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.606 - -Slack : 0.679 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.609 - -Slack : 0.680 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.799 - -Slack : 0.683 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.802 - -Slack : 0.686 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.616 - -Slack : 0.686 -From Node : ula:ula_|video:video_|attr_prefetch[1] -To Node : ula:ula_|video:video_|attr[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.616 - -Slack : 0.689 -From Node : ula:ula_|video:video_|vga_vc[7] To Node : ula:ula_|video:video_|vram_address[11] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.808 +Clock Skew : 0.041 +Data Delay : 0.679 -Slack : 0.689 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vram_address[8] +Slack : 0.578 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.808 +Clock Skew : -0.142 +Data Delay : 0.520 -Slack : 0.697 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] +Slack : 0.606 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.627 +Clock Skew : 0.036 +Data Delay : 0.726 -Slack : 0.701 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.820 - -Slack : 0.705 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.824 - -Slack : 0.711 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.830 - -Slack : 0.714 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.833 - -Slack : 0.717 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.838 - -Slack : 0.717 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.838 - -Slack : 0.746 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.865 - -Slack : 0.748 +Slack : 0.607 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.869 +Data Delay : 0.728 -Slack : 0.749 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Slack : 0.631 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.869 +Clock Skew : 0.043 +Data Delay : 0.758 -Slack : 0.754 -From Node : ula:ula_|video:video_|bits_prefetch[3] -To Node : ula:ula_|video:video_|bits[3] +Slack : 0.643 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.698 +Clock Skew : -0.127 +Data Delay : 0.600 -Slack : 0.760 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.647 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.879 +Clock Skew : -0.142 +Data Delay : 0.589 -Slack : 0.763 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.882 - -Slack : 0.765 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.695 - -Slack : 0.773 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.894 - -Slack : 0.776 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.897 - -Slack : 0.777 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.896 - -Slack : 0.797 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.916 - -Slack : 0.797 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.916 - -Slack : 0.801 +Slack : 0.660 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.922 +Data Delay : 0.781 -Slack : 0.815 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.934 - -Slack : 0.825 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.945 - -Slack : 0.826 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.945 - -Slack : 0.827 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.948 - -Slack : 0.837 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.958 - -Slack : 0.837 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.958 - -Slack : 0.849 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.140 -Data Delay : 0.793 - -Slack : 0.857 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.977 - -Slack : 0.859 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.980 - -Slack : 0.859 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.980 - -Slack : 0.859 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.980 - -Slack : 0.859 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.980 - -Slack : 0.859 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.980 - -Slack : 0.859 +Slack : 0.661 From Node : ula:ula_|video:video_|vga_hc[8] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.979 +Clock Skew : 0.052 +Data Delay : 0.797 -Slack : 0.860 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 0.662 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.035 -Data Delay : 0.979 +Clock Skew : 0.041 +Data Delay : 0.787 -Slack : 0.875 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.996 - -Slack : 0.881 +Slack : 0.673 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 1.002 +Data Delay : 0.794 -Slack : 0.885 -From Node : ula:ula_|video:video_|vga_hc[3] +Slack : 0.678 +From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vga_hc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 1.006 +Clock Skew : 0.041 +Data Delay : 0.803 -Slack : 0.886 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[4] +Slack : 0.678 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 1.007 +Data Delay : 0.799 -Slack : 0.888 +Slack : 0.686 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.811 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.824 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.824 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.824 + +Slack : 0.703 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.824 + +Slack : 0.706 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.142 +Data Delay : 0.648 + +Slack : 0.710 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.846 + +Slack : 0.716 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.852 + +Slack : 0.719 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.844 + +Slack : 0.719 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.844 + +Slack : 0.720 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.845 + +Slack : 0.721 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 0.857 + +Slack : 0.724 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.127 +Data Delay : 0.681 + +Slack : 0.726 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.127 +Data Delay : 0.683 + +Slack : 0.734 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.855 + +Slack : 0.736 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.861 + +Slack : 0.739 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.860 + +Slack : 0.743 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.864 + +Slack : 0.756 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.876 + +Slack : 0.758 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.142 +Data Delay : 0.700 + +Slack : 0.775 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.900 + +Slack : 0.791 From Node : ula:ula_|video:video_|vga_hc[8] To Node : ula:ula_|video:video_|vga_hc[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 1.008 +Clock Skew : 0.052 +Data Delay : 0.927 -Slack : 0.888 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 1.008 - -Slack : 0.894 +Slack : 0.829 From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|bits_prefetch[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.038 -Data Delay : 1.016 +Clock Skew : 0.228 +Data Delay : 1.141 -Slack : 0.899 +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|bits_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.228 +Data Delay : 1.141 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.949 + +Slack : 0.830 From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|attr[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 1.020 +Data Delay : 0.951 + +Slack : 0.830 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.951 + +Slack : 0.833 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.954 + +Slack : 0.835 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 0.960 + +Slack : 0.846 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.966 + +Slack : 0.849 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.970 + +Slack : 0.849 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.970 + +Slack : 0.849 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.970 + +Slack : 0.849 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.970 + +Slack : 0.849 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.970 + +Slack : 0.858 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.978 + +Slack : 0.860 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.127 +Data Delay : 0.817 + +Slack : 0.860 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.980 + +Slack : 0.863 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.984 + +Slack : 0.872 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.993 + +Slack : 0.873 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vga_hc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.993 + +Slack : 0.877 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.052 +Data Delay : 1.013 + +Slack : 0.879 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 1.004 + +Slack : 0.882 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.002 + +Slack : 0.894 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 1.019 + +Slack : 0.907 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.142 +Data Delay : 0.849 + +Slack : 0.908 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 1.033 + +Slack : 0.909 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 1.034 + +Slack : 0.909 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 1.034 + +Slack : 0.909 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.041 +Data Delay : 1.034 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.186 +From Node : ula:ula_|clocks:clocks_|clk_cpu +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.193 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|counter[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.416 +From Node : ula:ula_|clocks:clocks_|counter[0] +To Node : ula:ula_|clocks:clocks_|clk_cpu +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Relationship : 0.000 +Clock Skew : 0.042 +Data Delay : 0.542 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.201 +From Node : debouncer:debounce_autofire|r_State +To Node : debouncer:debounce_autofire|r_State +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.022 +Data Delay : 0.307 + +Slack : 0.201 +From Node : debouncer:debounce_turbo|r_State +To Node : debouncer:debounce_turbo|r_State +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.022 +Data Delay : 0.307 + +Slack : 0.205 +From Node : debouncer:debounce_turbo|r_Count[20] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.325 + +Slack : 0.205 +From Node : debouncer:debounce_autofire|r_Count[20] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.325 + +Slack : 0.298 +From Node : debouncer:debounce_autofire|r_Count[3] +To Node : debouncer:debounce_autofire|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.418 + +Slack : 0.299 +From Node : debouncer:debounce_turbo|r_Count[1] +To Node : debouncer:debounce_turbo|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : debouncer:debounce_turbo|r_Count[3] +To Node : debouncer:debounce_turbo|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : debouncer:debounce_autofire|r_Count[1] +To Node : debouncer:debounce_autofire|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : debouncer:debounce_autofire|r_Count[19] +To Node : debouncer:debounce_autofire|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.300 +From Node : debouncer:debounce_turbo|r_Count[19] +To Node : debouncer:debounce_turbo|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_turbo|r_Count[9] +To Node : debouncer:debounce_turbo|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_turbo|r_Count[17] +To Node : debouncer:debounce_turbo|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_autofire|r_Count[9] +To Node : debouncer:debounce_autofire|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : debouncer:debounce_autofire|r_Count[17] +To Node : debouncer:debounce_autofire|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.301 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.421 + +Slack : 0.302 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.302 +From Node : debouncer:debounce_turbo|r_Count[15] +To Node : debouncer:debounce_turbo|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.302 +From Node : debouncer:debounce_autofire|r_Count[15] +To Node : debouncer:debounce_autofire|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.302 +From Node : debouncer:debounce_autofire|r_Count[5] +To Node : debouncer:debounce_autofire|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.302 +From Node : debouncer:debounce_autofire|r_Count[7] +To Node : debouncer:debounce_autofire|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.302 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.302 +From Node : debouncer:debounce_autofire|r_Count[13] +To Node : debouncer:debounce_autofire|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.422 + +Slack : 0.303 +From Node : debouncer:debounce_turbo|r_Count[13] +To Node : debouncer:debounce_turbo|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.423 + +Slack : 0.303 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.423 + +Slack : 0.304 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.424 + +Slack : 0.304 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.424 + +Slack : 0.305 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.305 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.306 +From Node : debouncer:debounce_turbo|r_Count[10] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.426 + +Slack : 0.306 +From Node : debouncer:debounce_autofire|r_Count[10] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.426 + +Slack : 0.308 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.428 + +Slack : 0.308 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.428 + +Slack : 0.309 +From Node : debouncer:debounce_turbo|r_Count[5] +To Node : debouncer:debounce_turbo|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.429 + +Slack : 0.309 +From Node : debouncer:debounce_turbo|r_Count[7] +To Node : debouncer:debounce_turbo|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.429 + +Slack : 0.309 +From Node : debouncer:debounce_turbo|r_Count[11] +To Node : debouncer:debounce_turbo|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.429 + +Slack : 0.309 +From Node : debouncer:debounce_autofire|r_Count[11] +To Node : debouncer:debounce_autofire|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.429 + +Slack : 0.310 +From Node : debouncer:debounce_turbo|r_Count[6] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.430 + +Slack : 0.447 +From Node : debouncer:debounce_autofire|r_Count[3] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.567 + +Slack : 0.448 +From Node : debouncer:debounce_turbo|r_Count[1] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.448 +From Node : debouncer:debounce_turbo|r_Count[3] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.448 +From Node : debouncer:debounce_autofire|r_Count[19] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.448 +From Node : debouncer:debounce_autofire|r_Count[1] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.449 +From Node : debouncer:debounce_turbo|r_Count[19] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.569 + +Slack : 0.449 +From Node : debouncer:debounce_turbo|r_Count[17] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.569 + +Slack : 0.449 +From Node : debouncer:debounce_autofire|r_Count[17] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.569 + +Slack : 0.449 +From Node : debouncer:debounce_autofire|r_Count[9] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.569 + +Slack : 0.451 +From Node : debouncer:debounce_turbo|r_Count[15] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.571 + +Slack : 0.451 +From Node : debouncer:debounce_turbo|r_Count[9] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.034 +Data Delay : 0.569 + +Slack : 0.451 +From Node : debouncer:debounce_autofire|r_Count[15] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.571 + +Slack : 0.451 +From Node : debouncer:debounce_autofire|r_Count[7] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.571 + +Slack : 0.451 +From Node : debouncer:debounce_autofire|r_Count[5] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.571 + +Slack : 0.451 +From Node : debouncer:debounce_autofire|r_Count[13] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.571 + +Slack : 0.452 +From Node : debouncer:debounce_turbo|r_Count[13] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.572 + +Slack : 0.457 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.577 + +Slack : 0.457 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.577 + +Slack : 0.457 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.577 + +Slack : 0.458 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_turbo|r_Count[7] +To Node : debouncer:debounce_turbo|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_turbo|r_Count[11] +To Node : debouncer:debounce_turbo|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_turbo|r_Count[5] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : debouncer:debounce_autofire|r_Count[11] +To Node : debouncer:debounce_autofire|r_Count[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.459 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.579 + +Slack : 0.460 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.580 + +Slack : 0.460 +From Node : debouncer:debounce_turbo|r_Count[0] +To Node : debouncer:debounce_turbo|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.580 + +Slack : 0.460 +From Node : debouncer:debounce_turbo|r_Count[2] +To Node : debouncer:debounce_turbo|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.580 + +Slack : 0.460 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.580 + +Slack : 0.460 +From Node : debouncer:debounce_autofire|r_Count[0] +To Node : debouncer:debounce_autofire|r_Count[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.580 + +Slack : 0.461 +From Node : debouncer:debounce_turbo|r_Count[18] +To Node : debouncer:debounce_turbo|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : debouncer:debounce_turbo|r_Count[16] +To Node : debouncer:debounce_turbo|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : debouncer:debounce_turbo|r_Count[4] +To Node : debouncer:debounce_turbo|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : debouncer:debounce_autofire|r_Count[2] +To Node : debouncer:debounce_autofire|r_Count[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : debouncer:debounce_autofire|r_Count[16] +To Node : debouncer:debounce_autofire|r_Count[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : debouncer:debounce_autofire|r_Count[4] +To Node : debouncer:debounce_autofire|r_Count[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.462 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.582 + +Slack : 0.462 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.582 + +Slack : 0.462 +From Node : debouncer:debounce_autofire|r_Count[18] +To Node : debouncer:debounce_autofire|r_Count[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.582 + +Slack : 0.463 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.583 + +Slack : 0.463 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.583 + +Slack : 0.463 +From Node : debouncer:debounce_autofire|r_Count[8] +To Node : debouncer:debounce_autofire|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.583 + +Slack : 0.464 +From Node : debouncer:debounce_turbo|r_Count[10] +To Node : debouncer:debounce_turbo|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.584 + +Slack : 0.464 +From Node : debouncer:debounce_autofire|r_Count[10] +To Node : debouncer:debounce_autofire|r_Count[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.584 + +Slack : 0.464 +From Node : debouncer:debounce_autofire|r_Count[6] +To Node : debouncer:debounce_autofire|r_Count[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.584 + +Slack : 0.465 +From Node : debouncer:debounce_turbo|r_Count[8] +To Node : debouncer:debounce_turbo|r_Count[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.034 +Data Delay : 0.583 + +Slack : 0.465 +From Node : debouncer:debounce_turbo|r_Count[12] +To Node : debouncer:debounce_turbo|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.585 + +Slack : 0.465 +From Node : debouncer:debounce_autofire|r_Count[12] +To Node : debouncer:debounce_autofire|r_Count[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.585 + +Slack : 0.466 +From Node : debouncer:debounce_turbo|r_Count[14] +To Node : debouncer:debounce_turbo|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.586 + +Slack : 0.466 +From Node : debouncer:debounce_autofire|r_Count[14] +To Node : debouncer:debounce_autofire|r_Count[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.586 +--------------------------------------------------------------------------------+ @@ -36189,14 +36863,14 @@ Relationship : 0.424 Clock Skew : -0.228 Data Delay : 2.778 -Slack : -4.566 +Slack : -4.572 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 2.642 +Data Delay : 2.648 Slack : -4.566 From Node : KEY[0] @@ -36207,167 +36881,401 @@ Relationship : 0.424 Clock Skew : -0.251 Data Delay : 2.639 -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.571 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.571 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.571 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.571 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.571 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.571 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.563 - -Slack : -4.421 +Slack : -4.427 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.563 +Clock Skew : -0.226 +Data Delay : 2.572 -Slack : -4.421 +Slack : -4.427 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.563 +Clock Skew : -0.226 +Data Delay : 2.572 -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.224 -Data Delay : 2.568 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.224 -Data Delay : 2.568 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.563 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.563 - -Slack : -4.421 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.563 - -Slack : -4.420 +Slack : -4.427 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.565 +Data Delay : 2.572 -Slack : -4.420 +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.225 +Data Delay : 2.573 + +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.572 + +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.572 + +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.225 +Data Delay : 2.573 + +Slack : -4.427 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.565 +Data Delay : 2.572 -Slack : -4.420 +Slack : -4.427 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.565 +Data Delay : 2.572 -Slack : -4.420 +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.225 +Data Delay : 2.573 + +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.225 +Data Delay : 2.573 + +Slack : -4.427 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.225 +Data Delay : 2.573 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.426 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.236 +Data Delay : 2.561 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.223 +Data Delay : 2.569 Slack : -4.420 From Node : KEY[0] @@ -36375,116 +37283,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.562 - -Slack : -4.420 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.565 +Clock Skew : -0.231 +Data Delay : 2.560 Slack : -4.420 From Node : KEY[0] @@ -36492,8 +37292,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 +Clock Skew : -0.231 +Data Delay : 2.560 Slack : -4.420 From Node : KEY[0] @@ -36501,8 +37301,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 +Clock Skew : -0.231 +Data Delay : 2.560 Slack : -4.420 From Node : KEY[0] @@ -36510,188 +37310,98 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.221 -Data Delay : 2.570 +Clock Skew : -0.231 +Data Delay : 2.560 -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.417 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.215 -Data Delay : 2.573 - -Slack : -4.233 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.565 - -Slack : -4.233 +Slack : -4.249 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.565 +Clock Skew : -0.049 +Data Delay : 2.571 -Slack : -4.233 +Slack : -4.249 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.565 +Clock Skew : -0.049 +Data Delay : 2.571 -Slack : -4.233 +Slack : -4.249 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.565 +Clock Skew : -0.049 +Data Delay : 2.571 -Slack : -4.233 +Slack : -4.249 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.565 +Clock Skew : -0.049 +Data Delay : 2.571 + +Slack : -4.249 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.049 +Data Delay : 2.571 + +Slack : -4.247 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.049 +Data Delay : 2.569 + +Slack : -4.237 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.572 + +Slack : -4.237 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.572 + +Slack : -4.237 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.572 + +Slack : -4.237 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.045 +Data Delay : 2.563 Slack : -4.232 From Node : KEY[0] @@ -36699,8 +37409,26 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.036 -Data Delay : 2.567 +Clock Skew : -0.034 +Data Delay : 2.569 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.034 +Data Delay : 2.569 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.034 +Data Delay : 2.569 Slack : -4.232 From Node : KEY[0] @@ -36708,8 +37436,35 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.036 -Data Delay : 2.567 +Clock Skew : -0.034 +Data Delay : 2.569 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.034 +Data Delay : 2.569 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.034 +Data Delay : 2.569 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.034 +Data Delay : 2.569 Slack : -4.232 From Node : KEY[0] @@ -36717,57 +37472,21 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.036 -Data Delay : 2.567 +Clock Skew : -0.034 +Data Delay : 2.569 -Slack : -4.231 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.035 -Data Delay : 2.567 - -Slack : -4.231 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.035 -Data Delay : 2.567 - -Slack : -4.231 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.035 -Data Delay : 2.567 - -Slack : -4.231 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.035 -Data Delay : 2.567 - -Slack : -4.231 +Slack : -4.232 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.036 -Data Delay : 2.566 +Clock Skew : -0.034 +Data Delay : 2.569 Slack : -4.231 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 @@ -36776,111 +37495,66 @@ Data Delay : 2.568 Slack : -4.231 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.573 +Clock Skew : -0.044 +Data Delay : 2.558 -Slack : -4.227 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.569 - -Slack : -4.221 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.025 -Data Delay : 2.567 - -Slack : -4.221 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.025 -Data Delay : 2.567 - -Slack : -4.220 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.026 -Data Delay : 2.565 - -Slack : -4.220 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.026 -Data Delay : 2.565 - -Slack : -4.193 +Slack : -4.192 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.563 +Data Delay : 2.562 -Slack : -4.193 +Slack : -4.192 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.563 +Data Delay : 2.562 -Slack : -4.193 +Slack : -4.192 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.563 +Data Delay : 2.562 -Slack : -4.193 +Slack : -4.192 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.563 +Data Delay : 2.562 -Slack : -4.193 +Slack : -4.192 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.563 +Data Delay : 2.562 -Slack : -4.193 +Slack : -4.192 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.563 +Data Delay : 2.562 +--------------------------------------------------------------------------------+ @@ -36942,67 +37616,13 @@ Relationship : -0.003 Clock Skew : 0.257 Data Delay : 1.935 -Slack : 2.541 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.228 -Data Delay : 1.937 - -Slack : 2.541 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.228 -Data Delay : 1.937 - -Slack : 2.542 +Slack : 2.553 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.229 -Data Delay : 1.939 - -Slack : 2.542 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.229 -Data Delay : 1.939 - -Slack : 2.548 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.940 - -Slack : 2.551 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.943 - -Slack : 2.552 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.219 +Clock Skew : 0.218 Data Delay : 1.939 Slack : 2.553 @@ -37011,8 +37631,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 Slack : 2.553 From Node : KEY[0] @@ -37020,8 +37640,17 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.219 +Data Delay : 1.940 Slack : 2.553 From Node : KEY[0] @@ -37029,8 +37658,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 Slack : 2.553 From Node : KEY[0] @@ -37038,8 +37667,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 Slack : 2.553 From Node : KEY[0] @@ -37047,8 +37676,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 Slack : 2.553 From Node : KEY[0] @@ -37056,8 +37685,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 Slack : 2.553 From Node : KEY[0] @@ -37065,305 +37694,242 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.217 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 -Slack : 2.554 +Slack : 2.553 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.216 -Data Delay : 1.938 +Clock Skew : 0.219 +Data Delay : 1.940 -Slack : 2.556 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.937 - -Slack : 2.556 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.937 - -Slack : 2.556 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.937 - -Slack : 2.556 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.937 - -Slack : 2.556 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.937 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 - -Slack : 2.745 +Slack : 2.554 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 +Clock Skew : 0.208 +Data Delay : 1.930 -Slack : 2.745 +Slack : 2.560 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.030 -Data Delay : 1.943 +Clock Skew : 0.216 +Data Delay : 1.944 -Slack : 2.750 +Slack : 2.560 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.942 +Clock Skew : 0.216 +Data Delay : 1.944 -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.942 - -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.942 - -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.942 - -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.942 - -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.024 -Data Delay : 1.942 - -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.021 -Data Delay : 1.939 - -Slack : 2.750 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.021 -Data Delay : 1.939 - -Slack : 2.751 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.937 - -Slack : 2.751 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.937 - -Slack : 2.751 +Slack : 2.560 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.937 +Clock Skew : 0.216 +Data Delay : 1.944 -Slack : 2.751 +Slack : 2.562 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 +Clock Skew : 0.207 +Data Delay : 1.937 + +Slack : 2.569 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.203 +Data Delay : 1.940 + +Slack : 2.573 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.203 +Data Delay : 1.944 + +Slack : 2.573 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.203 +Data Delay : 1.944 + +Slack : 2.573 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.203 +Data Delay : 1.944 + +Slack : 2.573 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.203 +Data Delay : 1.944 + +Slack : 2.573 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.203 +Data Delay : 1.944 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 + +Slack : 2.750 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.022 +Data Delay : 1.940 Slack : 2.751 From Node : KEY[0] @@ -37371,39 +37937,12 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 +Clock Skew : 0.013 +Data Delay : 1.932 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 - -Slack : 2.751 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 - -Slack : 2.751 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 - -Slack : 2.751 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -37412,7 +37951,7 @@ Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -37421,7 +37960,7 @@ Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -37430,7 +37969,7 @@ Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -37439,7 +37978,7 @@ Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -37448,7 +37987,7 @@ Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 @@ -37457,12 +37996,21 @@ Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.937 +Clock Skew : 0.016 +Data Delay : 1.935 + +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.935 Slack : 2.751 From Node : KEY[0] @@ -37470,8 +38018,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 +Clock Skew : 0.013 +Data Delay : 1.932 Slack : 2.751 From Node : KEY[0] @@ -37479,8 +38027,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 +Clock Skew : 0.013 +Data Delay : 1.932 Slack : 2.751 From Node : KEY[0] @@ -37488,89 +38036,206 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.023 -Data Delay : 1.942 +Clock Skew : 0.013 +Data Delay : 1.932 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.752 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.935 +Clock Skew : 0.008 +Data Delay : 1.934 -Slack : 2.884 +Slack : 2.758 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : -0.016 -Data Delay : 2.010 +Clock Skew : 0.008 +Data Delay : 1.934 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.008 +Data Delay : 1.934 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.758 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.944 + +Slack : 2.759 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.020 +Data Delay : 1.947 + +Slack : 2.759 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.020 +Data Delay : 1.947 + +Slack : 2.759 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.020 +Data Delay : 1.947 + +Slack : 2.759 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.020 +Data Delay : 1.947 + +Slack : 2.759 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.020 +Data Delay : 1.947 Slack : 2.886 From Node : KEY[0] @@ -37581,6 +38246,15 @@ Relationship : -0.006 Clock Skew : -0.019 Data Delay : 2.009 +Slack : 2.891 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : -0.016 +Data Delay : 2.017 + Slack : 2.997 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] @@ -37632,13 +38306,53 @@ Data Delay : 2.142 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 4.783 -Actual Width : 4.999 +Slack : 4.784 +Actual Width : 5.000 Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[3] +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 Slack : 4.784 Actual Width : 5.000 @@ -37696,6 +38410,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[2] +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + Slack : 4.784 Actual Width : 5.000 Required Width : 0.216 @@ -37760,6 +38482,38 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.state[4] +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + Slack : 4.784 Actual Width : 5.000 Required Width : 0.216 @@ -37774,7 +38528,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[0] +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 Slack : 4.785 Actual Width : 5.001 @@ -37782,7 +38536,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[1] +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 Slack : 4.785 Actual Width : 5.001 @@ -37790,7 +38544,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[2] +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 Slack : 4.785 Actual Width : 5.001 @@ -37798,7 +38552,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[3] +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 Slack : 4.785 Actual Width : 5.001 @@ -37806,7 +38560,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[4] +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 Slack : 4.785 Actual Width : 5.001 @@ -37814,7 +38568,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Target : sdram_controller:sdram_|r.init_counter[0] Slack : 4.785 Actual Width : 5.001 @@ -37904,134 +38658,6 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.rf_pending -Slack : 4.785 -Actual Width : 5.001 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[5] - -Slack : 4.785 -Actual Width : 5.001 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[6] - -Slack : 4.785 -Actual Width : 5.001 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[7] - -Slack : 4.785 -Actual Width : 5.001 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[8] - -Slack : 4.787 -Actual Width : 5.003 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 - -Slack : 4.787 -Actual Width : 5.003 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 - -Slack : 4.787 -Actual Width : 5.003 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 - -Slack : 4.787 -Actual Width : 5.003 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[0] - -Slack : 4.788 -Actual Width : 5.004 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 - -Slack : 4.788 -Actual Width : 5.004 -Required Width : 0.216 -Type : High Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 - -Slack : 4.810 -Actual Width : 4.994 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 - -Slack : 4.810 -Actual Width : 4.994 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 - -Slack : 4.810 -Actual Width : 4.994 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 - -Slack : 4.810 -Actual Width : 4.994 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 - -Slack : 4.810 -Actual Width : 4.994 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[0] - -Slack : 4.811 -Actual Width : 4.995 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 - Slack : 4.812 Actual Width : 4.996 Required Width : 0.184 @@ -38126,7 +38752,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[0] +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 Slack : 4.813 Actual Width : 4.997 @@ -38134,7 +38760,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[1] +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 Slack : 4.813 Actual Width : 4.997 @@ -38142,23 +38768,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[2] - -Slack : 4.813 -Actual Width : 4.997 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[3] - -Slack : 4.813 -Actual Width : 4.997 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.act_row[4] +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 Slack : 4.813 Actual Width : 4.997 @@ -38168,6 +38778,86 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + Slack : 4.813 Actual Width : 4.997 Required Width : 0.184 @@ -38176,6 +38866,54 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.init_counter[3] +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + Slack : 4.813 Actual Width : 4.997 Required Width : 0.184 @@ -38184,6 +38922,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.rd_pending +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + Slack : 4.813 Actual Width : 4.997 Required Width : 0.184 @@ -38230,7 +38976,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[10] +Target : sdram_controller:sdram_|r.act_row[0] Slack : 4.814 Actual Width : 4.998 @@ -38238,7 +38984,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[11] +Target : sdram_controller:sdram_|r.act_row[1] Slack : 4.814 Actual Width : 4.998 @@ -38246,7 +38992,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[12] +Target : sdram_controller:sdram_|r.act_row[2] Slack : 4.814 Actual Width : 4.998 @@ -38254,7 +39000,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[13] +Target : sdram_controller:sdram_|r.act_row[3] Slack : 4.814 Actual Width : 4.998 @@ -38262,103 +39008,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[14] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[1] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[2] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[4] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[5] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[6] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[7] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[8] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.init_counter[9] - -Slack : 4.814 -Actual Width : 4.998 -Required Width : 0.184 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[4] - -Slack : 4.815 -Actual Width : 4.970 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.address[11] - -Slack : 4.815 -Actual Width : 4.970 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[1] - -Slack : 4.815 -Actual Width : 4.970 -Required Width : 0.155 -Type : Low Pulse Width -Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : sdram_controller:sdram_|r.state[2] +Target : sdram_controller:sdram_|r.act_row[4] Slack : 4.817 Actual Width : 4.972 @@ -38400,6 +39050,14 @@ Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0 Clock Edge : Rise Target : sdram_controller:sdram_|r.state[0] +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + Slack : 4.818 Actual Width : 4.973 Required Width : 0.155 @@ -38431,6 +39089,22 @@ Type : Low Pulse Width Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : sdram_controller:sdram_|r.bank[0] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] +--------------------------------------------------------------------------------+ @@ -38444,7 +39118,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -38452,7 +39126,39 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -38476,7 +39182,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -38484,7 +39190,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -38492,7 +39198,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -38500,7 +39206,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -38508,7 +39214,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -38516,23 +39222,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg - -Slack : 9.208 -Actual Width : 9.438 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.208 -Actual Width : 9.438 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -38572,7 +39262,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -38580,7 +39270,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -38588,7 +39278,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -38596,7 +39286,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -38614,22 +39304,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -38652,7 +39326,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -38660,7 +39334,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -38684,7 +39374,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -38692,7 +39382,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -38732,7 +39438,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 Slack : 9.209 Actual Width : 9.439 @@ -38764,7 +39470,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : 9.209 Actual Width : 9.439 @@ -38772,15 +39478,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : 9.209 Actual Width : 9.439 @@ -38796,7 +39494,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38804,7 +39502,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38812,23 +39510,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38844,7 +39526,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38852,7 +39534,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38860,7 +39542,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38870,6 +39560,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + Slack : 9.210 Actual Width : 9.440 Required Width : 0.230 @@ -38902,22 +39600,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - Slack : 9.210 Actual Width : 9.440 Required Width : 0.230 @@ -38948,23 +39630,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -38974,6 +39640,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 + Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -38996,7 +39686,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -39004,23 +39694,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 - -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 - -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -39030,14 +39704,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 - Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -39052,7 +39718,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -39068,7 +39742,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : 9.211 Actual Width : 9.441 @@ -39078,13 +39760,21 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + Slack : 9.212 Actual Width : 9.442 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 Slack : 9.212 Actual Width : 9.442 @@ -39108,7 +39798,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 Slack : 9.212 Actual Width : 9.442 @@ -39116,7 +39806,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -39124,7 +39814,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 Slack : 9.212 Actual Width : 9.442 @@ -39132,7 +39822,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -39140,7 +39830,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -39166,6 +39864,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 + Slack : 9.212 Actual Width : 9.442 Required Width : 0.230 @@ -39189,54 +39911,6 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 - -Slack : 9.212 -Actual Width : 9.442 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 - -Slack : 9.212 -Actual Width : 9.442 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 - -Slack : 9.212 -Actual Width : 9.442 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 - -Slack : 9.212 -Actual Width : 9.442 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 - -Slack : 9.212 -Actual Width : 9.442 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 - -Slack : 9.213 -Actual Width : 9.443 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +--------------------------------------------------------------------------------+ @@ -39250,7 +39924,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -39258,7 +39932,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -39266,7 +39940,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -39274,7 +39948,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -39298,7 +39972,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -39306,7 +39980,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -39314,7 +39988,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -39322,39 +39996,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -39378,15 +40020,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 Slack : 19.610 Actual Width : 19.840 @@ -39442,7 +40076,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -39466,7 +40108,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -39490,7 +40140,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 Slack : 19.610 Actual Width : 19.840 @@ -39498,7 +40148,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -39516,14 +40174,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 - Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -39538,7 +40188,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -39546,7 +40196,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -39570,31 +40236,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 Slack : 19.610 Actual Width : 19.840 @@ -39628,6 +40270,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -39666,7 +40324,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -39674,7 +40332,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 Slack : 19.610 Actual Width : 19.840 @@ -39692,22 +40358,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg - Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -39746,7 +40396,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -39770,7 +40428,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -39802,7 +40460,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 Slack : 19.611 Actual Width : 19.841 @@ -39818,7 +40476,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 Slack : 19.611 Actual Width : 19.841 @@ -39834,7 +40492,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -39842,7 +40500,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 Slack : 19.611 Actual Width : 19.841 @@ -39850,7 +40508,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 Slack : 19.611 Actual Width : 19.841 @@ -39866,7 +40524,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 Slack : 19.611 Actual Width : 19.841 @@ -39874,7 +40532,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 Slack : 19.611 Actual Width : 19.841 @@ -39890,7 +40548,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0 Slack : 19.611 Actual Width : 19.841 @@ -39898,7 +40556,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -39906,7 +40564,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 Slack : 19.611 Actual Width : 19.841 @@ -39914,7 +40572,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -39954,7 +40620,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 Slack : 19.611 Actual Width : 19.841 @@ -39978,23 +40644,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -40010,7 +40660,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -40034,7 +40692,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 Slack : 19.612 Actual Width : 19.842 @@ -40043,6 +40701,22 @@ Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 19.612 +Actual Width : 19.842 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 19.612 +Actual Width : 19.842 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +--------------------------------------------------------------------------------+ @@ -40098,6 +40772,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -40136,7 +40818,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] Slack : 20.633 Actual Width : 20.849 @@ -40144,7 +40826,47 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop Slack : 20.633 Actual Width : 20.849 @@ -40258,21 +40980,117 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.634 -Actual Width : 20.850 +Slack : 20.633 +Actual Width : 20.849 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.634 -Actual Width : 20.850 +Slack : 20.633 +Actual Width : 20.849 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.634 Actual Width : 20.850 @@ -40338,414 +41156,270 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Slack : 20.634 -Actual Width : 20.850 +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.648 +Actual Width : 20.864 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Data +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.634 -Actual Width : 20.850 +Slack : 20.650 +Actual Width : 20.866 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.650 +Actual Width : 20.834 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.650 +Actual Width : 20.866 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.650 +Actual Width : 20.834 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.650 +Actual Width : 20.866 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.650 +Actual Width : 20.834 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.650 +Actual Width : 20.866 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.650 +Actual Width : 20.834 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.650 +Actual Width : 20.866 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.650 +Actual Width : 20.834 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.652 +Actual Width : 20.836 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 + +Slack : 20.657 +Actual Width : 20.873 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Slack : 20.634 -Actual Width : 20.850 +Slack : 20.657 +Actual Width : 20.873 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Slack : 20.634 -Actual Width : 20.850 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Start - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.636 -Actual Width : 20.852 +Slack : 20.657 +Actual Width : 20.873 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Slack : 20.636 -Actual Width : 20.852 +Slack : 20.657 +Actual Width : 20.873 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.636 -Actual Width : 20.852 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.639 -Actual Width : 20.823 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.639 -Actual Width : 20.823 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - -Slack : 20.640 -Actual Width : 20.824 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack - -Slack : 20.640 -Actual Width : 20.824 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop - -Slack : 20.640 -Actual Width : 20.824 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] - -Slack : 20.642 -Actual Width : 20.826 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] - -Slack : 20.645 -Actual Width : 20.829 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.647 -Actual Width : 20.831 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.652 -Actual Width : 20.868 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - -Slack : 20.655 -Actual Width : 20.871 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] - -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] - -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] - -Slack : 20.657 -Actual Width : 20.873 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - Slack : 20.658 Actual Width : 20.874 Required Width : 0.216 @@ -40754,6 +41428,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Slack : 20.658 +Actual Width : 20.874 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.658 +Actual Width : 20.874 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + Slack : 20.658 Actual Width : 20.874 Required Width : 0.216 @@ -40762,6 +41452,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Slack : 20.658 +Actual Width : 20.874 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.658 +Actual Width : 20.874 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.658 +Actual Width : 20.874 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + Slack : 20.658 Actual Width : 20.874 Required Width : 0.216 @@ -40770,85 +41484,45 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.660 -Actual Width : 20.876 +Slack : 20.658 +Actual Width : 20.874 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.661 -Actual Width : 20.877 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack - -Slack : 20.661 -Actual Width : 20.877 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop - -Slack : 20.661 -Actual Width : 20.877 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.661 -Actual Width : 20.877 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - -Slack : 20.664 -Actual Width : 20.848 +Slack : 20.667 +Actual Width : 20.851 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.664 -Actual Width : 20.848 +Slack : 20.667 +Actual Width : 20.851 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Slack : 20.664 -Actual Width : 20.848 +Slack : 20.667 +Actual Width : 20.851 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Slack : 20.664 -Actual Width : 20.848 +Slack : 20.667 +Actual Width : 20.851 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.664 -Actual Width : 20.848 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +--------------------------------------------------------------------------------+ @@ -40856,53 +41530,37 @@ Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : 35.535 -Actual Width : 35.719 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula:ula_|clocks:clocks_|clk_cpu - -Slack : 35.535 -Actual Width : 35.719 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula:ula_|clocks:clocks_|counter[0] - -Slack : 35.552 -Actual Width : 35.768 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula:ula_|clocks:clocks_|clk_cpu - -Slack : 35.552 -Actual Width : 35.768 +Slack : 35.525 +Actual Width : 35.741 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula:ula_|clocks:clocks_|counter[0] -Slack : 35.715 -Actual Width : 35.715 -Required Width : 0.000 -Type : Low Pulse Width +Slack : 35.526 +Actual Width : 35.742 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise -Target : ula_|clocks_|clk_cpu|clk +Target : ula:ula_|clocks:clocks_|clk_cpu -Slack : 35.715 -Actual Width : 35.715 -Required Width : 0.000 +Slack : 35.562 +Actual Width : 35.746 +Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise -Target : ula_|clocks_|counter[0]|clk +Target : ula:ula_|clocks:clocks_|clk_cpu + +Slack : 35.563 +Actual Width : 35.747 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula:ula_|clocks:clocks_|counter[0] Slack : 35.739 Actual Width : 35.739 @@ -40920,6 +41578,38 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk +Slack : 35.741 +Actual Width : 35.741 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + +Slack : 35.742 +Actual Width : 35.742 +Required Width : 0.000 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.746 +Actual Width : 35.746 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|counter[0]|clk + +Slack : 35.747 +Actual Width : 35.747 +Required Width : 0.000 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Edge : Rise +Target : ula_|clocks_|clk_cpu|clk + Slack : 35.749 Actual Width : 35.749 Required Width : 0.000 @@ -40936,22 +41626,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Clock Edge : Rise Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk -Slack : 35.774 -Actual Width : 35.774 -Required Width : 0.000 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula_|clocks_|clk_cpu|clk - -Slack : 35.774 -Actual Width : 35.774 -Required Width : 0.000 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Clock Edge : Rise -Target : ula_|clocks_|counter[0]|clk - Slack : 69.489 Actual Width : 71.489 Required Width : 2.000 @@ -40974,45 +41648,129 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : 0.815 -Fall : 1.610 +Rise : 1.699 +Fall : 2.367 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : 1.363 +Fall : 2.048 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : 1.240 +Fall : 1.933 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 1.677 +Fall : 2.333 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 1.699 +Fall : 2.367 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 1.293 +Fall : 1.980 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : 1.775 +Fall : 2.591 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 2.160 -Fall : 2.981 +Rise : 1.722 +Fall : 2.653 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : 1.939 +Fall : 2.782 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : 3.051 +Fall : 3.707 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : 0.624 -Fall : 1.147 +Rise : 2.615 +Fall : 3.300 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : 0.624 -Fall : 1.147 +Rise : 2.408 +Fall : 3.101 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 3.051 +Fall : 3.707 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 2.654 +Fall : 3.322 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 2.546 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 2.690 +Fall : 3.565 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 0.702 -Fall : 1.291 +Rise : 0.736 +Fall : 1.327 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 1.571 -Fall : 2.134 +Rise : 1.567 +Fall : 2.174 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -41022,45 +41780,129 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : -0.561 -Fall : -1.355 +Rise : -0.705 +Fall : -1.385 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : -0.766 +Fall : -1.438 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : -0.705 +Fall : -1.385 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -0.954 +Fall : -1.482 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -1.226 +Fall : -1.838 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -0.814 +Fall : -1.488 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : -0.910 +Fall : -1.730 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.405 -Fall : -2.156 +Rise : -1.415 +Fall : -2.313 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : -1.060 +Fall : -1.890 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : -1.705 +Fall : -2.281 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : -0.259 -Fall : -0.788 +Rise : -1.721 +Fall : -2.393 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : -0.259 -Fall : -0.788 +Rise : -1.828 +Fall : -2.508 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -1.705 +Fall : -2.281 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -1.871 +Fall : -2.483 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -1.708 +Fall : -2.382 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -2.085 +Fall : -2.924 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.342 -Fall : -0.923 +Rise : -0.377 +Fall : -0.959 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.737 -Fall : -1.290 +Rise : -0.536 +Fall : -1.088 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -41072,134 +41914,134 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 6.253 -Fall : 6.386 +Rise : 5.969 +Fall : 6.090 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 5.922 -Fall : 6.005 +Rise : 5.682 +Fall : 5.945 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.981 -Fall : 6.082 +Rise : 5.678 +Fall : 5.927 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 5.884 -Fall : 5.994 +Rise : 5.918 +Fall : 6.045 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 5.749 -Fall : 6.050 +Rise : 5.666 +Fall : 5.781 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 6.022 -Fall : 6.135 +Rise : 5.969 +Fall : 6.090 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 6.138 -Fall : 6.337 +Rise : 5.782 +Fall : 5.888 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 6.253 -Fall : 6.386 +Rise : 5.503 +Fall : 5.672 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 5.955 -Fall : 6.115 +Rise : 5.813 +Fall : 5.924 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 6.140 -Fall : 6.286 +Rise : 5.809 +Fall : 5.901 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 5.857 -Fall : 5.936 +Rise : 5.720 +Fall : 5.798 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.902 -Fall : 5.999 +Rise : 5.438 +Fall : 5.603 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 5.854 -Fall : 5.950 +Rise : 5.646 +Fall : 5.732 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.617 -Fall : 5.863 +Rise : 5.533 +Fall : 5.601 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.936 -Fall : 6.062 +Rise : 5.610 +Fall : 5.732 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.889 -Fall : 6.045 +Rise : 5.668 +Fall : 5.744 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 6.140 -Fall : 6.286 +Rise : 5.805 +Fall : 5.888 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.639 -Fall : 5.759 +Rise : 5.809 +Fall : 5.901 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_ADDR[*] Clock Port : CLOCK_50 -Rise : 2.061 -Fall : 1.989 +Rise : 2.060 +Fall : 1.988 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -41282,8 +42124,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 2.061 -Fall : 1.989 +Rise : 2.055 +Fall : 1.983 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -41317,127 +42159,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 2.059 -Fall : 1.987 +Rise : 2.053 +Fall : 1.981 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 3.748 -Fall : 3.683 +Rise : 3.533 +Fall : 3.638 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 3.219 -Fall : 3.327 +Rise : 3.099 +Fall : 3.170 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 3.352 -Fall : 3.462 +Rise : 3.264 +Fall : 3.395 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 3.199 -Fall : 3.311 +Rise : 3.180 +Fall : 3.297 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 3.049 -Fall : 3.160 +Rise : 3.446 +Fall : 3.638 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 3.251 -Fall : 3.356 +Rise : 3.315 +Fall : 3.446 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 3.329 -Fall : 3.459 +Rise : 3.477 +Fall : 3.607 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 3.243 -Fall : 3.342 +Rise : 2.941 +Fall : 3.024 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 3.337 -Fall : 3.469 +Rise : 3.453 +Fall : 3.593 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 3.748 -Fall : 3.683 +Rise : 3.529 +Fall : 3.461 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 3.617 -Fall : 3.572 +Rise : 3.513 +Fall : 3.447 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 3.607 -Fall : 3.563 +Rise : 3.521 +Fall : 3.453 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 3.607 -Fall : 3.563 +Rise : 3.521 +Fall : 3.453 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 3.738 -Fall : 3.680 +Rise : 3.510 +Fall : 3.443 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 3.739 -Fall : 3.675 +Rise : 3.533 +Fall : 3.464 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 3.739 -Fall : 3.675 +Rise : 3.533 +Fall : 3.464 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 3.495 -Fall : 3.473 +Rise : 3.529 +Fall : 3.479 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -41464,8 +42306,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 2.059 -Fall : 1.987 +Rise : 2.053 +Fall : 1.981 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -41492,197 +42334,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.941 -Fall : 5.043 +Rise : 4.722 +Fall : 4.866 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.372 -Fall : 4.489 +Rise : 4.343 +Fall : 4.425 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.445 -Fall : 4.546 +Rise : 4.521 +Fall : 4.771 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.681 -Fall : 4.807 +Rise : 4.677 +Fall : 4.819 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.459 -Fall : 4.699 +Rise : 4.389 +Fall : 4.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.870 -Fall : 4.993 +Rise : 4.722 +Fall : 4.866 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.675 -Fall : 4.823 +Rise : 4.564 +Fall : 4.673 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.941 -Fall : 5.043 +Rise : 4.241 +Fall : 4.364 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.571 -Fall : 4.718 +Rise : 4.430 +Fall : 4.558 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.828 -Fall : 4.943 +Rise : 4.450 +Fall : 4.535 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.307 -Fall : 4.420 +Rise : 4.196 +Fall : 4.274 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.366 -Fall : 4.463 +Rise : 4.284 +Fall : 4.386 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.651 -Fall : 4.763 +Rise : 4.405 +Fall : 4.507 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.327 -Fall : 4.512 +Rise : 4.310 +Fall : 4.501 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.784 -Fall : 4.920 +Rise : 4.346 +Fall : 4.469 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.430 -Fall : 4.536 +Rise : 4.450 +Fall : 4.529 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.828 -Fall : 4.943 +Rise : 4.321 +Fall : 4.438 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.190 -Fall : 4.281 +Rise : 4.426 +Fall : 4.535 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 5.317 -Fall : 5.146 +Rise : 5.244 +Fall : 5.062 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.317 -Fall : 5.146 +Rise : 5.244 +Fall : 5.062 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 4.196 -Fall : 4.364 +Rise : 3.952 +Fall : 4.028 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.803 -Fall : 3.875 +Rise : 3.709 +Fall : 3.763 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 3.804 -Fall : 3.876 +Rise : 3.715 +Fall : 3.770 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.981 -Fall : 4.019 +Rise : 4.038 +Fall : 4.112 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.588 -Fall : 3.585 +Rise : 3.700 +Fall : 3.729 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.818 -Fall : 3.952 +Rise : 3.576 +Fall : 3.589 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 3.981 -Fall : 4.019 +Rise : 4.038 +Fall : 4.112 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 3.981 -Fall : 4.019 +Rise : 4.038 +Fall : 4.112 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -41695,36 +42537,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 4.161 -Fall : 4.356 +Rise : 3.811 +Fall : 3.880 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 3.960 -Fall : 4.022 +Rise : 3.811 +Fall : 3.880 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.161 -Fall : 4.356 +Rise : 3.799 +Fall : 3.843 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.817 -Fall : 3.844 +Rise : 3.791 +Fall : 3.851 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 3.782 -Fall : 3.804 +Rise : 3.534 +Fall : 3.572 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -41792,127 +42634,127 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.488 -Fall : 4.607 +Rise : 4.294 +Fall : 4.375 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.624 -Fall : 4.719 +Rise : 5.038 +Fall : 5.019 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.670 -Fall : 4.779 +Rise : 5.016 +Fall : 5.109 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.488 -Fall : 4.607 +Rise : 5.044 +Fall : 5.159 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.700 -Fall : 4.843 +Rise : 4.369 +Fall : 4.471 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.819 -Fall : 4.940 +Rise : 5.022 +Fall : 5.129 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.988 -Fall : 5.131 +Rise : 5.081 +Fall : 5.174 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.747 -Fall : 4.889 +Rise : 4.294 +Fall : 4.375 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.935 -Fall : 5.065 +Rise : 4.780 +Fall : 4.902 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.461 -Fall : 4.568 +Rise : 4.240 +Fall : 4.298 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.562 -Fall : 4.652 +Rise : 4.794 +Fall : 4.862 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.593 -Fall : 4.698 +Rise : 4.650 +Fall : 4.705 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.461 -Fall : 4.568 +Rise : 4.787 +Fall : 4.861 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.577 -Fall : 4.666 +Rise : 4.240 +Fall : 4.298 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.732 -Fall : 4.867 +Rise : 4.668 +Fall : 4.774 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.749 -Fall : 4.851 +Rise : 4.972 +Fall : 5.036 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.636 -Fall : 4.789 +Rise : 4.316 +Fall : 4.410 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.637 -Fall : 4.728 +Rise : 4.780 +Fall : 4.882 Clock Edge : Rise Clock Reference : CLOCK_50 @@ -42002,8 +42844,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 1.808 -Fall : 1.737 +Rise : 1.802 +Fall : 1.731 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -42037,127 +42879,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 1.805 -Fall : 1.734 +Rise : 1.800 +Fall : 1.729 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 2.705 -Fall : 2.683 +Rise : 2.609 +Fall : 2.688 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 2.876 -Fall : 2.979 +Rise : 2.736 +Fall : 2.807 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 3.004 -Fall : 3.108 +Rise : 2.891 +Fall : 3.012 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 2.854 -Fall : 2.959 +Rise : 2.808 +Fall : 2.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 2.709 -Fall : 2.815 +Rise : 3.063 +Fall : 3.244 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 2.908 -Fall : 3.006 +Rise : 2.940 +Fall : 3.061 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 2.981 -Fall : 3.104 +Rise : 3.124 +Fall : 3.246 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 2.865 -Fall : 2.958 +Rise : 2.609 +Fall : 2.688 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 2.986 -Fall : 3.112 +Rise : 3.062 +Fall : 3.196 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 2.944 -Fall : 2.881 +Rise : 2.928 +Fall : 2.862 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 2.819 -Fall : 2.774 +Rise : 2.913 +Fall : 2.848 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 2.809 -Fall : 2.765 +Rise : 2.920 +Fall : 2.854 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 2.809 -Fall : 2.765 +Rise : 2.920 +Fall : 2.854 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 2.935 -Fall : 2.878 +Rise : 2.909 +Fall : 2.845 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 2.936 -Fall : 2.874 +Rise : 2.932 +Fall : 2.865 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 2.936 -Fall : 2.874 +Rise : 2.932 +Fall : 2.865 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 2.705 -Fall : 2.683 +Rise : 2.931 +Fall : 2.884 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -42184,8 +43026,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 1.805 -Fall : 1.734 +Rise : 1.800 +Fall : 1.729 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -42212,197 +43054,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 3.484 -Fall : 3.630 +Rise : 3.677 +Fall : 3.780 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 3.729 -Fall : 3.823 +Rise : 3.679 +Fall : 3.797 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 3.734 -Fall : 3.824 +Rise : 3.846 +Fall : 3.941 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 3.908 -Fall : 4.032 +Rise : 4.010 +Fall : 4.156 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 3.717 -Fall : 3.979 +Rise : 3.724 +Fall : 3.842 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 3.578 -Fall : 3.745 +Rise : 3.993 +Fall : 4.114 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 3.905 -Fall : 4.039 +Rise : 3.820 +Fall : 3.962 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 3.484 -Fall : 3.630 +Rise : 3.677 +Fall : 3.780 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 3.918 -Fall : 4.056 +Rise : 3.811 +Fall : 3.914 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 3.373 -Fall : 3.530 +Rise : 2.945 +Fall : 3.017 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 3.667 -Fall : 3.756 +Rise : 3.472 +Fall : 3.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 3.657 -Fall : 3.743 +Rise : 3.367 +Fall : 3.452 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 3.881 -Fall : 3.993 +Rise : 3.754 +Fall : 3.859 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 3.594 -Fall : 3.802 +Rise : 2.945 +Fall : 3.017 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 3.491 -Fall : 3.672 +Rise : 3.629 +Fall : 3.730 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 3.669 -Fall : 3.764 +Rise : 3.711 +Fall : 3.824 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 3.373 -Fall : 3.530 +Rise : 3.126 +Fall : 3.217 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 3.578 -Fall : 3.660 +Rise : 3.811 +Fall : 3.894 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.537 -Fall : 2.596 +Rise : 2.438 +Fall : 2.484 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 4.052 -Fall : 3.869 +Rise : 3.974 +Fall : 3.782 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.650 -Fall : 2.713 +Rise : 2.454 +Fall : 2.513 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.537 -Fall : 2.596 +Rise : 2.438 +Fall : 2.484 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.538 -Fall : 2.597 +Rise : 2.444 +Fall : 2.490 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.171 -Fall : 2.177 +Rise : 2.267 +Fall : 2.277 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.181 -Fall : 2.190 +Rise : 2.465 +Fall : 2.447 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.171 -Fall : 2.177 +Rise : 2.267 +Fall : 2.277 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.558 -Fall : 2.607 +Rise : 2.789 +Fall : 2.815 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.558 -Fall : 2.607 +Rise : 2.789 +Fall : 2.815 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -42415,36 +43257,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.368 -Fall : 2.401 +Rise : 2.202 +Fall : 2.223 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.539 -Fall : 2.610 +Rise : 2.468 +Fall : 2.519 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.549 -Fall : 2.620 +Rise : 2.426 +Fall : 2.459 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.402 -Fall : 2.440 +Rise : 2.449 +Fall : 2.491 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.368 -Fall : 2.401 +Rise : 2.202 +Fall : 2.223 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -42512,38 +43354,136 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.819 +RR : 2.879 RF : FR : -FF : 3.181 +FF : 3.248 -Input Port : SW[2] -Output Port : LED[2] -RR : 2.438 -RF : -FR : -FF : 2.867 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 3.948 +RF : 4.040 +FR : 4.626 +FF : 4.725 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 3.860 +RF : 3.903 +FR : 4.539 +FF : 4.589 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 2.630 +FR : 3.223 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 4.172 +RF : 4.262 +FR : 4.858 +FF : 4.955 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 4.068 +RF : 4.084 +FR : 4.716 +FF : 4.795 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 2.519 +FR : 3.078 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 4.628 +RF : 4.747 +FR : 5.277 +FF : 5.403 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 4.035 +RF : 4.111 +FR : 4.705 +FF : 4.762 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 3.961 +FR : 4.321 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 4.513 +RF : 4.613 +FR : 5.181 +FF : 5.281 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 4.398 +RF : 4.452 +FR : 5.031 +FF : 5.092 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 2.439 +FR : 3.023 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 4.303 +RF : 4.397 +FR : 4.983 +FF : 5.084 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 4.067 +RF : 4.165 +FR : 4.739 +FF : 4.819 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 4.030 +FR : 4.929 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 3.977 +RR : 4.506 RF : FR : -FF : 4.754 +FF : 5.349 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 4.061 +RR : 3.990 RF : FR : -FF : 4.868 +FF : 4.790 Input Port : raw_loader_in -Output Port : LED[3] -RR : 2.656 +Output Port : LED[1] +RR : 3.087 RF : FR : -FF : 3.282 +FF : 3.775 +--------------------------------------------------------------------------------+ @@ -42553,38 +43493,136 @@ FF : 3.282 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.733 +RR : 2.791 RF : FR : -FF : 3.101 +FF : 3.164 -Input Port : SW[2] -Output Port : LED[2] -RR : 2.367 -RF : -FR : -FF : 2.799 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 3.814 +RF : 3.901 +FR : 4.486 +FF : 4.580 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 3.732 +RF : 3.773 +FR : 4.405 +FF : 4.453 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 2.547 +FR : 3.137 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 4.029 +RF : 4.114 +FR : 4.709 +FF : 4.801 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 3.933 +RF : 3.925 +FR : 4.550 +FF : 4.648 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 2.445 +FR : 3.001 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 4.354 +RF : 4.138 +FR : 4.707 +FF : 5.142 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 3.901 +RF : 3.973 +FR : 4.566 +FF : 4.619 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 3.887 +FR : 4.243 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 4.297 +RF : 4.333 +FR : 4.909 +FF : 5.048 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 4.249 +RF : 4.300 +FR : 4.878 +FF : 4.936 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 2.365 +FR : 2.946 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 4.157 +RF : 4.246 +FR : 4.831 +FF : 4.927 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 3.929 +RF : 3.972 +FR : 4.566 +FF : 4.670 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 3.943 +FR : 4.839 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 3.843 +RR : 4.350 RF : FR : -FF : 4.611 +FF : 5.184 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.920 +RR : 3.831 RF : FR : -FF : 4.717 +FF : 4.623 Input Port : raw_loader_in -Output Port : LED[3] -RR : 2.572 +Output Port : LED[1] +RR : 2.986 RF : FR : -FF : 3.193 +FF : 3.666 +--------------------------------------------------------------------------------+ @@ -42594,64 +43632,64 @@ FF : 3.193 +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 3.466 -Fall : 3.373 +Rise : 3.312 +Fall : 3.219 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 3.753 -Fall : 3.660 +Rise : 3.403 +Fall : 3.310 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 3.753 -Fall : 3.660 +Rise : 3.403 +Fall : 3.310 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 3.566 -Fall : 3.492 +Rise : 3.363 +Fall : 3.289 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 3.562 -Fall : 3.497 +Rise : 3.461 +Fall : 3.396 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 3.466 -Fall : 3.373 +Rise : 3.472 +Fall : 3.379 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 3.529 -Fall : 3.436 +Rise : 3.312 +Fall : 3.219 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 3.529 -Fall : 3.436 +Rise : 3.312 +Fall : 3.219 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 3.532 -Fall : 3.458 +Rise : 3.483 +Fall : 3.409 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -42663,64 +43701,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 2.680 -Fall : 2.587 +Rise : 2.727 +Fall : 2.634 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 2.956 -Fall : 2.863 +Rise : 2.814 +Fall : 2.721 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 2.956 -Fall : 2.863 +Rise : 2.814 +Fall : 2.721 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 2.767 -Fall : 2.693 +Rise : 2.766 +Fall : 2.692 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 2.769 -Fall : 2.704 +Rise : 2.866 +Fall : 2.801 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 2.680 -Fall : 2.587 +Rise : 2.881 +Fall : 2.788 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 2.741 -Fall : 2.648 +Rise : 2.727 +Fall : 2.634 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 2.741 -Fall : 2.648 +Rise : 2.727 +Fall : 2.634 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 2.734 -Fall : 2.660 +Rise : 2.881 +Fall : 2.807 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -42732,64 +43770,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -0 to Hi-Z : 3.461 -1 to Hi-Z : 3.554 +0 to Hi-Z : 3.315 +1 to Hi-Z : 3.408 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -0 to Hi-Z : 3.795 -1 to Hi-Z : 3.888 +0 to Hi-Z : 3.409 +1 to Hi-Z : 3.502 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -0 to Hi-Z : 3.795 -1 to Hi-Z : 3.888 +0 to Hi-Z : 3.409 +1 to Hi-Z : 3.502 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -0 to Hi-Z : 3.575 -1 to Hi-Z : 3.649 +0 to Hi-Z : 3.388 +1 to Hi-Z : 3.462 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -0 to Hi-Z : 3.611 -1 to Hi-Z : 3.676 +0 to Hi-Z : 3.542 +1 to Hi-Z : 3.607 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -0 to Hi-Z : 3.461 -1 to Hi-Z : 3.554 +0 to Hi-Z : 3.495 +1 to Hi-Z : 3.588 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -0 to Hi-Z : 3.506 -1 to Hi-Z : 3.599 +0 to Hi-Z : 3.315 +1 to Hi-Z : 3.408 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -0 to Hi-Z : 3.506 -1 to Hi-Z : 3.599 +0 to Hi-Z : 3.315 +1 to Hi-Z : 3.408 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -0 to Hi-Z : 3.554 -1 to Hi-Z : 3.628 +0 to Hi-Z : 3.542 +1 to Hi-Z : 3.616 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -42801,64 +43839,64 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -0 to Hi-Z : 2.675 -1 to Hi-Z : 2.768 +0 to Hi-Z : 2.729 +1 to Hi-Z : 2.822 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -0 to Hi-Z : 2.996 -1 to Hi-Z : 3.089 +0 to Hi-Z : 2.819 +1 to Hi-Z : 2.912 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -0 to Hi-Z : 2.996 -1 to Hi-Z : 3.089 +0 to Hi-Z : 2.819 +1 to Hi-Z : 2.912 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -0 to Hi-Z : 2.775 -1 to Hi-Z : 2.849 +0 to Hi-Z : 2.789 +1 to Hi-Z : 2.863 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -0 to Hi-Z : 2.817 -1 to Hi-Z : 2.882 +0 to Hi-Z : 2.944 +1 to Hi-Z : 3.009 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -0 to Hi-Z : 2.675 -1 to Hi-Z : 2.768 +0 to Hi-Z : 2.901 +1 to Hi-Z : 2.994 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -0 to Hi-Z : 2.718 -1 to Hi-Z : 2.811 +0 to Hi-Z : 2.729 +1 to Hi-Z : 2.822 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -0 to Hi-Z : 2.718 -1 to Hi-Z : 2.811 +0 to Hi-Z : 2.729 +1 to Hi-Z : 2.822 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -0 to Hi-Z : 2.755 -1 to Hi-Z : 2.829 +0 to Hi-Z : 2.937 +1 to Hi-Z : 3.011 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -42875,56 +43913,56 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -18.571 -Hold : 0.098 -Recovery : -6.212 +Setup : -18.476 +Hold : 0.179 +Recovery : -6.210 Removal : 2.507 Minimum Pulse Width : 4.748 Clock : CLOCK_50 -Setup : -18.571 -Hold : 0.098 +Setup : -18.476 +Hold : 0.201 Recovery : N/A Removal : N/A Minimum Pulse Width : 9.208 Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Setup : 3.503 +Setup : 3.261 Hold : 0.186 Recovery : N/A Removal : N/A Minimum Pulse Width : 4.748 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -7.747 +Setup : -7.513 Hold : 0.186 Recovery : N/A Removal : N/A -Minimum Pulse Width : 19.596 +Minimum Pulse Width : 19.598 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Setup : -2.915 -Hold : 0.177 +Setup : 70.299 +Hold : 0.186 Recovery : N/A Removal : N/A -Minimum Pulse Width : 35.491 +Minimum Pulse Width : 35.487 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -4.731 -Hold : 0.177 -Recovery : -6.212 +Setup : -4.734 +Hold : 0.179 +Recovery : -6.210 Removal : 2.507 -Minimum Pulse Width : 20.591 +Minimum Pulse Width : 20.589 Clock : Design-wide TNS -Setup : -1152.857 +Setup : -1134.051 Hold : 0.0 -Recovery : -460.73 +Recovery : -460.961 Removal : 0.0 Minimum Pulse Width : 0.0 Clock : CLOCK_50 -Setup : -821.372 +Setup : -808.800 Hold : 0.000 Recovery : N/A Removal : N/A @@ -42938,23 +43976,23 @@ Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -287.138 +Setup : -282.972 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Setup : -2.915 +Setup : 0.000 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -41.432 +Setup : -42.279 Hold : 0.000 -Recovery : -460.730 +Recovery : -460.961 Removal : 0.000 Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ @@ -42964,45 +44002,129 @@ Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ ; Setup Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : 1.548 -Fall : 1.931 +Rise : 2.982 +Fall : 3.302 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : 2.346 +Fall : 2.671 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : 2.083 +Fall : 2.452 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 2.910 +Fall : 3.266 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 2.982 +Fall : 3.302 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 2.249 +Fall : 2.595 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : 3.159 +Fall : 3.711 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.846 -Fall : 4.271 +Rise : 3.214 +Fall : 3.753 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : 3.437 +Fall : 4.028 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : 5.217 +Fall : 5.573 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : 1.010 -Fall : 1.278 +Rise : 4.464 +Fall : 4.789 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : 1.010 -Fall : 1.278 +Rise : 4.077 +Fall : 4.446 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : 5.217 +Fall : 5.573 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : 4.615 +Fall : 4.935 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : 4.296 +Fall : 4.642 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : 4.842 +Fall : 5.311 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.221 -Fall : 1.461 +Rise : 1.275 +Fall : 1.518 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.814 -Fall : 3.095 +Rise : 2.868 +Fall : 3.098 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -43012,45 +44134,129 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Hold Times ; +--------------------------------------------------------------------------------+ -Data Port : raw_loader_in +Data Port : kempston[*] Clock Port : CLOCK_50 -Rise : -0.561 -Fall : -1.355 +Rise : -0.705 +Fall : -1.385 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[0] +Clock Port : CLOCK_50 +Rise : -0.766 +Fall : -1.438 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[1] +Clock Port : CLOCK_50 +Rise : -0.705 +Fall : -1.385 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -0.954 +Fall : -1.482 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -1.226 +Fall : -1.838 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -0.814 +Fall : -1.488 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston_autofire_button +Clock Port : CLOCK_50 +Rise : -0.910 +Fall : -1.730 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.405 -Fall : -2.156 +Rise : -1.415 +Fall : -2.313 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : turbo_button +Clock Port : CLOCK_50 +Rise : -1.060 +Fall : -1.890 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : kempston[*] +Clock Port : CLOCK_50 +Rise : -1.705 +Fall : -2.281 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[*] +Data Port : kempston[0] Clock Port : CLOCK_50 -Rise : -0.259 -Fall : -0.593 +Rise : -1.721 +Fall : -2.393 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : SW[2] +Data Port : kempston[1] Clock Port : CLOCK_50 -Rise : -0.259 -Fall : -0.593 +Rise : -1.828 +Fall : -2.508 Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[2] +Clock Port : CLOCK_50 +Rise : -1.705 +Fall : -2.281 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[3] +Clock Port : CLOCK_50 +Rise : -1.871 +Fall : -2.483 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : kempston[4] +Clock Port : CLOCK_50 +Rise : -1.708 +Fall : -2.382 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : raw_loader_in +Clock Port : CLOCK_50 +Rise : -2.085 +Fall : -2.924 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.342 -Fall : -0.733 +Rise : -0.377 +Fall : -0.786 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.737 -Fall : -1.290 +Rise : -0.536 +Fall : -1.071 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -43062,134 +44268,134 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 10.801 -Fall : 10.789 +Rise : 10.228 +Fall : 10.241 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 10.164 -Fall : 10.160 +Rise : 9.909 +Fall : 10.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 10.350 -Fall : 10.351 +Rise : 9.954 +Fall : 10.011 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 10.114 -Fall : 10.074 +Rise : 10.123 +Fall : 10.126 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 10.072 -Fall : 10.237 +Rise : 9.672 +Fall : 9.707 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 10.376 -Fall : 10.386 +Rise : 10.228 +Fall : 10.241 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 10.482 -Fall : 10.574 +Rise : 9.897 +Fall : 9.931 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 10.801 -Fall : 10.789 +Rise : 9.384 +Fall : 9.506 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 10.294 -Fall : 10.222 +Rise : 9.974 +Fall : 9.978 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 10.527 -Fall : 10.543 +Rise : 9.944 +Fall : 9.917 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 10.022 -Fall : 10.010 +Rise : 9.782 +Fall : 9.780 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 10.153 -Fall : 10.157 +Rise : 9.280 +Fall : 9.386 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 10.039 -Fall : 10.024 +Rise : 9.654 +Fall : 9.659 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 9.790 -Fall : 9.910 +Rise : 9.391 +Fall : 9.410 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 10.258 -Fall : 10.260 +Rise : 9.589 +Fall : 9.640 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 10.080 -Fall : 10.129 +Rise : 9.681 +Fall : 9.690 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 10.527 -Fall : 10.543 +Rise : 9.944 +Fall : 9.917 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 9.684 -Fall : 9.676 +Rise : 9.894 +Fall : 9.917 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_ADDR[*] Clock Port : CLOCK_50 -Rise : 3.430 -Fall : 3.345 +Rise : 3.425 +Fall : 3.340 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -43272,8 +44478,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 3.430 -Fall : 3.345 +Rise : 3.419 +Fall : 3.334 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -43307,127 +44513,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 3.426 -Fall : 3.341 +Rise : 3.417 +Fall : 3.332 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 6.248 -Fall : 6.300 +Rise : 6.004 +Fall : 6.086 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 5.552 -Fall : 5.647 +Rise : 5.305 +Fall : 5.354 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 5.839 -Fall : 5.898 +Rise : 5.578 +Fall : 5.696 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 5.545 -Fall : 5.576 +Rise : 5.445 +Fall : 5.512 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 5.269 -Fall : 5.330 +Rise : 5.941 +Fall : 6.086 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 5.626 -Fall : 5.683 +Rise : 5.645 +Fall : 5.775 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 5.718 -Fall : 5.830 +Rise : 6.004 +Fall : 6.051 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 5.584 -Fall : 5.653 +Rise : 4.996 +Fall : 5.088 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 5.733 -Fall : 5.777 +Rise : 5.954 +Fall : 6.010 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 6.248 -Fall : 6.299 +Rise : 5.903 +Fall : 5.918 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 6.038 -Fall : 6.073 +Rise : 5.870 +Fall : 5.876 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 6.021 -Fall : 6.053 +Rise : 5.883 +Fall : 5.889 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 6.021 -Fall : 6.053 +Rise : 5.883 +Fall : 5.889 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 6.215 -Fall : 6.300 +Rise : 5.873 +Fall : 5.891 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 6.241 -Fall : 6.286 +Rise : 5.904 +Fall : 5.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 6.241 -Fall : 6.286 +Rise : 5.904 +Fall : 5.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 5.859 -Fall : 5.918 +Rise : 5.941 +Fall : 5.965 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -43454,8 +44660,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 3.426 -Fall : 3.341 +Rise : 3.417 +Fall : 3.332 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -43482,197 +44688,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 8.525 -Fall : 8.506 +Rise : 8.091 +Fall : 8.109 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 7.614 -Fall : 7.674 +Rise : 7.500 +Fall : 7.498 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 7.796 -Fall : 7.806 +Rise : 7.943 +Fall : 8.029 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 8.092 -Fall : 8.080 +Rise : 8.038 +Fall : 8.056 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 7.910 -Fall : 8.021 +Rise : 7.578 +Fall : 7.658 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 8.495 -Fall : 8.500 +Rise : 8.091 +Fall : 8.109 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 8.018 -Fall : 8.084 +Rise : 7.839 +Fall : 7.890 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 8.525 -Fall : 8.506 +Rise : 7.255 +Fall : 7.347 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.947 -Fall : 7.936 +Rise : 7.712 +Fall : 7.706 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 8.377 -Fall : 8.374 +Rise : 7.632 +Fall : 7.649 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.472 -Fall : 7.524 +Rise : 7.222 +Fall : 7.219 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.599 -Fall : 7.612 +Rise : 7.315 +Fall : 7.384 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 8.017 -Fall : 8.030 +Rise : 7.565 +Fall : 7.591 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.628 -Fall : 7.694 +Rise : 7.471 +Fall : 7.581 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.377 -Fall : 8.374 +Rise : 7.421 +Fall : 7.433 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.619 -Fall : 7.643 +Rise : 7.623 +Fall : 7.649 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 8.251 -Fall : 8.260 +Rise : 7.465 +Fall : 7.500 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.224 -Fall : 7.248 +Rise : 7.632 +Fall : 7.645 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.645 -Fall : 8.352 +Rise : 8.550 +Fall : 8.202 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.645 -Fall : 8.352 +Rise : 8.550 +Fall : 8.202 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 7.356 -Fall : 7.355 +Rise : 6.928 +Fall : 6.937 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.643 -Fall : 6.643 +Rise : 6.512 +Fall : 6.445 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.647 -Fall : 6.639 +Rise : 6.524 +Fall : 6.454 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.988 -Fall : 6.893 +Rise : 7.146 +Fall : 7.041 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.282 -Fall : 6.183 +Rise : 6.553 +Fall : 6.432 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.690 -Fall : 6.712 +Rise : 6.279 +Fall : 6.217 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.988 -Fall : 6.893 +Rise : 7.146 +Fall : 7.041 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.988 -Fall : 6.893 +Rise : 7.146 +Fall : 7.041 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -43685,36 +44891,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 7.297 -Fall : 7.345 +Rise : 6.725 +Fall : 6.676 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.937 -Fall : 6.925 +Rise : 6.725 +Fall : 6.676 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 7.297 -Fall : 7.345 +Rise : 6.651 +Fall : 6.615 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.690 +Rise : 6.698 Fall : 6.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.641 -Fall : 6.567 +Rise : 6.230 +Fall : 6.171 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -43782,127 +44988,127 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.488 -Fall : 4.607 +Rise : 4.294 +Fall : 4.375 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.624 -Fall : 4.719 +Rise : 5.038 +Fall : 5.019 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.670 -Fall : 4.779 +Rise : 5.016 +Fall : 5.109 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.488 -Fall : 4.607 +Rise : 5.044 +Fall : 5.159 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.700 -Fall : 4.843 +Rise : 4.369 +Fall : 4.471 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.819 -Fall : 4.940 +Rise : 5.022 +Fall : 5.129 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.988 -Fall : 5.131 +Rise : 5.081 +Fall : 5.174 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.747 -Fall : 4.889 +Rise : 4.294 +Fall : 4.375 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.935 -Fall : 5.065 +Rise : 4.780 +Fall : 4.902 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.461 -Fall : 4.568 +Rise : 4.240 +Fall : 4.298 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.562 -Fall : 4.652 +Rise : 4.794 +Fall : 4.862 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.593 -Fall : 4.698 +Rise : 4.650 +Fall : 4.705 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.461 -Fall : 4.568 +Rise : 4.787 +Fall : 4.861 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.577 -Fall : 4.666 +Rise : 4.240 +Fall : 4.298 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.732 -Fall : 4.867 +Rise : 4.668 +Fall : 4.774 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.749 -Fall : 4.851 +Rise : 4.972 +Fall : 5.036 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.636 -Fall : 4.789 +Rise : 4.316 +Fall : 4.410 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.637 -Fall : 4.728 +Rise : 4.780 +Fall : 4.882 Clock Edge : Rise Clock Reference : CLOCK_50 @@ -43992,8 +45198,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_ADDR[11] Clock Port : CLOCK_50 -Rise : 1.808 -Fall : 1.737 +Rise : 1.802 +Fall : 1.731 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -44027,127 +45233,127 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_CAS_N Clock Port : CLOCK_50 -Rise : 1.805 -Fall : 1.734 +Rise : 1.800 +Fall : 1.729 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 2.705 -Fall : 2.683 +Rise : 2.609 +Fall : 2.688 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 2.876 -Fall : 2.979 +Rise : 2.736 +Fall : 2.807 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 3.004 -Fall : 3.108 +Rise : 2.891 +Fall : 3.012 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 2.854 -Fall : 2.959 +Rise : 2.808 +Fall : 2.913 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 2.709 -Fall : 2.815 +Rise : 3.063 +Fall : 3.244 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 2.908 -Fall : 3.006 +Rise : 2.940 +Fall : 3.061 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 2.981 -Fall : 3.104 +Rise : 3.124 +Fall : 3.246 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 2.865 -Fall : 2.958 +Rise : 2.609 +Fall : 2.688 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 2.986 -Fall : 3.112 +Rise : 3.062 +Fall : 3.196 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[8] Clock Port : CLOCK_50 -Rise : 2.944 -Fall : 2.881 +Rise : 2.928 +Fall : 2.862 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[9] Clock Port : CLOCK_50 -Rise : 2.819 -Fall : 2.774 +Rise : 2.913 +Fall : 2.848 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[10] Clock Port : CLOCK_50 -Rise : 2.809 -Fall : 2.765 +Rise : 2.920 +Fall : 2.854 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[11] Clock Port : CLOCK_50 -Rise : 2.809 -Fall : 2.765 +Rise : 2.920 +Fall : 2.854 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[12] Clock Port : CLOCK_50 -Rise : 2.935 -Fall : 2.878 +Rise : 2.909 +Fall : 2.845 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[13] Clock Port : CLOCK_50 -Rise : 2.936 -Fall : 2.874 +Rise : 2.932 +Fall : 2.865 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[14] Clock Port : CLOCK_50 -Rise : 2.936 -Fall : 2.874 +Rise : 2.932 +Fall : 2.865 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[15] Clock Port : CLOCK_50 -Rise : 2.705 -Fall : 2.683 +Rise : 2.931 +Fall : 2.884 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -44174,8 +45380,8 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_RAS_N Clock Port : CLOCK_50 -Rise : 1.805 -Fall : 1.734 +Rise : 1.800 +Fall : 1.729 Clock Edge : Rise Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] @@ -44202,197 +45408,197 @@ Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[ Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 3.484 -Fall : 3.630 +Rise : 3.677 +Fall : 3.780 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 3.729 -Fall : 3.823 +Rise : 3.679 +Fall : 3.797 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 3.734 -Fall : 3.824 +Rise : 3.846 +Fall : 3.941 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 3.908 -Fall : 4.032 +Rise : 4.010 +Fall : 4.156 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 3.717 -Fall : 3.979 +Rise : 3.724 +Fall : 3.842 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 3.578 -Fall : 3.745 +Rise : 3.993 +Fall : 4.114 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 3.905 -Fall : 4.039 +Rise : 3.820 +Fall : 3.962 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 3.484 -Fall : 3.630 +Rise : 3.677 +Fall : 3.780 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 3.918 -Fall : 4.056 +Rise : 3.811 +Fall : 3.914 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 3.373 -Fall : 3.530 +Rise : 2.945 +Fall : 3.017 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 3.667 -Fall : 3.756 +Rise : 3.472 +Fall : 3.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 3.657 -Fall : 3.743 +Rise : 3.367 +Fall : 3.452 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 3.881 -Fall : 3.993 +Rise : 3.754 +Fall : 3.859 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 3.594 -Fall : 3.802 +Rise : 2.945 +Fall : 3.017 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 3.491 -Fall : 3.672 +Rise : 3.629 +Fall : 3.730 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 3.669 -Fall : 3.764 +Rise : 3.711 +Fall : 3.824 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 3.373 -Fall : 3.530 +Rise : 3.126 +Fall : 3.217 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 3.578 -Fall : 3.660 +Rise : 3.811 +Fall : 3.894 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.537 -Fall : 2.596 +Rise : 2.438 +Fall : 2.484 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 4.052 -Fall : 3.869 +Rise : 3.974 +Fall : 3.782 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.650 -Fall : 2.713 +Rise : 2.454 +Fall : 2.513 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.537 -Fall : 2.596 +Rise : 2.438 +Fall : 2.484 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.538 -Fall : 2.597 +Rise : 2.444 +Fall : 2.490 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.171 -Fall : 2.177 +Rise : 2.267 +Fall : 2.277 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.181 -Fall : 2.190 +Rise : 2.465 +Fall : 2.447 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.171 -Fall : 2.177 +Rise : 2.267 +Fall : 2.277 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.558 -Fall : 2.607 +Rise : 2.789 +Fall : 2.815 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.558 -Fall : 2.607 +Rise : 2.789 +Fall : 2.815 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -44405,36 +45611,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.368 -Fall : 2.401 +Rise : 2.202 +Fall : 2.223 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.539 -Fall : 2.610 +Rise : 2.468 +Fall : 2.519 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.549 -Fall : 2.620 +Rise : 2.426 +Fall : 2.459 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.402 -Fall : 2.440 +Rise : 2.449 +Fall : 2.491 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.368 -Fall : 2.401 +Rise : 2.202 +Fall : 2.223 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -44502,38 +45708,136 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.629 +RR : 4.760 RF : FR : -FF : 4.693 +FF : 4.845 -Input Port : SW[2] -Output Port : LED[2] -RR : 4.045 -RF : -FR : -FF : 4.195 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 6.879 +RF : 6.888 +FR : 7.195 +FF : 7.213 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 6.687 +RF : 6.671 +FR : 7.003 +FF : 6.996 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 4.492 +FR : 4.693 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 7.200 +RF : 7.173 +FR : 7.560 +FF : 7.542 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 7.015 +RF : 6.950 +FR : 7.322 +FF : 7.358 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 4.319 +FR : 4.499 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 8.089 +RF : 8.112 +FR : 8.436 +FF : 8.468 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 6.945 +RF : 6.980 +FR : 7.315 +FF : 7.315 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 6.211 +FR : 6.117 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 7.927 +RF : 7.949 +FR : 8.239 +FF : 8.269 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 7.621 +RF : 7.586 +FR : 7.940 +FF : 7.914 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 4.174 +FR : 4.361 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 7.468 +RF : 7.451 +FR : 7.805 +FF : 7.797 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 7.041 +RF : 7.069 +FR : 7.371 +FF : 7.371 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 6.462 +FR : 7.117 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 6.893 +RR : 7.844 RF : FR : -FF : 7.253 +FF : 8.324 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 7.004 +RR : 6.881 RF : FR : -FF : 7.359 +FF : 7.298 Input Port : raw_loader_in -Output Port : LED[3] -RR : 4.487 +Output Port : LED[1] +RR : 5.229 RF : FR : -FF : 4.751 +FF : 5.518 +--------------------------------------------------------------------------------+ @@ -44543,38 +45847,136 @@ FF : 4.751 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.733 +RR : 2.791 RF : FR : -FF : 3.101 +FF : 3.164 -Input Port : SW[2] -Output Port : LED[2] -RR : 2.367 -RF : -FR : -FF : 2.799 +Input Port : kempston[0] +Output Port : DRAM_DQ[3] +RR : 3.814 +RF : 3.901 +FR : 4.486 +FF : 4.580 + +Input Port : kempston[0] +Output Port : GPIO_1[19] +RR : 3.732 +RF : 3.773 +FR : 4.405 +FF : 4.453 + +Input Port : kempston[0] +Output Port : LED[3] +RR : +RF : 2.547 +FR : 3.137 +FF : + +Input Port : kempston[1] +Output Port : DRAM_DQ[2] +RR : 4.029 +RF : 4.114 +FR : 4.709 +FF : 4.801 + +Input Port : kempston[1] +Output Port : GPIO_1[18] +RR : 3.933 +RF : 3.925 +FR : 4.550 +FF : 4.648 + +Input Port : kempston[1] +Output Port : LED[4] +RR : +RF : 2.445 +FR : 3.001 +FF : + +Input Port : kempston[2] +Output Port : DRAM_DQ[1] +RR : 4.354 +RF : 4.138 +FR : 4.707 +FF : 5.142 + +Input Port : kempston[2] +Output Port : GPIO_1[17] +RR : 3.901 +RF : 3.973 +FR : 4.566 +FF : 4.619 + +Input Port : kempston[2] +Output Port : LED[5] +RR : +RF : 3.887 +FR : 4.243 +FF : + +Input Port : kempston[3] +Output Port : DRAM_DQ[0] +RR : 4.297 +RF : 4.333 +FR : 4.909 +FF : 5.048 + +Input Port : kempston[3] +Output Port : GPIO_1[16] +RR : 4.249 +RF : 4.300 +FR : 4.878 +FF : 4.936 + +Input Port : kempston[3] +Output Port : LED[6] +RR : +RF : 2.365 +FR : 2.946 +FF : + +Input Port : kempston[4] +Output Port : DRAM_DQ[4] +RR : 4.157 +RF : 4.246 +FR : 4.831 +FF : 4.927 + +Input Port : kempston[4] +Output Port : GPIO_1[20] +RR : 3.929 +RF : 3.972 +FR : 4.566 +FF : 4.670 + +Input Port : kempston[4] +Output Port : LED[7] +RR : +RF : 3.943 +FR : 4.839 +FF : Input Port : raw_loader_in Output Port : DRAM_DQ[6] -RR : 3.843 +RR : 4.350 RF : FR : -FF : 4.611 +FF : 5.184 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.920 +RR : 3.831 RF : FR : -FF : 4.717 +FF : 4.623 Input Port : raw_loader_in -Output Port : LED[3] -RR : 2.572 +Output Port : LED[1] +RR : 2.986 RF : FR : -FF : 3.193 +FF : 3.666 +--------------------------------------------------------------------------------+ @@ -45939,52 +47341,6 @@ EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a -Pin : GPIO_1[32] -I/O Standard : 3.3-V LVTTL -Near Tline Length : 0 in -Near Tline L per Length : 0 H/in -Near Tline C per Length : 0 F/in -Near Series R : short -Near Differential R : - -Near Pull-up R : open -Near Pull-down R : open -Near C : open -Far Tline Length : 0 in -Far Tline L per Length : 0 H/in -Far Tline C per Length : 0 F/in -Far Series R : short -Far Pull-up R : open -Far Pull-down R : open -Far C : open -Termination Voltage : 0 V -Far Differential R : - -EBD File Name : n/a -EBD Signal Name : n/a -EBD Far-end : n/a - -Pin : GPIO_1[33] -I/O Standard : 3.3-V LVTTL -Near Tline Length : 0 in -Near Tline L per Length : 0 H/in -Near Tline C per Length : 0 F/in -Near Series R : short -Near Differential R : - -Near Pull-up R : open -Near Pull-down R : open -Near C : open -Far Tline Length : 0 in -Far Tline L per Length : 0 H/in -Far Tline C per Length : 0 F/in -Far Series R : short -Far Pull-up R : open -Far Pull-down R : open -Far C : open -Termination Voltage : 0 V -Far Differential R : - -EBD File Name : n/a -EBD Signal Name : n/a -EBD Far-end : n/a - Pin : buzzer_out I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in @@ -46537,6 +47893,29 @@ EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a +Pin : kempston_gnd +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in @@ -47008,6 +48387,11 @@ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps +Pin : SW[2] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + Pin : SW[3] I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps @@ -47108,12 +48492,32 @@ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps -Pin : SW[2] +Pin : raw_loader_in I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps -Pin : raw_loader_in +Pin : kempston[0] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : kempston[1] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : kempston[2] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : kempston[3] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : kempston[4] I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps @@ -47128,6 +48532,16 @@ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps +Pin : turbo_button +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : kempston_autofire_button +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + Pin : PS2_DAT I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps @@ -48644,56 +50058,6 @@ Ringback Voltage on Fall at Far-end : 0.194 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No -Pin : GPIO_1[32] -I/O Standard : 3.3-V LVTTL -Board Delay on Rise : 0 s -Board Delay on Fall : 0 s -Steady State Voh at FPGA Pin : 3.08 V -Steady State Vol at FPGA Pin : 1.54e-08 V -Voh Max at FPGA Pin : 3.14 V -Vol Min at FPGA Pin : -0.074 V -Ringback Voltage on Rise at FPGA Pin : 0.343 V -Ringback Voltage on Fall at FPGA Pin : 0.194 V -10-90 Rise Time at FPGA Pin : 7.35e-10 s -90-10 Fall Time at FPGA Pin : 6.36e-10 s -Monotonic Rise at FPGA Pin : No -Monotonic Fall at FPGA Pin : No -Steady State Voh at Far-end : 3.08 V -Steady State Vol at Far-end : 1.54e-08 V -Voh Max at Far-end : 3.14 V -Vol Min at Far-end : -0.074 V -Ringback Voltage on Rise at Far-end : 0.343 V -Ringback Voltage on Fall at Far-end : 0.194 V -10-90 Rise Time at Far-end : 7.35e-10 s -90-10 Fall Time at Far-end : 6.36e-10 s -Monotonic Rise at Far-end : No -Monotonic Fall at Far-end : No - -Pin : GPIO_1[33] -I/O Standard : 3.3-V LVTTL -Board Delay on Rise : 0 s -Board Delay on Fall : 0 s -Steady State Voh at FPGA Pin : 3.08 V -Steady State Vol at FPGA Pin : 1.54e-08 V -Voh Max at FPGA Pin : 3.14 V -Vol Min at FPGA Pin : -0.074 V -Ringback Voltage on Rise at FPGA Pin : 0.343 V -Ringback Voltage on Fall at FPGA Pin : 0.194 V -10-90 Rise Time at FPGA Pin : 7.35e-10 s -90-10 Fall Time at FPGA Pin : 6.36e-10 s -Monotonic Rise at FPGA Pin : No -Monotonic Fall at FPGA Pin : No -Steady State Voh at Far-end : 3.08 V -Steady State Vol at Far-end : 1.54e-08 V -Voh Max at Far-end : 3.14 V -Vol Min at Far-end : -0.074 V -Ringback Voltage on Rise at Far-end : 0.343 V -Ringback Voltage on Fall at Far-end : 0.194 V -10-90 Rise Time at Far-end : 7.35e-10 s -90-10 Fall Time at Far-end : 6.36e-10 s -Monotonic Rise at Far-end : No -Monotonic Fall at Far-end : No - Pin : buzzer_out I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -49294,6 +50658,31 @@ Ringback Voltage on Fall at Far-end : 0.22 V Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No +Pin : kempston_gnd +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -51275,56 +52664,6 @@ Ringback Voltage on Fall at Far-end : 0.181 V Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No -Pin : GPIO_1[32] -I/O Standard : 3.3-V LVTTL -Board Delay on Rise : 0 s -Board Delay on Fall : 0 s -Steady State Voh at FPGA Pin : 3.08 V -Steady State Vol at FPGA Pin : 2e-06 V -Voh Max at FPGA Pin : 3.12 V -Vol Min at FPGA Pin : -0.0547 V -Ringback Voltage on Rise at FPGA Pin : 0.276 V -Ringback Voltage on Fall at FPGA Pin : 0.181 V -10-90 Rise Time at FPGA Pin : 9.17e-10 s -90-10 Fall Time at FPGA Pin : 8.31e-10 s -Monotonic Rise at FPGA Pin : Yes -Monotonic Fall at FPGA Pin : No -Steady State Voh at Far-end : 3.08 V -Steady State Vol at Far-end : 2e-06 V -Voh Max at Far-end : 3.12 V -Vol Min at Far-end : -0.0547 V -Ringback Voltage on Rise at Far-end : 0.276 V -Ringback Voltage on Fall at Far-end : 0.181 V -10-90 Rise Time at Far-end : 9.17e-10 s -90-10 Fall Time at Far-end : 8.31e-10 s -Monotonic Rise at Far-end : Yes -Monotonic Fall at Far-end : No - -Pin : GPIO_1[33] -I/O Standard : 3.3-V LVTTL -Board Delay on Rise : 0 s -Board Delay on Fall : 0 s -Steady State Voh at FPGA Pin : 3.08 V -Steady State Vol at FPGA Pin : 2e-06 V -Voh Max at FPGA Pin : 3.12 V -Vol Min at FPGA Pin : -0.0547 V -Ringback Voltage on Rise at FPGA Pin : 0.276 V -Ringback Voltage on Fall at FPGA Pin : 0.181 V -10-90 Rise Time at FPGA Pin : 9.17e-10 s -90-10 Fall Time at FPGA Pin : 8.31e-10 s -Monotonic Rise at FPGA Pin : Yes -Monotonic Fall at FPGA Pin : No -Steady State Voh at Far-end : 3.08 V -Steady State Vol at Far-end : 2e-06 V -Voh Max at Far-end : 3.12 V -Vol Min at Far-end : -0.0547 V -Ringback Voltage on Rise at Far-end : 0.276 V -Ringback Voltage on Fall at Far-end : 0.181 V -10-90 Rise Time at Far-end : 9.17e-10 s -90-10 Fall Time at Far-end : 8.31e-10 s -Monotonic Rise at Far-end : Yes -Monotonic Fall at Far-end : No - Pin : buzzer_out I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -51925,6 +53264,31 @@ Ringback Voltage on Fall at Far-end : 0.359 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : kempston_gnd +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -53906,56 +55270,6 @@ Ringback Voltage on Fall at Far-end : 0.175 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No -Pin : GPIO_1[32] -I/O Standard : 3.3-V LVTTL -Board Delay on Rise : 0 s -Board Delay on Fall : 0 s -Steady State Voh at FPGA Pin : 3.46 V -Steady State Vol at FPGA Pin : 1.25e-07 V -Voh Max at FPGA Pin : 3.57 V -Vol Min at FPGA Pin : -0.0855 V -Ringback Voltage on Rise at FPGA Pin : 0.315 V -Ringback Voltage on Fall at FPGA Pin : 0.175 V -10-90 Rise Time at FPGA Pin : 6.79e-10 s -90-10 Fall Time at FPGA Pin : 6.15e-10 s -Monotonic Rise at FPGA Pin : No -Monotonic Fall at FPGA Pin : No -Steady State Voh at Far-end : 3.46 V -Steady State Vol at Far-end : 1.25e-07 V -Voh Max at Far-end : 3.57 V -Vol Min at Far-end : -0.0855 V -Ringback Voltage on Rise at Far-end : 0.315 V -Ringback Voltage on Fall at Far-end : 0.175 V -10-90 Rise Time at Far-end : 6.79e-10 s -90-10 Fall Time at Far-end : 6.15e-10 s -Monotonic Rise at Far-end : No -Monotonic Fall at Far-end : No - -Pin : GPIO_1[33] -I/O Standard : 3.3-V LVTTL -Board Delay on Rise : 0 s -Board Delay on Fall : 0 s -Steady State Voh at FPGA Pin : 3.46 V -Steady State Vol at FPGA Pin : 1.25e-07 V -Voh Max at FPGA Pin : 3.57 V -Vol Min at FPGA Pin : -0.0855 V -Ringback Voltage on Rise at FPGA Pin : 0.315 V -Ringback Voltage on Fall at FPGA Pin : 0.175 V -10-90 Rise Time at FPGA Pin : 6.79e-10 s -90-10 Fall Time at FPGA Pin : 6.15e-10 s -Monotonic Rise at FPGA Pin : No -Monotonic Fall at FPGA Pin : No -Steady State Voh at Far-end : 3.46 V -Steady State Vol at Far-end : 1.25e-07 V -Voh Max at Far-end : 3.57 V -Vol Min at Far-end : -0.0855 V -Ringback Voltage on Rise at Far-end : 0.315 V -Ringback Voltage on Fall at Far-end : 0.175 V -10-90 Rise Time at Far-end : 6.79e-10 s -90-10 Fall Time at Far-end : 6.15e-10 s -Monotonic Rise at Far-end : No -Monotonic Fall at Far-end : No - Pin : buzzer_out I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -54556,6 +55870,31 @@ Ringback Voltage on Fall at Far-end : 0.21 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : kempston_gnd +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -55078,7 +56417,7 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 300 +RR Paths : 1552 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -55099,7 +56438,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 1201 +RR Paths : 1182 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -55113,28 +56452,21 @@ FF Paths : 0 From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1926 +RR Paths : 1972 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 272 +RR Paths : 260 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1070 -FR Paths : 0 -RF Paths : 0 -FF Paths : 0 - -From Clock : CLOCK_50 -To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -RR Paths : 1 +RR Paths : 1054 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -55155,7 +56487,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -RR Paths : 1437 +RR Paths : 1425 FR Paths : 180 RF Paths : 0 FF Paths : 21 @@ -55183,7 +56515,7 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 300 +RR Paths : 1552 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -55204,7 +56536,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 1201 +RR Paths : 1182 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -55218,28 +56550,21 @@ FF Paths : 0 From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1926 +RR Paths : 1972 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 272 +RR Paths : 260 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1070 -FR Paths : 0 -RF Paths : 0 -FF Paths : 0 - -From Clock : CLOCK_50 -To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -RR Paths : 1 +RR Paths : 1054 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -55260,7 +56585,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -RR Paths : 1437 +RR Paths : 1425 FR Paths : 180 RF Paths : 0 FF Paths : 21 @@ -55317,8 +56642,8 @@ Setup : 0 Hold : 0 Property : Unconstrained Clocks -Setup : 2 -Hold : 2 +Setup : 4 +Hold : 4 Property : Unconstrained Input Ports Setup : 0 @@ -55345,7 +56670,7 @@ Hold : 0 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Sat Apr 2 14:51:13 2022 + Info: Processing started: Wed Apr 6 13:58:20 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -55371,643 +56696,654 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 513 nodes - Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" - Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~30|datad" - Warning (332126): Node "z80_|alu_control_|db[2]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" - Warning (332126): Node "z80_|bus_control_|db[2]~12|datac" - Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~13|datac" - Warning (332126): Node "z80_|alu_|db[2]~11|datad" - Warning (332126): Node "z80_|alu_|db[2]~11|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|datac" - Warning (332126): Node "z80_|alu_|db[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~18|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~19|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~19|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~20|combout" - Warning (332126): Node "z80_|alu_|db[1]~16|datac" - Warning (332126): Node "z80_|alu_|db[1]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" - Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~27|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~27|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~10|dataa" - Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" - Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" - Warning (332126): Node "z80_|sw1_|db_down[1]~2|dataa" - Warning (332126): Node "z80_|sw1_|db_down[1]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~27|datad" - Warning (332126): Node "z80_|alu_|db[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db[1]~15|combout" - Warning (332126): Node "z80_|alu_|db[1]~16|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~19|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datad" - Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~27|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~27|combout" - Warning (332126): Node "z80_|alu_|db[0]~17|datac" - Warning (332126): Node "z80_|alu_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datac" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~2|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~3|datac" +Warning (332125): Found combinational loop of 518 nodes + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~25|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~24|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~25|dataa" + Warning (332126): Node "z80_|alu_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|dataa" + Warning (332126): Node "z80_|alu_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~3|dataa" Warning (332126): Node "z80_|alu_|db_high[3]~3|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datad" Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" Warning (332126): Node "z80_|alu_|db_high[3]~7|datad" Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|datad" - Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~3|datab" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~8|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~8|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|datac" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~2|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~16|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db[7]~20|datac" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~3|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~3|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~19|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~13|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datac" + Warning (332126): Node "z80_|alu_|db[1]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~21|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~22|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~22|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~9|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~9|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[1]|datab" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[1]|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~22|dataa" + Warning (332126): Node "z80_|alu_|db[1]~15|datac" + Warning (332126): Node "z80_|alu_|db[1]~15|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~3|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~3|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~33|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~13|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~15|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~2|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~2|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~9|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datac" + Warning (332126): Node "z80_|alu_|db[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout" + Warning (332126): Node "z80_|alu_|db[2]~11|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~13|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~27|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|datad" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~14|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~14|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[2]|datac" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[2]|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_|db[2]~11|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~5|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~27|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~43|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~0|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~0|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~1|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~1|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|combout" + Warning (332126): Node "z80_|alu_|db[3]~14|datac" + Warning (332126): Node "z80_|alu_|db[3]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datac" + Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datad" Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|alu_|db[5]~24|datad" Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~8|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|combout" - Warning (332126): Node "z80_|alu_|db[5]~23|dataa" - Warning (332126): Node "z80_|alu_|db[5]~23|combout" - Warning (332126): Node "z80_|alu_|db[5]~24|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|dataa" - Warning (332126): Node "z80_|alu_control_|db[5]~17|datad" - Warning (332126): Node "z80_|alu_control_|db[5]~17|combout" - Warning (332126): Node "z80_|bus_control_|db[5]~15|dataa" - Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~14|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~20|datad" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa" - Warning (332126): Node "z80_|alu_control_|db[5]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~17|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~26|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~26|combout" - Warning (332126): Node "z80_|alu_|db[3]~13|dataa" - Warning (332126): Node "z80_|alu_|db[3]~13|combout" - Warning (332126): Node "z80_|alu_|db[3]~14|datab" - Warning (332126): Node "z80_|alu_|db[3]~14|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~36|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datad" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~36|datad" - Warning (332126): Node "z80_|alu_|db[3]~14|datad" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datac" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|sw1_|db_down[3]~3|datab" - Warning (332126): Node "z80_|sw1_|db_down[3]~3|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~13|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~14|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[2]~12|dataa" Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|datad" - Warning (332126): Node "z80_|alu_|db[4]~10|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datac" - Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~33|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~33|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datac" - Warning (332126): Node "z80_|alu_|db[4]~8|datac" - Warning (332126): Node "z80_|alu_|db[4]~8|combout" - Warning (332126): Node "z80_|alu_|db[4]~10|datac" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datac" - Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~33|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~10|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|dataa" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~25|datad" - Warning (332126): Node "z80_|alu_|db_low[0]~25|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~27|datac" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~16|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~3|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~10|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~17|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~18|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~18|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~7|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~7|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[0]|datac" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[0]|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~18|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~2|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~17|datad" + Warning (332126): Node "z80_|alu_|db[6]~21|datac" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~12|datad" + Warning (332126): Node "z80_|alu_control_|db[5]~12|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~48|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~48|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~51|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~51|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~52|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~52|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~10|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~11|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~12|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~53|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[5]~0|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~9|datad" + Warning (332126): Node "z80_|alu_control_|db[5]~9|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~12|dataa" + Warning (332126): Node "z80_|bus_control_|db[5]~16|datad" + Warning (332126): Node "z80_|bus_control_|db[5]~16|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datac" - Warning (332126): Node "z80_|alu_|db[4]~8|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~4|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~5|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datad" Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~22|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~3|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~3|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~7|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~8|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~8|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~11|datac" + Warning (332126): Node "z80_|alu_control_|db[5]~9|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~16|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~16|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~16|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~21|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~0|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~19|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" + Warning (332126): Node "z80_|alu_|db[4]~8|datab" + Warning (332126): Node "z80_|alu_|db[4]~8|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~29|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~29|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~30|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|bus_control_|db[4]~18|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" Warning (332126): Node "z80_|alu_|db_high[0]~23|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~20|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~7|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~14|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~3|datad" + Warning (332126): Node "z80_|alu_|db[4]~8|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~65|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~72|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~72|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~29|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~16|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~17|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~18|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~73|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~1|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|combout" Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|datab" Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datac" - Warning (332126): Node "z80_|alu_|db[3]~13|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~9|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~10|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~13|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~20|datad" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|bus_control_|db[3]~20|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~20|combout" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~16|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab" - Warning (332126): Node "z80_|alu_|db[5]~23|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~22|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datac" - Warning (332126): Node "z80_|alu_|db[6]~21|datac" - Warning (332126): Node "z80_|alu_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|datad" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" - Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~23|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~23|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~8|datad" - Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" - Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" - Warning (332126): Node "z80_|sw1_|db_down[6]~1|datac" - Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~23|datad" - Warning (332126): Node "z80_|alu_|db[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~23|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|datad" - Warning (332126): Node "z80_|alu_|db[7]~19|dataa" - Warning (332126): Node "z80_|alu_|db[7]~19|combout" - Warning (332126): Node "z80_|alu_|db[7]~20|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" - Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~19|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~20|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~37|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~37|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" - Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~20|datab" - Warning (332126): Node "z80_|alu_|db[7]~19|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~19|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datab" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~11|datad" - Warning (332126): Node "z80_|alu_control_|db[0]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~14|dataa" - Warning (332126): Node "z80_|alu_control_|db[0]~14|combout" - Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~10|datad" - Warning (332126): Node "z80_|alu_control_|db[0]~10|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa" - Warning (332126): Node "z80_|alu_|db[0]~18|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~11|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~18|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~33|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~33|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~20|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~14|datab" + Warning (332126): Node "z80_|alu_|db[3]~14|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~57|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~57|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~58|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~58|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~61|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~61|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~62|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~14|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~15|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~63|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~19|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" - Warning (332126): Node "z80_|alu_|db[0]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datab" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~7|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" - Warning (332126): Node "z80_|alu_|db[1]~15|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~10|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~30|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout" - Warning (332126): Node "z80_|alu_|db[2]~11|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~4|datac" -Critical Warning (332081): Design contains combinational loop of 513 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|alu_|db[0]~17|dataa" + Warning (332126): Node "z80_|alu_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datac" + Warning (332126): Node "z80_|alu_control_|db[0]~23|datac" + Warning (332126): Node "z80_|alu_control_|db[0]~23|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~25|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~25|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~11|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~11|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~12|datac" + Warning (332126): Node "z80_|bus_control_|db[0]~12|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[0]|datac" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_2[0]|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~24|datad" + Warning (332126): Node "z80_|alu_control_|db[0]~24|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~25|datac" + Warning (332126): Node "z80_|alu_|db[0]~17|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~16|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~16|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~18|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[0]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[0]~4|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~25|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~23|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~80|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~82|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~83|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~84|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~14|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~15|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~15|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~4|datad" + Warning (332126): Node "z80_|bus_control_|db[7]~4|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~6|datac" + Warning (332126): Node "z80_|bus_control_|db[7]~6|combout" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[1]|datab" + Warning (332126): Node "z80_|sw1_|SYNTHESIZED_WIRE_1[1]|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~14|datad" + Warning (332126): Node "z80_|alu_|db[7]~19|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" +Critical Warning (332081): Design contains combinational loop of 518 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -18.571 +Info (332146): Worst-case setup slack is -18.476 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -18.571 -821.372 CLOCK_50 - Info (332119): -7.747 -287.138 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -4.731 -41.432 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.915 -2.915 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 3.503 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case hold slack is 0.342 + Info (332119): -18.476 -808.800 CLOCK_50 + Info (332119): -7.513 -282.972 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.734 -42.279 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 3.261 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 70.299 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info (332146): Worst-case hold slack is 0.344 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.344 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 0.359 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 0.373 0.000 CLOCK_50 -Info (332146): Worst-case recovery slack is -6.212 + Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.358 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.382 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -6.210 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -6.212 -460.730 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.666 + Info (332119): -6.210 -460.961 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.689 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.666 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 3.689 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case minimum pulse width slack is 4.752 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.752 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.488 0.000 CLOCK_50 Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 20.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 20.593 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 35.490 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -17.727 +Info (332146): Worst-case setup slack is -17.646 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -17.727 -781.205 CLOCK_50 - Info (332119): -6.896 -255.894 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -4.422 -38.759 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.786 -2.786 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 4.148 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case hold slack is 0.298 + Info (332119): -17.646 -768.789 CLOCK_50 + Info (332119): -6.953 -254.832 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.416 -39.535 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 3.951 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 70.438 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info (332146): Worst-case hold slack is 0.300 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.300 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.312 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 0.339 0.000 CLOCK_50 -Info (332146): Worst-case recovery slack is -5.735 + Info (332119): 0.312 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.333 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -5.734 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -5.735 -424.927 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.339 + Info (332119): -5.734 -425.150 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.370 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.339 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 3.370 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case minimum pulse width slack is 4.748 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.748 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 9.489 0.000 CLOCK_50 - Info (332119): 19.596 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 20.591 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 9.488 0.000 CLOCK_50 + Info (332119): 19.598 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 20.589 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 35.487 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Fast 1200mV 0C Model Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_autofire|r_State was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: debouncer:debounce_turbo|r_State was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -15.243 +Info (332146): Worst-case setup slack is -15.170 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -15.243 -641.328 CLOCK_50 - Info (332119): -4.921 -171.346 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -3.770 -34.841 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 6.261 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case hold slack is 0.098 + Info (332119): -15.170 -635.207 CLOCK_50 + Info (332119): -5.647 -193.116 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -3.810 -35.303 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 6.131 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 70.800 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info (332146): Worst-case hold slack is 0.179 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.098 0.000 CLOCK_50 - Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.179 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.186 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.201 0.000 CLOCK_50 Info (332146): Worst-case recovery slack is -4.684 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -4.684 -358.844 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -4.684 -359.024 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case removal slack is 2.507 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.507 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case minimum pulse width slack is 4.783 +Info (332146): Worst-case minimum pulse width slack is 4.784 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 4.783 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 4.784 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.208 0.000 CLOCK_50 Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 35.525 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 534 warnings - Info: Peak virtual memory: 445 megabytes - Info: Processing ended: Sat Apr 2 14:51:17 2022 +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 545 warnings + Info: Peak virtual memory: 441 megabytes + Info: Processing ended: Wed Apr 6 13:58:24 2022 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 895d966..8cc96b0 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,51 +3,51 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -18.571 -TNS : -821.372 +Slack : -18.476 +TNS : -808.800 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -7.747 -TNS : -287.138 +Slack : -7.513 +TNS : -282.972 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.731 -TNS : -41.432 - -Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.915 -TNS : -2.915 +Slack : -4.734 +TNS : -42.279 Type : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' -Slack : 3.503 +Slack : 3.261 TNS : 0.000 -Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : 0.342 +Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 70.299 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.342 +Slack : 0.344 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' Slack : 0.357 TNS : 0.000 +Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.357 +TNS : 0.000 + Type : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.359 +Slack : 0.358 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.373 +Slack : 0.382 TNS : 0.000 Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.212 -TNS : -460.730 +Slack : -6.210 +TNS : -460.961 Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.666 +Slack : 3.689 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' @@ -63,39 +63,35 @@ Slack : 19.602 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 20.597 +Slack : 20.593 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : 35.503 +Slack : 35.490 TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -17.727 -TNS : -781.205 +Slack : -17.646 +TNS : -768.789 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -6.896 -TNS : -255.894 +Slack : -6.953 +TNS : -254.832 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.422 -TNS : -38.759 - -Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.786 -TNS : -2.786 +Slack : -4.416 +TNS : -39.535 Type : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.148 +Slack : 3.951 TNS : 0.000 -Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : 0.298 +Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 70.438 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.298 +Slack : 0.300 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' @@ -106,16 +102,20 @@ Type : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_ge Slack : 0.312 TNS : 0.000 +Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.312 +TNS : 0.000 + Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.339 +Slack : 0.333 TNS : 0.000 Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -5.735 -TNS : -424.927 +Slack : -5.734 +TNS : -425.150 Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.339 +Slack : 3.370 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' @@ -123,51 +123,43 @@ Slack : 4.748 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' -Slack : 9.489 +Slack : 9.488 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : 19.596 +Slack : 19.598 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 20.591 +Slack : 20.589 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : 35.491 +Slack : 35.487 TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -15.243 -TNS : -641.328 +Slack : -15.170 +TNS : -635.207 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -4.921 -TNS : -171.346 +Slack : -5.647 +TNS : -193.116 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -3.770 -TNS : -34.841 - -Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.784 -TNS : -2.784 +Slack : -3.810 +TNS : -35.303 Type : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' -Slack : 6.261 +Slack : 6.131 TNS : 0.000 -Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.098 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : 0.177 +Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 70.800 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.177 +Slack : 0.179 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' @@ -178,16 +170,24 @@ Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll Slack : 0.186 TNS : 0.000 +Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.186 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'CLOCK_50' +Slack : 0.201 +TNS : 0.000 + Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' Slack : -4.684 -TNS : -358.844 +TNS : -359.024 Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' Slack : 2.507 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.783 +Slack : 4.784 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -203,7 +203,7 @@ Slack : 20.600 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : 35.535 +Slack : 35.525 TNS : 0.000 ------------------------------------------------------------ diff --git a/output_files/stp1.stp b/output_files/stp1.stp new file mode 100644 index 0000000..a44832b --- /dev/null +++ b/output_files/stp1.stp @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 111111111111 + 111111111111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + +
+ + + + + + + + + + + + + + diff --git a/pll_sdram.ppf b/pll_sdram.ppf new file mode 100644 index 0000000..24c94ee --- /dev/null +++ b/pll_sdram.ppf @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/pll_sdram.qip b/pll_sdram.qip new file mode 100644 index 0000000..38db201 --- /dev/null +++ b/pll_sdram.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_sdram.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_sdram_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_sdram.ppf"] diff --git a/pll_sdram.v b/pll_sdram.v new file mode 100644 index 0000000..20ae977 --- /dev/null +++ b/pll_sdram.v @@ -0,0 +1,301 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_sdram.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_sdram ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [4:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 50, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 133, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_sdram", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "133.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "133" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sdram.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "133" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/pll_sdram_bb.v b/pll_sdram_bb.v new file mode 100644 index 0000000..9d30960 --- /dev/null +++ b/pll_sdram_bb.v @@ -0,0 +1,194 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_sdram.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module pll_sdram ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "133.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "133" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sdram.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "133" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sdram_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/rom/hc91.hex b/rom/hc91.hex new file mode 100644 index 0000000..641d865 --- /dev/null +++ b/rom/hc91.hex @@ -0,0 +1,514 @@ +:020000040000FA +:20000000F3AF11FFFFC3CB112A5D5C225F5C1843C3F215FFFFFFFFFF2A5D5C7ECD7D00D035 +:20002000CD740018F7FFFFFFC35B33FFFFFFFFFFC52A615CE5C39E16F5E52A785C2322788A +:200040005C7CB52003FD3440C5D5CDBF02D1C1E1F1FBC9E16EFD7500ED7B3D5CC3C516FFD0 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+:203FC000000044281028440000004444443C043800007C0810207C00000E083008080E0021 +:203FE00000080808080808000070100C1010700000142800000000003C4299A1A199423CC9 +:00000001FF diff --git a/rom/hc91.rom b/rom/hc91.rom new file mode 100644 index 0000000..7a8f634 Binary files /dev/null and b/rom/hc91.rom differ diff --git a/rom/hc91.zip b/rom/hc91.zip new file mode 100644 index 0000000..caf7f36 Binary files /dev/null and b/rom/hc91.zip differ diff --git a/rom0.v.bak b/rom0.v.bak new file mode 100644 index 0000000..69d769c --- /dev/null +++ b/rom0.v.bak @@ -0,0 +1,164 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: rom0.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module rom0 ( + address, + clock, + q); + + input [13:0] address; + input clock; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({8{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", +`ifdef NO_PLI + altsyncram_component.init_file = "./rom/gw03.rif" +`else + altsyncram_component.init_file = "./rom/gw03.hex" +`endif +, + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 16384, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.widthad_a = 14, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./rom/gw03.hex" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "14" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gw03.hex" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/sdram.v b/sdram.v new file mode 100644 index 0000000..c06deb8 --- /dev/null +++ b/sdram.v @@ -0,0 +1,436 @@ +/* + This SDRAM controller is for the Mojo's SDRAM shield which uses + a 48LC32M8A2-7E SDRAM chip. This module was designed under the + assumption that the click rate is 100MHz. Timing values would + need to be re-evaluated under different clock rates. + + This controller features two baisc improvements over the most + basic of controllers. It does burst reads and writes of 4 bytes, + and it only closes a row when it has to. +*/ + +module sdram ( + input clk, + input rst, + + // these signals go directly to the IO pins + output sdram_clk, + output sdram_cle, + output sdram_cs, + output sdram_cas, + output sdram_ras, + output sdram_we, + output sdram_dqm, + output [1:0] sdram_ba, + output [12:0] sdram_a, + inout [7:0] sdram_dq, + + // User interface + input [22:0] addr, // address to read/write + input rw, // 1 = write, 0 = read + input [31:0] data_in, // data from a read + output [31:0] data_out, // data for a write + output busy, // controller is busy when high + input in_valid, // pulse high to initiate a read/write + output out_valid // pulses high when data from read is valid + ); + + // Commands for the SDRAM + localparam CMD_UNSELECTED = 4'b1000; + localparam CMD_NOP = 4'b0111; + localparam CMD_ACTIVE = 4'b0011; + localparam CMD_READ = 4'b0101; + localparam CMD_WRITE = 4'b0100; + localparam CMD_TERMINATE = 4'b0110; + localparam CMD_PRECHARGE = 4'b0010; + localparam CMD_REFRESH = 4'b0001; + localparam CMD_LOAD_MODE_REG = 4'b0000; + + localparam STATE_SIZE = 4; + localparam INIT = 0, + WAIT = 1, + PRECHARGE_INIT = 2, + REFRESH_INIT_1 = 3, + REFRESH_INIT_2 = 4, + LOAD_MODE_REG = 5, + IDLE = 6, + REFRESH = 7, + ACTIVATE = 8, + READ = 9, + READ_RES = 10, + WRITE = 11, + PRECHARGE = 12; + + wire sdram_clk_ddr; + + // This is used to drive the SDRAM clock + ODDR2 #( + .DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC") + ) ODDR2_inst ( + .Q(sdram_clk_ddr), // 1-bit DDR output data + .C0(clk), // 1-bit clock input + .C1(~clk), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) // 1-bit set input + ); + + IODELAY2 #( + .IDELAY_VALUE(0), + .IDELAY_MODE("NORMAL"), + .ODELAY_VALUE(100), // value of 100 seems to work at 100MHz + .IDELAY_TYPE("FIXED"), + .DELAY_SRC("ODATAIN"), + .DATA_RATE("SDR") + ) IODELAY_inst ( + .IDATAIN(1'b0), + .T(1'b0), + .ODATAIN(sdram_clk_ddr), + .CAL(1'b0), + .IOCLK0(1'b0), + .IOCLK1(1'b0), + .CLK(1'b0), + .INC(1'b0), + .CE(1'b0), + .RST(1'b0), + .BUSY(), + .DATAOUT(), + .DATAOUT2(), + .TOUT(), + .DOUT(sdram_clk) + ); + + // registers for SDRAM signals + reg cle_d, dqm_d; + reg [3:0] cmd_d; + reg [1:0] ba_d; + reg [12:0] a_d; + reg [7:0] dq_d; + reg [7:0] dqi_d; + + // We want the output/input registers to be embedded in the + // IO buffers so we set IOB to "TRUE". This is to ensure all + // the signals are sent and received at the same time. + (* IOB = "TRUE" *) + reg cle_q, dqm_q; + (* IOB = "TRUE" *) + reg [3:0] cmd_q; + (* IOB = "TRUE" *) + reg [1:0] ba_q; + (* IOB = "TRUE" *) + reg [12:0] a_q; + (* IOB = "TRUE" *) + reg [7:0] dq_q; + (* IOB = "TRUE" *) + reg [7:0] dqi_q; + reg dq_en_d, dq_en_q; + + // Output assignments + assign sdram_cle = cle_q; + assign sdram_cs = cmd_q[3]; + assign sdram_ras = cmd_q[2]; + assign sdram_cas = cmd_q[1]; + assign sdram_we = cmd_q[0]; + assign sdram_dqm = dqm_q; + assign sdram_ba = ba_q; + assign sdram_a = a_q; + assign sdram_dq = dq_en_q ? dq_q : 8'hZZ; // only drive when dq_en_q is 1 + + reg [STATE_SIZE-1:0] state_d, state_q = INIT; + reg [STATE_SIZE-1:0] next_state_d, next_state_q; + + reg [22:0] addr_d, addr_q; + reg [31:0] data_d, data_q; + reg out_valid_d, out_valid_q; + + assign data_out = data_q; + assign busy = !ready_q; + assign out_valid = out_valid_q; + + reg [15:0] delay_ctr_d, delay_ctr_q; + reg [1:0] byte_ctr_d, byte_ctr_q; + + reg [9:0] refresh_ctr_d, refresh_ctr_q; + reg refresh_flag_d, refresh_flag_q; + + reg ready_d, ready_q; + reg saved_rw_d, saved_rw_q; + reg [22:0] saved_addr_d, saved_addr_q; + reg [31:0] saved_data_d, saved_data_q; + + reg rw_op_d, rw_op_q; + + reg [3:0] row_open_d, row_open_q; + reg [12:0] row_addr_d[3:0], row_addr_q[3:0]; + + reg [2:0] precharge_bank_d, precharge_bank_q; + integer i; + + always @* begin + // Default values + dq_d = dq_q; + dqi_d = sdram_dq; + dq_en_d = 1'b0; // normally keep the bus in high-Z + cle_d = cle_q; + cmd_d = CMD_NOP; // default to NOP + dqm_d = 1'b0; + ba_d = 2'd0; + a_d = 25'd0; + state_d = state_q; + next_state_d = next_state_q; + delay_ctr_d = delay_ctr_q; + addr_d = addr_q; + data_d = data_q; + out_valid_d = 1'b0; + precharge_bank_d = precharge_bank_q; + rw_op_d = rw_op_q; + byte_ctr_d = 2'd0; + + row_open_d = row_open_q; + + // row_addr is a 2d array and must be coppied this way + for (i = 0; i < 4; i = i + 1) + row_addr_d[i] = row_addr_q[i]; + + // The data in the SDRAM must be refreshed periodically. + // This conter ensures that the data remains intact. + refresh_flag_d = refresh_flag_q; + refresh_ctr_d = refresh_ctr_q + 1'b1; + if (refresh_ctr_q > 10'd750) begin + refresh_ctr_d = 10'd0; + refresh_flag_d = 1'b1; + end + + saved_rw_d = saved_rw_q; + saved_data_d = saved_data_q; + saved_addr_d = saved_addr_q; + ready_d = ready_q; + + // This is a queue of 1 for read/write operations. + // When the queue is empty we aren't busy and can + // accept another request. + if (ready_q && in_valid) begin + saved_rw_d = rw; + saved_data_d = data_in; + saved_addr_d = addr; + ready_d = 1'b0; + end + + case (state_q) + ///// INITALIZATION ///// + INIT: begin + ready_d = 1'b0; + row_open_d = 4'b0; + out_valid_d = 1'b0; + a_d = 13'b0; + ba_d = 2'b0; + cle_d = 1'b1; + state_d = WAIT; + delay_ctr_d = 16'd10100; // wait for 101us + next_state_d = PRECHARGE_INIT; + dq_en_d = 1'b0; + end + WAIT: begin + delay_ctr_d = delay_ctr_q - 1'b1; + if (delay_ctr_q == 13'd0) begin + state_d = next_state_q; + if (next_state_q == WRITE) begin + dq_en_d = 1'b1; // enable the bus early + dq_d = data_q[7:0]; + end + end + end + PRECHARGE_INIT: begin + cmd_d = CMD_PRECHARGE; + a_d[10] = 1'b1; // all banks + ba_d = 2'd0; + state_d = WAIT; + next_state_d = REFRESH_INIT_1; + delay_ctr_d = 13'd0; + end + REFRESH_INIT_1: begin + cmd_d = CMD_REFRESH; + state_d = WAIT; + delay_ctr_d = 13'd7; + next_state_d = REFRESH_INIT_2; + end + REFRESH_INIT_2: begin + cmd_d = CMD_REFRESH; + state_d = WAIT; + delay_ctr_d = 13'd7; + next_state_d = LOAD_MODE_REG; + end + LOAD_MODE_REG: begin + cmd_d = CMD_LOAD_MODE_REG; + ba_d = 2'b0; + // Reserved, Burst Access, Standard Op, CAS = 2, Sequential, Burst = 4 + a_d = {3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b010}; //010 + state_d = WAIT; + delay_ctr_d = 13'd1; + next_state_d = IDLE; + refresh_flag_d = 1'b0; + refresh_ctr_d = 10'b1; + ready_d = 1'b1; + end + + ///// IDLE STATE ///// + IDLE: begin + if (refresh_flag_q) begin // we need to do a refresh + state_d = PRECHARGE; + next_state_d = REFRESH; + precharge_bank_d = 3'b100; // all banks + refresh_flag_d = 1'b0; // clear the refresh flag + end else if (!ready_q) begin // operation waiting + ready_d = 1'b1; // clear the queue + rw_op_d = saved_rw_q; // save the values we'll need later + addr_d = saved_addr_q; + + if (saved_rw_q) // Write + data_d = saved_data_q; + + // if the row is open we don't have to activate it + if (row_open_q[saved_addr_q[9:8]]) begin + if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin + // Row is already open + if (saved_rw_q) + state_d = WRITE; + else + state_d = READ; + end else begin + // A different row in the bank is open + state_d = PRECHARGE; // precharge open row + precharge_bank_d = {1'b0, saved_addr_q[9:8]}; + next_state_d = ACTIVATE; // open current row + end + end else begin + // no rows open + state_d = ACTIVATE; // open the row + end + end + end + + ///// REFRESH ///// + REFRESH: begin + cmd_d = CMD_REFRESH; + state_d = WAIT; + delay_ctr_d = 13'd6; // gotta wait 7 clocks (66ns) + next_state_d = IDLE; + end + + ///// ACTIVATE ///// + ACTIVATE: begin + cmd_d = CMD_ACTIVE; + a_d = addr_q[22:10]; + ba_d = addr_q[9:8]; + delay_ctr_d = 13'd0; + state_d = WAIT; + + if (rw_op_q) + next_state_d = WRITE; + else + next_state_d = READ; + + row_open_d[addr_q[9:8]] = 1'b1; // row is now open + row_addr_d[addr_q[9:8]] = addr_q[22:10]; + end + + ///// READ ///// + READ: begin + cmd_d = CMD_READ; + a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0}; + ba_d = addr_q[9:8]; + state_d = WAIT; + delay_ctr_d = 13'd2; // wait for the data to show up + next_state_d = READ_RES; + + end + READ_RES: begin + byte_ctr_d = byte_ctr_q + 1'b1; // we need to read in 4 bytes + data_d = {dqi_q, data_q[31:8]}; // shift the data in + if (byte_ctr_q == 2'd3) begin + out_valid_d = 1'b1; + state_d = IDLE; + end + end + + ///// WRITE ///// + WRITE: begin + byte_ctr_d = byte_ctr_q + 1'b1; // send out 4 bytes + + if (byte_ctr_q == 2'd0) // first byte send write command + cmd_d = CMD_WRITE; + + dq_d = data_q[7:0]; + data_d = {8'h00, data_q[31:8]}; // shift the data out + dq_en_d = 1'b1; // enable out bus + a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00}; + ba_d = addr_q[9:8]; + + if (byte_ctr_q == 2'd3) begin + state_d = IDLE; + end + end + + ///// PRECHARGE ///// + PRECHARGE: begin + cmd_d = CMD_PRECHARGE; + a_d[10] = precharge_bank_q[2]; // all banks + ba_d = precharge_bank_q[1:0]; + state_d = WAIT; + delay_ctr_d = 13'd0; + + if (precharge_bank_q[2]) begin + row_open_d = 4'b0000; // closed all rows + end else begin + row_open_d[precharge_bank_q[1:0]] = 1'b0; // closed one row + end + end + + default: state_d = INIT; + endcase + + end + + always @(posedge clk) begin + if(rst) begin + cle_q <= 1'b0; + dq_en_q <= 1'b0; + state_q <= INIT; + ready_q <= 1'b0; + end else begin + cle_q <= cle_d; + dq_en_q <= dq_en_d; + state_q <= state_d; + ready_q <= ready_d; + end + + saved_rw_q <= saved_rw_d; + saved_data_q <= saved_data_d; + saved_addr_q <= saved_addr_d; + + cmd_q <= cmd_d; + dqm_q <= dqm_d; + ba_q <= ba_d; + a_q <= a_d; + dq_q <= dq_d; + dqi_q <= dqi_d; + + next_state_q <= next_state_d; + refresh_flag_q <= refresh_flag_d; + refresh_ctr_q <= refresh_ctr_d; + data_q <= data_d; + addr_q <= addr_d; + out_valid_q <= out_valid_d; + row_open_q <= row_open_d; + for (i = 0; i < 4; i = i + 1) + row_addr_q[i] <= row_addr_d[i]; + precharge_bank_q <= precharge_bank_d; + rw_op_q <= rw_op_d; + byte_ctr_q <= byte_ctr_d; + delay_ctr_q <= delay_ctr_d; + end +endmodule diff --git a/sdram.vhdl b/sdram.vhdl index df34a75..12763cf 100644 --- a/sdram.vhdl +++ b/sdram.vhdl @@ -71,8 +71,11 @@ architecture rtl of sdram_controller is end component; -- note to self - this constant should be "(others => '0')" when not simulating!!! +-- signal r : reg := ((others => '0'), (others => '0'), +-- (others => '0'), "000000000001000", (others => '0'), +-- '0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0')); signal r : reg := ((others => '0'), (others => '0'), - (others => '0'), "000000000001000", (others => '0'), + (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0')); signal n : reg; @@ -170,10 +173,12 @@ sdram_clk_pll: sdram_clk_gen n <= r; if req_read = '1' then n.rd_pending <= '1'; + n.data_out_valid <= '0'; end if; if req_write = '1' then n.wr_pending <= '1'; + n.data_out_valid <= '0'; end if; n.dq_masks <= "11"; diff --git a/sdram.vhdl.bak b/sdram.vhdl.bak new file mode 100644 index 0000000..df34a75 --- /dev/null +++ b/sdram.vhdl.bak @@ -0,0 +1,510 @@ +------------------------------------------------------ +-- FSM for a SDRAM controller +-- +-- Version 0.1 - Ready to simulate +-- +-- Author: Mike Field (hamster@snap.net.nz) +-- +-- Feel free to use it however you would like, but +-- just drop me an email to say thanks. +------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity sdram_controller is + PORT ( + CLOCK_50 : IN STD_LOGIC; + + -- Signals to/from the SDRAM chip + DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0); + DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); + DRAM_CAS_N : OUT STD_LOGIC; + DRAM_CKE : OUT STD_LOGIC; + DRAM_CLK : OUT STD_LOGIC; + DRAM_CS_N : OUT STD_LOGIC; + DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); + DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); + DRAM_RAS_N : OUT STD_LOGIC; + DRAM_WE_N : OUT STD_LOGIC; + + --- Inputs from rest of the system + address : IN STD_LOGIC_VECTOR (23 downto 0); + req_read : IN STD_LOGIC; + req_write : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (31 downto 0); + data_out_valid : OUT STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 downto 0) + ); +end entity; + + +architecture rtl of sdram_controller is + + + type reg is record + state : std_logic_vector(8 downto 0); + + address : std_logic_vector(12 downto 0); + bank : std_logic_vector( 1 downto 0); + + init_counter: std_logic_vector(14 downto 0); + rf_counter : std_logic_vector( 9 downto 0); + rf_pending : std_logic; + + rd_pending : std_logic; + wr_pending : std_logic; + act_row : std_logic_vector(12 downto 0); + + data_out_low: std_logic_vector(15 downto 0); + data_out_valid : std_logic; + + dq_masks : std_logic_vector(1 downto 0); + end record; + component sdram_clk_gen + PORT + ( + inclk0: IN STD_LOGIC; + c0 : OUT STD_LOGIC; + c1 : OUT STD_LOGIC + ); + end component; + + -- note to self - this constant should be "(others => '0')" when not simulating!!! + signal r : reg := ((others => '0'), (others => '0'), + (others => '0'), "000000000001000", (others => '0'), + '0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0')); + signal n : reg; + + -- Vectors for each SDRAM 'command' + --- CS_N, RAS_N, CAS_N, WE_N + constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; + constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. + constant cmd_write : std_logic_vector(3 downto 0) := "0100"; + constant cmd_act : std_logic_vector(3 downto 0) := "0011"; + constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. + constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; + constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set + -- State assignments + constant s_init_nop : std_logic_vector(8 downto 0) := "00000" & cmd_nop; + constant s_init_pre : std_logic_vector(8 downto 0) := "00000" & cmd_pre; + constant s_init_ref : std_logic_vector(8 downto 0) := "00000" & cmd_ref; + constant s_init_mrs : std_logic_vector(8 downto 0) := "00000" & cmd_mrs; + + constant s_idle : std_logic_vector(8 downto 0) := "00001" & cmd_nop; + + constant s_rf0 : std_logic_vector(8 downto 0) := "00010" & cmd_ref; + constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; + constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; + constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; + constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; + constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; + + constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; + constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; + constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; + + constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; + constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; + + constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; + constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; + constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; + constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_nop; + + constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; + constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_nop; + constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; + constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_nop; + constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; + constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_nop; + constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; + constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; + constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; + constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; + + constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; + constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; + constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; + + signal addr_row : std_logic_vector(12 downto 0); + signal addr_bank: std_logic_vector(1 downto 0); + signal addr_col : std_logic_vector(9 downto 0); + + signal captured : std_logic_vector(15 downto 0); + + signal clock_100 : std_logic; + signal clock_100_delayed_3ns : std_logic; +begin + -- Addressing is in 32 bit words - twice that of the DRAM width, + -- so each burst of four access two system words. + addr_row <= address(23 downto 11); + addr_bank <= address(10 downto 9); + addr_col <= address(8 downto 1) & "00"; + +sdram_clk_pll: sdram_clk_gen + + -- Generate the 100MHz clock and the same phase shifted by 3ns + PORT MAP + ( + inclk0 => CLOCK_50, + c0 => clock_100, + c1 => clock_100_delayed_3ns + ); + + DRAM_CLK <= clock_100_delayed_3ns; + DRAM_CKE <= '1'; + DRAM_CS_N <= r.state(3); + DRAM_RAS_N <= r.state(2); + DRAM_CAS_N <= r.state(1); + DRAM_WE_N <= r.state(0); + DRAM_ADDR <= r.address; + DRAM_BA <= r.bank; + DATA_OUT <= captured & r.data_out_low; + DRAM_DQM <= r.dq_masks; + data_out_valid <= r.data_out_valid; + + process (r, address, req_read, req_write, addr_row, addr_bank, addr_col, data_in, captured) + begin + -- copy the existing values + n <= r; + if req_read = '1' then + n.rd_pending <= '1'; + end if; + + if req_write = '1' then + n.wr_pending <= '1'; + end if; + + n.dq_masks <= "11"; + + -- first off, do we need to perform a refresh cycle ASAP? + if r.rf_counter = 770 then -- 781 = 64,000,000ns / 8192 / 10ns + n.rf_counter <= (others => '0'); + n.rf_pending <= '1'; + else + -- only start looking for refreshes outside of the initialisation state. + if not(r.state(8 downto 4) = s_init_nop(8 downto 4)) then + n.rf_counter <= r.rf_counter + 1; + end if; + end if; + + -- Set the data bus into HIZ, high and low bytes masked + DRAM_DQ <= (others => 'Z'); + + n.init_counter <= r.init_counter-1; + + -- Process the FSM + case r.state(8 downto 4) is + when s_init_nop(8 downto 4) => + n.state <= s_init_nop; + n.address <= (others => '0'); + n.bank <= (others => '0'); + n.rf_counter <= (others => '0'); + n.data_out_valid <= '1'; + + -- T-130, precharge all banks. + if r.init_counter = "000000010000010" then + n.state <= s_init_pre; + n.address(10) <= '1'; + end if; + + -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes + + if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then + n.state <= s_init_ref; + end if; + + -- T-3, the load mode register + if r.init_counter = 3 then + n.state <= s_init_mrs; + -- Mode register is as follows: + -- resvd wr_b OpMd CAS=3 Seq bust=4 + n.address <= "000" & "0" & "00" & "011" & "0" & "010"; + -- resvd + n.bank <= "00"; + end if; + + + -- T-1 The switch to the FSM (first command will be a NOP + if r.init_counter = 1 then + n.state <= s_idle; + end if; + + ------------------------------ + -- The Idle section + ------------------------------ + when s_idle(8 downto 4) => + n.state <= s_idle; + + -- do we have to activate a row? + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + end if; + + -- refreshes take priority over everything + if r.rf_pending = '1' then + n.state <= s_rf0; + n.rf_pending <= '0'; + end if; + ------------------------------ + -- Row activation + -- s_ra2 is also the "idle with active row" state and provides + -- a resting point between operations on the same row + ------------------------------ + when s_ra0(8 downto 4) => + n.state <= s_ra1; + when s_ra1(8 downto 4) => + n.state <= s_ra2; + when s_ra2(8 downto 4) => + -- we can stay in this state until we have something to do + n.state <= s_ra2; + + -- If there is a read pending, deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + -- unless we have a read to perform on the same row? do that instead + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + end if; + + -- unless we have a write on the same row? writes take priroty over reads + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_wr0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + n.wr_pending <= '0'; + end if; + + -- But refreshes take piority over everything! + if r.rf_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + ------------------------------------------------------ + -- Deactivate the current row and return to idle state + ------------------------------------------------------ + when s_dr0(8 downto 4) => + n.state <= s_dr1; + when s_dr1(8 downto 4) => + n.state <= s_idle; + + ------------------------------ + -- The Refresh section + ------------------------------ + when s_rf0(8 downto 4) => + n.state <= s_rf1; + when s_rf1(8 downto 4) => + n.state <= s_rf2; + when s_rf2(8 downto 4) => + n.state <= s_rf3; + when s_rf3(8 downto 4) => + n.state <= s_rf4; + when s_rf4(8 downto 4) => + n.state <= s_rf5; + when s_rf5(8 downto 4) => + n.state <= s_idle; + ------------------------------ + -- The Write section + ------------------------------ + when s_wr0(8 downto 4) => + n.state <= s_wr1; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + DRAM_DQ <= data_in(15 downto 0); + n.dq_masks<= "00"; + when s_wr1(8 downto 4) => + n.state <= s_wr2; + DRAM_DQ <= data_in(31 downto 16); + n.dq_masks<= "00"; + when s_wr2(8 downto 4) => + DRAM_DQ <= data_in(15 downto 0); + n.state <= s_wr3; + n.dq_masks<= "00"; + when s_wr3(8 downto 4) => + -- Default to the idle+row active state + n.state <= s_ra2; + DRAM_DQ <= data_in(31 downto 16); + n.dq_masks<= "11"; + + -- If there is a read or write then deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + -- But if there is a read pending in the same row, do that + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + end if; + + -- unless there is a write pending in the same row, do that + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_wr0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + n.wr_pending <= '0'; + end if; + + -- But always try and refresh if one is pending! + if r.rf_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Read section + ------------------------------ + when s_rd0(8 downto 4) => + n.state <= s_rd1; + n.dq_masks <= "00"; + when s_rd1(8 downto 4) => + n.state <= s_rd2; + n.dq_masks <= "00"; + when s_rd2(8 downto 4) => + n.state <= s_rd3; + n.dq_masks <= "00"; + when s_rd3(8 downto 4) => + -- default is to end the read with the row open + n.state <= s_rd7; + + -- otherwise if there is a read or write prepare to deactivate the row. + -- (This is overridden if the read/write is to the same page) + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_drdr0; + n.address(10) <= '1'; + end if; + + -- override if the write is from the same row + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_rd7; + end if; + + -- override if the read is from the same row + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd4; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + end if; + + -- If a refresh is pending then always deactivate the row + if r.rf_pending = '1' then + n.state <= s_drdr0; + n.address(10) <= '1'; + end if; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_rd4(8 downto 4) => + n.state <= s_rd5; + n.dq_masks<= "00"; + when s_rd5(8 downto 4) => + n.state <= s_rd6; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + n.dq_masks<= "00"; + when s_rd6(8 downto 4) => + n.state <= s_rd3; + n.dq_masks<= "00"; + when s_rd7(8 downto 4) => + n.state <= s_rd8; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_rd8(8 downto 4) => + n.state <= s_rd9; + when s_rd9(8 downto 4) => + -- by default go to the idle-with-row-active state + n.state <= s_ra2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + + -- otherwise if there is a read or write prepare to deactivate the row. + -- (This is overridden if the read/write is to the same row) + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + -- this is to catch if a read has turned up since the choices at state s_dr3 + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + end if; + + -- this is to catch if a read has turned up since the choices at state s_dr3 + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_wr0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + n.wr_pending <= '0'; + end if; + + if r.rf_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Deactivate row during read section + ------------------------------ + when s_drdr0(8 downto 4) => + n.state <= s_drdr1; + when s_drdr1(8 downto 4) => + n.state <= s_drdr2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_drdr2(8 downto 4) => + n.state <= s_idle; + + if r.rf_pending = '1' then + n.state <= s_rf0; + end if; + + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + when others => + n.state <= s_init_nop; + end case; + end process; + + --- The clock driven logic + process (clock_100, n) + begin + if clock_100'event and clock_100 = '1' then + r <= n; + end if; + end process; + + process (clock_100_delayed_3ns, dram_dq) + begin + if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then + captured <= dram_dq; + end if; + end process; + +end rtl; \ No newline at end of file diff --git a/sdram_controller.v b/sdram_controller.v new file mode 100644 index 0000000..f1955e6 --- /dev/null +++ b/sdram_controller.v @@ -0,0 +1,417 @@ +/** + * simple controller for ISSI IS42S16160G-7 SDRAM found in De0 Nano + * 16Mbit x 16 data bit bus (32 megabytes) + * Default options + * 133Mhz + * CAS 3 + * + * Very simple host interface + * * No burst support + * * haddr - address for reading and wriging 16 bits of data + * * data_input - data for writing, latched in when wr_enable is highz0 + * * data_output - data for reading, comes available sometime + * *few clocks* after rd_enable and address is presented on bus + * * rst_n - start init ram process + * * rd_enable - read enable, on clk posedge haddr will be latched in, + * after *few clocks* data will be available on the data_output port + * * wr_enable - write enable, on clk posedge haddr and data_input will + * be latched in, after *few clocks* data will be written to sdram + * + * Theory + * This simple host interface has a busy signal to tell you when you are + * not able to issue commands. + */ + +module sdram_controller_new ( + /* HOST INTERFACE */ + wr_addr, + wr_data, + wr_enable, + + rd_addr, + rd_data, + rd_ready, + rd_enable, + + busy, rst_n, clk, + + /* SDRAM SIDE */ + addr, bank_addr, data, clock_enable, cs_n, ras_n, cas_n, we_n, + data_mask_low, data_mask_high +); + +/* Internal Parameters */ +parameter ROW_WIDTH = 13; +parameter COL_WIDTH = 9; +parameter BANK_WIDTH = 2; + +parameter SDRADDR_WIDTH = ROW_WIDTH > COL_WIDTH ? ROW_WIDTH : COL_WIDTH; +parameter HADDR_WIDTH = BANK_WIDTH + ROW_WIDTH + COL_WIDTH; + +parameter CLK_FREQUENCY = 100; // Mhz +parameter REFRESH_TIME = 32; // ms (how often we need to refresh). original = 32 +parameter REFRESH_COUNT = 8192; // cycles (how many refreshes required per refresh time) + +// clk / refresh = clk / sec +// , sec / refbatch +// , ref / refbatch +localparam CYCLES_BETWEEN_REFRESH = ( CLK_FREQUENCY + * 1_000 + * REFRESH_TIME + ) / REFRESH_COUNT; + +// STATES - State +localparam IDLE = 5'b00000; + +localparam INIT_NOP1 = 5'b01000, + INIT_PRE1 = 5'b01001, + INIT_NOP1_1=5'b00101, + INIT_REF1 = 5'b01010, + INIT_NOP2 = 5'b01011, + INIT_REF2 = 5'b01100, + INIT_NOP3 = 5'b01101, + INIT_LOAD = 5'b01110, + INIT_NOP4 = 5'b01111; + +localparam REF_PRE = 5'b00001, + REF_NOP1 = 5'b00010, + REF_REF = 5'b00011, + REF_NOP2 = 5'b00100; + +localparam READ_ACT = 5'b10000, + READ_NOP1 = 5'b10001, + READ_CAS = 5'b10010, + READ_NOP2 = 5'b10011, + READ_READ = 5'b10100; + +localparam WRIT_ACT = 5'b11000, + WRIT_NOP1 = 5'b11001, + WRIT_CAS = 5'b11010, + WRIT_NOP2 = 5'b11011; + +// Commands CCRCWBBA +// ESSSE100 +localparam CMD_PALL = 8'b10010001, + CMD_REF = 8'b10001000, + CMD_NOP = 8'b10111000, + CMD_MRS = 8'b1000000x, + CMD_BACT = 8'b10011xxx, + CMD_READ = 8'b10101xx1, + CMD_WRIT = 8'b10100xx1; + +/* Interface Definition */ +/* HOST INTERFACE */ +input [HADDR_WIDTH-1:0] wr_addr; +input [15:0] wr_data; +input wr_enable; + +input [HADDR_WIDTH-1:0] rd_addr; +output [15:0] rd_data; +input rd_enable; +output rd_ready; + +output busy; +input rst_n; +input clk; + +/* SDRAM SIDE */ +output [SDRADDR_WIDTH-1:0] addr; +output [BANK_WIDTH-1:0] bank_addr; +inout [15:0] data; +output clock_enable; +output cs_n; +output ras_n; +output cas_n; +output we_n; +output data_mask_low; +output data_mask_high; + +/* I/O Registers */ + +reg [HADDR_WIDTH-1:0] haddr_r; +reg [15:0] wr_data_r; +reg [15:0] rd_data_r; +reg busy; +reg data_mask_low_r; +reg data_mask_high_r; +reg [SDRADDR_WIDTH-1:0] addr_r; +reg [BANK_WIDTH-1:0] bank_addr_r; +reg rd_ready_r; + +wire [15:0] data_output; +wire data_mask_low, data_mask_high; + +assign data_mask_high = data_mask_high_r; +assign data_mask_low = data_mask_low_r; +assign rd_data = rd_data_r; + +/* Internal Wiring */ +reg [3:0] state_cnt; +reg [9:0] refresh_cnt; + +reg [7:0] command; +reg [4:0] state; + +// TODO output addr[6:4] when programming mode register + +reg [7:0] command_nxt; +reg [3:0] state_cnt_nxt; +reg [4:0] next; + +assign {clock_enable, cs_n, ras_n, cas_n, we_n} = command[7:3]; +// state[4] will be set if mode is read/write +assign bank_addr = (state[4]) ? bank_addr_r : command[2:1]; +assign addr = (state[4] | state == INIT_LOAD) ? addr_r : { {SDRADDR_WIDTH-11{1'b0}}, command[0], 10'd0 }; + +assign data = (state == WRIT_CAS) ? wr_data_r : 16'bz; +assign rd_ready = rd_ready_r; + +// HOST INTERFACE +// all registered on posedge +always @ (posedge clk) + if (~rst_n) + begin + state <= INIT_NOP1; + command <= CMD_NOP; + state_cnt <= 4'hf; + + haddr_r <= {HADDR_WIDTH{1'b0}}; + wr_data_r <= 16'b0; + rd_data_r <= 16'b0; + busy <= 1'b0; + end + else + begin + + state <= next; + command <= command_nxt; + + if (!state_cnt) + state_cnt <= state_cnt_nxt; + else + state_cnt <= state_cnt - 1'b1; + + if (wr_enable) + wr_data_r <= wr_data; + + if (state == READ_READ) + begin + rd_data_r <= data; + rd_ready_r <= 1'b1; + end + else + rd_ready_r <= 1'b0; + + busy <= state[4]; + + if (rd_enable) + haddr_r <= rd_addr; + else if (wr_enable) + haddr_r <= wr_addr; + + end + +// Handle refresh counter +always @ (posedge clk) + if (~rst_n) + refresh_cnt <= 10'b0; + else + if (state == REF_NOP2) + refresh_cnt <= 10'b0; + else + refresh_cnt <= refresh_cnt + 1'b1; + + +/* Handle logic for sending addresses to SDRAM based on current state*/ +always @* +begin + if (state[4]) + {data_mask_low_r, data_mask_high_r} = 2'b00; + else + {data_mask_low_r, data_mask_high_r} = 2'b11; + + bank_addr_r = 2'b00; + addr_r = {SDRADDR_WIDTH{1'b0}}; + + if (state == READ_ACT | state == WRIT_ACT) + begin + bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)]; + addr_r = haddr_r[HADDR_WIDTH-(BANK_WIDTH+1):HADDR_WIDTH-(BANK_WIDTH+ROW_WIDTH)]; + end + else if (state == READ_CAS | state == WRIT_CAS) + begin + // Send Column Address + // Set bank to bank to precharge + bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)]; + + // Examples for math + // BANK ROW COL + // HADDR_WIDTH 2 + 13 + 9 = 24 + // SDRADDR_WIDTH 13 + + // Set CAS address to: + // 0s, + // 1 (A10 is always for auto precharge), + // 0s, + // column address + addr_r = { + {SDRADDR_WIDTH-(11){1'b0}}, + 1'b1, /* A10 */ + {10-COL_WIDTH{1'b0}}, + haddr_r[COL_WIDTH-1:0] + }; + end + else if (state == INIT_LOAD) + begin + // Program mode register during load cycle + // B C SB + // R A EUR + // S S-3Q ST + // T 654L210 + addr_r = {{SDRADDR_WIDTH-10{1'b0}}, 10'b1000110000}; + end +end + +// Next state logic +always @* +begin + state_cnt_nxt = 4'd0; + command_nxt = CMD_NOP; + if (state == IDLE) + // Monitor for refresh or hold + if (refresh_cnt >= CYCLES_BETWEEN_REFRESH) + begin + next = REF_PRE; + command_nxt = CMD_PALL; + end + else if (rd_enable) + begin + next = READ_ACT; + command_nxt = CMD_BACT; + end + else if (wr_enable) + begin + next = WRIT_ACT; + command_nxt = CMD_BACT; + end + else + begin + // HOLD + next = IDLE; + end + else + if (!state_cnt) + case (state) + // INIT ENGINE + INIT_NOP1: + begin + next = INIT_PRE1; + command_nxt = CMD_PALL; + end + INIT_PRE1: + begin + next = INIT_NOP1_1; + end + INIT_NOP1_1: + begin + next = INIT_REF1; + command_nxt = CMD_REF; + end + INIT_REF1: + begin + next = INIT_NOP2; + state_cnt_nxt = 4'd7; + end + INIT_NOP2: + begin + next = INIT_REF2; + command_nxt = CMD_REF; + end + INIT_REF2: + begin + next = INIT_NOP3; + state_cnt_nxt = 4'd7; + end + INIT_NOP3: + begin + next = INIT_LOAD; + command_nxt = CMD_MRS; + end + INIT_LOAD: + begin + next = INIT_NOP4; + state_cnt_nxt = 4'd1; + end + // INIT_NOP4: default - IDLE + + // REFRESH + REF_PRE: + begin + next = REF_NOP1; + end + REF_NOP1: + begin + next = REF_REF; + command_nxt = CMD_REF; + end + REF_REF: + begin + next = REF_NOP2; + state_cnt_nxt = 4'd7; + end + // REF_NOP2: default - IDLE + + // WRITE + WRIT_ACT: + begin + next = WRIT_NOP1; + state_cnt_nxt = 4'd1; + end + WRIT_NOP1: + begin + next = WRIT_CAS; + command_nxt = CMD_WRIT; + end + WRIT_CAS: + begin + next = WRIT_NOP2; + state_cnt_nxt = 4'd1; + end + // WRIT_NOP2: default - IDLE + + // READ + READ_ACT: + begin + next = READ_NOP1; + state_cnt_nxt = 4'd1; + end + READ_NOP1: + begin + next = READ_CAS; + command_nxt = CMD_READ; + end + READ_CAS: + begin + next = READ_NOP2; + state_cnt_nxt = 4'd1; + end + READ_NOP2: + begin + next = READ_READ; + end + // READ_READ: default - IDLE + + default: + begin + next = IDLE; + end + endcase + else + begin + // Counter Not Reached - HOLD + next = state; + command_nxt = command; + end +end + +endmodule \ No newline at end of file diff --git a/sdram_controller.v.bak b/sdram_controller.v.bak new file mode 100644 index 0000000..852fb56 --- /dev/null +++ b/sdram_controller.v.bak @@ -0,0 +1,417 @@ +/** + * simple controller for ISSI IS42S16160G-7 SDRAM found in De0 Nano + * 16Mbit x 16 data bit bus (32 megabytes) + * Default options + * 133Mhz + * CAS 3 + * + * Very simple host interface + * * No burst support + * * haddr - address for reading and wriging 16 bits of data + * * data_input - data for writing, latched in when wr_enable is highz0 + * * data_output - data for reading, comes available sometime + * *few clocks* after rd_enable and address is presented on bus + * * rst_n - start init ram process + * * rd_enable - read enable, on clk posedge haddr will be latched in, + * after *few clocks* data will be available on the data_output port + * * wr_enable - write enable, on clk posedge haddr and data_input will + * be latched in, after *few clocks* data will be written to sdram + * + * Theory + * This simple host interface has a busy signal to tell you when you are + * not able to issue commands. + */ + +module sdram_controller_new ( + /* HOST INTERFACE */ + wr_addr, + wr_data, + wr_enable, + + rd_addr, + rd_data, + rd_ready, + rd_enable, + + busy, rst_n, clk, + + /* SDRAM SIDE */ + addr, bank_addr, data, clock_enable, cs_n, ras_n, cas_n, we_n, + data_mask_low, data_mask_high +); + +/* Internal Parameters */ +parameter ROW_WIDTH = 13; +parameter COL_WIDTH = 9; +parameter BANK_WIDTH = 2; + +parameter SDRADDR_WIDTH = ROW_WIDTH > COL_WIDTH ? ROW_WIDTH : COL_WIDTH; +parameter HADDR_WIDTH = BANK_WIDTH + ROW_WIDTH + COL_WIDTH; + +parameter CLK_FREQUENCY = 133; // Mhz +parameter REFRESH_TIME = 32; // ms (how often we need to refresh) +parameter REFRESH_COUNT = 8192; // cycles (how many refreshes required per refresh time) + +// clk / refresh = clk / sec +// , sec / refbatch +// , ref / refbatch +localparam CYCLES_BETWEEN_REFRESH = ( CLK_FREQUENCY + * 1_000 + * REFRESH_TIME + ) / REFRESH_COUNT; + +// STATES - State +localparam IDLE = 5'b00000; + +localparam INIT_NOP1 = 5'b01000, + INIT_PRE1 = 5'b01001, + INIT_NOP1_1=5'b00101, + INIT_REF1 = 5'b01010, + INIT_NOP2 = 5'b01011, + INIT_REF2 = 5'b01100, + INIT_NOP3 = 5'b01101, + INIT_LOAD = 5'b01110, + INIT_NOP4 = 5'b01111; + +localparam REF_PRE = 5'b00001, + REF_NOP1 = 5'b00010, + REF_REF = 5'b00011, + REF_NOP2 = 5'b00100; + +localparam READ_ACT = 5'b10000, + READ_NOP1 = 5'b10001, + READ_CAS = 5'b10010, + READ_NOP2 = 5'b10011, + READ_READ = 5'b10100; + +localparam WRIT_ACT = 5'b11000, + WRIT_NOP1 = 5'b11001, + WRIT_CAS = 5'b11010, + WRIT_NOP2 = 5'b11011; + +// Commands CCRCWBBA +// ESSSE100 +localparam CMD_PALL = 8'b10010001, + CMD_REF = 8'b10001000, + CMD_NOP = 8'b10111000, + CMD_MRS = 8'b1000000x, + CMD_BACT = 8'b10011xxx, + CMD_READ = 8'b10101xx1, + CMD_WRIT = 8'b10100xx1; + +/* Interface Definition */ +/* HOST INTERFACE */ +input [HADDR_WIDTH-1:0] wr_addr; +input [15:0] wr_data; +input wr_enable; + +input [HADDR_WIDTH-1:0] rd_addr; +output [15:0] rd_data; +input rd_enable; +output rd_ready; + +output busy; +input rst_n; +input clk; + +/* SDRAM SIDE */ +output [SDRADDR_WIDTH-1:0] addr; +output [BANK_WIDTH-1:0] bank_addr; +inout [15:0] data; +output clock_enable; +output cs_n; +output ras_n; +output cas_n; +output we_n; +output data_mask_low; +output data_mask_high; + +/* I/O Registers */ + +reg [HADDR_WIDTH-1:0] haddr_r; +reg [15:0] wr_data_r; +reg [15:0] rd_data_r; +reg busy; +reg data_mask_low_r; +reg data_mask_high_r; +reg [SDRADDR_WIDTH-1:0] addr_r; +reg [BANK_WIDTH-1:0] bank_addr_r; +reg rd_ready_r; + +wire [15:0] data_output; +wire data_mask_low, data_mask_high; + +assign data_mask_high = data_mask_high_r; +assign data_mask_low = data_mask_low_r; +assign rd_data = rd_data_r; + +/* Internal Wiring */ +reg [3:0] state_cnt; +reg [9:0] refresh_cnt; + +reg [7:0] command; +reg [4:0] state; + +// TODO output addr[6:4] when programming mode register + +reg [7:0] command_nxt; +reg [3:0] state_cnt_nxt; +reg [4:0] next; + +assign {clock_enable, cs_n, ras_n, cas_n, we_n} = command[7:3]; +// state[4] will be set if mode is read/write +assign bank_addr = (state[4]) ? bank_addr_r : command[2:1]; +assign addr = (state[4] | state == INIT_LOAD) ? addr_r : { {SDRADDR_WIDTH-11{1'b0}}, command[0], 10'd0 }; + +assign data = (state == WRIT_CAS) ? wr_data_r : 16'bz; +assign rd_ready = rd_ready_r; + +// HOST INTERFACE +// all registered on posedge +always @ (posedge clk) + if (~rst_n) + begin + state <= INIT_NOP1; + command <= CMD_NOP; + state_cnt <= 4'hf; + + haddr_r <= {HADDR_WIDTH{1'b0}}; + wr_data_r <= 16'b0; + rd_data_r <= 16'b0; + busy <= 1'b0; + end + else + begin + + state <= next; + command <= command_nxt; + + if (!state_cnt) + state_cnt <= state_cnt_nxt; + else + state_cnt <= state_cnt - 1'b1; + + if (wr_enable) + wr_data_r <= wr_data; + + if (state == READ_READ) + begin + rd_data_r <= data; + rd_ready_r <= 1'b1; + end + else + rd_ready_r <= 1'b0; + + busy <= state[4]; + + if (rd_enable) + haddr_r <= rd_addr; + else if (wr_enable) + haddr_r <= wr_addr; + + end + +// Handle refresh counter +always @ (posedge clk) + if (~rst_n) + refresh_cnt <= 10'b0; + else + if (state == REF_NOP2) + refresh_cnt <= 10'b0; + else + refresh_cnt <= refresh_cnt + 1'b1; + + +/* Handle logic for sending addresses to SDRAM based on current state*/ +always @* +begin + if (state[4]) + {data_mask_low_r, data_mask_high_r} = 2'b00; + else + {data_mask_low_r, data_mask_high_r} = 2'b11; + + bank_addr_r = 2'b00; + addr_r = {SDRADDR_WIDTH{1'b0}}; + + if (state == READ_ACT | state == WRIT_ACT) + begin + bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)]; + addr_r = haddr_r[HADDR_WIDTH-(BANK_WIDTH+1):HADDR_WIDTH-(BANK_WIDTH+ROW_WIDTH)]; + end + else if (state == READ_CAS | state == WRIT_CAS) + begin + // Send Column Address + // Set bank to bank to precharge + bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)]; + + // Examples for math + // BANK ROW COL + // HADDR_WIDTH 2 + 13 + 9 = 24 + // SDRADDR_WIDTH 13 + + // Set CAS address to: + // 0s, + // 1 (A10 is always for auto precharge), + // 0s, + // column address + addr_r = { + {SDRADDR_WIDTH-(11){1'b0}}, + 1'b1, /* A10 */ + {10-COL_WIDTH{1'b0}}, + haddr_r[COL_WIDTH-1:0] + }; + end + else if (state == INIT_LOAD) + begin + // Program mode register during load cycle + // B C SB + // R A EUR + // S S-3Q ST + // T 654L210 + addr_r = {{SDRADDR_WIDTH-10{1'b0}}, 10'b1000110000}; + end +end + +// Next state logic +always @* +begin + state_cnt_nxt = 4'd0; + command_nxt = CMD_NOP; + if (state == IDLE) + // Monitor for refresh or hold + if (refresh_cnt >= CYCLES_BETWEEN_REFRESH) + begin + next = REF_PRE; + command_nxt = CMD_PALL; + end + else if (rd_enable) + begin + next = READ_ACT; + command_nxt = CMD_BACT; + end + else if (wr_enable) + begin + next = WRIT_ACT; + command_nxt = CMD_BACT; + end + else + begin + // HOLD + next = IDLE; + end + else + if (!state_cnt) + case (state) + // INIT ENGINE + INIT_NOP1: + begin + next = INIT_PRE1; + command_nxt = CMD_PALL; + end + INIT_PRE1: + begin + next = INIT_NOP1_1; + end + INIT_NOP1_1: + begin + next = INIT_REF1; + command_nxt = CMD_REF; + end + INIT_REF1: + begin + next = INIT_NOP2; + state_cnt_nxt = 4'd7; + end + INIT_NOP2: + begin + next = INIT_REF2; + command_nxt = CMD_REF; + end + INIT_REF2: + begin + next = INIT_NOP3; + state_cnt_nxt = 4'd7; + end + INIT_NOP3: + begin + next = INIT_LOAD; + command_nxt = CMD_MRS; + end + INIT_LOAD: + begin + next = INIT_NOP4; + state_cnt_nxt = 4'd1; + end + // INIT_NOP4: default - IDLE + + // REFRESH + REF_PRE: + begin + next = REF_NOP1; + end + REF_NOP1: + begin + next = REF_REF; + command_nxt = CMD_REF; + end + REF_REF: + begin + next = REF_NOP2; + state_cnt_nxt = 4'd7; + end + // REF_NOP2: default - IDLE + + // WRITE + WRIT_ACT: + begin + next = WRIT_NOP1; + state_cnt_nxt = 4'd1; + end + WRIT_NOP1: + begin + next = WRIT_CAS; + command_nxt = CMD_WRIT; + end + WRIT_CAS: + begin + next = WRIT_NOP2; + state_cnt_nxt = 4'd1; + end + // WRIT_NOP2: default - IDLE + + // READ + READ_ACT: + begin + next = READ_NOP1; + state_cnt_nxt = 4'd1; + end + READ_NOP1: + begin + next = READ_CAS; + command_nxt = CMD_READ; + end + READ_CAS: + begin + next = READ_NOP2; + state_cnt_nxt = 4'd1; + end + READ_NOP2: + begin + next = READ_READ; + end + // READ_READ: default - IDLE + + default: + begin + next = IDLE; + end + endcase + else + begin + // Counter Not Reached - HOLD + next = state; + command_nxt = command; + end +end + +endmodule \ No newline at end of file diff --git a/sdram_ctrl.v b/sdram_ctrl.v new file mode 100644 index 0000000..44cce3b --- /dev/null +++ b/sdram_ctrl.v @@ -0,0 +1,125 @@ +/////////////////////////////////////////////// +// Demo SDRAM controller for MT48LC1M16A1 legacy SDRAM +// (C) fpga4fun.com & KNJN LLC 2014 + +// The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits (using 2 banks) + +// This controller feature set has been reduced to make it easy to understand +// It is based on a more complete controller targeted for Xylo-EM and Xylo-LM boards + +// Assumptions: +// 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode +// 2. the read agent is active enough to refresh the RAM (if not, add a refresh timer) + +// For more info, check +// http://www.fpga4fun.com/SDRAM.html + +/////////////////////////////////////////////// +module SDRAM_ctrl( + input clk, + + // read agent + input RdReq, + output RdGnt, + input [19:0] RdAddr, + output reg [15:0] RdData, + output RdDataValid, + + // write agent + input WrReq, + output WrGnt, + input [19:0] WrAddr, + input [15:0] WrData, + + // SDRAM + output SDRAM_CKE, SDRAM_WEn, SDRAM_CASn, SDRAM_RASn, + output reg [10:0] SDRAM_A, + output reg [0:0] SDRAM_BA, + output reg [1:0] SDRAM_DQM = 2'b11, + inout [15:0] SDRAM_DQ +); + +assign SDRAM_CKE = 1'b1; + +localparam [2:0] SDRAM_CMD_LOADMODE = 3'b000; +localparam [2:0] SDRAM_CMD_REFRESH = 3'b001; +localparam [2:0] SDRAM_CMD_PRECHARGE = 3'b010; +localparam [2:0] SDRAM_CMD_ACTIVE = 3'b011; +localparam [2:0] SDRAM_CMD_WRITE = 3'b100; +localparam [2:0] SDRAM_CMD_READ = 3'b101; +localparam [2:0] SDRAM_CMD_NOP = 3'b111; + +reg [2:0] SDRAM_CMD = SDRAM_CMD_NOP; +assign {SDRAM_RASn, SDRAM_CASn, SDRAM_WEn} = SDRAM_CMD; + +// here we decide which of reads or writes have priority +wire read_now = RdReq; // give priority to read requests +wire write_now = ~RdReq & WrReq; // and if a read is not requested, give writes a chance... + +reg [1:0] state=0; +reg ReadSelected=0; always @(posedge clk) if(state==2'h0) ReadSelected <= read_now; +wire WriteSelected = ~ReadSelected; + +wire ReadCycle = (state==2'h0) ? read_now : ReadSelected; +wire [19:0] Addr = ReadCycle ? RdAddr : WrAddr; +reg [19:0] AddrR=0; always @(posedge clk) AddrR <= Addr; + +wire SameRowAndBank = (Addr[19:8]==AddrR[19:8]); +assign RdGnt = (state==2'h0 & read_now) | (state==2'h1 & ReadSelected & RdReq & SameRowAndBank); +assign WrGnt = (state==2'h0 & write_now) | (state==2'h1 & WriteSelected & WrReq & SameRowAndBank); + +always @(posedge clk) +case(state) + 2'h0: begin + if(RdReq | WrReq) begin // is there a read or write request? + SDRAM_CMD <= SDRAM_CMD_ACTIVE; // if so activate + SDRAM_BA <= Addr[19]; // this bank + SDRAM_A <= Addr[18:8]; // this row + SDRAM_DQM <= 2'b11; + state <= 2'h1; + end + else + begin + SDRAM_CMD <= SDRAM_CMD_NOP; // otherwise stay idle + SDRAM_BA <= 0; + SDRAM_A <= 0; + SDRAM_DQM <= 2'b11; + state <= 2'h0; + end + end + 2'h1: begin + SDRAM_CMD <= ReadSelected ? SDRAM_CMD_READ : SDRAM_CMD_WRITE; + SDRAM_BA <= AddrR[19]; + SDRAM_A[9:0] <= {2'b00, AddrR[7:0]}; // column + SDRAM_A[10] <= 1'b0; // no auto-precharge + SDRAM_DQM <= 2'b00; + state <= (ReadSelected ? RdReq : WrReq) & SameRowAndBank ? 2'h1 : 2'h2; + end + 2'h2: begin + SDRAM_CMD <= SDRAM_CMD_PRECHARGE; // close the row when we're done with it + SDRAM_BA <= 0; + SDRAM_A <= 11'b100_0000_0000; // all banks precharge + SDRAM_DQM <= 2'b11; + state <= 2'h0; + end + 2'h3: begin + SDRAM_CMD <= SDRAM_CMD_NOP; + SDRAM_BA <= 0; + SDRAM_A <= 0; + SDRAM_DQM <= 2'b11; + state <= 2'h0; + end +endcase + +localparam trl = 4; // total read latency is the SDRAM CAS-latency (two) plus the SDRAM controller induced latency (two) +reg [trl-1:0] RdDataValidPipe; always @(posedge clk) RdDataValidPipe <= {RdDataValidPipe[trl-2:0], state==2'h1 & ReadSelected}; +assign RdDataValid = RdDataValidPipe[trl-1]; +always @(posedge clk) RdData <= SDRAM_DQ; + +reg SDRAM_DQ_OE = 1'b0; always @(posedge clk) SDRAM_DQ_OE <= (state==2'h1) & WriteSelected; +reg [15:0] WrData1=0; always @(posedge clk) WrData1 <= WrData; +reg [15:0] WrData2=0; always @(posedge clk) WrData2 <= WrData1; + +assign SDRAM_DQ = SDRAM_DQ_OE ? WrData2 : 16'hZZZZ; +endmodule +/////////////////////////////////////////////// diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index dcf16aa..8657f3e 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/02/2022 14:51:21" +// DATE "04/06/2022 13:58:28" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -60,14 +60,18 @@ module spectrum ( DRAM_WE_N, DRAM_CS_N, DRAM_DQ, - DRAM_ADDR); + DRAM_ADDR, + kempston, + kempston_gnd, + turbo_button, + kempston_autofire_button); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -80,7 +84,7 @@ output [3:0] VGA_B; output VGA_HS; output VGA_VS; input [3:0] SW; -output [33:0] GPIO_1; +output [31:0] GPIO_1; output buzzer_out; input raw_loader_in; output [1:0] DRAM_BA; @@ -91,8 +95,12 @@ output DRAM_CKE; output DRAM_CLK; output DRAM_WE_N; output DRAM_CS_N; -inout [15:0] DRAM_DQ; +output [15:0] DRAM_DQ; output [12:0] DRAM_ADDR; +input [4:0] kempston; +output kempston_gnd; +input turbo_button; +input kempston_autofire_button; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -123,6 +131,7 @@ output [12:0] DRAM_ADDR; // VGA_HS => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // VGA_VS => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[0] => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[3] => Location: PIN_M15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // GPIO_1[0] => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[1] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -156,8 +165,6 @@ output [12:0] DRAM_ADDR; // GPIO_1[29] => Location: PIN_L13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[30] => Location: PIN_J16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[31] => Location: PIN_K15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -182,6 +189,7 @@ output [12:0] DRAM_ADDR; // DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// kempston_gnd => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -201,10 +209,16 @@ output [12:0] DRAM_ADDR; // DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[0] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[1] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[2] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[3] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[4] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// turbo_button => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston_autofire_button => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -227,6 +241,7 @@ initial $sdf_annotate("spectrum_v.sdo"); // synopsys translate_on wire \SW[0]~input_o ; +wire \SW[2]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; wire \DRAM_DQ[0]~input_o ; @@ -248,13 +263,69 @@ wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \turbo_button~input_o ; +wire \CLOCK_50~inputclkctrl_outclk ; +wire \debounce_turbo|r_Count[0]~21_combout ; +wire \debounce_turbo|r_Count[0]~22 ; +wire \debounce_turbo|r_Count[1]~23_combout ; +wire \debounce_turbo|r_Count[1]~24 ; +wire \debounce_turbo|r_Count[2]~25_combout ; +wire \debounce_turbo|r_Count[2]~26 ; +wire \debounce_turbo|r_Count[3]~27_combout ; +wire \debounce_turbo|r_Count[3]~28 ; +wire \debounce_turbo|r_Count[4]~29_combout ; +wire \debounce_turbo|r_Count[4]~30 ; +wire \debounce_turbo|r_Count[5]~31_combout ; +wire \debounce_turbo|r_Count[5]~32 ; +wire \debounce_turbo|r_Count[6]~33_combout ; +wire \debounce_turbo|r_Count[6]~34 ; +wire \debounce_turbo|r_Count[7]~35_combout ; +wire \debounce_turbo|r_Count[7]~36 ; +wire \debounce_turbo|r_Count[8]~37_combout ; +wire \debounce_turbo|r_Count[8]~38 ; +wire \debounce_turbo|r_Count[9]~39_combout ; +wire \debounce_turbo|r_Count[9]~40 ; +wire \debounce_turbo|r_Count[10]~41_combout ; +wire \debounce_turbo|r_Count[10]~42 ; +wire \debounce_turbo|r_Count[11]~43_combout ; +wire \debounce_turbo|r_Count[11]~44 ; +wire \debounce_turbo|r_Count[12]~45_combout ; +wire \debounce_turbo|r_Count[12]~46 ; +wire \debounce_turbo|r_Count[13]~47_combout ; +wire \debounce_turbo|r_State~7_combout ; +wire \debounce_turbo|LessThan0~0_combout ; +wire \debounce_turbo|LessThan0~1_combout ; +wire \debounce_turbo|r_Count[13]~48 ; +wire \debounce_turbo|r_Count[14]~49_combout ; +wire \debounce_turbo|r_Count[14]~50 ; +wire \debounce_turbo|r_Count[15]~51_combout ; +wire \debounce_turbo|r_Count[15]~52 ; +wire \debounce_turbo|r_Count[16]~53_combout ; +wire \debounce_turbo|r_Count[16]~54 ; +wire \debounce_turbo|r_Count[17]~55_combout ; +wire \debounce_turbo|r_Count[17]~56 ; +wire \debounce_turbo|r_Count[18]~57_combout ; +wire \debounce_turbo|r_Count[18]~58 ; +wire \debounce_turbo|r_Count[19]~59_combout ; +wire \debounce_turbo|always0~0_combout ; +wire \debounce_turbo|always0~1_combout ; +wire \debounce_turbo|r_Count[19]~60 ; +wire \debounce_turbo|r_Count[20]~61_combout ; +wire \debounce_turbo|always0~2_combout ; +wire \debounce_turbo|r_State~4_combout ; +wire \debounce_turbo|r_State~2_combout ; +wire \debounce_turbo|r_State~0_combout ; +wire \debounce_turbo|r_State~1_combout ; +wire \debounce_turbo|r_State~3_combout ; +wire \debounce_turbo|r_State~5_combout ; +wire \debounce_turbo|r_State~6_combout ; +wire \debounce_turbo|r_State~q ; +wire \turbo~0_combout ; +wire \turbo~q ; wire \ula_|clocks_|counter[0]~0_combout ; -wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -263,12 +334,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; @@ -279,16 +351,9 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Add0~9 ; -wire \ula_|video_|Add0~10_combout ; -wire \ula_|video_|vga_hc~0_combout ; -wire \ula_|video_|Add0~11 ; -wire \ula_|video_|Add0~12_combout ; -wire \ula_|video_|Add0~13 ; -wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Equal0~1_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; @@ -297,6 +362,30 @@ wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~9 ; +wire \ula_|video_|Add0~10_combout ; +wire \ula_|video_|vga_hc~0_combout ; +wire \ula_|video_|Add0~11 ; +wire \ula_|video_|Add0~12_combout ; +wire \ula_|video_|Add0~13 ; +wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Add1~11 ; +wire \ula_|video_|Add1~12_combout ; +wire \ula_|video_|vga_vc[6]~4_combout ; +wire \ula_|video_|Add1~13 ; +wire \ula_|video_|Add1~14_combout ; +wire \ula_|video_|vga_vc[7]~6_combout ; +wire \ula_|video_|Add1~15 ; +wire \ula_|video_|Add1~16_combout ; +wire \ula_|video_|vga_vc[8]~7_combout ; +wire \ula_|video_|Add1~17 ; +wire \ula_|video_|Add1~18_combout ; +wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; +wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; @@ -312,163 +401,1526 @@ wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; wire \ula_|video_|Add1~10_combout ; wire \ula_|video_|vga_vc[5]~8_combout ; -wire \ula_|video_|Add1~11 ; -wire \ula_|video_|Add1~12_combout ; -wire \ula_|video_|vga_vc[6]~4_combout ; -wire \ula_|video_|Add1~13 ; -wire \ula_|video_|Add1~14_combout ; -wire \ula_|video_|vga_vc[7]~6_combout ; -wire \ula_|video_|Add1~15 ; -wire \ula_|video_|Add1~16_combout ; -wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Add1~17 ; -wire \ula_|video_|Add1~18_combout ; -wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal3~0_combout ; -wire \ula_|video_|Equal2~0_combout ; -wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|ir_|opcode[4]~feeder_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|pla_decode_|Equal1~0_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal1~1_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; wire \z80_|pla_decode_|Equal21~0_combout ; wire \z80_|execute_|ctl_mRead~3_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_sw_1d~2_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_sw_1d~3_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~3_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~2_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_mWrite~19_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_bus_db_oe~8_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; wire \z80_|pla_decode_|Equal9~0_combout ; wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_ir_we~16_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|ctl_inc_cy~97_combout ; -wire \z80_|execute_|ctl_inc_cy~96_combout ; -wire \z80_|execute_|ctl_inc_cy~98_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~17_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|pla_decode_|Equal6~2_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~3_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~16_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_inc_cy~28_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~13_combout ; +wire \z80_|execute_|ctl_ir_we~19_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_inc_cy~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_out_hi~3_combout ; +wire \z80_|execute_|ctl_sw_2u~9_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|pla_decode_|Equal13~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_sw_2u~8_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|ctl_sw_4d~9_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|pla_decode_|Equal1~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_reg_out_hi~2_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~15_combout ; +wire \z80_|execute_|ctl_flags_pf_we~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~1_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_oe~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~50_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~49_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~51_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~48_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~17_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~22_combout ; +wire \z80_|pla_decode_|Equal5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~7_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|ctl_al_we~3_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~2_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~9_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_low[3]~2_combout ; +wire \z80_|alu_|db_low[3]~3_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~24_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~25_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~14_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~22_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~21_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~19_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~8_combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~17_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~18_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~23_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|reg_file_|db_hi_as[0]~3_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|pla_decode_|Equal1~3_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|pla_decode_|Equal2~4_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~29_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~26_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~32_combout ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~30_combout ; +wire \z80_|execute_|ctl_inc_cy~31_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|Q[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~33_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~13_combout ; +wire \z80_|reg_file_|db_lo_as[3]~14_combout ; +wire \z80_|reg_file_|db_lo_as[3]~15_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~58_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~59_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~61_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~62_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~63_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~65_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~70_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~72_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~73_combout ; +wire \z80_|reg_file_|db_lo_as[4]~16_combout ; +wire \z80_|reg_file_|db_lo_as[4]~17_combout ; +wire \z80_|reg_file_|db_lo_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~49_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; +wire \z80_|pla_decode_|Equal72~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|execute_|ctl_mWrite~20_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[0]~4_combout ; +wire \z80_|alu_control_|db[0]~23_combout ; +wire \z80_|alu_control_|db[0]~24_combout ; +wire \z80_|alu_control_|db[0]~25_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ; +wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~83_combout ; +wire \z80_|reg_file_|db_hi_as[7]~23_combout ; +wire \z80_|reg_file_|db_hi_as[7]~24_combout ; +wire \z80_|reg_file_|db_hi_as[7]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~84_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~19_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|db_hi_as[5]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~7_combout ; +wire \z80_|alu_|db_low[2]~8_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~13_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~8_combout ; +wire \z80_|reg_file_|db_lo_ds[5]~0_combout ; +wire \z80_|alu_control_|db[5]~9_combout ; +wire \z80_|alu_control_|db[5]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~48_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~53_combout ; +wire \z80_|reg_file_|db_lo_as[5]~10_combout ; +wire \z80_|reg_file_|db_lo_as[5]~11_combout ; +wire \z80_|reg_file_|db_lo_as[5]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~7_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|alu_|db_low[3]~0_combout ; +wire \z80_|alu_|db_low[3]~1_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_control_|db[2]~26_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~5_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~q ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; +wire \z80_|alu_control_|flags_cond_true~0_combout ; +wire \z80_|alu_control_|flags_cond_true~q ; +wire \z80_|execute_|ctl_reg_sel_wz~28_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~23_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~21_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~13_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|alu_control_|db[7]~14_combout ; +wire \z80_|alu_control_|db[7]~15_combout ; +wire \z80_|bus_control_|db[7]~4_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|nextM~16_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|ctl_ir_we~20_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~38_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; @@ -478,1535 +1930,104 @@ wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|execute_|ctl_mWrite~18_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_flags_alu~21_combout ; -wire \z80_|execute_|ctl_flags_alu~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_alu~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ixy_d~15_combout ; wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; wire \z80_|memory_ifc_|mwr_wr~q ; wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|execute_|ctl_mRead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pla_decode_|Equal40~2_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|pc_inc_hold~14_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_inc_cy~99_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|pla_decode_|Equal76~2_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~11_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|pla_decode_|Equal10~1_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|reg_control_|reg_sel_de2~2_combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_core_hf~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~23_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; -wire \z80_|reg_control_|reg_sel_de2~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; -wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|sw1_|db_down[3]~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~17_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~15_combout ; -wire \z80_|execute_|pc_inc_hold~16_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|execute_|ctl_inc_cy~95_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~100_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~10_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_alu_op_low~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[7]~16_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; -wire \z80_|alu_control_|db[6]~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_control_|db[7]~19_combout ; -wire \z80_|alu_control_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; -wire \z80_|reg_file_|db_hi_as[2]~10_combout ; -wire \z80_|reg_file_|db_hi_as[2]~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; -wire \z80_|reg_file_|db_hi_as[4]~13_combout ; -wire \z80_|reg_file_|db_hi_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[1]~18_combout ; -wire \z80_|alu_|db_low[1]~19_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|db_low[1]~20_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~8_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; -wire \z80_|reg_file_|db_hi_as[6]~19_combout ; -wire \z80_|reg_file_|db_hi_as[6]~20_combout ; -wire \z80_|reg_file_|db_hi_as[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~14_combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; -wire \z80_|reg_file_|db_hi_as[5]~22_combout ; -wire \z80_|reg_file_|db_hi_as[5]~23_combout ; -wire \z80_|reg_file_|db_hi_as[5]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|alu_op1[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|db_low[0]~24_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db_low[0]~25_combout ; -wire \z80_|alu_|db_low[0]~27_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~13_combout ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|alu_|db_high[0]~20_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_low[2]~11_combout ; -wire \z80_|alu_|db_low[2]~12_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~13_combout ; -wire \z80_|alu_|db_low[2]~14_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~24_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_control_|db[2]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~11_combout ; -wire \z80_|alu_control_|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_control_|db[3]~36_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|db_low[3]~5_combout ; -wire \z80_|alu_|db_low[3]~6_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~26_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; -wire \z80_|alu_|alu_op2[3]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_control_|db[4]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; -wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; -wire \z80_|alu_control_|flags_cond_true~0_combout ; -wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~7_combout ; -wire \z80_|reg_file_|db_hi_as[3]~8_combout ; -wire \z80_|reg_file_|db_hi_as[3]~9_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \D[0]~49_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \Equal5~0_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~20_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~43_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; +wire \Equal3~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; +wire \z80_|address_pins_|abus[6]~25_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; +wire \z80_|address_pins_|abus[7]~26_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; +wire \Equal3~1_combout ; +wire \Equal3~2_combout ; +wire \D[5]~26_combout ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|abus[15]~23_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~22_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~44_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~45_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \D[2]~42_combout ; -wire \D[2]~46_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|control_pins_|pin_nIORQ~1_combout ; -wire \Equal2~0_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; wire \ExtRamWE~0_combout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; -wire \z80_|address_pins_|abus[1]~25_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; -wire \z80_|address_pins_|abus[2]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; -wire \z80_|address_pins_|abus[3]~27_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; -wire \z80_|address_pins_|abus[4]~28_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; -wire \z80_|address_pins_|abus[5]~29_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; -wire \z80_|address_pins_|abus[6]~30_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; -wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \D[2]~50_combout ; -wire \D[2]~51_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \CLOCK_50~inputclkctrl_outclk ; +wire \z80_|address_pins_|abus[0]~24_combout ; +wire \z80_|address_pins_|abus[1]~27_combout ; +wire \z80_|address_pins_|abus[2]~28_combout ; +wire \z80_|address_pins_|abus[3]~29_combout ; +wire \z80_|address_pins_|abus[4]~30_combout ; +wire \z80_|address_pins_|abus[5]~31_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~16_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; -wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -2018,521 +2039,710 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[8]~1_combout ; +wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Selector0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \Selector0~1_combout ; +wire \D[7]~36_combout ; +wire \D[7]~37_combout ; +wire \D[7]~48_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[7]~6_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|setM1~59_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal5~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~47_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~48_combout ; -wire \D[2]~49_combout ; -wire \D[2]~119_combout ; -wire \D[2]~52_combout ; -wire \D[2]~53_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; +wire \Selector10~0_combout ; +wire \Selector10~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|keys[3][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~5_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~46_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~4_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~7_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~6_combout ; +wire \Selector14~17_combout ; +wire \Selector14~18_combout ; +wire \kempston[1]~input_o ; +wire \Selector10~2_combout ; +wire \Selector10~3_combout ; +wire \D[2]~13_combout ; wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|ir_|opcode[2]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|sw1_|db_down[6]~1_combout ; -wire \z80_|alu_control_|db[6]~23_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|bus_control_|db[2]~14_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_ir_we~17_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal2~3_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_66_oe~4_combout ; +wire \z80_|alu_control_|db[6]~16_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~2_combout ; +wire \z80_|alu_control_|db[6]~17_combout ; +wire \z80_|alu_control_|db[6]~18_combout ; +wire \z80_|bus_control_|db[6]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \raw_loader_in~input_o ; +wire \D[6]~28_combout ; +wire \D[6]~43_combout ; +wire \D[6]~44_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~103_combout ; -wire \D[6]~104_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~42_combout ; +wire \D[6]~45_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~100_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~101_combout ; -wire \D[6]~102_combout ; -wire \D[6]~127_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~99_combout ; -wire \D[6]~114_combout ; -wire \D[6]~115_combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Mux1~0_combout ; +wire \D[6]~41_combout ; +wire \D[6]~46_combout ; +wire \D[6]~47_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~18_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~16_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~9_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~10_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~130_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~11_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~72_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~69_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~8_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~9_combout ; +wire \kempston[3]~input_o ; +wire \Selector14~8_combout ; +wire \Selector14~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector14~19_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \Selector14~10_combout ; +wire \Selector14~11_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector14~20_combout ; +wire \Selector14~9_combout ; +wire \Selector14~12_combout ; +wire \Selector14~14_combout ; +wire \D[0]~14_combout ; +wire \z80_|bus_control_|db[0]~11_combout ; +wire \z80_|bus_control_|db[0]~12_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~29_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~16_combout ; +wire \debounce_autofire|r_Count[0]~21_combout ; +wire \debounce_autofire|r_Count[0]~22 ; +wire \debounce_autofire|r_Count[1]~23_combout ; +wire \debounce_autofire|r_Count[1]~24 ; +wire \debounce_autofire|r_Count[2]~25_combout ; +wire \debounce_autofire|r_Count[2]~26 ; +wire \debounce_autofire|r_Count[3]~27_combout ; +wire \debounce_autofire|r_Count[3]~28 ; +wire \debounce_autofire|r_Count[4]~29_combout ; +wire \debounce_autofire|r_Count[4]~30 ; +wire \debounce_autofire|r_Count[5]~31_combout ; +wire \debounce_autofire|r_Count[5]~32 ; +wire \debounce_autofire|r_Count[6]~33_combout ; +wire \debounce_autofire|r_Count[6]~34 ; +wire \debounce_autofire|r_Count[7]~35_combout ; +wire \debounce_autofire|r_Count[7]~36 ; +wire \debounce_autofire|r_Count[8]~37_combout ; +wire \debounce_autofire|r_Count[8]~38 ; +wire \debounce_autofire|r_Count[9]~39_combout ; +wire \debounce_autofire|r_Count[9]~40 ; +wire \debounce_autofire|r_Count[10]~41_combout ; +wire \debounce_autofire|r_Count[10]~42 ; +wire \debounce_autofire|r_Count[11]~43_combout ; +wire \debounce_autofire|r_Count[11]~44 ; +wire \debounce_autofire|r_Count[12]~45_combout ; +wire \debounce_autofire|r_Count[12]~46 ; +wire \debounce_autofire|r_Count[13]~47_combout ; +wire \debounce_autofire|r_Count[13]~48 ; +wire \debounce_autofire|r_Count[14]~49_combout ; +wire \debounce_autofire|r_Count[14]~50 ; +wire \debounce_autofire|r_Count[15]~51_combout ; +wire \debounce_autofire|r_Count[15]~52 ; +wire \debounce_autofire|r_Count[16]~53_combout ; +wire \debounce_autofire|r_Count[16]~54 ; +wire \debounce_autofire|r_Count[17]~55_combout ; +wire \debounce_autofire|r_Count[17]~56 ; +wire \debounce_autofire|r_Count[18]~57_combout ; +wire \debounce_autofire|r_Count[18]~58 ; +wire \debounce_autofire|r_Count[19]~59_combout ; +wire \debounce_autofire|r_Count[19]~60 ; +wire \debounce_autofire|r_Count[20]~61_combout ; +wire \kempston_autofire_button~input_o ; +wire \debounce_autofire|r_State~7_combout ; +wire \debounce_autofire|LessThan0~0_combout ; +wire \debounce_autofire|LessThan0~1_combout ; +wire \debounce_autofire|always0~0_combout ; +wire \debounce_autofire|always0~1_combout ; +wire \debounce_autofire|always0~2_combout ; +wire \debounce_autofire|r_State~4_combout ; +wire \debounce_autofire|r_State~5_combout ; +wire \debounce_autofire|r_State~2_combout ; +wire \debounce_autofire|r_State~0_combout ; +wire \debounce_autofire|r_State~1_combout ; +wire \debounce_autofire|r_State~3_combout ; +wire \debounce_autofire|r_State~6_combout ; +wire \debounce_autofire|r_State~q ; +wire \kempston_autofire_enabled~0_combout ; +wire \kempston_autofire_enabled~q ; +wire \kempston_auto_fire_counter[0]~51_combout ; +wire \kempston_auto_fire_counter[1]~17_combout ; +wire \kempston_auto_fire_counter[1]~18 ; +wire \kempston_auto_fire_counter[2]~19_combout ; +wire \kempston_auto_fire_counter[2]~20 ; +wire \kempston_auto_fire_counter[3]~21_combout ; +wire \kempston_auto_fire_counter[3]~22 ; +wire \kempston_auto_fire_counter[4]~23_combout ; +wire \kempston_auto_fire_counter[4]~24 ; +wire \kempston_auto_fire_counter[5]~25_combout ; +wire \kempston_auto_fire_counter[5]~26 ; +wire \kempston_auto_fire_counter[6]~27_combout ; +wire \kempston_auto_fire_counter[6]~28 ; +wire \kempston_auto_fire_counter[7]~29_combout ; +wire \kempston_auto_fire_counter[7]~30 ; +wire \kempston_auto_fire_counter[8]~31_combout ; +wire \kempston_auto_fire_counter[8]~32 ; +wire \kempston_auto_fire_counter[9]~33_combout ; +wire \kempston_auto_fire_counter[9]~34 ; +wire \kempston_auto_fire_counter[10]~35_combout ; +wire \kempston_auto_fire_counter[10]~36 ; +wire \kempston_auto_fire_counter[11]~37_combout ; +wire \kempston_auto_fire_counter[11]~38 ; +wire \kempston_auto_fire_counter[12]~39_combout ; +wire \kempston_auto_fire_counter[12]~40 ; +wire \kempston_auto_fire_counter[13]~41_combout ; +wire \kempston_auto_fire_counter[13]~42 ; +wire \kempston_auto_fire_counter[14]~43_combout ; +wire \kempston_auto_fire_counter[14]~44 ; +wire \kempston_auto_fire_counter[15]~45_combout ; +wire \Equal2~3_combout ; +wire \Equal2~2_combout ; +wire \Equal2~0_combout ; +wire \Equal2~1_combout ; +wire \Equal2~4_combout ; +wire \kempston_auto_fire_counter[15]~46 ; +wire \kempston_auto_fire_counter[16]~47_combout ; +wire \kempston_auto_fire_counter[16]~48 ; +wire \kempston_auto_fire_counter[17]~49_combout ; +wire \kempston_auto_fire~0_combout ; +wire \kempston_auto_fire~q ; +wire \Selector6~2_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~17_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~133_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \Selector6~3_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \Selector6~4_combout ; +wire \Selector6~5_combout ; +wire \kempston[4]~input_o ; +wire \Selector6~6_combout ; +wire \Selector6~7_combout ; +wire \D[4]~39_combout ; +wire \z80_|bus_control_|db[4]~17_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~3_combout ; +wire \z80_|alu_control_|db[1]~20_combout ; +wire \z80_|alu_control_|db[1]~21_combout ; +wire \z80_|alu_control_|db[1]~22_combout ; +wire \z80_|bus_control_|db[1]~9_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~2_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~1_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~38_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~3_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~0_combout ; +wire \kempston[2]~input_o ; +wire \Selector12~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \Selector12~7_combout ; +wire \Selector12~8_combout ; +wire \Selector12~9_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector12~15_combout ; +wire \Selector12~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~14_combout ; +wire \Selector12~6_combout ; +wire \Selector12~11_combout ; +wire \D[1]~12_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|test1~4_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~36_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; -wire \ula_|zx_keyboard_|WideOr16~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~74_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \D[3]~73_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~2_combout ; +wire \z80_|bus_control_|db[0]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector8~5_combout ; +wire \Selector8~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \Selector8~7_combout ; +wire \Selector8~8_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|key_row[3]~15_combout ; wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; wire \ula_|zx_keyboard_|keys[0][3]~q ; wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \D[3]~72_combout ; -wire \D[3]~76_combout ; -wire \D[3]~122_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~79_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~77_combout ; -wire \D[3]~80_combout ; -wire \D[3]~81_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~124_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~123_combout ; -wire \D[3]~78_combout ; -wire \D[3]~82_combout ; -wire \D[3]~108_combout ; -wire \D[3]~109_combout ; +wire \ula_|zx_keyboard_|key_row[3]~12_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~13_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~14_combout ; +wire \kempston[0]~input_o ; +wire \Selector8~4_combout ; +wire \Selector8~9_combout ; +wire \D[3]~38_combout ; +wire \z80_|bus_control_|db[3]~19_combout ; wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; -wire \D[5]~97_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~116_combout ; -wire \D[7]~117_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|ir_|opcode[3]~feeder_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~60_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~17_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|interrupts_|im1~feeder_combout ; wire \z80_|interrupts_|im1~q ; wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~57_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \D[0]~56_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~69_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~71_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~54_combout ; -wire \D[0]~55_combout ; -wire \D[0]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \D[0]~62_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~63_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~59_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~60_combout ; -wire \D[0]~61_combout ; -wire \D[0]~120_combout ; -wire \D[0]~64_combout ; -wire \D[0]~65_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|sw1_|db_down[1]~2_combout ; -wire \z80_|alu_control_|db[1]~27_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|WideOr16~0_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~34_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \D[1]~38_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \D[1]~39_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \D[1]~35_combout ; -wire \D[1]~36_combout ; -wire \D[1]~37_combout ; -wire \D[1]~118_combout ; -wire \D[1]~40_combout ; -wire \D[1]~41_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~88_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~87_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~85_combout ; -wire \D[4]~86_combout ; -wire \D[4]~89_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \D[4]~93_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \D[4]~94_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \D[4]~90_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \D[4]~91_combout ; -wire \D[4]~92_combout ; -wire \D[4]~125_combout ; -wire \D[4]~110_combout ; -wire \D[4]~111_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \z80_|alu_control_|db[5]~16_combout ; -wire \z80_|alu_control_|db[5]~17_combout ; +wire \z80_|bus_control_|db[0]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; -wire \D[5]~112_combout ; -wire \D[5]~113_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[5]~25_combout ; +wire \D[5]~27_combout ; +wire \D[5]~40_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|ena_M~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; +wire \z80_|bus_control_|db[5]~16_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~51_combout ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~47_combout ; wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~55_combout ; wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~66_combout ; -wire \D[0]~67_combout ; -wire \D[0]~121_combout ; -wire \D[1]~68_combout ; -wire \D[1]~69_combout ; -wire \D[2]~70_combout ; -wire \D[2]~71_combout ; -wire \D[3]~83_combout ; -wire \D[3]~84_combout ; -wire \D[4]~95_combout ; -wire \D[4]~96_combout ; -wire \D[5]~126_combout ; -wire \D[5]~98_combout ; -wire \D[6]~105_combout ; -wire \D[6]~106_combout ; -wire \D[7]~128_combout ; -wire \D[7]~107_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ; +wire \Selector14~15_combout ; +wire \Selector14~16_combout ; +wire \D[0]~15_combout ; +wire \D[0]~16_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ; +wire \Selector12~12_combout ; +wire \Selector12~13_combout ; +wire \D[1]~17_combout ; +wire \D[1]~18_combout ; +wire \D[2]~19_combout ; +wire \D[2]~20_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \Selector8~2_combout ; +wire \Selector8~3_combout ; +wire \D[3]~21_combout ; +wire \D[3]~22_combout ; +wire \D[4]~23_combout ; +wire \D[4]~24_combout ; +wire \D[6]~32_combout ; +wire \D[6]~33_combout ; +wire \D[6]~29_combout ; +wire \D[6]~30_combout ; +wire \D[6]~31_combout ; +wire \D[6]~50_combout ; +wire \D[6]~34_combout ; +wire \D[6]~35_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2541,54 +2751,55 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|Mux42~0_combout ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit~4_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; +wire \I2C_SDAT~input_o ; +wire \ula_|i2c_loader_|nbyte[0]~1_combout ; +wire \ula_|i2c_loader_|nbyte[0]~2_combout ; +wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state~24_combout ; wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state.Data~0_combout ; wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~6_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; -wire \I2C_SDAT~input_o ; -wire \ula_|i2c_loader_|nbyte[0]~1_combout ; -wire \ula_|i2c_loader_|nbyte[0]~2_combout ; -wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; -wire \ula_|i2c_loader_|nbyte[1]~5_combout ; +wire \ula_|i2c_loader_|nbyte[0]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; wire \ula_|i2c_loader_|thisbyte[1]~10_combout ; @@ -2596,9 +2807,9 @@ wire \ula_|i2c_loader_|thisbyte[1]~11 ; wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; -wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; +wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|state.Pause~4_combout ; @@ -2611,31 +2822,30 @@ wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~27_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~28_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg~6_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~27_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; -wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; +wire \ula_|i2c_loader_|shiftreg~25_combout ; +wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; +wire \ula_|i2c_loader_|shiftreg[7]~7_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; wire \ula_|i2c_loader_|sda_out~2_combout ; @@ -2644,16 +2854,38 @@ wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \sdram_|Mux38~0_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux38~3_combout ; +wire \sdram_|Mux38~2_combout ; wire \sdram_|r.rd_pending~q ; +wire \sdram_|n~3_combout ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux13~8_combout ; wire \sdram_|r.rf_counter[0]~12_combout ; -wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[8]~32_combout ; wire \sdram_|r.rf_counter[0]~13 ; wire \sdram_|r.rf_counter[1]~14_combout ; wire \sdram_|r.rf_counter[1]~15 ; wire \sdram_|r.rf_counter[2]~16_combout ; wire \sdram_|r.rf_counter[2]~17 ; wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[3]~19 ; wire \sdram_|r.rf_counter[4]~20_combout ; wire \sdram_|r.rf_counter[4]~21 ; @@ -2662,105 +2894,84 @@ wire \sdram_|r.rf_counter[5]~23 ; wire \sdram_|r.rf_counter[6]~24_combout ; wire \sdram_|r.rf_counter[6]~25 ; wire \sdram_|r.rf_counter[7]~26_combout ; -wire \sdram_|Equal0~1_combout ; wire \sdram_|r.rf_counter[7]~27 ; wire \sdram_|r.rf_counter[8]~28_combout ; -wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[8]~29 ; wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~1_combout ; wire \sdram_|Equal0~2_combout ; -wire \sdram_|Mux13~8_combout ; wire \sdram_|Mux37~0_combout ; wire \sdram_|r.rf_pending~q ; -wire \sdram_|Mux4~0_combout ; wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~4_combout ; wire \sdram_|Mux4~2_combout ; -wire \sdram_|Mux4~3_combout ; -wire \sdram_|r.act_row[1]~0_combout ; -wire \sdram_|process_0~2_combout ; -wire \sdram_|r.act_row[1]~1_combout ; -wire \sdram_|r.act_row[2]~feeder_combout ; -wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux4~5_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|r.act_row[2]~0_combout ; +wire \sdram_|r.act_row[2]~1_combout ; wire \sdram_|Equal7~0_combout ; wire \sdram_|Equal7~2_combout ; -wire \sdram_|Mux39~0_combout ; -wire \sdram_|Mux39~1_combout ; -wire \sdram_|Mux39~2_combout ; -wire \sdram_|r.wr_pending~q ; -wire \sdram_|Mux9~8_combout ; -wire \sdram_|Mux9~9_combout ; -wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~2_combout ; wire \sdram_|Mux6~5_combout ; -wire \sdram_|process_0~3_combout ; +wire \sdram_|process_0~2_combout ; wire \sdram_|Mux6~0_combout ; wire \sdram_|Mux6~1_combout ; wire \sdram_|Mux6~6_combout ; -wire \sdram_|r.address[3]~6_combout ; -wire \sdram_|Mux7~2_combout ; -wire \sdram_|n~3_combout ; -wire \sdram_|Mux7~3_combout ; -wire \sdram_|Mux7~4_combout ; -wire \sdram_|Mux7~5_combout ; -wire \sdram_|Mux23~0_combout ; -wire \sdram_|Mux13~7_combout ; -wire \sdram_|Mux10~10_combout ; -wire \sdram_|Mux7~1_combout ; -wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~2_combout ; wire \sdram_|Mux5~10_combout ; wire \sdram_|Mux5~3_combout ; wire \sdram_|Mux5~4_combout ; -wire \sdram_|Mux5~7_combout ; -wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~5_combout ; wire \sdram_|Mux5~6_combout ; wire \sdram_|Mux5~9_combout ; wire \sdram_|n~2_combout ; -wire \sdram_|Mux8~3_combout ; -wire \sdram_|Mux8~4_combout ; -wire \sdram_|Mux9~10_combout ; -wire \sdram_|r.init_counter[0]~0_combout ; -wire \sdram_|Add1~1_cout ; -wire \sdram_|Add1~2_combout ; -wire \sdram_|Add1~3 ; -wire \sdram_|Add1~4_combout ; -wire \sdram_|Add1~5 ; -wire \sdram_|Add1~6_combout ; -wire \sdram_|r.init_counter[3]~1_combout ; -wire \sdram_|Add1~7 ; -wire \sdram_|Add1~8_combout ; -wire \sdram_|Add1~9 ; -wire \sdram_|Add1~10_combout ; -wire \sdram_|Add1~11 ; -wire \sdram_|Add1~12_combout ; -wire \sdram_|Add1~13 ; -wire \sdram_|Add1~14_combout ; -wire \sdram_|Add1~15 ; -wire \sdram_|Add1~16_combout ; -wire \sdram_|Add1~17 ; -wire \sdram_|Add1~18_combout ; -wire \sdram_|Add1~19 ; -wire \sdram_|Add1~20_combout ; -wire \sdram_|Equal2~0_combout ; -wire \sdram_|Equal2~1_combout ; -wire \sdram_|Add1~21 ; -wire \sdram_|Add1~22_combout ; -wire \sdram_|Add1~23 ; -wire \sdram_|Add1~24_combout ; -wire \sdram_|Add1~25 ; -wire \sdram_|Add1~26_combout ; -wire \sdram_|Add1~27 ; -wire \sdram_|Add1~28_combout ; -wire \sdram_|process_0~5_combout ; -wire \sdram_|Equal2~2_combout ; -wire \sdram_|Mux9~11_combout ; -wire \sdram_|Mux9~12_combout ; -wire \sdram_|Mux9~13_combout ; -wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~6_combout ; +wire \sdram_|Mux8~7_combout ; wire \sdram_|Mux8~1_combout ; wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|r.init_counter[0]~44_combout ; +wire \sdram_|r.init_counter[1]~15_cout ; +wire \sdram_|r.init_counter[1]~16_combout ; +wire \sdram_|r.init_counter[1]~17 ; +wire \sdram_|r.init_counter[2]~18_combout ; +wire \sdram_|r.init_counter[2]~19 ; +wire \sdram_|r.init_counter[3]~20_combout ; +wire \sdram_|r.init_counter[3]~21 ; +wire \sdram_|r.init_counter[4]~22_combout ; +wire \sdram_|r.init_counter[4]~23 ; +wire \sdram_|r.init_counter[5]~24_combout ; +wire \sdram_|r.init_counter[5]~25 ; +wire \sdram_|r.init_counter[6]~26_combout ; +wire \sdram_|r.init_counter[6]~27 ; +wire \sdram_|r.init_counter[7]~28_combout ; +wire \sdram_|r.init_counter[7]~29 ; +wire \sdram_|r.init_counter[8]~30_combout ; +wire \sdram_|r.init_counter[8]~31 ; +wire \sdram_|r.init_counter[9]~32_combout ; +wire \sdram_|r.init_counter[9]~33 ; +wire \sdram_|r.init_counter[10]~34_combout ; +wire \sdram_|r.init_counter[10]~35 ; +wire \sdram_|r.init_counter[11]~36_combout ; +wire \sdram_|r.init_counter[11]~37 ; +wire \sdram_|r.init_counter[12]~38_combout ; +wire \sdram_|r.init_counter[12]~39 ; +wire \sdram_|r.init_counter[13]~40_combout ; +wire \sdram_|r.init_counter[13]~41 ; +wire \sdram_|r.init_counter[14]~42_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux8~5_combout ; wire \sdram_|Mux72~0_combout ; wire \sdram_|Mux72~1_combout ; wire \sdram_|Mux84~0_combout ; @@ -2774,13 +2985,14 @@ wire \sdram_|Mux1~1_combout ; wire \sdram_|Mux0~0_combout ; wire \sdram_|Mux0~1_combout ; wire \sdram_|Mux73~0_combout ; -wire \sdram_|Mux73~1_combout ; wire \sdram_|Mux74~0_combout ; wire \sdram_|Mux74~1_combout ; wire \sdram_|Mux75~0_combout ; +wire \LED~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|Add0~1_cout ; wire \ula_|i2s_intf_|Add0~2_combout ; wire \ula_|i2s_intf_|lrdivider~2_combout ; @@ -2811,25 +3023,10 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2843,19 +3040,33 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~9_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~10_combout ; +wire \ula_|i2s_intf_|bitcount[2]~11 ; +wire \ula_|i2s_intf_|bitcount[3]~12_combout ; +wire \ula_|i2s_intf_|bitcount[3]~13 ; +wire \ula_|i2s_intf_|bitcount[4]~14_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|LessThan0~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~18_combout ; wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg[7]~1_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; wire \ula_|i2s_intf_|shiftreg~14_combout ; @@ -2866,25 +3077,19 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; +wire \ula_|i2s_intf_|shiftreg~2_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; wire \ula_|video_|Decoder0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2893,58 +3098,51 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; -wire \ula_|video_|bits[5]~feeder_combout ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[2]~feeder_combout ; -wire \ula_|video_|bits[2]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[2]~0_combout ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; +wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan6~0_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; -wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|border[2]~feeder_combout ; -wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|video_|attr[2]~feeder_combout ; +wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; -wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|VGA_HS~_Duplicate_1_q ; +wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|Selector0~0_combout ; wire \ula_|video_|VGA_HS~q ; wire \ula_|video_|VGA_VS~_Duplicate_1_q ; @@ -2958,290 +3156,305 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire \sdram_|Mux26~4_combout ; -wire \sdram_|r.bank[0]~7_combout ; -wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~6_combout ; wire \sdram_|r.bank[0]~4_combout ; wire \sdram_|r.bank[0]~5_combout ; -wire \sdram_|r.bank[0]~6_combout ; -wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|r.bank[0]~13_combout ; +wire \sdram_|r.bank[0]~11_combout ; wire \sdram_|Mux25~4_combout ; -wire \sdram_|Mux24~5_combout ; -wire \sdram_|Mux71~0_combout ; -wire \sdram_|process_0~7_combout ; -wire \sdram_|process_0~4_combout ; -wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~6_combout ; wire \sdram_|Mux71~2_combout ; wire \sdram_|Mux71~3_combout ; +wire \sdram_|process_0~8_combout ; +wire \sdram_|process_0~3_combout ; wire \sdram_|Mux71~4_combout ; -wire \sdram_|r.bank[0]~10_combout ; -wire \sdram_|Mux9~3_combout ; -wire \sdram_|n~5_combout ; -wire \sdram_|Mux9~4_combout ; -wire \sdram_|Mux9~2_combout ; -wire \sdram_|Equal2~3_combout ; -wire \sdram_|Mux10~2_combout ; -wire \sdram_|Mux10~3_combout ; -wire \sdram_|process_0~6_combout ; -wire \sdram_|Mux10~4_combout ; -wire \sdram_|Mux9~5_combout ; -wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux24~8_combout ; +wire \sdram_|Mux71~5_combout ; +wire \sdram_|n~6_combout ; +wire \sdram_|Mux9~0_combout ; wire \sdram_|Mux9~6_combout ; wire \sdram_|Mux9~7_combout ; -wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Equal5~1_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux9~1_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Mux9~3_combout ; wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|Mux10~4_combout ; wire \sdram_|Mux10~5_combout ; wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~12_combout ; wire \sdram_|Mux10~8_combout ; -wire \sdram_|Mux10~9_combout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~8_combout ; wire \sdram_|Mux11~2_combout ; wire \sdram_|Mux11~3_combout ; -wire \sdram_|Mux11~4_combout ; wire \sdram_|Mux11~5_combout ; wire \sdram_|Mux11~6_combout ; wire \sdram_|Mux11~7_combout ; -wire \sdram_|Mux11~9_combout ; -wire \sdram_|Mux11~8_combout ; -wire \sdram_|Mux24~2_combout ; -wire \sdram_|r.address[0]~7_combout ; -wire \sdram_|r.address[0]~0_combout ; -wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux24~6_combout ; wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~9_combout ; wire \sdram_|Mux13~5_combout ; wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~2_combout ; wire \sdram_|Mux24~3_combout ; wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~0_combout ; wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~8_combout ; +wire \sdram_|r.address[1]~9_combout ; +wire \sdram_|r.address[1]~7_combout ; +wire \sdram_|r.address[1]~10_combout ; +wire \sdram_|r.address[1]~1_combout ; wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; -wire \sdram_|Mux23~4_combout ; -wire \sdram_|Equal5~0_combout ; -wire \sdram_|Mux23~5_combout ; -wire \sdram_|Mux23~6_combout ; wire \sdram_|Mux19~0_combout ; wire \sdram_|r.address[1]~_Duplicate_1_q ; -wire \sdram_|Mux23~2_combout ; wire \sdram_|Mux23~3_combout ; -wire \sdram_|Mux23~1_combout ; -wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~5_combout ; wire \sdram_|r.address[1]~SLOAD_MUX_combout ; -wire \sdram_|r.address[3]~8_combout ; -wire \sdram_|r.address[3]~9_combout ; -wire \sdram_|Mux21~0_combout ; -wire \sdram_|Mux22~0_combout ; -wire \sdram_|r.address[3]~10_combout ; wire \sdram_|r.address[3]~11_combout ; wire \sdram_|r.address[3]~12_combout ; -wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; wire \sdram_|r.address[3]~14_combout ; wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~13_combout ; wire \sdram_|r.address[3]~16_combout ; wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|r.address[3]~18_combout ; +wire \sdram_|r.address[3]~19_combout ; +wire \sdram_|r.address[3]~20_combout ; wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux24~7_combout ; wire \sdram_|Mux20~4_combout ; -wire \sdram_|Mux20~7_combout ; -wire \sdram_|Mux23~7_combout ; -wire \sdram_|Mux20~8_combout ; -wire \sdram_|Mux20~10_combout ; -wire \sdram_|Mux20~9_combout ; -wire \sdram_|Mux20~11_combout ; -wire \sdram_|r.address[4]~_Duplicate_1_q ; -wire \sdram_|Mux20~12_combout ; -wire \sdram_|Mux20~5_combout ; -wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~2_combout ; +wire \sdram_|Mux20~3_combout ; wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~_Duplicate_1feeder_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~9_combout ; wire \sdram_|r.address[4]~SLOAD_MUX_combout ; -wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~4_combout ; -wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~7_combout ; wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~2_combout ; wire \sdram_|Mux19~3_combout ; wire \sdram_|r.address[5]~3_combout ; wire \sdram_|r.address[5]~SLOAD_MUX_combout ; wire \sdram_|Mux18~0_combout ; -wire \sdram_|Mux17~0_combout ; -wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux17~2_combout ; +wire \sdram_|Mux16~2_combout ; wire \sdram_|Mux15~2_combout ; -wire \sdram_|Mux14~0_combout ; -wire \sdram_|Mux14~1_combout ; -wire \sdram_|r.address[10]~4_combout ; -wire \sdram_|r.address[10]~_Duplicate_1_q ; -wire \sdram_|n~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1feeder_combout ; +wire \sdram_|n~5_combout ; wire \sdram_|Mux14~2_combout ; wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|r.address[10]~4_combout ; wire \sdram_|r.address[10]~SLOAD_MUX_combout ; -wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~21_combout ; +wire \sdram_|r.address[11]~22_combout ; wire \sdram_|r.address[11]~5_combout ; -wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; wire \sdram_|r.address[11]~_Duplicate_2_q ; wire \sdram_|Mux13~10_combout ; wire \sdram_|Mux13~6_combout ; wire \sdram_|r.address[11]~SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1_q ; -wire [9:0] \sdram_|r.rf_counter ; -wire [12:0] \sdram_|r.address ; -wire [15:0] \ula_|pcm_outl ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [8:0] \sdram_|r.state ; +wire [1:0] \sdram_|r.bank ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; +wire [1:0] \z80_|sw1_|SYNTHESIZED_WIRE_1 ; +wire [7:0] \z80_|data_pins_|dout ; +wire [3:0] \z80_|alu_|op1_low ; +wire [20:0] \debounce_autofire|r_Count ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [9:0] \sdram_|r.rf_counter ; +wire [1:0] \sdram_|r.dq_masks ; +wire [12:0] \sdram_|r.address ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [15:0] \ula_|pcm_outl ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; +wire [17:0] kempston_auto_fire_counter; +wire [20:0] \debounce_turbo|r_Count ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; -wire [3:0] \z80_|alu_|op2_low ; +wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|dout ; -wire [8:0] \sdram_|r.state ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [2:0] \z80_|sw1_|SYNTHESIZED_WIRE_2 ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [4:0] \ula_|zx_keyboard_|key_row ; +wire [3:0] \z80_|alu_|result_lo ; +wire [3:0] \z80_|alu_|op2_high ; +wire [3:0] \z80_|alu_|op1_high ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; wire [14:0] \sdram_|r.init_counter ; -wire [1:0] \sdram_|r.bank ; wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [3:0] \z80_|alu_|result_lo ; -wire [3:0] \z80_|alu_|op2_high ; -wire [3:0] \z80_|alu_|op1_high ; -wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; -wire [7:0] \z80_|ir_|opcode ; -wire [1:0] \sdram_|r.dq_masks ; -wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [3:0] \z80_|alu_|op1_low ; wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|ir_|opcode ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -3255,96 +3468,104 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; @@ -3355,14 +3576,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3375,11 +3588,19 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3391,14 +3612,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; - // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3609,8 +3822,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~67_combout ), - .oe(\D[0]~121_combout ), + .i(\D[0]~16_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3622,8 +3835,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~69_combout ), - .oe(\D[0]~121_combout ), + .i(\D[1]~18_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3635,8 +3848,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~71_combout ), - .oe(\D[0]~121_combout ), + .i(\D[2]~20_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3648,8 +3861,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~84_combout ), - .oe(\D[0]~121_combout ), + .i(\D[3]~22_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3661,8 +3874,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~96_combout ), - .oe(\D[0]~121_combout ), + .i(\D[4]~24_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3674,8 +3887,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~98_combout ), - .oe(\D[0]~121_combout ), + .i(\D[5]~27_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3687,8 +3900,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~106_combout ), - .oe(\D[0]~121_combout ), + .i(\D[6]~35_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3700,8 +3913,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~107_combout ), - .oe(\D[0]~121_combout ), + .i(\D[7]~37_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3739,7 +3952,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3778,7 +3991,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3791,7 +4004,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\SW[2]~input_o ), + .i(\turbo~q ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3804,7 +4017,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\raw_loader_in~input_o ), + .i(!\kempston[0]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3817,7 +4030,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(gnd), + .i(!\kempston[1]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3830,7 +4043,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(gnd), + .i(!\kempston[2]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3843,7 +4056,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(gnd), + .i(!\kempston[3]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3856,7 +4069,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\LED~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4166,32 +4379,6 @@ defparam \GPIO_1[31]~output .bus_hold = "false"; defparam \GPIO_1[31]~output .open_drain_output = "false"; // synopsys translate_on -// Location: IOOBUF_X53_Y16_N9 -cycloneive_io_obuf \GPIO_1[32]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[32]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[32]~output .bus_hold = "false"; -defparam \GPIO_1[32]~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOOBUF_X53_Y15_N9 -cycloneive_io_obuf \GPIO_1[33]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[33]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[33]~output .bus_hold = "false"; -defparam \GPIO_1[33]~output .open_drain_output = "false"; -// synopsys translate_on - // Location: IOOBUF_X16_Y34_N2 cycloneive_io_obuf \buzzer_out~output ( .i(\ula_|beep~q ), @@ -4504,6 +4691,19 @@ defparam \DRAM_ADDR[12]~output .bus_hold = "false"; defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \kempston_gnd~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(kempston_gnd), + .obar()); +// synopsys translate_off +defparam \kempston_gnd~output .bus_hold = "false"; +defparam \kempston_gnd~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -4597,7 +4797,7 @@ defparam \DRAM_DQ[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y15_N2 cycloneive_io_obuf \DRAM_DQ[5]~output ( - .i(\sdram_|Mux73~1_combout ), + .i(\sdram_|Mux73~0_combout ), .oe(\sdram_|Mux84~1_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4869,7 +5069,1083 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: IOIBUF_X53_Y16_N8 +cycloneive_io_ibuf \turbo_button~input ( + .i(turbo_button), + .ibar(gnd), + .o(\turbo_button~input_o )); +// synopsys translate_off +defparam \turbo_button~input .bus_hold = "false"; +defparam \turbo_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[0]~21 ( +// Equation(s): +// \debounce_turbo|r_Count[0]~21_combout = \debounce_turbo|r_Count [0] $ (VCC) +// \debounce_turbo|r_Count[0]~22 = CARRY(\debounce_turbo|r_Count [0]) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_turbo|r_Count[0]~21_combout ), + .cout(\debounce_turbo|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_turbo|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[1]~23 ( +// Equation(s): +// \debounce_turbo|r_Count[1]~23_combout = (\debounce_turbo|r_Count [1] & (!\debounce_turbo|r_Count[0]~22 )) # (!\debounce_turbo|r_Count [1] & ((\debounce_turbo|r_Count[0]~22 ) # (GND))) +// \debounce_turbo|r_Count[1]~24 = CARRY((!\debounce_turbo|r_Count[0]~22 ) # (!\debounce_turbo|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[0]~22 ), + .combout(\debounce_turbo|r_Count[1]~23_combout ), + .cout(\debounce_turbo|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N15 +dffeas \debounce_turbo|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[2]~25 ( +// Equation(s): +// \debounce_turbo|r_Count[2]~25_combout = (\debounce_turbo|r_Count [2] & (\debounce_turbo|r_Count[1]~24 $ (GND))) # (!\debounce_turbo|r_Count [2] & (!\debounce_turbo|r_Count[1]~24 & VCC)) +// \debounce_turbo|r_Count[2]~26 = CARRY((\debounce_turbo|r_Count [2] & !\debounce_turbo|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[1]~24 ), + .combout(\debounce_turbo|r_Count[2]~25_combout ), + .cout(\debounce_turbo|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N17 +dffeas \debounce_turbo|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[3]~27 ( +// Equation(s): +// \debounce_turbo|r_Count[3]~27_combout = (\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count[2]~26 )) # (!\debounce_turbo|r_Count [3] & ((\debounce_turbo|r_Count[2]~26 ) # (GND))) +// \debounce_turbo|r_Count[3]~28 = CARRY((!\debounce_turbo|r_Count[2]~26 ) # (!\debounce_turbo|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[2]~26 ), + .combout(\debounce_turbo|r_Count[3]~27_combout ), + .cout(\debounce_turbo|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N19 +dffeas \debounce_turbo|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[4]~29 ( +// Equation(s): +// \debounce_turbo|r_Count[4]~29_combout = (\debounce_turbo|r_Count [4] & (\debounce_turbo|r_Count[3]~28 $ (GND))) # (!\debounce_turbo|r_Count [4] & (!\debounce_turbo|r_Count[3]~28 & VCC)) +// \debounce_turbo|r_Count[4]~30 = CARRY((\debounce_turbo|r_Count [4] & !\debounce_turbo|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[3]~28 ), + .combout(\debounce_turbo|r_Count[4]~29_combout ), + .cout(\debounce_turbo|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N21 +dffeas \debounce_turbo|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N22 +cycloneive_lcell_comb \debounce_turbo|r_Count[5]~31 ( +// Equation(s): +// \debounce_turbo|r_Count[5]~31_combout = (\debounce_turbo|r_Count [5] & (!\debounce_turbo|r_Count[4]~30 )) # (!\debounce_turbo|r_Count [5] & ((\debounce_turbo|r_Count[4]~30 ) # (GND))) +// \debounce_turbo|r_Count[5]~32 = CARRY((!\debounce_turbo|r_Count[4]~30 ) # (!\debounce_turbo|r_Count [5])) + + .dataa(\debounce_turbo|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[4]~30 ), + .combout(\debounce_turbo|r_Count[5]~31_combout ), + .cout(\debounce_turbo|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N23 +dffeas \debounce_turbo|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N24 +cycloneive_lcell_comb \debounce_turbo|r_Count[6]~33 ( +// Equation(s): +// \debounce_turbo|r_Count[6]~33_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count[5]~32 $ (GND))) # (!\debounce_turbo|r_Count [6] & (!\debounce_turbo|r_Count[5]~32 & VCC)) +// \debounce_turbo|r_Count[6]~34 = CARRY((\debounce_turbo|r_Count [6] & !\debounce_turbo|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[5]~32 ), + .combout(\debounce_turbo|r_Count[6]~33_combout ), + .cout(\debounce_turbo|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N25 +dffeas \debounce_turbo|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N26 +cycloneive_lcell_comb \debounce_turbo|r_Count[7]~35 ( +// Equation(s): +// \debounce_turbo|r_Count[7]~35_combout = (\debounce_turbo|r_Count [7] & (!\debounce_turbo|r_Count[6]~34 )) # (!\debounce_turbo|r_Count [7] & ((\debounce_turbo|r_Count[6]~34 ) # (GND))) +// \debounce_turbo|r_Count[7]~36 = CARRY((!\debounce_turbo|r_Count[6]~34 ) # (!\debounce_turbo|r_Count [7])) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[6]~34 ), + .combout(\debounce_turbo|r_Count[7]~35_combout ), + .cout(\debounce_turbo|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N27 +dffeas \debounce_turbo|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N28 +cycloneive_lcell_comb \debounce_turbo|r_Count[8]~37 ( +// Equation(s): +// \debounce_turbo|r_Count[8]~37_combout = (\debounce_turbo|r_Count [8] & (\debounce_turbo|r_Count[7]~36 $ (GND))) # (!\debounce_turbo|r_Count [8] & (!\debounce_turbo|r_Count[7]~36 & VCC)) +// \debounce_turbo|r_Count[8]~38 = CARRY((\debounce_turbo|r_Count [8] & !\debounce_turbo|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[7]~36 ), + .combout(\debounce_turbo|r_Count[8]~37_combout ), + .cout(\debounce_turbo|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N29 +dffeas \debounce_turbo|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N30 +cycloneive_lcell_comb \debounce_turbo|r_Count[9]~39 ( +// Equation(s): +// \debounce_turbo|r_Count[9]~39_combout = (\debounce_turbo|r_Count [9] & (!\debounce_turbo|r_Count[8]~38 )) # (!\debounce_turbo|r_Count [9] & ((\debounce_turbo|r_Count[8]~38 ) # (GND))) +// \debounce_turbo|r_Count[9]~40 = CARRY((!\debounce_turbo|r_Count[8]~38 ) # (!\debounce_turbo|r_Count [9])) + + .dataa(\debounce_turbo|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[8]~38 ), + .combout(\debounce_turbo|r_Count[9]~39_combout ), + .cout(\debounce_turbo|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N31 +dffeas \debounce_turbo|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N0 +cycloneive_lcell_comb \debounce_turbo|r_Count[10]~41 ( +// Equation(s): +// \debounce_turbo|r_Count[10]~41_combout = (\debounce_turbo|r_Count [10] & (\debounce_turbo|r_Count[9]~40 $ (GND))) # (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count[9]~40 & VCC)) +// \debounce_turbo|r_Count[10]~42 = CARRY((\debounce_turbo|r_Count [10] & !\debounce_turbo|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[9]~40 ), + .combout(\debounce_turbo|r_Count[10]~41_combout ), + .cout(\debounce_turbo|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N1 +dffeas \debounce_turbo|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N2 +cycloneive_lcell_comb \debounce_turbo|r_Count[11]~43 ( +// Equation(s): +// \debounce_turbo|r_Count[11]~43_combout = (\debounce_turbo|r_Count [11] & (!\debounce_turbo|r_Count[10]~42 )) # (!\debounce_turbo|r_Count [11] & ((\debounce_turbo|r_Count[10]~42 ) # (GND))) +// \debounce_turbo|r_Count[11]~44 = CARRY((!\debounce_turbo|r_Count[10]~42 ) # (!\debounce_turbo|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[10]~42 ), + .combout(\debounce_turbo|r_Count[11]~43_combout ), + .cout(\debounce_turbo|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N3 +dffeas \debounce_turbo|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N4 +cycloneive_lcell_comb \debounce_turbo|r_Count[12]~45 ( +// Equation(s): +// \debounce_turbo|r_Count[12]~45_combout = (\debounce_turbo|r_Count [12] & (\debounce_turbo|r_Count[11]~44 $ (GND))) # (!\debounce_turbo|r_Count [12] & (!\debounce_turbo|r_Count[11]~44 & VCC)) +// \debounce_turbo|r_Count[12]~46 = CARRY((\debounce_turbo|r_Count [12] & !\debounce_turbo|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[11]~44 ), + .combout(\debounce_turbo|r_Count[12]~45_combout ), + .cout(\debounce_turbo|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N5 +dffeas \debounce_turbo|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N6 +cycloneive_lcell_comb \debounce_turbo|r_Count[13]~47 ( +// Equation(s): +// \debounce_turbo|r_Count[13]~47_combout = (\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count[12]~46 )) # (!\debounce_turbo|r_Count [13] & ((\debounce_turbo|r_Count[12]~46 ) # (GND))) +// \debounce_turbo|r_Count[13]~48 = CARRY((!\debounce_turbo|r_Count[12]~46 ) # (!\debounce_turbo|r_Count [13])) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[12]~46 ), + .combout(\debounce_turbo|r_Count[13]~47_combout ), + .cout(\debounce_turbo|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N7 +dffeas \debounce_turbo|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_State~7 ( +// Equation(s): +// \debounce_turbo|r_State~7_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count [7] & \debounce_turbo|r_Count [5])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(\debounce_turbo|r_Count [7]), + .datad(\debounce_turbo|r_Count [5]), + .cin(gnd), + .combout(\debounce_turbo|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~7 .lut_mask = 16'hC000; +defparam \debounce_turbo|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N2 +cycloneive_lcell_comb \debounce_turbo|LessThan0~0 ( +// Equation(s): +// \debounce_turbo|LessThan0~0_combout = (!\debounce_turbo|r_State~7_combout & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_State~7_combout ), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N30 +cycloneive_lcell_comb \debounce_turbo|LessThan0~1 ( +// Equation(s): +// \debounce_turbo|LessThan0~1_combout = (!\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count [12] & ((\debounce_turbo|LessThan0~0_combout ) # (!\debounce_turbo|r_Count [11])))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [12]), + .datac(\debounce_turbo|LessThan0~0_combout ), + .datad(\debounce_turbo|r_Count [11]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~1 .lut_mask = 16'h1011; +defparam \debounce_turbo|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N8 +cycloneive_lcell_comb \debounce_turbo|r_Count[14]~49 ( +// Equation(s): +// \debounce_turbo|r_Count[14]~49_combout = (\debounce_turbo|r_Count [14] & (\debounce_turbo|r_Count[13]~48 $ (GND))) # (!\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count[13]~48 & VCC)) +// \debounce_turbo|r_Count[14]~50 = CARRY((\debounce_turbo|r_Count [14] & !\debounce_turbo|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[13]~48 ), + .combout(\debounce_turbo|r_Count[14]~49_combout ), + .cout(\debounce_turbo|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N9 +dffeas \debounce_turbo|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N10 +cycloneive_lcell_comb \debounce_turbo|r_Count[15]~51 ( +// Equation(s): +// \debounce_turbo|r_Count[15]~51_combout = (\debounce_turbo|r_Count [15] & (!\debounce_turbo|r_Count[14]~50 )) # (!\debounce_turbo|r_Count [15] & ((\debounce_turbo|r_Count[14]~50 ) # (GND))) +// \debounce_turbo|r_Count[15]~52 = CARRY((!\debounce_turbo|r_Count[14]~50 ) # (!\debounce_turbo|r_Count [15])) + + .dataa(\debounce_turbo|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[14]~50 ), + .combout(\debounce_turbo|r_Count[15]~51_combout ), + .cout(\debounce_turbo|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N11 +dffeas \debounce_turbo|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[16]~53 ( +// Equation(s): +// \debounce_turbo|r_Count[16]~53_combout = (\debounce_turbo|r_Count [16] & (\debounce_turbo|r_Count[15]~52 $ (GND))) # (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count[15]~52 & VCC)) +// \debounce_turbo|r_Count[16]~54 = CARRY((\debounce_turbo|r_Count [16] & !\debounce_turbo|r_Count[15]~52 )) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[15]~52 ), + .combout(\debounce_turbo|r_Count[16]~53_combout ), + .cout(\debounce_turbo|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_turbo|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N13 +dffeas \debounce_turbo|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[17]~55 ( +// Equation(s): +// \debounce_turbo|r_Count[17]~55_combout = (\debounce_turbo|r_Count [17] & (!\debounce_turbo|r_Count[16]~54 )) # (!\debounce_turbo|r_Count [17] & ((\debounce_turbo|r_Count[16]~54 ) # (GND))) +// \debounce_turbo|r_Count[17]~56 = CARRY((!\debounce_turbo|r_Count[16]~54 ) # (!\debounce_turbo|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[16]~54 ), + .combout(\debounce_turbo|r_Count[17]~55_combout ), + .cout(\debounce_turbo|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N15 +dffeas \debounce_turbo|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[18]~57 ( +// Equation(s): +// \debounce_turbo|r_Count[18]~57_combout = (\debounce_turbo|r_Count [18] & (\debounce_turbo|r_Count[17]~56 $ (GND))) # (!\debounce_turbo|r_Count [18] & (!\debounce_turbo|r_Count[17]~56 & VCC)) +// \debounce_turbo|r_Count[18]~58 = CARRY((\debounce_turbo|r_Count [18] & !\debounce_turbo|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[17]~56 ), + .combout(\debounce_turbo|r_Count[18]~57_combout ), + .cout(\debounce_turbo|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N17 +dffeas \debounce_turbo|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[19]~59 ( +// Equation(s): +// \debounce_turbo|r_Count[19]~59_combout = (\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count[18]~58 )) # (!\debounce_turbo|r_Count [19] & ((\debounce_turbo|r_Count[18]~58 ) # (GND))) +// \debounce_turbo|r_Count[19]~60 = CARRY((!\debounce_turbo|r_Count[18]~58 ) # (!\debounce_turbo|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[18]~58 ), + .combout(\debounce_turbo|r_Count[19]~59_combout ), + .cout(\debounce_turbo|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N19 +dffeas \debounce_turbo|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N22 +cycloneive_lcell_comb \debounce_turbo|always0~0 ( +// Equation(s): +// \debounce_turbo|always0~0_combout = (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count [17] & !\debounce_turbo|r_Count [18]))) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(\debounce_turbo|r_Count [19]), + .datac(\debounce_turbo|r_Count [17]), + .datad(\debounce_turbo|r_Count [18]), + .cin(gnd), + .combout(\debounce_turbo|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N24 +cycloneive_lcell_comb \debounce_turbo|always0~1 ( +// Equation(s): +// \debounce_turbo|always0~1_combout = (\debounce_turbo|always0~0_combout & ((\debounce_turbo|LessThan0~1_combout ) # ((!\debounce_turbo|r_Count [15]) # (!\debounce_turbo|r_Count [14])))) + + .dataa(\debounce_turbo|LessThan0~1_combout ), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|always0~0_combout ), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_turbo|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[20]~61 ( +// Equation(s): +// \debounce_turbo|r_Count[20]~61_combout = \debounce_turbo|r_Count[19]~60 $ (!\debounce_turbo|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_turbo|r_Count [20]), + .cin(\debounce_turbo|r_Count[19]~60 ), + .combout(\debounce_turbo|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_turbo|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N21 +dffeas \debounce_turbo|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N0 +cycloneive_lcell_comb \debounce_turbo|always0~2 ( +// Equation(s): +// \debounce_turbo|always0~2_combout = (\debounce_turbo|always0~1_combout & (\debounce_turbo|r_State~q $ ((!\turbo_button~input_o )))) # (!\debounce_turbo|always0~1_combout & ((\debounce_turbo|r_Count [20]) # (\debounce_turbo|r_State~q $ +// (!\turbo_button~input_o )))) + + .dataa(\debounce_turbo|always0~1_combout ), + .datab(\debounce_turbo|r_State~q ), + .datac(\turbo_button~input_o ), + .datad(\debounce_turbo|r_Count [20]), + .cin(gnd), + .combout(\debounce_turbo|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~2 .lut_mask = 16'hD7C3; +defparam \debounce_turbo|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y29_N13 +dffeas \debounce_turbo|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N10 +cycloneive_lcell_comb \debounce_turbo|r_State~4 ( +// Equation(s): +// \debounce_turbo|r_State~4_combout = (!\debounce_turbo|r_Count [0] & (!\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count [1] & !\debounce_turbo|r_Count [2]))) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(\debounce_turbo|r_Count [3]), + .datac(\debounce_turbo|r_Count [1]), + .datad(\debounce_turbo|r_Count [2]), + .cin(gnd), + .combout(\debounce_turbo|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_turbo|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N6 +cycloneive_lcell_comb \debounce_turbo|r_State~2 ( +// Equation(s): +// \debounce_turbo|r_State~2_combout = (\debounce_turbo|r_Count [20] & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_Count [20]), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_turbo|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N28 +cycloneive_lcell_comb \debounce_turbo|r_State~0 ( +// Equation(s): +// \debounce_turbo|r_State~0_combout = (!\debounce_turbo|r_Count [13] & (\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count [12] & \debounce_turbo|r_Count [15]))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|r_Count [12]), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_turbo|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~1 ( +// Equation(s): +// \debounce_turbo|r_State~1_combout = (\debounce_turbo|r_Count [7] & (\debounce_turbo|r_Count [11] & (\debounce_turbo|r_Count [5] & \debounce_turbo|r_Count [6]))) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(\debounce_turbo|r_Count [11]), + .datac(\debounce_turbo|r_Count [5]), + .datad(\debounce_turbo|r_Count [6]), + .cin(gnd), + .combout(\debounce_turbo|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N0 +cycloneive_lcell_comb \debounce_turbo|r_State~3 ( +// Equation(s): +// \debounce_turbo|r_State~3_combout = (\debounce_turbo|r_State~2_combout & (\debounce_turbo|r_State~0_combout & (\debounce_turbo|r_State~1_combout & \debounce_turbo|always0~0_combout ))) + + .dataa(\debounce_turbo|r_State~2_combout ), + .datab(\debounce_turbo|r_State~0_combout ), + .datac(\debounce_turbo|r_State~1_combout ), + .datad(\debounce_turbo|always0~0_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N8 +cycloneive_lcell_comb \debounce_turbo|r_State~5 ( +// Equation(s): +// \debounce_turbo|r_State~5_combout = (\debounce_turbo|r_State~4_combout & (!\debounce_turbo|r_Count [4] & \debounce_turbo|r_State~3_combout )) + + .dataa(\debounce_turbo|r_State~4_combout ), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(\debounce_turbo|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~5 .lut_mask = 16'h2200; +defparam \debounce_turbo|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~6 ( +// Equation(s): +// \debounce_turbo|r_State~6_combout = (\debounce_turbo|r_State~5_combout & (\turbo_button~input_o )) # (!\debounce_turbo|r_State~5_combout & ((\debounce_turbo|r_State~q ))) + + .dataa(\turbo_button~input_o ), + .datab(gnd), + .datac(\debounce_turbo|r_State~q ), + .datad(\debounce_turbo|r_State~5_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~6 .lut_mask = 16'hAAF0; +defparam \debounce_turbo|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N5 +dffeas \debounce_turbo|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_turbo|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_State .is_wysiwyg = "true"; +defparam \debounce_turbo|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N14 +cycloneive_lcell_comb \turbo~0 ( +// Equation(s): +// \turbo~0_combout = !\turbo~q + + .dataa(gnd), + .datab(gnd), + .datac(\turbo~q ), + .datad(gnd), + .cin(gnd), + .combout(\turbo~0_combout ), + .cout()); +// synopsys translate_off +defparam \turbo~0 .lut_mask = 16'h0F0F; +defparam \turbo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N15 +dffeas turbo( + .clk(!\debounce_turbo|r_State~q ), + .d(\turbo~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\turbo~q ), + .prn(vcc)); +// synopsys translate_off +defparam turbo.is_wysiwyg = "true"; +defparam turbo.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y29_N4 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4886,7 +6162,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y29_N5 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4905,34 +6181,24 @@ defparam \ula_|clocks_|counter[0] .is_wysiwyg = "true"; defparam \ula_|clocks_|counter[0] .power_up = "low"; // synopsys translate_on -// Location: IOIBUF_X25_Y34_N8 -cycloneive_io_ibuf \SW[2]~input ( - .i(SW[2]), - .ibar(gnd), - .o(\SW[2]~input_o )); -// synopsys translate_off -defparam \SW[2]~input .bus_hold = "false"; -defparam \SW[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): -// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) +// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\turbo~q ) # (!\ula_|clocks_|counter [0]))) .dataa(gnd), - .datab(\ula_|clocks_|counter [0]), + .datab(\turbo~q ), .datac(\ula_|clocks_|clk_cpu~q ), - .datad(\SW[2]~input_o ), + .datad(\ula_|clocks_|counter [0]), .cin(gnd), .combout(\ula_|clocks_|clk_cpu~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; +defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h3C0F; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4951,7 +6217,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4964,33 +6230,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -5001,7 +6240,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N12 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -5018,7 +6257,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N18 +// Location: LCCOMB_X27_Y15_N4 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -5035,7 +6274,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y32_N8 +// Location: LCCOMB_X27_Y1_N28 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -5052,7 +6291,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X26_Y32_N9 +// Location: FF_X27_Y1_N29 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -5071,7 +6310,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -5084,7 +6323,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y14_N19 +// Location: FF_X27_Y15_N5 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -5103,79 +6342,68 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: FF_X31_Y14_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Location: LCCOMB_X23_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC .dataa(gnd), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(gnd), + .datad(gnd), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y10_N1 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G7 +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~55_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), @@ -5188,21 +6416,40 @@ defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout ) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .combout(\z80_|sequencer_|ena_M~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N19 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -5218,7 +6465,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N8 +// Location: LCCOMB_X26_Y31_N0 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) @@ -5236,24 +6483,24 @@ defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N14 +// Location: LCCOMB_X30_Y31_N10 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~0_combout ), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Add0~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hC0C0; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y29_N15 +// Location: FF_X30_Y31_N11 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -5272,7 +6519,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N10 +// Location: LCCOMB_X26_Y31_N2 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -5290,7 +6537,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N22 +// Location: LCCOMB_X29_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -5307,7 +6554,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y30_N23 +// Location: FF_X29_Y31_N13 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -5326,7 +6573,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N12 +// Location: LCCOMB_X26_Y31_N4 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -5344,7 +6591,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N31 +// Location: FF_X29_Y31_N15 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5363,33 +6610,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N14 +// Location: LCCOMB_X26_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(\ula_|video_|vga_hc [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y30_N11 +// Location: FF_X26_Y31_N7 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|Add0~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -5400,7 +6647,24 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N16 +// Location: LCCOMB_X30_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N8 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -5418,7 +6682,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N7 +// Location: FF_X26_Y31_N25 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5437,169 +6701,42 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Location: LCCOMB_X30_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( // Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & !\ula_|video_|vga_hc [4]))) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Add0~10_combout ), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [4]), .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), + .combout(\ula_|video_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y30_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N22 +// Location: LCCOMB_X26_Y31_N14 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) // \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - .dataa(\ula_|video_|vga_hc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~13 ), .combout(\ula_|video_|Add0~14_combout ), .cout(\ula_|video_|Add0~15 )); // synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N3 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N26 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N24 +// Location: LCCOMB_X26_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) @@ -5617,15 +6754,15 @@ defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N28 +// Location: LCCOMB_X26_Y31_N22 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~16_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); @@ -5634,7 +6771,7 @@ defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N17 +// Location: FF_X26_Y31_N15 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5653,32 +6790,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N26 +// Location: LCCOMB_X26_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N2 +// Location: LCCOMB_X26_Y31_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -5687,7 +6824,7 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N5 +// Location: FF_X26_Y31_N31 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5706,24 +6843,134 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y29_N0 +// Location: LCCOMB_X30_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal1~0 ( // Equation(s): // \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N0 +// Location: LCCOMB_X26_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y31_N23 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N21 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N29 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) @@ -5741,312 +6988,77 @@ defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Location: LCCOMB_X31_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [0] & !\ula_|video_|vga_vc [1]))) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Add1~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N31 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [3]), .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), + .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N21 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N26 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N27 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N23 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N10 +// Location: LCCOMB_X31_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N9 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N12 +// Location: LCCOMB_X31_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N16 +// Location: LCCOMB_X27_Y31_N28 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N17 +// Location: FF_X27_Y31_N29 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -6065,7 +7077,7 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N14 +// Location: LCCOMB_X31_Y31_N20 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) @@ -6083,7 +7095,7 @@ defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N22 +// Location: LCCOMB_X27_Y31_N8 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) @@ -6100,7 +7112,7 @@ defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N23 +// Location: FF_X27_Y31_N9 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -6119,25 +7131,25 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N16 +// Location: LCCOMB_X31_Y31_N22 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) // \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~15 ), .combout(\ula_|video_|Add1~16_combout ), .cout(\ula_|video_|Add1~17 )); // synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N20 +// Location: LCCOMB_X27_Y31_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): // \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) @@ -6154,7 +7166,7 @@ defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N21 +// Location: FF_X27_Y31_N7 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -6173,41 +7185,41 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N18 +// Location: LCCOMB_X31_Y31_N24 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) +// \ula_|video_|Add1~18_combout = \ula_|video_|vga_vc [9] $ (\ula_|video_|Add1~17 ) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [9]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), + .datad(gnd), .cin(\ula_|video_|Add1~17 ), .combout(\ula_|video_|Add1~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .lut_mask = 16'h5A5A; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N8 +// Location: LCCOMB_X27_Y31_N4 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N9 +// Location: FF_X27_Y31_N5 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -6226,32 +7238,15 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N30 +// Location: LCCOMB_X27_Y31_N24 cycloneive_lcell_comb \ula_|video_|Equal2~0 ( // Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [6]))) .dataa(\ula_|video_|vga_vc [8]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), .combout(\ula_|video_|Equal2~0_combout ), .cout()); @@ -6260,13 +7255,13 @@ defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N16 +// Location: LCCOMB_X31_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) +// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal3~0_combout & (\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|Equal3~0_combout ), + .dataa(\ula_|video_|Equal3~0_combout ), + .datab(\ula_|video_|vga_vc [9]), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), @@ -6277,24 +7272,24 @@ defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N24 +// Location: LCCOMB_X27_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( // Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~0_combout ), .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N25 +// Location: FF_X27_Y31_N13 dffeas \ula_|video_|vga_vc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[0]~0_combout ), @@ -6313,15 +7308,267 @@ defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N18 +// Location: LCCOMB_X31_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N18 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N19 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h0A0C; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[2]~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N2 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [3]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~6_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~6_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N3 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N0 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) .dataa(\ula_|video_|vga_vc [0]), .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [3]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -6330,20 +7577,20 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N12 +// Location: LCCOMB_X31_Y31_N26 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(\ula_|video_|Equal2~1_combout ), - .datab(gnd), - .datac(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(gnd), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -6357,14 +7604,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X31_Y27_N2 +// Location: LCCOMB_X28_Y31_N26 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & !\SW[1]~input_o ))) - .dataa(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), .datab(\ula_|video_|vga_vc [1]), - .datac(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -6374,75 +7621,77 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|ir_|opcode[4]~feeder ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|ir_|opcode[4]~feeder_combout = \z80_|bus_control_|db[4]~18_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal0~0_combout ), + .combout(\z80_|ir_|opcode[4]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; -defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; +defparam \z80_|ir_|opcode[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N8 +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N13 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N9 +// Location: FF_X36_Y11_N21 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -6461,340 +7710,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N27 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - - .dataa(\z80_|clk_delay_|DFF_inst5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N24 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~2_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & -// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N25 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 +// Location: LCCOMB_X36_Y11_N30 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N1 +// Location: FF_X36_Y11_N31 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -6813,2615 +7746,32 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N2 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIOWrite~2_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|fMWrite~3_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~45_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N11 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~97_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~96_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~98_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~98_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), - .datab(\z80_|execute_|ctl_inc_cy~96_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(gnd), - .datad(\z80_|execute_|fMWrite~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [7]), - .datac(gnd), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N24 +// Location: LCCOMB_X37_Y14_N10 cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( // Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) +// \z80_|execute_|ctl_ir_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|ctl_ir_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h5050; defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; -defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & -// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|fMWrite~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # -// (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N21 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y11_N17 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N15 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X40_Y11_N23 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~12_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~16_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N13 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N21 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N17 +// Location: FF_X30_Y12_N5 dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~53_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|execute_|setM1~55_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -9432,24 +7782,24 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N8 +// Location: LCCOMB_X30_Y12_N8 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h0F0F; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N9 +// Location: FF_X30_Y12_N9 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -9468,7 +7818,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N7 +// Location: FF_X30_Y12_N19 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -9487,7 +7837,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N6 +// Location: LCCOMB_X30_Y12_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & @@ -9505,34385 +7855,358 @@ defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N10 +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h333B; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~0_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~0 .lut_mask = 16'h0505; +defparam \z80_|pla_decode_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [0] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0800; defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|fIOWrite~0_combout ), - .datad(\z80_|execute_|fIORead~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|execute_|fIORead~0_combout ), - .datac(\z80_|execute_|fIOWrite~1_combout ), - .datad(\z80_|execute_|fIORead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N23 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|im2~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|execute_|fMRead~4_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal40~2_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; -defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~14_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|execute_|setM1~57_combout ), - .datab(\z80_|execute_|setM1~38_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~19_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|DFFE_instED~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~31_combout ), - .datab(\z80_|execute_|ctl_mRead~32_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N19 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~33_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N29 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N11 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) - - .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), - .datab(\z80_|execute_|fIORead~3_combout ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~1_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N12 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h3000; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G9 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & -// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N13 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [5]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [3]), - .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N27 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N7 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [0]), - .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N17 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X18_Y12_N19 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N29 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N13 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N23 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\PS2_DAT~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|always1~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y10_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N13 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X21_Y8_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) - - .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N25 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N27 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N25 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N5 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) - - .dataa(\z80_|resets_|clrpc_int~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & -// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~99_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~37_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal12~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal33~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout -// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal76~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal10~1_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & -// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|fMRead~8_combout ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_sw_4d~0_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; -defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_inc_dec~3_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N25 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|setM1~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & -// ((\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|execute_|ctl_state_alu~13_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|fMRead~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~25_combout ), - .datac(\z80_|execute_|ctl_mRead~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & -// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_sw_1d~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & -// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; -defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # -// (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # -// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_1d~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(\z80_|execute_|ctl_sw_4u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .datad(\z80_|execute_|ctl_sw_4u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_2d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|fMRead~18_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~22_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|fMRead~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_2d~9_combout ), - .datac(\z80_|execute_|ctl_sw_1d~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; -defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal44~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & -// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; -defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_flags_alu~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; -defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~18_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~26_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datab(\z80_|alu_control_|db[1]~27_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Location: LCCOMB_X35_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), .datac(\z80_|sequencer_|DFFE_M2_ff~q ), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & -// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_oe~15_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ -// (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datac(\z80_|execute_|ctl_sw_2u~6_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N27 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; -defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_cy~50_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N24 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~26_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~10_combout ), - .datad(\z80_|execute_|ctl_sw_2d~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_alu_oe~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~10_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & -// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) - - .dataa(\z80_|alu_control_|db[3]~36_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # -// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) - - .dataa(\z80_|execute_|setM1~50_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(\z80_|alu_flags_|flags_xf~q ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; -defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~87_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~64_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~65_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~97_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~57_combout ), - .datad(\z80_|execute_|ctl_inc_cy~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout -// & (\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal33~2_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; -defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|pc_inc_hold~19_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; -defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|pc_inc_hold~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # -// ((\z80_|execute_|ctl_inc_cy~62_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_inc_cy~68_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~17_combout ), - .datab(\z80_|execute_|ctl_inc_cy~74_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~73_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~95_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|ctl_inc_cy~95_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datad(\z80_|execute_|ctl_inc_cy~77_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_inc_cy~78_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~15_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~70_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|ctl_inc_cy~79_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # -// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|pc_inc_hold~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_inc_cy~51_combout ), - .datac(\z80_|execute_|ctl_inc_cy~49_combout ), - .datad(\z80_|execute_|ctl_inc_cy~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_inc_cy~90_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~83_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~96_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~100_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|ctl_inc_cy~84_combout ), - .datac(\z80_|execute_|ctl_inc_cy~100_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~24_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|pc_inc_hold~29_combout ), - .datad(\z80_|execute_|pc_inc_hold~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|Q [0]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( -// Equation(s): -// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[0]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|execute_|ctl_inc_dec~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [2]), - .datab(gnd), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( -// Equation(s): -// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db_low[2]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; -defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|alu_|db[1]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & -// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(\z80_|execute_|ctl_al_we~10_combout ), - .datac(\z80_|execute_|ctl_al_we~8_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~11_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N7 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( -// Equation(s): -// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; -defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & -// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N11 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( -// Equation(s): -// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; -defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( -// Equation(s): -// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; -defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( -// Equation(s): -// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; -defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(\z80_|address_latch_|Q [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N3 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q -// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N1 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & -// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N2 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[4]~8_combout ), - .datad(\z80_|alu_|db_high[0]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N13 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( -// Equation(s): -// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( -// Equation(s): -// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db_low[1]~18_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [1]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~16_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( -// Equation(s): -// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # -// (!\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|alu_|db_low[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[1]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; -defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[1]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N9 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout -// )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_flags_alu~21_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # -// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N11 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & -// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # -// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|alu_|db_high[2]~13_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[2]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N3 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_high [2]), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( -// Equation(s): -// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; -defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db_high[2]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|alu_|db_high[2]~10_combout ), - .datac(\z80_|alu_|db_high[2]~9_combout ), - .datad(\z80_|alu_|db_high[2]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[2]~12_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|alu_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N16 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( -// Equation(s): -// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; -defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [1]), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[1]~14_combout ), - .datad(\z80_|alu_|db_high[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|db_high[1]~18_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N21 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N4 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N18 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[7]~19_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & -// ((\z80_|alu_|db[7]~20_combout ))))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~8_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N11 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|alu_|op1_high [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; -defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_high[2]~13_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[2]~14_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N31 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; -defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|op1_low [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_|alu_op2[2]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|alu_op2[2]~1_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # -// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|alu_op1[3]~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op2[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( -// Equation(s): -// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N23 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( -// Equation(s): -// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~24_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( -// Equation(s): -// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & -// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[0]~22_combout ), - .datac(\z80_|alu_|db_low[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_low[0]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N17 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # -// (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & -// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout -// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # -// (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & -// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[0]~1_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(gnd), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( -// Equation(s): -// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; -defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[0]~23_combout ), - .datad(\z80_|alu_|db_high[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|db_high[0]~24_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N19 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( -// Equation(s): -// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|result_lo [2]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( -// Equation(s): -// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( -// Equation(s): -// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|alu_|db_low[2]~12_combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; -defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( -// Equation(s): -// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[2]~10_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~11_combout ), - .datad(\z80_|alu_|db_low[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; -defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N22 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~11_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~33_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( -// Equation(s): -// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; -defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( -// Equation(s): -// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[2]~28_combout ), - .datab(\z80_|alu_control_|db[2]~24_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[2]~29_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; -defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N27 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & -// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N20 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_control_|db[0]~14_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( -// Equation(s): -// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( -// Equation(s): -// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[0]~11_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_flags_|flags_cf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout -// ))))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(\z80_|execute_|ctl_inc_cy~93_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~9_combout ), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & -// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q -// [2]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~34_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|sw1_|db_down[3]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( -// Equation(s): -// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; -defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N10 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( -// Equation(s): -// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y10_N25 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( -// Equation(s): -// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~6_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) - - .dataa(\z80_|alu_|db_low[3]~5_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|result_lo [3]), - .datad(\z80_|alu_|db_low[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( -// Equation(s): -// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; -defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[3]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N13 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[3]~7_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N21 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op1[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & -// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|alu_control_|out[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|alu_|db[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout -// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_control_|out[6]~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal10~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( // Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), + .combout(\z80_|execute_|ctl_mRead~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_sw_1d~2_combout = (\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~2_combout & +// (((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - .dataa(\z80_|pla_decode_|Equal64~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N2 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[4]~31_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( -// Equation(s): -// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[4]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; -defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N5 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [4]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|Q [5]), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [3]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [1]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [14]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X30_Y12_N19 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// (!\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; -defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .datad(\z80_|alu_|alu_parity_out~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y11_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|alu_|db_high[0]~25_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .datab(\z80_|alu_control_|db[6]~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N25 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|alu_control_|sel[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_control_|sel[1]~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N9 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N13 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [11]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & -// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y4_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [11]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N6 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N7 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N26 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\z80_|address_pins_|abus[10]~20_combout ), - .datad(\ula_|zx_keyboard_|keys[3][2]~q ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hC4F5; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~2_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N31 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; -defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) - - .dataa(\z80_|address_latch_|abusz [14]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N14 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; -defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; -defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N1 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N10 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & -// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hC4F5; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [13]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N18 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|key_row~1_combout ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'h80A0; -defparam \D[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [0]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; -defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N13 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [9]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [8]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N20 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'hF531; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N24 -cycloneive_lcell_comb \D[2]~46 ( -// Equation(s): -// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) - - .dataa(\D[2]~43_combout ), - .datab(\D[2]~45_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hF8F0; -defparam \D[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N3 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|clk_delay_|DFF_inst5~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( -// Equation(s): -// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; -defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N8 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0020; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N18 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h4000; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N16 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|address_latch_|abusz [2]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [3]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [3]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [6]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X24_Y19_N11 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N3 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ExtRamWE~0_combout ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X25_Y19_N15 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N19 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N10 -cycloneive_lcell_comb \D[2]~50 ( -// Equation(s): -// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\D[2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~50 .lut_mask = 16'hF838; -defparam \D[2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N26 -cycloneive_lcell_comb \D[2]~51 ( -// Equation(s): -// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~50_combout ), - .cin(gnd), - .combout(\D[2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~51 .lut_mask = 16'hEE30; -defparam \D[2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N24 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N8 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N25 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|vram_address[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N31 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N4 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N5 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N23 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N17 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( -// Equation(s): -// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) - - .dataa(\ula_|video_|vga_vc [8]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N7 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N18 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|vram_address[10]~2_combout ), - .datab(\ula_|video_|Add4~4_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N19 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N24 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N25 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N3 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N28 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N29 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N20 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N21 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y18_N0 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N22 -cycloneive_lcell_comb \D[2]~47 ( -// Equation(s): -// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~47 .lut_mask = 16'hE6A2; -defparam \D[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N24 -cycloneive_lcell_comb \D[2]~48 ( -// Equation(s): -// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[2]~47_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~48 .lut_mask = 16'h4B48; -defparam \D[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N16 -cycloneive_lcell_comb \D[2]~49 ( -// Equation(s): -// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[2]~47_combout ), - .datad(\D[2]~48_combout ), - .cin(gnd), - .combout(\D[2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~49 .lut_mask = 16'hC3E0; -defparam \D[2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N6 -cycloneive_lcell_comb \D[2]~119 ( -// Equation(s): -// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~51_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~51_combout ), - .datad(\D[2]~49_combout ), - .cin(gnd), - .combout(\D[2]~119_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~119 .lut_mask = 16'hF4B0; -defparam \D[2]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N20 -cycloneive_lcell_comb \D[2]~52 ( -// Equation(s): -// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[2]~46_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~52 .lut_mask = 16'hBFB3; -defparam \D[2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N26 -cycloneive_lcell_comb \D[2]~53 ( -// Equation(s): -// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~52_combout ), - .cin(gnd), - .combout(\D[2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~53 .lut_mask = 16'hF511; -defparam \D[2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout -// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\D[2]~53_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_re~combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N17 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[2]~12_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N9 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .combout(\z80_|execute_|ctl_sw_1d~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_1d~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_1d~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Location: LCCOMB_X31_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & -// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~21_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(gnd), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; -defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( -// Equation(s): -// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|sw1_|db_down[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; -defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N2 -cycloneive_lcell_comb \D[6]~103 ( -// Equation(s): -// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~103 .lut_mask = 16'hEA4A; -defparam \D[6]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N30 -cycloneive_lcell_comb \D[6]~104 ( -// Equation(s): -// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~103_combout ), - .cin(gnd), - .combout(\D[6]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~104 .lut_mask = 16'hEE30; -defparam \D[6]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N14 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hBCB0; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N12 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\D[6]~100_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'h2D28; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N0 -cycloneive_lcell_comb \D[6]~102 ( -// Equation(s): -// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~100_combout ), - .datad(\D[6]~101_combout ), - .cin(gnd), - .combout(\D[6]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~102 .lut_mask = 16'hC3E0; -defparam \D[6]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N8 -cycloneive_lcell_comb \D[6]~127 ( -// Equation(s): -// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~104_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[6]~104_combout ), - .datad(\D[6]~102_combout ), - .cin(gnd), - .combout(\D[6]~127_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~127 .lut_mask = 16'hF4B0; -defparam \D[6]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N28 -cycloneive_lcell_comb \D[6]~99 ( -// Equation(s): -// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\raw_loader_in~input_o ), - .cin(gnd), - .combout(\D[6]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~99 .lut_mask = 16'hFFCF; -defparam \D[6]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N10 -cycloneive_lcell_comb \D[6]~114 ( -// Equation(s): -// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~114_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~114 .lut_mask = 16'hFB73; -defparam \D[6]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N12 -cycloneive_lcell_comb \D[6]~115 ( -// Equation(s): -// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~114_combout ), - .cin(gnd), - .combout(\D[6]~115_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~115 .lut_mask = 16'hF511; -defparam \D[6]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & -// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[6]~115_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N15 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[6]~9_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|interrupts_|iff1~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y12_N5 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y27_N8 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal2~3_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [5]))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\ula_|video_|vga_hc [7]), - .datad(\z80_|interrupts_|iff1~q ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y27_N9 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N25 -dffeas \z80_|interrupts_|DFFE_inst44 ( +// Location: FF_X29_Y18_N25 +dffeas \z80_|decode_state_|DFFE_instED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), + .q(\z80_|decode_state_|DFFE_instED~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N16 +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -43892,24 +8215,58 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N12 +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0044; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|decode_state_|in_halt~0_combout ), - .datab(\z80_|pla_decode_|Equal77~1_combout ), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N13 +// Location: FF_X31_Y12_N29 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -43928,407 +8285,30744 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N22 +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0505; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~3 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_sw_1d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0101; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'hC000; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hA0A0; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~0_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_state_iy_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N25 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal1~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|pla_decode_|Equal3~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hDFFF; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((!\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h707F; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~3 ( +// Equation(s): +// \z80_|execute_|ixy_d~3_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (\z80_|execute_|ixy_d~8_combout ) # ((\z80_|execute_|ixy_d~16_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ixy_d~11_combout & +// ((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~12_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hBBB0; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~2 ( +// Equation(s): +// \z80_|execute_|ixy_d~2_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~2 .lut_mask = 16'h0500; +defparam \z80_|execute_|ixy_d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~10_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q +// & \z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~19 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~19_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~19 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~8_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~8 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_bus_db_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~8_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7500; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~16_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_mWrite~10_combout ))) # (!\z80_|execute_|ctl_ir_we~16_combout & (((!\z80_|execute_|ctl_ir_we~15_combout ) # +// (!\z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|nM1_int~2_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal1~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|pla_decode_|Equal47~0_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~19_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h3700; defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal12~0_combout ))) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|fMRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMWrite~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_mRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) +// \z80_|execute_|ctl_reg_in_hi~9_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) .dataa(\z80_|execute_|ctl_mRead~12_combout ), .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_reg_in_hi~9_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|nextM~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_mRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|ir_|opcode [7]), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~15_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~18_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout & (((!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h0037; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (((!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h3070; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|pla_decode_|Equal44~0_combout ))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|fMRead~29_combout ), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( // Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), + .combout(\z80_|pla_decode_|Equal52~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) - - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~30_combout ), - .datac(\z80_|execute_|fMRead~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) +// \z80_|execute_|fMRead~20_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~11_combout )))) - .dataa(\z80_|execute_|fMRead~27_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|fMRead~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~16_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|fMRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), + .combout(\z80_|execute_|fMRead~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h20A0; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X31_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|pla_decode_|Equal11~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X31_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) +// \z80_|pla_decode_|Equal10~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ctl_mRead~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|pla_decode_|Equal10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|execute_|fMRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X35_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~16_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|fMRead~15_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N10 +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|fMRead~19_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_mWrite~11_combout ))) + + .dataa(\z80_|execute_|fMRead~19_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~2_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [3])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~2 .lut_mask = 16'h0003; +defparam \z80_|pla_decode_|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~32_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal34~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & \z80_|execute_|ctl_reg_in_hi~10_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .dataa(\z80_|execute_|ctl_mRead~22_combout ), .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~17_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'h8000; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|fMRead~22_combout ))) - .dataa(\z80_|execute_|fMRead~23_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2d~8_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), .datad(\z80_|execute_|fMRead~22_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N0 +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (!\z80_|execute_|ctl_sw_1d~3_combout & (!\z80_|execute_|ctl_im_we~combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~3_combout ), + .datac(\z80_|execute_|ctl_im_we~combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # (((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) # (!\z80_|execute_|ctl_bus_db_oe~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~3_combout = (\z80_|execute_|ctl_bus_zero_oe~2_combout ) # ((\z80_|decode_state_|in_halt~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~3 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_bus_zero_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|execute_|ctl_sw_1d~4_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'h000D; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [1] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[7]~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = ((!\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_flags_bus~8_combout & !\z80_|execute_|ctl_mRead~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hFF1F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal68~2_combout & !\z80_|pla_decode_|Equal20~0_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~10_combout & (\z80_|execute_|ctl_flags_bus~11_combout & \z80_|execute_|ctl_flags_bus~14_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~10_combout ), + .datac(\z80_|execute_|ctl_flags_bus~11_combout ), + .datad(\z80_|execute_|ctl_flags_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~16_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~17_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_mRead~24_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~17_combout & (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~28 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~28_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~28 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~28_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_inc_cy~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~16_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (\z80_|execute_|ctl_reg_out_lo~6_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout )) # +// (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~13_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~19_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~19 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_ir_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|ir_|opcode [7])) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~19_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|setM1~58_combout )) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_sw_2u~6_combout ) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|setM1~58_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout & (\z80_|execute_|ctl_reg_out_lo~2_combout & ((!\z80_|execute_|ctl_sw_2u~7_combout ) # (!\z80_|execute_|rsel0~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) # (!\z80_|execute_|ctl_sw_1d~4_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~4_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~29 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~3_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~4_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|rsel3~combout ) # ((!\z80_|execute_|ctl_reg_out_lo~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~3 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_reg_out_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~9_combout = (\z80_|execute_|ctl_sw_2u~7_combout & (\z80_|ir_|opcode [0] $ (((!\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1]))))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~9 .lut_mask = 16'h9500; +defparam \z80_|execute_|ctl_sw_2u~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|execute_|ctl_mWrite~18_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_out_hi~3_combout & (!\z80_|execute_|ctl_sw_2u~9_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .datac(\z80_|execute_|ctl_sw_2u~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) # (!\z80_|execute_|ctl_ir_we~19_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|execute_|ctl_ir_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~3_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h0888; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~14_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h30F0; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_alu_oe~10_combout & (\z80_|execute_|ctl_bus_db_we~6_combout & \z80_|execute_|ctl_reg_in_lo~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~10_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~8_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~8 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_sw_2u~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal69~0_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|pla_decode_|Equal20~0_combout & (\z80_|execute_|nextM~4_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0030; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~49_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|setM1~51_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h1050; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~9_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~9 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_sw_4d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~52_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h007F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout ) # ((\z80_|execute_|ctl_sw_2u~8_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~2_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~2 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_flags_alu~22_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # (\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~14_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & \z80_|execute_|ctl_reg_out_hi~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_use_sp~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (!\z80_|ir_|opcode [5] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~14_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAFAB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_sw_2u~3_combout & !\z80_|execute_|ctl_alu_shift_oe~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|setM1~19_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|setM1~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~8 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~8_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_cf_we~7_combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~8 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~15_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) +// # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~15 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_pf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~1_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_pf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & +// (((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_flags_pf_we~1_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_flags_alu~12_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_alu~17_combout )) # (!\z80_|execute_|ctl_flags_alu~23_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~12_combout ), + .datab(\z80_|execute_|ctl_flags_alu~23_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~5_combout )))) # (!\z80_|pla_decode_|Equal48~0_combout & +// (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFD; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_ir_we~13_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~16 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & +// (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_oe~16_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & \z80_|execute_|ctl_alu_core_S~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~16_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (\z80_|execute_|ctl_flags_pf_we~1_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~23_combout & (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~23_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~50_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~50 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal1~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~5_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~19_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = ((!\z80_|execute_|ixy_d~5_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2020; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~49_combout = ((\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~49 .lut_mask = 16'hD555; +defparam \z80_|execute_|ctl_alu_shift_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~49_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~51_combout = (\z80_|execute_|ctl_ir_we~11_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~51_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~14_combout & (\z80_|execute_|ctl_alu_shift_oe~51_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0EAA; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~48_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~14_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~48 .lut_mask = 16'hBAAA; +defparam \z80_|execute_|ctl_alu_shift_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & !\z80_|execute_|ctl_reg_gp_sel~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (((\z80_|execute_|ctl_alu_shift_oe~48_combout & !\z80_|execute_|ctl_alu_bs_oe~8_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (\z80_|execute_|ctl_alu_shift_oe~35_combout & (\z80_|execute_|ctl_alu_shift_oe~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ))) # (!\z80_|execute_|ixy_d~5_combout & +// (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = ((\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~24_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_ir_we~11_combout & +// (((\z80_|execute_|ctl_ir_we~14_combout & \z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~36_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~18_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'hF400; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~47_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~26_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (\z80_|execute_|ctl_mWrite~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & \z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (\z80_|execute_|ctl_alu_shift_oe~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_alu_bs_oe~combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|alu_|db_high[3]~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~17_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_alu_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_oe~5_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_alu_oe~8_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_66_oe~4_combout ) # (\z80_|execute_|ctl_alu_oe~13_combout ))) # (!\z80_|execute_|ctl_alu_oe~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~12_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # (((!\z80_|execute_|ctl_flags_alu~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|nextM~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (((\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~17_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~11_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0F07; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~10_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hDCFC; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = (\z80_|execute_|ctl_sw_2d~12_combout ) # (((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout )) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_sw_2d~12_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~15_combout ) # ((\z80_|execute_|ctl_reg_out_hi~5_combout ) # (\z80_|execute_|ctl_sw_2d~13_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~22_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal37~0_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|fMRead~10_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h1F00; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|fMRead~11_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~9_combout )) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~9_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~27_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~27 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_sel_wz~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal47~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'hAA00; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_in_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h2323; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & ((\z80_|execute_|ctl_reg_sel_wz~16_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'hAF03; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~22_combout = (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal5~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal5~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~3_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal2~3_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal5~2 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (((\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal5~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h0233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_mRead~9_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~4_combout & (\z80_|execute_|ctl_inc_dec~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_sw_1d~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|execute_|ctl_sw_4d~5_combout & (\z80_|execute_|ctl_reg_sel_wz~22_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h3F2A; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_al_we~7_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (!\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout & (!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~3_combout = (!\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~3 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_al_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (!\z80_|execute_|ctl_mRead~4_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'h4555; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )) # (!\z80_|execute_|ctl_al_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~3_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout ))) # (!\z80_|pla_decode_|Equal77~0_combout ) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & !\z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout )) # (!\z80_|execute_|ctl_alu_oe~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_ir_we~18_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (!\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0300; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & \z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~17_combout & (!\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~2_combout = (!\z80_|execute_|ctl_mRead~3_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # ((!\z80_|execute_|ctl_al_we~2_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = ((\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_al_we~4_combout ) # (\z80_|execute_|ctl_al_we~6_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~8_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout ))) # (!\z80_|execute_|setM1~55_combout ) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~9_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N25 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~0_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h0F0D; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & \z80_|pla_decode_|Equal52~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~8_combout ) # (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_reg_gp_sel~13_combout )) # (!\z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~9 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~9 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_pf_sel[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_flags_pf_we~2_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[2] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [2] = (\z80_|bus_control_|db[2]~14_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[2]~14_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h80FF; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal21~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~2_combout = ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # (\z80_|execute_|ctl_alu_op1_oe~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~2 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_alu_op1_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_ir_we~15_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h5400; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|execute_|ctl_alu_op_low~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~4_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~18_combout & ((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~13_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~11_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~36_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[3]~5_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_low[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFEE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N17 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N25 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFCA0; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # ((\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~7_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (((\z80_|execute_|ctl_alu_op_low~17_combout ) # (!\z80_|execute_|ctl_state_alu~7_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'h5FDF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout ) # (((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h00C0; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ixy_d~3_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal21~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88C0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|db_low[3]~5_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h5540; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N5 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( +// Equation(s): +// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [3])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hF351; +defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( +// Equation(s): +// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_low[3]~3_combout ), + .datad(\z80_|alu_|result_lo [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hF0A0; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_out_lo~9_combout & (\z80_|execute_|ctl_inc_cy~29_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~35_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~24_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~24 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_sel_wz~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout = (\z80_|execute_|ctl_mRead~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~25_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~24_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~25 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_sw_4u~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ctl_inc_cy~80_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~80_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout & (\z80_|execute_|ctl_inc_cy~79_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout & \z80_|execute_|ctl_inc_cy~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal4~0_combout & \z80_|sequencer_|DFFE_T5_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_inc_cy~72_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_inc_cy~72_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|execute_|ctl_inc_cy~44_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~73_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|ctl_inc_cy~44_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_bus_inc_oe~36_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (!\z80_|execute_|ctl_sw_4u~2_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~17_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~25_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~16_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'hF4F4; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (\z80_|execute_|ctl_reg_sel_pc~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ixy_d~16_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~22_combout = (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~22 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_pc~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_reg_sel_pc~8_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~22_combout & \z80_|execute_|ctl_reg_sel_pc~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sel_pc~11_combout & (\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & \z80_|execute_|ctl_inc_cy~35_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal21~1_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h0303; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0011; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|ixy_d~8_combout & (!\z80_|pla_decode_|Equal33~2_combout & ((!\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0105; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|pc_inc_hold~16_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~20_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_reg_sel_pc~16_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~20 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_bus_inc_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~21_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|ctl_bus_inc_oe~20_combout & !\z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~21 .lut_mask = 16'h0A8A; +defparam \z80_|execute_|ctl_bus_inc_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hF0C0; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~18_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEC00; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~19_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~19 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_bus_inc_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~19_combout & \z80_|execute_|ixy_d~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~4_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~20_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) # (!\z80_|execute_|ctl_reg_in_hi~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~11_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|ctl_reg_sel_pc~13_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (\z80_|execute_|setM1~55_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~16_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~6_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|ctl_reg_sys_hilo~6_combout ) # ((!\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3310; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal35~0_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'h0055; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~8_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # ((!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_inc_dec~3_combout & +// (!\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'h8ACF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h5100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~17_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h3B00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((\z80_|execute_|ctl_al_we~3_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h00A2; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_pc~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|execute_|ctl_reg_sel_wz~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~30_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~30 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_reg_sel_wz~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (!\z80_|execute_|ctl_reg_sel_wz~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (((!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout )) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFAFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~7_combout )) # (!\z80_|execute_|setM1~48_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_al_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~8_combout = ((\z80_|execute_|ctl_sw_4d~2_combout ) # ((\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_state_alu~3_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~8 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hBF00; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = (\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'h8C8C; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = (!\z80_|execute_|ctl_mWrite~8_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'h3233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~17_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~19_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~17 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_bus_inc_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~18_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_bus_inc_oe~38_combout & \z80_|execute_|ctl_bus_inc_oe~17_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~25_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~26_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~18_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~27_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = ((\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~36_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~22_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~22 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~23_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~23 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~73_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_inc_cy~44_combout & \z80_|execute_|ctl_inc_cy~74_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~24_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_bus_inc_oe~32_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~3_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # (\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [11]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = ((\z80_|reg_file_|db_hi_as[3]~9_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = (\z80_|execute_|ctl_alu_oe~17_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~2_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|pla_decode_|Equal25~0_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h00BF; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~17_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~17 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (!\z80_|pla_decode_|Equal49~0_combout & (!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|execute_|ctl_mRead~11_combout )) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_sw_1d~7_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & \z80_|execute_|ctl_reg_gp_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mRead~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~14_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (!\z80_|execute_|ctl_66_oe~4_combout & !\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~14 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_in_hi~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~15_combout = ((\z80_|execute_|ctl_reg_in_hi~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~15 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_in_hi~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )))) # (!\z80_|execute_|setM1~32_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ctl_al_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8FAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~7_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h3F2F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & ((\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|comb~1_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|comb~1_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~4_combout )) # +// (!\z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|execute_|fMRead~9_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~11_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ))) + + .dataa(\z80_|execute_|fMRead~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|fMRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|setM1~58_combout & \z80_|execute_|ctl_sw_2u~3_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|setM1~58_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (!\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'h00BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = (((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) # (!\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~3_combout = (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal1~2_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~3_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~4_combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~4 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & \z80_|execute_|ctl_sw_2u~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h000E; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~43_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~27_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .lut_mask = 16'h8DCD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~28_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_reg_gp_sel[1]~27_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_reg_use_sp~2_combout & \z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datad(\z80_|execute_|nextM~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~43_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~28_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & \z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~41_combout = (\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h8F88; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # (\z80_|pla_decode_|Equal5~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal5~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ))) # (!\z80_|execute_|ctl_alu_op_low~16_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|ir_|opcode [5]))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~38_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|execute_|ctl_mRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~39_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout )) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~37_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .lut_mask = 16'h08AA; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~40_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~37_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h5455; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hD800; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~6_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N11 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hE400; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0A0A; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_in_hi~6_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~23_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~20_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~23 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~29_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~21_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~29 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_sel_wz~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~26_combout = (\z80_|execute_|ctl_reg_sel_wz~23_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~25_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~22_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~26 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & !\z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0008; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFEFC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~15_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|gdfx_temp1[3]~31_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hA0A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~33_combout & (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~37_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'hC040; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~10_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & ((\z80_|alu_|db_low[3]~5_combout ) # ((!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_|db_low[3]~5_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~16_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (!\z80_|execute_|fMRead~27_combout ))) # (!\z80_|execute_|ctl_flags_bus~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~13_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~7_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout & +// (\z80_|alu_|db_low[3]~5_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N13 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~32 ( +// Equation(s): +// \z80_|alu_control_|db[3]~32_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (!\z80_|execute_|ctl_66_oe~combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~32 .lut_mask = 16'h1101; +defparam \z80_|alu_control_|db[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|db[3]~32_combout & ((\z80_|bus_control_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|alu_control_|db[3]~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hD0D0; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~18_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|pc_inc_hold~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mWrite~10_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0800; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ixy_d~16_combout ) # (\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hECA8; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~3_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hEAFA; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~20_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~21_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'h777F; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hABFF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (\z80_|execute_|pc_inc_hold~37_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|pc_inc_hold~37_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~27_combout & \z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout ))) # (!\z80_|execute_|ctl_inc_cy~78_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~64_combout & \z80_|execute_|ctl_inc_cy~65_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_mWrite~18_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~3_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = ((\z80_|execute_|ctl_inc_dec~6_combout ) # ((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~0_combout ))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'hDDFD; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_alu_oe~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~32_combout & \z80_|execute_|pc_inc_hold~28_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_inc_cy~69_combout & ((!\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~36_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~67_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFF2A; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (((!\z80_|execute_|ctl_inc_cy~33_combout ) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~28_combout )) # (!\z80_|execute_|ctl_inc_cy~29_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~29_combout ), + .datab(\z80_|execute_|ctl_inc_cy~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~36_combout ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((\z80_|execute_|ctl_inc_cy~71_combout ) # (!\z80_|execute_|ctl_inc_cy~74_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~32_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~75_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hEFCC; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (!\z80_|execute_|ctl_inc_cy~81_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|pc_inc_hold~38_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0A08; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & +// (\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_inc_cy~79_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_inc_cy~42_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~42_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~44_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~30_combout = ((!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~8_combout ))) # (!\z80_|execute_|ctl_mWrite~18_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & (!\z80_|execute_|pc_inc_hold~29_combout +// & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|ctl_inc_cy~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hB0BB; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (!\z80_|execute_|ctl_inc_cy~34_combout & (((\z80_|execute_|pc_inc_hold~19_combout & !\z80_|execute_|pc_inc_hold~23_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0545; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~48_combout ) # ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # (\z80_|execute_|ctl_inc_cy~47_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~48_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~46_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & (!\z80_|execute_|pc_inc_hold~20_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|execute_|ctl_inc_cy~60_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~20_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_mRead~34_combout & +// \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~9_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (!\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|execute_|ctl_inc_cy~56_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_inc_cy~57_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~57_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~20_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~21_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~8_combout & !\z80_|execute_|pc_inc_hold~20_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h888C; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|execute_|pc_inc_hold~31_combout & \z80_|execute_|ctl_mRead~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~31_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((\z80_|execute_|ctl_inc_cy~58_combout ) # (\z80_|execute_|ctl_inc_cy~53_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|ctl_inc_cy~61_combout ), + .datac(\z80_|execute_|ctl_inc_cy~58_combout ), + .datad(\z80_|execute_|ctl_inc_cy~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~77_combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # ((!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hC4F5; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((!\z80_|execute_|pc_inc_hold~30_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~27_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~30_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~78_combout & \z80_|execute_|pc_inc_hold~28_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((\z80_|execute_|ctl_inc_cy~39_combout ) # (\z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_inc_cy~62_combout ), + .datac(\z80_|execute_|ctl_inc_cy~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_inc_cy~76_combout ) # +// (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~66_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hCCC8; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|address_latch_|Q[3]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[3]~feeder_combout = \z80_|address_latch_|abusz [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = ((\z80_|execute_|ctl_inc_dec~7_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout = (\z80_|execute_|setM1~51_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|execute_|setM1~51_combout & (((\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout +// & \z80_|execute_|rsel0~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mWrite~18_combout ) # (\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hF4F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h006A; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ctl_mRead~23_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_ir_we~18_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~18_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|pla_decode_|Equal25~0_combout & (!\z80_|pla_decode_|Equal12~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (((\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h00C8; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_mRead~3_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~21_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'h8888; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[2]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~40_combout & (\z80_|reg_file_|gdfx_temp0[2]~36_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~38_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~41_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~43_combout = ((\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[2]~43_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~33_combout ) # ((\z80_|execute_|ctl_sw_4d~8_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_sw_4d~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|gdfx_temp0[1]~27_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~26_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~31_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~33_combout = ((\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[1]~33_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datac(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ +// (\z80_|address_latch_|Q [1]))))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N13 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [2]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [1]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h6666; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~13_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[3]~63_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~14_combout = (\z80_|reg_file_|db_lo_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~14 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~15_combout = ((\z80_|reg_file_|db_lo_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~15 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~57_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~35_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~58_combout = (\z80_|reg_file_|gdfx_temp0[3]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~59_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~61_combout = (\z80_|reg_file_|gdfx_temp0[3]~58_combout & (\z80_|reg_file_|gdfx_temp0[3]~60_combout & (\z80_|reg_file_|gdfx_temp0[3]~59_combout & \z80_|reg_file_|gdfx_temp0[3]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~62_combout = (\z80_|reg_file_|gdfx_temp0[3]~55_combout & (\z80_|reg_file_|gdfx_temp0[3]~61_combout & \z80_|reg_file_|gdfx_temp0[3]~54_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~63_combout = ((\z80_|reg_file_|gdfx_temp0[3]~62_combout & ((\z80_|reg_file_|db_lo_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & ((\z80_|reg_file_|gdfx_temp0[3]~63_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8A8A; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hB3BB; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[3]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~16_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~16_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~8_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~4_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|alu_control_|db[1]~22_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = (\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N31 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [3]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~67_combout = (\z80_|reg_file_|gdfx_temp0[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~65_combout = (\z80_|reg_file_|gdfx_temp0[4]~64_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~70_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~71_combout = (\z80_|reg_file_|gdfx_temp0[4]~70_combout & (\z80_|reg_file_|gdfx_temp0[4]~69_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .lut_mask = 16'h8A00; +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~72_combout = (\z80_|reg_file_|gdfx_temp0[4]~68_combout & (\z80_|reg_file_|gdfx_temp0[4]~67_combout & (\z80_|reg_file_|gdfx_temp0[4]~65_combout & \z80_|reg_file_|gdfx_temp0[4]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~73_combout = ((\z80_|reg_file_|gdfx_temp0[4]~72_combout & ((\z80_|reg_file_|db_lo_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~16_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~17_combout = (\z80_|reg_file_|db_lo_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~17 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~18_combout = ((\z80_|reg_file_|db_lo_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~18 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N15 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~49_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_high[2]~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N3 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = ((!\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|db_low[1]~15_combout & (\z80_|alu_|db_low[1]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hB030; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|execute_|ctl_alu_core_S~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|ir_|opcode [4]) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|execute_|ctl_alu_op_low~33_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~9_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|pla_decode_|Equal73~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (\z80_|execute_|ctl_state_alu~11_combout & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|execute_|ctl_state_alu~11_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'hCC40; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal73~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hA080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~20 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~20_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~20 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~20_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h0515; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|execute_|ctl_flags_cf_cpl~0_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & !\z80_|execute_|ctl_flags_cf_cpl~1_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[0]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h3336; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDD5D; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~25_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|gdfx_temp0[0]~17_combout & \z80_|reg_file_|gdfx_temp0[0]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~23_combout = ((\z80_|reg_file_|gdfx_temp0[0]~18_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[0]~4_combout = (\z80_|reg_file_|gdfx_temp0[0]~23_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[0]~4 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~23 ( +// Equation(s): +// \z80_|alu_control_|db[0]~23_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~8_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~18_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~23 .lut_mask = 16'hF500; +defparam \z80_|alu_control_|db[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[0]~12_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~24 ( +// Equation(s): +// \z80_|alu_control_|db[0]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_cf~combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0])) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~24 .lut_mask = 16'hF531; +defparam \z80_|alu_control_|db[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~25 ( +// Equation(s): +// \z80_|alu_control_|db[0]~25_combout = ((\z80_|reg_file_|db_lo_ds[0]~4_combout & (\z80_|alu_control_|db[0]~23_combout & \z80_|alu_control_|db[0]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .datab(\z80_|alu_control_|db[0]~23_combout ), + .datac(\z80_|alu_control_|db[0]~24_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~25 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_control_|db[0]~25_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # +// (!\z80_|alu_control_|db[0]~25_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[0]~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )) # (!\z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout = (\z80_|execute_|ixy_d~14_combout & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~0_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ) # ((\z80_|execute_|ctl_flags_cf2_we~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~9_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|ir_|opcode [6] & (\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout & !\z80_|ir_|opcode [7]))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'hFFE0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [7] & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[7]~20_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|alu_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~81_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~82_combout = (\z80_|reg_file_|gdfx_temp1[7]~79_combout & (\z80_|reg_file_|gdfx_temp1[7]~80_combout & (\z80_|reg_file_|gdfx_temp1[7]~81_combout & \z80_|reg_file_|gdfx_temp1[7]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~83_combout = (\z80_|reg_file_|gdfx_temp1[7]~77_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout & (\z80_|reg_file_|gdfx_temp1[7]~82_combout & \z80_|reg_file_|gdfx_temp1[7]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~23 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~24_combout = (\z80_|reg_file_|db_hi_as[7]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~24 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_hi_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~25_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [14]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~25 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~25_combout = ((\z80_|reg_file_|db_hi_as[7]~24_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~25 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~84_combout = ((\z80_|reg_file_|gdfx_temp1[7]~83_combout & ((\z80_|reg_file_|db_hi_as[7]~25_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & ((\z80_|alu_control_|db[7]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|alu_control_|db[7]~15_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~19_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # +// (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h5432; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hFE04; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8030; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_flags_alu~20_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hF2F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_core_S~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (((!\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # (((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBBB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout & +// \z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & !\z80_|pla_decode_|Equal71~2_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h2F3F; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|execute_|ctl_flags_nf_we~2_combout ) # ((!\z80_|execute_|ctl_flags_nf_we~1_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hEEEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_control_|db[1]~22_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~18_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h10F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0E0E; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h7773; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((\z80_|pla_decode_|Equal68~2_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hCC08; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal71~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~8_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal21~1_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout )))) # +// (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (((\z80_|execute_|ctl_alu_op_low~30_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((\z80_|execute_|ctl_alu_core_hf~21_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ixy_d~5_combout & ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_core_hf~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0302; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mWrite~10_combout & !\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hCC0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout ))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((!\z80_|execute_|ctl_alu_op_low~21_combout & \z80_|execute_|ctl_alu_core_hf~32_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((!\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_core_hf~40_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(gnd), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hF0CC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[0]~25_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N19 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N7 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hC0A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0E0A; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~34_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hB2E8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|pla_decode_|Equal71~2_combout ) # (\z80_|execute_|ctl_alu_core_S~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal71~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hAAAF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~17_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[1]~17_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N29 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|alu_|op2_high [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~1_combout & \z80_|alu_|alu_op1[1]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op1[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op2[1]~1_combout )))) # (!\z80_|alu_|alu_op1[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[1]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hCE8C; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'h0088; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|alu_|db[4]~10_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[4]~10_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~60_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & \z80_|reg_file_|gdfx_temp1[4]~61_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout & \z80_|reg_file_|gdfx_temp1[4]~58_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~19_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[4]~66_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = (\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~19_combout = ((\z80_|reg_file_|db_hi_as[4]~18_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~19 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~19_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout = \z80_|address_latch_|Q [12] $ ((((\z80_|execute_|ctl_inc_dec~11_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .lut_mask = 16'h02FD; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~16_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N5 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout = \z80_|address_latch_|Q [11] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # ((\z80_|execute_|ctl_inc_dec~11_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .lut_mask = 16'h1E0F; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = (\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~16_combout = ((\z80_|reg_file_|db_hi_as[5]~15_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~16 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~52_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~53_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout ) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout & \z80_|reg_file_|gdfx_temp1[5]~50_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~16_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// (((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_control_|db[5]~12_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[5]~23_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[1]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[5]~24_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~16_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[1]~16_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[1]~17_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N5 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA280; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h5051; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|pla_decode_|Equal71~2_combout ) # ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) # +// (!\z80_|execute_|ctl_alu_core_S~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal71~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'h45C7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .lut_mask = 16'hFF88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N27 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hC088; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~11_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[2]~11_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N11 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( +// Equation(s): +// \z80_|alu_|db_low[2]~6_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [2])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( +// Equation(s): +// \z80_|alu_|db_low[2]~7_combout = (\z80_|alu_|db_low[2]~6_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[2]~6_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( +// Equation(s): +// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'hFA00; +defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~16_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|gdfx_temp1[2]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = (\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~13_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N9 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (\z80_|address_latch_|Q [7] & !\z80_|execute_|ctl_inc_dec~10_combout +// )) # (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [7] & \z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1080; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~13_combout = ((\z80_|reg_file_|db_hi_as[2]~12_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~13 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~43_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~44_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout & (\z80_|reg_file_|gdfx_temp1[2]~41_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & \z80_|reg_file_|gdfx_temp1[2]~46_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~13_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~11_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[2]~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[2]~9_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|alu_|db_low[2]~9_combout ), + .datac(gnd), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hDD88; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = ((\z80_|alu_|db_low[2]~8_combout & ((\z80_|alu_|db_low[2]~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~8_combout ), + .datad(\z80_|alu_|db_low[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hF373; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[2]~13_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N27 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|alu_|op1_high [0]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~12_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|alu_control_|db[5]~12_combout +// & (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[5]~12_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~8 ( +// Equation(s): +// \z80_|alu_control_|db[5]~8_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|flags_yf~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~8 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[5]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[5]~0_combout = (\z80_|reg_file_|gdfx_temp0[5]~53_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[5]~0 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~9 ( +// Equation(s): +// \z80_|alu_control_|db[5]~9_combout = (\z80_|alu_control_|db[5]~8_combout & (\z80_|reg_file_|db_lo_ds[5]~0_combout & ((\z80_|bus_control_|db[5]~16_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|alu_control_|db[5]~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~9 .lut_mask = 16'hD000; +defparam \z80_|alu_control_|db[5]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~12 ( +// Equation(s): +// \z80_|alu_control_|db[5]~12_combout = ((\z80_|alu_control_|db[5]~9_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[5]~9_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~12 .lut_mask = 16'hBB3B; +defparam \z80_|alu_control_|db[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~47_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~48_combout = (\z80_|reg_file_|gdfx_temp0[5]~47_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~51_combout = (\z80_|reg_file_|gdfx_temp0[5]~49_combout & (\z80_|reg_file_|gdfx_temp0[5]~48_combout & (\z80_|reg_file_|gdfx_temp0[5]~50_combout & \z80_|reg_file_|gdfx_temp0[5]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~52_combout = (\z80_|reg_file_|gdfx_temp0[5]~44_combout & (\z80_|reg_file_|gdfx_temp0[5]~51_combout & \z80_|reg_file_|gdfx_temp0[5]~45_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~53_combout = ((\z80_|reg_file_|gdfx_temp0[5]~52_combout & ((\z80_|reg_file_|db_lo_as[5]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~10_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[5]~53_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~11_combout = (\z80_|reg_file_|db_lo_as[5]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~11 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~12_combout = ((\z80_|reg_file_|db_lo_as[5]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~12 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h6555; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~26_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[6]~82_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3393; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N9 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0DD0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~89_combout & (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[7]~92_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [7]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h9A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~7_combout = ((\z80_|reg_file_|db_hi_as[0]~6_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~7 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [0] & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[0]~18_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datac(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'hD000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~7_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datac(\z80_|alu_control_|db[0]~25_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[1]~12_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[1]~16_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hBBF3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = ((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hAF0F; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[1]~15_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hC4FF; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [5] & ((\z80_|alu_|db[0]~18_combout ))))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout +// & (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'h8E82; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'h08A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~3 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout & !\z80_|ir_|opcode [4])) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .lut_mask = 16'hFF0C; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[0]~18_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[0]~18_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h396C; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h555F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_|alu_op2[0]~3_combout )))) +// # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|alu_op2[0]~3_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|alu_op1[0]~1_combout ), + .datac(\z80_|alu_|alu_op2[0]~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hFE80; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N9 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = ((!\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|alu_|op1_low [0] & (((\z80_|alu_|op2_low [0])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [0] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|alu_|db_low[0]~20_combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|result_lo [0]), + .datac(\z80_|alu_|db_low[0]~20_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hE000; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((\z80_|alu_|db_low[0]~19_combout & \z80_|alu_|db_low[0]~22_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hCF0F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N27 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[0]~20_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[4]~10_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[0]~20_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hF7B3; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'h0022; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~22_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[0]~22_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|alu_control_|db[4]~31_combout & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|alu_control_|db[4]~31_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db[4]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( +// Equation(s): +// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( +// Equation(s): +// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db_low[3]~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hF5DD; +defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|alu_|db_low[3]~4_combout & \z80_|alu_|db_low[3]~1_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|alu_|db_low[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hF333; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[3]~7_combout & (\z80_|alu_|db_low[3]~5_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N25 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h27D8; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [3]))))) # +// (!\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|alu_|op1_low [3])) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hCCE4; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFC0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF3F2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~31_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~31_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFCB8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( +// Equation(s): +// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~26 ( +// Equation(s): +// \z80_|alu_control_|db[2]~26_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~26 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~5_combout = (\z80_|reg_file_|gdfx_temp0[2]~43_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~5 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_control_|db[2]~26_combout & (\z80_|reg_file_|db_lo_ds[2]~5_combout & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[2]~26_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = ((\z80_|alu_control_|db[2]~27_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~8_combout & (((\z80_|alu_control_|db[2]~28_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|execute_|ctl_flags_pf_we~8_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hE444; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h0770; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & (!\z80_|pla_decode_|Equal62~3_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h0CFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [6]))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|Q [6]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & (\z80_|address_latch_|Q [0] & !\z80_|address_latch_|Q [3]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0010; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [10] & !\z80_|address_latch_|Q [9]))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|Q [9]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [14] & !\z80_|address_latch_|Q [12]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~7_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~7_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE4F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80A2; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h80B0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|alu_|alu_parity_out~0_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h555A; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_pf_we~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hEAAA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h7F00; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hFCFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[1]~19_combout & !\z80_|alu_|db_high[2]~13_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~18_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hCC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~5_combout & (!\z80_|alu_|db_low[2]~11_combout & (!\z80_|alu_|db_low[1]~17_combout & !\z80_|alu_|db_low[0]~23_combout ))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|alu_|db_low[2]~11_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .lut_mask = 16'hF8F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hDF00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & (((\z80_|alu_control_|sel[1]~0_combout ) # (\z80_|alu_flags_|flags_cf~combout )))) # (!\z80_|ir_|opcode [4] & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAEA4; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~28_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|pla_decode_|Equal5~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = (\z80_|execute_|ctl_reg_sel_wz~16_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h3FBF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_bus_inc_oe~19_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~23_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~23 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sel_pc~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (!\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hCCDF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~21_combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~21 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_sel_pc~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~28_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_reg_sel_pc~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [1] & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~2_combout = (\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datad(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~2 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~4_combout = ((\z80_|reg_file_|db_hi_as[1]~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~4 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~10_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~10_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [14]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = (\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = ((\z80_|reg_file_|db_hi_as[6]~21_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~71_combout & \z80_|reg_file_|gdfx_temp1[6]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|gdfx_temp1[6]~68_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~22_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|alu_control_|db[6]~18_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[6]~21_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|alu_|op2_high [2] & (((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~11_combout & (((\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'h8C0C; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|execute_|ctl_alu_res_oe~2_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hFFF8; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~12_combout & \z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[2]~11_combout ))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0415; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hF0FB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # +// (\z80_|alu_|alu_op1[3]~2_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFD40; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [3]) +// # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hEF2F; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[3]~5_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFD55; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_control_|db[7]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & \z80_|alu_|db_high[3]~7_combout )))) # (!\z80_|alu_control_|db[7]~15_combout & +// (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_control_|db[7]~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~13 ( +// Equation(s): +// \z80_|alu_control_|db[7]~13_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~13 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_out_lo~3_combout & !\z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF08; +defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~14 ( +// Equation(s): +// \z80_|alu_control_|db[7]~14_combout = (\z80_|alu_control_|db[7]~13_combout & (\z80_|reg_file_|db_lo_ds[7]~1_combout & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[7]~13_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~14 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~15 ( +// Equation(s): +// \z80_|alu_control_|db[7]~15_combout = ((\z80_|alu_control_|db[7]~14_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[7]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~15 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~4 ( +// Equation(s): +// \z80_|bus_control_|db[7]~4_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~4 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~2_combout & \z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|fMRead~27_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~27_combout ), + .datac(\z80_|execute_|ixy_d~2_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|fMRead~36_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - .dataa(\z80_|execute_|fMRead~35_combout ), - .datab(\z80_|execute_|fMRead~34_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'h0A08; defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N30 +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~16 ( +// Equation(s): +// \z80_|execute_|nextM~16_combout = (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|nextM~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|nextM~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~20_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~20 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~20_combout & (((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) # (!\z80_|execute_|ctl_ir_we~20_combout & (\z80_|execute_|ctl_ir_we~19_combout & ((\z80_|ir_|opcode [7])))) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|execute_|ctl_ir_we~20_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~38 ( +// Equation(s): +// \z80_|execute_|fMRead~38_combout = (\z80_|execute_|fMRead~29_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|fMRead~30_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~38 .lut_mask = 16'hECCC; +defparam \z80_|execute_|fMRead~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = ((\z80_|execute_|fMRead~37_combout ) # ((\z80_|execute_|fMRead~38_combout ) # (!\z80_|execute_|nextM~16_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~37_combout ), + .datac(\z80_|execute_|nextM~16_combout ), + .datad(\z80_|execute_|fMRead~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~36_combout ) # (\z80_|execute_|fMRead~31_combout ))) # (!\z80_|execute_|fMRead~8_combout ) + + .dataa(\z80_|execute_|fMRead~8_combout ), + .datab(\z80_|execute_|fMRead~28_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|fMRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (!\z80_|execute_|fMWrite~0_combout & ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|fMRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ixy_d~16_combout )) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|fMRead~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|fMRead~13_combout ))) + + .dataa(\z80_|execute_|fMRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|fMRead~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~14_combout ) # ((\z80_|execute_|fMRead~17_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|fMRead~18_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) # (!\z80_|execute_|fMRead~22_combout ) + + .dataa(\z80_|execute_|fMRead~22_combout ), + .datab(\z80_|execute_|fMRead~18_combout ), + .datac(\z80_|execute_|ctl_sw_4d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|execute_|ctl_mRead~15_combout & +// ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~25_combout ) # (((!\z80_|execute_|pc_inc_hold~17_combout & \z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|fMRead~25_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|fMWrite~2_combout ) + + .dataa(\z80_|execute_|fMWrite~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|ctl_reg_sys_hilo~6_combout ))) + + .dataa(\z80_|execute_|fMRead~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|fMRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~35_combout )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), @@ -44338,1712 +39032,1971 @@ defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~6_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~2_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|execute_|ixy_d~2_combout ), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hF500; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) +// \z80_|execute_|ctl_iorw~12_combout = ((\z80_|ir_|opcode [7]) # ((!\z80_|ir_|opcode [6]) # (!\z80_|decode_state_|DFFE_instED~q ))) # (!\z80_|pla_decode_|Equal1~0_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .combout(\z80_|execute_|ctl_iorw~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~2_combout ) # ((!\z80_|execute_|ctl_iorw~12_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (!\z80_|execute_|ctl_iorw~12_combout & ((\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .combout(\z80_|execute_|ctl_iorw~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( // Equation(s): -// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~16_combout ) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .dataa(\z80_|execute_|nextM~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_iorw~8_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .combout(\z80_|execute_|ctl_iorw~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; -defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[4][3] ( +// Location: FF_X30_Y18_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N12 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\ula_|zx_keyboard_|keys[5][3]~q ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][3]~q ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hA2F3; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & -// !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; -defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; -defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & -// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N23 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N25 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N20 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[3][3]~q ), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'h8ACF; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; -defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; -defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & -// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N5 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N30 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hCF45; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N8 -cycloneive_lcell_comb \D[3]~72 ( -// Equation(s): -// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][3]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][3]~q ), - .cin(gnd), - .combout(\D[3]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'hA2F3; -defparam \D[3]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) - - .dataa(\D[3]~74_combout ), - .datab(\D[3]~73_combout ), - .datac(\D[3]~75_combout ), - .datad(\D[3]~72_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'h8000; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N2 -cycloneive_lcell_comb \D[3]~122 ( -// Equation(s): -// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[3]~76_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[3]~122_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~122 .lut_mask = 16'hEF00; -defparam \D[3]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N28 -cycloneive_lcell_comb \D[3]~79 ( -// Equation(s): -// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~79 .lut_mask = 16'h3332; -defparam \D[3]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N20 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # -// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hF5E4; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N22 -cycloneive_lcell_comb \D[3]~80 ( -// Equation(s): -// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) - - .dataa(gnd), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~80 .lut_mask = 16'hCFC0; -defparam \D[3]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N4 -cycloneive_lcell_comb \D[3]~81 ( -// Equation(s): -// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout -// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\D[3]~80_combout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~81 .lut_mask = 16'hF0DD; -defparam \D[3]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N30 -cycloneive_lcell_comb \D[3]~124 ( -// Equation(s): -// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~124_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~124 .lut_mask = 16'hF200; -defparam \D[3]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N0 -cycloneive_lcell_comb \D[3]~123 ( -// Equation(s): -// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~123_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~123 .lut_mask = 16'hF2D0; -defparam \D[3]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N10 -cycloneive_lcell_comb \D[3]~78 ( -// Equation(s): -// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - - .dataa(\Equal2~0_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[3]~124_combout ), - .datad(\D[3]~123_combout ), - .cin(gnd), - .combout(\D[3]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~78 .lut_mask = 16'h5410; -defparam \D[3]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N6 -cycloneive_lcell_comb \D[3]~82 ( -// Equation(s): -// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[3]~79_combout ), - .datac(\D[3]~81_combout ), - .datad(\D[3]~78_combout ), - .cin(gnd), - .combout(\D[3]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~82 .lut_mask = 16'hD580; -defparam \D[3]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N26 -cycloneive_lcell_comb \D[3]~108 ( -// Equation(s): -// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[3]~122_combout ), - .datac(gnd), - .datad(\D[3]~82_combout ), - .cin(gnd), - .combout(\D[3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hFFDD; -defparam \D[3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N8 -cycloneive_lcell_comb \D[3]~109 ( -// Equation(s): -// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(\D[3]~108_combout ), - .datad(\Equal2~1_combout ), - .cin(gnd), - .combout(\D[3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~109 .lut_mask = 16'hD0D5; -defparam \D[3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[3]~109_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N5 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|alu_control_|db[3]~36_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|execute_|ctl_iorw~9_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y8_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X30_Y18_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y1_N0 +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N27 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y18_N15 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(\z80_|memory_ifc_|wait_iorq~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~13_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout & (\z80_|execute_|ctl_mWrite~14_combout & (\z80_|execute_|ctl_mWrite~12_combout & \z80_|execute_|ctl_bus_db_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = (!\z80_|execute_|ixy_d~8_combout & !\z80_|pla_decode_|Equal33~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h0303; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = ((\z80_|execute_|ctl_mWrite~16_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~15_combout ))) # (!\z80_|execute_|ctl_mWrite~15_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y15_N21 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N3 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(gnd), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|mwr_wr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFFA0; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFF0; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # ((\z80_|sequencer_|M5~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # +// (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_mWrite~8_combout & !\z80_|execute_|ctl_mRead~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0055; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~0_combout ) # ((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|fMWrite~1_combout )))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h2322; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & ((\z80_|execute_|fMWrite~2_combout ) # (!\z80_|execute_|fMWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hA200; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~6_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((\z80_|execute_|ixy_d~2_combout ) # ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~2_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h8CCC; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_alu_oe~4_combout ) # ((\z80_|execute_|ctl_reg_in_hi~6_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|pla_decode_|Equal9~1_combout & +// ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|pla_decode_|Equal3~2_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h10F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h070F; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout & \z80_|execute_|fMRead~6_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout )) # +// (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h1F13; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fIOWrite~0_combout ) # ((!\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|execute_|fMWrite~5_combout & (\z80_|execute_|fMWrite~6_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'hC8FA; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~9_combout & (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~11_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_bus_inc_oe~18_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~13_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h40C0; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|execute_|ctl_inc_cy~31_combout & (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # +// (!\z80_|execute_|fIOWrite~5_combout & (((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h88F8; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hFF40; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N17 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N17 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \Equal5~0 ( +// Equation(s): +// \Equal5~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~0 .lut_mask = 16'h0080; +defparam \Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~18_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|address_latch_|abusz [1]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h00DD; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~35_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h44F4; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N10 +cycloneive_lcell_comb \Equal3~0 ( +// Equation(s): +// \Equal3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((!\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|address_pins_|DFFE_apin_latch [1])) # (!\z80_|address_pins_|DFFE_apin_latch [0]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~0 .lut_mask = 16'h2AAA; +defparam \Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [6]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[6]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~26 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N16 +cycloneive_lcell_comb \Equal3~1 ( +// Equation(s): +// \Equal3~1_combout = (((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|address_pins_|DFFE_apin_latch [4])) # (!\z80_|address_pins_|DFFE_apin_latch [3]) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~1 .lut_mask = 16'hF7FF; +defparam \Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N0 +cycloneive_lcell_comb \Equal3~2 ( +// Equation(s): +// \Equal3~2_combout = (\Equal3~0_combout ) # ((\z80_|address_pins_|abus[6]~25_combout ) # ((\z80_|address_pins_|abus[7]~26_combout ) # (\Equal3~1_combout ))) + + .dataa(\Equal3~0_combout ), + .datab(\z80_|address_pins_|abus[6]~25_combout ), + .datac(\z80_|address_pins_|abus[7]~26_combout ), + .datad(\Equal3~1_combout ), + .cin(gnd), + .combout(\Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~2 .lut_mask = 16'hFFFE; +defparam \Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \D[5]~26 ( +// Equation(s): +// \D[5]~26_combout = (\Equal5~1_combout & ((!\Equal3~2_combout ) # (!\Equal5~0_combout ))) + + .dataa(\Equal5~1_combout ), + .datab(gnd), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\D[5]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~26 .lut_mask = 16'h0AAA; +defparam \D[5]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [15])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [15]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~23 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[15]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h1000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~24 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~27 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~28 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[3]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~30 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[5]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~17 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[8]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~16 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|address_latch_|abusz [10]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [11]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~18 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -46059,10 +41012,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46100,7 +41053,170 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: FF_X21_Y15_N25 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N23 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0088; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -46116,10 +41232,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46157,7 +41273,96 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: LCCOMB_X29_Y12_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~20_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~22_combout & \z80_|address_pins_|abus[15]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -46173,10 +41378,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46214,10 +41419,10 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) @@ -46226,52 +41431,776 @@ cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .lut_mask = 16'hBBC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N2 -cycloneive_lcell_comb \D[5]~97 ( +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( // Equation(s): -// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\D[5]~97_combout ), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[5]~97 .lut_mask = 16'h2000; -defparam \D[5]~97 .sum_lutc_input = "datac"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), +// Location: FF_X31_Y22_N13 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N29 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (!\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0400; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N29 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N11 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N27 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N17 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h9933; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N19 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] $ (VCC))) # (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0])) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N1 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N5 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(\ula_|video_|Add4~12_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N19 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & ((\ula_|video_|Add4~4_combout )))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vram_address[10]~2_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|Add4~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N25 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~12_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFAA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N31 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -46279,16 +42208,181 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hD9C8; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -46342,283 +42436,111 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N6 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \Selector0~1 ( // Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # (!\Selector0~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\Selector0~0_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector0~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hB9A8; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector0~1 .lut_mask = 16'hF838; +defparam \Selector0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N4 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \D[7]~36 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \D[7]~36_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector0~1_combout ))))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), + .datad(\Selector0~1_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\D[7]~36_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \D[7]~36 .lut_mask = 16'h5140; +defparam \D[7]~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N20 -cycloneive_lcell_comb \D[7]~116 ( +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \D[7]~37 ( // Equation(s): -// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) +// \D[7]~37_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~36_combout ) # (!\D[5]~26_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~36_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datab(\D[5]~97_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~116_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~116 .lut_mask = 16'hBFB3; -defparam \D[7]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N26 -cycloneive_lcell_comb \D[7]~117 ( -// Equation(s): -// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), + .dataa(\z80_|data_pins_|dout [7]), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [7]), - .datad(\D[7]~116_combout ), + .datac(\D[5]~26_combout ), + .datad(\D[7]~36_combout ), .cin(gnd), - .combout(\D[7]~117_combout ), + .combout(\D[7]~37_combout ), .cout()); // synopsys translate_off -defparam \D[7]~117 .lut_mask = 16'hF311; -defparam \D[7]~117 .sum_lutc_input = "datac"; +defparam \D[7]~37 .lut_mask = 16'hBB0B; +defparam \D[7]~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N0 +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \D[7]~48 ( +// Equation(s): +// \D[7]~48_combout = (\D[7]~37_combout ) # (!\D[0]~49_combout ) + + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), + .cin(gnd), + .combout(\D[7]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~48 .lut_mask = 16'hFF33; +defparam \D[7]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~48_combout )))) # (!\z80_|bus_control_|db[7]~6_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~48_combout )))) - .dataa(\z80_|bus_control_|db[7]~7_combout ), + .dataa(\z80_|bus_control_|db[7]~6_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[7]~117_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[7]~48_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N1 +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFF8; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 dffeas \z80_|data_pins_|dout[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), @@ -46637,33 +42559,33 @@ defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~6 ( // Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[7]~6_combout = ((\z80_|bus_control_|db[7]~4_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[7]~5_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[7]~4_combout ), .datad(\z80_|data_pins_|dout [7]), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), + .combout(\z80_|bus_control_|db[7]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[7]~6 .lut_mask = 16'hF575; +defparam \z80_|bus_control_|db[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N13 +// Location: FF_X29_Y17_N3 dffeas \z80_|ir_|opcode[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|bus_control_|db[7]~6_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [7]), @@ -46673,93 +42595,3266 @@ defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & \z80_|ir_|opcode [6])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~0_combout & (\z80_|execute_|ctl_mWrite~7_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((!\z80_|execute_|fIOWrite~0_combout & \z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|fIORead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~6_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~5_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0500; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~59 ( +// Equation(s): +// \z80_|execute_|setM1~59_combout = (!\z80_|execute_|ctl_mRead~11_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~59 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & (\z80_|execute_|setM1~39_combout & (!\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|setM1~59_combout ))) + + .dataa(\z80_|execute_|setM1~40_combout ), + .datab(\z80_|execute_|setM1~39_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|setM1~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0800; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_mRead~22_combout & \z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFFC0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~29_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (!\z80_|execute_|ctl_mRead~27_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ctl_mRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y17_N21 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: FF_X32_Y15_N9 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N27 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \Equal5~1 ( +// Equation(s): +// \Equal5~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~1 .lut_mask = 16'h0808; +defparam \Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \Selector10~0 ( +// Equation(s): +// \Selector10~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~0 .lut_mask = 16'hD9C8; +defparam \Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \Selector10~1 ( +// Equation(s): +// \Selector10~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector10~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector10~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector10~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\Selector10~0_combout ), + .cin(gnd), + .combout(\Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~1 .lut_mask = 16'hBBC0; +defparam \Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y29_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|clk_filter [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N17 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [1]), + .datab(\ula_|ps2_keyboard_|clk_filter [3]), + .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N1 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y21_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y20_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hC4C4; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N25 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF850; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N21 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~52_combout = (\ula_|zx_keyboard_|keys[3][2]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~52 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~51_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~54_combout = (\ula_|zx_keyboard_|keys[2][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~53_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~54 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N17 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~5 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~5_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~5 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~48 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|keys[0][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (\ula_|zx_keyboard_|keys[0][2]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[0][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[0][2]~48_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~46_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~46 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h0088; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[3][3]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N21 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~4_combout = (\ula_|zx_keyboard_|keys[0][2]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\ula_|zx_keyboard_|keys[0][2]~q & +// (((\z80_|address_pins_|abus[9]~16_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~q ), + .datab(\ula_|zx_keyboard_|keys[1][2]~q ), + .datac(\z80_|address_pins_|abus[9]~16_combout ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~4 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~60_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h0A0A; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hC888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N23 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hCCFC; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~59_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~59 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[7][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[7][2]~63_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][2]~q ))))) # (!\ula_|zx_keyboard_|keys[7][2]~63_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~66 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[6][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~66_combout & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~65_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~65 .lut_mask = 16'hFF0C; +defparam \ula_|zx_keyboard_|keys[5][0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|zx_keyboard_|keys[6][2]~67_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|zx_keyboard_|keys[6][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~7 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~7_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~22_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~7 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][2]~30_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|zx_keyboard_|keys[5][2]~55_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~55_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~57_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~57 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~129_combout = (\ula_|zx_keyboard_|keys[4][2]~57_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~129 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[4][2]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~128_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~128 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|zx_keyboard_|keys[4][2]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~6 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~6_combout = (\ula_|zx_keyboard_|keys[5][2]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~6 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [2] = (\ula_|zx_keyboard_|key_row[2]~5_combout & (\ula_|zx_keyboard_|key_row[2]~4_combout & (\ula_|zx_keyboard_|key_row[2]~7_combout & \ula_|zx_keyboard_|key_row[2]~6_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .datab(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .datac(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .datad(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [2]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \Selector14~17 ( +// Equation(s): +// \Selector14~17_combout = (\Equal5~0_combout & (((!\z80_|address_pins_|DFFE_apin_latch [0] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\Equal3~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~17_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~17 .lut_mask = 16'h40F0; +defparam \Selector14~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \Selector14~18 ( +// Equation(s): +// \Selector14~18_combout = (\Equal5~0_combout & (((!\Equal3~2_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [15]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~18_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~18 .lut_mask = 16'h0BFB; +defparam \Selector14~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N22 +cycloneive_io_ibuf \kempston[1]~input ( + .i(kempston[1]), + .ibar(gnd), + .o(\kempston[1]~input_o )); +// synopsys translate_off +defparam \kempston[1]~input .bus_hold = "false"; +defparam \kempston[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \Selector10~2 ( +// Equation(s): +// \Selector10~2_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[1]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [2])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [2]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[1]~input_o ), + .cin(gnd), + .combout(\Selector10~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~2 .lut_mask = 16'h0BCB; +defparam \Selector10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \Selector10~3 ( +// Equation(s): +// \Selector10~3_combout = (\Equal5~0_combout & (((\Selector10~2_combout )))) # (!\Equal5~0_combout & ((\Selector10~2_combout & ((\Selector10~1_combout ))) # (!\Selector10~2_combout & +// (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector10~1_combout ), + .datad(\Selector10~2_combout ), + .cin(gnd), + .combout(\Selector10~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~3 .lut_mask = 16'hFC22; +defparam \Selector10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \D[2]~13 ( +// Equation(s): +// \D[2]~13_combout = (\Equal5~1_combout & (\Selector10~3_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout +// ))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Selector10~3_combout ), + .datad(\z80_|data_pins_|dout [2]), + .cin(gnd), + .combout(\D[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~13 .lut_mask = 16'hF531; +defparam \D[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\D[2]~13_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[2]~14_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[2]~13_combout & (\z80_|bus_control_|db[2]~14_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\D[2]~13_combout ), + .datab(\z80_|bus_control_|db[2]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N23 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[2]~28_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~14 ( +// Equation(s): +// \z80_|bus_control_|db[2]~14_combout = ((\z80_|bus_control_|db[2]~13_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|bus_control_|db[0]~5_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~14 .lut_mask = 16'h8FCF; +defparam \z80_|bus_control_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N1 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~14_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hC800; defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 +// Location: LCCOMB_X29_Y14_N12 cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), .datad(\z80_|pla_decode_|Equal41~1_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N8 +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~17_combout = ((\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~17 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_ir_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[4]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~3_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~2_combout = (!\z80_|ir_|opcode [5] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal2~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal2~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( // Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # -// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_state_tbl_cb_set~2_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .dataa(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hBAAA; defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N9 +// Location: FF_X29_Y18_N15 dffeas \z80_|decode_state_|DFFE_instCB ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), @@ -46778,941 +45873,1095 @@ defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y6_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - .dataa(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|decode_state_|table_xx~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal47~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y12_N29 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_66_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [0] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[6]~8_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~16 ( +// Equation(s): +// \z80_|alu_control_|db[6]~16_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~16 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[6]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~2_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~2 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~17 ( +// Equation(s): +// \z80_|alu_control_|db[6]~17_combout = (\z80_|alu_control_|db[6]~16_combout & (\z80_|reg_file_|db_lo_ds[6]~2_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|db[6]~16_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~17 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[6]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~18 ( +// Equation(s): +// \z80_|alu_control_|db[6]~18_combout = ((\z80_|alu_control_|db[6]~17_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .datab(\z80_|alu_control_|db[6]~17_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( +// Equation(s): +// \z80_|bus_control_|db[6]~7_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'h8A8A; +defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \D[6]~28 ( +// Equation(s): +// \D[6]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~28 .lut_mask = 16'hFFCF; +defparam \D[6]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \D[6]~43 ( +// Equation(s): +// \D[6]~43_combout = (\Equal5~0_combout & (\Equal3~2_combout & ((\D[6]~28_combout )))) # (!\Equal5~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\Equal5~0_combout ), + .datab(\Equal3~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\D[6]~28_combout ), + .cin(gnd), + .combout(\D[6]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~43 .lut_mask = 16'hD850; +defparam \D[6]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[6]~44 ( +// Equation(s): +// \D[6]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\Equal5~0_combout & ((\D[6]~43_combout ))) # (!\Equal5~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[6]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\Equal5~0_combout ), + .datad(\D[6]~43_combout ), + .cin(gnd), + .combout(\D[6]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~44 .lut_mask = 16'hFB08; +defparam \D[6]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[6]~42 ( +// Equation(s): +// \D[6]~42_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[6]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~42 .lut_mask = 16'hAACC; +defparam \D[6]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[6]~45 ( +// Equation(s): +// \D[6]~45_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~44_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Equal5~0_combout & (\D[6]~44_combout )) # (!\Equal5~0_combout & +// ((\D[6]~42_combout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\D[6]~44_combout ), + .datad(\D[6]~42_combout ), + .cin(gnd), + .combout(\D[6]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~45 .lut_mask = 16'hF1E0; +defparam \D[6]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) # (!\z80_|address_pins_|abus[14]~22_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux1~0 .lut_mask = 16'hDC98; +defparam \Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[6]~41 ( +// Equation(s): +// \D[6]~41_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux1~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # (!\Mux1~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux1~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Mux1~0_combout ), + .cin(gnd), + .combout(\D[6]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~41 .lut_mask = 16'hF388; +defparam \D[6]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[6]~46 ( +// Equation(s): +// \D[6]~46_combout = (\Equal5~0_combout & (((\D[6]~45_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\D[6]~45_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\D[6]~41_combout ))))) + + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\D[6]~45_combout ), + .datad(\D[6]~41_combout ), + .cin(gnd), + .combout(\D[6]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~46 .lut_mask = 16'hF1E0; +defparam \D[6]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[6]~47 ( +// Equation(s): +// \D[6]~47_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~46_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~46_combout ), + .cin(gnd), + .combout(\D[6]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~47 .lut_mask = 16'hAF23; +defparam \D[6]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~47_combout )))) # (!\z80_|bus_control_|db[6]~8_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~47_combout )))) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[6]~47_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = ((\z80_|bus_control_|db[6]~7_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[6]~7_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~8_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~8_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N29 +dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), + .q(\z80_|ir_|opcode [6]), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~18 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) +// \z80_|execute_|ctl_ir_we~18_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|im2~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .combout(\z80_|execute_|ctl_ir_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~16 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_bus_inc_oe~16_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_bus_inc_oe~15_combout )) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_mWrite~12_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|ctl_bus_db_we~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~18_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~10 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_bus_db_we~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( // Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) +// \z80_|execute_|ctl_bus_db_we~7_combout = (((\z80_|execute_|ctl_bus_db_we~10_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_bus_db_we~6_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~10_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_ir_we~8_combout ))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~9 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|execute_|ctl_bus_db_we~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~9 .lut_mask = 16'h4440; +defparam \z80_|execute_|ctl_bus_db_we~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|execute_|ctl_bus_db_we~5_combout ) # ((\z80_|execute_|ctl_bus_db_we~4_combout ) # (\z80_|execute_|ctl_bus_db_we~9_combout ))) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout -// )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; -defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N1 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N28 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hD0DD; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; -defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & -// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; -defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & -// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N2 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~q ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'h8ACF; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & -// \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; -defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .datac(\ula_|zx_keyboard_|keys~69_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; -defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys~71_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y8_N11 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N15 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N17 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][0]~q ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'h8CAF; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N12 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), - .datab(\z80_|address_pins_|abus[9]~17_combout ), - .datac(\ula_|zx_keyboard_|key_row~2_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hD000; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) - - .dataa(\D[0]~57_combout ), - .datab(\D[0]~56_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[0]~55_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hF8F0; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -47728,10 +46977,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47769,140 +47018,879 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N12 -cycloneive_lcell_comb \D[0]~62 ( +// Location: LCCOMB_X19_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( // Equation(s): -// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\D[0]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), .cout()); // synopsys translate_off -defparam \D[0]~62 .lut_mask = 16'hEC64; -defparam \D[0]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'hFF30; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'h1204; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][1]~34_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|keys[4][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~83_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~82_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[5][0]~79_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h2080; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|zx_keyboard_|keys[5][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~10_combout = (\ula_|zx_keyboard_|keys[4][0]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) # (!\ula_|zx_keyboard_|keys[4][0]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~10 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~130_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~76_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~130 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & ((\ula_|zx_keyboard_|keys[7][0]~85_combout ) # (\ula_|zx_keyboard_|keys[7][0]~130_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N17 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~11 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~11_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][0]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~11 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg +// [5] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (!\ula_|zx_keyboard_|extended~q & ((\ula_|ps2_keyboard_|shiftreg [3]) # ((!\ula_|zx_keyboard_|keys[4][1]~29_combout ) # (!\ula_|zx_keyboard_|WideOr4~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h0B0F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~72_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~45_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~72 .lut_mask = 16'h335F; +defparam \ula_|zx_keyboard_|keys~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~71_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~71 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~73_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~72_combout & \ula_|zx_keyboard_|keys[4][3]~71_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys~72_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~73 .lut_mask = 16'h4C0C; +defparam \ula_|zx_keyboard_|keys[0][0]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys~74_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~74_combout & ((\ula_|zx_keyboard_|keys[0][0]~73_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[0][0]~73_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys~74_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hCC00; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~69_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~69 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][0]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~70_combout = (\ula_|zx_keyboard_|keys[1][0]~69_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~69_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~70 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~8 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~8_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\z80_|address_pins_|abus[9]~16_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~8 .lut_mask = 16'hDD0D; +defparam \ula_|zx_keyboard_|key_row[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~78 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[2][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~77_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~76_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~77 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~9 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~9_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~19_combout & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & +// (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~9 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [0] = (\ula_|zx_keyboard_|key_row[0]~10_combout & (\ula_|zx_keyboard_|key_row[0]~11_combout & (\ula_|zx_keyboard_|key_row[0]~8_combout & \ula_|zx_keyboard_|key_row[0]~9_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .datab(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .datac(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .datad(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [0]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y34_N22 +cycloneive_io_ibuf \kempston[3]~input ( + .i(kempston[3]), + .ibar(gnd), + .o(\kempston[3]~input_o )); +// synopsys translate_off +defparam \kempston[3]~input .bus_hold = "false"; +defparam \kempston[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \Selector14~8 ( +// Equation(s): +// \Selector14~8_combout = (\Selector14~18_combout & (((!\kempston[3]~input_o & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row [0]) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [0]), + .datab(\Selector14~18_combout ), + .datac(\kempston[3]~input_o ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~8 .lut_mask = 16'h2E33; +defparam \Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \Selector14~13 ( +// Equation(s): +// \Selector14~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\Selector14~8_combout ) # ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a +// [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~13 .lut_mask = 16'hFFEA; +defparam \Selector14~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -47918,10 +47906,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47959,27 +47947,9 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N8 -cycloneive_lcell_comb \D[0]~63 ( -// Equation(s): -// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~62_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~63 .lut_mask = 16'hE3E0; -defparam \D[0]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -47987,16 +47957,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48050,7 +48020,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y4_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), @@ -48060,16 +48030,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48108,27 +48078,176 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \Selector14~19 ( // Equation(s): -// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) +// \Selector14~19_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\Selector14~19_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hE6A2; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \Selector14~19 .lut_mask = 16'hF4B0; +defparam \Selector14~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y29_N0 +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \Selector14~10 ( +// Equation(s): +// \Selector14~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~10 .lut_mask = 16'hFA0A; +defparam \Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \Selector14~11 ( +// Equation(s): +// \Selector14~11_combout = (\Selector14~8_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((!\Selector14~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector14~10_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~11 .lut_mask = 16'hCC0A; +defparam \Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -48136,16 +48255,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48198,7 +48317,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y11_N0 +// Location: M9K_X22_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -48208,16 +48327,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48256,104 +48375,102 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N28 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \Selector14~20 ( // Equation(s): -// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) +// \Selector14~20_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'h30CA; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N10 -cycloneive_lcell_comb \D[0]~61 ( -// Equation(s): -// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) - - .dataa(\D[0]~59_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\D[0]~60_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~61_combout ), + .combout(\Selector14~20_combout ), .cout()); // synopsys translate_off -defparam \D[0]~61 .lut_mask = 16'h99A8; -defparam \D[0]~61 .sum_lutc_input = "datac"; +defparam \Selector14~20 .lut_mask = 16'hF2D0; +defparam \Selector14~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N18 -cycloneive_lcell_comb \D[0]~120 ( +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \Selector14~9 ( // Equation(s): -// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~63_combout )))) +// \Selector14~9_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector14~20_combout )) # (!\Selector14~8_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~63_combout ), - .datad(\D[0]~61_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\Selector14~20_combout ), + .datad(\Selector14~8_combout ), .cin(gnd), - .combout(\D[0]~120_combout ), + .combout(\Selector14~9_combout ), .cout()); // synopsys translate_off -defparam \D[0]~120 .lut_mask = 16'hF4B0; -defparam \D[0]~120 .sum_lutc_input = "datac"; +defparam \Selector14~9 .lut_mask = 16'hDC33; +defparam \Selector14~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N26 -cycloneive_lcell_comb \D[0]~64 ( +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \Selector14~12 ( // Equation(s): -// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) +// \Selector14~12_combout = (\Selector14~11_combout & (\Selector14~8_combout & ((\Selector14~19_combout ) # (\Selector14~9_combout )))) # (!\Selector14~11_combout & (((\Selector14~9_combout )))) - .dataa(\D[0]~58_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[0]~120_combout ), + .dataa(\Selector14~19_combout ), + .datab(\Selector14~8_combout ), + .datac(\Selector14~11_combout ), + .datad(\Selector14~9_combout ), .cin(gnd), - .combout(\D[0]~64_combout ), + .combout(\Selector14~12_combout ), .cout()); // synopsys translate_off -defparam \D[0]~64 .lut_mask = 16'hBF8F; -defparam \D[0]~64 .sum_lutc_input = "datac"; +defparam \Selector14~12 .lut_mask = 16'hCF80; +defparam \Selector14~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N16 -cycloneive_lcell_comb \D[0]~65 ( +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \Selector14~14 ( // Equation(s): -// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) +// \Selector14~14_combout = (\Selector14~12_combout & ((\Selector14~13_combout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\Selector14~13_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\Selector14~12_combout ), + .cin(gnd), + .combout(\Selector14~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~14 .lut_mask = 16'hBA00; +defparam \Selector14~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \D[0]~14 ( +// Equation(s): +// \D[0]~14_combout = (\z80_|data_pins_|dout [0] & (((\Selector14~14_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [0]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[0]~64_combout ), - .datad(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), - .combout(\D[0]~65_combout ), + .combout(\D[0]~14_combout ), .cout()); // synopsys translate_off -defparam \D[0]~65 .lut_mask = 16'hB0B3; -defparam \D[0]~65 .sum_lutc_input = "datac"; +defparam \D[0]~14 .lut_mask = 16'hAF23; +defparam \D[0]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N26 +// Location: LCCOMB_X26_Y16_N8 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & -// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[0]~12_combout & +// (((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\D[0]~65_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\D[0]~14_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), .cout()); @@ -48362,7 +48479,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N27 +// Location: FF_X26_Y16_N9 dffeas \z80_|data_pins_|dout[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), @@ -48381,50 +48498,51 @@ defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~11 ( // Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[0]~11_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|alu_control_|db[0]~25_combout ) # ((!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|execute_|ctl_bus_ff_oe~1_combout & +// (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|data_pins_|dout [0]), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|alu_control_|db[0]~25_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), + .combout(\z80_|bus_control_|db[0]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~11 .lut_mask = 16'h8ACF; +defparam \z80_|bus_control_|db[0]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~12 ( // Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[0]~12_combout = ((\z80_|bus_control_|db[0]~11_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[0]~16_combout ), - .datab(\z80_|alu_control_|db[0]~14_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|bus_control_|db[0]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), + .combout(\z80_|bus_control_|db[0]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~12 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N19 +// Location: FF_X26_Y15_N15 dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), + .d(\z80_|bus_control_|db[0]~12_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [0]), @@ -48434,2832 +48552,311 @@ defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y7_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( // Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal3~2_combout ), + .dataa(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y7_N31 -dffeas \z80_|decode_state_|DFFE_instIY1 ( +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((\z80_|alu_control_|db[4]~31_combout & \z80_|execute_|ctl_flags_bus~combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))) # +// (!\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_control_|db[4]~31_combout & ((\z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hCE0A; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # -// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~12_combout ), - .datac(\z80_|execute_|ixy_d~13_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|ixy_d~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~11_combout ), - .datac(\z80_|execute_|ctl_alu_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N0 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~20_combout ), - .datad(\z80_|alu_|db[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|alu_control_|db[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; -defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( -// Equation(s): -// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|sw1_|db_down[1]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; -defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; -defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N9 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; -defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y10_N25 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; -defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N28 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hCF45; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N12 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|key_row~0_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hB000; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; -defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & -// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N16 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), - .datab(\ula_|zx_keyboard_|keys[0][1]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hF531; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N21 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N8 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'h8ACF; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N6 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~33_combout ), - .datab(\D[1]~30_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF8F0; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N22 -cycloneive_lcell_comb \D[1]~38 ( -// Equation(s): -// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .cin(gnd), - .combout(\D[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~38 .lut_mask = 16'hE6A2; -defparam \D[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N4 -cycloneive_lcell_comb \D[1]~39 ( -// Equation(s): -// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\D[1]~38_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\D[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~39 .lut_mask = 16'hE5E0; -defparam \D[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N24 -cycloneive_lcell_comb \D[1]~35 ( -// Equation(s): -// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\D[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~35 .lut_mask = 16'hEA62; -defparam \D[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N14 -cycloneive_lcell_comb \D[1]~36 ( -// Equation(s): -// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~36 .lut_mask = 16'h44B8; -defparam \D[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \D[1]~37 ( -// Equation(s): -// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datac(\D[1]~36_combout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~37 .lut_mask = 16'hAE50; -defparam \D[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[1]~118 ( -// Equation(s): -// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[1]~39_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[1]~39_combout ), - .datad(\D[1]~37_combout ), - .cin(gnd), - .combout(\D[1]~118_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~118 .lut_mask = 16'hF4B0; -defparam \D[1]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N2 -cycloneive_lcell_comb \D[1]~40 ( -// Equation(s): -// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[1]~34_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[1]~118_combout ), - .cin(gnd), - .combout(\D[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~40 .lut_mask = 16'hBF8F; -defparam \D[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N12 -cycloneive_lcell_comb \D[1]~41 ( -// Equation(s): -// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[1]~40_combout ), - .cin(gnd), - .combout(\D[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~41 .lut_mask = 16'hAF03; -defparam \D[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & -// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[1]~41_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[1]~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[1]~10_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N1 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~1_combout ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .combout(\z80_|alu_flags_|flags_hf~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h31CE; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y9_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N16 -cycloneive_lcell_comb \D[4]~88 ( +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~29 ( // Equation(s): -// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_control_|db[4]~29_combout = (\z80_|reg_file_|gdfx_temp0[4]~73_combout & (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # +// ((!\z80_|alu_|db[4]~10_combout & \z80_|execute_|ctl_sw_2u~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .dataa(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), .cin(gnd), - .combout(\D[4]~88_combout ), + .combout(\z80_|alu_control_|db[4]~29_combout ), .cout()); // synopsys translate_off -defparam \D[4]~88 .lut_mask = 16'hD0DD; -defparam \D[4]~88 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~29 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|alu_control_|db[4]~30_combout = (!\z80_|alu_control_|db[4]~29_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_control_|db[4]~29_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h2300; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|alu_control_|db[4]~31_combout = ((\z80_|alu_control_|db[4]~30_combout & ((\z80_|bus_control_|db[4]~18_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|bus_control_|db[4]~18_combout ), + .datab(\z80_|alu_control_|db[4]~30_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h8FCF; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N28 -cycloneive_lcell_comb \D[4]~87 ( -// Equation(s): -// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\D[4]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'h8ACF; -defparam \D[4]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N21 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|Equal0~2_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N15 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N6 -cycloneive_lcell_comb \D[4]~85 ( -// Equation(s): -// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~85 .lut_mask = 16'hA2F3; -defparam \D[4]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y11_N20 -cycloneive_lcell_comb \D[4]~86 ( -// Equation(s): -// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|key_row~3_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\D[4]~85_combout ), - .cin(gnd), - .combout(\D[4]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~86 .lut_mask = 16'h8A00; -defparam \D[4]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N24 -cycloneive_lcell_comb \D[4]~89 ( -// Equation(s): -// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) - - .dataa(\D[4]~88_combout ), - .datab(\D[4]~87_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[4]~86_combout ), - .cin(gnd), - .combout(\D[4]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~89 .lut_mask = 16'hF8F0; -defparam \D[4]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N18 -cycloneive_lcell_comb \D[4]~93 ( -// Equation(s): -// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .cin(gnd), - .combout(\D[4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~93 .lut_mask = 16'hF838; -defparam \D[4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N4 -cycloneive_lcell_comb \D[4]~94 ( -// Equation(s): -// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\D[4]~93_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .cin(gnd), - .combout(\D[4]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~94 .lut_mask = 16'hCEC2; -defparam \D[4]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X22_Y21_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51267,16 +48864,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51330,83 +48927,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N8 -cycloneive_lcell_comb \D[4]~90 ( -// Equation(s): -// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .cin(gnd), - .combout(\D[4]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~90 .lut_mask = 16'hE6A2; -defparam \D[4]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 +// Location: M9K_X33_Y22_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -51416,16 +48937,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51464,104 +48985,2926 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N22 -cycloneive_lcell_comb \D[4]~91 ( +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \Selector6~0 ( // Equation(s): -// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ) # (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & ((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hCCE2; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector6~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hF388; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[4]~90_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), .cin(gnd), - .combout(\D[4]~91_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), .cout()); // synopsys translate_off -defparam \D[4]~91 .lut_mask = 16'h4B48; -defparam \D[4]~91 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N28 -cycloneive_lcell_comb \D[4]~92 ( +// Location: LCCOMB_X19_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( // Equation(s): -// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [0]))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[4]~90_combout ), - .datad(\D[4]~91_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~92_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~92 .lut_mask = 16'hC3E0; -defparam \D[4]~92 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N8 -cycloneive_lcell_comb \D[4]~125 ( +// Location: LCCOMB_X20_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~114 ( // Equation(s): -// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (((\D[4]~94_combout )))) +// \ula_|zx_keyboard_|keys[6][4]~114_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\D[4]~94_combout ), - .datad(\D[4]~92_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\D[4]~125_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~114_combout ), .cout()); // synopsys translate_off -defparam \D[4]~125 .lut_mask = 16'hF2D0; -defparam \D[4]~125 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N30 -cycloneive_lcell_comb \D[4]~110 ( +// Location: LCCOMB_X20_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~115 ( // Equation(s): -// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) +// \ula_|zx_keyboard_|keys[6][4]~115_combout = (\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~115 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~113_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~1_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~113 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N5 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~16_combout = (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][4]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~16 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[0]~21 ( +// Equation(s): +// \debounce_autofire|r_Count[0]~21_combout = \debounce_autofire|r_Count [0] $ (VCC) +// \debounce_autofire|r_Count[0]~22 = CARRY(\debounce_autofire|r_Count [0]) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_autofire|r_Count[0]~21_combout ), + .cout(\debounce_autofire|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_autofire|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[1]~23 ( +// Equation(s): +// \debounce_autofire|r_Count[1]~23_combout = (\debounce_autofire|r_Count [1] & (!\debounce_autofire|r_Count[0]~22 )) # (!\debounce_autofire|r_Count [1] & ((\debounce_autofire|r_Count[0]~22 ) # (GND))) +// \debounce_autofire|r_Count[1]~24 = CARRY((!\debounce_autofire|r_Count[0]~22 ) # (!\debounce_autofire|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[0]~22 ), + .combout(\debounce_autofire|r_Count[1]~23_combout ), + .cout(\debounce_autofire|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \debounce_autofire|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[2]~25 ( +// Equation(s): +// \debounce_autofire|r_Count[2]~25_combout = (\debounce_autofire|r_Count [2] & (\debounce_autofire|r_Count[1]~24 $ (GND))) # (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count[1]~24 & VCC)) +// \debounce_autofire|r_Count[2]~26 = CARRY((\debounce_autofire|r_Count [2] & !\debounce_autofire|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[1]~24 ), + .combout(\debounce_autofire|r_Count[2]~25_combout ), + .cout(\debounce_autofire|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \debounce_autofire|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[3]~27 ( +// Equation(s): +// \debounce_autofire|r_Count[3]~27_combout = (\debounce_autofire|r_Count [3] & (!\debounce_autofire|r_Count[2]~26 )) # (!\debounce_autofire|r_Count [3] & ((\debounce_autofire|r_Count[2]~26 ) # (GND))) +// \debounce_autofire|r_Count[3]~28 = CARRY((!\debounce_autofire|r_Count[2]~26 ) # (!\debounce_autofire|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[2]~26 ), + .combout(\debounce_autofire|r_Count[3]~27_combout ), + .cout(\debounce_autofire|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \debounce_autofire|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[4]~29 ( +// Equation(s): +// \debounce_autofire|r_Count[4]~29_combout = (\debounce_autofire|r_Count [4] & (\debounce_autofire|r_Count[3]~28 $ (GND))) # (!\debounce_autofire|r_Count [4] & (!\debounce_autofire|r_Count[3]~28 & VCC)) +// \debounce_autofire|r_Count[4]~30 = CARRY((\debounce_autofire|r_Count [4] & !\debounce_autofire|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[3]~28 ), + .combout(\debounce_autofire|r_Count[4]~29_combout ), + .cout(\debounce_autofire|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \debounce_autofire|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \debounce_autofire|r_Count[5]~31 ( +// Equation(s): +// \debounce_autofire|r_Count[5]~31_combout = (\debounce_autofire|r_Count [5] & (!\debounce_autofire|r_Count[4]~30 )) # (!\debounce_autofire|r_Count [5] & ((\debounce_autofire|r_Count[4]~30 ) # (GND))) +// \debounce_autofire|r_Count[5]~32 = CARRY((!\debounce_autofire|r_Count[4]~30 ) # (!\debounce_autofire|r_Count [5])) + + .dataa(\debounce_autofire|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[4]~30 ), + .combout(\debounce_autofire|r_Count[5]~31_combout ), + .cout(\debounce_autofire|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \debounce_autofire|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \debounce_autofire|r_Count[6]~33 ( +// Equation(s): +// \debounce_autofire|r_Count[6]~33_combout = (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count[5]~32 $ (GND))) # (!\debounce_autofire|r_Count [6] & (!\debounce_autofire|r_Count[5]~32 & VCC)) +// \debounce_autofire|r_Count[6]~34 = CARRY((\debounce_autofire|r_Count [6] & !\debounce_autofire|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[5]~32 ), + .combout(\debounce_autofire|r_Count[6]~33_combout ), + .cout(\debounce_autofire|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \debounce_autofire|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \debounce_autofire|r_Count[7]~35 ( +// Equation(s): +// \debounce_autofire|r_Count[7]~35_combout = (\debounce_autofire|r_Count [7] & (!\debounce_autofire|r_Count[6]~34 )) # (!\debounce_autofire|r_Count [7] & ((\debounce_autofire|r_Count[6]~34 ) # (GND))) +// \debounce_autofire|r_Count[7]~36 = CARRY((!\debounce_autofire|r_Count[6]~34 ) # (!\debounce_autofire|r_Count [7])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[6]~34 ), + .combout(\debounce_autofire|r_Count[7]~35_combout ), + .cout(\debounce_autofire|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N27 +dffeas \debounce_autofire|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \debounce_autofire|r_Count[8]~37 ( +// Equation(s): +// \debounce_autofire|r_Count[8]~37_combout = (\debounce_autofire|r_Count [8] & (\debounce_autofire|r_Count[7]~36 $ (GND))) # (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_Count[7]~36 & VCC)) +// \debounce_autofire|r_Count[8]~38 = CARRY((\debounce_autofire|r_Count [8] & !\debounce_autofire|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[7]~36 ), + .combout(\debounce_autofire|r_Count[8]~37_combout ), + .cout(\debounce_autofire|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N29 +dffeas \debounce_autofire|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \debounce_autofire|r_Count[9]~39 ( +// Equation(s): +// \debounce_autofire|r_Count[9]~39_combout = (\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count[8]~38 )) # (!\debounce_autofire|r_Count [9] & ((\debounce_autofire|r_Count[8]~38 ) # (GND))) +// \debounce_autofire|r_Count[9]~40 = CARRY((!\debounce_autofire|r_Count[8]~38 ) # (!\debounce_autofire|r_Count [9])) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[8]~38 ), + .combout(\debounce_autofire|r_Count[9]~39_combout ), + .cout(\debounce_autofire|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \debounce_autofire|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_Count[10]~41 ( +// Equation(s): +// \debounce_autofire|r_Count[10]~41_combout = (\debounce_autofire|r_Count [10] & (\debounce_autofire|r_Count[9]~40 $ (GND))) # (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count[9]~40 & VCC)) +// \debounce_autofire|r_Count[10]~42 = CARRY((\debounce_autofire|r_Count [10] & !\debounce_autofire|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[9]~40 ), + .combout(\debounce_autofire|r_Count[10]~41_combout ), + .cout(\debounce_autofire|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \debounce_autofire|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \debounce_autofire|r_Count[11]~43 ( +// Equation(s): +// \debounce_autofire|r_Count[11]~43_combout = (\debounce_autofire|r_Count [11] & (!\debounce_autofire|r_Count[10]~42 )) # (!\debounce_autofire|r_Count [11] & ((\debounce_autofire|r_Count[10]~42 ) # (GND))) +// \debounce_autofire|r_Count[11]~44 = CARRY((!\debounce_autofire|r_Count[10]~42 ) # (!\debounce_autofire|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[10]~42 ), + .combout(\debounce_autofire|r_Count[11]~43_combout ), + .cout(\debounce_autofire|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \debounce_autofire|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \debounce_autofire|r_Count[12]~45 ( +// Equation(s): +// \debounce_autofire|r_Count[12]~45_combout = (\debounce_autofire|r_Count [12] & (\debounce_autofire|r_Count[11]~44 $ (GND))) # (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count[11]~44 & VCC)) +// \debounce_autofire|r_Count[12]~46 = CARRY((\debounce_autofire|r_Count [12] & !\debounce_autofire|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[11]~44 ), + .combout(\debounce_autofire|r_Count[12]~45_combout ), + .cout(\debounce_autofire|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \debounce_autofire|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \debounce_autofire|r_Count[13]~47 ( +// Equation(s): +// \debounce_autofire|r_Count[13]~47_combout = (\debounce_autofire|r_Count [13] & (!\debounce_autofire|r_Count[12]~46 )) # (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|r_Count[12]~46 ) # (GND))) +// \debounce_autofire|r_Count[13]~48 = CARRY((!\debounce_autofire|r_Count[12]~46 ) # (!\debounce_autofire|r_Count [13])) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[12]~46 ), + .combout(\debounce_autofire|r_Count[13]~47_combout ), + .cout(\debounce_autofire|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \debounce_autofire|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \debounce_autofire|r_Count[14]~49 ( +// Equation(s): +// \debounce_autofire|r_Count[14]~49_combout = (\debounce_autofire|r_Count [14] & (\debounce_autofire|r_Count[13]~48 $ (GND))) # (!\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count[13]~48 & VCC)) +// \debounce_autofire|r_Count[14]~50 = CARRY((\debounce_autofire|r_Count [14] & !\debounce_autofire|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[13]~48 ), + .combout(\debounce_autofire|r_Count[14]~49_combout ), + .cout(\debounce_autofire|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \debounce_autofire|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \debounce_autofire|r_Count[15]~51 ( +// Equation(s): +// \debounce_autofire|r_Count[15]~51_combout = (\debounce_autofire|r_Count [15] & (!\debounce_autofire|r_Count[14]~50 )) # (!\debounce_autofire|r_Count [15] & ((\debounce_autofire|r_Count[14]~50 ) # (GND))) +// \debounce_autofire|r_Count[15]~52 = CARRY((!\debounce_autofire|r_Count[14]~50 ) # (!\debounce_autofire|r_Count [15])) + + .dataa(\debounce_autofire|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[14]~50 ), + .combout(\debounce_autofire|r_Count[15]~51_combout ), + .cout(\debounce_autofire|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \debounce_autofire|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[16]~53 ( +// Equation(s): +// \debounce_autofire|r_Count[16]~53_combout = (\debounce_autofire|r_Count [16] & (\debounce_autofire|r_Count[15]~52 $ (GND))) # (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count[15]~52 & VCC)) +// \debounce_autofire|r_Count[16]~54 = CARRY((\debounce_autofire|r_Count [16] & !\debounce_autofire|r_Count[15]~52 )) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[15]~52 ), + .combout(\debounce_autofire|r_Count[16]~53_combout ), + .cout(\debounce_autofire|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_autofire|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \debounce_autofire|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[17]~55 ( +// Equation(s): +// \debounce_autofire|r_Count[17]~55_combout = (\debounce_autofire|r_Count [17] & (!\debounce_autofire|r_Count[16]~54 )) # (!\debounce_autofire|r_Count [17] & ((\debounce_autofire|r_Count[16]~54 ) # (GND))) +// \debounce_autofire|r_Count[17]~56 = CARRY((!\debounce_autofire|r_Count[16]~54 ) # (!\debounce_autofire|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[16]~54 ), + .combout(\debounce_autofire|r_Count[17]~55_combout ), + .cout(\debounce_autofire|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \debounce_autofire|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[18]~57 ( +// Equation(s): +// \debounce_autofire|r_Count[18]~57_combout = (\debounce_autofire|r_Count [18] & (\debounce_autofire|r_Count[17]~56 $ (GND))) # (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count[17]~56 & VCC)) +// \debounce_autofire|r_Count[18]~58 = CARRY((\debounce_autofire|r_Count [18] & !\debounce_autofire|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[17]~56 ), + .combout(\debounce_autofire|r_Count[18]~57_combout ), + .cout(\debounce_autofire|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \debounce_autofire|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[19]~59 ( +// Equation(s): +// \debounce_autofire|r_Count[19]~59_combout = (\debounce_autofire|r_Count [19] & (!\debounce_autofire|r_Count[18]~58 )) # (!\debounce_autofire|r_Count [19] & ((\debounce_autofire|r_Count[18]~58 ) # (GND))) +// \debounce_autofire|r_Count[19]~60 = CARRY((!\debounce_autofire|r_Count[18]~58 ) # (!\debounce_autofire|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[18]~58 ), + .combout(\debounce_autofire|r_Count[19]~59_combout ), + .cout(\debounce_autofire|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \debounce_autofire|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[20]~61 ( +// Equation(s): +// \debounce_autofire|r_Count[20]~61_combout = \debounce_autofire|r_Count[19]~60 $ (!\debounce_autofire|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_autofire|r_Count [20]), + .cin(\debounce_autofire|r_Count[19]~60 ), + .combout(\debounce_autofire|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_autofire|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \debounce_autofire|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y15_N8 +cycloneive_io_ibuf \kempston_autofire_button~input ( + .i(kempston_autofire_button), + .ibar(gnd), + .o(\kempston_autofire_button~input_o )); +// synopsys translate_off +defparam \kempston_autofire_button~input .bus_hold = "false"; +defparam \kempston_autofire_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~7 ( +// Equation(s): +// \debounce_autofire|r_State~7_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [6])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [6]), + .cin(gnd), + .combout(\debounce_autofire|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~7 .lut_mask = 16'hA000; +defparam \debounce_autofire|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \debounce_autofire|LessThan0~0 ( +// Equation(s): +// \debounce_autofire|LessThan0~0_combout = (!\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_State~7_combout & !\debounce_autofire|r_Count [10]))) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(\debounce_autofire|r_Count [8]), + .datac(\debounce_autofire|r_State~7_combout ), + .datad(\debounce_autofire|r_Count [10]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \debounce_autofire|LessThan0~1 ( +// Equation(s): +// \debounce_autofire|LessThan0~1_combout = (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|LessThan0~0_combout ) # (!\debounce_autofire|r_Count [11])))) + + .dataa(\debounce_autofire|LessThan0~0_combout ), + .datab(\debounce_autofire|r_Count [11]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [13]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~1 .lut_mask = 16'h000B; +defparam \debounce_autofire|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \debounce_autofire|always0~0 ( +// Equation(s): +// \debounce_autofire|always0~0_combout = (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count [17] & !\debounce_autofire|r_Count [19]))) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(\debounce_autofire|r_Count [18]), + .datac(\debounce_autofire|r_Count [17]), + .datad(\debounce_autofire|r_Count [19]), + .cin(gnd), + .combout(\debounce_autofire|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \debounce_autofire|always0~1 ( +// Equation(s): +// \debounce_autofire|always0~1_combout = (\debounce_autofire|always0~0_combout & ((\debounce_autofire|LessThan0~1_combout ) # ((!\debounce_autofire|r_Count [15]) # (!\debounce_autofire|r_Count [14])))) + + .dataa(\debounce_autofire|LessThan0~1_combout ), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|always0~0_combout ), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_autofire|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \debounce_autofire|always0~2 ( +// Equation(s): +// \debounce_autofire|always0~2_combout = (\debounce_autofire|r_Count [20] & ((\debounce_autofire|r_State~q $ (!\kempston_autofire_button~input_o )) # (!\debounce_autofire|always0~1_combout ))) # (!\debounce_autofire|r_Count [20] & +// (\debounce_autofire|r_State~q $ ((!\kempston_autofire_button~input_o )))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_State~q ), + .datac(\kempston_autofire_button~input_o ), + .datad(\debounce_autofire|always0~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~2 .lut_mask = 16'hC3EB; +defparam \debounce_autofire|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \debounce_autofire|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \debounce_autofire|r_State~4 ( +// Equation(s): +// \debounce_autofire|r_State~4_combout = (!\debounce_autofire|r_Count [0] & (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count [1] & !\debounce_autofire|r_Count [3]))) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(\debounce_autofire|r_Count [2]), + .datac(\debounce_autofire|r_Count [1]), + .datad(\debounce_autofire|r_Count [3]), + .cin(gnd), + .combout(\debounce_autofire|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_autofire|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \debounce_autofire|r_State~5 ( +// Equation(s): +// \debounce_autofire|r_State~5_combout = (\debounce_autofire|r_State~4_combout & !\debounce_autofire|r_Count [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\debounce_autofire|r_State~4_combout ), + .datad(\debounce_autofire|r_Count [4]), + .cin(gnd), + .combout(\debounce_autofire|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~5 .lut_mask = 16'h00F0; +defparam \debounce_autofire|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \debounce_autofire|r_State~2 ( +// Equation(s): +// \debounce_autofire|r_State~2_combout = (\debounce_autofire|r_Count [20] & (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count [9] & !\debounce_autofire|r_Count [8]))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_Count [10]), + .datac(\debounce_autofire|r_Count [9]), + .datad(\debounce_autofire|r_Count [8]), + .cin(gnd), + .combout(\debounce_autofire|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_autofire|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \debounce_autofire|r_State~0 ( +// Equation(s): +// \debounce_autofire|r_State~0_combout = (!\debounce_autofire|r_Count [13] & (\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count [12] & \debounce_autofire|r_Count [15]))) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_autofire|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \debounce_autofire|r_State~1 ( +// Equation(s): +// \debounce_autofire|r_State~1_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [11]))) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(\debounce_autofire|r_Count [6]), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [11]), + .cin(gnd), + .combout(\debounce_autofire|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~3 ( +// Equation(s): +// \debounce_autofire|r_State~3_combout = (\debounce_autofire|always0~0_combout & (\debounce_autofire|r_State~2_combout & (\debounce_autofire|r_State~0_combout & \debounce_autofire|r_State~1_combout ))) + + .dataa(\debounce_autofire|always0~0_combout ), + .datab(\debounce_autofire|r_State~2_combout ), + .datac(\debounce_autofire|r_State~0_combout ), + .datad(\debounce_autofire|r_State~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_State~6 ( +// Equation(s): +// \debounce_autofire|r_State~6_combout = (\debounce_autofire|r_State~5_combout & ((\debounce_autofire|r_State~3_combout & (\kempston_autofire_button~input_o )) # (!\debounce_autofire|r_State~3_combout & ((\debounce_autofire|r_State~q ))))) # +// (!\debounce_autofire|r_State~5_combout & (((\debounce_autofire|r_State~q )))) + + .dataa(\debounce_autofire|r_State~5_combout ), + .datab(\kempston_autofire_button~input_o ), + .datac(\debounce_autofire|r_State~q ), + .datad(\debounce_autofire|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~6 .lut_mask = 16'hD8F0; +defparam \debounce_autofire|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N19 +dffeas \debounce_autofire|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_autofire|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_State .is_wysiwyg = "true"; +defparam \debounce_autofire|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N30 +cycloneive_lcell_comb \kempston_autofire_enabled~0 ( +// Equation(s): +// \kempston_autofire_enabled~0_combout = !\kempston_autofire_enabled~q + + .dataa(gnd), + .datab(gnd), + .datac(\kempston_autofire_enabled~q ), + .datad(gnd), + .cin(gnd), + .combout(\kempston_autofire_enabled~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_autofire_enabled~0 .lut_mask = 16'h0F0F; +defparam \kempston_autofire_enabled~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N31 +dffeas kempston_autofire_enabled( + .clk(!\debounce_autofire|r_State~q ), + .d(\kempston_autofire_enabled~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_autofire_enabled~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_autofire_enabled.is_wysiwyg = "true"; +defparam kempston_autofire_enabled.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[0]~51 ( +// Equation(s): +// \kempston_auto_fire_counter[0]~51_combout = \kempston_autofire_enabled~q $ (kempston_auto_fire_counter[0]) + + .dataa(\kempston_autofire_enabled~q ), + .datab(gnd), + .datac(kempston_auto_fire_counter[0]), + .datad(gnd), + .cin(gnd), + .combout(\kempston_auto_fire_counter[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0]~51 .lut_mask = 16'h5A5A; +defparam \kempston_auto_fire_counter[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N13 +dffeas \kempston_auto_fire_counter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[0]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[0]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[1]~17 ( +// Equation(s): +// \kempston_auto_fire_counter[1]~17_combout = (kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] $ (VCC))) # (!kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] & VCC)) +// \kempston_auto_fire_counter[1]~18 = CARRY((kempston_auto_fire_counter[0] & kempston_auto_fire_counter[1])) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\kempston_auto_fire_counter[1]~17_combout ), + .cout(\kempston_auto_fire_counter[1]~18 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1]~17 .lut_mask = 16'h6688; +defparam \kempston_auto_fire_counter[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N17 +dffeas \kempston_auto_fire_counter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[1]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[1]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N18 +cycloneive_lcell_comb \kempston_auto_fire_counter[2]~19 ( +// Equation(s): +// \kempston_auto_fire_counter[2]~19_combout = (kempston_auto_fire_counter[2] & (!\kempston_auto_fire_counter[1]~18 )) # (!kempston_auto_fire_counter[2] & ((\kempston_auto_fire_counter[1]~18 ) # (GND))) +// \kempston_auto_fire_counter[2]~20 = CARRY((!\kempston_auto_fire_counter[1]~18 ) # (!kempston_auto_fire_counter[2])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[1]~18 ), + .combout(\kempston_auto_fire_counter[2]~19_combout ), + .cout(\kempston_auto_fire_counter[2]~20 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2]~19 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[2]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N19 +dffeas \kempston_auto_fire_counter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[2]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \kempston_auto_fire_counter[3]~21 ( +// Equation(s): +// \kempston_auto_fire_counter[3]~21_combout = (kempston_auto_fire_counter[3] & (\kempston_auto_fire_counter[2]~20 $ (GND))) # (!kempston_auto_fire_counter[3] & (!\kempston_auto_fire_counter[2]~20 & VCC)) +// \kempston_auto_fire_counter[3]~22 = CARRY((kempston_auto_fire_counter[3] & !\kempston_auto_fire_counter[2]~20 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[2]~20 ), + .combout(\kempston_auto_fire_counter[3]~21_combout ), + .cout(\kempston_auto_fire_counter[3]~22 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3]~21 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[3]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N21 +dffeas \kempston_auto_fire_counter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[3]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N22 +cycloneive_lcell_comb \kempston_auto_fire_counter[4]~23 ( +// Equation(s): +// \kempston_auto_fire_counter[4]~23_combout = (kempston_auto_fire_counter[4] & (!\kempston_auto_fire_counter[3]~22 )) # (!kempston_auto_fire_counter[4] & ((\kempston_auto_fire_counter[3]~22 ) # (GND))) +// \kempston_auto_fire_counter[4]~24 = CARRY((!\kempston_auto_fire_counter[3]~22 ) # (!kempston_auto_fire_counter[4])) + + .dataa(kempston_auto_fire_counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[3]~22 ), + .combout(\kempston_auto_fire_counter[4]~23_combout ), + .cout(\kempston_auto_fire_counter[4]~24 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4]~23 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[4]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N23 +dffeas \kempston_auto_fire_counter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[4]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N24 +cycloneive_lcell_comb \kempston_auto_fire_counter[5]~25 ( +// Equation(s): +// \kempston_auto_fire_counter[5]~25_combout = (kempston_auto_fire_counter[5] & (\kempston_auto_fire_counter[4]~24 $ (GND))) # (!kempston_auto_fire_counter[5] & (!\kempston_auto_fire_counter[4]~24 & VCC)) +// \kempston_auto_fire_counter[5]~26 = CARRY((kempston_auto_fire_counter[5] & !\kempston_auto_fire_counter[4]~24 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[4]~24 ), + .combout(\kempston_auto_fire_counter[5]~25_combout ), + .cout(\kempston_auto_fire_counter[5]~26 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5]~25 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[5]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N25 +dffeas \kempston_auto_fire_counter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[5]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N26 +cycloneive_lcell_comb \kempston_auto_fire_counter[6]~27 ( +// Equation(s): +// \kempston_auto_fire_counter[6]~27_combout = (kempston_auto_fire_counter[6] & (!\kempston_auto_fire_counter[5]~26 )) # (!kempston_auto_fire_counter[6] & ((\kempston_auto_fire_counter[5]~26 ) # (GND))) +// \kempston_auto_fire_counter[6]~28 = CARRY((!\kempston_auto_fire_counter[5]~26 ) # (!kempston_auto_fire_counter[6])) + + .dataa(kempston_auto_fire_counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[5]~26 ), + .combout(\kempston_auto_fire_counter[6]~27_combout ), + .cout(\kempston_auto_fire_counter[6]~28 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6]~27 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[6]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N27 +dffeas \kempston_auto_fire_counter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[6]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N28 +cycloneive_lcell_comb \kempston_auto_fire_counter[7]~29 ( +// Equation(s): +// \kempston_auto_fire_counter[7]~29_combout = (kempston_auto_fire_counter[7] & (\kempston_auto_fire_counter[6]~28 $ (GND))) # (!kempston_auto_fire_counter[7] & (!\kempston_auto_fire_counter[6]~28 & VCC)) +// \kempston_auto_fire_counter[7]~30 = CARRY((kempston_auto_fire_counter[7] & !\kempston_auto_fire_counter[6]~28 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[6]~28 ), + .combout(\kempston_auto_fire_counter[7]~29_combout ), + .cout(\kempston_auto_fire_counter[7]~30 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7]~29 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[7]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N29 +dffeas \kempston_auto_fire_counter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[7]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \kempston_auto_fire_counter[8]~31 ( +// Equation(s): +// \kempston_auto_fire_counter[8]~31_combout = (kempston_auto_fire_counter[8] & (!\kempston_auto_fire_counter[7]~30 )) # (!kempston_auto_fire_counter[8] & ((\kempston_auto_fire_counter[7]~30 ) # (GND))) +// \kempston_auto_fire_counter[8]~32 = CARRY((!\kempston_auto_fire_counter[7]~30 ) # (!kempston_auto_fire_counter[8])) + + .dataa(kempston_auto_fire_counter[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[7]~30 ), + .combout(\kempston_auto_fire_counter[8]~31_combout ), + .cout(\kempston_auto_fire_counter[8]~32 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8]~31 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[8]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N31 +dffeas \kempston_auto_fire_counter[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[8]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \kempston_auto_fire_counter[9]~33 ( +// Equation(s): +// \kempston_auto_fire_counter[9]~33_combout = (kempston_auto_fire_counter[9] & (\kempston_auto_fire_counter[8]~32 $ (GND))) # (!kempston_auto_fire_counter[9] & (!\kempston_auto_fire_counter[8]~32 & VCC)) +// \kempston_auto_fire_counter[9]~34 = CARRY((kempston_auto_fire_counter[9] & !\kempston_auto_fire_counter[8]~32 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[9]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[8]~32 ), + .combout(\kempston_auto_fire_counter[9]~33_combout ), + .cout(\kempston_auto_fire_counter[9]~34 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9]~33 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[9]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N1 +dffeas \kempston_auto_fire_counter[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[9]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \kempston_auto_fire_counter[10]~35 ( +// Equation(s): +// \kempston_auto_fire_counter[10]~35_combout = (kempston_auto_fire_counter[10] & (!\kempston_auto_fire_counter[9]~34 )) # (!kempston_auto_fire_counter[10] & ((\kempston_auto_fire_counter[9]~34 ) # (GND))) +// \kempston_auto_fire_counter[10]~36 = CARRY((!\kempston_auto_fire_counter[9]~34 ) # (!kempston_auto_fire_counter[10])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[9]~34 ), + .combout(\kempston_auto_fire_counter[10]~35_combout ), + .cout(\kempston_auto_fire_counter[10]~36 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10]~35 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[10]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N3 +dffeas \kempston_auto_fire_counter[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[10]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N4 +cycloneive_lcell_comb \kempston_auto_fire_counter[11]~37 ( +// Equation(s): +// \kempston_auto_fire_counter[11]~37_combout = (kempston_auto_fire_counter[11] & (\kempston_auto_fire_counter[10]~36 $ (GND))) # (!kempston_auto_fire_counter[11] & (!\kempston_auto_fire_counter[10]~36 & VCC)) +// \kempston_auto_fire_counter[11]~38 = CARRY((kempston_auto_fire_counter[11] & !\kempston_auto_fire_counter[10]~36 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[10]~36 ), + .combout(\kempston_auto_fire_counter[11]~37_combout ), + .cout(\kempston_auto_fire_counter[11]~38 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11]~37 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[11]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N5 +dffeas \kempston_auto_fire_counter[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[11]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \kempston_auto_fire_counter[12]~39 ( +// Equation(s): +// \kempston_auto_fire_counter[12]~39_combout = (kempston_auto_fire_counter[12] & (!\kempston_auto_fire_counter[11]~38 )) # (!kempston_auto_fire_counter[12] & ((\kempston_auto_fire_counter[11]~38 ) # (GND))) +// \kempston_auto_fire_counter[12]~40 = CARRY((!\kempston_auto_fire_counter[11]~38 ) # (!kempston_auto_fire_counter[12])) + + .dataa(kempston_auto_fire_counter[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[11]~38 ), + .combout(\kempston_auto_fire_counter[12]~39_combout ), + .cout(\kempston_auto_fire_counter[12]~40 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12]~39 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[12]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N7 +dffeas \kempston_auto_fire_counter[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[12]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N8 +cycloneive_lcell_comb \kempston_auto_fire_counter[13]~41 ( +// Equation(s): +// \kempston_auto_fire_counter[13]~41_combout = (kempston_auto_fire_counter[13] & (\kempston_auto_fire_counter[12]~40 $ (GND))) # (!kempston_auto_fire_counter[13] & (!\kempston_auto_fire_counter[12]~40 & VCC)) +// \kempston_auto_fire_counter[13]~42 = CARRY((kempston_auto_fire_counter[13] & !\kempston_auto_fire_counter[12]~40 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[12]~40 ), + .combout(\kempston_auto_fire_counter[13]~41_combout ), + .cout(\kempston_auto_fire_counter[13]~42 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13]~41 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[13]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N9 +dffeas \kempston_auto_fire_counter[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[13]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N10 +cycloneive_lcell_comb \kempston_auto_fire_counter[14]~43 ( +// Equation(s): +// \kempston_auto_fire_counter[14]~43_combout = (kempston_auto_fire_counter[14] & (!\kempston_auto_fire_counter[13]~42 )) # (!kempston_auto_fire_counter[14] & ((\kempston_auto_fire_counter[13]~42 ) # (GND))) +// \kempston_auto_fire_counter[14]~44 = CARRY((!\kempston_auto_fire_counter[13]~42 ) # (!kempston_auto_fire_counter[14])) + + .dataa(kempston_auto_fire_counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[13]~42 ), + .combout(\kempston_auto_fire_counter[14]~43_combout ), + .cout(\kempston_auto_fire_counter[14]~44 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14]~43 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[14]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N11 +dffeas \kempston_auto_fire_counter[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[14]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[15]~45 ( +// Equation(s): +// \kempston_auto_fire_counter[15]~45_combout = (kempston_auto_fire_counter[15] & (\kempston_auto_fire_counter[14]~44 $ (GND))) # (!kempston_auto_fire_counter[15] & (!\kempston_auto_fire_counter[14]~44 & VCC)) +// \kempston_auto_fire_counter[15]~46 = CARRY((kempston_auto_fire_counter[15] & !\kempston_auto_fire_counter[14]~44 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[14]~44 ), + .combout(\kempston_auto_fire_counter[15]~45_combout ), + .cout(\kempston_auto_fire_counter[15]~46 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15]~45 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[15]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \kempston_auto_fire_counter[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[15]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \Equal2~3 ( +// Equation(s): +// \Equal2~3_combout = (!kempston_auto_fire_counter[14] & (!kempston_auto_fire_counter[15] & (!kempston_auto_fire_counter[13] & !kempston_auto_fire_counter[12]))) + + .dataa(kempston_auto_fire_counter[14]), + .datab(kempston_auto_fire_counter[15]), + .datac(kempston_auto_fire_counter[13]), + .datad(kempston_auto_fire_counter[12]), + .cin(gnd), + .combout(\Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~3 .lut_mask = 16'h0001; +defparam \Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \Equal2~2 ( +// Equation(s): +// \Equal2~2_combout = (!kempston_auto_fire_counter[8] & (!kempston_auto_fire_counter[9] & (!kempston_auto_fire_counter[11] & !kempston_auto_fire_counter[10]))) + + .dataa(kempston_auto_fire_counter[8]), + .datab(kempston_auto_fire_counter[9]), + .datac(kempston_auto_fire_counter[11]), + .datad(kempston_auto_fire_counter[10]), + .cin(gnd), + .combout(\Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~2 .lut_mask = 16'h0001; +defparam \Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N10 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!kempston_auto_fire_counter[0] & (!kempston_auto_fire_counter[1] & (!kempston_auto_fire_counter[3] & !kempston_auto_fire_counter[2]))) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(kempston_auto_fire_counter[3]), + .datad(kempston_auto_fire_counter[2]), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N0 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!kempston_auto_fire_counter[4] & (!kempston_auto_fire_counter[5] & (!kempston_auto_fire_counter[6] & !kempston_auto_fire_counter[7]))) + + .dataa(kempston_auto_fire_counter[4]), + .datab(kempston_auto_fire_counter[5]), + .datac(kempston_auto_fire_counter[6]), + .datad(kempston_auto_fire_counter[7]), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0001; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \Equal2~4 ( +// Equation(s): +// \Equal2~4_combout = (\Equal2~3_combout & (\Equal2~2_combout & (\Equal2~0_combout & \Equal2~1_combout ))) + + .dataa(\Equal2~3_combout ), + .datab(\Equal2~2_combout ), + .datac(\Equal2~0_combout ), .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[4]~110_combout ), + .combout(\Equal2~4_combout ), .cout()); // synopsys translate_off -defparam \D[4]~110 .lut_mask = 16'hB8FF; -defparam \D[4]~110 .sum_lutc_input = "datac"; +defparam \Equal2~4 .lut_mask = 16'h8000; +defparam \Equal2~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N4 -cycloneive_lcell_comb \D[4]~111 ( +// Location: LCCOMB_X18_Y12_N14 +cycloneive_lcell_comb \kempston_auto_fire_counter[16]~47 ( // Equation(s): -// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) +// \kempston_auto_fire_counter[16]~47_combout = (kempston_auto_fire_counter[16] & (!\kempston_auto_fire_counter[15]~46 )) # (!kempston_auto_fire_counter[16] & ((\kempston_auto_fire_counter[15]~46 ) # (GND))) +// \kempston_auto_fire_counter[16]~48 = CARRY((!\kempston_auto_fire_counter[15]~46 ) # (!kempston_auto_fire_counter[16])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[15]~46 ), + .combout(\kempston_auto_fire_counter[16]~47_combout ), + .cout(\kempston_auto_fire_counter[16]~48 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16]~47 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[16]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N15 +dffeas \kempston_auto_fire_counter[16] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[16]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[17]~49 ( +// Equation(s): +// \kempston_auto_fire_counter[17]~49_combout = \kempston_auto_fire_counter[16]~48 $ (!kempston_auto_fire_counter[17]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(kempston_auto_fire_counter[17]), + .cin(\kempston_auto_fire_counter[16]~48 ), + .combout(\kempston_auto_fire_counter[17]~49_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17]~49 .lut_mask = 16'hF00F; +defparam \kempston_auto_fire_counter[17]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N17 +dffeas \kempston_auto_fire_counter[17] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[17]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N26 +cycloneive_lcell_comb \kempston_auto_fire~0 ( +// Equation(s): +// \kempston_auto_fire~0_combout = \kempston_auto_fire~q $ (((\Equal2~4_combout & (!kempston_auto_fire_counter[16] & !kempston_auto_fire_counter[17])))) + + .dataa(\Equal2~4_combout ), + .datab(kempston_auto_fire_counter[16]), + .datac(\kempston_auto_fire~q ), + .datad(kempston_auto_fire_counter[17]), + .cin(gnd), + .combout(\kempston_auto_fire~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire~0 .lut_mask = 16'hF0D2; +defparam \kempston_auto_fire~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N27 +dffeas kempston_auto_fire( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\kempston_autofire_enabled~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_auto_fire~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_auto_fire.is_wysiwyg = "true"; +defparam kempston_auto_fire.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \Selector6~2 ( +// Equation(s): +// \Selector6~2_combout = (\Selector14~18_combout & (((\kempston_auto_fire~q & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row[4]~16_combout ) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .datab(\Selector14~18_combout ), + .datac(\kempston_auto_fire~q ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~2 .lut_mask = 16'hE233; +defparam \Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~116 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~117_combout = (\ula_|zx_keyboard_|keys[5][4]~116_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[5][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~116_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~117 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [6])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~118 .lut_mask = 16'h4242; +defparam \ula_|zx_keyboard_|keys[4][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~119_combout = (\ula_|zx_keyboard_|keys[4][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~119 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~120_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~119_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~119_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~120 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~17_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~17 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~121 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~133_combout = (\ula_|zx_keyboard_|keys[3][4]~121_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~133 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[3][4]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~122_combout = (\ula_|zx_keyboard_|keys[3][4]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & +// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~133_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .datab(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~122 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N1 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hBBAA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~124_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~123_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~124 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~125_combout = (\ula_|zx_keyboard_|keys[2][4]~124_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~124_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~125 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \Selector6~3 ( +// Equation(s): +// \Selector6~3_combout = (\ula_|zx_keyboard_|keys[3][4]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~3 .lut_mask = 16'hDD0D; +defparam \Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~126_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~126 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~127_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N19 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y23_N8 +cycloneive_lcell_comb \Selector6~4 ( +// Equation(s): +// \Selector6~4_combout = (\ula_|zx_keyboard_|keys[1][4]~q & (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[1][4]~q & +// (((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~4 .lut_mask = 16'hDD0D; +defparam \Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \Selector6~5 ( +// Equation(s): +// \Selector6~5_combout = ((\ula_|zx_keyboard_|key_row[4]~17_combout & (\Selector6~3_combout & \Selector6~4_combout ))) # (!\Selector14~17_combout ) + + .dataa(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .datab(\Selector14~17_combout ), + .datac(\Selector6~3_combout ), + .datad(\Selector6~4_combout ), + .cin(gnd), + .combout(\Selector6~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~5 .lut_mask = 16'hB333; +defparam \Selector6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y34_N15 +cycloneive_io_ibuf \kempston[4]~input ( + .i(kempston[4]), + .ibar(gnd), + .o(\kempston[4]~input_o )); +// synopsys translate_off +defparam \kempston[4]~input .bus_hold = "false"; +defparam \kempston[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \Selector6~6 ( +// Equation(s): +// \Selector6~6_combout = (\Selector6~2_combout & ((\Selector14~18_combout & ((!\kempston[4]~input_o ))) # (!\Selector14~18_combout & (\Selector6~5_combout )))) + + .dataa(\Selector6~2_combout ), + .datab(\Selector6~5_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[4]~input_o ), + .cin(gnd), + .combout(\Selector6~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~6 .lut_mask = 16'h08A8; +defparam \Selector6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \Selector6~7 ( +// Equation(s): +// \Selector6~7_combout = (\Equal5~0_combout & (((\Selector6~6_combout )))) # (!\Equal5~0_combout & ((\Selector6~6_combout & (\Selector6~1_combout )) # (!\Selector6~6_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout +// ))))) + + .dataa(\Selector6~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector6~6_combout ), + .cin(gnd), + .combout(\Selector6~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~7 .lut_mask = 16'hEE30; +defparam \Selector6~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[4]~39 ( +// Equation(s): +// \D[4]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector6~7_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[4]~110_combout ), - .datad(\z80_|data_pins_|dout [4]), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), - .combout(\D[4]~111_combout ), + .combout(\D[4]~39_combout ), .cout()); // synopsys translate_off -defparam \D[4]~111 .lut_mask = 16'hF151; -defparam \D[4]~111 .sum_lutc_input = "datac"; +defparam \D[4]~39 .lut_mask = 16'hDD0D; +defparam \D[4]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N10 +// Location: LCCOMB_X26_Y16_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & -// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~39_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) # (!\D[4]~39_combout & +// (((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) - .dataa(\D[4]~111_combout ), + .dataa(\D[4]~39_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -51570,7 +51913,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N11 +// Location: FF_X26_Y16_N25 dffeas \z80_|data_pins_|dout[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), @@ -51589,145 +51932,3743 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N18 +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~17 ( +// Equation(s): +// \z80_|bus_control_|db[4]~17_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [4]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~17 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[4]~18_combout = ((\z80_|bus_control_|db[4]~17_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~17_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( // Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[4]~18_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N23 -dffeas \z80_|ir_|opcode[4] ( +// Location: FF_X27_Y12_N15 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[4]~19_combout ), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [4]), + .q(\z80_|interrupts_|im2~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|DFFE_inst44~q & \z80_|interrupts_|im2~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [1] = (\z80_|bus_control_|db[1]~10_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~3_combout = (\z80_|reg_file_|gdfx_temp0[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~3 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~20 ( +// Equation(s): +// \z80_|alu_control_|db[1]~20_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~20 .lut_mask = 16'h88CC; +defparam \z80_|alu_control_|db[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~21 ( +// Equation(s): +// \z80_|alu_control_|db[1]~21_combout = (\z80_|reg_file_|db_lo_ds[1]~3_combout & (\z80_|alu_control_|db[1]~20_combout & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|db[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~21 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~22 ( +// Equation(s): +// \z80_|alu_control_|db[1]~22_combout = ((\z80_|alu_control_|db[1]~21_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .datab(\z80_|alu_control_|db[1]~21_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~22 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~9 ( +// Equation(s): +// \z80_|bus_control_|db[1]~9_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|alu_control_|db[1]~22_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~9 .lut_mask = 16'hA0F0; +defparam \z80_|bus_control_|db[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[5][1]~33_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~2_combout = (\ula_|zx_keyboard_|keys[5][1]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~2 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][1]~q )))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N5 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~1_combout = (\z80_|address_pins_|abus[10]~19_combout & (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~q ))) # (!\z80_|address_pins_|abus[10]~19_combout & (!\ula_|zx_keyboard_|keys[2][1]~q +// & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~1 .lut_mask = 16'hA2F3; +defparam \ula_|zx_keyboard_|key_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~38 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg +// [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0210; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr16~2_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h8B88; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & ((\ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hE2C0; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~39_combout = (\ula_|zx_keyboard_|keys[7][1]~38_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|WideOr16~6_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) # +// (!\ula_|zx_keyboard_|keys[7][1]~38_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~39 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hFCCC; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~42_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~3_combout = (\z80_|address_pins_|abus[15]~23_combout & (((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][1]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~3 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & (!\ula_|zx_keyboard_|keys[0][1]~12_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][4]~18_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N25 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~0_combout = (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~16_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & +// ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~16_combout ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~0 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [1] = (\ula_|zx_keyboard_|key_row[1]~2_combout & (\ula_|zx_keyboard_|key_row[1]~1_combout & (\ula_|zx_keyboard_|key_row[1]~3_combout & \ula_|zx_keyboard_|key_row[1]~0_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .datab(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .datac(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .datad(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [1]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y34_N1 +cycloneive_io_ibuf \kempston[2]~input ( + .i(kempston[2]), + .ibar(gnd), + .o(\kempston[2]~input_o )); +// synopsys translate_off +defparam \kempston[2]~input .bus_hold = "false"; +defparam \kempston[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \Selector12~4 ( +// Equation(s): +// \Selector12~4_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[2]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [1])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [1]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[2]~input_o ), + .cin(gnd), + .combout(\Selector12~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~4 .lut_mask = 16'h0BCB; +defparam \Selector12~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \Selector12~10 ( +// Equation(s): +// \Selector12~10_combout = (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector12~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~10 .lut_mask = 16'hFFCF; +defparam \Selector12~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \Selector12~7 ( +// Equation(s): +// \Selector12~7_combout = (\Selector12~4_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\Selector12~4_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\Selector12~4_combout ), + .cin(gnd), + .combout(\Selector12~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~7 .lut_mask = 16'hEEF0; +defparam \Selector12~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \Selector12~8 ( +// Equation(s): +// \Selector12~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\Selector12~7_combout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\Selector12~7_combout ), + .cin(gnd), + .combout(\Selector12~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~8 .lut_mask = 16'hAFA0; +defparam \Selector12~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \Selector12~9 ( +// Equation(s): +// \Selector12~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\Selector12~8_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a +// [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector12~8_combout ), + .cin(gnd), + .combout(\Selector12~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~9 .lut_mask = 16'hFE0E; +defparam \Selector12~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \Selector12~15 ( +// Equation(s): +// \Selector12~15_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~15_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~15 .lut_mask = 16'hF2D0; +defparam \Selector12~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \Selector12~5 ( +// Equation(s): +// \Selector12~5_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector12~15_combout )) # (!\Selector12~4_combout ))) + + .dataa(\Equal5~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector12~4_combout ), + .datad(\Selector12~15_combout ), + .cin(gnd), + .combout(\Selector12~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~5 .lut_mask = 16'hB5A5; +defparam \Selector12~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \Selector12~14 ( +// Equation(s): +// \Selector12~14_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\Selector12~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~14 .lut_mask = 16'hF2D0; +defparam \Selector12~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \Selector12~6 ( +// Equation(s): +// \Selector12~6_combout = (\Selector12~5_combout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\Selector12~4_combout & \Selector12~14_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Selector12~4_combout ), + .datac(\Selector12~5_combout ), + .datad(\Selector12~14_combout ), + .cin(gnd), + .combout(\Selector12~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~6 .lut_mask = 16'hF8F0; +defparam \Selector12~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \Selector12~11 ( +// Equation(s): +// \Selector12~11_combout = (\Selector12~6_combout & ((\Selector12~4_combout ) # ((\Selector12~10_combout & \Selector12~9_combout )))) + + .dataa(\Selector12~4_combout ), + .datab(\Selector12~10_combout ), + .datac(\Selector12~9_combout ), + .datad(\Selector12~6_combout ), + .cin(gnd), + .combout(\Selector12~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~11 .lut_mask = 16'hEA00; +defparam \Selector12~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[1]~12 ( +// Equation(s): +// \D[1]~12_combout = (\Equal5~1_combout & (\Selector12~11_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout +// )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector12~11_combout ), + .cin(gnd), + .combout(\D[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~12 .lut_mask = 16'hCF45; +defparam \D[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~12_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[1]~10_combout )))) # (!\D[1]~12_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[1]~10_combout ))) + + .dataa(\D[1]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N17 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = ((\z80_|bus_control_|db[1]~9_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[1]~9_combout ), + .datab(\z80_|bus_control_|db[0]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB3B; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[1]~10_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(\z80_|ir_|opcode [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|iff1~q ))))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal79~0_combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFCF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N26 +// Location: LCCOMB_X29_Y17_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) +// \z80_|interrupts_|test1~2_combout = ((\z80_|ir_|opcode [5] & ((!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|ir_|opcode [5] & (!\z80_|pla_decode_|Equal2~2_combout ))) # (!\z80_|pla_decode_|Equal2~3_combout ) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal43~0_combout ), + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h3F77; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N30 +// Location: LCCOMB_X29_Y14_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (\z80_|interrupts_|test1~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & ((!\z80_|pla_decode_|Equal3~2_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h002A; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N7 +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|interrupts_|test1~4 ( +// Equation(s): +// \z80_|interrupts_|test1~4_combout = (!\z80_|execute_|setM1~55_combout & ((\z80_|interrupts_|test1~3_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~4 .lut_mask = 16'h3323; +defparam \z80_|interrupts_|test1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_inst44~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(gnd), + .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datac(\z80_|clk_delay_|DFF_inst5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0303; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|execute_|setM1~55_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h5000; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N11 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~2 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~3 ( +// Equation(s): +// \z80_|bus_control_|db[0]~3_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~2_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~3 .lut_mask = 16'hAEAF; +defparam \z80_|bus_control_|db[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \Selector8~5 ( +// Equation(s): +// \Selector8~5_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~5 .lut_mask = 16'hCBC8; +defparam \Selector8~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \Selector8~6 ( +// Equation(s): +// \Selector8~6_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~5_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~5_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~5_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~5_combout ), + .cin(gnd), + .combout(\Selector8~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~6 .lut_mask = 16'hF388; +defparam \Selector8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \Selector8~7 ( +// Equation(s): +// \Selector8~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\Selector8~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~7 .lut_mask = 16'hAEA4; +defparam \Selector8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \Selector8~8 ( +// Equation(s): +// \Selector8~8_combout = (\Selector8~7_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\Selector8~7_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\Selector8~7_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector8~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~8 .lut_mask = 16'hACF0; +defparam \Selector8~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~134_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[0][0]~13_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [3]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~134 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~135_combout = (\ula_|zx_keyboard_|keys[6][3]~134_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~134_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~15_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][3]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~15 .lut_mask = 16'hBB0B; +defparam \ula_|zx_keyboard_|key_row[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[0][3]~94_combout & ((!\ula_|zx_keyboard_|keys[2][4]~93_combout ))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N27 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~12_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// ((\z80_|address_pins_|abus[9]~16_combout ) # ((!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~12 .lut_mask = 16'hCF45; +defparam \ula_|zx_keyboard_|key_row[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h00A0; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~46_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N23 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[2][3]~100_combout & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[2][3]~101_combout & ((\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|zx_keyboard_|keys[2][3]~99_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & +// ((\ula_|zx_keyboard_|keys[2][3]~q ))))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N15 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~13_combout = (\ula_|zx_keyboard_|keys[3][3]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[3][3]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~13 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~76_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~131_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|Selector5~1_combout ), + .datad(\ula_|zx_keyboard_|Selector5~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~131 .lut_mask = 16'hFF20; +defparam \ula_|zx_keyboard_|keys[4][3]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~105_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~131_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hB888; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|shifted~q & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hCCDC; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[4][3]~106_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & ((!\ula_|zx_keyboard_|keys[4][3]~132_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~103_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~14_combout = (\ula_|zx_keyboard_|keys[4][3]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~14 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [3] = (\ula_|zx_keyboard_|key_row[3]~15_combout & (\ula_|zx_keyboard_|key_row[3]~12_combout & (\ula_|zx_keyboard_|key_row[3]~13_combout & \ula_|zx_keyboard_|key_row[3]~14_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .datab(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .datac(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .datad(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [3]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y34_N1 +cycloneive_io_ibuf \kempston[0]~input ( + .i(kempston[0]), + .ibar(gnd), + .o(\kempston[0]~input_o )); +// synopsys translate_off +defparam \kempston[0]~input .bus_hold = "false"; +defparam \kempston[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \Selector8~4 ( +// Equation(s): +// \Selector8~4_combout = (\Selector14~18_combout & (\Selector14~17_combout & ((!\kempston[0]~input_o )))) # (!\Selector14~18_combout & (((\ula_|zx_keyboard_|key_row [3])) # (!\Selector14~17_combout ))) + + .dataa(\Selector14~18_combout ), + .datab(\Selector14~17_combout ), + .datac(\ula_|zx_keyboard_|key_row [3]), + .datad(\kempston[0]~input_o ), + .cin(gnd), + .combout(\Selector8~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~4 .lut_mask = 16'h51D9; +defparam \Selector8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \Selector8~9 ( +// Equation(s): +// \Selector8~9_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & (\Selector8~6_combout )) # (!\Selector8~4_combout & ((\Selector8~8_combout ))))) + + .dataa(\Selector8~6_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector8~8_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\Selector8~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~9 .lut_mask = 16'hEE30; +defparam \Selector8~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[3]~38 ( +// Equation(s): +// \D[3]~38_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector8~9_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), + .cin(gnd), + .combout(\D[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~38 .lut_mask = 16'hDD0D; +defparam \D[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\D[3]~38_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[3]~20_combout )))) # (!\D[3]~38_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[3]~20_combout ))) + + .dataa(\D[3]~38_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N31 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~19 ( +// Equation(s): +// \z80_|bus_control_|db[3]~19_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~19 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = ((\z80_|bus_control_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[3]~19_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[0]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|ir_|opcode[3]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[3]~feeder_combout = \z80_|bus_control_|db[3]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N13 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = (!\z80_|execute_|ctl_alu_op_low~11_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|pla_decode_|Equal56~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|setM1~41_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~60 ( +// Equation(s): +// \z80_|execute_|setM1~60_combout = (\z80_|execute_|ctl_mRead~17_combout & (((\z80_|ir_|opcode [1]) # (\z80_|ir_|opcode [2])) # (!\z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|setM1~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~60 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|setM1~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~60_combout ) # (!\z80_|execute_|setM1~42_combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~60_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~17 ( +// Equation(s): +// \z80_|execute_|nextM~17_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|fMRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~17 .lut_mask = 16'hA020; +defparam \z80_|execute_|nextM~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|nextM~5_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = ((\z80_|execute_|nextM~7_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|nextM~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|nextM~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hA080; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = (\z80_|execute_|nextM~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|nextM~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~17_combout ) # ((\z80_|execute_|nextM~8_combout ) # (\z80_|execute_|nextM~13_combout )) + + .dataa(\z80_|execute_|nextM~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|nextM~8_combout ), + .datad(\z80_|execute_|nextM~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|execute_|nextM~6_combout ) # (((\z80_|execute_|nextM~14_combout ) # (!\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ctl_mWrite~15_combout )) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|setM1~55_combout )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h1010; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N23 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FC; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N14 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y11_N25 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -51736,7 +55677,7 @@ dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .ena(\z80_|interrupts_|test1~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), @@ -51746,115 +55687,363 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X26_Y11_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|interrupts_|im1~feeder ( // Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) +// \z80_|interrupts_|im1~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), + .combout(\z80_|interrupts_|im1~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|im1~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|im1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & -// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N3 -dffeas \z80_|alu_flags_|flags_yf ( +// Location: FF_X27_Y12_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .d(\z80_|interrupts_|im1~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & -// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_yf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .dataa(\z80_|interrupts_|im1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|interrupts_|im2~q ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( // Equation(s): -// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~4_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|alu_control_|db[5]~15_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~16_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~5 ( // Equation(s): -// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) +// \z80_|bus_control_|db[0]~5_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_zero_oe~3_combout ))) - .dataa(\z80_|alu_control_|db[5]~16_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[0]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~5 .lut_mask = 16'hFFFE; +defparam \z80_|bus_control_|db[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y24_N0 +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hEE30; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51862,16 +56051,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51925,7 +56114,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y33_N0 +// Location: M9K_X33_Y6_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -51935,16 +56124,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51983,9 +56172,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51993,16 +56182,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -52055,7 +56244,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -52065,16 +56254,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -52113,361 +56302,112 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N2 -cycloneive_lcell_comb \Mux2~0 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), - .combout(\Mux2~0_combout ), + .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hB9A8; -defparam \Mux2~0 .sum_lutc_input = "datac"; +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \Mux2~1 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \Selector4~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Selector4~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), + .datad(\Selector4~0_combout ), .cin(gnd), - .combout(\Mux2~1_combout ), + .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; +defparam \Selector4~1 .lut_mask = 16'hDDA0; +defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \D[5]~25 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) +// \D[5]~25_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector4~1_combout ))))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datad(\Selector4~1_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .combout(\D[5]~25_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +defparam \D[5]~25 .lut_mask = 16'h3120; +defparam \D[5]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \D[5]~27 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) +// \D[5]~27_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~25_combout )) # (!\D[5]~26_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~25_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~26_combout ), + .datac(\D[5]~25_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\D[5]~27_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \D[5]~27 .lut_mask = 16'hA2F3; +defparam \D[5]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N30 -cycloneive_lcell_comb \D[5]~112 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[5]~40 ( // Equation(s): -// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) +// \D[5]~40_combout = (\D[5]~27_combout ) # (!\D[0]~49_combout ) - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[5]~97_combout ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[5]~27_combout ), .cin(gnd), - .combout(\D[5]~112_combout ), + .combout(\D[5]~40_combout ), .cout()); // synopsys translate_off -defparam \D[5]~112 .lut_mask = 16'hFB73; -defparam \D[5]~112 .sum_lutc_input = "datac"; +defparam \D[5]~40 .lut_mask = 16'hFF33; +defparam \D[5]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N8 -cycloneive_lcell_comb \D[5]~113 ( -// Equation(s): -// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[5]~112_combout ), - .datad(\z80_|data_pins_|dout [5]), - .cin(gnd), - .combout(\D[5]~113_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~113 .lut_mask = 16'hF151; -defparam \D[5]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 +// Location: LCCOMB_X26_Y16_N18 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~40_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[5]~16_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[5]~40_combout & (\z80_|bus_control_|db[5]~16_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[5]~113_combout ), + .dataa(\D[5]~40_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N25 +// Location: FF_X26_Y16_N19 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -52486,50 +56426,50 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|data_pins_|dout [5]), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N24 +// Location: LCCOMB_X26_Y15_N16 cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|alu_control_|db[5]~17_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[5]~14_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hA0AA; defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N25 +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Equation(s): +// \z80_|bus_control_|db[5]~16_combout = ((\z80_|bus_control_|db[5]~15_combout & ((\z80_|alu_control_|db[5]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N21 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~15_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~16_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [5]), @@ -52539,991 +56479,75 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) - - .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|nextM~3_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) - - .dataa(\z80_|execute_|nextM~7_combout ), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mWrite~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N23 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N27 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N31 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N21 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # -// (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~22_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|pla_decode_|Equal4~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) - - .dataa(\z80_|execute_|setM1~55_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~31_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|setM1~20_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~28_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & -// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|interrupts_|test1~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) - - .dataa(\z80_|execute_|setM1~8_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) - - .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~12_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N16 +// Location: LCCOMB_X31_Y15_N8 cycloneive_lcell_comb \z80_|execute_|setM1~43 ( // Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|setM1~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h1515; defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|setM1~42_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|execute_|setM1~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|setM1~50_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 +// Location: LCCOMB_X36_Y11_N28 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~55_combout )) - .dataa(gnd), + .dataa(\z80_|execute_|nextM~15_combout ), .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h4040; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N19 +// Location: FF_X36_Y11_N29 dffeas \z80_|sequencer_|T6 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), @@ -53542,59 +56566,625 @@ defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; defparam \z80_|sequencer_|T6 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( // Equation(s): -// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & -// (!\z80_|execute_|setM1~41_combout ))) +// \z80_|execute_|setM1~16_combout = (!\z80_|execute_|ctl_alu_oe~5_combout & (!\z80_|pla_decode_|Equal1~3_combout & (!\z80_|pla_decode_|Equal77~1_combout & !\z80_|pla_decode_|Equal2~4_combout ))) - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|sequencer_|T6~q ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|setM1~40_combout ), + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), + .combout(\z80_|execute_|setM1~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|interrupts_|test1~3_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~17_combout )) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h080C; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~13_combout & (\z80_|execute_|setM1~45_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|pla_decode_|Equal5~2_combout & \z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 cycloneive_lcell_comb \z80_|execute_|setM1~53 ( // Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|setM1~18_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|setM1~48_combout ))) - .dataa(\z80_|execute_|setM1~35_combout ), - .datab(\z80_|execute_|setM1~19_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~18_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~48_combout ), .cin(gnd), .combout(\z80_|execute_|setM1~53_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h8000; defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) +// \z80_|execute_|setM1~54_combout = (\z80_|execute_|setM1~43_combout & (((\z80_|execute_|setM1~42_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~43_combout & ((\z80_|sequencer_|T6~q ) # ((\z80_|execute_|setM1~42_combout & +// \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'hCCCE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~24_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hE0A0; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|fMWrite~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|setM1~57_combout & (((\z80_|execute_|ctl_reg_in_hi~6_combout & !\z80_|execute_|setM1~25_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~57_combout & +// (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|setM1~25_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (((\z80_|pla_decode_|Equal40~1_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~10_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & +// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|setM1~26_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~29_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hCCDC; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~13_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (((\z80_|execute_|setM1~31_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~32_combout )) # (!\z80_|execute_|setM1~58_combout ) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~32_combout ), + .datac(\z80_|execute_|setM1~31_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~34_combout ), + .datac(\z80_|execute_|setM1~35_combout ), + .datad(\z80_|execute_|setM1~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|execute_|ctl_mRead~9_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h2A0A; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout ) # ((\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|setM1~36_combout ) # ((\z80_|execute_|setM1~56_combout ) # (\z80_|execute_|setM1~23_combout ))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|setM1~56_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMWrite~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~12_combout ) # (((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|setM1~13_combout )) # (!\z80_|execute_|nextM~4_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|sequencer_|M5~q ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|execute_|ctl_sw_4d~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_M4_ff~q & +// (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCF0F; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|execute_|setM1~11_combout ) # (((\z80_|execute_|setM1~14_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~14_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|setM1~19_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~15_combout ) # (((!\z80_|execute_|setM1~18_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~20_combout )) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|setM1~20_combout ), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hBFBB; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|setM1~37_combout & (!\z80_|execute_|setM1~21_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~54_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h000B; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~15_combout ))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N15 +// Location: FF_X36_Y11_N7 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -53613,27 +57203,28 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & +// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hC1F0; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N29 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), +// Location: FF_X27_Y15_N23 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53642,65 +57233,156 @@ dffeas \z80_|sequencer_|DFFE_M2_ff ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .q(\z80_|resets_|clrpc_int~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y16_N20 +// Location: FF_X26_Y9_N3 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N5 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y9_N1 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y16_N21 +// Location: FF_X29_Y9_N17 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53719,332 +57401,561 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N30 -cycloneive_lcell_comb \D[0]~66 ( +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 ( // Equation(s): -// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[0]~58_combout ), - .datad(\D[0]~120_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~66_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cout()); // synopsys translate_off -defparam \D[0]~66 .lut_mask = 16'hF3C0; -defparam \D[0]~66 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N18 -cycloneive_lcell_comb \D[0]~67 ( +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 ( // Equation(s): -// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\Equal2~1_combout ), - .datad(\D[0]~66_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cin(gnd), - .combout(\D[0]~67_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), .cout()); // synopsys translate_off -defparam \D[0]~67 .lut_mask = 16'hDD0D; -defparam \D[0]~67 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .lut_mask = 16'hF388; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N24 -cycloneive_lcell_comb \D[0]~121 ( +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \Selector14~15 ( // Equation(s): -// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \Selector14~15_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # +// (!\z80_|address_pins_|abus[14]~22_combout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~121_combout ), + .combout(\Selector14~15_combout ), .cout()); // synopsys translate_off -defparam \D[0]~121 .lut_mask = 16'hFF20; -defparam \D[0]~121 .sum_lutc_input = "datac"; +defparam \Selector14~15 .lut_mask = 16'hBA98; +defparam \Selector14~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N16 -cycloneive_lcell_comb \D[1]~68 ( +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \Selector14~16 ( // Equation(s): -// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) +// \Selector14~16_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector14~15_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\Selector14~15_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector14~15_combout )))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[1]~34_combout ), - .datad(\D[1]~118_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\Selector14~15_combout ), .cin(gnd), - .combout(\D[1]~68_combout ), + .combout(\Selector14~16_combout ), .cout()); // synopsys translate_off -defparam \D[1]~68 .lut_mask = 16'hF3C0; -defparam \D[1]~68 .sum_lutc_input = "datac"; +defparam \Selector14~16 .lut_mask = 16'hBBC0; +defparam \Selector14~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N14 -cycloneive_lcell_comb \D[1]~69 ( +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \D[0]~15 ( // Equation(s): -// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) +// \D[0]~15_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & ((\Selector14~8_combout & ((\Selector14~16_combout ))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout +// )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), + .datac(\Selector14~16_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\D[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~15 .lut_mask = 16'hFA44; +defparam \D[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \D[0]~16 ( +// Equation(s): +// \D[0]~16_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~15_combout ) # (!\Equal5~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[0]~15_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Equal5~1_combout ), + .datad(\D[0]~15_combout ), + .cin(gnd), + .combout(\D[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~16 .lut_mask = 16'hBB0B; +defparam \D[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \Selector12~12 ( +// Equation(s): +// \Selector12~12_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~12_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~12 .lut_mask = 16'hD9C8; +defparam \Selector12~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N2 +cycloneive_lcell_comb \Selector12~13 ( +// Equation(s): +// \Selector12~13_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector12~12_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector12~12_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector12~12_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector12~12_combout ), + .cin(gnd), + .combout(\Selector12~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~13 .lut_mask = 16'hDDA0; +defparam \Selector12~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \D[1]~17 ( +// Equation(s): +// \D[1]~17_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & ((\Selector12~4_combout & ((\Selector12~13_combout ))) # (!\Selector12~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout +// )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .datac(\Selector12~4_combout ), + .datad(\Selector12~13_combout ), + .cin(gnd), + .combout(\D[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~17 .lut_mask = 16'hF4A4; +defparam \D[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \D[1]~18 ( +// Equation(s): +// \D[1]~18_combout = (\Equal5~1_combout & (\D[1]~17_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), .datab(\z80_|data_pins_|dout [1]), - .datac(\Equal2~1_combout ), - .datad(\D[1]~68_combout ), - .cin(gnd), - .combout(\D[1]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~69 .lut_mask = 16'hDD0D; -defparam \D[1]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N16 -cycloneive_lcell_comb \D[2]~70 ( -// Equation(s): -// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) - - .dataa(gnd), - .datab(\D[2]~46_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~70 .lut_mask = 16'hCFC0; -defparam \D[2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N14 -cycloneive_lcell_comb \D[2]~71 ( -// Equation(s): -// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~70_combout ), - .cin(gnd), - .combout(\D[2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~71 .lut_mask = 16'hF531; -defparam \D[2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N24 -cycloneive_lcell_comb \D[3]~83 ( -// Equation(s): -// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [3]), - .datad(gnd), - .cin(gnd), - .combout(\D[3]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~83 .lut_mask = 16'hF5F5; -defparam \D[3]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \D[3]~84 ( -// Equation(s): -// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) - - .dataa(\D[3]~122_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[3]~82_combout ), - .datad(\D[3]~83_combout ), - .cin(gnd), - .combout(\D[3]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~84 .lut_mask = 16'hFB00; -defparam \D[3]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N20 -cycloneive_lcell_comb \D[4]~95 ( -// Equation(s): -// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) - - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~95 .lut_mask = 16'hB8B8; -defparam \D[4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N6 -cycloneive_lcell_comb \D[4]~96 ( -// Equation(s): -// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\Equal2~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[4]~95_combout ), + .datad(\D[1]~17_combout ), .cin(gnd), - .combout(\D[4]~96_combout ), + .combout(\D[1]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~96 .lut_mask = 16'hAF23; -defparam \D[4]~96 .sum_lutc_input = "datac"; +defparam \D[1]~18 .lut_mask = 16'hCF45; +defparam \D[1]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N18 -cycloneive_lcell_comb \D[5]~126 ( +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \D[2]~19 ( // Equation(s): -// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) +// \D[2]~19_combout = (\Selector10~2_combout & (((\Selector10~1_combout ) # (\Equal5~0_combout )))) # (!\Selector10~2_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout & ((!\Equal5~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Selector10~2_combout ), + .datac(\Selector10~1_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~19 .lut_mask = 16'hCCE2; +defparam \D[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \D[2]~20 ( +// Equation(s): +// \D[2]~20_combout = (\Equal5~1_combout & (\D[2]~19_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [2]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [2]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[2]~19_combout ), + .cin(gnd), + .combout(\D[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~20 .lut_mask = 16'hCF45; +defparam \D[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \Selector8~2 ( +// Equation(s): +// \Selector8~2_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~2 .lut_mask = 16'hCBC8; +defparam \Selector8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \Selector8~3 ( +// Equation(s): +// \Selector8~3_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~2_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~2_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~2_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~2_combout ), + .cin(gnd), + .combout(\Selector8~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~3 .lut_mask = 16'hF388; +defparam \Selector8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[3]~21 ( +// Equation(s): +// \D[3]~21_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & ((\Selector8~3_combout ))) # (!\Selector8~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datac(\Selector8~3_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\D[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~21 .lut_mask = 16'hFA44; +defparam \D[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~22 ( +// Equation(s): +// \D[3]~22_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~21_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[3]~21_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[3]~21_combout ), + .cin(gnd), + .combout(\D[3]~22_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~22 .lut_mask = 16'hAF23; +defparam \D[3]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[4]~23 ( +// Equation(s): +// \D[4]~23_combout = (\Selector6~6_combout & ((\Selector6~1_combout ) # ((\Equal5~0_combout )))) # (!\Selector6~6_combout & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout & !\Equal5~0_combout )))) + + .dataa(\Selector6~1_combout ), + .datab(\Selector6~6_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~23 .lut_mask = 16'hCCB8; +defparam \D[4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[4]~24 ( +// Equation(s): +// \D[4]~24_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~23_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~23_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\D[4]~23_combout ), + .cin(gnd), + .combout(\D[4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~24 .lut_mask = 16'hDD0D; +defparam \D[4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[6]~32 ( +// Equation(s): +// \D[6]~32_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~32 .lut_mask = 16'hE3E0; +defparam \D[6]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[6]~33 ( +// Equation(s): +// \D[6]~33_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~32_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~32_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~32_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~32_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~33 .lut_mask = 16'hF838; +defparam \D[6]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \D[6]~29 ( +// Equation(s): +// \D[6]~29_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~29 .lut_mask = 16'hE6A2; +defparam \D[6]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[6]~30 ( +// Equation(s): +// \D[6]~30_combout = (\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~29_combout ))))) # (!\z80_|address_pins_|abus[15]~23_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~29_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~29_combout ), + .cin(gnd), + .combout(\D[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~30 .lut_mask = 16'h44B8; +defparam \D[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \D[6]~31 ( +// Equation(s): +// \D[6]~31_combout = (\D[6]~29_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~30_combout )))) # (!\D[6]~29_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~30_combout )))) + + .dataa(\D[6]~29_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~30_combout ), + .cin(gnd), + .combout(\D[6]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~31 .lut_mask = 16'h99A8; +defparam \D[6]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[6]~50 ( +// Equation(s): +// \D[6]~50_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~33_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~31_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~33_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .datac(\D[6]~33_combout ), + .datad(\D[6]~31_combout ), .cin(gnd), - .combout(\D[5]~126_combout ), + .combout(\D[6]~50_combout ), .cout()); // synopsys translate_off -defparam \D[5]~126 .lut_mask = 16'hFB40; -defparam \D[5]~126 .sum_lutc_input = "datac"; +defparam \D[6]~50 .lut_mask = 16'hF4B0; +defparam \D[6]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N0 -cycloneive_lcell_comb \D[5]~98 ( +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \D[6]~34 ( // Equation(s): -// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) +// \D[6]~34_combout = (\Equal5~0_combout & (\D[6]~28_combout & (\Equal3~2_combout ))) # (!\Equal5~0_combout & (((\D[6]~50_combout )))) - .dataa(\z80_|data_pins_|dout [5]), - .datab(\D[5]~97_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[5]~126_combout ), + .dataa(\D[6]~28_combout ), + .datab(\Equal3~2_combout ), + .datac(\Equal5~0_combout ), + .datad(\D[6]~50_combout ), .cin(gnd), - .combout(\D[5]~98_combout ), + .combout(\D[6]~34_combout ), .cout()); // synopsys translate_off -defparam \D[5]~98 .lut_mask = 16'hAF23; -defparam \D[5]~98 .sum_lutc_input = "datac"; +defparam \D[6]~34 .lut_mask = 16'h8F80; +defparam \D[6]~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N18 -cycloneive_lcell_comb \D[6]~105 ( +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[6]~35 ( // Equation(s): -// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) - - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~105 .lut_mask = 16'hFC30; -defparam \D[6]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N0 -cycloneive_lcell_comb \D[6]~106 ( -// Equation(s): -// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) +// \D[6]~35_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~34_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~34_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [6]), - .datab(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~105_combout ), + .datad(\D[6]~34_combout ), .cin(gnd), - .combout(\D[6]~106_combout ), + .combout(\D[6]~35_combout ), .cout()); // synopsys translate_off -defparam \D[6]~106 .lut_mask = 16'hAF23; -defparam \D[6]~106 .sum_lutc_input = "datac"; +defparam \D[6]~35 .lut_mask = 16'hAF23; +defparam \D[6]~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N10 -cycloneive_lcell_comb \D[7]~128 ( -// Equation(s): -// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~128_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~128 .lut_mask = 16'hF2D0; -defparam \D[7]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N16 -cycloneive_lcell_comb \D[7]~107 ( -// Equation(s): -// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[5]~97_combout ), - .datad(\D[7]~128_combout ), - .cin(gnd), - .combout(\D[7]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~107 .lut_mask = 16'hBB0B; -defparam \D[7]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 +// Location: LCCOMB_X36_Y11_N2 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; +defparam \z80_|nM1_int~3 .lut_mask = 16'hE0E0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N13 +// Location: FF_X36_Y11_N3 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -54063,7 +57974,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X26_Y12_N22 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -54080,7 +57991,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N5 +// Location: FF_X26_Y12_N23 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -54099,7 +58010,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N27 +// Location: FF_X26_Y12_N21 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -54118,32 +58029,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N26 +// Location: LCCOMB_X26_Y12_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|wait_mwr~q ), - .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .datab(\z80_|memory_ifc_|wait_mwr~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N2 +// Location: LCCOMB_X26_Y12_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ))) - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(\z80_|memory_ifc_|wait_mrd~q ), - .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -54165,7 +58076,24 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -54182,7 +58110,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X3_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -54201,14 +58129,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X3_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -54219,7 +58147,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N9 +// Location: FF_X3_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -54238,7 +58166,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X3_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -54256,7 +58184,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N11 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -54275,7 +58203,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X3_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -54293,7 +58221,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -54312,24 +58240,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) - - .dataa(\ula_|i2c_loader_|divider [3]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [1]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -54347,7 +58258,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -54366,7 +58277,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X3_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -54383,7 +58294,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X3_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -54402,60 +58313,41 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N30 +// Location: LCCOMB_X3_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), .datac(\ula_|i2c_loader_|divider [4]), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 -dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|scl_out~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N23 +// Location: FF_X1_Y23_N19 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -54474,7 +58366,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -54491,7 +58383,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -54510,24 +58402,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0CC0; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N31 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -54546,75 +58438,174 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: FF_X1_Y23_N5 +dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|scl_out~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N24 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hA0A0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~4_combout ), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; -defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEAAE; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X2_Y23_N15 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54633,67 +58624,135 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hCCC0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y22_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|state.Pause~0_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|nbit[0]~1_combout )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~0_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N27 +// Location: LCCOMB_X1_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|Mux42~0_combout & !\ula_|i2c_loader_|WideAnd0~combout ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0040; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~4_combout ), + .d(\ula_|i2c_loader_|nbit~5_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [0]), @@ -54703,43 +58762,7 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y25_N1 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y25_N28 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) @@ -54756,75 +58779,41 @@ defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 +// Location: LCCOMB_X2_Y22_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N4 +// Location: LCCOMB_X2_Y22_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|state~27_combout ), + .datab(\ula_|i2c_loader_|state~26_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), + .datad(\ula_|i2c_loader_|state~27_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X2_Y22_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54843,24 +58832,60 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N12 +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): // \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [1]), + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|nbit [2]), .datad(\ula_|i2c_loader_|nbit [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N13 +// Location: FF_X2_Y23_N13 dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~0_combout ), @@ -54869,7 +58894,7 @@ dffeas \ula_|i2c_loader_|nbit[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [2]), @@ -54879,32 +58904,32 @@ defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N30 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [0] & \ula_|i2c_loader_|state.Data~q ))) .dataa(\ula_|i2c_loader_|nbit [2]), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0100; defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N2 +// Location: LCCOMB_X2_Y22_N16 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Idle~0_combout ), .cout()); @@ -54913,7 +58938,7 @@ defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N16 +// Location: LCCOMB_X2_Y22_N6 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( // Equation(s): // \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) @@ -54930,25 +58955,25 @@ defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y22_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Ack~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N25 +// Location: FF_X2_Y22_N3 dffeas \ula_|i2c_loader_|state.Ack ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Ack~1_combout ), @@ -54967,121 +58992,24 @@ defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2c_loader_|nbyte~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) +// \ula_|i2c_loader_|state.Stop~0_combout = (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N6 +// Location: LCCOMB_X2_Y22_N4 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): // \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # @@ -55099,7 +59027,7 @@ defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N7 +// Location: FF_X2_Y22_N5 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -55118,24 +59046,24 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 +// Location: LCCOMB_X2_Y22_N22 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Stop~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h5FCC; defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -55153,41 +59081,41 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~5 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\I2C_SDAT~input_o ), + .datad(\ula_|i2c_loader_|nbyte [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .combout(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbyte[0]~5 .lut_mask = 16'hFAD8; +defparam \ula_|i2c_loader_|nbyte[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|nbyte[0]~5_combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h2000; defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|thisbyte[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), @@ -55206,25 +59134,25 @@ defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N20 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) // \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N21 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|thisbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), @@ -55243,25 +59171,25 @@ defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) // \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: FF_X3_Y23_N9 dffeas \ula_|i2c_loader_|thisbyte[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), @@ -55280,25 +59208,25 @@ defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X3_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) // \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N25 +// Location: FF_X3_Y23_N11 dffeas \ula_|i2c_loader_|thisbyte[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), @@ -55318,40 +59246,23 @@ defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N27 +// Location: FF_X3_Y23_N13 dffeas \ula_|i2c_loader_|thisbyte[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), @@ -55370,94 +59281,111 @@ defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N22 +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0004; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N12 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|Equal2~0_combout ) # (!\ula_|i2c_loader_|thisbyte [4]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~2_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0AAA; defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X2_Y22_N10 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Stop~q ), + .dataa(gnd), .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(gnd), + .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N26 +// Location: LCCOMB_X2_Y22_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Pause~1_combout )))) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h0ACE; defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y22_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF373; defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N20 +// Location: LCCOMB_X2_Y22_N26 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # // (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~3_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE2F0; defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N21 +// Location: FF_X2_Y22_N27 dffeas \ula_|i2c_loader_|state.Pause ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Pause~6_combout ), @@ -55476,25 +59404,25 @@ defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N30 +// Location: LCCOMB_X2_Y22_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( // Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|state.Start~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|state.Pause~q & \ula_|i2c_loader_|Mux42~0_combout ))) # // (!\ula_|i2c_loader_|state.Idle~q ) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h3BF3; defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N31 +// Location: FF_X2_Y22_N29 dffeas \ula_|i2c_loader_|state.Start ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state~25_combout ), @@ -55513,38 +59441,38 @@ defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Start .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # // ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hC3EA; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~1_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC0C3; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55586,186 +59514,152 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|shiftreg~19_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~13_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hFF10; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte [4])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|shiftreg~22_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h3530; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [3]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hF404; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h1010; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~27_combout = (\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; -defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - - .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datab(\ula_|i2c_loader_|state~24_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; -defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .lut_mask = 16'hEEE4; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~28 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~28_combout = (\ula_|i2c_loader_|shiftreg[0]~27_combout & (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Idle~q & !\ula_|i2c_loader_|WideAnd0~combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~27_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .lut_mask = 16'h0080; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N21 +// Location: FF_X2_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55775,85 +59669,136 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg~23_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [0]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; -defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h8090; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y22_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~6 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~6_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~6 .lut_mask = 16'h0033; +defparam \ula_|i2c_loader_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~6_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((!\ula_|i2c_loader_|thisbyte [0] & \ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~6_combout ), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8C88; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [1]) # ((!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state~24_combout )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'h8CBF; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~9_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state~24_combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h2E2F; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X2_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & -// !\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (!\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; -defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 +// Location: FF_X2_Y24_N17 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~24_combout ), + .d(\ula_|i2c_loader_|shiftreg~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55863,33 +59808,67 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) - .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h5030; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N11 +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~18_combout ))) # (!\ula_|i2c_loader_|shiftreg~6_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~6_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h2EFF; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hCF00; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~21_combout ), + .d(\ula_|i2c_loader_|shiftreg~20_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55899,84 +59878,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg~17_combout & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~17_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAE04; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), - .datab(\ula_|i2c_loader_|shiftreg~15_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [2]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; -defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N23 +// Location: FF_X2_Y24_N19 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~27_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55986,67 +59914,33 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE54; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|shiftreg~14_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [3]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~16_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N15 +// Location: FF_X2_Y24_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -56056,33 +59950,50 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - .dataa(\ula_|i2c_loader_|Mux35~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|shiftreg [4]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h40C0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N5 +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [4])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg [4]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hBB88; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~13_combout ), + .d(\ula_|i2c_loader_|shiftreg~12_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -56092,33 +60003,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), - .datab(\ula_|i2c_loader_|Mux35~0_combout ), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [5]), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -56128,33 +60039,33 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) +// \ula_|i2c_loader_|shiftreg[7]~7_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|shiftreg [6]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .combout(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N29 +// Location: FF_X2_Y24_N1 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .d(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -56164,16 +60075,16 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); @@ -56182,14 +60093,14 @@ defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~6_combout & !\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~6_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), @@ -56199,38 +60110,38 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h0C0E; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2F4; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56239,15 +60150,15 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56391,735 +60302,118 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux38~0 ( -// Equation(s): -// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) - - .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), - .datab(\Equal2~1_combout ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Mux39~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux38~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; -defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y12_N15 -dffeas \sdram_|r.rd_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux38~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rd_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rd_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N0 -cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( -// Equation(s): -// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) -// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\sdram_|r.rf_counter[0]~12_combout ), - .cout(\sdram_|r.rf_counter[0]~13 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; -defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N26 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.address[3]~6_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.rf_counter[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; -defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N1 -dffeas \sdram_|r.rf_counter[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N2 -cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( -// Equation(s): -// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) -// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [1]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[0]~13 ), - .combout(\sdram_|r.rf_counter[1]~14_combout ), - .cout(\sdram_|r.rf_counter[1]~15 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N3 -dffeas \sdram_|r.rf_counter[1] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[1]~14_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N4 -cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( -// Equation(s): -// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) -// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [2]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[1]~15 ), - .combout(\sdram_|r.rf_counter[2]~16_combout ), - .cout(\sdram_|r.rf_counter[2]~17 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N5 -dffeas \sdram_|r.rf_counter[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[2]~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N6 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) -// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[2]~17 ), - .combout(\sdram_|r.rf_counter[3]~18_combout ), - .cout(\sdram_|r.rf_counter[3]~19 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N7 -dffeas \sdram_|r.rf_counter[3] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[3]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N8 -cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( -// Equation(s): -// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) -// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [4]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[3]~19 ), - .combout(\sdram_|r.rf_counter[4]~20_combout ), - .cout(\sdram_|r.rf_counter[4]~21 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N9 -dffeas \sdram_|r.rf_counter[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[4]~20_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N10 -cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( -// Equation(s): -// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) -// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[4]~21 ), - .combout(\sdram_|r.rf_counter[5]~22_combout ), - .cout(\sdram_|r.rf_counter[5]~23 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N11 -dffeas \sdram_|r.rf_counter[5] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[5]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N12 -cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( -// Equation(s): -// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) -// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) - - .dataa(\sdram_|r.rf_counter [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[5]~23 ), - .combout(\sdram_|r.rf_counter[6]~24_combout ), - .cout(\sdram_|r.rf_counter[6]~25 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; -defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N13 -dffeas \sdram_|r.rf_counter[6] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N14 -cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( -// Equation(s): -// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) -// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [7]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[6]~25 ), - .combout(\sdram_|r.rf_counter[7]~26_combout ), - .cout(\sdram_|r.rf_counter[7]~27 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N15 -dffeas \sdram_|r.rf_counter[7] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[7]~26_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N24 -cycloneive_lcell_comb \sdram_|Equal0~1 ( -// Equation(s): -// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(\sdram_|r.rf_counter [7]), - .datac(\sdram_|r.rf_counter [4]), - .datad(\sdram_|r.rf_counter [6]), - .cin(gnd), - .combout(\sdram_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; -defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N16 -cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( -// Equation(s): -// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) -// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [8]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[7]~27 ), - .combout(\sdram_|r.rf_counter[8]~28_combout ), - .cout(\sdram_|r.rf_counter[8]~29 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N17 -dffeas \sdram_|r.rf_counter[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[8]~28_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal0~0 ( -// Equation(s): -// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(\sdram_|r.rf_counter [0]), - .datac(\sdram_|r.rf_counter [2]), - .datad(\sdram_|r.rf_counter [1]), - .cin(gnd), - .combout(\sdram_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; -defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N18 -cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( -// Equation(s): -// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\sdram_|r.rf_counter [9]), - .cin(\sdram_|r.rf_counter[8]~29 ), - .combout(\sdram_|r.rf_counter[9]~30_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; -defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N19 -dffeas \sdram_|r.rf_counter[9] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[9]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [9]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N22 -cycloneive_lcell_comb \sdram_|Equal0~2 ( -// Equation(s): -// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) - - .dataa(\sdram_|Equal0~1_combout ), - .datab(\sdram_|r.rf_counter [8]), - .datac(\sdram_|Equal0~0_combout ), - .datad(\sdram_|r.rf_counter [9]), - .cin(gnd), - .combout(\sdram_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; -defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N28 -cycloneive_lcell_comb \sdram_|Mux13~8 ( -// Equation(s): -// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|Mux13~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; -defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N20 -cycloneive_lcell_comb \sdram_|Mux37~0 ( -// Equation(s): -// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux13~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux37~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; -defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N21 -dffeas \sdram_|r.rf_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux37~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rf_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N14 -cycloneive_lcell_comb \sdram_|Mux4~0 ( -// Equation(s): -// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; -defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux4~1 ( -// Equation(s): -// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; -defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N2 -cycloneive_lcell_comb \sdram_|Mux4~2 ( -// Equation(s): -// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; -defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N30 +// Location: LCCOMB_X21_Y19_N4 cycloneive_lcell_comb \sdram_|Mux4~3 ( // Equation(s): -// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) +// \sdram_|Mux4~3_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [6])) - .dataa(\sdram_|Mux4~1_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux4~2_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux4~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .lut_mask = 16'hAA50; defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N31 -dffeas \sdram_|r.state[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux4~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.state [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.state[8] .is_wysiwyg = "true"; -defparam \sdram_|r.state[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N6 -cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~0 ( // Equation(s): -// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) +// \sdram_|Mux4~0_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4]))) .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.act_row[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; -defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N18 -cycloneive_lcell_comb \sdram_|process_0~2 ( -// Equation(s): -// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) - - .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|process_0~2_combout ), + .combout(\sdram_|Mux4~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; -defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux4~0 .lut_mask = 16'hAF00; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N0 -cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( // Equation(s): -// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - .dataa(\sdram_|r.act_row[1]~0_combout ), - .datab(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.state [6]), + .datab(gnd), .datac(\sdram_|r.state [7]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.act_row[1]~1_combout ), + .combout(\sdram_|r.address[3]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; -defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N9 -dffeas \sdram_|r.act_row[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\z80_|address_pins_|abus[15]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [4]), - .prn(vcc)); +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[4] .power_up = "low"; +defparam \sdram_|Mux7~2 .lut_mask = 16'h0B00; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N23 -dffeas \sdram_|r.act_row[3] ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [6] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hCC00; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h5500; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \sdram_|r.act_row[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N20 -cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( -// Equation(s): -// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\sdram_|r.act_row[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; -defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y13_N21 -dffeas \sdram_|r.act_row[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.act_row[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.act_row [2]), @@ -57129,115 +60423,80 @@ defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; defparam \sdram_|r.act_row[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N22 +// Location: FF_X21_Y14_N11 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 cycloneive_lcell_comb \sdram_|Equal7~1 ( // Equation(s): -// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & -// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\sdram_|r.act_row [3]), - .datad(\sdram_|r.act_row [2]), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\sdram_|r.act_row [2]), + .datad(\sdram_|r.act_row [3]), .cin(gnd), .combout(\sdram_|Equal7~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .lut_mask = 16'h8241; defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N3 -dffeas \sdram_|r.act_row[1] ( +// Location: FF_X21_Y14_N1 +dffeas \sdram_|r.act_row[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .asdata(\z80_|address_pins_|abus[15]~23_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.act_row [1]), + .q(\sdram_|r.act_row [4]), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[1] .power_up = "low"; +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X21_Y13_N13 -dffeas \sdram_|r.act_row[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[11]~19_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N2 -cycloneive_lcell_comb \sdram_|Equal7~0 ( -// Equation(s): -// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & -// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\sdram_|r.act_row [1]), - .datad(\sdram_|r.act_row [0]), - .cin(gnd), - .combout(\sdram_|Equal7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; -defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal7~2 ( -// Equation(s): -// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\sdram_|r.act_row [4]), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|Equal7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; -defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N4 +// Location: LCCOMB_X20_Y15_N20 cycloneive_lcell_comb \sdram_|Mux39~0 ( // Equation(s): -// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) +// \sdram_|Mux39~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux39~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .lut_mask = 16'h8402; defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N12 +// Location: LCCOMB_X20_Y15_N14 cycloneive_lcell_comb \sdram_|Mux39~1 ( // Equation(s): // \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) @@ -57254,24 +60513,24 @@ defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N24 +// Location: LCCOMB_X21_Y15_N30 cycloneive_lcell_comb \sdram_|Mux39~2 ( // Equation(s): -// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.wr_pending~q & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~23_combout ))) - .dataa(\sdram_|Mux39~1_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), .datac(\sdram_|r.wr_pending~q ), - .datad(\ExtRamWE~0_combout ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), .combout(\sdram_|Mux39~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .lut_mask = 16'hF808; defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y12_N25 +// Location: FF_X21_Y15_N31 dffeas \sdram_|r.wr_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux39~2_combout ), @@ -57290,180 +60549,44 @@ defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; defparam \sdram_|r.wr_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux38~3 ( // Equation(s): -// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) +// \sdram_|Mux38~3_combout = (!\sdram_|r.rd_pending~q & (((!\z80_|memory_ifc_|nIORQ_out~0_combout & \z80_|address_pins_|DFFE_apin_latch [15])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux9~8_combout ), + .combout(\sdram_|Mux38~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; -defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~3 .lut_mask = 16'h0073; +defparam \sdram_|Mux38~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux38~2 ( // Equation(s): -// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) +// \sdram_|Mux38~2_combout = (\Equal5~1_combout & ((\sdram_|Mux38~3_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) # (!\Equal5~1_combout & (((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|Mux38~3_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), - .combout(\sdram_|Mux9~9_combout ), + .combout(\sdram_|Mux38~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; -defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~2 .lut_mask = 16'hF888; +defparam \sdram_|Mux38~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N26 -cycloneive_lcell_comb \sdram_|Mux6~3 ( -// Equation(s): -// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux9~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; -defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N0 -cycloneive_lcell_comb \sdram_|Mux6~4 ( -// Equation(s): -// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) - - .dataa(gnd), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux6~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; -defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N6 -cycloneive_lcell_comb \sdram_|Mux6~2 ( -// Equation(s): -// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; -defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N10 -cycloneive_lcell_comb \sdram_|Mux6~5 ( -// Equation(s): -// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) - - .dataa(\sdram_|Mux6~3_combout ), - .datab(\sdram_|Mux6~4_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|Mux6~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; -defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N8 -cycloneive_lcell_comb \sdram_|process_0~3 ( -// Equation(s): -// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|process_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; -defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux6~0 ( -// Equation(s): -// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|process_0~3_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; -defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N16 -cycloneive_lcell_comb \sdram_|Mux6~1 ( -// Equation(s): -// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux6~0_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; -defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N24 -cycloneive_lcell_comb \sdram_|Mux6~6 ( -// Equation(s): -// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux6~5_combout ), - .datad(\sdram_|Mux6~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; -defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y15_N25 -dffeas \sdram_|r.state[6] ( +// Location: FF_X21_Y15_N21 +dffeas \sdram_|r.rd_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux6~6_combout ), + .d(\sdram_|Mux38~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57472,175 +60595,73 @@ dffeas \sdram_|r.state[6] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.state [6]), + .q(\sdram_|r.rd_pending~q ), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.state[6] .is_wysiwyg = "true"; -defparam \sdram_|r.state[6] .power_up = "low"; +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N12 -cycloneive_lcell_comb \sdram_|r.address[3]~6 ( -// Equation(s): -// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; -defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux7~2 ( -// Equation(s): -// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) - - .dataa(\sdram_|r.address[3]~6_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; -defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N12 +// Location: LCCOMB_X21_Y14_N22 cycloneive_lcell_comb \sdram_|n~3 ( // Equation(s): -// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) +// \sdram_|n~3_combout = (\sdram_|r.wr_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ ((!\sdram_|r.act_row [4])))) # (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) - .dataa(gnd), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Equal7~2_combout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|n~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .lut_mask = 16'h9990; defparam \sdram_|n~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N6 -cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \sdram_|n~4 ( // Equation(s): -// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.state [6]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; -defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N28 -cycloneive_lcell_comb \sdram_|Mux7~4 ( -// Equation(s): -// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) - - .dataa(\sdram_|Mux7~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux7~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; -defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N10 -cycloneive_lcell_comb \sdram_|Mux7~5 ( -// Equation(s): -// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux7~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux7~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; -defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux23~0 ( -// Equation(s): -// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) +// \sdram_|n~4_combout = (\sdram_|Equal7~1_combout & (\sdram_|n~3_combout & \sdram_|Equal7~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(gnd), + .datab(\sdram_|Equal7~1_combout ), + .datac(\sdram_|n~3_combout ), + .datad(\sdram_|Equal7~0_combout ), .cin(gnd), - .combout(\sdram_|Mux23~0_combout ), + .combout(\sdram_|n~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; -defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +defparam \sdram_|n~4 .lut_mask = 16'hC000; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \sdram_|Mux10~9 ( // Equation(s): -// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) +// \sdram_|Mux10~9_combout = (!\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|Mux13~7_combout ), + .combout(\sdram_|Mux10~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; -defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux10~9 .lut_mask = 16'h00EF; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux10~10 ( -// Equation(s): -// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.rf_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; -defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N18 +// Location: LCCOMB_X19_Y17_N20 cycloneive_lcell_comb \sdram_|Mux7~1 ( // Equation(s): -// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~9_combout ) # (!\sdram_|r.state [7])))) .dataa(\sdram_|Mux23~0_combout ), .datab(\sdram_|Mux13~7_combout ), .datac(\sdram_|r.state [7]), - .datad(\sdram_|Mux10~10_combout ), + .datad(\sdram_|Mux10~9_combout ), .cin(gnd), .combout(\sdram_|Mux7~1_combout ), .cout()); @@ -57649,24 +60670,75 @@ defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N22 +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h3F00; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.wr_pending~q & \sdram_|Mux7~3_combout ))) # (!\sdram_|r.state [6] & (\sdram_|r.state [7] $ (((\sdram_|Mux7~3_combout ))))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux7~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h250A; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.rf_pending~q & (\sdram_|r.state [6] $ (((!\sdram_|Mux7~4_combout ))))) # (!\sdram_|r.rf_pending~q & (!\sdram_|r.state [6] & (!\sdram_|n~4_combout & !\sdram_|Mux7~4_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'h8823; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \sdram_|Mux7~6 ( // Equation(s): -// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|r.state [8] & \sdram_|Mux7~5_combout ))) .dataa(\sdram_|Mux7~2_combout ), - .datab(\sdram_|Mux7~5_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux7~1_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux7~1_combout ), + .datad(\sdram_|Mux7~5_combout ), .cin(gnd), .combout(\sdram_|Mux7~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .lut_mask = 16'hFEFA; defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N23 +// Location: FF_X23_Y19_N3 dffeas \sdram_|r.state[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux7~6_combout ), @@ -57685,14 +60757,938 @@ defparam \sdram_|r.state[5] .is_wysiwyg = "true"; defparam \sdram_|r.state[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N6 +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~32_combout = ((\sdram_|r.address[3]~6_combout & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[8]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~32 .lut_mask = 16'h555D; +defparam \sdram_|r.rf_counter[8]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(\sdram_|r.rf_counter [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [2]) # ((\sdram_|r.rf_counter [0]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [2]), + .datac(\sdram_|r.rf_counter [0]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter [9] $ (\sdram_|r.rf_counter[8]~29 ) + + .dataa(\sdram_|r.rf_counter [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h5A5A; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N23 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [4]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [5]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [5]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~0_combout ) # (((\sdram_|Equal0~1_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~0_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|r.rf_counter [9]), + .datad(\sdram_|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFFBF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|r.address[3]~6_combout )) # (!\sdram_|Mux13~8_combout ))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|Equal0~2_combout )))) + + .dataa(\sdram_|Mux13~8_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h707F; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N25 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (!\sdram_|r.rf_pending~q & (\sdram_|r.rd_pending~q & (\sdram_|Equal7~2_combout & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h0040; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux4~4 ( +// Equation(s): +// \sdram_|Mux4~4_combout = (\sdram_|r.state [8] & (((!\sdram_|Mux4~0_combout & \sdram_|Mux4~1_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|Mux4~1_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux4~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~4 .lut_mask = 16'h5F44; +defparam \sdram_|Mux4~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [5] & (((\sdram_|r.state [6] & !\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [6] $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'h39FE; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux4~5 ( +// Equation(s): +// \sdram_|Mux4~5_combout = (\sdram_|Mux4~2_combout & (((\sdram_|r.state [8])))) # (!\sdram_|Mux4~2_combout & (\sdram_|Mux4~4_combout & ((\sdram_|Mux4~3_combout ) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~3_combout ), + .datab(\sdram_|Mux4~4_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~5 .lut_mask = 16'hF0C8; +defparam \sdram_|Mux4~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = (\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~0 ( +// Equation(s): +// \sdram_|r.act_row[2]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [5] & (\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [6] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \sdram_|r.act_row[2]~1 ( +// Equation(s): +// \sdram_|r.act_row[2]~1_combout = (\sdram_|process_0~4_combout & (\sdram_|r.act_row[2]~0_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.act_row[2]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~1 .lut_mask = 16'h9000; +defparam \sdram_|r.act_row[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N3 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~18_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~18_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~18_combout ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~0_combout & (\sdram_|Equal7~1_combout & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|r.act_row [4]), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h8040; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF88; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (!\sdram_|r.rf_pending~q & (!\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'h0501; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (!\sdram_|r.state [4] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'h0F00; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~4_combout )) # (!\sdram_|Mux9~5_combout ))) # (!\sdram_|r.state [6] & (((!\sdram_|r.rf_pending~q & \sdram_|Mux9~4_combout )))) + + .dataa(\sdram_|Mux9~5_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux9~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h47CC; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hAFF0; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~4_combout & (\sdram_|Mux6~3_combout ))) + + .dataa(\sdram_|Mux6~4_combout ), + .datab(\sdram_|Mux6~3_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hCC00; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [4] & (\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~2_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8C10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|Mux6~0_combout ) # (\sdram_|r.state [6]))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h6628; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFA50; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (\sdram_|r.state [4] & (!\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h00E0; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N28 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rf_pending~q & \sdram_|Mux5~7_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux5~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h4544; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 cycloneive_lcell_comb \sdram_|Mux5~2 ( // Equation(s): -// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [8] & !\sdram_|Mux4~1_combout )))) - .dataa(\sdram_|Mux4~0_combout ), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [8]), + .datac(\sdram_|Mux4~1_combout ), .datad(\sdram_|Mux13~7_combout ), .cin(gnd), .combout(\sdram_|Mux5~2_combout ), @@ -57702,143 +61698,109 @@ defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N18 +// Location: LCCOMB_X18_Y17_N22 cycloneive_lcell_comb \sdram_|Mux5~10 ( // Equation(s): -// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) +// \sdram_|Mux5~10_combout = (\sdram_|r.state [8] & (\sdram_|r.state [6] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6])) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux5~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .lut_mask = 16'h9991; defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N16 +// Location: LCCOMB_X18_Y17_N2 cycloneive_lcell_comb \sdram_|Mux5~3 ( // Equation(s): -// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|Mux4~1_combout & !\sdram_|r.state [6]))) # (!\sdram_|r.state [5]) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux4~0_combout ), - .datad(\sdram_|Mux5~10_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux4~1_combout ), + .datac(\sdram_|Mux5~10_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .lut_mask = 16'hF5F7; defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N30 +// Location: LCCOMB_X18_Y17_N0 cycloneive_lcell_comb \sdram_|Mux5~4 ( // Equation(s): -// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|r.state [4] & \sdram_|Mux5~3_combout )))) - .dataa(\sdram_|Mux5~2_combout ), - .datab(\sdram_|Mux5~3_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux5~2_combout ), + .datad(\sdram_|Mux5~3_combout ), .cin(gnd), .combout(\sdram_|Mux5~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .lut_mask = 16'hC8C0; defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N18 -cycloneive_lcell_comb \sdram_|Mux5~7 ( -// Equation(s): -// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.rd_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux5~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; -defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N4 -cycloneive_lcell_comb \sdram_|Mux5~8 ( -// Equation(s): -// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) - - .dataa(\sdram_|Mux5~7_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux5~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; -defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N26 +// Location: LCCOMB_X20_Y16_N26 cycloneive_lcell_comb \sdram_|Mux5~5 ( // Equation(s): // \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [7]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|Mux5~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .lut_mask = 16'h0D0F; defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N12 +// Location: LCCOMB_X20_Y16_N8 cycloneive_lcell_comb \sdram_|Mux5~6 ( // Equation(s): -// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~4_combout & ((\sdram_|Mux5~5_combout ) # ((\sdram_|process_0~2_combout & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~3_combout ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux5~5_combout ), + .dataa(\sdram_|Mux5~5_combout ), + .datab(\sdram_|Mux9~4_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .lut_mask = 16'h88C8; defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N20 +// Location: LCCOMB_X23_Y19_N10 cycloneive_lcell_comb \sdram_|Mux5~9 ( // Equation(s): // \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|Mux5~4_combout ), - .datac(\sdram_|Mux5~8_combout ), + .dataa(\sdram_|Mux5~8_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux5~4_combout ), .datad(\sdram_|Mux5~6_combout ), .cin(gnd), .combout(\sdram_|Mux5~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .lut_mask = 16'hF3F2; defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N21 +// Location: FF_X23_Y19_N11 dffeas \sdram_|r.state[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux5~9_combout ), @@ -57857,7 +61819,7 @@ defparam \sdram_|r.state[7] .is_wysiwyg = "true"; defparam \sdram_|r.state[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N8 +// Location: LCCOMB_X18_Y17_N16 cycloneive_lcell_comb \sdram_|n~2 ( // Equation(s): // \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) @@ -57874,78 +61836,112 @@ defparam \sdram_|n~2 .lut_mask = 16'hFFFC; defparam \sdram_|n~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Location: LCCOMB_X19_Y19_N10 +cycloneive_lcell_comb \sdram_|Mux8~6 ( // Equation(s): -// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) +// \sdram_|Mux8~6_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), .datad(\sdram_|r.state [4]), .cin(gnd), + .combout(\sdram_|Mux8~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~6 .lut_mask = 16'hB03B; +defparam \sdram_|Mux8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux8~7 ( +// Equation(s): +// \sdram_|Mux8~7_combout = (\sdram_|r.state [8] & (\sdram_|Mux8~6_combout $ ((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|Mux8~6_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|Mux8~6_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~7 .lut_mask = 16'h606E; +defparam \sdram_|Mux8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|r.state [5] $ (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [5]) # (\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7336; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N28 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [6] & (\sdram_|Mux8~1_combout & (!\sdram_|r.state [8]))) # (!\sdram_|r.state [6] & (\sdram_|r.state [8] $ (((!\sdram_|n~2_combout ) # (!\sdram_|Mux8~1_combout ))))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'h490D; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N26 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [6] & ((\sdram_|Mux9~5_combout & ((\sdram_|Mux8~2_combout ))) # (!\sdram_|Mux9~5_combout & (\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|Mux8~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux8~2_combout ), + .cin(gnd), .combout(\sdram_|Mux8~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .lut_mask = 16'hFD08; defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Location: LCCOMB_X19_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~44 ( // Equation(s): -// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux8~3_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux8~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; -defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux9~10 ( -// Equation(s): -// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) - - .dataa(gnd), - .datab(\sdram_|Mux9~9_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux9~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; -defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N28 -cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( -// Equation(s): -// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] +// \sdram_|r.init_counter[0]~44_combout = !\sdram_|r.init_counter [0] .dataa(gnd), .datab(gnd), .datac(\sdram_|r.init_counter [0]), .datad(gnd), .cin(gnd), - .combout(\sdram_|r.init_counter[0]~0_combout ), + .combout(\sdram_|r.init_counter[0]~44_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[0]~44 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y7_N29 +// Location: FF_X19_Y16_N7 dffeas \sdram_|r.init_counter[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[0]~0_combout ), + .d(\sdram_|r.init_counter[0]~44_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57961,45 +61957,45 @@ defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N2 -cycloneive_lcell_comb \sdram_|Add1~1 ( +// Location: LCCOMB_X18_Y16_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~15 ( // Equation(s): -// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) +// \sdram_|r.init_counter[1]~15_cout = CARRY(\sdram_|r.init_counter [0]) - .dataa(gnd), - .datab(\sdram_|r.init_counter [0]), + .dataa(\sdram_|r.init_counter [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), - .cout(\sdram_|Add1~1_cout )); + .cout(\sdram_|r.init_counter[1]~15_cout )); // synopsys translate_off -defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; -defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[1]~15 .lut_mask = 16'h00AA; +defparam \sdram_|r.init_counter[1]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N4 -cycloneive_lcell_comb \sdram_|Add1~2 ( +// Location: LCCOMB_X18_Y16_N4 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~16 ( // Equation(s): -// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) -// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) +// \sdram_|r.init_counter[1]~16_combout = (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter[1]~15_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter[1]~15_cout )) +// \sdram_|r.init_counter[1]~17 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|r.init_counter[1]~15_cout )) .dataa(gnd), .datab(\sdram_|r.init_counter [1]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~1_cout ), - .combout(\sdram_|Add1~2_combout ), - .cout(\sdram_|Add1~3 )); + .cin(\sdram_|r.init_counter[1]~15_cout ), + .combout(\sdram_|r.init_counter[1]~16_combout ), + .cout(\sdram_|r.init_counter[1]~17 )); // synopsys translate_off -defparam \sdram_|Add1~2 .lut_mask = 16'hC303; -defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[1]~16 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[1]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N5 +// Location: FF_X18_Y16_N5 dffeas \sdram_|r.init_counter[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~2_combout ), + .d(\sdram_|r.init_counter[1]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58015,28 +62011,28 @@ defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N6 -cycloneive_lcell_comb \sdram_|Add1~4 ( +// Location: LCCOMB_X18_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[2]~18 ( // Equation(s): -// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) -// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) +// \sdram_|r.init_counter[2]~18_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|r.init_counter[1]~17 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter[1]~17 $ (GND))) +// \sdram_|r.init_counter[2]~19 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|r.init_counter[1]~17 )) .dataa(\sdram_|r.init_counter [2]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~3 ), - .combout(\sdram_|Add1~4_combout ), - .cout(\sdram_|Add1~5 )); + .cin(\sdram_|r.init_counter[1]~17 ), + .combout(\sdram_|r.init_counter[2]~18_combout ), + .cout(\sdram_|r.init_counter[2]~19 )); // synopsys translate_off -defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[2]~18 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[2]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N7 +// Location: FF_X18_Y16_N7 dffeas \sdram_|r.init_counter[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~4_combout ), + .d(\sdram_|r.init_counter[2]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58052,45 +62048,28 @@ defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N8 -cycloneive_lcell_comb \sdram_|Add1~6 ( +// Location: LCCOMB_X18_Y16_N8 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~20 ( // Equation(s): -// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) -// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) - - .dataa(\sdram_|r.init_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|Add1~5 ), - .combout(\sdram_|Add1~6_combout ), - .cout(\sdram_|Add1~7 )); -// synopsys translate_off -defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; -defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N2 -cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( -// Equation(s): -// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout +// \sdram_|r.init_counter[3]~20_combout = (\sdram_|r.init_counter [3] & (\sdram_|r.init_counter[2]~19 & VCC)) # (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter[2]~19 )) +// \sdram_|r.init_counter[3]~21 = CARRY((!\sdram_|r.init_counter [3] & !\sdram_|r.init_counter[2]~19 )) .dataa(gnd), - .datab(gnd), - .datac(\sdram_|Add1~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.init_counter[3]~1_combout ), - .cout()); + .datab(\sdram_|r.init_counter [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.init_counter[2]~19 ), + .combout(\sdram_|r.init_counter[3]~20_combout ), + .cout(\sdram_|r.init_counter[3]~21 )); // synopsys translate_off -defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[3]~20 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[3]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X20_Y3_N3 +// Location: FF_X18_Y16_N9 dffeas \sdram_|r.init_counter[3] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[3]~1_combout ), + .d(\sdram_|r.init_counter[3]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58106,28 +62085,28 @@ defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N10 -cycloneive_lcell_comb \sdram_|Add1~8 ( +// Location: LCCOMB_X18_Y16_N10 +cycloneive_lcell_comb \sdram_|r.init_counter[4]~22 ( // Equation(s): -// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) -// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) +// \sdram_|r.init_counter[4]~22_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|r.init_counter[3]~21 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|r.init_counter[3]~21 $ (GND))) +// \sdram_|r.init_counter[4]~23 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|r.init_counter[3]~21 )) .dataa(\sdram_|r.init_counter [4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~7 ), - .combout(\sdram_|Add1~8_combout ), - .cout(\sdram_|Add1~9 )); + .cin(\sdram_|r.init_counter[3]~21 ), + .combout(\sdram_|r.init_counter[4]~22_combout ), + .cout(\sdram_|r.init_counter[4]~23 )); // synopsys translate_off -defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[4]~22 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[4]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N11 +// Location: FF_X18_Y16_N11 dffeas \sdram_|r.init_counter[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~8_combout ), + .d(\sdram_|r.init_counter[4]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58143,28 +62122,28 @@ defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N12 -cycloneive_lcell_comb \sdram_|Add1~10 ( +// Location: LCCOMB_X18_Y16_N12 +cycloneive_lcell_comb \sdram_|r.init_counter[5]~24 ( // Equation(s): -// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) -// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) +// \sdram_|r.init_counter[5]~24_combout = (\sdram_|r.init_counter [5] & (\sdram_|r.init_counter[4]~23 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|r.init_counter[4]~23 )) +// \sdram_|r.init_counter[5]~25 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|r.init_counter[4]~23 )) .dataa(\sdram_|r.init_counter [5]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~9 ), - .combout(\sdram_|Add1~10_combout ), - .cout(\sdram_|Add1~11 )); + .cin(\sdram_|r.init_counter[4]~23 ), + .combout(\sdram_|r.init_counter[5]~24_combout ), + .cout(\sdram_|r.init_counter[5]~25 )); // synopsys translate_off -defparam \sdram_|Add1~10 .lut_mask = 16'hA505; -defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[5]~24 .lut_mask = 16'hA505; +defparam \sdram_|r.init_counter[5]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N13 +// Location: FF_X18_Y16_N13 dffeas \sdram_|r.init_counter[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~10_combout ), + .d(\sdram_|r.init_counter[5]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58180,28 +62159,28 @@ defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N14 -cycloneive_lcell_comb \sdram_|Add1~12 ( +// Location: LCCOMB_X18_Y16_N14 +cycloneive_lcell_comb \sdram_|r.init_counter[6]~26 ( // Equation(s): -// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) -// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) +// \sdram_|r.init_counter[6]~26_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|r.init_counter[5]~25 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|r.init_counter[5]~25 $ (GND))) +// \sdram_|r.init_counter[6]~27 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|r.init_counter[5]~25 )) .dataa(gnd), .datab(\sdram_|r.init_counter [6]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~11 ), - .combout(\sdram_|Add1~12_combout ), - .cout(\sdram_|Add1~13 )); + .cin(\sdram_|r.init_counter[5]~25 ), + .combout(\sdram_|r.init_counter[6]~26_combout ), + .cout(\sdram_|r.init_counter[6]~27 )); // synopsys translate_off -defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[6]~26 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[6]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N15 +// Location: FF_X18_Y16_N15 dffeas \sdram_|r.init_counter[6] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~12_combout ), + .d(\sdram_|r.init_counter[6]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58217,28 +62196,28 @@ defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N16 -cycloneive_lcell_comb \sdram_|Add1~14 ( +// Location: LCCOMB_X18_Y16_N16 +cycloneive_lcell_comb \sdram_|r.init_counter[7]~28 ( // Equation(s): -// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) -// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) +// \sdram_|r.init_counter[7]~28_combout = (\sdram_|r.init_counter [7] & (\sdram_|r.init_counter[6]~27 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|r.init_counter[6]~27 )) +// \sdram_|r.init_counter[7]~29 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|r.init_counter[6]~27 )) .dataa(gnd), .datab(\sdram_|r.init_counter [7]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~13 ), - .combout(\sdram_|Add1~14_combout ), - .cout(\sdram_|Add1~15 )); + .cin(\sdram_|r.init_counter[6]~27 ), + .combout(\sdram_|r.init_counter[7]~28_combout ), + .cout(\sdram_|r.init_counter[7]~29 )); // synopsys translate_off -defparam \sdram_|Add1~14 .lut_mask = 16'hC303; -defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[7]~28 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[7]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N17 +// Location: FF_X18_Y16_N17 dffeas \sdram_|r.init_counter[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~14_combout ), + .d(\sdram_|r.init_counter[7]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58254,28 +62233,28 @@ defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N18 -cycloneive_lcell_comb \sdram_|Add1~16 ( +// Location: LCCOMB_X18_Y16_N18 +cycloneive_lcell_comb \sdram_|r.init_counter[8]~30 ( // Equation(s): -// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) -// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) +// \sdram_|r.init_counter[8]~30_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|r.init_counter[7]~29 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|r.init_counter[7]~29 $ (GND))) +// \sdram_|r.init_counter[8]~31 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|r.init_counter[7]~29 )) .dataa(gnd), .datab(\sdram_|r.init_counter [8]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~15 ), - .combout(\sdram_|Add1~16_combout ), - .cout(\sdram_|Add1~17 )); + .cin(\sdram_|r.init_counter[7]~29 ), + .combout(\sdram_|r.init_counter[8]~30_combout ), + .cout(\sdram_|r.init_counter[8]~31 )); // synopsys translate_off -defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[8]~30 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[8]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N19 +// Location: FF_X18_Y16_N19 dffeas \sdram_|r.init_counter[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~16_combout ), + .d(\sdram_|r.init_counter[8]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58291,28 +62270,28 @@ defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N20 -cycloneive_lcell_comb \sdram_|Add1~18 ( +// Location: LCCOMB_X18_Y16_N20 +cycloneive_lcell_comb \sdram_|r.init_counter[9]~32 ( // Equation(s): -// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) -// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) +// \sdram_|r.init_counter[9]~32_combout = (\sdram_|r.init_counter [9] & (\sdram_|r.init_counter[8]~31 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter[8]~31 )) +// \sdram_|r.init_counter[9]~33 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|r.init_counter[8]~31 )) .dataa(gnd), .datab(\sdram_|r.init_counter [9]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~17 ), - .combout(\sdram_|Add1~18_combout ), - .cout(\sdram_|Add1~19 )); + .cin(\sdram_|r.init_counter[8]~31 ), + .combout(\sdram_|r.init_counter[9]~32_combout ), + .cout(\sdram_|r.init_counter[9]~33 )); // synopsys translate_off -defparam \sdram_|Add1~18 .lut_mask = 16'hC303; -defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[9]~32 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[9]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N21 +// Location: FF_X18_Y16_N21 dffeas \sdram_|r.init_counter[9] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~18_combout ), + .d(\sdram_|r.init_counter[9]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58328,28 +62307,28 @@ defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N22 -cycloneive_lcell_comb \sdram_|Add1~20 ( +// Location: LCCOMB_X18_Y16_N22 +cycloneive_lcell_comb \sdram_|r.init_counter[10]~34 ( // Equation(s): -// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) -// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) +// \sdram_|r.init_counter[10]~34_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|r.init_counter[9]~33 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|r.init_counter[9]~33 $ (GND))) +// \sdram_|r.init_counter[10]~35 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|r.init_counter[9]~33 )) .dataa(\sdram_|r.init_counter [10]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~19 ), - .combout(\sdram_|Add1~20_combout ), - .cout(\sdram_|Add1~21 )); + .cin(\sdram_|r.init_counter[9]~33 ), + .combout(\sdram_|r.init_counter[10]~34_combout ), + .cout(\sdram_|r.init_counter[10]~35 )); // synopsys translate_off -defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[10]~34 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[10]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N23 +// Location: FF_X18_Y16_N23 dffeas \sdram_|r.init_counter[10] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~20_combout ), + .d(\sdram_|r.init_counter[10]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58365,62 +62344,28 @@ defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N22 -cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Location: LCCOMB_X18_Y16_N24 +cycloneive_lcell_comb \sdram_|r.init_counter[11]~36 ( // Equation(s): -// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|r.init_counter [4]), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; -defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N0 -cycloneive_lcell_comb \sdram_|Equal2~1 ( -// Equation(s): -// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [3]), - .cin(gnd), - .combout(\sdram_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; -defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y3_N24 -cycloneive_lcell_comb \sdram_|Add1~22 ( -// Equation(s): -// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) -// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) +// \sdram_|r.init_counter[11]~36_combout = (\sdram_|r.init_counter [11] & (\sdram_|r.init_counter[10]~35 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter[10]~35 )) +// \sdram_|r.init_counter[11]~37 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|r.init_counter[10]~35 )) .dataa(gnd), .datab(\sdram_|r.init_counter [11]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~21 ), - .combout(\sdram_|Add1~22_combout ), - .cout(\sdram_|Add1~23 )); + .cin(\sdram_|r.init_counter[10]~35 ), + .combout(\sdram_|r.init_counter[11]~36_combout ), + .cout(\sdram_|r.init_counter[11]~37 )); // synopsys translate_off -defparam \sdram_|Add1~22 .lut_mask = 16'hC303; -defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[11]~36 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[11]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N25 +// Location: FF_X18_Y16_N25 dffeas \sdram_|r.init_counter[11] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~22_combout ), + .d(\sdram_|r.init_counter[11]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58436,28 +62381,28 @@ defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N26 -cycloneive_lcell_comb \sdram_|Add1~24 ( +// Location: LCCOMB_X18_Y16_N26 +cycloneive_lcell_comb \sdram_|r.init_counter[12]~38 ( // Equation(s): -// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) -// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) +// \sdram_|r.init_counter[12]~38_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|r.init_counter[11]~37 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|r.init_counter[11]~37 $ (GND))) +// \sdram_|r.init_counter[12]~39 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|r.init_counter[11]~37 )) .dataa(\sdram_|r.init_counter [12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~23 ), - .combout(\sdram_|Add1~24_combout ), - .cout(\sdram_|Add1~25 )); + .cin(\sdram_|r.init_counter[11]~37 ), + .combout(\sdram_|r.init_counter[12]~38_combout ), + .cout(\sdram_|r.init_counter[12]~39 )); // synopsys translate_off -defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[12]~38 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[12]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N27 +// Location: FF_X18_Y16_N27 dffeas \sdram_|r.init_counter[12] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~24_combout ), + .d(\sdram_|r.init_counter[12]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58473,28 +62418,28 @@ defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N28 -cycloneive_lcell_comb \sdram_|Add1~26 ( +// Location: LCCOMB_X18_Y16_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[13]~40 ( // Equation(s): -// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) -// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) +// \sdram_|r.init_counter[13]~40_combout = (\sdram_|r.init_counter [13] & (\sdram_|r.init_counter[12]~39 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter[12]~39 )) +// \sdram_|r.init_counter[13]~41 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|r.init_counter[12]~39 )) .dataa(gnd), .datab(\sdram_|r.init_counter [13]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~25 ), - .combout(\sdram_|Add1~26_combout ), - .cout(\sdram_|Add1~27 )); + .cin(\sdram_|r.init_counter[12]~39 ), + .combout(\sdram_|r.init_counter[13]~40_combout ), + .cout(\sdram_|r.init_counter[13]~41 )); // synopsys translate_off -defparam \sdram_|Add1~26 .lut_mask = 16'hC303; -defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[13]~40 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[13]~40 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N29 +// Location: FF_X18_Y16_N29 dffeas \sdram_|r.init_counter[13] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~26_combout ), + .d(\sdram_|r.init_counter[13]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58510,27 +62455,27 @@ defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N30 -cycloneive_lcell_comb \sdram_|Add1~28 ( +// Location: LCCOMB_X18_Y16_N30 +cycloneive_lcell_comb \sdram_|r.init_counter[14]~42 ( // Equation(s): -// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) +// \sdram_|r.init_counter[14]~42_combout = \sdram_|r.init_counter [14] $ (\sdram_|r.init_counter[13]~41 ) .dataa(\sdram_|r.init_counter [14]), .datab(gnd), .datac(gnd), .datad(gnd), - .cin(\sdram_|Add1~27 ), - .combout(\sdram_|Add1~28_combout ), + .cin(\sdram_|r.init_counter[13]~41 ), + .combout(\sdram_|r.init_counter[14]~42_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; -defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[14]~42 .lut_mask = 16'h5A5A; +defparam \sdram_|r.init_counter[14]~42 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N31 +// Location: FF_X18_Y16_N31 dffeas \sdram_|r.init_counter[14] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~28_combout ), + .d(\sdram_|r.init_counter[14]~42_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58546,15 +62491,32 @@ defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N0 +// Location: LCCOMB_X19_Y16_N2 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0003; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y16_N0 cycloneive_lcell_comb \sdram_|process_0~5 ( // Equation(s): -// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [10] & !\sdram_|r.init_counter [9]))) - .dataa(\sdram_|r.init_counter [14]), + .dataa(\sdram_|r.init_counter [8]), .datab(\sdram_|r.init_counter [11]), - .datac(\sdram_|r.init_counter [12]), - .datad(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [10]), + .datad(\sdram_|r.init_counter [9]), .cin(gnd), .combout(\sdram_|process_0~5_combout ), .cout()); @@ -58563,129 +62525,95 @@ defparam \sdram_|process_0~5 .lut_mask = 16'h0001; defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N6 +// Location: LCCOMB_X19_Y16_N10 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter [4] & (!\sdram_|r.init_counter [2] & !\sdram_|r.init_counter [5]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|r.init_counter [4]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [5]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N0 cycloneive_lcell_comb \sdram_|Equal2~2 ( // Equation(s): -// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) +// \sdram_|Equal2~2_combout = (!\sdram_|r.init_counter [6] & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & \sdram_|Equal2~0_combout ))) - .dataa(\sdram_|Equal2~0_combout ), + .dataa(\sdram_|r.init_counter [6]), .datab(\sdram_|Equal2~1_combout ), .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [2]), + .datad(\sdram_|Equal2~0_combout ), .cin(gnd), .combout(\sdram_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .lut_mask = 16'h4000; defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~11 ( -// Equation(s): -// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(gnd), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Mux9~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; -defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux9~12 ( -// Equation(s): -// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) - - .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux9~11_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; -defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N0 -cycloneive_lcell_comb \sdram_|Mux9~13 ( -// Equation(s): -// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|n~2_combout ), - .datad(\sdram_|Mux9~12_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; -defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N2 +// Location: LCCOMB_X19_Y16_N4 cycloneive_lcell_comb \sdram_|Mux8~0 ( // Equation(s): -// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) +// \sdram_|Mux8~0_combout = (\sdram_|r.init_counter [0] & (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux9~10_combout ), - .datad(\sdram_|Mux9~13_combout ), + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), .cin(gnd), .combout(\sdram_|Mux8~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .lut_mask = 16'h0200; defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N16 -cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Location: LCCOMB_X19_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux8~4 ( // Equation(s): -// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) +// \sdram_|Mux8~4_combout = (\sdram_|r.state [5] & (((\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux8~3_combout & ((\sdram_|Mux8~1_combout ) # (\sdram_|Mux8~0_combout )))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), + .dataa(\sdram_|Mux8~3_combout ), + .datab(\sdram_|Mux8~1_combout ), .datac(\sdram_|r.state [5]), .datad(\sdram_|Mux8~0_combout ), .cin(gnd), - .combout(\sdram_|Mux8~1_combout ), + .combout(\sdram_|Mux8~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; -defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~4 .lut_mask = 16'hCAC8; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux8~5 ( // Equation(s): -// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) +// \sdram_|Mux8~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~7_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~4_combout ))) .dataa(\sdram_|r.state [7]), .datab(gnd), - .datac(\sdram_|Mux8~4_combout ), - .datad(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux8~7_combout ), + .datad(\sdram_|Mux8~4_combout ), .cin(gnd), - .combout(\sdram_|Mux8~2_combout ), + .combout(\sdram_|Mux8~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; -defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~5 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y15_N21 +// Location: FF_X23_Y19_N5 dffeas \sdram_|r.state[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux8~2_combout ), + .d(\sdram_|Mux8~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58701,49 +62629,49 @@ defparam \sdram_|r.state[4] .is_wysiwyg = "true"; defparam \sdram_|r.state[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 +// Location: LCCOMB_X23_Y19_N18 cycloneive_lcell_comb \sdram_|Mux72~0 ( // Equation(s): -// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux72~0_combout = (\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [0]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux72~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 +// Location: LCCOMB_X23_Y19_N20 cycloneive_lcell_comb \sdram_|Mux72~1 ( // Equation(s): -// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux72~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux72~0_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|r.state [4]), .datac(\sdram_|Mux72~0_combout ), - .datad(\D[0]~64_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), .combout(\sdram_|Mux72~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .lut_mask = 16'hC040; defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N0 +// Location: LCCOMB_X23_Y19_N6 cycloneive_lcell_comb \sdram_|Mux84~0 ( // Equation(s): -// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) +// \sdram_|Mux84~0_combout = (\sdram_|r.state [4]) # (\sdram_|r.state [5]) .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux84~0_combout ), .cout()); @@ -58752,245 +62680,245 @@ defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N2 +// Location: LCCOMB_X23_Y19_N28 cycloneive_lcell_comb \sdram_|Mux84~1 ( // Equation(s): -// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) +// \sdram_|Mux84~1_combout = (\sdram_|r.state [7] & (!\sdram_|r.state [8] & (\sdram_|r.state [6] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [6] & !\sdram_|Mux84~0_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|Mux84~0_combout ), .cin(gnd), .combout(\sdram_|Mux84~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .lut_mask = 16'h2004; defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 +// Location: LCCOMB_X23_Y19_N26 cycloneive_lcell_comb \sdram_|Mux3~0 ( // Equation(s): -// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux3~0_combout = (\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|data_pins_|dout [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), .combout(\sdram_|Mux3~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .lut_mask = 16'hAAFF; defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 +// Location: LCCOMB_X23_Y19_N8 cycloneive_lcell_comb \sdram_|Mux3~1 ( // Equation(s): -// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & (\sdram_|r.state [4] & ((\Selector12~11_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux3~0_combout ), - .datad(\D[1]~40_combout ), + .dataa(\sdram_|Mux3~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector12~11_combout ), .cin(gnd), .combout(\sdram_|Mux3~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .lut_mask = 16'h8808; defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 +// Location: LCCOMB_X27_Y19_N8 cycloneive_lcell_comb \sdram_|Mux2~0 ( // Equation(s): -// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux2~0_combout = (\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [2]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 +// Location: LCCOMB_X23_Y19_N30 cycloneive_lcell_comb \sdram_|Mux2~1 ( // Equation(s): -// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & (\sdram_|r.state [4] & ((\Selector10~3_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux2~0_combout ), - .datad(\D[2]~52_combout ), + .dataa(\sdram_|Mux2~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Selector10~3_combout ), + .datad(\Equal5~1_combout ), .cin(gnd), .combout(\sdram_|Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .lut_mask = 16'h8088; defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y16_N6 cycloneive_lcell_comb \sdram_|Mux1~0 ( // Equation(s): -// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux1~0_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\sdram_|Mux1~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N10 +// Location: LCCOMB_X24_Y15_N4 cycloneive_lcell_comb \sdram_|Mux1~1 ( // Equation(s): -// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux1~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux1~0_combout & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[3]~108_combout ), - .datad(\sdram_|Mux1~0_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|Mux1~0_combout ), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), .cin(gnd), .combout(\sdram_|Mux1~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .lut_mask = 16'h8808; defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N12 +// Location: LCCOMB_X25_Y16_N8 cycloneive_lcell_comb \sdram_|Mux0~0 ( // Equation(s): -// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux0~0_combout = (\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [4]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [4]), .cin(gnd), .combout(\sdram_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 +// Location: LCCOMB_X23_Y19_N12 cycloneive_lcell_comb \sdram_|Mux0~1 ( // Equation(s): -// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & (\sdram_|r.state [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux0~0_combout ), - .datad(\D[4]~110_combout ), + .dataa(\sdram_|Mux0~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), .combout(\sdram_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .lut_mask = 16'h8808; defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 +// Location: LCCOMB_X29_Y19_N4 cycloneive_lcell_comb \sdram_|Mux73~0 ( // Equation(s): -// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\D[5]~27_combout ) # (!\D[0]~49_combout ))) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[5]~27_combout ), .cin(gnd), .combout(\sdram_|Mux73~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .lut_mask = 16'hF030; defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux73~1 ( -// Equation(s): -// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux73~0_combout ), - .datad(\D[5]~112_combout ), - .cin(gnd), - .combout(\sdram_|Mux73~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; -defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N24 +// Location: LCCOMB_X26_Y16_N10 cycloneive_lcell_comb \sdram_|Mux74~0 ( // Equation(s): -// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux74~0_combout = (\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [6]), .cin(gnd), .combout(\sdram_|Mux74~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N6 +// Location: LCCOMB_X23_Y19_N14 cycloneive_lcell_comb \sdram_|Mux74~1 ( // Equation(s): -// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & (\sdram_|r.state [4] & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), + .dataa(\Equal5~1_combout ), .datab(\sdram_|Mux74~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~114_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[6]~46_combout ), .cin(gnd), .combout(\sdram_|Mux74~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .lut_mask = 16'hC040; defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X17_Y4_N28 +// Location: LCCOMB_X24_Y16_N8 cycloneive_lcell_comb \sdram_|Mux75~0 ( // Equation(s): -// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & ((\D[7]~37_combout ) # (!\D[0]~49_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\D[7]~117_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), .cin(gnd), .combout(\sdram_|Mux75~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .lut_mask = 16'hAA22; defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N8 +// Location: LCCOMB_X1_Y10_N16 +cycloneive_lcell_comb \LED~0 ( +// Equation(s): +// \LED~0_combout = (!\kempston[4]~input_o & \kempston_auto_fire~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\kempston[4]~input_o ), + .datad(\kempston_auto_fire~q ), + .cin(gnd), + .combout(\LED~0_combout ), + .cout()); +// synopsys translate_off +defparam \LED~0 .lut_mask = 16'h0F00; +defparam \LED~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -59007,7 +62935,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N9 +// Location: FF_X21_Y33_N13 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -59045,24 +62973,43 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N12 +// Location: FF_X24_Y19_N13 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N14 +// Location: LCCOMB_X25_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -59080,24 +63027,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N0 +// Location: LCCOMB_X25_Y30_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N1 +// Location: FF_X25_Y30_N29 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -59116,42 +63063,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N16 +// Location: LCCOMB_X25_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N6 +// Location: LCCOMB_X26_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N7 +// Location: FF_X26_Y30_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -59170,25 +63117,25 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N18 +// Location: LCCOMB_X25_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(\ula_|i2s_intf_|lrdivider [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N30 +// Location: LCCOMB_X26_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout @@ -59205,7 +63152,7 @@ defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N31 +// Location: FF_X26_Y30_N9 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -59224,7 +63171,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N20 +// Location: LCCOMB_X25_Y30_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -59242,24 +63189,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N4 +// Location: LCCOMB_X25_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~8_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N5 +// Location: FF_X25_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -59278,7 +63225,7 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N22 +// Location: LCCOMB_X25_Y30_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) @@ -59296,24 +63243,24 @@ defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N4 +// Location: LCCOMB_X26_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~10_combout ), + .datac(\ula_|i2s_intf_|Add0~10_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N5 +// Location: FF_X26_Y30_N7 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -59332,24 +63279,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N10 +// Location: LCCOMB_X25_Y30_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|lrdivider [4] & \ula_|i2s_intf_|lrdivider [2]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(\ula_|i2s_intf_|lrdivider [3]), - .datad(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(\ula_|i2s_intf_|lrdivider [4]), + .datad(\ula_|i2s_intf_|lrdivider [2]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N24 +// Location: LCCOMB_X25_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -59367,7 +63314,7 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N22 +// Location: LCCOMB_X26_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -59384,7 +63331,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N23 +// Location: FF_X26_Y30_N13 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -59403,42 +63350,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N26 +// Location: LCCOMB_X25_Y30_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N20 +// Location: LCCOMB_X26_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N21 +// Location: FF_X26_Y30_N11 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -59457,7 +63404,7 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N28 +// Location: LCCOMB_X25_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) @@ -59475,24 +63422,24 @@ defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N8 +// Location: LCCOMB_X25_Y30_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~16_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N9 +// Location: FF_X25_Y30_N1 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -59511,7 +63458,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N30 +// Location: LCCOMB_X25_Y30_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -59528,24 +63475,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X19_Y31_N24 +// Location: LCCOMB_X26_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~18_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y31_N25 +// Location: FF_X26_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -59564,73 +63511,54 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N6 +// Location: LCCOMB_X25_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [6] & !\ula_|i2s_intf_|lrdivider [8]))) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [8]), - .datad(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [9]), + .datab(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [8]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N2 +// Location: LCCOMB_X25_Y30_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|Equal0~0_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & !\ula_|i2s_intf_|lrdivider [1]))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|Equal0~0_combout ), - .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|lrdivider [1]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 +// Location: LCCOMB_X24_Y19_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q $ (\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(gnd), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59672,43 +63600,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 +// Location: LCCOMB_X24_Y23_N14 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -59726,303 +63618,50 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N25 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N17 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N19 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N21 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N23 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(\ula_|i2s_intf_|bitcount [0]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; -defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 +// Location: LCCOMB_X24_Y19_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): // \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add2~7_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N20 +// Location: LCCOMB_X24_Y19_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( // Equation(s): // \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) // \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~7_cout ), .combout(\ula_|i2s_intf_|Add2~8_combout ), .cout(\ula_|i2s_intf_|Add2~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N4 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( // Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|bdivider [0]) # (!\ula_|i2s_intf_|Equal1~0_combout )))) - .dataa(\ula_|i2s_intf_|bdivider [0]), + .dataa(\ula_|i2s_intf_|Equal1~0_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|Add2~8_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~20_combout ), .cout()); @@ -60031,7 +63670,7 @@ defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N5 +// Location: FF_X24_Y19_N31 dffeas \ula_|i2s_intf_|bdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~20_combout ), @@ -60050,7 +63689,7 @@ defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N22 +// Location: LCCOMB_X24_Y19_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( // Equation(s): // \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) @@ -60068,24 +63707,24 @@ defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N16 +// Location: LCCOMB_X24_Y23_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( // Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~10_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~10_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~10_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N17 +// Location: FF_X24_Y23_N31 dffeas \ula_|i2s_intf_|bdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~17_combout ), @@ -60104,42 +63743,42 @@ defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N24 +// Location: LCCOMB_X24_Y19_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( // Equation(s): // \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) // \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~11 ), .combout(\ula_|i2s_intf_|Add2~12_combout ), .cout(\ula_|i2s_intf_|Add2~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N14 +// Location: LCCOMB_X24_Y23_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( // Equation(s): // \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Add2~12_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Add2~12_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h0222; defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N15 +// Location: FF_X24_Y23_N1 dffeas \ula_|i2s_intf_|bdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~19_combout ), @@ -60158,7 +63797,7 @@ defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N26 +// Location: LCCOMB_X24_Y19_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( // Equation(s): // \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) @@ -60175,24 +63814,24 @@ defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N6 +// Location: LCCOMB_X24_Y23_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( // Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~14_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~14_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~14_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N7 +// Location: FF_X24_Y23_N25 dffeas \ula_|i2s_intf_|bdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~16_combout ), @@ -60211,78 +63850,333 @@ defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N2 +// Location: LCCOMB_X24_Y19_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & (!\ula_|i2s_intf_|bdivider [1] & \ula_|i2s_intf_|bdivider [4]))) - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(\ula_|i2s_intf_|bdivider [1]), + .datad(\ula_|i2s_intf_|bdivider [4]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0400; defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N28 +// Location: LCCOMB_X24_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (((!\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~0_combout )) # (!\ula_|i2s_intf_|bdivider [0]))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1303; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N27 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hAA00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) +// Location: FF_X24_Y23_N29 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), +// Location: LCCOMB_X24_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~9_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~9 .lut_mask = 16'hCCEC; +defparam \ula_|i2s_intf_|bitcount[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~10 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~10_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~11 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~10 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~12 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~12_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~11 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~11 )) +// \ula_|i2s_intf_|bitcount[3]~13 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~11 ), + .combout(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~14 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~14_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~13 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~13 ), + .combout(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~14 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [2]), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~1 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~1_combout = (\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]) + + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~1 .lut_mask = 16'hFF0F; +defparam \ula_|i2s_intf_|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~1_combout ))))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h0078; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -60298,15 +64192,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N16 +// Location: LCCOMB_X23_Y18_N26 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~38_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~109_combout ), + .datad(\D[3]~38_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -60315,41 +64209,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N30 +// Location: LCCOMB_X23_Y17_N0 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) +// \ula_|always0~2_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h00C0; +defparam \ula_|always0~2 .lut_mask = 16'h2020; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N2 +// Location: LCCOMB_X23_Y17_N24 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h0200; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N17 +// Location: FF_X23_Y18_N27 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -60368,538 +64262,25 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N7 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; -defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N29 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N15 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N17 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N23 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N13 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N19 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N9 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [7]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N3 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N5 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N11 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [10]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N1 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N27 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 +// Location: LCCOMB_X24_Y19_N26 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hD8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N11 +// Location: FF_X24_Y19_N27 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -60918,25 +64299,25 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N12 +// Location: LCCOMB_X24_Y19_N20 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INL [14])))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # +// (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INL [14]))))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hE4F0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N13 +// Location: FF_X24_Y19_N21 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -60955,24 +64336,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N0 +// Location: LCCOMB_X24_Y19_N14 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N1 +// Location: FF_X24_Y19_N15 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -60991,25 +64372,502 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N20 +// Location: LCCOMB_X24_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~18_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~18 .lut_mask = 16'h008C; +defparam \ula_|i2s_intf_|shiftreg[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|shiftreg[0]~18_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~18_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[7]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[7]~1_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7]~1 .lut_mask = 16'hECCC; +defparam \ula_|i2s_intf_|shiftreg[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N7 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [6]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [8]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [9]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [9]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [10]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|shiftreg [12]), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|pcm_outl [12]), + .datac(\ula_|i2s_intf_|shiftreg [11]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N21 -dffeas \ula_|i2s_intf_|shiftreg[13] ( +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), .asdata(vcc), @@ -61017,7 +64875,43 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [12])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [12]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|pcm_outl [12]), + .datad(\ula_|i2s_intf_|shiftreg [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hF3C0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -61027,33 +64921,33 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|pcm_outl [13]), .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF5A0; +defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N31 +// Location: FF_X24_Y21_N13 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .d(\ula_|i2s_intf_|shiftreg~4_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -61063,32 +64957,15 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N22 -cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( -// Equation(s): -// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[4]~111_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y19_N23 +// Location: FF_X25_Y19_N13 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[14]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[4]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -61099,33 +64976,33 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( +// Location: LCCOMB_X24_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [14]), .datad(\ula_|pcm_outl [14]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~4_combout ), + .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; -defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N25 +// Location: FF_X24_Y22_N21 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~4_combout ), + .d(\ula_|i2s_intf_|shiftreg~3_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -61135,33 +65012,33 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~3_combout ), + .combout(\ula_|i2s_intf_|shiftreg~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; -defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~2 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y33_N1 +// Location: FF_X24_Y30_N17 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~3_combout ), + .d(\ula_|i2s_intf_|shiftreg~2_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -61171,7 +65048,7 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N14 +// Location: LCCOMB_X24_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) @@ -61197,7 +65074,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -61207,1083 +65084,41 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y18_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( -// Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~41_combout ), - .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y18_N13 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N28 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N14 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N6 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N24 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N0 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N1 -dffeas \ula_|video_|attr_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N7 -dffeas \ula_|video_|attr[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( -// Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - - .dataa(gnd), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(gnd), - .datad(\ula_|video_|frame [0]), - .cin(gnd), - .combout(\ula_|video_|frame[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; -defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|frame[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( -// Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|frame[1]~4_combout ), - .cout(\ula_|video_|frame[1]~5 )); -// synopsys translate_off -defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; -defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|frame[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[1]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( -// Equation(s): -// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) -// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - - .dataa(gnd), - .datab(\ula_|video_|frame [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[1]~5 ), - .combout(\ula_|video_|frame[2]~6_combout ), - .cout(\ula_|video_|frame[2]~7 )); -// synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|frame[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[2]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( -// Equation(s): -// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) -// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - - .dataa(gnd), - .datab(\ula_|video_|frame [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[2]~7 ), - .combout(\ula_|video_|frame[3]~8_combout ), - .cout(\ula_|video_|frame[3]~9 )); -// synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|frame[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[3]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( -// Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|frame [4]), - .cin(\ula_|video_|frame[3]~9 ), - .combout(\ula_|video_|frame[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; -defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|frame[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N6 -cycloneive_lcell_comb \ula_|video_|inverted ( -// Equation(s): -// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|attr [7]), - .datad(\ula_|video_|frame [4]), - .cin(gnd), - .combout(\ula_|video_|inverted~combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|inverted .lut_mask = 16'hF000; -defparam \ula_|video_|inverted .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N29 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N5 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N26 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N27 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N29 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N14 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N15 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N24 -cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( -// Equation(s): -// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [5]), - .cin(gnd), - .combout(\ula_|video_|bits[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N12 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N13 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N20 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N21 -dffeas \ula_|video_|bits_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N14 -cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( -// Equation(s): -// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [2]), - .cin(gnd), - .combout(\ula_|video_|bits[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N15 -dffeas \ula_|video_|bits[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N18 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N19 -dffeas \ula_|video_|bits_prefetch[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N1 -dffeas \ula_|video_|bits[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N6 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N7 -dffeas \ula_|video_|bits_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N20 -cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( -// Equation(s): -// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|bits[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N21 -dffeas \ula_|video_|bits[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N24 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N25 -dffeas \ula_|video_|bits_prefetch[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N3 -dffeas \ula_|video_|bits[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N2 -cycloneive_lcell_comb \ula_|video_|Mux0~2 ( -// Equation(s): -// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), - .datac(\ula_|video_|bits [3]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Mux0~3 ( -// Equation(s): -// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), - .datac(\ula_|video_|bits [0]), - .datad(\ula_|video_|Mux0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N10 -cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( -// Equation(s): -// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - - .dataa(\ula_|video_|inverted~combout ), - .datab(\ula_|video_|Mux0~1_combout ), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|Mux0~3_combout ), - .cin(gnd), - .combout(\ula_|video_|cindex[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; -defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N17 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N4 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N5 +// Location: LCCOMB_X30_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -62302,7 +65137,24 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N19 +// Location: LCCOMB_X29_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N11 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62321,82 +65173,832 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N16 +// Location: LCCOMB_X25_Y31_N6 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N7 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N27 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N21 +dffeas \ula_|video_|attr_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N7 +dffeas \ula_|video_|attr[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N2 +cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( +// Equation(s): +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) + + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|frame [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|frame[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h3C3C; +defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y31_N3 +dffeas \ula_|video_|frame[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N14 +cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( +// Equation(s): +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) + + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|frame[1]~4_combout ), + .cout(\ula_|video_|frame[1]~5 )); +// synopsys translate_off +defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; +defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N15 +dffeas \ula_|video_|frame[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N16 +cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( +// Equation(s): +// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) +// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) + + .dataa(gnd), + .datab(\ula_|video_|frame [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[1]~5 ), + .combout(\ula_|video_|frame[2]~6_combout ), + .cout(\ula_|video_|frame[2]~7 )); +// synopsys translate_off +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N17 +dffeas \ula_|video_|frame[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N18 +cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( +// Equation(s): +// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) +// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) + + .dataa(gnd), + .datab(\ula_|video_|frame [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[2]~7 ), + .combout(\ula_|video_|frame[3]~8_combout ), + .cout(\ula_|video_|frame[3]~9 )); +// synopsys translate_off +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N19 +dffeas \ula_|video_|frame[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N20 +cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( +// Equation(s): +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame [4]), + .cin(\ula_|video_|frame[3]~9 ), + .combout(\ula_|video_|frame[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N1 +dffeas \ula_|video_|frame[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N6 +cycloneive_lcell_comb \ula_|video_|inverted ( +// Equation(s): +// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|attr [7]), + .datad(\ula_|video_|frame [4]), + .cin(gnd), + .combout(\ula_|video_|inverted~combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|inverted .lut_mask = 16'hF000; +defparam \ula_|video_|inverted .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N13 +dffeas \ula_|video_|bits_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N1 +dffeas \ula_|video_|bits[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N19 +dffeas \ula_|video_|bits_prefetch[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N31 +dffeas \ula_|video_|bits[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N15 +dffeas \ula_|video_|bits_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N22 +cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( +// Equation(s): +// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [1]), + .cin(gnd), + .combout(\ula_|video_|bits[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y31_N23 +dffeas \ula_|video_|bits[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N17 +dffeas \ula_|video_|bits_prefetch[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N21 +dffeas \ula_|video_|bits[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Mux0~2 ( +// Equation(s): +// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [1]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [3] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Mux0~3 ( +// Equation(s): +// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), + .datac(\ula_|video_|bits [0]), + .datad(\ula_|video_|Mux0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N4 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N5 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N29 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N11 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N19 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N30 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N31 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N25 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N9 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N29 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N16 +cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Equation(s): +// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~3_combout )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~1_combout ))))) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~3_combout ), + .datad(\ula_|video_|Mux0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|cindex[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h396C; +defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N26 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), + .dataa(\ula_|video_|attr [1]), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|attr [1]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N4 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y31_N20 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|video_|LessThan6~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N2 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N14 +// Location: LCCOMB_X27_Y31_N10 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): // \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~0_combout ), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~0_combout ), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N0 +// Location: LCCOMB_X26_Y31_N24 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [5]), .datab(gnd), - .datac(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), @@ -62406,84 +66008,189 @@ defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N4 +// Location: LCCOMB_X26_Y31_N30 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): // \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & // !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_hc [7]), .datac(\ula_|video_|vga_hc [9]), .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7A5E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N12 +// Location: LCCOMB_X27_Y31_N16 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [6]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h4F00; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N24 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) +// \ula_|video_|disp_enable~1_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & !\ula_|video_|LessThan2~1_combout )) - .dataa(gnd), - .datab(\ula_|video_|LessThan2~1_combout ), - .datac(\ula_|video_|LessThan3~0_combout ), - .datad(\ula_|video_|disp_enable~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), + .datac(gnd), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h0088; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N26 -cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( -// Equation(s): -// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - - .dataa(\ula_|border [1]), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), - .cin(gnd), - .combout(\ula_|video_|VGA_R[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; -defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N22 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N23 -dffeas \ula_|video_|attr_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), +// Location: FF_X24_Y19_N17 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[1]~12_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N0 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N26 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N24 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N10 +cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( +// Equation(s): +// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout )) # (!\ula_|video_|screen_en~1_combout & ((\ula_|border [1]))))) + + .dataa(\ula_|video_|cindex[1]~1_combout ), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [1]), + .datad(\ula_|video_|screen_en~1_combout ), + .cin(gnd), + .combout(\ula_|video_|VGA_R[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'h88C0; +defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N23 +dffeas \ula_|video_|attr_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62494,7 +66201,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y30_N29 +// Location: FF_X27_Y31_N27 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62513,66 +66220,49 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N28 +// Location: LCCOMB_X27_Y31_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & \ula_|video_|LessThan3~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|LessThan2~1_combout ), + .datad(\ula_|video_|LessThan3~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N6 +// Location: LCCOMB_X28_Y31_N4 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(gnd), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y27_N20 -cycloneive_lcell_comb \ula_|border[2]~feeder ( -// Equation(s): -// \ula_|border[2]~feeder_combout = \D[2]~53_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[2]~53_combout ), - .cin(gnd), - .combout(\ula_|border[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y27_N21 +// Location: FF_X24_Y19_N5 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[2]~13_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62583,79 +66273,24 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N30 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N31 -dffeas \ula_|video_|attr_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N31 -dffeas \ula_|video_|attr[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N16 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N17 +// Location: FF_X25_Y31_N25 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -62674,15 +66309,32 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N13 +// Location: LCCOMB_X28_Y31_N30 +cycloneive_lcell_comb \ula_|video_|attr[2]~feeder ( +// Equation(s): +// \ula_|video_|attr[2]~feeder_combout = \ula_|video_|attr_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|attr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N31 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), + .d(\ula_|video_|attr[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62693,48 +66345,103 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N30 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 +dffeas \ula_|video_|attr_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N5 +dffeas \ula_|video_|attr[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N4 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|attr [2]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N0 +// Location: LCCOMB_X29_Y31_N2 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|border [2]), - .datad(\ula_|video_|cindex[2]~2_combout ), + .dataa(\ula_|border [2]), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|video_|cindex[2]~2_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC088; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N18 +// Location: LCCOMB_X28_Y31_N12 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[2]~2_combout )) - .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), @@ -62744,32 +66451,15 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~65_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~65_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 +// Location: FF_X23_Y20_N25 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~14_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62780,24 +66470,24 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N8 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N9 +// Location: FF_X25_Y31_N1 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -62816,15 +66506,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N23 +// Location: LCCOMB_X28_Y31_N2 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N3 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62835,24 +66542,24 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -62871,7 +66578,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N9 +// Location: FF_X29_Y31_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62890,47 +66597,47 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N8 +// Location: LCCOMB_X29_Y31_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[2]~0_combout ), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N26 +// Location: LCCOMB_X29_Y31_N6 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[0]~3_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N12 +// Location: LCCOMB_X29_Y31_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|cindex[0]~3_combout ), - .datab(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|cindex[0]~3_combout ), .datac(gnd), .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), @@ -62941,24 +66648,7 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~2 ( -// Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; -defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y29_N1 +// Location: FF_X30_Y31_N13 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -62977,16 +66667,33 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N0 +// Location: LCCOMB_X30_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Equal0~2 ( +// Equation(s): +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9])) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h000A; +defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N12 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~1_combout & ((\ula_|video_|Equal0~2_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~1_combout & (\ula_|video_|Equal1~0_combout & // (\ula_|video_|VGA_HS~_Duplicate_1_q ))) - .dataa(\ula_|video_|Equal0~2_combout ), + .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); @@ -63014,7 +66721,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X31_Y31_N29 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -63033,21 +66740,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X31_Y31_N28 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((!\ula_|video_|Equal3~1_combout & \ula_|video_|VGA_VS~_Duplicate_1_q )))) # (!\ula_|video_|Equal2~2_combout & (!\ula_|video_|Equal3~1_combout & +// (\ula_|video_|VGA_VS~_Duplicate_1_q ))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hBA30; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63070,7 +66777,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N4 +// Location: LCCOMB_X36_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -63087,7 +66794,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N5 +// Location: FF_X36_Y11_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -63106,7 +66813,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y13_N3 +// Location: FF_X36_Y11_N1 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -63125,7 +66832,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 +// Location: LCCOMB_X36_Y11_N0 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -63142,41 +66849,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N24 +// Location: LCCOMB_X52_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF33; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N24 +// Location: LCCOMB_X23_Y18_N4 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~38_combout $ (\D[4]~39_combout )) - .dataa(\D[3]~109_combout ), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\D[4]~111_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~38_combout ), + .datac(gnd), + .datad(\D[4]~39_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA55A; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N25 +// Location: FF_X23_Y18_N5 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -63195,160 +66902,194 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N4 +// Location: LCCOMB_X29_Y8_N18 cycloneive_lcell_comb \sdram_|Mux26~4 ( // Equation(s): // \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.address[3]~6_combout ), .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), .combout(\sdram_|Mux26~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .lut_mask = 16'h0F05; defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N10 -cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( -// Equation(s): -// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.bank[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; -defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N8 -cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( -// Equation(s): -// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.bank[0]~7_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; -defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( -// Equation(s): -// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; -defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( -// Equation(s): -// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.bank[0]~4_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; -defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N4 +// Location: LCCOMB_X19_Y13_N28 cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( // Equation(s): -// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # -// (\sdram_|r.bank[0]~5_combout ))))) +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.bank[0]~5_combout ), + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.bank[0]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hA005; defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( // Equation(s): -// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) +// \sdram_|r.bank[0]~4_combout = (\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.bank[0]~8_combout ), + .combout(\sdram_|r.bank[0]~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; -defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hFC00; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N18 +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [6] & ((\sdram_|r.bank[0]~4_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'hF888; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( // Equation(s): -// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) +// \sdram_|r.bank[0]~12_combout = ((!\sdram_|r.bank[0]~5_combout & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|r.bank[0]~6_combout ) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.bank[0]~11_combout ), - .datad(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.bank[0]~6_combout ), + .datac(\sdram_|r.bank[0]~5_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'h373F; defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N2 +// Location: LCCOMB_X19_Y13_N22 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [5]) # ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hAFFF; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [7] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'h5A7A; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( // Equation(s): -// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [4]) # ((\sdram_|r.bank[0]~8_combout ) # ((\sdram_|r.state [5] & !\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.bank[0]~11_combout ), - .datac(\sdram_|r.bank[0]~6_combout ), - .datad(\sdram_|r.bank[0]~12_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~8_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'hFFF2; defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~9_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~7_combout ), + .datad(\sdram_|r.bank[0]~9_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'hB9A8; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~13 ( +// Equation(s): +// \sdram_|r.bank[0]~13_combout = ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [7])))) # (!\sdram_|r.bank[0]~5_combout ) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.bank[0]~5_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~13 .lut_mask = 16'h7FFB; +defparam \sdram_|r.bank[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N26 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.state [8] & ((\sdram_|r.bank[0]~10_combout & ((!\sdram_|r.bank[0]~13_combout ))) # (!\sdram_|r.bank[0]~10_combout & (!\sdram_|r.bank[0]~12_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~10_combout +// )))) + + .dataa(\sdram_|r.bank[0]~12_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~10_combout ), + .datad(\sdram_|r.bank[0]~13_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'h07C7; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X11_Y0_N18 dffeas \sdram_|r.bank[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -63358,7 +67099,7 @@ dffeas \sdram_|r.bank[0] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [0]), @@ -63368,20 +67109,20 @@ defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; defparam \sdram_|r.bank[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N2 +// Location: LCCOMB_X29_Y8_N26 cycloneive_lcell_comb \sdram_|Mux25~4 ( // Equation(s): // \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [10]), + .datab(\sdram_|r.address[3]~6_combout ), .datac(gnd), - .datad(\sdram_|r.address[3]~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\sdram_|Mux25~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .lut_mask = 16'h2233; defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63394,7 +67135,7 @@ dffeas \sdram_|r.bank[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [1]), @@ -63404,146 +67145,146 @@ defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; defparam \sdram_|r.bank[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux71~6 ( // Equation(s): -// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) +// \sdram_|Mux71~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [4] & \sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux24~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; -defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux71~0 ( -// Equation(s): -// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|Mux71~0_combout ), + .combout(\sdram_|Mux71~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; -defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux71~6 .lut_mask = 16'hF710; +defparam \sdram_|Mux71~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N4 -cycloneive_lcell_comb \sdram_|process_0~7 ( -// Equation(s): -// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\sdram_|r.act_row [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\sdram_|process_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; -defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N28 -cycloneive_lcell_comb \sdram_|process_0~4 ( -// Equation(s): -// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|process_0~7_combout ), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|process_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; -defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux71~1 ( -// Equation(s): -// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux71~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; -defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N28 +// Location: LCCOMB_X20_Y15_N0 cycloneive_lcell_comb \sdram_|Mux71~2 ( // Equation(s): -// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) +// \sdram_|Mux71~2_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux71~1_combout ), - .datad(\sdram_|Mux71~0_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux71~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .lut_mask = 16'h000F; defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N14 +// Location: LCCOMB_X20_Y15_N16 cycloneive_lcell_comb \sdram_|Mux71~3 ( // Equation(s): -// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) +// \sdram_|Mux71~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [7])) # (!\sdram_|Mux71~2_combout ))) # (!\sdram_|r.state [8] & ((\sdram_|Mux71~2_combout ) # ((!\sdram_|Mux4~0_combout )))) - .dataa(\sdram_|process_0~4_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux71~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux71~2_combout ), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux71~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .lut_mask = 16'hEF67; defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N4 +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \sdram_|process_0~8 ( +// Equation(s): +// \sdram_|process_0~8_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\sdram_|process_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~8 .lut_mask = 16'h0FA5; +defparam \sdram_|process_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (((\sdram_|process_0~8_combout ) # (!\sdram_|Equal7~1_combout )) # (!\sdram_|Equal7~0_combout )) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|process_0~8_combout ), + .datad(\sdram_|Equal7~1_combout ), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hF7FF; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 cycloneive_lcell_comb \sdram_|Mux71~4 ( // Equation(s): -// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) +// \sdram_|Mux71~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux71~6_combout & ((\sdram_|Mux71~3_combout ) # (\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux71~3_combout )))) - .dataa(\sdram_|Mux24~5_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|Mux71~3_combout ), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|Mux71~6_combout ), + .datab(\sdram_|Mux71~3_combout ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux71~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .lut_mask = 16'hA8CC; defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux24~8 ( +// Equation(s): +// \sdram_|Mux24~8_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~8 .lut_mask = 16'h0307; +defparam \sdram_|Mux24~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux71~5 ( +// Equation(s): +// \sdram_|Mux71~5_combout = (\sdram_|Mux71~4_combout ) # ((\sdram_|Mux24~8_combout & ((\sdram_|r.state [7]) # (\sdram_|Mux71~2_combout )))) + + .dataa(\sdram_|Mux71~4_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~8_combout ), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~5 .lut_mask = 16'hFAEA; +defparam \sdram_|Mux71~5 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y0_N11 dffeas \sdram_|r.dq_masks[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63562,7 +67303,7 @@ defparam \sdram_|r.dq_masks[0] .power_up = "low"; // Location: DDIOOUTCELL_X14_Y0_N18 dffeas \sdram_|r.dq_masks[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63578,248 +67319,248 @@ defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; defparam \sdram_|r.dq_masks[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N2 -cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \sdram_|n~6 ( // Equation(s): -// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) +// \sdram_|n~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.bank[0]~10_combout ), + .combout(\sdram_|n~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; -defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +defparam \sdram_|n~6 .lut_mask = 16'h5051; +defparam \sdram_|n~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N18 -cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Location: LCCOMB_X19_Y19_N12 +cycloneive_lcell_comb \sdram_|Mux9~0 ( // Equation(s): -// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) +// \sdram_|Mux9~0_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [7] & ((!\sdram_|r.state [4]))) # (!\sdram_|r.state [7] & ((\sdram_|n~6_combout ) # (\sdram_|r.state [4]))))) + + .dataa(\sdram_|n~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~0 .lut_mask = 16'h3E00; +defparam \sdram_|Mux9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N14 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|r.state [6] & (!\sdram_|n~2_combout & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (((\sdram_|n~6_combout )))) .dataa(\sdram_|n~2_combout ), .datab(\sdram_|r.state [6]), .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.bank[0]~10_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; -defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N30 -cycloneive_lcell_comb \sdram_|n~5 ( -// Equation(s): -// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|n~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|n~5 .lut_mask = 16'h3031; -defparam \sdram_|n~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N12 -cycloneive_lcell_comb \sdram_|Mux9~4 ( -// Equation(s): -// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) - - .dataa(\sdram_|Mux9~3_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux9~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N4 -cycloneive_lcell_comb \sdram_|Mux9~2 ( -// Equation(s): -// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux9~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; -defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N30 -cycloneive_lcell_comb \sdram_|Equal2~3 ( -// Equation(s): -// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Equal2~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; -defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N8 -cycloneive_lcell_comb \sdram_|Mux10~2 ( -// Equation(s): -// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [4]), - .cin(gnd), - .combout(\sdram_|Mux10~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; -defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N26 -cycloneive_lcell_comb \sdram_|Mux10~3 ( -// Equation(s): -// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) - - .dataa(\sdram_|r.init_counter [2]), - .datab(\sdram_|r.init_counter [3]), - .datac(\sdram_|Mux10~2_combout ), - .datad(\sdram_|r.init_counter [1]), - .cin(gnd), - .combout(\sdram_|Mux10~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; -defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N4 -cycloneive_lcell_comb \sdram_|process_0~6 ( -// Equation(s): -// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|process_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~6 .lut_mask = 16'h0010; -defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N24 -cycloneive_lcell_comb \sdram_|Mux10~4 ( -// Equation(s): -// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) - - .dataa(\sdram_|Mux10~3_combout ), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|process_0~6_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux10~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; -defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux9~5 ( -// Equation(s): -// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|n~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; -defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N20 -cycloneive_lcell_comb \sdram_|Mux7~0 ( -// Equation(s): -// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; -defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~6 ( -// Equation(s): -// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|Mux10~4_combout ), - .datac(\sdram_|Mux9~5_combout ), - .datad(\sdram_|Mux7~0_combout ), + .datad(\sdram_|n~6_combout ), .cin(gnd), .combout(\sdram_|Mux9~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .lut_mask = 16'h7340; defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N24 +// Location: LCCOMB_X19_Y19_N0 cycloneive_lcell_comb \sdram_|Mux9~7 ( // Equation(s): -// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~6_combout & ((\sdram_|r.state [6]) # ((\sdram_|r.state [5]) # (\sdram_|r.state [7])))) # (!\sdram_|Mux9~6_combout & ((\sdram_|r.state [5] $ (\sdram_|r.state [7])))) - .dataa(\sdram_|Mux9~4_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|Mux9~2_combout ), - .datad(\sdram_|Mux9~6_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux9~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux9~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .lut_mask = 16'hCFF8; defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y19_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h000F; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (!\sdram_|r.init_counter [0] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h4000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (\sdram_|process_0~5_combout & (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14]))) + + .dataa(\sdram_|process_0~5_combout ), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0002; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [6]), + .datab(gnd), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h0500; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \sdram_|Equal5~1 ( +// Equation(s): +// \sdram_|Equal5~1_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal5~0_combout & (\sdram_|r.init_counter [1] & \sdram_|process_0~6_combout ))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal5~0_combout ), + .datac(\sdram_|r.init_counter [1]), + .datad(\sdram_|process_0~6_combout ), + .cin(gnd), + .combout(\sdram_|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~1 .lut_mask = 16'h8000; +defparam \sdram_|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = (!\sdram_|r.init_counter [7] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [2] & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [7]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h4000; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (!\sdram_|Equal5~1_combout & (((!\sdram_|process_0~7_combout ) # (!\sdram_|process_0~6_combout )) # (!\sdram_|r.init_counter [3]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|process_0~6_combout ), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|process_0~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'h070F; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N6 +cycloneive_lcell_comb \sdram_|Mux9~1 ( +// Equation(s): +// \sdram_|Mux9~1_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~1 .lut_mask = 16'hFFD0; +defparam \sdram_|Mux9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N2 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|Mux9~1_combout ) # ((\sdram_|Mux7~0_combout & (!\sdram_|Equal2~3_combout & \sdram_|Mux10~2_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|Equal2~3_combout ), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux9~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'hFF20; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|Mux9~0_combout ) # ((\sdram_|Mux9~7_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~2_combout ))) + + .dataa(\sdram_|Mux9~0_combout ), + .datab(\sdram_|Mux9~7_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux9~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hEFEE; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X0_Y11_N4 dffeas \sdram_|r.state[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux9~7_combout ), + .d(\sdram_|Mux9~3_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63835,112 +67576,163 @@ defparam \sdram_|r.state[2] .is_wysiwyg = "true"; defparam \sdram_|r.state[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux10~11 ( -// Equation(s): -// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; -defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N12 +// Location: LCCOMB_X19_Y17_N12 cycloneive_lcell_comb \sdram_|Mux10~6 ( // Equation(s): -// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) +// \sdram_|Mux10~6_combout = (\sdram_|r.state [4] & (((\sdram_|r.rd_pending~q & \sdram_|r.state [6])) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & (((\sdram_|r.state [6]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Mux10~11_combout ), - .datac(\sdram_|process_0~4_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .lut_mask = 16'hD5FA; defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N26 +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((\sdram_|Mux10~2_combout & !\sdram_|Mux10~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h6676; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.state [8]) # ((\sdram_|r.state [4] & \sdram_|r.state [7])))) # (!\sdram_|r.rf_pending~q & (\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'hEEA2; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [8])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [8]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'h1120; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 cycloneive_lcell_comb \sdram_|Mux10~5 ( // Equation(s): -// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) +// \sdram_|Mux10~5_combout = (\sdram_|r.state [6] & ((\sdram_|Mux10~3_combout ) # ((!\sdram_|Mux10~4_combout )))) # (!\sdram_|r.state [6] & ((\sdram_|Mux10~4_combout & ((!\sdram_|n~4_combout ))) # (!\sdram_|Mux10~4_combout & (\sdram_|Mux10~3_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~3_combout ), + .datac(\sdram_|n~4_combout ), .datad(\sdram_|Mux10~4_combout ), .cin(gnd), .combout(\sdram_|Mux10~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .lut_mask = 16'h8DEE; defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N10 +// Location: LCCOMB_X19_Y17_N22 cycloneive_lcell_comb \sdram_|Mux10~7 ( // Equation(s): -// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & ((\sdram_|r.wr_pending~q ) # ((!\sdram_|r.rf_pending~q & \sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|r.rf_pending~q )) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .lut_mask = 16'hDACA; defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N20 +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~6_combout ) # ((!\sdram_|r.state [6] & !\sdram_|n~4_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|n~4_combout ), + .datac(\sdram_|Mux10~7_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hFFF1; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux10~12 ( +// Equation(s): +// \sdram_|Mux10~12_combout = (\sdram_|r.state [7] & (((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (\sdram_|r.state [6] & (\sdram_|process_0~3_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~12 .lut_mask = 16'hEC20; +defparam \sdram_|Mux10~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 cycloneive_lcell_comb \sdram_|Mux10~8 ( // Equation(s): -// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) +// \sdram_|Mux10~8_combout = (\sdram_|Mux10~10_combout ) # ((\sdram_|Mux10~12_combout ) # ((!\sdram_|r.state [7] & \sdram_|Mux10~5_combout ))) - .dataa(\sdram_|Mux10~7_combout ), + .dataa(\sdram_|Mux10~10_combout ), .datab(\sdram_|r.state [7]), .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~11_combout ), + .datad(\sdram_|Mux10~12_combout ), .cin(gnd), .combout(\sdram_|Mux10~8_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .lut_mask = 16'hFFBA; defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux10~9 ( -// Equation(s): -// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) - - .dataa(\sdram_|Mux10~6_combout ), - .datab(\sdram_|r.bank[0]~10_combout ), - .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux10~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; -defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y11_N11 dffeas \sdram_|r.state[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux10~9_combout ), + .d(\sdram_|Mux10~8_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63969,146 +67761,129 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux11~2 ( -// Equation(s): -// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux11~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; -defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux11~3 ( -// Equation(s): -// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|Mux11~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux11~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; -defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N26 +// Location: LCCOMB_X18_Y17_N26 cycloneive_lcell_comb \sdram_|Mux11~4 ( // Equation(s): -// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) +// \sdram_|Mux11~4_combout = (\sdram_|r.state [5] & ((\sdram_|r.state [8] $ (\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & (\sdram_|r.state [7])) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|Mux11~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux11~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .lut_mask = 16'h6EE6; defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N28 +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|r.state [6] & (((\sdram_|n~6_combout ) # (!\sdram_|r.state [8])) # (!\sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hCC4C; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (!\sdram_|Equal2~3_combout & (!\sdram_|r.state [8] & (!\sdram_|Equal5~1_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'h0001; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~2_combout ) # ((!\sdram_|Mux23~0_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|Mux11~2_combout ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 cycloneive_lcell_comb \sdram_|Mux11~5 ( // Equation(s): -// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) +// \sdram_|Mux11~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((\sdram_|r.state [8] & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux11~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .lut_mask = 16'h0C0E; defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N0 +// Location: LCCOMB_X18_Y17_N10 cycloneive_lcell_comb \sdram_|Mux11~6 ( // Equation(s): -// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) +// \sdram_|Mux11~6_combout = (\sdram_|Mux11~5_combout & (!\sdram_|r.wr_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|Mux11~5_combout ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux11~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .lut_mask = 16'h008A; defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N30 +// Location: LCCOMB_X18_Y17_N24 cycloneive_lcell_comb \sdram_|Mux11~7 ( // Equation(s): -// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) +// \sdram_|Mux11~7_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~8_combout ) # ((\sdram_|Mux11~3_combout ) # (\sdram_|Mux11~6_combout ))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~8_combout ), + .datac(\sdram_|Mux11~3_combout ), .datad(\sdram_|Mux11~6_combout ), .cin(gnd), .combout(\sdram_|Mux11~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .lut_mask = 16'hFFFE; defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux11~9 ( -// Equation(s): -// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|Mux7~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; -defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N14 -cycloneive_lcell_comb \sdram_|Mux11~8 ( -// Equation(s): -// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) - - .dataa(\sdram_|Mux11~4_combout ), - .datab(\sdram_|Mux11~5_combout ), - .datac(\sdram_|Mux11~7_combout ), - .datad(\sdram_|Mux11~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; -defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y27_N4 dffeas \sdram_|r.state[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux11~8_combout ), + .d(\sdram_|Mux11~7_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -64124,75 +67899,41 @@ defparam \sdram_|r.state[0] .is_wysiwyg = "true"; defparam \sdram_|r.state[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \sdram_|Mux24~5 ( // Equation(s): -// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) +// \sdram_|Mux24~5_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[11]~18_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q )))) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux24~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; -defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N2 -cycloneive_lcell_comb \sdram_|r.address[0]~7 ( -// Equation(s): -// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .dataa(\sdram_|process_0~4_combout ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\sdram_|Mux23~0_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~7_combout ), + .combout(\sdram_|Mux24~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; -defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~5 .lut_mask = 16'hE400; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N12 -cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \sdram_|Mux24~6 ( // Equation(s): -// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) +// \sdram_|Mux24~6_combout = (\sdram_|Mux24~5_combout ) # ((!\sdram_|n~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.address[0]~_Duplicate_1_q ), - .datad(\sdram_|r.address[0]~7_combout ), + .dataa(\sdram_|n~4_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux24~5_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~0_combout ), + .combout(\sdram_|Mux24~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; -defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~6 .lut_mask = 16'hFF04; +defparam \sdram_|Mux24~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux13~9 ( -// Equation(s): -// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux13~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; -defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N0 +// Location: LCCOMB_X21_Y16_N6 cycloneive_lcell_comb \sdram_|Mux13~4 ( // Equation(s): // \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) @@ -64209,28 +67950,45 @@ defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N2 +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 cycloneive_lcell_comb \sdram_|Mux13~5 ( // Equation(s): -// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux13~9_combout ))) - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux13~9_combout ), - .datad(\sdram_|Mux13~4_combout ), + .dataa(\sdram_|Mux13~4_combout ), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux13~9_combout ), .cin(gnd), .combout(\sdram_|Mux13~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .lut_mask = 16'hAFA0; defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N13 +// Location: FF_X20_Y14_N21 dffeas \sdram_|r.address[0]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[0]~0_combout ), - .asdata(\sdram_|Mux24~4_combout ), + .asdata(\sdram_|Mux24~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64245,54 +68003,88 @@ defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N4 +// Location: LCCOMB_X19_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & (\z80_|address_pins_|abus[11]~18_combout )) # (!\sdram_|process_0~4_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hD800; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 cycloneive_lcell_comb \sdram_|Mux24~3 ( // Equation(s): -// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) +// \sdram_|Mux24~3_combout = (\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q ) - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux24~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .lut_mask = 16'hFF55; defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N14 +// Location: LCCOMB_X21_Y14_N6 cycloneive_lcell_comb \sdram_|Mux24~4 ( // Equation(s): -// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) +// \sdram_|Mux24~4_combout = (\sdram_|r.address[0]~_Duplicate_1_q & (((!\sdram_|r.rd_pending~q & \sdram_|Mux24~3_combout )) # (!\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|n~3_combout ), + .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux24~3_combout ), - .datad(\sdram_|r.state [6]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux24~3_combout ), .cin(gnd), .combout(\sdram_|Mux24~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .lut_mask = 16'h4C0C; defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N24 +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & ((\sdram_|Mux24~4_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux24~2_combout )) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux24~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'hEE22; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux24~6_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[0]~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux24~4_combout ), - .datad(\sdram_|r.address[0]~0_combout ), + .datab(\sdram_|r.address[0]~0_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux24~6_combout ), .cin(gnd), .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64315,114 +68107,148 @@ defparam \sdram_|r.address[0] .is_wysiwyg = "true"; defparam \sdram_|r.address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N16 +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [4] & (\sdram_|process_0~4_combout & ((\sdram_|Equal7~2_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'h8880; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~8 ( +// Equation(s): +// \sdram_|r.address[1]~8_combout = (\sdram_|r.state [4]) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~8 .lut_mask = 16'hEEFF; +defparam \sdram_|r.address[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[1]~9 ( +// Equation(s): +// \sdram_|r.address[1]~9_combout = (\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~9 .lut_mask = 16'hDD00; +defparam \sdram_|r.address[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \sdram_|r.address[1]~7 ( +// Equation(s): +// \sdram_|r.address[1]~7_combout = (\sdram_|r.address[1]~_Duplicate_1_q & (((\sdram_|r.state [8]) # (!\sdram_|r.state [6])) # (!\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~7 .lut_mask = 16'hF070; +defparam \sdram_|r.address[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|r.address[1]~10 ( +// Equation(s): +// \sdram_|r.address[1]~10_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~9_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[1]~7_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[1]~9_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~10 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~8_combout & (\sdram_|r.address[1]~10_combout ))) # (!\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~7_combout & ((\sdram_|r.address[1]~8_combout ) # +// (!\sdram_|r.address[1]~10_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|r.address[1]~8_combout ), + .datac(\sdram_|r.address[1]~10_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hC580; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( // Equation(s): // \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout - .dataa(\sdram_|r.address[1]~1_combout ), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hFF00; defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux23~4 ( -// Equation(s): -// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & -// (\sdram_|r.address[1]~_Duplicate_1_q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\z80_|address_pins_|abus[12]~24_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; -defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N16 -cycloneive_lcell_comb \sdram_|Equal5~0 ( -// Equation(s): -// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Equal5~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; -defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux23~5 ( -// Equation(s): -// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux23~4_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Equal5~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; -defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux23~6 ( -// Equation(s): -// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|Mux23~5_combout ), - .datad(\sdram_|Mux24~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; -defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N2 +// Location: LCCOMB_X21_Y16_N30 cycloneive_lcell_comb \sdram_|Mux19~0 ( // Equation(s): // \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .lut_mask = 16'h9299; defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y12_N17 +// Location: FF_X25_Y16_N25 dffeas \sdram_|r.address[1]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), - .asdata(\sdram_|Mux23~6_combout ), + .asdata(\sdram_|Mux23~5_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64437,88 +68263,89 @@ defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N28 -cycloneive_lcell_comb \sdram_|Mux23~2 ( -// Equation(s): -// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux23~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; -defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N30 +// Location: LCCOMB_X20_Y17_N2 cycloneive_lcell_comb \sdram_|Mux23~3 ( // Equation(s): -// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) +// \sdram_|Mux23~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.address[1]~_Duplicate_1_q )))) # (!\sdram_|r.state [8] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[12]~21_combout ))) # (!\sdram_|process_0~4_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|Mux23~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), .cin(gnd), .combout(\sdram_|Mux23~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .lut_mask = 16'hF4B0; defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N18 -cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Location: LCCOMB_X20_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux23~4 ( // Equation(s): -// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (((\sdram_|Mux23~3_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((\sdram_|Mux23~3_combout ))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )))) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|Mux23~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hCCCA; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = ((!\sdram_|r.rd_pending~q & ((\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|Equal7~2_combout ) .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux23~1_combout ), + .combout(\sdram_|Mux23~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; -defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~2 .lut_mask = 16'h33BF; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N22 -cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( // Equation(s): -// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) +// \sdram_|Mux23~5_combout = (\sdram_|Mux23~4_combout & (((\sdram_|Mux23~2_combout ) # (\sdram_|r.state [4])) # (!\sdram_|r.state [8]))) - .dataa(gnd), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~3_combout ), - .datad(\sdram_|Mux23~1_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|Mux23~2_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.address[1]~1_combout ), + .combout(\sdram_|Mux23~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; -defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~5 .lut_mask = 16'hCCC4; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N2 +// Location: LCCOMB_X21_Y16_N4 cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|r.address[1]~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux23~5_combout )) - .dataa(\sdram_|r.address[1]~1_combout ), - .datab(\sdram_|Mux23~6_combout ), + .dataa(gnd), + .datab(\sdram_|Mux23~5_combout ), .datac(\sdram_|r.state [7]), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64541,211 +68368,211 @@ defparam \sdram_|r.address[1] .is_wysiwyg = "true"; defparam \sdram_|r.address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N10 -cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( // Equation(s): -// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[3]~8_combout ), + .combout(\sdram_|r.address[3]~11_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; -defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h5F5C; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N24 -cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( // Equation(s): -// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) +// \sdram_|r.address[3]~12_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|r.address[3]~9_combout ), + .combout(\sdram_|r.address[3]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; -defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hF000; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N26 +// Location: LCCOMB_X23_Y14_N28 cycloneive_lcell_comb \sdram_|Mux21~0 ( // Equation(s): -// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~11_combout & ((\sdram_|r.address[3]~12_combout ) # ((\sdram_|r.state [4] & \sdram_|r.address[3]~6_combout )))) - .dataa(\sdram_|r.address[3]~6_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.address[3]~9_combout ), - .datad(\sdram_|r.address[3]~8_combout ), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.address[3]~12_combout ), .cin(gnd), .combout(\sdram_|Mux21~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .lut_mask = 16'h5540; defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N18 +// Location: LCCOMB_X24_Y8_N12 cycloneive_lcell_comb \sdram_|Mux22~0 ( // Equation(s): -// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[1]~27_combout ) # ((\z80_|address_pins_|abus[13]~20_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[13]~20_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[1]~25_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[1]~27_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux22~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .lut_mask = 16'hECA0; defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N20 -cycloneive_lcell_comb \sdram_|r.address[3]~10 ( -// Equation(s): -// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.address[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; -defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N14 -cycloneive_lcell_comb \sdram_|r.address[3]~11 ( -// Equation(s): -// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|r.address[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; -defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N0 -cycloneive_lcell_comb \sdram_|r.address[3]~12 ( -// Equation(s): -// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~11_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; -defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N6 -cycloneive_lcell_comb \sdram_|r.address[3]~13 ( -// Equation(s): -// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[3]~10_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.address[3]~12_combout ), - .cin(gnd), - .combout(\sdram_|r.address[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; -defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N16 +// Location: LCCOMB_X18_Y17_N12 cycloneive_lcell_comb \sdram_|r.address[3]~14 ( // Equation(s): -// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), + .dataa(gnd), + .datab(\sdram_|r.state [4]), .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.address[3]~14_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h33CF; defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N22 +// Location: LCCOMB_X18_Y17_N30 cycloneive_lcell_comb \sdram_|r.address[3]~15 ( // Equation(s): -// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [8] & ((\sdram_|r.state [4]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4]))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~14_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.address[3]~14_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~15_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hFF9B; defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N24 +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|r.state [4])) # (!\sdram_|r.state [7]) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'h37FF; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 cycloneive_lcell_comb \sdram_|r.address[3]~16 ( // Equation(s): -// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~15_combout )))) - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [5]), .datac(\sdram_|r.address[3]~15_combout ), - .datad(\sdram_|r.state [8]), + .datad(\sdram_|r.address[3]~13_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~16_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .lut_mask = 16'hFC74; defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N26 +// Location: LCCOMB_X19_Y13_N24 cycloneive_lcell_comb \sdram_|r.address[3]~17 ( // Equation(s): -// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & (!\sdram_|r.wr_pending~q & \sdram_|r.state [4]))) - .dataa(\sdram_|r.address[3]~13_combout ), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.address[3]~16_combout ), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|r.address[3]~17_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .lut_mask = 16'hAB02; defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~18 ( +// Equation(s): +// \sdram_|r.address[3]~18_combout = (\sdram_|r.address[3]~17_combout ) # ((\sdram_|r.state [7] & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (\sdram_|r.state [5]))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[3]~17_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~18 .lut_mask = 16'hDEFE; +defparam \sdram_|r.address[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~19 ( +// Equation(s): +// \sdram_|r.address[3]~19_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout ) # (!\sdram_|n~4_combout )))) # (!\sdram_|r.state [8] & (\sdram_|r.address[3]~18_combout )) + + .dataa(\sdram_|r.address[3]~18_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.bank[0]~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~19 .lut_mask = 16'h2EEE; +defparam \sdram_|r.address[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[3]~20 ( +// Equation(s): +// \sdram_|r.address[3]~20_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~16_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~19_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[3]~16_combout ), + .datad(\sdram_|r.address[3]~19_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~20 .lut_mask = 16'h0A5F; +defparam \sdram_|r.address[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X5_Y0_N4 dffeas \sdram_|r.address[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -64755,7 +68582,7 @@ dffeas \sdram_|r.address[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [2]), @@ -64765,21 +68592,21 @@ defparam \sdram_|r.address[2] .is_wysiwyg = "true"; defparam \sdram_|r.address[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N2 +// Location: LCCOMB_X24_Y8_N4 cycloneive_lcell_comb \sdram_|Mux21~1 ( // Equation(s): -// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[2]~28_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[14]~22_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[2]~26_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[2]~28_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux21~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .lut_mask = 16'hECA0; defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -64792,7 +68619,7 @@ dffeas \sdram_|r.address[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [3]), @@ -64802,130 +68629,114 @@ defparam \sdram_|r.address[3] .is_wysiwyg = "true"; defparam \sdram_|r.address[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N22 +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \sdram_|Mux24~7 ( +// Equation(s): +// \sdram_|Mux24~7_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~7 .lut_mask = 16'hA0A8; +defparam \sdram_|Mux24~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 cycloneive_lcell_comb \sdram_|Mux20~4 ( // Equation(s): -// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) +// \sdram_|Mux20~4_combout = (\sdram_|Mux24~7_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~29_combout )))) # (!\sdram_|Mux24~7_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), + .dataa(\z80_|address_pins_|abus[3]~29_combout ), + .datab(\sdram_|Mux24~7_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), .cin(gnd), .combout(\sdram_|Mux20~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .lut_mask = 16'hFB08; defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N26 -cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \sdram_|Mux20~2 ( // Equation(s): -// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) - - .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\sdram_|Mux20~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; -defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux23~7 ( -// Equation(s): -// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; -defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux20~8 ( -// Equation(s): -// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) +// \sdram_|Mux20~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[15]~23_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[4]~_Duplicate_1_q )))) .dataa(\sdram_|r.state [4]), - .datab(\sdram_|n~3_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|Mux20~8_combout ), + .combout(\sdram_|Mux20~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; -defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~2 .lut_mask = 16'hA088; +defparam \sdram_|Mux20~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N18 -cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \sdram_|Mux20~3 ( // Equation(s): -// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|Mux20~3_combout = (\sdram_|Mux20~2_combout ) # ((!\sdram_|r.state [4] & \sdram_|Equal5~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|Mux20~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~10_combout ), + .combout(\sdram_|Mux20~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; -defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~3 .lut_mask = 16'hFF50; +defparam \sdram_|Mux20~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( // Equation(s): -// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux20~3_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux20~4_combout ), + .datad(\sdram_|Mux20~3_combout ), .cin(gnd), - .combout(\sdram_|Mux20~9_combout ), + .combout(\sdram_|r.address[4]~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; -defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \sdram_|r.address[4]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) +// \sdram_|r.address[4]~_Duplicate_1feeder_combout = \sdram_|r.address[4]~2_combout - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|Mux20~10_combout ), - .datad(\sdram_|Mux20~9_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~11_combout ), + .combout(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; -defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N5 +// Location: FF_X21_Y13_N17 dffeas \sdram_|r.address[4]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[4]~2_combout ), - .asdata(\sdram_|Mux20~11_combout ), + .d(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux20~9_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64940,89 +68751,122 @@ defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N2 -cycloneive_lcell_comb \sdram_|Mux20~12 ( -// Equation(s): -// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) - - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux20~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; -defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N4 +// Location: LCCOMB_X21_Y13_N20 cycloneive_lcell_comb \sdram_|Mux20~5 ( // Equation(s): -// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) +// \sdram_|Mux20~5_combout = ((\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [15]))) # (!\sdram_|r.state [6] & (\z80_|address_pins_|DFFE_apin_latch [3]))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\sdram_|Mux20~4_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux20~12_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux20~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .lut_mask = 16'hCFAF; defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N16 +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (((\sdram_|Mux20~5_combout )))) # (!\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [3]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\sdram_|r.state [8]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|Mux20~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'hEF23; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 cycloneive_lcell_comb \sdram_|Mux20~6 ( // Equation(s): -// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[4]~_Duplicate_1_q )))) +// \sdram_|Mux20~6_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .dataa(gnd), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|Mux20~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .lut_mask = 16'hCCC0; defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Mux20~7 ( // Equation(s): -// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) +// \sdram_|Mux20~7_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|Mux20~6_combout & !\sdram_|r.state [8]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~5_combout ), - .datac(gnd), - .datad(\sdram_|Mux20~6_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux20~6_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[4]~2_combout ), + .combout(\sdram_|Mux20~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; -defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~7 .lut_mask = 16'h4498; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N8 -cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \sdram_|Mux20~8 ( // Equation(s): -// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) +// \sdram_|Mux20~8_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~1_combout & ((\sdram_|Mux20~10_combout ) # (!\sdram_|Mux20~7_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~7_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|Mux20~10_combout ), + .datac(\sdram_|Mux20~7_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h8AF0; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|Mux20~8_combout & ((\sdram_|Mux20~10_combout ))) # (!\sdram_|Mux20~8_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[4]~2_combout ), - .datad(\sdram_|Mux20~11_combout ), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\sdram_|Mux20~8_combout ), + .datad(\sdram_|Mux20~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'hFC0C; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux20~9_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[4]~2_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux20~9_combout ), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hF5A0; defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65045,66 +68889,32 @@ defparam \sdram_|r.address[4] .is_wysiwyg = "true"; defparam \sdram_|r.address[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N26 -cycloneive_lcell_comb \sdram_|Mux19~1 ( -// Equation(s): -// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux19~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; -defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N12 +// Location: LCCOMB_X21_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~4 ( // Equation(s): -// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~6_combout )) - .dataa(\sdram_|r.state [8]), + .dataa(\sdram_|Mux20~6_combout ), .datab(gnd), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|Mux23~1_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux19~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .lut_mask = 16'hF0AA; defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux19~5 ( -// Equation(s): -// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux19~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; -defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N20 +// Location: LCCOMB_X20_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~6 ( // Equation(s): -// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) +// \sdram_|Mux19~6_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & (\sdram_|Mux19~4_combout & \sdram_|r.state [4]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux19~6_combout ), .cout()); @@ -65113,25 +68923,42 @@ defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N14 +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h6250; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 cycloneive_lcell_comb \sdram_|Mux19~7 ( // Equation(s): -// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~6_combout & (\sdram_|r.address[5]~_Duplicate_1_q & (\sdram_|Mux19~5_combout ))) # (!\sdram_|Mux19~6_combout & ((\sdram_|Mux19~5_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # +// (!\sdram_|Mux19~5_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) - .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .dataa(\sdram_|Mux19~6_combout ), .datab(\sdram_|r.address[5]~_Duplicate_1_q ), .datac(\sdram_|Mux19~5_combout ), - .datad(\sdram_|Mux19~6_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .lut_mask = 16'hD484; defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N31 +// Location: FF_X20_Y14_N11 dffeas \sdram_|r.address[5]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[5]~3_combout ), @@ -65150,72 +68977,89 @@ defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N20 +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~4_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[5]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h30AA; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 cycloneive_lcell_comb \sdram_|Mux19~2 ( // Equation(s): -// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) +// \sdram_|Mux19~2_combout = (!\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) - .dataa(\sdram_|Mux19~1_combout ), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .lut_mask = 16'h2232; defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N6 +// Location: LCCOMB_X20_Y14_N16 cycloneive_lcell_comb \sdram_|Mux19~3 ( // Equation(s): -// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q )))) +// \sdram_|Mux19~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|Mux19~2_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # (!\sdram_|Mux19~2_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|Equal7~2_combout & +// (\sdram_|r.address[5]~_Duplicate_1_q )) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [4]), - .datac(\z80_|address_pins_|abus[4]~28_combout ), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~2_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .lut_mask = 16'hEC4C; defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N30 +// Location: LCCOMB_X20_Y14_N10 cycloneive_lcell_comb \sdram_|r.address[5]~3 ( // Equation(s): -// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux19~2_combout ), + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|r.state [8]), .datac(gnd), .datad(\sdram_|Mux19~3_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N26 +// Location: LCCOMB_X20_Y14_N6 cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) .dataa(\sdram_|r.address[5]~3_combout ), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux19~7_combout ), - .datad(gnd), + .datac(gnd), + .datad(\sdram_|Mux19~7_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65238,15 +69082,15 @@ defparam \sdram_|r.address[5] .is_wysiwyg = "true"; defparam \sdram_|r.address[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N6 +// Location: LCCOMB_X24_Y8_N20 cycloneive_lcell_comb \sdram_|Mux18~0 ( // Equation(s): -// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux18~0_combout ), .cout()); @@ -65264,7 +69108,7 @@ dffeas \sdram_|r.address[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [6]), @@ -65274,33 +69118,33 @@ defparam \sdram_|r.address[6] .is_wysiwyg = "true"; defparam \sdram_|r.address[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Location: LCCOMB_X24_Y8_N24 +cycloneive_lcell_comb \sdram_|Mux17~2 ( // Equation(s): -// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux17~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux17~0_combout ), + .combout(\sdram_|Mux17~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux17~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X14_Y0_N4 dffeas \sdram_|r.address[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux17~0_combout ), + .d(\sdram_|Mux17~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [7]), @@ -65310,33 +69154,33 @@ defparam \sdram_|r.address[7] .is_wysiwyg = "true"; defparam \sdram_|r.address[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Location: LCCOMB_X24_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux16~2 ( // Equation(s): -// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux16~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux16~0_combout ), + .combout(\sdram_|Mux16~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux16~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X0_Y5_N25 dffeas \sdram_|r.address[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux16~0_combout ), + .d(\sdram_|Mux16~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [8]), @@ -65346,20 +69190,20 @@ defparam \sdram_|r.address[8] .is_wysiwyg = "true"; defparam \sdram_|r.address[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N30 +// Location: LCCOMB_X24_Y8_N8 cycloneive_lcell_comb \sdram_|Mux15~2 ( // Equation(s): -// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\sdram_|r.address[3]~8_combout ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [8]), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux15~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .lut_mask = 16'hF500; defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -65372,7 +69216,7 @@ dffeas \sdram_|r.address[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [9]), @@ -65382,61 +69226,78 @@ defparam \sdram_|r.address[9] .is_wysiwyg = "true"; defparam \sdram_|r.address[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \sdram_|r.address[10]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) +// \sdram_|r.address[10]~_Duplicate_1feeder_combout = \sdram_|r.address[10]~4_combout - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; -defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N28 -cycloneive_lcell_comb \sdram_|Mux14~1 ( -// Equation(s): -// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; -defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N10 -cycloneive_lcell_comb \sdram_|r.address[10]~4 ( -// Equation(s): -// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) - - .dataa(\sdram_|Mux14~0_combout ), - .datab(\sdram_|r.state [8]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\sdram_|Mux14~1_combout ), + .datad(\sdram_|r.address[10]~4_combout ), .cin(gnd), - .combout(\sdram_|r.address[10]~4_combout ), + .combout(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; -defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N11 +// Location: LCCOMB_X20_Y16_N2 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q ) # (\sdram_|r.address[10]~_Duplicate_1_q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.address[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h5F5C; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & !\sdram_|process_0~2_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h00AE; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((!\sdram_|process_0~4_combout & (\sdram_|r.address[10]~_Duplicate_1_q & \sdram_|Mux23~0_combout ))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux14~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y16_N25 dffeas \sdram_|r.address[10]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[10]~4_combout ), + .d(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .asdata(\sdram_|Mux14~3_combout ), .clrn(vcc), .aload(gnd), @@ -65452,71 +69313,71 @@ defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N16 -cycloneive_lcell_comb \sdram_|n~4 ( +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \sdram_|Mux14~1 ( // Equation(s): -// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~4_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - .dataa(\sdram_|Equal7~2_combout ), + .dataa(\sdram_|Equal2~3_combout ), .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|n~4_combout ), + .combout(\sdram_|Mux14~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~4 .lut_mask = 16'h5F5C; -defparam \sdram_|n~4 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N30 -cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \sdram_|Mux14~0 ( // Equation(s): -// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~2_combout )))) - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|Mux14~2_combout ), + .combout(\sdram_|Mux14~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; -defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~0 .lut_mask = 16'hEEAE; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N8 -cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( // Equation(s): -// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) - - .dataa(\sdram_|Mux14~2_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N26 -cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( -// Equation(s): -// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux14~0_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux14~1_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux14~1_combout ), + .datad(\sdram_|Mux14~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hFC30; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux14~3_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[10]~4_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[10]~4_combout ), .datac(\sdram_|Mux14~3_combout ), - .datad(\sdram_|r.address[10]~4_combout ), + .datad(gnd), .cin(gnd), .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hE4E4; defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65539,61 +69400,61 @@ defparam \sdram_|r.address[10] .is_wysiwyg = "true"; defparam \sdram_|r.address[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N28 -cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~21 ( // Equation(s): -// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) +// \sdram_|r.address[11]~21_combout = (!\sdram_|r.rd_pending~q & (((\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.wr_pending~q ))) - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.rd_pending~q ), .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.address[11]~18_combout ), + .combout(\sdram_|r.address[11]~21_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; -defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[11]~21 .lut_mask = 16'h080F; +defparam \sdram_|r.address[11]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N26 +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \sdram_|r.address[11]~22 ( +// Equation(s): +// \sdram_|r.address[11]~22_combout = (\sdram_|r.address[11]~21_combout & ((\sdram_|r.state [8]) # (\sdram_|r.state [4]))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[11]~21_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~22 .lut_mask = 16'hFC00; +defparam \sdram_|r.address[11]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 cycloneive_lcell_comb \sdram_|r.address[11]~5 ( // Equation(s): -// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.address[11]~22_combout ) # ((\sdram_|r.state [8] & !\sdram_|Equal7~2_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux24~2_combout ), + .dataa(\sdram_|r.address[11]~22_combout ), + .datab(\sdram_|r.state [8]), .datac(\sdram_|r.address[11]~_Duplicate_2_q ), - .datad(\sdram_|r.address[11]~18_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .lut_mask = 16'hA0E0; defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( -// Equation(s): -// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout - - .dataa(\sdram_|r.address[11]~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; -defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y11_N5 +// Location: FF_X20_Y14_N9 dffeas \sdram_|r.address[11]~_Duplicate_2 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .d(\sdram_|r.address[11]~5_combout ), .asdata(\sdram_|Mux13~6_combout ), .clrn(vcc), .aload(gnd), @@ -65609,54 +69470,54 @@ defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N8 +// Location: LCCOMB_X20_Y14_N14 cycloneive_lcell_comb \sdram_|Mux13~10 ( // Equation(s): // \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) - .dataa(gnd), - .datab(\sdram_|r.address[11]~_Duplicate_2_q ), - .datac(\sdram_|r.state [6]), + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux13~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .lut_mask = 16'hF050; defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N22 +// Location: LCCOMB_X20_Y14_N0 cycloneive_lcell_comb \sdram_|Mux13~6 ( // Equation(s): -// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|Equal7~2_combout & !\sdram_|r.state [6])) # (!\sdram_|process_0~4_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|Mux13~10_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux13~10_combout ), .cin(gnd), .combout(\sdram_|Mux13~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .lut_mask = 16'h3700; defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N12 +// Location: LCCOMB_X20_Y14_N4 cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65679,20 +69540,20 @@ defparam \sdram_|r.address[11] .is_wysiwyg = "true"; defparam \sdram_|r.address[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N6 +// Location: LCCOMB_X20_Y14_N2 cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65725,6 +69586,16 @@ defparam \SW[0]~input .bus_hold = "false"; defparam \SW[0]~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X25_Y34_N8 +cycloneive_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + // Location: IOIBUF_X53_Y17_N15 cycloneive_io_ibuf \SW[3]~input ( .i(SW[3]), diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index 518d14d..b384d86 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/02/2022 14:51:20" +// DATE "04/06/2022 13:58:27" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -60,14 +60,18 @@ module spectrum ( DRAM_WE_N, DRAM_CS_N, DRAM_DQ, - DRAM_ADDR); + DRAM_ADDR, + kempston, + kempston_gnd, + turbo_button, + kempston_autofire_button); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -80,7 +84,7 @@ output [3:0] VGA_B; output VGA_HS; output VGA_VS; input [3:0] SW; -output [33:0] GPIO_1; +output [31:0] GPIO_1; output buzzer_out; input raw_loader_in; output [1:0] DRAM_BA; @@ -91,8 +95,12 @@ output DRAM_CKE; output DRAM_CLK; output DRAM_WE_N; output DRAM_CS_N; -inout [15:0] DRAM_DQ; +output [15:0] DRAM_DQ; output [12:0] DRAM_ADDR; +input [4:0] kempston; +output kempston_gnd; +input turbo_button; +input kempston_autofire_button; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -123,6 +131,7 @@ output [12:0] DRAM_ADDR; // VGA_HS => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // VGA_VS => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[0] => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[3] => Location: PIN_M15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // GPIO_1[0] => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[1] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -156,8 +165,6 @@ output [12:0] DRAM_ADDR; // GPIO_1[29] => Location: PIN_L13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[30] => Location: PIN_J16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[31] => Location: PIN_K15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -182,6 +189,7 @@ output [12:0] DRAM_ADDR; // DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// kempston_gnd => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -201,10 +209,16 @@ output [12:0] DRAM_ADDR; // DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[0] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[1] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[2] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[3] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[4] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// turbo_button => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston_autofire_button => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -227,6 +241,7 @@ initial $sdf_annotate("spectrum_6_1200mv_0c_v_slow.sdo"); // synopsys translate_on wire \SW[0]~input_o ; +wire \SW[2]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; wire \DRAM_DQ[0]~input_o ; @@ -248,13 +263,69 @@ wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \turbo_button~input_o ; +wire \CLOCK_50~inputclkctrl_outclk ; +wire \debounce_turbo|r_Count[0]~21_combout ; +wire \debounce_turbo|r_Count[0]~22 ; +wire \debounce_turbo|r_Count[1]~23_combout ; +wire \debounce_turbo|r_Count[1]~24 ; +wire \debounce_turbo|r_Count[2]~25_combout ; +wire \debounce_turbo|r_Count[2]~26 ; +wire \debounce_turbo|r_Count[3]~27_combout ; +wire \debounce_turbo|r_Count[3]~28 ; +wire \debounce_turbo|r_Count[4]~29_combout ; +wire \debounce_turbo|r_Count[4]~30 ; +wire \debounce_turbo|r_Count[5]~31_combout ; +wire \debounce_turbo|r_Count[5]~32 ; +wire \debounce_turbo|r_Count[6]~33_combout ; +wire \debounce_turbo|r_Count[6]~34 ; +wire \debounce_turbo|r_Count[7]~35_combout ; +wire \debounce_turbo|r_Count[7]~36 ; +wire \debounce_turbo|r_Count[8]~37_combout ; +wire \debounce_turbo|r_Count[8]~38 ; +wire \debounce_turbo|r_Count[9]~39_combout ; +wire \debounce_turbo|r_Count[9]~40 ; +wire \debounce_turbo|r_Count[10]~41_combout ; +wire \debounce_turbo|r_Count[10]~42 ; +wire \debounce_turbo|r_Count[11]~43_combout ; +wire \debounce_turbo|r_Count[11]~44 ; +wire \debounce_turbo|r_Count[12]~45_combout ; +wire \debounce_turbo|r_Count[12]~46 ; +wire \debounce_turbo|r_Count[13]~47_combout ; +wire \debounce_turbo|r_State~7_combout ; +wire \debounce_turbo|LessThan0~0_combout ; +wire \debounce_turbo|LessThan0~1_combout ; +wire \debounce_turbo|r_Count[13]~48 ; +wire \debounce_turbo|r_Count[14]~49_combout ; +wire \debounce_turbo|r_Count[14]~50 ; +wire \debounce_turbo|r_Count[15]~51_combout ; +wire \debounce_turbo|r_Count[15]~52 ; +wire \debounce_turbo|r_Count[16]~53_combout ; +wire \debounce_turbo|r_Count[16]~54 ; +wire \debounce_turbo|r_Count[17]~55_combout ; +wire \debounce_turbo|r_Count[17]~56 ; +wire \debounce_turbo|r_Count[18]~57_combout ; +wire \debounce_turbo|r_Count[18]~58 ; +wire \debounce_turbo|r_Count[19]~59_combout ; +wire \debounce_turbo|always0~0_combout ; +wire \debounce_turbo|always0~1_combout ; +wire \debounce_turbo|r_Count[19]~60 ; +wire \debounce_turbo|r_Count[20]~61_combout ; +wire \debounce_turbo|always0~2_combout ; +wire \debounce_turbo|r_State~4_combout ; +wire \debounce_turbo|r_State~2_combout ; +wire \debounce_turbo|r_State~0_combout ; +wire \debounce_turbo|r_State~1_combout ; +wire \debounce_turbo|r_State~3_combout ; +wire \debounce_turbo|r_State~5_combout ; +wire \debounce_turbo|r_State~6_combout ; +wire \debounce_turbo|r_State~q ; +wire \turbo~0_combout ; +wire \turbo~q ; wire \ula_|clocks_|counter[0]~0_combout ; -wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -263,12 +334,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; @@ -279,16 +351,9 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Add0~9 ; -wire \ula_|video_|Add0~10_combout ; -wire \ula_|video_|vga_hc~0_combout ; -wire \ula_|video_|Add0~11 ; -wire \ula_|video_|Add0~12_combout ; -wire \ula_|video_|Add0~13 ; -wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Equal0~1_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; @@ -297,6 +362,30 @@ wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~9 ; +wire \ula_|video_|Add0~10_combout ; +wire \ula_|video_|vga_hc~0_combout ; +wire \ula_|video_|Add0~11 ; +wire \ula_|video_|Add0~12_combout ; +wire \ula_|video_|Add0~13 ; +wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Add1~11 ; +wire \ula_|video_|Add1~12_combout ; +wire \ula_|video_|vga_vc[6]~4_combout ; +wire \ula_|video_|Add1~13 ; +wire \ula_|video_|Add1~14_combout ; +wire \ula_|video_|vga_vc[7]~6_combout ; +wire \ula_|video_|Add1~15 ; +wire \ula_|video_|Add1~16_combout ; +wire \ula_|video_|vga_vc[8]~7_combout ; +wire \ula_|video_|Add1~17 ; +wire \ula_|video_|Add1~18_combout ; +wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; +wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; @@ -312,163 +401,1526 @@ wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; wire \ula_|video_|Add1~10_combout ; wire \ula_|video_|vga_vc[5]~8_combout ; -wire \ula_|video_|Add1~11 ; -wire \ula_|video_|Add1~12_combout ; -wire \ula_|video_|vga_vc[6]~4_combout ; -wire \ula_|video_|Add1~13 ; -wire \ula_|video_|Add1~14_combout ; -wire \ula_|video_|vga_vc[7]~6_combout ; -wire \ula_|video_|Add1~15 ; -wire \ula_|video_|Add1~16_combout ; -wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Add1~17 ; -wire \ula_|video_|Add1~18_combout ; -wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal3~0_combout ; -wire \ula_|video_|Equal2~0_combout ; -wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|ir_|opcode[4]~feeder_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|pla_decode_|Equal1~0_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal1~1_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; wire \z80_|pla_decode_|Equal21~0_combout ; wire \z80_|execute_|ctl_mRead~3_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_sw_1d~2_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_sw_1d~3_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~3_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~2_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_mWrite~19_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_bus_db_oe~8_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; wire \z80_|pla_decode_|Equal9~0_combout ; wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_ir_we~16_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|ctl_inc_cy~97_combout ; -wire \z80_|execute_|ctl_inc_cy~96_combout ; -wire \z80_|execute_|ctl_inc_cy~98_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~17_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|pla_decode_|Equal6~2_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~3_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~16_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_inc_cy~28_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~13_combout ; +wire \z80_|execute_|ctl_ir_we~19_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_inc_cy~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_out_hi~3_combout ; +wire \z80_|execute_|ctl_sw_2u~9_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|pla_decode_|Equal13~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_sw_2u~8_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|ctl_sw_4d~9_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|pla_decode_|Equal1~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_reg_out_hi~2_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~15_combout ; +wire \z80_|execute_|ctl_flags_pf_we~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~1_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_oe~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~50_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~49_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~51_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~48_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~17_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~22_combout ; +wire \z80_|pla_decode_|Equal5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~7_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|ctl_al_we~3_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~2_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~9_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_low[3]~2_combout ; +wire \z80_|alu_|db_low[3]~3_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~24_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~25_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~14_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~22_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~21_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~19_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~8_combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~17_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~18_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~23_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|reg_file_|db_hi_as[0]~3_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|pla_decode_|Equal1~3_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|pla_decode_|Equal2~4_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~29_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~26_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~32_combout ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~30_combout ; +wire \z80_|execute_|ctl_inc_cy~31_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|Q[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~33_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~13_combout ; +wire \z80_|reg_file_|db_lo_as[3]~14_combout ; +wire \z80_|reg_file_|db_lo_as[3]~15_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~58_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~59_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~61_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~62_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~63_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~65_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~70_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~72_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~73_combout ; +wire \z80_|reg_file_|db_lo_as[4]~16_combout ; +wire \z80_|reg_file_|db_lo_as[4]~17_combout ; +wire \z80_|reg_file_|db_lo_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~49_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; +wire \z80_|pla_decode_|Equal72~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|execute_|ctl_mWrite~20_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[0]~4_combout ; +wire \z80_|alu_control_|db[0]~23_combout ; +wire \z80_|alu_control_|db[0]~24_combout ; +wire \z80_|alu_control_|db[0]~25_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ; +wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~83_combout ; +wire \z80_|reg_file_|db_hi_as[7]~23_combout ; +wire \z80_|reg_file_|db_hi_as[7]~24_combout ; +wire \z80_|reg_file_|db_hi_as[7]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~84_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~19_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|db_hi_as[5]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~7_combout ; +wire \z80_|alu_|db_low[2]~8_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~13_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~8_combout ; +wire \z80_|reg_file_|db_lo_ds[5]~0_combout ; +wire \z80_|alu_control_|db[5]~9_combout ; +wire \z80_|alu_control_|db[5]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~48_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~53_combout ; +wire \z80_|reg_file_|db_lo_as[5]~10_combout ; +wire \z80_|reg_file_|db_lo_as[5]~11_combout ; +wire \z80_|reg_file_|db_lo_as[5]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~7_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|alu_|db_low[3]~0_combout ; +wire \z80_|alu_|db_low[3]~1_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_control_|db[2]~26_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~5_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~q ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; +wire \z80_|alu_control_|flags_cond_true~0_combout ; +wire \z80_|alu_control_|flags_cond_true~q ; +wire \z80_|execute_|ctl_reg_sel_wz~28_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~23_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~21_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~13_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|alu_control_|db[7]~14_combout ; +wire \z80_|alu_control_|db[7]~15_combout ; +wire \z80_|bus_control_|db[7]~4_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|nextM~16_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|ctl_ir_we~20_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~38_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; @@ -478,1535 +1930,104 @@ wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|execute_|ctl_mWrite~18_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_flags_alu~21_combout ; -wire \z80_|execute_|ctl_flags_alu~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_alu~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ixy_d~15_combout ; wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; wire \z80_|memory_ifc_|mwr_wr~q ; wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|execute_|ctl_mRead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pla_decode_|Equal40~2_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|pc_inc_hold~14_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_inc_cy~99_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|pla_decode_|Equal76~2_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~11_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|pla_decode_|Equal10~1_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|reg_control_|reg_sel_de2~2_combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_core_hf~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~23_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; -wire \z80_|reg_control_|reg_sel_de2~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; -wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|sw1_|db_down[3]~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~17_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~15_combout ; -wire \z80_|execute_|pc_inc_hold~16_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|execute_|ctl_inc_cy~95_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~100_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~10_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_alu_op_low~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[7]~16_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; -wire \z80_|alu_control_|db[6]~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_control_|db[7]~19_combout ; -wire \z80_|alu_control_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; -wire \z80_|reg_file_|db_hi_as[2]~10_combout ; -wire \z80_|reg_file_|db_hi_as[2]~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; -wire \z80_|reg_file_|db_hi_as[4]~13_combout ; -wire \z80_|reg_file_|db_hi_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[1]~18_combout ; -wire \z80_|alu_|db_low[1]~19_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|db_low[1]~20_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~8_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; -wire \z80_|reg_file_|db_hi_as[6]~19_combout ; -wire \z80_|reg_file_|db_hi_as[6]~20_combout ; -wire \z80_|reg_file_|db_hi_as[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~14_combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; -wire \z80_|reg_file_|db_hi_as[5]~22_combout ; -wire \z80_|reg_file_|db_hi_as[5]~23_combout ; -wire \z80_|reg_file_|db_hi_as[5]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|alu_op1[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|db_low[0]~24_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db_low[0]~25_combout ; -wire \z80_|alu_|db_low[0]~27_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~13_combout ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|alu_|db_high[0]~20_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_low[2]~11_combout ; -wire \z80_|alu_|db_low[2]~12_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~13_combout ; -wire \z80_|alu_|db_low[2]~14_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~24_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_control_|db[2]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~11_combout ; -wire \z80_|alu_control_|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_control_|db[3]~36_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|db_low[3]~5_combout ; -wire \z80_|alu_|db_low[3]~6_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~26_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; -wire \z80_|alu_|alu_op2[3]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_control_|db[4]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; -wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; -wire \z80_|alu_control_|flags_cond_true~0_combout ; -wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~7_combout ; -wire \z80_|reg_file_|db_hi_as[3]~8_combout ; -wire \z80_|reg_file_|db_hi_as[3]~9_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \D[0]~49_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \Equal5~0_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~20_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~43_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; +wire \Equal3~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; +wire \z80_|address_pins_|abus[6]~25_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; +wire \z80_|address_pins_|abus[7]~26_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; +wire \Equal3~1_combout ; +wire \Equal3~2_combout ; +wire \D[5]~26_combout ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|abus[15]~23_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~22_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~44_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~45_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \D[2]~42_combout ; -wire \D[2]~46_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|control_pins_|pin_nIORQ~1_combout ; -wire \Equal2~0_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; wire \ExtRamWE~0_combout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; -wire \z80_|address_pins_|abus[1]~25_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; -wire \z80_|address_pins_|abus[2]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; -wire \z80_|address_pins_|abus[3]~27_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; -wire \z80_|address_pins_|abus[4]~28_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; -wire \z80_|address_pins_|abus[5]~29_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; -wire \z80_|address_pins_|abus[6]~30_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; -wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \D[2]~50_combout ; -wire \D[2]~51_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \CLOCK_50~inputclkctrl_outclk ; +wire \z80_|address_pins_|abus[0]~24_combout ; +wire \z80_|address_pins_|abus[1]~27_combout ; +wire \z80_|address_pins_|abus[2]~28_combout ; +wire \z80_|address_pins_|abus[3]~29_combout ; +wire \z80_|address_pins_|abus[4]~30_combout ; +wire \z80_|address_pins_|abus[5]~31_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~16_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; -wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -2018,521 +2039,710 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[8]~1_combout ; +wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Selector0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \Selector0~1_combout ; +wire \D[7]~36_combout ; +wire \D[7]~37_combout ; +wire \D[7]~48_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[7]~6_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|setM1~59_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal5~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~47_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~48_combout ; -wire \D[2]~49_combout ; -wire \D[2]~119_combout ; -wire \D[2]~52_combout ; -wire \D[2]~53_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; +wire \Selector10~0_combout ; +wire \Selector10~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|keys[3][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~5_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~46_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~4_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~7_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~6_combout ; +wire \Selector14~17_combout ; +wire \Selector14~18_combout ; +wire \kempston[1]~input_o ; +wire \Selector10~2_combout ; +wire \Selector10~3_combout ; +wire \D[2]~13_combout ; wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|ir_|opcode[2]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|sw1_|db_down[6]~1_combout ; -wire \z80_|alu_control_|db[6]~23_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|bus_control_|db[2]~14_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_ir_we~17_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal2~3_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_66_oe~4_combout ; +wire \z80_|alu_control_|db[6]~16_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~2_combout ; +wire \z80_|alu_control_|db[6]~17_combout ; +wire \z80_|alu_control_|db[6]~18_combout ; +wire \z80_|bus_control_|db[6]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \raw_loader_in~input_o ; +wire \D[6]~28_combout ; +wire \D[6]~43_combout ; +wire \D[6]~44_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~103_combout ; -wire \D[6]~104_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~42_combout ; +wire \D[6]~45_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~100_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~101_combout ; -wire \D[6]~102_combout ; -wire \D[6]~127_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~99_combout ; -wire \D[6]~114_combout ; -wire \D[6]~115_combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Mux1~0_combout ; +wire \D[6]~41_combout ; +wire \D[6]~46_combout ; +wire \D[6]~47_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~18_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~16_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~9_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~10_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~130_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~11_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~72_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~69_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~8_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~9_combout ; +wire \kempston[3]~input_o ; +wire \Selector14~8_combout ; +wire \Selector14~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector14~19_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \Selector14~10_combout ; +wire \Selector14~11_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector14~20_combout ; +wire \Selector14~9_combout ; +wire \Selector14~12_combout ; +wire \Selector14~14_combout ; +wire \D[0]~14_combout ; +wire \z80_|bus_control_|db[0]~11_combout ; +wire \z80_|bus_control_|db[0]~12_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~29_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~16_combout ; +wire \debounce_autofire|r_Count[0]~21_combout ; +wire \debounce_autofire|r_Count[0]~22 ; +wire \debounce_autofire|r_Count[1]~23_combout ; +wire \debounce_autofire|r_Count[1]~24 ; +wire \debounce_autofire|r_Count[2]~25_combout ; +wire \debounce_autofire|r_Count[2]~26 ; +wire \debounce_autofire|r_Count[3]~27_combout ; +wire \debounce_autofire|r_Count[3]~28 ; +wire \debounce_autofire|r_Count[4]~29_combout ; +wire \debounce_autofire|r_Count[4]~30 ; +wire \debounce_autofire|r_Count[5]~31_combout ; +wire \debounce_autofire|r_Count[5]~32 ; +wire \debounce_autofire|r_Count[6]~33_combout ; +wire \debounce_autofire|r_Count[6]~34 ; +wire \debounce_autofire|r_Count[7]~35_combout ; +wire \debounce_autofire|r_Count[7]~36 ; +wire \debounce_autofire|r_Count[8]~37_combout ; +wire \debounce_autofire|r_Count[8]~38 ; +wire \debounce_autofire|r_Count[9]~39_combout ; +wire \debounce_autofire|r_Count[9]~40 ; +wire \debounce_autofire|r_Count[10]~41_combout ; +wire \debounce_autofire|r_Count[10]~42 ; +wire \debounce_autofire|r_Count[11]~43_combout ; +wire \debounce_autofire|r_Count[11]~44 ; +wire \debounce_autofire|r_Count[12]~45_combout ; +wire \debounce_autofire|r_Count[12]~46 ; +wire \debounce_autofire|r_Count[13]~47_combout ; +wire \debounce_autofire|r_Count[13]~48 ; +wire \debounce_autofire|r_Count[14]~49_combout ; +wire \debounce_autofire|r_Count[14]~50 ; +wire \debounce_autofire|r_Count[15]~51_combout ; +wire \debounce_autofire|r_Count[15]~52 ; +wire \debounce_autofire|r_Count[16]~53_combout ; +wire \debounce_autofire|r_Count[16]~54 ; +wire \debounce_autofire|r_Count[17]~55_combout ; +wire \debounce_autofire|r_Count[17]~56 ; +wire \debounce_autofire|r_Count[18]~57_combout ; +wire \debounce_autofire|r_Count[18]~58 ; +wire \debounce_autofire|r_Count[19]~59_combout ; +wire \debounce_autofire|r_Count[19]~60 ; +wire \debounce_autofire|r_Count[20]~61_combout ; +wire \kempston_autofire_button~input_o ; +wire \debounce_autofire|r_State~7_combout ; +wire \debounce_autofire|LessThan0~0_combout ; +wire \debounce_autofire|LessThan0~1_combout ; +wire \debounce_autofire|always0~0_combout ; +wire \debounce_autofire|always0~1_combout ; +wire \debounce_autofire|always0~2_combout ; +wire \debounce_autofire|r_State~4_combout ; +wire \debounce_autofire|r_State~5_combout ; +wire \debounce_autofire|r_State~2_combout ; +wire \debounce_autofire|r_State~0_combout ; +wire \debounce_autofire|r_State~1_combout ; +wire \debounce_autofire|r_State~3_combout ; +wire \debounce_autofire|r_State~6_combout ; +wire \debounce_autofire|r_State~q ; +wire \kempston_autofire_enabled~0_combout ; +wire \kempston_autofire_enabled~q ; +wire \kempston_auto_fire_counter[0]~51_combout ; +wire \kempston_auto_fire_counter[1]~17_combout ; +wire \kempston_auto_fire_counter[1]~18 ; +wire \kempston_auto_fire_counter[2]~19_combout ; +wire \kempston_auto_fire_counter[2]~20 ; +wire \kempston_auto_fire_counter[3]~21_combout ; +wire \kempston_auto_fire_counter[3]~22 ; +wire \kempston_auto_fire_counter[4]~23_combout ; +wire \kempston_auto_fire_counter[4]~24 ; +wire \kempston_auto_fire_counter[5]~25_combout ; +wire \kempston_auto_fire_counter[5]~26 ; +wire \kempston_auto_fire_counter[6]~27_combout ; +wire \kempston_auto_fire_counter[6]~28 ; +wire \kempston_auto_fire_counter[7]~29_combout ; +wire \kempston_auto_fire_counter[7]~30 ; +wire \kempston_auto_fire_counter[8]~31_combout ; +wire \kempston_auto_fire_counter[8]~32 ; +wire \kempston_auto_fire_counter[9]~33_combout ; +wire \kempston_auto_fire_counter[9]~34 ; +wire \kempston_auto_fire_counter[10]~35_combout ; +wire \kempston_auto_fire_counter[10]~36 ; +wire \kempston_auto_fire_counter[11]~37_combout ; +wire \kempston_auto_fire_counter[11]~38 ; +wire \kempston_auto_fire_counter[12]~39_combout ; +wire \kempston_auto_fire_counter[12]~40 ; +wire \kempston_auto_fire_counter[13]~41_combout ; +wire \kempston_auto_fire_counter[13]~42 ; +wire \kempston_auto_fire_counter[14]~43_combout ; +wire \kempston_auto_fire_counter[14]~44 ; +wire \kempston_auto_fire_counter[15]~45_combout ; +wire \Equal2~3_combout ; +wire \Equal2~2_combout ; +wire \Equal2~0_combout ; +wire \Equal2~1_combout ; +wire \Equal2~4_combout ; +wire \kempston_auto_fire_counter[15]~46 ; +wire \kempston_auto_fire_counter[16]~47_combout ; +wire \kempston_auto_fire_counter[16]~48 ; +wire \kempston_auto_fire_counter[17]~49_combout ; +wire \kempston_auto_fire~0_combout ; +wire \kempston_auto_fire~q ; +wire \Selector6~2_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~17_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~133_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \Selector6~3_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \Selector6~4_combout ; +wire \Selector6~5_combout ; +wire \kempston[4]~input_o ; +wire \Selector6~6_combout ; +wire \Selector6~7_combout ; +wire \D[4]~39_combout ; +wire \z80_|bus_control_|db[4]~17_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~3_combout ; +wire \z80_|alu_control_|db[1]~20_combout ; +wire \z80_|alu_control_|db[1]~21_combout ; +wire \z80_|alu_control_|db[1]~22_combout ; +wire \z80_|bus_control_|db[1]~9_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~2_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~1_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~38_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~3_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~0_combout ; +wire \kempston[2]~input_o ; +wire \Selector12~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \Selector12~7_combout ; +wire \Selector12~8_combout ; +wire \Selector12~9_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector12~15_combout ; +wire \Selector12~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~14_combout ; +wire \Selector12~6_combout ; +wire \Selector12~11_combout ; +wire \D[1]~12_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|test1~4_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~36_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; -wire \ula_|zx_keyboard_|WideOr16~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~74_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \D[3]~73_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~2_combout ; +wire \z80_|bus_control_|db[0]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector8~5_combout ; +wire \Selector8~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \Selector8~7_combout ; +wire \Selector8~8_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|key_row[3]~15_combout ; wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; wire \ula_|zx_keyboard_|keys[0][3]~q ; wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \D[3]~72_combout ; -wire \D[3]~76_combout ; -wire \D[3]~122_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~79_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~77_combout ; -wire \D[3]~80_combout ; -wire \D[3]~81_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~124_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~123_combout ; -wire \D[3]~78_combout ; -wire \D[3]~82_combout ; -wire \D[3]~108_combout ; -wire \D[3]~109_combout ; +wire \ula_|zx_keyboard_|key_row[3]~12_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~13_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~14_combout ; +wire \kempston[0]~input_o ; +wire \Selector8~4_combout ; +wire \Selector8~9_combout ; +wire \D[3]~38_combout ; +wire \z80_|bus_control_|db[3]~19_combout ; wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; -wire \D[5]~97_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~116_combout ; -wire \D[7]~117_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|ir_|opcode[3]~feeder_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~60_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~17_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|interrupts_|im1~feeder_combout ; wire \z80_|interrupts_|im1~q ; wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~57_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \D[0]~56_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~69_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~71_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~54_combout ; -wire \D[0]~55_combout ; -wire \D[0]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \D[0]~62_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~63_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~59_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~60_combout ; -wire \D[0]~61_combout ; -wire \D[0]~120_combout ; -wire \D[0]~64_combout ; -wire \D[0]~65_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|sw1_|db_down[1]~2_combout ; -wire \z80_|alu_control_|db[1]~27_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|WideOr16~0_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~34_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \D[1]~38_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \D[1]~39_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \D[1]~35_combout ; -wire \D[1]~36_combout ; -wire \D[1]~37_combout ; -wire \D[1]~118_combout ; -wire \D[1]~40_combout ; -wire \D[1]~41_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~88_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~87_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~85_combout ; -wire \D[4]~86_combout ; -wire \D[4]~89_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \D[4]~93_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \D[4]~94_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \D[4]~90_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \D[4]~91_combout ; -wire \D[4]~92_combout ; -wire \D[4]~125_combout ; -wire \D[4]~110_combout ; -wire \D[4]~111_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \z80_|alu_control_|db[5]~16_combout ; -wire \z80_|alu_control_|db[5]~17_combout ; +wire \z80_|bus_control_|db[0]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; -wire \D[5]~112_combout ; -wire \D[5]~113_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[5]~25_combout ; +wire \D[5]~27_combout ; +wire \D[5]~40_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|ena_M~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; +wire \z80_|bus_control_|db[5]~16_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~51_combout ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~47_combout ; wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~55_combout ; wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~66_combout ; -wire \D[0]~67_combout ; -wire \D[0]~121_combout ; -wire \D[1]~68_combout ; -wire \D[1]~69_combout ; -wire \D[2]~70_combout ; -wire \D[2]~71_combout ; -wire \D[3]~83_combout ; -wire \D[3]~84_combout ; -wire \D[4]~95_combout ; -wire \D[4]~96_combout ; -wire \D[5]~126_combout ; -wire \D[5]~98_combout ; -wire \D[6]~105_combout ; -wire \D[6]~106_combout ; -wire \D[7]~128_combout ; -wire \D[7]~107_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ; +wire \Selector14~15_combout ; +wire \Selector14~16_combout ; +wire \D[0]~15_combout ; +wire \D[0]~16_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ; +wire \Selector12~12_combout ; +wire \Selector12~13_combout ; +wire \D[1]~17_combout ; +wire \D[1]~18_combout ; +wire \D[2]~19_combout ; +wire \D[2]~20_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \Selector8~2_combout ; +wire \Selector8~3_combout ; +wire \D[3]~21_combout ; +wire \D[3]~22_combout ; +wire \D[4]~23_combout ; +wire \D[4]~24_combout ; +wire \D[6]~32_combout ; +wire \D[6]~33_combout ; +wire \D[6]~29_combout ; +wire \D[6]~30_combout ; +wire \D[6]~31_combout ; +wire \D[6]~50_combout ; +wire \D[6]~34_combout ; +wire \D[6]~35_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2541,54 +2751,55 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|Mux42~0_combout ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit~4_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; +wire \I2C_SDAT~input_o ; +wire \ula_|i2c_loader_|nbyte[0]~1_combout ; +wire \ula_|i2c_loader_|nbyte[0]~2_combout ; +wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state~24_combout ; wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state.Data~0_combout ; wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~6_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; -wire \I2C_SDAT~input_o ; -wire \ula_|i2c_loader_|nbyte[0]~1_combout ; -wire \ula_|i2c_loader_|nbyte[0]~2_combout ; -wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; -wire \ula_|i2c_loader_|nbyte[1]~5_combout ; +wire \ula_|i2c_loader_|nbyte[0]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; wire \ula_|i2c_loader_|thisbyte[1]~10_combout ; @@ -2596,9 +2807,9 @@ wire \ula_|i2c_loader_|thisbyte[1]~11 ; wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; -wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; +wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|state.Pause~4_combout ; @@ -2611,31 +2822,30 @@ wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~27_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~28_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg~6_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~27_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; -wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; +wire \ula_|i2c_loader_|shiftreg~25_combout ; +wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; +wire \ula_|i2c_loader_|shiftreg[7]~7_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; wire \ula_|i2c_loader_|sda_out~2_combout ; @@ -2644,16 +2854,38 @@ wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \sdram_|Mux38~0_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux38~3_combout ; +wire \sdram_|Mux38~2_combout ; wire \sdram_|r.rd_pending~q ; +wire \sdram_|n~3_combout ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux13~8_combout ; wire \sdram_|r.rf_counter[0]~12_combout ; -wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[8]~32_combout ; wire \sdram_|r.rf_counter[0]~13 ; wire \sdram_|r.rf_counter[1]~14_combout ; wire \sdram_|r.rf_counter[1]~15 ; wire \sdram_|r.rf_counter[2]~16_combout ; wire \sdram_|r.rf_counter[2]~17 ; wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[3]~19 ; wire \sdram_|r.rf_counter[4]~20_combout ; wire \sdram_|r.rf_counter[4]~21 ; @@ -2662,105 +2894,84 @@ wire \sdram_|r.rf_counter[5]~23 ; wire \sdram_|r.rf_counter[6]~24_combout ; wire \sdram_|r.rf_counter[6]~25 ; wire \sdram_|r.rf_counter[7]~26_combout ; -wire \sdram_|Equal0~1_combout ; wire \sdram_|r.rf_counter[7]~27 ; wire \sdram_|r.rf_counter[8]~28_combout ; -wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[8]~29 ; wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~1_combout ; wire \sdram_|Equal0~2_combout ; -wire \sdram_|Mux13~8_combout ; wire \sdram_|Mux37~0_combout ; wire \sdram_|r.rf_pending~q ; -wire \sdram_|Mux4~0_combout ; wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~4_combout ; wire \sdram_|Mux4~2_combout ; -wire \sdram_|Mux4~3_combout ; -wire \sdram_|r.act_row[1]~0_combout ; -wire \sdram_|process_0~2_combout ; -wire \sdram_|r.act_row[1]~1_combout ; -wire \sdram_|r.act_row[2]~feeder_combout ; -wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux4~5_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|r.act_row[2]~0_combout ; +wire \sdram_|r.act_row[2]~1_combout ; wire \sdram_|Equal7~0_combout ; wire \sdram_|Equal7~2_combout ; -wire \sdram_|Mux39~0_combout ; -wire \sdram_|Mux39~1_combout ; -wire \sdram_|Mux39~2_combout ; -wire \sdram_|r.wr_pending~q ; -wire \sdram_|Mux9~8_combout ; -wire \sdram_|Mux9~9_combout ; -wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~2_combout ; wire \sdram_|Mux6~5_combout ; -wire \sdram_|process_0~3_combout ; +wire \sdram_|process_0~2_combout ; wire \sdram_|Mux6~0_combout ; wire \sdram_|Mux6~1_combout ; wire \sdram_|Mux6~6_combout ; -wire \sdram_|r.address[3]~6_combout ; -wire \sdram_|Mux7~2_combout ; -wire \sdram_|n~3_combout ; -wire \sdram_|Mux7~3_combout ; -wire \sdram_|Mux7~4_combout ; -wire \sdram_|Mux7~5_combout ; -wire \sdram_|Mux23~0_combout ; -wire \sdram_|Mux13~7_combout ; -wire \sdram_|Mux10~10_combout ; -wire \sdram_|Mux7~1_combout ; -wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~2_combout ; wire \sdram_|Mux5~10_combout ; wire \sdram_|Mux5~3_combout ; wire \sdram_|Mux5~4_combout ; -wire \sdram_|Mux5~7_combout ; -wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~5_combout ; wire \sdram_|Mux5~6_combout ; wire \sdram_|Mux5~9_combout ; wire \sdram_|n~2_combout ; -wire \sdram_|Mux8~3_combout ; -wire \sdram_|Mux8~4_combout ; -wire \sdram_|Mux9~10_combout ; -wire \sdram_|r.init_counter[0]~0_combout ; -wire \sdram_|Add1~1_cout ; -wire \sdram_|Add1~2_combout ; -wire \sdram_|Add1~3 ; -wire \sdram_|Add1~4_combout ; -wire \sdram_|Add1~5 ; -wire \sdram_|Add1~6_combout ; -wire \sdram_|r.init_counter[3]~1_combout ; -wire \sdram_|Add1~7 ; -wire \sdram_|Add1~8_combout ; -wire \sdram_|Add1~9 ; -wire \sdram_|Add1~10_combout ; -wire \sdram_|Add1~11 ; -wire \sdram_|Add1~12_combout ; -wire \sdram_|Add1~13 ; -wire \sdram_|Add1~14_combout ; -wire \sdram_|Add1~15 ; -wire \sdram_|Add1~16_combout ; -wire \sdram_|Add1~17 ; -wire \sdram_|Add1~18_combout ; -wire \sdram_|Add1~19 ; -wire \sdram_|Add1~20_combout ; -wire \sdram_|Equal2~0_combout ; -wire \sdram_|Equal2~1_combout ; -wire \sdram_|Add1~21 ; -wire \sdram_|Add1~22_combout ; -wire \sdram_|Add1~23 ; -wire \sdram_|Add1~24_combout ; -wire \sdram_|Add1~25 ; -wire \sdram_|Add1~26_combout ; -wire \sdram_|Add1~27 ; -wire \sdram_|Add1~28_combout ; -wire \sdram_|process_0~5_combout ; -wire \sdram_|Equal2~2_combout ; -wire \sdram_|Mux9~11_combout ; -wire \sdram_|Mux9~12_combout ; -wire \sdram_|Mux9~13_combout ; -wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~6_combout ; +wire \sdram_|Mux8~7_combout ; wire \sdram_|Mux8~1_combout ; wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|r.init_counter[0]~44_combout ; +wire \sdram_|r.init_counter[1]~15_cout ; +wire \sdram_|r.init_counter[1]~16_combout ; +wire \sdram_|r.init_counter[1]~17 ; +wire \sdram_|r.init_counter[2]~18_combout ; +wire \sdram_|r.init_counter[2]~19 ; +wire \sdram_|r.init_counter[3]~20_combout ; +wire \sdram_|r.init_counter[3]~21 ; +wire \sdram_|r.init_counter[4]~22_combout ; +wire \sdram_|r.init_counter[4]~23 ; +wire \sdram_|r.init_counter[5]~24_combout ; +wire \sdram_|r.init_counter[5]~25 ; +wire \sdram_|r.init_counter[6]~26_combout ; +wire \sdram_|r.init_counter[6]~27 ; +wire \sdram_|r.init_counter[7]~28_combout ; +wire \sdram_|r.init_counter[7]~29 ; +wire \sdram_|r.init_counter[8]~30_combout ; +wire \sdram_|r.init_counter[8]~31 ; +wire \sdram_|r.init_counter[9]~32_combout ; +wire \sdram_|r.init_counter[9]~33 ; +wire \sdram_|r.init_counter[10]~34_combout ; +wire \sdram_|r.init_counter[10]~35 ; +wire \sdram_|r.init_counter[11]~36_combout ; +wire \sdram_|r.init_counter[11]~37 ; +wire \sdram_|r.init_counter[12]~38_combout ; +wire \sdram_|r.init_counter[12]~39 ; +wire \sdram_|r.init_counter[13]~40_combout ; +wire \sdram_|r.init_counter[13]~41 ; +wire \sdram_|r.init_counter[14]~42_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux8~5_combout ; wire \sdram_|Mux72~0_combout ; wire \sdram_|Mux72~1_combout ; wire \sdram_|Mux84~0_combout ; @@ -2774,13 +2985,14 @@ wire \sdram_|Mux1~1_combout ; wire \sdram_|Mux0~0_combout ; wire \sdram_|Mux0~1_combout ; wire \sdram_|Mux73~0_combout ; -wire \sdram_|Mux73~1_combout ; wire \sdram_|Mux74~0_combout ; wire \sdram_|Mux74~1_combout ; wire \sdram_|Mux75~0_combout ; +wire \LED~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|Add0~1_cout ; wire \ula_|i2s_intf_|Add0~2_combout ; wire \ula_|i2s_intf_|lrdivider~2_combout ; @@ -2811,25 +3023,10 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2843,19 +3040,33 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~9_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~10_combout ; +wire \ula_|i2s_intf_|bitcount[2]~11 ; +wire \ula_|i2s_intf_|bitcount[3]~12_combout ; +wire \ula_|i2s_intf_|bitcount[3]~13 ; +wire \ula_|i2s_intf_|bitcount[4]~14_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|LessThan0~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~18_combout ; wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg[7]~1_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; wire \ula_|i2s_intf_|shiftreg~14_combout ; @@ -2866,25 +3077,19 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; +wire \ula_|i2s_intf_|shiftreg~2_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; wire \ula_|video_|Decoder0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2893,58 +3098,51 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; -wire \ula_|video_|bits[5]~feeder_combout ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[2]~feeder_combout ; -wire \ula_|video_|bits[2]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[2]~0_combout ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; +wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan6~0_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; -wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|border[2]~feeder_combout ; -wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|video_|attr[2]~feeder_combout ; +wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; -wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|VGA_HS~_Duplicate_1_q ; +wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|Selector0~0_combout ; wire \ula_|video_|VGA_HS~q ; wire \ula_|video_|VGA_VS~_Duplicate_1_q ; @@ -2958,290 +3156,305 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire \sdram_|Mux26~4_combout ; -wire \sdram_|r.bank[0]~7_combout ; -wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~6_combout ; wire \sdram_|r.bank[0]~4_combout ; wire \sdram_|r.bank[0]~5_combout ; -wire \sdram_|r.bank[0]~6_combout ; -wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|r.bank[0]~13_combout ; +wire \sdram_|r.bank[0]~11_combout ; wire \sdram_|Mux25~4_combout ; -wire \sdram_|Mux24~5_combout ; -wire \sdram_|Mux71~0_combout ; -wire \sdram_|process_0~7_combout ; -wire \sdram_|process_0~4_combout ; -wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~6_combout ; wire \sdram_|Mux71~2_combout ; wire \sdram_|Mux71~3_combout ; +wire \sdram_|process_0~8_combout ; +wire \sdram_|process_0~3_combout ; wire \sdram_|Mux71~4_combout ; -wire \sdram_|r.bank[0]~10_combout ; -wire \sdram_|Mux9~3_combout ; -wire \sdram_|n~5_combout ; -wire \sdram_|Mux9~4_combout ; -wire \sdram_|Mux9~2_combout ; -wire \sdram_|Equal2~3_combout ; -wire \sdram_|Mux10~2_combout ; -wire \sdram_|Mux10~3_combout ; -wire \sdram_|process_0~6_combout ; -wire \sdram_|Mux10~4_combout ; -wire \sdram_|Mux9~5_combout ; -wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux24~8_combout ; +wire \sdram_|Mux71~5_combout ; +wire \sdram_|n~6_combout ; +wire \sdram_|Mux9~0_combout ; wire \sdram_|Mux9~6_combout ; wire \sdram_|Mux9~7_combout ; -wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Equal5~1_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux9~1_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Mux9~3_combout ; wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|Mux10~4_combout ; wire \sdram_|Mux10~5_combout ; wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~12_combout ; wire \sdram_|Mux10~8_combout ; -wire \sdram_|Mux10~9_combout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~8_combout ; wire \sdram_|Mux11~2_combout ; wire \sdram_|Mux11~3_combout ; -wire \sdram_|Mux11~4_combout ; wire \sdram_|Mux11~5_combout ; wire \sdram_|Mux11~6_combout ; wire \sdram_|Mux11~7_combout ; -wire \sdram_|Mux11~9_combout ; -wire \sdram_|Mux11~8_combout ; -wire \sdram_|Mux24~2_combout ; -wire \sdram_|r.address[0]~7_combout ; -wire \sdram_|r.address[0]~0_combout ; -wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux24~6_combout ; wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~9_combout ; wire \sdram_|Mux13~5_combout ; wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~2_combout ; wire \sdram_|Mux24~3_combout ; wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~0_combout ; wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~8_combout ; +wire \sdram_|r.address[1]~9_combout ; +wire \sdram_|r.address[1]~7_combout ; +wire \sdram_|r.address[1]~10_combout ; +wire \sdram_|r.address[1]~1_combout ; wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; -wire \sdram_|Mux23~4_combout ; -wire \sdram_|Equal5~0_combout ; -wire \sdram_|Mux23~5_combout ; -wire \sdram_|Mux23~6_combout ; wire \sdram_|Mux19~0_combout ; wire \sdram_|r.address[1]~_Duplicate_1_q ; -wire \sdram_|Mux23~2_combout ; wire \sdram_|Mux23~3_combout ; -wire \sdram_|Mux23~1_combout ; -wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~5_combout ; wire \sdram_|r.address[1]~SLOAD_MUX_combout ; -wire \sdram_|r.address[3]~8_combout ; -wire \sdram_|r.address[3]~9_combout ; -wire \sdram_|Mux21~0_combout ; -wire \sdram_|Mux22~0_combout ; -wire \sdram_|r.address[3]~10_combout ; wire \sdram_|r.address[3]~11_combout ; wire \sdram_|r.address[3]~12_combout ; -wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; wire \sdram_|r.address[3]~14_combout ; wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~13_combout ; wire \sdram_|r.address[3]~16_combout ; wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|r.address[3]~18_combout ; +wire \sdram_|r.address[3]~19_combout ; +wire \sdram_|r.address[3]~20_combout ; wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux24~7_combout ; wire \sdram_|Mux20~4_combout ; -wire \sdram_|Mux20~7_combout ; -wire \sdram_|Mux23~7_combout ; -wire \sdram_|Mux20~8_combout ; -wire \sdram_|Mux20~10_combout ; -wire \sdram_|Mux20~9_combout ; -wire \sdram_|Mux20~11_combout ; -wire \sdram_|r.address[4]~_Duplicate_1_q ; -wire \sdram_|Mux20~12_combout ; -wire \sdram_|Mux20~5_combout ; -wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~2_combout ; +wire \sdram_|Mux20~3_combout ; wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~_Duplicate_1feeder_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~9_combout ; wire \sdram_|r.address[4]~SLOAD_MUX_combout ; -wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~4_combout ; -wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~7_combout ; wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~2_combout ; wire \sdram_|Mux19~3_combout ; wire \sdram_|r.address[5]~3_combout ; wire \sdram_|r.address[5]~SLOAD_MUX_combout ; wire \sdram_|Mux18~0_combout ; -wire \sdram_|Mux17~0_combout ; -wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux17~2_combout ; +wire \sdram_|Mux16~2_combout ; wire \sdram_|Mux15~2_combout ; -wire \sdram_|Mux14~0_combout ; -wire \sdram_|Mux14~1_combout ; -wire \sdram_|r.address[10]~4_combout ; -wire \sdram_|r.address[10]~_Duplicate_1_q ; -wire \sdram_|n~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1feeder_combout ; +wire \sdram_|n~5_combout ; wire \sdram_|Mux14~2_combout ; wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|r.address[10]~4_combout ; wire \sdram_|r.address[10]~SLOAD_MUX_combout ; -wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~21_combout ; +wire \sdram_|r.address[11]~22_combout ; wire \sdram_|r.address[11]~5_combout ; -wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; wire \sdram_|r.address[11]~_Duplicate_2_q ; wire \sdram_|Mux13~10_combout ; wire \sdram_|Mux13~6_combout ; wire \sdram_|r.address[11]~SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1_q ; -wire [9:0] \sdram_|r.rf_counter ; -wire [12:0] \sdram_|r.address ; -wire [15:0] \ula_|pcm_outl ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [8:0] \sdram_|r.state ; +wire [1:0] \sdram_|r.bank ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; +wire [1:0] \z80_|sw1_|SYNTHESIZED_WIRE_1 ; +wire [7:0] \z80_|data_pins_|dout ; +wire [3:0] \z80_|alu_|op1_low ; +wire [20:0] \debounce_autofire|r_Count ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [9:0] \sdram_|r.rf_counter ; +wire [1:0] \sdram_|r.dq_masks ; +wire [12:0] \sdram_|r.address ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [15:0] \ula_|pcm_outl ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; +wire [17:0] kempston_auto_fire_counter; +wire [20:0] \debounce_turbo|r_Count ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; -wire [3:0] \z80_|alu_|op2_low ; +wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|dout ; -wire [8:0] \sdram_|r.state ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [2:0] \z80_|sw1_|SYNTHESIZED_WIRE_2 ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [4:0] \ula_|zx_keyboard_|key_row ; +wire [3:0] \z80_|alu_|result_lo ; +wire [3:0] \z80_|alu_|op2_high ; +wire [3:0] \z80_|alu_|op1_high ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; wire [14:0] \sdram_|r.init_counter ; -wire [1:0] \sdram_|r.bank ; wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [3:0] \z80_|alu_|result_lo ; -wire [3:0] \z80_|alu_|op2_high ; -wire [3:0] \z80_|alu_|op1_high ; -wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; -wire [7:0] \z80_|ir_|opcode ; -wire [1:0] \sdram_|r.dq_masks ; -wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [3:0] \z80_|alu_|op1_low ; wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|ir_|opcode ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -3255,96 +3468,104 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; @@ -3355,14 +3576,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3375,11 +3588,19 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3391,14 +3612,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; - // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3609,8 +3822,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~67_combout ), - .oe(\D[0]~121_combout ), + .i(\D[0]~16_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3622,8 +3835,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~69_combout ), - .oe(\D[0]~121_combout ), + .i(\D[1]~18_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3635,8 +3848,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~71_combout ), - .oe(\D[0]~121_combout ), + .i(\D[2]~20_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3648,8 +3861,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~84_combout ), - .oe(\D[0]~121_combout ), + .i(\D[3]~22_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3661,8 +3874,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~96_combout ), - .oe(\D[0]~121_combout ), + .i(\D[4]~24_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3674,8 +3887,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~98_combout ), - .oe(\D[0]~121_combout ), + .i(\D[5]~27_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3687,8 +3900,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~106_combout ), - .oe(\D[0]~121_combout ), + .i(\D[6]~35_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3700,8 +3913,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~107_combout ), - .oe(\D[0]~121_combout ), + .i(\D[7]~37_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3739,7 +3952,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3778,7 +3991,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3791,7 +4004,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\SW[2]~input_o ), + .i(\turbo~q ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3804,7 +4017,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\raw_loader_in~input_o ), + .i(!\kempston[0]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3817,7 +4030,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(gnd), + .i(!\kempston[1]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3830,7 +4043,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(gnd), + .i(!\kempston[2]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3843,7 +4056,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(gnd), + .i(!\kempston[3]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3856,7 +4069,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\LED~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4166,32 +4379,6 @@ defparam \GPIO_1[31]~output .bus_hold = "false"; defparam \GPIO_1[31]~output .open_drain_output = "false"; // synopsys translate_on -// Location: IOOBUF_X53_Y16_N9 -cycloneive_io_obuf \GPIO_1[32]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[32]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[32]~output .bus_hold = "false"; -defparam \GPIO_1[32]~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOOBUF_X53_Y15_N9 -cycloneive_io_obuf \GPIO_1[33]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[33]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[33]~output .bus_hold = "false"; -defparam \GPIO_1[33]~output .open_drain_output = "false"; -// synopsys translate_on - // Location: IOOBUF_X16_Y34_N2 cycloneive_io_obuf \buzzer_out~output ( .i(\ula_|beep~q ), @@ -4504,6 +4691,19 @@ defparam \DRAM_ADDR[12]~output .bus_hold = "false"; defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \kempston_gnd~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(kempston_gnd), + .obar()); +// synopsys translate_off +defparam \kempston_gnd~output .bus_hold = "false"; +defparam \kempston_gnd~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -4597,7 +4797,7 @@ defparam \DRAM_DQ[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y15_N2 cycloneive_io_obuf \DRAM_DQ[5]~output ( - .i(\sdram_|Mux73~1_combout ), + .i(\sdram_|Mux73~0_combout ), .oe(\sdram_|Mux84~1_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4869,7 +5069,1083 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: IOIBUF_X53_Y16_N8 +cycloneive_io_ibuf \turbo_button~input ( + .i(turbo_button), + .ibar(gnd), + .o(\turbo_button~input_o )); +// synopsys translate_off +defparam \turbo_button~input .bus_hold = "false"; +defparam \turbo_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[0]~21 ( +// Equation(s): +// \debounce_turbo|r_Count[0]~21_combout = \debounce_turbo|r_Count [0] $ (VCC) +// \debounce_turbo|r_Count[0]~22 = CARRY(\debounce_turbo|r_Count [0]) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_turbo|r_Count[0]~21_combout ), + .cout(\debounce_turbo|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_turbo|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[1]~23 ( +// Equation(s): +// \debounce_turbo|r_Count[1]~23_combout = (\debounce_turbo|r_Count [1] & (!\debounce_turbo|r_Count[0]~22 )) # (!\debounce_turbo|r_Count [1] & ((\debounce_turbo|r_Count[0]~22 ) # (GND))) +// \debounce_turbo|r_Count[1]~24 = CARRY((!\debounce_turbo|r_Count[0]~22 ) # (!\debounce_turbo|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[0]~22 ), + .combout(\debounce_turbo|r_Count[1]~23_combout ), + .cout(\debounce_turbo|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N15 +dffeas \debounce_turbo|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[2]~25 ( +// Equation(s): +// \debounce_turbo|r_Count[2]~25_combout = (\debounce_turbo|r_Count [2] & (\debounce_turbo|r_Count[1]~24 $ (GND))) # (!\debounce_turbo|r_Count [2] & (!\debounce_turbo|r_Count[1]~24 & VCC)) +// \debounce_turbo|r_Count[2]~26 = CARRY((\debounce_turbo|r_Count [2] & !\debounce_turbo|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[1]~24 ), + .combout(\debounce_turbo|r_Count[2]~25_combout ), + .cout(\debounce_turbo|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N17 +dffeas \debounce_turbo|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[3]~27 ( +// Equation(s): +// \debounce_turbo|r_Count[3]~27_combout = (\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count[2]~26 )) # (!\debounce_turbo|r_Count [3] & ((\debounce_turbo|r_Count[2]~26 ) # (GND))) +// \debounce_turbo|r_Count[3]~28 = CARRY((!\debounce_turbo|r_Count[2]~26 ) # (!\debounce_turbo|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[2]~26 ), + .combout(\debounce_turbo|r_Count[3]~27_combout ), + .cout(\debounce_turbo|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N19 +dffeas \debounce_turbo|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[4]~29 ( +// Equation(s): +// \debounce_turbo|r_Count[4]~29_combout = (\debounce_turbo|r_Count [4] & (\debounce_turbo|r_Count[3]~28 $ (GND))) # (!\debounce_turbo|r_Count [4] & (!\debounce_turbo|r_Count[3]~28 & VCC)) +// \debounce_turbo|r_Count[4]~30 = CARRY((\debounce_turbo|r_Count [4] & !\debounce_turbo|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[3]~28 ), + .combout(\debounce_turbo|r_Count[4]~29_combout ), + .cout(\debounce_turbo|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N21 +dffeas \debounce_turbo|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N22 +cycloneive_lcell_comb \debounce_turbo|r_Count[5]~31 ( +// Equation(s): +// \debounce_turbo|r_Count[5]~31_combout = (\debounce_turbo|r_Count [5] & (!\debounce_turbo|r_Count[4]~30 )) # (!\debounce_turbo|r_Count [5] & ((\debounce_turbo|r_Count[4]~30 ) # (GND))) +// \debounce_turbo|r_Count[5]~32 = CARRY((!\debounce_turbo|r_Count[4]~30 ) # (!\debounce_turbo|r_Count [5])) + + .dataa(\debounce_turbo|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[4]~30 ), + .combout(\debounce_turbo|r_Count[5]~31_combout ), + .cout(\debounce_turbo|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N23 +dffeas \debounce_turbo|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N24 +cycloneive_lcell_comb \debounce_turbo|r_Count[6]~33 ( +// Equation(s): +// \debounce_turbo|r_Count[6]~33_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count[5]~32 $ (GND))) # (!\debounce_turbo|r_Count [6] & (!\debounce_turbo|r_Count[5]~32 & VCC)) +// \debounce_turbo|r_Count[6]~34 = CARRY((\debounce_turbo|r_Count [6] & !\debounce_turbo|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[5]~32 ), + .combout(\debounce_turbo|r_Count[6]~33_combout ), + .cout(\debounce_turbo|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N25 +dffeas \debounce_turbo|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N26 +cycloneive_lcell_comb \debounce_turbo|r_Count[7]~35 ( +// Equation(s): +// \debounce_turbo|r_Count[7]~35_combout = (\debounce_turbo|r_Count [7] & (!\debounce_turbo|r_Count[6]~34 )) # (!\debounce_turbo|r_Count [7] & ((\debounce_turbo|r_Count[6]~34 ) # (GND))) +// \debounce_turbo|r_Count[7]~36 = CARRY((!\debounce_turbo|r_Count[6]~34 ) # (!\debounce_turbo|r_Count [7])) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[6]~34 ), + .combout(\debounce_turbo|r_Count[7]~35_combout ), + .cout(\debounce_turbo|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N27 +dffeas \debounce_turbo|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N28 +cycloneive_lcell_comb \debounce_turbo|r_Count[8]~37 ( +// Equation(s): +// \debounce_turbo|r_Count[8]~37_combout = (\debounce_turbo|r_Count [8] & (\debounce_turbo|r_Count[7]~36 $ (GND))) # (!\debounce_turbo|r_Count [8] & (!\debounce_turbo|r_Count[7]~36 & VCC)) +// \debounce_turbo|r_Count[8]~38 = CARRY((\debounce_turbo|r_Count [8] & !\debounce_turbo|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[7]~36 ), + .combout(\debounce_turbo|r_Count[8]~37_combout ), + .cout(\debounce_turbo|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N29 +dffeas \debounce_turbo|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N30 +cycloneive_lcell_comb \debounce_turbo|r_Count[9]~39 ( +// Equation(s): +// \debounce_turbo|r_Count[9]~39_combout = (\debounce_turbo|r_Count [9] & (!\debounce_turbo|r_Count[8]~38 )) # (!\debounce_turbo|r_Count [9] & ((\debounce_turbo|r_Count[8]~38 ) # (GND))) +// \debounce_turbo|r_Count[9]~40 = CARRY((!\debounce_turbo|r_Count[8]~38 ) # (!\debounce_turbo|r_Count [9])) + + .dataa(\debounce_turbo|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[8]~38 ), + .combout(\debounce_turbo|r_Count[9]~39_combout ), + .cout(\debounce_turbo|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N31 +dffeas \debounce_turbo|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N0 +cycloneive_lcell_comb \debounce_turbo|r_Count[10]~41 ( +// Equation(s): +// \debounce_turbo|r_Count[10]~41_combout = (\debounce_turbo|r_Count [10] & (\debounce_turbo|r_Count[9]~40 $ (GND))) # (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count[9]~40 & VCC)) +// \debounce_turbo|r_Count[10]~42 = CARRY((\debounce_turbo|r_Count [10] & !\debounce_turbo|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[9]~40 ), + .combout(\debounce_turbo|r_Count[10]~41_combout ), + .cout(\debounce_turbo|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N1 +dffeas \debounce_turbo|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N2 +cycloneive_lcell_comb \debounce_turbo|r_Count[11]~43 ( +// Equation(s): +// \debounce_turbo|r_Count[11]~43_combout = (\debounce_turbo|r_Count [11] & (!\debounce_turbo|r_Count[10]~42 )) # (!\debounce_turbo|r_Count [11] & ((\debounce_turbo|r_Count[10]~42 ) # (GND))) +// \debounce_turbo|r_Count[11]~44 = CARRY((!\debounce_turbo|r_Count[10]~42 ) # (!\debounce_turbo|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[10]~42 ), + .combout(\debounce_turbo|r_Count[11]~43_combout ), + .cout(\debounce_turbo|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N3 +dffeas \debounce_turbo|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N4 +cycloneive_lcell_comb \debounce_turbo|r_Count[12]~45 ( +// Equation(s): +// \debounce_turbo|r_Count[12]~45_combout = (\debounce_turbo|r_Count [12] & (\debounce_turbo|r_Count[11]~44 $ (GND))) # (!\debounce_turbo|r_Count [12] & (!\debounce_turbo|r_Count[11]~44 & VCC)) +// \debounce_turbo|r_Count[12]~46 = CARRY((\debounce_turbo|r_Count [12] & !\debounce_turbo|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[11]~44 ), + .combout(\debounce_turbo|r_Count[12]~45_combout ), + .cout(\debounce_turbo|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N5 +dffeas \debounce_turbo|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N6 +cycloneive_lcell_comb \debounce_turbo|r_Count[13]~47 ( +// Equation(s): +// \debounce_turbo|r_Count[13]~47_combout = (\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count[12]~46 )) # (!\debounce_turbo|r_Count [13] & ((\debounce_turbo|r_Count[12]~46 ) # (GND))) +// \debounce_turbo|r_Count[13]~48 = CARRY((!\debounce_turbo|r_Count[12]~46 ) # (!\debounce_turbo|r_Count [13])) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[12]~46 ), + .combout(\debounce_turbo|r_Count[13]~47_combout ), + .cout(\debounce_turbo|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N7 +dffeas \debounce_turbo|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_State~7 ( +// Equation(s): +// \debounce_turbo|r_State~7_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count [7] & \debounce_turbo|r_Count [5])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(\debounce_turbo|r_Count [7]), + .datad(\debounce_turbo|r_Count [5]), + .cin(gnd), + .combout(\debounce_turbo|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~7 .lut_mask = 16'hC000; +defparam \debounce_turbo|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N2 +cycloneive_lcell_comb \debounce_turbo|LessThan0~0 ( +// Equation(s): +// \debounce_turbo|LessThan0~0_combout = (!\debounce_turbo|r_State~7_combout & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_State~7_combout ), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N30 +cycloneive_lcell_comb \debounce_turbo|LessThan0~1 ( +// Equation(s): +// \debounce_turbo|LessThan0~1_combout = (!\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count [12] & ((\debounce_turbo|LessThan0~0_combout ) # (!\debounce_turbo|r_Count [11])))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [12]), + .datac(\debounce_turbo|LessThan0~0_combout ), + .datad(\debounce_turbo|r_Count [11]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~1 .lut_mask = 16'h1011; +defparam \debounce_turbo|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N8 +cycloneive_lcell_comb \debounce_turbo|r_Count[14]~49 ( +// Equation(s): +// \debounce_turbo|r_Count[14]~49_combout = (\debounce_turbo|r_Count [14] & (\debounce_turbo|r_Count[13]~48 $ (GND))) # (!\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count[13]~48 & VCC)) +// \debounce_turbo|r_Count[14]~50 = CARRY((\debounce_turbo|r_Count [14] & !\debounce_turbo|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[13]~48 ), + .combout(\debounce_turbo|r_Count[14]~49_combout ), + .cout(\debounce_turbo|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N9 +dffeas \debounce_turbo|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N10 +cycloneive_lcell_comb \debounce_turbo|r_Count[15]~51 ( +// Equation(s): +// \debounce_turbo|r_Count[15]~51_combout = (\debounce_turbo|r_Count [15] & (!\debounce_turbo|r_Count[14]~50 )) # (!\debounce_turbo|r_Count [15] & ((\debounce_turbo|r_Count[14]~50 ) # (GND))) +// \debounce_turbo|r_Count[15]~52 = CARRY((!\debounce_turbo|r_Count[14]~50 ) # (!\debounce_turbo|r_Count [15])) + + .dataa(\debounce_turbo|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[14]~50 ), + .combout(\debounce_turbo|r_Count[15]~51_combout ), + .cout(\debounce_turbo|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N11 +dffeas \debounce_turbo|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[16]~53 ( +// Equation(s): +// \debounce_turbo|r_Count[16]~53_combout = (\debounce_turbo|r_Count [16] & (\debounce_turbo|r_Count[15]~52 $ (GND))) # (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count[15]~52 & VCC)) +// \debounce_turbo|r_Count[16]~54 = CARRY((\debounce_turbo|r_Count [16] & !\debounce_turbo|r_Count[15]~52 )) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[15]~52 ), + .combout(\debounce_turbo|r_Count[16]~53_combout ), + .cout(\debounce_turbo|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_turbo|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N13 +dffeas \debounce_turbo|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[17]~55 ( +// Equation(s): +// \debounce_turbo|r_Count[17]~55_combout = (\debounce_turbo|r_Count [17] & (!\debounce_turbo|r_Count[16]~54 )) # (!\debounce_turbo|r_Count [17] & ((\debounce_turbo|r_Count[16]~54 ) # (GND))) +// \debounce_turbo|r_Count[17]~56 = CARRY((!\debounce_turbo|r_Count[16]~54 ) # (!\debounce_turbo|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[16]~54 ), + .combout(\debounce_turbo|r_Count[17]~55_combout ), + .cout(\debounce_turbo|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N15 +dffeas \debounce_turbo|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[18]~57 ( +// Equation(s): +// \debounce_turbo|r_Count[18]~57_combout = (\debounce_turbo|r_Count [18] & (\debounce_turbo|r_Count[17]~56 $ (GND))) # (!\debounce_turbo|r_Count [18] & (!\debounce_turbo|r_Count[17]~56 & VCC)) +// \debounce_turbo|r_Count[18]~58 = CARRY((\debounce_turbo|r_Count [18] & !\debounce_turbo|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[17]~56 ), + .combout(\debounce_turbo|r_Count[18]~57_combout ), + .cout(\debounce_turbo|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N17 +dffeas \debounce_turbo|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[19]~59 ( +// Equation(s): +// \debounce_turbo|r_Count[19]~59_combout = (\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count[18]~58 )) # (!\debounce_turbo|r_Count [19] & ((\debounce_turbo|r_Count[18]~58 ) # (GND))) +// \debounce_turbo|r_Count[19]~60 = CARRY((!\debounce_turbo|r_Count[18]~58 ) # (!\debounce_turbo|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[18]~58 ), + .combout(\debounce_turbo|r_Count[19]~59_combout ), + .cout(\debounce_turbo|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N19 +dffeas \debounce_turbo|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N22 +cycloneive_lcell_comb \debounce_turbo|always0~0 ( +// Equation(s): +// \debounce_turbo|always0~0_combout = (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count [17] & !\debounce_turbo|r_Count [18]))) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(\debounce_turbo|r_Count [19]), + .datac(\debounce_turbo|r_Count [17]), + .datad(\debounce_turbo|r_Count [18]), + .cin(gnd), + .combout(\debounce_turbo|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N24 +cycloneive_lcell_comb \debounce_turbo|always0~1 ( +// Equation(s): +// \debounce_turbo|always0~1_combout = (\debounce_turbo|always0~0_combout & ((\debounce_turbo|LessThan0~1_combout ) # ((!\debounce_turbo|r_Count [15]) # (!\debounce_turbo|r_Count [14])))) + + .dataa(\debounce_turbo|LessThan0~1_combout ), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|always0~0_combout ), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_turbo|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[20]~61 ( +// Equation(s): +// \debounce_turbo|r_Count[20]~61_combout = \debounce_turbo|r_Count[19]~60 $ (!\debounce_turbo|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_turbo|r_Count [20]), + .cin(\debounce_turbo|r_Count[19]~60 ), + .combout(\debounce_turbo|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_turbo|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N21 +dffeas \debounce_turbo|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N0 +cycloneive_lcell_comb \debounce_turbo|always0~2 ( +// Equation(s): +// \debounce_turbo|always0~2_combout = (\debounce_turbo|always0~1_combout & (\debounce_turbo|r_State~q $ ((!\turbo_button~input_o )))) # (!\debounce_turbo|always0~1_combout & ((\debounce_turbo|r_Count [20]) # (\debounce_turbo|r_State~q $ +// (!\turbo_button~input_o )))) + + .dataa(\debounce_turbo|always0~1_combout ), + .datab(\debounce_turbo|r_State~q ), + .datac(\turbo_button~input_o ), + .datad(\debounce_turbo|r_Count [20]), + .cin(gnd), + .combout(\debounce_turbo|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~2 .lut_mask = 16'hD7C3; +defparam \debounce_turbo|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y29_N13 +dffeas \debounce_turbo|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N10 +cycloneive_lcell_comb \debounce_turbo|r_State~4 ( +// Equation(s): +// \debounce_turbo|r_State~4_combout = (!\debounce_turbo|r_Count [0] & (!\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count [1] & !\debounce_turbo|r_Count [2]))) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(\debounce_turbo|r_Count [3]), + .datac(\debounce_turbo|r_Count [1]), + .datad(\debounce_turbo|r_Count [2]), + .cin(gnd), + .combout(\debounce_turbo|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_turbo|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N6 +cycloneive_lcell_comb \debounce_turbo|r_State~2 ( +// Equation(s): +// \debounce_turbo|r_State~2_combout = (\debounce_turbo|r_Count [20] & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_Count [20]), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_turbo|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N28 +cycloneive_lcell_comb \debounce_turbo|r_State~0 ( +// Equation(s): +// \debounce_turbo|r_State~0_combout = (!\debounce_turbo|r_Count [13] & (\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count [12] & \debounce_turbo|r_Count [15]))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|r_Count [12]), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_turbo|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~1 ( +// Equation(s): +// \debounce_turbo|r_State~1_combout = (\debounce_turbo|r_Count [7] & (\debounce_turbo|r_Count [11] & (\debounce_turbo|r_Count [5] & \debounce_turbo|r_Count [6]))) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(\debounce_turbo|r_Count [11]), + .datac(\debounce_turbo|r_Count [5]), + .datad(\debounce_turbo|r_Count [6]), + .cin(gnd), + .combout(\debounce_turbo|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N0 +cycloneive_lcell_comb \debounce_turbo|r_State~3 ( +// Equation(s): +// \debounce_turbo|r_State~3_combout = (\debounce_turbo|r_State~2_combout & (\debounce_turbo|r_State~0_combout & (\debounce_turbo|r_State~1_combout & \debounce_turbo|always0~0_combout ))) + + .dataa(\debounce_turbo|r_State~2_combout ), + .datab(\debounce_turbo|r_State~0_combout ), + .datac(\debounce_turbo|r_State~1_combout ), + .datad(\debounce_turbo|always0~0_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N8 +cycloneive_lcell_comb \debounce_turbo|r_State~5 ( +// Equation(s): +// \debounce_turbo|r_State~5_combout = (\debounce_turbo|r_State~4_combout & (!\debounce_turbo|r_Count [4] & \debounce_turbo|r_State~3_combout )) + + .dataa(\debounce_turbo|r_State~4_combout ), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(\debounce_turbo|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~5 .lut_mask = 16'h2200; +defparam \debounce_turbo|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~6 ( +// Equation(s): +// \debounce_turbo|r_State~6_combout = (\debounce_turbo|r_State~5_combout & (\turbo_button~input_o )) # (!\debounce_turbo|r_State~5_combout & ((\debounce_turbo|r_State~q ))) + + .dataa(\turbo_button~input_o ), + .datab(gnd), + .datac(\debounce_turbo|r_State~q ), + .datad(\debounce_turbo|r_State~5_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~6 .lut_mask = 16'hAAF0; +defparam \debounce_turbo|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N5 +dffeas \debounce_turbo|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_turbo|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_State .is_wysiwyg = "true"; +defparam \debounce_turbo|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N14 +cycloneive_lcell_comb \turbo~0 ( +// Equation(s): +// \turbo~0_combout = !\turbo~q + + .dataa(gnd), + .datab(gnd), + .datac(\turbo~q ), + .datad(gnd), + .cin(gnd), + .combout(\turbo~0_combout ), + .cout()); +// synopsys translate_off +defparam \turbo~0 .lut_mask = 16'h0F0F; +defparam \turbo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N15 +dffeas turbo( + .clk(!\debounce_turbo|r_State~q ), + .d(\turbo~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\turbo~q ), + .prn(vcc)); +// synopsys translate_off +defparam turbo.is_wysiwyg = "true"; +defparam turbo.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y29_N4 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4886,7 +6162,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y29_N5 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4905,34 +6181,24 @@ defparam \ula_|clocks_|counter[0] .is_wysiwyg = "true"; defparam \ula_|clocks_|counter[0] .power_up = "low"; // synopsys translate_on -// Location: IOIBUF_X25_Y34_N8 -cycloneive_io_ibuf \SW[2]~input ( - .i(SW[2]), - .ibar(gnd), - .o(\SW[2]~input_o )); -// synopsys translate_off -defparam \SW[2]~input .bus_hold = "false"; -defparam \SW[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): -// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) +// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\turbo~q ) # (!\ula_|clocks_|counter [0]))) .dataa(gnd), - .datab(\ula_|clocks_|counter [0]), + .datab(\turbo~q ), .datac(\ula_|clocks_|clk_cpu~q ), - .datad(\SW[2]~input_o ), + .datad(\ula_|clocks_|counter [0]), .cin(gnd), .combout(\ula_|clocks_|clk_cpu~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; +defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h3C0F; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4951,7 +6217,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4964,33 +6230,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -5001,7 +6240,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N12 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -5018,7 +6257,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N18 +// Location: LCCOMB_X27_Y15_N4 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -5035,7 +6274,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y32_N8 +// Location: LCCOMB_X27_Y1_N28 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -5052,7 +6291,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X26_Y32_N9 +// Location: FF_X27_Y1_N29 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -5071,7 +6310,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -5084,7 +6323,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y14_N19 +// Location: FF_X27_Y15_N5 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -5103,79 +6342,68 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: FF_X31_Y14_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Location: LCCOMB_X23_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC .dataa(gnd), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(gnd), + .datad(gnd), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y10_N1 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G7 +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~55_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), @@ -5188,21 +6416,40 @@ defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout ) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .combout(\z80_|sequencer_|ena_M~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N19 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -5218,7 +6465,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N8 +// Location: LCCOMB_X26_Y31_N0 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) @@ -5236,24 +6483,24 @@ defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N14 +// Location: LCCOMB_X30_Y31_N10 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~0_combout ), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Add0~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hC0C0; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y29_N15 +// Location: FF_X30_Y31_N11 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -5272,7 +6519,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N10 +// Location: LCCOMB_X26_Y31_N2 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -5290,7 +6537,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N22 +// Location: LCCOMB_X29_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -5307,7 +6554,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y30_N23 +// Location: FF_X29_Y31_N13 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -5326,7 +6573,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N12 +// Location: LCCOMB_X26_Y31_N4 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -5344,7 +6591,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N31 +// Location: FF_X29_Y31_N15 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5363,33 +6610,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N14 +// Location: LCCOMB_X26_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(\ula_|video_|vga_hc [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y30_N11 +// Location: FF_X26_Y31_N7 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|Add0~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -5400,7 +6647,24 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N16 +// Location: LCCOMB_X30_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N8 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -5418,7 +6682,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N7 +// Location: FF_X26_Y31_N25 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5437,169 +6701,42 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Location: LCCOMB_X30_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( // Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & !\ula_|video_|vga_hc [4]))) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Add0~10_combout ), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [4]), .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), + .combout(\ula_|video_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y30_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N22 +// Location: LCCOMB_X26_Y31_N14 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) // \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - .dataa(\ula_|video_|vga_hc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~13 ), .combout(\ula_|video_|Add0~14_combout ), .cout(\ula_|video_|Add0~15 )); // synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N3 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N26 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N24 +// Location: LCCOMB_X26_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) @@ -5617,15 +6754,15 @@ defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N28 +// Location: LCCOMB_X26_Y31_N22 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~16_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); @@ -5634,7 +6771,7 @@ defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N17 +// Location: FF_X26_Y31_N15 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5653,32 +6790,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N26 +// Location: LCCOMB_X26_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N2 +// Location: LCCOMB_X26_Y31_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -5687,7 +6824,7 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N5 +// Location: FF_X26_Y31_N31 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5706,24 +6843,134 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y29_N0 +// Location: LCCOMB_X30_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal1~0 ( // Equation(s): // \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N0 +// Location: LCCOMB_X26_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y31_N23 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N21 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N29 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) @@ -5741,312 +6988,77 @@ defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Location: LCCOMB_X31_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [0] & !\ula_|video_|vga_vc [1]))) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Add1~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N31 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [3]), .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), + .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N21 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N26 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N27 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N23 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N10 +// Location: LCCOMB_X31_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N9 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N12 +// Location: LCCOMB_X31_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N16 +// Location: LCCOMB_X27_Y31_N28 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N17 +// Location: FF_X27_Y31_N29 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -6065,7 +7077,7 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N14 +// Location: LCCOMB_X31_Y31_N20 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) @@ -6083,7 +7095,7 @@ defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N22 +// Location: LCCOMB_X27_Y31_N8 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) @@ -6100,7 +7112,7 @@ defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N23 +// Location: FF_X27_Y31_N9 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -6119,25 +7131,25 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N16 +// Location: LCCOMB_X31_Y31_N22 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) // \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~15 ), .combout(\ula_|video_|Add1~16_combout ), .cout(\ula_|video_|Add1~17 )); // synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N20 +// Location: LCCOMB_X27_Y31_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): // \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) @@ -6154,7 +7166,7 @@ defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N21 +// Location: FF_X27_Y31_N7 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -6173,41 +7185,41 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N18 +// Location: LCCOMB_X31_Y31_N24 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) +// \ula_|video_|Add1~18_combout = \ula_|video_|vga_vc [9] $ (\ula_|video_|Add1~17 ) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [9]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), + .datad(gnd), .cin(\ula_|video_|Add1~17 ), .combout(\ula_|video_|Add1~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .lut_mask = 16'h5A5A; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N8 +// Location: LCCOMB_X27_Y31_N4 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N9 +// Location: FF_X27_Y31_N5 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -6226,32 +7238,15 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N30 +// Location: LCCOMB_X27_Y31_N24 cycloneive_lcell_comb \ula_|video_|Equal2~0 ( // Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [6]))) .dataa(\ula_|video_|vga_vc [8]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), .combout(\ula_|video_|Equal2~0_combout ), .cout()); @@ -6260,13 +7255,13 @@ defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N16 +// Location: LCCOMB_X31_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) +// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal3~0_combout & (\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|Equal3~0_combout ), + .dataa(\ula_|video_|Equal3~0_combout ), + .datab(\ula_|video_|vga_vc [9]), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), @@ -6277,24 +7272,24 @@ defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N24 +// Location: LCCOMB_X27_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( // Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~0_combout ), .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N25 +// Location: FF_X27_Y31_N13 dffeas \ula_|video_|vga_vc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[0]~0_combout ), @@ -6313,15 +7308,267 @@ defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N18 +// Location: LCCOMB_X31_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N18 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N19 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h0A0C; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[2]~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N2 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [3]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~6_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~6_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N3 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N0 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) .dataa(\ula_|video_|vga_vc [0]), .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [3]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -6330,20 +7577,20 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N12 +// Location: LCCOMB_X31_Y31_N26 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(\ula_|video_|Equal2~1_combout ), - .datab(gnd), - .datac(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(gnd), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -6357,14 +7604,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X31_Y27_N2 +// Location: LCCOMB_X28_Y31_N26 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & !\SW[1]~input_o ))) - .dataa(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), .datab(\ula_|video_|vga_vc [1]), - .datac(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -6374,75 +7621,77 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|ir_|opcode[4]~feeder ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|ir_|opcode[4]~feeder_combout = \z80_|bus_control_|db[4]~18_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal0~0_combout ), + .combout(\z80_|ir_|opcode[4]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; -defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; +defparam \z80_|ir_|opcode[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N8 +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N13 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N9 +// Location: FF_X36_Y11_N21 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -6461,340 +7710,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N27 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - - .dataa(\z80_|clk_delay_|DFF_inst5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N24 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~2_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & -// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N25 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 +// Location: LCCOMB_X36_Y11_N30 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N1 +// Location: FF_X36_Y11_N31 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -6813,2615 +7746,32 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N2 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIOWrite~2_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|fMWrite~3_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~45_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N11 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~97_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~96_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~98_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~98_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), - .datab(\z80_|execute_|ctl_inc_cy~96_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(gnd), - .datad(\z80_|execute_|fMWrite~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [7]), - .datac(gnd), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N24 +// Location: LCCOMB_X37_Y14_N10 cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( // Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) +// \z80_|execute_|ctl_ir_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|ctl_ir_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h5050; defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; -defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & -// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|fMWrite~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # -// (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N21 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y11_N17 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N15 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X40_Y11_N23 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~12_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~16_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N13 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N21 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N17 +// Location: FF_X30_Y12_N5 dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~53_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|execute_|setM1~55_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -9432,24 +7782,24 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N8 +// Location: LCCOMB_X30_Y12_N8 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h0F0F; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N9 +// Location: FF_X30_Y12_N9 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -9468,7 +7818,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N7 +// Location: FF_X30_Y12_N19 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -9487,7 +7837,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N6 +// Location: LCCOMB_X30_Y12_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & @@ -9505,34385 +7855,358 @@ defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N10 +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h333B; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~0_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~0 .lut_mask = 16'h0505; +defparam \z80_|pla_decode_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [0] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0800; defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|fIOWrite~0_combout ), - .datad(\z80_|execute_|fIORead~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|execute_|fIORead~0_combout ), - .datac(\z80_|execute_|fIOWrite~1_combout ), - .datad(\z80_|execute_|fIORead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N23 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|im2~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|execute_|fMRead~4_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal40~2_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; -defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~14_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|execute_|setM1~57_combout ), - .datab(\z80_|execute_|setM1~38_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~19_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|DFFE_instED~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~31_combout ), - .datab(\z80_|execute_|ctl_mRead~32_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N19 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~33_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N29 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N11 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) - - .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), - .datab(\z80_|execute_|fIORead~3_combout ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~1_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N12 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h3000; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G9 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & -// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N13 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [5]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [3]), - .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N27 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N7 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [0]), - .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N17 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X18_Y12_N19 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N29 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N13 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N23 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\PS2_DAT~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|always1~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y10_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N13 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X21_Y8_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) - - .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N25 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N27 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N25 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N5 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) - - .dataa(\z80_|resets_|clrpc_int~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & -// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~99_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~37_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal12~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal33~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout -// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal76~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal10~1_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & -// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|fMRead~8_combout ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_sw_4d~0_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; -defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_inc_dec~3_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N25 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|setM1~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & -// ((\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|execute_|ctl_state_alu~13_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|fMRead~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~25_combout ), - .datac(\z80_|execute_|ctl_mRead~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & -// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_sw_1d~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & -// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; -defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # -// (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # -// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_1d~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(\z80_|execute_|ctl_sw_4u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .datad(\z80_|execute_|ctl_sw_4u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_2d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|fMRead~18_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~22_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|fMRead~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_2d~9_combout ), - .datac(\z80_|execute_|ctl_sw_1d~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; -defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal44~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & -// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; -defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_flags_alu~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; -defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~18_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~26_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datab(\z80_|alu_control_|db[1]~27_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Location: LCCOMB_X35_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), .datac(\z80_|sequencer_|DFFE_M2_ff~q ), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & -// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_oe~15_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ -// (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datac(\z80_|execute_|ctl_sw_2u~6_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N27 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; -defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_cy~50_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N24 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~26_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~10_combout ), - .datad(\z80_|execute_|ctl_sw_2d~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_alu_oe~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~10_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & -// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) - - .dataa(\z80_|alu_control_|db[3]~36_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # -// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) - - .dataa(\z80_|execute_|setM1~50_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(\z80_|alu_flags_|flags_xf~q ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; -defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~87_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~64_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~65_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~97_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~57_combout ), - .datad(\z80_|execute_|ctl_inc_cy~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout -// & (\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal33~2_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; -defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|pc_inc_hold~19_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; -defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|pc_inc_hold~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # -// ((\z80_|execute_|ctl_inc_cy~62_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_inc_cy~68_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~17_combout ), - .datab(\z80_|execute_|ctl_inc_cy~74_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~73_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~95_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|ctl_inc_cy~95_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datad(\z80_|execute_|ctl_inc_cy~77_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_inc_cy~78_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~15_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~70_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|ctl_inc_cy~79_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # -// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|pc_inc_hold~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_inc_cy~51_combout ), - .datac(\z80_|execute_|ctl_inc_cy~49_combout ), - .datad(\z80_|execute_|ctl_inc_cy~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_inc_cy~90_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~83_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~96_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~100_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|ctl_inc_cy~84_combout ), - .datac(\z80_|execute_|ctl_inc_cy~100_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~24_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|pc_inc_hold~29_combout ), - .datad(\z80_|execute_|pc_inc_hold~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|Q [0]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( -// Equation(s): -// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[0]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|execute_|ctl_inc_dec~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [2]), - .datab(gnd), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( -// Equation(s): -// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db_low[2]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; -defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|alu_|db[1]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & -// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(\z80_|execute_|ctl_al_we~10_combout ), - .datac(\z80_|execute_|ctl_al_we~8_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~11_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N7 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( -// Equation(s): -// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; -defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & -// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N11 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( -// Equation(s): -// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; -defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( -// Equation(s): -// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; -defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( -// Equation(s): -// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; -defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(\z80_|address_latch_|Q [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N3 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q -// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N1 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & -// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N2 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[4]~8_combout ), - .datad(\z80_|alu_|db_high[0]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N13 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( -// Equation(s): -// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( -// Equation(s): -// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db_low[1]~18_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [1]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~16_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( -// Equation(s): -// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # -// (!\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|alu_|db_low[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[1]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; -defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[1]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N9 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout -// )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_flags_alu~21_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # -// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N11 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & -// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # -// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|alu_|db_high[2]~13_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[2]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N3 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_high [2]), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( -// Equation(s): -// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; -defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db_high[2]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|alu_|db_high[2]~10_combout ), - .datac(\z80_|alu_|db_high[2]~9_combout ), - .datad(\z80_|alu_|db_high[2]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[2]~12_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|alu_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N16 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( -// Equation(s): -// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; -defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [1]), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[1]~14_combout ), - .datad(\z80_|alu_|db_high[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|db_high[1]~18_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N21 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N4 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N18 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[7]~19_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & -// ((\z80_|alu_|db[7]~20_combout ))))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~8_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N11 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|alu_|op1_high [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; -defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_high[2]~13_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[2]~14_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N31 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; -defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|op1_low [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_|alu_op2[2]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|alu_op2[2]~1_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # -// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|alu_op1[3]~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op2[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( -// Equation(s): -// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N23 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( -// Equation(s): -// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~24_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( -// Equation(s): -// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & -// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[0]~22_combout ), - .datac(\z80_|alu_|db_low[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_low[0]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N17 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # -// (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & -// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout -// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # -// (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & -// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[0]~1_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(gnd), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( -// Equation(s): -// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; -defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[0]~23_combout ), - .datad(\z80_|alu_|db_high[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|db_high[0]~24_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N19 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( -// Equation(s): -// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|result_lo [2]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( -// Equation(s): -// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( -// Equation(s): -// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|alu_|db_low[2]~12_combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; -defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( -// Equation(s): -// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[2]~10_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~11_combout ), - .datad(\z80_|alu_|db_low[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; -defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N22 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~11_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~33_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( -// Equation(s): -// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; -defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( -// Equation(s): -// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[2]~28_combout ), - .datab(\z80_|alu_control_|db[2]~24_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[2]~29_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; -defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N27 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & -// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N20 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_control_|db[0]~14_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( -// Equation(s): -// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( -// Equation(s): -// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[0]~11_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_flags_|flags_cf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout -// ))))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(\z80_|execute_|ctl_inc_cy~93_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~9_combout ), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & -// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q -// [2]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~34_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|sw1_|db_down[3]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( -// Equation(s): -// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; -defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N10 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( -// Equation(s): -// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y10_N25 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( -// Equation(s): -// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~6_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) - - .dataa(\z80_|alu_|db_low[3]~5_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|result_lo [3]), - .datad(\z80_|alu_|db_low[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( -// Equation(s): -// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; -defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[3]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N13 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[3]~7_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N21 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op1[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & -// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|alu_control_|out[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|alu_|db[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout -// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_control_|out[6]~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal10~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( // Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), + .combout(\z80_|execute_|ctl_mRead~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_sw_1d~2_combout = (\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~2_combout & +// (((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - .dataa(\z80_|pla_decode_|Equal64~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N2 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[4]~31_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( -// Equation(s): -// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[4]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; -defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N5 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [4]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|Q [5]), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [3]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [1]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [14]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X30_Y12_N19 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// (!\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; -defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .datad(\z80_|alu_|alu_parity_out~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y11_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|alu_|db_high[0]~25_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .datab(\z80_|alu_control_|db[6]~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N25 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|alu_control_|sel[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_control_|sel[1]~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N9 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N13 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [11]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & -// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y4_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [11]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N6 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N7 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N26 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\z80_|address_pins_|abus[10]~20_combout ), - .datad(\ula_|zx_keyboard_|keys[3][2]~q ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hC4F5; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~2_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N31 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; -defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) - - .dataa(\z80_|address_latch_|abusz [14]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N14 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; -defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; -defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N1 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N10 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & -// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hC4F5; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [13]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N18 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|key_row~1_combout ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'h80A0; -defparam \D[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [0]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; -defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N13 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [9]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [8]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N20 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'hF531; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N24 -cycloneive_lcell_comb \D[2]~46 ( -// Equation(s): -// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) - - .dataa(\D[2]~43_combout ), - .datab(\D[2]~45_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hF8F0; -defparam \D[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N3 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|clk_delay_|DFF_inst5~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( -// Equation(s): -// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; -defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N8 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0020; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N18 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h4000; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N16 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|address_latch_|abusz [2]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [3]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [3]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [6]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X24_Y19_N11 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N3 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ExtRamWE~0_combout ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X25_Y19_N15 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N19 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N10 -cycloneive_lcell_comb \D[2]~50 ( -// Equation(s): -// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\D[2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~50 .lut_mask = 16'hF838; -defparam \D[2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N26 -cycloneive_lcell_comb \D[2]~51 ( -// Equation(s): -// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~50_combout ), - .cin(gnd), - .combout(\D[2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~51 .lut_mask = 16'hEE30; -defparam \D[2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N24 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N8 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N25 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|vram_address[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N31 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N4 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N5 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N23 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N17 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( -// Equation(s): -// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) - - .dataa(\ula_|video_|vga_vc [8]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N7 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N18 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|vram_address[10]~2_combout ), - .datab(\ula_|video_|Add4~4_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N19 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N24 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N25 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N3 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N28 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N29 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N20 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N21 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y18_N0 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N22 -cycloneive_lcell_comb \D[2]~47 ( -// Equation(s): -// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~47 .lut_mask = 16'hE6A2; -defparam \D[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N24 -cycloneive_lcell_comb \D[2]~48 ( -// Equation(s): -// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[2]~47_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~48 .lut_mask = 16'h4B48; -defparam \D[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N16 -cycloneive_lcell_comb \D[2]~49 ( -// Equation(s): -// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[2]~47_combout ), - .datad(\D[2]~48_combout ), - .cin(gnd), - .combout(\D[2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~49 .lut_mask = 16'hC3E0; -defparam \D[2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N6 -cycloneive_lcell_comb \D[2]~119 ( -// Equation(s): -// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~51_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~51_combout ), - .datad(\D[2]~49_combout ), - .cin(gnd), - .combout(\D[2]~119_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~119 .lut_mask = 16'hF4B0; -defparam \D[2]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N20 -cycloneive_lcell_comb \D[2]~52 ( -// Equation(s): -// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[2]~46_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~52 .lut_mask = 16'hBFB3; -defparam \D[2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N26 -cycloneive_lcell_comb \D[2]~53 ( -// Equation(s): -// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~52_combout ), - .cin(gnd), - .combout(\D[2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~53 .lut_mask = 16'hF511; -defparam \D[2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout -// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\D[2]~53_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_re~combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N17 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[2]~12_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N9 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .combout(\z80_|execute_|ctl_sw_1d~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_1d~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_1d~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Location: LCCOMB_X31_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & -// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~21_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(gnd), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; -defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( -// Equation(s): -// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|sw1_|db_down[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; -defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N2 -cycloneive_lcell_comb \D[6]~103 ( -// Equation(s): -// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~103 .lut_mask = 16'hEA4A; -defparam \D[6]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N30 -cycloneive_lcell_comb \D[6]~104 ( -// Equation(s): -// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~103_combout ), - .cin(gnd), - .combout(\D[6]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~104 .lut_mask = 16'hEE30; -defparam \D[6]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N14 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hBCB0; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N12 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\D[6]~100_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'h2D28; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N0 -cycloneive_lcell_comb \D[6]~102 ( -// Equation(s): -// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~100_combout ), - .datad(\D[6]~101_combout ), - .cin(gnd), - .combout(\D[6]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~102 .lut_mask = 16'hC3E0; -defparam \D[6]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N8 -cycloneive_lcell_comb \D[6]~127 ( -// Equation(s): -// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~104_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[6]~104_combout ), - .datad(\D[6]~102_combout ), - .cin(gnd), - .combout(\D[6]~127_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~127 .lut_mask = 16'hF4B0; -defparam \D[6]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N28 -cycloneive_lcell_comb \D[6]~99 ( -// Equation(s): -// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\raw_loader_in~input_o ), - .cin(gnd), - .combout(\D[6]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~99 .lut_mask = 16'hFFCF; -defparam \D[6]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N10 -cycloneive_lcell_comb \D[6]~114 ( -// Equation(s): -// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~114_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~114 .lut_mask = 16'hFB73; -defparam \D[6]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N12 -cycloneive_lcell_comb \D[6]~115 ( -// Equation(s): -// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~114_combout ), - .cin(gnd), - .combout(\D[6]~115_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~115 .lut_mask = 16'hF511; -defparam \D[6]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & -// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[6]~115_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N15 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[6]~9_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|interrupts_|iff1~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y12_N5 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y27_N8 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal2~3_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [5]))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\ula_|video_|vga_hc [7]), - .datad(\z80_|interrupts_|iff1~q ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y27_N9 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N25 -dffeas \z80_|interrupts_|DFFE_inst44 ( +// Location: FF_X29_Y18_N25 +dffeas \z80_|decode_state_|DFFE_instED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), + .q(\z80_|decode_state_|DFFE_instED~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N16 +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -43892,24 +8215,58 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N12 +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0044; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|decode_state_|in_halt~0_combout ), - .datab(\z80_|pla_decode_|Equal77~1_combout ), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N13 +// Location: FF_X31_Y12_N29 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -43928,407 +8285,30744 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N22 +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0505; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~3 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_sw_1d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0101; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'hC000; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hA0A0; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~0_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_state_iy_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N25 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal1~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|pla_decode_|Equal3~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hDFFF; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((!\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h707F; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~3 ( +// Equation(s): +// \z80_|execute_|ixy_d~3_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (\z80_|execute_|ixy_d~8_combout ) # ((\z80_|execute_|ixy_d~16_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ixy_d~11_combout & +// ((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~12_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hBBB0; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~2 ( +// Equation(s): +// \z80_|execute_|ixy_d~2_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~2 .lut_mask = 16'h0500; +defparam \z80_|execute_|ixy_d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~10_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q +// & \z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~19 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~19_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~19 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~8_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~8 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_bus_db_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~8_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7500; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~16_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_mWrite~10_combout ))) # (!\z80_|execute_|ctl_ir_we~16_combout & (((!\z80_|execute_|ctl_ir_we~15_combout ) # +// (!\z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|nM1_int~2_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal1~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|pla_decode_|Equal47~0_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~19_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h3700; defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal12~0_combout ))) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|fMRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMWrite~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_mRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) +// \z80_|execute_|ctl_reg_in_hi~9_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) .dataa(\z80_|execute_|ctl_mRead~12_combout ), .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_reg_in_hi~9_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|nextM~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_mRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|ir_|opcode [7]), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~15_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~18_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout & (((!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h0037; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (((!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h3070; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|pla_decode_|Equal44~0_combout ))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|fMRead~29_combout ), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( // Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), + .combout(\z80_|pla_decode_|Equal52~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) - - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~30_combout ), - .datac(\z80_|execute_|fMRead~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) +// \z80_|execute_|fMRead~20_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~11_combout )))) - .dataa(\z80_|execute_|fMRead~27_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|fMRead~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~16_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|fMRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), + .combout(\z80_|execute_|fMRead~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h20A0; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X31_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|pla_decode_|Equal11~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X31_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) +// \z80_|pla_decode_|Equal10~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ctl_mRead~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|pla_decode_|Equal10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|execute_|fMRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X35_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~16_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|fMRead~15_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N10 +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|fMRead~19_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_mWrite~11_combout ))) + + .dataa(\z80_|execute_|fMRead~19_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~2_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [3])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~2 .lut_mask = 16'h0003; +defparam \z80_|pla_decode_|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~32_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal34~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & \z80_|execute_|ctl_reg_in_hi~10_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .dataa(\z80_|execute_|ctl_mRead~22_combout ), .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~17_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'h8000; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|fMRead~22_combout ))) - .dataa(\z80_|execute_|fMRead~23_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2d~8_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), .datad(\z80_|execute_|fMRead~22_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N0 +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (!\z80_|execute_|ctl_sw_1d~3_combout & (!\z80_|execute_|ctl_im_we~combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~3_combout ), + .datac(\z80_|execute_|ctl_im_we~combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # (((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) # (!\z80_|execute_|ctl_bus_db_oe~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~3_combout = (\z80_|execute_|ctl_bus_zero_oe~2_combout ) # ((\z80_|decode_state_|in_halt~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~3 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_bus_zero_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|execute_|ctl_sw_1d~4_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'h000D; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [1] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[7]~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = ((!\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_flags_bus~8_combout & !\z80_|execute_|ctl_mRead~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hFF1F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal68~2_combout & !\z80_|pla_decode_|Equal20~0_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~10_combout & (\z80_|execute_|ctl_flags_bus~11_combout & \z80_|execute_|ctl_flags_bus~14_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~10_combout ), + .datac(\z80_|execute_|ctl_flags_bus~11_combout ), + .datad(\z80_|execute_|ctl_flags_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~16_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~17_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_mRead~24_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~17_combout & (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~28 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~28_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~28 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~28_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_inc_cy~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~16_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (\z80_|execute_|ctl_reg_out_lo~6_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout )) # +// (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~13_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~19_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~19 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_ir_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|ir_|opcode [7])) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~19_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|setM1~58_combout )) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_sw_2u~6_combout ) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|setM1~58_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout & (\z80_|execute_|ctl_reg_out_lo~2_combout & ((!\z80_|execute_|ctl_sw_2u~7_combout ) # (!\z80_|execute_|rsel0~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) # (!\z80_|execute_|ctl_sw_1d~4_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~4_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~29 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~3_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~4_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|rsel3~combout ) # ((!\z80_|execute_|ctl_reg_out_lo~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~3 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_reg_out_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~9_combout = (\z80_|execute_|ctl_sw_2u~7_combout & (\z80_|ir_|opcode [0] $ (((!\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1]))))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~9 .lut_mask = 16'h9500; +defparam \z80_|execute_|ctl_sw_2u~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|execute_|ctl_mWrite~18_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_out_hi~3_combout & (!\z80_|execute_|ctl_sw_2u~9_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .datac(\z80_|execute_|ctl_sw_2u~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) # (!\z80_|execute_|ctl_ir_we~19_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|execute_|ctl_ir_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~3_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h0888; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~14_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h30F0; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_alu_oe~10_combout & (\z80_|execute_|ctl_bus_db_we~6_combout & \z80_|execute_|ctl_reg_in_lo~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~10_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~8_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~8 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_sw_2u~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal69~0_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|pla_decode_|Equal20~0_combout & (\z80_|execute_|nextM~4_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0030; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~49_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|setM1~51_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h1050; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~9_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~9 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_sw_4d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~52_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h007F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout ) # ((\z80_|execute_|ctl_sw_2u~8_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~2_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~2 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_flags_alu~22_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # (\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~14_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & \z80_|execute_|ctl_reg_out_hi~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_use_sp~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (!\z80_|ir_|opcode [5] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~14_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAFAB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_sw_2u~3_combout & !\z80_|execute_|ctl_alu_shift_oe~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|setM1~19_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|setM1~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~8 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~8_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_cf_we~7_combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~8 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~15_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) +// # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~15 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_pf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~1_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_pf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & +// (((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_flags_pf_we~1_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_flags_alu~12_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_alu~17_combout )) # (!\z80_|execute_|ctl_flags_alu~23_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~12_combout ), + .datab(\z80_|execute_|ctl_flags_alu~23_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~5_combout )))) # (!\z80_|pla_decode_|Equal48~0_combout & +// (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFD; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_ir_we~13_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~16 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & +// (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_oe~16_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & \z80_|execute_|ctl_alu_core_S~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~16_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (\z80_|execute_|ctl_flags_pf_we~1_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~23_combout & (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~23_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~50_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~50 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal1~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~5_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~19_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = ((!\z80_|execute_|ixy_d~5_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2020; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~49_combout = ((\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~49 .lut_mask = 16'hD555; +defparam \z80_|execute_|ctl_alu_shift_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~49_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~51_combout = (\z80_|execute_|ctl_ir_we~11_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~51_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~14_combout & (\z80_|execute_|ctl_alu_shift_oe~51_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0EAA; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~48_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~14_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~48 .lut_mask = 16'hBAAA; +defparam \z80_|execute_|ctl_alu_shift_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & !\z80_|execute_|ctl_reg_gp_sel~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (((\z80_|execute_|ctl_alu_shift_oe~48_combout & !\z80_|execute_|ctl_alu_bs_oe~8_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (\z80_|execute_|ctl_alu_shift_oe~35_combout & (\z80_|execute_|ctl_alu_shift_oe~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ))) # (!\z80_|execute_|ixy_d~5_combout & +// (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = ((\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~24_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_ir_we~11_combout & +// (((\z80_|execute_|ctl_ir_we~14_combout & \z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~36_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~18_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'hF400; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~47_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~26_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (\z80_|execute_|ctl_mWrite~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & \z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (\z80_|execute_|ctl_alu_shift_oe~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_alu_bs_oe~combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|alu_|db_high[3]~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~17_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_alu_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_oe~5_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_alu_oe~8_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_66_oe~4_combout ) # (\z80_|execute_|ctl_alu_oe~13_combout ))) # (!\z80_|execute_|ctl_alu_oe~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~12_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # (((!\z80_|execute_|ctl_flags_alu~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|nextM~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (((\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~17_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~11_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0F07; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~10_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hDCFC; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = (\z80_|execute_|ctl_sw_2d~12_combout ) # (((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout )) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_sw_2d~12_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~15_combout ) # ((\z80_|execute_|ctl_reg_out_hi~5_combout ) # (\z80_|execute_|ctl_sw_2d~13_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~22_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal37~0_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|fMRead~10_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h1F00; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|fMRead~11_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~9_combout )) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~9_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~27_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~27 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_sel_wz~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal47~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'hAA00; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_in_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h2323; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & ((\z80_|execute_|ctl_reg_sel_wz~16_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'hAF03; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~22_combout = (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal5~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal5~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~3_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal2~3_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal5~2 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (((\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal5~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h0233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_mRead~9_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~4_combout & (\z80_|execute_|ctl_inc_dec~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_sw_1d~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|execute_|ctl_sw_4d~5_combout & (\z80_|execute_|ctl_reg_sel_wz~22_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h3F2A; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_al_we~7_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (!\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout & (!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~3_combout = (!\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~3 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_al_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (!\z80_|execute_|ctl_mRead~4_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'h4555; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )) # (!\z80_|execute_|ctl_al_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~3_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout ))) # (!\z80_|pla_decode_|Equal77~0_combout ) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & !\z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout )) # (!\z80_|execute_|ctl_alu_oe~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_ir_we~18_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (!\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0300; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & \z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~17_combout & (!\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~2_combout = (!\z80_|execute_|ctl_mRead~3_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # ((!\z80_|execute_|ctl_al_we~2_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = ((\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_al_we~4_combout ) # (\z80_|execute_|ctl_al_we~6_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~8_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout ))) # (!\z80_|execute_|setM1~55_combout ) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~9_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N25 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~0_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h0F0D; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & \z80_|pla_decode_|Equal52~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~8_combout ) # (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_reg_gp_sel~13_combout )) # (!\z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~9 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~9 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_pf_sel[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_flags_pf_we~2_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[2] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [2] = (\z80_|bus_control_|db[2]~14_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[2]~14_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h80FF; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal21~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~2_combout = ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # (\z80_|execute_|ctl_alu_op1_oe~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~2 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_alu_op1_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_ir_we~15_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h5400; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|execute_|ctl_alu_op_low~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~4_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~18_combout & ((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~13_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~11_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~36_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[3]~5_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_low[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFEE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N17 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N25 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFCA0; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # ((\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~7_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (((\z80_|execute_|ctl_alu_op_low~17_combout ) # (!\z80_|execute_|ctl_state_alu~7_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'h5FDF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout ) # (((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h00C0; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ixy_d~3_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal21~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88C0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|db_low[3]~5_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h5540; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N5 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( +// Equation(s): +// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [3])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hF351; +defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( +// Equation(s): +// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_low[3]~3_combout ), + .datad(\z80_|alu_|result_lo [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hF0A0; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_out_lo~9_combout & (\z80_|execute_|ctl_inc_cy~29_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~35_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~24_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~24 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_sel_wz~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout = (\z80_|execute_|ctl_mRead~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~25_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~24_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~25 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_sw_4u~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ctl_inc_cy~80_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~80_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout & (\z80_|execute_|ctl_inc_cy~79_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout & \z80_|execute_|ctl_inc_cy~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal4~0_combout & \z80_|sequencer_|DFFE_T5_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_inc_cy~72_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_inc_cy~72_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|execute_|ctl_inc_cy~44_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~73_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|ctl_inc_cy~44_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_bus_inc_oe~36_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (!\z80_|execute_|ctl_sw_4u~2_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~17_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~25_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~16_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'hF4F4; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (\z80_|execute_|ctl_reg_sel_pc~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ixy_d~16_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~22_combout = (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~22 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_pc~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_reg_sel_pc~8_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~22_combout & \z80_|execute_|ctl_reg_sel_pc~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sel_pc~11_combout & (\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & \z80_|execute_|ctl_inc_cy~35_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal21~1_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h0303; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0011; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|ixy_d~8_combout & (!\z80_|pla_decode_|Equal33~2_combout & ((!\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0105; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|pc_inc_hold~16_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~20_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_reg_sel_pc~16_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~20 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_bus_inc_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~21_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|ctl_bus_inc_oe~20_combout & !\z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~21 .lut_mask = 16'h0A8A; +defparam \z80_|execute_|ctl_bus_inc_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hF0C0; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~18_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEC00; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~19_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~19 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_bus_inc_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~19_combout & \z80_|execute_|ixy_d~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~4_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~20_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) # (!\z80_|execute_|ctl_reg_in_hi~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~11_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|ctl_reg_sel_pc~13_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (\z80_|execute_|setM1~55_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~16_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~6_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|ctl_reg_sys_hilo~6_combout ) # ((!\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3310; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal35~0_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'h0055; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~8_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # ((!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_inc_dec~3_combout & +// (!\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'h8ACF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h5100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~17_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h3B00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((\z80_|execute_|ctl_al_we~3_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h00A2; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_pc~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|execute_|ctl_reg_sel_wz~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~30_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~30 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_reg_sel_wz~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (!\z80_|execute_|ctl_reg_sel_wz~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (((!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout )) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFAFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~7_combout )) # (!\z80_|execute_|setM1~48_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_al_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~8_combout = ((\z80_|execute_|ctl_sw_4d~2_combout ) # ((\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_state_alu~3_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~8 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hBF00; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = (\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'h8C8C; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = (!\z80_|execute_|ctl_mWrite~8_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'h3233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~17_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~19_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~17 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_bus_inc_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~18_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_bus_inc_oe~38_combout & \z80_|execute_|ctl_bus_inc_oe~17_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~25_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~26_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~18_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~27_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = ((\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~36_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~22_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~22 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~23_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~23 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~73_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_inc_cy~44_combout & \z80_|execute_|ctl_inc_cy~74_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~24_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_bus_inc_oe~32_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~3_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # (\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [11]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = ((\z80_|reg_file_|db_hi_as[3]~9_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = (\z80_|execute_|ctl_alu_oe~17_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~2_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|pla_decode_|Equal25~0_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h00BF; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~17_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~17 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (!\z80_|pla_decode_|Equal49~0_combout & (!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|execute_|ctl_mRead~11_combout )) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_sw_1d~7_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & \z80_|execute_|ctl_reg_gp_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mRead~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~14_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (!\z80_|execute_|ctl_66_oe~4_combout & !\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~14 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_in_hi~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~15_combout = ((\z80_|execute_|ctl_reg_in_hi~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~15 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_in_hi~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )))) # (!\z80_|execute_|setM1~32_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ctl_al_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8FAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~7_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h3F2F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & ((\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|comb~1_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|comb~1_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~4_combout )) # +// (!\z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|execute_|fMRead~9_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~11_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ))) + + .dataa(\z80_|execute_|fMRead~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|fMRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|setM1~58_combout & \z80_|execute_|ctl_sw_2u~3_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|setM1~58_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (!\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'h00BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = (((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) # (!\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~3_combout = (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal1~2_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~3_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~4_combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~4 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & \z80_|execute_|ctl_sw_2u~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h000E; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~43_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~27_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .lut_mask = 16'h8DCD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~28_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_reg_gp_sel[1]~27_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_reg_use_sp~2_combout & \z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datad(\z80_|execute_|nextM~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~43_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~28_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & \z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~41_combout = (\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h8F88; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # (\z80_|pla_decode_|Equal5~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal5~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ))) # (!\z80_|execute_|ctl_alu_op_low~16_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|ir_|opcode [5]))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~38_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|execute_|ctl_mRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~39_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout )) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~37_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .lut_mask = 16'h08AA; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~40_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~37_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h5455; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hD800; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~6_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N11 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hE400; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0A0A; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_in_hi~6_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~23_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~20_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~23 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~29_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~21_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~29 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_sel_wz~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~26_combout = (\z80_|execute_|ctl_reg_sel_wz~23_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~25_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~22_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~26 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & !\z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0008; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFEFC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~15_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|gdfx_temp1[3]~31_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hA0A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~33_combout & (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~37_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'hC040; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~10_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & ((\z80_|alu_|db_low[3]~5_combout ) # ((!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_|db_low[3]~5_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~16_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (!\z80_|execute_|fMRead~27_combout ))) # (!\z80_|execute_|ctl_flags_bus~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~13_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~7_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout & +// (\z80_|alu_|db_low[3]~5_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N13 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~32 ( +// Equation(s): +// \z80_|alu_control_|db[3]~32_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (!\z80_|execute_|ctl_66_oe~combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~32 .lut_mask = 16'h1101; +defparam \z80_|alu_control_|db[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|db[3]~32_combout & ((\z80_|bus_control_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|alu_control_|db[3]~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hD0D0; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~18_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|pc_inc_hold~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mWrite~10_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0800; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ixy_d~16_combout ) # (\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hECA8; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~3_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hEAFA; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~20_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~21_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'h777F; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hABFF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (\z80_|execute_|pc_inc_hold~37_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|pc_inc_hold~37_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~27_combout & \z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout ))) # (!\z80_|execute_|ctl_inc_cy~78_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~64_combout & \z80_|execute_|ctl_inc_cy~65_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_mWrite~18_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~3_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = ((\z80_|execute_|ctl_inc_dec~6_combout ) # ((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~0_combout ))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'hDDFD; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_alu_oe~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~32_combout & \z80_|execute_|pc_inc_hold~28_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_inc_cy~69_combout & ((!\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~36_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~67_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFF2A; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (((!\z80_|execute_|ctl_inc_cy~33_combout ) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~28_combout )) # (!\z80_|execute_|ctl_inc_cy~29_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~29_combout ), + .datab(\z80_|execute_|ctl_inc_cy~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~36_combout ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((\z80_|execute_|ctl_inc_cy~71_combout ) # (!\z80_|execute_|ctl_inc_cy~74_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~32_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~75_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hEFCC; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (!\z80_|execute_|ctl_inc_cy~81_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|pc_inc_hold~38_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0A08; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & +// (\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_inc_cy~79_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_inc_cy~42_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~42_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~44_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~30_combout = ((!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~8_combout ))) # (!\z80_|execute_|ctl_mWrite~18_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & (!\z80_|execute_|pc_inc_hold~29_combout +// & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|ctl_inc_cy~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hB0BB; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (!\z80_|execute_|ctl_inc_cy~34_combout & (((\z80_|execute_|pc_inc_hold~19_combout & !\z80_|execute_|pc_inc_hold~23_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0545; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~48_combout ) # ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # (\z80_|execute_|ctl_inc_cy~47_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~48_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~46_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & (!\z80_|execute_|pc_inc_hold~20_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|execute_|ctl_inc_cy~60_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~20_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_mRead~34_combout & +// \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~9_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (!\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|execute_|ctl_inc_cy~56_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_inc_cy~57_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~57_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~20_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~21_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~8_combout & !\z80_|execute_|pc_inc_hold~20_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h888C; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|execute_|pc_inc_hold~31_combout & \z80_|execute_|ctl_mRead~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~31_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((\z80_|execute_|ctl_inc_cy~58_combout ) # (\z80_|execute_|ctl_inc_cy~53_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|ctl_inc_cy~61_combout ), + .datac(\z80_|execute_|ctl_inc_cy~58_combout ), + .datad(\z80_|execute_|ctl_inc_cy~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~77_combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # ((!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hC4F5; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((!\z80_|execute_|pc_inc_hold~30_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~27_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~30_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~78_combout & \z80_|execute_|pc_inc_hold~28_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((\z80_|execute_|ctl_inc_cy~39_combout ) # (\z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_inc_cy~62_combout ), + .datac(\z80_|execute_|ctl_inc_cy~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_inc_cy~76_combout ) # +// (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~66_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hCCC8; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|address_latch_|Q[3]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[3]~feeder_combout = \z80_|address_latch_|abusz [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = ((\z80_|execute_|ctl_inc_dec~7_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout = (\z80_|execute_|setM1~51_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|execute_|setM1~51_combout & (((\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout +// & \z80_|execute_|rsel0~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mWrite~18_combout ) # (\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hF4F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h006A; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ctl_mRead~23_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_ir_we~18_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~18_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|pla_decode_|Equal25~0_combout & (!\z80_|pla_decode_|Equal12~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (((\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h00C8; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_mRead~3_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~21_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'h8888; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[2]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~40_combout & (\z80_|reg_file_|gdfx_temp0[2]~36_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~38_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~41_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~43_combout = ((\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[2]~43_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~33_combout ) # ((\z80_|execute_|ctl_sw_4d~8_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_sw_4d~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|gdfx_temp0[1]~27_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~26_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~31_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~33_combout = ((\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[1]~33_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datac(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ +// (\z80_|address_latch_|Q [1]))))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N13 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [2]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [1]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h6666; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~13_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[3]~63_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~14_combout = (\z80_|reg_file_|db_lo_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~14 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~15_combout = ((\z80_|reg_file_|db_lo_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~15 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~57_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~35_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~58_combout = (\z80_|reg_file_|gdfx_temp0[3]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~59_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~61_combout = (\z80_|reg_file_|gdfx_temp0[3]~58_combout & (\z80_|reg_file_|gdfx_temp0[3]~60_combout & (\z80_|reg_file_|gdfx_temp0[3]~59_combout & \z80_|reg_file_|gdfx_temp0[3]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~62_combout = (\z80_|reg_file_|gdfx_temp0[3]~55_combout & (\z80_|reg_file_|gdfx_temp0[3]~61_combout & \z80_|reg_file_|gdfx_temp0[3]~54_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~63_combout = ((\z80_|reg_file_|gdfx_temp0[3]~62_combout & ((\z80_|reg_file_|db_lo_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & ((\z80_|reg_file_|gdfx_temp0[3]~63_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8A8A; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hB3BB; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[3]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~16_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~16_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~8_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~4_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|alu_control_|db[1]~22_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = (\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N31 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [3]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~67_combout = (\z80_|reg_file_|gdfx_temp0[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~65_combout = (\z80_|reg_file_|gdfx_temp0[4]~64_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~70_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~71_combout = (\z80_|reg_file_|gdfx_temp0[4]~70_combout & (\z80_|reg_file_|gdfx_temp0[4]~69_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .lut_mask = 16'h8A00; +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~72_combout = (\z80_|reg_file_|gdfx_temp0[4]~68_combout & (\z80_|reg_file_|gdfx_temp0[4]~67_combout & (\z80_|reg_file_|gdfx_temp0[4]~65_combout & \z80_|reg_file_|gdfx_temp0[4]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~73_combout = ((\z80_|reg_file_|gdfx_temp0[4]~72_combout & ((\z80_|reg_file_|db_lo_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~16_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~17_combout = (\z80_|reg_file_|db_lo_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~17 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~18_combout = ((\z80_|reg_file_|db_lo_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~18 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N15 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~49_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_high[2]~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N3 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = ((!\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|db_low[1]~15_combout & (\z80_|alu_|db_low[1]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hB030; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|execute_|ctl_alu_core_S~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|ir_|opcode [4]) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|execute_|ctl_alu_op_low~33_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~9_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|pla_decode_|Equal73~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (\z80_|execute_|ctl_state_alu~11_combout & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|execute_|ctl_state_alu~11_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'hCC40; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal73~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hA080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~20 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~20_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~20 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~20_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h0515; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|execute_|ctl_flags_cf_cpl~0_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & !\z80_|execute_|ctl_flags_cf_cpl~1_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[0]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h3336; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDD5D; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~25_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|gdfx_temp0[0]~17_combout & \z80_|reg_file_|gdfx_temp0[0]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~23_combout = ((\z80_|reg_file_|gdfx_temp0[0]~18_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[0]~4_combout = (\z80_|reg_file_|gdfx_temp0[0]~23_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[0]~4 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~23 ( +// Equation(s): +// \z80_|alu_control_|db[0]~23_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~8_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~18_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~23 .lut_mask = 16'hF500; +defparam \z80_|alu_control_|db[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[0]~12_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~24 ( +// Equation(s): +// \z80_|alu_control_|db[0]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_cf~combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0])) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~24 .lut_mask = 16'hF531; +defparam \z80_|alu_control_|db[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~25 ( +// Equation(s): +// \z80_|alu_control_|db[0]~25_combout = ((\z80_|reg_file_|db_lo_ds[0]~4_combout & (\z80_|alu_control_|db[0]~23_combout & \z80_|alu_control_|db[0]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .datab(\z80_|alu_control_|db[0]~23_combout ), + .datac(\z80_|alu_control_|db[0]~24_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~25 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_control_|db[0]~25_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # +// (!\z80_|alu_control_|db[0]~25_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[0]~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )) # (!\z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout = (\z80_|execute_|ixy_d~14_combout & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~0_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ) # ((\z80_|execute_|ctl_flags_cf2_we~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~9_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|ir_|opcode [6] & (\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout & !\z80_|ir_|opcode [7]))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'hFFE0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [7] & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[7]~20_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|alu_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~81_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~82_combout = (\z80_|reg_file_|gdfx_temp1[7]~79_combout & (\z80_|reg_file_|gdfx_temp1[7]~80_combout & (\z80_|reg_file_|gdfx_temp1[7]~81_combout & \z80_|reg_file_|gdfx_temp1[7]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~83_combout = (\z80_|reg_file_|gdfx_temp1[7]~77_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout & (\z80_|reg_file_|gdfx_temp1[7]~82_combout & \z80_|reg_file_|gdfx_temp1[7]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~23 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~24_combout = (\z80_|reg_file_|db_hi_as[7]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~24 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_hi_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~25_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [14]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~25 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~25_combout = ((\z80_|reg_file_|db_hi_as[7]~24_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~25 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~84_combout = ((\z80_|reg_file_|gdfx_temp1[7]~83_combout & ((\z80_|reg_file_|db_hi_as[7]~25_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & ((\z80_|alu_control_|db[7]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|alu_control_|db[7]~15_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~19_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # +// (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h5432; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hFE04; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8030; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_flags_alu~20_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hF2F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_core_S~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (((!\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # (((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBBB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout & +// \z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & !\z80_|pla_decode_|Equal71~2_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h2F3F; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|execute_|ctl_flags_nf_we~2_combout ) # ((!\z80_|execute_|ctl_flags_nf_we~1_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hEEEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_control_|db[1]~22_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~18_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h10F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0E0E; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h7773; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((\z80_|pla_decode_|Equal68~2_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hCC08; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal71~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~8_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal21~1_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout )))) # +// (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (((\z80_|execute_|ctl_alu_op_low~30_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((\z80_|execute_|ctl_alu_core_hf~21_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ixy_d~5_combout & ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_core_hf~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0302; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mWrite~10_combout & !\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hCC0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout ))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((!\z80_|execute_|ctl_alu_op_low~21_combout & \z80_|execute_|ctl_alu_core_hf~32_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((!\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_core_hf~40_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(gnd), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hF0CC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[0]~25_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N19 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N7 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hC0A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0E0A; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~34_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hB2E8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|pla_decode_|Equal71~2_combout ) # (\z80_|execute_|ctl_alu_core_S~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal71~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hAAAF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~17_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[1]~17_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N29 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|alu_|op2_high [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~1_combout & \z80_|alu_|alu_op1[1]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op1[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op2[1]~1_combout )))) # (!\z80_|alu_|alu_op1[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[1]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hCE8C; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'h0088; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|alu_|db[4]~10_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[4]~10_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~60_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & \z80_|reg_file_|gdfx_temp1[4]~61_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout & \z80_|reg_file_|gdfx_temp1[4]~58_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~19_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[4]~66_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = (\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~19_combout = ((\z80_|reg_file_|db_hi_as[4]~18_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~19 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~19_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout = \z80_|address_latch_|Q [12] $ ((((\z80_|execute_|ctl_inc_dec~11_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .lut_mask = 16'h02FD; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~16_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N5 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout = \z80_|address_latch_|Q [11] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # ((\z80_|execute_|ctl_inc_dec~11_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .lut_mask = 16'h1E0F; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = (\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~16_combout = ((\z80_|reg_file_|db_hi_as[5]~15_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~16 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~52_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~53_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout ) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout & \z80_|reg_file_|gdfx_temp1[5]~50_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~16_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// (((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_control_|db[5]~12_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[5]~23_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[1]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[5]~24_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~16_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[1]~16_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[1]~17_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N5 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA280; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h5051; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|pla_decode_|Equal71~2_combout ) # ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) # +// (!\z80_|execute_|ctl_alu_core_S~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal71~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'h45C7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .lut_mask = 16'hFF88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N27 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hC088; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~11_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[2]~11_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N11 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( +// Equation(s): +// \z80_|alu_|db_low[2]~6_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [2])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( +// Equation(s): +// \z80_|alu_|db_low[2]~7_combout = (\z80_|alu_|db_low[2]~6_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[2]~6_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( +// Equation(s): +// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'hFA00; +defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~16_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|gdfx_temp1[2]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = (\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~13_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N9 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (\z80_|address_latch_|Q [7] & !\z80_|execute_|ctl_inc_dec~10_combout +// )) # (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [7] & \z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1080; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~13_combout = ((\z80_|reg_file_|db_hi_as[2]~12_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~13 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~43_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~44_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout & (\z80_|reg_file_|gdfx_temp1[2]~41_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & \z80_|reg_file_|gdfx_temp1[2]~46_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~13_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~11_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[2]~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[2]~9_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|alu_|db_low[2]~9_combout ), + .datac(gnd), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hDD88; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = ((\z80_|alu_|db_low[2]~8_combout & ((\z80_|alu_|db_low[2]~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~8_combout ), + .datad(\z80_|alu_|db_low[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hF373; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[2]~13_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N27 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|alu_|op1_high [0]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~12_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|alu_control_|db[5]~12_combout +// & (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[5]~12_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~8 ( +// Equation(s): +// \z80_|alu_control_|db[5]~8_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|flags_yf~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~8 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[5]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[5]~0_combout = (\z80_|reg_file_|gdfx_temp0[5]~53_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[5]~0 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~9 ( +// Equation(s): +// \z80_|alu_control_|db[5]~9_combout = (\z80_|alu_control_|db[5]~8_combout & (\z80_|reg_file_|db_lo_ds[5]~0_combout & ((\z80_|bus_control_|db[5]~16_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|alu_control_|db[5]~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~9 .lut_mask = 16'hD000; +defparam \z80_|alu_control_|db[5]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~12 ( +// Equation(s): +// \z80_|alu_control_|db[5]~12_combout = ((\z80_|alu_control_|db[5]~9_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[5]~9_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~12 .lut_mask = 16'hBB3B; +defparam \z80_|alu_control_|db[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~47_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~48_combout = (\z80_|reg_file_|gdfx_temp0[5]~47_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~51_combout = (\z80_|reg_file_|gdfx_temp0[5]~49_combout & (\z80_|reg_file_|gdfx_temp0[5]~48_combout & (\z80_|reg_file_|gdfx_temp0[5]~50_combout & \z80_|reg_file_|gdfx_temp0[5]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~52_combout = (\z80_|reg_file_|gdfx_temp0[5]~44_combout & (\z80_|reg_file_|gdfx_temp0[5]~51_combout & \z80_|reg_file_|gdfx_temp0[5]~45_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~53_combout = ((\z80_|reg_file_|gdfx_temp0[5]~52_combout & ((\z80_|reg_file_|db_lo_as[5]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~10_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[5]~53_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~11_combout = (\z80_|reg_file_|db_lo_as[5]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~11 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~12_combout = ((\z80_|reg_file_|db_lo_as[5]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~12 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h6555; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~26_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[6]~82_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3393; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N9 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0DD0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~89_combout & (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[7]~92_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [7]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h9A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~7_combout = ((\z80_|reg_file_|db_hi_as[0]~6_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~7 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [0] & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[0]~18_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datac(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'hD000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~7_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datac(\z80_|alu_control_|db[0]~25_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[1]~12_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[1]~16_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hBBF3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = ((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hAF0F; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[1]~15_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hC4FF; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [5] & ((\z80_|alu_|db[0]~18_combout ))))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout +// & (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'h8E82; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'h08A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~3 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout & !\z80_|ir_|opcode [4])) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .lut_mask = 16'hFF0C; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[0]~18_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[0]~18_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h396C; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h555F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_|alu_op2[0]~3_combout )))) +// # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|alu_op2[0]~3_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|alu_op1[0]~1_combout ), + .datac(\z80_|alu_|alu_op2[0]~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hFE80; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N9 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = ((!\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|alu_|op1_low [0] & (((\z80_|alu_|op2_low [0])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [0] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|alu_|db_low[0]~20_combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|result_lo [0]), + .datac(\z80_|alu_|db_low[0]~20_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hE000; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((\z80_|alu_|db_low[0]~19_combout & \z80_|alu_|db_low[0]~22_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hCF0F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N27 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[0]~20_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[4]~10_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[0]~20_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hF7B3; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'h0022; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~22_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[0]~22_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|alu_control_|db[4]~31_combout & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|alu_control_|db[4]~31_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db[4]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( +// Equation(s): +// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( +// Equation(s): +// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db_low[3]~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hF5DD; +defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|alu_|db_low[3]~4_combout & \z80_|alu_|db_low[3]~1_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|alu_|db_low[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hF333; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[3]~7_combout & (\z80_|alu_|db_low[3]~5_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N25 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h27D8; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [3]))))) # +// (!\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|alu_|op1_low [3])) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hCCE4; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFC0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF3F2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~31_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~31_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFCB8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( +// Equation(s): +// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~26 ( +// Equation(s): +// \z80_|alu_control_|db[2]~26_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~26 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~5_combout = (\z80_|reg_file_|gdfx_temp0[2]~43_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~5 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_control_|db[2]~26_combout & (\z80_|reg_file_|db_lo_ds[2]~5_combout & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[2]~26_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = ((\z80_|alu_control_|db[2]~27_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~8_combout & (((\z80_|alu_control_|db[2]~28_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|execute_|ctl_flags_pf_we~8_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hE444; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h0770; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & (!\z80_|pla_decode_|Equal62~3_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h0CFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [6]))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|Q [6]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & (\z80_|address_latch_|Q [0] & !\z80_|address_latch_|Q [3]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0010; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [10] & !\z80_|address_latch_|Q [9]))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|Q [9]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [14] & !\z80_|address_latch_|Q [12]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~7_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~7_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE4F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80A2; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h80B0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|alu_|alu_parity_out~0_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h555A; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_pf_we~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hEAAA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h7F00; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hFCFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[1]~19_combout & !\z80_|alu_|db_high[2]~13_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~18_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hCC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~5_combout & (!\z80_|alu_|db_low[2]~11_combout & (!\z80_|alu_|db_low[1]~17_combout & !\z80_|alu_|db_low[0]~23_combout ))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|alu_|db_low[2]~11_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .lut_mask = 16'hF8F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hDF00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & (((\z80_|alu_control_|sel[1]~0_combout ) # (\z80_|alu_flags_|flags_cf~combout )))) # (!\z80_|ir_|opcode [4] & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAEA4; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~28_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|pla_decode_|Equal5~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = (\z80_|execute_|ctl_reg_sel_wz~16_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h3FBF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_bus_inc_oe~19_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~23_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~23 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sel_pc~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (!\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hCCDF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~21_combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~21 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_sel_pc~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~28_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_reg_sel_pc~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [1] & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~2_combout = (\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datad(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~2 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~4_combout = ((\z80_|reg_file_|db_hi_as[1]~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~4 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~10_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~10_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [14]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = (\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = ((\z80_|reg_file_|db_hi_as[6]~21_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~71_combout & \z80_|reg_file_|gdfx_temp1[6]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|gdfx_temp1[6]~68_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~22_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|alu_control_|db[6]~18_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[6]~21_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|alu_|op2_high [2] & (((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~11_combout & (((\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'h8C0C; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|execute_|ctl_alu_res_oe~2_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hFFF8; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~12_combout & \z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[2]~11_combout ))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0415; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hF0FB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # +// (\z80_|alu_|alu_op1[3]~2_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFD40; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [3]) +// # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hEF2F; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[3]~5_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFD55; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_control_|db[7]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & \z80_|alu_|db_high[3]~7_combout )))) # (!\z80_|alu_control_|db[7]~15_combout & +// (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_control_|db[7]~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~13 ( +// Equation(s): +// \z80_|alu_control_|db[7]~13_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~13 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_out_lo~3_combout & !\z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF08; +defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~14 ( +// Equation(s): +// \z80_|alu_control_|db[7]~14_combout = (\z80_|alu_control_|db[7]~13_combout & (\z80_|reg_file_|db_lo_ds[7]~1_combout & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[7]~13_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~14 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~15 ( +// Equation(s): +// \z80_|alu_control_|db[7]~15_combout = ((\z80_|alu_control_|db[7]~14_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[7]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~15 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~4 ( +// Equation(s): +// \z80_|bus_control_|db[7]~4_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~4 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~2_combout & \z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|fMRead~27_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~27_combout ), + .datac(\z80_|execute_|ixy_d~2_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|fMRead~36_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - .dataa(\z80_|execute_|fMRead~35_combout ), - .datab(\z80_|execute_|fMRead~34_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'h0A08; defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N30 +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~16 ( +// Equation(s): +// \z80_|execute_|nextM~16_combout = (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|nextM~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|nextM~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~20_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~20 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~20_combout & (((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) # (!\z80_|execute_|ctl_ir_we~20_combout & (\z80_|execute_|ctl_ir_we~19_combout & ((\z80_|ir_|opcode [7])))) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|execute_|ctl_ir_we~20_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~38 ( +// Equation(s): +// \z80_|execute_|fMRead~38_combout = (\z80_|execute_|fMRead~29_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|fMRead~30_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~38 .lut_mask = 16'hECCC; +defparam \z80_|execute_|fMRead~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = ((\z80_|execute_|fMRead~37_combout ) # ((\z80_|execute_|fMRead~38_combout ) # (!\z80_|execute_|nextM~16_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~37_combout ), + .datac(\z80_|execute_|nextM~16_combout ), + .datad(\z80_|execute_|fMRead~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~36_combout ) # (\z80_|execute_|fMRead~31_combout ))) # (!\z80_|execute_|fMRead~8_combout ) + + .dataa(\z80_|execute_|fMRead~8_combout ), + .datab(\z80_|execute_|fMRead~28_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|fMRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (!\z80_|execute_|fMWrite~0_combout & ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|fMRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ixy_d~16_combout )) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|fMRead~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|fMRead~13_combout ))) + + .dataa(\z80_|execute_|fMRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|fMRead~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~14_combout ) # ((\z80_|execute_|fMRead~17_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|fMRead~18_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) # (!\z80_|execute_|fMRead~22_combout ) + + .dataa(\z80_|execute_|fMRead~22_combout ), + .datab(\z80_|execute_|fMRead~18_combout ), + .datac(\z80_|execute_|ctl_sw_4d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|execute_|ctl_mRead~15_combout & +// ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~25_combout ) # (((!\z80_|execute_|pc_inc_hold~17_combout & \z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|fMRead~25_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|fMWrite~2_combout ) + + .dataa(\z80_|execute_|fMWrite~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|ctl_reg_sys_hilo~6_combout ))) + + .dataa(\z80_|execute_|fMRead~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|fMRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~35_combout )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), @@ -44338,1712 +39032,1971 @@ defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~6_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~2_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|execute_|ixy_d~2_combout ), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hF500; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) +// \z80_|execute_|ctl_iorw~12_combout = ((\z80_|ir_|opcode [7]) # ((!\z80_|ir_|opcode [6]) # (!\z80_|decode_state_|DFFE_instED~q ))) # (!\z80_|pla_decode_|Equal1~0_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .combout(\z80_|execute_|ctl_iorw~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~2_combout ) # ((!\z80_|execute_|ctl_iorw~12_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (!\z80_|execute_|ctl_iorw~12_combout & ((\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .combout(\z80_|execute_|ctl_iorw~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( // Equation(s): -// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~16_combout ) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .dataa(\z80_|execute_|nextM~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_iorw~8_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .combout(\z80_|execute_|ctl_iorw~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; -defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[4][3] ( +// Location: FF_X30_Y18_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N12 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\ula_|zx_keyboard_|keys[5][3]~q ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][3]~q ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hA2F3; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & -// !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; -defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; -defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & -// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N23 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N25 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N20 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[3][3]~q ), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'h8ACF; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; -defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; -defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & -// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N5 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N30 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hCF45; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N8 -cycloneive_lcell_comb \D[3]~72 ( -// Equation(s): -// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][3]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][3]~q ), - .cin(gnd), - .combout(\D[3]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'hA2F3; -defparam \D[3]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) - - .dataa(\D[3]~74_combout ), - .datab(\D[3]~73_combout ), - .datac(\D[3]~75_combout ), - .datad(\D[3]~72_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'h8000; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N2 -cycloneive_lcell_comb \D[3]~122 ( -// Equation(s): -// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[3]~76_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[3]~122_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~122 .lut_mask = 16'hEF00; -defparam \D[3]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N28 -cycloneive_lcell_comb \D[3]~79 ( -// Equation(s): -// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~79 .lut_mask = 16'h3332; -defparam \D[3]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N20 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # -// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hF5E4; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N22 -cycloneive_lcell_comb \D[3]~80 ( -// Equation(s): -// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) - - .dataa(gnd), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~80 .lut_mask = 16'hCFC0; -defparam \D[3]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N4 -cycloneive_lcell_comb \D[3]~81 ( -// Equation(s): -// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout -// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\D[3]~80_combout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~81 .lut_mask = 16'hF0DD; -defparam \D[3]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N30 -cycloneive_lcell_comb \D[3]~124 ( -// Equation(s): -// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~124_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~124 .lut_mask = 16'hF200; -defparam \D[3]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N0 -cycloneive_lcell_comb \D[3]~123 ( -// Equation(s): -// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~123_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~123 .lut_mask = 16'hF2D0; -defparam \D[3]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N10 -cycloneive_lcell_comb \D[3]~78 ( -// Equation(s): -// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - - .dataa(\Equal2~0_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[3]~124_combout ), - .datad(\D[3]~123_combout ), - .cin(gnd), - .combout(\D[3]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~78 .lut_mask = 16'h5410; -defparam \D[3]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N6 -cycloneive_lcell_comb \D[3]~82 ( -// Equation(s): -// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[3]~79_combout ), - .datac(\D[3]~81_combout ), - .datad(\D[3]~78_combout ), - .cin(gnd), - .combout(\D[3]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~82 .lut_mask = 16'hD580; -defparam \D[3]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N26 -cycloneive_lcell_comb \D[3]~108 ( -// Equation(s): -// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[3]~122_combout ), - .datac(gnd), - .datad(\D[3]~82_combout ), - .cin(gnd), - .combout(\D[3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hFFDD; -defparam \D[3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N8 -cycloneive_lcell_comb \D[3]~109 ( -// Equation(s): -// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(\D[3]~108_combout ), - .datad(\Equal2~1_combout ), - .cin(gnd), - .combout(\D[3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~109 .lut_mask = 16'hD0D5; -defparam \D[3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[3]~109_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N5 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|alu_control_|db[3]~36_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|execute_|ctl_iorw~9_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y8_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X30_Y18_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y1_N0 +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N27 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y18_N15 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(\z80_|memory_ifc_|wait_iorq~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~13_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout & (\z80_|execute_|ctl_mWrite~14_combout & (\z80_|execute_|ctl_mWrite~12_combout & \z80_|execute_|ctl_bus_db_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = (!\z80_|execute_|ixy_d~8_combout & !\z80_|pla_decode_|Equal33~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h0303; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = ((\z80_|execute_|ctl_mWrite~16_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~15_combout ))) # (!\z80_|execute_|ctl_mWrite~15_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y15_N21 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N3 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(gnd), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|mwr_wr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFFA0; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFF0; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # ((\z80_|sequencer_|M5~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # +// (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_mWrite~8_combout & !\z80_|execute_|ctl_mRead~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0055; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~0_combout ) # ((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|fMWrite~1_combout )))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h2322; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & ((\z80_|execute_|fMWrite~2_combout ) # (!\z80_|execute_|fMWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hA200; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~6_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((\z80_|execute_|ixy_d~2_combout ) # ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~2_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h8CCC; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_alu_oe~4_combout ) # ((\z80_|execute_|ctl_reg_in_hi~6_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|pla_decode_|Equal9~1_combout & +// ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|pla_decode_|Equal3~2_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h10F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h070F; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout & \z80_|execute_|fMRead~6_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout )) # +// (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h1F13; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fIOWrite~0_combout ) # ((!\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|execute_|fMWrite~5_combout & (\z80_|execute_|fMWrite~6_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'hC8FA; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~9_combout & (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~11_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_bus_inc_oe~18_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~13_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h40C0; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|execute_|ctl_inc_cy~31_combout & (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # +// (!\z80_|execute_|fIOWrite~5_combout & (((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h88F8; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hFF40; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N17 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N17 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \Equal5~0 ( +// Equation(s): +// \Equal5~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~0 .lut_mask = 16'h0080; +defparam \Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~18_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|address_latch_|abusz [1]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h00DD; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~35_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h44F4; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N10 +cycloneive_lcell_comb \Equal3~0 ( +// Equation(s): +// \Equal3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((!\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|address_pins_|DFFE_apin_latch [1])) # (!\z80_|address_pins_|DFFE_apin_latch [0]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~0 .lut_mask = 16'h2AAA; +defparam \Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [6]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[6]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~26 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N16 +cycloneive_lcell_comb \Equal3~1 ( +// Equation(s): +// \Equal3~1_combout = (((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|address_pins_|DFFE_apin_latch [4])) # (!\z80_|address_pins_|DFFE_apin_latch [3]) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~1 .lut_mask = 16'hF7FF; +defparam \Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N0 +cycloneive_lcell_comb \Equal3~2 ( +// Equation(s): +// \Equal3~2_combout = (\Equal3~0_combout ) # ((\z80_|address_pins_|abus[6]~25_combout ) # ((\z80_|address_pins_|abus[7]~26_combout ) # (\Equal3~1_combout ))) + + .dataa(\Equal3~0_combout ), + .datab(\z80_|address_pins_|abus[6]~25_combout ), + .datac(\z80_|address_pins_|abus[7]~26_combout ), + .datad(\Equal3~1_combout ), + .cin(gnd), + .combout(\Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~2 .lut_mask = 16'hFFFE; +defparam \Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \D[5]~26 ( +// Equation(s): +// \D[5]~26_combout = (\Equal5~1_combout & ((!\Equal3~2_combout ) # (!\Equal5~0_combout ))) + + .dataa(\Equal5~1_combout ), + .datab(gnd), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\D[5]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~26 .lut_mask = 16'h0AAA; +defparam \D[5]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [15])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [15]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~23 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[15]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h1000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~24 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~27 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~28 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[3]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~30 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[5]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~17 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[8]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~16 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|address_latch_|abusz [10]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [11]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~18 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -46059,10 +41012,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46100,7 +41053,170 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: FF_X21_Y15_N25 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N23 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0088; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -46116,10 +41232,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46157,7 +41273,96 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: LCCOMB_X29_Y12_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~20_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~22_combout & \z80_|address_pins_|abus[15]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -46173,10 +41378,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46214,10 +41419,10 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) @@ -46226,52 +41431,776 @@ cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .lut_mask = 16'hBBC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N2 -cycloneive_lcell_comb \D[5]~97 ( +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( // Equation(s): -// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\D[5]~97_combout ), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[5]~97 .lut_mask = 16'h2000; -defparam \D[5]~97 .sum_lutc_input = "datac"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), +// Location: FF_X31_Y22_N13 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N29 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (!\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0400; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N29 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N11 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N27 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N17 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h9933; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N19 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] $ (VCC))) # (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0])) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N1 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N5 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(\ula_|video_|Add4~12_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N19 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & ((\ula_|video_|Add4~4_combout )))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vram_address[10]~2_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|Add4~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N25 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~12_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFAA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N31 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -46279,16 +42208,181 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hD9C8; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -46342,283 +42436,111 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N6 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \Selector0~1 ( // Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # (!\Selector0~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\Selector0~0_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector0~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hB9A8; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector0~1 .lut_mask = 16'hF838; +defparam \Selector0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N4 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \D[7]~36 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \D[7]~36_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector0~1_combout ))))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), + .datad(\Selector0~1_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\D[7]~36_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \D[7]~36 .lut_mask = 16'h5140; +defparam \D[7]~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N20 -cycloneive_lcell_comb \D[7]~116 ( +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \D[7]~37 ( // Equation(s): -// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) +// \D[7]~37_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~36_combout ) # (!\D[5]~26_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~36_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datab(\D[5]~97_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~116_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~116 .lut_mask = 16'hBFB3; -defparam \D[7]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N26 -cycloneive_lcell_comb \D[7]~117 ( -// Equation(s): -// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), + .dataa(\z80_|data_pins_|dout [7]), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [7]), - .datad(\D[7]~116_combout ), + .datac(\D[5]~26_combout ), + .datad(\D[7]~36_combout ), .cin(gnd), - .combout(\D[7]~117_combout ), + .combout(\D[7]~37_combout ), .cout()); // synopsys translate_off -defparam \D[7]~117 .lut_mask = 16'hF311; -defparam \D[7]~117 .sum_lutc_input = "datac"; +defparam \D[7]~37 .lut_mask = 16'hBB0B; +defparam \D[7]~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N0 +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \D[7]~48 ( +// Equation(s): +// \D[7]~48_combout = (\D[7]~37_combout ) # (!\D[0]~49_combout ) + + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), + .cin(gnd), + .combout(\D[7]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~48 .lut_mask = 16'hFF33; +defparam \D[7]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~48_combout )))) # (!\z80_|bus_control_|db[7]~6_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~48_combout )))) - .dataa(\z80_|bus_control_|db[7]~7_combout ), + .dataa(\z80_|bus_control_|db[7]~6_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[7]~117_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[7]~48_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N1 +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFF8; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 dffeas \z80_|data_pins_|dout[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), @@ -46637,33 +42559,33 @@ defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~6 ( // Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[7]~6_combout = ((\z80_|bus_control_|db[7]~4_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[7]~5_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[7]~4_combout ), .datad(\z80_|data_pins_|dout [7]), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), + .combout(\z80_|bus_control_|db[7]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[7]~6 .lut_mask = 16'hF575; +defparam \z80_|bus_control_|db[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N13 +// Location: FF_X29_Y17_N3 dffeas \z80_|ir_|opcode[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|bus_control_|db[7]~6_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [7]), @@ -46673,93 +42595,3266 @@ defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & \z80_|ir_|opcode [6])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~0_combout & (\z80_|execute_|ctl_mWrite~7_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((!\z80_|execute_|fIOWrite~0_combout & \z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|fIORead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~6_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~5_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0500; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~59 ( +// Equation(s): +// \z80_|execute_|setM1~59_combout = (!\z80_|execute_|ctl_mRead~11_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~59 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & (\z80_|execute_|setM1~39_combout & (!\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|setM1~59_combout ))) + + .dataa(\z80_|execute_|setM1~40_combout ), + .datab(\z80_|execute_|setM1~39_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|setM1~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0800; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_mRead~22_combout & \z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFFC0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~29_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (!\z80_|execute_|ctl_mRead~27_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ctl_mRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y17_N21 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: FF_X32_Y15_N9 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N27 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \Equal5~1 ( +// Equation(s): +// \Equal5~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~1 .lut_mask = 16'h0808; +defparam \Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \Selector10~0 ( +// Equation(s): +// \Selector10~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~0 .lut_mask = 16'hD9C8; +defparam \Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \Selector10~1 ( +// Equation(s): +// \Selector10~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector10~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector10~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector10~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\Selector10~0_combout ), + .cin(gnd), + .combout(\Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~1 .lut_mask = 16'hBBC0; +defparam \Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y29_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|clk_filter [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N17 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [1]), + .datab(\ula_|ps2_keyboard_|clk_filter [3]), + .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N1 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y21_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y20_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hC4C4; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N25 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF850; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N21 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~52_combout = (\ula_|zx_keyboard_|keys[3][2]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~52 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~51_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~54_combout = (\ula_|zx_keyboard_|keys[2][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~53_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~54 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N17 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~5 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~5_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~5 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~48 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|keys[0][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (\ula_|zx_keyboard_|keys[0][2]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[0][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[0][2]~48_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~46_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~46 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h0088; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[3][3]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N21 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~4_combout = (\ula_|zx_keyboard_|keys[0][2]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\ula_|zx_keyboard_|keys[0][2]~q & +// (((\z80_|address_pins_|abus[9]~16_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~q ), + .datab(\ula_|zx_keyboard_|keys[1][2]~q ), + .datac(\z80_|address_pins_|abus[9]~16_combout ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~4 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~60_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h0A0A; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hC888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N23 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hCCFC; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~59_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~59 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[7][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[7][2]~63_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][2]~q ))))) # (!\ula_|zx_keyboard_|keys[7][2]~63_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~66 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[6][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~66_combout & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~65_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~65 .lut_mask = 16'hFF0C; +defparam \ula_|zx_keyboard_|keys[5][0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|zx_keyboard_|keys[6][2]~67_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|zx_keyboard_|keys[6][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~7 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~7_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~22_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~7 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][2]~30_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|zx_keyboard_|keys[5][2]~55_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~55_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~57_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~57 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~129_combout = (\ula_|zx_keyboard_|keys[4][2]~57_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~129 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[4][2]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~128_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~128 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|zx_keyboard_|keys[4][2]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~6 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~6_combout = (\ula_|zx_keyboard_|keys[5][2]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~6 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [2] = (\ula_|zx_keyboard_|key_row[2]~5_combout & (\ula_|zx_keyboard_|key_row[2]~4_combout & (\ula_|zx_keyboard_|key_row[2]~7_combout & \ula_|zx_keyboard_|key_row[2]~6_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .datab(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .datac(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .datad(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [2]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \Selector14~17 ( +// Equation(s): +// \Selector14~17_combout = (\Equal5~0_combout & (((!\z80_|address_pins_|DFFE_apin_latch [0] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\Equal3~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~17_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~17 .lut_mask = 16'h40F0; +defparam \Selector14~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \Selector14~18 ( +// Equation(s): +// \Selector14~18_combout = (\Equal5~0_combout & (((!\Equal3~2_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [15]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~18_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~18 .lut_mask = 16'h0BFB; +defparam \Selector14~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N22 +cycloneive_io_ibuf \kempston[1]~input ( + .i(kempston[1]), + .ibar(gnd), + .o(\kempston[1]~input_o )); +// synopsys translate_off +defparam \kempston[1]~input .bus_hold = "false"; +defparam \kempston[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \Selector10~2 ( +// Equation(s): +// \Selector10~2_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[1]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [2])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [2]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[1]~input_o ), + .cin(gnd), + .combout(\Selector10~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~2 .lut_mask = 16'h0BCB; +defparam \Selector10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \Selector10~3 ( +// Equation(s): +// \Selector10~3_combout = (\Equal5~0_combout & (((\Selector10~2_combout )))) # (!\Equal5~0_combout & ((\Selector10~2_combout & ((\Selector10~1_combout ))) # (!\Selector10~2_combout & +// (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector10~1_combout ), + .datad(\Selector10~2_combout ), + .cin(gnd), + .combout(\Selector10~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~3 .lut_mask = 16'hFC22; +defparam \Selector10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \D[2]~13 ( +// Equation(s): +// \D[2]~13_combout = (\Equal5~1_combout & (\Selector10~3_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout +// ))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Selector10~3_combout ), + .datad(\z80_|data_pins_|dout [2]), + .cin(gnd), + .combout(\D[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~13 .lut_mask = 16'hF531; +defparam \D[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\D[2]~13_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[2]~14_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[2]~13_combout & (\z80_|bus_control_|db[2]~14_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\D[2]~13_combout ), + .datab(\z80_|bus_control_|db[2]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N23 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[2]~28_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~14 ( +// Equation(s): +// \z80_|bus_control_|db[2]~14_combout = ((\z80_|bus_control_|db[2]~13_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|bus_control_|db[0]~5_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~14 .lut_mask = 16'h8FCF; +defparam \z80_|bus_control_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N1 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~14_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hC800; defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 +// Location: LCCOMB_X29_Y14_N12 cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), .datad(\z80_|pla_decode_|Equal41~1_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N8 +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~17_combout = ((\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~17 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_ir_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[4]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~3_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~2_combout = (!\z80_|ir_|opcode [5] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal2~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal2~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( // Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # -// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_state_tbl_cb_set~2_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .dataa(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hBAAA; defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N9 +// Location: FF_X29_Y18_N15 dffeas \z80_|decode_state_|DFFE_instCB ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), @@ -46778,941 +45873,1095 @@ defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y6_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - .dataa(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|decode_state_|table_xx~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal47~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y12_N29 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_66_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [0] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[6]~8_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~16 ( +// Equation(s): +// \z80_|alu_control_|db[6]~16_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~16 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[6]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~2_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~2 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~17 ( +// Equation(s): +// \z80_|alu_control_|db[6]~17_combout = (\z80_|alu_control_|db[6]~16_combout & (\z80_|reg_file_|db_lo_ds[6]~2_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|db[6]~16_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~17 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[6]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~18 ( +// Equation(s): +// \z80_|alu_control_|db[6]~18_combout = ((\z80_|alu_control_|db[6]~17_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .datab(\z80_|alu_control_|db[6]~17_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( +// Equation(s): +// \z80_|bus_control_|db[6]~7_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'h8A8A; +defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \D[6]~28 ( +// Equation(s): +// \D[6]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~28 .lut_mask = 16'hFFCF; +defparam \D[6]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \D[6]~43 ( +// Equation(s): +// \D[6]~43_combout = (\Equal5~0_combout & (\Equal3~2_combout & ((\D[6]~28_combout )))) # (!\Equal5~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\Equal5~0_combout ), + .datab(\Equal3~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\D[6]~28_combout ), + .cin(gnd), + .combout(\D[6]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~43 .lut_mask = 16'hD850; +defparam \D[6]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[6]~44 ( +// Equation(s): +// \D[6]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\Equal5~0_combout & ((\D[6]~43_combout ))) # (!\Equal5~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[6]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\Equal5~0_combout ), + .datad(\D[6]~43_combout ), + .cin(gnd), + .combout(\D[6]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~44 .lut_mask = 16'hFB08; +defparam \D[6]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[6]~42 ( +// Equation(s): +// \D[6]~42_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[6]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~42 .lut_mask = 16'hAACC; +defparam \D[6]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[6]~45 ( +// Equation(s): +// \D[6]~45_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~44_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Equal5~0_combout & (\D[6]~44_combout )) # (!\Equal5~0_combout & +// ((\D[6]~42_combout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\D[6]~44_combout ), + .datad(\D[6]~42_combout ), + .cin(gnd), + .combout(\D[6]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~45 .lut_mask = 16'hF1E0; +defparam \D[6]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) # (!\z80_|address_pins_|abus[14]~22_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux1~0 .lut_mask = 16'hDC98; +defparam \Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[6]~41 ( +// Equation(s): +// \D[6]~41_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux1~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # (!\Mux1~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux1~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Mux1~0_combout ), + .cin(gnd), + .combout(\D[6]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~41 .lut_mask = 16'hF388; +defparam \D[6]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[6]~46 ( +// Equation(s): +// \D[6]~46_combout = (\Equal5~0_combout & (((\D[6]~45_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\D[6]~45_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\D[6]~41_combout ))))) + + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\D[6]~45_combout ), + .datad(\D[6]~41_combout ), + .cin(gnd), + .combout(\D[6]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~46 .lut_mask = 16'hF1E0; +defparam \D[6]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[6]~47 ( +// Equation(s): +// \D[6]~47_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~46_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~46_combout ), + .cin(gnd), + .combout(\D[6]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~47 .lut_mask = 16'hAF23; +defparam \D[6]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~47_combout )))) # (!\z80_|bus_control_|db[6]~8_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~47_combout )))) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[6]~47_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = ((\z80_|bus_control_|db[6]~7_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[6]~7_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~8_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~8_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N29 +dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), + .q(\z80_|ir_|opcode [6]), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~18 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) +// \z80_|execute_|ctl_ir_we~18_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|im2~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .combout(\z80_|execute_|ctl_ir_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~16 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_bus_inc_oe~16_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_bus_inc_oe~15_combout )) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_mWrite~12_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|ctl_bus_db_we~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~18_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~10 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_bus_db_we~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( // Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) +// \z80_|execute_|ctl_bus_db_we~7_combout = (((\z80_|execute_|ctl_bus_db_we~10_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_bus_db_we~6_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~10_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_ir_we~8_combout ))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~9 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|execute_|ctl_bus_db_we~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~9 .lut_mask = 16'h4440; +defparam \z80_|execute_|ctl_bus_db_we~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|execute_|ctl_bus_db_we~5_combout ) # ((\z80_|execute_|ctl_bus_db_we~4_combout ) # (\z80_|execute_|ctl_bus_db_we~9_combout ))) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout -// )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; -defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N1 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N28 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hD0DD; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; -defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & -// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; -defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & -// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N2 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~q ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'h8ACF; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & -// \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; -defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .datac(\ula_|zx_keyboard_|keys~69_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; -defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys~71_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y8_N11 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N15 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N17 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][0]~q ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'h8CAF; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N12 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), - .datab(\z80_|address_pins_|abus[9]~17_combout ), - .datac(\ula_|zx_keyboard_|key_row~2_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hD000; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) - - .dataa(\D[0]~57_combout ), - .datab(\D[0]~56_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[0]~55_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hF8F0; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -47728,10 +46977,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47769,140 +47018,879 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N12 -cycloneive_lcell_comb \D[0]~62 ( +// Location: LCCOMB_X19_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( // Equation(s): -// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\D[0]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), .cout()); // synopsys translate_off -defparam \D[0]~62 .lut_mask = 16'hEC64; -defparam \D[0]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'hFF30; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'h1204; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][1]~34_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|keys[4][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~83_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~82_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[5][0]~79_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h2080; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|zx_keyboard_|keys[5][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~10_combout = (\ula_|zx_keyboard_|keys[4][0]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) # (!\ula_|zx_keyboard_|keys[4][0]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~10 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~130_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~76_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~130 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & ((\ula_|zx_keyboard_|keys[7][0]~85_combout ) # (\ula_|zx_keyboard_|keys[7][0]~130_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N17 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~11 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~11_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][0]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~11 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg +// [5] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (!\ula_|zx_keyboard_|extended~q & ((\ula_|ps2_keyboard_|shiftreg [3]) # ((!\ula_|zx_keyboard_|keys[4][1]~29_combout ) # (!\ula_|zx_keyboard_|WideOr4~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h0B0F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~72_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~45_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~72 .lut_mask = 16'h335F; +defparam \ula_|zx_keyboard_|keys~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~71_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~71 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~73_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~72_combout & \ula_|zx_keyboard_|keys[4][3]~71_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys~72_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~73 .lut_mask = 16'h4C0C; +defparam \ula_|zx_keyboard_|keys[0][0]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys~74_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~74_combout & ((\ula_|zx_keyboard_|keys[0][0]~73_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[0][0]~73_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys~74_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hCC00; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~69_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~69 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][0]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~70_combout = (\ula_|zx_keyboard_|keys[1][0]~69_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~69_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~70 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~8 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~8_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\z80_|address_pins_|abus[9]~16_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~8 .lut_mask = 16'hDD0D; +defparam \ula_|zx_keyboard_|key_row[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~78 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[2][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~77_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~76_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~77 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~9 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~9_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~19_combout & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & +// (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~9 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [0] = (\ula_|zx_keyboard_|key_row[0]~10_combout & (\ula_|zx_keyboard_|key_row[0]~11_combout & (\ula_|zx_keyboard_|key_row[0]~8_combout & \ula_|zx_keyboard_|key_row[0]~9_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .datab(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .datac(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .datad(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [0]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y34_N22 +cycloneive_io_ibuf \kempston[3]~input ( + .i(kempston[3]), + .ibar(gnd), + .o(\kempston[3]~input_o )); +// synopsys translate_off +defparam \kempston[3]~input .bus_hold = "false"; +defparam \kempston[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \Selector14~8 ( +// Equation(s): +// \Selector14~8_combout = (\Selector14~18_combout & (((!\kempston[3]~input_o & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row [0]) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [0]), + .datab(\Selector14~18_combout ), + .datac(\kempston[3]~input_o ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~8 .lut_mask = 16'h2E33; +defparam \Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \Selector14~13 ( +// Equation(s): +// \Selector14~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\Selector14~8_combout ) # ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a +// [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~13 .lut_mask = 16'hFFEA; +defparam \Selector14~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -47918,10 +47906,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47959,27 +47947,9 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N8 -cycloneive_lcell_comb \D[0]~63 ( -// Equation(s): -// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~62_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~63 .lut_mask = 16'hE3E0; -defparam \D[0]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -47987,16 +47957,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48050,7 +48020,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y4_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), @@ -48060,16 +48030,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48108,27 +48078,176 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \Selector14~19 ( // Equation(s): -// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) +// \Selector14~19_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\Selector14~19_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hE6A2; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \Selector14~19 .lut_mask = 16'hF4B0; +defparam \Selector14~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y29_N0 +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \Selector14~10 ( +// Equation(s): +// \Selector14~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~10 .lut_mask = 16'hFA0A; +defparam \Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \Selector14~11 ( +// Equation(s): +// \Selector14~11_combout = (\Selector14~8_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((!\Selector14~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector14~10_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~11 .lut_mask = 16'hCC0A; +defparam \Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -48136,16 +48255,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48198,7 +48317,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y11_N0 +// Location: M9K_X22_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -48208,16 +48327,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48256,104 +48375,102 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N28 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \Selector14~20 ( // Equation(s): -// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) +// \Selector14~20_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'h30CA; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N10 -cycloneive_lcell_comb \D[0]~61 ( -// Equation(s): -// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) - - .dataa(\D[0]~59_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\D[0]~60_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~61_combout ), + .combout(\Selector14~20_combout ), .cout()); // synopsys translate_off -defparam \D[0]~61 .lut_mask = 16'h99A8; -defparam \D[0]~61 .sum_lutc_input = "datac"; +defparam \Selector14~20 .lut_mask = 16'hF2D0; +defparam \Selector14~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N18 -cycloneive_lcell_comb \D[0]~120 ( +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \Selector14~9 ( // Equation(s): -// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~63_combout )))) +// \Selector14~9_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector14~20_combout )) # (!\Selector14~8_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~63_combout ), - .datad(\D[0]~61_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\Selector14~20_combout ), + .datad(\Selector14~8_combout ), .cin(gnd), - .combout(\D[0]~120_combout ), + .combout(\Selector14~9_combout ), .cout()); // synopsys translate_off -defparam \D[0]~120 .lut_mask = 16'hF4B0; -defparam \D[0]~120 .sum_lutc_input = "datac"; +defparam \Selector14~9 .lut_mask = 16'hDC33; +defparam \Selector14~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N26 -cycloneive_lcell_comb \D[0]~64 ( +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \Selector14~12 ( // Equation(s): -// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) +// \Selector14~12_combout = (\Selector14~11_combout & (\Selector14~8_combout & ((\Selector14~19_combout ) # (\Selector14~9_combout )))) # (!\Selector14~11_combout & (((\Selector14~9_combout )))) - .dataa(\D[0]~58_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[0]~120_combout ), + .dataa(\Selector14~19_combout ), + .datab(\Selector14~8_combout ), + .datac(\Selector14~11_combout ), + .datad(\Selector14~9_combout ), .cin(gnd), - .combout(\D[0]~64_combout ), + .combout(\Selector14~12_combout ), .cout()); // synopsys translate_off -defparam \D[0]~64 .lut_mask = 16'hBF8F; -defparam \D[0]~64 .sum_lutc_input = "datac"; +defparam \Selector14~12 .lut_mask = 16'hCF80; +defparam \Selector14~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N16 -cycloneive_lcell_comb \D[0]~65 ( +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \Selector14~14 ( // Equation(s): -// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) +// \Selector14~14_combout = (\Selector14~12_combout & ((\Selector14~13_combout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\Selector14~13_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\Selector14~12_combout ), + .cin(gnd), + .combout(\Selector14~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~14 .lut_mask = 16'hBA00; +defparam \Selector14~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \D[0]~14 ( +// Equation(s): +// \D[0]~14_combout = (\z80_|data_pins_|dout [0] & (((\Selector14~14_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [0]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[0]~64_combout ), - .datad(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), - .combout(\D[0]~65_combout ), + .combout(\D[0]~14_combout ), .cout()); // synopsys translate_off -defparam \D[0]~65 .lut_mask = 16'hB0B3; -defparam \D[0]~65 .sum_lutc_input = "datac"; +defparam \D[0]~14 .lut_mask = 16'hAF23; +defparam \D[0]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N26 +// Location: LCCOMB_X26_Y16_N8 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & -// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[0]~12_combout & +// (((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\D[0]~65_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\D[0]~14_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), .cout()); @@ -48362,7 +48479,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N27 +// Location: FF_X26_Y16_N9 dffeas \z80_|data_pins_|dout[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), @@ -48381,50 +48498,51 @@ defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~11 ( // Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[0]~11_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|alu_control_|db[0]~25_combout ) # ((!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|execute_|ctl_bus_ff_oe~1_combout & +// (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|data_pins_|dout [0]), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|alu_control_|db[0]~25_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), + .combout(\z80_|bus_control_|db[0]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~11 .lut_mask = 16'h8ACF; +defparam \z80_|bus_control_|db[0]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~12 ( // Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[0]~12_combout = ((\z80_|bus_control_|db[0]~11_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[0]~16_combout ), - .datab(\z80_|alu_control_|db[0]~14_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|bus_control_|db[0]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), + .combout(\z80_|bus_control_|db[0]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~12 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N19 +// Location: FF_X26_Y15_N15 dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), + .d(\z80_|bus_control_|db[0]~12_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [0]), @@ -48434,2832 +48552,311 @@ defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y7_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( // Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal3~2_combout ), + .dataa(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y7_N31 -dffeas \z80_|decode_state_|DFFE_instIY1 ( +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((\z80_|alu_control_|db[4]~31_combout & \z80_|execute_|ctl_flags_bus~combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))) # +// (!\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_control_|db[4]~31_combout & ((\z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hCE0A; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # -// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~12_combout ), - .datac(\z80_|execute_|ixy_d~13_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|ixy_d~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~11_combout ), - .datac(\z80_|execute_|ctl_alu_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N0 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~20_combout ), - .datad(\z80_|alu_|db[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|alu_control_|db[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; -defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( -// Equation(s): -// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|sw1_|db_down[1]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; -defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; -defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N9 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; -defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y10_N25 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; -defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N28 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hCF45; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N12 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|key_row~0_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hB000; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; -defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & -// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N16 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), - .datab(\ula_|zx_keyboard_|keys[0][1]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hF531; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N21 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N8 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'h8ACF; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N6 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~33_combout ), - .datab(\D[1]~30_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF8F0; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N22 -cycloneive_lcell_comb \D[1]~38 ( -// Equation(s): -// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .cin(gnd), - .combout(\D[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~38 .lut_mask = 16'hE6A2; -defparam \D[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N4 -cycloneive_lcell_comb \D[1]~39 ( -// Equation(s): -// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\D[1]~38_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\D[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~39 .lut_mask = 16'hE5E0; -defparam \D[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N24 -cycloneive_lcell_comb \D[1]~35 ( -// Equation(s): -// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\D[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~35 .lut_mask = 16'hEA62; -defparam \D[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N14 -cycloneive_lcell_comb \D[1]~36 ( -// Equation(s): -// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~36 .lut_mask = 16'h44B8; -defparam \D[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \D[1]~37 ( -// Equation(s): -// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datac(\D[1]~36_combout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~37 .lut_mask = 16'hAE50; -defparam \D[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[1]~118 ( -// Equation(s): -// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[1]~39_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[1]~39_combout ), - .datad(\D[1]~37_combout ), - .cin(gnd), - .combout(\D[1]~118_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~118 .lut_mask = 16'hF4B0; -defparam \D[1]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N2 -cycloneive_lcell_comb \D[1]~40 ( -// Equation(s): -// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[1]~34_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[1]~118_combout ), - .cin(gnd), - .combout(\D[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~40 .lut_mask = 16'hBF8F; -defparam \D[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N12 -cycloneive_lcell_comb \D[1]~41 ( -// Equation(s): -// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[1]~40_combout ), - .cin(gnd), - .combout(\D[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~41 .lut_mask = 16'hAF03; -defparam \D[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & -// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[1]~41_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[1]~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[1]~10_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N1 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~1_combout ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .combout(\z80_|alu_flags_|flags_hf~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h31CE; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y9_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N16 -cycloneive_lcell_comb \D[4]~88 ( +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~29 ( // Equation(s): -// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_control_|db[4]~29_combout = (\z80_|reg_file_|gdfx_temp0[4]~73_combout & (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # +// ((!\z80_|alu_|db[4]~10_combout & \z80_|execute_|ctl_sw_2u~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .dataa(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), .cin(gnd), - .combout(\D[4]~88_combout ), + .combout(\z80_|alu_control_|db[4]~29_combout ), .cout()); // synopsys translate_off -defparam \D[4]~88 .lut_mask = 16'hD0DD; -defparam \D[4]~88 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~29 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|alu_control_|db[4]~30_combout = (!\z80_|alu_control_|db[4]~29_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_control_|db[4]~29_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h2300; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|alu_control_|db[4]~31_combout = ((\z80_|alu_control_|db[4]~30_combout & ((\z80_|bus_control_|db[4]~18_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|bus_control_|db[4]~18_combout ), + .datab(\z80_|alu_control_|db[4]~30_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h8FCF; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N28 -cycloneive_lcell_comb \D[4]~87 ( -// Equation(s): -// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\D[4]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'h8ACF; -defparam \D[4]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N21 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|Equal0~2_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N15 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N6 -cycloneive_lcell_comb \D[4]~85 ( -// Equation(s): -// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~85 .lut_mask = 16'hA2F3; -defparam \D[4]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y11_N20 -cycloneive_lcell_comb \D[4]~86 ( -// Equation(s): -// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|key_row~3_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\D[4]~85_combout ), - .cin(gnd), - .combout(\D[4]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~86 .lut_mask = 16'h8A00; -defparam \D[4]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N24 -cycloneive_lcell_comb \D[4]~89 ( -// Equation(s): -// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) - - .dataa(\D[4]~88_combout ), - .datab(\D[4]~87_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[4]~86_combout ), - .cin(gnd), - .combout(\D[4]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~89 .lut_mask = 16'hF8F0; -defparam \D[4]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N18 -cycloneive_lcell_comb \D[4]~93 ( -// Equation(s): -// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .cin(gnd), - .combout(\D[4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~93 .lut_mask = 16'hF838; -defparam \D[4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N4 -cycloneive_lcell_comb \D[4]~94 ( -// Equation(s): -// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\D[4]~93_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .cin(gnd), - .combout(\D[4]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~94 .lut_mask = 16'hCEC2; -defparam \D[4]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X22_Y21_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51267,16 +48864,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51330,83 +48927,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N8 -cycloneive_lcell_comb \D[4]~90 ( -// Equation(s): -// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .cin(gnd), - .combout(\D[4]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~90 .lut_mask = 16'hE6A2; -defparam \D[4]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 +// Location: M9K_X33_Y22_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -51416,16 +48937,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51464,104 +48985,2926 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N22 -cycloneive_lcell_comb \D[4]~91 ( +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \Selector6~0 ( // Equation(s): -// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ) # (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & ((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hCCE2; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector6~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hF388; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[4]~90_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), .cin(gnd), - .combout(\D[4]~91_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), .cout()); // synopsys translate_off -defparam \D[4]~91 .lut_mask = 16'h4B48; -defparam \D[4]~91 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N28 -cycloneive_lcell_comb \D[4]~92 ( +// Location: LCCOMB_X19_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( // Equation(s): -// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [0]))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[4]~90_combout ), - .datad(\D[4]~91_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~92_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~92 .lut_mask = 16'hC3E0; -defparam \D[4]~92 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N8 -cycloneive_lcell_comb \D[4]~125 ( +// Location: LCCOMB_X20_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~114 ( // Equation(s): -// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (((\D[4]~94_combout )))) +// \ula_|zx_keyboard_|keys[6][4]~114_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\D[4]~94_combout ), - .datad(\D[4]~92_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\D[4]~125_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~114_combout ), .cout()); // synopsys translate_off -defparam \D[4]~125 .lut_mask = 16'hF2D0; -defparam \D[4]~125 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N30 -cycloneive_lcell_comb \D[4]~110 ( +// Location: LCCOMB_X20_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~115 ( // Equation(s): -// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) +// \ula_|zx_keyboard_|keys[6][4]~115_combout = (\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~115 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~113_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~1_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~113 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N5 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~16_combout = (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][4]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~16 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[0]~21 ( +// Equation(s): +// \debounce_autofire|r_Count[0]~21_combout = \debounce_autofire|r_Count [0] $ (VCC) +// \debounce_autofire|r_Count[0]~22 = CARRY(\debounce_autofire|r_Count [0]) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_autofire|r_Count[0]~21_combout ), + .cout(\debounce_autofire|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_autofire|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[1]~23 ( +// Equation(s): +// \debounce_autofire|r_Count[1]~23_combout = (\debounce_autofire|r_Count [1] & (!\debounce_autofire|r_Count[0]~22 )) # (!\debounce_autofire|r_Count [1] & ((\debounce_autofire|r_Count[0]~22 ) # (GND))) +// \debounce_autofire|r_Count[1]~24 = CARRY((!\debounce_autofire|r_Count[0]~22 ) # (!\debounce_autofire|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[0]~22 ), + .combout(\debounce_autofire|r_Count[1]~23_combout ), + .cout(\debounce_autofire|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \debounce_autofire|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[2]~25 ( +// Equation(s): +// \debounce_autofire|r_Count[2]~25_combout = (\debounce_autofire|r_Count [2] & (\debounce_autofire|r_Count[1]~24 $ (GND))) # (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count[1]~24 & VCC)) +// \debounce_autofire|r_Count[2]~26 = CARRY((\debounce_autofire|r_Count [2] & !\debounce_autofire|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[1]~24 ), + .combout(\debounce_autofire|r_Count[2]~25_combout ), + .cout(\debounce_autofire|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \debounce_autofire|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[3]~27 ( +// Equation(s): +// \debounce_autofire|r_Count[3]~27_combout = (\debounce_autofire|r_Count [3] & (!\debounce_autofire|r_Count[2]~26 )) # (!\debounce_autofire|r_Count [3] & ((\debounce_autofire|r_Count[2]~26 ) # (GND))) +// \debounce_autofire|r_Count[3]~28 = CARRY((!\debounce_autofire|r_Count[2]~26 ) # (!\debounce_autofire|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[2]~26 ), + .combout(\debounce_autofire|r_Count[3]~27_combout ), + .cout(\debounce_autofire|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \debounce_autofire|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[4]~29 ( +// Equation(s): +// \debounce_autofire|r_Count[4]~29_combout = (\debounce_autofire|r_Count [4] & (\debounce_autofire|r_Count[3]~28 $ (GND))) # (!\debounce_autofire|r_Count [4] & (!\debounce_autofire|r_Count[3]~28 & VCC)) +// \debounce_autofire|r_Count[4]~30 = CARRY((\debounce_autofire|r_Count [4] & !\debounce_autofire|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[3]~28 ), + .combout(\debounce_autofire|r_Count[4]~29_combout ), + .cout(\debounce_autofire|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \debounce_autofire|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \debounce_autofire|r_Count[5]~31 ( +// Equation(s): +// \debounce_autofire|r_Count[5]~31_combout = (\debounce_autofire|r_Count [5] & (!\debounce_autofire|r_Count[4]~30 )) # (!\debounce_autofire|r_Count [5] & ((\debounce_autofire|r_Count[4]~30 ) # (GND))) +// \debounce_autofire|r_Count[5]~32 = CARRY((!\debounce_autofire|r_Count[4]~30 ) # (!\debounce_autofire|r_Count [5])) + + .dataa(\debounce_autofire|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[4]~30 ), + .combout(\debounce_autofire|r_Count[5]~31_combout ), + .cout(\debounce_autofire|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \debounce_autofire|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \debounce_autofire|r_Count[6]~33 ( +// Equation(s): +// \debounce_autofire|r_Count[6]~33_combout = (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count[5]~32 $ (GND))) # (!\debounce_autofire|r_Count [6] & (!\debounce_autofire|r_Count[5]~32 & VCC)) +// \debounce_autofire|r_Count[6]~34 = CARRY((\debounce_autofire|r_Count [6] & !\debounce_autofire|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[5]~32 ), + .combout(\debounce_autofire|r_Count[6]~33_combout ), + .cout(\debounce_autofire|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \debounce_autofire|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \debounce_autofire|r_Count[7]~35 ( +// Equation(s): +// \debounce_autofire|r_Count[7]~35_combout = (\debounce_autofire|r_Count [7] & (!\debounce_autofire|r_Count[6]~34 )) # (!\debounce_autofire|r_Count [7] & ((\debounce_autofire|r_Count[6]~34 ) # (GND))) +// \debounce_autofire|r_Count[7]~36 = CARRY((!\debounce_autofire|r_Count[6]~34 ) # (!\debounce_autofire|r_Count [7])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[6]~34 ), + .combout(\debounce_autofire|r_Count[7]~35_combout ), + .cout(\debounce_autofire|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N27 +dffeas \debounce_autofire|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \debounce_autofire|r_Count[8]~37 ( +// Equation(s): +// \debounce_autofire|r_Count[8]~37_combout = (\debounce_autofire|r_Count [8] & (\debounce_autofire|r_Count[7]~36 $ (GND))) # (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_Count[7]~36 & VCC)) +// \debounce_autofire|r_Count[8]~38 = CARRY((\debounce_autofire|r_Count [8] & !\debounce_autofire|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[7]~36 ), + .combout(\debounce_autofire|r_Count[8]~37_combout ), + .cout(\debounce_autofire|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N29 +dffeas \debounce_autofire|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \debounce_autofire|r_Count[9]~39 ( +// Equation(s): +// \debounce_autofire|r_Count[9]~39_combout = (\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count[8]~38 )) # (!\debounce_autofire|r_Count [9] & ((\debounce_autofire|r_Count[8]~38 ) # (GND))) +// \debounce_autofire|r_Count[9]~40 = CARRY((!\debounce_autofire|r_Count[8]~38 ) # (!\debounce_autofire|r_Count [9])) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[8]~38 ), + .combout(\debounce_autofire|r_Count[9]~39_combout ), + .cout(\debounce_autofire|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \debounce_autofire|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_Count[10]~41 ( +// Equation(s): +// \debounce_autofire|r_Count[10]~41_combout = (\debounce_autofire|r_Count [10] & (\debounce_autofire|r_Count[9]~40 $ (GND))) # (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count[9]~40 & VCC)) +// \debounce_autofire|r_Count[10]~42 = CARRY((\debounce_autofire|r_Count [10] & !\debounce_autofire|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[9]~40 ), + .combout(\debounce_autofire|r_Count[10]~41_combout ), + .cout(\debounce_autofire|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \debounce_autofire|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \debounce_autofire|r_Count[11]~43 ( +// Equation(s): +// \debounce_autofire|r_Count[11]~43_combout = (\debounce_autofire|r_Count [11] & (!\debounce_autofire|r_Count[10]~42 )) # (!\debounce_autofire|r_Count [11] & ((\debounce_autofire|r_Count[10]~42 ) # (GND))) +// \debounce_autofire|r_Count[11]~44 = CARRY((!\debounce_autofire|r_Count[10]~42 ) # (!\debounce_autofire|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[10]~42 ), + .combout(\debounce_autofire|r_Count[11]~43_combout ), + .cout(\debounce_autofire|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \debounce_autofire|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \debounce_autofire|r_Count[12]~45 ( +// Equation(s): +// \debounce_autofire|r_Count[12]~45_combout = (\debounce_autofire|r_Count [12] & (\debounce_autofire|r_Count[11]~44 $ (GND))) # (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count[11]~44 & VCC)) +// \debounce_autofire|r_Count[12]~46 = CARRY((\debounce_autofire|r_Count [12] & !\debounce_autofire|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[11]~44 ), + .combout(\debounce_autofire|r_Count[12]~45_combout ), + .cout(\debounce_autofire|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \debounce_autofire|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \debounce_autofire|r_Count[13]~47 ( +// Equation(s): +// \debounce_autofire|r_Count[13]~47_combout = (\debounce_autofire|r_Count [13] & (!\debounce_autofire|r_Count[12]~46 )) # (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|r_Count[12]~46 ) # (GND))) +// \debounce_autofire|r_Count[13]~48 = CARRY((!\debounce_autofire|r_Count[12]~46 ) # (!\debounce_autofire|r_Count [13])) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[12]~46 ), + .combout(\debounce_autofire|r_Count[13]~47_combout ), + .cout(\debounce_autofire|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \debounce_autofire|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \debounce_autofire|r_Count[14]~49 ( +// Equation(s): +// \debounce_autofire|r_Count[14]~49_combout = (\debounce_autofire|r_Count [14] & (\debounce_autofire|r_Count[13]~48 $ (GND))) # (!\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count[13]~48 & VCC)) +// \debounce_autofire|r_Count[14]~50 = CARRY((\debounce_autofire|r_Count [14] & !\debounce_autofire|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[13]~48 ), + .combout(\debounce_autofire|r_Count[14]~49_combout ), + .cout(\debounce_autofire|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \debounce_autofire|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \debounce_autofire|r_Count[15]~51 ( +// Equation(s): +// \debounce_autofire|r_Count[15]~51_combout = (\debounce_autofire|r_Count [15] & (!\debounce_autofire|r_Count[14]~50 )) # (!\debounce_autofire|r_Count [15] & ((\debounce_autofire|r_Count[14]~50 ) # (GND))) +// \debounce_autofire|r_Count[15]~52 = CARRY((!\debounce_autofire|r_Count[14]~50 ) # (!\debounce_autofire|r_Count [15])) + + .dataa(\debounce_autofire|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[14]~50 ), + .combout(\debounce_autofire|r_Count[15]~51_combout ), + .cout(\debounce_autofire|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \debounce_autofire|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[16]~53 ( +// Equation(s): +// \debounce_autofire|r_Count[16]~53_combout = (\debounce_autofire|r_Count [16] & (\debounce_autofire|r_Count[15]~52 $ (GND))) # (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count[15]~52 & VCC)) +// \debounce_autofire|r_Count[16]~54 = CARRY((\debounce_autofire|r_Count [16] & !\debounce_autofire|r_Count[15]~52 )) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[15]~52 ), + .combout(\debounce_autofire|r_Count[16]~53_combout ), + .cout(\debounce_autofire|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_autofire|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \debounce_autofire|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[17]~55 ( +// Equation(s): +// \debounce_autofire|r_Count[17]~55_combout = (\debounce_autofire|r_Count [17] & (!\debounce_autofire|r_Count[16]~54 )) # (!\debounce_autofire|r_Count [17] & ((\debounce_autofire|r_Count[16]~54 ) # (GND))) +// \debounce_autofire|r_Count[17]~56 = CARRY((!\debounce_autofire|r_Count[16]~54 ) # (!\debounce_autofire|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[16]~54 ), + .combout(\debounce_autofire|r_Count[17]~55_combout ), + .cout(\debounce_autofire|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \debounce_autofire|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[18]~57 ( +// Equation(s): +// \debounce_autofire|r_Count[18]~57_combout = (\debounce_autofire|r_Count [18] & (\debounce_autofire|r_Count[17]~56 $ (GND))) # (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count[17]~56 & VCC)) +// \debounce_autofire|r_Count[18]~58 = CARRY((\debounce_autofire|r_Count [18] & !\debounce_autofire|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[17]~56 ), + .combout(\debounce_autofire|r_Count[18]~57_combout ), + .cout(\debounce_autofire|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \debounce_autofire|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[19]~59 ( +// Equation(s): +// \debounce_autofire|r_Count[19]~59_combout = (\debounce_autofire|r_Count [19] & (!\debounce_autofire|r_Count[18]~58 )) # (!\debounce_autofire|r_Count [19] & ((\debounce_autofire|r_Count[18]~58 ) # (GND))) +// \debounce_autofire|r_Count[19]~60 = CARRY((!\debounce_autofire|r_Count[18]~58 ) # (!\debounce_autofire|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[18]~58 ), + .combout(\debounce_autofire|r_Count[19]~59_combout ), + .cout(\debounce_autofire|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \debounce_autofire|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[20]~61 ( +// Equation(s): +// \debounce_autofire|r_Count[20]~61_combout = \debounce_autofire|r_Count[19]~60 $ (!\debounce_autofire|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_autofire|r_Count [20]), + .cin(\debounce_autofire|r_Count[19]~60 ), + .combout(\debounce_autofire|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_autofire|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \debounce_autofire|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y15_N8 +cycloneive_io_ibuf \kempston_autofire_button~input ( + .i(kempston_autofire_button), + .ibar(gnd), + .o(\kempston_autofire_button~input_o )); +// synopsys translate_off +defparam \kempston_autofire_button~input .bus_hold = "false"; +defparam \kempston_autofire_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~7 ( +// Equation(s): +// \debounce_autofire|r_State~7_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [6])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [6]), + .cin(gnd), + .combout(\debounce_autofire|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~7 .lut_mask = 16'hA000; +defparam \debounce_autofire|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \debounce_autofire|LessThan0~0 ( +// Equation(s): +// \debounce_autofire|LessThan0~0_combout = (!\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_State~7_combout & !\debounce_autofire|r_Count [10]))) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(\debounce_autofire|r_Count [8]), + .datac(\debounce_autofire|r_State~7_combout ), + .datad(\debounce_autofire|r_Count [10]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \debounce_autofire|LessThan0~1 ( +// Equation(s): +// \debounce_autofire|LessThan0~1_combout = (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|LessThan0~0_combout ) # (!\debounce_autofire|r_Count [11])))) + + .dataa(\debounce_autofire|LessThan0~0_combout ), + .datab(\debounce_autofire|r_Count [11]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [13]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~1 .lut_mask = 16'h000B; +defparam \debounce_autofire|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \debounce_autofire|always0~0 ( +// Equation(s): +// \debounce_autofire|always0~0_combout = (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count [17] & !\debounce_autofire|r_Count [19]))) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(\debounce_autofire|r_Count [18]), + .datac(\debounce_autofire|r_Count [17]), + .datad(\debounce_autofire|r_Count [19]), + .cin(gnd), + .combout(\debounce_autofire|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \debounce_autofire|always0~1 ( +// Equation(s): +// \debounce_autofire|always0~1_combout = (\debounce_autofire|always0~0_combout & ((\debounce_autofire|LessThan0~1_combout ) # ((!\debounce_autofire|r_Count [15]) # (!\debounce_autofire|r_Count [14])))) + + .dataa(\debounce_autofire|LessThan0~1_combout ), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|always0~0_combout ), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_autofire|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \debounce_autofire|always0~2 ( +// Equation(s): +// \debounce_autofire|always0~2_combout = (\debounce_autofire|r_Count [20] & ((\debounce_autofire|r_State~q $ (!\kempston_autofire_button~input_o )) # (!\debounce_autofire|always0~1_combout ))) # (!\debounce_autofire|r_Count [20] & +// (\debounce_autofire|r_State~q $ ((!\kempston_autofire_button~input_o )))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_State~q ), + .datac(\kempston_autofire_button~input_o ), + .datad(\debounce_autofire|always0~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~2 .lut_mask = 16'hC3EB; +defparam \debounce_autofire|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \debounce_autofire|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \debounce_autofire|r_State~4 ( +// Equation(s): +// \debounce_autofire|r_State~4_combout = (!\debounce_autofire|r_Count [0] & (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count [1] & !\debounce_autofire|r_Count [3]))) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(\debounce_autofire|r_Count [2]), + .datac(\debounce_autofire|r_Count [1]), + .datad(\debounce_autofire|r_Count [3]), + .cin(gnd), + .combout(\debounce_autofire|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_autofire|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \debounce_autofire|r_State~5 ( +// Equation(s): +// \debounce_autofire|r_State~5_combout = (\debounce_autofire|r_State~4_combout & !\debounce_autofire|r_Count [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\debounce_autofire|r_State~4_combout ), + .datad(\debounce_autofire|r_Count [4]), + .cin(gnd), + .combout(\debounce_autofire|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~5 .lut_mask = 16'h00F0; +defparam \debounce_autofire|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \debounce_autofire|r_State~2 ( +// Equation(s): +// \debounce_autofire|r_State~2_combout = (\debounce_autofire|r_Count [20] & (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count [9] & !\debounce_autofire|r_Count [8]))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_Count [10]), + .datac(\debounce_autofire|r_Count [9]), + .datad(\debounce_autofire|r_Count [8]), + .cin(gnd), + .combout(\debounce_autofire|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_autofire|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \debounce_autofire|r_State~0 ( +// Equation(s): +// \debounce_autofire|r_State~0_combout = (!\debounce_autofire|r_Count [13] & (\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count [12] & \debounce_autofire|r_Count [15]))) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_autofire|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \debounce_autofire|r_State~1 ( +// Equation(s): +// \debounce_autofire|r_State~1_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [11]))) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(\debounce_autofire|r_Count [6]), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [11]), + .cin(gnd), + .combout(\debounce_autofire|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~3 ( +// Equation(s): +// \debounce_autofire|r_State~3_combout = (\debounce_autofire|always0~0_combout & (\debounce_autofire|r_State~2_combout & (\debounce_autofire|r_State~0_combout & \debounce_autofire|r_State~1_combout ))) + + .dataa(\debounce_autofire|always0~0_combout ), + .datab(\debounce_autofire|r_State~2_combout ), + .datac(\debounce_autofire|r_State~0_combout ), + .datad(\debounce_autofire|r_State~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_State~6 ( +// Equation(s): +// \debounce_autofire|r_State~6_combout = (\debounce_autofire|r_State~5_combout & ((\debounce_autofire|r_State~3_combout & (\kempston_autofire_button~input_o )) # (!\debounce_autofire|r_State~3_combout & ((\debounce_autofire|r_State~q ))))) # +// (!\debounce_autofire|r_State~5_combout & (((\debounce_autofire|r_State~q )))) + + .dataa(\debounce_autofire|r_State~5_combout ), + .datab(\kempston_autofire_button~input_o ), + .datac(\debounce_autofire|r_State~q ), + .datad(\debounce_autofire|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~6 .lut_mask = 16'hD8F0; +defparam \debounce_autofire|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N19 +dffeas \debounce_autofire|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_autofire|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_State .is_wysiwyg = "true"; +defparam \debounce_autofire|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N30 +cycloneive_lcell_comb \kempston_autofire_enabled~0 ( +// Equation(s): +// \kempston_autofire_enabled~0_combout = !\kempston_autofire_enabled~q + + .dataa(gnd), + .datab(gnd), + .datac(\kempston_autofire_enabled~q ), + .datad(gnd), + .cin(gnd), + .combout(\kempston_autofire_enabled~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_autofire_enabled~0 .lut_mask = 16'h0F0F; +defparam \kempston_autofire_enabled~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N31 +dffeas kempston_autofire_enabled( + .clk(!\debounce_autofire|r_State~q ), + .d(\kempston_autofire_enabled~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_autofire_enabled~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_autofire_enabled.is_wysiwyg = "true"; +defparam kempston_autofire_enabled.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[0]~51 ( +// Equation(s): +// \kempston_auto_fire_counter[0]~51_combout = \kempston_autofire_enabled~q $ (kempston_auto_fire_counter[0]) + + .dataa(\kempston_autofire_enabled~q ), + .datab(gnd), + .datac(kempston_auto_fire_counter[0]), + .datad(gnd), + .cin(gnd), + .combout(\kempston_auto_fire_counter[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0]~51 .lut_mask = 16'h5A5A; +defparam \kempston_auto_fire_counter[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N13 +dffeas \kempston_auto_fire_counter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[0]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[0]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[1]~17 ( +// Equation(s): +// \kempston_auto_fire_counter[1]~17_combout = (kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] $ (VCC))) # (!kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] & VCC)) +// \kempston_auto_fire_counter[1]~18 = CARRY((kempston_auto_fire_counter[0] & kempston_auto_fire_counter[1])) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\kempston_auto_fire_counter[1]~17_combout ), + .cout(\kempston_auto_fire_counter[1]~18 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1]~17 .lut_mask = 16'h6688; +defparam \kempston_auto_fire_counter[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N17 +dffeas \kempston_auto_fire_counter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[1]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[1]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N18 +cycloneive_lcell_comb \kempston_auto_fire_counter[2]~19 ( +// Equation(s): +// \kempston_auto_fire_counter[2]~19_combout = (kempston_auto_fire_counter[2] & (!\kempston_auto_fire_counter[1]~18 )) # (!kempston_auto_fire_counter[2] & ((\kempston_auto_fire_counter[1]~18 ) # (GND))) +// \kempston_auto_fire_counter[2]~20 = CARRY((!\kempston_auto_fire_counter[1]~18 ) # (!kempston_auto_fire_counter[2])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[1]~18 ), + .combout(\kempston_auto_fire_counter[2]~19_combout ), + .cout(\kempston_auto_fire_counter[2]~20 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2]~19 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[2]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N19 +dffeas \kempston_auto_fire_counter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[2]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \kempston_auto_fire_counter[3]~21 ( +// Equation(s): +// \kempston_auto_fire_counter[3]~21_combout = (kempston_auto_fire_counter[3] & (\kempston_auto_fire_counter[2]~20 $ (GND))) # (!kempston_auto_fire_counter[3] & (!\kempston_auto_fire_counter[2]~20 & VCC)) +// \kempston_auto_fire_counter[3]~22 = CARRY((kempston_auto_fire_counter[3] & !\kempston_auto_fire_counter[2]~20 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[2]~20 ), + .combout(\kempston_auto_fire_counter[3]~21_combout ), + .cout(\kempston_auto_fire_counter[3]~22 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3]~21 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[3]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N21 +dffeas \kempston_auto_fire_counter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[3]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N22 +cycloneive_lcell_comb \kempston_auto_fire_counter[4]~23 ( +// Equation(s): +// \kempston_auto_fire_counter[4]~23_combout = (kempston_auto_fire_counter[4] & (!\kempston_auto_fire_counter[3]~22 )) # (!kempston_auto_fire_counter[4] & ((\kempston_auto_fire_counter[3]~22 ) # (GND))) +// \kempston_auto_fire_counter[4]~24 = CARRY((!\kempston_auto_fire_counter[3]~22 ) # (!kempston_auto_fire_counter[4])) + + .dataa(kempston_auto_fire_counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[3]~22 ), + .combout(\kempston_auto_fire_counter[4]~23_combout ), + .cout(\kempston_auto_fire_counter[4]~24 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4]~23 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[4]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N23 +dffeas \kempston_auto_fire_counter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[4]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N24 +cycloneive_lcell_comb \kempston_auto_fire_counter[5]~25 ( +// Equation(s): +// \kempston_auto_fire_counter[5]~25_combout = (kempston_auto_fire_counter[5] & (\kempston_auto_fire_counter[4]~24 $ (GND))) # (!kempston_auto_fire_counter[5] & (!\kempston_auto_fire_counter[4]~24 & VCC)) +// \kempston_auto_fire_counter[5]~26 = CARRY((kempston_auto_fire_counter[5] & !\kempston_auto_fire_counter[4]~24 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[4]~24 ), + .combout(\kempston_auto_fire_counter[5]~25_combout ), + .cout(\kempston_auto_fire_counter[5]~26 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5]~25 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[5]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N25 +dffeas \kempston_auto_fire_counter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[5]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N26 +cycloneive_lcell_comb \kempston_auto_fire_counter[6]~27 ( +// Equation(s): +// \kempston_auto_fire_counter[6]~27_combout = (kempston_auto_fire_counter[6] & (!\kempston_auto_fire_counter[5]~26 )) # (!kempston_auto_fire_counter[6] & ((\kempston_auto_fire_counter[5]~26 ) # (GND))) +// \kempston_auto_fire_counter[6]~28 = CARRY((!\kempston_auto_fire_counter[5]~26 ) # (!kempston_auto_fire_counter[6])) + + .dataa(kempston_auto_fire_counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[5]~26 ), + .combout(\kempston_auto_fire_counter[6]~27_combout ), + .cout(\kempston_auto_fire_counter[6]~28 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6]~27 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[6]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N27 +dffeas \kempston_auto_fire_counter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[6]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N28 +cycloneive_lcell_comb \kempston_auto_fire_counter[7]~29 ( +// Equation(s): +// \kempston_auto_fire_counter[7]~29_combout = (kempston_auto_fire_counter[7] & (\kempston_auto_fire_counter[6]~28 $ (GND))) # (!kempston_auto_fire_counter[7] & (!\kempston_auto_fire_counter[6]~28 & VCC)) +// \kempston_auto_fire_counter[7]~30 = CARRY((kempston_auto_fire_counter[7] & !\kempston_auto_fire_counter[6]~28 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[6]~28 ), + .combout(\kempston_auto_fire_counter[7]~29_combout ), + .cout(\kempston_auto_fire_counter[7]~30 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7]~29 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[7]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N29 +dffeas \kempston_auto_fire_counter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[7]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \kempston_auto_fire_counter[8]~31 ( +// Equation(s): +// \kempston_auto_fire_counter[8]~31_combout = (kempston_auto_fire_counter[8] & (!\kempston_auto_fire_counter[7]~30 )) # (!kempston_auto_fire_counter[8] & ((\kempston_auto_fire_counter[7]~30 ) # (GND))) +// \kempston_auto_fire_counter[8]~32 = CARRY((!\kempston_auto_fire_counter[7]~30 ) # (!kempston_auto_fire_counter[8])) + + .dataa(kempston_auto_fire_counter[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[7]~30 ), + .combout(\kempston_auto_fire_counter[8]~31_combout ), + .cout(\kempston_auto_fire_counter[8]~32 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8]~31 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[8]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N31 +dffeas \kempston_auto_fire_counter[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[8]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \kempston_auto_fire_counter[9]~33 ( +// Equation(s): +// \kempston_auto_fire_counter[9]~33_combout = (kempston_auto_fire_counter[9] & (\kempston_auto_fire_counter[8]~32 $ (GND))) # (!kempston_auto_fire_counter[9] & (!\kempston_auto_fire_counter[8]~32 & VCC)) +// \kempston_auto_fire_counter[9]~34 = CARRY((kempston_auto_fire_counter[9] & !\kempston_auto_fire_counter[8]~32 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[9]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[8]~32 ), + .combout(\kempston_auto_fire_counter[9]~33_combout ), + .cout(\kempston_auto_fire_counter[9]~34 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9]~33 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[9]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N1 +dffeas \kempston_auto_fire_counter[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[9]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \kempston_auto_fire_counter[10]~35 ( +// Equation(s): +// \kempston_auto_fire_counter[10]~35_combout = (kempston_auto_fire_counter[10] & (!\kempston_auto_fire_counter[9]~34 )) # (!kempston_auto_fire_counter[10] & ((\kempston_auto_fire_counter[9]~34 ) # (GND))) +// \kempston_auto_fire_counter[10]~36 = CARRY((!\kempston_auto_fire_counter[9]~34 ) # (!kempston_auto_fire_counter[10])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[9]~34 ), + .combout(\kempston_auto_fire_counter[10]~35_combout ), + .cout(\kempston_auto_fire_counter[10]~36 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10]~35 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[10]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N3 +dffeas \kempston_auto_fire_counter[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[10]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N4 +cycloneive_lcell_comb \kempston_auto_fire_counter[11]~37 ( +// Equation(s): +// \kempston_auto_fire_counter[11]~37_combout = (kempston_auto_fire_counter[11] & (\kempston_auto_fire_counter[10]~36 $ (GND))) # (!kempston_auto_fire_counter[11] & (!\kempston_auto_fire_counter[10]~36 & VCC)) +// \kempston_auto_fire_counter[11]~38 = CARRY((kempston_auto_fire_counter[11] & !\kempston_auto_fire_counter[10]~36 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[10]~36 ), + .combout(\kempston_auto_fire_counter[11]~37_combout ), + .cout(\kempston_auto_fire_counter[11]~38 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11]~37 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[11]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N5 +dffeas \kempston_auto_fire_counter[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[11]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \kempston_auto_fire_counter[12]~39 ( +// Equation(s): +// \kempston_auto_fire_counter[12]~39_combout = (kempston_auto_fire_counter[12] & (!\kempston_auto_fire_counter[11]~38 )) # (!kempston_auto_fire_counter[12] & ((\kempston_auto_fire_counter[11]~38 ) # (GND))) +// \kempston_auto_fire_counter[12]~40 = CARRY((!\kempston_auto_fire_counter[11]~38 ) # (!kempston_auto_fire_counter[12])) + + .dataa(kempston_auto_fire_counter[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[11]~38 ), + .combout(\kempston_auto_fire_counter[12]~39_combout ), + .cout(\kempston_auto_fire_counter[12]~40 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12]~39 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[12]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N7 +dffeas \kempston_auto_fire_counter[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[12]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N8 +cycloneive_lcell_comb \kempston_auto_fire_counter[13]~41 ( +// Equation(s): +// \kempston_auto_fire_counter[13]~41_combout = (kempston_auto_fire_counter[13] & (\kempston_auto_fire_counter[12]~40 $ (GND))) # (!kempston_auto_fire_counter[13] & (!\kempston_auto_fire_counter[12]~40 & VCC)) +// \kempston_auto_fire_counter[13]~42 = CARRY((kempston_auto_fire_counter[13] & !\kempston_auto_fire_counter[12]~40 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[12]~40 ), + .combout(\kempston_auto_fire_counter[13]~41_combout ), + .cout(\kempston_auto_fire_counter[13]~42 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13]~41 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[13]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N9 +dffeas \kempston_auto_fire_counter[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[13]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N10 +cycloneive_lcell_comb \kempston_auto_fire_counter[14]~43 ( +// Equation(s): +// \kempston_auto_fire_counter[14]~43_combout = (kempston_auto_fire_counter[14] & (!\kempston_auto_fire_counter[13]~42 )) # (!kempston_auto_fire_counter[14] & ((\kempston_auto_fire_counter[13]~42 ) # (GND))) +// \kempston_auto_fire_counter[14]~44 = CARRY((!\kempston_auto_fire_counter[13]~42 ) # (!kempston_auto_fire_counter[14])) + + .dataa(kempston_auto_fire_counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[13]~42 ), + .combout(\kempston_auto_fire_counter[14]~43_combout ), + .cout(\kempston_auto_fire_counter[14]~44 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14]~43 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[14]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N11 +dffeas \kempston_auto_fire_counter[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[14]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[15]~45 ( +// Equation(s): +// \kempston_auto_fire_counter[15]~45_combout = (kempston_auto_fire_counter[15] & (\kempston_auto_fire_counter[14]~44 $ (GND))) # (!kempston_auto_fire_counter[15] & (!\kempston_auto_fire_counter[14]~44 & VCC)) +// \kempston_auto_fire_counter[15]~46 = CARRY((kempston_auto_fire_counter[15] & !\kempston_auto_fire_counter[14]~44 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[14]~44 ), + .combout(\kempston_auto_fire_counter[15]~45_combout ), + .cout(\kempston_auto_fire_counter[15]~46 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15]~45 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[15]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \kempston_auto_fire_counter[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[15]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \Equal2~3 ( +// Equation(s): +// \Equal2~3_combout = (!kempston_auto_fire_counter[14] & (!kempston_auto_fire_counter[15] & (!kempston_auto_fire_counter[13] & !kempston_auto_fire_counter[12]))) + + .dataa(kempston_auto_fire_counter[14]), + .datab(kempston_auto_fire_counter[15]), + .datac(kempston_auto_fire_counter[13]), + .datad(kempston_auto_fire_counter[12]), + .cin(gnd), + .combout(\Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~3 .lut_mask = 16'h0001; +defparam \Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \Equal2~2 ( +// Equation(s): +// \Equal2~2_combout = (!kempston_auto_fire_counter[8] & (!kempston_auto_fire_counter[9] & (!kempston_auto_fire_counter[11] & !kempston_auto_fire_counter[10]))) + + .dataa(kempston_auto_fire_counter[8]), + .datab(kempston_auto_fire_counter[9]), + .datac(kempston_auto_fire_counter[11]), + .datad(kempston_auto_fire_counter[10]), + .cin(gnd), + .combout(\Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~2 .lut_mask = 16'h0001; +defparam \Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N10 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!kempston_auto_fire_counter[0] & (!kempston_auto_fire_counter[1] & (!kempston_auto_fire_counter[3] & !kempston_auto_fire_counter[2]))) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(kempston_auto_fire_counter[3]), + .datad(kempston_auto_fire_counter[2]), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N0 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!kempston_auto_fire_counter[4] & (!kempston_auto_fire_counter[5] & (!kempston_auto_fire_counter[6] & !kempston_auto_fire_counter[7]))) + + .dataa(kempston_auto_fire_counter[4]), + .datab(kempston_auto_fire_counter[5]), + .datac(kempston_auto_fire_counter[6]), + .datad(kempston_auto_fire_counter[7]), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0001; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \Equal2~4 ( +// Equation(s): +// \Equal2~4_combout = (\Equal2~3_combout & (\Equal2~2_combout & (\Equal2~0_combout & \Equal2~1_combout ))) + + .dataa(\Equal2~3_combout ), + .datab(\Equal2~2_combout ), + .datac(\Equal2~0_combout ), .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[4]~110_combout ), + .combout(\Equal2~4_combout ), .cout()); // synopsys translate_off -defparam \D[4]~110 .lut_mask = 16'hB8FF; -defparam \D[4]~110 .sum_lutc_input = "datac"; +defparam \Equal2~4 .lut_mask = 16'h8000; +defparam \Equal2~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N4 -cycloneive_lcell_comb \D[4]~111 ( +// Location: LCCOMB_X18_Y12_N14 +cycloneive_lcell_comb \kempston_auto_fire_counter[16]~47 ( // Equation(s): -// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) +// \kempston_auto_fire_counter[16]~47_combout = (kempston_auto_fire_counter[16] & (!\kempston_auto_fire_counter[15]~46 )) # (!kempston_auto_fire_counter[16] & ((\kempston_auto_fire_counter[15]~46 ) # (GND))) +// \kempston_auto_fire_counter[16]~48 = CARRY((!\kempston_auto_fire_counter[15]~46 ) # (!kempston_auto_fire_counter[16])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[15]~46 ), + .combout(\kempston_auto_fire_counter[16]~47_combout ), + .cout(\kempston_auto_fire_counter[16]~48 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16]~47 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[16]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N15 +dffeas \kempston_auto_fire_counter[16] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[16]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[17]~49 ( +// Equation(s): +// \kempston_auto_fire_counter[17]~49_combout = \kempston_auto_fire_counter[16]~48 $ (!kempston_auto_fire_counter[17]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(kempston_auto_fire_counter[17]), + .cin(\kempston_auto_fire_counter[16]~48 ), + .combout(\kempston_auto_fire_counter[17]~49_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17]~49 .lut_mask = 16'hF00F; +defparam \kempston_auto_fire_counter[17]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N17 +dffeas \kempston_auto_fire_counter[17] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[17]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N26 +cycloneive_lcell_comb \kempston_auto_fire~0 ( +// Equation(s): +// \kempston_auto_fire~0_combout = \kempston_auto_fire~q $ (((\Equal2~4_combout & (!kempston_auto_fire_counter[16] & !kempston_auto_fire_counter[17])))) + + .dataa(\Equal2~4_combout ), + .datab(kempston_auto_fire_counter[16]), + .datac(\kempston_auto_fire~q ), + .datad(kempston_auto_fire_counter[17]), + .cin(gnd), + .combout(\kempston_auto_fire~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire~0 .lut_mask = 16'hF0D2; +defparam \kempston_auto_fire~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N27 +dffeas kempston_auto_fire( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\kempston_autofire_enabled~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_auto_fire~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_auto_fire.is_wysiwyg = "true"; +defparam kempston_auto_fire.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \Selector6~2 ( +// Equation(s): +// \Selector6~2_combout = (\Selector14~18_combout & (((\kempston_auto_fire~q & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row[4]~16_combout ) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .datab(\Selector14~18_combout ), + .datac(\kempston_auto_fire~q ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~2 .lut_mask = 16'hE233; +defparam \Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~116 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~117_combout = (\ula_|zx_keyboard_|keys[5][4]~116_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[5][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~116_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~117 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [6])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~118 .lut_mask = 16'h4242; +defparam \ula_|zx_keyboard_|keys[4][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~119_combout = (\ula_|zx_keyboard_|keys[4][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~119 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~120_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~119_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~119_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~120 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~17_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~17 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~121 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~133_combout = (\ula_|zx_keyboard_|keys[3][4]~121_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~133 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[3][4]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~122_combout = (\ula_|zx_keyboard_|keys[3][4]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & +// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~133_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .datab(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~122 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N1 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hBBAA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~124_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~123_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~124 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~125_combout = (\ula_|zx_keyboard_|keys[2][4]~124_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~124_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~125 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \Selector6~3 ( +// Equation(s): +// \Selector6~3_combout = (\ula_|zx_keyboard_|keys[3][4]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~3 .lut_mask = 16'hDD0D; +defparam \Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~126_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~126 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~127_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N19 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y23_N8 +cycloneive_lcell_comb \Selector6~4 ( +// Equation(s): +// \Selector6~4_combout = (\ula_|zx_keyboard_|keys[1][4]~q & (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[1][4]~q & +// (((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~4 .lut_mask = 16'hDD0D; +defparam \Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \Selector6~5 ( +// Equation(s): +// \Selector6~5_combout = ((\ula_|zx_keyboard_|key_row[4]~17_combout & (\Selector6~3_combout & \Selector6~4_combout ))) # (!\Selector14~17_combout ) + + .dataa(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .datab(\Selector14~17_combout ), + .datac(\Selector6~3_combout ), + .datad(\Selector6~4_combout ), + .cin(gnd), + .combout(\Selector6~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~5 .lut_mask = 16'hB333; +defparam \Selector6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y34_N15 +cycloneive_io_ibuf \kempston[4]~input ( + .i(kempston[4]), + .ibar(gnd), + .o(\kempston[4]~input_o )); +// synopsys translate_off +defparam \kempston[4]~input .bus_hold = "false"; +defparam \kempston[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \Selector6~6 ( +// Equation(s): +// \Selector6~6_combout = (\Selector6~2_combout & ((\Selector14~18_combout & ((!\kempston[4]~input_o ))) # (!\Selector14~18_combout & (\Selector6~5_combout )))) + + .dataa(\Selector6~2_combout ), + .datab(\Selector6~5_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[4]~input_o ), + .cin(gnd), + .combout(\Selector6~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~6 .lut_mask = 16'h08A8; +defparam \Selector6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \Selector6~7 ( +// Equation(s): +// \Selector6~7_combout = (\Equal5~0_combout & (((\Selector6~6_combout )))) # (!\Equal5~0_combout & ((\Selector6~6_combout & (\Selector6~1_combout )) # (!\Selector6~6_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout +// ))))) + + .dataa(\Selector6~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector6~6_combout ), + .cin(gnd), + .combout(\Selector6~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~7 .lut_mask = 16'hEE30; +defparam \Selector6~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[4]~39 ( +// Equation(s): +// \D[4]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector6~7_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[4]~110_combout ), - .datad(\z80_|data_pins_|dout [4]), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), - .combout(\D[4]~111_combout ), + .combout(\D[4]~39_combout ), .cout()); // synopsys translate_off -defparam \D[4]~111 .lut_mask = 16'hF151; -defparam \D[4]~111 .sum_lutc_input = "datac"; +defparam \D[4]~39 .lut_mask = 16'hDD0D; +defparam \D[4]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N10 +// Location: LCCOMB_X26_Y16_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & -// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~39_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) # (!\D[4]~39_combout & +// (((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) - .dataa(\D[4]~111_combout ), + .dataa(\D[4]~39_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -51570,7 +51913,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N11 +// Location: FF_X26_Y16_N25 dffeas \z80_|data_pins_|dout[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), @@ -51589,145 +51932,3743 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N18 +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~17 ( +// Equation(s): +// \z80_|bus_control_|db[4]~17_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [4]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~17 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[4]~18_combout = ((\z80_|bus_control_|db[4]~17_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~17_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( // Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[4]~18_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N23 -dffeas \z80_|ir_|opcode[4] ( +// Location: FF_X27_Y12_N15 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[4]~19_combout ), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [4]), + .q(\z80_|interrupts_|im2~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|DFFE_inst44~q & \z80_|interrupts_|im2~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [1] = (\z80_|bus_control_|db[1]~10_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~3_combout = (\z80_|reg_file_|gdfx_temp0[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~3 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~20 ( +// Equation(s): +// \z80_|alu_control_|db[1]~20_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~20 .lut_mask = 16'h88CC; +defparam \z80_|alu_control_|db[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~21 ( +// Equation(s): +// \z80_|alu_control_|db[1]~21_combout = (\z80_|reg_file_|db_lo_ds[1]~3_combout & (\z80_|alu_control_|db[1]~20_combout & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|db[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~21 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~22 ( +// Equation(s): +// \z80_|alu_control_|db[1]~22_combout = ((\z80_|alu_control_|db[1]~21_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .datab(\z80_|alu_control_|db[1]~21_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~22 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~9 ( +// Equation(s): +// \z80_|bus_control_|db[1]~9_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|alu_control_|db[1]~22_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~9 .lut_mask = 16'hA0F0; +defparam \z80_|bus_control_|db[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[5][1]~33_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~2_combout = (\ula_|zx_keyboard_|keys[5][1]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~2 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][1]~q )))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N5 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~1_combout = (\z80_|address_pins_|abus[10]~19_combout & (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~q ))) # (!\z80_|address_pins_|abus[10]~19_combout & (!\ula_|zx_keyboard_|keys[2][1]~q +// & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~1 .lut_mask = 16'hA2F3; +defparam \ula_|zx_keyboard_|key_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~38 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg +// [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0210; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr16~2_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h8B88; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & ((\ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hE2C0; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~39_combout = (\ula_|zx_keyboard_|keys[7][1]~38_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|WideOr16~6_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) # +// (!\ula_|zx_keyboard_|keys[7][1]~38_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~39 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hFCCC; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~42_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~3_combout = (\z80_|address_pins_|abus[15]~23_combout & (((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][1]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~3 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & (!\ula_|zx_keyboard_|keys[0][1]~12_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][4]~18_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N25 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~0_combout = (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~16_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & +// ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~16_combout ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~0 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [1] = (\ula_|zx_keyboard_|key_row[1]~2_combout & (\ula_|zx_keyboard_|key_row[1]~1_combout & (\ula_|zx_keyboard_|key_row[1]~3_combout & \ula_|zx_keyboard_|key_row[1]~0_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .datab(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .datac(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .datad(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [1]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y34_N1 +cycloneive_io_ibuf \kempston[2]~input ( + .i(kempston[2]), + .ibar(gnd), + .o(\kempston[2]~input_o )); +// synopsys translate_off +defparam \kempston[2]~input .bus_hold = "false"; +defparam \kempston[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \Selector12~4 ( +// Equation(s): +// \Selector12~4_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[2]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [1])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [1]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[2]~input_o ), + .cin(gnd), + .combout(\Selector12~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~4 .lut_mask = 16'h0BCB; +defparam \Selector12~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \Selector12~10 ( +// Equation(s): +// \Selector12~10_combout = (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector12~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~10 .lut_mask = 16'hFFCF; +defparam \Selector12~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \Selector12~7 ( +// Equation(s): +// \Selector12~7_combout = (\Selector12~4_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\Selector12~4_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\Selector12~4_combout ), + .cin(gnd), + .combout(\Selector12~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~7 .lut_mask = 16'hEEF0; +defparam \Selector12~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \Selector12~8 ( +// Equation(s): +// \Selector12~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\Selector12~7_combout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\Selector12~7_combout ), + .cin(gnd), + .combout(\Selector12~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~8 .lut_mask = 16'hAFA0; +defparam \Selector12~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \Selector12~9 ( +// Equation(s): +// \Selector12~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\Selector12~8_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a +// [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector12~8_combout ), + .cin(gnd), + .combout(\Selector12~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~9 .lut_mask = 16'hFE0E; +defparam \Selector12~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \Selector12~15 ( +// Equation(s): +// \Selector12~15_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~15_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~15 .lut_mask = 16'hF2D0; +defparam \Selector12~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \Selector12~5 ( +// Equation(s): +// \Selector12~5_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector12~15_combout )) # (!\Selector12~4_combout ))) + + .dataa(\Equal5~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector12~4_combout ), + .datad(\Selector12~15_combout ), + .cin(gnd), + .combout(\Selector12~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~5 .lut_mask = 16'hB5A5; +defparam \Selector12~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \Selector12~14 ( +// Equation(s): +// \Selector12~14_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\Selector12~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~14 .lut_mask = 16'hF2D0; +defparam \Selector12~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \Selector12~6 ( +// Equation(s): +// \Selector12~6_combout = (\Selector12~5_combout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\Selector12~4_combout & \Selector12~14_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Selector12~4_combout ), + .datac(\Selector12~5_combout ), + .datad(\Selector12~14_combout ), + .cin(gnd), + .combout(\Selector12~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~6 .lut_mask = 16'hF8F0; +defparam \Selector12~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \Selector12~11 ( +// Equation(s): +// \Selector12~11_combout = (\Selector12~6_combout & ((\Selector12~4_combout ) # ((\Selector12~10_combout & \Selector12~9_combout )))) + + .dataa(\Selector12~4_combout ), + .datab(\Selector12~10_combout ), + .datac(\Selector12~9_combout ), + .datad(\Selector12~6_combout ), + .cin(gnd), + .combout(\Selector12~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~11 .lut_mask = 16'hEA00; +defparam \Selector12~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[1]~12 ( +// Equation(s): +// \D[1]~12_combout = (\Equal5~1_combout & (\Selector12~11_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout +// )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector12~11_combout ), + .cin(gnd), + .combout(\D[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~12 .lut_mask = 16'hCF45; +defparam \D[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~12_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[1]~10_combout )))) # (!\D[1]~12_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[1]~10_combout ))) + + .dataa(\D[1]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N17 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = ((\z80_|bus_control_|db[1]~9_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[1]~9_combout ), + .datab(\z80_|bus_control_|db[0]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB3B; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[1]~10_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(\z80_|ir_|opcode [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|iff1~q ))))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal79~0_combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFCF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N26 +// Location: LCCOMB_X29_Y17_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) +// \z80_|interrupts_|test1~2_combout = ((\z80_|ir_|opcode [5] & ((!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|ir_|opcode [5] & (!\z80_|pla_decode_|Equal2~2_combout ))) # (!\z80_|pla_decode_|Equal2~3_combout ) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal43~0_combout ), + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h3F77; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N30 +// Location: LCCOMB_X29_Y14_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (\z80_|interrupts_|test1~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & ((!\z80_|pla_decode_|Equal3~2_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h002A; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N7 +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|interrupts_|test1~4 ( +// Equation(s): +// \z80_|interrupts_|test1~4_combout = (!\z80_|execute_|setM1~55_combout & ((\z80_|interrupts_|test1~3_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~4 .lut_mask = 16'h3323; +defparam \z80_|interrupts_|test1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_inst44~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(gnd), + .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datac(\z80_|clk_delay_|DFF_inst5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0303; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|execute_|setM1~55_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h5000; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N11 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~2 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~3 ( +// Equation(s): +// \z80_|bus_control_|db[0]~3_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~2_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~3 .lut_mask = 16'hAEAF; +defparam \z80_|bus_control_|db[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \Selector8~5 ( +// Equation(s): +// \Selector8~5_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~5 .lut_mask = 16'hCBC8; +defparam \Selector8~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \Selector8~6 ( +// Equation(s): +// \Selector8~6_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~5_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~5_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~5_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~5_combout ), + .cin(gnd), + .combout(\Selector8~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~6 .lut_mask = 16'hF388; +defparam \Selector8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \Selector8~7 ( +// Equation(s): +// \Selector8~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\Selector8~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~7 .lut_mask = 16'hAEA4; +defparam \Selector8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \Selector8~8 ( +// Equation(s): +// \Selector8~8_combout = (\Selector8~7_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\Selector8~7_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\Selector8~7_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector8~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~8 .lut_mask = 16'hACF0; +defparam \Selector8~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~134_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[0][0]~13_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [3]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~134 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~135_combout = (\ula_|zx_keyboard_|keys[6][3]~134_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~134_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~15_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][3]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~15 .lut_mask = 16'hBB0B; +defparam \ula_|zx_keyboard_|key_row[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[0][3]~94_combout & ((!\ula_|zx_keyboard_|keys[2][4]~93_combout ))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N27 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~12_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// ((\z80_|address_pins_|abus[9]~16_combout ) # ((!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~12 .lut_mask = 16'hCF45; +defparam \ula_|zx_keyboard_|key_row[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h00A0; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~46_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N23 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[2][3]~100_combout & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[2][3]~101_combout & ((\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|zx_keyboard_|keys[2][3]~99_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & +// ((\ula_|zx_keyboard_|keys[2][3]~q ))))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N15 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~13_combout = (\ula_|zx_keyboard_|keys[3][3]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[3][3]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~13 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~76_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~131_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|Selector5~1_combout ), + .datad(\ula_|zx_keyboard_|Selector5~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~131 .lut_mask = 16'hFF20; +defparam \ula_|zx_keyboard_|keys[4][3]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~105_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~131_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hB888; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|shifted~q & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hCCDC; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[4][3]~106_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & ((!\ula_|zx_keyboard_|keys[4][3]~132_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~103_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~14_combout = (\ula_|zx_keyboard_|keys[4][3]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~14 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [3] = (\ula_|zx_keyboard_|key_row[3]~15_combout & (\ula_|zx_keyboard_|key_row[3]~12_combout & (\ula_|zx_keyboard_|key_row[3]~13_combout & \ula_|zx_keyboard_|key_row[3]~14_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .datab(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .datac(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .datad(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [3]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y34_N1 +cycloneive_io_ibuf \kempston[0]~input ( + .i(kempston[0]), + .ibar(gnd), + .o(\kempston[0]~input_o )); +// synopsys translate_off +defparam \kempston[0]~input .bus_hold = "false"; +defparam \kempston[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \Selector8~4 ( +// Equation(s): +// \Selector8~4_combout = (\Selector14~18_combout & (\Selector14~17_combout & ((!\kempston[0]~input_o )))) # (!\Selector14~18_combout & (((\ula_|zx_keyboard_|key_row [3])) # (!\Selector14~17_combout ))) + + .dataa(\Selector14~18_combout ), + .datab(\Selector14~17_combout ), + .datac(\ula_|zx_keyboard_|key_row [3]), + .datad(\kempston[0]~input_o ), + .cin(gnd), + .combout(\Selector8~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~4 .lut_mask = 16'h51D9; +defparam \Selector8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \Selector8~9 ( +// Equation(s): +// \Selector8~9_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & (\Selector8~6_combout )) # (!\Selector8~4_combout & ((\Selector8~8_combout ))))) + + .dataa(\Selector8~6_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector8~8_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\Selector8~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~9 .lut_mask = 16'hEE30; +defparam \Selector8~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[3]~38 ( +// Equation(s): +// \D[3]~38_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector8~9_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), + .cin(gnd), + .combout(\D[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~38 .lut_mask = 16'hDD0D; +defparam \D[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\D[3]~38_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[3]~20_combout )))) # (!\D[3]~38_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[3]~20_combout ))) + + .dataa(\D[3]~38_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N31 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~19 ( +// Equation(s): +// \z80_|bus_control_|db[3]~19_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~19 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = ((\z80_|bus_control_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[3]~19_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[0]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|ir_|opcode[3]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[3]~feeder_combout = \z80_|bus_control_|db[3]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N13 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = (!\z80_|execute_|ctl_alu_op_low~11_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|pla_decode_|Equal56~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|setM1~41_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~60 ( +// Equation(s): +// \z80_|execute_|setM1~60_combout = (\z80_|execute_|ctl_mRead~17_combout & (((\z80_|ir_|opcode [1]) # (\z80_|ir_|opcode [2])) # (!\z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|setM1~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~60 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|setM1~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~60_combout ) # (!\z80_|execute_|setM1~42_combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~60_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~17 ( +// Equation(s): +// \z80_|execute_|nextM~17_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|fMRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~17 .lut_mask = 16'hA020; +defparam \z80_|execute_|nextM~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|nextM~5_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = ((\z80_|execute_|nextM~7_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|nextM~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|nextM~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hA080; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = (\z80_|execute_|nextM~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|nextM~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~17_combout ) # ((\z80_|execute_|nextM~8_combout ) # (\z80_|execute_|nextM~13_combout )) + + .dataa(\z80_|execute_|nextM~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|nextM~8_combout ), + .datad(\z80_|execute_|nextM~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|execute_|nextM~6_combout ) # (((\z80_|execute_|nextM~14_combout ) # (!\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ctl_mWrite~15_combout )) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|setM1~55_combout )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h1010; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N23 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FC; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N14 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y11_N25 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -51736,7 +55677,7 @@ dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .ena(\z80_|interrupts_|test1~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), @@ -51746,115 +55687,363 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X26_Y11_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|interrupts_|im1~feeder ( // Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) +// \z80_|interrupts_|im1~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), + .combout(\z80_|interrupts_|im1~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|im1~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|im1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & -// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N3 -dffeas \z80_|alu_flags_|flags_yf ( +// Location: FF_X27_Y12_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .d(\z80_|interrupts_|im1~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & -// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_yf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .dataa(\z80_|interrupts_|im1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|interrupts_|im2~q ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( // Equation(s): -// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~4_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|alu_control_|db[5]~15_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~16_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~5 ( // Equation(s): -// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) +// \z80_|bus_control_|db[0]~5_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_zero_oe~3_combout ))) - .dataa(\z80_|alu_control_|db[5]~16_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[0]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~5 .lut_mask = 16'hFFFE; +defparam \z80_|bus_control_|db[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y24_N0 +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hEE30; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51862,16 +56051,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51925,7 +56114,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y33_N0 +// Location: M9K_X33_Y6_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -51935,16 +56124,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51983,9 +56172,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51993,16 +56182,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -52055,7 +56244,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -52065,16 +56254,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -52113,361 +56302,112 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N2 -cycloneive_lcell_comb \Mux2~0 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), - .combout(\Mux2~0_combout ), + .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hB9A8; -defparam \Mux2~0 .sum_lutc_input = "datac"; +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \Mux2~1 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \Selector4~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Selector4~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), + .datad(\Selector4~0_combout ), .cin(gnd), - .combout(\Mux2~1_combout ), + .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; +defparam \Selector4~1 .lut_mask = 16'hDDA0; +defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \D[5]~25 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) +// \D[5]~25_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector4~1_combout ))))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datad(\Selector4~1_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .combout(\D[5]~25_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +defparam \D[5]~25 .lut_mask = 16'h3120; +defparam \D[5]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \D[5]~27 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) +// \D[5]~27_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~25_combout )) # (!\D[5]~26_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~25_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~26_combout ), + .datac(\D[5]~25_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\D[5]~27_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \D[5]~27 .lut_mask = 16'hA2F3; +defparam \D[5]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N30 -cycloneive_lcell_comb \D[5]~112 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[5]~40 ( // Equation(s): -// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) +// \D[5]~40_combout = (\D[5]~27_combout ) # (!\D[0]~49_combout ) - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[5]~97_combout ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[5]~27_combout ), .cin(gnd), - .combout(\D[5]~112_combout ), + .combout(\D[5]~40_combout ), .cout()); // synopsys translate_off -defparam \D[5]~112 .lut_mask = 16'hFB73; -defparam \D[5]~112 .sum_lutc_input = "datac"; +defparam \D[5]~40 .lut_mask = 16'hFF33; +defparam \D[5]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N8 -cycloneive_lcell_comb \D[5]~113 ( -// Equation(s): -// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[5]~112_combout ), - .datad(\z80_|data_pins_|dout [5]), - .cin(gnd), - .combout(\D[5]~113_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~113 .lut_mask = 16'hF151; -defparam \D[5]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 +// Location: LCCOMB_X26_Y16_N18 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~40_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[5]~16_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[5]~40_combout & (\z80_|bus_control_|db[5]~16_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[5]~113_combout ), + .dataa(\D[5]~40_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N25 +// Location: FF_X26_Y16_N19 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -52486,50 +56426,50 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|data_pins_|dout [5]), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N24 +// Location: LCCOMB_X26_Y15_N16 cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|alu_control_|db[5]~17_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[5]~14_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hA0AA; defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N25 +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Equation(s): +// \z80_|bus_control_|db[5]~16_combout = ((\z80_|bus_control_|db[5]~15_combout & ((\z80_|alu_control_|db[5]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N21 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~15_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~16_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [5]), @@ -52539,991 +56479,75 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) - - .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|nextM~3_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) - - .dataa(\z80_|execute_|nextM~7_combout ), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mWrite~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N23 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N27 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N31 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N21 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # -// (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~22_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|pla_decode_|Equal4~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) - - .dataa(\z80_|execute_|setM1~55_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~31_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|setM1~20_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~28_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & -// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|interrupts_|test1~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) - - .dataa(\z80_|execute_|setM1~8_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) - - .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~12_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N16 +// Location: LCCOMB_X31_Y15_N8 cycloneive_lcell_comb \z80_|execute_|setM1~43 ( // Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|setM1~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h1515; defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|setM1~42_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|execute_|setM1~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|setM1~50_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 +// Location: LCCOMB_X36_Y11_N28 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~55_combout )) - .dataa(gnd), + .dataa(\z80_|execute_|nextM~15_combout ), .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h4040; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N19 +// Location: FF_X36_Y11_N29 dffeas \z80_|sequencer_|T6 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), @@ -53542,59 +56566,625 @@ defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; defparam \z80_|sequencer_|T6 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( // Equation(s): -// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & -// (!\z80_|execute_|setM1~41_combout ))) +// \z80_|execute_|setM1~16_combout = (!\z80_|execute_|ctl_alu_oe~5_combout & (!\z80_|pla_decode_|Equal1~3_combout & (!\z80_|pla_decode_|Equal77~1_combout & !\z80_|pla_decode_|Equal2~4_combout ))) - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|sequencer_|T6~q ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|setM1~40_combout ), + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), + .combout(\z80_|execute_|setM1~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|interrupts_|test1~3_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~17_combout )) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h080C; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~13_combout & (\z80_|execute_|setM1~45_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|pla_decode_|Equal5~2_combout & \z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 cycloneive_lcell_comb \z80_|execute_|setM1~53 ( // Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|setM1~18_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|setM1~48_combout ))) - .dataa(\z80_|execute_|setM1~35_combout ), - .datab(\z80_|execute_|setM1~19_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~18_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~48_combout ), .cin(gnd), .combout(\z80_|execute_|setM1~53_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h8000; defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) +// \z80_|execute_|setM1~54_combout = (\z80_|execute_|setM1~43_combout & (((\z80_|execute_|setM1~42_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~43_combout & ((\z80_|sequencer_|T6~q ) # ((\z80_|execute_|setM1~42_combout & +// \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'hCCCE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~24_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hE0A0; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|fMWrite~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|setM1~57_combout & (((\z80_|execute_|ctl_reg_in_hi~6_combout & !\z80_|execute_|setM1~25_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~57_combout & +// (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|setM1~25_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (((\z80_|pla_decode_|Equal40~1_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~10_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & +// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|setM1~26_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~29_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hCCDC; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~13_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (((\z80_|execute_|setM1~31_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~32_combout )) # (!\z80_|execute_|setM1~58_combout ) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~32_combout ), + .datac(\z80_|execute_|setM1~31_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~34_combout ), + .datac(\z80_|execute_|setM1~35_combout ), + .datad(\z80_|execute_|setM1~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|execute_|ctl_mRead~9_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h2A0A; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout ) # ((\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|setM1~36_combout ) # ((\z80_|execute_|setM1~56_combout ) # (\z80_|execute_|setM1~23_combout ))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|setM1~56_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMWrite~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~12_combout ) # (((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|setM1~13_combout )) # (!\z80_|execute_|nextM~4_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|sequencer_|M5~q ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|execute_|ctl_sw_4d~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_M4_ff~q & +// (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCF0F; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|execute_|setM1~11_combout ) # (((\z80_|execute_|setM1~14_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~14_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|setM1~19_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~15_combout ) # (((!\z80_|execute_|setM1~18_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~20_combout )) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|setM1~20_combout ), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hBFBB; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|setM1~37_combout & (!\z80_|execute_|setM1~21_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~54_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h000B; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~15_combout ))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N15 +// Location: FF_X36_Y11_N7 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -53613,27 +57203,28 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & +// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hC1F0; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N29 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), +// Location: FF_X27_Y15_N23 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53642,65 +57233,156 @@ dffeas \z80_|sequencer_|DFFE_M2_ff ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .q(\z80_|resets_|clrpc_int~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y16_N20 +// Location: FF_X26_Y9_N3 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N5 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y9_N1 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y16_N21 +// Location: FF_X29_Y9_N17 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53719,332 +57401,561 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N30 -cycloneive_lcell_comb \D[0]~66 ( +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 ( // Equation(s): -// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[0]~58_combout ), - .datad(\D[0]~120_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~66_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cout()); // synopsys translate_off -defparam \D[0]~66 .lut_mask = 16'hF3C0; -defparam \D[0]~66 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N18 -cycloneive_lcell_comb \D[0]~67 ( +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 ( // Equation(s): -// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\Equal2~1_combout ), - .datad(\D[0]~66_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cin(gnd), - .combout(\D[0]~67_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), .cout()); // synopsys translate_off -defparam \D[0]~67 .lut_mask = 16'hDD0D; -defparam \D[0]~67 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .lut_mask = 16'hF388; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N24 -cycloneive_lcell_comb \D[0]~121 ( +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \Selector14~15 ( // Equation(s): -// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \Selector14~15_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # +// (!\z80_|address_pins_|abus[14]~22_combout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~121_combout ), + .combout(\Selector14~15_combout ), .cout()); // synopsys translate_off -defparam \D[0]~121 .lut_mask = 16'hFF20; -defparam \D[0]~121 .sum_lutc_input = "datac"; +defparam \Selector14~15 .lut_mask = 16'hBA98; +defparam \Selector14~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N16 -cycloneive_lcell_comb \D[1]~68 ( +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \Selector14~16 ( // Equation(s): -// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) +// \Selector14~16_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector14~15_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\Selector14~15_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector14~15_combout )))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[1]~34_combout ), - .datad(\D[1]~118_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\Selector14~15_combout ), .cin(gnd), - .combout(\D[1]~68_combout ), + .combout(\Selector14~16_combout ), .cout()); // synopsys translate_off -defparam \D[1]~68 .lut_mask = 16'hF3C0; -defparam \D[1]~68 .sum_lutc_input = "datac"; +defparam \Selector14~16 .lut_mask = 16'hBBC0; +defparam \Selector14~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N14 -cycloneive_lcell_comb \D[1]~69 ( +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \D[0]~15 ( // Equation(s): -// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) +// \D[0]~15_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & ((\Selector14~8_combout & ((\Selector14~16_combout ))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout +// )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), + .datac(\Selector14~16_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\D[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~15 .lut_mask = 16'hFA44; +defparam \D[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \D[0]~16 ( +// Equation(s): +// \D[0]~16_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~15_combout ) # (!\Equal5~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[0]~15_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Equal5~1_combout ), + .datad(\D[0]~15_combout ), + .cin(gnd), + .combout(\D[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~16 .lut_mask = 16'hBB0B; +defparam \D[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \Selector12~12 ( +// Equation(s): +// \Selector12~12_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~12_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~12 .lut_mask = 16'hD9C8; +defparam \Selector12~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N2 +cycloneive_lcell_comb \Selector12~13 ( +// Equation(s): +// \Selector12~13_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector12~12_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector12~12_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector12~12_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector12~12_combout ), + .cin(gnd), + .combout(\Selector12~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~13 .lut_mask = 16'hDDA0; +defparam \Selector12~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \D[1]~17 ( +// Equation(s): +// \D[1]~17_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & ((\Selector12~4_combout & ((\Selector12~13_combout ))) # (!\Selector12~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout +// )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .datac(\Selector12~4_combout ), + .datad(\Selector12~13_combout ), + .cin(gnd), + .combout(\D[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~17 .lut_mask = 16'hF4A4; +defparam \D[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \D[1]~18 ( +// Equation(s): +// \D[1]~18_combout = (\Equal5~1_combout & (\D[1]~17_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), .datab(\z80_|data_pins_|dout [1]), - .datac(\Equal2~1_combout ), - .datad(\D[1]~68_combout ), - .cin(gnd), - .combout(\D[1]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~69 .lut_mask = 16'hDD0D; -defparam \D[1]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N16 -cycloneive_lcell_comb \D[2]~70 ( -// Equation(s): -// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) - - .dataa(gnd), - .datab(\D[2]~46_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~70 .lut_mask = 16'hCFC0; -defparam \D[2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N14 -cycloneive_lcell_comb \D[2]~71 ( -// Equation(s): -// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~70_combout ), - .cin(gnd), - .combout(\D[2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~71 .lut_mask = 16'hF531; -defparam \D[2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N24 -cycloneive_lcell_comb \D[3]~83 ( -// Equation(s): -// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [3]), - .datad(gnd), - .cin(gnd), - .combout(\D[3]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~83 .lut_mask = 16'hF5F5; -defparam \D[3]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \D[3]~84 ( -// Equation(s): -// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) - - .dataa(\D[3]~122_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[3]~82_combout ), - .datad(\D[3]~83_combout ), - .cin(gnd), - .combout(\D[3]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~84 .lut_mask = 16'hFB00; -defparam \D[3]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N20 -cycloneive_lcell_comb \D[4]~95 ( -// Equation(s): -// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) - - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~95 .lut_mask = 16'hB8B8; -defparam \D[4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N6 -cycloneive_lcell_comb \D[4]~96 ( -// Equation(s): -// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\Equal2~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[4]~95_combout ), + .datad(\D[1]~17_combout ), .cin(gnd), - .combout(\D[4]~96_combout ), + .combout(\D[1]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~96 .lut_mask = 16'hAF23; -defparam \D[4]~96 .sum_lutc_input = "datac"; +defparam \D[1]~18 .lut_mask = 16'hCF45; +defparam \D[1]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N18 -cycloneive_lcell_comb \D[5]~126 ( +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \D[2]~19 ( // Equation(s): -// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) +// \D[2]~19_combout = (\Selector10~2_combout & (((\Selector10~1_combout ) # (\Equal5~0_combout )))) # (!\Selector10~2_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout & ((!\Equal5~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Selector10~2_combout ), + .datac(\Selector10~1_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~19 .lut_mask = 16'hCCE2; +defparam \D[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \D[2]~20 ( +// Equation(s): +// \D[2]~20_combout = (\Equal5~1_combout & (\D[2]~19_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [2]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [2]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[2]~19_combout ), + .cin(gnd), + .combout(\D[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~20 .lut_mask = 16'hCF45; +defparam \D[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \Selector8~2 ( +// Equation(s): +// \Selector8~2_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~2 .lut_mask = 16'hCBC8; +defparam \Selector8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \Selector8~3 ( +// Equation(s): +// \Selector8~3_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~2_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~2_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~2_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~2_combout ), + .cin(gnd), + .combout(\Selector8~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~3 .lut_mask = 16'hF388; +defparam \Selector8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[3]~21 ( +// Equation(s): +// \D[3]~21_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & ((\Selector8~3_combout ))) # (!\Selector8~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datac(\Selector8~3_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\D[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~21 .lut_mask = 16'hFA44; +defparam \D[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~22 ( +// Equation(s): +// \D[3]~22_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~21_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[3]~21_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[3]~21_combout ), + .cin(gnd), + .combout(\D[3]~22_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~22 .lut_mask = 16'hAF23; +defparam \D[3]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[4]~23 ( +// Equation(s): +// \D[4]~23_combout = (\Selector6~6_combout & ((\Selector6~1_combout ) # ((\Equal5~0_combout )))) # (!\Selector6~6_combout & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout & !\Equal5~0_combout )))) + + .dataa(\Selector6~1_combout ), + .datab(\Selector6~6_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~23 .lut_mask = 16'hCCB8; +defparam \D[4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[4]~24 ( +// Equation(s): +// \D[4]~24_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~23_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~23_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\D[4]~23_combout ), + .cin(gnd), + .combout(\D[4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~24 .lut_mask = 16'hDD0D; +defparam \D[4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[6]~32 ( +// Equation(s): +// \D[6]~32_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~32 .lut_mask = 16'hE3E0; +defparam \D[6]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[6]~33 ( +// Equation(s): +// \D[6]~33_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~32_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~32_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~32_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~32_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~33 .lut_mask = 16'hF838; +defparam \D[6]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \D[6]~29 ( +// Equation(s): +// \D[6]~29_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~29 .lut_mask = 16'hE6A2; +defparam \D[6]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[6]~30 ( +// Equation(s): +// \D[6]~30_combout = (\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~29_combout ))))) # (!\z80_|address_pins_|abus[15]~23_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~29_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~29_combout ), + .cin(gnd), + .combout(\D[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~30 .lut_mask = 16'h44B8; +defparam \D[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \D[6]~31 ( +// Equation(s): +// \D[6]~31_combout = (\D[6]~29_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~30_combout )))) # (!\D[6]~29_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~30_combout )))) + + .dataa(\D[6]~29_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~30_combout ), + .cin(gnd), + .combout(\D[6]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~31 .lut_mask = 16'h99A8; +defparam \D[6]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[6]~50 ( +// Equation(s): +// \D[6]~50_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~33_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~31_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~33_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .datac(\D[6]~33_combout ), + .datad(\D[6]~31_combout ), .cin(gnd), - .combout(\D[5]~126_combout ), + .combout(\D[6]~50_combout ), .cout()); // synopsys translate_off -defparam \D[5]~126 .lut_mask = 16'hFB40; -defparam \D[5]~126 .sum_lutc_input = "datac"; +defparam \D[6]~50 .lut_mask = 16'hF4B0; +defparam \D[6]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N0 -cycloneive_lcell_comb \D[5]~98 ( +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \D[6]~34 ( // Equation(s): -// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) +// \D[6]~34_combout = (\Equal5~0_combout & (\D[6]~28_combout & (\Equal3~2_combout ))) # (!\Equal5~0_combout & (((\D[6]~50_combout )))) - .dataa(\z80_|data_pins_|dout [5]), - .datab(\D[5]~97_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[5]~126_combout ), + .dataa(\D[6]~28_combout ), + .datab(\Equal3~2_combout ), + .datac(\Equal5~0_combout ), + .datad(\D[6]~50_combout ), .cin(gnd), - .combout(\D[5]~98_combout ), + .combout(\D[6]~34_combout ), .cout()); // synopsys translate_off -defparam \D[5]~98 .lut_mask = 16'hAF23; -defparam \D[5]~98 .sum_lutc_input = "datac"; +defparam \D[6]~34 .lut_mask = 16'h8F80; +defparam \D[6]~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N18 -cycloneive_lcell_comb \D[6]~105 ( +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[6]~35 ( // Equation(s): -// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) - - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~105 .lut_mask = 16'hFC30; -defparam \D[6]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N0 -cycloneive_lcell_comb \D[6]~106 ( -// Equation(s): -// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) +// \D[6]~35_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~34_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~34_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [6]), - .datab(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~105_combout ), + .datad(\D[6]~34_combout ), .cin(gnd), - .combout(\D[6]~106_combout ), + .combout(\D[6]~35_combout ), .cout()); // synopsys translate_off -defparam \D[6]~106 .lut_mask = 16'hAF23; -defparam \D[6]~106 .sum_lutc_input = "datac"; +defparam \D[6]~35 .lut_mask = 16'hAF23; +defparam \D[6]~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N10 -cycloneive_lcell_comb \D[7]~128 ( -// Equation(s): -// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~128_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~128 .lut_mask = 16'hF2D0; -defparam \D[7]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N16 -cycloneive_lcell_comb \D[7]~107 ( -// Equation(s): -// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[5]~97_combout ), - .datad(\D[7]~128_combout ), - .cin(gnd), - .combout(\D[7]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~107 .lut_mask = 16'hBB0B; -defparam \D[7]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 +// Location: LCCOMB_X36_Y11_N2 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; +defparam \z80_|nM1_int~3 .lut_mask = 16'hE0E0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N13 +// Location: FF_X36_Y11_N3 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -54063,7 +57974,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X26_Y12_N22 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -54080,7 +57991,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N5 +// Location: FF_X26_Y12_N23 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -54099,7 +58010,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N27 +// Location: FF_X26_Y12_N21 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -54118,32 +58029,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N26 +// Location: LCCOMB_X26_Y12_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|wait_mwr~q ), - .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .datab(\z80_|memory_ifc_|wait_mwr~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N2 +// Location: LCCOMB_X26_Y12_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ))) - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(\z80_|memory_ifc_|wait_mrd~q ), - .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -54165,7 +58076,24 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -54182,7 +58110,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X3_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -54201,14 +58129,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X3_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -54219,7 +58147,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N9 +// Location: FF_X3_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -54238,7 +58166,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X3_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -54256,7 +58184,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N11 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -54275,7 +58203,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X3_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -54293,7 +58221,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -54312,24 +58240,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) - - .dataa(\ula_|i2c_loader_|divider [3]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [1]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -54347,7 +58258,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -54366,7 +58277,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X3_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -54383,7 +58294,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X3_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -54402,60 +58313,41 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N30 +// Location: LCCOMB_X3_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), .datac(\ula_|i2c_loader_|divider [4]), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 -dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|scl_out~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N23 +// Location: FF_X1_Y23_N19 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -54474,7 +58366,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -54491,7 +58383,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -54510,24 +58402,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0CC0; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N31 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -54546,75 +58438,174 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: FF_X1_Y23_N5 +dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|scl_out~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N24 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hA0A0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~4_combout ), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; -defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEAAE; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X2_Y23_N15 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54633,67 +58624,135 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hCCC0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y22_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|state.Pause~0_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|nbit[0]~1_combout )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~0_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N27 +// Location: LCCOMB_X1_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|Mux42~0_combout & !\ula_|i2c_loader_|WideAnd0~combout ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0040; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~4_combout ), + .d(\ula_|i2c_loader_|nbit~5_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [0]), @@ -54703,43 +58762,7 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y25_N1 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y25_N28 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) @@ -54756,75 +58779,41 @@ defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 +// Location: LCCOMB_X2_Y22_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N4 +// Location: LCCOMB_X2_Y22_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|state~27_combout ), + .datab(\ula_|i2c_loader_|state~26_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), + .datad(\ula_|i2c_loader_|state~27_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X2_Y22_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54843,24 +58832,60 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N12 +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): // \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [1]), + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|nbit [2]), .datad(\ula_|i2c_loader_|nbit [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N13 +// Location: FF_X2_Y23_N13 dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~0_combout ), @@ -54869,7 +58894,7 @@ dffeas \ula_|i2c_loader_|nbit[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [2]), @@ -54879,32 +58904,32 @@ defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N30 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [0] & \ula_|i2c_loader_|state.Data~q ))) .dataa(\ula_|i2c_loader_|nbit [2]), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0100; defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N2 +// Location: LCCOMB_X2_Y22_N16 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Idle~0_combout ), .cout()); @@ -54913,7 +58938,7 @@ defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N16 +// Location: LCCOMB_X2_Y22_N6 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( // Equation(s): // \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) @@ -54930,25 +58955,25 @@ defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y22_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Ack~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N25 +// Location: FF_X2_Y22_N3 dffeas \ula_|i2c_loader_|state.Ack ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Ack~1_combout ), @@ -54967,121 +58992,24 @@ defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2c_loader_|nbyte~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) +// \ula_|i2c_loader_|state.Stop~0_combout = (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N6 +// Location: LCCOMB_X2_Y22_N4 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): // \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # @@ -55099,7 +59027,7 @@ defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N7 +// Location: FF_X2_Y22_N5 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -55118,24 +59046,24 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 +// Location: LCCOMB_X2_Y22_N22 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Stop~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h5FCC; defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -55153,41 +59081,41 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~5 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\I2C_SDAT~input_o ), + .datad(\ula_|i2c_loader_|nbyte [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .combout(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbyte[0]~5 .lut_mask = 16'hFAD8; +defparam \ula_|i2c_loader_|nbyte[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|nbyte[0]~5_combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h2000; defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|thisbyte[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), @@ -55206,25 +59134,25 @@ defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N20 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) // \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N21 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|thisbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), @@ -55243,25 +59171,25 @@ defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) // \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: FF_X3_Y23_N9 dffeas \ula_|i2c_loader_|thisbyte[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), @@ -55280,25 +59208,25 @@ defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X3_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) // \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N25 +// Location: FF_X3_Y23_N11 dffeas \ula_|i2c_loader_|thisbyte[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), @@ -55318,40 +59246,23 @@ defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N27 +// Location: FF_X3_Y23_N13 dffeas \ula_|i2c_loader_|thisbyte[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), @@ -55370,94 +59281,111 @@ defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N22 +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0004; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N12 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|Equal2~0_combout ) # (!\ula_|i2c_loader_|thisbyte [4]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~2_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0AAA; defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X2_Y22_N10 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Stop~q ), + .dataa(gnd), .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(gnd), + .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N26 +// Location: LCCOMB_X2_Y22_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Pause~1_combout )))) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h0ACE; defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y22_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF373; defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N20 +// Location: LCCOMB_X2_Y22_N26 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # // (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~3_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE2F0; defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N21 +// Location: FF_X2_Y22_N27 dffeas \ula_|i2c_loader_|state.Pause ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Pause~6_combout ), @@ -55476,25 +59404,25 @@ defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N30 +// Location: LCCOMB_X2_Y22_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( // Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|state.Start~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|state.Pause~q & \ula_|i2c_loader_|Mux42~0_combout ))) # // (!\ula_|i2c_loader_|state.Idle~q ) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h3BF3; defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N31 +// Location: FF_X2_Y22_N29 dffeas \ula_|i2c_loader_|state.Start ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state~25_combout ), @@ -55513,38 +59441,38 @@ defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Start .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # // ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hC3EA; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~1_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC0C3; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55586,186 +59514,152 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|shiftreg~19_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~13_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hFF10; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte [4])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|shiftreg~22_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h3530; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [3]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hF404; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h1010; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~27_combout = (\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; -defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - - .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datab(\ula_|i2c_loader_|state~24_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; -defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .lut_mask = 16'hEEE4; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~28 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~28_combout = (\ula_|i2c_loader_|shiftreg[0]~27_combout & (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Idle~q & !\ula_|i2c_loader_|WideAnd0~combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~27_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .lut_mask = 16'h0080; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N21 +// Location: FF_X2_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55775,85 +59669,136 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg~23_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [0]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; -defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h8090; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y22_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~6 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~6_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~6 .lut_mask = 16'h0033; +defparam \ula_|i2c_loader_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~6_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((!\ula_|i2c_loader_|thisbyte [0] & \ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~6_combout ), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8C88; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [1]) # ((!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state~24_combout )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'h8CBF; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~9_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state~24_combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h2E2F; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X2_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & -// !\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (!\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; -defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 +// Location: FF_X2_Y24_N17 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~24_combout ), + .d(\ula_|i2c_loader_|shiftreg~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55863,33 +59808,67 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) - .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h5030; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N11 +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~18_combout ))) # (!\ula_|i2c_loader_|shiftreg~6_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~6_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h2EFF; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hCF00; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~21_combout ), + .d(\ula_|i2c_loader_|shiftreg~20_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55899,84 +59878,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg~17_combout & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~17_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAE04; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), - .datab(\ula_|i2c_loader_|shiftreg~15_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [2]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; -defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N23 +// Location: FF_X2_Y24_N19 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~27_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55986,67 +59914,33 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE54; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|shiftreg~14_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [3]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~16_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N15 +// Location: FF_X2_Y24_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -56056,33 +59950,50 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - .dataa(\ula_|i2c_loader_|Mux35~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|shiftreg [4]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h40C0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N5 +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [4])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg [4]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hBB88; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~13_combout ), + .d(\ula_|i2c_loader_|shiftreg~12_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -56092,33 +60003,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), - .datab(\ula_|i2c_loader_|Mux35~0_combout ), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [5]), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -56128,33 +60039,33 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) +// \ula_|i2c_loader_|shiftreg[7]~7_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|shiftreg [6]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .combout(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N29 +// Location: FF_X2_Y24_N1 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .d(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -56164,16 +60075,16 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); @@ -56182,14 +60093,14 @@ defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~6_combout & !\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~6_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), @@ -56199,38 +60110,38 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h0C0E; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2F4; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56239,15 +60150,15 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56391,735 +60302,118 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux38~0 ( -// Equation(s): -// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) - - .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), - .datab(\Equal2~1_combout ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Mux39~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux38~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; -defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y12_N15 -dffeas \sdram_|r.rd_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux38~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rd_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rd_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N0 -cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( -// Equation(s): -// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) -// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\sdram_|r.rf_counter[0]~12_combout ), - .cout(\sdram_|r.rf_counter[0]~13 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; -defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N26 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.address[3]~6_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.rf_counter[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; -defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N1 -dffeas \sdram_|r.rf_counter[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N2 -cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( -// Equation(s): -// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) -// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [1]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[0]~13 ), - .combout(\sdram_|r.rf_counter[1]~14_combout ), - .cout(\sdram_|r.rf_counter[1]~15 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N3 -dffeas \sdram_|r.rf_counter[1] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[1]~14_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N4 -cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( -// Equation(s): -// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) -// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [2]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[1]~15 ), - .combout(\sdram_|r.rf_counter[2]~16_combout ), - .cout(\sdram_|r.rf_counter[2]~17 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N5 -dffeas \sdram_|r.rf_counter[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[2]~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N6 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) -// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[2]~17 ), - .combout(\sdram_|r.rf_counter[3]~18_combout ), - .cout(\sdram_|r.rf_counter[3]~19 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N7 -dffeas \sdram_|r.rf_counter[3] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[3]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N8 -cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( -// Equation(s): -// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) -// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [4]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[3]~19 ), - .combout(\sdram_|r.rf_counter[4]~20_combout ), - .cout(\sdram_|r.rf_counter[4]~21 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N9 -dffeas \sdram_|r.rf_counter[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[4]~20_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N10 -cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( -// Equation(s): -// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) -// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[4]~21 ), - .combout(\sdram_|r.rf_counter[5]~22_combout ), - .cout(\sdram_|r.rf_counter[5]~23 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N11 -dffeas \sdram_|r.rf_counter[5] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[5]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N12 -cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( -// Equation(s): -// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) -// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) - - .dataa(\sdram_|r.rf_counter [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[5]~23 ), - .combout(\sdram_|r.rf_counter[6]~24_combout ), - .cout(\sdram_|r.rf_counter[6]~25 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; -defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N13 -dffeas \sdram_|r.rf_counter[6] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N14 -cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( -// Equation(s): -// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) -// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [7]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[6]~25 ), - .combout(\sdram_|r.rf_counter[7]~26_combout ), - .cout(\sdram_|r.rf_counter[7]~27 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N15 -dffeas \sdram_|r.rf_counter[7] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[7]~26_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N24 -cycloneive_lcell_comb \sdram_|Equal0~1 ( -// Equation(s): -// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(\sdram_|r.rf_counter [7]), - .datac(\sdram_|r.rf_counter [4]), - .datad(\sdram_|r.rf_counter [6]), - .cin(gnd), - .combout(\sdram_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; -defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N16 -cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( -// Equation(s): -// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) -// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [8]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[7]~27 ), - .combout(\sdram_|r.rf_counter[8]~28_combout ), - .cout(\sdram_|r.rf_counter[8]~29 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N17 -dffeas \sdram_|r.rf_counter[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[8]~28_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal0~0 ( -// Equation(s): -// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(\sdram_|r.rf_counter [0]), - .datac(\sdram_|r.rf_counter [2]), - .datad(\sdram_|r.rf_counter [1]), - .cin(gnd), - .combout(\sdram_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; -defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N18 -cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( -// Equation(s): -// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\sdram_|r.rf_counter [9]), - .cin(\sdram_|r.rf_counter[8]~29 ), - .combout(\sdram_|r.rf_counter[9]~30_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; -defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N19 -dffeas \sdram_|r.rf_counter[9] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[9]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [9]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N22 -cycloneive_lcell_comb \sdram_|Equal0~2 ( -// Equation(s): -// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) - - .dataa(\sdram_|Equal0~1_combout ), - .datab(\sdram_|r.rf_counter [8]), - .datac(\sdram_|Equal0~0_combout ), - .datad(\sdram_|r.rf_counter [9]), - .cin(gnd), - .combout(\sdram_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; -defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N28 -cycloneive_lcell_comb \sdram_|Mux13~8 ( -// Equation(s): -// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|Mux13~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; -defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N20 -cycloneive_lcell_comb \sdram_|Mux37~0 ( -// Equation(s): -// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux13~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux37~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; -defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N21 -dffeas \sdram_|r.rf_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux37~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rf_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N14 -cycloneive_lcell_comb \sdram_|Mux4~0 ( -// Equation(s): -// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; -defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux4~1 ( -// Equation(s): -// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; -defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N2 -cycloneive_lcell_comb \sdram_|Mux4~2 ( -// Equation(s): -// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; -defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N30 +// Location: LCCOMB_X21_Y19_N4 cycloneive_lcell_comb \sdram_|Mux4~3 ( // Equation(s): -// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) +// \sdram_|Mux4~3_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [6])) - .dataa(\sdram_|Mux4~1_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux4~2_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux4~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .lut_mask = 16'hAA50; defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N31 -dffeas \sdram_|r.state[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux4~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.state [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.state[8] .is_wysiwyg = "true"; -defparam \sdram_|r.state[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N6 -cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~0 ( // Equation(s): -// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) +// \sdram_|Mux4~0_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4]))) .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.act_row[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; -defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N18 -cycloneive_lcell_comb \sdram_|process_0~2 ( -// Equation(s): -// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) - - .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|process_0~2_combout ), + .combout(\sdram_|Mux4~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; -defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux4~0 .lut_mask = 16'hAF00; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N0 -cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( // Equation(s): -// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - .dataa(\sdram_|r.act_row[1]~0_combout ), - .datab(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.state [6]), + .datab(gnd), .datac(\sdram_|r.state [7]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.act_row[1]~1_combout ), + .combout(\sdram_|r.address[3]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; -defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N9 -dffeas \sdram_|r.act_row[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\z80_|address_pins_|abus[15]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [4]), - .prn(vcc)); +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[4] .power_up = "low"; +defparam \sdram_|Mux7~2 .lut_mask = 16'h0B00; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N23 -dffeas \sdram_|r.act_row[3] ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [6] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hCC00; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h5500; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \sdram_|r.act_row[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N20 -cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( -// Equation(s): -// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\sdram_|r.act_row[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; -defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y13_N21 -dffeas \sdram_|r.act_row[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.act_row[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.act_row [2]), @@ -57129,115 +60423,80 @@ defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; defparam \sdram_|r.act_row[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N22 +// Location: FF_X21_Y14_N11 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 cycloneive_lcell_comb \sdram_|Equal7~1 ( // Equation(s): -// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & -// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\sdram_|r.act_row [3]), - .datad(\sdram_|r.act_row [2]), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\sdram_|r.act_row [2]), + .datad(\sdram_|r.act_row [3]), .cin(gnd), .combout(\sdram_|Equal7~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .lut_mask = 16'h8241; defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N3 -dffeas \sdram_|r.act_row[1] ( +// Location: FF_X21_Y14_N1 +dffeas \sdram_|r.act_row[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .asdata(\z80_|address_pins_|abus[15]~23_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.act_row [1]), + .q(\sdram_|r.act_row [4]), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[1] .power_up = "low"; +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X21_Y13_N13 -dffeas \sdram_|r.act_row[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[11]~19_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N2 -cycloneive_lcell_comb \sdram_|Equal7~0 ( -// Equation(s): -// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & -// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\sdram_|r.act_row [1]), - .datad(\sdram_|r.act_row [0]), - .cin(gnd), - .combout(\sdram_|Equal7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; -defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal7~2 ( -// Equation(s): -// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\sdram_|r.act_row [4]), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|Equal7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; -defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N4 +// Location: LCCOMB_X20_Y15_N20 cycloneive_lcell_comb \sdram_|Mux39~0 ( // Equation(s): -// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) +// \sdram_|Mux39~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux39~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .lut_mask = 16'h8402; defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N12 +// Location: LCCOMB_X20_Y15_N14 cycloneive_lcell_comb \sdram_|Mux39~1 ( // Equation(s): // \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) @@ -57254,24 +60513,24 @@ defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N24 +// Location: LCCOMB_X21_Y15_N30 cycloneive_lcell_comb \sdram_|Mux39~2 ( // Equation(s): -// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.wr_pending~q & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~23_combout ))) - .dataa(\sdram_|Mux39~1_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), .datac(\sdram_|r.wr_pending~q ), - .datad(\ExtRamWE~0_combout ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), .combout(\sdram_|Mux39~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .lut_mask = 16'hF808; defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y12_N25 +// Location: FF_X21_Y15_N31 dffeas \sdram_|r.wr_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux39~2_combout ), @@ -57290,180 +60549,44 @@ defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; defparam \sdram_|r.wr_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux38~3 ( // Equation(s): -// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) +// \sdram_|Mux38~3_combout = (!\sdram_|r.rd_pending~q & (((!\z80_|memory_ifc_|nIORQ_out~0_combout & \z80_|address_pins_|DFFE_apin_latch [15])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux9~8_combout ), + .combout(\sdram_|Mux38~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; -defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~3 .lut_mask = 16'h0073; +defparam \sdram_|Mux38~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux38~2 ( // Equation(s): -// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) +// \sdram_|Mux38~2_combout = (\Equal5~1_combout & ((\sdram_|Mux38~3_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) # (!\Equal5~1_combout & (((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|Mux38~3_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), - .combout(\sdram_|Mux9~9_combout ), + .combout(\sdram_|Mux38~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; -defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~2 .lut_mask = 16'hF888; +defparam \sdram_|Mux38~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N26 -cycloneive_lcell_comb \sdram_|Mux6~3 ( -// Equation(s): -// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux9~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; -defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N0 -cycloneive_lcell_comb \sdram_|Mux6~4 ( -// Equation(s): -// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) - - .dataa(gnd), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux6~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; -defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N6 -cycloneive_lcell_comb \sdram_|Mux6~2 ( -// Equation(s): -// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; -defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N10 -cycloneive_lcell_comb \sdram_|Mux6~5 ( -// Equation(s): -// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) - - .dataa(\sdram_|Mux6~3_combout ), - .datab(\sdram_|Mux6~4_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|Mux6~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; -defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N8 -cycloneive_lcell_comb \sdram_|process_0~3 ( -// Equation(s): -// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|process_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; -defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux6~0 ( -// Equation(s): -// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|process_0~3_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; -defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N16 -cycloneive_lcell_comb \sdram_|Mux6~1 ( -// Equation(s): -// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux6~0_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; -defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N24 -cycloneive_lcell_comb \sdram_|Mux6~6 ( -// Equation(s): -// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux6~5_combout ), - .datad(\sdram_|Mux6~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; -defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y15_N25 -dffeas \sdram_|r.state[6] ( +// Location: FF_X21_Y15_N21 +dffeas \sdram_|r.rd_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux6~6_combout ), + .d(\sdram_|Mux38~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57472,175 +60595,73 @@ dffeas \sdram_|r.state[6] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.state [6]), + .q(\sdram_|r.rd_pending~q ), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.state[6] .is_wysiwyg = "true"; -defparam \sdram_|r.state[6] .power_up = "low"; +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N12 -cycloneive_lcell_comb \sdram_|r.address[3]~6 ( -// Equation(s): -// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; -defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux7~2 ( -// Equation(s): -// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) - - .dataa(\sdram_|r.address[3]~6_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; -defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N12 +// Location: LCCOMB_X21_Y14_N22 cycloneive_lcell_comb \sdram_|n~3 ( // Equation(s): -// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) +// \sdram_|n~3_combout = (\sdram_|r.wr_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ ((!\sdram_|r.act_row [4])))) # (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) - .dataa(gnd), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Equal7~2_combout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|n~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .lut_mask = 16'h9990; defparam \sdram_|n~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N6 -cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \sdram_|n~4 ( // Equation(s): -// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.state [6]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; -defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N28 -cycloneive_lcell_comb \sdram_|Mux7~4 ( -// Equation(s): -// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) - - .dataa(\sdram_|Mux7~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux7~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; -defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N10 -cycloneive_lcell_comb \sdram_|Mux7~5 ( -// Equation(s): -// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux7~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux7~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; -defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux23~0 ( -// Equation(s): -// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) +// \sdram_|n~4_combout = (\sdram_|Equal7~1_combout & (\sdram_|n~3_combout & \sdram_|Equal7~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(gnd), + .datab(\sdram_|Equal7~1_combout ), + .datac(\sdram_|n~3_combout ), + .datad(\sdram_|Equal7~0_combout ), .cin(gnd), - .combout(\sdram_|Mux23~0_combout ), + .combout(\sdram_|n~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; -defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +defparam \sdram_|n~4 .lut_mask = 16'hC000; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \sdram_|Mux10~9 ( // Equation(s): -// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) +// \sdram_|Mux10~9_combout = (!\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|Mux13~7_combout ), + .combout(\sdram_|Mux10~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; -defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux10~9 .lut_mask = 16'h00EF; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux10~10 ( -// Equation(s): -// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.rf_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; -defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N18 +// Location: LCCOMB_X19_Y17_N20 cycloneive_lcell_comb \sdram_|Mux7~1 ( // Equation(s): -// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~9_combout ) # (!\sdram_|r.state [7])))) .dataa(\sdram_|Mux23~0_combout ), .datab(\sdram_|Mux13~7_combout ), .datac(\sdram_|r.state [7]), - .datad(\sdram_|Mux10~10_combout ), + .datad(\sdram_|Mux10~9_combout ), .cin(gnd), .combout(\sdram_|Mux7~1_combout ), .cout()); @@ -57649,24 +60670,75 @@ defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N22 +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h3F00; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.wr_pending~q & \sdram_|Mux7~3_combout ))) # (!\sdram_|r.state [6] & (\sdram_|r.state [7] $ (((\sdram_|Mux7~3_combout ))))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux7~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h250A; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.rf_pending~q & (\sdram_|r.state [6] $ (((!\sdram_|Mux7~4_combout ))))) # (!\sdram_|r.rf_pending~q & (!\sdram_|r.state [6] & (!\sdram_|n~4_combout & !\sdram_|Mux7~4_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'h8823; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \sdram_|Mux7~6 ( // Equation(s): -// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|r.state [8] & \sdram_|Mux7~5_combout ))) .dataa(\sdram_|Mux7~2_combout ), - .datab(\sdram_|Mux7~5_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux7~1_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux7~1_combout ), + .datad(\sdram_|Mux7~5_combout ), .cin(gnd), .combout(\sdram_|Mux7~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .lut_mask = 16'hFEFA; defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N23 +// Location: FF_X23_Y19_N3 dffeas \sdram_|r.state[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux7~6_combout ), @@ -57685,14 +60757,938 @@ defparam \sdram_|r.state[5] .is_wysiwyg = "true"; defparam \sdram_|r.state[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N6 +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~32_combout = ((\sdram_|r.address[3]~6_combout & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[8]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~32 .lut_mask = 16'h555D; +defparam \sdram_|r.rf_counter[8]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(\sdram_|r.rf_counter [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [2]) # ((\sdram_|r.rf_counter [0]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [2]), + .datac(\sdram_|r.rf_counter [0]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter [9] $ (\sdram_|r.rf_counter[8]~29 ) + + .dataa(\sdram_|r.rf_counter [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h5A5A; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N23 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [4]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [5]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [5]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~0_combout ) # (((\sdram_|Equal0~1_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~0_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|r.rf_counter [9]), + .datad(\sdram_|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFFBF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|r.address[3]~6_combout )) # (!\sdram_|Mux13~8_combout ))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|Equal0~2_combout )))) + + .dataa(\sdram_|Mux13~8_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h707F; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N25 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (!\sdram_|r.rf_pending~q & (\sdram_|r.rd_pending~q & (\sdram_|Equal7~2_combout & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h0040; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux4~4 ( +// Equation(s): +// \sdram_|Mux4~4_combout = (\sdram_|r.state [8] & (((!\sdram_|Mux4~0_combout & \sdram_|Mux4~1_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|Mux4~1_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux4~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~4 .lut_mask = 16'h5F44; +defparam \sdram_|Mux4~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [5] & (((\sdram_|r.state [6] & !\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [6] $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'h39FE; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux4~5 ( +// Equation(s): +// \sdram_|Mux4~5_combout = (\sdram_|Mux4~2_combout & (((\sdram_|r.state [8])))) # (!\sdram_|Mux4~2_combout & (\sdram_|Mux4~4_combout & ((\sdram_|Mux4~3_combout ) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~3_combout ), + .datab(\sdram_|Mux4~4_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~5 .lut_mask = 16'hF0C8; +defparam \sdram_|Mux4~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = (\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~0 ( +// Equation(s): +// \sdram_|r.act_row[2]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [5] & (\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [6] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \sdram_|r.act_row[2]~1 ( +// Equation(s): +// \sdram_|r.act_row[2]~1_combout = (\sdram_|process_0~4_combout & (\sdram_|r.act_row[2]~0_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.act_row[2]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~1 .lut_mask = 16'h9000; +defparam \sdram_|r.act_row[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N3 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~18_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~18_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~18_combout ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~0_combout & (\sdram_|Equal7~1_combout & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|r.act_row [4]), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h8040; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF88; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (!\sdram_|r.rf_pending~q & (!\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'h0501; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (!\sdram_|r.state [4] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'h0F00; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~4_combout )) # (!\sdram_|Mux9~5_combout ))) # (!\sdram_|r.state [6] & (((!\sdram_|r.rf_pending~q & \sdram_|Mux9~4_combout )))) + + .dataa(\sdram_|Mux9~5_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux9~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h47CC; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hAFF0; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~4_combout & (\sdram_|Mux6~3_combout ))) + + .dataa(\sdram_|Mux6~4_combout ), + .datab(\sdram_|Mux6~3_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hCC00; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [4] & (\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~2_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8C10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|Mux6~0_combout ) # (\sdram_|r.state [6]))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h6628; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFA50; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (\sdram_|r.state [4] & (!\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h00E0; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N28 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rf_pending~q & \sdram_|Mux5~7_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux5~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h4544; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 cycloneive_lcell_comb \sdram_|Mux5~2 ( // Equation(s): -// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [8] & !\sdram_|Mux4~1_combout )))) - .dataa(\sdram_|Mux4~0_combout ), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [8]), + .datac(\sdram_|Mux4~1_combout ), .datad(\sdram_|Mux13~7_combout ), .cin(gnd), .combout(\sdram_|Mux5~2_combout ), @@ -57702,143 +61698,109 @@ defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N18 +// Location: LCCOMB_X18_Y17_N22 cycloneive_lcell_comb \sdram_|Mux5~10 ( // Equation(s): -// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) +// \sdram_|Mux5~10_combout = (\sdram_|r.state [8] & (\sdram_|r.state [6] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6])) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux5~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .lut_mask = 16'h9991; defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N16 +// Location: LCCOMB_X18_Y17_N2 cycloneive_lcell_comb \sdram_|Mux5~3 ( // Equation(s): -// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|Mux4~1_combout & !\sdram_|r.state [6]))) # (!\sdram_|r.state [5]) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux4~0_combout ), - .datad(\sdram_|Mux5~10_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux4~1_combout ), + .datac(\sdram_|Mux5~10_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .lut_mask = 16'hF5F7; defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N30 +// Location: LCCOMB_X18_Y17_N0 cycloneive_lcell_comb \sdram_|Mux5~4 ( // Equation(s): -// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|r.state [4] & \sdram_|Mux5~3_combout )))) - .dataa(\sdram_|Mux5~2_combout ), - .datab(\sdram_|Mux5~3_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux5~2_combout ), + .datad(\sdram_|Mux5~3_combout ), .cin(gnd), .combout(\sdram_|Mux5~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .lut_mask = 16'hC8C0; defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N18 -cycloneive_lcell_comb \sdram_|Mux5~7 ( -// Equation(s): -// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.rd_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux5~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; -defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N4 -cycloneive_lcell_comb \sdram_|Mux5~8 ( -// Equation(s): -// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) - - .dataa(\sdram_|Mux5~7_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux5~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; -defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N26 +// Location: LCCOMB_X20_Y16_N26 cycloneive_lcell_comb \sdram_|Mux5~5 ( // Equation(s): // \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [7]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|Mux5~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .lut_mask = 16'h0D0F; defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N12 +// Location: LCCOMB_X20_Y16_N8 cycloneive_lcell_comb \sdram_|Mux5~6 ( // Equation(s): -// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~4_combout & ((\sdram_|Mux5~5_combout ) # ((\sdram_|process_0~2_combout & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~3_combout ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux5~5_combout ), + .dataa(\sdram_|Mux5~5_combout ), + .datab(\sdram_|Mux9~4_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .lut_mask = 16'h88C8; defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N20 +// Location: LCCOMB_X23_Y19_N10 cycloneive_lcell_comb \sdram_|Mux5~9 ( // Equation(s): // \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|Mux5~4_combout ), - .datac(\sdram_|Mux5~8_combout ), + .dataa(\sdram_|Mux5~8_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux5~4_combout ), .datad(\sdram_|Mux5~6_combout ), .cin(gnd), .combout(\sdram_|Mux5~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .lut_mask = 16'hF3F2; defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N21 +// Location: FF_X23_Y19_N11 dffeas \sdram_|r.state[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux5~9_combout ), @@ -57857,7 +61819,7 @@ defparam \sdram_|r.state[7] .is_wysiwyg = "true"; defparam \sdram_|r.state[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N8 +// Location: LCCOMB_X18_Y17_N16 cycloneive_lcell_comb \sdram_|n~2 ( // Equation(s): // \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) @@ -57874,78 +61836,112 @@ defparam \sdram_|n~2 .lut_mask = 16'hFFFC; defparam \sdram_|n~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Location: LCCOMB_X19_Y19_N10 +cycloneive_lcell_comb \sdram_|Mux8~6 ( // Equation(s): -// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) +// \sdram_|Mux8~6_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), .datad(\sdram_|r.state [4]), .cin(gnd), + .combout(\sdram_|Mux8~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~6 .lut_mask = 16'hB03B; +defparam \sdram_|Mux8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux8~7 ( +// Equation(s): +// \sdram_|Mux8~7_combout = (\sdram_|r.state [8] & (\sdram_|Mux8~6_combout $ ((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|Mux8~6_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|Mux8~6_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~7 .lut_mask = 16'h606E; +defparam \sdram_|Mux8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|r.state [5] $ (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [5]) # (\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7336; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N28 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [6] & (\sdram_|Mux8~1_combout & (!\sdram_|r.state [8]))) # (!\sdram_|r.state [6] & (\sdram_|r.state [8] $ (((!\sdram_|n~2_combout ) # (!\sdram_|Mux8~1_combout ))))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'h490D; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N26 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [6] & ((\sdram_|Mux9~5_combout & ((\sdram_|Mux8~2_combout ))) # (!\sdram_|Mux9~5_combout & (\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|Mux8~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux8~2_combout ), + .cin(gnd), .combout(\sdram_|Mux8~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .lut_mask = 16'hFD08; defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Location: LCCOMB_X19_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~44 ( // Equation(s): -// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux8~3_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux8~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; -defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux9~10 ( -// Equation(s): -// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) - - .dataa(gnd), - .datab(\sdram_|Mux9~9_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux9~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; -defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N28 -cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( -// Equation(s): -// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] +// \sdram_|r.init_counter[0]~44_combout = !\sdram_|r.init_counter [0] .dataa(gnd), .datab(gnd), .datac(\sdram_|r.init_counter [0]), .datad(gnd), .cin(gnd), - .combout(\sdram_|r.init_counter[0]~0_combout ), + .combout(\sdram_|r.init_counter[0]~44_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[0]~44 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y7_N29 +// Location: FF_X19_Y16_N7 dffeas \sdram_|r.init_counter[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[0]~0_combout ), + .d(\sdram_|r.init_counter[0]~44_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57961,45 +61957,45 @@ defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N2 -cycloneive_lcell_comb \sdram_|Add1~1 ( +// Location: LCCOMB_X18_Y16_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~15 ( // Equation(s): -// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) +// \sdram_|r.init_counter[1]~15_cout = CARRY(\sdram_|r.init_counter [0]) - .dataa(gnd), - .datab(\sdram_|r.init_counter [0]), + .dataa(\sdram_|r.init_counter [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), - .cout(\sdram_|Add1~1_cout )); + .cout(\sdram_|r.init_counter[1]~15_cout )); // synopsys translate_off -defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; -defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[1]~15 .lut_mask = 16'h00AA; +defparam \sdram_|r.init_counter[1]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N4 -cycloneive_lcell_comb \sdram_|Add1~2 ( +// Location: LCCOMB_X18_Y16_N4 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~16 ( // Equation(s): -// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) -// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) +// \sdram_|r.init_counter[1]~16_combout = (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter[1]~15_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter[1]~15_cout )) +// \sdram_|r.init_counter[1]~17 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|r.init_counter[1]~15_cout )) .dataa(gnd), .datab(\sdram_|r.init_counter [1]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~1_cout ), - .combout(\sdram_|Add1~2_combout ), - .cout(\sdram_|Add1~3 )); + .cin(\sdram_|r.init_counter[1]~15_cout ), + .combout(\sdram_|r.init_counter[1]~16_combout ), + .cout(\sdram_|r.init_counter[1]~17 )); // synopsys translate_off -defparam \sdram_|Add1~2 .lut_mask = 16'hC303; -defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[1]~16 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[1]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N5 +// Location: FF_X18_Y16_N5 dffeas \sdram_|r.init_counter[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~2_combout ), + .d(\sdram_|r.init_counter[1]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58015,28 +62011,28 @@ defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N6 -cycloneive_lcell_comb \sdram_|Add1~4 ( +// Location: LCCOMB_X18_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[2]~18 ( // Equation(s): -// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) -// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) +// \sdram_|r.init_counter[2]~18_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|r.init_counter[1]~17 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter[1]~17 $ (GND))) +// \sdram_|r.init_counter[2]~19 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|r.init_counter[1]~17 )) .dataa(\sdram_|r.init_counter [2]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~3 ), - .combout(\sdram_|Add1~4_combout ), - .cout(\sdram_|Add1~5 )); + .cin(\sdram_|r.init_counter[1]~17 ), + .combout(\sdram_|r.init_counter[2]~18_combout ), + .cout(\sdram_|r.init_counter[2]~19 )); // synopsys translate_off -defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[2]~18 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[2]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N7 +// Location: FF_X18_Y16_N7 dffeas \sdram_|r.init_counter[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~4_combout ), + .d(\sdram_|r.init_counter[2]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58052,45 +62048,28 @@ defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N8 -cycloneive_lcell_comb \sdram_|Add1~6 ( +// Location: LCCOMB_X18_Y16_N8 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~20 ( // Equation(s): -// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) -// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) - - .dataa(\sdram_|r.init_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|Add1~5 ), - .combout(\sdram_|Add1~6_combout ), - .cout(\sdram_|Add1~7 )); -// synopsys translate_off -defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; -defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N2 -cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( -// Equation(s): -// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout +// \sdram_|r.init_counter[3]~20_combout = (\sdram_|r.init_counter [3] & (\sdram_|r.init_counter[2]~19 & VCC)) # (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter[2]~19 )) +// \sdram_|r.init_counter[3]~21 = CARRY((!\sdram_|r.init_counter [3] & !\sdram_|r.init_counter[2]~19 )) .dataa(gnd), - .datab(gnd), - .datac(\sdram_|Add1~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.init_counter[3]~1_combout ), - .cout()); + .datab(\sdram_|r.init_counter [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.init_counter[2]~19 ), + .combout(\sdram_|r.init_counter[3]~20_combout ), + .cout(\sdram_|r.init_counter[3]~21 )); // synopsys translate_off -defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[3]~20 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[3]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X20_Y3_N3 +// Location: FF_X18_Y16_N9 dffeas \sdram_|r.init_counter[3] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[3]~1_combout ), + .d(\sdram_|r.init_counter[3]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58106,28 +62085,28 @@ defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N10 -cycloneive_lcell_comb \sdram_|Add1~8 ( +// Location: LCCOMB_X18_Y16_N10 +cycloneive_lcell_comb \sdram_|r.init_counter[4]~22 ( // Equation(s): -// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) -// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) +// \sdram_|r.init_counter[4]~22_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|r.init_counter[3]~21 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|r.init_counter[3]~21 $ (GND))) +// \sdram_|r.init_counter[4]~23 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|r.init_counter[3]~21 )) .dataa(\sdram_|r.init_counter [4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~7 ), - .combout(\sdram_|Add1~8_combout ), - .cout(\sdram_|Add1~9 )); + .cin(\sdram_|r.init_counter[3]~21 ), + .combout(\sdram_|r.init_counter[4]~22_combout ), + .cout(\sdram_|r.init_counter[4]~23 )); // synopsys translate_off -defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[4]~22 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[4]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N11 +// Location: FF_X18_Y16_N11 dffeas \sdram_|r.init_counter[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~8_combout ), + .d(\sdram_|r.init_counter[4]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58143,28 +62122,28 @@ defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N12 -cycloneive_lcell_comb \sdram_|Add1~10 ( +// Location: LCCOMB_X18_Y16_N12 +cycloneive_lcell_comb \sdram_|r.init_counter[5]~24 ( // Equation(s): -// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) -// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) +// \sdram_|r.init_counter[5]~24_combout = (\sdram_|r.init_counter [5] & (\sdram_|r.init_counter[4]~23 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|r.init_counter[4]~23 )) +// \sdram_|r.init_counter[5]~25 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|r.init_counter[4]~23 )) .dataa(\sdram_|r.init_counter [5]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~9 ), - .combout(\sdram_|Add1~10_combout ), - .cout(\sdram_|Add1~11 )); + .cin(\sdram_|r.init_counter[4]~23 ), + .combout(\sdram_|r.init_counter[5]~24_combout ), + .cout(\sdram_|r.init_counter[5]~25 )); // synopsys translate_off -defparam \sdram_|Add1~10 .lut_mask = 16'hA505; -defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[5]~24 .lut_mask = 16'hA505; +defparam \sdram_|r.init_counter[5]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N13 +// Location: FF_X18_Y16_N13 dffeas \sdram_|r.init_counter[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~10_combout ), + .d(\sdram_|r.init_counter[5]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58180,28 +62159,28 @@ defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N14 -cycloneive_lcell_comb \sdram_|Add1~12 ( +// Location: LCCOMB_X18_Y16_N14 +cycloneive_lcell_comb \sdram_|r.init_counter[6]~26 ( // Equation(s): -// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) -// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) +// \sdram_|r.init_counter[6]~26_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|r.init_counter[5]~25 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|r.init_counter[5]~25 $ (GND))) +// \sdram_|r.init_counter[6]~27 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|r.init_counter[5]~25 )) .dataa(gnd), .datab(\sdram_|r.init_counter [6]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~11 ), - .combout(\sdram_|Add1~12_combout ), - .cout(\sdram_|Add1~13 )); + .cin(\sdram_|r.init_counter[5]~25 ), + .combout(\sdram_|r.init_counter[6]~26_combout ), + .cout(\sdram_|r.init_counter[6]~27 )); // synopsys translate_off -defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[6]~26 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[6]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N15 +// Location: FF_X18_Y16_N15 dffeas \sdram_|r.init_counter[6] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~12_combout ), + .d(\sdram_|r.init_counter[6]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58217,28 +62196,28 @@ defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N16 -cycloneive_lcell_comb \sdram_|Add1~14 ( +// Location: LCCOMB_X18_Y16_N16 +cycloneive_lcell_comb \sdram_|r.init_counter[7]~28 ( // Equation(s): -// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) -// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) +// \sdram_|r.init_counter[7]~28_combout = (\sdram_|r.init_counter [7] & (\sdram_|r.init_counter[6]~27 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|r.init_counter[6]~27 )) +// \sdram_|r.init_counter[7]~29 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|r.init_counter[6]~27 )) .dataa(gnd), .datab(\sdram_|r.init_counter [7]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~13 ), - .combout(\sdram_|Add1~14_combout ), - .cout(\sdram_|Add1~15 )); + .cin(\sdram_|r.init_counter[6]~27 ), + .combout(\sdram_|r.init_counter[7]~28_combout ), + .cout(\sdram_|r.init_counter[7]~29 )); // synopsys translate_off -defparam \sdram_|Add1~14 .lut_mask = 16'hC303; -defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[7]~28 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[7]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N17 +// Location: FF_X18_Y16_N17 dffeas \sdram_|r.init_counter[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~14_combout ), + .d(\sdram_|r.init_counter[7]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58254,28 +62233,28 @@ defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N18 -cycloneive_lcell_comb \sdram_|Add1~16 ( +// Location: LCCOMB_X18_Y16_N18 +cycloneive_lcell_comb \sdram_|r.init_counter[8]~30 ( // Equation(s): -// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) -// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) +// \sdram_|r.init_counter[8]~30_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|r.init_counter[7]~29 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|r.init_counter[7]~29 $ (GND))) +// \sdram_|r.init_counter[8]~31 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|r.init_counter[7]~29 )) .dataa(gnd), .datab(\sdram_|r.init_counter [8]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~15 ), - .combout(\sdram_|Add1~16_combout ), - .cout(\sdram_|Add1~17 )); + .cin(\sdram_|r.init_counter[7]~29 ), + .combout(\sdram_|r.init_counter[8]~30_combout ), + .cout(\sdram_|r.init_counter[8]~31 )); // synopsys translate_off -defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[8]~30 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[8]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N19 +// Location: FF_X18_Y16_N19 dffeas \sdram_|r.init_counter[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~16_combout ), + .d(\sdram_|r.init_counter[8]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58291,28 +62270,28 @@ defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N20 -cycloneive_lcell_comb \sdram_|Add1~18 ( +// Location: LCCOMB_X18_Y16_N20 +cycloneive_lcell_comb \sdram_|r.init_counter[9]~32 ( // Equation(s): -// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) -// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) +// \sdram_|r.init_counter[9]~32_combout = (\sdram_|r.init_counter [9] & (\sdram_|r.init_counter[8]~31 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter[8]~31 )) +// \sdram_|r.init_counter[9]~33 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|r.init_counter[8]~31 )) .dataa(gnd), .datab(\sdram_|r.init_counter [9]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~17 ), - .combout(\sdram_|Add1~18_combout ), - .cout(\sdram_|Add1~19 )); + .cin(\sdram_|r.init_counter[8]~31 ), + .combout(\sdram_|r.init_counter[9]~32_combout ), + .cout(\sdram_|r.init_counter[9]~33 )); // synopsys translate_off -defparam \sdram_|Add1~18 .lut_mask = 16'hC303; -defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[9]~32 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[9]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N21 +// Location: FF_X18_Y16_N21 dffeas \sdram_|r.init_counter[9] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~18_combout ), + .d(\sdram_|r.init_counter[9]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58328,28 +62307,28 @@ defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N22 -cycloneive_lcell_comb \sdram_|Add1~20 ( +// Location: LCCOMB_X18_Y16_N22 +cycloneive_lcell_comb \sdram_|r.init_counter[10]~34 ( // Equation(s): -// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) -// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) +// \sdram_|r.init_counter[10]~34_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|r.init_counter[9]~33 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|r.init_counter[9]~33 $ (GND))) +// \sdram_|r.init_counter[10]~35 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|r.init_counter[9]~33 )) .dataa(\sdram_|r.init_counter [10]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~19 ), - .combout(\sdram_|Add1~20_combout ), - .cout(\sdram_|Add1~21 )); + .cin(\sdram_|r.init_counter[9]~33 ), + .combout(\sdram_|r.init_counter[10]~34_combout ), + .cout(\sdram_|r.init_counter[10]~35 )); // synopsys translate_off -defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[10]~34 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[10]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N23 +// Location: FF_X18_Y16_N23 dffeas \sdram_|r.init_counter[10] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~20_combout ), + .d(\sdram_|r.init_counter[10]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58365,62 +62344,28 @@ defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N22 -cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Location: LCCOMB_X18_Y16_N24 +cycloneive_lcell_comb \sdram_|r.init_counter[11]~36 ( // Equation(s): -// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|r.init_counter [4]), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; -defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N0 -cycloneive_lcell_comb \sdram_|Equal2~1 ( -// Equation(s): -// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [3]), - .cin(gnd), - .combout(\sdram_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; -defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y3_N24 -cycloneive_lcell_comb \sdram_|Add1~22 ( -// Equation(s): -// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) -// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) +// \sdram_|r.init_counter[11]~36_combout = (\sdram_|r.init_counter [11] & (\sdram_|r.init_counter[10]~35 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter[10]~35 )) +// \sdram_|r.init_counter[11]~37 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|r.init_counter[10]~35 )) .dataa(gnd), .datab(\sdram_|r.init_counter [11]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~21 ), - .combout(\sdram_|Add1~22_combout ), - .cout(\sdram_|Add1~23 )); + .cin(\sdram_|r.init_counter[10]~35 ), + .combout(\sdram_|r.init_counter[11]~36_combout ), + .cout(\sdram_|r.init_counter[11]~37 )); // synopsys translate_off -defparam \sdram_|Add1~22 .lut_mask = 16'hC303; -defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[11]~36 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[11]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N25 +// Location: FF_X18_Y16_N25 dffeas \sdram_|r.init_counter[11] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~22_combout ), + .d(\sdram_|r.init_counter[11]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58436,28 +62381,28 @@ defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N26 -cycloneive_lcell_comb \sdram_|Add1~24 ( +// Location: LCCOMB_X18_Y16_N26 +cycloneive_lcell_comb \sdram_|r.init_counter[12]~38 ( // Equation(s): -// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) -// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) +// \sdram_|r.init_counter[12]~38_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|r.init_counter[11]~37 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|r.init_counter[11]~37 $ (GND))) +// \sdram_|r.init_counter[12]~39 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|r.init_counter[11]~37 )) .dataa(\sdram_|r.init_counter [12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~23 ), - .combout(\sdram_|Add1~24_combout ), - .cout(\sdram_|Add1~25 )); + .cin(\sdram_|r.init_counter[11]~37 ), + .combout(\sdram_|r.init_counter[12]~38_combout ), + .cout(\sdram_|r.init_counter[12]~39 )); // synopsys translate_off -defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[12]~38 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[12]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N27 +// Location: FF_X18_Y16_N27 dffeas \sdram_|r.init_counter[12] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~24_combout ), + .d(\sdram_|r.init_counter[12]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58473,28 +62418,28 @@ defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N28 -cycloneive_lcell_comb \sdram_|Add1~26 ( +// Location: LCCOMB_X18_Y16_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[13]~40 ( // Equation(s): -// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) -// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) +// \sdram_|r.init_counter[13]~40_combout = (\sdram_|r.init_counter [13] & (\sdram_|r.init_counter[12]~39 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter[12]~39 )) +// \sdram_|r.init_counter[13]~41 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|r.init_counter[12]~39 )) .dataa(gnd), .datab(\sdram_|r.init_counter [13]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~25 ), - .combout(\sdram_|Add1~26_combout ), - .cout(\sdram_|Add1~27 )); + .cin(\sdram_|r.init_counter[12]~39 ), + .combout(\sdram_|r.init_counter[13]~40_combout ), + .cout(\sdram_|r.init_counter[13]~41 )); // synopsys translate_off -defparam \sdram_|Add1~26 .lut_mask = 16'hC303; -defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[13]~40 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[13]~40 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N29 +// Location: FF_X18_Y16_N29 dffeas \sdram_|r.init_counter[13] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~26_combout ), + .d(\sdram_|r.init_counter[13]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58510,27 +62455,27 @@ defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N30 -cycloneive_lcell_comb \sdram_|Add1~28 ( +// Location: LCCOMB_X18_Y16_N30 +cycloneive_lcell_comb \sdram_|r.init_counter[14]~42 ( // Equation(s): -// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) +// \sdram_|r.init_counter[14]~42_combout = \sdram_|r.init_counter [14] $ (\sdram_|r.init_counter[13]~41 ) .dataa(\sdram_|r.init_counter [14]), .datab(gnd), .datac(gnd), .datad(gnd), - .cin(\sdram_|Add1~27 ), - .combout(\sdram_|Add1~28_combout ), + .cin(\sdram_|r.init_counter[13]~41 ), + .combout(\sdram_|r.init_counter[14]~42_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; -defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[14]~42 .lut_mask = 16'h5A5A; +defparam \sdram_|r.init_counter[14]~42 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N31 +// Location: FF_X18_Y16_N31 dffeas \sdram_|r.init_counter[14] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~28_combout ), + .d(\sdram_|r.init_counter[14]~42_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58546,15 +62491,32 @@ defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N0 +// Location: LCCOMB_X19_Y16_N2 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0003; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y16_N0 cycloneive_lcell_comb \sdram_|process_0~5 ( // Equation(s): -// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [10] & !\sdram_|r.init_counter [9]))) - .dataa(\sdram_|r.init_counter [14]), + .dataa(\sdram_|r.init_counter [8]), .datab(\sdram_|r.init_counter [11]), - .datac(\sdram_|r.init_counter [12]), - .datad(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [10]), + .datad(\sdram_|r.init_counter [9]), .cin(gnd), .combout(\sdram_|process_0~5_combout ), .cout()); @@ -58563,129 +62525,95 @@ defparam \sdram_|process_0~5 .lut_mask = 16'h0001; defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N6 +// Location: LCCOMB_X19_Y16_N10 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter [4] & (!\sdram_|r.init_counter [2] & !\sdram_|r.init_counter [5]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|r.init_counter [4]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [5]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N0 cycloneive_lcell_comb \sdram_|Equal2~2 ( // Equation(s): -// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) +// \sdram_|Equal2~2_combout = (!\sdram_|r.init_counter [6] & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & \sdram_|Equal2~0_combout ))) - .dataa(\sdram_|Equal2~0_combout ), + .dataa(\sdram_|r.init_counter [6]), .datab(\sdram_|Equal2~1_combout ), .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [2]), + .datad(\sdram_|Equal2~0_combout ), .cin(gnd), .combout(\sdram_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .lut_mask = 16'h4000; defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~11 ( -// Equation(s): -// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(gnd), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Mux9~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; -defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux9~12 ( -// Equation(s): -// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) - - .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux9~11_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; -defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N0 -cycloneive_lcell_comb \sdram_|Mux9~13 ( -// Equation(s): -// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|n~2_combout ), - .datad(\sdram_|Mux9~12_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; -defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N2 +// Location: LCCOMB_X19_Y16_N4 cycloneive_lcell_comb \sdram_|Mux8~0 ( // Equation(s): -// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) +// \sdram_|Mux8~0_combout = (\sdram_|r.init_counter [0] & (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux9~10_combout ), - .datad(\sdram_|Mux9~13_combout ), + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), .cin(gnd), .combout(\sdram_|Mux8~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .lut_mask = 16'h0200; defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N16 -cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Location: LCCOMB_X19_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux8~4 ( // Equation(s): -// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) +// \sdram_|Mux8~4_combout = (\sdram_|r.state [5] & (((\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux8~3_combout & ((\sdram_|Mux8~1_combout ) # (\sdram_|Mux8~0_combout )))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), + .dataa(\sdram_|Mux8~3_combout ), + .datab(\sdram_|Mux8~1_combout ), .datac(\sdram_|r.state [5]), .datad(\sdram_|Mux8~0_combout ), .cin(gnd), - .combout(\sdram_|Mux8~1_combout ), + .combout(\sdram_|Mux8~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; -defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~4 .lut_mask = 16'hCAC8; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux8~5 ( // Equation(s): -// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) +// \sdram_|Mux8~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~7_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~4_combout ))) .dataa(\sdram_|r.state [7]), .datab(gnd), - .datac(\sdram_|Mux8~4_combout ), - .datad(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux8~7_combout ), + .datad(\sdram_|Mux8~4_combout ), .cin(gnd), - .combout(\sdram_|Mux8~2_combout ), + .combout(\sdram_|Mux8~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; -defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~5 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y15_N21 +// Location: FF_X23_Y19_N5 dffeas \sdram_|r.state[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux8~2_combout ), + .d(\sdram_|Mux8~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58701,49 +62629,49 @@ defparam \sdram_|r.state[4] .is_wysiwyg = "true"; defparam \sdram_|r.state[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 +// Location: LCCOMB_X23_Y19_N18 cycloneive_lcell_comb \sdram_|Mux72~0 ( // Equation(s): -// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux72~0_combout = (\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [0]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux72~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 +// Location: LCCOMB_X23_Y19_N20 cycloneive_lcell_comb \sdram_|Mux72~1 ( // Equation(s): -// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux72~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux72~0_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|r.state [4]), .datac(\sdram_|Mux72~0_combout ), - .datad(\D[0]~64_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), .combout(\sdram_|Mux72~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .lut_mask = 16'hC040; defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N0 +// Location: LCCOMB_X23_Y19_N6 cycloneive_lcell_comb \sdram_|Mux84~0 ( // Equation(s): -// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) +// \sdram_|Mux84~0_combout = (\sdram_|r.state [4]) # (\sdram_|r.state [5]) .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux84~0_combout ), .cout()); @@ -58752,245 +62680,245 @@ defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N2 +// Location: LCCOMB_X23_Y19_N28 cycloneive_lcell_comb \sdram_|Mux84~1 ( // Equation(s): -// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) +// \sdram_|Mux84~1_combout = (\sdram_|r.state [7] & (!\sdram_|r.state [8] & (\sdram_|r.state [6] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [6] & !\sdram_|Mux84~0_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|Mux84~0_combout ), .cin(gnd), .combout(\sdram_|Mux84~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .lut_mask = 16'h2004; defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 +// Location: LCCOMB_X23_Y19_N26 cycloneive_lcell_comb \sdram_|Mux3~0 ( // Equation(s): -// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux3~0_combout = (\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|data_pins_|dout [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), .combout(\sdram_|Mux3~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .lut_mask = 16'hAAFF; defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 +// Location: LCCOMB_X23_Y19_N8 cycloneive_lcell_comb \sdram_|Mux3~1 ( // Equation(s): -// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & (\sdram_|r.state [4] & ((\Selector12~11_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux3~0_combout ), - .datad(\D[1]~40_combout ), + .dataa(\sdram_|Mux3~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector12~11_combout ), .cin(gnd), .combout(\sdram_|Mux3~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .lut_mask = 16'h8808; defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 +// Location: LCCOMB_X27_Y19_N8 cycloneive_lcell_comb \sdram_|Mux2~0 ( // Equation(s): -// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux2~0_combout = (\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [2]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 +// Location: LCCOMB_X23_Y19_N30 cycloneive_lcell_comb \sdram_|Mux2~1 ( // Equation(s): -// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & (\sdram_|r.state [4] & ((\Selector10~3_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux2~0_combout ), - .datad(\D[2]~52_combout ), + .dataa(\sdram_|Mux2~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Selector10~3_combout ), + .datad(\Equal5~1_combout ), .cin(gnd), .combout(\sdram_|Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .lut_mask = 16'h8088; defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y16_N6 cycloneive_lcell_comb \sdram_|Mux1~0 ( // Equation(s): -// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux1~0_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\sdram_|Mux1~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N10 +// Location: LCCOMB_X24_Y15_N4 cycloneive_lcell_comb \sdram_|Mux1~1 ( // Equation(s): -// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux1~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux1~0_combout & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[3]~108_combout ), - .datad(\sdram_|Mux1~0_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|Mux1~0_combout ), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), .cin(gnd), .combout(\sdram_|Mux1~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .lut_mask = 16'h8808; defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N12 +// Location: LCCOMB_X25_Y16_N8 cycloneive_lcell_comb \sdram_|Mux0~0 ( // Equation(s): -// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux0~0_combout = (\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [4]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [4]), .cin(gnd), .combout(\sdram_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 +// Location: LCCOMB_X23_Y19_N12 cycloneive_lcell_comb \sdram_|Mux0~1 ( // Equation(s): -// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & (\sdram_|r.state [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux0~0_combout ), - .datad(\D[4]~110_combout ), + .dataa(\sdram_|Mux0~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), .combout(\sdram_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .lut_mask = 16'h8808; defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 +// Location: LCCOMB_X29_Y19_N4 cycloneive_lcell_comb \sdram_|Mux73~0 ( // Equation(s): -// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\D[5]~27_combout ) # (!\D[0]~49_combout ))) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[5]~27_combout ), .cin(gnd), .combout(\sdram_|Mux73~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .lut_mask = 16'hF030; defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux73~1 ( -// Equation(s): -// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux73~0_combout ), - .datad(\D[5]~112_combout ), - .cin(gnd), - .combout(\sdram_|Mux73~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; -defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N24 +// Location: LCCOMB_X26_Y16_N10 cycloneive_lcell_comb \sdram_|Mux74~0 ( // Equation(s): -// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux74~0_combout = (\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [6]), .cin(gnd), .combout(\sdram_|Mux74~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N6 +// Location: LCCOMB_X23_Y19_N14 cycloneive_lcell_comb \sdram_|Mux74~1 ( // Equation(s): -// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & (\sdram_|r.state [4] & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), + .dataa(\Equal5~1_combout ), .datab(\sdram_|Mux74~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~114_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[6]~46_combout ), .cin(gnd), .combout(\sdram_|Mux74~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .lut_mask = 16'hC040; defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X17_Y4_N28 +// Location: LCCOMB_X24_Y16_N8 cycloneive_lcell_comb \sdram_|Mux75~0 ( // Equation(s): -// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & ((\D[7]~37_combout ) # (!\D[0]~49_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\D[7]~117_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), .cin(gnd), .combout(\sdram_|Mux75~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .lut_mask = 16'hAA22; defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N8 +// Location: LCCOMB_X1_Y10_N16 +cycloneive_lcell_comb \LED~0 ( +// Equation(s): +// \LED~0_combout = (!\kempston[4]~input_o & \kempston_auto_fire~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\kempston[4]~input_o ), + .datad(\kempston_auto_fire~q ), + .cin(gnd), + .combout(\LED~0_combout ), + .cout()); +// synopsys translate_off +defparam \LED~0 .lut_mask = 16'h0F00; +defparam \LED~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -59007,7 +62935,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N9 +// Location: FF_X21_Y33_N13 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -59045,24 +62973,43 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N12 +// Location: FF_X24_Y19_N13 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N14 +// Location: LCCOMB_X25_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -59080,24 +63027,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N0 +// Location: LCCOMB_X25_Y30_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N1 +// Location: FF_X25_Y30_N29 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -59116,42 +63063,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N16 +// Location: LCCOMB_X25_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N6 +// Location: LCCOMB_X26_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N7 +// Location: FF_X26_Y30_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -59170,25 +63117,25 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N18 +// Location: LCCOMB_X25_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(\ula_|i2s_intf_|lrdivider [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N30 +// Location: LCCOMB_X26_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout @@ -59205,7 +63152,7 @@ defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N31 +// Location: FF_X26_Y30_N9 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -59224,7 +63171,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N20 +// Location: LCCOMB_X25_Y30_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -59242,24 +63189,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N4 +// Location: LCCOMB_X25_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~8_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N5 +// Location: FF_X25_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -59278,7 +63225,7 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N22 +// Location: LCCOMB_X25_Y30_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) @@ -59296,24 +63243,24 @@ defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N4 +// Location: LCCOMB_X26_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~10_combout ), + .datac(\ula_|i2s_intf_|Add0~10_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N5 +// Location: FF_X26_Y30_N7 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -59332,24 +63279,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N10 +// Location: LCCOMB_X25_Y30_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|lrdivider [4] & \ula_|i2s_intf_|lrdivider [2]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(\ula_|i2s_intf_|lrdivider [3]), - .datad(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(\ula_|i2s_intf_|lrdivider [4]), + .datad(\ula_|i2s_intf_|lrdivider [2]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N24 +// Location: LCCOMB_X25_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -59367,7 +63314,7 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N22 +// Location: LCCOMB_X26_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -59384,7 +63331,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N23 +// Location: FF_X26_Y30_N13 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -59403,42 +63350,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N26 +// Location: LCCOMB_X25_Y30_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N20 +// Location: LCCOMB_X26_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N21 +// Location: FF_X26_Y30_N11 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -59457,7 +63404,7 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N28 +// Location: LCCOMB_X25_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) @@ -59475,24 +63422,24 @@ defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N8 +// Location: LCCOMB_X25_Y30_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~16_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N9 +// Location: FF_X25_Y30_N1 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -59511,7 +63458,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N30 +// Location: LCCOMB_X25_Y30_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -59528,24 +63475,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X19_Y31_N24 +// Location: LCCOMB_X26_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~18_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y31_N25 +// Location: FF_X26_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -59564,73 +63511,54 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N6 +// Location: LCCOMB_X25_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [6] & !\ula_|i2s_intf_|lrdivider [8]))) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [8]), - .datad(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [9]), + .datab(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [8]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N2 +// Location: LCCOMB_X25_Y30_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|Equal0~0_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & !\ula_|i2s_intf_|lrdivider [1]))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|Equal0~0_combout ), - .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|lrdivider [1]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 +// Location: LCCOMB_X24_Y19_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q $ (\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(gnd), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59672,43 +63600,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 +// Location: LCCOMB_X24_Y23_N14 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -59726,303 +63618,50 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N25 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N17 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N19 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N21 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N23 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(\ula_|i2s_intf_|bitcount [0]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; -defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 +// Location: LCCOMB_X24_Y19_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): // \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add2~7_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N20 +// Location: LCCOMB_X24_Y19_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( // Equation(s): // \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) // \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~7_cout ), .combout(\ula_|i2s_intf_|Add2~8_combout ), .cout(\ula_|i2s_intf_|Add2~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N4 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( // Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|bdivider [0]) # (!\ula_|i2s_intf_|Equal1~0_combout )))) - .dataa(\ula_|i2s_intf_|bdivider [0]), + .dataa(\ula_|i2s_intf_|Equal1~0_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|Add2~8_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~20_combout ), .cout()); @@ -60031,7 +63670,7 @@ defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N5 +// Location: FF_X24_Y19_N31 dffeas \ula_|i2s_intf_|bdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~20_combout ), @@ -60050,7 +63689,7 @@ defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N22 +// Location: LCCOMB_X24_Y19_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( // Equation(s): // \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) @@ -60068,24 +63707,24 @@ defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N16 +// Location: LCCOMB_X24_Y23_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( // Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~10_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~10_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~10_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N17 +// Location: FF_X24_Y23_N31 dffeas \ula_|i2s_intf_|bdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~17_combout ), @@ -60104,42 +63743,42 @@ defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N24 +// Location: LCCOMB_X24_Y19_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( // Equation(s): // \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) // \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~11 ), .combout(\ula_|i2s_intf_|Add2~12_combout ), .cout(\ula_|i2s_intf_|Add2~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N14 +// Location: LCCOMB_X24_Y23_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( // Equation(s): // \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Add2~12_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Add2~12_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h0222; defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N15 +// Location: FF_X24_Y23_N1 dffeas \ula_|i2s_intf_|bdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~19_combout ), @@ -60158,7 +63797,7 @@ defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N26 +// Location: LCCOMB_X24_Y19_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( // Equation(s): // \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) @@ -60175,24 +63814,24 @@ defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N6 +// Location: LCCOMB_X24_Y23_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( // Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~14_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~14_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~14_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N7 +// Location: FF_X24_Y23_N25 dffeas \ula_|i2s_intf_|bdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~16_combout ), @@ -60211,78 +63850,333 @@ defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N2 +// Location: LCCOMB_X24_Y19_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & (!\ula_|i2s_intf_|bdivider [1] & \ula_|i2s_intf_|bdivider [4]))) - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(\ula_|i2s_intf_|bdivider [1]), + .datad(\ula_|i2s_intf_|bdivider [4]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0400; defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N28 +// Location: LCCOMB_X24_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (((!\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~0_combout )) # (!\ula_|i2s_intf_|bdivider [0]))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1303; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N27 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hAA00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) +// Location: FF_X24_Y23_N29 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), +// Location: LCCOMB_X24_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~9_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~9 .lut_mask = 16'hCCEC; +defparam \ula_|i2s_intf_|bitcount[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~10 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~10_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~11 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~10 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~12 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~12_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~11 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~11 )) +// \ula_|i2s_intf_|bitcount[3]~13 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~11 ), + .combout(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~14 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~14_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~13 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~13 ), + .combout(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~14 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [2]), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~1 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~1_combout = (\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]) + + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~1 .lut_mask = 16'hFF0F; +defparam \ula_|i2s_intf_|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~1_combout ))))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h0078; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -60298,15 +64192,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N16 +// Location: LCCOMB_X23_Y18_N26 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~38_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~109_combout ), + .datad(\D[3]~38_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -60315,41 +64209,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N30 +// Location: LCCOMB_X23_Y17_N0 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) +// \ula_|always0~2_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h00C0; +defparam \ula_|always0~2 .lut_mask = 16'h2020; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N2 +// Location: LCCOMB_X23_Y17_N24 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h0200; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N17 +// Location: FF_X23_Y18_N27 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -60368,538 +64262,25 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N7 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; -defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N29 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N15 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N17 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N23 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N13 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N19 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N9 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [7]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N3 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N5 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N11 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [10]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N1 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N27 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 +// Location: LCCOMB_X24_Y19_N26 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hD8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N11 +// Location: FF_X24_Y19_N27 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -60918,25 +64299,25 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N12 +// Location: LCCOMB_X24_Y19_N20 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INL [14])))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # +// (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INL [14]))))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hE4F0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N13 +// Location: FF_X24_Y19_N21 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -60955,24 +64336,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N0 +// Location: LCCOMB_X24_Y19_N14 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N1 +// Location: FF_X24_Y19_N15 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -60991,25 +64372,502 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N20 +// Location: LCCOMB_X24_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~18_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~18 .lut_mask = 16'h008C; +defparam \ula_|i2s_intf_|shiftreg[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|shiftreg[0]~18_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~18_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[7]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[7]~1_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7]~1 .lut_mask = 16'hECCC; +defparam \ula_|i2s_intf_|shiftreg[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N7 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [6]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [8]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [9]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [9]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [10]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|shiftreg [12]), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|pcm_outl [12]), + .datac(\ula_|i2s_intf_|shiftreg [11]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N21 -dffeas \ula_|i2s_intf_|shiftreg[13] ( +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), .asdata(vcc), @@ -61017,7 +64875,43 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [12])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [12]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|pcm_outl [12]), + .datad(\ula_|i2s_intf_|shiftreg [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hF3C0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -61027,33 +64921,33 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|pcm_outl [13]), .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF5A0; +defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N31 +// Location: FF_X24_Y21_N13 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .d(\ula_|i2s_intf_|shiftreg~4_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -61063,32 +64957,15 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N22 -cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( -// Equation(s): -// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[4]~111_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y19_N23 +// Location: FF_X25_Y19_N13 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[14]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[4]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -61099,33 +64976,33 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( +// Location: LCCOMB_X24_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [14]), .datad(\ula_|pcm_outl [14]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~4_combout ), + .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; -defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N25 +// Location: FF_X24_Y22_N21 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~4_combout ), + .d(\ula_|i2s_intf_|shiftreg~3_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -61135,33 +65012,33 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~3_combout ), + .combout(\ula_|i2s_intf_|shiftreg~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; -defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~2 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y33_N1 +// Location: FF_X24_Y30_N17 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~3_combout ), + .d(\ula_|i2s_intf_|shiftreg~2_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -61171,7 +65048,7 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N14 +// Location: LCCOMB_X24_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) @@ -61197,7 +65074,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -61207,1083 +65084,41 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y18_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( -// Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~41_combout ), - .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y18_N13 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N28 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N14 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N6 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N24 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N0 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N1 -dffeas \ula_|video_|attr_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N7 -dffeas \ula_|video_|attr[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( -// Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - - .dataa(gnd), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(gnd), - .datad(\ula_|video_|frame [0]), - .cin(gnd), - .combout(\ula_|video_|frame[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; -defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|frame[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( -// Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|frame[1]~4_combout ), - .cout(\ula_|video_|frame[1]~5 )); -// synopsys translate_off -defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; -defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|frame[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[1]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( -// Equation(s): -// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) -// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - - .dataa(gnd), - .datab(\ula_|video_|frame [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[1]~5 ), - .combout(\ula_|video_|frame[2]~6_combout ), - .cout(\ula_|video_|frame[2]~7 )); -// synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|frame[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[2]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( -// Equation(s): -// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) -// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - - .dataa(gnd), - .datab(\ula_|video_|frame [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[2]~7 ), - .combout(\ula_|video_|frame[3]~8_combout ), - .cout(\ula_|video_|frame[3]~9 )); -// synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|frame[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[3]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( -// Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|frame [4]), - .cin(\ula_|video_|frame[3]~9 ), - .combout(\ula_|video_|frame[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; -defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|frame[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N6 -cycloneive_lcell_comb \ula_|video_|inverted ( -// Equation(s): -// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|attr [7]), - .datad(\ula_|video_|frame [4]), - .cin(gnd), - .combout(\ula_|video_|inverted~combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|inverted .lut_mask = 16'hF000; -defparam \ula_|video_|inverted .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N29 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N5 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N26 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N27 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N29 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N14 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N15 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N24 -cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( -// Equation(s): -// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [5]), - .cin(gnd), - .combout(\ula_|video_|bits[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N12 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N13 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N20 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N21 -dffeas \ula_|video_|bits_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N14 -cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( -// Equation(s): -// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [2]), - .cin(gnd), - .combout(\ula_|video_|bits[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N15 -dffeas \ula_|video_|bits[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N18 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N19 -dffeas \ula_|video_|bits_prefetch[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N1 -dffeas \ula_|video_|bits[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N6 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N7 -dffeas \ula_|video_|bits_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N20 -cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( -// Equation(s): -// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|bits[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N21 -dffeas \ula_|video_|bits[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N24 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N25 -dffeas \ula_|video_|bits_prefetch[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N3 -dffeas \ula_|video_|bits[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N2 -cycloneive_lcell_comb \ula_|video_|Mux0~2 ( -// Equation(s): -// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), - .datac(\ula_|video_|bits [3]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Mux0~3 ( -// Equation(s): -// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), - .datac(\ula_|video_|bits [0]), - .datad(\ula_|video_|Mux0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N10 -cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( -// Equation(s): -// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - - .dataa(\ula_|video_|inverted~combout ), - .datab(\ula_|video_|Mux0~1_combout ), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|Mux0~3_combout ), - .cin(gnd), - .combout(\ula_|video_|cindex[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; -defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N17 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N4 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N5 +// Location: LCCOMB_X30_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -62302,7 +65137,24 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N19 +// Location: LCCOMB_X29_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N11 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62321,82 +65173,832 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N16 +// Location: LCCOMB_X25_Y31_N6 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N7 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N27 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N21 +dffeas \ula_|video_|attr_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N7 +dffeas \ula_|video_|attr[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N2 +cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( +// Equation(s): +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) + + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|frame [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|frame[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h3C3C; +defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y31_N3 +dffeas \ula_|video_|frame[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N14 +cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( +// Equation(s): +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) + + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|frame[1]~4_combout ), + .cout(\ula_|video_|frame[1]~5 )); +// synopsys translate_off +defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; +defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N15 +dffeas \ula_|video_|frame[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N16 +cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( +// Equation(s): +// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) +// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) + + .dataa(gnd), + .datab(\ula_|video_|frame [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[1]~5 ), + .combout(\ula_|video_|frame[2]~6_combout ), + .cout(\ula_|video_|frame[2]~7 )); +// synopsys translate_off +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N17 +dffeas \ula_|video_|frame[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N18 +cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( +// Equation(s): +// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) +// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) + + .dataa(gnd), + .datab(\ula_|video_|frame [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[2]~7 ), + .combout(\ula_|video_|frame[3]~8_combout ), + .cout(\ula_|video_|frame[3]~9 )); +// synopsys translate_off +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N19 +dffeas \ula_|video_|frame[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N20 +cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( +// Equation(s): +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame [4]), + .cin(\ula_|video_|frame[3]~9 ), + .combout(\ula_|video_|frame[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N1 +dffeas \ula_|video_|frame[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N6 +cycloneive_lcell_comb \ula_|video_|inverted ( +// Equation(s): +// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|attr [7]), + .datad(\ula_|video_|frame [4]), + .cin(gnd), + .combout(\ula_|video_|inverted~combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|inverted .lut_mask = 16'hF000; +defparam \ula_|video_|inverted .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N13 +dffeas \ula_|video_|bits_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N1 +dffeas \ula_|video_|bits[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N19 +dffeas \ula_|video_|bits_prefetch[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N31 +dffeas \ula_|video_|bits[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N15 +dffeas \ula_|video_|bits_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N22 +cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( +// Equation(s): +// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [1]), + .cin(gnd), + .combout(\ula_|video_|bits[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y31_N23 +dffeas \ula_|video_|bits[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N17 +dffeas \ula_|video_|bits_prefetch[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N21 +dffeas \ula_|video_|bits[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Mux0~2 ( +// Equation(s): +// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [1]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [3] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Mux0~3 ( +// Equation(s): +// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), + .datac(\ula_|video_|bits [0]), + .datad(\ula_|video_|Mux0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N4 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N5 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N29 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N11 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N19 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N30 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N31 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N25 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N9 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N29 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N16 +cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Equation(s): +// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~3_combout )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~1_combout ))))) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~3_combout ), + .datad(\ula_|video_|Mux0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|cindex[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h396C; +defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N26 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), + .dataa(\ula_|video_|attr [1]), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|attr [1]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N4 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y31_N20 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|video_|LessThan6~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N2 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N14 +// Location: LCCOMB_X27_Y31_N10 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): // \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~0_combout ), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~0_combout ), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N0 +// Location: LCCOMB_X26_Y31_N24 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [5]), .datab(gnd), - .datac(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), @@ -62406,84 +66008,189 @@ defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N4 +// Location: LCCOMB_X26_Y31_N30 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): // \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & // !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_hc [7]), .datac(\ula_|video_|vga_hc [9]), .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7A5E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N12 +// Location: LCCOMB_X27_Y31_N16 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [6]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h4F00; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N24 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) +// \ula_|video_|disp_enable~1_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & !\ula_|video_|LessThan2~1_combout )) - .dataa(gnd), - .datab(\ula_|video_|LessThan2~1_combout ), - .datac(\ula_|video_|LessThan3~0_combout ), - .datad(\ula_|video_|disp_enable~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), + .datac(gnd), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h0088; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N26 -cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( -// Equation(s): -// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - - .dataa(\ula_|border [1]), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), - .cin(gnd), - .combout(\ula_|video_|VGA_R[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; -defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N22 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N23 -dffeas \ula_|video_|attr_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), +// Location: FF_X24_Y19_N17 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[1]~12_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N0 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N26 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N24 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N10 +cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( +// Equation(s): +// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout )) # (!\ula_|video_|screen_en~1_combout & ((\ula_|border [1]))))) + + .dataa(\ula_|video_|cindex[1]~1_combout ), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [1]), + .datad(\ula_|video_|screen_en~1_combout ), + .cin(gnd), + .combout(\ula_|video_|VGA_R[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'h88C0; +defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N23 +dffeas \ula_|video_|attr_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62494,7 +66201,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y30_N29 +// Location: FF_X27_Y31_N27 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62513,66 +66220,49 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N28 +// Location: LCCOMB_X27_Y31_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & \ula_|video_|LessThan3~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|LessThan2~1_combout ), + .datad(\ula_|video_|LessThan3~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N6 +// Location: LCCOMB_X28_Y31_N4 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(gnd), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y27_N20 -cycloneive_lcell_comb \ula_|border[2]~feeder ( -// Equation(s): -// \ula_|border[2]~feeder_combout = \D[2]~53_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[2]~53_combout ), - .cin(gnd), - .combout(\ula_|border[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y27_N21 +// Location: FF_X24_Y19_N5 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[2]~13_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62583,79 +66273,24 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N30 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N31 -dffeas \ula_|video_|attr_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N31 -dffeas \ula_|video_|attr[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N16 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N17 +// Location: FF_X25_Y31_N25 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -62674,15 +66309,32 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N13 +// Location: LCCOMB_X28_Y31_N30 +cycloneive_lcell_comb \ula_|video_|attr[2]~feeder ( +// Equation(s): +// \ula_|video_|attr[2]~feeder_combout = \ula_|video_|attr_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|attr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N31 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), + .d(\ula_|video_|attr[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62693,48 +66345,103 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N30 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 +dffeas \ula_|video_|attr_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N5 +dffeas \ula_|video_|attr[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N4 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|attr [2]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N0 +// Location: LCCOMB_X29_Y31_N2 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|border [2]), - .datad(\ula_|video_|cindex[2]~2_combout ), + .dataa(\ula_|border [2]), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|video_|cindex[2]~2_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC088; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N18 +// Location: LCCOMB_X28_Y31_N12 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[2]~2_combout )) - .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), @@ -62744,32 +66451,15 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~65_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~65_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 +// Location: FF_X23_Y20_N25 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~14_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62780,24 +66470,24 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N8 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N9 +// Location: FF_X25_Y31_N1 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -62816,15 +66506,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N23 +// Location: LCCOMB_X28_Y31_N2 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N3 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62835,24 +66542,24 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -62871,7 +66578,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N9 +// Location: FF_X29_Y31_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62890,47 +66597,47 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N8 +// Location: LCCOMB_X29_Y31_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[2]~0_combout ), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N26 +// Location: LCCOMB_X29_Y31_N6 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[0]~3_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N12 +// Location: LCCOMB_X29_Y31_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|cindex[0]~3_combout ), - .datab(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|cindex[0]~3_combout ), .datac(gnd), .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), @@ -62941,24 +66648,7 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~2 ( -// Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; -defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y29_N1 +// Location: FF_X30_Y31_N13 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -62977,16 +66667,33 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N0 +// Location: LCCOMB_X30_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Equal0~2 ( +// Equation(s): +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9])) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h000A; +defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N12 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~1_combout & ((\ula_|video_|Equal0~2_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~1_combout & (\ula_|video_|Equal1~0_combout & // (\ula_|video_|VGA_HS~_Duplicate_1_q ))) - .dataa(\ula_|video_|Equal0~2_combout ), + .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); @@ -63014,7 +66721,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X31_Y31_N29 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -63033,21 +66740,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X31_Y31_N28 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((!\ula_|video_|Equal3~1_combout & \ula_|video_|VGA_VS~_Duplicate_1_q )))) # (!\ula_|video_|Equal2~2_combout & (!\ula_|video_|Equal3~1_combout & +// (\ula_|video_|VGA_VS~_Duplicate_1_q ))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hBA30; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63070,7 +66777,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N4 +// Location: LCCOMB_X36_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -63087,7 +66794,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N5 +// Location: FF_X36_Y11_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -63106,7 +66813,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y13_N3 +// Location: FF_X36_Y11_N1 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -63125,7 +66832,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 +// Location: LCCOMB_X36_Y11_N0 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -63142,41 +66849,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N24 +// Location: LCCOMB_X52_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF33; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N24 +// Location: LCCOMB_X23_Y18_N4 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~38_combout $ (\D[4]~39_combout )) - .dataa(\D[3]~109_combout ), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\D[4]~111_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~38_combout ), + .datac(gnd), + .datad(\D[4]~39_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA55A; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N25 +// Location: FF_X23_Y18_N5 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -63195,160 +66902,194 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N4 +// Location: LCCOMB_X29_Y8_N18 cycloneive_lcell_comb \sdram_|Mux26~4 ( // Equation(s): // \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.address[3]~6_combout ), .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), .combout(\sdram_|Mux26~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .lut_mask = 16'h0F05; defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N10 -cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( -// Equation(s): -// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.bank[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; -defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N8 -cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( -// Equation(s): -// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.bank[0]~7_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; -defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( -// Equation(s): -// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; -defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( -// Equation(s): -// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.bank[0]~4_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; -defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N4 +// Location: LCCOMB_X19_Y13_N28 cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( // Equation(s): -// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # -// (\sdram_|r.bank[0]~5_combout ))))) +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.bank[0]~5_combout ), + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.bank[0]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hA005; defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( // Equation(s): -// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) +// \sdram_|r.bank[0]~4_combout = (\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.bank[0]~8_combout ), + .combout(\sdram_|r.bank[0]~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; -defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hFC00; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N18 +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [6] & ((\sdram_|r.bank[0]~4_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'hF888; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( // Equation(s): -// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) +// \sdram_|r.bank[0]~12_combout = ((!\sdram_|r.bank[0]~5_combout & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|r.bank[0]~6_combout ) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.bank[0]~11_combout ), - .datad(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.bank[0]~6_combout ), + .datac(\sdram_|r.bank[0]~5_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'h373F; defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N2 +// Location: LCCOMB_X19_Y13_N22 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [5]) # ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hAFFF; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [7] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'h5A7A; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( // Equation(s): -// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [4]) # ((\sdram_|r.bank[0]~8_combout ) # ((\sdram_|r.state [5] & !\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.bank[0]~11_combout ), - .datac(\sdram_|r.bank[0]~6_combout ), - .datad(\sdram_|r.bank[0]~12_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~8_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'hFFF2; defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~9_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~7_combout ), + .datad(\sdram_|r.bank[0]~9_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'hB9A8; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~13 ( +// Equation(s): +// \sdram_|r.bank[0]~13_combout = ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [7])))) # (!\sdram_|r.bank[0]~5_combout ) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.bank[0]~5_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~13 .lut_mask = 16'h7FFB; +defparam \sdram_|r.bank[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N26 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.state [8] & ((\sdram_|r.bank[0]~10_combout & ((!\sdram_|r.bank[0]~13_combout ))) # (!\sdram_|r.bank[0]~10_combout & (!\sdram_|r.bank[0]~12_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~10_combout +// )))) + + .dataa(\sdram_|r.bank[0]~12_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~10_combout ), + .datad(\sdram_|r.bank[0]~13_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'h07C7; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X11_Y0_N18 dffeas \sdram_|r.bank[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -63358,7 +67099,7 @@ dffeas \sdram_|r.bank[0] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [0]), @@ -63368,20 +67109,20 @@ defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; defparam \sdram_|r.bank[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N2 +// Location: LCCOMB_X29_Y8_N26 cycloneive_lcell_comb \sdram_|Mux25~4 ( // Equation(s): // \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [10]), + .datab(\sdram_|r.address[3]~6_combout ), .datac(gnd), - .datad(\sdram_|r.address[3]~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\sdram_|Mux25~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .lut_mask = 16'h2233; defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63394,7 +67135,7 @@ dffeas \sdram_|r.bank[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [1]), @@ -63404,146 +67145,146 @@ defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; defparam \sdram_|r.bank[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux71~6 ( // Equation(s): -// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) +// \sdram_|Mux71~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [4] & \sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux24~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; -defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux71~0 ( -// Equation(s): -// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|Mux71~0_combout ), + .combout(\sdram_|Mux71~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; -defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux71~6 .lut_mask = 16'hF710; +defparam \sdram_|Mux71~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N4 -cycloneive_lcell_comb \sdram_|process_0~7 ( -// Equation(s): -// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\sdram_|r.act_row [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\sdram_|process_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; -defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N28 -cycloneive_lcell_comb \sdram_|process_0~4 ( -// Equation(s): -// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|process_0~7_combout ), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|process_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; -defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux71~1 ( -// Equation(s): -// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux71~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; -defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N28 +// Location: LCCOMB_X20_Y15_N0 cycloneive_lcell_comb \sdram_|Mux71~2 ( // Equation(s): -// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) +// \sdram_|Mux71~2_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux71~1_combout ), - .datad(\sdram_|Mux71~0_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux71~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .lut_mask = 16'h000F; defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N14 +// Location: LCCOMB_X20_Y15_N16 cycloneive_lcell_comb \sdram_|Mux71~3 ( // Equation(s): -// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) +// \sdram_|Mux71~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [7])) # (!\sdram_|Mux71~2_combout ))) # (!\sdram_|r.state [8] & ((\sdram_|Mux71~2_combout ) # ((!\sdram_|Mux4~0_combout )))) - .dataa(\sdram_|process_0~4_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux71~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux71~2_combout ), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux71~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .lut_mask = 16'hEF67; defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N4 +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \sdram_|process_0~8 ( +// Equation(s): +// \sdram_|process_0~8_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\sdram_|process_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~8 .lut_mask = 16'h0FA5; +defparam \sdram_|process_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (((\sdram_|process_0~8_combout ) # (!\sdram_|Equal7~1_combout )) # (!\sdram_|Equal7~0_combout )) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|process_0~8_combout ), + .datad(\sdram_|Equal7~1_combout ), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hF7FF; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 cycloneive_lcell_comb \sdram_|Mux71~4 ( // Equation(s): -// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) +// \sdram_|Mux71~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux71~6_combout & ((\sdram_|Mux71~3_combout ) # (\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux71~3_combout )))) - .dataa(\sdram_|Mux24~5_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|Mux71~3_combout ), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|Mux71~6_combout ), + .datab(\sdram_|Mux71~3_combout ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux71~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .lut_mask = 16'hA8CC; defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux24~8 ( +// Equation(s): +// \sdram_|Mux24~8_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~8 .lut_mask = 16'h0307; +defparam \sdram_|Mux24~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux71~5 ( +// Equation(s): +// \sdram_|Mux71~5_combout = (\sdram_|Mux71~4_combout ) # ((\sdram_|Mux24~8_combout & ((\sdram_|r.state [7]) # (\sdram_|Mux71~2_combout )))) + + .dataa(\sdram_|Mux71~4_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~8_combout ), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~5 .lut_mask = 16'hFAEA; +defparam \sdram_|Mux71~5 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y0_N11 dffeas \sdram_|r.dq_masks[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63562,7 +67303,7 @@ defparam \sdram_|r.dq_masks[0] .power_up = "low"; // Location: DDIOOUTCELL_X14_Y0_N18 dffeas \sdram_|r.dq_masks[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63578,248 +67319,248 @@ defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; defparam \sdram_|r.dq_masks[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N2 -cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \sdram_|n~6 ( // Equation(s): -// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) +// \sdram_|n~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.bank[0]~10_combout ), + .combout(\sdram_|n~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; -defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +defparam \sdram_|n~6 .lut_mask = 16'h5051; +defparam \sdram_|n~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N18 -cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Location: LCCOMB_X19_Y19_N12 +cycloneive_lcell_comb \sdram_|Mux9~0 ( // Equation(s): -// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) +// \sdram_|Mux9~0_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [7] & ((!\sdram_|r.state [4]))) # (!\sdram_|r.state [7] & ((\sdram_|n~6_combout ) # (\sdram_|r.state [4]))))) + + .dataa(\sdram_|n~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~0 .lut_mask = 16'h3E00; +defparam \sdram_|Mux9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N14 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|r.state [6] & (!\sdram_|n~2_combout & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (((\sdram_|n~6_combout )))) .dataa(\sdram_|n~2_combout ), .datab(\sdram_|r.state [6]), .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.bank[0]~10_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; -defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N30 -cycloneive_lcell_comb \sdram_|n~5 ( -// Equation(s): -// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|n~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|n~5 .lut_mask = 16'h3031; -defparam \sdram_|n~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N12 -cycloneive_lcell_comb \sdram_|Mux9~4 ( -// Equation(s): -// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) - - .dataa(\sdram_|Mux9~3_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux9~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N4 -cycloneive_lcell_comb \sdram_|Mux9~2 ( -// Equation(s): -// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux9~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; -defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N30 -cycloneive_lcell_comb \sdram_|Equal2~3 ( -// Equation(s): -// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Equal2~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; -defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N8 -cycloneive_lcell_comb \sdram_|Mux10~2 ( -// Equation(s): -// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [4]), - .cin(gnd), - .combout(\sdram_|Mux10~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; -defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N26 -cycloneive_lcell_comb \sdram_|Mux10~3 ( -// Equation(s): -// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) - - .dataa(\sdram_|r.init_counter [2]), - .datab(\sdram_|r.init_counter [3]), - .datac(\sdram_|Mux10~2_combout ), - .datad(\sdram_|r.init_counter [1]), - .cin(gnd), - .combout(\sdram_|Mux10~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; -defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N4 -cycloneive_lcell_comb \sdram_|process_0~6 ( -// Equation(s): -// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|process_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~6 .lut_mask = 16'h0010; -defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N24 -cycloneive_lcell_comb \sdram_|Mux10~4 ( -// Equation(s): -// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) - - .dataa(\sdram_|Mux10~3_combout ), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|process_0~6_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux10~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; -defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux9~5 ( -// Equation(s): -// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|n~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; -defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N20 -cycloneive_lcell_comb \sdram_|Mux7~0 ( -// Equation(s): -// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; -defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~6 ( -// Equation(s): -// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|Mux10~4_combout ), - .datac(\sdram_|Mux9~5_combout ), - .datad(\sdram_|Mux7~0_combout ), + .datad(\sdram_|n~6_combout ), .cin(gnd), .combout(\sdram_|Mux9~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .lut_mask = 16'h7340; defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N24 +// Location: LCCOMB_X19_Y19_N0 cycloneive_lcell_comb \sdram_|Mux9~7 ( // Equation(s): -// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~6_combout & ((\sdram_|r.state [6]) # ((\sdram_|r.state [5]) # (\sdram_|r.state [7])))) # (!\sdram_|Mux9~6_combout & ((\sdram_|r.state [5] $ (\sdram_|r.state [7])))) - .dataa(\sdram_|Mux9~4_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|Mux9~2_combout ), - .datad(\sdram_|Mux9~6_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux9~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux9~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .lut_mask = 16'hCFF8; defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y19_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h000F; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (!\sdram_|r.init_counter [0] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h4000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (\sdram_|process_0~5_combout & (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14]))) + + .dataa(\sdram_|process_0~5_combout ), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0002; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [6]), + .datab(gnd), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h0500; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \sdram_|Equal5~1 ( +// Equation(s): +// \sdram_|Equal5~1_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal5~0_combout & (\sdram_|r.init_counter [1] & \sdram_|process_0~6_combout ))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal5~0_combout ), + .datac(\sdram_|r.init_counter [1]), + .datad(\sdram_|process_0~6_combout ), + .cin(gnd), + .combout(\sdram_|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~1 .lut_mask = 16'h8000; +defparam \sdram_|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = (!\sdram_|r.init_counter [7] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [2] & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [7]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h4000; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (!\sdram_|Equal5~1_combout & (((!\sdram_|process_0~7_combout ) # (!\sdram_|process_0~6_combout )) # (!\sdram_|r.init_counter [3]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|process_0~6_combout ), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|process_0~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'h070F; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N6 +cycloneive_lcell_comb \sdram_|Mux9~1 ( +// Equation(s): +// \sdram_|Mux9~1_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~1 .lut_mask = 16'hFFD0; +defparam \sdram_|Mux9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N2 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|Mux9~1_combout ) # ((\sdram_|Mux7~0_combout & (!\sdram_|Equal2~3_combout & \sdram_|Mux10~2_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|Equal2~3_combout ), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux9~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'hFF20; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|Mux9~0_combout ) # ((\sdram_|Mux9~7_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~2_combout ))) + + .dataa(\sdram_|Mux9~0_combout ), + .datab(\sdram_|Mux9~7_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux9~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hEFEE; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X0_Y11_N4 dffeas \sdram_|r.state[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux9~7_combout ), + .d(\sdram_|Mux9~3_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63835,112 +67576,163 @@ defparam \sdram_|r.state[2] .is_wysiwyg = "true"; defparam \sdram_|r.state[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux10~11 ( -// Equation(s): -// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; -defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N12 +// Location: LCCOMB_X19_Y17_N12 cycloneive_lcell_comb \sdram_|Mux10~6 ( // Equation(s): -// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) +// \sdram_|Mux10~6_combout = (\sdram_|r.state [4] & (((\sdram_|r.rd_pending~q & \sdram_|r.state [6])) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & (((\sdram_|r.state [6]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Mux10~11_combout ), - .datac(\sdram_|process_0~4_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .lut_mask = 16'hD5FA; defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N26 +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((\sdram_|Mux10~2_combout & !\sdram_|Mux10~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h6676; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.state [8]) # ((\sdram_|r.state [4] & \sdram_|r.state [7])))) # (!\sdram_|r.rf_pending~q & (\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'hEEA2; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [8])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [8]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'h1120; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 cycloneive_lcell_comb \sdram_|Mux10~5 ( // Equation(s): -// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) +// \sdram_|Mux10~5_combout = (\sdram_|r.state [6] & ((\sdram_|Mux10~3_combout ) # ((!\sdram_|Mux10~4_combout )))) # (!\sdram_|r.state [6] & ((\sdram_|Mux10~4_combout & ((!\sdram_|n~4_combout ))) # (!\sdram_|Mux10~4_combout & (\sdram_|Mux10~3_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~3_combout ), + .datac(\sdram_|n~4_combout ), .datad(\sdram_|Mux10~4_combout ), .cin(gnd), .combout(\sdram_|Mux10~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .lut_mask = 16'h8DEE; defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N10 +// Location: LCCOMB_X19_Y17_N22 cycloneive_lcell_comb \sdram_|Mux10~7 ( // Equation(s): -// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & ((\sdram_|r.wr_pending~q ) # ((!\sdram_|r.rf_pending~q & \sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|r.rf_pending~q )) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .lut_mask = 16'hDACA; defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N20 +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~6_combout ) # ((!\sdram_|r.state [6] & !\sdram_|n~4_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|n~4_combout ), + .datac(\sdram_|Mux10~7_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hFFF1; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux10~12 ( +// Equation(s): +// \sdram_|Mux10~12_combout = (\sdram_|r.state [7] & (((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (\sdram_|r.state [6] & (\sdram_|process_0~3_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~12 .lut_mask = 16'hEC20; +defparam \sdram_|Mux10~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 cycloneive_lcell_comb \sdram_|Mux10~8 ( // Equation(s): -// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) +// \sdram_|Mux10~8_combout = (\sdram_|Mux10~10_combout ) # ((\sdram_|Mux10~12_combout ) # ((!\sdram_|r.state [7] & \sdram_|Mux10~5_combout ))) - .dataa(\sdram_|Mux10~7_combout ), + .dataa(\sdram_|Mux10~10_combout ), .datab(\sdram_|r.state [7]), .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~11_combout ), + .datad(\sdram_|Mux10~12_combout ), .cin(gnd), .combout(\sdram_|Mux10~8_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .lut_mask = 16'hFFBA; defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux10~9 ( -// Equation(s): -// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) - - .dataa(\sdram_|Mux10~6_combout ), - .datab(\sdram_|r.bank[0]~10_combout ), - .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux10~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; -defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y11_N11 dffeas \sdram_|r.state[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux10~9_combout ), + .d(\sdram_|Mux10~8_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63969,146 +67761,129 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux11~2 ( -// Equation(s): -// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux11~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; -defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux11~3 ( -// Equation(s): -// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|Mux11~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux11~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; -defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N26 +// Location: LCCOMB_X18_Y17_N26 cycloneive_lcell_comb \sdram_|Mux11~4 ( // Equation(s): -// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) +// \sdram_|Mux11~4_combout = (\sdram_|r.state [5] & ((\sdram_|r.state [8] $ (\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & (\sdram_|r.state [7])) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|Mux11~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux11~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .lut_mask = 16'h6EE6; defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N28 +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|r.state [6] & (((\sdram_|n~6_combout ) # (!\sdram_|r.state [8])) # (!\sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hCC4C; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (!\sdram_|Equal2~3_combout & (!\sdram_|r.state [8] & (!\sdram_|Equal5~1_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'h0001; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~2_combout ) # ((!\sdram_|Mux23~0_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|Mux11~2_combout ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 cycloneive_lcell_comb \sdram_|Mux11~5 ( // Equation(s): -// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) +// \sdram_|Mux11~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((\sdram_|r.state [8] & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux11~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .lut_mask = 16'h0C0E; defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N0 +// Location: LCCOMB_X18_Y17_N10 cycloneive_lcell_comb \sdram_|Mux11~6 ( // Equation(s): -// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) +// \sdram_|Mux11~6_combout = (\sdram_|Mux11~5_combout & (!\sdram_|r.wr_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|Mux11~5_combout ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux11~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .lut_mask = 16'h008A; defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N30 +// Location: LCCOMB_X18_Y17_N24 cycloneive_lcell_comb \sdram_|Mux11~7 ( // Equation(s): -// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) +// \sdram_|Mux11~7_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~8_combout ) # ((\sdram_|Mux11~3_combout ) # (\sdram_|Mux11~6_combout ))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~8_combout ), + .datac(\sdram_|Mux11~3_combout ), .datad(\sdram_|Mux11~6_combout ), .cin(gnd), .combout(\sdram_|Mux11~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .lut_mask = 16'hFFFE; defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux11~9 ( -// Equation(s): -// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|Mux7~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; -defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N14 -cycloneive_lcell_comb \sdram_|Mux11~8 ( -// Equation(s): -// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) - - .dataa(\sdram_|Mux11~4_combout ), - .datab(\sdram_|Mux11~5_combout ), - .datac(\sdram_|Mux11~7_combout ), - .datad(\sdram_|Mux11~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; -defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y27_N4 dffeas \sdram_|r.state[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux11~8_combout ), + .d(\sdram_|Mux11~7_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -64124,75 +67899,41 @@ defparam \sdram_|r.state[0] .is_wysiwyg = "true"; defparam \sdram_|r.state[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \sdram_|Mux24~5 ( // Equation(s): -// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) +// \sdram_|Mux24~5_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[11]~18_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q )))) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux24~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; -defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N2 -cycloneive_lcell_comb \sdram_|r.address[0]~7 ( -// Equation(s): -// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .dataa(\sdram_|process_0~4_combout ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\sdram_|Mux23~0_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~7_combout ), + .combout(\sdram_|Mux24~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; -defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~5 .lut_mask = 16'hE400; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N12 -cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \sdram_|Mux24~6 ( // Equation(s): -// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) +// \sdram_|Mux24~6_combout = (\sdram_|Mux24~5_combout ) # ((!\sdram_|n~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.address[0]~_Duplicate_1_q ), - .datad(\sdram_|r.address[0]~7_combout ), + .dataa(\sdram_|n~4_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux24~5_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~0_combout ), + .combout(\sdram_|Mux24~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; -defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~6 .lut_mask = 16'hFF04; +defparam \sdram_|Mux24~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux13~9 ( -// Equation(s): -// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux13~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; -defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N0 +// Location: LCCOMB_X21_Y16_N6 cycloneive_lcell_comb \sdram_|Mux13~4 ( // Equation(s): // \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) @@ -64209,28 +67950,45 @@ defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N2 +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 cycloneive_lcell_comb \sdram_|Mux13~5 ( // Equation(s): -// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux13~9_combout ))) - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux13~9_combout ), - .datad(\sdram_|Mux13~4_combout ), + .dataa(\sdram_|Mux13~4_combout ), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux13~9_combout ), .cin(gnd), .combout(\sdram_|Mux13~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .lut_mask = 16'hAFA0; defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N13 +// Location: FF_X20_Y14_N21 dffeas \sdram_|r.address[0]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[0]~0_combout ), - .asdata(\sdram_|Mux24~4_combout ), + .asdata(\sdram_|Mux24~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64245,54 +68003,88 @@ defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N4 +// Location: LCCOMB_X19_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & (\z80_|address_pins_|abus[11]~18_combout )) # (!\sdram_|process_0~4_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hD800; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 cycloneive_lcell_comb \sdram_|Mux24~3 ( // Equation(s): -// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) +// \sdram_|Mux24~3_combout = (\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q ) - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux24~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .lut_mask = 16'hFF55; defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N14 +// Location: LCCOMB_X21_Y14_N6 cycloneive_lcell_comb \sdram_|Mux24~4 ( // Equation(s): -// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) +// \sdram_|Mux24~4_combout = (\sdram_|r.address[0]~_Duplicate_1_q & (((!\sdram_|r.rd_pending~q & \sdram_|Mux24~3_combout )) # (!\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|n~3_combout ), + .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux24~3_combout ), - .datad(\sdram_|r.state [6]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux24~3_combout ), .cin(gnd), .combout(\sdram_|Mux24~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .lut_mask = 16'h4C0C; defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N24 +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & ((\sdram_|Mux24~4_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux24~2_combout )) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux24~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'hEE22; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux24~6_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[0]~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux24~4_combout ), - .datad(\sdram_|r.address[0]~0_combout ), + .datab(\sdram_|r.address[0]~0_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux24~6_combout ), .cin(gnd), .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64315,114 +68107,148 @@ defparam \sdram_|r.address[0] .is_wysiwyg = "true"; defparam \sdram_|r.address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N16 +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [4] & (\sdram_|process_0~4_combout & ((\sdram_|Equal7~2_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'h8880; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~8 ( +// Equation(s): +// \sdram_|r.address[1]~8_combout = (\sdram_|r.state [4]) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~8 .lut_mask = 16'hEEFF; +defparam \sdram_|r.address[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[1]~9 ( +// Equation(s): +// \sdram_|r.address[1]~9_combout = (\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~9 .lut_mask = 16'hDD00; +defparam \sdram_|r.address[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \sdram_|r.address[1]~7 ( +// Equation(s): +// \sdram_|r.address[1]~7_combout = (\sdram_|r.address[1]~_Duplicate_1_q & (((\sdram_|r.state [8]) # (!\sdram_|r.state [6])) # (!\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~7 .lut_mask = 16'hF070; +defparam \sdram_|r.address[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|r.address[1]~10 ( +// Equation(s): +// \sdram_|r.address[1]~10_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~9_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[1]~7_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[1]~9_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~10 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~8_combout & (\sdram_|r.address[1]~10_combout ))) # (!\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~7_combout & ((\sdram_|r.address[1]~8_combout ) # +// (!\sdram_|r.address[1]~10_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|r.address[1]~8_combout ), + .datac(\sdram_|r.address[1]~10_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hC580; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( // Equation(s): // \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout - .dataa(\sdram_|r.address[1]~1_combout ), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hFF00; defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux23~4 ( -// Equation(s): -// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & -// (\sdram_|r.address[1]~_Duplicate_1_q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\z80_|address_pins_|abus[12]~24_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; -defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N16 -cycloneive_lcell_comb \sdram_|Equal5~0 ( -// Equation(s): -// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Equal5~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; -defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux23~5 ( -// Equation(s): -// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux23~4_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Equal5~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; -defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux23~6 ( -// Equation(s): -// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|Mux23~5_combout ), - .datad(\sdram_|Mux24~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; -defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N2 +// Location: LCCOMB_X21_Y16_N30 cycloneive_lcell_comb \sdram_|Mux19~0 ( // Equation(s): // \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .lut_mask = 16'h9299; defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y12_N17 +// Location: FF_X25_Y16_N25 dffeas \sdram_|r.address[1]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), - .asdata(\sdram_|Mux23~6_combout ), + .asdata(\sdram_|Mux23~5_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64437,88 +68263,89 @@ defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N28 -cycloneive_lcell_comb \sdram_|Mux23~2 ( -// Equation(s): -// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux23~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; -defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N30 +// Location: LCCOMB_X20_Y17_N2 cycloneive_lcell_comb \sdram_|Mux23~3 ( // Equation(s): -// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) +// \sdram_|Mux23~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.address[1]~_Duplicate_1_q )))) # (!\sdram_|r.state [8] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[12]~21_combout ))) # (!\sdram_|process_0~4_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|Mux23~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), .cin(gnd), .combout(\sdram_|Mux23~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .lut_mask = 16'hF4B0; defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N18 -cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Location: LCCOMB_X20_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux23~4 ( // Equation(s): -// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (((\sdram_|Mux23~3_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((\sdram_|Mux23~3_combout ))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )))) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|Mux23~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hCCCA; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = ((!\sdram_|r.rd_pending~q & ((\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|Equal7~2_combout ) .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux23~1_combout ), + .combout(\sdram_|Mux23~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; -defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~2 .lut_mask = 16'h33BF; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N22 -cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( // Equation(s): -// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) +// \sdram_|Mux23~5_combout = (\sdram_|Mux23~4_combout & (((\sdram_|Mux23~2_combout ) # (\sdram_|r.state [4])) # (!\sdram_|r.state [8]))) - .dataa(gnd), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~3_combout ), - .datad(\sdram_|Mux23~1_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|Mux23~2_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.address[1]~1_combout ), + .combout(\sdram_|Mux23~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; -defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~5 .lut_mask = 16'hCCC4; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N2 +// Location: LCCOMB_X21_Y16_N4 cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|r.address[1]~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux23~5_combout )) - .dataa(\sdram_|r.address[1]~1_combout ), - .datab(\sdram_|Mux23~6_combout ), + .dataa(gnd), + .datab(\sdram_|Mux23~5_combout ), .datac(\sdram_|r.state [7]), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64541,211 +68368,211 @@ defparam \sdram_|r.address[1] .is_wysiwyg = "true"; defparam \sdram_|r.address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N10 -cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( // Equation(s): -// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[3]~8_combout ), + .combout(\sdram_|r.address[3]~11_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; -defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h5F5C; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N24 -cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( // Equation(s): -// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) +// \sdram_|r.address[3]~12_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|r.address[3]~9_combout ), + .combout(\sdram_|r.address[3]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; -defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hF000; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N26 +// Location: LCCOMB_X23_Y14_N28 cycloneive_lcell_comb \sdram_|Mux21~0 ( // Equation(s): -// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~11_combout & ((\sdram_|r.address[3]~12_combout ) # ((\sdram_|r.state [4] & \sdram_|r.address[3]~6_combout )))) - .dataa(\sdram_|r.address[3]~6_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.address[3]~9_combout ), - .datad(\sdram_|r.address[3]~8_combout ), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.address[3]~12_combout ), .cin(gnd), .combout(\sdram_|Mux21~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .lut_mask = 16'h5540; defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N18 +// Location: LCCOMB_X24_Y8_N12 cycloneive_lcell_comb \sdram_|Mux22~0 ( // Equation(s): -// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[1]~27_combout ) # ((\z80_|address_pins_|abus[13]~20_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[13]~20_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[1]~25_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[1]~27_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux22~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .lut_mask = 16'hECA0; defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N20 -cycloneive_lcell_comb \sdram_|r.address[3]~10 ( -// Equation(s): -// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.address[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; -defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N14 -cycloneive_lcell_comb \sdram_|r.address[3]~11 ( -// Equation(s): -// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|r.address[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; -defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N0 -cycloneive_lcell_comb \sdram_|r.address[3]~12 ( -// Equation(s): -// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~11_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; -defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N6 -cycloneive_lcell_comb \sdram_|r.address[3]~13 ( -// Equation(s): -// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[3]~10_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.address[3]~12_combout ), - .cin(gnd), - .combout(\sdram_|r.address[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; -defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N16 +// Location: LCCOMB_X18_Y17_N12 cycloneive_lcell_comb \sdram_|r.address[3]~14 ( // Equation(s): -// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), + .dataa(gnd), + .datab(\sdram_|r.state [4]), .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.address[3]~14_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h33CF; defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N22 +// Location: LCCOMB_X18_Y17_N30 cycloneive_lcell_comb \sdram_|r.address[3]~15 ( // Equation(s): -// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [8] & ((\sdram_|r.state [4]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4]))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~14_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.address[3]~14_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~15_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hFF9B; defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N24 +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|r.state [4])) # (!\sdram_|r.state [7]) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'h37FF; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 cycloneive_lcell_comb \sdram_|r.address[3]~16 ( // Equation(s): -// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~15_combout )))) - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [5]), .datac(\sdram_|r.address[3]~15_combout ), - .datad(\sdram_|r.state [8]), + .datad(\sdram_|r.address[3]~13_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~16_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .lut_mask = 16'hFC74; defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N26 +// Location: LCCOMB_X19_Y13_N24 cycloneive_lcell_comb \sdram_|r.address[3]~17 ( // Equation(s): -// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & (!\sdram_|r.wr_pending~q & \sdram_|r.state [4]))) - .dataa(\sdram_|r.address[3]~13_combout ), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.address[3]~16_combout ), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|r.address[3]~17_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .lut_mask = 16'hAB02; defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~18 ( +// Equation(s): +// \sdram_|r.address[3]~18_combout = (\sdram_|r.address[3]~17_combout ) # ((\sdram_|r.state [7] & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (\sdram_|r.state [5]))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[3]~17_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~18 .lut_mask = 16'hDEFE; +defparam \sdram_|r.address[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~19 ( +// Equation(s): +// \sdram_|r.address[3]~19_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout ) # (!\sdram_|n~4_combout )))) # (!\sdram_|r.state [8] & (\sdram_|r.address[3]~18_combout )) + + .dataa(\sdram_|r.address[3]~18_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.bank[0]~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~19 .lut_mask = 16'h2EEE; +defparam \sdram_|r.address[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[3]~20 ( +// Equation(s): +// \sdram_|r.address[3]~20_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~16_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~19_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[3]~16_combout ), + .datad(\sdram_|r.address[3]~19_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~20 .lut_mask = 16'h0A5F; +defparam \sdram_|r.address[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X5_Y0_N4 dffeas \sdram_|r.address[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -64755,7 +68582,7 @@ dffeas \sdram_|r.address[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [2]), @@ -64765,21 +68592,21 @@ defparam \sdram_|r.address[2] .is_wysiwyg = "true"; defparam \sdram_|r.address[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N2 +// Location: LCCOMB_X24_Y8_N4 cycloneive_lcell_comb \sdram_|Mux21~1 ( // Equation(s): -// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[2]~28_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[14]~22_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[2]~26_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[2]~28_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux21~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .lut_mask = 16'hECA0; defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -64792,7 +68619,7 @@ dffeas \sdram_|r.address[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [3]), @@ -64802,130 +68629,114 @@ defparam \sdram_|r.address[3] .is_wysiwyg = "true"; defparam \sdram_|r.address[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N22 +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \sdram_|Mux24~7 ( +// Equation(s): +// \sdram_|Mux24~7_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~7 .lut_mask = 16'hA0A8; +defparam \sdram_|Mux24~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 cycloneive_lcell_comb \sdram_|Mux20~4 ( // Equation(s): -// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) +// \sdram_|Mux20~4_combout = (\sdram_|Mux24~7_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~29_combout )))) # (!\sdram_|Mux24~7_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), + .dataa(\z80_|address_pins_|abus[3]~29_combout ), + .datab(\sdram_|Mux24~7_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), .cin(gnd), .combout(\sdram_|Mux20~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .lut_mask = 16'hFB08; defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N26 -cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \sdram_|Mux20~2 ( // Equation(s): -// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) - - .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\sdram_|Mux20~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; -defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux23~7 ( -// Equation(s): -// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; -defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux20~8 ( -// Equation(s): -// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) +// \sdram_|Mux20~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[15]~23_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[4]~_Duplicate_1_q )))) .dataa(\sdram_|r.state [4]), - .datab(\sdram_|n~3_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|Mux20~8_combout ), + .combout(\sdram_|Mux20~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; -defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~2 .lut_mask = 16'hA088; +defparam \sdram_|Mux20~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N18 -cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \sdram_|Mux20~3 ( // Equation(s): -// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|Mux20~3_combout = (\sdram_|Mux20~2_combout ) # ((!\sdram_|r.state [4] & \sdram_|Equal5~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|Mux20~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~10_combout ), + .combout(\sdram_|Mux20~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; -defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~3 .lut_mask = 16'hFF50; +defparam \sdram_|Mux20~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( // Equation(s): -// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux20~3_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux20~4_combout ), + .datad(\sdram_|Mux20~3_combout ), .cin(gnd), - .combout(\sdram_|Mux20~9_combout ), + .combout(\sdram_|r.address[4]~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; -defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \sdram_|r.address[4]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) +// \sdram_|r.address[4]~_Duplicate_1feeder_combout = \sdram_|r.address[4]~2_combout - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|Mux20~10_combout ), - .datad(\sdram_|Mux20~9_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~11_combout ), + .combout(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; -defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N5 +// Location: FF_X21_Y13_N17 dffeas \sdram_|r.address[4]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[4]~2_combout ), - .asdata(\sdram_|Mux20~11_combout ), + .d(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux20~9_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64940,89 +68751,122 @@ defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N2 -cycloneive_lcell_comb \sdram_|Mux20~12 ( -// Equation(s): -// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) - - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux20~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; -defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N4 +// Location: LCCOMB_X21_Y13_N20 cycloneive_lcell_comb \sdram_|Mux20~5 ( // Equation(s): -// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) +// \sdram_|Mux20~5_combout = ((\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [15]))) # (!\sdram_|r.state [6] & (\z80_|address_pins_|DFFE_apin_latch [3]))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\sdram_|Mux20~4_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux20~12_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux20~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .lut_mask = 16'hCFAF; defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N16 +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (((\sdram_|Mux20~5_combout )))) # (!\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [3]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\sdram_|r.state [8]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|Mux20~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'hEF23; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 cycloneive_lcell_comb \sdram_|Mux20~6 ( // Equation(s): -// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[4]~_Duplicate_1_q )))) +// \sdram_|Mux20~6_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .dataa(gnd), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|Mux20~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .lut_mask = 16'hCCC0; defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Mux20~7 ( // Equation(s): -// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) +// \sdram_|Mux20~7_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|Mux20~6_combout & !\sdram_|r.state [8]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~5_combout ), - .datac(gnd), - .datad(\sdram_|Mux20~6_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux20~6_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[4]~2_combout ), + .combout(\sdram_|Mux20~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; -defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~7 .lut_mask = 16'h4498; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N8 -cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \sdram_|Mux20~8 ( // Equation(s): -// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) +// \sdram_|Mux20~8_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~1_combout & ((\sdram_|Mux20~10_combout ) # (!\sdram_|Mux20~7_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~7_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|Mux20~10_combout ), + .datac(\sdram_|Mux20~7_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h8AF0; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|Mux20~8_combout & ((\sdram_|Mux20~10_combout ))) # (!\sdram_|Mux20~8_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[4]~2_combout ), - .datad(\sdram_|Mux20~11_combout ), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\sdram_|Mux20~8_combout ), + .datad(\sdram_|Mux20~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'hFC0C; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux20~9_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[4]~2_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux20~9_combout ), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hF5A0; defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65045,66 +68889,32 @@ defparam \sdram_|r.address[4] .is_wysiwyg = "true"; defparam \sdram_|r.address[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N26 -cycloneive_lcell_comb \sdram_|Mux19~1 ( -// Equation(s): -// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux19~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; -defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N12 +// Location: LCCOMB_X21_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~4 ( // Equation(s): -// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~6_combout )) - .dataa(\sdram_|r.state [8]), + .dataa(\sdram_|Mux20~6_combout ), .datab(gnd), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|Mux23~1_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux19~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .lut_mask = 16'hF0AA; defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux19~5 ( -// Equation(s): -// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux19~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; -defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N20 +// Location: LCCOMB_X20_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~6 ( // Equation(s): -// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) +// \sdram_|Mux19~6_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & (\sdram_|Mux19~4_combout & \sdram_|r.state [4]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux19~6_combout ), .cout()); @@ -65113,25 +68923,42 @@ defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N14 +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h6250; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 cycloneive_lcell_comb \sdram_|Mux19~7 ( // Equation(s): -// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~6_combout & (\sdram_|r.address[5]~_Duplicate_1_q & (\sdram_|Mux19~5_combout ))) # (!\sdram_|Mux19~6_combout & ((\sdram_|Mux19~5_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # +// (!\sdram_|Mux19~5_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) - .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .dataa(\sdram_|Mux19~6_combout ), .datab(\sdram_|r.address[5]~_Duplicate_1_q ), .datac(\sdram_|Mux19~5_combout ), - .datad(\sdram_|Mux19~6_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .lut_mask = 16'hD484; defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N31 +// Location: FF_X20_Y14_N11 dffeas \sdram_|r.address[5]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[5]~3_combout ), @@ -65150,72 +68977,89 @@ defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N20 +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~4_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[5]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h30AA; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 cycloneive_lcell_comb \sdram_|Mux19~2 ( // Equation(s): -// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) +// \sdram_|Mux19~2_combout = (!\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) - .dataa(\sdram_|Mux19~1_combout ), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .lut_mask = 16'h2232; defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N6 +// Location: LCCOMB_X20_Y14_N16 cycloneive_lcell_comb \sdram_|Mux19~3 ( // Equation(s): -// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q )))) +// \sdram_|Mux19~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|Mux19~2_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # (!\sdram_|Mux19~2_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|Equal7~2_combout & +// (\sdram_|r.address[5]~_Duplicate_1_q )) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [4]), - .datac(\z80_|address_pins_|abus[4]~28_combout ), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~2_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .lut_mask = 16'hEC4C; defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N30 +// Location: LCCOMB_X20_Y14_N10 cycloneive_lcell_comb \sdram_|r.address[5]~3 ( // Equation(s): -// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux19~2_combout ), + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|r.state [8]), .datac(gnd), .datad(\sdram_|Mux19~3_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N26 +// Location: LCCOMB_X20_Y14_N6 cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) .dataa(\sdram_|r.address[5]~3_combout ), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux19~7_combout ), - .datad(gnd), + .datac(gnd), + .datad(\sdram_|Mux19~7_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65238,15 +69082,15 @@ defparam \sdram_|r.address[5] .is_wysiwyg = "true"; defparam \sdram_|r.address[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N6 +// Location: LCCOMB_X24_Y8_N20 cycloneive_lcell_comb \sdram_|Mux18~0 ( // Equation(s): -// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux18~0_combout ), .cout()); @@ -65264,7 +69108,7 @@ dffeas \sdram_|r.address[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [6]), @@ -65274,33 +69118,33 @@ defparam \sdram_|r.address[6] .is_wysiwyg = "true"; defparam \sdram_|r.address[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Location: LCCOMB_X24_Y8_N24 +cycloneive_lcell_comb \sdram_|Mux17~2 ( // Equation(s): -// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux17~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux17~0_combout ), + .combout(\sdram_|Mux17~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux17~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X14_Y0_N4 dffeas \sdram_|r.address[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux17~0_combout ), + .d(\sdram_|Mux17~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [7]), @@ -65310,33 +69154,33 @@ defparam \sdram_|r.address[7] .is_wysiwyg = "true"; defparam \sdram_|r.address[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Location: LCCOMB_X24_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux16~2 ( // Equation(s): -// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux16~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux16~0_combout ), + .combout(\sdram_|Mux16~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux16~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X0_Y5_N25 dffeas \sdram_|r.address[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux16~0_combout ), + .d(\sdram_|Mux16~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [8]), @@ -65346,20 +69190,20 @@ defparam \sdram_|r.address[8] .is_wysiwyg = "true"; defparam \sdram_|r.address[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N30 +// Location: LCCOMB_X24_Y8_N8 cycloneive_lcell_comb \sdram_|Mux15~2 ( // Equation(s): -// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\sdram_|r.address[3]~8_combout ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [8]), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux15~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .lut_mask = 16'hF500; defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -65372,7 +69216,7 @@ dffeas \sdram_|r.address[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [9]), @@ -65382,61 +69226,78 @@ defparam \sdram_|r.address[9] .is_wysiwyg = "true"; defparam \sdram_|r.address[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \sdram_|r.address[10]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) +// \sdram_|r.address[10]~_Duplicate_1feeder_combout = \sdram_|r.address[10]~4_combout - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; -defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N28 -cycloneive_lcell_comb \sdram_|Mux14~1 ( -// Equation(s): -// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; -defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N10 -cycloneive_lcell_comb \sdram_|r.address[10]~4 ( -// Equation(s): -// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) - - .dataa(\sdram_|Mux14~0_combout ), - .datab(\sdram_|r.state [8]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\sdram_|Mux14~1_combout ), + .datad(\sdram_|r.address[10]~4_combout ), .cin(gnd), - .combout(\sdram_|r.address[10]~4_combout ), + .combout(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; -defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N11 +// Location: LCCOMB_X20_Y16_N2 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q ) # (\sdram_|r.address[10]~_Duplicate_1_q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.address[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h5F5C; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & !\sdram_|process_0~2_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h00AE; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((!\sdram_|process_0~4_combout & (\sdram_|r.address[10]~_Duplicate_1_q & \sdram_|Mux23~0_combout ))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux14~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y16_N25 dffeas \sdram_|r.address[10]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[10]~4_combout ), + .d(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .asdata(\sdram_|Mux14~3_combout ), .clrn(vcc), .aload(gnd), @@ -65452,71 +69313,71 @@ defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N16 -cycloneive_lcell_comb \sdram_|n~4 ( +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \sdram_|Mux14~1 ( // Equation(s): -// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~4_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - .dataa(\sdram_|Equal7~2_combout ), + .dataa(\sdram_|Equal2~3_combout ), .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|n~4_combout ), + .combout(\sdram_|Mux14~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~4 .lut_mask = 16'h5F5C; -defparam \sdram_|n~4 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N30 -cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \sdram_|Mux14~0 ( // Equation(s): -// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~2_combout )))) - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|Mux14~2_combout ), + .combout(\sdram_|Mux14~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; -defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~0 .lut_mask = 16'hEEAE; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N8 -cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( // Equation(s): -// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) - - .dataa(\sdram_|Mux14~2_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N26 -cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( -// Equation(s): -// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux14~0_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux14~1_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux14~1_combout ), + .datad(\sdram_|Mux14~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hFC30; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux14~3_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[10]~4_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[10]~4_combout ), .datac(\sdram_|Mux14~3_combout ), - .datad(\sdram_|r.address[10]~4_combout ), + .datad(gnd), .cin(gnd), .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hE4E4; defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65539,61 +69400,61 @@ defparam \sdram_|r.address[10] .is_wysiwyg = "true"; defparam \sdram_|r.address[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N28 -cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~21 ( // Equation(s): -// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) +// \sdram_|r.address[11]~21_combout = (!\sdram_|r.rd_pending~q & (((\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.wr_pending~q ))) - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.rd_pending~q ), .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.address[11]~18_combout ), + .combout(\sdram_|r.address[11]~21_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; -defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[11]~21 .lut_mask = 16'h080F; +defparam \sdram_|r.address[11]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N26 +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \sdram_|r.address[11]~22 ( +// Equation(s): +// \sdram_|r.address[11]~22_combout = (\sdram_|r.address[11]~21_combout & ((\sdram_|r.state [8]) # (\sdram_|r.state [4]))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[11]~21_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~22 .lut_mask = 16'hFC00; +defparam \sdram_|r.address[11]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 cycloneive_lcell_comb \sdram_|r.address[11]~5 ( // Equation(s): -// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.address[11]~22_combout ) # ((\sdram_|r.state [8] & !\sdram_|Equal7~2_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux24~2_combout ), + .dataa(\sdram_|r.address[11]~22_combout ), + .datab(\sdram_|r.state [8]), .datac(\sdram_|r.address[11]~_Duplicate_2_q ), - .datad(\sdram_|r.address[11]~18_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .lut_mask = 16'hA0E0; defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( -// Equation(s): -// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout - - .dataa(\sdram_|r.address[11]~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; -defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y11_N5 +// Location: FF_X20_Y14_N9 dffeas \sdram_|r.address[11]~_Duplicate_2 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .d(\sdram_|r.address[11]~5_combout ), .asdata(\sdram_|Mux13~6_combout ), .clrn(vcc), .aload(gnd), @@ -65609,54 +69470,54 @@ defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N8 +// Location: LCCOMB_X20_Y14_N14 cycloneive_lcell_comb \sdram_|Mux13~10 ( // Equation(s): // \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) - .dataa(gnd), - .datab(\sdram_|r.address[11]~_Duplicate_2_q ), - .datac(\sdram_|r.state [6]), + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux13~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .lut_mask = 16'hF050; defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N22 +// Location: LCCOMB_X20_Y14_N0 cycloneive_lcell_comb \sdram_|Mux13~6 ( // Equation(s): -// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|Equal7~2_combout & !\sdram_|r.state [6])) # (!\sdram_|process_0~4_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|Mux13~10_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux13~10_combout ), .cin(gnd), .combout(\sdram_|Mux13~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .lut_mask = 16'h3700; defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N12 +// Location: LCCOMB_X20_Y14_N4 cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65679,20 +69540,20 @@ defparam \sdram_|r.address[11] .is_wysiwyg = "true"; defparam \sdram_|r.address[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N6 +// Location: LCCOMB_X20_Y14_N2 cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65725,6 +69586,16 @@ defparam \SW[0]~input .bus_hold = "false"; defparam \SW[0]~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X25_Y34_N8 +cycloneive_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + // Location: IOIBUF_X53_Y17_N15 cycloneive_io_ibuf \SW[3]~input ( .i(SW[3]), diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index 52dc786..4b4eecb 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/02/2022 14:51:21") + (DATE "04/06/2022 13:58:29") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1389:1389:1389) (1434:1434:1434)) - (PORT oe (1581:1581:1581) (1600:1600:1600)) + (PORT i (2192:2192:2192) (2198:2198:2198)) + (PORT oe (4491:4491:4491) (4501:4501:4501)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1902:1902:1902) (1871:1871:1871)) - (PORT oe (1566:1566:1566) (1592:1592:1592)) + (PORT i (1582:1582:1582) (1619:1619:1619)) + (PORT oe (3306:3306:3306) (3338:3338:3338)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (2060:2060:2060) (2022:2022:2022)) - (PORT oe (1566:1566:1566) (1592:1592:1592)) + (PORT i (1234:1234:1234) (1241:1241:1241)) + (PORT oe (3306:3306:3306) (3338:3338:3338)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1683:1683:1683) (1652:1652:1652)) - (PORT oe (1959:1959:1959) (1951:1951:1951)) + (PORT i (1460:1460:1460) (1457:1457:1457)) + (PORT oe (3134:3134:3134) (3174:3174:3174)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1753:1753:1753) (1733:1733:1733)) - (PORT oe (1959:1959:1959) (1951:1951:1951)) + (PORT i (1502:1502:1502) (1512:1512:1512)) + (PORT oe (3134:3134:3134) (3174:3174:3174)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1415:1415:1415) (1479:1479:1479)) - (PORT oe (2181:2181:2181) (2185:2185:2185)) + (PORT i (1231:1231:1231) (1228:1228:1228)) + (PORT oe (2892:2892:2892) (2937:2937:2937)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1527:1527:1527) (1518:1518:1518)) - (PORT oe (2181:2181:2181) (2185:2185:2185)) + (PORT i (1291:1291:1291) (1330:1330:1330)) + (PORT oe (2892:2892:2892) (2937:2937:2937)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1534:1534:1534) (1562:1562:1562)) - (PORT oe (2181:2181:2181) (2185:2185:2185)) + (PORT i (1326:1326:1326) (1331:1331:1331)) + (PORT oe (2892:2892:2892) (2937:2937:2937)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1354:1354:1354) (1354:1354:1354)) - (PORT oe (2447:2447:2447) (2429:2429:2429)) + (PORT i (1088:1088:1088) (1079:1079:1079)) + (PORT oe (2707:2707:2707) (2779:2779:2779)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1499:1499:1499) (1481:1481:1481)) - (PORT oe (2447:2447:2447) (2429:2429:2429)) + (PORT i (1261:1261:1261) (1263:1263:1263)) + (PORT oe (2707:2707:2707) (2779:2779:2779)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1577:1577:1577) (1622:1622:1622)) - (PORT oe (2194:2194:2194) (2185:2185:2185)) + (PORT i (1361:1361:1361) (1316:1316:1316)) + (PORT oe (2960:2960:2960) (3019:3019:3019)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) (IOPATH oe o (4029:4029:4029) (3565:3565:3565)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1445:1445:1445) (1430:1430:1430)) - (PORT oe (2447:2447:2447) (2429:2429:2429)) + (PORT i (1362:1362:1362) (1317:1317:1317)) + (PORT oe (2707:2707:2707) (2779:2779:2779)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1521:1521:1521) (1518:1518:1518)) - (PORT oe (1588:1588:1588) (1607:1607:1607)) + (PORT i (2001:2001:2001) (1992:1992:1992)) + (PORT oe (3343:3343:3343) (3368:3368:3368)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1526:1526:1526) (1561:1561:1561)) - (PORT oe (2194:2194:2194) (2185:2185:2185)) + (PORT i (1485:1485:1485) (1453:1453:1453)) + (PORT oe (2961:2961:2961) (3019:3019:3019)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1317:1317:1317) (1363:1363:1363)) - (PORT oe (1953:1953:1953) (2028:2028:2028)) + (PORT i (1003:1003:1003) (1019:1019:1019)) + (PORT oe (2418:2418:2418) (2482:2482:2482)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1675:1675:1675) (1640:1640:1640)) - (PORT oe (1763:1763:1763) (1772:1772:1772)) + (PORT i (1430:1430:1430) (1408:1408:1408)) + (PORT oe (3295:3295:3295) (3331:3331:3331)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1077:1077:1077) (1106:1106:1106)) - (PORT oe (1299:1299:1299) (1308:1308:1308)) + (PORT i (1501:1501:1501) (1506:1506:1506)) + (PORT oe (1729:1729:1729) (1701:1701:1701)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1121:1121:1121) (1157:1157:1157)) - (PORT oe (1550:1550:1550) (1564:1564:1564)) + (PORT i (1321:1321:1321) (1352:1352:1352)) + (PORT oe (2484:2484:2484) (2456:2456:2456)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1347:1347:1347) (1358:1358:1358)) - (PORT oe (1521:1521:1521) (1518:1518:1518)) + (PORT i (1282:1282:1282) (1300:1300:1300)) + (PORT oe (2166:2166:2166) (2138:2138:2138)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1290:1290:1290) (1266:1266:1266)) - (PORT oe (1299:1299:1299) (1308:1308:1308)) + (PORT i (1081:1081:1081) (1112:1112:1112)) + (PORT oe (1729:1729:1729) (1701:1701:1701)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1508:1508:1508) (1504:1504:1504)) - (PORT oe (1315:1315:1315) (1323:1323:1323)) + (PORT i (1314:1314:1314) (1327:1327:1327)) + (PORT oe (1913:1913:1913) (1870:1870:1870)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1351:1351:1351) (1368:1368:1368)) - (PORT oe (1576:1576:1576) (1576:1576:1576)) + (PORT i (1425:1425:1425) (1444:1444:1444)) + (PORT oe (2167:2167:2167) (2121:2121:2121)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1498:1498:1498) (1552:1552:1552)) - (PORT oe (1516:1516:1516) (1502:1502:1502)) + (PORT i (1290:1290:1290) (1305:1305:1305)) + (PORT oe (1937:1937:1937) (1893:1893:1893)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1281:1281:1281) (1310:1310:1310)) - (PORT oe (1289:1289:1289) (1299:1299:1299)) + (PORT i (1503:1503:1503) (1492:1492:1492)) + (PORT oe (2196:2196:2196) (2163:2163:2163)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1292:1292:1292) (1340:1340:1340)) - (PORT oe (1411:1411:1411) (1448:1448:1448)) + (PORT i (1760:1760:1760) (1767:1767:1767)) + (PORT oe (3437:3437:3437) (3418:3418:3418)) (IOPATH i o (2119:2119:2119) (2194:2194:2194)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1126:1126:1126) (1146:1146:1146)) - (PORT oe (1763:1763:1763) (1772:1772:1772)) + (PORT i (1409:1409:1409) (1365:1365:1365)) + (PORT oe (3295:3295:3295) (3331:3331:3331)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1045:1045:1045)) - (PORT oe (1707:1707:1707) (1746:1746:1746)) - (IOPATH i o (2277:2277:2277) (2180:2180:2180)) + (PORT i (1777:1777:1777) (1798:1798:1798)) + (PORT oe (3691:3691:3691) (3674:3674:3674)) + (IOPATH i o (2180:2180:2180) (2277:2277:2277)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1083:1083:1083) (1032:1032:1032)) - (PORT oe (920:920:920) (954:954:954)) + (PORT i (1796:1796:1796) (1718:1718:1718)) + (PORT oe (3959:3959:3959) (3951:3951:3951)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -377,7 +377,17 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1448:1448:1448) (1410:1410:1410)) + (PORT i (1557:1557:1557) (1550:1550:1550)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2050:2050:2050) (2091:2091:2091)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -387,7 +397,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (917:917:917) (942:942:942)) + (PORT i (1395:1395:1395) (1441:1441:1441)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -397,8 +407,48 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1356:1356:1356) (1406:1406:1406)) - (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + (PORT i (1350:1350:1350) (1368:1368:1368)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1126:1126:1126) (1161:1161:1161)) + (IOPATH i o (2180:2180:2180) (2277:2277:2277)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1116:1116:1116) (1151:1151:1151)) + (IOPATH i o (3539:3539:3539) (3961:3961:3961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1122:1122:1122) (1142:1142:1142)) + (IOPATH i o (2119:2119:2119) (2194:2194:2194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (291:291:291) (285:285:285)) + (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) ) @@ -452,7 +502,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1034:1034:1034) (1046:1046:1046)) + (PORT i (966:966:966) (944:944:944)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -462,7 +512,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1049:1049:1049) (1057:1057:1057)) + (PORT i (929:929:929) (901:901:901)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -472,7 +522,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (805:805:805) (799:799:799)) + (PORT i (934:934:934) (895:895:895)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -482,7 +532,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (765:765:765) (747:747:747)) + (PORT i (500:500:500) (493:493:493)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -492,7 +542,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (536:536:536) (534:534:534)) + (PORT i (658:658:658) (632:632:632)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -502,7 +552,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (516:516:516) (516:516:516)) + (PORT i (674:674:674) (627:627:627)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -512,7 +562,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1192:1192:1192) (1149:1149:1149)) + (PORT i (1210:1210:1210) (1182:1182:1182)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -522,7 +572,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1192:1192:1192) (1149:1149:1149)) + (PORT i (1210:1210:1210) (1182:1182:1182)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -532,7 +582,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1029:1029:1029) (1033:1033:1033)) + (PORT i (994:994:994) (992:992:992)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) ) ) @@ -542,7 +592,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1156:1156:1156) (1115:1115:1115)) + (PORT i (962:962:962) (940:940:940)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -552,7 +602,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1054:1054:1054) (1070:1070:1070)) + (PORT i (977:977:977) (982:982:982)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -562,7 +612,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1054:1054:1054) (1064:1064:1064)) + (PORT i (989:989:989) (991:991:991)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -590,7 +640,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1548:1548:1548) (1532:1532:1532)) + (PORT i (1660:1660:1660) (1707:1707:1707)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -600,7 +650,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1028:1028:1028) (1076:1076:1076)) + (PORT i (1226:1226:1226) (1281:1281:1281)) (IOPATH i o (3539:3539:3539) (3961:3961:3961)) ) ) @@ -610,7 +660,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (826:826:826) (776:776:776)) + (PORT i (285:285:285) (280:280:280)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -620,7 +670,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1528:1528:1528) (1518:1518:1518)) + (PORT i (1483:1483:1483) (1468:1468:1468)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -838,8 +888,8 @@ (INSTANCE DRAM_DQ\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1156:1156:1156) (1184:1184:1184)) - (PORT oe (1586:1586:1586) (1588:1588:1588)) + (PORT i (1063:1063:1063) (1070:1070:1070)) + (PORT oe (1324:1324:1324) (1307:1307:1307)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -850,8 +900,8 @@ (INSTANCE DRAM_DQ\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1295:1295:1295) (1296:1296:1296)) - (PORT oe (1586:1586:1586) (1588:1588:1588)) + (PORT i (1328:1328:1328) (1354:1354:1354)) + (PORT oe (1324:1324:1324) (1307:1307:1307)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -862,8 +912,8 @@ (INSTANCE DRAM_DQ\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1044:1044:1044) (1027:1027:1027)) - (PORT oe (1266:1266:1266) (1273:1273:1273)) + (PORT i (1249:1249:1249) (1241:1241:1241)) + (PORT oe (1310:1310:1310) (1310:1310:1310)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -874,8 +924,8 @@ (INSTANCE DRAM_DQ\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1106:1106:1106) (1135:1135:1135)) - (PORT oe (1368:1368:1368) (1397:1397:1397)) + (PORT i (1374:1374:1374) (1406:1406:1406)) + (PORT oe (1496:1496:1496) (1568:1568:1568)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -886,8 +936,8 @@ (INSTANCE DRAM_DQ\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1111:1111:1111)) - (PORT oe (1104:1104:1104) (1100:1100:1100)) + (PORT i (1387:1387:1387) (1417:1417:1417)) + (PORT oe (1414:1414:1414) (1428:1428:1428)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -898,8 +948,8 @@ (INSTANCE DRAM_DQ\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1316:1316:1316) (1350:1350:1350)) - (PORT oe (1293:1293:1293) (1201:1201:1201)) + (PORT i (1341:1341:1341) (1365:1365:1365)) + (PORT oe (1165:1165:1165) (1182:1182:1182)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -910,8 +960,8 @@ (INSTANCE DRAM_DQ\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1066:1066:1066) (1083:1083:1083)) - (PORT oe (1293:1293:1293) (1201:1201:1201)) + (PORT i (903:903:903) (943:943:943)) + (PORT oe (1165:1165:1165) (1182:1182:1182)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -922,8 +972,8 @@ (INSTANCE DRAM_DQ\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (512:512:512) (512:512:512)) - (PORT oe (1273:1273:1273) (1259:1259:1259)) + (PORT i (1308:1308:1308) (1317:1317:1317)) + (PORT oe (1462:1462:1462) (1504:1504:1504)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -934,7 +984,7 @@ (INSTANCE DRAM_DQ\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1496:1496:1496) (1514:1514:1514)) + (PORT i (1454:1454:1454) (1423:1423:1423)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -944,7 +994,7 @@ (INSTANCE DRAM_DQ\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1317:1317:1317) (1306:1306:1306)) + (PORT i (1425:1425:1425) (1380:1380:1380)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -954,7 +1004,7 @@ (INSTANCE DRAM_DQ\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1299:1299:1299) (1285:1285:1285)) + (PORT i (1436:1436:1436) (1394:1394:1394)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -964,7 +1014,7 @@ (INSTANCE DRAM_DQ\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1299:1299:1299) (1285:1285:1285)) + (PORT i (1436:1436:1436) (1394:1394:1394)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -974,7 +1024,7 @@ (INSTANCE DRAM_DQ\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1468:1468:1468) (1513:1513:1513)) + (PORT i (1425:1425:1425) (1395:1395:1395)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -984,7 +1034,7 @@ (INSTANCE DRAM_DQ\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1490:1490:1490) (1505:1505:1505)) + (PORT i (1454:1454:1454) (1417:1417:1417)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -994,7 +1044,7 @@ (INSTANCE DRAM_DQ\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1490:1490:1490) (1505:1505:1505)) + (PORT i (1454:1454:1454) (1417:1417:1417)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -1004,7 +1054,7 @@ (INSTANCE DRAM_DQ\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1100:1100:1100) (1104:1104:1104)) + (PORT i (1428:1428:1428) (1414:1414:1414)) (IOPATH i o (2180:2180:2180) (2277:2277:2277)) ) ) @@ -1036,6 +1086,887 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE turbo_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (461:461:461) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (133:133:133) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (309:309:309)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (301:301:301)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (301:301:301)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (322:322:322)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (316:316:316)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (323:323:323)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (234:234:234) (305:305:305)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (311:311:311)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (238:238:238) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (315:315:315)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (232:232:232) (307:307:307)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (316:316:316)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT datab (412:412:412) (444:444:444)) + (PORT datac (564:564:564) (579:579:579)) + (PORT datad (375:375:375) (409:409:409)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (353:353:353)) + (PORT datab (383:383:383) (435:435:435)) + (PORT datac (211:211:211) (286:286:286)) + (PORT datad (213:213:213) (277:277:277)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (322:322:322)) + (PORT datab (236:236:236) (313:313:313)) + (PORT datac (574:574:574) (572:572:572)) + (PORT datad (224:224:224) (286:286:286)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (309:309:309)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (303:303:303)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datac (201:201:201) (271:271:271)) + (PORT datad (204:204:204) (264:264:264)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (234:234:234) (310:310:310)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (212:212:212) (276:276:276)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (276:276:276)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (751:751:751) (796:796:796)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (610:610:610)) + (PORT datab (229:229:229) (299:299:299)) + (PORT datac (3233:3233:3233) (3475:3475:3475)) + (PORT datad (625:625:625) (657:657:657)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1005:1005:1005) (1039:1039:1039)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (228:228:228) (302:302:302)) + (PORT datac (202:202:202) (274:274:274)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (659:659:659)) + (PORT datab (383:383:383) (433:433:433)) + (PORT datac (209:209:209) (284:284:284)) + (PORT datad (211:211:211) (275:275:275)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (321:321:321)) + (PORT datab (235:235:235) (313:313:313)) + (PORT datac (209:209:209) (285:285:285)) + (PORT datad (213:213:213) (278:278:278)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (327:327:327)) + (PORT datab (644:644:644) (662:662:662)) + (PORT datac (220:220:220) (292:292:292)) + (PORT datad (222:222:222) (284:284:284)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (585:585:585) (580:580:580)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (590:590:590) (584:584:584)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (229:229:229) (301:301:301)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (3272:3272:3272) (3512:3512:3512)) + (PORT datad (554:554:554) (551:551:551)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1620:1620:1620)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE turbo\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE turbo) + (DELAY + (ABSOLUTE + (PORT clk (773:773:773) (721:721:721)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|counter\[0\]\~0) @@ -1050,7 +1981,7 @@ (INSTANCE ula_\|clocks_\|counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1706:1706:1706) (1726:1726:1726)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1059,23 +1990,14 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE SW\[2\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (492:492:492) (527:527:527)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (821:821:821) (866:866:866)) + (PORT datad (601:601:601) (634:634:634)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1086,7 +2008,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu) (DELAY (ABSOLUTE - (PORT clk (1706:1706:1706) (1726:1726:1726)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1100,16 +2022,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (658:658:658) (673:673:673)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[1\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (461:461:461) (708:708:708)) + (PORT inclk[0] (667:667:667) (673:673:673)) ) ) ) @@ -1127,8 +2040,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1395:1395:1395) (1419:1419:1419)) - (PORT datad (489:489:489) (462:462:462)) + (PORT datac (1395:1395:1395) (1420:1420:1420)) + (PORT datad (490:490:490) (462:462:462)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1139,7 +2052,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (180:180:180) (203:203:203)) + (PORT datad (1705:1705:1705) (1686:1686:1686)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -1149,7 +2062,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1366:1366:1366)) + (PORT clk (1356:1356:1356) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1163,7 +2076,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (683:683:683) (701:701:701)) + (PORT inclk[0] (652:652:652) (663:663:663)) ) ) ) @@ -1172,9 +2085,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1367:1367:1367)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1365:1365:1365)) + (PORT clrn (1387:1387:1387) (1359:1359:1359)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -1184,69 +2097,11 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[1\]\~input) (DELAY (ABSOLUTE - (PORT dataa (1758:1758:1758) (1865:1865:1865)) - (PORT datac (1361:1361:1361) (1383:1383:1383)) - (PORT datad (1075:1075:1075) (1125:1125:1125)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1367:1367:1367)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT datac (672:672:672) (729:729:729)) - (PORT datad (281:281:281) (373:373:373)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1978:1978:1978) (2017:2017:2017)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1356:1356:1356) (1330:1330:1330)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (2051:2051:2051) (2092:2092:2092)) + (IOPATH i o (461:461:461) (708:708:708)) ) ) ) @@ -1255,13 +2110,66 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (1370:1370:1370) (1411:1411:1411)) - (PORT datad (1524:1524:1524) (1631:1631:1631)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datac (1692:1692:1692) (1799:1799:1799)) + (PORT datad (1463:1463:1463) (1515:1515:1515)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1174:1174:1174)) + (PORT datac (216:216:216) (283:283:283)) + (PORT datad (888:888:888) (931:931:931)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (4426:4426:4426) (4447:4447:4447)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (1094:1094:1094) (1113:1113:1113)) + (PORT datad (895:895:895) (936:936:936)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -1276,7 +2184,7 @@ (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (662:662:662)) + (PORT dataa (635:635:635) (666:666:666)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1288,10 +2196,10 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (347:347:347) (361:361:361)) - (PORT datad (582:582:582) (577:577:577)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (207:207:207) (246:246:246)) + (PORT datac (703:703:703) (671:671:671)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -1300,7 +2208,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1377:1377:1377)) + (PORT clk (1362:1362:1362) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1314,7 +2222,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (430:430:430) (462:462:462)) + (PORT datab (610:610:610) (658:658:658)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1328,7 +2236,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (306:306:306) (310:310:310)) + (PORT datad (759:759:759) (749:749:749)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -1338,7 +2246,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1352,7 +2260,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (377:377:377) (433:433:433)) + (PORT datab (628:628:628) (649:649:649)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1366,8 +2274,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (804:804:804) (779:779:779)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1510:1510:1510) (1500:1500:1500)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1380,9 +2288,9 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (598:598:598) (617:617:617)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (598:598:598) (652:652:652)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -1394,13 +2302,29 @@ (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (803:803:803) (785:785:785)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (518:518:518)) + (PORT datab (1305:1305:1305) (1401:1401:1401)) + (PORT datac (1510:1510:1510) (1505:1505:1505)) + (PORT datad (248:248:248) (313:313:313)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) ) ) (CELL @@ -1408,7 +2332,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (630:630:630)) + (PORT dataa (388:388:388) (431:431:431)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1422,8 +2346,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (812:812:812) (784:784:784)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (467:467:467) (493:493:493)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1433,10 +2357,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT datab (763:763:763) (784:784:784)) + (PORT dataa (1463:1463:1463) (1449:1449:1449)) + (PORT datab (1290:1290:1290) (1343:1343:1343)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (617:617:617) (658:658:658)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (642:642:642) (687:687:687)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1445,126 +2385,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) - (DELAY - (ABSOLUTE - (PORT datab (183:183:183) (215:215:215)) - (PORT datad (582:582:582) (580:580:580)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (469:469:469) (496:496:496)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT datab (1271:1271:1271) (1273:1273:1273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (603:603:603) (601:601:601)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (645:645:645)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (1334:1334:1334) (1318:1318:1318)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (488:488:488)) - (PORT datab (895:895:895) (920:920:920)) - (PORT datac (639:639:639) (679:679:679)) - (PORT datad (684:684:684) (712:712:712)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1173:1173:1173)) - (PORT datab (849:849:849) (860:860:860)) - (PORT datac (602:602:602) (629:629:629)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (998:998:998) (1009:1009:1009)) + (PORT dataa (389:389:389) (433:433:433)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1578,8 +2404,8 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (581:581:581) (580:580:580)) + (PORT datab (604:604:604) (604:604:604)) + (PORT datad (159:159:159) (179:179:179)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1590,8 +2416,8 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (805:805:805) (783:783:783)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1409:1409:1409) (1465:1465:1465)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1604,8 +2430,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (311:311:311)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datad (620:620:620) (663:663:663)) + (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -1615,8 +2441,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (325:325:325) (338:338:338)) - (PORT datad (583:583:583) (582:582:582)) + (PORT datab (604:604:604) (603:603:603)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1627,8 +2453,8 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (1321:1321:1321) (1291:1291:1291)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (606:606:606) (604:604:604)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1641,35 +2467,23 @@ (INSTANCE ula_\|video_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (243:243:243)) - (PORT datab (1155:1155:1155) (1174:1174:1174)) - (PORT datac (827:827:827) (849:849:849)) - (PORT datad (810:810:810) (819:819:819)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (1472:1472:1472) (1469:1469:1469)) + (PORT datac (646:646:646) (697:697:697)) + (PORT datad (663:663:663) (702:702:702)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (1153:1153:1153) (1187:1187:1187)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (662:662:662) (682:682:682)) + (PORT datab (1254:1254:1254) (1250:1250:1250)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1680,39 +2494,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (607:607:607) (630:630:630)) - (PORT datab (1389:1389:1389) (1361:1361:1361)) - (PORT datad (545:545:545) (541:541:541)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (605:605:605) (604:604:604)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1420:1420:1420) (1425:1425:1425)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~4) + (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (625:625:625) (654:654:654)) + (PORT datab (658:658:658) (697:697:697)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1721,172 +2532,84 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (634:634:634)) - (PORT datab (589:589:589) (597:597:597)) - (PORT datad (1352:1352:1352) (1330:1330:1330)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[2\]) + (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (640:640:640) (655:655:655)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datab (646:646:646) (677:677:677)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (629:629:629)) - (PORT datab (1390:1390:1390) (1360:1360:1360)) - (PORT datad (557:557:557) (544:544:544)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[3\]) + (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (467:467:467) (493:493:493)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~8) + (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (895:895:895) (895:895:895)) + (PORT dataa (702:702:702) (756:756:756)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (632:632:632)) - (PORT datab (620:620:620) (612:612:612)) - (PORT datad (1349:1349:1349) (1328:1328:1328)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (1573:1573:1573) (1577:1577:1577)) + (PORT datab (598:598:598) (621:621:621)) + (PORT datac (664:664:664) (720:720:720)) + (PORT datad (655:655:655) (707:707:707)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (676:676:676) (721:721:721)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (571:571:571) (600:600:600)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (634:634:634)) - (PORT datab (1394:1394:1394) (1364:1364:1364)) - (PORT datad (547:547:547) (534:534:534)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (885:885:885) (901:901:901)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (592:592:592) (609:609:609)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -1898,11 +2621,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (643:643:643)) - (PORT datab (539:539:539) (545:545:545)) - (PORT datad (724:724:724) (689:689:689)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (638:638:638) (669:669:669)) + (PORT datab (531:531:531) (515:515:515)) + (PORT datad (1526:1526:1526) (1502:1502:1502)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -1913,7 +2636,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1927,7 +2650,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (887:887:887) (927:927:927)) + (PORT datab (871:871:871) (886:886:886)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1941,9 +2664,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (630:630:630) (640:640:640)) - (PORT datab (997:997:997) (949:949:949)) - (PORT datad (514:514:514) (509:509:509)) + (PORT dataa (634:634:634) (659:659:659)) + (PORT datab (747:747:747) (709:709:709)) + (PORT datad (1518:1518:1518) (1495:1495:1495)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -1956,7 +2679,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -1970,9 +2693,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (876:876:876) (903:903:903)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (629:629:629) (651:651:651)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -1984,9 +2707,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (643:643:643)) - (PORT datab (1042:1042:1042) (1017:1017:1017)) - (PORT datad (514:514:514) (513:513:513)) + (PORT dataa (633:633:633) (657:657:657)) + (PORT datab (713:713:713) (689:689:689)) + (PORT datad (1517:1517:1517) (1495:1495:1495)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -1999,7 +2722,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -2013,8 +2736,8 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (594:594:594) (627:627:627)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (703:703:703) (753:753:753)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -2024,11 +2747,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (641:641:641)) - (PORT datab (540:540:540) (542:542:542)) - (PORT datad (727:727:727) (699:699:699)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (633:633:633) (655:655:655)) + (PORT datab (493:493:493) (487:487:487)) + (PORT datad (1516:1516:1516) (1494:1494:1494)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2039,7 +2762,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -2048,31 +2771,15 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (340:340:340)) - (PORT datab (654:654:654) (686:686:686)) - (PORT datac (599:599:599) (628:628:628)) - (PORT datad (1093:1093:1093) (1098:1098:1098)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (437:437:437)) - (PORT datab (262:262:262) (334:334:334)) - (PORT datac (226:226:226) (298:298:298)) - (PORT datad (390:390:390) (426:426:426)) + (PORT dataa (247:247:247) (324:324:324)) + (PORT datab (262:262:262) (336:336:336)) + (PORT datac (243:243:243) (319:319:319)) + (PORT datad (226:226:226) (290:290:290)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -2085,10 +2792,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (432:432:432)) - (PORT datab (813:813:813) (810:810:810)) - (PORT datac (576:576:576) (601:601:601)) - (PORT datad (549:549:549) (532:532:532)) + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (877:877:877) (911:911:911)) + (PORT datac (546:546:546) (569:569:569)) + (PORT datad (528:528:528) (515:515:515)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -2101,11 +2808,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (605:605:605) (632:632:632)) - (PORT datab (1389:1389:1389) (1363:1363:1363)) - (PORT datad (289:289:289) (297:297:297)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (634:634:634) (662:662:662)) + (PORT datab (502:502:502) (503:503:503)) + (PORT datad (1520:1520:1520) (1498:1498:1498)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2116,7 +2823,209 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (744:744:744)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (666:666:666)) + (PORT datab (505:505:505) (492:492:492)) + (PORT datad (1524:1524:1524) (1502:1502:1502)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (598:598:598) (626:626:626)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1073:1073:1073)) + (PORT datab (534:534:534) (514:514:514)) + (PORT datac (1030:1030:1030) (1019:1019:1019)) + (PORT datad (985:985:985) (944:944:944)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (795:795:795) (787:787:787)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1574:1574:1574)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (653:653:653)) + (PORT datab (545:545:545) (526:526:526)) + (PORT datad (1516:1516:1516) (1491:1491:1491)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (863:863:863) (885:885:885)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (667:667:667)) + (PORT datab (502:502:502) (495:495:495)) + (PORT datad (1525:1525:1525) (1496:1496:1496)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (669:669:669)) + (PORT datab (538:538:538) (514:514:514)) + (PORT datad (1527:1527:1527) (1502:1502:1502)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -2130,10 +3039,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (430:430:430)) - (PORT datab (654:654:654) (686:686:686)) - (PORT datac (598:598:598) (626:626:626)) - (PORT datad (345:345:345) (396:396:396)) + (PORT dataa (703:703:703) (759:759:759)) + (PORT datab (601:601:601) (627:627:627)) + (PORT datac (661:661:661) (712:712:712)) + (PORT datad (1547:1547:1547) (1535:1535:1535)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -2146,11 +3055,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (344:344:344)) - (PORT datac (576:576:576) (600:600:600)) - (PORT datad (549:549:549) (533:533:533)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (570:570:570) (597:597:597)) + (PORT datab (185:185:185) (218:218:218)) + (PORT datad (524:524:524) (511:511:511)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -2169,10 +3078,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (852:852:852) (879:879:879)) - (PORT datab (877:877:877) (888:888:888)) - (PORT datac (834:834:834) (858:858:858)) - (PORT datad (1162:1162:1162) (1116:1116:1116)) + (PORT dataa (617:617:617) (661:661:661)) + (PORT datab (654:654:654) (707:707:707)) + (PORT datac (609:609:609) (651:651:651)) + (PORT datad (1310:1310:1310) (1299:1299:1299)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -2182,54 +3091,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (INSTANCE z80_\|ir_\|opcode\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (1292:1292:1292) (1293:1293:1293)) - (PORT datad (1770:1770:1770) (1803:1803:1803)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datad (221:221:221) (255:255:255)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (699:699:699) (750:750:750)) - (PORT datab (1378:1378:1378) (1431:1431:1431)) - (PORT datac (1694:1694:1694) (1775:1775:1775)) - (PORT datad (1560:1560:1560) (1564:1564:1564)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1141:1141:1141) (1170:1170:1170)) + (PORT datab (391:391:391) (433:433:433)) + (PORT datad (895:895:895) (933:933:933)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (1633:1633:1633) (1686:1686:1686)) - (PORT datad (309:309:309) (317:317:317)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (428:428:428)) - (PORT datab (641:641:641) (683:683:683)) - (PORT datad (832:832:832) (839:839:839)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1133:1133:1133) (1154:1154:1154)) + (PORT datab (383:383:383) (429:429:429)) + (PORT datad (894:894:894) (937:937:937)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2240,9 +3150,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -2251,284 +3161,16 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1397:1397:1397)) - (PORT datad (865:865:865) (926:926:926)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1765:1765:1765) (1763:1763:1763)) - (PORT datab (188:188:188) (225:225:225)) - (PORT datac (582:582:582) (603:603:603)) - (PORT datad (1483:1483:1483) (1572:1572:1572)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1630:1630:1630) (1683:1683:1683)) - (PORT datab (1520:1520:1520) (1605:1605:1605)) - (PORT datad (1740:1740:1740) (1725:1725:1725)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1482:1482:1482)) - (PORT datab (235:235:235) (280:280:280)) - (PORT datac (1345:1345:1345) (1347:1347:1347)) - (PORT datad (1091:1091:1091) (1102:1102:1102)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (753:753:753)) - (PORT datab (696:696:696) (740:740:740)) - (PORT datac (1687:1687:1687) (1770:1770:1770)) - (PORT datad (1552:1552:1552) (1558:1558:1558)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1143:1143:1143)) - (PORT datac (849:849:849) (883:883:883)) - (PORT datad (1092:1092:1092) (1102:1102:1102)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (632:632:632)) - (PORT datac (616:616:616) (657:657:657)) - (PORT datad (829:829:829) (838:838:838)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1340:1340:1340)) - (PORT datab (2045:2045:2045) (2160:2160:2160)) - (PORT datac (359:359:359) (399:399:399)) - (PORT datad (282:282:282) (374:374:374)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1376:1376:1376)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1092:1092:1092) (1111:1111:1111)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (PORT datad (1090:1090:1090) (1107:1107:1107)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (1427:1427:1427) (1447:1447:1447)) - (PORT datac (1090:1090:1090) (1115:1115:1115)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1116:1116:1116)) - (PORT datab (1128:1128:1128) (1118:1118:1118)) - (PORT datac (2095:2095:2095) (2153:2153:2153)) - (PORT datad (339:339:339) (350:350:350)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2119:2119:2119) (2152:2152:2152)) - (PORT datab (2016:2016:2016) (2098:2098:2098)) - (PORT datac (1128:1128:1128) (1172:1172:1172)) - (PORT datad (806:806:806) (824:824:824)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1384:1384:1384) (1355:1355:1355)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (390:390:390)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (908:908:908) (952:952:952)) - (PORT datad (1384:1384:1384) (1431:1431:1431)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (445:445:445)) - (PORT datab (642:642:642) (681:681:681)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1126:1126:1126) (1147:1147:1147)) + (PORT datab (241:241:241) (311:311:311)) + (PORT datad (897:897:897) (932:932:932)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2539,9 +3181,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -2550,2264 +3192,14 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2292:2292:2292) (2375:2375:2375)) - (PORT datab (1433:1433:1433) (1504:1504:1504)) - (PORT datac (1099:1099:1099) (1134:1134:1134)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2356:2356:2356) (2373:2373:2373)) - (PORT datac (2247:2247:2247) (2354:2354:2354)) - (PORT datad (1693:1693:1693) (1721:1721:1721)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1824:1824:1824) (1826:1826:1826)) - (PORT datab (1946:1946:1946) (1990:1990:1990)) - (PORT datac (1339:1339:1339) (1399:1399:1399)) - (PORT datad (191:191:191) (222:222:222)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datab (2297:2297:2297) (2383:2383:2383)) - (PORT datac (2003:2003:2003) (2031:2031:2031)) - (PORT datad (1353:1353:1353) (1395:1395:1395)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (646:646:646)) - (PORT datac (1308:1308:1308) (1355:1355:1355)) - (PORT datad (610:610:610) (649:649:649)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT datac (547:547:547) (578:578:578)) - (PORT datad (613:613:613) (652:652:652)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT datab (1097:1097:1097) (1132:1132:1132)) - (PORT datac (1375:1375:1375) (1441:1441:1441)) - (PORT datad (1114:1114:1114) (1136:1136:1136)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT datab (1499:1499:1499) (1588:1588:1588)) - (PORT datad (1559:1559:1559) (1583:1583:1583)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2355:2355:2355) (2370:2370:2370)) - (PORT datab (2281:2281:2281) (2390:2390:2390)) - (PORT datac (1342:1342:1342) (1403:1403:1403)) - (PORT datad (1695:1695:1695) (1725:1725:1725)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (279:279:279)) - (PORT datab (829:829:829) (810:810:810)) - (PORT datac (1178:1178:1178) (1209:1209:1209)) - (PORT datad (728:728:728) (755:755:755)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datab (1510:1510:1510) (1637:1637:1637)) - (PORT datad (1662:1662:1662) (1724:1724:1724)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (444:444:444)) - (PORT datad (223:223:223) (286:286:286)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1570:1570:1570) (1603:1603:1603)) - (PORT datab (1046:1046:1046) (1070:1070:1070)) - (PORT datac (828:828:828) (851:851:851)) - (PORT datad (1814:1814:1814) (1833:1833:1833)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (949:949:949) (1024:1024:1024)) - (PORT datad (1170:1170:1170) (1214:1214:1214)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (972:972:972)) - (PORT datab (1396:1396:1396) (1397:1397:1397)) - (PORT datac (1003:1003:1003) (979:979:979)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (952:952:952)) - (PORT datab (689:689:689) (743:743:743)) - (PORT datac (836:836:836) (869:869:869)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (656:656:656) (712:712:712)) - (PORT datad (646:646:646) (699:699:699)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (608:608:608)) - (PORT datab (600:600:600) (602:602:602)) - (PORT datac (314:314:314) (322:322:322)) - (PORT datad (569:569:569) (556:556:556)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1500:1500:1500) (1470:1470:1470)) - (PORT datad (566:566:566) (575:575:575)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (841:841:841)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (977:977:977) (979:979:979)) - (PORT datad (1115:1115:1115) (1189:1189:1189)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (682:682:682) (746:746:746)) - (PORT datac (892:892:892) (930:930:930)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT datab (1487:1487:1487) (1576:1576:1576)) - (PORT datad (1712:1712:1712) (1762:1762:1762)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (257:257:257)) - (PORT datab (1262:1262:1262) (1251:1251:1251)) - (PORT datac (1524:1524:1524) (1539:1539:1539)) - (PORT datad (1565:1565:1565) (1587:1587:1587)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datac (608:608:608) (638:638:638)) - (PORT datad (622:622:622) (672:672:672)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (949:949:949) (1019:1019:1019)) - (PORT datad (1170:1170:1170) (1216:1216:1216)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1953:1953:1953) (2030:2030:2030)) - (PORT datab (1369:1369:1369) (1339:1339:1339)) - (PORT datac (1030:1030:1030) (1032:1032:1032)) - (PORT datad (590:590:590) (601:601:601)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1077:1077:1077)) - (PORT datab (836:836:836) (855:855:855)) - (PORT datac (1307:1307:1307) (1293:1293:1293)) - (PORT datad (583:583:583) (606:606:606)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1707:1707:1707) (1766:1766:1766)) - (PORT datab (1506:1506:1506) (1630:1630:1630)) - (PORT datac (1568:1568:1568) (1606:1606:1606)) - (PORT datad (804:804:804) (798:798:798)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT datab (1459:1459:1459) (1528:1528:1528)) - (PORT datac (1628:1628:1628) (1684:1684:1684)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1332:1332:1332)) - (PORT datab (1393:1393:1393) (1407:1407:1407)) - (PORT datac (1141:1141:1141) (1158:1158:1158)) - (PORT datad (1120:1120:1120) (1128:1128:1128)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (1043:1043:1043) (1047:1047:1047)) - (PORT datac (1572:1572:1572) (1553:1553:1553)) - (PORT datad (917:917:917) (925:925:925)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (830:830:830)) - (PORT datab (627:627:627) (634:634:634)) - (PORT datac (1906:1906:1906) (1985:1985:1985)) - (PORT datad (841:841:841) (848:848:848)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1569:1569:1569) (1598:1598:1598)) - (PORT datab (226:226:226) (271:271:271)) - (PORT datac (830:830:830) (850:850:850)) - (PORT datad (857:857:857) (879:879:879)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1512:1512:1512) (1637:1637:1637)) - (PORT datad (1661:1661:1661) (1720:1720:1720)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1571:1571:1571) (1603:1603:1603)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (1065:1065:1065) (1076:1076:1076)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1547:1547:1547) (1563:1563:1563)) - (PORT datab (1278:1278:1278) (1257:1257:1257)) - (PORT datac (2333:2333:2333) (2289:2289:2289)) - (PORT datad (1039:1039:1039) (1045:1045:1045)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (838:838:838)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1032:1032:1032) (1056:1056:1056)) - (PORT datad (887:887:887) (933:933:933)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (451:451:451)) - (PORT datab (640:640:640) (686:686:686)) - (PORT datad (826:826:826) (841:841:841)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (950:950:950)) - (PORT datac (615:615:615) (680:680:680)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (2105:2105:2105) (2203:2203:2203)) - (PORT datad (1155:1155:1155) (1194:1194:1194)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (605:605:605)) - (PORT datab (1279:1279:1279) (1256:1256:1256)) - (PORT datac (1522:1522:1522) (1535:1535:1535)) - (PORT datad (826:826:826) (855:855:855)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (835:835:835)) - (PORT datab (324:324:324) (336:336:336)) - (PORT datac (572:572:572) (573:573:573)) - (PORT datad (184:184:184) (210:210:210)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1269:1269:1269)) - (PORT datab (899:899:899) (885:885:885)) - (PORT datac (1284:1284:1284) (1392:1392:1392)) - (PORT datad (1099:1099:1099) (1093:1093:1093)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (237:237:237) (306:306:306)) - (PORT datac (211:211:211) (278:278:278)) - (PORT datad (357:357:357) (411:411:411)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (448:448:448)) - (PORT datab (1552:1552:1552) (1570:1570:1570)) - (PORT datac (1688:1688:1688) (1768:1768:1768)) - (PORT datad (720:720:720) (761:761:761)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (448:448:448)) - (PORT datab (1553:1553:1553) (1570:1570:1570)) - (PORT datac (1689:1689:1689) (1768:1768:1768)) - (PORT datad (721:721:721) (759:759:759)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (449:449:449)) - (PORT datab (1556:1556:1556) (1572:1572:1572)) - (PORT datac (1697:1697:1697) (1777:1777:1777)) - (PORT datad (728:728:728) (764:764:764)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1325:1325:1325)) - (PORT datab (593:593:593) (609:609:609)) - (PORT datac (605:605:605) (616:616:616)) - (PORT datad (604:604:604) (612:612:612)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (670:670:670)) - (PORT datab (1300:1300:1300) (1357:1357:1357)) - (PORT datac (1266:1266:1266) (1321:1321:1321)) - (PORT datad (620:620:620) (667:667:667)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1114:1114:1114)) - (PORT datab (890:890:890) (899:899:899)) - (PORT datac (616:616:616) (683:683:683)) - (PORT datad (642:642:642) (697:697:697)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1273:1273:1273)) - (PORT datab (1068:1068:1068) (1100:1100:1100)) - (PORT datac (615:615:615) (683:683:683)) - (PORT datad (642:642:642) (697:697:697)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (2307:2307:2307) (2328:2328:2328)) - (PORT datab (218:218:218) (250:250:250)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1589:1589:1589) (1515:1515:1515)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (846:846:846)) - (PORT datab (325:325:325) (336:336:336)) - (PORT datad (316:316:316) (321:321:321)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1508:1508:1508) (1562:1562:1562)) - (PORT datab (1430:1430:1430) (1500:1500:1500)) - (PORT datac (1542:1542:1542) (1567:1567:1567)) - (PORT datad (1606:1606:1606) (1669:1669:1669)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1062:1062:1062)) - (PORT datab (1383:1383:1383) (1397:1397:1397)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (723:723:723) (755:755:755)) - (PORT datac (908:908:908) (930:930:930)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1660:1660:1660) (1705:1705:1705)) - (PORT datab (984:984:984) (1027:1027:1027)) - (PORT datac (1577:1577:1577) (1613:1613:1613)) - (PORT datad (198:198:198) (233:233:233)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1318:1318:1318)) - (PORT datad (1839:1839:1839) (1872:1872:1872)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1313:1313:1313)) - (PORT datab (798:798:798) (793:793:793)) - (PORT datac (847:847:847) (872:872:872)) - (PORT datad (579:579:579) (571:571:571)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1144:1144:1144)) - (PORT datab (237:237:237) (284:284:284)) - (PORT datac (853:853:853) (889:889:889)) - (PORT datad (1096:1096:1096) (1108:1108:1108)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (526:526:526)) - (PORT datab (1228:1228:1228) (1309:1309:1309)) - (PORT datac (750:750:750) (728:728:728)) - (PORT datad (768:768:768) (830:830:830)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1709:1709:1709) (1770:1770:1770)) - (PORT datab (1512:1512:1512) (1639:1639:1639)) - (PORT datac (1577:1577:1577) (1614:1614:1614)) - (PORT datad (805:805:805) (801:801:801)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT datab (1495:1495:1495) (1566:1566:1566)) - (PORT datac (1289:1289:1289) (1304:1304:1304)) - (PORT datad (1218:1218:1218) (1232:1232:1232)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (1921:1921:1921) (2005:2005:2005)) - (PORT datad (864:864:864) (923:923:923)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (875:875:875)) - (PORT datab (1280:1280:1280) (1258:1258:1258)) - (PORT datac (1522:1522:1522) (1535:1535:1535)) - (PORT datad (1077:1077:1077) (1089:1089:1089)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (850:850:850)) - (PORT datab (644:644:644) (683:683:683)) - (PORT datac (848:848:848) (848:848:848)) - (PORT datad (612:612:612) (648:648:648)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1083:1083:1083)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (807:807:807) (819:819:819)) - (PORT datad (167:167:167) (193:193:193)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (952:952:952)) - (PORT datab (1859:1859:1859) (1833:1833:1833)) - (PORT datac (921:921:921) (925:925:925)) - (PORT datad (1019:1019:1019) (1028:1028:1028)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) - (DELAY - (ABSOLUTE - (PORT dataa (2247:2247:2247) (2326:2326:2326)) - (PORT datab (1119:1119:1119) (1163:1163:1163)) - (PORT datac (1293:1293:1293) (1352:1352:1352)) - (PORT datad (523:523:523) (502:502:502)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (454:454:454)) - (PORT datab (694:694:694) (743:743:743)) - (PORT datac (992:992:992) (977:977:977)) - (PORT datad (726:726:726) (769:769:769)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2033:2033:2033) (2119:2119:2119)) - (PORT datab (639:639:639) (633:633:633)) - (PORT datac (782:782:782) (792:792:792)) - (PORT datad (1734:1734:1734) (1802:1802:1802)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1631:1631:1631) (1680:1680:1680)) - (PORT datab (676:676:676) (710:710:710)) - (PORT datac (1712:1712:1712) (1688:1688:1688)) - (PORT datad (1483:1483:1483) (1569:1569:1569)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (807:807:807)) - (PORT datab (1727:1727:1727) (1808:1808:1808)) - (PORT datac (306:306:306) (314:314:314)) - (PORT datad (1560:1560:1560) (1564:1564:1564)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (911:911:911)) - (PORT datab (1754:1754:1754) (1831:1831:1831)) - (PORT datac (2007:2007:2007) (2086:2086:2086)) - (PORT datad (885:885:885) (892:892:892)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (1556:1556:1556) (1562:1562:1562)) - (PORT datad (2013:2013:2013) (2000:2000:2000)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_ir_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1195:1195:1195) (1217:1217:1217)) - (PORT datab (612:612:612) (634:634:634)) - (PORT datac (788:788:788) (784:784:784)) - (PORT datad (788:788:788) (785:785:785)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1345:1345:1345)) - (PORT datab (1382:1382:1382) (1399:1399:1399)) - (PORT datac (1139:1139:1139) (1152:1152:1152)) - (PORT datad (858:858:858) (880:880:880)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (824:824:824) (846:846:846)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1653:1653:1653)) - (PORT datab (1510:1510:1510) (1635:1635:1635)) - (PORT datad (1659:1659:1659) (1723:1723:1723)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (950:950:950)) - (PORT datac (1218:1218:1218) (1276:1276:1276)) - (PORT datad (839:839:839) (848:848:848)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (2475:2475:2475) (2459:2459:2459)) - (PORT datab (691:691:691) (713:713:713)) - (PORT datac (931:931:931) (942:942:942)) - (PORT datad (824:824:824) (829:829:829)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (947:947:947)) - (PORT datac (1000:1000:1000) (977:977:977)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datab (1427:1427:1427) (1496:1496:1496)) - (PORT datac (1102:1102:1102) (1138:1138:1138)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (950:950:950)) - (PORT datab (1342:1342:1342) (1352:1352:1352)) - (PORT datac (1221:1221:1221) (1276:1276:1276)) - (PORT datad (842:842:842) (847:847:847)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1154:1154:1154)) - (PORT datab (586:586:586) (599:599:599)) - (PORT datac (1084:1084:1084) (1105:1105:1105)) - (PORT datad (1804:1804:1804) (1823:1823:1823)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1175:1175:1175)) - (PORT datab (1273:1273:1273) (1347:1347:1347)) - (PORT datac (2079:2079:2079) (2115:2115:2115)) - (PORT datad (2221:2221:2221) (2289:2289:2289)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (797:797:797)) - (PORT datab (1722:1722:1722) (1802:1802:1802)) - (PORT datac (303:303:303) (310:310:310)) - (PORT datad (1551:1551:1551) (1557:1557:1557)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1260:1260:1260)) - (PORT datab (599:599:599) (621:621:621)) - (PORT datac (2053:2053:2053) (2071:2071:2071)) - (PORT datad (1859:1859:1859) (1881:1881:1881)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1174:1174:1174)) - (PORT datab (1320:1320:1320) (1383:1383:1383)) - (PORT datac (2080:2080:2080) (2112:2112:2112)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (335:335:335) (353:353:353)) - (PORT datac (756:756:756) (738:738:738)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1537:1537:1537) (1557:1557:1557)) - (PORT datac (830:830:830) (840:840:840)) - (PORT datad (1280:1280:1280) (1312:1312:1312)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1478:1478:1478)) - (PORT datab (1862:1862:1862) (1832:1832:1832)) - (PORT datac (1042:1042:1042) (1038:1038:1038)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2478:2478:2478) (2461:2461:2461)) - (PORT datab (948:948:948) (952:952:952)) - (PORT datac (734:734:734) (800:800:800)) - (PORT datad (654:654:654) (677:677:677)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (559:559:559)) - (PORT datab (730:730:730) (752:752:752)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (905:905:905)) - (PORT datab (1094:1094:1094) (1112:1112:1112)) - (PORT datac (1746:1746:1746) (1751:1751:1751)) - (PORT datad (595:595:595) (593:593:593)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1577:1577:1577)) - (PORT datab (529:529:529) (518:518:518)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (326:326:326) (338:338:338)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (376:376:376)) - (PORT datab (853:853:853) (886:886:886)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1016:1016:1016) (989:989:989)) + (PORT dataa (895:895:895) (947:947:947)) + (PORT datac (892:892:892) (955:955:955)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datab (1267:1267:1267) (1333:1333:1333)) - (PORT datad (898:898:898) (935:935:935)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (588:588:588)) - (PORT datab (748:748:748) (794:794:794)) - (PORT datac (1608:1608:1608) (1628:1628:1628)) - (PORT datad (183:183:183) (210:210:210)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1133:1133:1133)) - (PORT datab (743:743:743) (811:811:811)) - (PORT datac (735:735:735) (804:804:804)) - (PORT datad (824:824:824) (826:826:826)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1160:1160:1160) (1141:1141:1141)) - (PORT datac (965:965:965) (934:934:934)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (831:831:831)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (177:177:177) (209:209:209)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (598:598:598)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (332:332:332) (342:342:342)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT datab (1429:1429:1429) (1498:1498:1498)) - (PORT datac (1542:1542:1542) (1565:1565:1565)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1309:1309:1309)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1112:1112:1112) (1185:1185:1185)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1785:1785:1785) (1881:1881:1881)) - (PORT datac (1081:1081:1081) (1098:1098:1098)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (267:267:267)) - (PORT datab (1434:1434:1434) (1483:1483:1483)) - (PORT datac (1567:1567:1567) (1609:1609:1609)) - (PORT datad (1224:1224:1224) (1189:1189:1189)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1385:1385:1385)) - (PORT datab (1098:1098:1098) (1122:1122:1122)) - (PORT datac (588:588:588) (603:603:603)) - (PORT datad (590:590:590) (613:613:613)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (949:949:949) (1021:1021:1021)) - (PORT datad (1172:1172:1172) (1211:1211:1211)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2139:2139:2139) (2190:2190:2190)) - (PORT datac (1244:1244:1244) (1363:1363:1363)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1736:1736:1736) (1797:1797:1797)) - (PORT datab (1491:1491:1491) (1581:1581:1581)) - (PORT datac (1356:1356:1356) (1359:1359:1359)) - (PORT datad (972:972:972) (995:995:995)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (595:595:595)) - (PORT datab (1265:1265:1265) (1228:1228:1228)) - (PORT datac (580:580:580) (584:584:584)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1097:1097:1097)) - (PORT datab (616:616:616) (630:630:630)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (551:551:551) (557:557:557)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1341:1341:1341) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1366:1366:1366)) - (PORT ena (1137:1137:1137) (1130:1130:1130)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (1341:1341:1341) (1362:1362:1362)) - (PORT asdata (644:644:644) (684:684:684)) - (PORT clrn (1398:1398:1398) (1366:1366:1366)) - (PORT ena (1319:1319:1319) (1295:1295:1295)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (601:601:601) (634:634:634)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) - (PORT asdata (512:512:512) (577:577:577)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (227:227:227) (296:296:296)) - (PORT datad (601:601:601) (632:632:632)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1482:1482:1482)) - (PORT datac (1345:1345:1345) (1347:1347:1347)) - (PORT datad (1091:1091:1091) (1102:1102:1102)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (251:251:251)) - (PORT datab (201:201:201) (242:242:242)) - (PORT datac (904:904:904) (954:954:954)) - (PORT datad (1379:1379:1379) (1423:1423:1423)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1135:1135:1135)) - (PORT datab (1720:1720:1720) (1750:1750:1750)) - (PORT datac (949:949:949) (988:988:988)) - (PORT datad (945:945:945) (974:974:974)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1630:1630:1630) (1658:1658:1658)) - (PORT datab (618:618:618) (608:608:608)) - (PORT datad (1474:1474:1474) (1554:1554:1554)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (849:849:849)) - (PORT datab (1155:1155:1155) (1145:1145:1145)) - (PORT datac (772:772:772) (767:767:767)) - (PORT datad (170:170:170) (198:198:198)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (915:915:915)) - (PORT datab (923:923:923) (932:932:932)) - (PORT datac (1866:1866:1866) (1882:1882:1882)) - (PORT datad (1378:1378:1378) (1423:1423:1423)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (624:624:624)) - (PORT datab (1389:1389:1389) (1428:1428:1428)) - (PORT datac (1587:1587:1587) (1630:1630:1630)) - (PORT datad (584:584:584) (589:589:589)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (588:588:588)) - (PORT datab (1638:1638:1638) (1656:1656:1656)) - (PORT datac (837:837:837) (842:842:842)) - (PORT datad (536:536:536) (520:520:520)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (566:566:566)) - (PORT datab (601:601:601) (607:607:607)) - (PORT datac (1296:1296:1296) (1331:1331:1331)) - (PORT datad (1633:1633:1633) (1669:1669:1669)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (596:596:596)) - (PORT datab (1100:1100:1100) (1091:1091:1091)) - (PORT datac (845:845:845) (862:862:862)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (577:577:577)) - (PORT datab (1648:1648:1648) (1662:1662:1662)) - (PORT datac (793:793:793) (797:797:797)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datab (2396:2396:2396) (2501:2501:2501)) - (PORT datac (1871:1871:1871) (1915:1915:1915)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1550:1550:1550) (1564:1564:1564)) - (PORT datab (1539:1539:1539) (1529:1529:1529)) - (PORT datac (1247:1247:1247) (1224:1224:1224)) - (PORT datad (1044:1044:1044) (1047:1047:1047)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (880:880:880)) - (PORT datab (1138:1138:1138) (1170:1170:1170)) - (PORT datac (626:626:626) (666:666:666)) - (PORT datad (619:619:619) (648:648:648)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (687:687:687)) - (PORT datab (187:187:187) (222:222:222)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1084:1084:1084) (1079:1079:1079)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1193:1193:1193)) - (PORT datab (1013:1013:1013) (1018:1018:1018)) - (PORT datac (1287:1287:1287) (1305:1305:1305)) - (PORT datad (177:177:177) (200:200:200)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1393:1393:1393)) - (PORT datab (1387:1387:1387) (1462:1462:1462)) - (PORT datac (1310:1310:1310) (1344:1344:1344)) - (PORT datad (1293:1293:1293) (1282:1282:1282)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (592:592:592) (611:611:611)) - (PORT datac (1631:1631:1631) (1624:1624:1624)) - (PORT datad (606:606:606) (614:614:614)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT datac (1102:1102:1102) (1136:1136:1136)) - (PORT datad (1113:1113:1113) (1099:1099:1099)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1398:1398:1398)) - (PORT datab (1077:1077:1077) (1044:1044:1044)) - (PORT datac (605:605:605) (616:616:616)) - (PORT datad (1359:1359:1359) (1428:1428:1428)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT datac (1106:1106:1106) (1139:1139:1139)) - (PORT datad (1116:1116:1116) (1102:1102:1102)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (617:617:617)) - (PORT datab (224:224:224) (262:262:262)) - (PORT datac (853:853:853) (861:861:861)) - (PORT datad (778:778:778) (766:766:766)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (859:859:859)) - (PORT datab (838:838:838) (840:840:840)) - (PORT datac (823:823:823) (821:821:821)) - (PORT datad (548:548:548) (544:544:544)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1392:1392:1392)) - (PORT datad (1125:1125:1125) (1163:1163:1163)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (595:595:595)) - (PORT datab (763:763:763) (763:763:763)) - (PORT datac (1019:1019:1019) (998:998:998)) - (PORT datad (2206:2206:2206) (2183:2183:2183)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1406:1406:1406) (1372:1372:1372)) - (PORT ena (1106:1106:1106) (1073:1073:1073)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (199:199:199) (257:257:257)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1406:1406:1406) (1372:1372:1372)) - (PORT ena (1081:1081:1081) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (848:848:848)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (246:246:246)) - (PORT datab (226:226:226) (295:295:295)) - (PORT datac (948:948:948) (966:966:966)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) @@ -4817,16 +3209,16 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) + (PORT clk (1347:1347:1347) (1357:1357:1357)) + (PORT asdata (1041:1041:1041) (1030:1030:1030)) + (PORT clrn (1383:1383:1383) (1356:1356:1356)) + (PORT ena (1123:1123:1123) (1109:1109:1109)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -4835,8 +3227,8 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (200:200:200) (256:256:256)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (196:196:196) (263:263:263)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -4845,10 +3237,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT clk (1347:1347:1347) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) + (PORT clrn (1383:1383:1383) (1356:1356:1356)) + (PORT ena (1123:1123:1123) (1109:1109:1109)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -4863,10 +3255,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1342:1342:1342) (1363:1363:1363)) - (PORT asdata (510:510:510) (576:576:576)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1171:1171:1171) (1166:1166:1166)) + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (512:512:512) (579:579:579)) + (PORT clrn (1383:1383:1383) (1356:1356:1356)) + (PORT ena (1152:1152:1152) (1151:1151:1151)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -4881,9 +3273,9 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1039:1039:1039) (1034:1034:1034)) - (PORT datab (226:226:226) (295:295:295)) - (PORT datad (1281:1281:1281) (1269:1269:1269)) + (PORT dataa (1083:1083:1083) (1108:1108:1108)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datad (393:393:393) (443:443:443)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -4891,215 +3283,83 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1553:1553:1553)) + (PORT datab (1150:1150:1150) (1183:1183:1183)) + (PORT datac (2217:2217:2217) (2266:2266:2266)) + (PORT datad (1154:1154:1154) (1214:1214:1214)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1210:1210:1210)) + (PORT datac (1427:1427:1427) (1561:1561:1561)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (1396:1396:1396) (1444:1444:1444)) + (PORT datad (1675:1675:1675) (1681:1681:1681)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (836:836:836) (873:873:873)) + (PORT datad (1720:1720:1720) (1801:1801:1801)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1158:1158:1158)) + (PORT datab (1132:1132:1132) (1158:1158:1158)) + (PORT datac (640:640:640) (702:702:702)) + (PORT datad (210:210:210) (267:267:267)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (979:979:979)) - (PORT datab (213:213:213) (252:252:252)) - (PORT datac (1004:1004:1004) (980:980:980)) - (PORT datad (1362:1362:1362) (1362:1362:1362)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1239:1239:1239)) - (PORT datab (859:859:859) (906:906:906)) - (PORT datac (1070:1070:1070) (1079:1079:1079)) - (PORT datad (1323:1323:1323) (1313:1313:1313)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1597:1597:1597) (1647:1647:1647)) - (PORT datab (1506:1506:1506) (1630:1630:1630)) - (PORT datac (957:957:957) (996:996:996)) - (PORT datad (1662:1662:1662) (1723:1723:1723)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datab (1487:1487:1487) (1576:1576:1576)) - (PORT datad (1709:1709:1709) (1762:1762:1762)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (283:283:283)) - (PORT datab (1540:1540:1540) (1662:1662:1662)) - (PORT datac (1184:1184:1184) (1265:1265:1265)) - (PORT datad (2637:2637:2637) (2640:2640:2640)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (283:283:283)) - (PORT datab (859:859:859) (906:906:906)) - (PORT datac (1069:1069:1069) (1079:1079:1079)) - (PORT datad (1624:1624:1624) (1620:1620:1620)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1050:1050:1050) (1048:1048:1048)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1299:1299:1299) (1293:1293:1293)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1461:1461:1461)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (459:459:459)) - (PORT datad (554:554:554) (560:560:560)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1365:1365:1365)) - (PORT datab (1332:1332:1332) (1322:1322:1322)) - (PORT datac (1245:1245:1245) (1363:1363:1363)) - (PORT datad (2346:2346:2346) (2359:2359:2359)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (893:893:893) (884:884:884)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (889:889:889) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (402:402:402)) - (PORT datab (795:795:795) (809:809:809)) - (PORT datad (240:240:240) (313:313:313)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1480:1480:1480)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (1341:1341:1341) (1345:1345:1345)) - (PORT datad (1097:1097:1097) (1108:1108:1108)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1573:1573:1573)) - (PORT datab (217:217:217) (259:259:259)) - (PORT datac (1619:1619:1619) (1657:1657:1657)) - (PORT datad (742:742:742) (792:792:792)) + (PORT dataa (209:209:209) (251:251:251)) + (PORT datab (675:675:675) (699:699:699)) + (PORT datac (2706:2706:2706) (2722:2722:2722)) + (PORT datad (1036:1036:1036) (1031:1031:1031)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -5109,2457 +3369,50 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (INSTANCE z80_\|execute_\|ixy_d\~5) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (440:440:440)) - (PORT datab (1176:1176:1176) (1203:1203:1203)) - (PORT datac (1234:1234:1234) (1231:1231:1231)) - (PORT datad (603:603:603) (609:609:609)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT datab (604:604:604) (597:597:597)) - (PORT datac (795:795:795) (782:782:782)) - (PORT datad (799:799:799) (783:783:783)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (455:455:455)) - (PORT datab (1557:1557:1557) (1576:1576:1576)) - (PORT datac (1699:1699:1699) (1776:1776:1776)) - (PORT datad (730:730:730) (769:769:769)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT datab (1349:1349:1349) (1345:1345:1345)) - (PORT datac (1089:1089:1089) (1093:1093:1093)) - (PORT datad (1319:1319:1319) (1350:1350:1350)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (753:753:753)) - (PORT datab (696:696:696) (742:742:742)) - (PORT datac (1684:1684:1684) (1774:1774:1774)) - (PORT datad (1557:1557:1557) (1563:1563:1563)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (834:834:834)) - (PORT datab (935:935:935) (980:980:980)) - (PORT datac (1341:1341:1341) (1347:1347:1347)) - (PORT datad (1383:1383:1383) (1430:1430:1430)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (852:852:852)) - (PORT datab (813:813:813) (885:885:885)) - (PORT datac (979:979:979) (978:978:978)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT datab (587:587:587) (614:614:614)) - (PORT datac (745:745:745) (737:737:737)) - (PORT datad (786:786:786) (792:792:792)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1483:1483:1483)) - (PORT datac (1341:1341:1341) (1348:1348:1348)) - (PORT datad (1095:1095:1095) (1108:1108:1108)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1378:1378:1378)) - (PORT datab (881:881:881) (916:916:916)) - (PORT datac (1105:1105:1105) (1111:1111:1111)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1100:1100:1100)) - (PORT datab (614:614:614) (623:623:623)) - (PORT datac (1539:1539:1539) (1535:1535:1535)) - (PORT datad (835:835:835) (864:864:864)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1660:1660:1660) (1708:1708:1708)) - (PORT datab (986:986:986) (1030:1030:1030)) - (PORT datac (1575:1575:1575) (1607:1607:1607)) - (PORT datad (199:199:199) (234:234:234)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1952:1952:1952) (2030:2030:2030)) - (PORT datab (2427:2427:2427) (2430:2430:2430)) - (PORT datac (1261:1261:1261) (1331:1331:1331)) - (PORT datad (812:812:812) (821:821:821)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2086:2086:2086) (2103:2103:2103)) - (PORT datab (208:208:208) (244:244:244)) - (PORT datac (572:572:572) (594:594:594)) - (PORT datad (932:932:932) (948:948:948)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT datab (1476:1476:1476) (1476:1476:1476)) - (PORT datac (1114:1114:1114) (1140:1140:1140)) - (PORT datad (1029:1029:1029) (1014:1014:1014)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1262:1262:1262)) - (PORT datab (902:902:902) (889:889:889)) - (PORT datac (1271:1271:1271) (1381:1381:1381)) - (PORT datad (1104:1104:1104) (1099:1099:1099)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (834:834:834)) - (PORT datab (934:934:934) (979:979:979)) - (PORT datac (1346:1346:1346) (1352:1352:1352)) - (PORT datad (1377:1377:1377) (1422:1422:1422)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (745:745:745)) - (PORT datab (559:559:559) (562:562:562)) - (PORT datac (1499:1499:1499) (1474:1474:1474)) - (PORT datad (1478:1478:1478) (1428:1428:1428)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (627:627:627)) - (PORT datac (1034:1034:1034) (1025:1025:1025)) - (PORT datad (730:730:730) (781:781:781)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1953:1953:1953) (2030:2030:2030)) - (PORT datab (629:629:629) (636:636:636)) - (PORT datac (980:980:980) (1006:1006:1006)) - (PORT datad (803:803:803) (792:792:792)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (359:359:359)) - (PORT datab (357:357:357) (376:376:376)) - (PORT datac (602:602:602) (637:637:637)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1290:1290:1290)) - (PORT datab (1773:1773:1773) (1782:1782:1782)) - (PORT datac (828:828:828) (852:852:852)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (2849:2849:2849) (2861:2861:2861)) - (PORT datab (788:788:788) (790:790:790)) - (PORT datac (1333:1333:1333) (1397:1397:1397)) - (PORT datad (1833:1833:1833) (1840:1840:1840)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datab (1671:1671:1671) (1701:1701:1701)) - (PORT datad (2143:2143:2143) (2150:2150:2150)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (831:831:831)) - (PORT datab (367:367:367) (377:377:377)) - (PORT datac (1620:1620:1620) (1657:1657:1657)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1121:1121:1121)) - (PORT datab (1637:1637:1637) (1660:1660:1660)) - (PORT datac (551:551:551) (557:557:557)) - (PORT datad (574:574:574) (580:580:580)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (814:814:814) (824:824:824)) - (PORT datac (860:860:860) (867:867:867)) - (PORT datad (541:541:541) (534:534:534)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1764:1764:1764) (1758:1758:1758)) - (PORT datab (1523:1523:1523) (1607:1607:1607)) - (PORT datac (569:569:569) (589:589:589)) - (PORT datad (1607:1607:1607) (1641:1641:1641)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (812:812:812)) - (PORT datab (320:320:320) (342:342:342)) - (PORT datac (1860:1860:1860) (1884:1884:1884)) - (PORT datad (1016:1016:1016) (987:987:987)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (235:235:235) (280:280:280)) - (PORT datac (313:313:313) (326:326:326)) - (PORT datad (175:175:175) (207:207:207)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1086:1086:1086)) - (PORT datab (608:608:608) (606:606:606)) - (PORT datac (856:856:856) (883:883:883)) - (PORT datad (1058:1058:1058) (1075:1075:1075)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1578:1578:1578)) - (PORT datab (1260:1260:1260) (1253:1253:1253)) - (PORT datac (1618:1618:1618) (1659:1659:1659)) - (PORT datad (195:195:195) (230:230:230)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (571:571:571) (582:582:582)) - (PORT datad (774:774:774) (751:751:751)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1122:1122:1122)) - (PORT datab (337:337:337) (355:355:355)) - (PORT datac (1690:1690:1690) (1716:1716:1716)) - (PORT datad (552:552:552) (547:547:547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2354:2354:2354) (2371:2371:2371)) - (PORT datab (2281:2281:2281) (2388:2388:2388)) - (PORT datad (1694:1694:1694) (1723:1723:1723)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1769:1769:1769) (1792:1792:1792)) - (PORT datab (840:840:840) (833:833:833)) - (PORT datac (1477:1477:1477) (1567:1567:1567)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1571:1571:1571) (1599:1599:1599)) - (PORT datab (1022:1022:1022) (1035:1035:1035)) - (PORT datac (829:829:829) (849:849:849)) - (PORT datad (200:200:200) (234:234:234)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (887:887:887)) - (PORT datab (1315:1315:1315) (1279:1279:1279)) - (PORT datac (571:571:571) (589:589:589)) - (PORT datad (757:757:757) (740:740:740)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1763:1763:1763) (1758:1758:1758)) - (PORT datab (1523:1523:1523) (1606:1606:1606)) - (PORT datac (569:569:569) (589:589:589)) - (PORT datad (1606:1606:1606) (1641:1641:1641)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2078:2078:2078) (2098:2098:2098)) - (PORT datab (817:817:817) (813:813:813)) - (PORT datac (1449:1449:1449) (1527:1527:1527)) - (PORT datad (1563:1563:1563) (1582:1582:1582)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (850:850:850)) - (PORT datab (1486:1486:1486) (1494:1494:1494)) - (PORT datac (1101:1101:1101) (1111:1111:1111)) - (PORT datad (1541:1541:1541) (1528:1528:1528)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (715:715:715)) - (PORT datab (1476:1476:1476) (1477:1477:1477)) - (PORT datac (1114:1114:1114) (1140:1140:1140)) - (PORT datad (1029:1029:1029) (1014:1014:1014)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1948:1948:1948) (2028:2028:2028)) - (PORT datab (1367:1367:1367) (1339:1339:1339)) - (PORT datac (1029:1029:1029) (1032:1032:1032)) - (PORT datad (588:588:588) (601:601:601)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (880:880:880)) - (PORT datab (516:516:516) (522:522:522)) - (PORT datac (524:524:524) (516:516:516)) - (PORT datad (531:531:531) (528:528:528)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (200:200:200) (227:227:227)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (845:845:845)) - (PORT datab (647:647:647) (671:671:671)) - (PORT datac (1229:1229:1229) (1207:1207:1207)) - (PORT datad (1102:1102:1102) (1090:1090:1090)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (859:859:859)) - (PORT datab (1348:1348:1348) (1390:1390:1390)) - (PORT datac (813:813:813) (820:820:820)) - (PORT datad (196:196:196) (223:223:223)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (816:816:816)) - (PORT datab (637:637:637) (677:677:677)) - (PORT datac (300:300:300) (310:310:310)) - (PORT datad (782:782:782) (796:796:796)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (629:629:629)) - (PORT datab (829:829:829) (844:844:844)) - (PORT datac (161:161:161) (193:193:193)) - (PORT datad (808:808:808) (810:810:810)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (447:447:447)) - (PORT datab (1020:1020:1020) (1003:1003:1003)) - (PORT datac (661:661:661) (717:717:717)) - (PORT datad (657:657:657) (710:710:710)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (575:575:575)) - (PORT datab (609:609:609) (624:624:624)) - (PORT datac (537:537:537) (527:527:527)) - (PORT datad (608:608:608) (626:626:626)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (806:806:806)) - (PORT datab (579:579:579) (559:559:559)) - (PORT datac (1390:1390:1390) (1397:1397:1397)) - (PORT datad (173:173:173) (204:204:204)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (838:838:838) (844:844:844)) - (PORT datac (529:529:529) (549:549:549)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (601:601:601)) - (PORT datab (1146:1146:1146) (1144:1144:1144)) - (PORT datad (816:816:816) (825:825:825)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1101:1101:1101)) - (PORT datab (583:583:583) (608:608:608)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (2206:2206:2206) (2183:2183:2183)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (734:734:734)) - (PORT datab (555:555:555) (548:548:548)) - (PORT datac (776:776:776) (786:786:786)) - (PORT datad (915:915:915) (946:946:946)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1171:1171:1171) (1166:1166:1166)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (213:213:213) (279:279:279)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (303:303:303)) - (PORT datad (212:212:212) (278:278:278)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (762:762:762) (763:763:763)) - (PORT datac (183:183:183) (219:219:219)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (1725:1725:1725) (1809:1809:1809)) - (PORT datac (2847:2847:2847) (2968:2968:2968)) - (PORT datad (2391:2391:2391) (2370:2370:2370)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (769:769:769) (767:767:767)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datab (259:259:259) (342:342:342)) - (PORT datad (228:228:228) (301:301:301)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (2878:2878:2878) (3118:3118:3118)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (207:207:207) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (206:206:206) (266:266:266)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (207:207:207) (270:270:270)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (277:277:277)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (307:307:307)) - (PORT datab (229:229:229) (300:300:300)) - (PORT datac (353:353:353) (394:394:394)) - (PORT datad (207:207:207) (267:267:267)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (206:206:206) (267:267:267)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (307:307:307)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datac (202:202:202) (271:271:271)) - (PORT datad (208:208:208) (269:269:269)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (203:203:203) (272:272:272)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (308:308:308)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (204:204:204) (277:277:277)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1377:1377:1377) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (PORT ena (1966:1966:1966) (2011:2011:2011)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (331:331:331)) - (PORT datab (250:250:250) (327:327:327)) - (PORT datad (228:228:228) (300:300:300)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (PORT ena (1966:1966:1966) (2011:2011:2011)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (336:336:336)) - (PORT datab (261:261:261) (345:345:345)) - (PORT datad (225:225:225) (295:295:295)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (PORT ena (1966:1966:1966) (2011:2011:2011)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (337:337:337)) - (PORT datab (258:258:258) (340:340:340)) - (PORT datad (222:222:222) (293:293:293)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (PORT ena (1966:1966:1966) (2011:2011:2011)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (334:334:334)) - (PORT datab (260:260:260) (343:343:343)) - (PORT datad (225:225:225) (294:294:294)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (334:334:334)) - (PORT datab (250:250:250) (330:330:330)) - (PORT datac (356:356:356) (394:394:394)) - (PORT datad (2885:2885:2885) (3130:3130:3130)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (331:331:331)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1378:1378:1378) (1434:1434:1434)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT asdata (3179:3179:3179) (3438:3438:3438)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (PORT ena (1512:1512:1512) (1469:1469:1469)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT asdata (639:639:639) (682:682:682)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (PORT ena (1512:1512:1512) (1469:1469:1469)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT asdata (556:556:556) (650:650:650)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (PORT ena (1512:1512:1512) (1469:1469:1469)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT asdata (1195:1195:1195) (1234:1234:1234)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (PORT ena (1544:1544:1544) (1514:1514:1514)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT asdata (1143:1143:1143) (1183:1183:1183)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (PORT ena (1512:1512:1512) (1469:1469:1469)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT asdata (1231:1231:1231) (1282:1282:1282)) - (PORT clrn (1364:1364:1364) (1345:1345:1345)) - (PORT ena (1310:1310:1310) (1303:1303:1303)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT asdata (1089:1089:1089) (1101:1101:1101)) - (PORT clrn (1364:1364:1364) (1345:1345:1345)) - (PORT ena (1310:1310:1310) (1303:1303:1303)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT asdata (549:549:549) (628:628:628)) - (PORT clrn (1364:1364:1364) (1345:1345:1345)) - (PORT ena (1310:1310:1310) (1303:1303:1303)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT asdata (1169:1169:1169) (1199:1199:1199)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (PORT ena (1512:1512:1512) (1469:1469:1469)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (374:374:374)) - (PORT datab (861:861:861) (916:916:916)) - (PORT datac (227:227:227) (302:302:302)) - (PORT datad (873:873:873) (914:914:914)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (795:795:795)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (854:854:854) (890:890:890)) - (PORT datad (241:241:241) (306:306:306)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (382:382:382)) - (PORT datab (914:914:914) (947:947:947)) - (PORT datad (241:241:241) (306:306:306)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (893:893:893)) - (PORT datab (886:886:886) (920:920:920)) - (PORT datad (690:690:690) (760:760:760)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (213:213:213) (280:280:280)) - (PORT datad (286:286:286) (291:291:291)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (627:627:627)) - (PORT datab (2920:2920:2920) (3163:3163:3163)) - (PORT datac (1379:1379:1379) (1434:1434:1434)) - (PORT datad (168:168:168) (194:194:194)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (637:637:637)) - (PORT datab (808:808:808) (833:833:833)) - (PORT datad (647:647:647) (688:688:688)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (706:706:706)) - (PORT datab (719:719:719) (793:793:793)) - (PORT datac (655:655:655) (717:717:717)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (721:721:721)) - (PORT datad (681:681:681) (732:732:732)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (640:640:640)) - (PORT datad (640:640:640) (679:679:679)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (PORT ena (1363:1363:1363) (1376:1376:1376)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (367:367:367)) - (PORT datab (635:635:635) (657:657:657)) - (PORT datac (831:831:831) (852:852:852)) - (PORT datad (243:243:243) (311:311:311)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (612:612:612)) - (PORT datab (704:704:704) (753:753:753)) - (PORT datac (164:164:164) (199:199:199)) - (PORT datad (1045:1045:1045) (1020:1020:1020)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (393:393:393)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1867:1867:1867)) - (PORT datab (1390:1390:1390) (1410:1410:1410)) - (PORT datad (1075:1075:1075) (1122:1122:1122)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1712:1712:1712) (1681:1681:1681)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (878:878:878) (897:897:897)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (206:206:206) (266:266:266)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1357:1357:1357)) - (PORT asdata (512:512:512) (579:579:579)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (663:663:663)) - (PORT datab (228:228:228) (300:300:300)) - (PORT datad (207:207:207) (267:267:267)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1231:1231:1231)) - (PORT datab (904:904:904) (957:957:957)) - (PORT datac (577:577:577) (604:604:604)) - (PORT datad (822:822:822) (821:821:821)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1769:1769:1769) (1790:1790:1790)) - (PORT datab (1100:1100:1100) (1090:1090:1090)) - (PORT datac (1480:1480:1480) (1567:1567:1567)) - (PORT datad (802:802:802) (795:795:795)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1769:1769:1769) (1790:1790:1790)) - (PORT datab (839:839:839) (830:830:830)) - (PORT datac (1480:1480:1480) (1567:1567:1567)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1766:1766:1766) (1793:1793:1793)) - (PORT datab (1619:1619:1619) (1580:1580:1580)) - (PORT datac (1477:1477:1477) (1564:1564:1564)) - (PORT datad (802:802:802) (798:798:798)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (224:224:224) (275:275:275)) - (PORT datad (224:224:224) (272:272:272)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (593:593:593)) - (PORT datac (1545:1545:1545) (1548:1548:1548)) - (PORT datad (1056:1056:1056) (1053:1053:1053)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (625:625:625)) - (PORT datac (582:582:582) (572:572:572)) - (PORT datad (1137:1137:1137) (1128:1128:1128)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (623:623:623)) - (PORT datab (1339:1339:1339) (1318:1318:1318)) - (PORT datac (546:546:546) (541:541:541)) - (PORT datad (1030:1030:1030) (1043:1043:1043)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (611:611:611)) - (PORT datab (872:872:872) (860:860:860)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (814:814:814) (809:809:809)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT datab (1381:1381:1381) (1395:1395:1395)) - (PORT datac (1136:1136:1136) (1148:1148:1148)) - (PORT datad (1310:1310:1310) (1319:1319:1319)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1262:1262:1262)) - (PORT datab (1477:1477:1477) (1550:1550:1550)) - (PORT datac (572:572:572) (595:595:595)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1828:1828:1828) (1912:1912:1912)) - (PORT datab (2391:2391:2391) (2483:2483:2483)) - (PORT datad (1582:1582:1582) (1631:1631:1631)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1353:1353:1353)) - (PORT datab (905:905:905) (879:879:879)) - (PORT datac (806:806:806) (821:821:821)) - (PORT datad (847:847:847) (864:864:864)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (2180:2180:2180) (2223:2223:2223)) - (PORT datac (1740:1740:1740) (1694:1694:1694)) - (PORT datad (1637:1637:1637) (1696:1696:1696)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (904:904:904)) - (PORT datab (189:189:189) (225:225:225)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1133:1133:1133)) - (PORT datab (590:590:590) (569:569:569)) - (PORT datac (831:831:831) (859:859:859)) - (PORT datad (802:802:802) (806:806:806)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (831:831:831) (824:824:824)) - (PORT datac (571:571:571) (589:589:589)) - (PORT datad (583:583:583) (587:587:587)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (803:803:803)) - (PORT datab (1408:1408:1408) (1461:1461:1461)) - (PORT datac (576:576:576) (603:603:603)) - (PORT datad (1136:1136:1136) (1126:1126:1126)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (165:165:165) (203:203:203)) - (PORT datad (1151:1151:1151) (1165:1165:1165)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (2531:2531:2531) (2628:2628:2628)) - (PORT datac (1599:1599:1599) (1628:1628:1628)) - (PORT datad (774:774:774) (770:770:770)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1454:1454:1454) (1517:1517:1517)) - (PORT datab (1859:1859:1859) (1914:1914:1914)) - (PORT datac (2041:2041:2041) (2037:2037:2037)) - (PORT datad (1626:1626:1626) (1655:1655:1655)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1634:1634:1634) (1685:1685:1685)) - (PORT datab (332:332:332) (347:347:347)) - (PORT datac (1716:1716:1716) (1692:1692:1692)) - (PORT datad (1470:1470:1470) (1561:1561:1561)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2173:2173:2173) (2248:2248:2248)) - (PORT datab (1040:1040:1040) (1047:1047:1047)) - (PORT datac (1429:1429:1429) (1486:1486:1486)) - (PORT datad (1837:1837:1837) (1881:1881:1881)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (829:829:829)) - (PORT datab (776:776:776) (773:773:773)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (1512:1512:1512) (1536:1536:1536)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (260:260:260)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (597:597:597) (630:630:630)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1096:1096:1096)) - (PORT datab (798:798:798) (783:783:783)) - (PORT datac (1086:1086:1086) (1106:1106:1106)) - (PORT datad (824:824:824) (829:829:829)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1421:1421:1421) (1415:1415:1415)) - (PORT datab (1026:1026:1026) (1006:1006:1006)) - (PORT datac (1592:1592:1592) (1604:1604:1604)) - (PORT datad (1088:1088:1088) (1092:1092:1092)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1419:1419:1419) (1413:1413:1413)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (1164:1164:1164) (1198:1198:1198)) - (PORT datad (1086:1086:1086) (1102:1102:1102)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datab (1458:1458:1458) (1516:1516:1516)) + (PORT datac (1186:1186:1186) (1233:1233:1233)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datac (967:967:967) (1045:1045:1045)) + (PORT datad (1919:1919:1919) (1976:1976:1976)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (318:318:318)) - (PORT datab (225:225:225) (270:270:270)) - (PORT datac (220:220:220) (272:272:272)) - (PORT datad (1331:1331:1331) (1314:1314:1314)) - (IOPATH dataa combout (265:265:265) (273:273:273)) + (PORT datac (1379:1379:1379) (1415:1415:1415)) + (PORT datad (1128:1128:1128) (1154:1154:1154)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1400:1400:1400)) + (PORT datab (666:666:666) (695:695:695)) + (PORT datac (2710:2710:2710) (2721:2721:2721)) + (PORT datad (1036:1036:1036) (1029:1029:1029)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -7568,29 +3421,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~2) (DELAY (ABSOLUTE - (PORT dataa (550:550:550) (559:559:559)) - (PORT datab (795:795:795) (770:770:770)) - (PORT datac (346:346:346) (351:351:351)) - (PORT datad (828:828:828) (850:850:850)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (551:551:551)) - (PORT datab (204:204:204) (241:241:241)) - (PORT datac (1034:1034:1034) (1034:1034:1034)) - (PORT datad (821:821:821) (839:839:839)) + (PORT dataa (1075:1075:1075) (1058:1058:1058)) + (PORT datab (628:628:628) (655:655:655)) + (PORT datac (1345:1345:1345) (1354:1354:1354)) + (PORT datad (1049:1049:1049) (1021:1021:1021)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -7600,15 +3437,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (INSTANCE z80_\|pla_decode_\|Equal33\~0) (DELAY (ABSOLUTE - (PORT dataa (1027:1027:1027) (1035:1035:1035)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (1152:1152:1152) (1242:1242:1242)) + (PORT datab (1528:1528:1528) (1687:1687:1687)) + (PORT datac (1116:1116:1116) (1198:1198:1198)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1167:1167:1167)) + (PORT datac (1369:1369:1369) (1397:1397:1397)) + (PORT datad (2392:2392:2392) (2397:2397:2397)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -7616,79 +3465,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1047:1047:1047)) - (PORT datab (1855:1855:1855) (1879:1879:1879)) - (PORT datac (1265:1265:1265) (1338:1338:1338)) - (PORT datad (1740:1740:1740) (1736:1736:1736)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1552:1552:1552) (1573:1573:1573)) - (PORT datab (609:609:609) (596:596:596)) - (PORT datac (1619:1619:1619) (1656:1656:1656)) - (PORT datad (973:973:973) (996:996:996)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1577:1577:1577)) - (PORT datab (609:609:609) (598:598:598)) - (PORT datac (1618:1618:1618) (1661:1661:1661)) - (PORT datad (971:971:971) (997:997:997)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1106:1106:1106)) - (PORT datab (828:828:828) (835:835:835)) - (PORT datac (875:875:875) (900:900:900)) - (PORT datad (871:871:871) (878:878:878)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (387:387:387)) - (PORT datab (882:882:882) (865:865:865)) - (PORT datac (546:546:546) (559:559:559)) - (PORT datad (203:203:203) (230:230:230)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT datac (1335:1335:1335) (1469:1469:1469)) + (PORT datad (1152:1152:1152) (1221:1221:1221)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -7696,31 +3477,65 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) (DELAY (ABSOLUTE - (PORT dataa (838:838:838) (861:861:861)) - (PORT datab (881:881:881) (872:872:872)) - (PORT datac (598:598:598) (609:609:609)) - (PORT datad (1089:1089:1089) (1111:1111:1111)) + (PORT dataa (1390:1390:1390) (1374:1374:1374)) + (PORT datab (1179:1179:1179) (1238:1238:1238)) + (PORT datac (565:565:565) (561:561:561)) + (PORT datad (1142:1142:1142) (1209:1209:1209)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1964:1964:1964) (2101:2101:2101)) + (PORT datab (1453:1453:1453) (1515:1515:1515)) + (PORT datac (819:819:819) (840:840:840)) + (PORT datad (1859:1859:1859) (1878:1878:1878)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (930:930:930)) - (PORT datab (906:906:906) (915:915:915)) - (PORT datac (1074:1074:1074) (1075:1075:1075)) - (PORT datad (909:909:909) (944:944:944)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1602:1602:1602) (1642:1642:1642)) + (PORT datab (896:896:896) (937:937:937)) + (PORT datac (621:621:621) (661:661:661)) + (PORT datad (806:806:806) (821:821:821)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -7728,217 +3543,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (609:609:609)) - (PORT datab (1357:1357:1357) (1357:1357:1357)) - (PORT datac (760:760:760) (823:823:823)) - (PORT datad (1761:1761:1761) (1803:1803:1803)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datac (1220:1220:1220) (1304:1304:1304)) - (PORT datad (2019:2019:2019) (2122:2122:2122)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (781:781:781)) - (PORT datab (195:195:195) (237:237:237)) - (PORT datac (1068:1068:1068) (1048:1048:1048)) - (PORT datad (587:587:587) (602:602:602)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (883:883:883)) - (PORT datab (1370:1370:1370) (1391:1391:1391)) - (PORT datac (1296:1296:1296) (1351:1351:1351)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (577:577:577)) - (PORT datab (208:208:208) (244:244:244)) - (PORT datac (763:763:763) (750:750:750)) - (PORT datad (723:723:723) (765:765:765)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1852:1852:1852) (1889:1889:1889)) - (PORT datab (559:559:559) (570:570:570)) - (PORT datac (767:767:767) (773:773:773)) - (PORT datad (646:646:646) (661:661:661)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1531:1531:1531) (1548:1548:1548)) - (PORT datab (1639:1639:1639) (1660:1660:1660)) - (PORT datac (833:833:833) (838:838:838)) - (PORT datad (645:645:645) (656:656:656)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (853:853:853)) - (PORT datab (1832:1832:1832) (1865:1865:1865)) - (PORT datac (1661:1661:1661) (1617:1617:1617)) - (PORT datad (1326:1326:1326) (1285:1285:1285)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (578:578:578)) - (PORT datab (683:683:683) (691:691:691)) - (PORT datac (1062:1062:1062) (1084:1084:1084)) - (PORT datad (745:745:745) (734:734:734)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (589:589:589)) - (PORT datab (684:684:684) (694:694:694)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (568:568:568) (569:569:569)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (337:337:337)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1532:1532:1532) (1507:1507:1507)) - (PORT datab (772:772:772) (767:767:767)) - (PORT datac (811:811:811) (824:824:824)) - (PORT datad (538:538:538) (542:542:542)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1527:1527:1527) (1544:1544:1544)) - (PORT datab (558:558:558) (567:567:567)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (1806:1806:1806) (1845:1845:1845)) + (PORT dataa (1088:1088:1088) (1070:1070:1070)) + (PORT datac (1120:1120:1120) (1142:1142:1142)) + (PORT datad (753:753:753) (730:730:730)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (789:789:789)) - (PORT datab (1028:1028:1028) (1044:1044:1044)) - (PORT datac (702:702:702) (740:740:740)) - (PORT datad (600:600:600) (603:603:603)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -7946,15 +3557,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (660:660:660) (715:715:715)) - (PORT datab (2176:2176:2176) (2234:2234:2234)) - (PORT datac (683:683:683) (756:756:756)) - (PORT datad (1698:1698:1698) (1692:1692:1692)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (1596:1596:1596) (1636:1636:1636)) + (PORT datab (893:893:893) (930:930:930)) + (PORT datac (617:617:617) (654:654:654)) + (PORT datad (802:802:802) (817:817:817)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -7962,13 +3573,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (574:574:574) (589:589:589)) - (PORT datac (329:329:329) (344:344:344)) - (PORT datad (761:761:761) (756:756:756)) + (PORT dataa (849:849:849) (825:825:825)) + (PORT datab (2321:2321:2321) (2344:2344:2344)) + (PORT datac (1386:1386:1386) (1401:1401:1401)) + (PORT datad (1086:1086:1086) (1072:1072:1072)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -7981,8 +3592,95 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) (DELAY (ABSOLUTE - (PORT datac (1948:1948:1948) (2007:2007:2007)) - (PORT datad (1523:1523:1523) (1632:1632:1632)) + (PORT dataa (1135:1135:1135) (1182:1182:1182)) + (PORT datad (2215:2215:2215) (2291:2291:2291)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1116:1116:1116)) + (PORT datab (396:396:396) (446:446:446)) + (PORT datad (394:394:394) (441:441:441)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1037:1037:1037)) + (PORT datab (1149:1149:1149) (1172:1172:1172)) + (PORT datad (299:299:299) (292:292:292)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (1237:1237:1237) (1257:1257:1257)) + (PORT datac (1386:1386:1386) (1396:1396:1396)) + (PORT datad (1085:1085:1085) (1074:1074:1074)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1475:1475:1475)) + (PORT datac (1626:1626:1626) (1654:1654:1654)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1208:1208:1208)) + (PORT datab (323:323:323) (347:347:347)) + (PORT datac (1426:1426:1426) (1561:1561:1561)) + (PORT datad (1301:1301:1301) (1340:1340:1340)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -7990,15 +3688,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (824:824:824) (808:808:808)) - (PORT datad (341:341:341) (342:342:342)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1672:1672:1672) (1707:1707:1707)) + (PORT datab (1812:1812:1812) (1836:1836:1836)) + (PORT datac (1322:1322:1322) (1359:1359:1359)) + (PORT datad (606:606:606) (627:627:627)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8006,13 +3704,398 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~3) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (344:344:344)) - (PORT datab (574:574:574) (558:558:558)) - (PORT datac (545:545:545) (536:536:536)) - (PORT datad (761:761:761) (721:721:721)) + (PORT dataa (1315:1315:1315) (1324:1324:1324)) + (PORT datab (1136:1136:1136) (1130:1130:1130)) + (PORT datac (1066:1066:1066) (1065:1065:1065)) + (PORT datad (767:767:767) (763:763:763)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (912:912:912)) + (PORT datab (1329:1329:1329) (1365:1365:1365)) + (PORT datac (1350:1350:1350) (1360:1360:1360)) + (PORT datad (955:955:955) (1004:1004:1004)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1529:1529:1529)) + (PORT datab (1360:1360:1360) (1494:1494:1494)) + (PORT datad (1156:1156:1156) (1226:1226:1226)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2388:2388:2388) (2402:2402:2402)) + (PORT datab (1366:1366:1366) (1394:1394:1394)) + (PORT datac (1158:1158:1158) (1195:1195:1195)) + (PORT datad (1231:1231:1231) (1267:1267:1267)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (675:675:675)) + (PORT datab (1036:1036:1036) (1108:1108:1108)) + (PORT datac (1015:1015:1015) (1074:1074:1074)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (850:850:850)) + (PORT datab (1004:1004:1004) (1087:1087:1087)) + (PORT datac (1551:1551:1551) (1590:1590:1590)) + (PORT datad (835:835:835) (850:850:850)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT datab (1309:1309:1309) (1327:1327:1327)) + (PORT datac (190:190:190) (233:233:233)) + (PORT datad (907:907:907) (948:948:948)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1225:1225:1225)) + (PORT datab (217:217:217) (259:259:259)) + (PORT datac (1280:1280:1280) (1299:1299:1299)) + (PORT datad (907:907:907) (948:948:948)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1776:1776:1776) (1767:1767:1767)) + (PORT datab (1118:1118:1118) (1168:1168:1168)) + (PORT datad (850:850:850) (864:864:864)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1157:1157:1157)) + (PORT datac (1105:1105:1105) (1134:1134:1134)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1542:1542:1542)) + (PORT datab (234:234:234) (299:299:299)) + (PORT datac (641:641:641) (698:698:698)) + (PORT datad (230:230:230) (270:270:270)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (530:530:530)) + (PORT datab (618:618:618) (648:648:648)) + (PORT datac (2405:2405:2405) (2439:2439:2439)) + (PORT datad (1244:1244:1244) (1248:1248:1248)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (335:335:335)) + (PORT datac (1082:1082:1082) (1117:1117:1117)) + (PORT datad (895:895:895) (937:937:937)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (254:254:254)) + (PORT datab (2743:2743:2743) (2758:2758:2758)) + (PORT datac (1092:1092:1092) (1105:1105:1105)) + (PORT datad (629:629:629) (656:656:656)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1100:1100:1100)) + (PORT datab (1235:1235:1235) (1263:1263:1263)) + (PORT datac (502:502:502) (496:496:496)) + (PORT datad (583:583:583) (608:608:608)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1358:1358:1358)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1027:1027:1027)) + (PORT datac (1501:1501:1501) (1602:1602:1602)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~3) + (DELAY + (ABSOLUTE + (PORT datac (1103:1103:1103) (1153:1153:1153)) + (PORT datad (1130:1130:1130) (1193:1193:1193)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (1318:1318:1318) (1332:1332:1332)) + (PORT datad (1127:1127:1127) (1160:1160:1160)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1340:1340:1340) (1384:1384:1384)) + (PORT datad (1498:1498:1498) (1553:1553:1553)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (1458:1458:1458) (1515:1515:1515)) + (PORT datac (1297:1297:1297) (1331:1331:1331)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (971:971:971)) + (PORT datab (1110:1110:1110) (1104:1104:1104)) + (PORT datac (1298:1298:1298) (1302:1302:1302)) + (PORT datad (1697:1697:1697) (1715:1715:1715)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1108:1108:1108)) + (PORT datab (812:812:812) (817:817:817)) + (PORT datac (1667:1667:1667) (1708:1708:1708)) + (PORT datad (1201:1201:1201) (1228:1228:1228)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1253:1253:1253)) + (PORT datab (651:651:651) (692:692:692)) + (PORT datad (619:619:619) (662:662:662)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1027:1027:1027)) + (PORT datab (1158:1158:1158) (1177:1177:1177)) + (PORT datac (1493:1493:1493) (1600:1600:1600)) + (PORT datad (1848:1848:1848) (1827:1827:1827)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1430:1430:1430)) + (PORT datab (818:818:818) (826:826:826)) + (PORT datac (1381:1381:1381) (1396:1396:1396)) + (PORT datad (1622:1622:1622) (1640:1640:1640)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -8022,13 +4105,399 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (INSTANCE z80_\|execute_\|ixy_d\~9) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (317:317:317)) - (PORT datab (1626:1626:1626) (1629:1629:1629)) - (PORT datac (222:222:222) (275:275:275)) - (PORT datad (200:200:200) (240:240:240)) + (PORT dataa (881:881:881) (893:893:893)) + (PORT datab (651:651:651) (664:664:664)) + (PORT datac (1563:1563:1563) (1595:1595:1595)) + (PORT datad (502:502:502) (499:499:499)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (602:602:602)) + (PORT datab (546:546:546) (557:557:557)) + (PORT datac (568:568:568) (565:565:565)) + (PORT datad (203:203:203) (239:239:239)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (533:533:533)) + (PORT datab (601:601:601) (591:591:591)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (785:785:785) (769:769:769)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (996:996:996)) + (PORT datac (1873:1873:1873) (1910:1910:1910)) + (PORT datad (862:862:862) (902:902:902)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (764:764:764)) + (PORT datab (1202:1202:1202) (1259:1259:1259)) + (PORT datac (599:599:599) (644:644:644)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1012:1012:1012)) + (PORT datab (524:524:524) (526:526:526)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2141:2141:2141) (2156:2156:2156)) + (PORT datab (1233:1233:1233) (1262:1262:1262)) + (PORT datac (1066:1066:1066) (1070:1070:1070)) + (PORT datad (1686:1686:1686) (1802:1802:1802)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1358:1358:1358)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1029:1029:1029)) + (PORT datac (1507:1507:1507) (1608:1608:1608)) + (PORT datad (919:919:919) (976:976:976)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1263:1263:1263)) + (PORT datab (821:821:821) (827:827:827)) + (PORT datac (402:402:402) (457:457:457)) + (PORT datad (1084:1084:1084) (1097:1097:1097)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1602:1602:1602) (1642:1642:1642)) + (PORT datab (650:650:650) (690:690:690)) + (PORT datac (867:867:867) (908:908:908)) + (PORT datad (2432:2432:2432) (2464:2464:2464)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1236:1236:1236)) + (PORT datab (1159:1159:1159) (1247:1247:1247)) + (PORT datac (1506:1506:1506) (1668:1668:1668)) + (PORT datad (368:368:368) (384:384:384)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1498:1498:1498)) + (PORT datab (1460:1460:1460) (1511:1511:1511)) + (PORT datac (760:760:760) (751:751:751)) + (PORT datad (975:975:975) (967:967:967)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1287:1287:1287)) + (PORT datab (798:798:798) (777:777:777)) + (PORT datac (664:664:664) (724:724:724)) + (PORT datad (1130:1130:1130) (1193:1193:1193)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (641:641:641)) + (PORT datab (798:798:798) (777:777:777)) + (PORT datac (1288:1288:1288) (1286:1286:1286)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1629:1629:1629) (1671:1671:1671)) + (PORT datab (1580:1580:1580) (1615:1615:1615)) + (PORT datac (916:916:916) (986:986:986)) + (PORT datad (778:778:778) (775:775:775)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (837:837:837) (871:871:871)) + (PORT datad (1720:1720:1720) (1800:1800:1800)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (551:551:551)) + (PORT datab (2735:2735:2735) (2748:2748:2748)) + (PORT datac (1269:1269:1269) (1252:1252:1252)) + (PORT datad (632:632:632) (659:659:659)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1644:1644:1644) (1657:1657:1657)) + (PORT datad (1464:1464:1464) (1520:1520:1520)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (641:641:641)) + (PORT datab (532:532:532) (539:539:539)) + (PORT datac (804:804:804) (817:817:817)) + (PORT datad (1306:1306:1306) (1310:1310:1310)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1199:1199:1199)) + (PORT datab (876:876:876) (868:868:868)) + (PORT datac (787:787:787) (787:787:787)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1265:1265:1265)) + (PORT datab (819:819:819) (825:825:825)) + (PORT datac (402:402:402) (459:459:459)) + (PORT datad (1088:1088:1088) (1098:1098:1098)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (981:981:981)) + (PORT datac (652:652:652) (715:715:715)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (2023:2023:2023)) + (PORT datab (1456:1456:1456) (1506:1506:1506)) + (PORT datac (1933:1933:1933) (2047:2047:2047)) + (PORT datad (922:922:922) (977:977:977)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1259:1259:1259)) + (PORT datab (255:255:255) (336:336:336)) + (PORT datac (1078:1078:1078) (1065:1065:1065)) + (PORT datad (1082:1082:1082) (1091:1091:1091)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1067:1067:1067)) + (PORT datab (1350:1350:1350) (1383:1383:1383)) + (PORT datac (1582:1582:1582) (1557:1557:1557)) + (PORT datad (354:354:354) (365:365:365)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -8038,183 +4507,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) (DELAY (ABSOLUTE (PORT dataa (864:864:864) (905:905:905)) - (PORT datab (894:894:894) (914:914:914)) - (PORT datac (1746:1746:1746) (1751:1751:1751)) - (PORT datad (596:596:596) (596:596:596)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (939:939:939)) - (PORT datab (1304:1304:1304) (1379:1379:1379)) - (PORT datac (872:872:872) (925:925:925)) - (PORT datad (759:759:759) (739:739:739)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (632:632:632)) - (PORT datab (1488:1488:1488) (1495:1495:1495)) - (PORT datac (1185:1185:1185) (1218:1218:1218)) - (PORT datad (1062:1062:1062) (1042:1042:1042)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (1785:1785:1785) (1786:1786:1786)) - (PORT datad (1904:1904:1904) (1949:1949:1949)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (238:238:238)) - (PORT datab (1368:1368:1368) (1427:1427:1427)) - (PORT datac (1809:1809:1809) (1809:1809:1809)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1822:1822:1822) (1823:1823:1823)) - (PORT datab (1941:1941:1941) (1986:1986:1986)) - (PORT datac (1342:1342:1342) (1397:1397:1397)) - (PORT datad (194:194:194) (224:224:224)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1836:1836:1836) (1840:1840:1840)) - (PORT datab (1121:1121:1121) (1123:1123:1123)) - (PORT datac (1593:1593:1593) (1593:1593:1593)) - (PORT datad (868:868:868) (891:891:891)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1373:1373:1373)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1279:1279:1279) (1272:1272:1272)) - (PORT datad (569:569:569) (579:579:579)) - (IOPATH dataa combout (299:299:299) (304:304:304)) + (PORT datab (1451:1451:1451) (1473:1473:1473)) + (PORT datac (803:803:803) (811:811:811)) + (PORT datad (840:840:840) (873:873:873)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1074:1074:1074)) - (PORT datab (1488:1488:1488) (1495:1495:1495)) - (PORT datac (823:823:823) (828:828:828)) - (PORT datad (832:832:832) (840:840:840)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (180:180:180) (214:214:214)) - (PORT datac (161:161:161) (195:195:195)) - (PORT datad (192:192:192) (219:219:219)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT datab (1945:1945:1945) (1990:1990:1990)) - (PORT datac (1338:1338:1338) (1396:1396:1396)) - (PORT datad (191:191:191) (221:221:221)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (1374:1374:1374) (1413:1413:1413)) - (PORT datac (1950:1950:1950) (2007:2007:2007)) - (PORT datad (1528:1528:1528) (1633:1633:1633)) - (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8222,169 +4523,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (INSTANCE z80_\|execute_\|ctl_mRead\~34) (DELAY (ABSOLUTE - (PORT dataa (884:884:884) (885:885:885)) - (PORT datab (1006:1006:1006) (1006:1006:1006)) - (PORT datac (594:594:594) (616:616:616)) - (PORT datad (577:577:577) (576:576:576)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (555:555:555)) - (PORT datab (852:852:852) (849:849:849)) - (PORT datac (543:543:543) (526:526:526)) - (PORT datad (1499:1499:1499) (1446:1446:1446)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (2070:2070:2070) (2090:2090:2090)) - (PORT datab (1483:1483:1483) (1557:1557:1557)) - (PORT datac (788:788:788) (785:785:785)) - (PORT datad (808:808:808) (809:809:809)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (630:630:630)) - (PORT datab (812:812:812) (822:822:822)) - (PORT datac (1571:1571:1571) (1570:1570:1570)) - (PORT datad (1391:1391:1391) (1374:1374:1374)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1096:1096:1096)) - (PORT datab (584:584:584) (589:589:589)) - (PORT datac (605:605:605) (624:624:624)) - (PORT datad (1089:1089:1089) (1073:1073:1073)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1135:1135:1135) (1172:1172:1172)) - (PORT datab (905:905:905) (913:913:913)) - (PORT datac (1553:1553:1553) (1540:1540:1540)) - (PORT datad (1274:1274:1274) (1284:1284:1284)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (230:230:230)) - (PORT datab (929:929:929) (974:974:974)) - (PORT datac (1648:1648:1648) (1671:1671:1671)) - (PORT datad (1274:1274:1274) (1284:1284:1284)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (900:900:900)) - (PORT datab (879:879:879) (878:878:878)) - (PORT datad (831:831:831) (859:859:859)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (914:914:914) (938:938:938)) - (PORT datac (748:748:748) (722:722:722)) - (PORT datad (1295:1295:1295) (1274:1274:1274)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1634:1634:1634) (1680:1680:1680)) - (PORT datab (1512:1512:1512) (1598:1598:1598)) - (PORT datad (1743:1743:1743) (1723:1723:1723)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1041:1041:1041)) - (PORT datac (1611:1611:1611) (1672:1672:1672)) - (PORT datad (587:587:587) (619:619:619)) + (PORT dataa (1151:1151:1151) (1237:1237:1237)) + (PORT datab (1162:1162:1162) (1248:1248:1248)) + (PORT datac (1508:1508:1508) (1667:1667:1667)) + (PORT datad (368:368:368) (383:383:383)) (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8392,15 +4539,193 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1047:1047:1047)) - (PORT datab (850:850:850) (891:891:891)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (529:529:529) (516:516:516)) + (PORT dataa (1175:1175:1175) (1246:1246:1246)) + (PORT datab (1463:1463:1463) (1552:1552:1552)) + (PORT datac (1348:1348:1348) (1339:1339:1339)) + (PORT datad (179:179:179) (209:209:209)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (365:365:365)) + (PORT datab (578:578:578) (572:572:572)) + (PORT datac (591:591:591) (621:621:621)) + (PORT datad (820:820:820) (811:811:811)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT datab (680:680:680) (734:734:734)) + (PORT datad (360:360:360) (370:370:370)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1179:1179:1179)) + (PORT datab (1151:1151:1151) (1183:1183:1183)) + (PORT datad (1138:1138:1138) (1175:1175:1175)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1138:1138:1138)) + (PORT datac (1907:1907:1907) (2026:2026:2026)) + (PORT datad (1588:1588:1588) (1631:1631:1631)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1659:1659:1659)) + (PORT datab (1160:1160:1160) (1207:1207:1207)) + (PORT datad (1590:1590:1590) (1607:1607:1607)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1634:1634:1634) (1659:1659:1659)) + (PORT datab (1148:1148:1148) (1171:1171:1171)) + (PORT datac (1906:1906:1906) (1934:1934:1934)) + (PORT datad (1593:1593:1593) (1615:1615:1615)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1610:1610:1610)) + (PORT datab (224:224:224) (262:262:262)) + (PORT datac (181:181:181) (215:215:215)) + (PORT datad (185:185:185) (210:210:210)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (340:340:340)) + (PORT datab (1630:1630:1630) (1649:1649:1649)) + (PORT datac (1605:1605:1605) (1625:1625:1625)) + (PORT datad (1138:1138:1138) (1178:1178:1178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1630:1630:1630) (1657:1657:1657)) + (PORT datab (607:607:607) (601:601:601)) + (PORT datac (1901:1901:1901) (1929:1929:1929)) + (PORT datad (1587:1587:1587) (1609:1609:1609)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1178:1178:1178)) + (PORT datab (1150:1150:1150) (1182:1182:1182)) + (PORT datad (1138:1138:1138) (1175:1175:1175)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (868:868:868) (868:868:868)) + (PORT datac (744:744:744) (727:727:727)) + (PORT datad (1136:1136:1136) (1157:1157:1157)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (396:396:396)) + (PORT datab (346:346:346) (362:362:362)) + (PORT datac (534:534:534) (528:528:528)) + (PORT datad (866:866:866) (897:897:897)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8408,15 +4733,388 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (INSTANCE z80_\|pla_decode_\|Equal29\~0) (DELAY (ABSOLUTE - (PORT dataa (1768:1768:1768) (1796:1796:1796)) - (PORT datab (1399:1399:1399) (1420:1420:1420)) - (PORT datac (1479:1479:1479) (1568:1568:1568)) - (PORT datad (803:803:803) (795:795:795)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (579:579:579) (584:584:584)) + (PORT datab (2737:2737:2737) (2751:2751:2751)) + (PORT datac (833:833:833) (873:873:873)) + (PORT datad (633:633:633) (656:656:656)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1119:1119:1119)) + (PORT datab (2736:2736:2736) (2746:2746:2746)) + (PORT datac (539:539:539) (545:545:545)) + (PORT datad (634:634:634) (664:664:664)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1236:1236:1236)) + (PORT datab (1161:1161:1161) (1248:1248:1248)) + (PORT datac (1507:1507:1507) (1667:1667:1667)) + (PORT datad (316:316:316) (329:329:329)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (820:820:820)) + (PORT datab (236:236:236) (302:302:302)) + (PORT datac (640:640:640) (702:702:702)) + (PORT datad (237:237:237) (280:280:280)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1552:1552:1552) (1539:1539:1539)) + (PORT datab (238:238:238) (300:300:300)) + (PORT datac (641:641:641) (697:697:697)) + (PORT datad (237:237:237) (274:274:274)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (669:669:669)) + (PORT datab (236:236:236) (297:297:297)) + (PORT datac (642:642:642) (701:701:701)) + (PORT datad (238:238:238) (280:280:280)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (804:804:804)) + (PORT datab (789:789:789) (800:800:800)) + (PORT datac (563:563:563) (587:587:587)) + (PORT datad (600:600:600) (617:617:617)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (551:551:551)) + (PORT datab (2736:2736:2736) (2750:2750:2750)) + (PORT datac (1270:1270:1270) (1254:1254:1254)) + (PORT datad (627:627:627) (664:664:664)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1460:1460:1460)) + (PORT datab (1302:1302:1302) (1285:1285:1285)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1247:1247:1247) (1206:1206:1206)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1965:1965:1965) (2034:2034:2034)) + (PORT datad (890:890:890) (939:939:939)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1717:1717:1717) (1692:1692:1692)) + (PORT datab (1168:1168:1168) (1184:1184:1184)) + (PORT datac (1516:1516:1516) (1495:1495:1495)) + (PORT datad (1059:1059:1059) (1034:1034:1034)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (360:360:360)) + (PORT datab (1171:1171:1171) (1184:1184:1184)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1936:1936:1936) (2026:2026:2026)) + (PORT datab (2440:2440:2440) (2484:2484:2484)) + (PORT datac (1762:1762:1762) (1788:1788:1788)) + (PORT datad (182:182:182) (205:205:205)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (399:399:399)) + (PORT datab (870:870:870) (874:874:874)) + (PORT datac (1330:1330:1330) (1349:1349:1349)) + (PORT datad (330:330:330) (339:339:339)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (1096:1096:1096) (1070:1070:1070)) + (PORT datac (1331:1331:1331) (1349:1349:1349)) + (PORT datad (196:196:196) (219:219:219)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1167:1167:1167)) + (PORT datab (367:367:367) (425:425:425)) + (PORT datad (897:897:897) (936:936:936)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT datab (1127:1127:1127) (1195:1195:1195)) + (PORT datad (1879:1879:1879) (1925:1925:1925)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (614:614:614)) + (PORT datab (245:245:245) (289:289:289)) + (PORT datac (1784:1784:1784) (1757:1757:1757)) + (PORT datad (819:819:819) (828:828:828)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M5T3_9) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (659:659:659)) + (PORT datab (1866:1866:1866) (1900:1900:1900)) + (PORT datad (1463:1463:1463) (1510:1510:1510)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1457:1457:1457)) + (PORT datab (1355:1355:1355) (1380:1380:1380)) + (PORT datac (788:788:788) (771:771:771)) + (PORT datad (297:297:297) (295:295:295)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1242:1242:1242)) + (PORT datab (1353:1353:1353) (1382:1382:1382)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (597:597:597) (617:617:617)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1263:1263:1263)) + (PORT datab (821:821:821) (830:830:830)) + (PORT datac (402:402:402) (457:457:457)) + (PORT datad (1085:1085:1085) (1098:1098:1098)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1027:1027:1027)) + (PORT datab (1162:1162:1162) (1179:1179:1179)) + (PORT datac (1496:1496:1496) (1594:1594:1594)) + (PORT datad (1849:1849:1849) (1831:1831:1831)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (862:862:862)) + (PORT datab (697:697:697) (759:759:759)) + (PORT datac (624:624:624) (694:694:694)) + (PORT datad (236:236:236) (274:274:274)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8427,10 +5125,312 @@ (INSTANCE z80_\|execute_\|ctl_state_alu\~7) (DELAY (ABSOLUTE - (PORT dataa (1342:1342:1342) (1352:1352:1352)) - (PORT datab (1149:1149:1149) (1160:1160:1160)) - (PORT datac (861:861:861) (897:897:897)) - (PORT datad (777:777:777) (766:766:766)) + (PORT dataa (1588:1588:1588) (1601:1601:1601)) + (PORT datab (1119:1119:1119) (1119:1119:1119)) + (PORT datac (1046:1046:1046) (1038:1038:1038)) + (PORT datad (220:220:220) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1016:1016:1016)) + (PORT datab (1965:1965:1965) (1929:1929:1929)) + (PORT datac (534:534:534) (525:525:525)) + (PORT datad (220:220:220) (254:254:254)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1244:1244:1244)) + (PORT datab (1153:1153:1153) (1238:1238:1238)) + (PORT datac (1500:1500:1500) (1655:1655:1655)) + (PORT datad (369:369:369) (389:389:389)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1239:1239:1239)) + (PORT datab (1158:1158:1158) (1245:1245:1245)) + (PORT datac (1504:1504:1504) (1666:1666:1666)) + (PORT datad (370:370:370) (389:389:389)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (881:881:881)) + (PORT datab (1097:1097:1097) (1091:1091:1091)) + (PORT datac (967:967:967) (1047:1047:1047)) + (PORT datad (1920:1920:1920) (1977:1977:1977)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (847:847:847)) + (PORT datab (818:818:818) (825:825:825)) + (PORT datac (1384:1384:1384) (1396:1396:1396)) + (PORT datad (1621:1621:1621) (1643:1643:1643)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1068:1068:1068)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1202:1202:1202) (1182:1182:1182)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1255:1255:1255)) + (PORT datab (254:254:254) (334:334:334)) + (PORT datac (1079:1079:1079) (1061:1061:1061)) + (PORT datad (1082:1082:1082) (1091:1091:1091)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1523:1523:1523)) + (PORT datab (1991:1991:1991) (2078:2078:2078)) + (PORT datac (1035:1035:1035) (1035:1035:1035)) + (PORT datad (1028:1028:1028) (1023:1023:1023)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1117:1117:1117)) + (PORT datab (815:815:815) (840:840:840)) + (PORT datac (860:860:860) (876:876:876)) + (PORT datad (1055:1055:1055) (1060:1060:1060)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (866:866:866)) + (PORT datab (259:259:259) (310:310:310)) + (PORT datac (624:624:624) (698:698:698)) + (PORT datad (1284:1284:1284) (1291:1291:1291)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2029:2029:2029) (2077:2077:2077)) + (PORT datab (1326:1326:1326) (1292:1292:1292)) + (PORT datac (1394:1394:1394) (1454:1454:1454)) + (PORT datad (843:843:843) (829:829:829)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1266:1266:1266)) + (PORT datab (258:258:258) (339:339:339)) + (PORT datac (1078:1078:1078) (1060:1060:1060)) + (PORT datad (1089:1089:1089) (1099:1099:1099)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1809:1809:1809) (1807:1807:1807)) + (PORT datab (878:878:878) (877:877:877)) + (PORT datac (1394:1394:1394) (1452:1452:1452)) + (PORT datad (1985:1985:1985) (2032:2032:2032)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (617:617:617)) + (PORT datab (837:837:837) (844:844:844)) + (PORT datac (865:865:865) (864:864:864)) + (PORT datad (825:825:825) (818:818:818)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (726:726:726)) + (PORT datac (1686:1686:1686) (1832:1832:1832)) + (PORT datad (1593:1593:1593) (1638:1638:1638)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (370:370:370)) + (PORT datab (234:234:234) (299:299:299)) + (PORT datac (642:642:642) (698:698:698)) + (PORT datad (230:230:230) (271:271:271)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1199:1199:1199)) + (PORT datab (1154:1154:1154) (1154:1154:1154)) + (PORT datac (1884:1884:1884) (1881:1881:1881)) + (PORT datad (1299:1299:1299) (1279:1279:1279)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (906:906:906)) + (PORT datab (1324:1324:1324) (1310:1310:1310)) + (PORT datac (1321:1321:1321) (1328:1328:1328)) + (PORT datad (1134:1134:1134) (1154:1154:1154)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -8440,63 +5440,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (268:268:268)) - (PORT datab (1826:1826:1826) (1856:1856:1856)) - (PORT datac (1304:1304:1304) (1316:1316:1316)) - (PORT datad (1395:1395:1395) (1471:1471:1471)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1307:1307:1307)) - (PORT datab (1432:1432:1432) (1503:1503:1503)) - (PORT datac (2254:2254:2254) (2339:2339:2339)) - (PORT datad (1129:1129:1129) (1214:1214:1214)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1534:1534:1534) (1555:1555:1555)) - (PORT datab (857:857:857) (869:869:869)) - (PORT datac (2383:2383:2383) (2320:2320:2320)) - (PORT datad (709:709:709) (740:740:740)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1347:1347:1347) (1360:1360:1360)) - (PORT datab (560:560:560) (550:550:550)) - (PORT datac (1047:1047:1047) (1032:1032:1032)) - (PORT datad (545:545:545) (534:534:534)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (578:578:578) (584:584:584)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (182:182:182) (218:218:218)) + (PORT datad (660:660:660) (699:699:699)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8504,47 +5456,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) (DELAY (ABSOLUTE - (PORT dataa (1343:1343:1343) (1355:1355:1355)) - (PORT datab (1314:1314:1314) (1319:1319:1319)) - (PORT datac (858:858:858) (899:899:899)) - (PORT datad (1306:1306:1306) (1286:1286:1286)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1710:1710:1710)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (729:729:729)) - (PORT datab (1107:1107:1107) (1092:1092:1092)) - (PORT datac (1111:1111:1111) (1129:1129:1129)) - (PORT datad (821:821:821) (844:844:844)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1324:1324:1324) (1309:1309:1309)) + (PORT datac (671:671:671) (734:734:734)) + (PORT datad (1657:1657:1657) (1700:1700:1700)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8552,13 +5470,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) (DELAY (ABSOLUTE - (PORT dataa (754:754:754) (808:808:808)) - (PORT datab (1731:1731:1731) (1808:1808:1808)) - (PORT datac (307:307:307) (314:314:314)) - (PORT datad (1562:1562:1562) (1567:1567:1567)) + (PORT dataa (1745:1745:1745) (1787:1787:1787)) + (PORT datab (853:853:853) (866:866:866)) + (PORT datac (1582:1582:1582) (1590:1590:1590)) + (PORT datad (184:184:184) (210:210:210)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (602:602:602) (638:638:638)) + (PORT datac (1016:1016:1016) (1016:1016:1016)) + (PORT datad (303:303:303) (306:306:306)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (897:897:897) (916:916:916)) + (PORT datac (297:297:297) (307:307:307)) + (PORT datad (546:546:546) (539:539:539)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1056:1056:1056)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (747:747:747) (735:735:735)) + (PORT datad (1018:1018:1018) (1001:1001:1001)) (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -8571,13 +5537,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (2017:2017:2017) (2129:2129:2129)) - (PORT datab (1296:1296:1296) (1292:1292:1292)) - (PORT datac (1321:1321:1321) (1303:1303:1303)) - (PORT datad (2101:2101:2101) (2138:2138:2138)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (1639:1639:1639) (1674:1674:1674)) + (PORT datab (874:874:874) (868:868:868)) + (PORT datac (1645:1645:1645) (1679:1679:1679)) + (PORT datad (1885:1885:1885) (1920:1920:1920)) + (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -8587,90 +5553,42 @@ (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (1202:1202:1202) (1233:1233:1233)) - (PORT datab (1123:1123:1123) (1125:1125:1125)) - (PORT datac (601:601:601) (639:639:639)) - (PORT datad (1057:1057:1057) (1055:1055:1055)) + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (1285:1285:1285) (1256:1256:1256)) + (PORT datac (781:781:781) (780:780:780)) + (PORT datad (1377:1377:1377) (1412:1412:1412)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1276:1276:1276)) + (PORT datab (1351:1351:1351) (1346:1346:1346)) + (PORT datac (169:169:169) (209:209:209)) + (PORT datad (1372:1372:1372) (1409:1409:1409)) (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) (DELAY (ABSOLUTE - (PORT dataa (1351:1351:1351) (1349:1349:1349)) - (PORT datab (1102:1102:1102) (1134:1134:1134)) - (PORT datac (604:604:604) (640:640:640)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1977:1977:1977) (2042:2042:2042)) - (PORT datab (1561:1561:1561) (1668:1668:1668)) - (PORT datac (1066:1066:1066) (1088:1088:1088)) - (PORT datad (1804:1804:1804) (1792:1792:1792)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (803:803:803)) - (PORT datab (852:852:852) (870:870:870)) - (PORT datac (518:518:518) (524:524:524)) - (PORT datad (1017:1017:1017) (988:988:988)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (821:821:821)) - (PORT datab (958:958:958) (983:983:983)) - (PORT datac (1085:1085:1085) (1070:1070:1070)) - (PORT datad (590:590:590) (592:592:592)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (609:609:609)) - (PORT datab (617:617:617) (625:625:625)) - (PORT datac (588:588:588) (602:602:602)) - (PORT datad (1054:1054:1054) (1044:1044:1044)) + (PORT dataa (1643:1643:1643) (1678:1678:1678)) + (PORT datab (1286:1286:1286) (1261:1261:1261)) + (PORT datac (846:846:846) (837:837:837)) + (PORT datad (937:937:937) (967:967:967)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -8680,15 +5598,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (609:609:609)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1084:1084:1084) (1072:1072:1072)) - (PORT datad (523:523:523) (518:518:518)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1308:1308:1308) (1276:1276:1276)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (777:777:777) (778:778:778)) + (PORT datad (938:938:938) (969:969:969)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8696,31 +5614,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) (DELAY (ABSOLUTE - (PORT dataa (1221:1221:1221) (1271:1271:1271)) - (PORT datab (1422:1422:1422) (1405:1405:1405)) - (PORT datac (1285:1285:1285) (1393:1393:1393)) - (PORT datad (2356:2356:2356) (2373:2373:2373)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1328:1328:1328) (1330:1330:1330)) + (PORT datab (878:878:878) (877:877:877)) + (PORT datac (783:783:783) (780:780:780)) + (PORT datad (1665:1665:1665) (1698:1698:1698)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (1382:1382:1382) (1372:1372:1372)) - (PORT datab (1390:1390:1390) (1428:1428:1428)) - (PORT datac (1530:1530:1530) (1519:1519:1519)) - (PORT datad (1377:1377:1377) (1442:1442:1442)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (567:567:567) (585:585:585)) + (PORT datab (646:646:646) (678:678:678)) + (PORT datac (1116:1116:1116) (1130:1130:1130)) + (PORT datad (1545:1545:1545) (1538:1538:1538)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8728,63 +5646,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (1154:1154:1154) (1165:1165:1165)) - (PORT datab (609:609:609) (627:627:627)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (622:622:622) (642:642:642)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datab (804:804:804) (801:801:801)) + (PORT datac (738:738:738) (731:731:731)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2147:2147:2147) (2204:2204:2204)) - (PORT datab (2061:2061:2061) (2084:2084:2084)) - (PORT datac (1284:1284:1284) (1392:1392:1392)) - (PORT datad (1081:1081:1081) (1077:1077:1077)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1609:1609:1609) (1650:1650:1650)) - (PORT datab (1513:1513:1513) (1636:1636:1636)) - (PORT datac (952:952:952) (992:992:992)) - (PORT datad (1661:1661:1661) (1721:1721:1721)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1374:1374:1374)) - (PORT datab (1056:1056:1056) (1054:1054:1054)) - (PORT datac (753:753:753) (736:736:736)) - (PORT datad (1382:1382:1382) (1447:1447:1447)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8792,15 +5660,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (979:979:979) (1025:1025:1025)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (1569:1569:1569) (1607:1607:1607)) - (PORT datad (1411:1411:1411) (1450:1450:1450)) + (PORT dataa (1992:1992:1992) (2017:2017:2017)) + (PORT datab (1969:1969:1969) (2038:2038:2038)) + (PORT datac (876:876:876) (904:904:904)) + (PORT datad (1218:1218:1218) (1329:1329:1329)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (787:787:787)) + (PORT datab (966:966:966) (944:944:944)) + (PORT datac (806:806:806) (828:828:828)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (764:764:764)) + (PORT datab (852:852:852) (871:871:871)) + (PORT datac (572:572:572) (599:599:599)) + (PORT datad (517:517:517) (511:511:511)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8808,13 +5708,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~2) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) (DELAY (ABSOLUTE - (PORT dataa (610:610:610) (614:614:614)) - (PORT datac (2053:2053:2053) (2069:2069:2069)) - (PORT datad (1559:1559:1559) (1577:1577:1577)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (887:887:887) (947:947:947)) + (PORT datab (1023:1023:1023) (979:979:979)) + (PORT datac (1296:1296:1296) (1311:1311:1311)) + (PORT datad (1848:1848:1848) (1830:1830:1830)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1018:1018:1018)) + (PORT datab (841:841:841) (861:861:861)) + (PORT datac (561:561:561) (585:585:585)) + (PORT datad (596:596:596) (615:615:615)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1048:1048:1048)) + (PORT datab (796:796:796) (808:808:808)) + (PORT datac (603:603:603) (637:637:637)) + (PORT datad (1293:1293:1293) (1294:1294:1294)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1236:1236:1236)) + (PORT datab (1160:1160:1160) (1247:1247:1247)) + (PORT datac (1507:1507:1507) (1666:1666:1666)) + (PORT datad (316:316:316) (329:329:329)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1071:1071:1071)) + (PORT datab (1033:1033:1033) (1022:1022:1022)) + (PORT datac (604:604:604) (640:640:640)) + (PORT datad (553:553:553) (554:554:554)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (330:330:330)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (606:606:606) (638:638:638)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8825,28 +5807,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (598:598:598) (596:596:596)) - (PORT datab (1380:1380:1380) (1363:1363:1363)) - (PORT datac (1119:1119:1119) (1127:1127:1127)) - (PORT datad (523:523:523) (523:523:523)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1745:1745:1745)) - (PORT datab (832:832:832) (818:818:818)) - (PORT datac (797:797:797) (784:784:784)) - (PORT datad (1408:1408:1408) (1377:1377:1377)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1188:1188:1188) (1232:1232:1232)) + (PORT datab (368:368:368) (379:379:379)) + (PORT datac (1024:1024:1024) (1031:1031:1031)) + (PORT datad (1300:1300:1300) (1291:1291:1291)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -8854,13 +5820,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) (DELAY (ABSOLUTE - (PORT dataa (1023:1023:1023) (1015:1015:1015)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1119:1119:1119) (1127:1127:1127)) - (PORT datad (850:850:850) (871:871:871)) + (PORT dataa (863:863:863) (866:866:866)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1330:1330:1330) (1404:1404:1404)) + (PORT datad (1030:1030:1030) (1039:1039:1039)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1635:1635:1635) (1674:1674:1674)) + (PORT datab (1575:1575:1575) (1613:1613:1613)) + (PORT datac (919:919:919) (987:987:987)) + (PORT datad (777:777:777) (773:773:773)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (372:372:372)) + (PORT datab (529:529:529) (518:518:518)) + (PORT datac (1759:1759:1759) (1839:1839:1839)) + (PORT datad (1669:1669:1669) (1705:1705:1705)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -8873,10 +5871,150 @@ (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (1422:1422:1422) (1430:1430:1430)) + (PORT datab (369:369:369) (376:376:376)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (1033:1033:1033) (1041:1041:1041)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1759:1759:1759) (1775:1775:1775)) + (PORT datab (1001:1001:1001) (1083:1083:1083)) + (PORT datac (1363:1363:1363) (1349:1349:1349)) + (PORT datad (835:835:835) (853:853:853)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1629:1629:1629) (1669:1669:1669)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (781:781:781) (772:772:772)) + (PORT datad (877:877:877) (932:932:932)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1000:1000:1000)) + (PORT datab (1653:1653:1653) (1676:1676:1676)) + (PORT datac (1715:1715:1715) (1770:1770:1770)) + (PORT datad (569:569:569) (588:588:588)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (724:724:724)) + (PORT datab (1390:1390:1390) (1412:1412:1412)) + (PORT datac (844:844:844) (843:843:843)) + (PORT datad (1669:1669:1669) (1697:1697:1697)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1589:1589:1589) (1657:1657:1657)) + (PORT datab (1695:1695:1695) (1816:1816:1816)) + (PORT datac (846:846:846) (849:849:849)) + (PORT datad (2077:2077:2077) (2120:2120:2120)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1536:1536:1536) (1698:1698:1698)) + (PORT datac (1125:1125:1125) (1209:1209:1209)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1021:1021:1021)) + (PORT datab (999:999:999) (1080:1080:1080)) + (PORT datac (1546:1546:1546) (1585:1585:1585)) + (PORT datad (760:760:760) (739:739:739)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1869:1869:1869)) + (PORT datab (779:779:779) (823:823:823)) + (PORT datac (348:348:348) (352:352:352)) + (PORT datad (1669:1669:1669) (1703:1703:1703)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (746:746:746) (750:750:750)) + (PORT datad (160:160:160) (182:182:182)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -8886,13 +6024,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (622:622:622)) - (PORT datab (360:360:360) (364:364:364)) - (PORT datac (1068:1068:1068) (1052:1052:1052)) - (PORT datad (870:870:870) (877:877:877)) + (PORT dataa (870:870:870) (873:873:873)) + (PORT datab (788:788:788) (789:789:789)) + (PORT datac (817:817:817) (817:817:817)) + (PORT datad (1054:1054:1054) (1050:1050:1050)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -8905,122 +6043,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) (DELAY (ABSOLUTE - (PORT dataa (1141:1141:1141) (1175:1175:1175)) - (PORT datab (895:895:895) (947:947:947)) - (PORT datac (775:775:775) (783:783:783)) - (PORT datad (1245:1245:1245) (1317:1317:1317)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (825:825:825)) - (PORT datab (1131:1131:1131) (1132:1132:1132)) - (PORT datac (1125:1125:1125) (1133:1133:1133)) - (PORT datad (628:628:628) (658:658:658)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1921:1921:1921) (1991:1991:1991)) - (PORT datab (1406:1406:1406) (1435:1435:1435)) - (PORT datac (546:546:546) (561:561:561)) - (PORT datad (1939:1939:1939) (1989:1989:1989)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (885:885:885)) - (PORT datab (227:227:227) (269:269:269)) - (PORT datac (1111:1111:1111) (1129:1129:1129)) - (PORT datad (1614:1614:1614) (1620:1620:1620)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (269:269:269)) - (PORT datab (594:594:594) (596:596:596)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (974:974:974)) - (PORT datab (821:821:821) (806:806:806)) - (PORT datac (951:951:951) (1023:1023:1023)) - (PORT datad (1170:1170:1170) (1212:1212:1212)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (819:819:819)) - (PORT datab (587:587:587) (601:601:601)) - (PORT datac (1526:1526:1526) (1585:1585:1585)) - (PORT datad (1056:1056:1056) (1035:1035:1035)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (723:723:723)) - (PORT datab (1137:1137:1137) (1153:1153:1153)) - (PORT datac (1197:1197:1197) (1255:1255:1255)) - (PORT datad (822:822:822) (844:844:844)) + (PORT dataa (1113:1113:1113) (1152:1152:1152)) + (PORT datab (1406:1406:1406) (1441:1441:1441)) + (PORT datac (850:850:850) (869:869:869)) + (PORT datad (1129:1129:1129) (1152:1152:1152)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -9030,125 +6056,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (381:381:381)) - (PORT datab (1121:1121:1121) (1136:1136:1136)) - (PORT datac (887:887:887) (922:922:922)) - (PORT datad (1775:1775:1775) (1857:1857:1857)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1262:1262:1262)) - (PORT datab (1420:1420:1420) (1502:1502:1502)) - (PORT datac (2033:2033:2033) (2061:2061:2061)) - (PORT datad (848:848:848) (872:872:872)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (2372:2372:2372) (2473:2473:2473)) - (PORT datab (1161:1161:1161) (1175:1175:1175)) - (PORT datac (817:817:817) (826:826:826)) - (PORT datad (1995:1995:1995) (2065:2065:2065)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1185:1185:1185)) - (PORT datac (1311:1311:1311) (1283:1283:1283)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (597:597:597)) - (PORT datab (1160:1160:1160) (1157:1157:1157)) - (PORT datac (1735:1735:1735) (1819:1819:1819)) - (PORT datad (1528:1528:1528) (1635:1635:1635)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT dataa (1263:1263:1263) (1338:1338:1338)) + (PORT datab (904:904:904) (921:921:921)) + (PORT datac (2154:2154:2154) (2177:2177:2177)) + (PORT datad (1615:1615:1615) (1637:1637:1637)) + (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) (DELAY (ABSOLUTE - (PORT dataa (1126:1126:1126) (1130:1130:1130)) - (PORT datab (531:531:531) (520:520:520)) - (PORT datac (1894:1894:1894) (1961:1961:1961)) - (PORT datad (1212:1212:1212) (1280:1280:1280)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (924:924:924) (988:988:988)) + (PORT datad (917:917:917) (977:977:977)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (252:252:252)) - (PORT datab (639:639:639) (632:632:632)) - (PORT datac (809:809:809) (821:821:821)) - (PORT datad (287:287:287) (294:294:294)) + (PORT dataa (873:873:873) (893:893:893)) + (PORT datab (193:193:193) (230:230:230)) + (PORT datac (521:521:521) (512:512:512)) + (PORT datad (1093:1093:1093) (1114:1114:1114)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1501:1501:1501)) - (PORT datab (1390:1390:1390) (1428:1428:1428)) - (PORT datac (162:162:162) (197:197:197)) - (PORT datad (644:644:644) (687:687:687)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -9156,28 +6100,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (INSTANCE z80_\|pla_decode_\|Equal48\~0) (DELAY (ABSOLUTE - (PORT datac (1974:1974:1974) (1977:1977:1977)) - (PORT datad (1309:1309:1309) (1309:1309:1309)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1124:1124:1124)) - (PORT datab (1321:1321:1321) (1318:1318:1318)) - (PORT datac (162:162:162) (198:198:198)) - (PORT datad (1318:1318:1318) (1354:1354:1354)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (2390:2390:2390) (2404:2404:2404)) + (PORT datab (1365:1365:1365) (1397:1397:1397)) + (PORT datac (1160:1160:1160) (1200:1200:1200)) + (PORT datad (1228:1228:1228) (1267:1267:1267)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -9187,12 +6119,12 @@ (INSTANCE z80_\|pla_decode_\|Equal69\~0) (DELAY (ABSOLUTE - (PORT dataa (1822:1822:1822) (1823:1823:1823)) - (PORT datab (1941:1941:1941) (1986:1986:1986)) - (PORT datac (1342:1342:1342) (1397:1397:1397)) - (PORT datad (194:194:194) (224:224:224)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (2393:2393:2393) (2405:2405:2405)) + (PORT datab (1365:1365:1365) (1393:1393:1393)) + (PORT datac (1163:1163:1163) (1197:1197:1197)) + (PORT datad (1228:1228:1228) (1261:1261:1261)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -9200,13 +6132,477 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1753:1753:1753) (1714:1714:1714)) - (PORT datab (1251:1251:1251) (1313:1313:1313)) - (PORT datac (1895:1895:1895) (1963:1963:1963)) - (PORT datad (1940:1940:1940) (1990:1990:1990)) + (PORT dataa (328:328:328) (342:342:342)) + (PORT datab (854:854:854) (856:856:856)) + (PORT datac (1456:1456:1456) (1528:1528:1528)) + (PORT datad (576:576:576) (598:598:598)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1053:1053:1053) (1039:1039:1039)) + (PORT datad (1546:1546:1546) (1556:1556:1556)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1705:1705:1705)) + (PORT datab (1323:1323:1323) (1299:1299:1299)) + (PORT datac (1599:1599:1599) (1616:1616:1616)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (691:691:691)) + (PORT datab (1017:1017:1017) (1047:1047:1047)) + (PORT datac (586:586:586) (589:589:589)) + (PORT datad (632:632:632) (667:667:667)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (665:665:665) (724:724:724)) + (PORT datad (358:358:358) (366:366:366)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datac (1152:1152:1152) (1209:1209:1209)) + (PORT datad (1121:1121:1121) (1198:1198:1198)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1129:1129:1129)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (917:917:917) (987:987:987)) + (PORT datad (1171:1171:1171) (1194:1194:1194)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (783:783:783)) + (PORT datab (631:631:631) (676:676:676)) + (PORT datac (1027:1027:1027) (1022:1022:1022)) + (PORT datad (1253:1253:1253) (1224:1224:1224)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (339:339:339)) + (PORT datab (862:862:862) (867:867:867)) + (PORT datac (1052:1052:1052) (1050:1050:1050)) + (PORT datad (490:490:490) (482:482:482)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1485:1485:1485)) + (PORT datac (885:885:885) (909:909:909)) + (PORT datad (1102:1102:1102) (1162:1162:1162)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2070:2070:2070) (2070:2070:2070)) + (PORT datab (871:871:871) (889:889:889)) + (PORT datac (879:879:879) (879:879:879)) + (PORT datad (825:825:825) (824:824:824)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1426:1426:1426) (1458:1458:1458)) + (PORT datad (1104:1104:1104) (1165:1165:1165)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1103:1103:1103)) + (PORT datab (636:636:636) (669:669:669)) + (PORT datac (1019:1019:1019) (1015:1015:1015)) + (PORT datad (1098:1098:1098) (1089:1089:1089)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (868:868:868)) + (PORT datab (922:922:922) (968:968:968)) + (PORT datac (1132:1132:1132) (1161:1161:1161)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1389:1389:1389)) + (PORT datab (1923:1923:1923) (1943:1943:1943)) + (PORT datac (1219:1219:1219) (1247:1247:1247)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1164:1164:1164)) + (PORT datac (1367:1367:1367) (1394:1394:1394)) + (PORT datad (2393:2393:2393) (2396:2396:2396)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1161:1161:1161)) + (PORT datab (692:692:692) (716:716:716)) + (PORT datac (1582:1582:1582) (1591:1591:1591)) + (PORT datad (1249:1249:1249) (1240:1240:1240)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1242:1242:1242)) + (PORT datab (1149:1149:1149) (1235:1235:1235)) + (PORT datac (1497:1497:1497) (1657:1657:1657)) + (PORT datad (316:316:316) (328:328:328)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1159:1159:1159)) + (PORT datab (1289:1289:1289) (1285:1285:1285)) + (PORT datac (1662:1662:1662) (1684:1684:1684)) + (PORT datad (1046:1046:1046) (1058:1058:1058)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (842:842:842)) + (PORT datab (377:377:377) (391:391:391)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (163:163:163) (186:186:186)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1118:1118:1118)) + (PORT datab (675:675:675) (697:697:697)) + (PORT datac (1144:1144:1144) (1131:1131:1131)) + (PORT datad (1723:1723:1723) (1796:1796:1796)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (782:782:782)) + (PORT datab (1802:1802:1802) (1790:1790:1790)) + (PORT datac (1335:1335:1335) (1376:1376:1376)) + (PORT datad (1497:1497:1497) (1498:1498:1498)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (227:227:227)) + (PORT datab (205:205:205) (241:241:241)) + (PORT datac (545:545:545) (546:546:546)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datac (1101:1101:1101) (1154:1154:1154)) + (PORT datad (362:362:362) (369:369:369)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1549:1549:1549)) + (PORT datad (1133:1133:1133) (1176:1176:1176)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (690:690:690)) + (PORT datab (1018:1018:1018) (1045:1045:1045)) + (PORT datac (1498:1498:1498) (1531:1531:1531)) + (PORT datad (634:634:634) (668:668:668)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1378:1378:1378)) + (PORT datab (943:943:943) (962:962:962)) + (PORT datac (1393:1393:1393) (1377:1377:1377)) + (PORT datad (1112:1112:1112) (1120:1120:1120)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1528:1528:1528)) + (PORT datab (1363:1363:1363) (1500:1500:1500)) + (PORT datad (1153:1153:1153) (1224:1224:1224)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1776:1776:1776) (1768:1768:1768)) + (PORT datab (886:886:886) (903:903:903)) + (PORT datac (1789:1789:1789) (1797:1797:1797)) + (PORT datad (1075:1075:1075) (1133:1133:1133)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1338:1338:1338)) + (PORT datab (1287:1287:1287) (1335:1335:1335)) + (PORT datac (1288:1288:1288) (1282:1282:1282)) + (PORT datad (1240:1240:1240) (1292:1292:1292)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1111:1111:1111)) + (PORT datab (815:815:815) (822:822:822)) + (PORT datac (1667:1667:1667) (1712:1712:1712)) + (PORT datad (1197:1197:1197) (1220:1220:1220)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1115:1115:1115)) + (PORT datab (1698:1698:1698) (1736:1736:1736)) + (PORT datac (1385:1385:1385) (1396:1396:1396)) + (PORT datad (1191:1191:1191) (1220:1220:1220)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -9216,31 +6612,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) (DELAY (ABSOLUTE - (PORT dataa (1624:1624:1624) (1649:1649:1649)) - (PORT datab (858:858:858) (861:861:861)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (578:578:578) (587:587:587)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (592:592:592) (605:605:605)) - (PORT datac (564:564:564) (557:557:557)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (872:872:872) (875:875:875)) + (PORT datab (1412:1412:1412) (1415:1415:1415)) + (PORT datac (1530:1530:1530) (1505:1505:1505)) + (PORT datad (1808:1808:1808) (1805:1805:1805)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -9248,29 +6628,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (971:971:971)) - (PORT datab (820:820:820) (804:804:804)) - (PORT datac (1520:1520:1520) (1616:1616:1616)) - (PORT datad (1978:1978:1978) (2057:2057:2057)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (839:839:839) (861:861:861)) + (PORT datab (1131:1131:1131) (1156:1156:1156)) + (PORT datac (565:565:565) (603:603:603)) + (PORT datad (209:209:209) (263:263:263)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) (DELAY (ABSOLUTE - (PORT dataa (1029:1029:1029) (1021:1021:1021)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (157:157:157) (186:186:186)) - (PORT datad (796:796:796) (803:803:803)) + (PORT dataa (792:792:792) (771:771:771)) + (PORT datab (615:615:615) (626:626:626)) + (PORT datac (1303:1303:1303) (1300:1300:1300)) + (PORT datad (1666:1666:1666) (1698:1698:1698)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~13) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (864:864:864)) + (PORT datab (237:237:237) (302:302:302)) + (PORT datac (1003:1003:1003) (991:991:991)) + (PORT datad (235:235:235) (275:275:275)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1030:1030:1030)) + (PORT datab (945:945:945) (1008:1008:1008)) + (PORT datac (1506:1506:1506) (1606:1606:1606)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~58) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (556:556:556)) + (PORT datab (677:677:677) (740:740:740)) + (PORT datac (1098:1098:1098) (1127:1127:1127)) + (PORT datad (1471:1471:1471) (1486:1486:1486)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -9278,17 +6706,367 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (856:856:856)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datac (796:796:796) (788:788:788)) + (PORT datad (1090:1090:1090) (1079:1079:1079)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (798:798:798) (796:796:796)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (853:853:853)) + (PORT datac (782:782:782) (770:770:770)) + (PORT datad (1049:1049:1049) (1021:1021:1021)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1108:1108:1108)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (584:584:584) (610:610:610)) + (PORT datad (1098:1098:1098) (1117:1117:1117)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~29) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (949:949:949)) + (PORT datab (1043:1043:1043) (1037:1037:1037)) + (PORT datac (1059:1059:1059) (1074:1074:1074)) + (PORT datad (2043:2043:2043) (2029:2029:2029)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (983:983:983)) + (PORT datab (923:923:923) (967:967:967)) + (PORT datac (832:832:832) (832:832:832)) + (PORT datad (172:172:172) (201:201:201)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (709:709:709)) + (PORT datab (379:379:379) (396:396:396)) + (PORT datac (1509:1509:1509) (1469:1469:1469)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1525:1525:1525)) + (PORT datab (1177:1177:1177) (1256:1256:1256)) + (PORT datac (1334:1334:1334) (1469:1469:1469)) + (PORT datad (798:798:798) (797:797:797)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (919:919:919)) + (PORT datab (1709:1709:1709) (1778:1778:1778)) + (PORT datac (2079:2079:2079) (2081:2081:2081)) + (PORT datad (1084:1084:1084) (1107:1107:1107)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (836:836:836)) + (PORT datab (691:691:691) (736:736:736)) + (PORT datac (1597:1597:1597) (1612:1612:1612)) + (PORT datad (800:800:800) (784:784:784)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2161:2161:2161) (2299:2299:2299)) + (PORT datab (668:668:668) (693:693:693)) + (PORT datac (1218:1218:1218) (1261:1261:1261)) + (PORT datad (1721:1721:1721) (1794:1794:1794)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1145:1145:1145)) + (PORT datab (1150:1150:1150) (1149:1149:1149)) + (PORT datac (647:647:647) (675:675:675)) + (PORT datad (845:845:845) (878:878:878)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (966:966:966)) + (PORT datab (866:866:866) (861:861:861)) + (PORT datac (585:585:585) (609:609:609)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1753:1753:1753) (1808:1808:1808)) + (PORT datab (1212:1212:1212) (1249:1249:1249)) + (PORT datac (857:857:857) (869:869:869)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (499:499:499)) + (PORT datab (808:808:808) (796:796:796)) + (PORT datac (996:996:996) (974:974:974)) + (PORT datad (1299:1299:1299) (1301:1301:1301)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (694:694:694)) + (PORT datab (661:661:661) (704:704:704)) + (PORT datac (990:990:990) (976:976:976)) + (PORT datad (1087:1087:1087) (1080:1080:1080)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1413:1413:1413)) + (PORT datab (859:859:859) (862:862:862)) + (PORT datac (876:876:876) (893:893:893)) + (PORT datad (854:854:854) (845:845:845)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1570:1570:1570) (1575:1575:1575)) + (PORT datab (1584:1584:1584) (1555:1555:1555)) + (PORT datac (784:784:784) (781:781:781)) + (PORT datad (1455:1455:1455) (1484:1484:1484)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1521:1521:1521)) + (PORT datab (1684:1684:1684) (1678:1678:1678)) + (PORT datac (1245:1245:1245) (1252:1252:1252)) + (PORT datad (515:515:515) (514:514:514)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (812:812:812)) + (PORT datab (927:927:927) (992:992:992)) + (PORT datac (918:918:918) (989:989:989)) + (PORT datad (761:761:761) (741:741:741)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1252:1252:1252)) + (PORT datab (1450:1450:1450) (1512:1512:1512)) + (PORT datac (1671:1671:1671) (1707:1707:1707)) + (PORT datad (319:319:319) (331:331:331)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (835:835:835)) + (PORT datab (205:205:205) (250:250:250)) + (PORT datac (1268:1268:1268) (1248:1248:1248)) + (PORT datad (987:987:987) (980:980:980)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (309:309:309)) - (PORT datab (225:225:225) (275:275:275)) - (PORT datac (1084:1084:1084) (1088:1088:1088)) - (PORT datad (228:228:228) (279:279:279)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (1437:1437:1437) (1446:1446:1446)) + (PORT datab (885:885:885) (896:896:896)) + (PORT datac (1750:1750:1750) (1734:1734:1734)) + (PORT datad (1076:1076:1076) (1134:1134:1134)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -9299,10 +7077,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) (DELAY (ABSOLUTE - (PORT dataa (1432:1432:1432) (1502:1502:1502)) - (PORT datab (1850:1850:1850) (1838:1838:1838)) - (PORT datac (816:816:816) (825:825:825)) - (PORT datad (1582:1582:1582) (1631:1631:1631)) + (PORT dataa (1629:1629:1629) (1638:1638:1638)) + (PORT datab (1418:1418:1418) (1450:1450:1450)) + (PORT datac (1377:1377:1377) (1483:1483:1483)) + (PORT datad (2036:2036:2036) (2079:2079:2079)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -9315,13 +7093,13 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (1142:1142:1142) (1160:1160:1160)) - (PORT datab (569:569:569) (581:581:581)) - (PORT datac (571:571:571) (593:593:593)) - (PORT datad (823:823:823) (829:829:829)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (578:578:578) (577:577:577)) + (PORT datab (776:776:776) (758:758:758)) + (PORT datac (567:567:567) (608:608:608)) + (PORT datad (1130:1130:1130) (1144:1144:1144)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -9331,532 +7109,56 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) (DELAY (ABSOLUTE - (PORT dataa (1700:1700:1700) (1753:1753:1753)) - (PORT datab (850:850:850) (875:875:875)) - (PORT datad (588:588:588) (589:589:589)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT datab (666:666:666) (710:710:710)) + (PORT datac (1022:1022:1022) (989:989:989)) + (PORT datad (585:585:585) (579:579:579)) (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1073:1073:1073) (1036:1036:1036)) - (PORT datac (300:300:300) (310:310:310)) - (PORT datad (612:612:612) (646:646:646)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (205:205:205) (241:241:241)) - (PORT datac (569:569:569) (575:575:575)) + (PORT dataa (1070:1070:1070) (1042:1042:1042)) + (PORT datab (317:317:317) (339:339:339)) + (PORT datac (771:771:771) (750:750:750)) + (PORT datad (552:552:552) (552:552:552)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1699:1699:1699) (1750:1750:1750)) - (PORT datab (625:625:625) (622:622:622)) - (PORT datac (161:161:161) (193:193:193)) - (PORT datad (826:826:826) (840:840:840)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (975:975:975)) - (PORT datab (1698:1698:1698) (1746:1746:1746)) - (PORT datac (914:914:914) (948:948:948)) - (PORT datad (1137:1137:1137) (1170:1170:1170)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2107:2107:2107) (2188:2188:2188)) - (PORT datab (1699:1699:1699) (1745:1745:1745)) - (PORT datac (806:806:806) (817:817:817)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (787:787:787)) - (PORT datab (1296:1296:1296) (1351:1351:1351)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (625:625:625) (674:674:674)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (317:317:317)) - (PORT datab (225:225:225) (270:270:270)) - (PORT datac (220:220:220) (272:272:272)) - (PORT datad (1121:1121:1121) (1127:1127:1127)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (769:769:769)) - (PORT datab (591:591:591) (632:632:632)) - (PORT datac (770:770:770) (796:796:796)) - (PORT datad (614:614:614) (647:647:647)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (1445:1445:1445) (1445:1445:1445)) - (PORT datac (2559:2559:2559) (2571:2571:2571)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (641:641:641)) - (PORT datab (354:354:354) (356:356:356)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (831:831:831) (829:829:829)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1215:1215:1215)) - (PORT datab (926:926:926) (952:952:952)) - (PORT datac (877:877:877) (900:900:900)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1123:1123:1123) (1104:1104:1104)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1214:1214:1214)) - (PORT datab (927:927:927) (955:955:955)) - (PORT datac (877:877:877) (897:897:897)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1386:1386:1386)) - (PORT datab (995:995:995) (1021:1021:1021)) - (PORT datac (1089:1089:1089) (1092:1092:1092)) - (PORT datad (1309:1309:1309) (1311:1311:1311)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (588:588:588)) - (PORT datab (187:187:187) (220:220:220)) - (PORT datac (1283:1283:1283) (1258:1258:1258)) - (PORT datad (1155:1155:1155) (1167:1167:1167)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1421:1421:1421) (1458:1458:1458)) - (PORT datab (1629:1629:1629) (1626:1626:1626)) - (PORT datac (562:562:562) (557:557:557)) - (PORT datad (582:582:582) (580:580:580)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT datab (638:638:638) (651:651:651)) - (PORT datac (354:354:354) (362:362:362)) - (PORT datad (795:795:795) (787:787:787)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (847:847:847)) - (PORT datab (1145:1145:1145) (1122:1122:1122)) - (PORT datac (167:167:167) (206:206:206)) - (PORT datad (1329:1329:1329) (1341:1341:1341)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (827:827:827)) - (PORT datab (628:628:628) (663:663:663)) - (PORT datac (821:821:821) (822:822:822)) - (PORT datad (1360:1360:1360) (1356:1356:1356)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (598:598:598)) - (PORT datab (628:628:628) (663:663:663)) - (PORT datac (1534:1534:1534) (1540:1540:1540)) - (PORT datad (336:336:336) (346:346:346)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (600:600:600)) - (PORT datab (1562:1562:1562) (1568:1568:1568)) - (PORT datac (767:767:767) (749:749:749)) - (PORT datad (774:774:774) (753:753:753)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (596:596:596)) - (PORT datab (838:838:838) (844:844:844)) - (PORT datac (1532:1532:1532) (1537:1537:1537)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (592:592:592) (582:582:582)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1313:1313:1313)) - (PORT datac (1814:1814:1814) (1910:1910:1910)) - (PORT datad (1080:1080:1080) (1071:1071:1071)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1649:1649:1649) (1694:1694:1694)) - (PORT datab (221:221:221) (266:266:266)) - (PORT datac (819:819:819) (833:833:833)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (853:853:853) (886:886:886)) - (PORT datac (957:957:957) (1011:1011:1011)) - (PORT datad (570:570:570) (571:571:571)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1552:1552:1552) (1576:1576:1576)) - (PORT datab (1670:1670:1670) (1701:1701:1701)) - (PORT datac (1233:1233:1233) (1228:1228:1228)) - (PORT datad (596:596:596) (614:614:614)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (862:862:862)) - (PORT datab (987:987:987) (990:990:990)) - (PORT datac (1380:1380:1380) (1410:1410:1410)) - (PORT datad (1109:1109:1109) (1113:1113:1113)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (225:225:225)) - (PORT datab (1408:1408:1408) (1432:1432:1432)) - (PORT datac (1014:1014:1014) (990:990:990)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (849:849:849)) - (PORT datab (1529:1529:1529) (1498:1498:1498)) - (PORT datac (1177:1177:1177) (1208:1208:1208)) - (PORT datad (1475:1475:1475) (1423:1423:1423)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (594:594:594)) - (PORT datac (1122:1122:1122) (1118:1118:1118)) - (PORT datad (821:821:821) (838:838:838)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1342:1342:1342)) - (PORT datab (608:608:608) (594:594:594)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (872:872:872) (866:866:866)) - (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) (DELAY (ABSOLUTE - (PORT datac (547:547:547) (537:537:537)) - (PORT datad (800:800:800) (779:779:779)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (662:662:662) (698:698:698)) + (PORT datab (1158:1158:1158) (1185:1185:1185)) + (PORT datac (600:600:600) (628:628:628)) + (PORT datad (2094:2094:2094) (2072:2072:2072)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (765:765:765) (743:743:743)) + (PORT dataa (793:793:793) (792:792:792)) + (PORT datab (575:575:575) (577:577:577)) + (PORT datac (555:555:555) (544:544:544)) + (PORT datad (847:847:847) (862:862:862)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -9866,242 +7168,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~8) (DELAY (ABSOLUTE - (PORT datab (342:342:342) (349:349:349)) - (PORT datac (549:549:549) (545:545:545)) - (PORT datad (565:565:565) (574:574:574)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1249:1249:1249)) - (PORT datab (1486:1486:1486) (1494:1494:1494)) - (PORT datac (895:895:895) (929:929:929)) - (PORT datad (2050:2050:2050) (1954:1954:1954)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (770:770:770)) - (PORT datab (201:201:201) (234:234:234)) - (PORT datac (900:900:900) (904:904:904)) - (PORT datad (1028:1028:1028) (1042:1042:1042)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1070:1070:1070) (1064:1064:1064)) - (PORT datab (840:840:840) (837:837:837)) - (PORT datac (884:884:884) (913:913:913)) - (PORT datad (180:180:180) (211:211:211)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1232:1232:1232)) - (PORT datab (591:591:591) (580:580:580)) - (PORT datac (167:167:167) (205:205:205)) - (PORT datad (884:884:884) (936:936:936)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT datab (1137:1137:1137) (1154:1154:1154)) - (PORT datac (862:862:862) (884:884:884)) - (PORT datad (839:839:839) (867:867:867)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1087:1087:1087)) - (PORT datab (849:849:849) (840:840:840)) - (PORT datac (1046:1046:1046) (1033:1033:1033)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (1245:1245:1245) (1206:1206:1206)) - (PORT datad (1059:1059:1059) (1042:1042:1042)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (610:610:610)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (755:755:755) (745:745:745)) - (PORT datad (761:761:761) (754:754:754)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (603:603:603)) - (PORT datab (909:909:909) (962:962:962)) - (PORT datac (1010:1010:1010) (983:983:983)) - (PORT datad (1654:1654:1654) (1710:1710:1710)) + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (1051:1051:1051) (1032:1032:1032)) + (PORT datac (836:836:836) (846:846:846)) + (PORT datad (759:759:759) (741:741:741)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (605:605:605)) - (PORT datab (882:882:882) (865:865:865)) - (PORT datac (334:334:334) (354:354:354)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (579:579:579) (558:558:558)) - (PORT datac (809:809:809) (802:802:802)) - (PORT datad (537:537:537) (523:523:523)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1216:1216:1216)) - (PORT datab (914:914:914) (919:919:919)) - (PORT datac (895:895:895) (920:920:920)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1202:1202:1202)) - (PORT datab (910:910:910) (918:918:918)) - (PORT datac (902:902:902) (927:927:927)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (484:484:484) (510:510:510)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (873:873:873)) - (PORT datab (2423:2423:2423) (2439:2439:2439)) - (PORT datac (169:169:169) (208:208:208)) - (PORT datad (1277:1277:1277) (1281:1281:1281)) - (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -10110,110 +7184,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) (DELAY (ABSOLUTE - (PORT dataa (1761:1761:1761) (1869:1869:1869)) - (PORT datab (1393:1393:1393) (1412:1412:1412)) - (PORT datad (1072:1072:1072) (1043:1043:1043)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1712:1712:1712) (1681:1681:1681)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1522:1522:1522) (1510:1510:1510)) - (PORT datab (1608:1608:1608) (1577:1577:1577)) - (PORT datac (1098:1098:1098) (1115:1115:1115)) - (PORT datad (1127:1127:1127) (1147:1147:1147)) + (PORT dataa (587:587:587) (624:624:624)) + (PORT datac (641:641:641) (700:700:700)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1124:1124:1124)) - (PORT datab (1117:1117:1117) (1129:1129:1129)) - (PORT datac (1547:1547:1547) (1532:1532:1532)) - (PORT datad (545:545:545) (534:534:534)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1380:1380:1380)) - (PORT datab (880:880:880) (913:913:913)) - (PORT datac (1104:1104:1104) (1110:1110:1110)) - (PORT datad (1095:1095:1095) (1103:1103:1103)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) (DELAY (ABSOLUTE - (PORT dataa (573:573:573) (579:579:579)) - (PORT datab (1718:1718:1718) (1747:1747:1747)) - (PORT datac (948:948:948) (985:985:985)) - (PORT datad (2417:2417:2417) (2388:2388:2388)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1143:1143:1143)) - (PORT datab (1165:1165:1165) (1181:1181:1181)) - (PORT datac (804:804:804) (835:835:835)) - (PORT datad (823:823:823) (858:858:858)) + (PORT dataa (966:966:966) (1000:1000:1000)) + (PORT datab (542:542:542) (545:545:545)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (185:185:185) (212:212:212)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (353:353:353)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datac (849:849:849) (874:874:874)) + (PORT datad (1325:1325:1325) (1317:1317:1317)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -10221,12 +7228,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (INSTANCE z80_\|execute_\|setM1\~49) (DELAY (ABSOLUTE - (PORT datab (847:847:847) (836:836:836)) - (PORT datac (586:586:586) (597:597:597)) - (PORT datad (178:178:178) (201:201:201)) + (PORT datab (786:786:786) (800:800:800)) + (PORT datac (1841:1841:1841) (1837:1837:1837)) + (PORT datad (1667:1667:1667) (1704:1704:1704)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT datab (1026:1026:1026) (1030:1030:1030)) + (PORT datac (737:737:737) (733:733:733)) + (PORT datad (1031:1031:1031) (1019:1019:1019)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -10235,235 +7256,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (INSTANCE z80_\|execute_\|setM1\~52) (DELAY (ABSOLUTE - (PORT datab (207:207:207) (253:253:253)) - (PORT datac (2500:2500:2500) (2608:2608:2608)) - (PORT datad (197:197:197) (229:229:229)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1453:1453:1453)) - (PORT datab (1388:1388:1388) (1407:1407:1407)) - (PORT datac (1366:1366:1366) (1382:1382:1382)) - (PORT datad (1029:1029:1029) (1031:1031:1031)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1179:1179:1179)) - (PORT datab (893:893:893) (949:949:949)) - (PORT datac (1810:1810:1810) (1805:1805:1805)) - (PORT datad (1249:1249:1249) (1320:1320:1320)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1358:1358:1358)) - (PORT datab (1209:1209:1209) (1281:1281:1281)) - (PORT datac (858:858:858) (900:900:900)) - (PORT datad (1392:1392:1392) (1470:1470:1470)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (902:902:902)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (548:548:548) (564:564:564)) - (PORT datad (1143:1143:1143) (1150:1150:1150)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1435:1435:1435)) - (PORT datab (824:824:824) (825:825:825)) - (PORT datac (1350:1350:1350) (1325:1325:1325)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (882:882:882) (891:891:891)) - (PORT datac (583:583:583) (578:578:578)) - (PORT datad (534:534:534) (530:530:530)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (652:652:652)) - (PORT datab (1043:1043:1043) (1047:1047:1047)) - (PORT datac (1777:1777:1777) (1816:1816:1816)) - (PORT datad (755:755:755) (757:757:757)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (881:881:881)) - (PORT datab (516:516:516) (520:520:520)) - (PORT datac (888:888:888) (903:903:903)) - (PORT datad (858:858:858) (869:869:869)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (336:336:336)) - (PORT datab (227:227:227) (263:263:263)) - (PORT datac (888:888:888) (900:900:900)) - (PORT datad (858:858:858) (866:866:866)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (969:969:969)) - (PORT datab (715:715:715) (786:786:786)) - (PORT datac (673:673:673) (738:738:738)) - (PORT datad (579:579:579) (606:606:606)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1130:1130:1130)) - (PORT datab (315:315:315) (332:332:332)) - (PORT datac (1751:1751:1751) (1851:1851:1851)) - (PORT datad (570:570:570) (574:574:574)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (251:251:251)) - (PORT datab (370:370:370) (388:388:388)) - (PORT datac (905:905:905) (911:911:911)) - (PORT datad (755:755:755) (735:735:735)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1122:1122:1122) (1120:1120:1120)) - (PORT datad (301:301:301) (306:306:306)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1478:1478:1478)) - (PORT datab (1119:1119:1119) (1115:1115:1115)) - (PORT datac (1197:1197:1197) (1256:1256:1256)) - (PORT datad (636:636:636) (687:687:687)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT dataa (605:605:605) (600:600:600)) + (PORT datab (880:880:880) (897:897:897)) + (PORT datac (783:783:783) (795:795:795)) + (PORT datad (618:618:618) (646:646:646)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~9) + (DELAY + (ABSOLUTE + (PORT datab (1155:1155:1155) (1239:1239:1239)) + (PORT datac (1503:1503:1503) (1661:1661:1661)) + (PORT datad (369:369:369) (383:383:383)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -10471,47 +7286,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (247:247:247)) - (PORT datab (575:575:575) (573:573:573)) - (PORT datac (1051:1051:1051) (1038:1038:1038)) - (PORT datad (643:643:643) (684:684:684)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (724:724:724)) - (PORT datab (619:619:619) (644:644:644)) - (PORT datac (589:589:589) (606:606:606)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (201:201:201) (233:233:233)) - (PORT datac (1060:1060:1060) (1049:1049:1049)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datab (1159:1159:1159) (1246:1246:1246)) + (PORT datac (1505:1505:1505) (1667:1667:1667)) + (PORT datad (368:368:368) (384:384:384)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -10522,10 +7303,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (557:557:557) (567:567:567)) - (PORT datab (1090:1090:1090) (1068:1068:1068)) - (PORT datac (1306:1306:1306) (1296:1296:1296)) - (PORT datad (798:798:798) (785:785:785)) + (PORT dataa (1197:1197:1197) (1190:1190:1190)) + (PORT datab (1310:1310:1310) (1276:1276:1276)) + (PORT datac (1080:1080:1080) (1108:1108:1108)) + (PORT datad (603:603:603) (612:612:612)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -10538,881 +7319,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (264:264:264)) - (PORT datab (918:918:918) (938:938:938)) - (PORT datac (593:593:593) (624:624:624)) - (PORT datad (298:298:298) (294:294:294)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT datab (3331:3331:3331) (3323:3323:3323)) - (PORT datad (1395:1395:1395) (1422:1422:1422)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (572:572:572)) - (PORT datab (1084:1084:1084) (1088:1088:1088)) - (PORT datac (580:580:580) (580:580:580)) - (PORT datad (770:770:770) (756:756:756)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1744:1744:1744)) - (PORT datab (832:832:832) (871:871:871)) - (PORT datac (822:822:822) (822:822:822)) - (PORT datad (797:797:797) (801:801:801)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datab (609:609:609) (622:622:622)) - (PORT datad (1028:1028:1028) (1015:1015:1015)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT datab (809:809:809) (814:814:814)) - (PORT datac (977:977:977) (1012:1012:1012)) - (PORT datad (1394:1394:1394) (1376:1376:1376)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (349:349:349)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (516:516:516) (500:500:500)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1524:1524:1524) (1638:1638:1638)) - (PORT datab (1165:1165:1165) (1220:1220:1220)) - (PORT datac (1273:1273:1273) (1247:1247:1247)) - (PORT datad (545:545:545) (541:541:541)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2069:2069:2069) (2089:2089:2089)) - (PORT datab (817:817:817) (812:812:812)) - (PORT datac (1451:1451:1451) (1528:1528:1528)) - (PORT datad (1564:1564:1564) (1582:1582:1582)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (866:866:866)) - (PORT datab (1250:1250:1250) (1227:1227:1227)) - (PORT datac (817:817:817) (828:828:828)) - (PORT datad (1315:1315:1315) (1289:1289:1289)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (646:646:646)) - (PORT datab (1366:1366:1366) (1352:1352:1352)) - (PORT datac (792:792:792) (785:785:785)) - (PORT datad (621:621:621) (645:645:645)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1178:1178:1178)) - (PORT datab (869:869:869) (857:857:857)) - (PORT datac (1309:1309:1309) (1294:1294:1294)) - (PORT datad (1630:1630:1630) (1640:1640:1640)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (801:801:801) (790:790:790)) - (PORT datad (305:305:305) (319:319:319)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (609:609:609) (613:613:613)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (877:877:877)) - (PORT datab (920:920:920) (934:934:934)) - (PORT datac (807:807:807) (827:827:827)) - (PORT datad (821:821:821) (815:815:815)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1652:1652:1652) (1679:1679:1679)) - (PORT datab (1426:1426:1426) (1406:1406:1406)) - (PORT datac (976:976:976) (1009:1009:1009)) - (PORT datad (782:782:782) (779:779:779)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1087:1087:1087)) - (PORT datab (807:807:807) (811:811:811)) - (PORT datac (977:977:977) (1009:1009:1009)) - (PORT datad (1389:1389:1389) (1371:1371:1371)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1631:1631:1631) (1629:1629:1629)) - (PORT datab (1787:1787:1787) (1769:1769:1769)) - (PORT datac (1451:1451:1451) (1404:1404:1404)) - (PORT datad (971:971:971) (997:997:997)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (256:256:256)) - (PORT datab (213:213:213) (254:254:254)) - (PORT datac (938:938:938) (958:958:958)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1527:1527:1527) (1639:1639:1639)) - (PORT datac (1141:1141:1141) (1199:1199:1199)) - (PORT datad (1036:1036:1036) (1023:1023:1023)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1288:1288:1288)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (758:758:758) (748:748:748)) - (PORT datad (786:786:786) (789:789:789)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1107:1107:1107)) - (PORT datac (846:846:846) (845:845:845)) - (PORT datad (795:795:795) (793:793:793)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1269:1269:1269)) - (PORT datab (859:859:859) (860:860:860)) - (PORT datac (1279:1279:1279) (1390:1390:1390)) - (PORT datad (1100:1100:1100) (1096:1096:1096)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (865:865:865)) - (PORT datab (1420:1420:1420) (1505:1505:1505)) - (PORT datac (2031:2031:2031) (2059:2059:2059)) - (PORT datad (1408:1408:1408) (1475:1475:1475)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (1103:1103:1103) (1098:1098:1098)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1525:1525:1525) (1634:1634:1634)) - (PORT datab (327:327:327) (345:345:345)) - (PORT datac (1137:1137:1137) (1194:1194:1194)) - (PORT datad (559:559:559) (569:569:569)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (556:556:556)) - (PORT datab (896:896:896) (914:914:914)) - (PORT datac (609:609:609) (637:637:637)) - (PORT datad (548:548:548) (535:535:535)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (813:813:813)) - (PORT datab (191:191:191) (230:230:230)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (1439:1439:1439) (1492:1492:1492)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (564:564:564)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (583:583:583) (599:599:599)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (238:238:238)) - (PORT datab (590:590:590) (611:611:611)) - (PORT datac (765:765:765) (748:748:748)) - (PORT datad (1563:1563:1563) (1577:1577:1577)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (353:353:353)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1117:1117:1117) (1138:1138:1138)) - (PORT datad (976:976:976) (971:971:971)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1302:1302:1302)) - (PORT datab (1081:1081:1081) (1064:1064:1064)) - (PORT datad (1485:1485:1485) (1526:1526:1526)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1469:1469:1469) (1453:1453:1453)) - (PORT datab (1496:1496:1496) (1567:1567:1567)) - (PORT datac (806:806:806) (818:818:818)) - (PORT datad (1218:1218:1218) (1233:1233:1233)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (391:391:391)) - (PORT datab (220:220:220) (265:265:265)) - (PORT datac (1354:1354:1354) (1358:1358:1358)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1334:1334:1334)) - (PORT datab (1024:1024:1024) (989:989:989)) - (PORT datac (1387:1387:1387) (1391:1391:1391)) - (PORT datad (585:585:585) (592:592:592)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (565:565:565)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (570:570:570) (588:588:588)) - (PORT datad (581:581:581) (585:585:585)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1172:1172:1172)) - (PORT datab (2234:2234:2234) (2241:2241:2241)) - (PORT datac (1550:1550:1550) (1541:1541:1541)) - (PORT datad (908:908:908) (944:944:944)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (972:972:972)) - (PORT datab (702:702:702) (761:761:761)) - (PORT datac (563:563:563) (580:580:580)) - (PORT datad (813:813:813) (809:809:809)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1065:1065:1065)) - (PORT datab (349:349:349) (348:348:348)) - (PORT datac (853:853:853) (879:879:879)) - (PORT datad (763:763:763) (766:766:766)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (178:178:178) (223:223:223)) - (PORT datad (807:807:807) (821:821:821)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1425:1425:1425) (1469:1469:1469)) - (PORT datab (934:934:934) (982:982:982)) - (PORT datac (311:311:311) (327:327:327)) - (PORT datad (177:177:177) (209:209:209)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1317:1317:1317)) - (PORT datab (1034:1034:1034) (1013:1013:1013)) - (PORT datac (1286:1286:1286) (1278:1278:1278)) - (PORT datad (309:309:309) (323:323:323)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (846:846:846)) - (PORT datab (653:653:653) (705:705:705)) - (PORT datac (624:624:624) (666:666:666)) - (PORT datad (539:539:539) (538:538:538)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (443:443:443)) - (PORT datab (245:245:245) (316:316:316)) - (PORT datac (1290:1290:1290) (1350:1350:1350)) - (PORT datad (1085:1085:1085) (1129:1129:1129)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1471:1471:1471) (1558:1558:1558)) - (PORT datab (1783:1783:1783) (1836:1836:1836)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (2390:2390:2390) (2402:2402:2402)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2057:2057:2057) (2042:2042:2042)) - (PORT datab (2299:2299:2299) (2386:2386:2386)) - (PORT datac (2055:2055:2055) (2071:2071:2071)) - (PORT datad (1520:1520:1520) (1530:1530:1530)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1117:1117:1117) (1153:1153:1153)) - (PORT datab (817:817:817) (806:806:806)) - (PORT datac (2053:2053:2053) (2071:2071:2071)) - (PORT datad (2264:2264:2264) (2348:2348:2348)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1909:1909:1909) (1895:1895:1895)) - (PORT datad (183:183:183) (209:209:209)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (771:771:771)) - (PORT datab (772:772:772) (760:760:760)) - (PORT datac (1442:1442:1442) (1516:1516:1516)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (360:360:360)) - (PORT datab (180:180:180) (211:211:211)) - (PORT datac (1113:1113:1113) (1133:1133:1133)) - (PORT datad (803:803:803) (817:817:817)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) - (DELAY - (ABSOLUTE - (PORT datac (794:794:794) (776:776:776)) - (PORT datad (1264:1264:1264) (1241:1241:1241)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1343:1343:1343)) - (PORT datab (1113:1113:1113) (1110:1110:1110)) - (PORT datac (1616:1616:1616) (1660:1660:1660)) - (PORT datad (1349:1349:1349) (1370:1370:1370)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (829:829:829)) - (PORT datab (624:624:624) (630:630:630)) - (PORT datac (1900:1900:1900) (1981:1981:1981)) - (PORT datad (1329:1329:1329) (1300:1300:1300)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (755:755:755)) - (PORT datab (829:829:829) (825:825:825)) - (PORT datad (1115:1115:1115) (1107:1107:1107)) - (IOPATH dataa combout (273:273:273) (273:273:273)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (754:754:754)) - (PORT datab (204:204:204) (247:247:247)) - (PORT datac (727:727:727) (707:707:707)) - (PORT datad (204:204:204) (264:264:264)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1044:1044:1044)) - (PORT datab (850:850:850) (890:890:890)) - (PORT datac (1748:1748:1748) (1851:1851:1851)) - (PORT datad (1110:1110:1110) (1136:1136:1136)) + (PORT dataa (1120:1120:1120) (1115:1115:1115)) + (PORT datab (1520:1520:1520) (1494:1494:1494)) + (PORT datac (1078:1078:1078) (1087:1087:1087)) + (PORT datad (292:292:292) (301:301:301)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -11422,1231 +7332,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (834:834:834)) - (PORT datab (426:426:426) (467:467:467)) - (PORT datac (392:392:392) (431:431:431)) - (PORT datad (903:903:903) (942:942:942)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1709:1709:1709) (1732:1732:1732)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datac (622:622:622) (652:652:652)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1018:1018:1018)) - (PORT datab (1140:1140:1140) (1138:1138:1138)) - (PORT datac (1106:1106:1106) (1142:1142:1142)) - (PORT datad (164:164:164) (190:190:190)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (681:681:681)) - (PORT datab (1397:1397:1397) (1391:1391:1391)) - (PORT datac (1845:1845:1845) (1825:1825:1825)) - (PORT datad (1328:1328:1328) (1336:1336:1336)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (831:831:831)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (294:294:294) (299:299:299)) - (PORT datad (551:551:551) (555:555:555)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (2614:2614:2614) (2718:2718:2718)) - (PORT datab (1021:1021:1021) (986:986:986)) - (PORT datac (1388:1388:1388) (1392:1392:1392)) - (PORT datad (1173:1173:1173) (1248:1248:1248)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (811:811:811)) - (PORT datab (195:195:195) (235:235:235)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1436:1436:1436) (1492:1492:1492)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1156:1156:1156)) - (PORT datab (1300:1300:1300) (1293:1293:1293)) - (PORT datac (1113:1113:1113) (1107:1107:1107)) - (PORT datad (1327:1327:1327) (1322:1322:1322)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1166:1166:1166)) - (PORT datab (796:796:796) (828:828:828)) - (PORT datac (1606:1606:1606) (1607:1607:1607)) - (PORT datad (759:759:759) (806:806:806)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (708:708:708)) - (PORT datac (1267:1267:1267) (1320:1320:1320)) - (PORT datad (625:625:625) (672:672:672)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1017:1017:1017)) - (PORT datab (206:206:206) (243:243:243)) - (PORT datac (1274:1274:1274) (1289:1289:1289)) - (PORT datad (183:183:183) (210:210:210)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (668:668:668)) - (PORT datab (623:623:623) (657:657:657)) - (PORT datac (1110:1110:1110) (1135:1135:1135)) - (PORT datad (1026:1026:1026) (1009:1009:1009)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1044:1044:1044)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (162:162:162) (197:197:197)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (2081:2081:2081) (2101:2101:2101)) - (PORT datac (1448:1448:1448) (1525:1525:1525)) - (PORT datad (1561:1561:1561) (1577:1577:1577)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1326:1326:1326)) - (PORT datab (1039:1039:1039) (1025:1025:1025)) - (PORT datac (294:294:294) (312:312:312)) - (PORT datad (562:562:562) (570:570:570)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1230:1230:1230)) - (PORT datab (908:908:908) (956:956:956)) - (PORT datac (822:822:822) (834:834:834)) - (PORT datad (578:578:578) (584:584:584)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (594:594:594)) - (PORT datab (1371:1371:1371) (1394:1394:1394)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1156:1156:1156) (1172:1172:1172)) + (PORT dataa (543:543:543) (536:536:536)) + (PORT datab (1115:1115:1115) (1105:1105:1105)) + (PORT datac (1572:1572:1572) (1582:1582:1582)) + (PORT datad (1083:1083:1083) (1092:1092:1092)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (950:950:950)) - (PORT datab (839:839:839) (839:839:839)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (817:817:817) (819:819:819)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (254:254:254)) - (PORT datac (795:795:795) (811:811:811)) - (PORT datad (196:196:196) (225:225:225)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2182:2182:2182) (2183:2183:2183)) - (PORT datab (2529:2529:2529) (2637:2637:2637)) - (PORT datad (808:808:808) (822:822:822)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (603:603:603)) - (PORT datab (589:589:589) (603:603:603)) - (PORT datac (580:580:580) (574:574:574)) - (PORT datad (1058:1058:1058) (1058:1058:1058)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (592:592:592)) - (PORT datab (590:590:590) (585:585:585)) - (PORT datac (601:601:601) (615:615:615)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1424:1424:1424)) - (PORT datab (884:884:884) (898:898:898)) - (PORT datac (1188:1188:1188) (1237:1237:1237)) - (PORT datad (1100:1100:1100) (1097:1097:1097)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (867:867:867)) - (PORT datab (1251:1251:1251) (1224:1224:1224)) - (PORT datac (299:299:299) (318:318:318)) - (PORT datad (1316:1316:1316) (1289:1289:1289)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (611:611:611) (605:605:605)) - (PORT datac (854:854:854) (863:863:863)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (819:819:819)) - (PORT datab (1304:1304:1304) (1378:1378:1378)) - (PORT datac (520:520:520) (515:515:515)) - (PORT datad (867:867:867) (924:924:924)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1235:1235:1235)) - (PORT datab (1719:1719:1719) (1804:1804:1804)) - (PORT datac (1747:1747:1747) (1842:1842:1842)) - (PORT datad (980:980:980) (970:970:970)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (265:265:265)) - (PORT datab (832:832:832) (833:833:833)) - (PORT datac (1576:1576:1576) (1618:1618:1618)) - (PORT datad (590:590:590) (596:596:596)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (964:964:964) (914:914:914)) - (PORT datab (1353:1353:1353) (1337:1337:1337)) - (PORT datac (1715:1715:1715) (1659:1659:1659)) - (PORT datad (836:836:836) (828:828:828)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (833:833:833) (852:852:852)) - (PORT datac (1197:1197:1197) (1223:1223:1223)) - (PORT datad (758:758:758) (730:730:730)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (911:911:911)) - (PORT datab (1419:1419:1419) (1503:1503:1503)) - (PORT datac (2033:2033:2033) (2056:2056:2056)) - (PORT datad (1405:1405:1405) (1473:1473:1473)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (910:910:910)) - (PORT datab (1123:1123:1123) (1127:1127:1127)) - (PORT datac (763:763:763) (747:747:747)) - (PORT datad (541:541:541) (545:545:545)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (1106:1106:1106) (1101:1101:1101)) - (PORT datac (518:518:518) (512:512:512)) - (PORT datad (579:579:579) (597:597:597)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1065:1065:1065)) - (PORT datab (1362:1362:1362) (1367:1367:1367)) - (PORT datac (990:990:990) (968:968:968)) - (PORT datad (1337:1337:1337) (1331:1331:1331)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (337:337:337)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (780:780:780) (787:787:787)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (387:387:387)) - (PORT datab (204:204:204) (249:249:249)) - (PORT datac (1103:1103:1103) (1089:1089:1089)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (792:792:792)) - (PORT datab (1590:1590:1590) (1584:1584:1584)) - (PORT datad (1678:1678:1678) (1714:1714:1714)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (757:757:757)) - (PORT datab (829:829:829) (824:824:824)) - (PORT datad (1114:1114:1114) (1107:1107:1107)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (752:752:752)) - (PORT datab (225:225:225) (296:296:296)) - (PORT datac (726:726:726) (707:707:707)) - (PORT datad (177:177:177) (209:209:209)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (259:259:259)) - (PORT datac (1300:1300:1300) (1260:1260:1260)) - (PORT datad (1721:1721:1721) (1698:1698:1698)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (258:258:258)) - (PORT datac (1297:1297:1297) (1258:1258:1258)) - (PORT datad (1724:1724:1724) (1699:1699:1699)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (911:911:911) (911:911:911)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1590:1590:1590) (1588:1588:1588)) - (PORT datac (768:768:768) (766:766:766)) - (PORT datad (1676:1676:1676) (1712:1712:1712)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (914:914:914) (914:914:914)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (293:293:293)) - (PORT datab (1005:1005:1005) (991:991:991)) - (PORT datad (330:330:330) (372:372:372)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1347:1347:1347) (1359:1359:1359)) - (PORT datab (1041:1041:1041) (1033:1033:1033)) - (PORT datac (856:856:856) (895:895:895)) - (PORT datad (547:547:547) (535:535:535)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (391:391:391)) - (PORT datab (202:202:202) (237:237:237)) - (PORT datac (180:180:180) (227:227:227)) - (PORT datad (1210:1210:1210) (1178:1178:1178)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1891:1891:1891) (1972:1972:1972)) - (PORT datab (1267:1267:1267) (1341:1341:1341)) - (PORT datac (1029:1029:1029) (1038:1038:1038)) - (PORT datad (825:825:825) (807:807:807)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (894:894:894)) - (PORT datab (1024:1024:1024) (1010:1010:1010)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (812:812:812) (791:791:791)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1070:1070:1070)) - (PORT datab (892:892:892) (923:923:923)) - (PORT datac (1106:1106:1106) (1137:1137:1137)) - (PORT datad (2646:2646:2646) (2656:2656:2656)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (226:226:226)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1257:1257:1257) (1240:1240:1240)) - (PORT datad (604:604:604) (595:595:595)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2118:2118:2118) (2206:2206:2206)) - (PORT datab (1616:1616:1616) (1649:1649:1649)) - (PORT datac (1336:1336:1336) (1319:1319:1319)) - (PORT datad (1030:1030:1030) (1011:1011:1011)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1024:1024:1024)) - (PORT datab (1138:1138:1138) (1124:1124:1124)) - (PORT datac (1106:1106:1106) (1101:1101:1101)) - (PORT datad (2057:2057:2057) (2027:2027:2027)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1072:1072:1072)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (789:789:789) (788:788:788)) - (PORT datad (1876:1876:1876) (1812:1812:1812)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1150:1150:1150)) - (PORT datab (1259:1259:1259) (1230:1230:1230)) - (PORT datac (832:832:832) (834:834:834)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1198:1198:1198)) - (PORT datad (801:801:801) (821:821:821)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (878:878:878)) - (PORT datab (617:617:617) (610:610:610)) - (PORT datac (1799:1799:1799) (1813:1813:1813)) - (PORT datad (1474:1474:1474) (1557:1557:1557)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (869:869:869)) - (PORT datab (903:903:903) (908:908:908)) - (PORT datac (1258:1258:1258) (1237:1237:1237)) - (PORT datad (551:551:551) (548:548:548)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1096:1096:1096)) - (PORT datab (599:599:599) (606:606:606)) - (PORT datac (839:839:839) (836:836:836)) - (PORT datad (796:796:796) (796:796:796)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (273:273:273)) - (PORT datab (866:866:866) (873:873:873)) - (PORT datac (1351:1351:1351) (1373:1373:1373)) - (PORT datad (777:777:777) (769:769:769)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (529:529:529) (531:531:531)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (636:636:636)) - (PORT datab (1486:1486:1486) (1494:1494:1494)) - (PORT datac (1186:1186:1186) (1219:1219:1219)) - (PORT datad (830:830:830) (839:839:839)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (582:582:582)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (571:571:571) (566:566:566)) - (PORT datad (849:849:849) (861:861:861)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (345:345:345)) - (PORT datab (1124:1124:1124) (1130:1130:1130)) - (PORT datac (1481:1481:1481) (1444:1444:1444)) - (PORT datad (900:900:900) (905:905:905)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (578:578:578) (587:587:587)) - (PORT datad (798:798:798) (782:782:782)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1168:1168:1168)) - (PORT datab (1362:1362:1362) (1365:1365:1365)) - (PORT datac (1057:1057:1057) (1048:1048:1048)) - (PORT datad (1098:1098:1098) (1111:1111:1111)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (338:338:338)) - (PORT datab (1274:1274:1274) (1252:1252:1252)) - (PORT datac (993:993:993) (986:986:986)) - (PORT datad (1255:1255:1255) (1228:1228:1228)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (667:667:667)) - (PORT datab (850:850:850) (851:851:851)) - (PORT datad (1090:1090:1090) (1122:1122:1122)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) - (DELAY - (ABSOLUTE - (PORT dataa (2042:2042:2042) (2131:2131:2131)) - (PORT datab (1463:1463:1463) (1529:1529:1529)) - (PORT datac (1387:1387:1387) (1436:1436:1436)) - (PORT datad (804:804:804) (801:801:801)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1659:1659:1659)) - (PORT datab (1094:1094:1094) (1112:1112:1112)) - (PORT datac (1746:1746:1746) (1751:1751:1751)) - (PORT datad (1020:1020:1020) (1006:1006:1006)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (356:356:356)) - (PORT datab (591:591:591) (602:602:602)) - (PORT datac (579:579:579) (583:583:583)) - (PORT datad (552:552:552) (547:547:547)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1048:1048:1048)) - (PORT datab (806:806:806) (815:815:815)) - (PORT datac (1626:1626:1626) (1652:1652:1652)) - (PORT datad (1039:1039:1039) (1046:1046:1046)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (908:908:908)) - (PORT datab (820:820:820) (815:815:815)) - (PORT datac (856:856:856) (859:859:859)) - (PORT datad (1293:1293:1293) (1282:1282:1282)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (245:245:245)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (1096:1096:1096) (1097:1097:1097)) - (PORT datad (566:566:566) (586:586:586)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1135:1135:1135)) - (PORT datab (903:903:903) (925:925:925)) - (PORT datac (815:815:815) (823:823:823)) - (PORT datad (1126:1126:1126) (1142:1142:1142)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (561:561:561) (569:569:569)) - (PORT datad (197:197:197) (220:220:220)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) (DELAY (ABSOLUTE - (PORT dataa (1137:1137:1137) (1174:1174:1174)) - (PORT datab (892:892:892) (949:949:949)) - (PORT datac (594:594:594) (616:616:616)) - (PORT datad (1248:1248:1248) (1323:1323:1323)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (908:908:908) (967:967:967)) + (PORT datab (1071:1071:1071) (1071:1071:1071)) + (PORT datac (1879:1879:1879) (1951:1951:1951)) + (PORT datad (834:834:834) (877:877:877)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (855:855:855)) - (PORT datab (1289:1289:1289) (1357:1357:1357)) - (PORT datac (596:596:596) (617:617:617)) - (PORT datad (331:331:331) (350:350:350)) + (PORT dataa (1322:1322:1322) (1324:1324:1324)) + (PORT datab (643:643:643) (673:673:673)) + (PORT datac (567:567:567) (590:590:590)) + (PORT datad (975:975:975) (969:969:969)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -12656,345 +7380,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (1765:1765:1765) (1762:1762:1762)) - (PORT datab (1517:1517:1517) (1602:1602:1602)) - (PORT datac (566:566:566) (587:587:587)) - (PORT datad (1608:1608:1608) (1642:1642:1642)) + (PORT dataa (634:634:634) (653:653:653)) + (PORT datad (324:324:324) (326:326:326)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1029:1029:1029) (1023:1023:1023)) - (PORT datab (852:852:852) (854:854:854)) - (PORT datac (2057:2057:2057) (2054:2054:2054)) - (PORT datad (1477:1477:1477) (1555:1555:1555)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1269:1269:1269)) - (PORT datab (860:860:860) (859:859:859)) - (PORT datac (2031:2031:2031) (2059:2059:2059)) - (PORT datad (1382:1382:1382) (1472:1472:1472)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (972:972:972)) - (PORT datab (821:821:821) (803:803:803)) - (PORT datac (188:188:188) (227:227:227)) - (PORT datad (184:184:184) (206:206:206)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (626:626:626)) - (PORT datab (1125:1125:1125) (1150:1150:1150)) - (PORT datac (1153:1153:1153) (1176:1176:1176)) - (PORT datad (526:526:526) (518:518:518)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (948:948:948)) - (PORT datab (1083:1083:1083) (1077:1077:1077)) - (PORT datac (1289:1289:1289) (1272:1272:1272)) - (PORT datad (834:834:834) (838:838:838)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (604:604:604)) - (PORT datab (849:849:849) (884:884:884)) - (PORT datac (1354:1354:1354) (1372:1372:1372)) - (PORT datad (1059:1059:1059) (1062:1062:1062)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (835:835:835)) - (PORT datab (1055:1055:1055) (1052:1052:1052)) - (PORT datac (331:331:331) (349:349:349)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (388:388:388) (390:390:390)) + (PORT datab (562:562:562) (553:553:553)) + (PORT datac (616:616:616) (633:633:633)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1144:1144:1144)) - (PORT datab (189:189:189) (225:225:225)) - (PORT datac (168:168:168) (204:204:204)) - (PORT datad (1881:1881:1881) (1925:1925:1925)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (188:188:188) (226:226:226)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (3401:3401:3401) (3385:3385:3385)) - (PORT datab (885:885:885) (944:944:944)) - (PORT datac (1137:1137:1137) (1176:1176:1176)) - (PORT datad (622:622:622) (645:645:645)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1921:1921:1921)) - (PORT datab (1365:1365:1365) (1354:1354:1354)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (1227:1227:1227) (1339:1339:1339)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (728:728:728)) - (PORT datab (201:201:201) (234:234:234)) - (PORT datac (1480:1480:1480) (1470:1470:1470)) - (PORT datad (1365:1365:1365) (1396:1396:1396)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (975:975:975)) - (PORT datab (718:718:718) (788:788:788)) - (PORT datac (1351:1351:1351) (1371:1371:1371)) - (PORT datad (585:585:585) (616:616:616)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1925:1925:1925)) - (PORT datab (1042:1042:1042) (1016:1016:1016)) - (PORT datac (801:801:801) (797:797:797)) - (PORT datad (618:618:618) (644:644:644)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (972:972:972)) - (PORT datab (702:702:702) (761:761:761)) - (PORT datac (1354:1354:1354) (1371:1371:1371)) - (PORT datad (824:824:824) (850:850:850)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1367:1367:1367) (1357:1357:1357)) - (PORT datac (959:959:959) (937:937:937)) - (PORT datad (563:563:563) (594:594:594)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (900:900:900)) - (PORT datab (1159:1159:1159) (1171:1171:1171)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (800:800:800) (801:801:801)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1609:1609:1609) (1650:1650:1650)) - (PORT datac (1264:1264:1264) (1262:1262:1262)) - (PORT datad (1570:1570:1570) (1629:1629:1629)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (591:591:591)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (988:988:988) (960:960:960)) - (PORT datad (776:776:776) (799:799:799)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (594:594:594)) - (PORT datab (1101:1101:1101) (1089:1089:1089)) - (PORT datac (471:471:471) (460:460:460)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (604:604:604) (616:616:616)) + (PORT datac (868:868:868) (863:863:863)) + (PORT datad (825:825:825) (816:816:816)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (947:947:947)) - (PORT datab (1367:1367:1367) (1425:1425:1425)) - (PORT datac (172:172:172) (211:211:211)) - (PORT datad (188:188:188) (218:218:218)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1466:1466:1466) (1590:1590:1590)) + (PORT datac (1435:1435:1435) (1490:1490:1490)) + (PORT datad (629:629:629) (665:665:665)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13005,11 +7439,39 @@ (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) (DELAY (ABSOLUTE - (PORT dataa (1288:1288:1288) (1384:1384:1384)) - (PORT datac (1127:1127:1127) (1135:1135:1135)) - (PORT datad (1220:1220:1220) (1329:1329:1329)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1439:1439:1439) (1490:1490:1490)) + (PORT datab (1247:1247:1247) (1286:1286:1286)) + (PORT datad (947:947:947) (1000:1000:1000)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (2734:2734:2734) (2748:2748:2748)) + (PORT datac (839:839:839) (872:872:872)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2240:2240:2240) (2326:2326:2326)) + (PORT datab (622:622:622) (629:629:629)) + (PORT datac (1159:1159:1159) (1195:1195:1195)) + (PORT datad (1230:1230:1230) (1267:1267:1267)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13019,28 +7481,28 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) (DELAY (ABSOLUTE - (PORT dataa (1288:1288:1288) (1379:1379:1379)) - (PORT datab (1533:1533:1533) (1540:1540:1540)) - (PORT datac (1615:1615:1615) (1652:1652:1652)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1147:1147:1147) (1169:1169:1169)) + (PORT datab (1175:1175:1175) (1204:1204:1204)) + (PORT datac (753:753:753) (733:733:733)) + (PORT datad (572:572:572) (587:587:587)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) (DELAY (ABSOLUTE - (PORT dataa (1287:1287:1287) (1382:1382:1382)) - (PORT datab (2376:2376:2376) (2487:2487:2487)) - (PORT datac (1112:1112:1112) (1127:1127:1127)) - (PORT datad (822:822:822) (830:830:830)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (652:652:652) (702:702:702)) + (PORT datac (1068:1068:1068) (1049:1049:1049)) + (PORT datad (1086:1086:1086) (1079:1079:1079)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13051,12 +7513,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) (DELAY (ABSOLUTE - (PORT dataa (1147:1147:1147) (1145:1145:1145)) - (PORT datab (571:571:571) (582:582:582)) - (PORT datac (189:189:189) (230:230:230)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (327:327:327) (345:345:345)) + (PORT datab (1031:1031:1031) (1010:1010:1010)) + (PORT datac (177:177:177) (209:209:209)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13064,30 +7526,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1570:1570:1570) (1563:1563:1563)) - (PORT datab (2395:2395:2395) (2500:2500:2500)) - (PORT datac (1523:1523:1523) (1614:1614:1614)) - (PORT datad (1465:1465:1465) (1420:1420:1420)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1192:1192:1192)) - (PORT datab (1013:1013:1013) (1018:1018:1018)) - (PORT datac (1466:1466:1466) (1538:1538:1538)) - (PORT datad (1362:1362:1362) (1362:1362:1362)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (1285:1285:1285) (1257:1257:1257)) + (PORT datab (1496:1496:1496) (1574:1574:1574)) + (PORT datac (835:835:835) (875:875:875)) + (PORT datad (602:602:602) (630:630:630)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13096,13 +7542,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) + (INSTANCE z80_\|pla_decode_\|Equal10\~1) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (1007:1007:1007) (1002:1002:1002)) - (PORT datad (199:199:199) (234:234:234)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT datac (1424:1424:1424) (1488:1488:1488)) + (PORT datad (1155:1155:1155) (1225:1225:1225)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1612:1612:1612)) + (PORT datab (1363:1363:1363) (1499:1499:1499)) + (PORT datac (1291:1291:1291) (1278:1278:1278)) + (PORT datad (173:173:173) (202:202:202)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (789:789:789)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (1347:1347:1347) (1372:1372:1372)) + (PORT datad (1016:1016:1016) (988:988:988)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13110,31 +7586,539 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) (DELAY (ABSOLUTE - (PORT dataa (1365:1365:1365) (1351:1351:1351)) - (PORT datab (1439:1439:1439) (1439:1439:1439)) - (PORT datac (1389:1389:1389) (1385:1385:1385)) - (PORT datad (1822:1822:1822) (1821:1821:1821)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (593:593:593) (588:588:588)) + (PORT datab (798:798:798) (797:797:797)) + (PORT datac (1519:1519:1519) (1543:1543:1543)) + (PORT datad (1389:1389:1389) (1398:1398:1398)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1751:1751:1751) (1749:1749:1749)) + (PORT datab (1532:1532:1532) (1505:1505:1505)) + (PORT datac (645:645:645) (674:674:674)) + (PORT datad (578:578:578) (607:607:607)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1492:1492:1492)) + (PORT datac (1219:1219:1219) (1263:1263:1263)) + (PORT datad (1314:1314:1314) (1324:1324:1324)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (809:809:809)) + (PORT datab (891:891:891) (900:900:900)) + (PORT datac (1749:1749:1749) (1732:1732:1732)) + (PORT datad (1078:1078:1078) (1132:1132:1132)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (756:756:756)) + (PORT datab (802:802:802) (788:788:788)) + (PORT datac (542:542:542) (539:539:539)) + (PORT datad (771:771:771) (766:766:766)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (243:243:243)) + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (774:774:774) (762:762:762)) + (PORT datad (1323:1323:1323) (1349:1349:1349)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1779:1779:1779) (1763:1763:1763)) + (PORT datab (1111:1111:1111) (1164:1164:1164)) + (PORT datac (800:800:800) (803:803:803)) + (PORT datad (777:777:777) (781:781:781)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (594:594:594) (610:610:610)) + (PORT datac (929:929:929) (916:916:916)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (991:991:991)) + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (666:666:666) (723:723:723)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (1011:1011:1011) (990:990:990)) + (PORT datad (973:973:973) (947:947:947)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (2393:2393:2393) (2410:2410:2410)) + (PORT datab (646:646:646) (660:660:660)) + (PORT datac (1356:1356:1356) (1370:1370:1370)) + (PORT datad (1229:1229:1229) (1260:1260:1260)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1976:1976:1976) (1966:1966:1966)) + (PORT datab (627:627:627) (677:677:677)) + (PORT datac (1025:1025:1025) (1023:1023:1023)) + (PORT datad (1250:1250:1250) (1224:1224:1224)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1067:1067:1067)) + (PORT datab (853:853:853) (844:844:844)) + (PORT datac (1083:1083:1083) (1068:1068:1068)) + (PORT datad (2201:2201:2201) (2158:2158:2158)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (902:902:902)) + (PORT datab (1737:1737:1737) (1817:1817:1817)) + (PORT datac (833:833:833) (869:869:869)) + (PORT datad (660:660:660) (716:716:716)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1529:1529:1529)) + (PORT datab (1460:1460:1460) (1494:1494:1494)) + (PORT datac (985:985:985) (971:971:971)) + (PORT datad (588:588:588) (598:598:598)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (412:412:412)) + (PORT datab (1351:1351:1351) (1384:1384:1384)) + (PORT datac (603:603:603) (624:624:624)) + (PORT datad (191:191:191) (220:220:220)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (608:608:608)) + (PORT datab (871:871:871) (869:869:869)) + (PORT datac (512:512:512) (499:499:499)) + (PORT datad (576:576:576) (567:567:567)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (798:798:798)) + (PORT datab (1280:1280:1280) (1263:1263:1263)) + (PORT datac (163:163:163) (199:199:199)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1911:1911:1911) (1944:1944:1944)) + (PORT datab (1430:1430:1430) (1481:1481:1481)) + (PORT datac (1061:1061:1061) (1065:1065:1065)) + (PORT datad (1453:1453:1453) (1436:1436:1436)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1018:1018:1018)) + (PORT datab (1394:1394:1394) (1376:1376:1376)) + (PORT datac (780:780:780) (773:773:773)) + (PORT datad (1052:1052:1052) (1037:1037:1037)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1259:1259:1259)) + (PORT datab (2244:2244:2244) (2292:2292:2292)) + (PORT datac (1064:1064:1064) (1064:1064:1064)) + (PORT datad (177:177:177) (208:208:208)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (648:648:648)) + (PORT datac (589:589:589) (594:594:594)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (843:843:843)) + (PORT datab (1699:1699:1699) (1742:1742:1742)) + (PORT datac (1382:1382:1382) (1393:1393:1393)) + (PORT datad (1554:1554:1554) (1548:1548:1548)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT datab (1065:1065:1065) (1039:1039:1039)) + (PORT datac (476:476:476) (462:462:462)) + (PORT datad (1017:1017:1017) (976:976:976)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) (DELAY (ABSOLUTE - (PORT dataa (869:869:869) (893:893:893)) - (PORT datab (639:639:639) (637:637:637)) - (PORT datac (583:583:583) (587:587:587)) - (PORT datad (178:178:178) (199:199:199)) + (PORT dataa (799:799:799) (783:783:783)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (166:166:166) (202:202:202)) + (PORT datad (822:822:822) (848:848:848)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (896:896:896)) + (PORT datab (1628:1628:1628) (1655:1655:1655)) + (PORT datac (864:864:864) (900:900:900)) + (PORT datad (1522:1522:1522) (1507:1507:1507)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1254:1254:1254) (1245:1245:1245)) + (PORT datab (1627:1627:1627) (1657:1657:1657)) + (PORT datac (1411:1411:1411) (1437:1437:1437)) + (PORT datad (1133:1133:1133) (1150:1150:1150)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1217:1217:1217)) + (PORT datab (678:678:678) (743:743:743)) + (PORT datac (892:892:892) (954:954:954)) + (PORT datad (912:912:912) (912:912:912)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (282:282:282)) + (PORT datab (186:186:186) (222:222:222)) + (PORT datad (1006:1006:1006) (971:971:971)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1533:1533:1533)) + (PORT datab (1463:1463:1463) (1503:1503:1503)) + (PORT datac (567:567:567) (590:590:590)) + (PORT datad (572:572:572) (597:597:597)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (895:895:895)) + (PORT datab (1739:1739:1739) (1817:1817:1817)) + (PORT datac (832:832:832) (869:869:869)) + (PORT datad (662:662:662) (717:717:717)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1420:1420:1420) (1427:1427:1427)) + (PORT datab (851:851:851) (859:859:859)) + (PORT datac (847:847:847) (848:848:848)) + (PORT datad (1669:1669:1669) (1701:1701:1701)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1077:1077:1077) (1041:1041:1041)) + (PORT datab (1704:1704:1704) (1732:1732:1732)) + (PORT datac (1098:1098:1098) (1119:1119:1119)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (634:634:634)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (768:768:768) (782:782:782)) + (PORT datad (496:496:496) (481:481:481)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1071:1071:1071)) + (PORT datab (1274:1274:1274) (1251:1251:1251)) + (PORT datac (1402:1402:1402) (1427:1427:1427)) + (PORT datad (996:996:996) (985:985:985)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13145,10 +8129,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (230:230:230)) - (PORT datab (609:609:609) (599:599:599)) - (PORT datac (828:828:828) (837:837:837)) - (PORT datad (854:854:854) (881:881:881)) + (PORT dataa (1238:1238:1238) (1184:1184:1184)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (573:573:573) (585:585:585)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -13161,179 +8145,9 @@ (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) (DELAY (ABSOLUTE - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (1249:1249:1249) (1220:1220:1220)) - (PORT datad (764:764:764) (757:757:757)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (804:804:804)) - (PORT datab (1003:1003:1003) (1003:1003:1003)) - (PORT datac (485:485:485) (472:472:472)) - (PORT datad (489:489:489) (477:477:477)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1267:1267:1267)) - (PORT datab (2060:2060:2060) (2091:2091:2091)) - (PORT datac (1278:1278:1278) (1385:1385:1385)) - (PORT datad (834:834:834) (826:826:826)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1099:1099:1099)) - (PORT datab (1104:1104:1104) (1147:1147:1147)) - (PORT datac (820:820:820) (830:830:830)) - (PORT datad (1124:1124:1124) (1140:1140:1140)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (877:877:877)) - (PORT datab (854:854:854) (860:860:860)) - (PORT datac (1110:1110:1110) (1126:1126:1126)) - (PORT datad (541:541:541) (538:538:538)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1235:1235:1235)) - (PORT datab (1631:1631:1631) (1634:1634:1634)) - (PORT datac (722:722:722) (759:759:759)) - (PORT datad (1973:1973:1973) (1910:1910:1910)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1042:1042:1042)) - (PORT datab (1139:1139:1139) (1156:1156:1156)) - (PORT datad (841:841:841) (870:870:870)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (888:888:888)) - (PORT datab (624:624:624) (621:621:621)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (800:800:800) (796:796:796)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (1071:1071:1071) (1065:1065:1065)) - (PORT datac (183:183:183) (220:220:220)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (622:622:622)) - (PORT datab (316:316:316) (336:336:336)) - (PORT datac (1070:1070:1070) (1054:1054:1054)) - (PORT datad (871:871:871) (879:879:879)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1041:1041:1041)) - (PORT datab (610:610:610) (640:640:640)) - (PORT datac (840:840:840) (845:845:845)) - (PORT datad (764:764:764) (754:754:754)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (241:241:241)) - (PORT datab (215:215:215) (259:259:259)) - (PORT datac (190:190:190) (231:231:231)) + (PORT dataa (203:203:203) (241:241:241)) + (PORT datab (360:360:360) (365:365:365)) + (PORT datac (821:821:821) (807:807:807)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -13342,47 +8156,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) (DELAY (ABSOLUTE - (PORT dataa (1207:1207:1207) (1213:1213:1213)) - (PORT datab (1872:1872:1872) (1914:1914:1914)) - (PORT datac (1809:1809:1809) (1847:1847:1847)) - (PORT datad (1204:1204:1204) (1236:1236:1236)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (773:773:773) (847:847:847)) + (PORT datab (814:814:814) (798:798:798)) + (PORT datac (986:986:986) (986:986:986)) + (PORT datad (1012:1012:1012) (1029:1029:1029)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1119:1119:1119)) - (PORT datab (1122:1122:1122) (1132:1132:1132)) - (PORT datac (966:966:966) (942:942:942)) - (PORT datad (290:290:290) (297:297:297)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1978:1978:1978) (2041:2041:2041)) - (PORT datab (1564:1564:1564) (1667:1667:1667)) - (PORT datac (553:553:553) (549:549:549)) - (PORT datad (1865:1865:1865) (1883:1883:1883)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (859:859:859) (864:864:864)) + (PORT datab (1316:1316:1316) (1298:1298:1298)) + (PORT datac (1530:1530:1530) (1505:1505:1505)) + (PORT datad (1375:1375:1375) (1381:1381:1381)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13390,141 +8188,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (1923:1923:1923) (1915:1915:1915)) - (PORT datab (1098:1098:1098) (1116:1116:1116)) - (PORT datac (1337:1337:1337) (1316:1316:1316)) - (PORT datad (1270:1270:1270) (1276:1276:1276)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (825:825:825)) - (PORT datab (631:631:631) (639:639:639)) - (PORT datac (1631:1631:1631) (1624:1624:1624)) - (PORT datad (1627:1627:1627) (1620:1620:1620)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1325:1325:1325)) - (PORT datab (846:846:846) (842:842:842)) - (PORT datac (1336:1336:1336) (1363:1363:1363)) - (PORT datad (782:782:782) (779:779:779)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (860:860:860)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (581:581:581) (596:596:596)) - (PORT datad (553:553:553) (573:573:573)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (814:814:814)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (751:751:751) (750:750:750)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (616:616:616)) - (PORT datab (606:606:606) (632:632:632)) - (PORT datac (590:590:590) (609:609:609)) - (PORT datad (323:323:323) (326:326:326)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1167:1167:1167)) - (PORT datab (1149:1149:1149) (1141:1141:1141)) - (PORT datac (584:584:584) (599:599:599)) - (PORT datad (1112:1112:1112) (1101:1101:1101)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (883:883:883) (872:872:872)) - (PORT datad (574:574:574) (584:584:584)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2178:2178:2178) (2226:2226:2226)) - (PORT datab (905:905:905) (916:916:916)) - (PORT datac (1006:1006:1006) (983:983:983)) - (PORT datad (1637:1637:1637) (1699:1699:1699)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1157:1157:1157) (1181:1181:1181)) + (PORT datab (877:877:877) (884:884:884)) + (PORT datac (1020:1020:1020) (1023:1023:1023)) + (PORT datad (1805:1805:1805) (1805:1805:1805)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13532,215 +8204,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (830:830:830) (817:817:817)) - (PORT datac (1105:1105:1105) (1098:1098:1098)) - (PORT datad (1334:1334:1334) (1324:1324:1324)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datac (1564:1564:1564) (1560:1560:1560)) + (PORT dataa (998:998:998) (1031:1031:1031)) + (PORT datab (849:849:849) (883:883:883)) + (PORT datac (1020:1020:1020) (1022:1022:1022)) + (PORT datad (2095:2095:2095) (2073:2073:2073)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (599:599:599)) - (PORT datab (540:540:540) (539:539:539)) - (PORT datac (1371:1371:1371) (1397:1397:1397)) - (PORT datad (1516:1516:1516) (1493:1493:1493)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1185:1185:1185)) - (PORT datab (1078:1078:1078) (1064:1064:1064)) - (PORT datac (848:848:848) (873:873:873)) - (PORT datad (295:295:295) (293:293:293)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (973:973:973) (934:934:934)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1667:1667:1667)) - (PORT datab (835:835:835) (875:875:875)) - (PORT datac (1116:1116:1116) (1125:1125:1125)) - (PORT datad (2260:2260:2260) (2349:2349:2349)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (621:621:621) (610:610:610)) - (PORT datac (166:166:166) (202:202:202)) - (PORT datad (174:174:174) (201:201:201)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1117:1117:1117) (1155:1155:1155)) - (PORT datab (1474:1474:1474) (1568:1568:1568)) - (PORT datac (1396:1396:1396) (1463:1463:1463)) - (PORT datad (1638:1638:1638) (1670:1670:1670)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1922:1922:1922) (1914:1914:1914)) - (PORT datab (1176:1176:1176) (1201:1201:1201)) - (PORT datac (1386:1386:1386) (1381:1381:1381)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (378:378:378)) - (PORT datab (1176:1176:1176) (1202:1202:1202)) - (PORT datac (1067:1067:1067) (1061:1061:1061)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (244:244:244)) - (PORT datab (561:561:561) (562:562:562)) - (PORT datac (1264:1264:1264) (1263:1263:1263)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (645:645:645)) - (PORT datab (888:888:888) (899:899:899)) - (PORT datac (1386:1386:1386) (1384:1384:1384)) - (PORT datad (1093:1093:1093) (1120:1120:1120)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (1353:1353:1353) (1330:1330:1330)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1237:1237:1237)) - (PORT datab (1103:1103:1103) (1133:1133:1133)) - (PORT datac (1392:1392:1392) (1384:1384:1384)) - (PORT datad (596:596:596) (611:611:611)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13748,285 +8220,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (1139:1139:1139) (1164:1164:1164)) - (PORT datac (1389:1389:1389) (1387:1387:1387)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1293:1293:1293)) - (PORT datab (1563:1563:1563) (1654:1654:1654)) - (PORT datac (908:908:908) (871:871:871)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1058:1058:1058)) - (PORT datab (617:617:617) (629:629:629)) - (PORT datac (586:586:586) (601:601:601)) - (PORT datad (591:591:591) (602:602:602)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1542:1542:1542) (1544:1544:1544)) - (PORT datab (1279:1279:1279) (1252:1252:1252)) - (PORT datac (1037:1037:1037) (1044:1044:1044)) - (PORT datad (571:571:571) (573:573:573)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1095:1095:1095)) - (PORT datab (1284:1284:1284) (1260:1260:1260)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (620:620:620) (612:612:612)) - (PORT datac (169:169:169) (207:207:207)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (340:340:340)) - (PORT datab (748:748:748) (727:727:727)) - (PORT datac (1315:1315:1315) (1318:1318:1318)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1525:1525:1525) (1508:1508:1508)) - (PORT datab (1154:1154:1154) (1204:1204:1204)) - (PORT datac (1386:1386:1386) (1381:1381:1381)) - (PORT datad (1899:1899:1899) (1879:1879:1879)) - (IOPATH dataa combout (307:307:307) (323:323:323)) + (PORT dataa (214:214:214) (258:258:258)) + (PORT datab (188:188:188) (222:222:222)) + (PORT datac (516:516:516) (502:502:502)) + (PORT datad (162:162:162) (188:188:188)) + (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1663:1663:1663) (1705:1705:1705)) - (PORT datab (1470:1470:1470) (1565:1565:1565)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (1503:1503:1503) (1469:1469:1469)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1419:1419:1419) (1416:1416:1416)) - (PORT datab (1622:1622:1622) (1635:1635:1635)) - (PORT datac (1407:1407:1407) (1403:1403:1403)) - (PORT datad (314:314:314) (314:314:314)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (673:673:673)) - (PORT datab (851:851:851) (861:861:861)) - (PORT datac (1593:1593:1593) (1608:1608:1608)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1418:1418:1418) (1413:1413:1413)) - (PORT datab (1028:1028:1028) (1008:1008:1008)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1752:1752:1752) (1755:1755:1755)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (671:671:671)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (1000:1000:1000) (984:984:984)) - (PORT datad (1559:1559:1559) (1528:1528:1528)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1350:1350:1350)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (592:592:592) (583:583:583)) - (PORT datad (1757:1757:1757) (1760:1760:1760)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (608:608:608)) - (PORT datab (571:571:571) (573:573:573)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1332:1332:1332) (1325:1325:1325)) - (PORT datab (907:907:907) (903:903:903)) - (PORT datac (1107:1107:1107) (1119:1119:1119)) - (PORT datad (1095:1095:1095) (1094:1094:1094)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1070:1070:1070)) - (PORT datab (1068:1068:1068) (1054:1054:1054)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) (DELAY (ABSOLUTE - (PORT dataa (1618:1618:1618) (1635:1635:1635)) - (PORT datab (1300:1300:1300) (1292:1292:1292)) - (PORT datac (1111:1111:1111) (1137:1137:1137)) - (PORT datad (1390:1390:1390) (1393:1393:1393)) + (PORT dataa (864:864:864) (863:863:863)) + (PORT datab (834:834:834) (828:828:828)) + (PORT datac (1094:1094:1094) (1113:1113:1113)) + (PORT datad (1294:1294:1294) (1259:1259:1259)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14039,12 +8255,60 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) (DELAY (ABSOLUTE - (PORT dataa (1616:1616:1616) (1631:1631:1631)) - (PORT datab (1302:1302:1302) (1296:1296:1296)) - (PORT datac (1369:1369:1369) (1351:1351:1351)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (1418:1418:1418) (1424:1424:1424)) + (PORT datab (1330:1330:1330) (1293:1293:1293)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (840:840:840) (826:826:826)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1477:1477:1477)) + (PORT datab (1202:1202:1202) (1157:1157:1157)) + (PORT datac (1626:1626:1626) (1654:1654:1654)) + (PORT datad (587:587:587) (610:610:610)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (1506:1506:1506) (1559:1559:1559)) + (PORT datab (1581:1581:1581) (1595:1595:1595)) + (PORT datac (1015:1015:1015) (1019:1019:1019)) + (PORT datad (1596:1596:1596) (1612:1612:1612)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1049:1049:1049)) + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (1036:1036:1036) (1053:1053:1053)) + (PORT datad (746:746:746) (731:731:731)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14055,10 +8319,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) (DELAY (ABSOLUTE - (PORT dataa (1157:1157:1157) (1193:1193:1193)) - (PORT datab (1431:1431:1431) (1434:1434:1434)) - (PORT datac (854:854:854) (888:888:888)) - (PORT datad (888:888:888) (900:900:900)) + (PORT dataa (1055:1055:1055) (1064:1064:1064)) + (PORT datab (628:628:628) (647:647:647)) + (PORT datac (1038:1038:1038) (1040:1040:1040)) + (PORT datad (1027:1027:1027) (1021:1021:1021)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14071,44 +8335,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) (DELAY (ABSOLUTE - (PORT dataa (1102:1102:1102) (1106:1106:1106)) - (PORT datab (923:923:923) (932:932:932)) - (PORT datac (850:850:850) (883:883:883)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (865:865:865)) - (PORT datab (1768:1768:1768) (1854:1854:1854)) - (PORT datac (1747:1747:1747) (1840:1840:1840)) - (PORT datad (982:982:982) (971:971:971)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1168:1168:1168)) - (PORT datab (1134:1134:1134) (1122:1122:1122)) - (PORT datac (786:786:786) (771:771:771)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1051:1051:1051) (1056:1056:1056)) + (PORT datab (1022:1022:1022) (1010:1010:1010)) + (PORT datac (1038:1038:1038) (1035:1035:1035)) + (PORT datad (162:162:162) (187:187:187)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14119,12 +8351,76 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (570:570:570) (576:576:576)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (343:343:343) (362:362:362)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (715:715:715) (700:700:700)) + (PORT datad (563:563:563) (561:561:561)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1368:1368:1368) (1374:1374:1374)) + (PORT datab (853:853:853) (849:849:849)) + (PORT datac (1556:1556:1556) (1570:1570:1570)) + (PORT datad (879:879:879) (939:939:939)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (853:853:853)) + (PORT datab (1481:1481:1481) (1515:1515:1515)) + (PORT datac (568:568:568) (609:609:609)) + (PORT datad (826:826:826) (825:825:825)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (657:657:657)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (791:791:791) (799:799:799)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (280:280:280)) + (PORT datab (1550:1550:1550) (1552:1552:1552)) + (PORT datac (1787:1787:1787) (1791:1791:1791)) + (PORT datad (323:323:323) (316:316:316)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14135,10 +8431,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (842:842:842) (838:838:838)) - (PORT datab (810:810:810) (829:829:829)) - (PORT datac (596:596:596) (607:607:607)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (1020:1020:1020) (1023:1023:1023)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (916:916:916) (879:879:879)) + (PORT datad (178:178:178) (199:199:199)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -14148,15 +8444,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~50) (DELAY (ABSOLUTE - (PORT dataa (2681:2681:2681) (2642:2642:2642)) - (PORT datab (970:970:970) (1002:1002:1002)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (2383:2383:2383) (2407:2407:2407)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (973:973:973) (1039:1039:1039)) + (PORT datab (1364:1364:1364) (1382:1382:1382)) + (PORT datac (521:521:521) (512:512:512)) + (PORT datad (817:817:817) (823:823:823)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14164,15 +8460,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) (DELAY (ABSOLUTE - (PORT dataa (1123:1123:1123) (1123:1123:1123)) - (PORT datab (1023:1023:1023) (1010:1010:1010)) - (PORT datac (1256:1256:1256) (1242:1242:1242)) - (PORT datad (1112:1112:1112) (1101:1101:1101)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1168:1168:1168) (1232:1232:1232)) + (PORT datab (841:841:841) (822:822:822)) + (PORT datac (1092:1092:1092) (1087:1087:1087)) + (PORT datad (1084:1084:1084) (1046:1046:1046)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14180,15 +8476,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) (DELAY (ABSOLUTE - (PORT dataa (1282:1282:1282) (1288:1288:1288)) - (PORT datab (575:575:575) (594:594:594)) - (PORT datac (569:569:569) (573:573:573)) - (PORT datad (643:643:643) (684:684:684)) + (PORT dataa (1273:1273:1273) (1309:1309:1309)) + (PORT datab (594:594:594) (626:626:626)) + (PORT datac (1160:1160:1160) (1200:1200:1200)) + (PORT datad (585:585:585) (597:597:597)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1394:1394:1394) (1403:1403:1403)) + (PORT datab (1143:1143:1143) (1154:1154:1154)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (1046:1046:1046) (1058:1058:1058)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (750:750:750) (746:746:746)) + (PORT datad (312:312:312) (312:312:312)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1320:1320:1320)) + (PORT datab (846:846:846) (879:879:879)) + (PORT datac (1530:1530:1530) (1509:1509:1509)) + (PORT datad (1375:1375:1375) (1382:1382:1382)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (857:857:857)) + (PORT datab (1117:1117:1117) (1149:1149:1149)) + (PORT datac (868:868:868) (872:872:872)) + (PORT datad (845:845:845) (857:857:857)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14196,13 +8552,535 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (804:804:804)) - (PORT datab (822:822:822) (822:822:822)) - (PORT datac (1885:1885:1885) (1859:1859:1859)) - (PORT datad (759:759:759) (758:758:758)) + (PORT dataa (562:562:562) (584:584:584)) + (PORT datab (834:834:834) (832:832:832)) + (PORT datac (845:845:845) (845:845:845)) + (PORT datad (1667:1667:1667) (1702:1702:1702)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (787:787:787) (801:801:801)) + (PORT datac (583:583:583) (597:597:597)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (741:741:741)) + (PORT datab (1380:1380:1380) (1406:1406:1406)) + (PORT datac (1181:1181:1181) (1255:1255:1255)) + (PORT datad (850:850:850) (857:857:857)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (751:751:751)) + (PORT datab (843:843:843) (874:874:874)) + (PORT datac (750:750:750) (745:745:745)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (870:870:870)) + (PORT datab (1338:1338:1338) (1358:1358:1358)) + (PORT datac (1150:1150:1150) (1177:1177:1177)) + (PORT datad (967:967:967) (940:940:940)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (1475:1475:1475) (1456:1456:1456)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~51) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (361:361:361)) + (PORT datab (1999:1999:1999) (2059:2059:2059)) + (PORT datac (1419:1419:1419) (1477:1477:1477)) + (PORT datad (1624:1624:1624) (1649:1649:1649)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (1104:1104:1104) (1125:1125:1125)) + (PORT datac (1041:1041:1041) (1048:1048:1048)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (1447:1447:1447) (1505:1505:1505)) + (PORT datac (325:325:325) (339:339:339)) + (PORT datad (1651:1651:1651) (1672:1672:1672)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1477:1477:1477)) + (PORT datab (1549:1549:1549) (1555:1555:1555)) + (PORT datac (575:575:575) (599:599:599)) + (PORT datad (1444:1444:1444) (1496:1496:1496)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (541:541:541) (537:537:537)) + (PORT datad (173:173:173) (201:201:201)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1714:1714:1714) (1753:1753:1753)) + (PORT datab (819:819:819) (820:820:820)) + (PORT datac (2187:2187:2187) (2248:2248:2248)) + (PORT datad (307:307:307) (315:315:315)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1463:1463:1463)) + (PORT datab (1112:1112:1112) (1106:1106:1106)) + (PORT datac (771:771:771) (762:762:762)) + (PORT datad (289:289:289) (297:297:297)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (647:647:647) (649:649:649)) + (PORT datac (529:529:529) (521:521:521)) + (PORT datad (817:817:817) (820:820:820)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (956:956:956)) + (PORT datab (647:647:647) (657:657:657)) + (PORT datac (560:560:560) (589:589:589)) + (PORT datad (1055:1055:1055) (1049:1049:1049)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (657:657:657)) + (PORT datab (1285:1285:1285) (1267:1267:1267)) + (PORT datac (1204:1204:1204) (1164:1164:1164)) + (PORT datad (1084:1084:1084) (1103:1103:1103)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1070:1070:1070)) + (PORT datab (1033:1033:1033) (1022:1022:1022)) + (PORT datac (1400:1400:1400) (1425:1425:1425)) + (PORT datad (1048:1048:1048) (1037:1037:1037)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (1273:1273:1273) (1248:1248:1248)) + (PORT datac (589:589:589) (627:627:627)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1150:1150:1150)) + (PORT datab (1159:1159:1159) (1142:1142:1142)) + (PORT datac (762:762:762) (749:749:749)) + (PORT datad (980:980:980) (971:971:971)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (848:848:848) (852:852:852)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1270:1270:1270)) + (PORT datab (1415:1415:1415) (1447:1447:1447)) + (PORT datac (781:781:781) (780:780:780)) + (PORT datad (935:935:935) (968:968:968)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1011:1011:1011)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (1312:1312:1312) (1297:1297:1297)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (855:855:855)) + (PORT datab (630:630:630) (638:638:638)) + (PORT datac (549:549:549) (543:543:543)) + (PORT datad (601:601:601) (592:592:592)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (226:226:226)) + (PORT datab (192:192:192) (230:230:230)) + (PORT datac (543:543:543) (536:536:536)) + (PORT datad (168:168:168) (195:195:195)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (523:523:523)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (716:716:716) (713:713:713)) + (PORT datad (783:783:783) (764:764:764)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1015:1015:1015)) + (PORT datab (698:698:698) (705:705:705)) + (PORT datac (1598:1598:1598) (1590:1590:1590)) + (PORT datad (1258:1258:1258) (1225:1225:1225)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1909:1909:1909) (1956:1956:1956)) + (PORT datab (1282:1282:1282) (1254:1254:1254)) + (PORT datac (1645:1645:1645) (1677:1677:1677)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1015:1015:1015)) + (PORT datab (876:876:876) (869:869:869)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (660:660:660) (671:671:671)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (597:597:597)) + (PORT datab (1410:1410:1410) (1443:1443:1443)) + (PORT datac (849:849:849) (843:843:843)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1677:1677:1677)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (873:873:873) (871:871:871)) + (PORT datad (936:936:936) (974:974:974)) + (IOPATH dataa combout (307:307:307) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1410:1410:1410) (1445:1445:1445)) + (PORT datac (1612:1612:1612) (1639:1639:1639)) + (PORT datad (780:780:780) (774:774:774)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (564:564:564)) + (PORT datab (1350:1350:1350) (1345:1345:1345)) + (PORT datac (876:876:876) (873:873:873)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (837:837:837) (843:843:843)) + (PORT datad (543:543:543) (543:543:543)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (815:815:815)) + (PORT datab (1084:1084:1084) (1101:1101:1101)) + (PORT datac (1251:1251:1251) (1246:1246:1246)) + (PORT datad (1248:1248:1248) (1234:1234:1234)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14212,42 +9090,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (2177:2177:2177) (2222:2222:2222)) - (PORT datab (907:907:907) (916:916:916)) - (PORT datac (1739:1739:1739) (1694:1694:1694)) - (PORT datad (1640:1640:1640) (1700:1700:1700)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1090:1090:1090) (1113:1113:1113)) - (PORT datad (1576:1576:1576) (1610:1610:1610)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1887:1887:1887) (1922:1922:1922)) - (PORT datab (615:615:615) (601:601:601)) - (PORT datac (802:802:802) (798:798:798)) - (PORT datad (618:618:618) (645:645:645)) - (IOPATH dataa combout (265:265:265) (273:273:273)) + (PORT dataa (874:874:874) (898:898:898)) + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (861:861:861) (882:882:882)) + (PORT datad (205:205:205) (244:244:244)) + (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -14256,29 +9106,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~17) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (803:803:803) (786:786:786)) - (PORT datad (317:317:317) (320:320:320)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (797:797:797) (795:795:795)) + (PORT datab (1443:1443:1443) (1466:1466:1466)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (1186:1186:1186) (1222:1222:1222)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (1738:1738:1738) (1841:1841:1841)) - (PORT datab (1394:1394:1394) (1426:1426:1426)) - (PORT datac (1120:1120:1120) (1137:1137:1137)) - (PORT datad (567:567:567) (579:579:579)) + (PORT dataa (1896:1896:1896) (1887:1887:1887)) + (PORT datab (654:654:654) (681:681:681)) + (PORT datac (1804:1804:1804) (1763:1763:1763)) + (PORT datad (1224:1224:1224) (1199:1199:1199)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (285:285:285)) + (PORT datab (580:580:580) (594:594:594)) + (PORT datac (1783:1783:1783) (1787:1787:1787)) + (PORT datad (1525:1525:1525) (1519:1519:1519)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1574:1574:1574) (1547:1547:1547)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (810:810:810) (825:825:825)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (598:598:598)) + (PORT datab (198:198:198) (232:232:232)) + (PORT datac (172:172:172) (214:214:214)) + (PORT datad (165:165:165) (191:191:191)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14288,80 +9186,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (201:201:201) (236:236:236)) - (PORT datac (550:550:550) (544:544:544)) - (PORT datad (773:773:773) (777:777:777)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1497:1497:1497)) - (PORT datab (936:936:936) (1002:1002:1002)) - (PORT datac (2072:2072:2072) (2153:2153:2153)) - (PORT datad (588:588:588) (588:588:588)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (353:353:353)) - (PORT datab (818:818:818) (847:847:847)) - (PORT datac (2032:2032:2032) (2055:2055:2055)) - (PORT datad (1080:1080:1080) (1077:1077:1077)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (585:585:585)) - (PORT datab (568:568:568) (580:580:580)) - (PORT datac (1007:1007:1007) (982:982:982)) - (PORT datad (1331:1331:1331) (1320:1320:1320)) + (PORT dataa (1011:1011:1011) (1021:1021:1021)) + (PORT datab (1116:1116:1116) (1128:1128:1128)) + (PORT datac (822:822:822) (838:838:838)) + (PORT datad (1357:1357:1357) (1371:1371:1371)) (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (918:918:918)) - (PORT datab (1225:1225:1225) (1199:1199:1199)) - (PORT datac (1307:1307:1307) (1298:1298:1298)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14371,1242 +9205,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) (DELAY (ABSOLUTE - (PORT dataa (1078:1078:1078) (1080:1080:1080)) - (PORT datab (844:844:844) (841:841:841)) - (PORT datac (580:580:580) (577:577:577)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1373:1373:1373) (1352:1352:1352)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (292:292:292) (299:299:299)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (844:844:844)) - (PORT datab (193:193:193) (231:231:231)) - (PORT datac (556:556:556) (560:560:560)) - (PORT datad (1328:1328:1328) (1338:1338:1338)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (870:870:870)) - (PORT datab (891:891:891) (910:910:910)) - (PORT datac (714:714:714) (694:694:694)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (593:593:593)) - (PORT datab (1736:1736:1736) (1689:1689:1689)) - (PORT datac (875:875:875) (877:877:877)) - (PORT datad (1155:1155:1155) (1170:1170:1170)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (537:537:537) (548:548:548)) - (PORT datad (1001:1001:1001) (990:990:990)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (352:352:352)) - (PORT datab (589:589:589) (606:606:606)) - (PORT datac (560:560:560) (568:568:568)) - (PORT datad (570:570:570) (580:580:580)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (855:855:855)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (154:154:154) (185:185:185)) - (PORT datad (1041:1041:1041) (1035:1035:1035)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (816:816:816)) - (PORT datab (2049:2049:2049) (2133:2133:2133)) - (PORT datac (1145:1145:1145) (1231:1231:1231)) - (PORT datad (2588:2588:2588) (2680:2680:2680)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (554:554:554)) - (PORT datab (631:631:631) (656:656:656)) - (PORT datac (867:867:867) (886:886:886)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (564:564:564)) - (PORT datac (826:826:826) (804:804:804)) - (PORT datad (775:775:775) (762:762:762)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1850:1850:1850) (1840:1840:1840)) - (PORT datab (340:340:340) (348:348:348)) - (PORT datad (818:818:818) (819:819:819)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1376:1376:1376)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1325:1325:1325) (1313:1313:1313)) - (PORT datab (1115:1115:1115) (1111:1111:1111)) - (PORT datac (792:792:792) (817:817:817)) - (PORT datad (1282:1282:1282) (1230:1230:1230)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1630:1630:1630)) - (PORT datac (577:577:577) (601:601:601)) - (PORT datad (1307:1307:1307) (1339:1339:1339)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1084:1084:1084) (1145:1145:1145)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1376:1376:1376)) - (PORT datab (600:600:600) (622:622:622)) - (PORT datad (1511:1511:1511) (1576:1576:1576)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1218:1218:1218)) - (PORT datab (836:836:836) (834:834:834)) - (PORT datac (1331:1331:1331) (1344:1344:1344)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1358:1358:1358) (1380:1380:1380)) - (PORT datac (817:817:817) (829:829:829)) - (PORT datad (1133:1133:1133) (1178:1178:1178)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (934:934:934) (941:941:941)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1237:1237:1237)) - (PORT datab (833:833:833) (830:830:830)) - (PORT datac (1333:1333:1333) (1346:1346:1346)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (936:936:936) (944:944:944)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1362:1362:1362) (1373:1373:1373)) - (PORT datac (819:819:819) (829:829:829)) - (PORT datad (1126:1126:1126) (1172:1172:1172)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (880:880:880)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (838:838:838) (838:838:838)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (754:754:754)) - (PORT datab (225:225:225) (296:296:296)) - (PORT datac (727:727:727) (707:707:707)) - (PORT datad (179:179:179) (214:214:214)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1357:1357:1357) (1374:1374:1374)) - (PORT datac (792:792:792) (804:804:804)) - (PORT datad (1131:1131:1131) (1179:1179:1179)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (753:753:753)) - (PORT datab (202:202:202) (245:245:245)) - (PORT datac (726:726:726) (705:705:705)) - (PORT datad (204:204:204) (264:264:264)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1360:1360:1360) (1371:1371:1371)) - (PORT datac (782:782:782) (792:792:792)) - (PORT datad (1127:1127:1127) (1175:1175:1175)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1363:1363:1363) (1375:1375:1375)) - (PORT datac (792:792:792) (802:802:802)) - (PORT datad (1137:1137:1137) (1188:1188:1188)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1308:1308:1308) (1329:1329:1329)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1360:1360:1360) (1375:1375:1375)) - (PORT datac (780:780:780) (793:793:793)) - (PORT datad (1131:1131:1131) (1180:1180:1180)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1306:1306:1306) (1327:1327:1327)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (940:940:940)) - (PORT datab (891:891:891) (922:922:922)) - (PORT datad (327:327:327) (366:366:366)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (785:785:785) (828:828:828)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1367:1367:1367) (1357:1357:1357)) - (PORT datab (1119:1119:1119) (1117:1117:1117)) - (PORT datac (1612:1612:1612) (1654:1654:1654)) - (PORT datad (1352:1352:1352) (1371:1371:1371)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (1488:1488:1488) (1556:1556:1556)) - (PORT datac (1015:1015:1015) (1009:1009:1009)) - (PORT datad (324:324:324) (334:334:334)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (1485:1485:1485) (1552:1552:1552)) - (PORT datac (1013:1013:1013) (1008:1008:1008)) - (PORT datad (321:321:321) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datab (1484:1484:1484) (1552:1552:1552)) - (PORT datad (1603:1603:1603) (1601:1601:1601)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1370:1370:1370) (1357:1357:1357)) - (PORT datab (1643:1643:1643) (1684:1684:1684)) - (PORT datac (312:312:312) (322:322:322)) - (PORT datad (1082:1082:1082) (1081:1081:1081)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1298:1298:1298) (1328:1328:1328)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datab (1483:1483:1483) (1550:1550:1550)) - (PORT datac (1014:1014:1014) (1004:1004:1004)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1342:1342:1342)) - (PORT datab (342:342:342) (364:364:364)) - (PORT datac (1616:1616:1616) (1661:1661:1661)) - (PORT datad (1075:1075:1075) (1073:1073:1073)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (487:487:487)) - (PORT datab (460:460:460) (489:489:489)) - (PORT datad (590:590:590) (590:590:590)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (559:559:559) (578:578:578)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1314:1314:1314)) - (PORT datab (1115:1115:1115) (1111:1111:1111)) - (PORT datac (316:316:316) (327:327:327)) - (PORT datad (1283:1283:1283) (1231:1231:1231)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1355:1355:1355)) - (PORT datab (337:337:337) (358:358:358)) - (PORT datac (1299:1299:1299) (1287:1287:1287)) - (PORT datad (1080:1080:1080) (1080:1080:1080)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (626:626:626)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (190:190:190) (217:217:217)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1886:1886:1886)) - (PORT datab (1292:1292:1292) (1361:1361:1361)) - (PORT datac (1908:1908:1908) (1990:1990:1990)) - (PORT datad (812:812:812) (824:824:824)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (974:974:974)) - (PORT datab (1174:1174:1174) (1201:1201:1201)) - (PORT datac (1779:1779:1779) (1760:1760:1760)) - (PORT datad (339:339:339) (340:340:340)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datac (548:548:548) (563:563:563)) - (PORT datad (763:763:763) (756:756:756)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (641:641:641)) - (PORT datab (196:196:196) (239:239:239)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (804:804:804) (787:787:787)) - (PORT datad (592:592:592) (603:603:603)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (926:926:926)) - (PORT datac (848:848:848) (859:859:859)) - (PORT datad (1123:1123:1123) (1140:1140:1140)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (877:877:877) (889:889:889)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (919:919:919)) - (PORT datac (847:847:847) (856:856:856)) - (PORT datad (1117:1117:1117) (1135:1135:1135)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (292:292:292)) - (PORT datab (887:887:887) (915:915:915)) - (PORT datad (806:806:806) (819:819:819)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1352:1352:1352)) - (PORT datab (1118:1118:1118) (1119:1119:1119)) - (PORT datac (310:310:310) (330:330:330)) - (PORT datad (536:536:536) (568:568:568)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1352:1352:1352)) - (PORT datab (564:564:564) (605:605:605)) - (PORT datac (313:313:313) (324:324:324)) - (PORT datad (1078:1078:1078) (1083:1083:1083)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1320:1320:1320) (1353:1353:1353)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1362:1362:1362) (1351:1351:1351)) - (PORT datab (561:561:561) (603:603:603)) - (PORT datac (315:315:315) (326:326:326)) - (PORT datad (1073:1073:1073) (1078:1078:1078)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1325:1325:1325) (1359:1359:1359)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1367:1367:1367) (1356:1356:1356)) - (PORT datab (1119:1119:1119) (1116:1116:1116)) - (PORT datac (309:309:309) (330:330:330)) - (PORT datad (536:536:536) (565:565:565)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (619:619:619)) - (PORT datab (222:222:222) (292:292:292)) - (PORT datad (598:598:598) (595:595:595)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1313:1313:1313)) - (PORT datab (1119:1119:1119) (1117:1117:1117)) - (PORT datac (794:794:794) (819:819:819)) - (PORT datad (1286:1286:1286) (1232:1232:1232)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1382:1382:1382)) - (PORT datab (832:832:832) (820:820:820)) - (PORT datad (1521:1521:1521) (1583:1583:1583)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1486:1486:1486) (1500:1500:1500)) - (PORT datac (825:825:825) (830:830:830)) - (PORT datad (191:191:191) (217:217:217)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1556:1556:1556) (1553:1553:1553)) - (PORT datab (368:368:368) (370:370:370)) - (PORT datac (163:163:163) (199:199:199)) - (PORT datad (824:824:824) (803:803:803)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1379:1379:1379)) - (PORT datab (837:837:837) (825:825:825)) - (PORT datad (1514:1514:1514) (1575:1575:1575)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1301:1301:1301) (1332:1332:1332)) - (PORT ena (1148:1148:1148) (1134:1134:1134)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (919:919:919)) - (PORT datab (1202:1202:1202) (1198:1198:1198)) - (PORT datad (808:808:808) (813:813:813)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (1226:1226:1226) (1191:1191:1191)) - (PORT datac (312:312:312) (323:323:323)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (608:608:608)) - (PORT datab (512:512:512) (511:511:511)) - (PORT datac (768:768:768) (749:749:749)) - (PORT datad (952:952:952) (997:997:997)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (348:348:348)) - (PORT datab (1284:1284:1284) (1260:1260:1260)) - (PORT datac (1042:1042:1042) (1050:1050:1050)) - (PORT datad (570:570:570) (571:571:571)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (650:650:650)) - (PORT datab (833:833:833) (845:845:845)) - (PORT datac (1123:1123:1123) (1138:1138:1138)) - (PORT datad (523:523:523) (516:516:516)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (238:238:238)) - (PORT datab (808:808:808) (809:809:809)) - (PORT datac (312:312:312) (334:334:334)) - (PORT datad (1026:1026:1026) (1008:1008:1008)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (572:572:572) (577:577:577)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (531:531:531)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (851:851:851)) - (PORT datab (1278:1278:1278) (1261:1261:1261)) - (PORT datac (1279:1279:1279) (1273:1273:1273)) - (PORT datad (732:732:732) (759:759:759)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (586:586:586)) - (PORT datab (1282:1282:1282) (1263:1263:1263)) - (PORT datac (383:383:383) (398:398:398)) - (PORT datad (189:189:189) (219:219:219)) + (PORT dataa (1123:1123:1123) (1182:1182:1182)) + (PORT datab (817:817:817) (811:811:811)) + (PORT datac (2025:2025:2025) (2025:2025:2025)) + (PORT datad (1362:1362:1362) (1377:1377:1377)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -15616,16 +9218,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) (DELAY (ABSOLUTE - (PORT dataa (1391:1391:1391) (1415:1415:1415)) - (PORT datab (786:786:786) (768:768:768)) - (PORT datac (745:745:745) (817:817:817)) - (PORT datad (777:777:777) (787:787:787)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (600:600:600) (591:591:591)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (931:931:931) (912:912:912)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -15635,13 +9237,13 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) (DELAY (ABSOLUTE - (PORT dataa (893:893:893) (909:909:909)) - (PORT datab (1304:1304:1304) (1295:1295:1295)) - (PORT datac (1001:1001:1001) (1022:1022:1022)) - (PORT datad (185:185:185) (210:210:210)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1392:1392:1392) (1400:1400:1400)) + (PORT datab (833:833:833) (834:834:834)) + (PORT datac (1254:1254:1254) (1228:1228:1228)) + (PORT datad (342:342:342) (357:357:357)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -15651,12 +9253,12 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) (DELAY (ABSOLUTE - (PORT dataa (1044:1044:1044) (1038:1038:1038)) - (PORT datab (1718:1718:1718) (1746:1746:1746)) - (PORT datac (789:789:789) (812:812:812)) - (PORT datad (579:579:579) (594:594:594)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (1136:1136:1136) (1162:1162:1162)) + (PORT datab (1272:1272:1272) (1273:1273:1273)) + (PORT datac (1661:1661:1661) (1684:1684:1684)) + (PORT datad (341:341:341) (362:362:362)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15667,11 +9269,11 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) (DELAY (ABSOLUTE - (PORT dataa (1110:1110:1110) (1079:1079:1079)) - (PORT datab (1362:1362:1362) (1367:1367:1367)) - (PORT datac (1018:1018:1018) (978:978:978)) - (PORT datad (1114:1114:1114) (1144:1144:1144)) - (IOPATH dataa combout (299:299:299) (304:304:304)) + (PORT dataa (1142:1142:1142) (1162:1162:1162)) + (PORT datab (872:872:872) (910:910:910)) + (PORT datac (1831:1831:1831) (1804:1804:1804)) + (PORT datad (588:588:588) (612:612:612)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -15683,12 +9285,12 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) (DELAY (ABSOLUTE - (PORT dataa (1138:1138:1138) (1170:1170:1170)) - (PORT datab (1085:1085:1085) (1074:1074:1074)) - (PORT datac (850:850:850) (861:861:861)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (621:621:621) (641:641:641)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1570:1570:1570) (1547:1547:1547)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15699,12 +9301,146 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) (DELAY (ABSOLUTE - (PORT dataa (799:799:799) (802:802:802)) - (PORT datab (768:768:768) (746:746:746)) - (PORT datac (1484:1484:1484) (1457:1457:1457)) - (PORT datad (1024:1024:1024) (1012:1012:1012)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (557:557:557) (545:545:545)) + (PORT datab (1076:1076:1076) (1063:1063:1063)) + (PORT datac (1446:1446:1446) (1396:1396:1396)) + (PORT datad (492:492:492) (473:473:473)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (887:887:887)) + (PORT datac (836:836:836) (872:872:872)) + (PORT datad (601:601:601) (616:616:616)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (624:624:624)) + (PORT datac (579:579:579) (583:583:583)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (887:887:887)) + (PORT datab (1380:1380:1380) (1407:1407:1407)) + (PORT datac (744:744:744) (717:717:717)) + (PORT datad (861:861:861) (876:876:876)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (566:566:566)) + (PORT datab (929:929:929) (944:944:944)) + (PORT datac (645:645:645) (677:677:677)) + (PORT datad (505:505:505) (498:498:498)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (709:709:709)) + (PORT datab (929:929:929) (940:940:940)) + (PORT datac (585:585:585) (611:611:611)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1165:1165:1165)) + (PORT datab (928:928:928) (941:941:941)) + (PORT datac (984:984:984) (980:980:980)) + (PORT datad (1020:1020:1020) (999:999:999)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (913:913:913) (932:932:932)) + (PORT datac (164:164:164) (199:199:199)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1310:1310:1310)) + (PORT datab (851:851:851) (864:864:864)) + (PORT datac (603:603:603) (668:668:668)) + (PORT datad (1657:1657:1657) (1703:1703:1703)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT datab (1458:1458:1458) (1520:1520:1520)) + (PORT datac (1301:1301:1301) (1337:1337:1337)) + (PORT datad (1045:1045:1045) (1037:1037:1037)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15712,45 +9448,125 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) (DELAY (ABSOLUTE - (PORT dataa (936:936:936) (956:956:956)) - (PORT datab (598:598:598) (602:602:602)) - (PORT datac (820:820:820) (818:818:818)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1106:1106:1106) (1117:1117:1117)) + (PORT datab (590:590:590) (584:584:584)) + (PORT datac (790:790:790) (817:817:817)) + (PORT datad (1055:1055:1055) (1036:1036:1036)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) (DELAY (ABSOLUTE - (PORT dataa (1397:1397:1397) (1397:1397:1397)) - (PORT datab (600:600:600) (607:607:607)) - (PORT datac (854:854:854) (860:860:860)) - (PORT datad (1112:1112:1112) (1101:1101:1101)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (829:829:829) (846:846:846)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1257:1257:1257) (1243:1243:1243)) - (PORT datad (549:549:549) (559:559:559)) + (PORT datab (1374:1374:1374) (1398:1398:1398)) + (PORT datac (774:774:774) (762:762:762)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (786:786:786)) + (PORT datad (772:772:772) (767:767:767)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (794:794:794)) + (PORT datab (213:213:213) (253:253:253)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (1066:1066:1066) (1060:1060:1060)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1112:1112:1112)) + (PORT datab (205:205:205) (243:243:243)) + (PORT datad (1001:1001:1001) (1012:1012:1012)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1232:1232:1232)) + (PORT datab (1150:1150:1150) (1159:1159:1159)) + (PORT datac (923:923:923) (960:960:960)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (847:847:847)) + (PORT datab (214:214:214) (255:255:255)) + (PORT datac (833:833:833) (850:850:850)) + (PORT datad (1062:1062:1062) (1076:1076:1076)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~22) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (591:591:591) (628:628:628)) + (PORT datac (1447:1447:1447) (1471:1471:1471)) + (PORT datad (526:526:526) (514:514:514)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -15760,14 +9576,78 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (INSTANCE z80_\|pla_decode_\|Equal5\~2) (DELAY (ABSOLUTE - (PORT dataa (1279:1279:1279) (1292:1292:1292)) - (PORT datab (353:353:353) (355:355:355)) - (PORT datac (583:583:583) (592:592:592)) - (PORT datad (644:644:644) (688:688:688)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (1670:1670:1670) (1704:1704:1704)) + (PORT datab (1940:1940:1940) (2047:2047:2047)) + (PORT datac (553:553:553) (545:545:545)) + (PORT datad (1357:1357:1357) (1388:1388:1388)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (358:358:358)) + (PORT datab (566:566:566) (592:592:592)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (848:848:848) (866:866:866)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1779:1779:1779) (1759:1759:1759)) + (PORT datab (1047:1047:1047) (1043:1043:1043)) + (PORT datac (1055:1055:1055) (1073:1073:1073)) + (PORT datad (1776:1776:1776) (1754:1754:1754)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (987:987:987)) + (PORT datab (582:582:582) (590:590:590)) + (PORT datac (1427:1427:1427) (1493:1493:1493)) + (PORT datad (1013:1013:1013) (999:999:999)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1108:1108:1108)) + (PORT datab (1353:1353:1353) (1329:1329:1329)) + (PORT datac (1015:1015:1015) (1009:1009:1009)) + (PORT datad (1399:1399:1399) (1405:1405:1405)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -15776,1082 +9656,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (916:916:916)) - (PORT datab (789:789:789) (789:789:789)) - (PORT datac (513:513:513) (501:501:501)) - (PORT datad (1022:1022:1022) (1008:1008:1008)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1058:1058:1058)) - (PORT datab (861:861:861) (865:865:865)) - (PORT datac (1114:1114:1114) (1128:1128:1128)) - (PORT datad (1128:1128:1128) (1147:1147:1147)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) (DELAY (ABSOLUTE + (PORT dataa (1668:1668:1668) (1660:1660:1660)) (PORT datab (188:188:188) (222:222:222)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1020:1020:1020)) - (PORT datab (571:571:571) (577:577:577)) - (PORT datac (168:168:168) (206:206:206)) - (PORT datad (775:775:775) (747:747:747)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (1872:1872:1872) (1917:1917:1917)) - (PORT datac (1809:1809:1809) (1849:1849:1849)) - (PORT datad (1500:1500:1500) (1588:1588:1588)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1282:1282:1282)) - (PORT datab (1112:1112:1112) (1133:1133:1133)) - (PORT datac (1084:1084:1084) (1086:1086:1086)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datac (776:776:776) (784:784:784)) - (PORT datad (580:580:580) (583:583:583)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (530:530:530)) - (PORT datab (361:361:361) (365:365:365)) - (PORT datac (1011:1011:1011) (1003:1003:1003)) - (PORT datad (757:757:757) (738:738:738)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1491:1491:1491)) - (PORT datab (1522:1522:1522) (1494:1494:1494)) - (PORT datac (1545:1545:1545) (1548:1548:1548)) - (PORT datad (1058:1058:1058) (1056:1056:1056)) + (PORT datac (833:833:833) (828:828:828)) + (PORT datad (1313:1313:1313) (1294:1294:1294)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (640:640:640)) - (PORT datab (1318:1318:1318) (1322:1322:1322)) - (PORT datac (857:857:857) (895:895:895)) - (PORT datad (295:295:295) (305:305:305)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (408:408:408)) - (PORT datab (356:356:356) (368:368:368)) - (PORT datac (882:882:882) (893:893:893)) - (PORT datad (831:831:831) (832:832:832)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (814:814:814)) - (PORT datab (1080:1080:1080) (1078:1078:1078)) - (PORT datad (544:544:544) (544:544:544)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (594:594:594)) - (PORT datab (373:373:373) (403:403:403)) - (PORT datac (840:840:840) (855:855:855)) - (PORT datad (1073:1073:1073) (1099:1099:1099)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1041:1041:1041)) - (PORT datad (1725:1725:1725) (1693:1693:1693)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1078:1078:1078)) - (PORT datab (1082:1082:1082) (1070:1070:1070)) - (PORT datac (1264:1264:1264) (1261:1261:1261)) - (PORT datad (1025:1025:1025) (1001:1001:1001)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (368:368:368)) - (PORT datab (1589:1589:1589) (1581:1581:1581)) - (PORT datac (1456:1456:1456) (1520:1520:1520)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (1301:1301:1301) (1264:1264:1264)) - (PORT datad (1722:1722:1722) (1699:1699:1699)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1078:1078:1078)) - (PORT datab (1083:1083:1083) (1071:1071:1071)) - (PORT datac (1265:1265:1265) (1261:1261:1261)) - (PORT datad (774:774:774) (759:759:759)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (623:623:623) (635:635:635)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (366:366:366)) - (PORT datab (1590:1590:1590) (1581:1581:1581)) - (PORT datac (1454:1454:1454) (1520:1520:1520)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1564:1564:1564) (1566:1566:1566)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (298:298:298)) - (PORT datab (1292:1292:1292) (1363:1363:1363)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1230:1230:1230)) - (PORT datac (945:945:945) (943:943:943)) - (PORT datad (1272:1272:1272) (1260:1260:1260)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1044:1044:1044)) - (PORT datab (343:343:343) (364:364:364)) - (PORT datad (1725:1725:1725) (1696:1696:1696)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1225:1225:1225)) - (PORT datac (943:943:943) (941:941:941)) - (PORT datad (1268:1268:1268) (1254:1254:1254)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1559:1559:1559) (1542:1542:1542)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (832:832:832) (853:853:853)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1042:1042:1042)) - (PORT datab (340:340:340) (363:363:363)) - (PORT datad (1728:1728:1728) (1695:1695:1695)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (600:600:600)) - (PORT datab (866:866:866) (878:878:878)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1208:1208:1208)) - (PORT datab (928:928:928) (954:954:954)) - (PORT datac (847:847:847) (859:859:859)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1274:1274:1274) (1242:1242:1242)) - (PORT datab (206:206:206) (244:244:244)) - (PORT datac (1029:1029:1029) (1015:1015:1015)) - (PORT datad (548:548:548) (578:578:578)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (749:749:749)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (795:795:795) (774:774:774)) - (PORT datad (1264:1264:1264) (1239:1239:1239)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (885:885:885) (893:893:893)) - (PORT ena (1142:1142:1142) (1145:1145:1145)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1125:1125:1125)) - (PORT datab (626:626:626) (647:647:647)) - (PORT datad (880:880:880) (901:901:901)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1201:1201:1201)) - (PORT datab (931:931:931) (955:955:955)) - (PORT datac (848:848:848) (860:860:860)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (885:885:885) (895:895:895)) - (PORT ena (1081:1081:1081) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (409:409:409)) - (PORT datab (181:181:181) (214:214:214)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1365:1365:1365) (1355:1355:1355)) - (PORT datab (1117:1117:1117) (1120:1120:1120)) - (PORT datac (1615:1615:1615) (1660:1660:1660)) - (PORT datad (509:509:509) (493:493:493)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1043:1043:1043) (1033:1033:1033)) - (PORT ena (879:879:879) (881:881:881)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1645:1645:1645)) - (PORT datab (1285:1285:1285) (1240:1240:1240)) - (PORT datac (1030:1030:1030) (1013:1013:1013)) - (PORT datad (1038:1038:1038) (1007:1007:1007)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1049:1049:1049)) - (PORT datab (576:576:576) (613:613:613)) - (PORT datac (1247:1247:1247) (1207:1207:1207)) - (PORT datad (769:769:769) (735:735:735)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1041:1041:1041) (1031:1031:1031)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1277:1277:1277) (1243:1243:1243)) - (PORT datab (205:205:205) (242:242:242)) - (PORT datac (1030:1030:1030) (1017:1017:1017)) - (PORT datad (550:550:550) (580:580:580)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (294:294:294)) - (PORT datab (220:220:220) (266:266:266)) - (PORT datad (193:193:193) (220:220:220)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (616:616:616)) - (PORT datab (608:608:608) (601:601:601)) - (PORT datac (707:707:707) (698:698:698)) - (PORT datad (559:559:559) (576:576:576)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1232:1232:1232)) - (PORT datac (779:779:779) (795:795:795)) - (PORT datad (1271:1271:1271) (1255:1255:1255)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1236:1236:1236)) - (PORT datac (792:792:792) (801:801:801)) - (PORT datad (1275:1275:1275) (1260:1260:1260)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1236:1236:1236)) - (PORT datac (792:792:792) (801:801:801)) - (PORT datad (1275:1275:1275) (1260:1260:1260)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1104:1104:1104) (1106:1106:1106)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (621:621:621) (652:652:652)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1236:1236:1236)) - (PORT datac (780:780:780) (792:792:792)) - (PORT datad (1273:1273:1273) (1260:1260:1260)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (416:416:416)) - (PORT datab (410:410:410) (432:432:432)) - (PORT datad (198:198:198) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1021:1021:1021) (1001:1001:1001)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1020:1020:1020) (999:999:999)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (287:287:287)) - (PORT datab (1005:1005:1005) (993:993:993)) - (PORT datad (337:337:337) (365:365:365)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (616:616:616)) - (PORT datab (598:598:598) (623:623:623)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1745:1745:1745) (1734:1734:1734)) - (PORT datab (1691:1691:1691) (1727:1727:1727)) - (PORT datac (190:190:190) (232:232:232)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (807:807:807)) - (PORT datab (815:815:815) (812:812:812)) - (PORT datac (497:497:497) (492:492:492)) - (PORT datad (577:577:577) (581:581:581)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1094:1094:1094)) - (PORT datab (979:979:979) (971:971:971)) - (PORT datac (641:641:641) (669:669:669)) - (PORT datad (1049:1049:1049) (1030:1030:1030)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1128:1128:1128)) - (PORT datab (616:616:616) (657:657:657)) - (PORT datac (510:510:510) (498:498:498)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (488:488:488)) - (PORT datab (593:593:593) (621:621:621)) - (PORT datac (588:588:588) (585:585:585)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1123:1123:1123) (1104:1104:1104)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (486:486:486) (512:512:512)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1350:1350:1350)) - (PORT datab (534:534:534) (534:534:534)) - (PORT datad (595:595:595) (596:596:596)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (408:408:408)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (564:564:564) (560:560:560)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (927:927:927)) - (PORT datab (409:409:409) (449:449:449)) - (PORT datac (1073:1073:1073) (1075:1075:1075)) - (PORT datad (391:391:391) (436:436:436)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1662:1662:1662) (1674:1674:1674)) - (PORT datab (1139:1139:1139) (1137:1137:1137)) - (PORT datac (1106:1106:1106) (1142:1142:1142)) - (PORT datad (907:907:907) (944:944:944)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (836:836:836) (856:856:856)) - (PORT datad (168:168:168) (195:195:195)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1640:1640:1640) (1564:1564:1564)) - (PORT datab (1122:1122:1122) (1119:1119:1119)) - (PORT datac (593:593:593) (588:588:588)) - (PORT datad (759:759:759) (794:794:794)) - (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16860,645 +9672,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (614:614:614)) - (PORT datab (607:607:607) (596:596:596)) - (PORT datad (816:816:816) (824:824:824)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (852:852:852)) - (PORT datab (1060:1060:1060) (1035:1035:1035)) - (PORT datac (1500:1500:1500) (1474:1474:1474)) - (PORT datad (816:816:816) (806:806:806)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (332:332:332)) - (PORT datab (847:847:847) (843:843:843)) - (PORT datac (1001:1001:1001) (980:980:980)) - (PORT datad (1002:1002:1002) (982:982:982)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1071:1071:1071)) - (PORT datab (761:761:761) (829:829:829)) - (PORT datac (1051:1051:1051) (1054:1054:1054)) - (PORT datad (729:729:729) (759:759:759)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1028:1028:1028)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (917:917:917) (919:919:919)) - (PORT datad (825:825:825) (840:840:840)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (978:978:978)) - (PORT datab (882:882:882) (935:935:935)) - (PORT datac (1012:1012:1012) (998:998:998)) - (PORT datad (179:179:179) (210:210:210)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (839:839:839)) - (PORT datab (778:778:778) (752:752:752)) - (PORT datac (383:383:383) (426:426:426)) - (PORT datad (591:591:591) (628:628:628)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1044:1044:1044)) - (PORT datab (364:364:364) (414:414:414)) - (PORT datac (1023:1023:1023) (1011:1011:1011)) - (PORT datad (594:594:594) (630:630:630)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (564:564:564)) - (PORT datab (1498:1498:1498) (1501:1501:1501)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (799:799:799) (796:796:796)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (714:714:714)) - (PORT datab (207:207:207) (242:242:242)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (912:912:912) (919:919:919)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1353:1353:1353)) - (PORT datab (592:592:592) (597:597:597)) - (PORT datac (1104:1104:1104) (1121:1121:1121)) - (PORT datad (606:606:606) (602:602:602)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (408:408:408)) - (PORT datab (263:263:263) (344:344:344)) - (PORT datad (228:228:228) (290:290:290)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (623:623:623)) - (PORT datab (961:961:961) (937:937:937)) - (PORT datac (1121:1121:1121) (1148:1148:1148)) - (PORT datad (1887:1887:1887) (1822:1822:1822)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (973:973:973)) - (PORT datab (715:715:715) (790:790:790)) - (PORT datac (1353:1353:1353) (1374:1374:1374)) - (PORT datad (824:824:824) (855:855:855)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (737:737:737)) - (PORT datab (2279:2279:2279) (2310:2310:2310)) - (PORT datac (1242:1242:1242) (1219:1219:1219)) - (PORT datad (650:650:650) (715:715:715)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (758:758:758)) + (PORT dataa (216:216:216) (263:263:263)) (PORT datab (606:606:606) (624:624:624)) - (PORT datac (786:786:786) (780:780:780)) - (PORT datad (780:780:780) (781:781:781)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (983:983:983)) - (PORT datab (844:844:844) (833:833:833)) - (PORT datac (854:854:854) (905:905:905)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1012:1012:1012)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1135:1135:1135)) - (PORT datab (1804:1804:1804) (1838:1838:1838)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (537:537:537) (526:526:526)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1319:1319:1319) (1338:1338:1338)) - (PORT datab (1389:1389:1389) (1406:1406:1406)) - (PORT datac (801:801:801) (811:811:811)) - (PORT datad (1086:1086:1086) (1080:1080:1080)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1090:1090:1090)) - (PORT datab (806:806:806) (787:787:787)) - (PORT datac (615:615:615) (651:651:651)) - (PORT datad (1016:1016:1016) (983:983:983)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1598:1598:1598) (1581:1581:1581)) - (PORT datab (1804:1804:1804) (1840:1840:1840)) - (PORT datac (567:567:567) (588:588:588)) - (PORT datad (770:770:770) (761:761:761)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1104:1104:1104)) - (PORT datab (648:648:648) (674:674:674)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (621:621:621) (669:669:669)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (251:251:251)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (562:562:562) (571:571:571)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2023:2023:2023) (2066:2066:2066)) - (PORT datab (1348:1348:1348) (1390:1390:1390)) - (PORT datac (662:662:662) (696:696:696)) - (PORT datad (197:197:197) (224:224:224)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (980:980:980)) - (PORT datab (885:885:885) (937:937:937)) - (PORT datac (560:560:560) (565:565:565)) - (PORT datad (1091:1091:1091) (1076:1076:1076)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~17) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (551:551:551)) - (PORT datab (535:535:535) (535:535:535)) - (PORT datac (1994:1994:1994) (2036:2036:2036)) - (PORT datad (493:493:493) (486:486:486)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1276:1276:1276) (1286:1286:1286)) - (PORT datab (687:687:687) (722:722:722)) - (PORT datac (1995:1995:1995) (2033:2033:2033)) - (PORT datad (1179:1179:1179) (1191:1191:1191)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (943:943:943)) - (PORT datab (1247:1247:1247) (1298:1298:1298)) - (PORT datac (660:660:660) (695:695:695)) - (PORT datad (840:840:840) (843:843:843)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (787:787:787)) - (PORT datab (707:707:707) (780:780:780)) - (PORT datac (578:578:578) (603:603:603)) - (PORT datad (650:650:650) (715:715:715)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~15) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (577:577:577)) - (PORT datab (686:686:686) (695:695:695)) - (PORT datac (1803:1803:1803) (1838:1838:1838)) - (PORT datad (748:748:748) (738:738:738)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~16) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (753:753:753)) - (PORT datab (709:709:709) (780:780:780)) - (PORT datac (687:687:687) (757:757:757)) - (PORT datad (1697:1697:1697) (1689:1689:1689)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (640:640:640)) - (PORT datab (187:187:187) (222:222:222)) - (PORT datac (489:489:489) (479:479:479)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1070:1070:1070) (1040:1040:1040)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (756:756:756) (746:746:746)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1531:1531:1531) (1505:1505:1505)) - (PORT datab (1830:1830:1830) (1865:1865:1865)) - (PORT datac (814:814:814) (825:825:825)) - (PORT datad (1331:1331:1331) (1291:1291:1291)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (776:776:776)) - (PORT datac (684:684:684) (750:750:750)) - (PORT datad (937:937:937) (919:919:919)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (734:734:734)) - (PORT datab (2174:2174:2174) (2228:2228:2228)) - (PORT datac (684:684:684) (750:750:750)) - (PORT datad (599:599:599) (620:620:620)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) - (DELAY - (ABSOLUTE - (PORT datab (1067:1067:1067) (1099:1099:1099)) - (PORT datac (834:834:834) (870:870:870)) - (PORT datad (644:644:644) (701:701:701)) + (PORT datac (827:827:827) (846:846:846)) + (PORT datad (829:829:829) (849:849:849)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) - (DELAY - (ABSOLUTE - (PORT dataa (2305:2305:2305) (2330:2330:2330)) - (PORT datab (861:861:861) (868:868:868)) - (PORT datac (1046:1046:1046) (1044:1044:1044)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -17506,437 +9688,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (816:816:816) (842:842:842)) - (PORT datab (706:706:706) (777:777:777)) - (PORT datac (684:684:684) (750:750:750)) - (PORT datad (523:523:523) (513:513:513)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (216:216:216)) - (PORT datab (192:192:192) (231:231:231)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (189:189:189) (213:213:213)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT datab (357:357:357) (385:385:385)) - (PORT datad (818:818:818) (802:802:802)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (996:996:996)) - (PORT datab (418:418:418) (433:433:433)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (1857:1857:1857) (1786:1786:1786)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (949:949:949)) - (PORT datab (1248:1248:1248) (1304:1304:1304)) - (PORT datac (1994:1994:1994) (2038:2038:2038)) - (PORT datad (839:839:839) (848:848:848)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (345:345:345)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1477:1477:1477) (1439:1439:1439)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (642:642:642)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (818:818:818) (825:825:825)) - (PORT datad (1308:1308:1308) (1323:1323:1323)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (1342:1342:1342) (1353:1353:1353)) - (PORT datac (318:318:318) (328:328:328)) - (PORT datad (196:196:196) (224:224:224)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (788:788:788)) - (PORT datab (2175:2175:2175) (2233:2233:2233)) - (PORT datac (579:579:579) (602:602:602)) - (PORT datad (615:615:615) (672:672:672)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (638:638:638)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (488:488:488) (477:477:477)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (660:660:660) (698:698:698)) - (PORT datad (198:198:198) (227:227:227)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (399:399:399)) - (PORT datab (266:266:266) (348:348:348)) - (PORT datac (1052:1052:1052) (1044:1044:1044)) - (PORT datad (228:228:228) (288:288:288)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT dataa (2023:2023:2023) (2066:2066:2066)) - (PORT datab (211:211:211) (251:251:251)) - (PORT datac (564:564:564) (584:584:584)) - (PORT datad (965:965:965) (912:912:912)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (1345:1345:1345) (1353:1353:1353)) - (PORT datac (1343:1343:1343) (1335:1335:1335)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (531:531:531)) - (PORT datab (512:512:512) (500:500:500)) - (PORT datac (1262:1262:1262) (1225:1225:1225)) - (PORT datad (598:598:598) (600:600:600)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (519:519:519)) - (PORT datab (193:193:193) (234:234:234)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (191:191:191) (217:217:217)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (582:582:582) (600:600:600)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (563:563:563) (568:568:568)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (813:813:813)) - (PORT datab (1880:1880:1880) (1816:1816:1816)) - (PORT datac (752:752:752) (732:732:732)) - (PORT datad (818:818:818) (802:802:802)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT datab (195:195:195) (237:237:237)) - (PORT datac (163:163:163) (196:196:196)) - (PORT datad (193:193:193) (220:220:220)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1815:1815:1815) (1845:1845:1845)) - (PORT datac (766:766:766) (811:811:811)) - (PORT datad (506:506:506) (495:495:495)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (373:373:373)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (565:565:565) (571:571:571)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (248:248:248)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (164:164:164) (190:190:190)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (583:583:583)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datad (315:315:315) (319:319:319)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1101:1101:1101)) - (PORT datab (417:417:417) (432:432:432)) - (PORT datac (684:684:684) (722:722:722)) - (PORT datad (1779:1779:1779) (1810:1810:1810)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1127:1127:1127) (1134:1134:1134)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1854:1854:1854) (1784:1784:1784)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (853:853:853)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (882:882:882) (933:933:933)) - (PORT datad (1152:1152:1152) (1192:1192:1192)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (827:827:827)) - (PORT datab (515:515:515) (515:515:515)) - (PORT datac (2452:2452:2452) (2414:2414:2414)) - (PORT datad (303:303:303) (306:306:306)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (979:979:979)) - (PORT datab (719:719:719) (792:792:792)) - (PORT datac (669:669:669) (731:731:731)) - (PORT datad (1501:1501:1501) (1487:1487:1487)) + (PORT dataa (836:836:836) (859:859:859)) + (PORT datab (927:927:927) (944:944:944)) + (PORT datac (1506:1506:1506) (1482:1482:1482)) + (PORT datad (582:582:582) (610:610:610)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -17946,1086 +9704,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (506:506:506) (493:493:493)) - (PORT datad (1854:1854:1854) (1784:1784:1784)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1228:1228:1228)) - (PORT datab (1375:1375:1375) (1383:1383:1383)) - (PORT datac (568:568:568) (602:602:602)) - (PORT datad (761:761:761) (794:794:794)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (813:813:813)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1015:1015:1015) (973:973:973)) - (PORT datad (330:330:330) (355:355:355)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (2305:2305:2305) (2327:2327:2327)) - (PORT datab (889:889:889) (898:898:898)) - (PORT datac (1224:1224:1224) (1213:1213:1213)) - (PORT datad (791:791:791) (794:794:794)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (428:428:428)) - (PORT datab (889:889:889) (897:897:897)) - (PORT datac (1245:1245:1245) (1230:1230:1230)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (427:427:427)) - (PORT datab (817:817:817) (829:829:829)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (344:344:344)) - (PORT datab (355:355:355) (384:384:384)) - (PORT datac (163:163:163) (199:199:199)) - (PORT datad (817:817:817) (802:802:802)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1857:1857:1857) (1785:1785:1785)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (1301:1301:1301) (1280:1280:1280)) - (PORT datac (1278:1278:1278) (1259:1259:1259)) - (PORT datad (988:988:988) (992:992:992)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (909:909:909) (921:921:921)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (909:909:909) (921:921:921)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (600:600:600)) - (PORT datab (865:865:865) (882:882:882)) - (PORT datad (197:197:197) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (623:623:623) (622:622:622)) - (PORT ena (1142:1142:1142) (1145:1145:1145)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (300:300:300) (403:403:403)) - (PORT datab (872:872:872) (869:869:869)) - (PORT datac (886:886:886) (898:898:898)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (822:822:822)) - (PORT datab (818:818:818) (824:824:824)) - (PORT datac (740:740:740) (732:732:732)) - (PORT datad (525:525:525) (521:521:521)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1160:1160:1160) (1177:1177:1177)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1163:1163:1163) (1181:1181:1181)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (933:933:933)) - (PORT datab (889:889:889) (916:916:916)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (905:905:905) (911:911:911)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (594:594:594) (602:602:602)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (883:883:883)) - (PORT datab (878:878:878) (877:877:877)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1040:1040:1040) (1095:1095:1095)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1383:1383:1383)) - (PORT datab (608:608:608) (630:630:630)) - (PORT datad (1525:1525:1525) (1587:1587:1587)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (588:588:588) (609:609:609)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (925:925:925) (954:954:954)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (292:292:292)) - (PORT datab (884:884:884) (907:907:907)) - (PORT datad (807:807:807) (826:826:826)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT asdata (1055:1055:1055) (1091:1091:1091)) - (PORT ena (1103:1103:1103) (1073:1073:1073)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1383:1383:1383) (1382:1382:1382)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (661:661:661)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datad (544:544:544) (535:535:535)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1159:1159:1159) (1174:1174:1174)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1159:1159:1159) (1176:1176:1176)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (622:622:622)) - (PORT datab (221:221:221) (289:289:289)) - (PORT datad (597:597:597) (593:593:593)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1353:1353:1353)) - (PORT asdata (1428:1428:1428) (1491:1491:1491)) - (PORT ena (1148:1148:1148) (1139:1139:1139)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (818:818:818)) - (PORT datab (1185:1185:1185) (1170:1170:1170)) - (PORT datad (578:578:578) (579:579:579)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (611:611:611)) - (PORT datab (744:744:744) (776:776:776)) - (PORT datac (555:555:555) (560:560:560)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (765:765:765)) - (PORT datab (953:953:953) (974:974:974)) - (PORT datac (313:313:313) (320:320:320)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1088:1088:1088)) - (PORT datab (1292:1292:1292) (1268:1268:1268)) - (PORT datac (860:860:860) (893:893:893)) - (PORT datad (1252:1252:1252) (1235:1235:1235)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2397:2397:2397) (2425:2425:2425)) - (PORT datab (186:186:186) (220:220:220)) - (PORT datac (154:154:154) (183:183:183)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (1037:1037:1037) (1023:1023:1023)) - (PORT datad (1326:1326:1326) (1313:1313:1313)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (629:629:629)) - (PORT datab (870:870:870) (864:864:864)) - (PORT datac (1054:1054:1054) (1058:1058:1058)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1086:1086:1086)) - (PORT datac (843:843:843) (837:837:837)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1083:1083:1083)) - (PORT datab (872:872:872) (868:868:868)) - (PORT datac (1032:1032:1032) (1015:1015:1015)) - (PORT datad (1319:1319:1319) (1306:1306:1306)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (439:439:439)) - (PORT datac (522:522:522) (523:523:523)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (630:630:630) (644:644:644)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (631:631:631) (645:645:645)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (602:602:602)) - (PORT datab (869:869:869) (878:878:878)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1158:1158:1158) (1167:1167:1167)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1158:1158:1158) (1169:1169:1169)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (286:286:286)) - (PORT datab (1010:1010:1010) (988:988:988)) - (PORT datad (337:337:337) (370:370:370)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (846:846:846) (834:834:834)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (846:846:846) (834:834:834)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (414:414:414)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datad (381:381:381) (400:400:400)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1305:1305:1305) (1278:1278:1278)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1173:1173:1173) (1216:1216:1216)) - (PORT datab (925:925:925) (947:947:947)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1349:1349:1349) (1339:1339:1339)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1429:1429:1429)) - (PORT datab (1414:1414:1414) (1477:1477:1477)) - (PORT datac (1972:1972:1972) (1922:1922:1922)) - (PORT datad (585:585:585) (590:590:590)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (257:257:257)) - (PORT datab (673:673:673) (709:709:709)) - (PORT datac (824:824:824) (833:833:833)) - (PORT datad (1080:1080:1080) (1072:1072:1072)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (869:869:869)) - (PORT datab (599:599:599) (600:600:600)) - (PORT datac (1199:1199:1199) (1198:1198:1198)) - (PORT datad (312:312:312) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (763:763:763) (805:805:805)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (595:595:595) (612:612:612)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (825:825:825)) - (PORT datab (1302:1302:1302) (1274:1274:1274)) - (PORT datac (184:184:184) (219:219:219)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (185:185:185) (221:221:221)) - (PORT datad (1182:1182:1182) (1162:1162:1162)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1134:1134:1134)) - (PORT datac (1889:1889:1889) (1953:1953:1953)) - (PORT datad (1208:1208:1208) (1276:1276:1276)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (612:612:612)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (507:507:507) (498:498:498)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1890:1890:1890)) - (PORT datab (1390:1390:1390) (1377:1377:1377)) - (PORT datac (1014:1014:1014) (1003:1003:1003)) - (PORT datad (1448:1448:1448) (1537:1537:1537)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1678:1678:1678) (1701:1701:1701)) - (PORT datab (1472:1472:1472) (1565:1565:1565)) - (PORT datac (2902:2902:2902) (2899:2899:2899)) - (PORT datad (1751:1751:1751) (1849:1849:1849)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1365:1365:1365) (1347:1347:1347)) - (PORT datab (1833:1833:1833) (1840:1840:1840)) - (PORT datac (1410:1410:1410) (1412:1412:1412)) - (PORT datad (1638:1638:1638) (1668:1668:1668)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (180:180:180) (211:211:211)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (1433:1433:1433) (1464:1464:1464)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (573:573:573)) - (PORT datab (563:563:563) (579:579:579)) - (PORT datac (585:585:585) (578:578:578)) - (PORT datad (320:320:320) (321:321:321)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (259:259:259)) - (PORT datab (628:628:628) (629:629:629)) - (PORT datac (955:955:955) (919:919:919)) - (PORT datad (548:548:548) (556:556:556)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (1009:1009:1009) (977:977:977)) + (PORT datad (322:322:322) (320:320:320)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -19034,1237 +9718,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~7) (DELAY (ABSOLUTE - (PORT dataa (873:873:873) (869:869:869)) - (PORT datab (602:602:602) (608:608:608)) - (PORT datac (1623:1623:1623) (1632:1632:1632)) - (PORT datad (520:520:520) (513:513:513)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (564:564:564)) - (PORT datab (601:601:601) (611:611:611)) - (PORT datac (162:162:162) (198:198:198)) - (PORT datad (867:867:867) (876:876:876)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT datac (523:523:523) (522:522:522)) - (PORT datad (1012:1012:1012) (991:991:991)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1857:1857:1857) (1920:1920:1920)) - (PORT datab (1326:1326:1326) (1322:1322:1322)) - (PORT datad (1229:1229:1229) (1341:1341:1341)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (919:919:919)) - (PORT datab (922:922:922) (934:934:934)) - (PORT datac (1352:1352:1352) (1367:1367:1367)) - (PORT datad (1139:1139:1139) (1183:1183:1183)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (904:904:904) (909:909:909)) - (PORT datac (853:853:853) (883:883:883)) - (PORT datad (887:887:887) (895:895:895)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1670:1670:1670)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (547:547:547) (564:564:564)) - (PORT datad (1461:1461:1461) (1413:1413:1413)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1311:1311:1311)) - (PORT datab (1247:1247:1247) (1363:1363:1363)) - (PORT datac (1028:1028:1028) (1023:1023:1023)) - (PORT datad (1239:1239:1239) (1335:1335:1335)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (589:589:589) (611:611:611)) - (PORT datad (313:313:313) (317:317:317)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (995:995:995)) - (PORT datab (762:762:762) (755:755:755)) - (PORT datac (526:526:526) (522:522:522)) - (PORT datad (511:511:511) (495:495:495)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (980:980:980)) - (PORT datab (824:824:824) (808:808:808)) - (PORT datac (953:953:953) (1027:1027:1027)) - (PORT datad (1172:1172:1172) (1217:1217:1217)) + (PORT dataa (820:820:820) (830:830:830)) + (PORT datab (583:583:583) (583:583:583)) + (PORT datac (793:793:793) (775:775:775)) + (PORT datad (524:524:524) (517:517:517)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (652:652:652)) - (PORT datab (853:853:853) (887:887:887)) - (PORT datac (1351:1351:1351) (1371:1371:1371)) - (PORT datad (1063:1063:1063) (1064:1064:1064)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1026:1026:1026)) - (PORT datab (326:326:326) (350:350:350)) - (PORT datac (523:523:523) (521:521:521)) - (PORT datad (992:992:992) (968:968:968)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT datab (204:204:204) (241:241:241)) - (PORT datac (557:557:557) (564:564:564)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (801:801:801) (800:800:800)) - (PORT datad (552:552:552) (539:539:539)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (621:621:621)) - (PORT datab (1417:1417:1417) (1421:1421:1421)) - (PORT datac (887:887:887) (900:900:900)) - (PORT datad (1282:1282:1282) (1295:1295:1295)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (803:803:803)) - (PORT datab (528:528:528) (516:516:516)) - (PORT datac (745:745:745) (731:731:731)) - (PORT datad (780:780:780) (770:770:770)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (309:309:309)) - (PORT datab (1629:1629:1629) (1629:1629:1629)) - (PORT datac (223:223:223) (275:275:275)) - (PORT datad (1118:1118:1118) (1123:1123:1123)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1609:1609:1609) (1646:1646:1646)) - (PORT datab (824:824:824) (809:809:809)) - (PORT datac (794:794:794) (801:801:801)) - (PORT datad (1702:1702:1702) (1792:1792:1792)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1610:1610:1610) (1647:1647:1647)) - (PORT datab (1592:1592:1592) (1659:1659:1659)) - (PORT datac (794:794:794) (803:803:803)) - (PORT datad (1938:1938:1938) (2052:2052:2052)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (225:225:225)) - (PORT datab (199:199:199) (243:243:243)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (662:662:662) (663:663:663)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (661:661:661) (665:665:665)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (885:885:885)) - (PORT datab (881:881:881) (880:880:880)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1160:1160:1160) (1163:1163:1163)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1162:1162:1162) (1165:1165:1165)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (939:939:939)) - (PORT datab (893:893:893) (924:924:924)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (914:914:914) (931:931:931)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1383:1383:1383)) - (PORT datab (601:601:601) (621:621:621)) - (PORT datad (1515:1515:1515) (1580:1580:1580)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1632:1632:1632) (1652:1652:1652)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1763:1763:1763) (1774:1774:1774)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (626:626:626)) - (PORT datab (459:459:459) (488:488:488)) - (PORT datad (590:590:590) (590:590:590)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1353:1353:1353)) - (PORT asdata (1355:1355:1355) (1361:1361:1361)) - (PORT ena (1148:1148:1148) (1139:1139:1139)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (828:828:828)) - (PORT datab (616:616:616) (615:615:615)) - (PORT datad (1148:1148:1148) (1138:1138:1138)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (833:833:833) (827:827:827)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (867:867:867)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (845:845:845) (878:878:878)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (918:918:918) (944:944:944)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (916:916:916) (944:944:944)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (619:619:619)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datad (597:597:597) (588:588:588)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (593:593:593)) - (PORT datab (772:772:772) (813:813:813)) - (PORT datac (537:537:537) (528:528:528)) - (PORT datad (547:547:547) (542:542:542)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (760:760:760) (750:750:750)) - (PORT datab (956:956:956) (948:948:948)) - (PORT datac (757:757:757) (777:777:777)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (925:925:925)) - (PORT datac (877:877:877) (896:896:896)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT asdata (1079:1079:1079) (1062:1062:1062)) - (PORT ena (1070:1070:1070) (1040:1040:1040)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (921:921:921)) - (PORT datab (906:906:906) (921:921:921)) - (PORT datac (1134:1134:1134) (1176:1176:1176)) - (PORT datad (1039:1039:1039) (1007:1007:1007)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1413:1413:1413)) - (PORT datab (543:543:543) (547:547:547)) - (PORT datad (530:530:530) (529:529:529)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT datab (915:915:915) (923:923:923)) - (PORT datac (864:864:864) (891:891:891)) - (PORT datad (1123:1123:1123) (1141:1141:1141)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (917:917:917)) - (PORT datac (861:861:861) (886:886:886)) - (PORT datad (1118:1118:1118) (1135:1135:1135)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (221:221:221) (291:291:291)) - (PORT datad (522:522:522) (519:519:519)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (930:930:930) (957:957:957)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (930:930:930) (957:957:957)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (934:934:934)) - (PORT datab (889:889:889) (917:917:917)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (840:840:840) (827:827:827)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (840:840:840) (827:827:827)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (881:881:881)) - (PORT datab (876:876:876) (874:874:874)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1115:1115:1115) (1120:1120:1120)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1379:1379:1379)) - (PORT datab (600:600:600) (619:619:619)) - (PORT datad (1514:1514:1514) (1575:1575:1575)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1108:1108:1108) (1113:1113:1113)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1106:1106:1106) (1111:1111:1111)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (626:626:626)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (594:594:594) (592:592:592)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (636:636:636) (646:646:646)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (862:862:862)) - (PORT datab (885:885:885) (907:907:907)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1120:1120:1120) (1111:1111:1111)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1123:1123:1123) (1119:1119:1119)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (459:459:459)) - (PORT datab (460:460:460) (490:490:490)) - (PORT datad (589:589:589) (589:589:589)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1125:1125:1125) (1122:1122:1122)) - (PORT ena (1148:1148:1148) (1134:1134:1134)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (923:923:923)) - (PORT datab (1202:1202:1202) (1196:1196:1196)) - (PORT datad (1372:1372:1372) (1401:1401:1401)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (330:330:330)) - (PORT datab (604:604:604) (611:611:611)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (338:338:338)) - (PORT datab (571:571:571) (582:582:582)) - (PORT datac (591:591:591) (592:592:592)) - (PORT datad (574:574:574) (575:575:575)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (759:759:759) (768:768:768)) - (PORT datab (374:374:374) (393:393:393)) - (PORT datac (1262:1262:1262) (1243:1243:1243)) - (PORT datad (554:554:554) (536:536:536)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT asdata (827:827:827) (812:812:812)) - (PORT ena (1070:1070:1070) (1040:1040:1040)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (570:570:570)) - (PORT datab (1151:1151:1151) (1182:1182:1182)) - (PORT datad (519:519:519) (514:514:514)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (291:291:291)) - (PORT datab (544:544:544) (548:548:548)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (365:365:365)) - (PORT datac (813:813:813) (826:826:826)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (591:591:591)) - (PORT datab (195:195:195) (233:233:233)) - (PORT datac (163:163:163) (200:200:200)) - (PORT datad (556:556:556) (545:545:545)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (261:261:261)) - (PORT datab (626:626:626) (655:655:655)) - (PORT datac (1105:1105:1105) (1104:1104:1104)) - (PORT datad (1640:1640:1640) (1626:1626:1626)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (761:761:761)) - (PORT datab (1017:1017:1017) (1034:1034:1034)) - (PORT datac (929:929:929) (960:960:960)) - (PORT datad (785:785:785) (770:770:770)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20275,12 +9737,12 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (819:819:819) (850:850:850)) - (PORT datab (849:849:849) (843:843:843)) - (PORT datac (315:315:315) (320:320:320)) - (PORT datad (795:795:795) (789:789:789)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (891:891:891) (921:921:921)) + (PORT datab (1518:1518:1518) (1492:1492:1492)) + (PORT datac (1090:1090:1090) (1086:1086:1086)) + (PORT datad (871:871:871) (885:885:885)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20291,58 +9753,322 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (399:399:399)) - (PORT datab (1369:1369:1369) (1378:1378:1378)) - (PORT datac (938:938:938) (970:970:970)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (602:602:602) (614:614:614)) + (PORT datab (1866:1866:1866) (1885:1885:1885)) + (PORT datac (1342:1342:1342) (1350:1350:1350)) + (PORT datad (857:857:857) (862:862:862)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (919:919:919)) + (PORT datab (1129:1129:1129) (1137:1137:1137)) + (PORT datac (1067:1067:1067) (1102:1102:1102)) + (PORT datad (1066:1066:1066) (1060:1060:1060)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1348:1348:1348)) + (PORT datab (348:348:348) (357:357:357)) + (PORT datac (1314:1314:1314) (1320:1320:1320)) + (PORT datad (1042:1042:1042) (1046:1046:1046)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (684:684:684)) + (PORT datab (601:601:601) (636:636:636)) + (PORT datac (1573:1573:1573) (1586:1586:1586)) + (PORT datad (1064:1064:1064) (1076:1076:1076)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (774:774:774)) + (PORT datac (638:638:638) (709:709:709)) + (PORT datad (887:887:887) (942:942:942)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1428:1428:1428)) + (PORT datab (819:819:819) (827:827:827)) + (PORT datac (1383:1383:1383) (1394:1394:1394)) + (PORT datad (1622:1622:1622) (1643:1643:1643)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (324:324:324) (335:335:335)) - (PORT datab (610:610:610) (603:603:603)) - (PORT datac (514:514:514) (501:501:501)) - (PORT datad (566:566:566) (576:576:576)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1118:1118:1118) (1119:1119:1119)) + (PORT datab (1144:1144:1144) (1228:1228:1228)) + (PORT datac (1491:1491:1491) (1649:1649:1649)) + (PORT datad (374:374:374) (390:390:390)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (INSTANCE z80_\|execute_\|ctl_al_we\~4) (DELAY (ABSOLUTE - (PORT dataa (1069:1069:1069) (1097:1097:1097)) - (PORT datab (1114:1114:1114) (1133:1133:1133)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (776:776:776) (750:750:750)) + (PORT dataa (370:370:370) (386:386:386)) + (PORT datab (201:201:201) (234:234:234)) + (PORT datac (1099:1099:1099) (1114:1114:1114)) + (PORT datad (356:356:356) (366:366:366)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1110:1110:1110)) + (PORT datab (1698:1698:1698) (1736:1736:1736)) + (PORT datac (1390:1390:1390) (1397:1397:1397)) + (PORT datad (1200:1200:1200) (1224:1224:1224)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1139:1139:1139)) + (PORT datac (1634:1634:1634) (1654:1654:1654)) + (PORT datad (1050:1050:1050) (1034:1034:1034)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (373:373:373)) + (PORT datab (858:858:858) (856:856:856)) + (PORT datac (563:563:563) (555:555:555)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1219:1219:1219)) + (PORT datab (1810:1810:1810) (1781:1781:1781)) + (PORT datac (740:740:740) (730:730:730)) + (PORT datad (1941:1941:1941) (1896:1896:1896)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1656:1656:1656)) + (PORT datab (1626:1626:1626) (1644:1644:1644)) + (PORT datac (1901:1901:1901) (1928:1928:1928)) + (PORT datad (1133:1133:1133) (1170:1170:1170)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (1609:1609:1609) (1606:1606:1606)) + (PORT datac (1061:1061:1061) (1050:1050:1050)) + (PORT datad (1240:1240:1240) (1225:1225:1225)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1139:1139:1139)) + (PORT datab (547:547:547) (540:540:540)) + (PORT datac (596:596:596) (627:627:627)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1674:1674:1674) (1722:1722:1722)) + (PORT datab (1054:1054:1054) (1052:1052:1052)) + (PORT datac (1042:1042:1042) (1029:1029:1029)) + (PORT datad (1549:1549:1549) (1524:1524:1524)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1051:1051:1051)) + (PORT datab (549:549:549) (561:561:561)) + (PORT datac (1051:1051:1051) (1031:1031:1031)) + (PORT datad (205:205:205) (236:236:236)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (662:662:662)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1025:1025:1025) (1015:1015:1015)) + (PORT datad (604:604:604) (609:609:609)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1163:1163:1163)) + (PORT datab (917:917:917) (942:942:942)) + (PORT datac (543:543:543) (562:562:562)) + (PORT datad (1349:1349:1349) (1376:1376:1376)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) + (INSTANCE z80_\|address_latch_\|Q\[14\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT clk (1338:1338:1338) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1646:1646:1646) (1626:1626:1626)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -20352,626 +10078,65 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1123:1123:1123) (1104:1104:1104)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (831:831:831) (811:811:811)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (832:832:832) (813:813:813)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (292:292:292)) - (PORT datab (1006:1006:1006) (987:987:987)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1125:1125:1125) (1108:1108:1108)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1127:1127:1127) (1106:1106:1106)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (419:419:419)) - (PORT datab (416:416:416) (432:432:432)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (580:580:580) (573:573:573)) - (PORT datac (1216:1216:1216) (1187:1187:1187)) - (PORT datad (1046:1046:1046) (1035:1035:1035)) + (PORT dataa (1414:1414:1414) (1415:1415:1415)) + (PORT datab (2341:2341:2341) (2342:2342:2342)) + (PORT datac (876:876:876) (897:897:897)) + (PORT datad (854:854:854) (848:848:848)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) (DELAY (ABSOLUTE - (PORT dataa (527:527:527) (531:531:531)) - (PORT datab (1047:1047:1047) (1047:1047:1047)) - (PORT datac (994:994:994) (975:975:975)) - (PORT datad (764:764:764) (757:757:757)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (744:744:744)) - (PORT datab (364:364:364) (367:367:367)) - (PORT datac (995:995:995) (970:970:970)) - (PORT datad (1003:1003:1003) (985:985:985)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (611:611:611)) - (PORT datab (1241:1241:1241) (1210:1210:1210)) - (PORT datac (603:603:603) (633:633:633)) - (PORT datad (1053:1053:1053) (1039:1039:1039)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (834:834:834)) - (PORT datab (812:812:812) (813:813:813)) - (PORT datac (1005:1005:1005) (1022:1022:1022)) - (PORT datad (770:770:770) (758:758:758)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (813:813:813)) - (PORT datab (555:555:555) (550:550:550)) - (PORT datac (736:736:736) (725:725:725)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (835:835:835)) - (PORT datab (838:838:838) (823:823:823)) - (PORT datac (740:740:740) (731:731:731)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (1416:1416:1416) (1476:1476:1476)) + (PORT datab (1688:1688:1688) (1815:1815:1815)) + (PORT datac (1626:1626:1626) (1654:1654:1654)) + (PORT datad (1414:1414:1414) (1448:1448:1448)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) (DELAY (ABSOLUTE - (PORT dataa (850:850:850) (845:845:845)) - (PORT datab (824:824:824) (803:803:803)) - (PORT datac (801:801:801) (836:836:836)) - (PORT datad (991:991:991) (983:983:983)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (845:845:845) (826:826:826)) + (PORT datab (887:887:887) (911:911:911)) + (PORT datac (827:827:827) (834:834:834)) + (PORT datad (1368:1368:1368) (1370:1370:1370)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1569:1569:1569) (1544:1544:1544)) - (PORT ena (879:879:879) (881:881:881)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (930:930:930) (945:945:945)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (764:764:764) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (620:620:620)) - (PORT datab (217:217:217) (261:261:261)) - (PORT datad (515:515:515) (529:529:529)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1564:1564:1564) (1524:1524:1524)) - (PORT ena (1081:1081:1081) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1568:1568:1568) (1544:1544:1544)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1561:1561:1561) (1521:1521:1521)) - (PORT ena (1142:1142:1142) (1145:1145:1145)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (685:685:685)) - (PORT datab (625:625:625) (650:650:650)) - (PORT datad (587:587:587) (602:602:602)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (405:405:405)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1334:1334:1334) (1295:1295:1295)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1335:1335:1335) (1297:1297:1297)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (598:598:598)) - (PORT datab (865:865:865) (879:879:879)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (541:541:541)) - (PORT datab (753:753:753) (728:728:728)) - (PORT datac (596:596:596) (608:608:608)) - (PORT datad (768:768:768) (766:766:766)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (639:639:639)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datad (576:576:576) (592:592:592)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (789:789:789)) - (PORT datab (331:331:331) (348:348:348)) - (PORT datac (1058:1058:1058) (1052:1052:1052)) - (PORT datad (617:617:617) (641:641:641)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (616:616:616) (622:622:622)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1353:1353:1353)) - (PORT datab (769:769:769) (738:738:738)) - (PORT datad (606:606:606) (602:602:602)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datad (564:564:564) (562:562:562)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (649:649:649) (694:694:694)) - (PORT datad (741:741:741) (714:714:714)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) (DELAY (ABSOLUTE (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1104:1104:1104) (1124:1124:1124)) - (PORT datad (196:196:196) (228:228:228)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (1012:1012:1012) (1020:1020:1020)) - (PORT datad (580:580:580) (582:582:582)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1868:1868:1868) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1119:1119:1119)) - (PORT datab (834:834:834) (845:845:845)) - (PORT datac (351:351:351) (397:397:397)) - (PORT datad (844:844:844) (876:876:876)) + (PORT datab (646:646:646) (645:645:645)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (819:819:819) (820:820:820)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (363:363:363) (414:414:414)) - (PORT datad (173:173:173) (200:200:200)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20979,14 +10144,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (INSTANCE z80_\|pla_decode_\|Equal62\~2) (DELAY (ABSOLUTE - (PORT dataa (1418:1418:1418) (1444:1444:1444)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (387:387:387) (430:430:430)) - (PORT datad (299:299:299) (301:301:301)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datac (1040:1040:1040) (1046:1046:1046)) + (PORT datad (951:951:951) (1008:1008:1008)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (439:439:439)) + (PORT datab (196:196:196) (233:233:233)) + (PORT datac (833:833:833) (841:841:841)) + (PORT datad (373:373:373) (431:431:431)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1207:1207:1207)) + (PORT datab (1614:1614:1614) (1611:1611:1611)) + (PORT datac (1043:1043:1043) (1045:1045:1045)) + (PORT datad (947:947:947) (1004:1004:1004)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -20995,445 +10188,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT datac (810:810:810) (826:826:826)) - (PORT datad (292:292:292) (301:301:301)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1646:1646:1646) (1626:1626:1626)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (828:828:828) (817:817:817)) - (PORT ena (1110:1110:1110) (1083:1083:1083)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1267:1267:1267) (1244:1244:1244)) - (PORT ena (1148:1148:1148) (1134:1134:1134)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (923:923:923)) - (PORT datab (1199:1199:1199) (1193:1193:1193)) - (PORT datad (765:765:765) (810:810:810)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (1103:1103:1103) (1080:1080:1080)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (885:885:885) (912:912:912)) - (PORT datad (806:806:806) (822:822:822)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1136:1136:1136) (1124:1124:1124)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1136:1136:1136) (1124:1124:1124)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (620:620:620)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datad (592:592:592) (587:587:587)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1109:1109:1109) (1106:1106:1106)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1267:1267:1267) (1242:1242:1242)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (453:453:453)) - (PORT datab (459:459:459) (493:493:493)) - (PORT datad (587:587:587) (589:589:589)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (606:606:606)) - (PORT datab (790:790:790) (780:780:780)) - (PORT datac (538:538:538) (529:529:529)) - (PORT datad (534:534:534) (513:513:513)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1307:1307:1307) (1277:1277:1277)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (989:989:989) (965:965:965)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (939:939:939)) - (PORT datab (888:888:888) (922:922:922)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1104:1104:1104) (1102:1102:1102)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1374:1374:1374)) - (PORT datab (600:600:600) (623:623:623)) - (PORT datad (1513:1513:1513) (1577:1577:1577)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (651:651:651) (655:655:655)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (651:651:651) (655:655:655)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (880:880:880)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (843:843:843) (840:840:840)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (611:611:611)) - (PORT datab (621:621:621) (632:632:632)) - (PORT datac (801:801:801) (815:815:815)) - (PORT datad (300:300:300) (300:300:300)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (514:514:514)) - (PORT datab (369:369:369) (387:387:387)) - (PORT datac (1261:1261:1261) (1240:1240:1240)) - (PORT datad (532:532:532) (517:517:517)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (625:625:625)) - (PORT datab (574:574:574) (594:594:594)) - (PORT datad (532:532:532) (524:524:524)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (372:372:372) (427:427:427)) - (PORT datad (541:541:541) (544:544:544)) + (PORT dataa (895:895:895) (929:929:929)) + (PORT datab (655:655:655) (685:685:685)) + (PORT datac (1378:1378:1378) (1399:1399:1399)) + (PORT datad (1396:1396:1396) (1399:1399:1399)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1382:1382:1382)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1291:1291:1291) (1276:1276:1276)) + (PORT datad (1006:1006:1006) (973:973:973)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (476:476:476)) + (PORT datab (1935:1935:1935) (1941:1941:1941)) + (PORT datac (1039:1039:1039) (1046:1046:1046)) + (PORT datad (948:948:948) (1006:1006:1006)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21441,328 +10236,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) (DELAY (ABSOLUTE - (PORT dataa (392:392:392) (448:448:448)) - (PORT datab (835:835:835) (842:842:842)) - (PORT datac (375:375:375) (430:430:430)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (233:233:233) (287:287:287)) + (PORT datab (799:799:799) (787:787:787)) + (PORT datac (1388:1388:1388) (1405:1405:1405)) + (PORT datad (1016:1016:1016) (1021:1021:1021)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (849:849:849) (836:836:836)) + (PORT datac (587:587:587) (595:595:595)) + (PORT datad (555:555:555) (566:566:566)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (544:544:544)) + (PORT datab (953:953:953) (936:936:936)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (171:171:171) (203:203:203)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1442:1442:1442)) - (PORT datab (356:356:356) (373:373:373)) - (PORT datac (386:386:386) (436:436:436)) - (PORT datad (335:335:335) (334:334:334)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (813:813:813) (831:831:831)) - (PORT datad (309:309:309) (315:315:315)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1646:1646:1646) (1626:1626:1626)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (444:444:444)) - (PORT datab (835:835:835) (840:840:840)) - (PORT datac (373:373:373) (427:427:427)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (1986:1986:1986) (1972:1972:1972)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (1988:1988:1988) (1974:1974:1974)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (886:886:886)) - (PORT datab (876:876:876) (880:880:880)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1804:1804:1804) (1785:1785:1785)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1384:1384:1384)) - (PORT datab (605:605:605) (628:628:628)) - (PORT datad (1521:1521:1521) (1585:1585:1585)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (881:881:881) (886:886:886)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (883:883:883) (885:885:885)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (941:941:941)) - (PORT datab (888:888:888) (922:922:922)) - (PORT datad (334:334:334) (367:367:367)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1620:1620:1620) (1626:1626:1626)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1621:1621:1621) (1627:1627:1627)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (626:626:626)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (593:593:593) (591:591:591)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1747:1747:1747) (1736:1736:1736)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1826:1826:1826) (1808:1808:1808)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (454:454:454)) - (PORT datab (458:458:458) (494:494:494)) - (PORT datad (582:582:582) (581:581:581)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1826:1826:1826) (1810:1810:1810)) - (PORT ena (1148:1148:1148) (1134:1134:1134)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1005:1005:1005)) - (PORT datab (823:823:823) (810:810:810)) - (PORT datac (766:766:766) (742:742:742)) - (PORT datad (1043:1043:1043) (1027:1027:1027)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (1086:1086:1086) (1109:1109:1109)) + (PORT datab (652:652:652) (682:682:682)) + (PORT datac (1457:1457:1457) (1432:1432:1432)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21770,91 +10300,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (656:656:656)) - (PORT datab (1012:1012:1012) (982:982:982)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (884:884:884) (881:881:881)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (1199:1199:1199) (1194:1194:1194)) - (PORT datad (775:775:775) (820:820:820)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (1967:1967:1967) (1956:1956:1956)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (291:291:291)) - (PORT datab (884:884:884) (907:907:907)) - (PORT datad (806:806:806) (819:819:819)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (627:627:627)) - (PORT datab (598:598:598) (627:627:627)) - (PORT datac (571:571:571) (584:584:584)) - (PORT datad (583:583:583) (589:589:589)) + (PORT dataa (1352:1352:1352) (1344:1344:1344)) + (PORT datab (1105:1105:1105) (1132:1132:1132)) + (PORT datac (1118:1118:1118) (1135:1135:1135)) + (PORT datad (1671:1671:1671) (1638:1638:1638)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -21862,488 +10314,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (571:571:571)) - (PORT datab (609:609:609) (625:625:625)) - (PORT datac (777:777:777) (793:793:793)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1271:1271:1271)) - (PORT datab (595:595:595) (625:625:625)) - (PORT datac (511:511:511) (498:498:498)) - (PORT datad (344:344:344) (353:353:353)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT asdata (1050:1050:1050) (1034:1034:1034)) - (PORT ena (1070:1070:1070) (1040:1040:1040)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1498:1498:1498) (1500:1500:1500)) - (PORT datab (542:542:542) (547:547:547)) - (PORT datad (531:531:531) (529:529:529)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (195:195:195) (261:261:261)) - (PORT datad (521:521:521) (519:519:519)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (525:525:525)) - (PORT datab (659:659:659) (681:681:681)) - (PORT datac (353:353:353) (407:407:407)) - (PORT datad (581:581:581) (603:603:603)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (467:467:467)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (490:490:490) (486:486:486)) - (PORT datad (1373:1373:1373) (1406:1406:1406)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (837:837:837) (843:843:843)) - (PORT datac (743:743:743) (739:739:739)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) - (PORT ena (1625:1625:1625) (1596:1596:1596)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (528:528:528)) - (PORT datab (660:660:660) (682:682:682)) - (PORT datac (352:352:352) (402:402:402)) - (PORT datad (582:582:582) (602:602:602)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (448:448:448)) - (PORT datad (168:168:168) (198:198:198)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (884:884:884) (911:911:911)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (884:884:884) (910:910:910)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (940:940:940)) - (PORT datab (894:894:894) (918:918:918)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (621:621:621) (638:638:638)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (621:621:621) (637:637:637)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (886:886:886)) - (PORT datab (881:881:881) (879:879:879)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (826:826:826) (824:824:824)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1579:1579:1579) (1571:1571:1571)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (627:627:627)) - (PORT datab (462:462:462) (494:494:494)) - (PORT datad (581:581:581) (580:580:580)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1579:1579:1579) (1569:1569:1569)) - (PORT ena (1148:1148:1148) (1134:1134:1134)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1034:1034:1034)) - (PORT datab (657:657:657) (680:680:680)) - (PORT datac (1001:1001:1001) (992:992:992)) - (PORT datad (173:173:173) (203:203:203)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1150:1150:1150)) - (PORT datab (753:753:753) (754:754:754)) - (PORT datac (768:768:768) (764:764:764)) - (PORT datad (749:749:749) (718:718:718)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1178:1178:1178)) - (PORT datab (894:894:894) (948:948:948)) - (PORT datac (596:596:596) (619:619:619)) - (PORT datad (1252:1252:1252) (1323:1323:1323)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (343:343:343)) - (PORT datab (834:834:834) (846:846:846)) - (PORT datac (573:573:573) (592:592:592)) - (PORT datad (863:863:863) (894:894:894)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (878:878:878)) - (PORT datab (250:250:250) (308:308:308)) - (PORT datad (790:790:790) (763:763:763)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (311:311:311)) - (PORT datad (791:791:791) (763:763:763)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) (DELAY (ABSOLUTE - (PORT dataa (1858:1858:1858) (1922:1922:1922)) - (PORT datac (1011:1011:1011) (988:988:988)) - (PORT datad (1230:1230:1230) (1341:1341:1341)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (1463:1463:1463) (1498:1498:1498)) + (PORT datac (1437:1437:1437) (1493:1493:1493)) + (PORT datad (600:600:600) (625:625:625)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -22353,12 +10333,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (868:868:868) (854:854:854)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (816:816:816) (834:834:834)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (599:599:599) (623:623:623)) + (PORT datab (1244:1244:1244) (1246:1246:1246)) + (PORT datac (928:928:928) (911:911:911)) + (PORT datad (290:290:290) (297:297:297)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22366,13 +10346,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datac (641:641:641) (687:687:687)) - (PORT datad (784:784:784) (817:817:817)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (216:216:216) (262:262:262)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datad (163:163:163) (187:187:187)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1551:1551:1551)) + (PORT datab (1270:1270:1270) (1246:1246:1246)) + (PORT datac (1281:1281:1281) (1264:1264:1264)) + (PORT datad (1166:1166:1166) (1218:1218:1218)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22380,13 +10376,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) (DELAY (ABSOLUTE - (PORT datab (204:204:204) (239:239:239)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1240:1240:1240) (1231:1231:1231)) + (PORT dataa (593:593:593) (605:605:605)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (578:578:578) (573:573:573)) + (PORT datad (179:179:179) (210:210:210)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (862:862:862)) + (PORT datab (1148:1148:1148) (1171:1171:1171)) + (PORT datac (826:826:826) (836:836:836)) + (PORT datad (573:573:573) (570:570:570)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1364:1364:1364)) + (PORT datab (612:612:612) (623:623:623)) + (PORT datac (1123:1123:1123) (1139:1139:1139)) + (PORT datad (1243:1243:1243) (1219:1219:1219)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2039:2039:2039) (2182:2182:2182)) + (PORT datab (916:916:916) (951:951:951)) + (PORT datac (1383:1383:1383) (1394:1394:1394)) + (PORT datad (1087:1087:1087) (1105:1105:1105)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1190:1190:1190)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1319:1319:1319) (1314:1314:1314)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (863:863:863) (863:863:863)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (1290:1290:1290) (1263:1263:1263)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22394,91 +10472,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) (DELAY (ABSOLUTE - (PORT dataa (1436:1436:1436) (1474:1474:1474)) - (PORT datab (1474:1474:1474) (1502:1502:1502)) - (PORT datac (794:794:794) (811:811:811)) - (PORT datad (369:369:369) (420:420:420)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (457:457:457)) - (PORT datab (547:547:547) (541:541:541)) - (PORT datac (785:785:785) (803:803:803)) - (PORT datad (214:214:214) (255:255:255)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (608:608:608) (607:607:607)) - (PORT ena (1353:1353:1353) (1321:1321:1321)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (579:579:579)) - (PORT datab (1040:1040:1040) (1042:1042:1042)) - (PORT datad (785:785:785) (768:768:768)) + (PORT dataa (878:878:878) (903:903:903)) + (PORT datab (1738:1738:1738) (1814:1814:1814)) + (PORT datac (837:837:837) (874:874:874)) + (PORT datad (662:662:662) (714:714:714)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (585:585:585)) - (PORT datab (1221:1221:1221) (1198:1198:1198)) - (PORT datac (187:187:187) (223:223:223)) - (PORT datad (777:777:777) (764:764:764)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (222:222:222) (282:282:282)) - (PORT datad (322:322:322) (334:334:334)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (864:864:864) (865:865:865)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (861:861:861) (877:877:877)) + (PORT datad (1280:1280:1280) (1243:1243:1243)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -22488,10 +10507,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) (DELAY (ABSOLUTE - (PORT dataa (363:363:363) (372:372:372)) - (PORT datab (940:940:940) (946:946:946)) - (PORT datac (1556:1556:1556) (1555:1555:1555)) - (PORT datad (1101:1101:1101) (1102:1102:1102)) + (PORT dataa (218:218:218) (263:263:263)) + (PORT datab (1065:1065:1065) (1068:1068:1068)) + (PORT datac (1182:1182:1182) (1257:1257:1257)) + (PORT datad (850:850:850) (856:856:856)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -22501,16 +10520,154 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (551:551:551) (543:543:543)) - (PORT datac (838:838:838) (846:846:846)) - (PORT datad (789:789:789) (767:767:767)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1652:1652:1652) (1639:1639:1639)) + (PORT datab (1332:1332:1332) (1295:1295:1295)) + (PORT datac (583:583:583) (594:594:594)) + (PORT datad (839:839:839) (826:826:826)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (863:863:863)) + (PORT datab (1332:1332:1332) (1295:1295:1295)) + (PORT datac (825:825:825) (819:819:819)) + (PORT datad (156:156:156) (177:177:177)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1676:1676:1676) (1712:1712:1712)) + (PORT datab (1449:1449:1449) (1508:1508:1508)) + (PORT datad (197:197:197) (219:219:219)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1060:1060:1060)) + (PORT datab (2105:2105:2105) (2061:2061:2061)) + (PORT datac (1036:1036:1036) (1039:1039:1039)) + (PORT datad (1837:1837:1837) (1884:1884:1884)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1058:1058:1058)) + (PORT datab (1150:1150:1150) (1137:1137:1137)) + (PORT datac (1037:1037:1037) (1035:1035:1035)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (798:798:798)) + (PORT datab (352:352:352) (361:361:361)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (192:192:192) (220:220:220)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (390:390:390)) + (PORT datab (1991:1991:1991) (1977:1977:1977)) + (PORT datac (1089:1089:1089) (1124:1124:1124)) + (PORT datad (1280:1280:1280) (1258:1258:1258)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (346:346:346)) + (PORT datab (1250:1250:1250) (1239:1239:1239)) + (PORT datac (334:334:334) (339:339:339)) + (PORT datad (814:814:814) (831:831:831)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1366:1366:1366)) + (PORT datab (771:771:771) (764:764:764)) + (PORT datac (532:532:532) (525:525:525)) + (PORT datad (842:842:842) (842:842:842)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (887:887:887) (916:916:916)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -22520,23 +10677,23 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) (DELAY (ABSOLUTE - (PORT datab (556:556:556) (548:548:548)) - (PORT datac (222:222:222) (276:276:276)) - (PORT datad (795:795:795) (768:768:768)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1340:1340:1340) (1358:1358:1358)) + (PORT datab (776:776:776) (769:769:769)) + (PORT datad (838:838:838) (873:873:873)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT clk (1337:1337:1337) (1348:1348:1348)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) + (PORT ena (720:720:720) (722:722:722)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22550,1685 +10707,39 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT dataa (818:818:818) (815:815:815)) - (PORT datab (935:935:935) (938:938:938)) - (PORT datac (1560:1560:1560) (1559:1559:1559)) - (PORT datad (1095:1095:1095) (1094:1094:1094)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (917:917:917)) - (PORT datab (995:995:995) (1030:1030:1030)) - (PORT datac (808:808:808) (831:831:831)) - (PORT datad (591:591:591) (601:601:601)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (654:654:654)) - (PORT datab (600:600:600) (618:618:618)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (855:855:855) (853:853:853)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (649:649:649)) - (PORT datab (606:606:606) (634:634:634)) - (PORT datac (573:573:573) (590:590:590)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1415:1415:1415)) - (PORT datab (880:880:880) (872:872:872)) - (PORT datac (546:546:546) (534:534:534)) - (PORT datad (1425:1425:1425) (1498:1498:1498)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (835:835:835)) - (PORT datab (911:911:911) (930:930:930)) - (PORT datac (1315:1315:1315) (1296:1296:1296)) - (PORT datad (600:600:600) (610:610:610)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1193:1193:1193)) - (PORT datab (579:579:579) (582:582:582)) - (PORT datac (1353:1353:1353) (1363:1363:1363)) - (PORT datad (579:579:579) (570:570:570)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1139:1139:1139)) - (PORT datab (1160:1160:1160) (1170:1170:1170)) - (PORT datac (820:820:820) (830:830:830)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1193:1193:1193)) - (PORT datab (1176:1176:1176) (1216:1216:1216)) - (PORT datac (1960:1960:1960) (2010:2010:2010)) - (PORT datad (1339:1339:1339) (1343:1343:1343)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (360:360:360)) - (PORT datab (611:611:611) (596:596:596)) - (PORT datac (330:330:330) (335:335:335)) - (PORT datad (296:296:296) (297:297:297)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (161:161:161) (195:195:195)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (352:352:352)) - (PORT datab (309:309:309) (330:330:330)) - (PORT datac (804:804:804) (778:778:778)) - (PORT datad (559:559:559) (570:570:570)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (264:264:264)) - (PORT datab (818:818:818) (798:798:798)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (881:881:881)) - (PORT datab (199:199:199) (230:230:230)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (562:562:562) (571:571:571)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1219:1219:1219)) - (PORT datab (618:618:618) (637:637:637)) - (PORT datac (593:593:593) (620:620:620)) - (PORT datad (855:855:855) (853:853:853)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (572:572:572) (592:592:592)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (618:618:618)) - (PORT datab (223:223:223) (260:260:260)) - (PORT datac (774:774:774) (753:753:753)) - (PORT datad (777:777:777) (764:764:764)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (455:455:455)) - (PORT datab (809:809:809) (800:800:800)) - (PORT datac (560:560:560) (580:580:580)) - (PORT datad (523:523:523) (522:522:522)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1120:1120:1120)) - (PORT datab (533:533:533) (524:524:524)) - (PORT datac (799:799:799) (782:782:782)) - (PORT datad (1667:1667:1667) (1701:1701:1701)) + (PORT dataa (1591:1591:1591) (1564:1564:1564)) + (PORT datab (206:206:206) (242:242:242)) + (PORT datac (1899:1899:1899) (1949:1949:1949)) + (PORT datad (196:196:196) (217:217:217)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1123:1123:1123)) - (PORT datab (531:531:531) (525:525:525)) - (PORT datac (797:797:797) (783:783:783)) - (PORT datad (1668:1668:1668) (1704:1704:1704)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (269:269:269)) - (PORT datab (517:517:517) (508:508:508)) - (PORT datac (203:203:203) (242:242:242)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (194:194:194) (237:237:237)) - (PORT datad (186:186:186) (214:214:214)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (247:247:247)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (774:774:774) (742:742:742)) - (PORT datac (515:515:515) (511:511:511)) - (PORT datad (309:309:309) (313:313:313)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) - (PORT asdata (635:635:635) (632:632:632)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (967:967:967)) - (PORT datab (608:608:608) (629:629:629)) - (PORT datac (586:586:586) (612:612:612)) - (PORT datad (545:545:545) (540:540:540)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datac (572:572:572) (588:588:588)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (966:966:966)) - (PORT datab (1469:1469:1469) (1503:1503:1503)) - (PORT datac (793:793:793) (813:813:813)) - (PORT datad (384:384:384) (439:439:439)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (656:656:656) (718:718:718)) - (PORT datad (777:777:777) (814:814:814)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (827:827:827)) - (PORT datab (1303:1303:1303) (1276:1276:1276)) - (PORT datac (183:183:183) (219:219:219)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (464:464:464)) - (PORT datab (244:244:244) (295:295:295)) - (PORT datad (557:557:557) (566:566:566)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (807:807:807)) - (PORT datab (743:743:743) (786:786:786)) - (PORT datac (568:568:568) (558:558:558)) - (PORT datad (572:572:572) (578:578:578)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (206:206:206) (244:244:244)) - (PORT datac (792:792:792) (794:794:794)) - (PORT datad (607:607:607) (602:602:602)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (1577:1577:1577) (1638:1638:1638)) - (PORT ena (1360:1360:1360) (1335:1335:1335)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (1577:1577:1577) (1638:1638:1638)) - (PORT ena (1371:1371:1371) (1356:1356:1356)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (879:879:879)) - (PORT datab (876:876:876) (872:872:872)) - (PORT datad (195:195:195) (251:251:251)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1545:1545:1545) (1584:1584:1584)) - (PORT ena (1425:1425:1425) (1417:1417:1417)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (991:991:991) (1028:1028:1028)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1335:1335:1335) (1310:1310:1310)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (935:935:935)) - (PORT datab (893:893:893) (917:917:917)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1304:1304:1304) (1350:1350:1350)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1382:1382:1382)) - (PORT datab (606:606:606) (628:628:628)) - (PORT datad (1522:1522:1522) (1583:1583:1583)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (883:883:883) (891:891:891)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (883:883:883) (890:890:890)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (860:860:860)) - (PORT datab (885:885:885) (914:914:914)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1085:1085:1085) (1138:1138:1138)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1310:1310:1310) (1357:1357:1357)) - (PORT ena (1096:1096:1096) (1054:1054:1054)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (617:617:617)) - (PORT datab (424:424:424) (468:468:468)) - (PORT datad (590:590:590) (591:591:591)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1311:1311:1311) (1358:1358:1358)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (1311:1311:1311) (1359:1359:1359)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (619:619:619)) - (PORT datab (218:218:218) (286:286:286)) - (PORT datad (598:598:598) (595:595:595)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (1308:1308:1308) (1355:1355:1355)) - (PORT ena (1148:1148:1148) (1134:1134:1134)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (921:921:921)) - (PORT datab (1201:1201:1201) (1195:1195:1195)) - (PORT datad (746:746:746) (790:790:790)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (362:362:362)) - (PORT datab (797:797:797) (829:829:829)) - (PORT datac (534:534:534) (558:558:558)) - (PORT datad (747:747:747) (746:746:746)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (546:546:546)) - (PORT datab (778:778:778) (773:773:773)) - (PORT datac (570:570:570) (589:589:589)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT datab (836:836:836) (837:837:837)) - (PORT datad (809:809:809) (778:778:778)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) - (PORT ena (1625:1625:1625) (1596:1596:1596)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (450:450:450)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (542:542:542) (564:564:564)) - (PORT datad (620:620:620) (647:647:647)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (698:698:698) (715:715:715)) - (PORT ena (1110:1110:1110) (1083:1083:1083)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (572:572:572) (590:590:590)) - (PORT datad (521:521:521) (524:524:524)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT asdata (486:486:486) (513:513:513)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (561:561:561) (577:577:577)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (366:366:366) (412:412:412)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1441:1441:1441)) - (PORT datab (503:503:503) (498:498:498)) - (PORT datac (386:386:386) (430:430:430)) - (PORT datad (321:321:321) (335:335:335)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (1278:1278:1278) (1262:1262:1262)) - (PORT datac (390:390:390) (409:409:409)) - (PORT datad (188:188:188) (217:217:217)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (961:961:961)) - (PORT datab (820:820:820) (812:812:812)) - (PORT datac (1172:1172:1172) (1225:1225:1225)) - (PORT datad (978:978:978) (966:966:966)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (663:663:663)) - (PORT datab (1010:1010:1010) (977:977:977)) - (PORT datac (923:923:923) (929:929:929)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (686:686:686) (745:745:745)) - (PORT datac (179:179:179) (212:212:212)) - (PORT datad (207:207:207) (232:232:232)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (814:814:814) (847:847:847)) - (PORT datac (1276:1276:1276) (1252:1252:1252)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (608:608:608)) - (PORT datab (378:378:378) (415:415:415)) - (PORT datac (790:790:790) (805:805:805)) - (PORT datad (216:216:216) (256:256:256)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (639:639:639)) - (PORT datab (799:799:799) (794:794:794)) - (PORT datac (1883:1883:1883) (1857:1857:1857)) - (PORT datad (770:770:770) (835:835:835)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (396:396:396)) - (PORT datab (1221:1221:1221) (1198:1198:1198)) - (PORT datac (571:571:571) (572:572:572)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (821:821:821)) - (PORT datab (329:329:329) (344:344:344)) - (PORT datac (563:563:563) (557:557:557)) - (PORT datad (587:587:587) (585:585:585)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (845:845:845)) - (PORT datab (554:554:554) (552:552:552)) - (PORT datac (177:177:177) (210:210:210)) - (PORT datad (756:756:756) (736:736:736)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (664:664:664)) - (PORT datab (815:815:815) (827:827:827)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (198:198:198) (232:232:232)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (924:924:924)) - (PORT datab (1197:1197:1197) (1189:1189:1189)) - (PORT datad (1253:1253:1253) (1295:1295:1295)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1356:1356:1356) (1345:1345:1345)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT asdata (834:834:834) (832:832:832)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (290:290:290)) - (PORT datab (886:886:886) (907:907:907)) - (PORT datad (805:805:805) (818:818:818)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (886:886:886) (906:906:906)) - (PORT ena (1076:1076:1076) (1044:1044:1044)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (889:889:889) (908:908:908)) - (PORT ena (1114:1114:1114) (1081:1081:1081)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (625:625:625)) - (PORT datab (356:356:356) (400:400:400)) - (PORT datad (591:591:591) (585:585:585)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (977:977:977) (982:982:982)) - (PORT datad (305:305:305) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1117:1117:1117) (1124:1124:1124)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1383:1383:1383)) - (PORT datab (605:605:605) (629:629:629)) - (PORT datad (1520:1520:1520) (1585:1585:1585)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (752:752:752)) - (PORT datab (847:847:847) (839:839:839)) - (PORT datac (312:312:312) (319:319:319)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (561:561:561)) - (PORT datab (593:593:593) (622:622:622)) - (PORT datac (1258:1258:1258) (1243:1243:1243)) - (PORT datad (346:346:346) (358:358:358)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT asdata (800:800:800) (787:787:787)) - (PORT ena (1070:1070:1070) (1040:1040:1040)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (539:539:539)) - (PORT datab (573:573:573) (590:590:590)) - (PORT datac (396:396:396) (439:439:439)) - (PORT datad (524:524:524) (527:527:527)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (459:459:459)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (541:541:541) (542:542:542)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1438:1438:1438)) - (PORT datab (554:554:554) (533:533:533)) - (PORT datac (391:391:391) (437:437:437)) - (PORT datad (323:323:323) (337:337:337)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (837:837:837) (841:841:841)) - (PORT datac (723:723:723) (696:696:696)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) - (PORT ena (1625:1625:1625) (1596:1596:1596)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datab (658:658:658) (677:677:677)) - (PORT datac (364:364:364) (414:414:414)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (790:790:790)) - (PORT datad (801:801:801) (805:805:805)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) - (PORT ena (1625:1625:1625) (1596:1596:1596)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1073:1073:1073)) - (PORT datab (374:374:374) (420:420:420)) - (PORT datac (616:616:616) (631:631:631)) - (PORT datad (1064:1064:1064) (1060:1060:1060)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (193:193:193) (232:232:232)) - (PORT datac (514:514:514) (536:536:536)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1443:1443:1443)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (387:387:387) (433:433:433)) - (PORT datad (499:499:499) (478:478:478)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (565:565:565)) - (PORT datab (370:370:370) (392:392:392)) - (PORT datac (1258:1258:1258) (1242:1242:1242)) - (PORT datad (519:519:519) (498:498:498)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1110:1110:1110)) - (PORT datab (823:823:823) (810:810:810)) - (PORT datac (524:524:524) (520:520:520)) - (PORT datad (979:979:979) (962:962:962)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (662:662:662)) - (PORT datab (1010:1010:1010) (981:981:981)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (745:745:745) (785:785:785)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (437:437:437)) - (PORT datab (1716:1716:1716) (1738:1738:1738)) - (PORT datac (965:965:965) (989:989:989)) - (PORT datad (223:223:223) (282:282:282)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (754:754:754)) - (PORT datab (359:359:359) (365:365:365)) - (PORT datac (222:222:222) (280:280:280)) - (PORT datad (326:326:326) (320:320:320)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (387:387:387)) - (PORT datab (555:555:555) (547:547:547)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (794:794:794) (766:766:766)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (387:387:387)) - (PORT datab (252:252:252) (313:313:313)) - (PORT datad (792:792:792) (765:765:765)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT datab (774:774:774) (767:767:767)) + (PORT datac (533:533:533) (523:523:523)) + (PORT datad (840:840:840) (876:876:876)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (773:773:773) (770:770:770)) + (PORT datad (845:845:845) (878:878:878)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -24238,7 +10749,7 @@ (INSTANCE z80_\|alu_\|op1_high\[3\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT clk (1337:1337:1337) (1348:1348:1348)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -24251,29 +10762,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) (DELAY (ABSOLUTE - (PORT dataa (810:810:810) (820:820:820)) - (PORT datab (660:660:660) (694:694:694)) - (PORT datad (823:823:823) (807:807:807)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (626:626:626)) - (PORT datab (564:564:564) (558:558:558)) - (PORT datac (221:221:221) (276:276:276)) - (PORT datad (518:518:518) (512:512:512)) + (PORT dataa (841:841:841) (842:842:842)) + (PORT datab (1114:1114:1114) (1161:1161:1161)) + (PORT datac (1789:1789:1789) (1795:1795:1795)) + (PORT datad (836:836:836) (842:842:842)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24281,107 +10778,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) (DELAY (ABSOLUTE - (PORT datab (820:820:820) (801:801:801)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (535:535:535)) - (PORT datab (658:658:658) (700:700:700)) - (PORT datac (885:885:885) (940:940:940)) - (PORT datad (921:921:921) (950:950:950)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (647:647:647)) - (PORT datab (581:581:581) (574:574:574)) - (PORT datac (574:574:574) (593:593:593)) - (PORT datad (334:334:334) (345:345:345)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (476:476:476)) - (PORT datab (813:813:813) (805:805:805)) - (PORT datac (490:490:490) (477:477:477)) - (PORT datad (369:369:369) (417:417:417)) + (PORT dataa (1021:1021:1021) (1005:1005:1005)) + (PORT datab (646:646:646) (648:648:648)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (739:739:739) (733:733:733)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (437:437:437)) - (PORT datab (950:950:950) (972:972:972)) - (PORT datac (756:756:756) (767:767:767)) - (PORT datad (577:577:577) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24389,103 +10794,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (359:359:359)) - (PORT datab (1132:1132:1132) (1157:1157:1157)) - (PORT datac (638:638:638) (670:670:670)) - (PORT datad (823:823:823) (809:809:809)) + (PORT dataa (1533:1533:1533) (1563:1563:1563)) + (PORT datab (1015:1015:1015) (1042:1042:1042)) + (PORT datac (588:588:588) (588:588:588)) + (PORT datad (626:626:626) (664:664:664)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (353:353:353) (364:364:364)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (587:587:587)) - (PORT datab (193:193:193) (233:233:233)) - (PORT datac (541:541:541) (538:538:538)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (401:401:401)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (312:312:312) (315:315:315)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT datab (601:601:601) (618:618:618)) - (PORT datac (753:753:753) (743:743:743)) - (PORT datad (606:606:606) (613:613:613)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (759:759:759)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datad (324:324:324) (332:332:332)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (246:246:246)) - (PORT datab (625:625:625) (622:622:622)) - (PORT datac (777:777:777) (784:784:784)) - (PORT datad (863:863:863) (853:853:853)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -24493,521 +10810,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) (DELAY (ABSOLUTE - (PORT dataa (882:882:882) (904:904:904)) - (PORT datab (195:195:195) (235:235:235)) - (PORT datac (508:508:508) (499:499:499)) - (PORT datad (1145:1145:1145) (1151:1151:1151)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1223:1223:1223)) - (PORT datab (2112:2112:2112) (2126:2126:2126)) - (PORT datac (1100:1100:1100) (1126:1126:1126)) - (PORT datad (1243:1243:1243) (1209:1209:1209)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (554:554:554)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1156:1156:1156) (1179:1179:1179)) - (PORT datad (873:873:873) (892:892:892)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (491:491:491)) - (PORT datab (794:794:794) (782:782:782)) - (PORT datac (512:512:512) (501:501:501)) - (PORT datad (565:565:565) (570:570:570)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (780:780:780) (769:769:769)) - (PORT datac (768:768:768) (753:753:753)) - (PORT datad (1090:1090:1090) (1112:1112:1112)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1655:1655:1655) (1695:1695:1695)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (1695:1695:1695) (1758:1758:1758)) - (PORT datad (1473:1473:1473) (1563:1563:1563)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (1536:1536:1536) (1543:1543:1543)) - (PORT datac (1305:1305:1305) (1273:1273:1273)) - (PORT datad (2107:2107:2107) (2143:2143:2143)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (164:164:164) (191:191:191)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (324:324:324)) - (PORT datab (1718:1718:1718) (1741:1741:1741)) - (PORT datac (1012:1012:1012) (1011:1011:1011)) - (PORT datad (224:224:224) (284:284:284)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (321:321:321)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (870:870:870) (910:910:910)) - (PORT datac (988:988:988) (999:999:999)) - (PORT datad (578:578:578) (576:576:576)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1460:1460:1460)) - (PORT datab (884:884:884) (896:896:896)) - (PORT datac (955:955:955) (932:932:932)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (616:616:616)) - (PORT datab (252:252:252) (311:311:311)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (513:513:513) (507:507:507)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (819:819:819) (799:799:799)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (477:477:477)) - (PORT datab (1469:1469:1469) (1504:1504:1504)) - (PORT datac (793:793:793) (815:815:815)) - (PORT datad (564:564:564) (581:581:581)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1357:1357:1357)) - (PORT asdata (609:609:609) (621:621:621)) - (PORT ena (1415:1415:1415) (1385:1385:1385)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (460:460:460)) - (PORT datab (545:545:545) (541:541:541)) - (PORT datac (786:786:786) (803:803:803)) - (PORT datad (215:215:215) (257:257:257)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (817:817:817)) - (PORT datab (342:342:342) (349:349:349)) - (PORT datad (553:553:553) (558:558:558)) + (PORT dataa (843:843:843) (856:856:856)) + (PORT datab (557:557:557) (549:549:549)) + (PORT datac (1816:1816:1816) (1813:1813:1813)) + (PORT datad (609:609:609) (611:611:611)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (752:752:752)) - (PORT datab (616:616:616) (611:611:611)) - (PORT datac (530:530:530) (519:519:519)) - (PORT datad (324:324:324) (318:318:318)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (889:889:889)) - (PORT datab (992:992:992) (1029:1029:1029)) - (PORT datac (543:543:543) (573:573:573)) - (PORT datad (587:587:587) (599:599:599)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (653:653:653)) - (PORT datab (930:930:930) (943:943:943)) - (PORT datac (574:574:574) (594:594:594)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (646:646:646)) - (PORT datab (609:609:609) (630:630:630)) - (PORT datac (538:538:538) (533:533:533)) - (PORT datad (904:904:904) (907:907:907)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (574:574:574) (592:592:592)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (471:471:471)) - (PORT datab (547:547:547) (556:556:556)) - (PORT datac (397:397:397) (457:457:457)) - (PORT datad (771:771:771) (770:770:770)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (275:275:275)) - (PORT datab (515:515:515) (508:508:508)) - (PORT datac (522:522:522) (517:517:517)) - (PORT datad (1009:1009:1009) (986:986:986)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) (DELAY (ABSOLUTE - (PORT dataa (802:802:802) (802:802:802)) - (PORT datab (1008:1008:1008) (967:967:967)) - (PORT datac (745:745:745) (731:731:731)) - (PORT datad (735:735:735) (712:712:712)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT datab (201:201:201) (245:245:245)) - (PORT datac (193:193:193) (234:234:234)) - (PORT datad (780:780:780) (771:771:771)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (202:202:202) (246:246:246)) - (PORT datac (193:193:193) (231:231:231)) - (PORT datad (781:781:781) (771:771:771)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1399:1399:1399) (1416:1416:1416)) - (PORT datab (1354:1354:1354) (1338:1338:1338)) - (PORT datac (1714:1714:1714) (1656:1656:1656)) - (PORT datad (1239:1239:1239) (1207:1207:1207)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1027:1027:1027) (1009:1009:1009)) - (PORT datab (1279:1279:1279) (1304:1304:1304)) - (PORT datac (750:750:750) (729:729:729)) - (PORT datad (1220:1220:1220) (1202:1202:1202)) + (PORT dataa (651:651:651) (692:692:692)) + (PORT datab (1477:1477:1477) (1526:1526:1526)) + (PORT datac (1431:1431:1431) (1485:1485:1485)) + (PORT datad (1428:1428:1428) (1463:1463:1463)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -25017,77 +10842,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) (DELAY (ABSOLUTE - (PORT dataa (1800:1800:1800) (1837:1837:1837)) - (PORT datab (192:192:192) (231:231:231)) - (PORT datac (1807:1807:1807) (1845:1845:1845)) - (PORT datad (1499:1499:1499) (1475:1475:1475)) + (PORT dataa (784:784:784) (828:828:828)) + (PORT datab (995:995:995) (981:981:981)) + (PORT datac (724:724:724) (701:701:701)) + (PORT datad (752:752:752) (806:806:806)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) (DELAY (ABSOLUTE - (PORT dataa (1048:1048:1048) (1024:1024:1024)) - (PORT datab (344:344:344) (356:356:356)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (769:769:769) (762:762:762)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (494:494:494) (478:478:478)) - (PORT datad (539:539:539) (526:526:526)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (1629:1629:1629) (1629:1629:1629)) - (PORT datac (1086:1086:1086) (1089:1089:1089)) - (PORT datad (1335:1335:1335) (1317:1317:1317)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (309:309:309)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (225:225:225) (280:280:280)) - (PORT datad (1118:1118:1118) (1123:1123:1123)) + (PORT dataa (321:321:321) (337:337:337)) + (PORT datab (560:560:560) (557:557:557)) + (PORT datac (510:510:510) (499:499:499)) + (PORT datad (1242:1242:1242) (1271:1271:1271)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -25095,63 +10874,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) (DELAY (ABSOLUTE - (PORT dataa (2040:2040:2040) (2130:2130:2130)) - (PORT datab (1459:1459:1459) (1528:1528:1528)) - (PORT datac (1628:1628:1628) (1684:1684:1684)) - (PORT datad (800:800:800) (799:799:799)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (1718:1718:1718) (1764:1764:1764)) - (PORT datac (562:562:562) (570:570:570)) - (PORT datad (871:871:871) (875:875:875)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1673:1673:1673) (1700:1700:1700)) - (PORT datab (1321:1321:1321) (1291:1291:1291)) - (PORT datac (1307:1307:1307) (1298:1298:1298)) - (PORT datad (2153:2153:2153) (2218:2218:2218)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1451:1451:1451)) - (PORT datab (1131:1131:1131) (1128:1128:1128)) - (PORT datac (1306:1306:1306) (1296:1296:1296)) - (PORT datad (1510:1510:1510) (1535:1535:1535)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (1729:1729:1729) (1844:1844:1844)) + (PORT datab (1429:1429:1429) (1483:1483:1483)) + (PORT datac (754:754:754) (743:743:743)) + (PORT datad (1703:1703:1703) (1723:1723:1723)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -25159,47 +10890,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (INSTANCE z80_\|pla_decode_\|Equal21\~2) (DELAY (ABSOLUTE - (PORT dataa (1342:1342:1342) (1328:1328:1328)) - (PORT datab (627:627:627) (661:661:661)) - (PORT datac (1101:1101:1101) (1098:1098:1098)) - (PORT datad (1545:1545:1545) (1549:1549:1549)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (587:587:587)) - (PORT datab (1859:1859:1859) (1914:1914:1914)) - (PORT datac (1427:1427:1427) (1486:1486:1486)) - (PORT datad (2153:2153:2153) (2218:2218:2218)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1427:1427:1427) (1452:1452:1452)) - (PORT datab (623:623:623) (657:657:657)) - (PORT datac (1412:1412:1412) (1466:1466:1466)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (294:294:294)) + (PORT datab (1312:1312:1312) (1331:1331:1331)) + (PORT datac (193:193:193) (237:237:237)) + (PORT datad (908:908:908) (951:951:951)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -25207,13 +10904,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (624:624:624) (664:664:664)) - (PORT datac (1852:1852:1852) (1859:1859:1859)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (803:803:803) (809:809:809)) + (PORT datab (888:888:888) (900:900:900)) + (PORT datac (1789:1789:1789) (1797:1797:1797)) + (PORT datad (1078:1078:1078) (1136:1136:1136)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1050:1050:1050) (1023:1023:1023)) + (PORT datab (852:852:852) (888:888:888)) + (PORT datac (353:353:353) (377:377:377)) + (PORT datad (569:569:569) (573:573:573)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -25223,3413 +10936,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_alu_op_low) (DELAY (ABSOLUTE - (PORT dataa (317:317:317) (333:333:333)) - (PORT datab (351:351:351) (354:354:354)) - (PORT datac (297:297:297) (309:309:309)) - (PORT datad (814:814:814) (820:820:820)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (620:620:620)) - (PORT datab (592:592:592) (602:602:602)) - (PORT datac (1096:1096:1096) (1096:1096:1096)) - (PORT datad (342:342:342) (343:343:343)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (877:877:877)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (1289:1289:1289) (1272:1272:1272)) - (PORT datad (582:582:582) (573:573:573)) + (PORT dataa (613:613:613) (639:639:639)) + (PORT datab (831:831:831) (829:829:829)) + (PORT datac (1463:1463:1463) (1404:1404:1404)) + (PORT datad (164:164:164) (189:189:189)) (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (621:621:621)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (1092:1092:1092) (1094:1094:1094)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (598:598:598)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (541:541:541) (532:532:532)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1399:1399:1399) (1416:1416:1416)) - (PORT datab (1354:1354:1354) (1338:1338:1338)) - (PORT datac (984:984:984) (963:963:963)) - (PORT datad (1238:1238:1238) (1207:1207:1207)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (873:873:873) (864:864:864)) - (PORT datac (837:837:837) (872:872:872)) - (PORT datad (2087:2087:2087) (2094:2094:2094)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1262:1262:1262)) - (PORT datab (1182:1182:1182) (1204:1204:1204)) - (PORT datac (839:839:839) (873:873:873)) - (PORT datad (1075:1075:1075) (1079:1079:1079)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1332:1332:1332)) - (PORT datab (913:913:913) (931:931:931)) - (PORT datac (358:358:358) (360:360:360)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (359:359:359)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (493:493:493) (473:473:473)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (808:808:808)) - (PORT datab (611:611:611) (601:601:601)) - (PORT datac (321:321:321) (323:323:323)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (777:777:777)) - (PORT datab (595:595:595) (598:598:598)) - (PORT datac (755:755:755) (731:731:731)) - (PORT datad (1146:1146:1146) (1162:1162:1162)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (619:619:619)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (519:519:519) (507:507:507)) - (PORT datac (162:162:162) (198:198:198)) - (PORT datad (543:543:543) (542:542:542)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (489:489:489)) - (PORT datab (1469:1469:1469) (1503:1503:1503)) - (PORT datac (925:925:925) (967:967:967)) - (PORT datad (785:785:785) (793:793:793)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (717:717:717)) - (PORT datac (184:184:184) (221:221:221)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (653:653:653)) - (PORT datab (1266:1266:1266) (1266:1266:1266)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (608:608:608)) - (PORT datab (378:378:378) (415:415:415)) - (PORT datac (790:790:790) (805:805:805)) - (PORT datad (217:217:217) (255:255:255)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (790:790:790)) - (PORT datab (1218:1218:1218) (1197:1197:1197)) - (PORT datac (706:706:706) (767:767:767)) - (PORT datad (697:697:697) (710:710:710)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (820:820:820)) - (PORT datab (326:326:326) (344:344:344)) - (PORT datac (531:531:531) (520:520:520)) - (PORT datad (589:589:589) (588:588:588)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (614:614:614)) - (PORT datab (251:251:251) (308:308:308)) - (PORT datad (790:790:790) (764:764:764)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (954:954:954) (980:980:980)) - (PORT datac (925:925:925) (967:967:967)) - (PORT datad (563:563:563) (580:580:580)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (471:471:471)) - (PORT datab (549:549:549) (552:552:552)) - (PORT datac (397:397:397) (454:454:454)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (227:227:227)) - (PORT datab (809:809:809) (799:799:799)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (546:546:546) (546:546:546)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (274:274:274)) - (PORT datab (231:231:231) (272:272:272)) - (PORT datac (487:487:487) (482:482:482)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (401:401:401)) - (PORT datab (370:370:370) (370:370:370)) - (PORT datac (357:357:357) (358:358:358)) - (PORT datad (316:316:316) (315:315:315)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (358:358:358)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (543:543:543) (540:540:540)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (566:566:566) (562:562:562)) - (PORT datac (165:165:165) (203:203:203)) - (PORT datad (163:163:163) (186:186:186)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1357:1357:1357)) - (PORT asdata (505:505:505) (532:532:532)) - (PORT ena (1415:1415:1415) (1385:1385:1385)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (352:352:352) (401:401:401)) - (PORT datad (783:783:783) (765:765:765)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (847:847:847)) - (PORT datab (655:655:655) (699:699:699)) - (PORT datac (1440:1440:1440) (1468:1468:1468)) - (PORT datad (369:369:369) (418:418:418)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (450:450:450)) - (PORT datad (555:555:555) (565:565:565)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (741:741:741)) - (PORT datab (1012:1012:1012) (1032:1032:1032)) - (PORT datac (350:350:350) (370:370:370)) - (PORT datad (829:829:829) (834:834:834)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (728:728:728)) - (PORT datab (624:624:624) (619:619:619)) - (PORT datac (324:324:324) (327:327:327)) - (PORT datad (303:303:303) (311:311:311)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1011:1011:1011)) - (PORT datab (824:824:824) (815:815:815)) - (PORT datac (946:946:946) (983:983:983)) - (PORT datad (913:913:913) (917:917:917)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (1010:1010:1010) (979:979:979)) - (PORT datac (499:499:499) (483:483:483)) - (PORT datad (609:609:609) (624:624:624)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (591:591:591)) - (PORT datab (623:623:623) (646:646:646)) - (PORT datac (1212:1212:1212) (1181:1181:1181)) - (PORT datad (1054:1054:1054) (1041:1041:1041)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (919:919:919)) - (PORT datab (1035:1035:1035) (1029:1029:1029)) - (PORT datad (997:997:997) (970:970:970)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (354:354:354) (408:408:408)) - (PORT datac (354:354:354) (393:393:393)) - (PORT datad (355:355:355) (398:398:398)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (933:933:933)) - (PORT datab (2115:2115:2115) (2149:2149:2149)) - (PORT datad (2019:2019:2019) (2122:2122:2122)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (567:567:567) (579:579:579)) - (PORT datac (747:747:747) (734:734:734)) - (PORT datad (1318:1318:1318) (1297:1297:1297)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (1306:1306:1306) (1297:1297:1297)) - (PORT datad (167:167:167) (194:194:194)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1146:1146:1146)) - (PORT datab (875:875:875) (875:875:875)) - (PORT datac (1120:1120:1120) (1121:1121:1121)) - (PORT datad (1102:1102:1102) (1091:1091:1091)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (316:316:316)) - (PORT datab (1624:1624:1624) (1625:1625:1625)) - (PORT datac (220:220:220) (271:271:271)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (595:595:595)) - (PORT datab (188:188:188) (222:222:222)) - (PORT datac (1010:1010:1010) (989:989:989)) - (PORT datad (166:166:166) (191:191:191)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (777:777:777) (785:785:785)) - (PORT datab (847:847:847) (855:855:855)) - (PORT datac (775:775:775) (775:775:775)) - (PORT datad (765:765:765) (746:746:746)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (817:817:817)) - (PORT datab (185:185:185) (219:219:219)) - (PORT datac (585:585:585) (604:604:604)) - (PORT datad (574:574:574) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (774:774:774)) - (PORT datab (187:187:187) (221:221:221)) - (PORT datac (811:811:811) (818:818:818)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (301:301:301)) - (PORT datab (1049:1049:1049) (1067:1067:1067)) - (PORT datad (1139:1139:1139) (1125:1125:1125)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (493:493:493) (524:524:524)) - (PORT ena (1141:1141:1141) (1133:1133:1133)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (854:854:854) (864:864:864)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (764:764:764) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1128:1128:1128)) - (PORT datab (620:620:620) (664:664:664)) - (PORT datad (809:809:809) (837:837:837)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (586:586:586) (604:604:604)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (493:493:493) (524:524:524)) - (PORT ena (1173:1173:1173) (1181:1181:1181)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (695:695:695)) - (PORT datab (672:672:672) (698:698:698)) - (PORT datad (955:955:955) (935:935:935)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (610:610:610)) - (PORT datab (566:566:566) (581:581:581)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (363:363:363)) - (PORT datab (571:571:571) (585:585:585)) - (PORT datac (290:290:290) (293:293:293)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (236:236:236)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (757:757:757) (755:755:755)) - (PORT datad (1052:1052:1052) (1029:1029:1029)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1133:1133:1133) (1116:1116:1116)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1005:1005:1005)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datad (1038:1038:1038) (1010:1010:1010)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1145:1145:1145) (1120:1120:1120)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (579:579:579) (570:570:570)) - (PORT datac (604:604:604) (619:619:619)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (405:405:405)) - (PORT datab (581:581:581) (583:583:583)) - (PORT datac (1094:1094:1094) (1111:1111:1111)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1028:1028:1028)) - (PORT datad (813:813:813) (807:807:807)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1868:1868:1868) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1229:1229:1229)) - (PORT datad (346:346:346) (350:350:350)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT asdata (857:857:857) (867:867:867)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) - (PORT ena (1861:1861:1861) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (595:595:595)) - (PORT datab (571:571:571) (566:566:566)) - (PORT datac (547:547:547) (581:581:581)) - (PORT datad (608:608:608) (646:646:646)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (458:458:458)) - (PORT datab (573:573:573) (569:569:569)) - (PORT datac (560:560:560) (587:587:587)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1123:1123:1123) (1104:1104:1104)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (485:485:485) (513:513:513)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (873:873:873) (867:867:867)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (872:872:872) (866:866:866)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (290:290:290)) - (PORT datab (1005:1005:1005) (990:990:990)) - (PORT datad (326:326:326) (367:367:367)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1634:1634:1634) (1674:1674:1674)) - (PORT ena (879:879:879) (881:881:881)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1634:1634:1634) (1674:1674:1674)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datad (193:193:193) (220:220:220)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1637:1637:1637) (1669:1669:1669)) - (PORT ena (1142:1142:1142) (1145:1145:1145)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1122:1122:1122)) - (PORT datab (628:628:628) (651:651:651)) - (PORT datad (778:778:778) (768:768:768)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1638:1638:1638) (1669:1669:1669)) - (PORT ena (1081:1081:1081) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (403:403:403)) - (PORT datab (179:179:179) (211:211:211)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1564:1564:1564) (1566:1566:1566)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1035:1035:1035) (1005:1005:1005)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (299:299:299)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (1267:1267:1267) (1329:1329:1329)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (879:879:879) (890:890:890)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (879:879:879) (890:890:890)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (597:597:597)) - (PORT datab (865:865:865) (879:879:879)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (747:747:747)) - (PORT datab (594:594:594) (608:608:608)) - (PORT datac (553:553:553) (571:571:571)) - (PORT datad (573:573:573) (567:567:567)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1123:1123:1123) (1124:1124:1124)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1124:1124:1124) (1124:1124:1124)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (416:416:416)) - (PORT datab (219:219:219) (288:288:288)) - (PORT datad (381:381:381) (405:405:405)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (634:634:634)) - (PORT datab (804:804:804) (777:777:777)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (789:789:789)) - (PORT datab (375:375:375) (381:381:381)) - (PORT datac (1059:1059:1059) (1056:1056:1056)) - (PORT datad (613:613:613) (639:639:639)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1354:1354:1354)) - (PORT datab (626:626:626) (631:631:631)) - (PORT datad (308:308:308) (308:308:308)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (564:564:564)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (563:563:563) (562:562:562)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (795:795:795)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1104:1104:1104) (1124:1124:1124)) - (PORT datad (197:197:197) (228:228:228)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1028:1028:1028)) - (PORT datad (575:575:575) (571:571:571)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1868:1868:1868) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1057:1057:1057)) - (PORT datab (1362:1362:1362) (1347:1347:1347)) - (PORT datac (1094:1094:1094) (1100:1100:1100)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (557:557:557)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (577:577:577) (597:597:597)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1339:1339:1339) (1328:1328:1328)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1336:1336:1336) (1324:1324:1324)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (282:282:282)) - (PORT datab (1006:1006:1006) (994:994:994)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1120:1120:1120) (1137:1137:1137)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1119:1119:1119) (1136:1136:1136)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (421:421:421)) - (PORT datab (413:413:413) (428:428:428)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1097:1097:1097) (1085:1085:1085)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1200:1200:1200)) - (PORT datab (931:931:931) (954:954:954)) - (PORT datad (836:836:836) (838:838:838)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1727:1727:1727) (1737:1737:1737)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (295:295:295)) - (PORT datab (1051:1051:1051) (1069:1069:1069)) - (PORT datad (793:793:793) (778:778:778)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (896:896:896) (894:894:894)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (882:882:882) (906:906:906)) - (PORT ena (1173:1173:1173) (1181:1181:1181)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1103:1103:1103)) - (PORT datab (668:668:668) (692:692:692)) - (PORT datad (955:955:955) (935:935:935)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (882:882:882) (909:909:909)) - (PORT ena (1141:1141:1141) (1133:1133:1133)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1564:1564:1564) (1566:1566:1566)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1070:1070:1070) (1124:1124:1124)) - (PORT datab (615:615:615) (657:657:657)) - (PORT datad (602:602:602) (645:645:645)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (633:633:633)) - (PORT datab (599:599:599) (611:611:611)) - (PORT datac (529:529:529) (520:520:520)) - (PORT datad (287:287:287) (294:294:294)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1147:1147:1147) (1159:1159:1159)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (591:591:591) (623:623:623)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (596:596:596)) - (PORT datab (865:865:865) (879:879:879)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (594:594:594)) - (PORT datab (304:304:304) (321:321:321)) - (PORT datac (315:315:315) (322:322:322)) - (PORT datad (313:313:313) (312:312:312)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (623:623:623)) - (PORT datab (649:649:649) (674:674:674)) - (PORT datac (1062:1062:1062) (1054:1054:1054)) - (PORT datad (489:489:489) (479:479:479)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (789:789:789) (772:772:772)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1351:1351:1351)) - (PORT datab (357:357:357) (377:377:377)) - (PORT datad (596:596:596) (592:592:592)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1145:1145:1145) (1120:1120:1120)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (653:653:653)) - (PORT datab (309:309:309) (326:326:326)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (781:781:781)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1094:1094:1094) (1114:1114:1114)) - (PORT datad (343:343:343) (362:362:362)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datab (748:748:748) (733:733:733)) - (PORT datad (969:969:969) (981:981:981)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1868:1868:1868) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (248:248:248)) - (PORT datab (810:810:810) (820:820:820)) - (PORT datac (576:576:576) (595:595:595)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (226:226:226)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (538:538:538) (526:526:526)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1116:1116:1116)) - (PORT datab (838:838:838) (846:846:846)) - (PORT datac (352:352:352) (396:396:396)) - (PORT datad (847:847:847) (878:878:878)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (828:828:828) (822:822:822)) - (PORT ena (1110:1110:1110) (1083:1083:1083)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (624:624:624)) - (PORT datab (572:572:572) (595:595:595)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (563:563:563) (577:577:577)) - (PORT datad (386:386:386) (433:433:433)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (361:361:361)) - (PORT datab (375:375:375) (391:391:391)) - (PORT datac (388:388:388) (431:431:431)) - (PORT datad (1373:1373:1373) (1406:1406:1406)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (578:578:578)) - (PORT datab (213:213:213) (251:251:251)) - (PORT datac (516:516:516) (514:514:514)) - (PORT datad (1241:1241:1241) (1231:1231:1231)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (827:827:827)) - (PORT datab (814:814:814) (825:825:825)) - (PORT datac (582:582:582) (601:601:601)) - (PORT datad (752:752:752) (736:736:736)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1654:1654:1654)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (530:530:530) (527:527:527)) - (PORT datad (201:201:201) (236:236:236)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (818:818:818)) - (PORT datad (755:755:755) (744:744:744)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (222:222:222)) - (PORT datab (1137:1137:1137) (1146:1146:1146)) - (PORT datac (815:815:815) (808:808:808)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (802:802:802)) - (PORT datab (1073:1073:1073) (1071:1071:1071)) - (PORT datac (1059:1059:1059) (1049:1049:1049)) - (PORT datad (570:570:570) (583:583:583)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1126:1126:1126)) - (PORT datab (627:627:627) (647:647:647)) - (PORT datad (1007:1007:1007) (988:988:988)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1250:1250:1250) (1267:1267:1267)) - (PORT ena (1154:1154:1154) (1145:1145:1145)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1237:1237:1237)) - (PORT datab (860:860:860) (853:853:853)) - (PORT datad (1273:1273:1273) (1261:1261:1261)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1108:1108:1108) (1081:1081:1081)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1092:1092:1092) (1083:1083:1083)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1094:1094:1094) (1083:1083:1083)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (422:422:422)) - (PORT datab (416:416:416) (438:438:438)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (744:744:744)) - (PORT datab (582:582:582) (611:611:611)) - (PORT datad (565:565:565) (583:583:583)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1081:1081:1081) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (916:916:916) (931:931:931)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (915:915:915) (931:931:931)) - (PORT ena (879:879:879) (881:881:881)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (405:405:405)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datad (190:190:190) (217:217:217)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1091:1091:1091) (1066:1066:1066)) - (PORT ena (1564:1564:1564) (1566:1566:1566)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1089:1089:1089) (1063:1063:1063)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (303:303:303)) - (PORT datab (1296:1296:1296) (1366:1366:1366)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (566:566:566) (585:585:585)) - (PORT datac (351:351:351) (373:373:373)) - (PORT datad (287:287:287) (295:295:295)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (599:599:599)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (484:484:484) (477:477:477)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (995:995:995) (958:958:958)) - (PORT datab (1108:1108:1108) (1090:1090:1090)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (606:606:606) (617:617:617)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1057:1057:1057) (1033:1033:1033)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1350:1350:1350)) - (PORT datab (1089:1089:1089) (1108:1108:1108)) - (PORT datad (604:604:604) (597:597:597)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1145:1145:1145) (1120:1120:1120)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (333:333:333)) - (PORT datac (604:604:604) (618:618:618)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (398:398:398)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (1090:1090:1090) (1109:1109:1109)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (810:810:810) (827:827:827)) - (PORT datad (733:733:733) (711:711:711)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1646:1646:1646) (1626:1626:1626)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1326:1326:1326)) - (PORT datab (1011:1011:1011) (1021:1021:1021)) - (PORT datac (614:614:614) (618:618:618)) - (PORT datad (1032:1032:1032) (1028:1028:1028)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (665:665:665)) - (PORT datab (1303:1303:1303) (1283:1283:1283)) - (PORT datac (161:161:161) (195:195:195)) - (PORT datad (1267:1267:1267) (1243:1243:1243)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1145:1145:1145) (1120:1120:1120)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1349:1349:1349) (1350:1350:1350)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1352:1352:1352) (1353:1353:1353)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (420:420:420)) - (PORT datab (411:411:411) (427:427:427)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (913:913:913) (936:936:936)) - (PORT ena (1141:1141:1141) (1133:1133:1133)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1270:1270:1270) (1295:1295:1295)) - (PORT ena (764:764:764) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1070:1070:1070) (1127:1127:1127)) - (PORT datab (617:617:617) (660:660:660)) - (PORT datad (809:809:809) (835:835:835)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (1362:1362:1362) (1354:1354:1354)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1312:1312:1312) (1318:1318:1318)) - (PORT ena (1142:1142:1142) (1145:1145:1145)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (699:699:699)) - (PORT datab (628:628:628) (648:648:648)) - (PORT datad (590:590:590) (603:603:603)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1312:1312:1312) (1318:1318:1318)) - (PORT ena (1081:1081:1081) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (409:409:409)) - (PORT datab (179:179:179) (211:211:211)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (833:833:833) (828:828:828)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (859:859:859)) - (PORT datab (1248:1248:1248) (1234:1234:1234)) - (PORT datac (774:774:774) (776:776:776)) - (PORT datad (772:772:772) (803:803:803)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (335:335:335)) - (PORT datab (571:571:571) (587:587:587)) - (PORT datad (299:299:299) (299:299:299)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (860:860:860) (859:859:859)) - (PORT ena (1307:1307:1307) (1269:1269:1269)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (552:552:552) (550:550:550)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (764:764:764) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (292:292:292)) - (PORT datab (1006:1006:1006) (988:988:988)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1124:1124:1124) (1127:1127:1127)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (592:592:592) (620:620:620)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (602:602:602)) - (PORT datab (865:865:865) (884:884:884)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (486:486:486)) - (PORT datab (346:346:346) (352:352:352)) - (PORT datac (767:767:767) (747:747:747)) - (PORT datad (296:296:296) (288:288:288)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (763:763:763)) - (PORT datab (540:540:540) (527:527:527)) - (PORT datac (1062:1062:1062) (1058:1058:1058)) - (PORT datad (612:612:612) (638:638:638)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (789:789:789) (771:771:771)) - (PORT ena (1129:1129:1129) (1100:1100:1100)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1351:1351:1351)) - (PORT datab (357:357:357) (373:373:373)) - (PORT datad (597:597:597) (591:591:591)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (654:654:654)) - (PORT datac (197:197:197) (264:264:264)) - (PORT datad (310:310:310) (319:319:319)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (400:400:400)) - (PORT datab (1122:1122:1122) (1138:1138:1138)) - (PORT datac (162:162:162) (197:197:197)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1226:1226:1226)) - (PORT datad (498:498:498) (488:488:488)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (524:524:524) (516:516:516)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1868:1868:1868) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (1069:1069:1069) (1065:1065:1065)) - (PORT datac (613:613:613) (616:616:616)) - (PORT datad (1297:1297:1297) (1280:1280:1280)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (1302:1302:1302) (1282:1282:1282)) - (PORT datac (1277:1277:1277) (1257:1257:1257)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (599:599:599)) - (PORT datab (572:572:572) (566:566:566)) - (PORT datac (548:548:548) (583:583:583)) - (PORT datad (610:610:610) (648:648:648)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (1131:1131:1131) (1148:1148:1148)) - (PORT datac (812:812:812) (821:821:821)) - (PORT datad (194:194:194) (225:225:225)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (329:329:329)) - (PORT datab (654:654:654) (676:676:676)) - (PORT datac (1058:1058:1058) (1052:1052:1052)) - (PORT datad (343:343:343) (347:347:347)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (572:572:572)) - (PORT datab (386:386:386) (389:389:389)) - (PORT datac (503:503:503) (490:490:490)) - (PORT datad (567:567:567) (578:578:578)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (245:245:245)) - (PORT datab (1038:1038:1038) (1006:1006:1006)) - (PORT datac (783:783:783) (775:775:775)) - (PORT datad (318:318:318) (321:321:321)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (271:271:271)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (530:530:530) (528:528:528)) - (PORT datad (175:175:175) (197:197:197)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (686:686:686) (741:741:741)) - (PORT datac (185:185:185) (221:221:221)) - (PORT datad (201:201:201) (224:224:224)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (828:828:828)) - (PORT datab (623:623:623) (651:651:651)) - (PORT datac (1273:1273:1273) (1248:1248:1248)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1340:1340:1340) (1358:1358:1358)) - (PORT asdata (824:824:824) (808:808:808)) - (PORT ena (1486:1486:1486) (1479:1479:1479)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (862:862:862)) - (PORT datab (1468:1468:1468) (1502:1502:1502)) - (PORT datac (792:792:792) (814:814:814)) - (PORT datad (382:382:382) (437:437:437)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (789:789:789)) - (PORT datab (238:238:238) (290:290:290)) - (PORT datac (785:785:785) (804:804:804)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (787:787:787)) - (PORT datab (825:825:825) (821:821:821)) - (PORT datad (683:683:683) (704:704:704)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (1214:1214:1214) (1194:1194:1194)) - (PORT datac (187:187:187) (224:224:224)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28640,13 +10955,13 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) (DELAY (ABSOLUTE - (PORT dataa (856:856:856) (897:897:897)) - (PORT datab (995:995:995) (1034:1034:1034)) - (PORT datac (829:829:829) (842:842:842)) - (PORT datad (592:592:592) (606:606:606)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (886:886:886) (909:909:909)) + (PORT datab (1105:1105:1105) (1127:1127:1127)) + (PORT datac (813:813:813) (832:832:832)) + (PORT datad (969:969:969) (1014:1014:1014)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -28656,13 +10971,27 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (653:653:653)) - (PORT datab (788:788:788) (778:778:778)) - (PORT datac (573:573:573) (592:592:592)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (999:999:999) (990:990:990)) + (PORT datab (795:795:795) (786:786:786)) + (PORT datac (573:573:573) (581:581:581)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT datab (1107:1107:1107) (1133:1133:1133)) + (PORT datac (1042:1042:1042) (1052:1052:1052)) + (PORT datad (762:762:762) (750:750:750)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -28672,9 +11001,9 @@ (INSTANCE z80_\|alu_\|op2_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT clk (1339:1339:1339) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -28685,119 +11014,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (INSTANCE z80_\|alu_\|db_low\[3\]\~2) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (648:648:648)) - (PORT datab (784:784:784) (815:815:815)) - (PORT datac (763:763:763) (754:754:754)) - (PORT datad (580:580:580) (598:598:598)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (572:572:572) (595:595:595)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1335:1335:1335) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (478:478:478)) - (PORT datab (548:548:548) (553:553:553)) - (PORT datac (598:598:598) (640:640:640)) - (PORT datad (774:774:774) (769:769:769)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (347:347:347)) - (PORT datac (180:180:180) (212:212:212)) - (PORT datad (164:164:164) (189:189:189)) + (PORT dataa (1259:1259:1259) (1332:1332:1332)) + (PORT datab (1590:1590:1590) (1574:1574:1574)) + (PORT datac (331:331:331) (380:380:380)) + (PORT datad (625:625:625) (652:652:652)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (349:349:349)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (321:321:321) (331:331:331)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (636:636:636)) - (PORT datab (796:796:796) (793:793:793)) - (PORT datac (1887:1887:1887) (1861:1861:1861)) - (PORT datad (760:760:760) (829:829:829)) - (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (871:871:871) (911:911:911)) - (PORT datac (608:608:608) (612:612:612)) - (PORT datad (576:576:576) (574:574:574)) - (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28805,977 +11030,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (INSTANCE z80_\|alu_\|db_low\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1504:1504:1504) (1460:1460:1460)) - (PORT datab (664:664:664) (666:666:666)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (900:900:900) (877:877:877)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (462:462:462)) - (PORT datab (242:242:242) (295:295:295)) - (PORT datad (558:558:558) (568:568:568)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (592:592:592)) - (PORT datab (547:547:547) (536:536:536)) - (PORT datac (786:786:786) (801:801:801)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (866:866:866) (858:858:858)) + (PORT datab (593:593:593) (594:594:594)) + (PORT datac (1221:1221:1221) (1223:1223:1223)) + (PORT datad (823:823:823) (818:818:818)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) (DELAY (ABSOLUTE - (PORT dataa (542:542:542) (535:535:535)) + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1540:1540:1540) (1565:1565:1565)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (863:863:863)) + (PORT datac (741:741:741) (743:743:743)) + (PORT datad (346:346:346) (383:383:383)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2067:2067:2067) (2065:2065:2065)) (PORT datab (205:205:205) (243:243:243)) - (PORT datac (792:792:792) (794:794:794)) - (PORT datad (717:717:717) (746:746:746)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (646:646:646)) - (PORT datab (1050:1050:1050) (1044:1044:1044)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (503:503:503) (495:495:495)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1722:1722:1722) (1670:1670:1670)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (813:813:813) (829:829:829)) - (PORT datad (310:310:310) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1007:1007:1007)) - (PORT datab (1283:1283:1283) (1310:1310:1310)) - (PORT datac (749:749:749) (727:727:727)) - (PORT datad (523:523:523) (511:511:511)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (736:736:736)) - (PORT datab (329:329:329) (352:352:352)) - (PORT datac (983:983:983) (977:977:977)) - (PORT datad (986:986:986) (957:957:957)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (239:239:239)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (556:556:556) (550:550:550)) - (PORT datad (548:548:548) (535:535:535)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (881:881:881)) - (PORT datab (851:851:851) (855:855:855)) - (PORT datac (1109:1109:1109) (1124:1124:1124)) - (PORT datad (583:583:583) (577:577:577)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (207:207:207) (242:242:242)) - (PORT datac (795:795:795) (786:786:786)) - (PORT datad (574:574:574) (581:581:581)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (260:260:260)) - (PORT datab (1413:1413:1413) (1394:1394:1394)) - (PORT datac (1114:1114:1114) (1128:1128:1128)) - (PORT datad (631:631:631) (658:658:658)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) - (DELAY - (ABSOLUTE - (PORT datac (168:168:168) (205:205:205)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (740:740:740)) - (PORT datab (328:328:328) (356:356:356)) - (PORT datac (486:486:486) (478:478:478)) - (PORT datad (752:752:752) (726:726:726)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (594:594:594)) - (PORT datab (613:613:613) (607:607:607)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (571:571:571)) - (PORT datab (1318:1318:1318) (1318:1318:1318)) - (PORT datac (1353:1353:1353) (1333:1333:1333)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1127:1127:1127)) - (PORT datab (1315:1315:1315) (1318:1318:1318)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (773:773:773) (760:760:760)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (931:931:931)) - (PORT datab (1088:1088:1088) (1105:1105:1105)) - (PORT datac (581:581:581) (579:579:579)) - (PORT datad (1254:1254:1254) (1262:1262:1262)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (756:756:756)) - (PORT datab (1282:1282:1282) (1306:1306:1306)) - (PORT datac (997:997:997) (976:976:976)) - (PORT datad (1570:1570:1570) (1561:1561:1561)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1661:1661:1661) (1703:1703:1703)) - (PORT datab (622:622:622) (635:635:635)) - (PORT datac (958:958:958) (1001:1001:1001)) - (PORT datad (307:307:307) (321:321:321)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (779:779:779)) - (PORT datab (586:586:586) (592:592:592)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (576:576:576) (592:592:592)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (509:509:509)) - (PORT datab (598:598:598) (591:591:591)) - (PORT datac (523:523:523) (524:524:524)) - (PORT datad (301:301:301) (304:304:304)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (841:841:841)) - (PORT datab (1022:1022:1022) (1015:1015:1015)) - (PORT datac (751:751:751) (771:771:771)) - (PORT datad (545:545:545) (538:538:538)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (839:839:839)) - (PORT datab (408:408:408) (448:448:448)) - (PORT datac (300:300:300) (309:309:309)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT datab (873:873:873) (913:913:913)) - (PORT datac (630:630:630) (633:633:633)) - (PORT datad (856:856:856) (860:860:860)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (649:649:649)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (572:572:572) (588:588:588)) - (PORT datad (1460:1460:1460) (1421:1421:1421)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (783:783:783)) - (PORT datab (187:187:187) (221:221:221)) - (PORT datac (201:201:201) (272:272:272)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (784:784:784)) - (PORT datab (328:328:328) (339:339:339)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (1464:1464:1464) (1423:1423:1423)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1383:1383:1383)) - (PORT datab (2378:2378:2378) (2489:2489:2489)) - (PORT datac (1127:1127:1127) (1135:1135:1135)) - (PORT datad (1220:1220:1220) (1332:1332:1332)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (386:386:386)) - (PORT datab (594:594:594) (621:621:621)) - (PORT datac (1586:1586:1586) (1604:1604:1604)) - (PORT datad (784:784:784) (791:791:791)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (625:625:625)) - (PORT datab (610:610:610) (627:627:627)) - (PORT datad (1030:1030:1030) (1019:1019:1019)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1704:1704:1704) (1749:1749:1749)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (754:754:754) (736:736:736)) - (PORT datad (1097:1097:1097) (1087:1087:1087)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1023:1023:1023)) - (PORT datab (792:792:792) (810:810:810)) - (PORT datac (1075:1075:1075) (1067:1067:1067)) - (PORT datad (1030:1030:1030) (1003:1003:1003)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (302:302:302)) - (PORT datab (237:237:237) (306:306:306)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (787:787:787) (766:766:766)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (977:977:977)) - (PORT datab (821:821:821) (803:803:803)) - (PORT datac (948:948:948) (1019:1019:1019)) - (PORT datad (1170:1170:1170) (1213:1213:1213)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (255:255:255)) - (PORT datab (1290:1290:1290) (1358:1358:1358)) - (PORT datac (1813:1813:1813) (1806:1806:1806)) - (PORT datad (842:842:842) (852:852:852)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (916:916:916) (956:956:956)) - (PORT datac (1087:1087:1087) (1096:1096:1096)) - (PORT datad (1318:1318:1318) (1350:1350:1350)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1041:1041:1041)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (593:593:593) (607:607:607)) - (PORT datad (812:812:812) (811:811:811)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (616:616:616)) - (PORT datab (1150:1150:1150) (1159:1159:1159)) - (PORT datac (167:167:167) (204:204:204)) - (PORT datad (581:581:581) (590:590:590)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (590:590:590)) - (PORT datab (584:584:584) (567:567:567)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (301:301:301) (301:301:301)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT datac (885:885:885) (939:939:939)) - (PORT datad (784:784:784) (769:769:769)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (585:585:585) (567:567:567)) - (PORT datac (185:185:185) (223:223:223)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (833:833:833)) - (PORT datab (1840:1840:1840) (1853:1853:1853)) - (PORT datac (1259:1259:1259) (1237:1237:1237)) - (PORT datad (1938:1938:1938) (2052:2052:2052)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (817:817:817)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datac (193:193:193) (233:233:233)) - (PORT datad (175:175:175) (206:206:206)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (810:810:810)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (PORT datad (824:824:824) (823:823:823)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (1087:1087:1087) (1104:1104:1104)) - (PORT datad (168:168:168) (194:194:194)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1163:1163:1163)) - (PORT datab (627:627:627) (661:661:661)) - (PORT datac (749:749:749) (747:747:747)) - (PORT datad (1545:1545:1545) (1549:1549:1549)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (543:543:543)) - (PORT datab (760:760:760) (753:753:753)) - (PORT datac (552:552:552) (548:548:548)) - (PORT datad (600:600:600) (608:608:608)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (619:619:619) (615:615:615)) - (PORT datac (325:325:325) (328:328:328)) - (PORT datad (568:568:568) (561:561:561)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1247:1247:1247)) - (PORT datab (872:872:872) (866:866:866)) - (PORT datac (987:987:987) (967:967:967)) - (PORT datad (1315:1315:1315) (1307:1307:1307)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (360:360:360)) - (PORT datab (582:582:582) (586:586:586)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (666:666:666)) - (PORT datab (912:912:912) (924:924:924)) - (PORT datac (1861:1861:1861) (1883:1883:1883)) - (PORT datad (298:298:298) (308:308:308)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT datab (756:756:756) (737:737:737)) - (PORT datac (192:192:192) (230:230:230)) - (PORT datad (780:780:780) (771:771:771)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (323:323:323) (333:333:333)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (567:567:567) (575:575:575)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (579:579:579)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (532:532:532) (514:514:514)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1034:1034:1034)) - (PORT datab (1121:1121:1121) (1089:1089:1089)) - (PORT datac (1082:1082:1082) (1084:1084:1084)) - (PORT datad (1263:1263:1263) (1252:1252:1252)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1055:1055:1055) (1024:1024:1024)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (492:492:492) (488:488:488)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT datab (783:783:783) (761:761:761)) - (PORT datac (1010:1010:1010) (1006:1006:1006)) - (PORT datad (766:766:766) (740:740:740)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (752:752:752)) - (PORT datab (832:832:832) (820:820:820)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (866:866:866)) - (PORT datab (843:843:843) (826:826:826)) - (PORT datac (1308:1308:1308) (1302:1302:1302)) - (PORT datad (815:815:815) (797:797:797)) + (PORT datac (833:833:833) (829:829:829)) + (PORT datad (171:171:171) (198:198:198)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -29785,15 +11092,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1124:1124:1124)) - (PORT datab (819:819:819) (825:825:825)) - (PORT datac (1042:1042:1042) (1037:1037:1037)) - (PORT datad (883:883:883) (887:887:887)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT datac (1119:1119:1119) (1146:1146:1146)) + (PORT datad (2016:2016:2016) (2147:2147:2147)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29801,586 +11104,825 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) (DELAY (ABSOLUTE - (PORT dataa (1103:1103:1103) (1129:1129:1129)) - (PORT datab (1314:1314:1314) (1321:1321:1321)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (501:501:501) (491:491:491)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (617:617:617)) - (PORT datab (609:609:609) (661:661:661)) - (PORT datac (994:994:994) (974:974:974)) - (PORT datad (508:508:508) (499:499:499)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (680:680:680)) - (PORT datab (1242:1242:1242) (1213:1213:1213)) - (PORT datac (886:886:886) (899:899:899)) - (PORT datad (345:345:345) (354:354:354)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (1083:1083:1083) (1080:1080:1080)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (548:548:548) (545:545:545)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (542:542:542)) - (PORT datab (767:767:767) (749:749:749)) - (PORT datac (525:525:525) (518:518:518)) - (PORT datad (521:521:521) (509:509:509)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (935:935:935) (943:943:943)) - (PORT ena (901:901:901) (894:894:894)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (935:935:935) (943:943:943)) - (PORT ena (843:843:843) (827:827:827)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (422:422:422)) - (PORT datab (415:415:415) (432:432:432)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1127:1127:1127)) - (PORT datab (795:795:795) (803:803:803)) - (PORT datad (555:555:555) (556:556:556)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1097:1097:1097) (1081:1081:1081)) - (PORT ena (1141:1141:1141) (1133:1133:1133)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (922:922:922) (926:926:926)) - (PORT ena (1564:1564:1564) (1566:1566:1566)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (923:923:923) (929:929:929)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (302:302:302)) - (PORT datab (1296:1296:1296) (1366:1366:1366)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT datab (619:619:619) (659:659:659)) - (PORT datad (565:565:565) (576:576:576)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) - (PORT asdata (890:890:890) (901:901:901)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (1095:1095:1095) (1081:1081:1081)) - (PORT ena (1173:1173:1173) (1181:1181:1181)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (697:697:697)) - (PORT datab (668:668:668) (693:693:693)) - (PORT datad (955:955:955) (935:935:935)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1102:1102:1102) (1084:1084:1084)) - (PORT ena (1053:1053:1053) (1033:1033:1033)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT asdata (1101:1101:1101) (1086:1086:1086)) - (PORT ena (1141:1141:1141) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (604:604:604)) - (PORT datab (870:870:870) (885:885:885)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1081:1081:1081) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (622:622:622)) - (PORT datab (597:597:597) (595:595:595)) - (PORT datac (350:350:350) (375:375:375)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (738:738:738)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (596:596:596) (605:605:605)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1107:1107:1107) (1090:1090:1090)) - (PORT datac (1007:1007:1007) (970:970:970)) - (PORT datad (605:605:605) (618:618:618)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1350:1350:1350)) - (PORT datab (621:621:621) (631:631:631)) - (PORT datad (773:773:773) (746:746:746)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (429:429:429)) - (PORT datac (605:605:605) (616:616:616)) - (PORT datad (307:307:307) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (455:455:455)) - (PORT datad (184:184:184) (207:207:207)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (527:527:527)) - (PORT datab (223:223:223) (262:262:262)) - (PORT datac (1106:1106:1106) (1126:1126:1126)) - (PORT datad (573:573:573) (567:567:567)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1021:1021:1021)) - (PORT datad (791:791:791) (761:761:761)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1868:1868:1868) (1840:1840:1840)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (453:453:453)) - (PORT datab (358:358:358) (413:413:413)) - (PORT datac (219:219:219) (288:288:288)) - (PORT datad (215:215:215) (272:272:272)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (465:465:465)) - (PORT datab (384:384:384) (430:430:430)) - (PORT datac (366:366:366) (417:417:417)) - (PORT datad (217:217:217) (275:275:275)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1226:1226:1226)) - (PORT datab (650:650:650) (687:687:687)) - (PORT datac (550:550:550) (587:587:587)) - (PORT datad (218:218:218) (276:276:276)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (449:449:449)) - (PORT datab (382:382:382) (435:435:435)) - (PORT datac (517:517:517) (540:540:540)) - (PORT datad (353:353:353) (389:389:389)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (787:787:787)) - (PORT datab (760:760:760) (767:767:767)) - (PORT datac (571:571:571) (575:575:575)) - (PORT datad (578:578:578) (584:584:584)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (954:954:954)) - (PORT datab (639:639:639) (647:647:647)) - (PORT datad (570:570:570) (579:579:579)) + (PORT dataa (1219:1219:1219) (1239:1239:1239)) + (PORT datab (898:898:898) (932:932:932)) + (PORT datac (918:918:918) (957:957:957)) + (PORT datad (1122:1122:1122) (1151:1151:1151)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) (DELAY (ABSOLUTE - (PORT clk (1339:1339:1339) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1364:1364:1364)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + (PORT dataa (1177:1177:1177) (1221:1221:1221)) + (PORT datab (1022:1022:1022) (985:985:985)) + (PORT datad (914:914:914) (976:976:976)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (909:909:909)) - (PORT datab (590:590:590) (602:602:602)) - (PORT datac (779:779:779) (786:786:786)) - (PORT datad (585:585:585) (601:601:601)) + (PORT dataa (1200:1200:1200) (1296:1296:1296)) + (PORT datab (834:834:834) (849:849:849)) + (PORT datac (865:865:865) (929:929:929)) + (PORT datad (1278:1278:1278) (1358:1358:1358)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (787:787:787)) + (PORT datac (848:848:848) (873:873:873)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1632:1632:1632) (1657:1657:1657)) + (PORT datab (1627:1627:1627) (1644:1644:1644)) + (PORT datac (1902:1902:1902) (1928:1928:1928)) + (PORT datad (893:893:893) (921:921:921)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1363:1363:1363) (1391:1391:1391)) + (PORT datab (868:868:868) (867:867:867)) + (PORT datac (744:744:744) (728:728:728)) + (PORT datad (1133:1133:1133) (1154:1154:1154)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~24) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (771:771:771)) + (PORT datab (801:801:801) (811:811:811)) + (PORT datac (1548:1548:1548) (1585:1585:1585)) + (PORT datad (1648:1648:1648) (1675:1675:1675)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (762:762:762)) + (PORT datab (641:641:641) (678:678:678)) + (PORT datac (1321:1321:1321) (1312:1312:1312)) + (PORT datad (738:738:738) (763:763:763)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1119:1119:1119)) + (PORT datab (815:815:815) (841:841:841)) + (PORT datac (837:837:837) (844:844:844)) + (PORT datad (1071:1071:1071) (1076:1076:1076)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1139:1139:1139)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (723:723:723) (775:775:775)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (686:686:686)) + (PORT datab (653:653:653) (699:699:699)) + (PORT datac (1768:1768:1768) (1769:1769:1769)) + (PORT datad (978:978:978) (1007:1007:1007)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M4T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (999:999:999)) + (PORT datab (1403:1403:1403) (1451:1451:1451)) + (PORT datac (1388:1388:1388) (1419:1419:1419)) + (PORT datad (535:535:535) (529:529:529)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1391:1391:1391)) + (PORT datab (720:720:720) (775:775:775)) + (PORT datac (639:639:639) (695:695:695)) + (PORT datad (861:861:861) (884:884:884)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M5T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1001:1001:1001)) + (PORT datab (562:562:562) (564:564:564)) + (PORT datac (1386:1386:1386) (1415:1415:1415)) + (PORT datad (566:566:566) (570:570:570)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (931:931:931)) + (PORT datab (1331:1331:1331) (1335:1335:1335)) + (PORT datac (639:639:639) (699:699:699)) + (PORT datad (681:681:681) (741:741:741)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (635:635:635)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1371:1371:1371) (1381:1381:1381)) + (PORT datad (1511:1511:1511) (1489:1489:1489)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (186:186:186) (221:221:221)) + (PORT datac (160:160:160) (194:194:194)) + (PORT datad (162:162:162) (187:187:187)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1164:1164:1164)) + (PORT datab (964:964:964) (1005:1005:1005)) + (PORT datac (901:901:901) (929:929:929)) + (PORT datad (503:503:503) (495:495:495)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla5M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (2407:2407:2407) (2452:2452:2452)) + (PORT datac (565:565:565) (588:588:588)) + (PORT datad (1095:1095:1095) (1117:1117:1117)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (333:333:333)) + (PORT datab (1350:1350:1350) (1320:1320:1320)) + (PORT datac (899:899:899) (927:927:927)) + (PORT datad (939:939:939) (975:975:975)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (644:644:644)) + (PORT datab (965:965:965) (1006:1006:1006)) + (PORT datac (897:897:897) (924:924:924)) + (PORT datad (532:532:532) (526:526:526)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1009:1009:1009)) + (PORT datab (966:966:966) (1012:1012:1012)) + (PORT datac (896:896:896) (922:922:922)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (926:926:926)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1498:1498:1498)) + (PORT datab (1661:1661:1661) (1664:1664:1664)) + (PORT datac (1319:1319:1319) (1325:1325:1325)) + (PORT datad (616:616:616) (647:647:647)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1557:1557:1557)) + (PORT datab (1564:1564:1564) (1583:1583:1583)) + (PORT datac (1015:1015:1015) (1016:1016:1016)) + (PORT datad (1598:1598:1598) (1612:1612:1612)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1773:1773:1773) (1751:1751:1751)) + (PORT datab (1173:1173:1173) (1239:1239:1239)) + (PORT datac (1565:1565:1565) (1559:1559:1559)) + (PORT datad (672:672:672) (740:740:740)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (829:829:829)) + (PORT datab (1248:1248:1248) (1246:1246:1246)) + (PORT datac (924:924:924) (926:926:926)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (740:740:740)) + (PORT datab (1826:1826:1826) (1800:1800:1800)) + (PORT datad (591:591:591) (648:648:648)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (337:337:337)) + (PORT datab (1357:1357:1357) (1349:1349:1349)) + (PORT datac (1228:1228:1228) (1222:1222:1222)) + (PORT datad (168:168:168) (196:196:196)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T4_3\~0) + (DELAY + (ABSOLUTE + (PORT datab (698:698:698) (755:755:755)) + (PORT datac (633:633:633) (685:685:685)) + (PORT datad (1339:1339:1339) (1340:1340:1340)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (962:962:962)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (739:739:739) (725:725:725)) + (PORT datad (593:593:593) (586:586:586)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1394:1394:1394) (1403:1403:1403)) + (PORT datab (772:772:772) (759:759:759)) + (PORT datac (1057:1057:1057) (1070:1070:1070)) + (PORT datad (1089:1089:1089) (1124:1124:1124)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (973:973:973)) + (PORT datab (1588:1588:1588) (1588:1588:1588)) + (PORT datac (1024:1024:1024) (1027:1027:1027)) + (PORT datad (753:753:753) (746:746:746)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~16) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (785:785:785)) + (PORT datab (810:810:810) (802:802:802)) + (PORT datac (755:755:755) (759:759:759)) + (PORT datad (190:190:190) (221:221:221)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1119:1119:1119)) + (PORT datab (565:565:565) (561:561:561)) + (PORT datac (624:624:624) (622:622:622)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1247:1247:1247)) + (PORT datab (1129:1129:1129) (1155:1155:1155)) + (PORT datac (1311:1311:1311) (1284:1284:1284)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (617:617:617)) + (PORT datab (921:921:921) (955:955:955)) + (PORT datac (617:617:617) (625:625:625)) + (PORT datad (1071:1071:1071) (1091:1091:1091)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (862:862:862)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (180:180:180) (213:213:213)) + (PORT datad (186:186:186) (211:211:211)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (257:257:257)) + (PORT datab (648:648:648) (656:656:656)) + (PORT datac (809:809:809) (797:797:797)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~22) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (1171:1171:1171) (1209:1209:1209)) + (PORT datac (878:878:878) (959:959:959)) + (PORT datad (1050:1050:1050) (1022:1022:1022)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (357:357:357)) + (PORT datab (224:224:224) (262:262:262)) + (PORT datac (618:618:618) (627:627:627)) + (PORT datad (853:853:853) (867:867:867)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (516:516:516) (502:502:502)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (583:583:583)) + (PORT datab (1128:1128:1128) (1148:1148:1148)) + (PORT datac (1515:1515:1515) (1492:1492:1492)) + (PORT datad (588:588:588) (602:602:602)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (791:791:791)) + (PORT datab (878:878:878) (904:904:904)) + (PORT datac (1029:1029:1029) (1030:1030:1030)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1494:1494:1494)) + (PORT datab (1053:1053:1053) (1054:1054:1054)) + (PORT datac (1386:1386:1386) (1404:1404:1404)) + (PORT datad (1445:1445:1445) (1496:1496:1496)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (785:785:785)) + (PORT datab (1711:1711:1711) (1714:1714:1714)) + (PORT datac (723:723:723) (775:775:775)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (613:613:613)) + (PORT datab (1043:1043:1043) (1026:1026:1026)) + (PORT datac (760:760:760) (795:795:795)) + (PORT datad (769:769:769) (783:783:783)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT datab (1127:1127:1127) (1127:1127:1127)) + (PORT datac (1037:1037:1037) (1032:1032:1032)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (806:806:806)) + (PORT datab (1117:1117:1117) (1167:1167:1167)) + (PORT datad (852:852:852) (866:866:866)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1428:1428:1428)) + (PORT datab (1699:1699:1699) (1743:1743:1743)) + (PORT datac (1383:1383:1383) (1394:1394:1394)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (606:606:606)) + (PORT datab (527:527:527) (533:533:533)) + (PORT datac (318:318:318) (328:328:328)) + (PORT datad (992:992:992) (974:974:974)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (738:738:738)) + (PORT datab (604:604:604) (641:641:641)) + (PORT datac (606:606:606) (633:633:633)) + (PORT datad (617:617:617) (646:646:646)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (657:657:657)) + (PORT datab (865:865:865) (873:873:873)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (576:576:576) (581:581:581)) (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -30390,256 +11932,121 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~21) (DELAY (ABSOLUTE - (PORT dataa (566:566:566) (566:566:566)) - (PORT datab (2427:2427:2427) (2430:2430:2430)) - (PORT datac (1911:1911:1911) (1993:1993:1993)) - (PORT datad (1331:1331:1331) (1300:1300:1300)) + (PORT dataa (923:923:923) (946:946:946)) + (PORT datab (846:846:846) (842:842:842)) + (PORT datac (1176:1176:1176) (1214:1214:1214)) + (PORT datad (1082:1082:1082) (1095:1095:1095)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT datab (678:678:678) (741:741:741)) + (PORT datac (892:892:892) (952:952:952)) + (PORT datad (914:914:914) (979:979:979)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1619:1619:1619)) + (PORT datab (1890:1890:1890) (1893:1893:1893)) + (PORT datac (1132:1132:1132) (1162:1162:1162)) + (PORT datad (772:772:772) (769:769:769)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (1405:1405:1405) (1455:1455:1455)) + (PORT datac (1626:1626:1626) (1647:1647:1647)) + (PORT datad (1089:1089:1089) (1104:1104:1104)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1084:1084:1084)) + (PORT datab (670:670:670) (702:702:702)) + (PORT datac (802:802:802) (813:813:813)) + (PORT datad (1320:1320:1320) (1306:1306:1306)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (811:811:811)) + (PORT datab (1052:1052:1052) (1070:1070:1070)) + (PORT datac (1346:1346:1346) (1369:1369:1369)) + (PORT datad (1104:1104:1104) (1115:1115:1115)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1403:1403:1403)) + (PORT datab (1872:1872:1872) (1898:1898:1898)) + (PORT datad (1095:1095:1095) (1110:1110:1110)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) (DELAY (ABSOLUTE - (PORT dataa (547:547:547) (542:542:542)) - (PORT datab (565:565:565) (605:605:605)) - (PORT datad (1058:1058:1058) (1048:1048:1048)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (401:401:401)) - (PORT datac (667:667:667) (721:721:721)) - (PORT datad (239:239:239) (310:310:310)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1148:1148:1148) (1126:1126:1126)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1379:1379:1379) (1357:1357:1357)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (1280:1280:1280) (1254:1254:1254)) - (PORT datac (793:793:793) (810:810:810)) - (PORT datad (212:212:212) (277:277:277)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (314:314:314)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (900:900:900) (918:918:918)) - (PORT datad (775:775:775) (783:783:783)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (952:952:952)) - (PORT datab (1277:1277:1277) (1250:1250:1250)) - (PORT datac (559:559:559) (577:577:577)) - (PORT datad (852:852:852) (864:864:864)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (820:820:820)) - (PORT datab (591:591:591) (628:628:628)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (585:585:585) (599:599:599)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (949:949:949)) - (PORT datab (2006:2006:2006) (2121:2121:2121)) - (PORT datac (1252:1252:1252) (1225:1225:1225)) - (PORT datad (1231:1231:1231) (1319:1319:1319)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (956:956:956)) - (PORT datab (861:861:861) (884:884:884)) - (PORT datac (560:560:560) (573:573:573)) - (PORT datad (774:774:774) (782:782:782)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (818:818:818)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (585:585:585) (603:603:603)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (347:347:347)) - (PORT datab (232:232:232) (271:271:271)) - (PORT datac (340:340:340) (352:352:352)) - (PORT datad (534:534:534) (521:521:521)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1721:1721:1721) (1724:1724:1724)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (370:370:370)) - (PORT datab (331:331:331) (346:346:346)) - (PORT datac (295:295:295) (312:312:312)) - (PORT datad (175:175:175) (197:197:197)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT datab (1160:1160:1160) (1187:1187:1187)) - (PORT datad (729:729:729) (700:700:700)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (473:473:473) (461:461:461)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (1390:1390:1390) (1421:1421:1421)) + (PORT datab (1149:1149:1149) (1179:1179:1179)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1664:1664:1664) (1670:1670:1670)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -30649,216 +12056,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (417:417:417)) - (PORT datab (901:901:901) (920:920:920)) - (PORT datac (893:893:893) (901:901:901)) - (PORT datad (866:866:866) (872:872:872)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (913:913:913)) - (PORT datab (738:738:738) (729:729:729)) - (PORT datac (770:770:770) (768:768:768)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1140:1140:1140)) - (PORT datab (939:939:939) (945:945:945)) - (PORT datac (1059:1059:1059) (1064:1064:1064)) - (PORT datad (1065:1065:1065) (1058:1058:1058)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT dataa (2048:2048:2048) (2113:2113:2113)) + (PORT datab (1591:1591:1591) (1583:1583:1583)) + (PORT datac (1581:1581:1581) (1592:1592:1592)) + (PORT datad (1719:1719:1719) (1750:1750:1750)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (623:623:623)) - (PORT datab (206:206:206) (242:242:242)) - (PORT datac (506:506:506) (499:499:499)) - (PORT datad (324:324:324) (336:336:336)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (767:767:767)) - (PORT datab (583:583:583) (577:577:577)) - (PORT datac (515:515:515) (511:511:511)) - (PORT datad (506:506:506) (499:499:499)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (1046:1046:1046) (1039:1039:1039)) - (PORT datac (294:294:294) (299:299:299)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (592:592:592)) - (PORT datab (1202:1202:1202) (1219:1219:1219)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (764:764:764) (752:752:752)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (614:614:614)) - (PORT datab (867:867:867) (890:890:890)) - (PORT datac (1083:1083:1083) (1096:1096:1096)) - (PORT datad (730:730:730) (695:695:695)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (740:740:740)) - (PORT datab (624:624:624) (649:649:649)) - (PORT datac (606:606:606) (638:638:638)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (651:651:651)) - (PORT datab (896:896:896) (950:950:950)) - (PORT datad (473:473:473) (451:451:451)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1253:1253:1253)) - (PORT datab (921:921:921) (956:956:956)) - (PORT datac (1029:1029:1029) (1009:1009:1009)) - (PORT datad (1447:1447:1447) (1466:1466:1466)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -30869,10 +12075,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) (DELAY (ABSOLUTE - (PORT dataa (1368:1368:1368) (1363:1363:1363)) - (PORT datab (1074:1074:1074) (1036:1036:1036)) - (PORT datac (1010:1010:1010) (983:983:983)) - (PORT datad (558:558:558) (564:564:564)) + (PORT dataa (1745:1745:1745) (1789:1789:1789)) + (PORT datab (361:361:361) (367:367:367)) + (PORT datac (824:824:824) (838:838:838)) + (PORT datad (166:166:166) (190:190:190)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -30885,10 +12091,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) (DELAY (ABSOLUTE - (PORT dataa (586:586:586) (592:592:592)) - (PORT datab (205:205:205) (241:241:241)) - (PORT datac (569:569:569) (575:575:575)) - (PORT datad (158:158:158) (178:178:178)) + (PORT dataa (841:841:841) (847:847:847)) + (PORT datab (610:610:610) (614:614:614)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (773:773:773) (758:758:758)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -30898,27 +12104,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) (DELAY (ABSOLUTE - (PORT dataa (891:891:891) (922:922:922)) - (PORT datac (875:875:875) (897:897:897)) - (PORT datad (1123:1123:1123) (1138:1138:1138)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (911:911:911) (961:961:961)) + (PORT datab (951:951:951) (993:993:993)) + (PORT datac (1266:1266:1266) (1322:1322:1322)) + (PORT datad (849:849:849) (858:858:858)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (622:622:622)) - (PORT datab (1335:1335:1335) (1352:1352:1352)) - (PORT datac (545:545:545) (562:562:562)) - (PORT datad (539:539:539) (545:545:545)) + (PORT dataa (620:620:620) (618:618:618)) + (PORT datab (1659:1659:1659) (1659:1659:1659)) + (PORT datac (1322:1322:1322) (1330:1330:1330)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1522:1522:1522)) + (PORT datab (1655:1655:1655) (1697:1697:1697)) + (PORT datac (1622:1622:1622) (1667:1667:1667)) + (PORT datad (1631:1631:1631) (1669:1669:1669)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1354:1354:1354) (1409:1409:1409)) + (PORT datab (1519:1519:1519) (1494:1494:1494)) + (PORT datac (1092:1092:1092) (1085:1085:1085)) + (PORT datad (849:849:849) (840:840:840)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1013:1013:1013) (1019:1019:1019)) + (PORT datab (913:913:913) (937:937:937)) + (PORT datac (1100:1100:1100) (1134:1134:1134)) + (PORT datad (1351:1351:1351) (1374:1374:1374)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (387:387:387)) + (PORT datab (214:214:214) (255:255:255)) + (PORT datac (833:833:833) (850:850:850)) + (PORT datad (1062:1062:1062) (1075:1075:1075)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -30927,32 +12199,323 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~6) (DELAY (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) - (PORT asdata (691:691:691) (703:703:703)) - (PORT ena (1110:1110:1110) (1083:1083:1083)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1176:1176:1176) (1220:1220:1220)) + (PORT datab (952:952:952) (1010:1010:1010)) + (PORT datad (875:875:875) (914:914:914)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (620:620:620)) - (PORT datab (576:576:576) (595:595:595)) - (PORT datad (558:558:558) (575:575:575)) + (PORT dataa (642:642:642) (683:683:683)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (608:608:608) (636:636:636)) + (PORT datad (861:861:861) (864:864:864)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (873:873:873)) + (PORT datac (562:562:562) (556:556:556)) + (PORT datad (578:578:578) (601:601:601)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1363:1363:1363) (1348:1348:1348)) + (PORT datad (1042:1042:1042) (1050:1050:1050)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1040:1040:1040)) + (PORT datab (1457:1457:1457) (1518:1518:1518)) + (PORT datac (1187:1187:1187) (1236:1236:1236)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~8) + (DELAY + (ABSOLUTE + (PORT datab (1002:1002:1002) (1084:1084:1084)) + (PORT datac (752:752:752) (735:735:735)) + (PORT datad (1737:1737:1737) (1739:1739:1739)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (871:871:871)) + (PORT datab (787:787:787) (782:782:782)) + (PORT datac (894:894:894) (878:878:878)) + (PORT datad (615:615:615) (643:643:643)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1075:1075:1075)) + (PORT datab (606:606:606) (647:647:647)) + (PORT datac (1081:1081:1081) (1060:1060:1060)) + (PORT datad (304:304:304) (309:309:309)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (249:249:249)) + (PORT datab (1334:1334:1334) (1353:1353:1353)) + (PORT datac (799:799:799) (811:811:811)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (564:564:564)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (580:580:580) (600:600:600)) + (PORT datad (1841:1841:1841) (1850:1850:1850)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (768:768:768)) + (PORT datab (817:817:817) (826:826:826)) + (PORT datac (637:637:637) (705:705:705)) + (PORT datad (603:603:603) (605:605:605)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (216:216:216)) + (PORT datab (917:917:917) (924:924:924)) + (PORT datac (332:332:332) (350:350:350)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (844:844:844)) + (PORT datab (588:588:588) (625:625:625)) + (PORT datac (1449:1449:1449) (1472:1472:1472)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (637:637:637)) + (PORT datab (923:923:923) (940:940:940)) + (PORT datac (552:552:552) (559:559:559)) + (PORT datad (568:568:568) (578:578:578)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (825:825:825)) + (PORT datab (205:205:205) (241:241:241)) + (PORT datac (1582:1582:1582) (1587:1587:1587)) + (PORT datad (1719:1719:1719) (1746:1746:1746)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~30) + (DELAY + (ABSOLUTE + (PORT dataa (2121:2121:2121) (2096:2096:2096)) + (PORT datab (704:704:704) (767:767:767)) + (PORT datac (604:604:604) (673:673:673)) + (PORT datad (1663:1663:1663) (1709:1709:1709)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1745:1745:1745) (1783:1783:1783)) + (PORT datab (382:382:382) (389:389:389)) + (PORT datac (823:823:823) (836:836:836)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (794:794:794)) + (PORT datab (629:629:629) (679:679:679)) + (PORT datac (911:911:911) (967:967:967)) + (PORT datad (1258:1258:1258) (1245:1245:1245)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (757:757:757)) + (PORT datab (1350:1350:1350) (1375:1375:1375)) + (PORT datac (931:931:931) (914:914:914)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (716:716:716) (697:697:697)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (886:886:886) (887:887:887)) + (PORT datac (328:328:328) (352:352:352)) + (PORT datad (596:596:596) (618:618:618)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -30962,9 +12525,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1088:1088:1088) (1053:1053:1053)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -30973,16 +12536,199 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (372:372:372)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (311:311:311) (314:314:314)) + (PORT datad (1129:1129:1129) (1148:1148:1148)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (583:583:583)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (575:575:575) (581:581:581)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2390:2390:2390) (2408:2408:2408)) + (PORT datac (1162:1162:1162) (1195:1195:1195)) + (PORT datad (1228:1228:1228) (1265:1265:1265)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (631:631:631) (669:669:669)) + (PORT datac (585:585:585) (614:614:614)) + (PORT datad (1154:1154:1154) (1208:1208:1208)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (263:263:263)) + (PORT datab (847:847:847) (860:860:860)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1374:1374:1374) (1380:1380:1380)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (878:878:878)) + (PORT datab (999:999:999) (966:966:966)) + (PORT datac (1025:1025:1025) (1011:1011:1011)) + (PORT datad (324:324:324) (331:331:331)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1733:1733:1733)) + (PORT datab (916:916:916) (922:922:922)) + (PORT datac (1101:1101:1101) (1117:1117:1117)) + (PORT datad (777:777:777) (763:763:763)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (613:613:613) (626:626:626)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (404:404:404)) + (PORT datab (636:636:636) (648:648:648)) + (PORT datac (494:494:494) (480:480:480)) + (PORT datad (813:813:813) (805:805:805)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT datab (637:637:637) (650:650:650)) + (PORT datac (330:330:330) (349:349:349)) + (PORT datad (523:523:523) (511:511:511)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (825:825:825) (807:807:807)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (653:653:653)) + (PORT datac (332:332:332) (352:352:352)) + (PORT datad (521:521:521) (507:507:507)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (520:520:520) (515:515:515)) - (PORT datab (548:548:548) (548:548:548)) - (PORT datad (198:198:198) (256:256:256)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1405:1405:1405) (1468:1468:1468)) + (PORT datab (1204:1204:1204) (1262:1262:1262)) + (PORT datad (1065:1065:1065) (1073:1073:1073)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -30992,24 +12738,332 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) (DELAY (ABSOLUTE - (PORT dataa (425:425:425) (464:464:464)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1370:1370:1370) (1399:1399:1399)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (400:400:400) (433:433:433)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1054:1054:1054) (1049:1049:1049)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1032:1032:1032)) + (PORT datab (851:851:851) (838:838:838)) + (PORT datac (1506:1506:1506) (1607:1607:1607)) + (PORT datad (815:815:815) (817:817:817)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (621:621:621)) + (PORT datab (1557:1557:1557) (1543:1543:1543)) + (PORT datac (1570:1570:1570) (1598:1598:1598)) + (PORT datad (1571:1571:1571) (1530:1530:1530)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1164:1164:1164)) + (PORT datab (875:875:875) (883:883:883)) + (PORT datac (838:838:838) (859:859:859)) + (PORT datad (1110:1110:1110) (1107:1107:1107)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1231:1231:1231)) + (PORT datab (810:810:810) (824:824:824)) + (PORT datac (1104:1104:1104) (1154:1154:1154)) + (PORT datad (1038:1038:1038) (1032:1032:1032)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1313:1313:1313)) + (PORT datab (814:814:814) (839:839:839)) + (PORT datac (866:866:866) (929:929:929)) + (PORT datad (1278:1278:1278) (1354:1354:1354)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (818:818:818)) + (PORT datab (687:687:687) (730:730:730)) + (PORT datac (842:842:842) (869:869:869)) + (PORT datad (1323:1323:1323) (1360:1360:1360)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (939:939:939) (960:960:960)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (867:867:867)) + (PORT datac (1106:1106:1106) (1134:1134:1134)) + (PORT datad (1284:1284:1284) (1291:1291:1291)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (597:597:597)) + (PORT datab (1108:1108:1108) (1099:1099:1099)) + (PORT datac (1129:1129:1129) (1127:1127:1127)) + (PORT datad (726:726:726) (714:714:714)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (542:542:542)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (780:780:780) (763:763:763)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (594:594:594)) + (PORT datab (605:605:605) (619:619:619)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (577:577:577) (565:565:565)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (838:838:838)) + (PORT datab (1104:1104:1104) (1098:1098:1098)) + (PORT datac (562:562:562) (565:565:565)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1564:1564:1564)) + (PORT datab (1405:1405:1405) (1456:1456:1456)) + (PORT datac (1628:1628:1628) (1649:1649:1649)) + (PORT datad (1866:1866:1866) (1861:1861:1861)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1617:1617:1617)) + (PORT datab (1135:1135:1135) (1170:1170:1170)) + (PORT datac (640:640:640) (700:700:700)) + (PORT datad (681:681:681) (739:739:739)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (947:947:947)) + (PORT datab (1110:1110:1110) (1110:1110:1110)) + (PORT datac (837:837:837) (848:848:848)) + (PORT datad (1747:1747:1747) (1729:1729:1729)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (837:837:837)) + (PORT datac (807:807:807) (806:806:806)) + (PORT datad (798:798:798) (792:792:792)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (816:816:816) (810:810:810)) + (PORT datac (588:588:588) (590:590:590)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (620:620:620)) + (PORT datad (573:573:573) (578:578:578)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1121:1121:1121)) + (PORT datab (1202:1202:1202) (1270:1270:1270)) + (PORT datac (1058:1058:1058) (1055:1055:1055)) + (PORT datad (1047:1047:1047) (1034:1034:1034)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT datac (810:810:810) (830:830:830)) - (PORT datad (323:323:323) (328:328:328)) + (PORT datac (1089:1089:1089) (1087:1087:1087)) + (PORT datad (554:554:554) (555:555:555)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31020,10 +13074,10 @@ (INSTANCE z80_\|address_latch_\|Q\[11\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT clk (1339:1339:1339) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1646:1646:1646) (1626:1626:1626)) + (PORT clrn (1380:1380:1380) (1353:1353:1353)) + (PORT ena (1588:1588:1588) (1543:1543:1543)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -31038,8 +13092,134 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT datac (389:389:389) (423:423:423)) - (PORT datad (318:318:318) (320:320:320)) + (PORT datab (661:661:661) (710:710:710)) + (PORT datad (565:565:565) (572:572:572)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (488:488:488)) + (PORT datab (367:367:367) (390:390:390)) + (PORT datac (1075:1075:1075) (1082:1082:1082)) + (PORT datad (584:584:584) (585:585:585)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1011:1011:1011)) + (PORT datab (863:863:863) (885:885:885)) + (PORT datac (836:836:836) (846:846:846)) + (PORT datad (716:716:716) (701:701:701)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (378:378:378)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1149:1149:1149)) + (PORT datab (1394:1394:1394) (1400:1400:1400)) + (PORT datac (1098:1098:1098) (1119:1119:1119)) + (PORT datad (479:479:479) (465:465:465)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1238:1238:1238)) + (PORT datab (888:888:888) (899:899:899)) + (PORT datac (918:918:918) (958:958:958)) + (PORT datad (776:776:776) (762:762:762)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (255:255:255)) + (PORT datab (216:216:216) (260:260:260)) + (PORT datac (161:161:161) (197:197:197)) + (PORT datad (1551:1551:1551) (1554:1554:1554)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (764:764:764) (758:758:758)) + (PORT datac (815:815:815) (839:839:839)) + (PORT datad (1220:1220:1220) (1188:1188:1188)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (978:978:978)) + (PORT datab (1329:1329:1329) (1306:1306:1306)) + (PORT datac (827:827:827) (853:853:853)) + (PORT datad (1074:1074:1074) (1087:1087:1087)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31047,14 +13227,18390 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~17) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1124:1124:1124)) - (PORT datab (364:364:364) (369:369:369)) - (PORT datad (515:515:515) (492:492:492)) + (PORT dataa (2238:2238:2238) (2321:2321:2321)) + (PORT datab (1244:1244:1244) (1340:1340:1340)) + (PORT datac (785:785:785) (796:796:796)) + (PORT datad (859:859:859) (878:878:878)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (868:868:868)) + (PORT datac (1531:1531:1531) (1504:1504:1504)) + (PORT datad (1101:1101:1101) (1117:1117:1117)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1092:1092:1092)) + (PORT datab (574:574:574) (575:575:575)) + (PORT datac (1566:1566:1566) (1544:1544:1544)) + (PORT datad (574:574:574) (598:598:598)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (556:556:556)) + (PORT datab (1656:1656:1656) (1681:1681:1681)) + (PORT datac (1086:1086:1086) (1074:1074:1074)) + (PORT datad (1239:1239:1239) (1340:1340:1340)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (805:805:805)) + (PORT datab (574:574:574) (567:567:567)) + (PORT datac (577:577:577) (589:589:589)) + (PORT datad (1017:1017:1017) (1000:1000:1000)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1042:1042:1042)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (554:554:554) (574:574:574)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (1429:1429:1429) (1482:1482:1482)) + (PORT datac (1161:1161:1161) (1169:1169:1169)) + (PORT datad (1883:1883:1883) (1908:1908:1908)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1050:1050:1050) (1038:1038:1038)) + (PORT datab (572:572:572) (575:575:575)) + (PORT datac (1051:1051:1051) (1048:1048:1048)) + (PORT datad (847:847:847) (857:857:857)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1390:1390:1390) (1421:1421:1421)) + (PORT datab (871:871:871) (871:871:871)) + (PORT datac (328:328:328) (329:329:329)) + (PORT datad (304:304:304) (303:303:303)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~15) + (DELAY + (ABSOLUTE + (PORT datab (847:847:847) (840:840:840)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (706:706:706)) + (PORT datab (1536:1536:1536) (1494:1494:1494)) + (PORT datac (1067:1067:1067) (1071:1071:1071)) + (PORT datad (832:832:832) (852:852:852)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1091:1091:1091)) + (PORT datab (888:888:888) (886:886:886)) + (PORT datac (1565:1565:1565) (1542:1542:1542)) + (PORT datad (577:577:577) (598:598:598)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1393:1393:1393) (1406:1406:1406)) + (PORT datab (1273:1273:1273) (1272:1272:1272)) + (PORT datac (175:175:175) (205:205:205)) + (PORT datad (824:824:824) (830:830:830)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1083:1083:1083)) + (PORT datab (206:206:206) (250:250:250)) + (PORT datac (783:783:783) (779:779:779)) + (PORT datad (809:809:809) (793:793:793)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1168:1168:1168)) + (PORT datab (1118:1118:1118) (1121:1121:1121)) + (PORT datac (847:847:847) (864:864:864)) + (PORT datad (1593:1593:1593) (1604:1604:1604)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1594:1594:1594) (1574:1574:1574)) + (PORT datab (575:575:575) (576:576:576)) + (PORT datac (701:701:701) (703:703:703)) + (PORT datad (296:296:296) (290:290:290)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (378:378:378) (396:396:396)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1497:1497:1497)) + (PORT datab (1662:1662:1662) (1663:1663:1663)) + (PORT datac (1296:1296:1296) (1303:1303:1303)) + (PORT datad (1698:1698:1698) (1718:1718:1718)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (226:226:226)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (177:177:177) (197:197:197)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (620:620:620)) + (PORT datab (628:628:628) (615:615:615)) + (PORT datac (583:583:583) (601:601:601)) + (PORT datad (1045:1045:1045) (1018:1018:1018)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (857:857:857)) + (PORT datab (1110:1110:1110) (1110:1110:1110)) + (PORT datac (1069:1069:1069) (1056:1056:1056)) + (PORT datad (571:571:571) (588:588:588)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (828:828:828)) + (PORT datab (204:204:204) (239:239:239)) + (PORT datad (1081:1081:1081) (1072:1072:1072)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (187:187:187) (225:225:225)) + (PORT datac (1570:1570:1570) (1564:1564:1564)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1041:1041:1041)) + (PORT datab (1391:1391:1391) (1381:1381:1381)) + (PORT datac (615:615:615) (623:623:623)) + (PORT datad (848:848:848) (841:841:841)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (776:776:776)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (538:538:538) (525:525:525)) + (PORT datad (1008:1008:1008) (984:984:984)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (664:664:664) (697:697:697)) + (PORT datac (835:835:835) (875:875:875)) + (PORT datad (1720:1720:1720) (1800:1800:1800)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2062:2062:2062) (2184:2184:2184)) + (PORT datab (567:567:567) (586:586:586)) + (PORT datad (1398:1398:1398) (1399:1399:1399)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1204:1204:1204)) + (PORT datab (2440:2440:2440) (2484:2484:2484)) + (PORT datac (1115:1115:1115) (1170:1170:1170)) + (PORT datad (1448:1448:1448) (1577:1577:1577)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1157:1157:1157)) + (PORT datab (687:687:687) (759:759:759)) + (PORT datad (1103:1103:1103) (1131:1131:1131)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datac (796:796:796) (788:788:788)) + (PORT datad (833:833:833) (848:848:848)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (807:807:807)) + (PORT datab (622:622:622) (623:623:623)) + (PORT datac (155:155:155) (183:183:183)) + (PORT datad (829:829:829) (834:834:834)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (1055:1055:1055) (1035:1035:1035)) + (PORT datac (547:547:547) (537:537:537)) + (PORT datad (305:305:305) (301:301:301)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (750:750:750)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (586:586:586) (605:605:605)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1771:1771:1771)) + (PORT datab (1235:1235:1235) (1292:1292:1292)) + (PORT datac (616:616:616) (653:653:653)) + (PORT datad (801:801:801) (816:816:816)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1209:1209:1209)) + (PORT datab (1454:1454:1454) (1589:1589:1589)) + (PORT datac (1764:1764:1764) (1790:1790:1790)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (2028:2028:2028)) + (PORT datab (617:617:617) (630:630:630)) + (PORT datac (1633:1633:1633) (1685:1685:1685)) + (PORT datad (1301:1301:1301) (1336:1336:1336)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (2032:2032:2032)) + (PORT datab (2527:2527:2527) (2565:2565:2565)) + (PORT datac (1634:1634:1634) (1685:1685:1685)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1640:1640:1640)) + (PORT datab (894:894:894) (934:934:934)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1302:1302:1302) (1339:1339:1339)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1372:1372:1372)) + (PORT datab (1103:1103:1103) (1102:1102:1102)) + (PORT datac (891:891:891) (921:921:921)) + (PORT datad (773:773:773) (760:760:760)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1054:1054:1054)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (1537:1537:1537) (1557:1557:1557)) + (PORT datad (1124:1124:1124) (1168:1168:1168)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (858:858:858)) + (PORT datab (1002:1002:1002) (984:984:984)) + (PORT datac (681:681:681) (654:654:654)) + (PORT datad (989:989:989) (960:960:960)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (218:218:218)) + (PORT datab (898:898:898) (935:935:935)) + (PORT datac (496:496:496) (481:481:481)) + (PORT datad (294:294:294) (301:301:301)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (327:327:327)) + (PORT datab (344:344:344) (350:350:350)) + (PORT datac (296:296:296) (302:302:302)) + (PORT datad (508:508:508) (493:493:493)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1140:1140:1140)) + (PORT datac (573:573:573) (574:574:574)) + (PORT datad (186:186:186) (210:210:210)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (808:808:808)) + (PORT datab (920:920:920) (953:953:953)) + (PORT datac (862:862:862) (889:889:889)) + (PORT datad (1592:1592:1592) (1581:1581:1581)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (1764:1764:1764) (1791:1791:1791)) + (PORT datad (883:883:883) (913:913:913)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (824:824:824)) + (PORT datab (1250:1250:1250) (1249:1249:1249)) + (PORT datac (906:906:906) (962:962:962)) + (PORT datad (1138:1138:1138) (1206:1206:1206)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (555:555:555)) + (PORT datab (1106:1106:1106) (1094:1094:1094)) + (PORT datac (1130:1130:1130) (1128:1128:1128)) + (PORT datad (1211:1211:1211) (1212:1212:1212)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1162:1162:1162)) + (PORT datab (996:996:996) (1074:1074:1074)) + (PORT datac (1025:1025:1025) (1035:1035:1035)) + (PORT datad (1920:1920:1920) (1976:1976:1976)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1099:1099:1099)) + (PORT datab (245:245:245) (286:286:286)) + (PORT datac (1278:1278:1278) (1279:1279:1279)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (617:617:617)) + (PORT datab (205:205:205) (241:241:241)) + (PORT datac (855:855:855) (856:856:856)) + (PORT datad (853:853:853) (867:867:867)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (362:362:362)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (776:776:776) (746:746:746)) + (PORT datad (171:171:171) (199:199:199)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1578:1578:1578) (1554:1554:1554)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (839:839:839) (837:837:837)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (895:895:895)) + (PORT datab (790:790:790) (769:769:769)) + (PORT datac (1888:1888:1888) (1943:1943:1943)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1180:1180:1180)) + (PORT datab (1385:1385:1385) (1406:1406:1406)) + (PORT datac (1129:1129:1129) (1126:1126:1126)) + (PORT datad (1071:1071:1071) (1062:1062:1062)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1670:1670:1670) (1780:1780:1780)) + (PORT datab (921:921:921) (950:950:950)) + (PORT datad (815:815:815) (821:821:821)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1605:1605:1605) (1633:1633:1633)) + (PORT datab (921:921:921) (953:953:953)) + (PORT datac (503:503:503) (492:492:492)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (895:895:895)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1546:1546:1546) (1643:1643:1643)) + (PORT datab (854:854:854) (865:865:865)) + (PORT datac (837:837:837) (850:850:850)) + (PORT datad (869:869:869) (912:912:912)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (314:314:314) (324:324:324)) + (PORT datad (838:838:838) (852:852:852)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (305:305:305)) + (PORT datab (1099:1099:1099) (1136:1136:1136)) + (PORT datac (1283:1283:1283) (1289:1289:1289)) + (PORT datad (649:649:649) (722:722:722)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1279:1279:1279)) + (PORT datab (206:206:206) (250:250:250)) + (PORT datac (783:783:783) (781:781:781)) + (PORT datad (1043:1043:1043) (1059:1059:1059)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1110:1110:1110)) + (PORT datab (539:539:539) (545:545:545)) + (PORT datad (1048:1048:1048) (1059:1059:1059)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1160:1160:1160)) + (PORT datab (690:690:690) (764:764:764)) + (PORT datad (1101:1101:1101) (1130:1130:1130)) + (IOPATH dataa combout (273:273:273) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (302:302:302)) + (PORT datab (1098:1098:1098) (1132:1132:1132)) + (PORT datac (1283:1283:1283) (1287:1287:1287)) + (PORT datad (652:652:652) (720:720:720)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (858:858:858)) + (PORT datab (1145:1145:1145) (1194:1194:1194)) + (PORT datad (594:594:594) (603:603:603)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (306:306:306)) + (PORT datab (1099:1099:1099) (1132:1132:1132)) + (PORT datac (1284:1284:1284) (1290:1290:1290)) + (PORT datad (648:648:648) (724:724:724)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1110:1110:1110)) + (PORT datab (564:564:564) (544:544:544)) + (PORT datad (1049:1049:1049) (1063:1063:1063)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (305:305:305)) + (PORT datab (1101:1101:1101) (1137:1137:1137)) + (PORT datac (1284:1284:1284) (1291:1291:1291)) + (PORT datad (648:648:648) (722:722:722)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (860:860:860)) + (PORT datab (1148:1148:1148) (1193:1193:1193)) + (PORT datad (585:585:585) (597:597:597)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (991:991:991)) + (PORT datab (510:510:510) (498:498:498)) + (PORT datac (763:763:763) (832:832:832)) + (PORT datad (492:492:492) (472:472:472)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (891:891:891)) + (PORT datac (1002:1002:1002) (1028:1028:1028)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2137:2137:2137) (2149:2149:2149)) + (PORT datab (1429:1429:1429) (1479:1479:1479)) + (PORT datac (792:792:792) (792:792:792)) + (PORT datad (1886:1886:1886) (1910:1910:1910)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (876:876:876)) + (PORT datab (1128:1128:1128) (1144:1144:1144)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1045:1045:1045) (1041:1041:1041)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (335:335:335)) + (PORT datac (617:617:617) (642:642:642)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1152:1152:1152)) + (PORT datab (955:955:955) (1017:1017:1017)) + (PORT datad (590:590:590) (606:606:606)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1400:1400:1400)) + (PORT datab (1384:1384:1384) (1410:1410:1410)) + (PORT datac (1274:1274:1274) (1284:1284:1284)) + (PORT datad (586:586:586) (620:620:620)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT datab (588:588:588) (610:610:610)) + (PORT datac (1021:1021:1021) (1043:1043:1043)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~23) + (DELAY + (ABSOLUTE + (PORT datab (1092:1092:1092) (1082:1082:1082)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~29) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (620:620:620)) + (PORT datab (666:666:666) (708:708:708)) + (PORT datac (1020:1020:1020) (986:986:986)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~26) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (334:334:334) (352:352:352)) + (PORT datac (576:576:576) (592:592:592)) + (PORT datad (566:566:566) (581:581:581)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (379:379:379)) + (PORT datab (648:648:648) (674:674:674)) + (PORT datad (598:598:598) (612:612:612)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1397:1397:1397)) + (PORT datab (1388:1388:1388) (1407:1407:1407)) + (PORT datac (1270:1270:1270) (1279:1279:1279)) + (PORT datad (589:589:589) (621:621:621)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (371:371:371)) + (PORT datab (775:775:775) (758:758:758)) + (PORT datac (983:983:983) (979:979:979)) + (PORT datad (759:759:759) (746:746:746)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1303:1303:1303)) + (PORT datab (1422:1422:1422) (1460:1460:1460)) + (PORT datac (320:320:320) (340:340:340)) + (PORT datad (1412:1412:1412) (1450:1450:1450)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1490:1490:1490)) + (PORT datab (1425:1425:1425) (1461:1461:1461)) + (PORT datac (320:320:320) (337:337:337)) + (PORT datad (644:644:644) (706:706:706)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1546:1546:1546) (1643:1643:1643)) + (PORT datab (854:854:854) (866:866:866)) + (PORT datac (837:837:837) (851:851:851)) + (PORT datad (869:869:869) (912:912:912)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (867:867:867)) + (PORT datab (1146:1146:1146) (1188:1188:1188)) + (PORT datad (1121:1121:1121) (1113:1113:1113)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1480:1480:1480)) + (PORT datab (1422:1422:1422) (1451:1451:1451)) + (PORT datac (323:323:323) (341:341:341)) + (PORT datad (648:648:648) (711:711:711)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (831:831:831) (826:826:826)) + (PORT datad (185:185:185) (213:213:213)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1488:1488:1488)) + (PORT datab (1424:1424:1424) (1453:1453:1453)) + (PORT datac (320:320:320) (337:337:337)) + (PORT datad (1143:1143:1143) (1209:1209:1209)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1043:1043:1043)) + (PORT datab (1153:1153:1153) (1150:1150:1150)) + (PORT datac (463:463:463) (456:456:456)) + (PORT datad (536:536:536) (535:535:535)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1104:1104:1104)) + (PORT datab (1006:1006:1006) (986:986:986)) + (PORT datad (1052:1052:1052) (1067:1067:1067)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (869:869:869)) + (PORT datab (1142:1142:1142) (1185:1185:1185)) + (PORT datad (598:598:598) (610:610:610)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1116:1116:1116) (1128:1128:1128)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (869:869:869)) + (PORT datab (1142:1142:1142) (1184:1184:1184)) + (PORT datad (584:584:584) (597:597:597)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1116:1116:1116) (1130:1130:1130)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (800:800:800)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (775:775:775) (754:754:754)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (523:523:523)) + (PORT datac (1058:1058:1058) (1072:1072:1072)) + (PORT datad (1052:1052:1052) (1067:1067:1067)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1661:1661:1661) (1701:1701:1701)) + (PORT ena (914:914:914) (918:918:918)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (540:540:540) (549:549:549)) + (PORT datac (1061:1061:1061) (1080:1080:1080)) + (PORT datad (1048:1048:1048) (1058:1058:1058)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1661:1661:1661) (1701:1701:1701)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1108:1108:1108)) + (PORT datab (539:539:539) (549:549:549)) + (PORT datad (1050:1050:1050) (1067:1067:1067)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (816:816:816)) + (PORT datab (219:219:219) (265:265:265)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (890:890:890)) + (PORT datac (1004:1004:1004) (1027:1027:1027)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1490:1490:1490)) + (PORT datab (373:373:373) (379:379:379)) + (PORT datac (1392:1392:1392) (1432:1432:1432)) + (PORT datad (647:647:647) (713:713:713)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1703:1703:1703) (1761:1761:1761)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1491:1491:1491)) + (PORT datab (372:372:372) (377:377:377)) + (PORT datac (1395:1395:1395) (1433:1433:1433)) + (PORT datad (647:647:647) (709:709:709)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1705:1705:1705) (1762:1762:1762)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (673:673:673)) + (PORT datab (624:624:624) (632:632:632)) + (PORT datad (327:327:327) (366:366:366)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (864:864:864)) + (PORT datab (1149:1149:1149) (1193:1193:1193)) + (PORT datad (1122:1122:1122) (1113:1113:1113)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1242:1242:1242) (1251:1251:1251)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1364:1364:1364) (1429:1429:1429)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1487:1487:1487)) + (PORT datab (1185:1185:1185) (1249:1249:1249)) + (PORT datac (1391:1391:1391) (1429:1429:1429)) + (PORT datad (336:336:336) (347:347:347)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (898:898:898)) + (PORT datab (839:839:839) (831:831:831)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1435:1435:1435) (1483:1483:1483)) + (PORT datab (1421:1421:1421) (1453:1453:1453)) + (PORT datac (1263:1263:1263) (1273:1273:1273)) + (PORT datad (338:338:338) (344:344:344)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (881:881:881) (873:873:873)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (382:382:382)) + (PORT datab (648:648:648) (675:675:675)) + (PORT datad (596:596:596) (616:616:616)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (887:887:887) (877:877:877)) + (PORT ena (1600:1600:1600) (1568:1568:1568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (296:296:296)) + (PORT datab (425:425:425) (445:445:445)) + (PORT datad (1082:1082:1082) (1094:1094:1094)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (610:610:610)) + (PORT datac (1015:1015:1015) (1039:1039:1039)) + (PORT datad (177:177:177) (204:204:204)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1108:1108:1108) (1082:1082:1082)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (823:823:823)) + (PORT datab (1146:1146:1146) (1140:1140:1140)) + (PORT datad (789:789:789) (772:772:772)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (370:370:370)) + (PORT datab (597:597:597) (595:595:595)) + (PORT datac (323:323:323) (326:326:326)) + (PORT datad (560:560:560) (561:561:561)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1076:1076:1076)) + (PORT datab (214:214:214) (256:256:256)) + (PORT datac (564:564:564) (586:586:586)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1357:1357:1357) (1314:1314:1314)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (786:786:786) (796:796:796)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (362:362:362)) + (PORT datab (198:198:198) (232:232:232)) + (PORT datac (547:547:547) (562:562:562)) + (PORT datad (535:535:535) (526:526:526)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (862:862:862)) + (PORT datab (1024:1024:1024) (1023:1023:1023)) + (PORT datac (834:834:834) (869:869:869)) + (PORT datad (825:825:825) (842:842:842)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1360:1360:1360)) + (PORT datab (865:865:865) (898:898:898)) + (PORT datac (559:559:559) (584:584:584)) + (PORT datad (565:565:565) (597:597:597)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (847:847:847)) + (PORT datab (791:791:791) (790:790:790)) + (PORT datad (1055:1055:1055) (1049:1049:1049)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1416:1416:1416)) + (PORT datab (858:858:858) (865:865:865)) + (PORT datac (877:877:877) (898:898:898)) + (PORT datad (841:841:841) (860:860:860)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1261:1261:1261)) + (PORT datab (821:821:821) (822:822:822)) + (PORT datac (861:861:861) (872:872:872)) + (PORT datad (1097:1097:1097) (1135:1135:1135)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1412:1412:1412)) + (PORT datab (1348:1348:1348) (1338:1338:1338)) + (PORT datac (1514:1514:1514) (1558:1558:1558)) + (PORT datad (740:740:740) (765:765:765)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (516:516:516)) + (PORT datab (905:905:905) (923:923:923)) + (PORT datac (469:469:469) (458:458:458)) + (PORT datad (1008:1008:1008) (962:962:962)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (641:641:641)) + (PORT datab (1035:1035:1035) (1034:1034:1034)) + (PORT datac (703:703:703) (675:675:675)) + (PORT datad (720:720:720) (761:761:761)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1061:1061:1061)) + (PORT datab (318:318:318) (340:340:340)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (518:518:518) (502:502:502)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (241:241:241)) + (PORT datab (881:881:881) (868:868:868)) + (PORT datac (806:806:806) (799:799:799)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (1176:1176:1176) (1206:1206:1206)) + (PORT datac (1121:1121:1121) (1141:1141:1141)) + (PORT datad (1309:1309:1309) (1324:1324:1324)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (610:610:610) (623:623:623)) + (PORT datac (826:826:826) (836:836:836)) + (PORT datad (1113:1113:1113) (1139:1139:1139)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (244:244:244)) + (PORT datad (574:574:574) (570:570:570)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (958:958:958)) + (PORT datab (799:799:799) (795:795:795)) + (PORT datac (1714:1714:1714) (1663:1663:1663)) + (PORT datad (1030:1030:1030) (1010:1010:1010)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1019:1019:1019)) + (PORT datab (538:538:538) (537:537:537)) + (PORT datac (623:623:623) (657:657:657)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (537:537:537)) + (PORT datab (831:831:831) (806:806:806)) + (PORT datac (158:158:158) (189:189:189)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (734:734:734)) + (PORT datab (652:652:652) (702:702:702)) + (PORT datac (1306:1306:1306) (1282:1282:1282)) + (PORT datad (1031:1031:1031) (997:997:997)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (249:249:249)) + (PORT datab (877:877:877) (859:859:859)) + (PORT datac (1031:1031:1031) (1025:1025:1025)) + (PORT datad (1299:1299:1299) (1303:1303:1303)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1337:1337:1337) (1347:1347:1347)) + (PORT datab (1071:1071:1071) (1061:1061:1061)) + (PORT datac (1308:1308:1308) (1327:1327:1327)) + (PORT datad (576:576:576) (592:592:592)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1305:1305:1305) (1329:1329:1329)) + (PORT datad (180:180:180) (217:217:217)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1177:1177:1177)) + (PORT datab (1674:1674:1674) (1710:1710:1710)) + (PORT datac (580:580:580) (586:586:586)) + (PORT datad (969:969:969) (1004:1004:1004)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1191:1191:1191)) + (PORT datab (694:694:694) (748:748:748)) + (PORT datac (646:646:646) (708:708:708)) + (PORT datad (1134:1134:1134) (1146:1146:1146)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (992:992:992)) + (PORT datac (1139:1139:1139) (1177:1177:1177)) + (PORT datad (203:203:203) (236:236:236)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (235:235:235)) + (PORT datab (1612:1612:1612) (1621:1621:1621)) + (PORT datac (1331:1331:1331) (1464:1464:1464)) + (PORT datad (747:747:747) (739:739:739)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (791:791:791)) + (PORT datab (1412:1412:1412) (1418:1418:1418)) + (PORT datac (1006:1006:1006) (984:984:984)) + (PORT datad (300:300:300) (302:302:302)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1292:1292:1292)) + (PORT datab (814:814:814) (840:840:840)) + (PORT datac (1153:1153:1153) (1210:1210:1210)) + (PORT datad (937:937:937) (1018:1018:1018)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (919:919:919)) + (PORT datab (924:924:924) (907:907:907)) + (PORT datac (1501:1501:1501) (1494:1494:1494)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1079:1079:1079) (1062:1062:1062)) + (PORT datab (829:829:829) (843:843:843)) + (PORT datac (1304:1304:1304) (1330:1330:1330)) + (PORT datad (1090:1090:1090) (1084:1084:1084)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1525:1525:1525)) + (PORT datab (867:867:867) (871:871:871)) + (PORT datac (747:747:747) (731:731:731)) + (PORT datad (1133:1133:1133) (1156:1156:1156)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (992:992:992)) + (PORT datab (1203:1203:1203) (1259:1259:1259)) + (PORT datac (317:317:317) (328:328:328)) + (PORT datad (506:506:506) (498:498:498)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (603:603:603)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (852:852:852) (835:835:835)) + (PORT datad (564:564:564) (578:578:578)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (351:351:351)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (563:563:563) (547:547:547)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1293:1293:1293)) + (PORT datab (834:834:834) (847:847:847)) + (PORT datac (1151:1151:1151) (1208:1208:1208)) + (PORT datad (940:940:940) (1019:1019:1019)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (638:638:638)) + (PORT datab (841:841:841) (850:850:850)) + (PORT datac (530:530:530) (523:523:523)) + (PORT datad (546:546:546) (539:539:539)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (235:235:235)) + (PORT datab (606:606:606) (605:605:605)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (765:765:765) (768:768:768)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (583:583:583)) + (PORT datab (579:579:579) (584:584:584)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (811:811:811) (813:813:813)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (241:241:241)) + (PORT datab (826:826:826) (844:844:844)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (176:176:176) (207:207:207)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1245:1245:1245)) + (PORT datab (548:548:548) (535:535:535)) + (PORT datac (1105:1105:1105) (1131:1131:1131)) + (PORT datad (1598:1598:1598) (1624:1624:1624)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1107:1107:1107)) + (PORT datab (395:395:395) (442:442:442)) + (PORT datad (396:396:396) (440:440:440)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (870:870:870)) + (PORT datab (1591:1591:1591) (1597:1597:1597)) + (PORT datac (1179:1179:1179) (1214:1214:1214)) + (PORT datad (897:897:897) (908:908:908)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (857:857:857) (887:887:887)) + (PORT datac (597:597:597) (606:606:606)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (816:816:816)) + (PORT datab (1079:1079:1079) (1064:1064:1064)) + (PORT datac (1244:1244:1244) (1230:1230:1230)) + (PORT datad (816:816:816) (815:815:815)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1027:1027:1027)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1340:1340:1340) (1366:1366:1366)) + (PORT datad (321:321:321) (323:323:323)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (942:942:942)) + (PORT datab (1017:1017:1017) (1015:1015:1015)) + (PORT datac (832:832:832) (849:849:849)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT datab (1268:1268:1268) (1268:1268:1268)) + (PORT datad (1245:1245:1245) (1230:1230:1230)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1306:1306:1306)) + (PORT datab (339:339:339) (349:349:349)) + (PORT datac (1051:1051:1051) (1083:1083:1083)) + (PORT datad (983:983:983) (968:968:968)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (667:667:667)) + (PORT datab (1357:1357:1357) (1348:1348:1348)) + (PORT datac (807:807:807) (798:798:798)) + (PORT datad (1126:1126:1126) (1116:1116:1116)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (804:804:804)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (163:163:163) (199:199:199)) + (PORT datad (1067:1067:1067) (1035:1035:1035)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (728:728:728)) + (PORT datab (1675:1675:1675) (1710:1710:1710)) + (PORT datac (628:628:628) (677:677:677)) + (PORT datad (1132:1132:1132) (1163:1163:1163)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (242:242:242)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (176:176:176) (207:207:207)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (337:337:337)) + (PORT datab (546:546:546) (534:534:534)) + (PORT datac (592:592:592) (600:600:600)) + (PORT datad (507:507:507) (494:494:494)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (235:235:235)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datac (177:177:177) (208:208:208)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (838:838:838) (837:837:837)) + (PORT datad (551:551:551) (547:547:547)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (596:596:596) (606:606:606)) + (PORT datad (297:297:297) (295:295:295)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1294:1294:1294)) + (PORT datab (812:812:812) (837:837:837)) + (PORT datac (865:865:865) (930:930:930)) + (PORT datad (1280:1280:1280) (1358:1358:1358)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (606:606:606) (602:602:602)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (764:764:764) (764:764:764)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (582:582:582)) + (PORT datad (811:811:811) (813:813:813)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1091:1091:1091)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (1012:1012:1012) (1001:1001:1001)) + (PORT datad (1077:1077:1077) (1065:1065:1065)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1042:1042:1042)) + (PORT datab (1658:1658:1658) (1673:1673:1673)) + (PORT datac (1369:1369:1369) (1379:1379:1379)) + (PORT datad (1351:1351:1351) (1359:1359:1359)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (845:845:845)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (1542:1542:1542) (1526:1526:1526)) + (PORT datad (1352:1352:1352) (1362:1362:1362)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (713:713:713)) + (PORT datab (1353:1353:1353) (1324:1324:1324)) + (PORT datac (1505:1505:1505) (1480:1480:1480)) + (PORT datad (591:591:591) (582:582:582)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (629:629:629)) + (PORT datab (899:899:899) (932:932:932)) + (PORT datac (1126:1126:1126) (1135:1135:1135)) + (PORT datad (1121:1121:1121) (1148:1148:1148)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1274:1274:1274) (1270:1270:1270)) + (PORT datad (1072:1072:1072) (1070:1070:1070)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (861:861:861)) + (PORT datab (928:928:928) (954:954:954)) + (PORT datac (900:900:900) (915:915:915)) + (PORT datad (939:939:939) (978:978:978)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (895:895:895)) + (PORT datab (191:191:191) (227:227:227)) + (PORT datac (856:856:856) (863:863:863)) + (PORT datad (833:833:833) (850:850:850)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (373:373:373)) + (PORT datab (1630:1630:1630) (1636:1636:1636)) + (PORT datac (1035:1035:1035) (1037:1037:1037)) + (PORT datad (510:510:510) (493:493:493)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (789:789:789)) + (PORT datab (800:800:800) (802:802:802)) + (PORT datac (1598:1598:1598) (1609:1609:1609)) + (PORT datad (565:565:565) (569:569:569)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1118:1118:1118)) + (PORT datab (1109:1109:1109) (1108:1108:1108)) + (PORT datac (838:838:838) (846:846:846)) + (PORT datad (556:556:556) (566:566:566)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (425:425:425)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (897:897:897) (882:882:882)) + (PORT datad (548:548:548) (540:540:540)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (425:425:425)) + (PORT datab (1815:1815:1815) (1795:1795:1795)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1342:1342:1342) (1359:1359:1359)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1148:1148:1148)) + (PORT datab (1132:1132:1132) (1158:1158:1158)) + (PORT datac (1311:1311:1311) (1284:1284:1284)) + (PORT datad (808:808:808) (808:808:808)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1323:1323:1323) (1333:1333:1333)) + (PORT datab (1662:1662:1662) (1665:1665:1665)) + (PORT datac (1322:1322:1322) (1330:1330:1330)) + (PORT datad (616:616:616) (646:646:646)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1146:1146:1146)) + (PORT datab (626:626:626) (640:640:640)) + (PORT datac (1515:1515:1515) (1494:1494:1494)) + (PORT datad (1031:1031:1031) (1040:1040:1040)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1017:1017:1017) (1079:1079:1079)) + (PORT datab (819:819:819) (792:792:792)) + (PORT datac (330:330:330) (336:336:336)) + (PORT datad (561:561:561) (567:567:567)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1244:1244:1244)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (596:596:596) (601:601:601)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (424:424:424)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (1502:1502:1502) (1495:1495:1495)) + (PORT datad (549:549:549) (543:543:543)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1326:1326:1326)) + (PORT datab (415:415:415) (474:474:474)) + (PORT datac (1049:1049:1049) (1073:1073:1073)) + (PORT datad (366:366:366) (407:407:407)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1295:1295:1295)) + (PORT datab (923:923:923) (905:905:905)) + (PORT datac (759:759:759) (751:751:751)) + (PORT datad (551:551:551) (541:541:541)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1393:1393:1393)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (865:865:865) (884:884:884)) + (PORT datad (287:287:287) (293:293:293)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (883:883:883)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (854:854:854) (881:881:881)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1271:1271:1271)) + (PORT datab (1411:1411:1411) (1418:1418:1418)) + (PORT datac (773:773:773) (760:760:760)) + (PORT datad (1106:1106:1106) (1135:1135:1135)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (621:621:621)) + (PORT datab (202:202:202) (243:243:243)) + (PORT datac (1276:1276:1276) (1266:1266:1266)) + (PORT datad (777:777:777) (755:755:755)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (732:732:732)) + (PORT datab (1680:1680:1680) (1711:1711:1711)) + (PORT datac (1108:1108:1108) (1136:1136:1136)) + (PORT datad (1047:1047:1047) (1069:1069:1069)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (202:202:202) (244:244:244)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (775:775:775) (751:751:751)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (833:833:833)) + (PORT datab (839:839:839) (873:873:873)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (228:228:228)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (544:544:544) (528:528:528)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (631:631:631)) + (PORT datad (746:746:746) (726:726:726)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (177:177:177) (199:199:199)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1266:1266:1266)) + (PORT datab (1268:1268:1268) (1270:1270:1270)) + (PORT datac (1046:1046:1046) (1045:1045:1045)) + (PORT datad (1261:1261:1261) (1267:1267:1267)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datac (796:796:796) (793:793:793)) + (PORT datad (185:185:185) (211:211:211)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1077:1077:1077)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (2058:2058:2058) (2046:2046:2046)) + (PORT datad (1081:1081:1081) (1072:1072:1072)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1116:1116:1116)) + (PORT datab (1146:1146:1146) (1144:1144:1144)) + (PORT datac (903:903:903) (924:924:924)) + (PORT datad (814:814:814) (817:817:817)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (676:676:676) (703:703:703)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (2289:2289:2289) (2284:2284:2284)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1164:1164:1164)) + (PORT datab (2599:2599:2599) (2593:2593:2593)) + (PORT datac (1372:1372:1372) (1397:1397:1397)) + (PORT datad (509:509:509) (495:495:495)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1227:1227:1227)) + (PORT datab (1584:1584:1584) (1596:1596:1596)) + (PORT datac (1101:1101:1101) (1157:1157:1157)) + (PORT datad (1036:1036:1036) (1029:1029:1029)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (841:841:841)) + (PORT datab (639:639:639) (674:674:674)) + (PORT datac (1404:1404:1404) (1453:1453:1453)) + (PORT datad (836:836:836) (853:853:853)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1040:1040:1040)) + (PORT datab (1086:1086:1086) (1062:1062:1062)) + (PORT datac (762:762:762) (755:755:755)) + (PORT datad (1140:1140:1140) (1163:1163:1163)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (625:625:625)) + (PORT datab (867:867:867) (897:897:897)) + (PORT datac (1387:1387:1387) (1407:1407:1407)) + (PORT datad (830:830:830) (839:839:839)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (945:945:945)) + (PORT datab (860:860:860) (866:866:866)) + (PORT datac (1614:1614:1614) (1627:1627:1627)) + (PORT datad (895:895:895) (939:939:939)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (599:599:599) (611:611:611)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1156:1156:1156)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (817:817:817) (802:802:802)) + (PORT datad (575:575:575) (571:571:571)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (575:575:575) (587:587:587)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (344:344:344)) + (PORT datab (1100:1100:1100) (1122:1122:1122)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (996:996:996) (1018:1018:1018)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (1097:1097:1097) (1119:1119:1119)) + (PORT datac (1001:1001:1001) (1026:1026:1026)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (893:893:893)) + (PORT datab (1143:1143:1143) (1185:1185:1185)) + (PORT datad (1121:1121:1121) (1110:1110:1110)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1052:1052:1052)) + (PORT datad (1081:1081:1081) (1095:1095:1095)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1401:1401:1401)) + (PORT datab (210:210:210) (252:252:252)) + (PORT datac (1355:1355:1355) (1359:1359:1359)) + (PORT datad (1142:1142:1142) (1207:1207:1207)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1390:1390:1390) (1397:1397:1397)) + (PORT datab (1385:1385:1385) (1404:1404:1404)) + (PORT datac (1275:1275:1275) (1286:1286:1286)) + (PORT datad (307:307:307) (312:312:312)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1114:1114:1114)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (1022:1022:1022) (1045:1045:1045)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1748:1748:1748)) + (PORT datab (632:632:632) (701:701:701)) + (PORT datac (2084:2084:2084) (2062:2062:2062)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (748:748:748)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (571:571:571) (583:583:583)) + (PORT datad (1326:1326:1326) (1342:1342:1342)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (336:336:336) (354:354:354)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (747:747:747) (723:723:723)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT datab (614:614:614) (642:642:642)) + (PORT datac (618:618:618) (642:642:642)) + (PORT datad (348:348:348) (363:363:363)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1112:1112:1112)) + (PORT datac (1023:1023:1023) (1046:1046:1046)) + (PORT datad (178:178:178) (205:205:205)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (545:545:545)) + (PORT datab (596:596:596) (584:584:584)) + (PORT datac (836:836:836) (831:831:831)) + (PORT datad (535:535:535) (530:530:530)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT datab (666:666:666) (715:715:715)) + (PORT datac (677:677:677) (740:740:740)) + (PORT datad (602:602:602) (610:610:610)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (806:806:806)) + (PORT datab (198:198:198) (232:232:232)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1403:1403:1403)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (1353:1353:1353) (1358:1358:1358)) + (PORT datad (615:615:615) (680:680:680)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1406:1406:1406)) + (PORT datab (214:214:214) (256:256:256)) + (PORT datac (1354:1354:1354) (1361:1361:1361)) + (PORT datad (617:617:617) (682:682:682)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1552:1552:1552)) + (PORT datab (384:384:384) (413:413:413)) + (PORT datac (538:538:538) (536:536:536)) + (PORT datad (366:366:366) (376:376:376)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (638:638:638)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (485:485:485) (473:473:473)) + (PORT datad (306:306:306) (308:308:308)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (1029:1029:1029) (1053:1053:1053)) + (PORT datac (1068:1068:1068) (1092:1092:1092)) + (PORT datad (184:184:184) (210:210:210)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (313:313:313) (320:320:320)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (1073:1073:1073) (1097:1097:1097)) + (PORT datad (996:996:996) (1018:1018:1018)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1159:1159:1159) (1169:1169:1169)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (252:252:252)) + (PORT datab (1101:1101:1101) (1123:1123:1123)) + (PORT datac (1005:1005:1005) (1029:1029:1029)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1156:1156:1156) (1165:1165:1165)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (916:916:916)) + (PORT datab (676:676:676) (678:678:678)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1106:1106:1106)) + (PORT datab (1074:1074:1074) (1097:1097:1097)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1320:1320:1320)) + (PORT datab (1346:1346:1346) (1350:1350:1350)) + (PORT datac (175:175:175) (217:217:217)) + (PORT datad (1347:1347:1347) (1374:1374:1374)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (486:486:486) (512:512:512)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1362:1362:1362)) + (PORT datab (956:956:956) (921:921:921)) + (PORT datad (743:743:743) (727:727:727)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1094:1094:1094) (1113:1113:1113)) + (PORT datac (1025:1025:1025) (1047:1047:1047)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (924:924:924) (931:931:931)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (589:589:589) (600:600:600)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1114:1114:1114)) + (PORT datab (212:212:212) (255:255:255)) + (PORT datac (1022:1022:1022) (1046:1046:1046)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (652:652:652)) + (PORT datab (668:668:668) (675:675:675)) + (PORT datad (340:340:340) (372:372:372)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (586:586:586) (596:596:596)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (887:887:887)) + (PORT datab (1149:1149:1149) (1194:1194:1194)) + (PORT datad (1123:1123:1123) (1111:1111:1111)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1395:1395:1395) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1389:1389:1389) (1407:1407:1407)) + (PORT datac (1351:1351:1351) (1362:1362:1362)) + (PORT datad (1396:1396:1396) (1431:1431:1431)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (922:922:922) (928:928:928)) + (PORT ena (1152:1152:1152) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (612:612:612)) + (PORT datab (618:618:618) (641:641:641)) + (PORT datad (829:829:829) (818:818:818)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (753:753:753) (743:743:743)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (720:720:720)) + (PORT datab (1390:1390:1390) (1409:1409:1409)) + (PORT datac (178:178:178) (220:220:220)) + (PORT datad (1325:1325:1325) (1317:1317:1317)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (716:716:716)) + (PORT datab (1386:1386:1386) (1404:1404:1404)) + (PORT datac (174:174:174) (213:213:213)) + (PORT datad (1323:1323:1323) (1315:1315:1315)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1072:1072:1072) (1059:1059:1059)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (634:634:634)) + (PORT datab (379:379:379) (417:417:417)) + (PORT datad (362:362:362) (380:380:380)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (636:636:636)) + (PORT datac (618:618:618) (647:647:647)) + (PORT datad (348:348:348) (365:365:365)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1071:1071:1071) (1057:1057:1057)) + (PORT ena (1413:1413:1413) (1387:1387:1387)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (865:865:865) (871:871:871)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (567:567:567)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (779:779:779) (768:768:768)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (887:887:887)) + (PORT datab (1140:1140:1140) (1188:1188:1188)) + (PORT datad (584:584:584) (597:597:597)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (887:887:887)) + (PORT datab (1140:1140:1140) (1186:1186:1186)) + (PORT datad (598:598:598) (610:610:610)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (886:886:886)) + (PORT datab (1149:1149:1149) (1194:1194:1194)) + (PORT datad (585:585:585) (597:597:597)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1144:1144:1144) (1134:1134:1134)) + (PORT ena (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (891:891:891)) + (PORT datab (1150:1150:1150) (1192:1192:1192)) + (PORT datad (595:595:595) (607:607:607)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1143:1143:1143) (1134:1134:1134)) + (PORT ena (1357:1357:1357) (1322:1322:1322)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (898:898:898)) + (PORT datab (882:882:882) (907:907:907)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (544:544:544) (540:540:540)) + (PORT datad (316:316:316) (316:316:316)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (832:832:832)) + (PORT datab (821:821:821) (796:796:796)) + (PORT datac (840:840:840) (848:848:848)) + (PORT datad (540:540:540) (530:530:530)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (405:405:405)) + (PORT datab (886:886:886) (883:883:883)) + (PORT datad (581:581:581) (598:598:598)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (821:821:821) (805:805:805)) + (PORT ena (1126:1126:1126) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (401:401:401)) + (PORT datab (888:888:888) (884:884:884)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1157:1157:1157)) + (PORT datab (607:607:607) (631:631:631)) + (PORT datad (603:603:603) (609:609:609)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (400:400:400)) + (PORT datab (615:615:615) (636:636:636)) + (PORT datad (520:520:520) (507:507:507)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1165:1165:1165) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (405:405:405)) + (PORT datab (610:610:610) (636:636:636)) + (PORT datad (523:523:523) (511:511:511)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (195:195:195) (261:261:261)) + (PORT datad (618:618:618) (614:614:614)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (651:651:651)) + (PORT datab (625:625:625) (624:624:624)) + (PORT datac (1116:1116:1116) (1121:1121:1121)) + (PORT datad (598:598:598) (602:602:602)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (581:581:581) (599:599:599)) + (PORT datad (1011:1011:1011) (989:989:989)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1165:1165:1165) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1097:1097:1097) (1068:1068:1068)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1097:1097:1097) (1068:1068:1068)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (910:910:910)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datad (642:642:642) (649:649:649)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (1110:1110:1110) (1094:1094:1094)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1366:1366:1366)) + (PORT datab (774:774:774) (761:761:761)) + (PORT datad (742:742:742) (732:732:732)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1325:1325:1325) (1291:1291:1291)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (839:839:839) (833:833:833)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (655:655:655)) + (PORT datab (670:670:670) (678:678:678)) + (PORT datad (336:336:336) (367:367:367)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (200:200:200)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (878:878:878) (876:876:876)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (429:429:429)) + (PORT datab (378:378:378) (411:411:411)) + (PORT datad (362:362:362) (375:375:375)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (879:879:879) (873:873:873)) + (PORT ena (1413:1413:1413) (1387:1387:1387)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (180:180:180) (213:213:213)) + (PORT datad (864:864:864) (872:872:872)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (839:839:839) (835:835:835)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1395:1395:1395) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1325:1325:1325) (1293:1293:1293)) + (PORT ena (1152:1152:1152) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (633:633:633)) + (PORT datab (615:615:615) (637:637:637)) + (PORT datad (825:825:825) (813:813:813)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (615:615:615)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (822:822:822) (812:812:812)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1103:1103:1103) (1069:1069:1069)) + (PORT ena (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1103:1103:1103) (1070:1070:1070)) + (PORT ena (1357:1357:1357) (1322:1322:1322)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (893:893:893)) + (PORT datab (879:879:879) (901:901:901)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (557:557:557) (555:555:555)) + (PORT datad (296:296:296) (297:297:297)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (756:756:756)) + (PORT datab (793:793:793) (790:790:790)) + (PORT datac (520:520:520) (515:515:515)) + (PORT datad (557:557:557) (552:552:552)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (806:806:806) (793:793:793)) + (PORT ena (1126:1126:1126) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1154:1154:1154)) + (PORT datab (1045:1045:1045) (1011:1011:1011)) + (PORT datad (604:604:604) (604:604:604)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (222:222:222) (292:292:292)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (618:618:618) (614:614:614)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (656:656:656)) + (PORT datab (526:526:526) (522:522:522)) + (PORT datac (201:201:201) (245:245:245)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (623:623:623)) + (PORT datad (730:730:730) (699:699:699)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (320:320:320)) + (PORT datab (543:543:543) (529:529:529)) + (PORT datac (580:580:580) (599:599:599)) + (PORT datad (1010:1010:1010) (988:988:988)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (657:657:657)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (199:199:199) (243:243:243)) + (PORT datad (952:952:952) (908:908:908)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (626:626:626)) + (PORT datad (791:791:791) (772:772:772)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (582:582:582)) + (PORT datad (223:223:223) (285:285:285)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (584:584:584)) + (PORT datab (609:609:609) (628:628:628)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1025:1025:1025)) + (PORT datab (247:247:247) (319:319:319)) + (PORT datac (162:162:162) (194:194:194)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1165:1165:1165) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (791:791:791) (779:779:779)) + (PORT ena (1126:1126:1126) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1157:1157:1157)) + (PORT datab (772:772:772) (782:782:782)) + (PORT datad (600:600:600) (603:603:603)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (295:295:295)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (616:616:616) (613:613:613)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (658:658:658)) + (PORT datab (776:776:776) (757:757:757)) + (PORT datac (199:199:199) (243:243:243)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (752:752:752) (752:752:752)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (739:739:739) (742:742:742)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (1062:1062:1062) (1057:1057:1057)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (218:218:218) (287:287:287)) + (PORT datad (185:185:185) (212:212:212)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (837:837:837) (838:838:838)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1567:1567:1567) (1556:1556:1556)) + (PORT datab (788:788:788) (798:798:798)) + (PORT datad (354:354:354) (381:381:381)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (839:839:839) (838:838:838)) + (PORT ena (1413:1413:1413) (1387:1387:1387)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~58) + (DELAY + (ABSOLUTE + (PORT datab (181:181:181) (213:213:213)) + (PORT datad (870:870:870) (872:872:872)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (1102:1102:1102) (1080:1080:1080)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (783:783:783) (768:768:768)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1302:1302:1302) (1266:1266:1266)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (407:407:407)) + (PORT datab (767:767:767) (760:760:760)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (859:859:859) (855:855:855)) + (PORT ena (1128:1128:1128) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (856:856:856) (853:853:853)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datad (188:188:188) (216:216:216)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (817:817:817) (818:818:818)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1182:1182:1182) (1172:1172:1172)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (649:649:649)) + (PORT datab (389:389:389) (423:423:423)) + (PORT datad (630:630:630) (636:636:636)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (334:334:334)) + (PORT datab (579:579:579) (571:571:571)) + (PORT datac (515:515:515) (502:502:502)) + (PORT datad (784:784:784) (769:769:769)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (555:555:555) (550:550:550)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (897:897:897) (887:887:887)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (911:911:911)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (639:639:639) (654:654:654)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (577:577:577)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (556:556:556) (539:539:539)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (774:774:774)) + (PORT datab (616:616:616) (619:619:619)) + (PORT datac (808:808:808) (789:789:789)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (353:353:353)) + (PORT datab (1053:1053:1053) (1050:1050:1050)) + (PORT datac (358:358:358) (364:364:364)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (357:357:357)) + (PORT datab (349:349:349) (369:369:369)) + (PORT datac (1202:1202:1202) (1164:1164:1164)) + (PORT datad (567:567:567) (567:567:567)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (657:657:657)) + (PORT datab (236:236:236) (289:289:289)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (711:711:711) (695:695:695)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1364:1364:1364) (1387:1387:1387)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (778:778:778)) + (PORT datab (1144:1144:1144) (1145:1145:1145)) + (PORT datad (777:777:777) (775:775:775)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1781:1781:1781) (1829:1829:1829)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1781:1781:1781) (1829:1829:1829)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (673:673:673)) + (PORT datab (626:626:626) (635:635:635)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (484:484:484) (510:510:510)) + (PORT ena (1883:1883:1883) (1930:1930:1930)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1636:1636:1636) (1669:1669:1669)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (654:654:654)) + (PORT datab (420:420:420) (441:441:441)) + (PORT datad (1076:1076:1076) (1091:1091:1091)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1489:1489:1489) (1513:1513:1513)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1486:1486:1486) (1510:1510:1510)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (891:891:891)) + (PORT datab (839:839:839) (824:824:824)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (792:792:792)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (514:514:514) (499:499:499)) + (PORT datad (741:741:741) (763:763:763)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1365:1365:1365) (1395:1395:1395)) + (PORT ena (1381:1381:1381) (1334:1334:1334)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1285:1285:1285)) + (PORT datab (1251:1251:1251) (1296:1296:1296)) + (PORT datad (811:811:811) (797:797:797)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT asdata (1096:1096:1096) (1123:1123:1123)) + (PORT ena (1363:1363:1363) (1383:1383:1383)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1365:1365:1365) (1391:1391:1391)) + (PORT ena (1401:1401:1401) (1384:1384:1384)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (872:872:872)) + (PORT datab (808:808:808) (874:874:874)) + (PORT datad (922:922:922) (948:948:948)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1120:1120:1120) (1144:1144:1144)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1119:1119:1119) (1144:1144:1144)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (803:803:803)) + (PORT datab (221:221:221) (291:291:291)) + (PORT datad (776:776:776) (759:759:759)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (804:804:804)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (338:338:338) (354:354:354)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (646:646:646)) + (PORT datab (213:213:213) (254:254:254)) + (PORT datac (348:348:348) (352:352:352)) + (PORT datad (559:559:559) (560:560:560)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (916:916:916)) + (PORT datab (839:839:839) (888:888:888)) + (PORT datac (523:523:523) (521:521:521)) + (PORT datad (605:605:605) (612:612:612)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (660:660:660) (663:663:663)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1120:1120:1120)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datad (1164:1164:1164) (1229:1229:1229)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (560:560:560)) + (PORT datac (1021:1021:1021) (1008:1008:1008)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (809:809:809) (811:811:811)) + (PORT datad (325:325:325) (331:331:331)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1347:1347:1347)) + (PORT ena (1819:1819:1819) (1765:1765:1765)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (580:580:580)) + (PORT datad (222:222:222) (285:285:285)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (188:188:188) (221:221:221)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (1010:1010:1010) (989:989:989)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (587:587:587) (621:621:621)) + (PORT datac (581:581:581) (588:588:588)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1165:1165:1165) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1438:1438:1438) (1420:1420:1420)) + (PORT ena (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (860:860:860) (856:856:856)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1357:1357:1357) (1322:1322:1322)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (893:893:893)) + (PORT datab (880:880:880) (905:905:905)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (636:636:636) (644:644:644)) + (PORT ena (1081:1081:1081) (1042:1042:1042)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (821:821:821) (809:809:809)) + (PORT ena (1302:1302:1302) (1266:1266:1266)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (823:823:823) (812:812:812)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (409:409:409)) + (PORT datab (765:765:765) (761:761:761)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (791:791:791)) + (PORT datad (305:305:305) (314:314:314)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1403:1403:1403) (1374:1374:1374)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1401:1401:1401) (1372:1372:1372)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (917:917:917)) + (PORT datab (678:678:678) (683:683:683)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1079:1079:1079)) + (PORT datab (1059:1059:1059) (1048:1048:1048)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1039:1039:1039) (1005:1005:1005)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1318:1318:1318) (1280:1280:1280)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (407:407:407)) + (PORT datab (384:384:384) (421:421:421)) + (PORT datad (367:367:367) (381:381:381)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1438:1438:1438) (1408:1408:1408)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (597:597:597) (611:611:611)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (911:911:911) (910:910:910)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (655:655:655)) + (PORT datab (390:390:390) (426:426:426)) + (PORT datad (630:630:630) (640:640:640)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (575:575:575)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datac (835:835:835) (832:832:832)) + (PORT datad (583:583:583) (578:578:578)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (797:797:797)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (973:973:973) (943:943:943)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (843:843:843) (832:832:832)) + (PORT datac (580:580:580) (574:574:574)) + (PORT datad (1309:1309:1309) (1301:1301:1301)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (629:629:629) (632:632:632)) + (PORT ena (1126:1126:1126) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1150:1150:1150)) + (PORT datab (603:603:603) (594:594:594)) + (PORT datad (606:606:606) (610:610:610)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (296:296:296)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (616:616:616) (616:616:616)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (656:656:656)) + (PORT datab (755:755:755) (736:736:736)) + (PORT datac (199:199:199) (243:243:243)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datac (1087:1087:1087) (1085:1085:1085)) + (PORT datad (513:513:513) (499:499:499)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1353:1353:1353)) + (PORT ena (1588:1588:1588) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (618:618:618)) + (PORT datab (587:587:587) (619:619:619)) + (PORT datac (215:215:215) (295:295:295)) + (PORT datad (576:576:576) (572:572:572)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1165:1165:1165) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1201:1201:1201) (1203:1203:1203)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1205:1205:1205) (1208:1208:1208)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (911:911:911)) + (PORT datab (680:680:680) (689:689:689)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1079:1079:1079) (1064:1064:1064)) + (PORT ena (1128:1128:1128) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1076:1076:1076) (1059:1059:1059)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (210:210:210) (252:252:252)) + (PORT datad (190:190:190) (218:218:218)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1071:1071:1071) (1054:1054:1054)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (893:893:893) (922:922:922)) + (PORT datac (739:739:739) (731:731:731)) + (PORT datad (557:557:557) (574:574:574)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (731:731:731)) + (PORT datab (1266:1266:1266) (1269:1269:1269)) + (PORT datac (967:967:967) (1011:1011:1011)) + (PORT datad (656:656:656) (706:706:706)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (606:606:606)) + (PORT datab (1070:1070:1070) (1075:1075:1075)) + (PORT datac (1068:1068:1068) (1042:1042:1042)) + (PORT datad (767:767:767) (750:750:750)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (785:785:785)) + (PORT datab (1589:1589:1589) (1571:1571:1571)) + (PORT datac (1236:1236:1236) (1303:1303:1303)) + (PORT datad (633:633:633) (662:662:662)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT asdata (484:484:484) (511:511:511)) + (PORT ena (1530:1530:1530) (1547:1547:1547)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (316:316:316)) + (PORT datab (245:245:245) (307:307:307)) + (PORT datac (1175:1175:1175) (1153:1153:1153)) + (PORT datad (223:223:223) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (867:867:867)) + (PORT datab (779:779:779) (762:762:762)) + (PORT datac (558:558:558) (575:575:575)) + (PORT datad (720:720:720) (749:749:749)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (587:587:587)) + (PORT datab (625:625:625) (649:649:649)) + (PORT datac (985:985:985) (928:928:928)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1368:1368:1368)) + (PORT datab (779:779:779) (769:769:769)) + (PORT datac (587:587:587) (587:587:587)) + (PORT datad (854:854:854) (881:881:881)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (725:725:725)) + (PORT datac (965:965:965) (1011:1011:1011)) + (PORT datad (654:654:654) (705:705:705)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (380:380:380)) + (PORT datab (813:813:813) (832:832:832)) + (PORT datac (1365:1365:1365) (1377:1377:1377)) + (PORT datad (206:206:206) (243:243:243)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (839:839:839) (840:840:840)) + (PORT datad (316:316:316) (325:325:325)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2238:2238:2238) (2326:2326:2326)) + (PORT datab (879:879:879) (901:901:901)) + (PORT datac (1101:1101:1101) (1123:1123:1123)) + (PORT datad (1127:1127:1127) (1154:1154:1154)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (677:677:677)) + (PORT datab (206:206:206) (245:245:245)) + (PORT datac (850:850:850) (869:869:869)) + (PORT datad (608:608:608) (625:625:625)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (585:585:585) (608:608:608)) + (PORT datad (176:176:176) (197:197:197)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (750:750:750)) + (PORT datab (598:598:598) (591:591:591)) + (PORT datac (587:587:587) (597:597:597)) + (PORT datad (496:496:496) (483:483:483)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~0) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (472:472:472)) + (PORT datab (1934:1934:1934) (1944:1944:1944)) + (PORT datac (1043:1043:1043) (1050:1050:1050)) + (PORT datad (946:946:946) (1003:1003:1003)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (809:809:809)) + (PORT datab (1013:1013:1013) (987:987:987)) + (PORT datac (563:563:563) (595:595:595)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1169:1169:1169)) + (PORT datab (1679:1679:1679) (1714:1714:1714)) + (PORT datac (1265:1265:1265) (1245:1245:1245)) + (PORT datad (1134:1134:1134) (1166:1166:1166)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1031:1031:1031)) + (PORT datab (1013:1013:1013) (987:987:987)) + (PORT datac (565:565:565) (591:591:591)) + (PORT datad (170:170:170) (197:197:197)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (471:471:471)) + (PORT datab (1932:1932:1932) (1943:1943:1943)) + (PORT datac (1038:1038:1038) (1047:1047:1047)) + (PORT datad (948:948:948) (1007:1007:1007)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (805:805:805)) + (PORT datab (807:807:807) (778:778:778)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (855:855:855)) + (PORT datad (879:879:879) (938:938:938)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (809:809:809)) + (PORT datab (831:831:831) (831:831:831)) + (PORT datac (586:586:586) (612:612:612)) + (PORT datad (568:568:568) (571:571:571)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (808:808:808) (829:829:829)) + (PORT datac (807:807:807) (783:783:783)) + (PORT datad (191:191:191) (223:223:223)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2138:2138:2138) (2149:2149:2149)) + (PORT datab (779:779:779) (767:767:767)) + (PORT datac (1200:1200:1200) (1231:1231:1231)) + (PORT datad (1305:1305:1305) (1307:1307:1307)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (812:812:812)) + (PORT datab (1146:1146:1146) (1146:1146:1146)) + (PORT datac (582:582:582) (607:607:607)) + (PORT datad (572:572:572) (575:575:575)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1204:1204:1204)) + (PORT datab (326:326:326) (349:349:349)) + (PORT datac (1425:1425:1425) (1558:1558:1558)) + (PORT datad (1304:1304:1304) (1341:1341:1341)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (864:864:864)) + (PORT datab (1111:1111:1111) (1158:1158:1158)) + (PORT datac (1791:1791:1791) (1797:1797:1797)) + (PORT datad (832:832:832) (839:839:839)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (590:590:590) (620:620:620)) + (PORT datac (541:541:541) (551:551:551)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1438:1438:1438) (1447:1447:1447)) + (PORT datab (1112:1112:1112) (1164:1164:1164)) + (PORT datac (334:334:334) (343:343:343)) + (PORT datad (841:841:841) (858:858:858)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1219:1219:1219)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (1406:1406:1406) (1442:1442:1442)) + (PORT datad (1442:1442:1442) (1493:1493:1493)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (360:360:360)) + (PORT datab (868:868:868) (866:866:866)) + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (1686:1686:1686) (1641:1641:1641)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (813:813:813)) + (PORT datab (869:869:869) (873:873:873)) + (PORT datac (556:556:556) (553:553:553)) + (PORT datad (1701:1701:1701) (1717:1717:1717)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~20) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (958:958:958)) + (PORT datab (930:930:930) (985:985:985)) + (PORT datad (1923:1923:1923) (1996:1996:1996)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (786:786:786)) + (PORT datab (793:793:793) (824:824:824)) + (PORT datac (556:556:556) (556:556:556)) + (PORT datad (804:804:804) (822:822:822)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (512:512:512) (501:501:501)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (891:891:891)) + (PORT datab (218:218:218) (263:263:263)) + (PORT datac (189:189:189) (230:230:230)) + (PORT datad (1296:1296:1296) (1311:1311:1311)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (407:407:407)) + (PORT datab (813:813:813) (820:820:820)) + (PORT datac (322:322:322) (327:327:327)) + (PORT datad (937:937:937) (951:951:951)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (899:899:899)) + (PORT datab (617:617:617) (621:621:621)) + (PORT datac (1213:1213:1213) (1192:1192:1192)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (220:220:220)) + (PORT datab (590:590:590) (609:609:609)) + (PORT datac (562:562:562) (562:562:562)) + (PORT datad (572:572:572) (589:589:589)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1354:1354:1354)) + (PORT asdata (487:487:487) (515:515:515)) + (PORT ena (1092:1092:1092) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1118:1118:1118)) + (PORT datab (1086:1086:1086) (1076:1076:1076)) + (PORT datad (538:538:538) (530:530:530)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1105:1105:1105) (1066:1066:1066)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (504:504:504) (527:527:527)) + (PORT datad (556:556:556) (549:549:549)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (1089:1089:1089) (1103:1103:1103)) + (PORT datac (164:164:164) (200:200:200)) + (PORT datad (545:545:545) (529:529:529)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (646:646:646)) + (PORT datab (315:315:315) (334:334:334)) + (PORT datac (188:188:188) (227:227:227)) + (PORT datad (564:564:564) (574:574:574)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (1400:1400:1400) (1381:1381:1381)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1104:1104:1104) (1089:1089:1089)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (739:739:739) (742:742:742)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (250:250:250)) + (PORT datab (206:206:206) (242:242:242)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1655:1655:1655) (1626:1626:1626)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1656:1656:1656) (1627:1627:1627)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (914:914:914)) + (PORT datab (675:675:675) (682:682:682)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (2124:2124:2124) (2097:2097:2097)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (2102:2102:2102) (2068:2068:2068)) + (PORT ena (765:765:765) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (215:215:215) (253:253:253)) + (PORT datad (609:609:609) (637:637:637)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (2578:2578:2578) (2500:2500:2500)) + (PORT ena (1413:1413:1413) (1387:1387:1387)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (354:354:354)) + (PORT datad (870:870:870) (877:877:877)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (293:293:293) (302:302:302)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1081:1081:1081) (1042:1042:1042)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (2357:2357:2357) (2292:2292:2292)) + (PORT ena (1302:1302:1302) (1266:1266:1266)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (404:404:404)) + (PORT datab (357:357:357) (402:402:402)) + (PORT datad (588:588:588) (583:583:583)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1362:1362:1362)) + (PORT datab (770:770:770) (768:768:768)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (791:791:791) (781:781:781)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (333:333:333)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (2418:2418:2418) (2358:2358:2358)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT asdata (883:883:883) (882:882:882)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (654:654:654)) + (PORT datab (670:670:670) (673:673:673)) + (PORT datad (354:354:354) (387:387:387)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (586:586:586)) + (PORT datab (813:813:813) (799:799:799)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (553:553:553) (549:549:549)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (833:833:833)) + (PORT datab (868:868:868) (875:875:875)) + (PORT datac (559:559:559) (559:559:559)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1587:1587:1587) (1558:1558:1558)) + (PORT datab (809:809:809) (799:799:799)) + (PORT datac (800:800:800) (821:821:821)) + (PORT datad (1050:1050:1050) (1022:1022:1022)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (602:602:602)) + (PORT datac (520:520:520) (529:529:529)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1106:1106:1106)) + (PORT datab (645:645:645) (674:674:674)) + (PORT datac (845:845:845) (868:868:868)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (652:652:652)) + (PORT datab (560:560:560) (551:551:551)) + (PORT datac (846:846:846) (857:857:857)) + (PORT datad (775:775:775) (743:743:743)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (495:495:495) (479:479:479)) + (PORT datad (326:326:326) (337:337:337)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1091:1091:1091)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (554:554:554) (550:550:550)) + (PORT datad (368:368:368) (405:405:405)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (1041:1041:1041)) + (PORT datab (1250:1250:1250) (1290:1290:1290)) + (PORT datac (1357:1357:1357) (1357:1357:1357)) + (PORT datad (982:982:982) (968:968:968)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (899:899:899)) + (PORT datab (195:195:195) (232:232:232)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1095:1095:1095) (1117:1117:1117)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1370:1370:1370) (1427:1427:1427)) + (PORT datab (894:894:894) (909:909:909)) + (PORT datac (1574:1574:1574) (1566:1566:1566)) + (PORT datad (196:196:196) (217:217:217)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (281:281:281)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (156:156:156) (188:188:188)) + (PORT datad (182:182:182) (208:208:208)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1174:1174:1174)) + (PORT datab (1118:1118:1118) (1116:1116:1116)) + (PORT datac (860:860:860) (870:870:870)) + (PORT datad (1236:1236:1236) (1217:1217:1217)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (755:755:755)) + (PORT datab (588:588:588) (595:595:595)) + (PORT datac (774:774:774) (759:759:759)) + (PORT datad (505:505:505) (489:489:489)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1099:1099:1099)) + (PORT datac (2221:2221:2221) (2259:2259:2259)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1232:1232:1232)) + (PORT datab (844:844:844) (880:880:880)) + (PORT datad (733:733:733) (716:716:716)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1257:1257:1257)) + (PORT datab (603:603:603) (633:633:633)) + (PORT datac (570:570:570) (584:584:584)) + (PORT datad (1610:1610:1610) (1622:1622:1622)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (585:585:585)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datad (484:484:484) (474:474:474)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (635:635:635)) + (PORT datab (1822:1822:1822) (1816:1816:1816)) + (PORT datac (759:759:759) (743:743:743)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1033:1033:1033)) + (PORT datab (795:795:795) (775:775:775)) + (PORT datac (581:581:581) (588:588:588)) + (PORT datad (641:641:641) (685:685:685)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1505:1505:1505) (1558:1558:1558)) + (PORT datab (1063:1063:1063) (1079:1079:1079)) + (PORT datac (1680:1680:1680) (1721:1721:1721)) + (PORT datad (1535:1535:1535) (1560:1560:1560)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (854:854:854)) + (PORT datab (603:603:603) (603:603:603)) + (PORT datac (178:178:178) (223:223:223)) + (PORT datad (782:782:782) (798:798:798)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1075:1075:1075) (1053:1053:1053)) + (PORT datac (985:985:985) (947:947:947)) + (PORT datad (549:549:549) (535:535:535)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (996:996:996)) + (PORT datab (946:946:946) (1006:1006:1006)) + (PORT datac (1127:1127:1127) (1147:1147:1147)) + (PORT datad (815:815:815) (814:814:814)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (1295:1295:1295) (1300:1300:1300)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1692:1692:1692) (1696:1696:1696)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (638:638:638)) + (PORT datab (1822:1822:1822) (1816:1816:1816)) + (PORT datac (310:310:310) (328:328:328)) + (PORT datad (831:831:831) (832:832:832)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1068:1068:1068) (1090:1090:1090)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1532:1532:1532) (1593:1593:1593)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (809:809:809)) + (PORT datab (218:218:218) (286:286:286)) + (PORT datad (780:780:780) (761:761:761)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (904:904:904) (938:938:938)) + (PORT ena (1381:1381:1381) (1334:1334:1334)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1282:1282:1282)) + (PORT datab (1251:1251:1251) (1295:1295:1295)) + (PORT datad (811:811:811) (796:796:796)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (924:924:924) (949:949:949)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (925:925:925) (952:952:952)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (897:897:897)) + (PORT datab (219:219:219) (288:288:288)) + (PORT datad (805:805:805) (795:795:795)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (897:897:897) (916:916:916)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (823:823:823)) + (PORT datab (1142:1142:1142) (1146:1146:1146)) + (PORT datad (844:844:844) (834:834:834)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1600:1600:1600) (1568:1568:1568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (609:609:609) (614:614:614)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (292:292:292)) + (PORT datab (421:421:421) (437:437:437)) + (PORT datad (1079:1079:1079) (1087:1087:1087)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1553:1553:1553) (1597:1597:1597)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1553:1553:1553) (1595:1595:1595)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (670:670:670)) + (PORT datab (628:628:628) (638:638:638)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (782:782:782)) + (PORT datab (349:349:349) (348:348:348)) + (PORT datac (573:573:573) (581:581:581)) + (PORT datad (722:722:722) (775:775:775)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT asdata (1413:1413:1413) (1447:1447:1447)) + (PORT ena (1363:1363:1363) (1383:1383:1383)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (903:903:903) (936:936:936)) + (PORT ena (1401:1401:1401) (1384:1384:1384)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (872:872:872)) + (PORT datab (781:781:781) (859:859:859)) + (PORT datad (921:921:921) (947:947:947)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (400:400:400)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (825:825:825) (816:816:816)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1733:1733:1733) (1759:1759:1759)) + (PORT datab (1207:1207:1207) (1271:1271:1271)) + (PORT datad (1066:1066:1066) (1074:1074:1074)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (392:392:392) (428:428:428)) + (PORT datac (1057:1057:1057) (1053:1053:1053)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (624:624:624)) + (PORT datac (593:593:593) (595:595:595)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (590:590:590)) + (PORT datab (833:833:833) (809:809:809)) + (PORT datac (815:815:815) (826:826:826)) + (PORT datad (635:635:635) (669:669:669)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (353:353:353)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (1076:1076:1076) (1087:1087:1087)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (673:673:673)) + (PORT datab (561:561:561) (581:581:581)) + (PORT datac (565:565:565) (596:596:596)) + (PORT datad (762:762:762) (758:758:758)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (923:923:923)) + (PORT datab (590:590:590) (594:594:594)) + (PORT datac (838:838:838) (875:875:875)) + (PORT datad (599:599:599) (607:607:607)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (236:236:236) (289:289:289)) + (PORT datac (760:760:760) (735:735:735)) + (PORT datad (819:819:819) (836:836:836)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (760:760:760)) + (PORT datac (826:826:826) (807:807:807)) + (PORT datad (1111:1111:1111) (1128:1128:1128)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1100:1100:1100)) + (PORT datac (564:564:564) (574:574:574)) + (PORT datad (763:763:763) (748:748:748)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1097:1097:1097)) + (PORT datab (563:563:563) (567:567:567)) + (PORT datac (770:770:770) (762:762:762)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (562:562:562) (567:567:567)) + (PORT datad (483:483:483) (475:475:475)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1024:1024:1024)) + (PORT datab (237:237:237) (305:305:305)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1602:1602:1602) (1620:1620:1620)) + (PORT datab (935:935:935) (990:990:990)) + (PORT datac (1274:1274:1274) (1258:1258:1258)) + (PORT datad (1329:1329:1329) (1345:1345:1345)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1156:1156:1156)) + (PORT datab (1609:1609:1609) (1620:1620:1620)) + (PORT datac (1334:1334:1334) (1470:1470:1470)) + (PORT datad (173:173:173) (202:202:202)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1546:1546:1546)) + (PORT datab (1896:1896:1896) (1923:1923:1923)) + (PORT datac (1036:1036:1036) (1038:1038:1038)) + (PORT datad (1022:1022:1022) (1022:1022:1022)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (772:772:772)) + (PORT datab (680:680:680) (720:720:720)) + (PORT datac (545:545:545) (533:533:533)) + (PORT datad (1002:1002:1002) (994:994:994)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1214:1214:1214)) + (PORT datab (1607:1607:1607) (1584:1584:1584)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (588:588:588) (616:616:616)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1399:1399:1399)) + (PORT datab (1894:1894:1894) (1920:1920:1920)) + (PORT datac (2185:2185:2185) (2245:2245:2245)) + (PORT datad (355:355:355) (365:365:365)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (228:228:228)) + (PORT datab (351:351:351) (360:360:360)) + (PORT datac (790:790:790) (797:797:797)) + (PORT datad (191:191:191) (216:216:216)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (974:974:974)) + (PORT datab (834:834:834) (811:811:811)) + (PORT datac (801:801:801) (819:819:819)) + (PORT datad (964:964:964) (943:943:943)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (539:539:539)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (589:589:589) (589:589:589)) + (PORT datad (610:610:610) (632:632:632)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (339:339:339)) + (PORT datab (211:211:211) (250:250:250)) + (PORT datac (499:499:499) (482:482:482)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (786:786:786)) + (PORT datab (922:922:922) (955:955:955)) + (PORT datac (2092:2092:2092) (2157:2157:2157)) + (PORT datad (1624:1624:1624) (1677:1677:1677)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (789:789:789)) + (PORT datab (1087:1087:1087) (1091:1091:1091)) + (PORT datac (2090:2090:2090) (2160:2160:2160)) + (PORT datad (1623:1623:1623) (1681:1681:1681)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (790:790:790)) + (PORT datab (1099:1099:1099) (1084:1084:1084)) + (PORT datac (2090:2090:2090) (2158:2158:2158)) + (PORT datad (1623:1623:1623) (1679:1679:1679)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (826:826:826)) + (PORT datac (726:726:726) (702:702:702)) + (PORT datad (960:960:960) (947:947:947)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (883:883:883) (896:896:896)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (476:476:476)) + (PORT datab (1932:1932:1932) (1938:1938:1938)) + (PORT datac (1041:1041:1041) (1044:1044:1044)) + (PORT datad (951:951:951) (1010:1010:1010)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (586:586:586)) + (PORT datab (2741:2741:2741) (2755:2755:2755)) + (PORT datac (523:523:523) (518:518:518)) + (PORT datad (1242:1242:1242) (1228:1228:1228)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (902:902:902)) + (PORT datab (571:571:571) (578:578:578)) + (PORT datad (478:478:478) (466:466:466)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (891:891:891)) + (PORT datab (1369:1369:1369) (1412:1412:1412)) + (PORT datac (2152:2152:2152) (2180:2180:2180)) + (PORT datad (1616:1616:1616) (1639:1639:1639)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (975:975:975)) + (PORT datab (808:808:808) (831:831:831)) + (PORT datac (800:800:800) (818:818:818)) + (PORT datad (1006:1006:1006) (982:982:982)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (284:284:284)) + (PORT datab (891:891:891) (905:905:905)) + (PORT datac (569:569:569) (563:563:563)) + (PORT datad (780:780:780) (770:770:770)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1619:1619:1619) (1617:1617:1617)) + (PORT datab (1435:1435:1435) (1461:1461:1461)) + (PORT datac (327:327:327) (334:334:334)) + (PORT datad (2292:2292:2292) (2307:2307:2307)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (862:862:862) (860:860:860)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (207:207:207) (244:244:244)) + (PORT datac (739:739:739) (711:711:711)) + (PORT datad (574:574:574) (570:570:570)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (792:792:792)) + (PORT datab (812:812:812) (844:844:844)) + (PORT datac (2091:2091:2091) (2162:2162:2162)) + (PORT datad (1624:1624:1624) (1682:1682:1682)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (893:893:893)) + (PORT datab (854:854:854) (851:851:851)) + (PORT datac (2152:2152:2152) (2178:2178:2178)) + (PORT datad (1331:1331:1331) (1377:1377:1377)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1574:1574:1574) (1564:1564:1564)) + (PORT datab (877:877:877) (909:909:909)) + (PORT datac (863:863:863) (903:903:903)) + (PORT datad (1521:1521:1521) (1510:1510:1510)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (815:815:815) (802:802:802)) + (PORT datac (294:294:294) (304:304:304)) + (PORT datad (193:193:193) (224:224:224)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1227:1227:1227) (1210:1210:1210)) + (PORT datab (394:394:394) (442:442:442)) + (PORT datac (326:326:326) (334:334:334)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1035:1035:1035)) + (PORT datab (745:745:745) (739:739:739)) + (PORT datac (562:562:562) (594:594:594)) + (PORT datad (171:171:171) (199:199:199)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (235:235:235)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1078:1078:1078) (1079:1079:1079)) + (PORT datad (482:482:482) (469:469:469)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (220:220:220)) + (PORT datab (758:758:758) (739:739:739)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (791:791:791)) + (PORT datab (559:559:559) (561:561:561)) + (PORT datac (1213:1213:1213) (1205:1205:1205)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1620:1620:1620)) + (PORT datab (201:201:201) (236:236:236)) + (PORT datac (517:517:517) (520:520:520)) + (PORT datad (569:569:569) (588:588:588)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (248:248:248)) + (PORT datab (798:798:798) (827:827:827)) + (PORT datac (1574:1574:1574) (1584:1584:1584)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1607:1607:1607) (1613:1613:1613)) + (PORT datab (1337:1337:1337) (1326:1326:1326)) + (PORT datac (570:570:570) (561:561:561)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (243:243:243)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (752:752:752) (783:783:783)) + (PORT datad (203:203:203) (227:227:227)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (930:930:930) (933:933:933)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1335:1335:1335)) + (PORT datab (1591:1591:1591) (1592:1592:1592)) + (PORT datac (331:331:331) (340:340:340)) + (PORT datad (1100:1100:1100) (1106:1106:1106)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (251:251:251)) + (PORT datab (601:601:601) (633:633:633)) + (PORT datac (1292:1292:1292) (1300:1300:1300)) + (PORT datad (1017:1017:1017) (1003:1003:1003)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (549:549:549)) + (PORT datab (215:215:215) (256:256:256)) + (PORT datac (1111:1111:1111) (1099:1099:1099)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (582:582:582) (614:614:614)) + (PORT datac (582:582:582) (608:608:608)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (890:890:890)) + (PORT datab (1320:1320:1320) (1343:1343:1343)) + (PORT datac (334:334:334) (341:341:341)) + (PORT datad (1102:1102:1102) (1104:1104:1104)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (1150:1150:1150) (1200:1200:1200)) + (PORT datac (819:819:819) (855:855:855)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (278:278:278)) + (PORT datab (860:860:860) (896:896:896)) + (PORT datac (494:494:494) (485:485:485)) + (PORT datad (853:853:853) (874:874:874)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (241:241:241)) + (PORT datab (1068:1068:1068) (1073:1073:1073)) + (PORT datac (787:787:787) (783:783:783)) + (PORT datad (608:608:608) (634:634:634)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (842:842:842)) + (PORT datab (813:813:813) (817:817:817)) + (PORT datac (378:378:378) (403:403:403)) + (PORT datad (937:937:937) (949:949:949)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (360:360:360)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (202:202:202) (226:226:226)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (614:614:614)) + (PORT datab (630:630:630) (657:657:657)) + (PORT datac (887:887:887) (921:921:921)) + (PORT datad (1321:1321:1321) (1324:1324:1324)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1965:1965:1965) (2033:2033:2033)) + (PORT datab (1341:1341:1341) (1349:1349:1349)) + (PORT datac (902:902:902) (955:955:955)) + (PORT datad (1326:1326:1326) (1325:1325:1325)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (363:363:363)) + (PORT datab (376:376:376) (376:376:376)) + (PORT datac (1103:1103:1103) (1078:1078:1078)) + (PORT datad (316:316:316) (319:319:319)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1232:1232:1232)) + (PORT datab (1031:1031:1031) (1008:1008:1008)) + (PORT datac (308:308:308) (321:321:321)) + (PORT datad (1084:1084:1084) (1043:1043:1043)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1232:1232:1232)) + (PORT datab (1459:1459:1459) (1503:1503:1503)) + (PORT datac (1392:1392:1392) (1439:1439:1439)) + (PORT datad (1080:1080:1080) (1041:1041:1041)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (857:857:857)) + (PORT datab (1229:1229:1229) (1233:1233:1233)) + (PORT datac (311:311:311) (324:324:324)) + (PORT datad (1131:1131:1131) (1145:1145:1145)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1168:1168:1168) (1179:1179:1179)) + (PORT datac (565:565:565) (605:605:605)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1193:1193:1193)) + (PORT datab (843:843:843) (826:826:826)) + (PORT datac (1394:1394:1394) (1441:1441:1441)) + (PORT datad (1141:1141:1141) (1196:1196:1196)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (178:178:178) (224:224:224)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (689:689:689)) + (PORT datab (1475:1475:1475) (1523:1523:1523)) + (PORT datac (1434:1434:1434) (1488:1488:1488)) + (PORT datad (1420:1420:1420) (1543:1543:1543)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1021:1021:1021) (1045:1045:1045)) + (PORT datac (752:752:752) (783:783:783)) + (PORT datad (1088:1088:1088) (1080:1080:1080)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (745:745:745)) + (PORT datab (1111:1111:1111) (1095:1095:1095)) + (PORT datac (500:500:500) (483:483:483)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (814:814:814)) + (PORT datab (801:801:801) (814:814:814)) + (PORT datad (1392:1392:1392) (1405:1405:1405)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (331:331:331)) + (PORT datab (1116:1116:1116) (1167:1167:1167)) + (PORT datac (1791:1791:1791) (1800:1800:1800)) + (PORT datad (849:849:849) (861:861:861)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (421:421:421)) + (PORT datab (593:593:593) (607:607:607)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (316:316:316) (318:318:318)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (707:707:707) (744:744:744)) + (PORT datac (338:338:338) (359:359:359)) + (PORT datad (739:739:739) (708:708:708)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (612:612:612) (616:616:616)) + (PORT datac (174:174:174) (204:204:204)) + (PORT datad (304:304:304) (312:312:312)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (773:773:773) (769:769:769)) + (PORT datac (553:553:553) (577:577:577)) + (PORT datad (847:847:847) (873:873:873)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (608:608:608)) + (PORT datab (770:770:770) (766:766:766)) + (PORT datac (1314:1314:1314) (1334:1334:1334)) + (PORT datad (1035:1035:1035) (1033:1033:1033)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (892:892:892) (917:917:917)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (684:684:684)) + (PORT datab (1138:1138:1138) (1157:1157:1157)) + (PORT datac (1074:1074:1074) (1098:1098:1098)) + (PORT datad (966:966:966) (1011:1011:1011)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (793:793:793) (784:784:784)) + (PORT datac (1042:1042:1042) (1049:1049:1049)) + (PORT datad (816:816:816) (808:808:808)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (774:774:774)) + (PORT datac (364:364:364) (410:410:410)) + (PORT datad (341:341:341) (382:382:382)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (676:676:676) (704:704:704)) + (PORT datac (617:617:617) (646:646:646)) + (PORT datad (966:966:966) (1008:1008:1008)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (987:987:987)) + (PORT datab (212:212:212) (250:250:250)) + (PORT datac (737:737:737) (729:729:729)) + (PORT datad (769:769:769) (763:763:763)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (372:372:372)) + (PORT datab (541:541:541) (529:529:529)) + (PORT datac (1258:1258:1258) (1238:1238:1238)) + (PORT datad (1045:1045:1045) (1068:1068:1068)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (241:241:241)) + (PORT datab (809:809:809) (827:827:827)) + (PORT datac (1632:1632:1632) (1678:1678:1678)) + (PORT datad (1243:1243:1243) (1223:1223:1223)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2097:2097:2097) (2061:2061:2061)) + (PORT datab (2640:2640:2640) (2685:2685:2685)) + (PORT datac (897:897:897) (932:932:932)) + (PORT datad (1240:1240:1240) (1220:1220:1220)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (841:841:841)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1202:1202:1202)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (751:751:751) (804:804:804)) + (PORT datad (564:564:564) (584:584:584)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (959:959:959)) + (PORT datab (237:237:237) (305:305:305)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (827:827:827)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (813:813:813) (804:804:804)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (238:238:238)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (805:805:805)) + (PORT datac (789:789:789) (800:800:800)) + (PORT datad (807:807:807) (826:826:826)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (839:839:839)) + (PORT datac (562:562:562) (559:559:559)) + (PORT datad (340:340:340) (345:345:345)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (813:813:813)) + (PORT datab (1107:1107:1107) (1134:1134:1134)) + (PORT datac (1069:1069:1069) (1044:1044:1044)) + (PORT datad (760:760:760) (750:750:750)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (1045:1045:1045) (1053:1053:1053)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (639:639:639)) + (PORT datab (648:648:648) (677:677:677)) + (PORT datac (546:546:546) (538:538:538)) + (PORT datad (964:964:964) (951:951:951)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (238:238:238)) + (PORT datac (560:560:560) (544:544:544)) + (PORT datad (340:340:340) (342:342:342)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (236:236:236)) + (PORT datab (692:692:692) (736:736:736)) + (PORT datac (965:965:965) (1009:1009:1009)) + (PORT datad (630:630:630) (680:680:680)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (809:809:809)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (316:316:316) (319:319:319)) + (PORT datad (174:174:174) (206:206:206)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (728:728:728)) + (PORT datab (1261:1261:1261) (1242:1242:1242)) + (PORT datac (1138:1138:1138) (1200:1200:1200)) + (PORT datad (611:611:611) (639:639:639)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (325:325:325)) + (PORT datab (251:251:251) (314:314:314)) + (PORT datad (225:225:225) (259:259:259)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (388:388:388)) + (PORT datab (367:367:367) (372:372:372)) + (PORT datac (1290:1290:1290) (1301:1301:1301)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1306:1306:1306)) + (PORT datac (1048:1048:1048) (1044:1044:1044)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (824:824:824) (815:815:815)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1672:1672:1672) (1712:1712:1712)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1672:1672:1672) (1712:1712:1712)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (806:806:806)) + (PORT datab (390:390:390) (448:448:448)) + (PORT datad (778:778:778) (759:759:759)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1873:1873:1873) (1912:1912:1912)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (752:752:752) (786:786:786)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (666:666:666)) + (PORT datab (629:629:629) (638:638:638)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1531:1531:1531) (1532:1532:1532)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1083:1083:1083)) + (PORT datab (1147:1147:1147) (1141:1141:1141)) + (PORT datad (779:779:779) (777:777:777)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1883:1883:1883) (1930:1930:1930)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1591:1591:1591) (1615:1615:1615)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (627:627:627)) + (PORT datab (420:420:420) (444:444:444)) + (PORT datad (1078:1078:1078) (1090:1090:1090)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1316:1316:1316) (1359:1359:1359)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1317:1317:1317) (1359:1359:1359)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (893:893:893)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (806:806:806) (791:791:791)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (782:782:782)) + (PORT datab (522:522:522) (522:522:522)) + (PORT datac (917:917:917) (919:919:919)) + (PORT datad (333:333:333) (343:343:343)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1085:1085:1085) (1108:1108:1108)) + (PORT ena (1381:1381:1381) (1334:1334:1334)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1280:1280:1280)) + (PORT datab (1253:1253:1253) (1299:1299:1299)) + (PORT datad (810:810:810) (793:793:793)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1672:1672:1672) (1714:1714:1714)) + (PORT ena (914:914:914) (918:918:918)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1081:1081:1081) (1104:1104:1104)) + (PORT ena (1401:1401:1401) (1384:1384:1384)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (873:873:873)) + (PORT datab (609:609:609) (654:654:654)) + (PORT datad (921:921:921) (946:946:946)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (376:376:376)) + (PORT datab (734:734:734) (762:762:762)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (542:542:542)) + (PORT datab (212:212:212) (255:255:255)) + (PORT datac (586:586:586) (619:619:619)) + (PORT datad (748:748:748) (780:780:780)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1113:1113:1113)) + (PORT datab (1206:1206:1206) (1264:1264:1264)) + (PORT datad (176:176:176) (197:197:197)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (308:308:308) (324:324:324)) + (PORT datac (1021:1021:1021) (1006:1006:1006)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (671:671:671)) + (PORT datab (663:663:663) (713:713:713)) + (PORT datac (759:759:759) (743:743:743)) + (PORT datad (562:562:562) (569:569:569)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (1105:1105:1105) (1117:1117:1117)) + (PORT datac (611:611:611) (625:625:625)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datac (1085:1085:1085) (1081:1081:1081)) + (PORT datad (558:558:558) (567:567:567)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1353:1353:1353)) + (PORT ena (1588:1588:1588) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1547:1547:1547) (1531:1531:1531)) + (PORT datab (612:612:612) (620:620:620)) + (PORT datac (1009:1009:1009) (995:995:995)) + (PORT datad (591:591:591) (633:633:633)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (622:622:622)) + (PORT datad (304:304:304) (316:316:316)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1023:1023:1023)) + (PORT datab (608:608:608) (616:616:616)) + (PORT datac (808:808:808) (833:833:833)) + (PORT datad (1503:1503:1503) (1491:1491:1491)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (610:610:610)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datac (847:847:847) (879:879:879)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (648:648:648) (653:653:653)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1120:1120:1120)) + (PORT datab (1202:1202:1202) (1264:1264:1264)) + (PORT datad (1005:1005:1005) (998:998:998)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (355:355:355)) + (PORT datab (223:223:223) (292:292:292)) + (PORT datac (1025:1025:1025) (1013:1013:1013)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (603:603:603)) + (PORT datab (1105:1105:1105) (1113:1113:1113)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (342:342:342) (361:361:361)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (872:872:872) (866:866:866)) + (PORT ena (914:914:914) (918:918:918)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (872:872:872) (866:866:866)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (217:217:217) (262:262:262)) + (PORT datad (519:519:519) (501:501:501)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1363:1363:1363) (1365:1365:1365)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1363:1363:1363) (1365:1365:1365)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (892:892:892)) + (PORT datab (838:838:838) (825:825:825)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1600:1600:1600) (1568:1568:1568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (837:837:837) (818:818:818)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (PORT datab (420:420:420) (436:436:436)) + (PORT datad (1071:1071:1071) (1084:1084:1084)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (884:884:884) (878:878:878)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (883:883:883) (877:877:877)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (673:673:673)) + (PORT datab (625:625:625) (634:634:634)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (898:898:898) (907:907:907)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (822:822:822)) + (PORT datab (1145:1145:1145) (1139:1139:1139)) + (PORT datad (794:794:794) (783:783:783)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (582:582:582)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (503:503:503) (492:492:492)) + (PORT datad (540:540:540) (544:544:544)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (903:903:903) (911:911:911)) + (PORT ena (1358:1358:1358) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (756:756:756)) + (PORT datab (1082:1082:1082) (1084:1084:1084)) + (PORT datad (1222:1222:1222) (1213:1213:1213)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1267:1267:1267) (1296:1296:1296)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1265:1265:1265) (1295:1295:1295)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (807:807:807)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (779:779:779) (755:755:755)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1012:1012:1012)) + (PORT datab (590:590:590) (611:611:611)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (536:536:536) (539:539:539)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (667:667:667)) + (PORT datab (611:611:611) (610:610:610)) + (PORT datac (568:568:568) (597:597:597)) + (PORT datad (575:575:575) (588:588:588)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (656:656:656)) + (PORT datab (743:743:743) (730:730:730)) + (PORT datac (845:845:845) (882:882:882)) + (PORT datad (1380:1380:1380) (1409:1409:1409)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (880:880:880)) + (PORT datab (184:184:184) (218:218:218)) + (PORT datac (345:345:345) (367:367:367)) + (PORT datad (299:299:299) (307:307:307)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (337:337:337)) + (PORT datab (343:343:343) (368:368:368)) + (PORT datac (1255:1255:1255) (1252:1252:1252)) + (PORT datad (1405:1405:1405) (1420:1420:1420)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (598:598:598)) + (PORT datab (1281:1281:1281) (1266:1266:1266)) + (PORT datac (535:535:535) (521:521:521)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (618:618:618)) + (PORT datab (1085:1085:1085) (1101:1101:1101)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (310:310:310) (316:316:316)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (768:768:768) (761:761:761)) + (PORT datac (588:588:588) (588:588:588)) + (PORT datad (853:853:853) (882:882:882)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (232:232:232)) + (PORT datab (990:990:990) (1045:1045:1045)) + (PORT datac (798:798:798) (828:828:828)) + (PORT datad (1038:1038:1038) (1055:1055:1055)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (836:836:836)) + (PORT datab (204:204:204) (241:241:241)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (830:830:830)) + (PORT datab (842:842:842) (861:861:861)) + (PORT datac (777:777:777) (777:777:777)) + (PORT datad (790:790:790) (779:779:779)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (768:768:768)) + (PORT datab (363:363:363) (377:377:377)) + (PORT datac (552:552:552) (548:548:548)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (823:823:823)) + (PORT datab (364:364:364) (378:378:378)) + (PORT datad (163:163:163) (186:186:186)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1540:1540:1540) (1565:1565:1565)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1134:1134:1134)) + (PORT datab (1108:1108:1108) (1134:1134:1134)) + (PORT datac (625:625:625) (651:651:651)) + (PORT datad (966:966:966) (1012:1012:1012)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (812:812:812)) + (PORT datab (793:793:793) (785:785:785)) + (PORT datac (1040:1040:1040) (1050:1050:1050)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1330:1330:1330)) + (PORT datab (1589:1589:1589) (1572:1572:1572)) + (PORT datac (800:800:800) (829:829:829)) + (PORT datad (352:352:352) (396:396:396)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (245:245:245) (307:307:307)) + (PORT datad (223:223:223) (256:256:256)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (312:312:312)) + (PORT datab (530:530:530) (525:525:525)) + (PORT datac (1171:1171:1171) (1148:1148:1148)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (863:863:863)) + (PORT datac (353:353:353) (391:391:391)) + (PORT datad (725:725:725) (753:753:753)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1130:1130:1130)) + (PORT datab (828:828:828) (810:810:810)) + (PORT datac (758:758:758) (750:750:750)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (645:645:645) (649:649:649)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1442:1442:1442)) + (PORT datab (1206:1206:1206) (1264:1264:1264)) + (PORT datad (1065:1065:1065) (1072:1072:1072)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1090:1090:1090)) + (PORT datab (559:559:559) (593:593:593)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (812:812:812) (814:814:814)) + (PORT datad (501:501:501) (497:497:497)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1347:1347:1347)) + (PORT ena (1819:1819:1819) (1765:1765:1765)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (611:611:611)) + (PORT datab (856:856:856) (872:872:872)) + (PORT datac (577:577:577) (588:588:588)) + (PORT datad (964:964:964) (933:933:933)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (805:805:805)) + (PORT datab (989:989:989) (964:964:964)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (333:333:333)) + (PORT datab (363:363:363) (387:387:387)) + (PORT datac (1074:1074:1074) (1088:1088:1088)) + (PORT datad (529:529:529) (521:521:521)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1578:1578:1578) (1570:1570:1570)) + (PORT ena (1381:1381:1381) (1334:1334:1334)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1286:1286:1286)) + (PORT datab (1250:1250:1250) (1296:1296:1296)) + (PORT datad (811:811:811) (798:798:798)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1116:1116:1116) (1130:1130:1130)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1120:1120:1120) (1134:1134:1134)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (811:811:811)) + (PORT datab (223:223:223) (292:292:292)) + (PORT datad (781:781:781) (762:762:762)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (854:854:854) (838:838:838)) + (PORT ena (914:914:914) (918:918:918)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1578:1578:1578) (1568:1568:1568)) + (PORT ena (1401:1401:1401) (1384:1384:1384)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (870:870:870)) + (PORT datab (609:609:609) (653:653:653)) + (PORT datad (922:922:922) (949:949:949)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1701:1701:1701) (1707:1707:1707)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1699:1699:1699) (1706:1706:1706)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (893:893:893)) + (PORT datab (841:841:841) (828:828:828)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (177:177:177) (199:199:199)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1600:1600:1600) (1568:1568:1568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (847:847:847) (829:829:829)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (420:420:420) (441:441:441)) + (PORT datad (1077:1077:1077) (1091:1091:1091)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (840:840:840) (833:833:833)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1357:1357:1357) (1383:1383:1383)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (670:670:670)) + (PORT datab (629:629:629) (639:639:639)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1354:1354:1354) (1347:1347:1347)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (806:806:806)) + (PORT datab (1154:1154:1154) (1151:1151:1151)) + (PORT datad (826:826:826) (812:812:812)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (733:733:733)) + (PORT datab (595:595:595) (594:594:594)) + (PORT datac (721:721:721) (760:760:760)) + (PORT datad (300:300:300) (302:302:302)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (342:342:342) (368:368:368)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (619:619:619)) + (PORT datab (592:592:592) (620:620:620)) + (PORT datac (626:626:626) (640:640:640)) + (PORT datad (548:548:548) (555:555:555)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (663:663:663)) + (PORT datab (845:845:845) (879:879:879)) + (PORT datac (838:838:838) (873:873:873)) + (PORT datad (554:554:554) (558:558:558)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (237:237:237) (292:292:292)) + (PORT datac (1049:1049:1049) (1029:1029:1029)) + (PORT datad (825:825:825) (841:841:841)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1575:1575:1575)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (826:826:826) (815:815:815)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (554:554:554)) + (PORT datab (620:620:620) (640:640:640)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (774:774:774) (766:766:766)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1357:1357:1357)) + (PORT datab (576:576:576) (601:601:601)) + (PORT datac (745:745:745) (740:740:740)) + (PORT datad (782:782:782) (773:773:773)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (879:879:879) (907:907:907)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (239:239:239) (306:306:306)) + (PORT datac (214:214:214) (280:280:280)) + (PORT datad (215:215:215) (272:272:272)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (440:440:440)) + (PORT datab (238:238:238) (307:307:307)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (216:216:216) (273:273:273)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (555:555:555)) + (PORT datab (663:663:663) (702:702:702)) + (PORT datac (1057:1057:1057) (1060:1060:1060)) + (PORT datad (509:509:509) (501:501:501)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (769:769:769) (745:745:745)) + (PORT datab (785:785:785) (763:763:763)) + (PORT datac (590:590:590) (608:608:608)) + (PORT datad (721:721:721) (760:760:760)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (253:253:253)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datac (622:622:622) (653:653:653)) + (PORT datad (1076:1076:1076) (1044:1044:1044)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (867:867:867)) + (PORT datab (813:813:813) (809:809:809)) + (PORT datac (1005:1005:1005) (998:998:998)) + (PORT datad (1052:1052:1052) (1032:1032:1032)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (537:537:537)) + (PORT datab (1025:1025:1025) (1048:1048:1048)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (533:533:533) (510:510:510)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (358:358:358)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (617:617:617) (629:629:629)) + (PORT datad (525:525:525) (502:502:502)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1552:1552:1552)) + (PORT datab (384:384:384) (413:413:413)) + (PORT datad (720:720:720) (703:703:703)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1073:1073:1073) (1056:1056:1056)) + (PORT ena (1413:1413:1413) (1387:1387:1387)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (869:869:869) (870:870:870)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (641:641:641) (639:639:639)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (217:217:217)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1302:1302:1302) (1266:1266:1266)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (407:407:407)) + (PORT datab (767:767:767) (767:767:767)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (582:582:582) (584:584:584)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1419:1419:1419) (1407:1407:1407)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (650:650:650)) + (PORT datab (360:360:360) (405:405:405)) + (PORT datad (630:630:630) (637:637:637)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (328:328:328)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (526:526:526) (520:520:520)) + (PORT datad (739:739:739) (706:706:706)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1193:1193:1193) (1190:1190:1190)) + (PORT ena (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1195:1195:1195) (1192:1192:1192)) + (PORT ena (1357:1357:1357) (1322:1322:1322)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (894:894:894)) + (PORT datab (879:879:879) (905:905:905)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (354:354:354)) + (PORT datab (612:612:612) (609:609:609)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (832:832:832)) + (PORT datab (868:868:868) (875:875:875)) + (PORT datac (774:774:774) (754:754:754)) + (PORT datad (545:545:545) (535:535:535)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (614:614:614) (618:618:618)) + (PORT ena (1126:1126:1126) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1149:1149:1149)) + (PORT datab (892:892:892) (878:878:878)) + (PORT datad (605:605:605) (610:610:610)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (222:222:222) (292:292:292)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (617:617:617) (614:614:614)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (653:653:653)) + (PORT datab (594:594:594) (580:580:580)) + (PORT datac (201:201:201) (245:245:245)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datac (1089:1089:1089) (1087:1087:1087)) + (PORT datad (491:491:491) (480:480:480)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1353:1353:1353)) + (PORT ena (1588:1588:1588) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (323:323:323)) + (PORT datab (795:795:795) (786:786:786)) + (PORT datac (1018:1018:1018) (1036:1036:1036)) + (PORT datad (1272:1272:1272) (1246:1246:1246)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1151:1151:1151) (1144:1144:1144)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1153:1153:1153) (1146:1146:1146)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (912:912:912)) + (PORT datab (678:678:678) (684:684:684)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (746:746:746) (723:723:723)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1304:1304:1304) (1273:1273:1273)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (411:411:411)) + (PORT datab (380:380:380) (416:416:416)) + (PORT datad (363:363:363) (378:378:378)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1393:1393:1393) (1395:1395:1395)) + (PORT ena (1152:1152:1152) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT asdata (913:913:913) (925:925:925)) + (PORT ena (1395:1395:1395) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (855:855:855)) + (PORT datab (617:617:617) (641:641:641)) + (PORT datad (558:558:558) (580:580:580)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (891:891:891) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1557:1557:1557)) + (PORT datab (579:579:579) (591:591:591)) + (PORT datac (808:808:808) (822:822:822)) + (PORT datad (996:996:996) (968:968:968)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1353:1353:1353)) + (PORT asdata (1109:1109:1109) (1110:1110:1110)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (406:406:406)) + (PORT datab (648:648:648) (674:674:674)) + (PORT datad (583:583:583) (604:604:604)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (606:606:606)) + (PORT datab (556:556:556) (548:548:548)) + (PORT datac (534:534:534) (524:524:524)) + (PORT datad (562:562:562) (566:566:566)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1147:1147:1147) (1145:1145:1145)) + (PORT ena (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1148:1148:1148) (1147:1147:1147)) + (PORT ena (1357:1357:1357) (1322:1322:1322)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (897:897:897)) + (PORT datab (883:883:883) (908:908:908)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT asdata (911:911:911) (922:922:922)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1391:1391:1391) (1392:1392:1392)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (653:653:653)) + (PORT datab (393:393:393) (426:426:426)) + (PORT datad (631:631:631) (639:639:639)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (329:329:329)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (521:521:521) (511:511:511)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (827:827:827)) + (PORT datab (855:855:855) (860:860:860)) + (PORT datac (837:837:837) (841:841:841)) + (PORT datad (821:821:821) (808:808:808)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1354:1354:1354)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1092:1092:1092) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1117:1117:1117)) + (PORT datab (872:872:872) (883:883:883)) + (PORT datad (539:539:539) (530:530:530)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1105:1105:1105) (1066:1066:1066)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (589:589:589)) + (PORT datac (293:293:293) (300:300:300)) + (PORT datad (335:335:335) (370:370:370)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1285:1285:1285)) + (PORT datab (588:588:588) (621:621:621)) + (PORT datac (1017:1017:1017) (1035:1035:1035)) + (PORT datad (770:770:770) (752:752:752)) + (IOPATH dataa combout (299:299:299) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (425:425:425)) + (PORT datab (187:187:187) (225:225:225)) + (PORT datac (581:581:581) (590:590:590)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (259:259:259)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (601:601:601) (606:606:606)) + (PORT datad (565:565:565) (556:556:556)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (1114:1114:1114) (1111:1111:1111)) + (PORT datad (600:600:600) (592:592:592)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1353:1353:1353)) + (PORT ena (1588:1588:1588) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1142:1142:1142)) + (PORT datab (1133:1133:1133) (1142:1142:1142)) + (PORT datac (553:553:553) (572:572:572)) + (PORT datad (577:577:577) (573:573:573)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (622:622:622)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (598:598:598) (645:645:645)) + (PORT datad (505:505:505) (492:492:492)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1105:1105:1105) (1066:1066:1066)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1130:1130:1130) (1114:1114:1114)) + (PORT ena (1395:1395:1395) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1355:1355:1355)) + (PORT asdata (1128:1128:1128) (1113:1113:1113)) + (PORT ena (1365:1365:1365) (1327:1327:1327)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (917:917:917)) + (PORT datab (677:677:677) (679:679:679)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1137:1137:1137) (1122:1122:1122)) + (PORT ena (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1136:1136:1136) (1124:1124:1124)) + (PORT ena (1357:1357:1357) (1322:1322:1322)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (898:898:898)) + (PORT datab (883:883:883) (908:908:908)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1121:1121:1121) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1280:1280:1280)) + (PORT datab (595:595:595) (608:608:608)) + (PORT datac (193:193:193) (259:259:259)) + (PORT datad (712:712:712) (700:700:700)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1144:1144:1144) (1149:1149:1149)) + (PORT ena (1152:1152:1152) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT asdata (1109:1109:1109) (1107:1107:1107)) + (PORT ena (1395:1395:1395) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (851:851:851)) + (PORT datab (618:618:618) (637:637:637)) + (PORT datad (353:353:353) (389:389:389)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1076:1076:1076) (1041:1041:1041)) + (PORT ena (1080:1080:1080) (1041:1041:1041)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1275:1275:1275) (1234:1234:1234)) + (PORT ena (1373:1373:1373) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (426:426:426)) + (PORT datab (383:383:383) (419:419:419)) + (PORT datad (362:362:362) (380:380:380)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1277:1277:1277) (1235:1235:1235)) + (PORT ena (1413:1413:1413) (1387:1387:1387)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datad (865:865:865) (871:871:871)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1333:1333:1333) (1352:1352:1352)) + (PORT asdata (1110:1110:1110) (1109:1109:1109)) + (PORT ena (1131:1131:1131) (1102:1102:1102)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1353:1353:1353)) + (PORT asdata (1144:1144:1144) (1149:1149:1149)) + (PORT ena (1102:1102:1102) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (650:650:650)) + (PORT datab (362:362:362) (411:411:411)) + (PORT datad (628:628:628) (638:638:638)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (834:834:834) (843:843:843)) + (PORT datac (559:559:559) (552:552:552)) + (PORT datad (807:807:807) (797:797:797)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (567:567:567) (557:557:557)) + (PORT datac (569:569:569) (554:554:554)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (539:539:539)) + (PORT datab (779:779:779) (771:771:771)) + (PORT datac (1000:1000:1000) (1001:1001:1001)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1354:1354:1354)) + (PORT asdata (804:804:804) (789:789:789)) + (PORT ena (1092:1092:1092) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1111:1111:1111)) + (PORT datab (854:854:854) (876:876:876)) + (PORT datad (542:542:542) (535:535:535)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (297:297:297)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datad (556:556:556) (553:553:553)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (998:998:998) (960:960:960)) + (PORT datac (600:600:600) (606:606:606)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT datac (1235:1235:1235) (1207:1207:1207)) + (PORT datad (1712:1712:1712) (1687:1687:1687)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (660:660:660) (656:656:656)) + (PORT clrn (1378:1378:1378) (1351:1351:1351)) + (PORT ena (1574:1574:1574) (1532:1532:1532)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (610:610:610)) + (PORT datab (856:856:856) (873:873:873)) + (PORT datac (577:577:577) (587:587:587)) + (PORT datad (964:964:964) (931:931:931)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1104:1104:1104) (1115:1115:1115)) + (PORT datac (341:341:341) (345:345:345)) + (PORT datad (338:338:338) (359:359:359)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1116:1116:1116) (1117:1117:1117)) + (PORT ena (1358:1358:1358) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1121:1121:1121) (1129:1129:1129)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1120:1120:1120) (1127:1127:1127)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (809:809:809)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (777:777:777) (761:761:761)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1095:1095:1095) (1089:1089:1089)) + (PORT ena (914:914:914) (918:918:918)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1095:1095:1095) (1089:1089:1089)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1108:1108:1108)) + (PORT datab (539:539:539) (545:545:545)) + (PORT datad (1052:1052:1052) (1060:1060:1060)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (762:762:762)) + (PORT datab (218:218:218) (262:262:262)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (894:894:894) (888:888:888)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (896:896:896) (890:890:890)) + (PORT ena (1600:1600:1600) (1568:1568:1568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (424:424:424) (437:437:437)) + (PORT datad (1081:1081:1081) (1088:1088:1088)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (915:915:915) (916:916:916)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (912:912:912) (915:915:915)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (890:890:890)) + (PORT datab (839:839:839) (824:824:824)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1572:1572:1572) (1573:1573:1573)) + (PORT ena (1152:1152:1152) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1091:1091:1091) (1117:1117:1117)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1109:1109:1109) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (673:673:673)) + (PORT datab (622:622:622) (629:629:629)) + (PORT datad (375:375:375) (416:416:416)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1117:1117:1117) (1118:1118:1118)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (821:821:821)) + (PORT datab (1150:1150:1150) (1142:1142:1142)) + (PORT datad (795:795:795) (788:788:788)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (364:364:364)) + (PORT datab (590:590:590) (610:610:610)) + (PORT datac (315:315:315) (338:338:338)) + (PORT datad (560:560:560) (562:562:562)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (230:230:230)) + (PORT datab (612:612:612) (658:658:658)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (649:649:649)) + (PORT datab (214:214:214) (256:256:256)) + (PORT datac (349:349:349) (358:358:358)) + (PORT datad (577:577:577) (573:573:573)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (837:837:837)) + (PORT datab (572:572:572) (595:595:595)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1128:1128:1128)) + (PORT datab (237:237:237) (291:291:291)) + (PORT datac (534:534:534) (512:512:512)) + (PORT datad (823:823:823) (838:838:838)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (367:367:367)) + (PORT datac (1292:1292:1292) (1300:1300:1300)) + (PORT datad (556:556:556) (554:554:554)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1279:1279:1279) (1278:1278:1278)) + (PORT datac (339:339:339) (350:350:350)) + (PORT datad (1405:1405:1405) (1425:1425:1425)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (584:584:584)) + (PORT datac (597:597:597) (620:620:620)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (881:881:881)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (617:617:617) (626:626:626)) + (PORT datad (212:212:212) (254:254:254)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (677:677:677)) + (PORT datab (1102:1102:1102) (1113:1113:1113)) + (PORT datac (2574:2574:2574) (2569:2569:2569)) + (PORT datad (753:753:753) (727:727:727)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1436:1436:1436)) + (PORT datab (889:889:889) (914:914:914)) + (PORT datac (2571:2571:2571) (2565:2565:2565)) + (PORT datad (1109:1109:1109) (1126:1126:1126)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~3) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1368:1368:1368) (1400:1400:1400)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (374:374:374)) + (PORT datac (1292:1292:1292) (1300:1300:1300)) + (PORT datad (704:704:704) (680:680:680)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (363:363:363) (371:371:371)) + (PORT datac (1253:1253:1253) (1248:1248:1248)) + (PORT datad (1405:1405:1405) (1424:1424:1424)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (774:774:774)) + (PORT datab (838:838:838) (832:832:832)) + (PORT datac (365:365:365) (410:410:410)) + (PORT datad (342:342:342) (381:381:381)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (806:806:806)) + (PORT datac (558:558:558) (555:555:555)) + (PORT datad (336:336:336) (340:340:340)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (825:825:825)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (543:543:543) (531:531:531)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT asdata (868:868:868) (858:858:858)) + (PORT ena (1540:1540:1540) (1565:1565:1565)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (318:318:318)) + (PORT datab (244:244:244) (305:305:305)) + (PORT datac (1174:1174:1174) (1153:1153:1153)) + (PORT datad (222:222:222) (255:255:255)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (876:876:876)) + (PORT datab (1592:1592:1592) (1575:1575:1575)) + (PORT datac (1232:1232:1232) (1299:1299:1299)) + (PORT datad (344:344:344) (385:385:385)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (863:863:863)) + (PORT datab (567:567:567) (585:585:585)) + (PORT datac (736:736:736) (769:769:769)) + (PORT datad (742:742:742) (718:718:718)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (587:587:587) (598:598:598)) + (PORT datac (593:593:593) (613:613:613)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (984:984:984)) + (PORT datab (841:841:841) (839:839:839)) + (PORT datac (1080:1080:1080) (1105:1105:1105)) + (PORT datad (752:752:752) (744:744:744)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (216:216:216)) + (PORT datac (1044:1044:1044) (1053:1053:1053)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (447:447:447)) + (PORT datab (1584:1584:1584) (1566:1566:1566)) + (PORT datac (616:616:616) (646:646:646)) + (PORT datad (1412:1412:1412) (1459:1459:1459)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (363:363:363)) + (PORT datac (1291:1291:1291) (1299:1299:1299)) + (PORT datad (300:300:300) (303:303:303)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1157:1157:1157)) + (PORT datab (1062:1062:1062) (1061:1061:1061)) + (PORT datac (315:315:315) (323:323:323)) + (PORT datad (558:558:558) (550:550:550)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (324:324:324)) + (PORT datab (250:250:250) (314:314:314)) + (PORT datad (224:224:224) (259:259:259)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (577:577:577)) + (PORT datab (316:316:316) (327:327:327)) + (PORT datac (1217:1217:1217) (1219:1219:1219)) + (PORT datad (760:760:760) (755:755:755)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (607:607:607)) + (PORT datab (866:866:866) (887:887:887)) + (PORT datac (555:555:555) (552:552:552)) + (PORT datad (582:582:582) (596:596:596)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (407:407:407)) + (PORT datab (809:809:809) (889:889:889)) + (PORT datac (841:841:841) (877:877:877)) + (PORT datad (604:604:604) (617:617:617)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (889:889:889)) + (PORT datab (235:235:235) (290:290:290)) + (PORT datac (751:751:751) (741:741:741)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1085:1085:1085)) + (PORT datac (1069:1069:1069) (1099:1099:1099)) + (PORT datad (825:825:825) (812:812:812)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (819:819:819)) + (PORT datab (829:829:829) (808:808:808)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1548:1548:1548) (1538:1538:1538)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (625:625:625) (649:649:649)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (770:770:770) (765:765:765)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (825:825:825)) + (PORT datab (601:601:601) (610:610:610)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (766:766:766) (749:749:749)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1047:1047:1047)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (769:769:769)) + (PORT datab (386:386:386) (427:427:427)) + (PORT datac (331:331:331) (382:382:382)) + (PORT datad (811:811:811) (797:797:797)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1268:1268:1268)) + (PORT datab (658:658:658) (711:711:711)) + (PORT datac (592:592:592) (637:637:637)) + (PORT datad (801:801:801) (780:780:780)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datab (615:615:615) (615:615:615)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (1026:1026:1026)) + (PORT datab (655:655:655) (706:706:706)) + (PORT datac (594:594:594) (640:640:640)) + (PORT datad (580:580:580) (582:582:582)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (259:259:259)) + (PORT datab (188:188:188) (222:222:222)) + (PORT datac (765:765:765) (771:771:771)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT datac (553:553:553) (547:547:547)) + (PORT datad (369:369:369) (406:406:406)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (334:334:334)) + (PORT datab (909:909:909) (927:927:927)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (886:886:886)) + (PORT datab (564:564:564) (556:556:556)) + (PORT datac (991:991:991) (983:983:983)) + (PORT datad (509:509:509) (499:499:499)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (621:621:621) (655:655:655)) + (PORT datad (1008:1008:1008) (1058:1058:1058)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1035:1035:1035)) + (PORT datab (816:816:816) (806:806:806)) + (PORT datac (798:798:798) (824:824:824)) + (PORT datad (1052:1052:1052) (1026:1026:1026)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (355:355:355)) + (PORT datab (648:648:648) (657:657:657)) + (PORT datac (572:572:572) (576:576:576)) + (PORT datad (320:320:320) (321:321:321)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (579:579:579)) + (PORT datab (350:350:350) (370:370:370)) + (PORT datac (505:505:505) (489:489:489)) + (PORT datad (304:304:304) (312:312:312)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (977:977:977)) + (PORT datab (248:248:248) (322:322:322)) + (PORT datac (1151:1151:1151) (1153:1153:1153)) + (PORT datad (547:547:547) (545:545:545)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (680:680:680)) + (PORT datab (579:579:579) (596:596:596)) + (PORT datac (2050:2050:2050) (2021:2021:2021)) + (PORT datad (581:581:581) (586:586:586)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1400:1400:1400)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (788:788:788) (775:775:775)) + (PORT datad (970:970:970) (933:933:933)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (811:811:811)) + (PORT datab (1061:1061:1061) (1056:1056:1056)) + (PORT datac (2050:2050:2050) (2025:2025:2025)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (679:679:679)) + (PORT datab (619:619:619) (621:621:621)) + (PORT datac (551:551:551) (568:568:568)) + (PORT datad (1415:1415:1415) (1357:1357:1357)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1687:1687:1687) (1756:1756:1756)) + (PORT datab (1766:1766:1766) (1825:1825:1825)) + (PORT datad (171:171:171) (198:198:198)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (479:479:479)) + (PORT datac (1053:1053:1053) (1076:1076:1076)) + (PORT datad (1206:1206:1206) (1286:1286:1286)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2114:2114:2114) (2060:2060:2060)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (326:326:326)) + (PORT datab (588:588:588) (622:622:622)) + (PORT datac (614:614:614) (646:646:646)) + (PORT datad (350:350:350) (390:390:390)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (411:411:411)) + (PORT datab (592:592:592) (610:610:610)) + (PORT datac (530:530:530) (553:553:553)) + (PORT datad (377:377:377) (418:418:418)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (608:608:608)) + (PORT datab (648:648:648) (685:685:685)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (756:756:756) (762:762:762)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (706:706:706)) + (PORT datab (646:646:646) (691:691:691)) + (PORT datac (611:611:611) (657:657:657)) + (PORT datad (594:594:594) (635:635:635)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (592:592:592)) + (PORT datab (815:815:815) (812:812:812)) + (PORT datac (1000:1000:1000) (990:990:990)) + (PORT datad (556:556:556) (566:566:566)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1255:1255:1255)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (832:832:832) (839:839:839)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (808:808:808)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (201:201:201) (271:271:271)) + (PORT datad (386:386:386) (420:420:420)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1059:1059:1059) (1055:1055:1055)) + (PORT datac (2053:2053:2053) (2027:2027:2027)) + (PORT datad (386:386:386) (421:421:421)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (335:335:335) (354:354:354)) + (PORT datac (557:557:557) (553:553:553)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1295:1295:1295) (1315:1315:1315)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (327:327:327)) + (PORT datad (713:713:713) (745:745:745)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (808:808:808)) + (PORT datab (1059:1059:1059) (1054:1054:1054)) + (PORT datac (550:550:550) (565:565:565)) + (PORT datad (595:595:595) (633:633:633)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1395:1395:1395)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (2053:2053:2053) (2027:2027:2027)) + (PORT datad (584:584:584) (588:588:588)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (536:536:536) (540:540:540)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (798:798:798) (832:832:832)) + (PORT datac (518:518:518) (515:515:515)) + (PORT datad (973:973:973) (944:944:944)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (930:930:930)) + (PORT datab (221:221:221) (264:264:264)) + (PORT datac (1283:1283:1283) (1303:1303:1303)) + (PORT datad (909:909:909) (952:952:952)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT datab (1390:1390:1390) (1433:1433:1433)) + (PORT datac (1265:1265:1265) (1316:1316:1316)) + (PORT datad (1126:1126:1126) (1160:1160:1160)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (966:966:966)) + (PORT datab (784:784:784) (760:760:760)) + (PORT datac (1005:1005:1005) (968:968:968)) + (PORT datad (798:798:798) (793:793:793)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (827:827:827) (841:841:841)) + (PORT datad (543:543:543) (542:542:542)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (238:238:238)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (193:193:193) (224:224:224)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_3) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (420:420:420)) + (PORT datab (315:315:315) (335:335:335)) + (PORT datac (315:315:315) (323:323:323)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1062:1062:1062)) + (PORT datab (812:812:812) (798:798:798)) + (PORT datac (1642:1642:1642) (1668:1668:1668)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1224:1224:1224)) + (PORT datab (772:772:772) (777:777:777)) + (PORT datac (921:921:921) (947:947:947)) + (PORT datad (1012:1012:1012) (1027:1027:1027)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (970:970:970)) + (PORT datab (815:815:815) (868:868:868)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (337:337:337) (351:351:351)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1527:1527:1527)) + (PORT datab (248:248:248) (323:323:323)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1919:1919:1919) (1988:1988:1988)) + (PORT datab (859:859:859) (912:912:912)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~28) + (DELAY + (ABSOLUTE + (PORT dataa (2049:2049:2049) (2115:2115:2115)) + (PORT datab (705:705:705) (764:764:764)) + (PORT datac (1582:1582:1582) (1588:1588:1588)) + (PORT datad (1663:1663:1663) (1709:1709:1709)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (846:846:846)) + (PORT datab (1062:1062:1062) (1087:1087:1087)) + (PORT datac (1126:1126:1126) (1140:1140:1140)) + (PORT datad (307:307:307) (308:308:308)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1113:1113:1113)) + (PORT datab (1082:1082:1082) (1066:1066:1066)) + (PORT datad (574:574:574) (591:591:591)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (384:384:384)) + (PORT datab (892:892:892) (918:918:918)) + (PORT datac (991:991:991) (989:989:989)) + (PORT datad (186:186:186) (211:211:211)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (285:285:285)) + (PORT datab (1319:1319:1319) (1324:1324:1324)) + (PORT datac (1389:1389:1389) (1408:1408:1408)) + (PORT datad (1016:1016:1016) (1023:1023:1023)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1082:1082:1082) (1098:1098:1098)) + (PORT datac (1051:1051:1051) (1052:1052:1052)) + (PORT datad (971:971:971) (962:962:962)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~23) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (772:772:772)) + (PORT datab (911:911:911) (971:971:971)) + (PORT datac (330:330:330) (348:348:348)) + (PORT datad (358:358:358) (368:368:368)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (624:624:624)) + (PORT datab (805:805:805) (814:814:814)) + (PORT datac (164:164:164) (197:197:197)) + (PORT datad (864:864:864) (876:876:876)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~21) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (876:876:876) (884:884:884)) + (PORT datac (525:525:525) (527:527:527)) + (PORT datad (555:555:555) (563:563:563)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1070:1070:1070)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (803:803:803) (791:791:791)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (886:886:886) (883:883:883)) + (PORT datac (331:331:331) (348:348:348)) + (PORT datad (598:598:598) (613:613:613)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (659:659:659) (658:658:658)) + (PORT ena (1542:1542:1542) (1491:1491:1491)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1118:1118:1118)) + (PORT datab (370:370:370) (400:400:400)) + (PORT datad (1163:1163:1163) (1229:1229:1229)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1054:1054:1054) (1043:1043:1043)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (303:303:303) (312:312:312)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (219:219:219) (288:288:288)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (1104:1104:1104) (1113:1113:1113)) + (PORT datac (329:329:329) (334:334:334)) + (PORT datad (339:339:339) (354:354:354)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (812:812:812) (814:814:814)) + (PORT datad (303:303:303) (304:304:304)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1347:1347:1347)) + (PORT ena (1819:1819:1819) (1765:1765:1765)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (798:798:798)) + (PORT datab (992:992:992) (966:966:966)) + (PORT datac (212:212:212) (285:285:285)) + (PORT datad (170:170:170) (196:196:196)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (700:700:700)) + (PORT datab (1291:1291:1291) (1295:1295:1295)) + (PORT datac (583:583:583) (592:592:592)) + (PORT datad (1375:1375:1375) (1345:1345:1345)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (604:604:604)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (674:674:674) (706:706:706)) + (PORT datad (547:547:547) (554:554:554)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (890:890:890) (890:890:890)) + (PORT ena (1807:1807:1807) (1744:1744:1744)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1223:1223:1223)) + (PORT datab (645:645:645) (667:667:667)) + (PORT datad (1253:1253:1253) (1215:1215:1215)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1523:1523:1523) (1472:1472:1472)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (359:359:359)) + (PORT datab (219:219:219) (288:288:288)) + (PORT datac (1025:1025:1025) (1013:1013:1013)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (529:529:529)) + (PORT datab (1108:1108:1108) (1119:1119:1119)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (337:337:337) (353:353:353)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1088:1088:1088) (1084:1084:1084)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1071:1071:1071)) + (PORT datab (593:593:593) (610:610:610)) + (PORT datad (334:334:334) (337:337:337)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (824:824:824) (813:813:813)) + (PORT ena (914:914:914) (918:918:918)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (823:823:823) (811:811:811)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (219:219:219) (265:265:265)) + (PORT datad (518:518:518) (499:499:499)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1085:1085:1085) (1111:1111:1111)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1054:1054:1054) (1017:1017:1017)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT asdata (1145:1145:1145) (1165:1165:1165)) + (PORT ena (1283:1283:1283) (1249:1249:1249)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (802:802:802)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datad (775:775:775) (754:754:754)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1600:1600:1600) (1568:1568:1568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (828:828:828) (818:818:818)) + (PORT ena (883:883:883) (868:868:868)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (421:421:421) (440:440:440)) + (PORT datad (1078:1078:1078) (1091:1091:1091)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1587:1587:1587) (1615:1615:1615)) + (PORT ena (1293:1293:1293) (1263:1263:1263)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (1585:1585:1585) (1612:1612:1612)) + (PORT ena (1328:1328:1328) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (898:898:898)) + (PORT datab (845:845:845) (832:832:832)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT asdata (1866:1866:1866) (1887:1887:1887)) + (PORT ena (1286:1286:1286) (1235:1235:1235)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (813:813:813)) + (PORT datab (1151:1151:1151) (1151:1151:1151)) + (PORT datad (512:512:512) (495:495:495)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (623:623:623) (629:629:629)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (620:620:620) (625:625:625)) + (PORT ena (739:739:739) (742:742:742)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (209:209:209) (246:246:246)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (360:360:360)) + (PORT datab (806:806:806) (789:789:789)) + (PORT datac (715:715:715) (706:706:706)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (605:605:605)) + (PORT datab (518:518:518) (496:496:496)) + (PORT datac (957:957:957) (995:995:995)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (572:572:572)) + (PORT datab (592:592:592) (620:620:620)) + (PORT datac (626:626:626) (636:636:636)) + (PORT datad (315:315:315) (317:317:317)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (914:914:914)) + (PORT datab (842:842:842) (873:873:873)) + (PORT datac (555:555:555) (542:542:542)) + (PORT datad (604:604:604) (613:613:613)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1020:1020:1020) (1033:1033:1033)) + (PORT datab (236:236:236) (289:289:289)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (827:827:827) (841:841:841)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (371:371:371)) + (PORT datab (341:341:341) (365:365:365)) + (PORT datac (1288:1288:1288) (1303:1303:1303)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (399:399:399)) + (PORT datab (1280:1280:1280) (1276:1276:1276)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1406:1406:1406) (1425:1425:1425)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (447:447:447)) + (PORT datab (1595:1595:1595) (1579:1579:1579)) + (PORT datac (1239:1239:1239) (1304:1304:1304)) + (PORT datad (1041:1041:1041) (1056:1056:1056)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (863:863:863)) + (PORT datab (568:568:568) (572:572:572)) + (PORT datac (1222:1222:1222) (1228:1228:1228)) + (PORT datad (799:799:799) (807:807:807)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (819:819:819)) + (PORT datab (365:365:365) (380:380:380)) + (PORT datac (837:837:837) (860:860:860)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (630:630:630)) + (PORT datab (602:602:602) (604:604:604)) + (PORT datac (559:559:559) (564:564:564)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1276:1276:1276)) + (PORT datab (1109:1109:1109) (1133:1133:1133)) + (PORT datac (807:807:807) (779:779:779)) + (PORT datad (759:759:759) (745:745:745)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datac (1038:1038:1038) (1044:1044:1044)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (438:438:438)) + (PORT datab (838:838:838) (832:832:832)) + (PORT datac (754:754:754) (739:739:739)) + (PORT datad (351:351:351) (393:393:393)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (993:993:993) (1046:1046:1046)) + (PORT datac (799:799:799) (826:826:826)) + (PORT datad (1041:1041:1041) (1056:1056:1056)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (581:581:581)) + (PORT datab (364:364:364) (378:378:378)) + (PORT datac (768:768:768) (772:772:772)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (766:766:766)) + (PORT datab (185:185:185) (219:219:219)) + (PORT datac (190:190:190) (232:232:232)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (257:257:257)) + (PORT datab (615:615:615) (612:612:612)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1331:1331:1331)) + (PORT datab (386:386:386) (427:427:427)) + (PORT datac (1561:1561:1561) (1546:1546:1546)) + (PORT datad (813:813:813) (825:825:825)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (318:318:318)) + (PORT datab (236:236:236) (299:299:299)) + (PORT datad (223:223:223) (257:257:257)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (398:398:398)) + (PORT datac (1288:1288:1288) (1303:1303:1303)) + (PORT datad (703:703:703) (682:682:682)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (376:376:376)) + (PORT datab (1442:1442:1442) (1454:1454:1454)) + (PORT datac (1254:1254:1254) (1248:1248:1248)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (753:753:753)) + (PORT datab (1286:1286:1286) (1272:1272:1272)) + (PORT datac (806:806:806) (786:786:786)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (355:355:355)) + (PORT datab (1083:1083:1083) (1104:1104:1104)) + (PORT datac (557:557:557) (563:563:563)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (954:954:954)) + (PORT datab (393:393:393) (443:443:443)) + (PORT datac (1199:1199:1199) (1181:1181:1181)) + (PORT datad (199:199:199) (230:230:230)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (917:917:917) (905:905:905)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (1108:1108:1108) (1076:1076:1076)) + (PORT datac (619:619:619) (651:651:651)) + (PORT datad (630:630:630) (670:670:670)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (862:862:862)) + (PORT datab (1081:1081:1081) (1063:1063:1063)) + (PORT datac (784:784:784) (773:773:773)) + (PORT datad (778:778:778) (769:769:769)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (334:334:334)) + (PORT datab (646:646:646) (662:662:662)) + (PORT datac (593:593:593) (602:602:602)) + (PORT datad (319:319:319) (322:322:322)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (225:225:225)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (535:535:535) (526:526:526)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1321:1321:1321)) + (PORT datac (212:212:212) (263:263:263)) + (PORT datad (1338:1338:1338) (1391:1391:1391)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (959:959:959)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (575:575:575) (574:574:574)) + (PORT datad (850:850:850) (856:856:856)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1320:1320:1320)) + (PORT datab (1347:1347:1347) (1336:1336:1336)) + (PORT datac (1270:1270:1270) (1327:1327:1327)) + (PORT datad (755:755:755) (723:723:723)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1386:1386:1386)) + (PORT datab (1203:1203:1203) (1260:1260:1260)) + (PORT datac (1875:1875:1875) (1909:1909:1909)) + (PORT datad (785:785:785) (768:768:768)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1116:1116:1116)) + (PORT datab (1057:1057:1057) (1074:1074:1074)) + (PORT datac (1105:1105:1105) (1173:1173:1173)) + (PORT datad (2152:2152:2152) (2184:2184:2184)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1153:1153:1153)) + (PORT datab (1335:1335:1335) (1359:1359:1359)) + (PORT datac (801:801:801) (817:817:817)) + (PORT datad (634:634:634) (671:671:671)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1630:1630:1630)) + (PORT datab (1162:1162:1162) (1179:1179:1179)) + (PORT datac (918:918:918) (994:994:994)) + (PORT datad (920:920:920) (973:973:973)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (558:558:558)) + (PORT datab (549:549:549) (537:537:537)) + (PORT datac (1248:1248:1248) (1257:1257:1257)) + (PORT datad (1475:1475:1475) (1488:1488:1488)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~38) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (991:991:991)) + (PORT datab (595:595:595) (631:631:631)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (918:918:918) (981:981:981)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (615:615:615)) + (PORT datab (346:346:346) (354:354:354)) + (PORT datac (576:576:576) (599:599:599)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (388:388:388)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (526:526:526) (519:519:519)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (634:634:634)) + (PORT datab (360:360:360) (366:366:366)) + (PORT datac (1078:1078:1078) (1065:1065:1065)) + (PORT datad (574:574:574) (576:576:576)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1434:1434:1434)) + (PORT datab (1235:1235:1235) (1259:1259:1259)) + (PORT datac (790:790:790) (797:797:797)) + (PORT datad (1091:1091:1091) (1075:1075:1075)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (799:799:799)) + (PORT datab (645:645:645) (667:667:667)) + (PORT datac (1075:1075:1075) (1103:1103:1103)) + (PORT datad (829:829:829) (819:819:819)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (950:950:950)) + (PORT datac (890:890:890) (949:949:949)) + (PORT datad (914:914:914) (975:975:975)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (658:658:658)) + (PORT datac (1893:1893:1893) (1900:1900:1900)) + (PORT datad (827:827:827) (818:818:818)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (799:799:799)) + (PORT datab (998:998:998) (1050:1050:1050)) + (PORT datac (1169:1169:1169) (1160:1160:1160)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1021:1021:1021)) + (PORT datab (820:820:820) (820:820:820)) + (PORT datac (1160:1160:1160) (1169:1169:1169)) + (PORT datad (1451:1451:1451) (1439:1439:1439)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (822:822:822) (807:807:807)) + (PORT datad (522:522:522) (524:524:524)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (818:818:818)) + (PORT datab (812:812:812) (802:802:802)) + (PORT datac (595:595:595) (625:625:625)) + (PORT datad (829:829:829) (816:816:816)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (579:579:579)) + (PORT datab (357:357:357) (368:368:368)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (603:603:603) (616:616:616)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1033:1033:1033) (1027:1027:1027)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (573:573:573)) + (PORT datab (585:585:585) (619:619:619)) + (PORT datac (1013:1013:1013) (998:998:998)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1064:1064:1064)) + (PORT datab (609:609:609) (649:649:649)) + (PORT datac (592:592:592) (614:614:614)) + (PORT datad (1309:1309:1309) (1277:1277:1277)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (254:254:254)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (1309:1309:1309) (1333:1333:1333)) + (PORT datad (1046:1046:1046) (1019:1019:1019)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (859:859:859)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (556:556:556) (577:577:577)) + (PORT datad (539:539:539) (525:525:525)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (658:658:658)) + (PORT datab (1128:1128:1128) (1132:1132:1132)) + (PORT datac (1040:1040:1040) (1037:1037:1037)) + (PORT datad (580:580:580) (587:587:587)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (610:610:610)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (1078:1078:1078) (1108:1108:1108)) + (PORT datad (827:827:827) (815:815:815)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (570:570:570)) + (PORT datab (805:805:805) (814:814:814)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (864:864:864) (876:876:876)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (825:825:825)) + (PORT datab (2012:2012:2012) (2088:2088:2088)) + (PORT datac (1443:1443:1443) (1561:1561:1561)) + (PORT datad (1757:1757:1757) (1808:1808:1808)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (1472:1472:1472) (1587:1587:1587)) + (PORT datac (1066:1066:1066) (1041:1041:1041)) + (PORT datad (168:168:168) (193:193:193)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1461:1461:1461) (1550:1550:1550)) + (PORT datac (1180:1180:1180) (1226:1226:1226)) + (PORT datad (1462:1462:1462) (1513:1513:1513)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1385:1385:1385) (1374:1374:1374)) + (PORT datab (1102:1102:1102) (1116:1116:1116)) + (PORT datac (814:814:814) (827:827:827)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1805:1805:1805) (1850:1850:1850)) + (PORT datab (884:884:884) (880:880:880)) + (PORT datac (1476:1476:1476) (1475:1475:1475)) + (PORT datad (849:849:849) (870:870:870)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1092:1092:1092)) + (PORT datac (1184:1184:1184) (1231:1231:1231)) + (PORT datad (1437:1437:1437) (1517:1517:1517)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1299:1299:1299)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (340:340:340)) + (PORT datab (896:896:896) (937:937:937)) + (PORT datac (620:620:620) (658:658:658)) + (PORT datad (1574:1574:1574) (1602:1602:1602)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1459:1459:1459)) + (PORT datab (615:615:615) (613:613:613)) + (PORT datac (1004:1004:1004) (1002:1002:1002)) + (PORT datad (1019:1019:1019) (1017:1017:1017)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1009:1009:1009)) + (PORT datab (1036:1036:1036) (1019:1019:1019)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1240:1240:1240) (1218:1218:1218)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (1439:1439:1439) (1455:1455:1455)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (506:506:506) (568:568:568)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (1439:1439:1439) (1455:1455:1455)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (264:264:264)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (1467:1467:1467) (1487:1487:1487)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1367:1367:1367)) + (PORT asdata (513:513:513) (580:580:580)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (1467:1467:1467) (1487:1487:1487)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (303:303:303)) + (PORT datad (204:204:204) (263:263:263)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (859:859:859)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (826:826:826) (839:839:839)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (227:227:227)) + (PORT datab (786:786:786) (782:782:782)) + (PORT datac (1588:1588:1588) (1562:1562:1562)) + (PORT datad (1122:1122:1122) (1118:1118:1118)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1810:1810:1810) (1778:1778:1778)) + (PORT datab (1320:1320:1320) (1332:1332:1332)) + (PORT datac (1705:1705:1705) (1681:1681:1681)) + (PORT datad (804:804:804) (781:781:781)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (581:581:581)) + (PORT datab (605:605:605) (615:615:615)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (586:586:586) (579:579:579)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (176:176:176) (208:208:208)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (952:952:952)) + (PORT datab (577:577:577) (564:564:564)) + (PORT datac (1600:1600:1600) (1617:1617:1617)) + (PORT datad (548:548:548) (544:544:544)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (241:241:241)) + (PORT datab (1038:1038:1038) (1018:1018:1018)) + (PORT datac (526:526:526) (515:515:515)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (1364:1364:1364) (1340:1340:1340)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1357:1357:1357)) + (PORT asdata (1207:1207:1207) (1233:1233:1233)) + (PORT clrn (1383:1383:1383) (1356:1356:1356)) + (PORT ena (1123:1123:1123) (1109:1109:1109)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT asdata (872:872:872) (901:901:901)) + (PORT clrn (1375:1375:1375) (1348:1348:1348)) + (PORT ena (1445:1445:1445) (1437:1437:1437)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1086:1086:1086)) + (PORT datac (1047:1047:1047) (1087:1087:1087)) + (PORT datad (202:202:202) (261:261:261)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (1566:1566:1566) (1607:1607:1607)) + (PORT datad (1788:1788:1788) (1903:1903:1903)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1969:1969:1969) (2040:2040:2040)) + (PORT datab (971:971:971) (1036:1036:1036)) + (PORT datac (905:905:905) (953:953:953)) + (PORT datad (1348:1348:1348) (1389:1389:1389)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1490:1490:1490)) + (PORT datad (1442:1442:1442) (1477:1477:1477)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (242:242:242)) + (PORT datab (758:758:758) (743:743:743)) + (PORT datac (991:991:991) (955:955:955)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (800:800:800)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (588:588:588) (597:597:597)) + (PORT datad (550:550:550) (553:553:553)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1494:1494:1494)) + (PORT datab (534:534:534) (534:534:534)) + (PORT datac (761:761:761) (753:753:753)) + (PORT datad (1074:1074:1074) (1074:1074:1074)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (614:614:614)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (590:590:590) (602:602:602)) + (PORT datad (865:865:865) (914:914:914)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1122:1122:1122)) + (PORT datab (1080:1080:1080) (1059:1059:1059)) + (PORT datac (1039:1039:1039) (1037:1037:1037)) + (PORT datad (532:532:532) (524:524:524)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1462:1462:1462)) + (PORT datab (987:987:987) (971:971:971)) + (PORT datac (1179:1179:1179) (1252:1252:1252)) + (PORT datad (1057:1057:1057) (1056:1056:1056)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (736:736:736)) + (PORT datab (1380:1380:1380) (1406:1406:1406)) + (PORT datac (826:826:826) (844:844:844)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (666:666:666)) + (PORT datab (1104:1104:1104) (1097:1097:1097)) + (PORT datac (525:525:525) (524:524:524)) + (PORT datad (1130:1130:1130) (1139:1139:1139)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1969:1969:1969) (2039:2039:2039)) + (PORT datab (1295:1295:1295) (1270:1270:1270)) + (PORT datac (972:972:972) (954:954:954)) + (PORT datad (892:892:892) (942:942:942)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (836:836:836)) + (PORT datab (1156:1156:1156) (1151:1151:1151)) + (PORT datac (563:563:563) (562:562:562)) + (PORT datad (727:727:727) (713:713:713)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1368:1368:1368) (1424:1424:1424)) + (PORT datac (901:901:901) (949:949:949)) + (PORT datad (1920:1920:1920) (1991:1991:1991)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1255:1255:1255)) + (PORT datab (253:253:253) (334:334:334)) + (PORT datac (1079:1079:1079) (1061:1061:1061)) + (PORT datad (1082:1082:1082) (1090:1090:1090)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1130:1130:1130) (1096:1096:1096)) + (PORT datac (998:998:998) (1004:1004:1004)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1127:1127:1127)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (559:559:559) (566:566:566)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1655:1655:1655)) + (PORT datab (889:889:889) (904:904:904)) + (PORT datac (561:561:561) (554:554:554)) + (PORT datad (1404:1404:1404) (1413:1413:1413)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (354:354:354)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (529:529:529)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (976:976:976) (954:954:954)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1499:1499:1499)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (732:732:732) (779:779:779)) + (PORT datad (1698:1698:1698) (1719:1719:1719)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (630:630:630)) + (PORT datab (353:353:353) (351:351:351)) + (PORT datac (991:991:991) (984:984:984)) + (PORT datad (776:776:776) (775:775:775)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1087:1087:1087)) + (PORT datab (2352:2352:2352) (2351:2351:2351)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1242:1242:1242) (1223:1223:1223)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1071:1071:1071)) + (PORT datab (1074:1074:1074) (1063:1063:1063)) + (PORT datac (1125:1125:1125) (1184:1184:1184)) + (PORT datad (1118:1118:1118) (1139:1139:1139)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (512:512:512) (578:578:578)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1053:1053:1053) (1066:1066:1066)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1353:1353:1353)) + (PORT asdata (654:654:654) (690:690:690)) + (PORT clrn (1375:1375:1375) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (413:413:413)) + (PORT datad (1161:1161:1161) (1191:1191:1191)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1149:1149:1149)) + (PORT datab (1072:1072:1072) (1065:1065:1065)) + (PORT datac (1124:1124:1124) (1186:1186:1186)) + (PORT datad (1512:1512:1512) (1477:1477:1477)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (833:833:833)) + (PORT datac (875:875:875) (879:879:879)) + (PORT datad (1110:1110:1110) (1123:1123:1123)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (499:499:499)) + (PORT datab (511:511:511) (513:513:513)) + (PORT datad (799:799:799) (809:809:809)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31064,11 +31620,11 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (1276:1276:1276) (1394:1394:1394)) - (PORT datac (1230:1230:1230) (1303:1303:1303)) - (PORT datad (2345:2345:2345) (2358:2358:2358)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1405:1405:1405) (1428:1428:1428)) + (PORT datab (867:867:867) (900:900:900)) + (PORT datad (1396:1396:1396) (1398:1398:1398)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31078,10 +31634,10 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1058:1058:1058) (1025:1025:1025)) - (PORT datab (864:864:864) (872:872:872)) - (PORT datac (761:761:761) (760:760:760)) - (PORT datad (1529:1529:1529) (1635:1635:1635)) + (PORT dataa (809:809:809) (820:820:820)) + (PORT datab (2012:2012:2012) (2091:2091:2091)) + (PORT datac (1063:1063:1063) (1035:1035:1035)) + (PORT datad (757:757:757) (730:730:730)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -31094,12 +31650,12 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1766:1766:1766) (1849:1849:1849)) - (PORT datac (1952:1952:1952) (2012:2012:2012)) - (PORT datad (1530:1530:1530) (1637:1637:1637)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1404:1404:1404) (1446:1446:1446)) + (PORT datab (764:764:764) (796:796:796)) + (PORT datac (1716:1716:1716) (1772:1772:1772)) + (PORT datad (1630:1630:1630) (1644:1644:1644)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31107,14 +31663,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT clk (1342:1342:1342) (1352:1352:1352)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1088:1088:1088) (1091:1091:1091)) - (PORT sload (1315:1315:1315) (1359:1359:1359)) - (PORT ena (1338:1338:1338) (1327:1327:1327)) + (PORT asdata (1084:1084:1084) (1076:1076:1076)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -31127,24 +31683,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT datac (1294:1294:1294) (1315:1315:1315)) - (PORT datad (1815:1815:1815) (1915:1915:1915)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (346:346:346) (350:350:350)) + (PORT datab (503:503:503) (496:496:496)) + (PORT datad (799:799:799) (816:816:816)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (877:877:877) (890:890:890)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1342:1342:1342)) + (PORT datab (1039:1039:1039) (1059:1059:1059)) + (PORT datac (1042:1042:1042) (1061:1061:1061)) + (PORT datad (1060:1060:1060) (1077:1077:1077)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1094:1094:1094) (1120:1120:1120)) - (PORT datab (179:179:179) (211:211:211)) - (PORT datad (530:530:530) (516:516:516)) + (PORT dataa (818:818:818) (831:831:831)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (178:178:178) (200:200:200)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -31153,14 +31747,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT clk (1344:1344:1344) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (682:682:682) (728:728:728)) - (PORT sload (1315:1315:1315) (1359:1359:1359)) - (PORT ena (1338:1338:1338) (1327:1327:1327)) + (PORT asdata (865:865:865) (879:879:879)) + (PORT sload (1132:1132:1132) (1176:1176:1176)) + (PORT ena (1933:1933:1933) (1885:1885:1885)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -31173,104 +31767,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) + (INSTANCE z80_\|address_pins_\|abus\[6\]\~25) (DELAY (ABSOLUTE - (PORT dataa (2140:2140:2140) (2276:2276:2276)) - (PORT datad (1301:1301:1301) (1350:1350:1350)) + (PORT dataa (1231:1231:1231) (1337:1337:1337)) + (PORT datac (815:815:815) (859:859:859)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (380:380:380)) - (PORT datac (834:834:834) (854:854:854)) - (PORT datad (600:600:600) (625:625:625)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (573:573:573)) - (PORT datab (1197:1197:1197) (1215:1215:1215)) - (PORT datac (674:674:674) (720:720:720)) - (PORT datad (570:570:570) (564:564:564)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (297:297:297) (394:394:394)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (587:587:587) (604:604:604)) + (PORT datad (800:800:800) (812:812:812)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT clk (1342:1342:1342) (1352:1352:1352)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (PORT asdata (861:861:861) (884:884:884)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE z80_\|address_pins_\|abus\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (600:600:600) (628:628:628)) - (PORT datab (2569:2569:2569) (2664:2664:2664)) - (PORT datac (595:595:595) (614:614:614)) - (PORT datad (589:589:589) (620:620:620)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (327:327:327)) - (PORT datab (877:877:877) (917:917:917)) - (PORT datac (913:913:913) (955:955:955)) - (PORT datad (237:237:237) (304:304:304)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datac (212:212:212) (278:278:278)) + (PORT datad (2188:2188:2188) (2240:2240:2240)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31278,27 +31825,133 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (959:959:959) (1008:1008:1008)) - (PORT datac (240:240:240) (325:325:325)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (359:359:359) (369:369:369)) + (PORT datab (820:820:820) (845:845:845)) + (PORT datad (321:321:321) (327:327:327)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (878:878:878) (894:894:894)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (835:835:835)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (868:868:868) (893:893:893)) + (PORT sload (1132:1132:1132) (1176:1176:1176)) + (PORT ena (1933:1933:1933) (1885:1885:1885)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (837:837:837)) + (PORT datab (310:310:310) (326:326:326)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (527:527:527) (603:603:603)) + (PORT sload (1132:1132:1132) (1176:1176:1176)) + (PORT ena (1933:1933:1933) (1885:1885:1885)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1093:1093:1093)) + (PORT datab (1027:1027:1027) (1061:1061:1061)) + (PORT datac (1045:1045:1045) (1082:1082:1082)) + (PORT datad (1211:1211:1211) (1301:1301:1301)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (INSTANCE Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (375:375:375)) - (PORT datac (831:831:831) (855:855:855)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (331:331:331) (345:345:345)) + (PORT datac (1023:1023:1023) (1005:1005:1005)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -31306,148 +31959,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (INSTANCE D\[5\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1123:1123:1123) (1114:1114:1114)) - (PORT datac (642:642:642) (681:681:681)) - (PORT datad (573:573:573) (614:614:614)) + (PORT dataa (388:388:388) (408:408:408)) + (PORT datac (339:339:339) (355:355:355)) + (PORT datad (1009:1009:1009) (1018:1018:1018)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (720:720:720) (775:775:775)) - (PORT datab (313:313:313) (329:329:329)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (697:697:697) (758:758:758)) - (PORT datac (419:419:419) (476:476:476)) - (PORT datad (852:852:852) (871:871:871)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (963:963:963)) - (PORT datab (616:616:616) (651:651:651)) - (PORT datac (644:644:644) (682:682:682)) - (PORT datad (1077:1077:1077) (1068:1068:1068)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (942:942:942)) - (PORT datab (695:695:695) (756:756:756)) - (PORT datac (645:645:645) (687:687:687)) - (PORT datad (895:895:895) (921:921:921)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (749:749:749)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (529:529:529) (516:516:516)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datad (1036:1036:1036) (1054:1054:1054)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (600:600:600) (599:599:599)) + (PORT datab (826:826:826) (853:853:853)) + (PORT datad (525:525:525) (510:510:510)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31457,11 +31990,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1342:1342:1342) (1352:1352:1352)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (828:828:828) (846:846:846)) - (PORT sload (1103:1103:1103) (1144:1144:1144)) - (PORT ena (1325:1325:1325) (1316:1316:1316)) + (PORT asdata (832:832:832) (860:860:860)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -31474,12 +32007,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~23) (DELAY (ABSOLUTE - (PORT datac (1553:1553:1553) (1654:1654:1654)) - (PORT datad (2417:2417:2417) (2527:2527:2527)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2236:2236:2236) (2286:2286:2286)) + (PORT datad (217:217:217) (274:274:274)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31489,9 +32022,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (327:327:327) (335:335:335)) - (PORT datad (1036:1036:1036) (1050:1050:1050)) + (PORT dataa (517:517:517) (506:506:506)) + (PORT datab (589:589:589) (596:596:596)) + (PORT datad (795:795:795) (815:815:815)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -31503,11 +32036,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1342:1342:1342) (1352:1352:1352)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (854:854:854) (870:870:870)) - (PORT sload (1103:1103:1103) (1144:1144:1144)) - (PORT ena (1325:1325:1325) (1316:1316:1316)) + (PORT asdata (1602:1602:1602) (1617:1617:1617)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -31523,214 +32056,23 @@ (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) (DELAY (ABSOLUTE - (PORT dataa (2233:2233:2233) (2387:2387:2387)) - (PORT datad (1538:1538:1538) (1577:1577:1577)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (1178:1178:1178) (1218:1218:1218)) - (PORT datac (654:654:654) (716:716:716)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (884:884:884) (946:946:946)) + (PORT datac (1373:1373:1373) (1416:1416:1416)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (791:791:791)) - (PORT datab (647:647:647) (679:679:679)) - (PORT datac (641:641:641) (683:683:683)) - (PORT datad (168:168:168) (194:194:194)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT datac (629:629:629) (670:670:670)) - (PORT datad (683:683:683) (747:747:747)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (723:723:723)) - (PORT datab (1177:1177:1177) (1217:1217:1217)) - (PORT datac (654:654:654) (714:714:714)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (195:195:195) (230:230:230)) - (PORT datac (691:691:691) (764:764:764)) - (PORT datad (186:186:186) (213:213:213)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (353:353:353)) - (PORT datac (781:781:781) (782:782:782)) - (PORT datad (657:657:657) (698:698:698)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (678:678:678)) - (PORT datac (908:908:908) (937:937:937)) - (PORT datad (606:606:606) (638:638:638)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (832:832:832)) - (PORT datab (563:563:563) (571:571:571)) - (PORT datad (169:169:169) (194:194:194)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (636:636:636)) - (PORT datab (1362:1362:1362) (1339:1339:1339)) - (PORT datac (841:841:841) (844:844:844)) - (PORT datad (333:333:333) (373:373:373)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datad (1035:1035:1035) (1050:1050:1050)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (666:666:666) (711:711:711)) - (PORT sload (1103:1103:1103) (1144:1144:1144)) - (PORT ena (1325:1325:1325) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (1679:1679:1679) (1711:1711:1711)) - (PORT datac (2090:2090:2090) (2212:2212:2212)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (355:355:355)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (1039:1039:1039) (1054:1054:1054)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (755:755:755) (749:749:749)) + (PORT datab (749:749:749) (751:751:751)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -31740,11 +32082,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1347:1347:1347) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (678:678:678) (727:727:727)) - (PORT sload (1103:1103:1103) (1144:1144:1144)) - (PORT ena (1325:1325:1325) (1316:1316:1316)) + (PORT asdata (1158:1158:1158) (1186:1186:1186)) + (PORT sload (1592:1592:1592) (1649:1649:1649)) + (PORT ena (1313:1313:1313) (1291:1291:1291)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -31757,505 +32099,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (389:389:389)) - (PORT datab (709:709:709) (769:769:769)) - (PORT datac (642:642:642) (710:710:710)) - (PORT datad (325:325:325) (329:329:329)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT datab (392:392:392) (448:448:448)) - (PORT datac (675:675:675) (741:741:741)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (235:235:235)) - (PORT datab (716:716:716) (754:754:754)) - (PORT datad (162:162:162) (184:184:184)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1327:1327:1327) (1346:1346:1346)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1370:1370:1370) (1350:1350:1350)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1823:1823:1823) (1920:1920:1920)) - (PORT datac (2093:2093:2093) (2212:2212:2212)) - (PORT datad (614:614:614) (639:639:639)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (885:885:885)) - (PORT datab (913:913:913) (946:946:946)) - (PORT datad (186:186:186) (211:211:211)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (986:986:986)) - (PORT datab (262:262:262) (338:338:338)) - (PORT datac (222:222:222) (295:295:295)) - (PORT datad (662:662:662) (702:702:702)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1009:1009:1009)) - (PORT datab (878:878:878) (921:921:921)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (393:393:393)) - (PORT datab (579:579:579) (587:587:587)) - (PORT datad (735:735:735) (731:731:731)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (221:221:221)) - (PORT datab (208:208:208) (245:245:245)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (590:590:590) (613:613:613)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datab (1302:1302:1302) (1370:1370:1370)) + (PORT datac (218:218:218) (286:286:286)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datac (2343:2343:2343) (2477:2477:2477)) - (PORT datad (1094:1094:1094) (1146:1146:1146)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (733:733:733)) - (PORT datab (867:867:867) (899:899:899)) - (PORT datac (681:681:681) (744:744:744)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (893:893:893)) - (PORT datab (670:670:670) (712:712:712)) - (PORT datac (642:642:642) (709:709:709)) - (PORT datad (330:330:330) (354:354:354)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (416:416:416) (485:485:485)) - (PORT datad (584:584:584) (579:579:579)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT datab (463:463:463) (508:508:508)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1325:1325:1325) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1347:1347:1347)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (720:720:720)) - (PORT datad (681:681:681) (733:733:733)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (399:399:399)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1120:1120:1120)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datad (295:295:295) (301:301:301)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (676:676:676) (723:723:723)) - (PORT sload (1315:1315:1315) (1359:1359:1359)) - (PORT ena (1338:1338:1338) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2136:2136:2136) (2272:2272:2272)) - (PORT datad (1320:1320:1320) (1368:1368:1368)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1119:1119:1119)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (667:667:667) (705:705:705)) - (PORT sload (1315:1315:1315) (1359:1359:1359)) - (PORT ena (1338:1338:1338) (1327:1327:1327)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (862:862:862) (919:919:919)) - (PORT datad (2208:2208:2208) (2347:2347:2347)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (685:685:685)) - (PORT datab (621:621:621) (661:661:661)) - (PORT datac (616:616:616) (640:640:640)) - (PORT datad (1379:1379:1379) (1422:1422:1422)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (2189:2189:2189) (2317:2317:2317)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1360:1360:1360)) - (PORT asdata (515:515:515) (584:584:584)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (211:211:211) (272:272:272)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (806:806:806)) - (PORT datab (225:225:225) (297:297:297)) - (PORT datac (917:917:917) (930:930:930)) - (PORT datad (210:210:210) (270:270:270)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2429:2429:2429) (2458:2458:2458)) - (PORT datab (1787:1787:1787) (1868:1868:1868)) - (PORT datac (2566:2566:2566) (2669:2669:2669)) - (PORT datad (2051:2051:2051) (2020:2020:2020)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1825:1825:1825) (1924:1924:1924)) - (PORT datac (2092:2092:2092) (2210:2210:2210)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -32264,953 +32114,26 @@ (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (2429:2429:2429) (2462:2462:2462)) - (PORT datab (1785:1785:1785) (1869:1869:1869)) - (PORT datac (2568:2568:2568) (2669:2669:2669)) - (PORT datad (2053:2053:2053) (2023:2023:2023)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1112:1112:1112) (1152:1152:1152)) + (PORT datab (1070:1070:1070) (1066:1066:1066)) + (PORT datac (1122:1122:1122) (1187:1187:1187)) + (PORT datad (1512:1512:1512) (1478:1478:1478)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (415:415:415)) - (PORT datab (1157:1157:1157) (1168:1168:1168)) - (PORT datac (1135:1135:1135) (1143:1143:1143)) - (PORT datad (1288:1288:1288) (1263:1263:1263)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1783:1783:1783) (1908:1908:1908)) - (PORT datac (1831:1831:1831) (1936:1936:1936)) - (PORT datad (1320:1320:1320) (1359:1359:1359)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (227:227:227)) - (PORT datab (576:576:576) (559:559:559)) - (PORT datad (839:839:839) (839:839:839)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (915:915:915) (941:941:941)) - (PORT sload (1102:1102:1102) (1143:1143:1143)) - (PORT ena (1118:1118:1118) (1108:1108:1108)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2234:2234:2234) (2386:2386:2386)) - (PORT datac (1001:1001:1001) (1001:1001:1001)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1573:1573:1573) (1572:1572:1572)) - (PORT datad (305:305:305) (311:311:311)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (862:862:862) (893:893:893)) - (PORT sload (1505:1505:1505) (1525:1525:1525)) - (PORT ena (1340:1340:1340) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1078:1078:1078)) - (PORT datad (2208:2208:2208) (2347:2347:2347)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (807:807:807)) - (PORT datab (1587:1587:1587) (1606:1606:1606)) - (PORT datad (814:814:814) (809:809:809)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1166:1166:1166) (1198:1198:1198)) - (PORT sload (1258:1258:1258) (1265:1265:1265)) - (PORT ena (1296:1296:1296) (1261:1261:1261)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (309:309:309)) - (PORT datad (2202:2202:2202) (2341:2341:2341)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (240:240:240)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datad (1536:1536:1536) (1535:1535:1535)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (833:833:833) (855:855:855)) - (PORT sload (1505:1505:1505) (1525:1525:1525)) - (PORT ena (1340:1340:1340) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (256:256:256) (326:326:326)) - (PORT datad (347:347:347) (390:390:390)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1573:1573:1573) (1568:1568:1568)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (873:873:873) (894:894:894)) - (PORT sload (1505:1505:1505) (1525:1525:1525)) - (PORT ena (1340:1340:1340) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datac (1143:1143:1143) (1205:1205:1205)) - (PORT datad (2199:2199:2199) (2335:2335:2335)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (500:500:500)) - (PORT datab (1571:1571:1571) (1568:1568:1568)) - (PORT datad (296:296:296) (292:292:292)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (531:531:531) (596:596:596)) - (PORT sload (1505:1505:1505) (1525:1525:1525)) - (PORT ena (1340:1340:1340) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datac (1398:1398:1398) (1414:1414:1414)) - (PORT datad (2204:2204:2204) (2340:2340:2340)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (977:977:977)) - (PORT datab (842:842:842) (840:840:840)) - (PORT datad (1563:1563:1563) (1573:1573:1573)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1170:1170:1170) (1213:1213:1213)) - (PORT sload (1258:1258:1258) (1265:1265:1265)) - (PORT ena (1296:1296:1296) (1261:1261:1261)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (2232:2232:2232) (2381:2381:2381)) - (PORT datac (220:220:220) (290:290:290)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1232:1232:1232) (1255:1255:1255)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2192:2192:2192) (2312:2312:2312)) - (PORT d[1] (2398:2398:2398) (2408:2408:2408)) - (PORT d[2] (1747:1747:1747) (1768:1768:1768)) - (PORT d[3] (1173:1173:1173) (1196:1196:1196)) - (PORT d[4] (2105:2105:2105) (2108:2108:2108)) - (PORT d[5] (1192:1192:1192) (1219:1219:1219)) - (PORT d[6] (1349:1349:1349) (1338:1338:1338)) - (PORT d[7] (2178:2178:2178) (2237:2237:2237)) - (PORT d[8] (2072:2072:2072) (2150:2150:2150)) - (PORT d[9] (969:969:969) (998:998:998)) - (PORT d[10] (947:947:947) (967:967:967)) - (PORT d[11] (1341:1341:1341) (1349:1349:1349)) - (PORT d[12] (699:699:699) (736:736:736)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1633:1633:1633) (1597:1597:1597)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (1654:1654:1654) (1616:1616:1616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1669:1669:1669) (1690:1690:1690)) - (PORT asdata (1855:1855:1855) (1863:1863:1863)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1630:1630:1630) (1612:1612:1612)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (914:914:914)) - (PORT datab (830:830:830) (834:834:834)) - (PORT datac (1053:1053:1053) (1064:1064:1064)) - (PORT datad (883:883:883) (917:917:917)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1781:1781:1781) (1907:1907:1907)) - (PORT datac (1830:1830:1830) (1939:1939:1939)) - (PORT datad (1316:1316:1316) (1358:1358:1358)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1403:1403:1403) (1398:1398:1398)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1803:1803:1803) (1874:1874:1874)) - (PORT d[1] (2314:2314:2314) (2291:2291:2291)) - (PORT d[2] (2392:2392:2392) (2484:2484:2484)) - (PORT d[3] (1058:1058:1058) (1063:1063:1063)) - (PORT d[4] (2244:2244:2244) (2302:2302:2302)) - (PORT d[5] (2929:2929:2929) (2934:2934:2934)) - (PORT d[6] (2024:2024:2024) (2037:2037:2037)) - (PORT d[7] (1714:1714:1714) (1678:1678:1678)) - (PORT d[8] (2325:2325:2325) (2386:2386:2386)) - (PORT d[9] (1569:1569:1569) (1548:1548:1548)) - (PORT d[10] (2321:2321:2321) (2324:2324:2324)) - (PORT d[11] (3718:3718:3718) (3857:3857:3857)) - (PORT d[12] (2324:2324:2324) (2328:2328:2328)) - (PORT clk (1631:1631:1631) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1836:1836:1836) (1776:1776:1776)) - (PORT clk (1631:1631:1631) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (PORT d[0] (1991:1991:1991) (1922:1922:1922)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1627:1627:1627)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (415:415:415)) - (PORT datab (1157:1157:1157) (1174:1174:1174)) - (PORT datac (1135:1135:1135) (1147:1147:1147)) - (PORT datad (1288:1288:1288) (1267:1267:1267)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1782:1782:1782) (1907:1907:1907)) - (PORT datac (1830:1830:1830) (1934:1934:1934)) - (PORT datad (1320:1320:1320) (1355:1355:1355)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (798:798:798) (778:778:778)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2702:2702:2702) (2810:2810:2810)) - (PORT d[1] (3071:3071:3071) (3143:3143:3143)) - (PORT d[2] (1388:1388:1388) (1408:1408:1408)) - (PORT d[3] (3663:3663:3663) (3710:3710:3710)) - (PORT d[4] (2688:2688:2688) (2785:2785:2785)) - (PORT d[5] (4080:4080:4080) (4141:4141:4141)) - (PORT d[6] (2045:2045:2045) (2040:2040:2040)) - (PORT d[7] (3688:3688:3688) (3683:3683:3683)) - (PORT d[8] (1409:1409:1409) (1424:1424:1424)) - (PORT d[9] (1966:1966:1966) (2004:2004:2004)) - (PORT d[10] (2120:2120:2120) (2114:2114:2114)) - (PORT d[11] (2915:2915:2915) (3018:3018:3018)) - (PORT d[12] (3812:3812:3812) (3918:3918:3918)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1774:1774:1774) (1701:1701:1701)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (2479:2479:2479) (2455:2455:2455)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1366:1366:1366) (1386:1386:1386)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (867:867:867) (886:886:886)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (420:420:420)) - (PORT datab (1152:1152:1152) (1167:1167:1167)) - (PORT datac (1134:1134:1134) (1146:1146:1146)) - (PORT datad (1287:1287:1287) (1261:1261:1261)) + (PORT dataa (1938:1938:1938) (2006:2006:2006)) + (PORT datab (927:927:927) (944:944:944)) + (PORT datac (1634:1634:1634) (1669:1669:1669)) + (PORT datad (198:198:198) (227:227:227)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -33223,1468 +32146,10 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1778:1778:1778) (1903:1903:1903)) - (PORT datac (1832:1832:1832) (1935:1935:1935)) - (PORT datad (1314:1314:1314) (1353:1353:1353)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1219:1219:1219) (1239:1239:1239)) - (PORT clk (1637:1637:1637) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1968:1968:1968) (2075:2075:2075)) - (PORT d[1] (2097:2097:2097) (2114:2114:2114)) - (PORT d[2] (1482:1482:1482) (1499:1499:1499)) - (PORT d[3] (2317:2317:2317) (2327:2327:2327)) - (PORT d[4] (2131:2131:2131) (2125:2125:2125)) - (PORT d[5] (1457:1457:1457) (1474:1474:1474)) - (PORT d[6] (1593:1593:1593) (1587:1587:1587)) - (PORT d[7] (2052:2052:2052) (2057:2057:2057)) - (PORT d[8] (2295:2295:2295) (2395:2395:2395)) - (PORT d[9] (985:985:985) (1023:1023:1023)) - (PORT d[10] (1599:1599:1599) (1617:1617:1617)) - (PORT d[11] (1329:1329:1329) (1327:1327:1327)) - (PORT d[12] (941:941:941) (980:980:980)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1388:1388:1388) (1367:1367:1367)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (PORT d[0] (1831:1831:1831) (1775:1775:1775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (982:982:982)) - (PORT datab (1419:1419:1419) (1416:1416:1416)) - (PORT datac (1306:1306:1306) (1318:1318:1318)) - (PORT datad (1373:1373:1373) (1371:1371:1371)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1220:1220:1220)) - (PORT datab (1691:1691:1691) (1773:1773:1773)) - (PORT datac (1544:1544:1544) (1537:1537:1537)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (416:416:416)) - (PORT datab (1150:1150:1150) (1167:1167:1167)) - (PORT datac (1134:1134:1134) (1142:1142:1142)) - (PORT datad (1282:1282:1282) (1261:1261:1261)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (133:133:133) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (486:486:486)) - (PORT datab (895:895:895) (920:920:920)) - (PORT datac (642:642:642) (681:681:681)) - (PORT datad (684:684:684) (714:714:714)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT asdata (913:913:913) (935:935:935)) - (PORT ena (740:740:740) (743:743:743)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (826:826:826)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (829:829:829) (853:853:853)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (833:833:833) (858:858:858)) - (PORT datad (816:816:816) (835:835:835)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (893:893:893)) - (PORT datab (844:844:844) (870:870:870)) - (PORT datad (813:813:813) (824:824:824)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT datab (886:886:886) (948:948:948)) + (PORT datac (1374:1374:1374) (1420:1420:1420)) + (PORT datad (1095:1095:1095) (1134:1134:1134)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (740:740:740) (743:743:743)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1213:1213:1213)) - (PORT datab (586:586:586) (609:609:609)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (719:719:719)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (668:668:668)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (878:878:878) (871:871:871)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (864:864:864) (845:845:845)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (901:901:901)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (864:864:864) (845:845:845)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT datab (875:875:875) (902:902:902)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (864:864:864) (845:845:845)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (700:700:700)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (905:905:905)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[8\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (486:486:486)) - (PORT datab (893:893:893) (916:916:916)) - (PORT datac (643:643:643) (682:682:682)) - (PORT datad (682:682:682) (711:711:711)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (899:899:899) (893:893:893)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1046:1046:1046)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (899:899:899)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (899:899:899) (893:893:893)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (487:487:487)) - (PORT datab (901:901:901) (926:926:926)) - (PORT datac (637:637:637) (676:676:676)) - (PORT datad (687:687:687) (718:718:718)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (332:332:332)) - (PORT datab (354:354:354) (357:357:357)) - (PORT datad (686:686:686) (719:719:719)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datac (838:838:838) (869:869:869)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (899:899:899) (893:893:893)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (898:898:898)) - (PORT datac (165:165:165) (199:199:199)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (899:899:899) (893:893:893)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1189:1189:1189) (1207:1207:1207)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2600:2600:2600) (2662:2662:2662)) - (PORT d[1] (2747:2747:2747) (2782:2782:2782)) - (PORT d[2] (1792:1792:1792) (1855:1855:1855)) - (PORT d[3] (2004:2004:2004) (2045:2045:2045)) - (PORT d[4] (1916:1916:1916) (1963:1963:1963)) - (PORT d[5] (1727:1727:1727) (1774:1774:1774)) - (PORT d[6] (2147:2147:2147) (2209:2209:2209)) - (PORT d[7] (1761:1761:1761) (1785:1785:1785)) - (PORT d[8] (2953:2953:2953) (2996:2996:2996)) - (PORT d[9] (1855:1855:1855) (1943:1943:1943)) - (PORT d[10] (3321:3321:3321) (3370:3370:3370)) - (PORT d[11] (2216:2216:2216) (2269:2269:2269)) - (PORT d[12] (1822:1822:1822) (1911:1911:1911)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1643:1643:1643) (1624:1624:1624)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (2934:2934:2934) (2920:2920:2920)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1599:1599:1599)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1725:1725:1725) (1737:1737:1737)) - (PORT clk (1608:1608:1608) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4163:4163:4163) (4138:4138:4138)) - (PORT d[1] (4073:4073:4073) (4107:4107:4107)) - (PORT d[2] (4223:4223:4223) (4111:4111:4111)) - (PORT d[3] (3967:3967:3967) (3949:3949:3949)) - (PORT d[4] (4067:4067:4067) (4010:4010:4010)) - (PORT d[5] (4104:4104:4104) (4095:4095:4095)) - (PORT d[6] (4094:4094:4094) (4038:4038:4038)) - (PORT d[7] (4079:4079:4079) (4065:4065:4065)) - (PORT d[8] (4307:4307:4307) (4239:4239:4239)) - (PORT d[9] (4112:4112:4112) (4038:4038:4038)) - (PORT d[10] (4146:4146:4146) (4023:4023:4023)) - (PORT d[11] (4101:4101:4101) (4053:4053:4053)) - (PORT d[12] (4079:4079:4079) (3997:3997:3997)) - (PORT clk (1605:1605:1605) (1603:1603:1603)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1606:1606:1606)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1600:1600:1600)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1334:1334:1334) (1342:1342:1342)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (199:199:199) (257:257:257)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1104:1104:1104)) - (PORT datab (1171:1171:1171) (1178:1178:1178)) - (PORT datac (1323:1323:1323) (1348:1348:1348)) - (PORT datad (1044:1044:1044) (1067:1067:1067)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1133:1133:1133) (1102:1102:1102)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2873:2873:2873) (2947:2947:2947)) - (PORT d[1] (1964:1964:1964) (1976:1976:1976)) - (PORT d[2] (1509:1509:1509) (1557:1557:1557)) - (PORT d[3] (1427:1427:1427) (1466:1466:1466)) - (PORT d[4] (2472:2472:2472) (2528:2528:2528)) - (PORT d[5] (1455:1455:1455) (1490:1490:1490)) - (PORT d[6] (1877:1877:1877) (1920:1920:1920)) - (PORT d[7] (1746:1746:1746) (1757:1757:1757)) - (PORT d[8] (3214:3214:3214) (3263:3263:3263)) - (PORT d[9] (1565:1565:1565) (1638:1638:1638)) - (PORT d[10] (1519:1519:1519) (1575:1575:1575)) - (PORT d[11] (1502:1502:1502) (1531:1531:1531)) - (PORT d[12] (1545:1545:1545) (1620:1620:1620)) - (PORT clk (1628:1628:1628) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1317:1317:1317) (1261:1261:1261)) - (PORT clk (1628:1628:1628) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1660:1660:1660)) - (PORT d[0] (2636:2636:2636) (2629:2629:2629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1590:1590:1590)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1413:1413:1413) (1413:1413:1413)) - (PORT clk (1598:1598:1598) (1597:1597:1597)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4124:4124:4124) (4083:4083:4083)) - (PORT d[1] (4040:4040:4040) (3991:3991:3991)) - (PORT d[2] (4097:4097:4097) (4011:4011:4011)) - (PORT d[3] (3978:3978:3978) (3952:3952:3952)) - (PORT d[4] (4021:4021:4021) (3977:3977:3977)) - (PORT d[5] (4067:4067:4067) (4036:4036:4036)) - (PORT d[6] (4095:4095:4095) (3949:3949:3949)) - (PORT d[7] (4043:4043:4043) (4028:4028:4028)) - (PORT d[8] (4124:4124:4124) (4102:4102:4102)) - (PORT d[9] (4148:4148:4148) (4090:4090:4090)) - (PORT d[10] (4151:4151:4151) (4113:4113:4113)) - (PORT d[11] (4142:4142:4142) (4089:4089:4089)) - (PORT d[12] (4083:4083:4083) (3991:3991:3991)) - (PORT clk (1595:1595:1595) (1594:1594:1594)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1597:1597:1597)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2949:2949:2949) (3064:3064:3064)) - (PORT d[1] (3077:3077:3077) (3150:3150:3150)) - (PORT d[2] (1328:1328:1328) (1346:1346:1346)) - (PORT d[3] (3633:3633:3633) (3669:3669:3669)) - (PORT d[4] (2708:2708:2708) (2805:2805:2805)) - (PORT d[5] (4075:4075:4075) (4133:4133:4133)) - (PORT d[6] (2581:2581:2581) (2586:2586:2586)) - (PORT d[7] (1601:1601:1601) (1613:1613:1613)) - (PORT d[8] (1832:1832:1832) (1833:1833:1833)) - (PORT d[9] (1977:1977:1977) (2013:2013:2013)) - (PORT d[10] (2129:2129:2129) (2133:2133:2133)) - (PORT d[11] (2878:2878:2878) (2980:2980:2980)) - (PORT d[12] (3945:3945:3945) (4038:4038:4038)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (1781:1781:1781) (1761:1761:1761)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (900:900:900)) - (PORT datab (273:273:273) (354:354:354)) - (PORT datac (825:825:825) (829:829:829)) - (PORT datad (982:982:982) (946:946:946)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1813:1813:1813) (1837:1837:1837)) - (PORT d[1] (2372:2372:2372) (2409:2409:2409)) - (PORT d[2] (2184:2184:2184) (2246:2246:2246)) - (PORT d[3] (2777:2777:2777) (2778:2778:2778)) - (PORT d[4] (2118:2118:2118) (2144:2144:2144)) - (PORT d[5] (2861:2861:2861) (2865:2865:2865)) - (PORT d[6] (2623:2623:2623) (2631:2631:2631)) - (PORT d[7] (2917:2917:2917) (2919:2919:2919)) - (PORT d[8] (2209:2209:2209) (2233:2233:2233)) - (PORT d[9] (2806:2806:2806) (2873:2873:2873)) - (PORT d[10] (2112:2112:2112) (2110:2110:2110)) - (PORT d[11] (2306:2306:2306) (2369:2369:2369)) - (PORT d[12] (2976:2976:2976) (3046:3046:3046)) - (PORT clk (1654:1654:1654) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (2654:2654:2654) (2639:2639:2639)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1682:1682:1682)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1647:1647:1647)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (894:894:894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (980:980:980)) - (PORT datab (1353:1353:1353) (1375:1375:1375)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (1573:1573:1573) (1550:1550:1550)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1087:1087:1087)) - (PORT datab (275:275:275) (357:357:357)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1329:1329:1329)) - (PORT datab (2124:2124:2124) (2266:2266:2266)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1140:1140:1140) (1182:1182:1182)) - (PORT datab (577:577:577) (594:594:594)) - (PORT datac (783:783:783) (787:787:787)) - (PORT datad (307:307:307) (310:310:310)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2029:2029:2029) (2017:2017:2017)) - (PORT datab (579:579:579) (595:595:595)) - (PORT datac (1572:1572:1572) (1603:1603:1603)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34692,1943 +32157,209 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (INSTANCE z80_\|address_pins_\|abus\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (1043:1043:1043) (1062:1062:1062)) + (PORT datad (1212:1212:1212) (1302:1302:1302)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1344:1344:1344)) + (PORT datac (1041:1041:1041) (1058:1058:1058)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1344:1344:1344)) + (PORT datad (1059:1059:1059) (1074:1074:1074)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (314:314:314)) + (PORT datad (2188:2188:2188) (2240:2240:2240)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (1027:1027:1027) (1062:1062:1062)) + (PORT datad (1210:1210:1210) (1301:1301:1301)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1345:1345:1345)) + (PORT datac (1044:1044:1044) (1083:1083:1083)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (1326:1326:1326) (1317:1317:1317)) - (PORT datac (1018:1018:1018) (1002:1002:1002)) - (PORT datad (321:321:321) (326:326:326)) + (PORT datab (810:810:810) (831:831:831)) + (PORT datad (286:286:286) (291:291:291)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (865:865:865) (883:883:883)) + (PORT sload (1164:1164:1164) (1223:1223:1223)) + (PORT ena (1772:1772:1772) (1740:1740:1740)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (633:633:633)) + (PORT datac (1774:1774:1774) (1856:1856:1856)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1025:1025:1025)) - (PORT datab (1374:1374:1374) (1418:1418:1418)) - (PORT datac (1950:1950:1950) (2012:2012:2012)) - (PORT datad (1524:1524:1524) (1636:1636:1636)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (1569:1569:1569) (1598:1598:1598)) - (PORT datab (501:501:501) (498:498:498)) - (PORT datac (939:939:939) (914:914:914)) - (PORT datad (1042:1042:1042) (1029:1029:1029)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1064:1064:1064) (1031:1031:1031)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1039:1039:1039)) - (PORT datab (218:218:218) (259:259:259)) - (PORT datac (785:785:785) (760:760:760)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datac (1018:1018:1018) (999:999:999)) - (PORT datad (200:200:200) (236:236:236)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (414:414:414)) - (PORT datab (227:227:227) (273:273:273)) - (PORT datac (313:313:313) (323:323:323)) - (PORT datad (199:199:199) (229:229:229)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (570:570:570) (564:564:564)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1070:1070:1070) (1068:1068:1068)) - (PORT datab (2698:2698:2698) (2666:2666:2666)) - (PORT datac (1267:1267:1267) (1301:1301:1301)) - (PORT datad (734:734:734) (763:763:763)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1412:1412:1412) (1378:1378:1378)) - (PORT ena (2056:2056:2056) (1990:1990:1990)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1709:1709:1709) (1764:1764:1764)) - (PORT datab (1513:1513:1513) (1636:1636:1636)) - (PORT datac (1578:1578:1578) (1615:1615:1615)) - (PORT datad (807:807:807) (804:804:804)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (627:627:627)) - (PORT datab (780:780:780) (778:778:778)) - (PORT datac (325:325:325) (335:335:335)) - (PORT datad (565:565:565) (559:559:559)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (826:826:826) (861:861:861)) - (PORT datab (1089:1089:1089) (1091:1091:1091)) - (PORT datac (1056:1056:1056) (1057:1057:1057)) - (PORT datad (1077:1077:1077) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (336:336:336)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (796:796:796) (813:813:813)) - (PORT datad (197:197:197) (228:228:228)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (798:798:798)) - (PORT datac (744:744:744) (747:747:747)) - (PORT datad (765:765:765) (742:742:742)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (836:836:836)) - (PORT datab (838:838:838) (820:820:820)) - (PORT datac (739:739:739) (727:727:727)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (561:561:561)) - (PORT datab (1075:1075:1075) (1072:1072:1072)) - (PORT datac (835:835:835) (845:845:845)) - (PORT datad (542:542:542) (540:540:540)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (1244:1244:1244) (1216:1216:1216)) - (PORT datac (584:584:584) (589:589:589)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (784:784:784)) - (PORT datab (625:625:625) (644:644:644)) - (PORT datac (773:773:773) (773:773:773)) - (PORT datad (768:768:768) (745:745:745)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (764:764:764) (760:760:760)) - (PORT datac (330:330:330) (336:336:336)) - (PORT datad (786:786:786) (771:771:771)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (847:847:847)) - (PORT datab (590:590:590) (601:601:601)) - (PORT datac (158:158:158) (190:190:190)) - (PORT datad (548:548:548) (542:542:542)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1032:1032:1032)) - (PORT datab (220:220:220) (262:262:262)) - (PORT datad (1100:1100:1100) (1096:1096:1096)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1219:1219:1219) (1236:1236:1236)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2225:2225:2225) (2347:2347:2347)) - (PORT d[1] (2419:2419:2419) (2429:2429:2429)) - (PORT d[2] (1155:1155:1155) (1173:1173:1173)) - (PORT d[3] (1173:1173:1173) (1184:1184:1184)) - (PORT d[4] (1878:1878:1878) (1878:1878:1878)) - (PORT d[5] (1162:1162:1162) (1183:1183:1183)) - (PORT d[6] (1374:1374:1374) (1357:1357:1357)) - (PORT d[7] (2179:2179:2179) (2238:2238:2238)) - (PORT d[8] (2314:2314:2314) (2411:2411:2411)) - (PORT d[9] (716:716:716) (757:757:757)) - (PORT d[10] (1619:1619:1619) (1643:1643:1643)) - (PORT d[11] (1101:1101:1101) (1107:1107:1107)) - (PORT d[12] (673:673:673) (706:706:706)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1648:1648:1648) (1601:1601:1601)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (1654:1654:1654) (1615:1615:1615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (898:898:898) (896:896:896)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2259:2259:2259) (2374:2374:2374)) - (PORT d[1] (1158:1158:1158) (1167:1167:1167)) - (PORT d[2] (1537:1537:1537) (1570:1570:1570)) - (PORT d[3] (1478:1478:1478) (1518:1518:1518)) - (PORT d[4] (2760:2760:2760) (2842:2842:2842)) - (PORT d[5] (1170:1170:1170) (1191:1191:1191)) - (PORT d[6] (1442:1442:1442) (1483:1483:1483)) - (PORT d[7] (1199:1199:1199) (1208:1208:1208)) - (PORT d[8] (1163:1163:1163) (1180:1180:1180)) - (PORT d[9] (995:995:995) (1054:1054:1054)) - (PORT d[10] (989:989:989) (1043:1043:1043)) - (PORT d[11] (2058:2058:2058) (2128:2128:2128)) - (PORT d[12] (1004:1004:1004) (1063:1063:1063)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1121:1121:1121) (1058:1058:1058)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2116:2116:2116) (2080:2080:2080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1218:1218:1218) (1229:1229:1229)) - (PORT clk (1626:1626:1626) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2502:2502:2502) (2623:2623:2623)) - (PORT d[1] (2673:2673:2673) (2693:2693:2693)) - (PORT d[2] (1145:1145:1145) (1155:1155:1155)) - (PORT d[3] (910:910:910) (929:929:929)) - (PORT d[4] (1906:1906:1906) (1916:1916:1916)) - (PORT d[5] (882:882:882) (894:894:894)) - (PORT d[6] (1337:1337:1337) (1316:1316:1316)) - (PORT d[7] (2449:2449:2449) (2517:2517:2517)) - (PORT d[8] (2328:2328:2328) (2435:2435:2435)) - (PORT d[9] (685:685:685) (720:720:720)) - (PORT d[10] (698:698:698) (734:734:734)) - (PORT d[11] (2617:2617:2617) (2715:2715:2715)) - (PORT d[12] (659:659:659) (681:681:681)) - (PORT clk (1623:1623:1623) (1653:1653:1653)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1137:1137:1137) (1091:1091:1091)) - (PORT clk (1623:1623:1623) (1653:1653:1653)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1626:1626:1626) (1655:1655:1655)) - (PORT d[0] (1310:1310:1310) (1264:1264:1264)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1619:1619:1619)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (861:861:861) (866:866:866)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (635:635:635) (633:633:633)) - (PORT clk (1638:1638:1638) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2482:2482:2482) (2610:2610:2610)) - (PORT d[1] (1202:1202:1202) (1220:1220:1220)) - (PORT d[2] (1538:1538:1538) (1560:1560:1560)) - (PORT d[3] (1448:1448:1448) (1471:1471:1471)) - (PORT d[4] (2753:2753:2753) (2824:2824:2824)) - (PORT d[5] (1176:1176:1176) (1199:1199:1199)) - (PORT d[6] (1395:1395:1395) (1434:1434:1434)) - (PORT d[7] (1496:1496:1496) (1508:1508:1508)) - (PORT d[8] (1437:1437:1437) (1483:1483:1483)) - (PORT d[9] (1272:1272:1272) (1330:1330:1330)) - (PORT d[10] (1231:1231:1231) (1281:1281:1281)) - (PORT d[11] (1749:1749:1749) (1808:1808:1808)) - (PORT d[12] (1273:1273:1273) (1338:1338:1338)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1132:1132:1132) (1110:1110:1110)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1664:1664:1664)) - (PORT d[0] (2443:2443:2443) (2415:2415:2415)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1628:1628:1628)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1354:1354:1354)) - (PORT datab (1149:1149:1149) (1145:1145:1145)) - (PORT datad (1329:1329:1329) (1284:1284:1284)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1434:1434:1434)) - (PORT datab (1690:1690:1690) (1773:1773:1773)) - (PORT datac (1326:1326:1326) (1309:1309:1309)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1174:1174:1174) (1180:1180:1180)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2605:2605:2605) (2669:2669:2669)) - (PORT d[1] (1701:1701:1701) (1733:1733:1733)) - (PORT d[2] (1765:1765:1765) (1825:1825:1825)) - (PORT d[3] (1991:1991:1991) (2045:2045:2045)) - (PORT d[4] (2201:2201:2201) (2250:2250:2250)) - (PORT d[5] (1726:1726:1726) (1773:1773:1773)) - (PORT d[6] (2165:2165:2165) (2208:2208:2208)) - (PORT d[7] (2045:2045:2045) (2081:2081:2081)) - (PORT d[8] (2933:2933:2933) (2976:2976:2976)) - (PORT d[9] (1602:1602:1602) (1690:1690:1690)) - (PORT d[10] (1508:1508:1508) (1579:1579:1579)) - (PORT d[11] (2225:2225:2225) (2285:2285:2285)) - (PORT d[12] (2265:2265:2265) (2328:2328:2328)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1635:1635:1635) (1603:1603:1603)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2933:2933:2933) (2921:2921:2921)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1597:1597:1597) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1744:1744:1744) (1758:1758:1758)) - (PORT clk (1605:1605:1605) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4118:4118:4118) (4095:4095:4095)) - (PORT d[1] (4082:4082:4082) (4121:4121:4121)) - (PORT d[2] (4232:4232:4232) (4129:4129:4129)) - (PORT d[3] (3938:3938:3938) (3910:3910:3910)) - (PORT d[4] (4046:4046:4046) (3977:3977:3977)) - (PORT d[5] (4080:4080:4080) (4058:4058:4058)) - (PORT d[6] (4035:4035:4035) (3994:3994:3994)) - (PORT d[7] (4079:4079:4079) (4064:4064:4064)) - (PORT d[8] (4294:4294:4294) (4238:4238:4238)) - (PORT d[9] (4104:4104:4104) (4047:4047:4047)) - (PORT d[10] (4093:4093:4093) (4034:4034:4034)) - (PORT d[11] (4127:4127:4127) (4082:4082:4082)) - (PORT d[12] (4100:4100:4100) (4018:4018:4018)) - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1596:1596:1596)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1141:1141:1141) (1143:1143:1143)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2606:2606:2606) (2670:2670:2670)) - (PORT d[1] (1699:1699:1699) (1730:1730:1730)) - (PORT d[2] (2088:2088:2088) (2156:2156:2156)) - (PORT d[3] (1995:1995:1995) (2050:2050:2050)) - (PORT d[4] (2189:2189:2189) (2247:2247:2247)) - (PORT d[5] (1722:1722:1722) (1766:1766:1766)) - (PORT d[6] (1705:1705:1705) (1772:1772:1772)) - (PORT d[7] (1734:1734:1734) (1752:1752:1752)) - (PORT d[8] (2910:2910:2910) (2945:2945:2945)) - (PORT d[9] (1580:1580:1580) (1668:1668:1668)) - (PORT d[10] (3626:3626:3626) (3667:3667:3667)) - (PORT d[11] (2227:2227:2227) (2291:2291:2291)) - (PORT d[12] (1554:1554:1554) (1633:1633:1633)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1567:1567:1567) (1502:1502:1502)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2670:2670:2670) (2673:2673:2673)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1592:1592:1592)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1712:1712:1712) (1724:1724:1724)) - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4129:4129:4129) (4092:4092:4092)) - (PORT d[1] (4031:4031:4031) (4056:4056:4056)) - (PORT d[2] (4108:4108:4108) (4046:4046:4046)) - (PORT d[3] (3952:3952:3952) (3915:3915:3915)) - (PORT d[4] (4042:4042:4042) (3967:3967:3967)) - (PORT d[5] (4100:4100:4100) (4079:4079:4079)) - (PORT d[6] (4103:4103:4103) (4033:4033:4033)) - (PORT d[7] (4050:4050:4050) (4030:4030:4030)) - (PORT d[8] (4318:4318:4318) (4266:4266:4266)) - (PORT d[9] (4159:4159:4159) (4085:4085:4085)) - (PORT d[10] (4133:4133:4133) (4084:4084:4084)) - (PORT d[11] (4147:4147:4147) (4096:4096:4096)) - (PORT d[12] (4099:4099:4099) (4018:4018:4018)) - (PORT clk (1599:1599:1599) (1596:1596:1596)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2326:2326:2326) (2379:2379:2379)) - (PORT d[1] (2454:2454:2454) (2491:2491:2491)) - (PORT d[2] (2065:2065:2065) (2140:2140:2140)) - (PORT d[3] (1941:1941:1941) (1996:1996:1996)) - (PORT d[4] (1635:1635:1635) (1673:1673:1673)) - (PORT d[5] (1981:1981:1981) (2035:2035:2035)) - (PORT d[6] (2222:2222:2222) (2291:2291:2291)) - (PORT d[7] (3167:3167:3167) (3201:3201:3201)) - (PORT d[8] (2665:2665:2665) (2694:2694:2694)) - (PORT d[9] (1892:1892:1892) (1995:1995:1995)) - (PORT d[10] (1768:1768:1768) (1842:1842:1842)) - (PORT d[11] (1974:1974:1974) (2023:2023:2023)) - (PORT d[12] (2086:2086:2086) (2174:2174:2174)) - (PORT clk (1644:1644:1644) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (PORT d[0] (2385:2385:2385) (2403:2403:2403)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1090:1090:1090)) - (PORT datab (275:275:275) (357:357:357)) - (PORT datac (1055:1055:1055) (1079:1079:1079)) - (PORT datad (1337:1337:1337) (1335:1335:1335)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1821:1821:1821) (1875:1875:1875)) - (PORT d[1] (2776:2776:2776) (2838:2838:2838)) - (PORT d[2] (2092:2092:2092) (2106:2106:2106)) - (PORT d[3] (3365:3365:3365) (3401:3401:3401)) - (PORT d[4] (2411:2411:2411) (2492:2492:2492)) - (PORT d[5] (3823:3823:3823) (3873:3873:3873)) - (PORT d[6] (2552:2552:2552) (2551:2551:2551)) - (PORT d[7] (3438:3438:3438) (3438:3438:3438)) - (PORT d[8] (1871:1871:1871) (1885:1885:1885)) - (PORT d[9] (1981:1981:1981) (2019:2019:2019)) - (PORT d[10] (2182:2182:2182) (2193:2193:2193)) - (PORT d[11] (2612:2612:2612) (2700:2700:2700)) - (PORT d[12] (3545:3545:3545) (3643:3643:3643)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (PORT d[0] (2037:2037:2037) (2057:2057:2057)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1633:1633:1633)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (877:877:877) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1247:1247:1247)) - (PORT datab (1151:1151:1151) (1147:1147:1147)) - (PORT datac (162:162:162) (197:197:197)) - (PORT datad (984:984:984) (957:957:957)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1088:1088:1088)) - (PORT datab (276:276:276) (359:359:359)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1328:1328:1328)) - (PORT datab (2123:2123:2123) (2266:2266:2266)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~99) - (DELAY - (ABSOLUTE - (PORT datab (1132:1132:1132) (1181:1181:1181)) - (PORT datac (2344:2344:2344) (2478:2478:2478)) - (PORT datad (1350:1350:1350) (1398:1398:1398)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1455:1455:1455)) - (PORT datab (404:404:404) (424:424:424)) - (PORT datac (556:556:556) (530:530:530)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (2075:2075:2075) (2058:2058:2058)) - (PORT datab (405:405:405) (421:421:421)) - (PORT datac (1118:1118:1118) (1162:1162:1162)) - (PORT datad (177:177:177) (200:200:200)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1713:1713:1713)) - (PORT datab (382:382:382) (409:409:409)) - (PORT datac (325:325:325) (335:335:335)) - (PORT datad (1048:1048:1048) (1025:1025:1025)) + (PORT dataa (360:360:360) (369:369:369)) + (PORT datab (811:811:811) (833:833:833)) + (PORT datad (299:299:299) (298:298:298)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT clk (1345:1345:1345) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT asdata (530:530:530) (596:596:596)) + (PORT sload (1164:1164:1164) (1223:1223:1223)) + (PORT ena (1772:1772:1772) (1740:1740:1740)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (226:226:226) (273:273:273)) - (PORT datac (531:531:531) (555:555:555)) - (PORT datad (197:197:197) (227:227:227)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (637:637:637) (638:638:638)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1787:1787:1787) (1726:1726:1726)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (144:144:144)) (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (INSTANCE z80_\|address_pins_\|abus\[9\]\~16) (DELAY (ABSOLUTE - (PORT dataa (699:699:699) (745:745:745)) - (PORT datac (1700:1700:1700) (1776:1776:1776)) - (PORT datad (1563:1563:1563) (1567:1567:1567)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (2001:2001:2001) (2097:2097:2097)) + (PORT datad (222:222:222) (282:282:282)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (1606:1606:1606) (1650:1650:1650)) - (PORT datab (1511:1511:1511) (1636:1636:1636)) - (PORT datac (954:954:954) (996:996:996)) - (PORT datad (1663:1663:1663) (1723:1723:1723)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (546:546:546)) - (PORT datab (239:239:239) (309:309:309)) - (PORT datac (576:576:576) (603:603:603)) - (PORT datad (1059:1059:1059) (1050:1050:1050)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1549:1549:1549) (1530:1530:1530)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (344:344:344) (385:385:385)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (702:702:702) (756:756:756)) - (PORT datad (283:283:283) (377:377:377)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (324:324:324) (338:338:338)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datad (786:786:786) (799:799:799)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT clk (1345:1345:1345) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1121:1121:1121) (1096:1096:1096)) + (PORT asdata (524:524:524) (594:594:594)) + (PORT sload (1164:1164:1164) (1223:1223:1223)) + (PORT ena (1772:1772:1772) (1740:1740:1740)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (784:784:784)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (1061:1061:1061) (1074:1074:1074)) - (PORT datad (1425:1425:1425) (1491:1491:1491)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1384:1384:1384) (1363:1363:1363)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (1708:1708:1708) (1760:1760:1760)) - (PORT clrn (1408:1408:1408) (1376:1376:1376)) - (PORT ena (906:906:906) (903:903:903)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (144:144:144)) (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~19) (DELAY (ABSOLUTE - (PORT dataa (311:311:311) (419:419:419)) - (PORT datab (264:264:264) (346:346:346)) - (PORT datad (230:230:230) (291:291:291)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2142:2142:2142) (2198:2198:2198)) - (PORT datab (1137:1137:1137) (1160:1160:1160)) - (PORT datac (1062:1062:1062) (1070:1070:1070)) - (PORT datad (1130:1130:1130) (1115:1115:1115)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datac (741:741:741) (752:752:752)) + (PORT datad (1976:1976:1976) (2058:2058:2058)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36636,2814 +32367,102 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (659:659:659) (652:652:652)) - (PORT datad (834:834:834) (839:839:839)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1376:1376:1376)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1422:1422:1422) (1460:1460:1460)) - (PORT datab (590:590:590) (585:585:585)) - (PORT datac (1153:1153:1153) (1148:1148:1148)) - (PORT datad (584:584:584) (580:580:580)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (550:550:550) (540:540:540)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (842:842:842)) - (PORT datab (591:591:591) (595:595:595)) - (PORT datac (776:776:776) (756:756:756)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (838:838:838)) - (PORT datab (1336:1336:1336) (1385:1385:1385)) - (PORT datac (546:546:546) (575:575:575)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (645:645:645)) - (PORT datab (797:797:797) (791:791:791)) - (PORT datac (794:794:794) (806:806:806)) - (PORT datad (925:925:925) (960:960:960)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1071:1071:1071)) - (PORT datab (1139:1139:1139) (1153:1153:1153)) - (PORT datac (1205:1205:1205) (1221:1221:1221)) - (PORT datad (1815:1815:1815) (1832:1832:1832)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (855:855:855)) - (PORT datab (1759:1759:1759) (1742:1742:1742)) - (PORT datac (1075:1075:1075) (1087:1087:1087)) - (PORT datad (771:771:771) (761:761:761)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (441:441:441)) - (PORT datab (948:948:948) (992:992:992)) - (PORT datac (1233:1233:1233) (1233:1233:1233)) - (PORT datad (992:992:992) (1011:1011:1011)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (221:221:221)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (162:162:162) (188:188:188)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (612:612:612)) - (PORT datab (1357:1357:1357) (1359:1359:1359)) - (PORT datac (1372:1372:1372) (1413:1413:1413)) - (PORT datad (1500:1500:1500) (1528:1528:1528)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (589:589:589)) - (PORT datab (194:194:194) (235:235:235)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (2745:2745:2745) (2716:2716:2716)) - (PORT datab (588:588:588) (621:621:621)) - (PORT datac (561:561:561) (570:570:570)) - (PORT datad (196:196:196) (219:219:219)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (429:429:429)) - (PORT datab (816:816:816) (830:830:830)) - (PORT datac (1032:1032:1032) (1026:1026:1026)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (567:567:567)) - (PORT datab (597:597:597) (618:618:618)) - (PORT datac (170:170:170) (207:207:207)) - (PORT datad (1059:1059:1059) (1032:1032:1032)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1076:1076:1076)) - (PORT datab (851:851:851) (849:849:849)) - (PORT datac (170:170:170) (210:210:210)) - (PORT datad (1056:1056:1056) (1066:1066:1066)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (819:819:819)) - (PORT datab (1494:1494:1494) (1454:1454:1454)) - (PORT datac (1040:1040:1040) (1067:1067:1067)) - (PORT datad (1307:1307:1307) (1317:1317:1317)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (817:817:817) (812:812:812)) - (PORT datac (606:606:606) (617:617:617)) - (PORT datad (1083:1083:1083) (1091:1091:1091)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (827:827:827)) - (PORT datab (1182:1182:1182) (1179:1179:1179)) - (PORT datac (606:606:606) (616:616:616)) - (PORT datad (1297:1297:1297) (1294:1294:1294)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1329:1329:1329)) - (PORT datab (1006:1006:1006) (1020:1020:1020)) - (PORT datac (607:607:607) (622:622:622)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (893:893:893)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (755:755:755) (749:749:749)) + (PORT datab (344:344:344) (356:356:356)) + (PORT datad (539:539:539) (544:544:544)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (607:607:607) (617:617:617)) - (PORT datac (572:572:572) (580:580:580)) - (PORT datad (579:579:579) (561:561:561)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1060:1060:1060)) - (PORT datab (883:883:883) (881:881:881)) - (PORT datac (561:561:561) (558:558:558)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (865:865:865)) - (PORT datab (631:631:631) (624:624:624)) - (PORT datac (888:888:888) (889:889:889)) - (PORT datad (1014:1014:1014) (977:977:977)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (1364:1364:1364) (1398:1398:1398)) - (PORT datac (939:939:939) (914:914:914)) - (PORT datad (475:475:475) (463:463:463)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (513:513:513)) - (PORT datac (901:901:901) (943:943:943)) - (PORT datad (573:573:573) (610:610:610)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (702:702:702) (768:768:768)) - (PORT datac (617:617:617) (646:646:646)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (389:389:389)) - (PORT datab (709:709:709) (764:764:764)) - (PORT datac (639:639:639) (677:677:677)) - (PORT datad (175:175:175) (206:206:206)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (777:777:777)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datad (557:557:557) (552:552:552)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (731:731:731)) - (PORT datac (866:866:866) (909:909:909)) - (PORT datad (840:840:840) (866:866:866)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (796:796:796)) - (PORT datab (602:602:602) (618:618:618)) - (PORT datac (835:835:835) (881:881:881)) - (PORT datad (242:242:242) (307:307:307)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (334:334:334)) - (PORT datab (862:862:862) (916:916:916)) - (PORT datac (855:855:855) (893:893:893)) - (PORT datad (688:688:688) (762:762:762)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (910:910:910)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) - (DELAY - (ABSOLUTE - (PORT datab (717:717:717) (789:789:789)) - (PORT datac (631:631:631) (671:671:671)) - (PORT datad (678:678:678) (742:742:742)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (365:365:365)) - (PORT datab (671:671:671) (714:714:714)) - (PORT datac (825:825:825) (860:860:860)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (357:357:357)) - (PORT datab (584:584:584) (608:608:608)) - (PORT datac (615:615:615) (643:643:643)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (720:720:720) (777:777:777)) - (PORT datab (380:380:380) (440:440:440)) - (PORT datad (864:864:864) (897:897:897)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1110:1110:1110)) - (PORT datab (587:587:587) (589:589:589)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1206:1206:1206)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datac (818:818:818) (814:814:814)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (1007:1007:1007)) - (PORT datac (781:781:781) (782:782:782)) - (PORT datad (655:655:655) (697:697:697)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT datab (684:684:684) (746:746:746)) - (PORT datac (1149:1149:1149) (1189:1189:1189)) - (PORT datad (888:888:888) (929:929:929)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (961:961:961) (1016:1016:1016)) - (PORT datac (689:689:689) (759:759:759)) - (PORT datad (172:172:172) (201:201:201)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (752:752:752)) - (PORT datac (900:900:900) (943:943:943)) - (PORT datad (600:600:600) (629:629:629)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (851:851:851)) - (PORT datab (826:826:826) (821:821:821)) - (PORT datad (161:161:161) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1354:1354:1354)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (355:355:355)) - (PORT datab (961:961:961) (1016:1016:1016)) - (PORT datac (644:644:644) (687:687:687)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (972:972:972)) - (PORT datab (859:859:859) (854:854:854)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1354:1354:1354)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1372:1372:1372) (1351:1351:1351)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1088:1088:1088)) - (PORT datab (654:654:654) (692:692:692)) - (PORT datac (194:194:194) (261:261:261)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1164:1164:1164)) - (PORT datac (908:908:908) (937:937:937)) - (PORT datad (605:605:605) (637:637:637)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (230:230:230)) - (PORT datab (209:209:209) (245:245:245)) - (PORT datac (642:642:642) (687:687:687)) - (PORT datad (186:186:186) (213:213:213)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (855:855:855) (853:853:853)) - (PORT datad (532:532:532) (533:533:533)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1008:1008:1008)) - (PORT datab (384:384:384) (445:445:445)) - (PORT datac (907:907:907) (946:946:946)) - (PORT datad (558:558:558) (593:593:593)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (361:361:361)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (618:618:618) (665:665:665)) - (PORT datad (587:587:587) (595:595:595)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (814:814:814)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (661:661:661) (700:700:700)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (579:579:579)) - (PORT datab (708:708:708) (740:740:740)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (292:292:292)) - (PORT datab (844:844:844) (835:835:835)) - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (1302:1302:1302) (1275:1275:1275)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1163:1163:1163)) - (PORT datab (1198:1198:1198) (1229:1229:1229)) - (PORT datac (636:636:636) (689:689:689)) - (PORT datad (665:665:665) (706:706:706)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1163:1163:1163)) - (PORT datac (908:908:908) (939:939:939)) - (PORT datad (607:607:607) (640:640:640)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (995:995:995)) - (PORT datab (881:881:881) (922:922:922)) - (PORT datac (829:829:829) (823:823:823)) - (PORT datad (664:664:664) (705:705:705)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (189:189:189) (225:225:225)) - (PORT datad (571:571:571) (566:566:566)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (518:518:518)) - (PORT datab (823:823:823) (843:843:843)) - (PORT datac (575:575:575) (569:569:569)) - (PORT datad (173:173:173) (201:201:201)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (899:899:899) (935:935:935)) - (PORT datad (426:426:426) (468:468:468)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1325:1325:1325) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1347:1347:1347)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (683:683:683)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datac (2240:2240:2240) (2343:2343:2343)) - (PORT datad (816:816:816) (829:829:829)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (811:811:811)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (317:317:317) (325:325:325)) - (PORT datad (568:568:568) (562:562:562)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1017:1017:1017)) - (PORT datab (1174:1174:1174) (1238:1238:1238)) - (PORT datac (2381:2381:2381) (2522:2522:2522)) - (PORT datad (591:591:591) (610:610:610)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1042:1042:1042) (1019:1019:1019)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2357:2357:2357) (2442:2442:2442)) - (PORT d[1] (3336:3336:3336) (3420:3420:3420)) - (PORT d[2] (2202:2202:2202) (2231:2231:2231)) - (PORT d[3] (3965:3965:3965) (4034:4034:4034)) - (PORT d[4] (2962:2962:2962) (3073:3073:3073)) - (PORT d[5] (4383:4383:4383) (4458:4458:4458)) - (PORT d[6] (2351:2351:2351) (2366:2366:2366)) - (PORT d[7] (1306:1306:1306) (1302:1302:1302)) - (PORT d[8] (2623:2623:2623) (2703:2703:2703)) - (PORT d[9] (1670:1670:1670) (1670:1670:1670)) - (PORT d[10] (1589:1589:1589) (1569:1569:1569)) - (PORT d[11] (3167:3167:3167) (3292:3292:3292)) - (PORT d[12] (4243:4243:4243) (4350:4350:4350)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1537:1537:1537) (1457:1457:1457)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (2039:2039:2039) (1990:1990:1990)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1127:1127:1127)) - (PORT datab (624:624:624) (639:639:639)) - (PORT datac (1279:1279:1279) (1297:1297:1297)) - (PORT datad (1023:1023:1023) (1003:1003:1003)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1067:1067:1067) (1036:1036:1036)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1576:1576:1576) (1645:1645:1645)) - (PORT d[1] (2620:2620:2620) (2622:2622:2622)) - (PORT d[2] (2223:2223:2223) (2247:2247:2247)) - (PORT d[3] (3945:3945:3945) (4013:4013:4013)) - (PORT d[4] (915:915:915) (923:923:923)) - (PORT d[5] (2071:2071:2071) (2042:2042:2042)) - (PORT d[6] (2352:2352:2352) (2367:2367:2367)) - (PORT d[7] (1272:1272:1272) (1253:1253:1253)) - (PORT d[8] (2598:2598:2598) (2673:2673:2673)) - (PORT d[9] (1375:1375:1375) (1381:1381:1381)) - (PORT d[10] (1831:1831:1831) (1806:1806:1806)) - (PORT d[11] (3168:3168:3168) (3293:3293:3293)) - (PORT d[12] (4317:4317:4317) (4436:4436:4436)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2336:2336:2336) (2311:2311:2311)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (2017:2017:2017) (1966:1966:1966)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (698:698:698) (696:696:696)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2838:2838:2838) (2996:2996:2996)) - (PORT d[1] (1508:1508:1508) (1531:1531:1531)) - (PORT d[2] (934:934:934) (950:950:950)) - (PORT d[3] (888:888:888) (904:904:904)) - (PORT d[4] (3026:3026:3026) (3104:3104:3104)) - (PORT d[5] (898:898:898) (906:906:906)) - (PORT d[6] (1459:1459:1459) (1521:1521:1521)) - (PORT d[7] (922:922:922) (916:916:916)) - (PORT d[8] (1178:1178:1178) (1202:1202:1202)) - (PORT d[9] (979:979:979) (1018:1018:1018)) - (PORT d[10] (949:949:949) (981:981:981)) - (PORT d[11] (2036:2036:2036) (2114:2114:2114)) - (PORT d[12] (993:993:993) (1043:1043:1043)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (874:874:874) (840:840:840)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2712:2712:2712) (2702:2702:2702)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (932:932:932) (934:934:934)) - (PORT clk (1637:1637:1637) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2790:2790:2790) (2941:2941:2941)) - (PORT d[1] (1498:1498:1498) (1524:1524:1524)) - (PORT d[2] (913:913:913) (916:916:916)) - (PORT d[3] (892:892:892) (900:900:900)) - (PORT d[4] (1340:1340:1340) (1312:1312:1312)) - (PORT d[5] (876:876:876) (874:874:874)) - (PORT d[6] (1721:1721:1721) (1778:1778:1778)) - (PORT d[7] (876:876:876) (859:859:859)) - (PORT d[8] (1180:1180:1180) (1212:1212:1212)) - (PORT d[9] (694:694:694) (731:731:731)) - (PORT d[10] (699:699:699) (735:735:735)) - (PORT d[11] (2339:2339:2339) (2427:2427:2427)) - (PORT d[12] (715:715:715) (755:755:755)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (625:625:625) (568:568:568)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (PORT d[0] (1616:1616:1616) (1566:1566:1566)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2102:2102:2102) (2181:2181:2181)) - (PORT d[1] (2597:2597:2597) (2596:2596:2596)) - (PORT d[2] (2218:2218:2218) (2248:2248:2248)) - (PORT d[3] (4206:4206:4206) (4271:4271:4271)) - (PORT d[4] (927:927:927) (942:942:942)) - (PORT d[5] (2031:2031:2031) (2008:2008:2008)) - (PORT d[6] (862:862:862) (853:853:853)) - (PORT d[7] (1244:1244:1244) (1208:1208:1208)) - (PORT d[8] (2616:2616:2616) (2693:2693:2693)) - (PORT d[9] (1362:1362:1362) (1368:1368:1368)) - (PORT d[10] (1840:1840:1840) (1825:1825:1825)) - (PORT d[11] (3447:3447:3447) (3579:3579:3579)) - (PORT d[12] (4343:4343:4343) (4457:4457:4457)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1668:1668:1668)) - (PORT d[0] (1180:1180:1180) (1227:1227:1227)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1835:1835:1835)) - (PORT datab (1402:1402:1402) (1431:1431:1431)) - (PORT datac (822:822:822) (820:820:820)) - (PORT datad (995:995:995) (971:971:971)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (846:846:846) (825:825:825)) - (PORT datac (1278:1278:1278) (1297:1297:1297)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1447:1447:1447)) - (PORT datab (1056:1056:1056) (1037:1037:1037)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1660:1660:1660) (1695:1695:1695)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1344:1344:1344) (1333:1333:1333)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2306:2306:2306) (2353:2353:2353)) - (PORT d[1] (2494:2494:2494) (2544:2544:2544)) - (PORT d[2] (2375:2375:2375) (2404:2404:2404)) - (PORT d[3] (3103:3103:3103) (3127:3127:3127)) - (PORT d[4] (2137:2137:2137) (2207:2207:2207)) - (PORT d[5] (3500:3500:3500) (3534:3534:3534)) - (PORT d[6] (2369:2369:2369) (2379:2379:2379)) - (PORT d[7] (3144:3144:3144) (3137:3137:3137)) - (PORT d[8] (2711:2711:2711) (2759:2759:2759)) - (PORT d[9] (2523:2523:2523) (2571:2571:2571)) - (PORT d[10] (2399:2399:2399) (2411:2411:2411)) - (PORT d[11] (2339:2339:2339) (2422:2422:2422)) - (PORT d[12] (3251:3251:3251) (3338:3338:3338)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2615:2615:2615) (2588:2588:2588)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (3167:3167:3167) (3168:3168:3168)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1603:1603:1603)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2266:2266:2266) (2211:2211:2211)) - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4159:4159:4159) (4029:4029:4029)) - (PORT d[1] (4126:4126:4126) (4092:4092:4092)) - (PORT d[2] (4226:4226:4226) (4086:4086:4086)) - (PORT d[3] (4078:4078:4078) (3991:3991:3991)) - (PORT d[4] (3967:3967:3967) (3947:3947:3947)) - (PORT d[5] (4071:4071:4071) (4018:4018:4018)) - (PORT d[6] (4131:4131:4131) (4004:4004:4004)) - (PORT d[7] (4068:4068:4068) (3937:3937:3937)) - (PORT d[8] (4094:4094:4094) (3992:3992:3992)) - (PORT d[9] (4102:4102:4102) (4037:4037:4037)) - (PORT d[10] (3964:3964:3964) (3840:3840:3840)) - (PORT d[11] (4072:4072:4072) (4007:4007:4007)) - (PORT d[12] (3962:3962:3962) (3828:3828:3828)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1604:1604:1604)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (2423:2423:2423) (2563:2563:2563)) - (PORT datab (2280:2280:2280) (2312:2312:2312)) - (PORT datac (1473:1473:1473) (1523:1523:1523)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1293:1293:1293) (1290:1290:1290)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1812:1812:1812) (1859:1859:1859)) - (PORT d[1] (2792:2792:2792) (2855:2855:2855)) - (PORT d[2] (1672:1672:1672) (1704:1704:1704)) - (PORT d[3] (3380:3380:3380) (3415:3415:3415)) - (PORT d[4] (2432:2432:2432) (2519:2519:2519)) - (PORT d[5] (3796:3796:3796) (3844:3844:3844)) - (PORT d[6] (2523:2523:2523) (2513:2513:2513)) - (PORT d[7] (1839:1839:1839) (1853:1853:1853)) - (PORT d[8] (1846:1846:1846) (1858:1858:1858)) - (PORT d[9] (2247:2247:2247) (2298:2298:2298)) - (PORT d[10] (2436:2436:2436) (2454:2454:2454)) - (PORT d[11] (2592:2592:2592) (2685:2685:2685)) - (PORT d[12] (4223:4223:4223) (4300:4300:4300)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1433:1433:1433) (1350:1350:1350)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (PORT d[0] (2912:2912:2912) (2902:2902:2902)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1597:1597:1597)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2021:2021:2021) (1977:1977:1977)) - (PORT clk (1606:1606:1606) (1604:1604:1604)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4221:4221:4221) (4140:4140:4140)) - (PORT d[1] (4122:4122:4122) (4082:4082:4082)) - (PORT d[2] (4157:4157:4157) (4016:4016:4016)) - (PORT d[3] (4095:4095:4095) (4027:4027:4027)) - (PORT d[4] (4038:4038:4038) (4034:4034:4034)) - (PORT d[5] (4048:4048:4048) (3978:3978:3978)) - (PORT d[6] (4136:4136:4136) (3984:3984:3984)) - (PORT d[7] (4049:4049:4049) (4017:4017:4017)) - (PORT d[8] (4171:4171:4171) (4059:4059:4059)) - (PORT d[9] (4241:4241:4241) (4151:4151:4151)) - (PORT d[10] (4000:4000:4000) (3918:3918:3918)) - (PORT d[11] (4113:4113:4113) (4055:4055:4055)) - (PORT d[12] (3967:3967:3967) (3843:3843:3843)) - (PORT clk (1603:1603:1603) (1601:1601:1601)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1604:1604:1604)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2303:2303:2303) (2346:2346:2346)) - (PORT d[1] (2206:2206:2206) (2246:2246:2246)) - (PORT d[2] (2103:2103:2103) (2172:2172:2172)) - (PORT d[3] (2018:2018:2018) (2076:2076:2076)) - (PORT d[4] (1940:1940:1940) (1972:1972:1972)) - (PORT d[5] (2231:2231:2231) (2282:2282:2282)) - (PORT d[6] (2255:2255:2255) (2335:2335:2335)) - (PORT d[7] (2921:2921:2921) (2945:2945:2945)) - (PORT d[8] (2652:2652:2652) (2670:2670:2670)) - (PORT d[9] (2175:2175:2175) (2285:2285:2285)) - (PORT d[10] (3045:3045:3045) (3068:3068:3068)) - (PORT d[11] (1960:1960:1960) (1984:1984:1984)) - (PORT d[12] (2103:2103:2103) (2205:2205:2205)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (2373:2373:2373) (2397:2397:2397)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1640:1640:1640)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (884:884:884) (887:887:887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (885:885:885) (888:888:888)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (885:885:885) (888:888:888)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (885:885:885) (888:888:888)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (2418:2418:2418) (2557:2557:2557)) - (PORT datab (2282:2282:2282) (2314:2314:2314)) - (PORT datac (1223:1223:1223) (1219:1219:1219)) - (PORT datad (1550:1550:1550) (1542:1542:1542)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1175:1175:1175)) - (PORT datab (679:679:679) (754:754:754)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1814:1814:1814) (1832:1832:1832)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1421:1421:1421)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (2562:2562:2562) (2558:2558:2558)) - (PORT datab (867:867:867) (908:908:908)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (1390:1390:1390) (1375:1375:1375)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (268:268:268)) - (PORT datab (797:797:797) (802:802:802)) - (PORT datac (581:581:581) (587:587:587)) - (PORT datad (1049:1049:1049) (1028:1028:1028)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE (PORT clk (1347:1347:1347) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT asdata (1122:1122:1122) (1144:1144:1144)) + (PORT sload (1592:1592:1592) (1649:1649:1649)) + (PORT ena (1313:1313:1313) (1291:1291:1291)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (INSTANCE z80_\|address_pins_\|abus\[11\]\~18) (DELAY (ABSOLUTE - (PORT datab (392:392:392) (396:396:396)) - (PORT datac (331:331:331) (382:382:382)) - (PORT datad (359:359:359) (366:366:366)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (610:610:610) (629:629:629)) + (PORT datac (1013:1013:1013) (1093:1093:1093)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) (DELAY (ABSOLUTE - (PORT dataa (1213:1213:1213) (1165:1165:1165)) - (PORT datab (349:349:349) (349:349:349)) - (PORT datac (757:757:757) (793:793:793)) - (PORT datad (526:526:526) (523:523:523)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (753:753:753) (750:750:750)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datad (550:550:550) (549:549:549)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT clk (1347:1347:1347) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1804:1804:1804) (1767:1767:1767)) + (PORT asdata (1086:1086:1086) (1104:1104:1104)) + (PORT sload (1592:1592:1592) (1649:1649:1649)) + (PORT ena (1313:1313:1313) (1291:1291:1291)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) (DELAY (ABSOLUTE - (PORT dataa (2069:2069:2069) (2089:2089:2089)) - (PORT datac (1451:1451:1451) (1528:1528:1528)) - (PORT datad (1564:1564:1564) (1582:1582:1582)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (777:777:777)) - (PORT datab (1721:1721:1721) (1751:1751:1751)) - (PORT datac (1054:1054:1054) (1054:1054:1054)) - (PORT datad (577:577:577) (593:593:593)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (609:609:609)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (1084:1084:1084) (1074:1074:1074)) - (PORT datad (795:795:795) (794:794:794)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT datac (1272:1272:1272) (1339:1339:1339)) + (PORT datad (215:215:215) (271:271:271)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (407:407:407)) - (PORT datab (558:558:558) (548:548:548)) - (PORT datad (1051:1051:1051) (1028:1028:1028)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1404:1404:1404) (1378:1378:1378)) - (PORT clk (1636:1636:1636) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2201:2201:2201) (2312:2312:2312)) - (PORT d[1] (2367:2367:2367) (2384:2384:2384)) - (PORT d[2] (1436:1436:1436) (1464:1464:1464)) - (PORT d[3] (1174:1174:1174) (1200:1200:1200)) - (PORT d[4] (1867:1867:1867) (1874:1874:1874)) - (PORT d[5] (1168:1168:1168) (1192:1192:1192)) - (PORT d[6] (1584:1584:1584) (1571:1571:1571)) - (PORT d[7] (2173:2173:2173) (2230:2230:2230)) - (PORT d[8] (2286:2286:2286) (2379:2379:2379)) - (PORT d[9] (957:957:957) (997:997:997)) - (PORT d[10] (1609:1609:1609) (1637:1637:1637)) - (PORT d[11] (1363:1363:1363) (1363:1363:1363)) - (PORT d[12] (932:932:932) (963:963:963)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1628:1628:1628) (1593:1593:1593)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1662:1662:1662)) - (PORT d[0] (1911:1911:1911) (1866:1866:1866)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1382:1382:1382) (1346:1346:1346)) + (PORT d[0] (1186:1186:1186) (1179:1179:1179)) (PORT clk (1638:1638:1638) (1666:1666:1666)) ) ) @@ -39456,19 +32475,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2176:2176:2176) (2275:2275:2275)) - (PORT d[1] (1846:1846:1846) (1859:1859:1859)) - (PORT d[2] (1717:1717:1717) (1728:1728:1728)) - (PORT d[3] (2057:2057:2057) (2080:2080:2080)) - (PORT d[4] (1887:1887:1887) (1883:1883:1883)) - (PORT d[5] (1467:1467:1467) (1502:1502:1502)) - (PORT d[6] (1597:1597:1597) (1593:1593:1593)) - (PORT d[7] (2104:2104:2104) (2135:2135:2135)) - (PORT d[8] (2298:2298:2298) (2401:2401:2401)) - (PORT d[9] (1095:1095:1095) (1110:1110:1110)) - (PORT d[10] (1527:1527:1527) (1530:1530:1530)) - (PORT d[11] (1117:1117:1117) (1121:1121:1121)) - (PORT d[12] (970:970:970) (1014:1014:1014)) + (PORT d[0] (1176:1176:1176) (1194:1194:1194)) + (PORT d[1] (1127:1127:1127) (1105:1105:1105)) + (PORT d[2] (1184:1184:1184) (1200:1200:1200)) + (PORT d[3] (2840:2840:2840) (2916:2916:2916)) + (PORT d[4] (1819:1819:1819) (1903:1903:1903)) + (PORT d[5] (1180:1180:1180) (1185:1185:1185)) + (PORT d[6] (1138:1138:1138) (1149:1149:1149)) + (PORT d[7] (1456:1456:1456) (1479:1479:1479)) + (PORT d[8] (1604:1604:1604) (1599:1599:1599)) + (PORT d[9] (1657:1657:1657) (1688:1688:1688)) + (PORT d[10] (2025:2025:2025) (2092:2092:2092)) + (PORT d[11] (1572:1572:1572) (1591:1591:1591)) + (PORT d[12] (1534:1534:1534) (1614:1614:1614)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -39481,7 +32500,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1413:1413:1413) (1390:1390:1390)) + (PORT d[0] (1871:1871:1871) (1846:1846:1846)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -39495,7 +32514,7 @@ (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (1800:1800:1800) (1759:1759:1759)) + (PORT d[0] (2389:2389:2389) (2335:2335:2335)) ) ) ) @@ -39591,13 +32610,254 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (486:486:486) (513:513:513)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (927:927:927) (954:954:954)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (2007:2007:2007)) + (PORT datab (929:929:929) (945:945:945)) + (PORT datac (1635:1635:1635) (1670:1670:1670)) + (PORT datad (199:199:199) (229:229:229)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1229:1229:1229)) + (PORT datab (1408:1408:1408) (1461:1461:1461)) + (PORT datad (1138:1138:1138) (1175:1175:1175)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1105:1105:1105) (1122:1122:1122)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2413:2413:2413) (2433:2433:2433)) + (PORT d[1] (2567:2567:2567) (2516:2516:2516)) + (PORT d[2] (2124:2124:2124) (2138:2138:2138)) + (PORT d[3] (798:798:798) (805:805:805)) + (PORT d[4] (2168:2168:2168) (2299:2299:2299)) + (PORT d[5] (2583:2583:2583) (2574:2574:2574)) + (PORT d[6] (3731:3731:3731) (3851:3851:3851)) + (PORT d[7] (1314:1314:1314) (1274:1274:1274)) + (PORT d[8] (1105:1105:1105) (1089:1089:1089)) + (PORT d[9] (866:866:866) (868:868:868)) + (PORT d[10] (897:897:897) (907:907:907)) + (PORT d[11] (2632:2632:2632) (2643:2643:2643)) + (PORT d[12] (1712:1712:1712) (1733:1733:1733)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2529:2529:2529) (2451:2451:2451)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (2729:2729:2729) (2620:2620:2620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (2002:2002:2002)) + (PORT datab (929:929:929) (946:946:946)) + (PORT datac (1637:1637:1637) (1666:1666:1666)) + (PORT datad (197:197:197) (225:225:225)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1410:1410:1410) (1466:1466:1466)) + (PORT datac (1130:1130:1130) (1193:1193:1193)) + (PORT datad (1138:1138:1138) (1173:1173:1173)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (853:853:853) (849:849:849)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (1124:1124:1124) (1079:1079:1079)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) ) ) (TIMINGCHECK @@ -39609,20 +32869,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2688:2688:2688) (2797:2797:2797)) - (PORT d[1] (3299:3299:3299) (3366:3366:3366)) - (PORT d[2] (1809:1809:1809) (1807:1807:1807)) - (PORT d[3] (3669:3669:3669) (3718:3718:3718)) - (PORT d[4] (2946:2946:2946) (3040:3040:3040)) - (PORT d[5] (4355:4355:4355) (4410:4410:4410)) - (PORT d[6] (2058:2058:2058) (2055:2055:2055)) - (PORT d[7] (1565:1565:1565) (1567:1567:1567)) - (PORT d[8] (2881:2881:2881) (2970:2970:2970)) - (PORT d[9] (1680:1680:1680) (1708:1708:1708)) - (PORT d[10] (1874:1874:1874) (1868:1868:1868)) - (PORT d[11] (2860:2860:2860) (2960:2960:2960)) - (PORT d[12] (4231:4231:4231) (4317:4317:4317)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (2980:2980:2980) (3025:3025:3025)) + (PORT d[1] (2896:2896:2896) (2878:2878:2878)) + (PORT d[2] (3661:3661:3661) (3717:3717:3717)) + (PORT d[3] (1368:1368:1368) (1375:1375:1375)) + (PORT d[4] (2460:2460:2460) (2590:2590:2590)) + (PORT d[5] (2977:2977:2977) (2995:2995:2995)) + (PORT d[6] (3436:3436:3436) (3566:3566:3566)) + (PORT d[7] (1579:1579:1579) (1569:1569:1569)) + (PORT d[8] (3624:3624:3624) (3722:3722:3722)) + (PORT d[9] (3871:3871:3871) (4010:4010:4010)) + (PORT d[10] (3542:3542:3542) (3696:3696:3696)) + (PORT d[11] (1092:1092:1092) (1102:1102:1102)) + (PORT d[12] (2489:2489:2489) (2639:2639:2639)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -39634,8 +32894,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2096:2096:2096) (2055:2055:2055)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1674:1674:1674) (1669:1669:1669)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -39647,8 +32907,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (2290:2290:2290) (2277:2277:2277)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2181:2181:2181) (2128:2128:2128)) ) ) ) @@ -39657,7 +32917,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -39667,7 +32927,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -39677,7 +32937,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -39687,7 +32947,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -39695,159 +32955,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1099:1099:1099) (1095:1095:1095)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2383:2383:2383) (2472:2472:2472)) - (PORT d[1] (3359:3359:3359) (3442:3442:3442)) - (PORT d[2] (1949:1949:1949) (1966:1966:1966)) - (PORT d[3] (3931:3931:3931) (3992:3992:3992)) - (PORT d[4] (2976:2976:2976) (3087:3087:3087)) - (PORT d[5] (4330:4330:4330) (4401:4401:4401)) - (PORT d[6] (2382:2382:2382) (2392:2392:2392)) - (PORT d[7] (1319:1319:1319) (1315:1315:1315)) - (PORT d[8] (2899:2899:2899) (2987:2987:2987)) - (PORT d[9] (1691:1691:1691) (1714:1714:1714)) - (PORT d[10] (1845:1845:1845) (1833:1833:1833)) - (PORT d[11] (3152:3152:3152) (3266:3266:3266)) - (PORT d[12] (4216:4216:4216) (4313:4313:4313)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1457:1457:1457) (1373:1373:1373)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (2270:2270:2270) (2199:2199:2199)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1610:1610:1610) (1638:1638:1638)) @@ -39861,7 +32968,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (881:881:881) (885:885:885)) @@ -39870,7 +32977,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE (PORT clk (882:882:882) (886:886:886)) @@ -39879,7 +32986,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (882:882:882) (886:886:886)) @@ -39889,7 +32996,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (882:882:882) (886:886:886)) @@ -39899,59 +33006,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (779:779:779) (760:760:760)) - (PORT datab (1091:1091:1091) (1126:1126:1126)) - (PORT datac (1099:1099:1099) (1136:1136:1136)) - (PORT datad (1020:1020:1020) (1007:1007:1007)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) + (PORT datac (176:176:176) (208:208:208)) (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1153:1153:1153) (1189:1189:1189)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1840:1840:1840) (1858:1858:1858)) + (PORT datab (1180:1180:1180) (1192:1192:1192)) + (PORT datac (855:855:855) (891:891:891)) + (PORT datad (1548:1548:1548) (1547:1547:1547)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1141:1141:1141) (1152:1152:1152)) - (PORT datab (1175:1175:1175) (1207:1207:1207)) - (PORT datac (1604:1604:1604) (1633:1633:1633)) - (PORT datad (288:288:288) (295:295:295)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (2429:2429:2429) (2458:2458:2458)) - (PORT datab (1787:1787:1787) (1873:1873:1873)) - (PORT datac (2570:2570:2570) (2672:2672:2672)) - (PORT datad (2050:2050:2050) (2018:2018:2018)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (1303:1303:1303) (1372:1372:1372)) + (PORT datac (220:220:220) (290:290:290)) + (PORT datad (820:820:820) (846:846:846)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1469:1469:1469) (1503:1503:1503)) - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT d[0] (1206:1206:1206) (1201:1201:1201)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -39960,23 +33087,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2950:2950:2950) (3064:3064:3064)) - (PORT d[1] (3083:3083:3083) (3147:3147:3147)) - (PORT d[2] (2082:2082:2082) (2097:2097:2097)) - (PORT d[3] (3366:3366:3366) (3402:3402:3402)) - (PORT d[4] (2716:2716:2716) (2817:2817:2817)) - (PORT d[5] (4045:4045:4045) (4092:4092:4092)) - (PORT d[6] (1651:1651:1651) (1654:1654:1654)) - (PORT d[7] (1827:1827:1827) (1834:1834:1834)) - (PORT d[8] (1862:1862:1862) (1872:1872:1872)) - (PORT d[9] (1954:1954:1954) (1990:1990:1990)) - (PORT d[10] (2156:2156:2156) (2163:2163:2163)) - (PORT d[11] (2599:2599:2599) (2694:2694:2694)) - (PORT d[12] (3961:3961:3961) (4050:4050:4050)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (1684:1684:1684) (1695:1695:1695)) + (PORT d[1] (1884:1884:1884) (1862:1862:1862)) + (PORT d[2] (1217:1217:1217) (1227:1227:1227)) + (PORT d[3] (3080:3080:3080) (3179:3179:3179)) + (PORT d[4] (1826:1826:1826) (1911:1911:1911)) + (PORT d[5] (891:891:891) (900:900:900)) + (PORT d[6] (892:892:892) (902:902:902)) + (PORT d[7] (1121:1121:1121) (1131:1131:1131)) + (PORT d[8] (1606:1606:1606) (1595:1595:1595)) + (PORT d[9] (1669:1669:1669) (1694:1694:1694)) + (PORT d[10] (2322:2322:2322) (2413:2413:2413)) + (PORT d[11] (1859:1859:1859) (1889:1889:1889)) + (PORT d[12] (1541:1541:1541) (1611:1611:1611)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -39985,11 +33112,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1517:1517:1517) (1455:1455:1455)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (1709:1709:1709) (1677:1677:1677)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -39998,60 +33125,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (PORT d[0] (2606:2606:2606) (2582:2582:2582)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (2057:2057:2057) (2023:2023:2023)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1603:1603:1603) (1601:1601:1601)) + (PORT clk (1599:1599:1599) (1626:1626:1626)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40062,108 +33189,92 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2010:2010:2010) (1977:1977:1977)) - (PORT clk (1611:1611:1611) (1608:1608:1608)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4199:4199:4199) (4120:4120:4120)) - (PORT d[1] (4132:4132:4132) (4100:4100:4100)) - (PORT d[2] (4206:4206:4206) (4076:4076:4076)) - (PORT d[3] (4107:4107:4107) (4035:4035:4035)) - (PORT d[4] (4069:4069:4069) (4073:4073:4073)) - (PORT d[5] (4037:4037:4037) (3953:3953:3953)) - (PORT d[6] (4106:4106:4106) (3960:3960:3960)) - (PORT d[7] (4098:4098:4098) (4008:4008:4008)) - (PORT d[8] (4229:4229:4229) (4129:4129:4129)) - (PORT d[9] (4232:4232:4232) (4134:4134:4134)) - (PORT d[10] (4251:4251:4251) (4159:4159:4159)) - (PORT d[11] (4122:4122:4122) (4057:4057:4057)) - (PORT d[12] (4002:4002:4002) (3877:3877:3877)) - (PORT clk (1608:1608:1608) (1605:1605:1605)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (870:870:870) (873:873:873)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + (PORT clk (871:871:871) (874:874:874)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) + (PORT clk (871:871:871) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1612:1612:1612) (1609:1609:1609)) + (PORT clk (871:871:871) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (944:944:944)) + (PORT datab (1469:1469:1469) (1455:1455:1455)) + (PORT datac (1365:1365:1365) (1392:1392:1392)) + (PORT datad (1161:1161:1161) (1189:1189:1189)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1222:1222:1222)) + (PORT datab (1673:1673:1673) (1698:1698:1698)) + (PORT datac (1293:1293:1293) (1277:1277:1277)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1570:1570:1570) (1644:1644:1644)) - (PORT d[1] (1531:1531:1531) (1530:1530:1530)) - (PORT d[2] (2098:2098:2098) (2171:2171:2171)) - (PORT d[3] (1724:1724:1724) (1724:1724:1724)) - (PORT d[4] (2211:2211:2211) (2247:2247:2247)) - (PORT d[5] (2356:2356:2356) (2342:2342:2342)) - (PORT d[6] (1841:1841:1841) (1845:1845:1845)) - (PORT d[7] (1877:1877:1877) (1902:1902:1902)) - (PORT d[8] (1969:1969:1969) (2001:2001:2001)) - (PORT d[9] (1849:1849:1849) (1839:1839:1839)) - (PORT d[10] (1533:1533:1533) (1529:1529:1529)) - (PORT d[11] (4032:4032:4032) (4182:4182:4182)) - (PORT d[12] (1993:1993:1993) (1977:1977:1977)) + (PORT d[0] (2119:2119:2119) (2116:2116:2116)) + (PORT d[1] (2022:2022:2022) (1951:1951:1951)) + (PORT d[2] (1837:1837:1837) (1821:1821:1821)) + (PORT d[3] (1085:1085:1085) (1104:1104:1104)) + (PORT d[4] (2367:2367:2367) (2420:2420:2420)) + (PORT d[5] (2254:2254:2254) (2220:2220:2220)) + (PORT d[6] (3423:3423:3423) (3532:3532:3532)) + (PORT d[7] (1594:1594:1594) (1567:1567:1567)) + (PORT d[8] (1165:1165:1165) (1161:1161:1161)) + (PORT d[9] (1459:1459:1459) (1473:1473:1473)) + (PORT d[10] (1651:1651:1651) (1657:1657:1657)) + (PORT d[11] (1575:1575:1575) (1586:1586:1586)) + (PORT d[12] (1447:1447:1447) (1482:1482:1482)) (PORT clk (1642:1642:1642) (1670:1670:1670)) ) ) @@ -40177,7 +33288,7 @@ (DELAY (ABSOLUTE (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (1931:1931:1931) (1867:1867:1867)) + (PORT d[0] (1525:1525:1525) (1496:1496:1496)) ) ) ) @@ -40243,13 +33354,544 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (4067:4067:4067) (4107:4107:4107)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (1855:1855:1855) (1850:1850:1850)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (2006:2006:2006)) + (PORT datab (927:927:927) (943:943:943)) + (PORT datac (1634:1634:1634) (1668:1668:1668)) + (PORT datad (198:198:198) (227:227:227)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (619:619:619) (660:660:660)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (520:520:520)) + (PORT datab (1306:1306:1306) (1402:1402:1402)) + (PORT datac (1511:1511:1511) (1506:1506:1506)) + (PORT datad (248:248:248) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (765:765:765) (780:780:780)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1538:1538:1538) (1530:1530:1530)) + (PORT ena (1128:1128:1128) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (666:666:666) (707:707:707)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (765:765:765) (780:780:780)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1270:1270:1270) (1330:1330:1330)) + (PORT datad (664:664:664) (706:706:706)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (765:765:765) (780:780:780)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1366:1366:1366)) + (PORT datab (678:678:678) (730:730:730)) + (PORT datad (664:664:664) (707:707:707)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (765:765:765) (780:780:780)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1093:1093:1093)) + (PORT datab (1261:1261:1261) (1341:1341:1341)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT datab (584:584:584) (610:610:610)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1163:1163:1163)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (646:646:646)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (812:812:812) (798:798:798)) + (PORT ena (1128:1128:1128) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (783:783:783) (809:809:809)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (624:624:624) (630:630:630)) + (PORT ena (1128:1128:1128) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (620:620:620) (634:634:634)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1240:1240:1240) (1210:1210:1210)) + (PORT ena (1128:1128:1128) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (728:728:728)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (349:349:349)) + (PORT datac (565:565:565) (556:556:556)) + (PORT datad (853:853:853) (871:871:871)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (519:519:519)) + (PORT datab (1307:1307:1307) (1403:1403:1403)) + (PORT datac (1511:1511:1511) (1510:1510:1510)) + (PORT datad (251:251:251) (315:315:315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1301:1301:1301) (1255:1255:1255)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (745:745:745) (750:750:750)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (920:920:920)) + (PORT datac (300:300:300) (312:312:312)) + (PORT datad (325:325:325) (329:329:329)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1301:1301:1301) (1255:1255:1255)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (522:522:522)) + (PORT datab (1306:1306:1306) (1407:1407:1407)) + (PORT datac (1509:1509:1509) (1507:1507:1507)) + (PORT datad (251:251:251) (317:317:317)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (521:521:521)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (910:910:910) (854:854:854)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (303:303:303) (314:314:314)) + (PORT datad (854:854:854) (877:877:877)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1301:1301:1301) (1255:1255:1255)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (921:921:921)) + (PORT datad (323:323:323) (326:326:326)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1301:1301:1301) (1255:1255:1255)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1451:1451:1451) (1474:1474:1474)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1428:1428:1428) (1459:1459:1459)) + (PORT clk (1653:1653:1653) (1680:1680:1680)) ) ) (TIMINGCHECK @@ -40261,20 +33903,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1512:1512:1512) (1569:1569:1569)) - (PORT d[1] (2761:2761:2761) (2811:2811:2811)) - (PORT d[2] (2365:2365:2365) (2395:2395:2395)) - (PORT d[3] (3083:3083:3083) (3107:3107:3107)) - (PORT d[4] (2419:2419:2419) (2507:2507:2507)) - (PORT d[5] (3525:3525:3525) (3563:3563:3563)) - (PORT d[6] (2075:2075:2075) (2077:2077:2077)) - (PORT d[7] (3157:3157:3157) (3133:3133:3133)) - (PORT d[8] (2711:2711:2711) (2760:2760:2760)) - (PORT d[9] (2286:2286:2286) (2337:2337:2337)) - (PORT d[10] (2419:2419:2419) (2432:2432:2432)) - (PORT d[11] (2319:2319:2319) (2402:2402:2402)) - (PORT d[12] (4285:4285:4285) (4364:4364:4364)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (3423:3423:3423) (3440:3440:3440)) + (PORT d[1] (3983:3983:3983) (3994:3994:3994)) + (PORT d[2] (3023:3023:3023) (3038:3038:3038)) + (PORT d[3] (2919:2919:2919) (3028:3028:3028)) + (PORT d[4] (2947:2947:2947) (3078:3078:3078)) + (PORT d[5] (2837:2837:2837) (2925:2925:2925)) + (PORT d[6] (2832:2832:2832) (2926:2926:2926)) + (PORT d[7] (4052:4052:4052) (4062:4062:4062)) + (PORT d[8] (2772:2772:2772) (2824:2824:2824)) + (PORT d[9] (2568:2568:2568) (2677:2677:2677)) + (PORT d[10] (2535:2535:2535) (2683:2683:2683)) + (PORT d[11] (2210:2210:2210) (2265:2265:2265)) + (PORT d[12] (1896:1896:1896) (2017:2017:2017)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) ) ) (TIMINGCHECK @@ -40286,8 +33928,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2616:2616:2616) (2589:2589:2589)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (2058:2058:2058) (1998:1998:1998)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) ) ) (TIMINGCHECK @@ -40299,8 +33941,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (2893:2893:2893) (2895:2895:2895)) + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (PORT d[0] (4461:4461:4461) (4502:4502:4502)) ) ) ) @@ -40309,7 +33951,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -40319,7 +33961,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -40329,7 +33971,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -40339,7 +33981,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -40349,7 +33991,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) + (PORT clk (1612:1612:1612) (1610:1610:1610)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40363,8 +34005,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1797:1797:1797) (1757:1757:1757)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) + (PORT d[0] (1335:1335:1335) (1311:1311:1311)) + (PORT clk (1620:1620:1620) (1617:1617:1617)) ) ) (TIMINGCHECK @@ -40376,20 +34018,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4160:4160:4160) (4037:4037:4037)) - (PORT d[1] (4104:4104:4104) (4045:4045:4045)) - (PORT d[2] (4197:4197:4197) (4054:4054:4054)) - (PORT d[3] (3899:3899:3899) (3838:3838:3838)) - (PORT d[4] (3999:3999:3999) (3981:3981:3981)) - (PORT d[5] (4055:4055:4055) (3981:3981:3981)) - (PORT d[6] (4096:4096:4096) (3971:3971:3971)) - (PORT d[7] (3874:3874:3874) (3779:3779:3779)) - (PORT d[8] (4080:4080:4080) (3975:3975:3975)) - (PORT d[9] (4070:4070:4070) (3994:3994:3994)) - (PORT d[10] (3980:3980:3980) (3891:3891:3891)) - (PORT d[11] (4145:4145:4145) (4087:4087:4087)) - (PORT d[12] (4127:4127:4127) (3949:3949:3949)) - (PORT clk (1607:1607:1607) (1604:1604:1604)) + (PORT d[0] (3916:3916:3916) (3859:3859:3859)) + (PORT d[1] (3974:3974:3974) (3987:3987:3987)) + (PORT d[2] (3809:3809:3809) (3721:3721:3721)) + (PORT d[3] (3793:3793:3793) (3726:3726:3726)) + (PORT d[4] (3836:3836:3836) (3761:3761:3761)) + (PORT d[5] (4088:4088:4088) (4129:4129:4129)) + (PORT d[6] (4010:4010:4010) (4027:4027:4027)) + (PORT d[7] (4155:4155:4155) (4171:4171:4171)) + (PORT d[8] (3907:3907:3907) (3871:3871:3871)) + (PORT d[9] (3911:3911:3911) (3889:3889:3889)) + (PORT d[10] (3796:3796:3796) (3733:3733:3733)) + (PORT d[11] (3947:3947:3947) (3896:3896:3896)) + (PORT d[12] (3893:3893:3893) (3847:3847:3847)) + (PORT clk (1617:1617:1617) (1614:1614:1614)) ) ) (TIMINGCHECK @@ -40401,7 +34043,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) + (PORT clk (1620:1620:1620) (1617:1617:1617)) ) ) ) @@ -40410,7 +34052,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1621:1621:1621) (1618:1618:1618)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -40420,7 +34062,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1621:1621:1621) (1618:1618:1618)) (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) ) ) @@ -40430,7 +34072,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1621:1621:1621) (1618:1618:1618)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -40440,7 +34082,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1621:1621:1621) (1618:1618:1618)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -40450,7 +34092,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1603:1603:1603) (1601:1601:1601)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40464,20 +34106,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1544:1544:1544) (1606:1606:1606)) - (PORT d[1] (2499:2499:2499) (2543:2543:2543)) - (PORT d[2] (1955:1955:1955) (2002:2002:2002)) - (PORT d[3] (3077:3077:3077) (3098:3098:3098)) - (PORT d[4] (2136:2136:2136) (2206:2206:2206)) - (PORT d[5] (3465:3465:3465) (3498:3498:3498)) - (PORT d[6] (2348:2348:2348) (2357:2357:2357)) - (PORT d[7] (3181:3181:3181) (3148:3148:3148)) - (PORT d[8] (2706:2706:2706) (2753:2753:2753)) - (PORT d[9] (2552:2552:2552) (2610:2610:2610)) - (PORT d[10] (2154:2154:2154) (2163:2163:2163)) - (PORT d[11] (2306:2306:2306) (2384:2384:2384)) - (PORT d[12] (3248:3248:3248) (3331:3331:3331)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) + (PORT d[0] (2407:2407:2407) (2425:2425:2425)) + (PORT d[1] (2272:2272:2272) (2216:2216:2216)) + (PORT d[2] (2137:2137:2137) (2150:2150:2150)) + (PORT d[3] (834:834:834) (845:845:845)) + (PORT d[4] (2417:2417:2417) (2544:2544:2544)) + (PORT d[5] (2576:2576:2576) (2565:2565:2565)) + (PORT d[6] (3726:3726:3726) (3847:3847:3847)) + (PORT d[7] (1359:1359:1359) (1325:1325:1325)) + (PORT d[8] (1387:1387:1387) (1390:1390:1390)) + (PORT d[9] (1364:1364:1364) (1373:1373:1373)) + (PORT d[10] (615:615:615) (615:615:615)) + (PORT d[11] (2366:2366:2366) (2386:2386:2386)) + (PORT d[12] (1644:1644:1644) (1652:1652:1652)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) ) ) (TIMINGCHECK @@ -40489,8 +34131,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1675:1675:1675)) - (PORT d[0] (2384:2384:2384) (2376:2376:2376)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) + (PORT d[0] (983:983:983) (1023:1023:1023)) ) ) ) @@ -40499,7 +34141,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1676:1676:1676)) + (PORT clk (1632:1632:1632) (1662:1662:1662)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -40509,7 +34151,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1613:1613:1613) (1641:1641:1641)) + (PORT clk (1598:1598:1598) (1627:1627:1627)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40523,7 +34165,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (884:884:884) (888:888:888)) + (PORT clk (869:869:869) (874:874:874)) ) ) ) @@ -40532,7 +34174,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (885:885:885) (889:889:889)) + (PORT clk (870:870:870) (875:875:875)) ) ) ) @@ -40541,7 +34183,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (885:885:885) (889:889:889)) + (PORT clk (870:870:870) (875:875:875)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -40551,22 +34193,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (885:885:885) (889:889:889)) + (PORT clk (870:870:870) (875:875:875)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (INSTANCE Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1118:1118:1118) (1132:1132:1132)) - (PORT datab (670:670:670) (696:696:696)) - (PORT datac (1246:1246:1246) (1244:1244:1244)) - (PORT datad (1308:1308:1308) (1313:1313:1313)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (877:877:877) (924:924:924)) + (PORT datab (880:880:880) (917:917:917)) + (PORT datac (1554:1554:1554) (1527:1527:1527)) + (PORT datad (1296:1296:1296) (1295:1295:1295)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40574,48 +34216,277 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (645:645:645) (675:675:675)) - (PORT datab (1027:1027:1027) (982:982:982)) - (PORT datac (1436:1436:1436) (1461:1461:1461)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (1790:1790:1790) (1758:1758:1758)) + (PORT datab (1129:1129:1129) (1150:1150:1150)) + (PORT datac (1631:1631:1631) (1649:1649:1649)) + (PORT datad (1296:1296:1296) (1303:1303:1303)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1408:1408:1408) (1434:1434:1434)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3529:3529:3529) (3601:3601:3601)) + (PORT d[1] (3466:3466:3466) (3474:3474:3474)) + (PORT d[2] (3135:3135:3135) (3155:3155:3155)) + (PORT d[3] (3236:3236:3236) (3365:3365:3365)) + (PORT d[4] (3214:3214:3214) (3365:3365:3365)) + (PORT d[5] (2738:2738:2738) (2753:2753:2753)) + (PORT d[6] (2854:2854:2854) (2955:2955:2955)) + (PORT d[7] (4148:4148:4148) (4199:4199:4199)) + (PORT d[8] (3070:3070:3070) (3144:3144:3144)) + (PORT d[9] (3339:3339:3339) (3453:3453:3453)) + (PORT d[10] (2905:2905:2905) (3034:3034:3034)) + (PORT d[11] (2716:2716:2716) (2769:2769:2769)) + (PORT d[12] (2016:2016:2016) (2091:2091:2091)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2206:2206:2206) (2141:2141:2141)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (PORT d[0] (4848:4848:4848) (4850:4850:4850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1595:1595:1595)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1278:1278:1278) (1249:1249:1249)) + (PORT clk (1606:1606:1606) (1602:1602:1602)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3960:3960:3960) (3872:3872:3872)) + (PORT d[1] (3946:3946:3946) (3947:3947:3947)) + (PORT d[2] (3829:3829:3829) (3756:3756:3756)) + (PORT d[3] (3814:3814:3814) (3732:3732:3732)) + (PORT d[4] (3828:3828:3828) (3746:3746:3746)) + (PORT d[5] (3912:3912:3912) (3978:3978:3978)) + (PORT d[6] (3917:3917:3917) (4019:4019:4019)) + (PORT d[7] (3932:3932:3932) (3964:3964:3964)) + (PORT d[8] (3839:3839:3839) (3791:3791:3791)) + (PORT d[9] (3902:3902:3902) (3841:3841:3841)) + (PORT d[10] (3859:3859:3859) (3770:3770:3770)) + (PORT d[11] (3946:3946:3946) (3888:3888:3888)) + (PORT d[12] (3908:3908:3908) (3868:3868:3868)) + (PORT clk (1603:1603:1603) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1602:1602:1602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1409:1409:1409) (1418:1418:1418)) + (PORT datab (1073:1073:1073) (1101:1101:1101)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1434:1434:1434) (1403:1403:1403)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~116) + (INSTANCE D\[7\]\~36) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (898:898:898) (930:930:930)) - (PORT datad (568:568:568) (584:584:584)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1095:1095:1095) (1122:1122:1122)) + (PORT datab (1576:1576:1576) (1584:1584:1584)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~117) + (INSTANCE D\[7\]\~37) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1127:1127:1127)) - (PORT datab (2298:2298:2298) (2286:2286:2286)) - (PORT datac (1102:1102:1102) (1110:1110:1110)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (309:309:309) (326:326:326)) + (PORT dataa (619:619:619) (649:649:649)) + (PORT datab (2064:2064:2064) (2097:2097:2097)) + (PORT datac (1265:1265:1265) (1256:1256:1256)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (780:780:780) (777:777:777)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -40625,25 +34496,41 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (352:352:352)) - (PORT datab (386:386:386) (416:416:416)) - (PORT datac (1073:1073:1073) (1102:1102:1102)) - (PORT datad (1050:1050:1050) (1030:1030:1030)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (830:830:830) (805:805:805)) + (PORT datab (232:232:232) (284:284:284)) + (PORT datac (1361:1361:1361) (1363:1363:1363)) + (PORT datad (1939:1939:1939) (1937:1937:1937)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1076:1076:1076)) + (PORT datab (1472:1472:1472) (1587:1587:1587)) + (PORT datac (1351:1351:1351) (1353:1353:1353)) + (PORT datad (168:168:168) (193:193:193)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|data_pins_\|dout\[7\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT clk (1341:1341:1341) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -40654,16 +34541,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (INSTANCE z80_\|bus_control_\|db\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (392:392:392) (401:401:401)) - (PORT datac (549:549:549) (542:542:542)) - (PORT datad (219:219:219) (277:277:277)) - (IOPATH dataa combout (307:307:307) (280:280:280)) + (PORT dataa (216:216:216) (261:261:261)) + (PORT datab (247:247:247) (294:294:294)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (574:574:574) (602:602:602)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -40673,10 +34560,10 @@ (INSTANCE z80_\|ir_\|opcode\[7\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (618:618:618) (625:625:625)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1787:1787:1787) (1726:1726:1726)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1311:1311:1311) (1320:1320:1320)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (764:764:764) (771:771:771)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -40688,11 +34575,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT datac (1019:1019:1019) (1041:1041:1041)) - (PORT datad (1812:1812:1812) (1831:1831:1831)) + (PORT datab (894:894:894) (937:937:937)) + (PORT datac (620:620:620) (659:659:659)) + (PORT datad (1574:1574:1574) (1603:1603:1603)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40700,31 +34589,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) (DELAY (ABSOLUTE - (PORT dataa (2355:2355:2355) (2370:2370:2370)) - (PORT datab (1942:1942:1942) (1983:1983:1983)) - (PORT datac (2252:2252:2252) (2362:2362:2362)) - (PORT datad (1696:1696:1696) (1725:1725:1725)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1464:1464:1464) (1541:1541:1541)) + (PORT datab (1569:1569:1569) (1584:1584:1584)) + (PORT datac (1473:1473:1473) (1474:1474:1474)) + (PORT datad (2178:2178:2178) (2186:2186:2186)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1493:1493:1493) (1502:1502:1502)) - (PORT datab (533:533:533) (520:520:520)) - (PORT datac (782:782:782) (774:774:774)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (1500:1500:1500) (1503:1503:1503)) + (PORT datab (1975:1975:1975) (2000:2000:2000)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (2036:2036:2036) (2030:2030:2030)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40732,15 +34621,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (INSTANCE z80_\|execute_\|fIORead\~2) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (635:635:635)) - (PORT datab (792:792:792) (841:841:841)) - (PORT datac (1339:1339:1339) (1320:1320:1320)) - (PORT datad (1071:1071:1071) (1072:1072:1072)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (203:203:203) (241:241:241)) + (PORT datab (202:202:202) (238:238:238)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (829:829:829) (840:840:840)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40748,206 +34637,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (2120:2120:2120) (2150:2150:2150)) - (PORT datab (2017:2017:2017) (2098:2098:2098)) - (PORT datac (1096:1096:1096) (1146:1146:1146)) - (PORT datad (754:754:754) (807:807:807)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1384:1384:1384) (1355:1355:1355)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (753:753:753)) - (PORT datab (696:696:696) (740:740:740)) - (PORT datac (1686:1686:1686) (1771:1771:1771)) - (PORT datad (1553:1553:1553) (1559:1559:1559)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (910:910:910)) - (PORT datab (1090:1090:1090) (1109:1109:1109)) - (PORT datac (1747:1747:1747) (1755:1755:1755)) - (PORT datad (1325:1325:1325) (1301:1301:1301)) + (PORT dataa (1804:1804:1804) (1849:1849:1849)) + (PORT datab (1978:1978:1978) (2004:2004:2004)) + (PORT datac (1615:1615:1615) (1629:1629:1629)) + (PORT datad (2037:2037:2037) (2033:2033:2033)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (853:853:853) (842:842:842)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (889:889:889) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (INSTANCE z80_\|execute_\|fIORead\~3) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (605:605:605)) - (PORT datab (893:893:893) (909:909:909)) - (PORT datad (329:329:329) (374:374:374)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (861:861:861)) - (PORT datab (923:923:923) (949:949:949)) - (PORT datac (571:571:571) (578:578:578)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (605:605:605)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (1085:1085:1085) (1078:1078:1078)) - (PORT datad (791:791:791) (790:790:790)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1400:1400:1400) (1428:1428:1428)) - (PORT datab (1163:1163:1163) (1155:1155:1155)) - (PORT datac (1073:1073:1073) (1075:1075:1075)) - (PORT datad (1374:1374:1374) (1360:1360:1360)) + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1101:1101:1101) (1091:1091:1091)) + (PORT datad (165:165:165) (189:189:189)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (608:608:608) (608:608:608)) - (PORT datab (1349:1349:1349) (1324:1324:1324)) - (PORT datac (476:476:476) (460:460:460)) - (PORT datad (885:885:885) (911:911:911)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (836:836:836) (844:844:844)) + (PORT datab (638:638:638) (655:655:655)) + (PORT datac (1035:1035:1035) (1030:1030:1030)) + (PORT datad (560:560:560) (573:573:573)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT datac (837:837:837) (840:840:840)) - (PORT datad (569:569:569) (580:580:580)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (358:358:358) (362:362:362)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (492:492:492) (477:477:477)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (911:911:911)) - (PORT datab (862:862:862) (917:917:917)) - (PORT datac (227:227:227) (303:303:303)) - (PORT datad (243:243:243) (311:311:311)) + (PORT dataa (1679:1679:1679) (1680:1680:1680)) + (PORT datac (882:882:882) (904:904:904)) + (PORT datad (184:184:184) (208:208:208)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40955,88 +34699,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (INSTANCE z80_\|execute_\|setM1\~59) (DELAY (ABSOLUTE - (PORT datac (665:665:665) (725:725:725)) - (PORT datad (929:929:929) (969:969:969)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (944:944:944) (1025:1025:1025)) + (PORT datab (1599:1599:1599) (1565:1565:1565)) + (PORT datac (1494:1494:1494) (1599:1599:1599)) + (PORT datad (817:817:817) (818:818:818)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (INSTANCE z80_\|execute_\|setM1\~41) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (396:396:396)) - (PORT datab (313:313:313) (331:331:331)) - (PORT datac (682:682:682) (741:741:741)) - (PORT datad (541:541:541) (529:529:529)) + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (1021:1021:1021) (988:988:988)) + (PORT datad (544:544:544) (552:552:552)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (718:718:718) (754:754:754)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1327:1327:1327) (1346:1346:1346)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1370:1370:1370) (1350:1350:1350)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (377:377:377)) - (PORT datab (637:637:637) (662:662:662)) - (PORT datac (832:832:832) (856:856:856)) - (PORT datad (875:875:875) (915:915:915)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (749:749:749)) - (PORT datab (696:696:696) (757:757:757)) - (PORT datac (645:645:645) (686:686:686)) - (PORT datad (892:892:892) (918:918:918)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41044,285 +34731,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (INSTANCE z80_\|execute_\|ctl_mRead\~32) (DELAY (ABSOLUTE - (PORT datab (970:970:970) (1006:1006:1006)) - (PORT datad (168:168:168) (193:193:193)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (502:502:502) (496:496:496)) + (PORT datab (1368:1368:1368) (1410:1410:1410)) + (PORT datac (1126:1126:1126) (1168:1168:1168)) + (PORT datad (538:538:538) (544:544:544)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (INSTANCE z80_\|execute_\|ctl_mRead\~25) (DELAY (ABSOLUTE - (PORT dataa (610:610:610) (614:614:614)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (643:643:643) (685:685:685)) - (PORT datad (488:488:488) (477:477:477)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (338:338:338)) - (PORT datab (722:722:722) (759:759:759)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1327:1327:1327) (1346:1346:1346)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1370:1370:1370) (1350:1350:1350)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (292:292:292)) - (PORT datab (879:879:879) (894:894:894)) - (PORT datac (735:735:735) (725:725:725)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (510:510:510)) - (PORT datab (928:928:928) (966:966:966)) - (PORT datac (612:612:612) (646:646:646)) - (PORT datad (577:577:577) (610:610:610)) + (PORT dataa (857:857:857) (890:890:890)) + (PORT datab (221:221:221) (269:269:269)) + (PORT datac (1428:1428:1428) (1424:1424:1424)) + (PORT datad (602:602:602) (616:616:616)) (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1199:1199:1199)) + (PORT datab (1593:1593:1593) (1595:1595:1595)) + (PORT datac (335:335:335) (345:345:345)) + (PORT datad (1126:1126:1126) (1171:1171:1171)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (INSTANCE z80_\|execute_\|ctl_mRead\~27) (DELAY (ABSOLUTE - (PORT dataa (449:449:449) (510:510:510)) - (PORT datac (693:693:693) (744:744:744)) - (PORT datad (357:357:357) (405:405:405)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (996:996:996)) - (PORT datac (829:829:829) (824:824:824)) - (PORT datad (664:664:664) (705:705:705)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (185:185:185) (218:218:218)) - (PORT datad (539:539:539) (529:529:529)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (556:556:556)) - (PORT datab (970:970:970) (1006:1006:1006)) - (PORT datac (659:659:659) (718:718:718)) - (PORT datad (168:168:168) (193:193:193)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (234:234:234)) - (PORT datab (526:526:526) (514:514:514)) + (PORT dataa (803:803:803) (793:793:793)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1041:1041:1041) (1058:1058:1058)) (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (256:256:256)) - (PORT datab (206:206:206) (242:242:242)) - (PORT datac (858:858:858) (870:870:870)) - (PORT datad (576:576:576) (591:591:591)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) + (INSTANCE z80_\|execute_\|ctl_mRead\~30) (DELAY (ABSOLUTE - (PORT dataa (671:671:671) (719:719:719)) - (PORT datab (932:932:932) (990:990:990)) - (PORT datac (889:889:889) (928:928:928)) - (PORT datad (537:537:537) (535:535:535)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1267:1267:1267)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1373:1373:1373) (1354:1354:1354)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (599:599:599) (630:630:630)) - (PORT datac (909:909:909) (950:950:950)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (733:733:733)) - (PORT datab (897:897:897) (940:940:940)) - (PORT datac (681:681:681) (747:747:747)) - (PORT datad (841:841:841) (869:869:869)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (374:374:374) (393:393:393)) + (PORT datab (1077:1077:1077) (1091:1091:1091)) + (PORT datac (1057:1057:1057) (1049:1049:1049)) + (PORT datad (604:604:604) (637:637:637)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41330,244 +34811,131 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~69) + (INSTANCE z80_\|execute_\|ctl_mRead\~31) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (516:516:516)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (868:868:868) (906:906:906)) - (PORT datad (175:175:175) (204:204:204)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (911:911:911) (924:924:924)) + (PORT datac (1307:1307:1307) (1291:1291:1291)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1232:1232:1232) (1204:1204:1204)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (812:812:812)) - (PORT datab (183:183:183) (214:214:214)) - (PORT datac (560:560:560) (552:552:552)) - (PORT datad (664:664:664) (700:700:700)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (390:390:390) (448:448:448)) - (PORT datac (675:675:675) (743:743:743)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (1007:1007:1007)) - (PORT datab (555:555:555) (590:590:590)) - (PORT datac (912:912:912) (950:950:950)) - (PORT datad (564:564:564) (596:596:596)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~71) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (626:626:626)) - (PORT datab (699:699:699) (738:738:738)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (237:237:237) (305:305:305)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (221:221:221)) - (PORT datab (697:697:697) (726:726:726)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) (DELAY (ABSOLUTE - (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT clk (1347:1347:1347) (1364:1364:1364)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1364:1364:1364) (1345:1345:1345)) + (PORT clrn (1379:1379:1379) (1353:1353:1353)) + (PORT ena (1844:1844:1844) (1829:1829:1829)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1374:1374:1374) (1400:1400:1400)) - (PORT datac (2108:2108:2108) (2239:2239:2239)) - (PORT datad (815:815:815) (836:836:836)) + (PORT datad (916:916:916) (960:960:960)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1358:1358:1358)) + (PORT ena (1335:1335:1335) (1313:1313:1313)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1022:1022:1022) (1043:1043:1043)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1348:1348:1348)) + (PORT ena (1445:1445:1445) (1437:1437:1437)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (202:202:202) (271:271:271)) + (PORT datad (1020:1020:1020) (1044:1044:1044)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (551:551:551)) + (PORT datab (1074:1074:1074) (1094:1094:1094)) + (PORT datac (1045:1045:1045) (1086:1086:1086)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (716:716:716)) - (PORT datac (890:890:890) (927:927:927)) - (PORT datad (538:538:538) (533:533:533)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1270:1270:1270)) - (PORT datab (933:933:933) (989:989:989)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1373:1373:1373) (1354:1354:1354)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (671:671:671) (713:713:713)) - (PORT datac (826:826:826) (864:864:864)) - (PORT datad (180:180:180) (212:212:212)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1270:1270:1270)) - (PORT datab (887:887:887) (883:883:883)) - (PORT datad (556:556:556) (540:540:540)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1373:1373:1373) (1354:1354:1354)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (2590:2590:2590) (2690:2690:2690)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41575,26 +34943,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) + (INSTANCE Equal5\~1) (DELAY (ABSOLUTE - (PORT dataa (847:847:847) (836:836:836)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (2187:2187:2187) (2316:2316:2316)) - (PORT datad (574:574:574) (567:567:567)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (1152:1152:1152) (1215:1215:1215)) + (PORT datab (1073:1073:1073) (1067:1067:1067)) + (PORT datac (1047:1047:1047) (1040:1040:1040)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1125:1125:1125) (1122:1122:1122)) + (PORT d[0] (1130:1130:1130) (1137:1137:1137)) (PORT clk (1630:1630:1630) (1658:1658:1658)) ) ) @@ -41604,22 +34970,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2491:2491:2491) (2624:2624:2624)) - (PORT d[1] (2663:2663:2663) (2681:2681:2681)) - (PORT d[2] (947:947:947) (954:954:954)) - (PORT d[3] (906:906:906) (926:926:926)) - (PORT d[4] (1903:1903:1903) (1925:1925:1925)) - (PORT d[5] (902:902:902) (914:914:914)) - (PORT d[6] (1575:1575:1575) (1568:1568:1568)) - (PORT d[7] (2453:2453:2453) (2523:2523:2523)) - (PORT d[8] (2303:2303:2303) (2408:2408:2408)) - (PORT d[9] (697:697:697) (722:722:722)) - (PORT d[10] (689:689:689) (715:715:715)) - (PORT d[11] (2616:2616:2616) (2714:2714:2714)) - (PORT d[12] (400:400:400) (421:421:421)) + (PORT d[0] (928:928:928) (928:928:928)) + (PORT d[1] (1180:1180:1180) (1189:1189:1189)) + (PORT d[2] (937:937:937) (946:946:946)) + (PORT d[3] (2560:2560:2560) (2626:2626:2626)) + (PORT d[4] (1165:1165:1165) (1182:1182:1182)) + (PORT d[5] (1985:1985:1985) (2009:2009:2009)) + (PORT d[6] (853:853:853) (844:844:844)) + (PORT d[7] (870:870:870) (885:885:885)) + (PORT d[8] (1065:1065:1065) (1051:1051:1051)) + (PORT d[9] (1388:1388:1388) (1408:1408:1408)) + (PORT d[10] (1806:1806:1806) (1896:1896:1896)) + (PORT d[11] (2112:2112:2112) (2146:2146:2146)) + (PORT d[12] (1258:1258:1258) (1317:1317:1317)) (PORT clk (1627:1627:1627) (1656:1656:1656)) ) ) @@ -41629,10 +34995,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1401:1401:1401) (1351:1351:1351)) + (PORT d[0] (1596:1596:1596) (1541:1541:1541)) (PORT clk (1627:1627:1627) (1656:1656:1656)) ) ) @@ -41642,17 +35008,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1630:1630:1630) (1658:1658:1658)) - (PORT d[0] (1328:1328:1328) (1280:1280:1280)) + (PORT d[0] (1815:1815:1815) (1778:1778:1778)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1631:1631:1631) (1659:1659:1659)) @@ -41662,7 +35028,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1631:1631:1631) (1659:1659:1659)) @@ -41672,7 +35038,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1631:1631:1631) (1659:1659:1659)) @@ -41682,7 +35048,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1631:1631:1631) (1659:1659:1659)) @@ -41692,7 +35058,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1594:1594:1594) (1622:1622:1622)) @@ -41706,7 +35072,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (865:865:865) (869:869:869)) @@ -41715,7 +35081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) (DELAY (ABSOLUTE (PORT clk (866:866:866) (870:870:870)) @@ -41724,7 +35090,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (866:866:866) (870:870:870)) @@ -41734,7 +35100,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (866:866:866) (870:870:870)) @@ -41742,12 +35108,6221 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1202:1202:1202) (1211:1211:1211)) + (PORT clk (1626:1626:1626) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (632:632:632) (637:637:637)) + (PORT d[1] (1189:1189:1189) (1192:1192:1192)) + (PORT d[2] (1232:1232:1232) (1254:1254:1254)) + (PORT d[3] (2297:2297:2297) (2381:2381:2381)) + (PORT d[4] (1170:1170:1170) (1189:1189:1189)) + (PORT d[5] (1961:1961:1961) (1991:1991:1991)) + (PORT d[6] (1740:1740:1740) (1793:1793:1793)) + (PORT d[7] (1131:1131:1131) (1132:1132:1132)) + (PORT d[8] (1300:1300:1300) (1283:1283:1283)) + (PORT d[9] (1399:1399:1399) (1429:1429:1429)) + (PORT d[10] (1839:1839:1839) (1929:1929:1929)) + (PORT d[11] (912:912:912) (948:948:948)) + (PORT d[12] (1272:1272:1272) (1344:1344:1344)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1628:1628:1628) (1590:1590:1590)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1626:1626:1626) (1655:1655:1655)) + (PORT d[0] (1956:1956:1956) (1900:1900:1900)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1619:1619:1619)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (861:861:861) (866:866:866)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1128:1128:1128) (1133:1133:1133)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (917:917:917) (927:927:927)) + (PORT d[1] (1176:1176:1176) (1165:1165:1165)) + (PORT d[2] (921:921:921) (938:938:938)) + (PORT d[3] (2287:2287:2287) (2357:2357:2357)) + (PORT d[4] (890:890:890) (901:901:901)) + (PORT d[5] (875:875:875) (866:866:866)) + (PORT d[6] (1710:1710:1710) (1758:1758:1758)) + (PORT d[7] (1125:1125:1125) (1125:1125:1125)) + (PORT d[8] (1313:1313:1313) (1279:1279:1279)) + (PORT d[9] (1621:1621:1621) (1649:1649:1649)) + (PORT d[10] (1728:1728:1728) (1796:1796:1796)) + (PORT d[11] (1138:1138:1138) (1174:1174:1174)) + (PORT d[12] (1226:1226:1226) (1279:1279:1279)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1627:1627:1627) (1577:1577:1577)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (2068:2068:2068) (2006:2006:2006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1169:1169:1169) (1184:1184:1184)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2686:2686:2686) (2716:2716:2716)) + (PORT d[1] (2603:2603:2603) (2567:2567:2567)) + (PORT d[2] (2421:2421:2421) (2442:2442:2442)) + (PORT d[3] (1819:1819:1819) (1825:1825:1825)) + (PORT d[4] (3197:3197:3197) (3357:3357:3357)) + (PORT d[5] (2852:2852:2852) (2848:2848:2848)) + (PORT d[6] (2679:2679:2679) (2809:2809:2809)) + (PORT d[7] (891:891:891) (898:898:898)) + (PORT d[8] (1349:1349:1349) (1336:1336:1336)) + (PORT d[9] (4162:4162:4162) (4309:4309:4309)) + (PORT d[10] (3865:3865:3865) (4033:4033:4033)) + (PORT d[11] (3346:3346:3346) (3461:3461:3461)) + (PORT d[12] (1309:1309:1309) (1297:1297:1297)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1827:1827:1827) (1742:1742:1742)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT d[0] (1253:1253:1253) (1210:1210:1210)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1150:1150:1150)) + (PORT datab (1378:1378:1378) (1397:1397:1397)) + (PORT datac (1461:1461:1461) (1452:1452:1452)) + (PORT datad (1244:1244:1244) (1220:1220:1220)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1291:1291:1291)) + (PORT datab (1188:1188:1188) (1225:1225:1225)) + (PORT datac (1800:1800:1800) (1828:1828:1828)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1224:1224:1224)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2471:2471:2471) (2514:2514:2514)) + (PORT d[1] (2077:2077:2077) (2106:2106:2106)) + (PORT d[2] (2543:2543:2543) (2591:2591:2591)) + (PORT d[3] (2650:2650:2650) (2693:2693:2693)) + (PORT d[4] (3424:3424:3424) (3567:3567:3567)) + (PORT d[5] (2748:2748:2748) (2795:2795:2795)) + (PORT d[6] (3032:3032:3032) (3087:3087:3087)) + (PORT d[7] (2511:2511:2511) (2574:2574:2574)) + (PORT d[8] (2171:2171:2171) (2204:2204:2204)) + (PORT d[9] (2460:2460:2460) (2552:2552:2552)) + (PORT d[10] (1875:1875:1875) (1971:1971:1971)) + (PORT d[11] (2189:2189:2189) (2246:2246:2246)) + (PORT d[12] (2038:2038:2038) (2142:2142:2142)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1883:1883:1883) (1856:1856:1856)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (PORT d[0] (3419:3419:3419) (3405:3405:3405)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1604:1604:1604)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1139:1139:1139) (1133:1133:1133)) + (PORT clk (1614:1614:1614) (1611:1611:1611)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3916:3916:3916) (3901:3901:3901)) + (PORT d[1] (3982:3982:3982) (4008:4008:4008)) + (PORT d[2] (3949:3949:3949) (3888:3888:3888)) + (PORT d[3] (3929:3929:3929) (3874:3874:3874)) + (PORT d[4] (3860:3860:3860) (3814:3814:3814)) + (PORT d[5] (3870:3870:3870) (3900:3900:3900)) + (PORT d[6] (3962:3962:3962) (4058:4058:4058)) + (PORT d[7] (3961:3961:3961) (3917:3917:3917)) + (PORT d[8] (3943:3943:3943) (3837:3837:3837)) + (PORT d[9] (3844:3844:3844) (3778:3778:3778)) + (PORT d[10] (3775:3775:3775) (3681:3681:3681)) + (PORT d[11] (3866:3866:3866) (3790:3790:3790)) + (PORT d[12] (4006:4006:4006) (3888:3888:3888)) + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1612:1612:1612)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1612:1612:1612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1612:1612:1612)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1612:1612:1612)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1804:1804:1804) (1777:1777:1777)) + (PORT d[1] (1473:1473:1473) (1423:1423:1423)) + (PORT d[2] (1317:1317:1317) (1311:1311:1311)) + (PORT d[3] (3238:3238:3238) (3322:3322:3322)) + (PORT d[4] (1945:1945:1945) (2005:2005:2005)) + (PORT d[5] (1812:1812:1812) (1793:1793:1793)) + (PORT d[6] (3173:3173:3173) (3283:3283:3283)) + (PORT d[7] (1596:1596:1596) (1573:1573:1573)) + (PORT d[8] (1194:1194:1194) (1203:1203:1203)) + (PORT d[9] (1218:1218:1218) (1240:1240:1240)) + (PORT d[10] (1137:1137:1137) (1144:1144:1144)) + (PORT d[11] (1602:1602:1602) (1614:1614:1614)) + (PORT d[12] (1436:1436:1436) (1473:1473:1473)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (1274:1274:1274) (1240:1240:1240)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1439:1439:1439) (1460:1460:1460)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2220:2220:2220) (2262:2262:2262)) + (PORT d[1] (2324:2324:2324) (2355:2355:2355)) + (PORT d[2] (2558:2558:2558) (2620:2620:2620)) + (PORT d[3] (2343:2343:2343) (2428:2428:2428)) + (PORT d[4] (3690:3690:3690) (3842:3842:3842)) + (PORT d[5] (2794:2794:2794) (2850:2850:2850)) + (PORT d[6] (2329:2329:2329) (2403:2403:2403)) + (PORT d[7] (2232:2232:2232) (2297:2297:2297)) + (PORT d[8] (1718:1718:1718) (1724:1724:1724)) + (PORT d[9] (3068:3068:3068) (3183:3183:3183)) + (PORT d[10] (1843:1843:1843) (1964:1964:1964)) + (PORT d[11] (2493:2493:2493) (2555:2555:2555)) + (PORT d[12] (1799:1799:1799) (1897:1897:1897)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1859:1859:1859) (1806:1806:1806)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (3121:3121:3121) (3128:3128:3128)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1599:1599:1599)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1072:1072:1072) (1045:1045:1045)) + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3809:3809:3809) (3791:3791:3791)) + (PORT d[1] (3872:3872:3872) (3831:3831:3831)) + (PORT d[2] (3938:3938:3938) (3915:3915:3915)) + (PORT d[3] (3917:3917:3917) (3887:3887:3887)) + (PORT d[4] (3983:3983:3983) (3966:3966:3966)) + (PORT d[5] (3968:3968:3968) (4122:4122:4122)) + (PORT d[6] (3933:3933:3933) (4023:4023:4023)) + (PORT d[7] (3937:3937:3937) (3906:3906:3906)) + (PORT d[8] (3924:3924:3924) (3811:3811:3811)) + (PORT d[9] (3932:3932:3932) (3848:3848:3848)) + (PORT d[10] (3943:3943:3943) (3912:3912:3912)) + (PORT d[11] (3902:3902:3902) (3841:3841:3841)) + (PORT d[12] (3902:3902:3902) (3843:3843:3843)) + (PORT clk (1605:1605:1605) (1603:1603:1603)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2134:2134:2134) (2142:2142:2142)) + (PORT d[1] (2071:2071:2071) (2008:2008:2008)) + (PORT d[2] (1853:1853:1853) (1851:1851:1851)) + (PORT d[3] (1059:1059:1059) (1068:1068:1068)) + (PORT d[4] (2387:2387:2387) (2450:2450:2450)) + (PORT d[5] (2275:2275:2275) (2252:2252:2252)) + (PORT d[6] (2937:2937:2937) (3058:3058:3058)) + (PORT d[7] (1337:1337:1337) (1309:1309:1309)) + (PORT d[8] (934:934:934) (943:943:943)) + (PORT d[9] (904:904:904) (920:920:920)) + (PORT d[10] (1639:1639:1639) (1655:1655:1655)) + (PORT d[11] (2086:2086:2086) (2097:2097:2097)) + (PORT d[12] (1161:1161:1161) (1200:1200:1200)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1527:1527:1527) (1548:1548:1548)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (923:923:923)) + (PORT datab (881:881:881) (914:914:914)) + (PORT datac (1331:1331:1331) (1345:1345:1345)) + (PORT datad (1473:1473:1473) (1456:1456:1456)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1373:1373:1373) (1367:1367:1367)) + (PORT datab (1072:1072:1072) (1103:1103:1103)) + (PORT datac (1543:1543:1543) (1614:1614:1614)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (768:768:768) (767:767:767)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (337:337:337)) + (PORT datab (247:247:247) (334:334:334)) + (PORT datad (239:239:239) (309:309:309)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2715:2715:2715) (2895:2895:2895)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (207:207:207) (270:270:270)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (264:264:264)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT asdata (512:512:512) (577:577:577)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (268:268:268)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (265:265:265)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (303:303:303)) + (PORT datab (229:229:229) (299:299:299)) + (PORT datac (202:202:202) (271:271:271)) + (PORT datad (206:206:206) (265:265:265)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (230:230:230) (302:302:302)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (206:206:206) (267:267:267)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (267:267:267)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (234:234:234)) + (PORT datad (208:208:208) (268:268:268)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (233:233:233)) + (PORT datac (199:199:199) (267:267:267)) + (PORT datad (204:204:204) (263:263:263)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1372:1372:1372)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1618:1618:1618) (1644:1644:1644)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (337:337:337)) + (PORT datab (383:383:383) (420:420:420)) + (PORT datad (226:226:226) (293:293:293)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1618:1618:1618) (1644:1644:1644)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (337:337:337)) + (PORT datab (247:247:247) (334:334:334)) + (PORT datad (227:227:227) (294:294:294)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1618:1618:1618) (1644:1644:1644)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (345:345:345)) + (PORT datab (250:250:250) (337:337:337)) + (PORT datad (227:227:227) (293:293:293)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1618:1618:1618) (1644:1644:1644)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (346:346:346)) + (PORT datab (248:248:248) (335:335:335)) + (PORT datad (225:225:225) (295:295:295)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (328:328:328)) + (PORT datab (242:242:242) (328:328:328)) + (PORT datac (2839:2839:2839) (3074:3074:3074)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (329:329:329)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (1031:1031:1031) (1082:1082:1082)) + (PORT datad (162:162:162) (184:184:184)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (2978:2978:2978) (3219:3219:3219)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (PORT ena (1090:1090:1090) (1047:1047:1047)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (329:329:329) (370:370:370)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (PORT ena (1090:1090:1090) (1047:1047:1047)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (548:548:548) (635:635:635)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (PORT ena (1090:1090:1090) (1047:1047:1047)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT asdata (1445:1445:1445) (1498:1498:1498)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (PORT ena (1117:1117:1117) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1311:1311:1311) (1300:1300:1300)) + (PORT clrn (1373:1373:1373) (1352:1352:1352)) + (PORT ena (892:892:892) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (953:953:953) (994:994:994)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (PORT ena (1090:1090:1090) (1047:1047:1047)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1353:1353:1353)) + (PORT asdata (969:969:969) (1034:1034:1034)) + (PORT clrn (1380:1380:1380) (1364:1364:1364)) + (PORT ena (1403:1403:1403) (1364:1364:1364)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT datab (637:637:637) (695:695:695)) + (PORT datac (634:634:634) (690:690:690)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1655:1655:1655) (1671:1671:1671)) + (PORT clrn (1373:1373:1373) (1352:1352:1352)) + (PORT ena (892:892:892) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (395:395:395) (434:434:434)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1352:1352:1352)) + (PORT ena (892:892:892) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (728:728:728)) + (PORT datab (886:886:886) (924:924:924)) + (PORT datac (641:641:641) (701:701:701)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (770:770:770)) + (PORT datab (1078:1078:1078) (1098:1098:1098)) + (PORT datac (229:229:229) (305:305:305)) + (PORT datad (639:639:639) (678:678:678)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (360:360:360)) + (PORT datab (394:394:394) (456:456:456)) + (PORT datad (1317:1317:1317) (1328:1328:1328)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datac (644:644:644) (689:689:689)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2877:2877:2877) (3107:3107:3107)) + (PORT datab (191:191:191) (228:228:228)) + (PORT datac (1028:1028:1028) (1078:1078:1078)) + (PORT datad (556:556:556) (545:545:545)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (332:332:332)) + (PORT datab (679:679:679) (712:712:712)) + (PORT datac (241:241:241) (331:331:331)) + (PORT datad (1318:1318:1318) (1330:1330:1330)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (763:763:763)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1050:1050:1050) (1066:1066:1066)) + (PORT datad (373:373:373) (422:422:422)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (722:722:722)) + (PORT datab (214:214:214) (253:253:253)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (PORT ena (1188:1188:1188) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (625:625:625) (682:682:682)) + (PORT datac (243:243:243) (335:335:335)) + (PORT datad (231:231:231) (293:293:293)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (764:764:764)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (570:570:570) (582:582:582)) + (PORT datad (645:645:645) (695:695:695)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (706:706:706)) + (PORT datab (640:640:640) (698:698:698)) + (PORT datad (575:575:575) (583:583:583)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (370:370:370)) + (PORT datab (335:335:335) (356:356:356)) + (PORT datad (415:415:415) (471:471:471)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (315:315:315)) + (PORT datab (627:627:627) (681:681:681)) + (PORT datac (241:241:241) (333:333:333)) + (PORT datad (230:230:230) (292:292:292)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (632:632:632)) + (PORT datab (641:641:641) (705:705:705)) + (PORT datac (321:321:321) (334:334:334)) + (PORT datad (336:336:336) (343:343:343)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (453:453:453) (509:509:509)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (296:296:296)) + (PORT datab (1586:1586:1586) (1606:1606:1606)) + (PORT datac (2051:2051:2051) (2152:2152:2152)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (692:692:692)) + (PORT datac (637:637:637) (694:694:694)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (356:356:356)) + (PORT datab (337:337:337) (359:359:359)) + (PORT datad (413:413:413) (475:475:475)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (906:906:906)) + (PORT datab (939:939:939) (992:992:992)) + (PORT datac (585:585:585) (601:601:601)) + (PORT datad (855:855:855) (893:893:893)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (959:959:959)) + (PORT datab (1189:1189:1189) (1220:1220:1220)) + (PORT datad (629:629:629) (673:673:673)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (646:646:646)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datad (563:563:563) (558:558:558)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (408:408:408)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datac (3526:3526:3526) (3661:3661:3661)) + (PORT datad (2959:2959:2959) (3010:3010:3010)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT datac (634:634:634) (680:680:680)) + (PORT datad (371:371:371) (420:420:420)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (936:936:936)) + (PORT datab (913:913:913) (946:946:946)) + (PORT datac (861:861:861) (898:898:898)) + (PORT datad (167:167:167) (192:192:192)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (941:941:941)) + (PORT datac (881:881:881) (911:911:911)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (707:707:707)) + (PORT datac (861:861:861) (897:897:897)) + (PORT datad (374:374:374) (421:421:421)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (688:688:688) (729:729:729)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (191:191:191) (220:220:220)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (363:363:363)) + (PORT datab (625:625:625) (677:677:677)) + (PORT datac (186:186:186) (224:224:224)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (749:749:749)) + (PORT datac (782:782:782) (793:793:793)) + (PORT datad (860:860:860) (917:917:917)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (958:958:958)) + (PORT datab (1188:1188:1188) (1218:1218:1218)) + (PORT datac (931:931:931) (988:988:988)) + (PORT datad (948:948:948) (1010:1010:1010)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (344:344:344)) + (PORT datab (683:683:683) (724:724:724)) + (PORT datad (839:839:839) (851:851:851)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (682:682:682) (736:736:736)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT datab (692:692:692) (780:780:780)) + (PORT datac (613:613:613) (648:648:648)) + (PORT datad (1321:1321:1321) (1333:1333:1333)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (724:724:724)) + (PORT datac (782:782:782) (788:788:788)) + (PORT datad (660:660:660) (717:717:717)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (341:341:341)) + (PORT datab (597:597:597) (586:586:586)) + (PORT datad (562:562:562) (569:569:569)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (324:324:324)) + (PORT datab (799:799:799) (837:837:837)) + (PORT datac (250:250:250) (334:334:334)) + (PORT datad (645:645:645) (697:697:697)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (989:989:989)) + (PORT datab (684:684:684) (713:713:713)) + (PORT datac (1000:1000:1000) (994:994:994)) + (PORT datad (658:658:658) (720:720:720)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (752:752:752)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datad (173:173:173) (201:201:201)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (846:846:846) (882:882:882)) + (PORT datac (616:616:616) (665:665:665)) + (PORT datad (671:671:671) (745:745:745)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (597:597:597)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datac (1385:1385:1385) (1398:1398:1398)) + (PORT datad (1860:1860:1860) (1874:1874:1874)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (1181:1181:1181) (1213:1213:1213)) + (PORT datad (625:625:625) (670:670:670)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (660:660:660)) + (PORT datab (371:371:371) (369:369:369)) + (PORT datac (552:552:552) (549:549:549)) + (PORT datad (887:887:887) (906:906:906)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (923:923:923) (959:959:959)) + (PORT datad (798:798:798) (783:783:783)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (767:767:767)) + (PORT datab (682:682:682) (712:712:712)) + (PORT datac (221:221:221) (293:293:293)) + (PORT datad (656:656:656) (713:713:713)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (340:340:340)) + (PORT datab (796:796:796) (830:830:830)) + (PORT datac (248:248:248) (330:330:330)) + (PORT datad (649:649:649) (700:700:700)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (275:275:275) (372:372:372)) + (PORT datab (631:631:631) (685:685:685)) + (PORT datac (186:186:186) (224:224:224)) + (PORT datad (1321:1321:1321) (1334:1334:1334)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (995:995:995)) + (PORT datab (564:564:564) (544:544:544)) + (PORT datad (551:551:551) (542:542:542)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (430:430:430)) + (PORT datab (1949:1949:1949) (2031:2031:2031)) + (PORT datac (1861:1861:1861) (1883:1883:1883)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (557:557:557) (566:566:566)) + (PORT datad (561:561:561) (568:568:568)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1543:1543:1543) (1580:1580:1580)) + (PORT datab (877:877:877) (949:949:949)) + (PORT datac (340:340:340) (358:358:358)) + (PORT datad (1014:1014:1014) (1024:1024:1024)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1427:1427:1427) (1460:1460:1460)) + (PORT datab (876:876:876) (951:951:951)) + (PORT datac (339:339:339) (357:357:357)) + (PORT datad (1011:1011:1011) (1021:1021:1021)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1351:1351:1351) (1374:1374:1374)) + (PORT datab (1557:1557:1557) (1507:1507:1507)) + (PORT datac (1317:1317:1317) (1309:1309:1309)) + (PORT datad (1405:1405:1405) (1475:1475:1475)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (924:924:924) (934:934:934)) + (PORT datac (301:301:301) (311:311:311)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (838:838:838)) + (PORT datab (1762:1762:1762) (1736:1736:1736)) + (PORT datac (173:173:173) (204:204:204)) + (PORT datad (618:618:618) (666:666:666)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1281:1281:1281)) + (PORT datab (316:316:316) (337:337:337)) + (PORT datac (1360:1360:1360) (1365:1365:1365)) + (PORT datad (205:205:205) (250:250:250)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1343:1343:1343) (1327:1327:1327)) + (PORT datac (212:212:212) (264:264:264)) + (PORT datad (986:986:986) (1006:1006:1006)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (877:877:877)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (358:358:358) (384:384:384)) + (PORT datad (220:220:220) (264:264:264)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1351:1351:1351)) + (PORT ena (1685:1685:1685) (1696:1696:1696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1243:1243:1243)) + (PORT datab (1535:1535:1535) (1696:1696:1696)) + (PORT datac (1124:1124:1124) (1208:1208:1208)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1028:1028:1028)) + (PORT datab (1298:1298:1298) (1305:1305:1305)) + (PORT datac (1503:1503:1503) (1604:1604:1604)) + (PORT datad (1694:1694:1694) (1699:1699:1699)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (771:771:771)) + (PORT datab (798:798:798) (791:791:791)) + (PORT datac (1036:1036:1036) (1053:1053:1053)) + (PORT datad (568:568:568) (559:559:559)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1080:1080:1080)) + (PORT datab (336:336:336) (358:358:358)) + (PORT datac (566:566:566) (596:596:596)) + (PORT datad (1088:1088:1088) (1096:1096:1096)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1357:1357:1357)) + (PORT ena (1834:1834:1834) (1793:1793:1793)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datac (839:839:839) (876:876:876)) + (PORT datad (1723:1723:1723) (1801:1801:1801)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (787:787:787)) + (PORT datab (233:233:233) (298:298:298)) + (PORT datac (641:641:641) (697:697:697)) + (PORT datad (229:229:229) (270:270:270)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1250:1250:1250)) + (PORT datab (590:590:590) (587:587:587)) + (PORT datac (1042:1042:1042) (1070:1070:1070)) + (PORT datad (1159:1159:1159) (1207:1207:1207)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1450:1450:1450) (1512:1512:1512)) + (PORT datac (817:817:817) (838:838:838)) + (PORT datad (1859:1859:1859) (1881:1881:1881)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT datab (651:651:651) (724:724:724)) + (PORT datad (658:658:658) (725:725:725)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (731:731:731)) + (PORT datab (236:236:236) (294:294:294)) + (PORT datac (755:755:755) (759:759:759)) + (PORT datad (233:233:233) (274:274:274)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (927:927:927)) + (PORT datab (587:587:587) (628:628:628)) + (PORT datad (1395:1395:1395) (1395:1395:1395)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (628:628:628)) + (PORT datab (540:540:540) (543:543:543)) + (PORT datac (812:812:812) (805:805:805)) + (PORT datad (751:751:751) (727:727:727)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (1423:1423:1423) (1493:1493:1493)) + (PORT datac (621:621:621) (650:650:650)) + (PORT datad (1069:1069:1069) (1040:1040:1040)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1062:1062:1062)) + (PORT datab (813:813:813) (810:810:810)) + (PORT datac (801:801:801) (826:826:826)) + (PORT datad (1053:1053:1053) (1032:1032:1032)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (802:802:802)) + (PORT datab (314:314:314) (334:334:334)) + (PORT datac (618:618:618) (629:629:629)) + (PORT datad (319:319:319) (319:319:319)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (535:535:535) (526:526:526)) + (PORT datad (196:196:196) (227:227:227)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (290:290:290)) + (PORT datab (844:844:844) (865:865:865)) + (PORT datac (1311:1311:1311) (1289:1289:1289)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (929:929:929) (934:934:934)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (945:945:945) (958:958:958)) + (PORT d[1] (979:979:979) (1001:1001:1001)) + (PORT d[2] (1193:1193:1193) (1211:1211:1211)) + (PORT d[3] (2025:2025:2025) (2098:2098:2098)) + (PORT d[4] (930:930:930) (935:935:935)) + (PORT d[5] (1693:1693:1693) (1720:1720:1720)) + (PORT d[6] (1468:1468:1468) (1514:1514:1514)) + (PORT d[7] (1138:1138:1138) (1150:1150:1150)) + (PORT d[8] (1301:1301:1301) (1292:1292:1292)) + (PORT d[9] (1336:1336:1336) (1356:1356:1356)) + (PORT d[10] (1542:1542:1542) (1623:1623:1623)) + (PORT d[11] (706:706:706) (710:710:710)) + (PORT d[12] (1234:1234:1234) (1301:1301:1301)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1384:1384:1384) (1340:1340:1340)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (1702:1702:1702) (1641:1641:1641)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (654:654:654) (645:645:645)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1200:1200:1200) (1220:1220:1220)) + (PORT d[1] (2056:2056:2056) (2107:2107:2107)) + (PORT d[2] (3399:3399:3399) (3500:3500:3500)) + (PORT d[3] (1767:1767:1767) (1831:1831:1831)) + (PORT d[4] (1191:1191:1191) (1221:1221:1221)) + (PORT d[5] (1682:1682:1682) (1702:1702:1702)) + (PORT d[6] (1212:1212:1212) (1235:1235:1235)) + (PORT d[7] (1433:1433:1433) (1454:1454:1454)) + (PORT d[8] (3291:3291:3291) (3370:3370:3370)) + (PORT d[9] (1894:1894:1894) (1942:1942:1942)) + (PORT d[10] (1677:1677:1677) (1729:1729:1729)) + (PORT d[11] (927:927:927) (951:951:951)) + (PORT d[12] (1512:1512:1512) (1587:1587:1587)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1358:1358:1358) (1306:1306:1306)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1611:1611:1611) (1559:1559:1559)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (2308:2308:2308) (2338:2338:2338)) + (PORT datac (621:621:621) (679:679:679)) + (PORT datad (1395:1395:1395) (1464:1464:1464)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1365:1365:1365)) + (PORT datab (1240:1240:1240) (1229:1229:1229)) + (PORT datac (599:599:599) (589:589:589)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (853:853:853)) + (PORT datab (1151:1151:1151) (1185:1185:1185)) + (PORT datac (865:865:865) (886:886:886)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (949:949:949) (954:954:954)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1197:1197:1197) (1219:1219:1219)) + (PORT d[1] (2065:2065:2065) (2124:2124:2124)) + (PORT d[2] (1182:1182:1182) (1198:1198:1198)) + (PORT d[3] (2015:2015:2015) (2064:2064:2064)) + (PORT d[4] (1184:1184:1184) (1206:1206:1206)) + (PORT d[5] (1143:1143:1143) (1157:1157:1157)) + (PORT d[6] (1414:1414:1414) (1453:1453:1453)) + (PORT d[7] (1397:1397:1397) (1415:1415:1415)) + (PORT d[8] (3294:3294:3294) (3376:3376:3376)) + (PORT d[9] (1897:1897:1897) (1947:1947:1947)) + (PORT d[10] (1500:1500:1500) (1566:1566:1566)) + (PORT d[11] (902:902:902) (922:922:922)) + (PORT d[12] (1240:1240:1240) (1309:1309:1309)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1321:1321:1321) (1257:1257:1257)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1823:1823:1823) (1770:1770:1770)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (918:918:918) (923:923:923)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1209:1209:1209) (1218:1218:1218)) + (PORT d[1] (2088:2088:2088) (2157:2157:2157)) + (PORT d[2] (1199:1199:1199) (1205:1205:1205)) + (PORT d[3] (2266:2266:2266) (2333:2333:2333)) + (PORT d[4] (1166:1166:1166) (1182:1182:1182)) + (PORT d[5] (1717:1717:1717) (1746:1746:1746)) + (PORT d[6] (1442:1442:1442) (1484:1484:1484)) + (PORT d[7] (1113:1113:1113) (1123:1123:1123)) + (PORT d[8] (3295:3295:3295) (3376:3376:3376)) + (PORT d[9] (1360:1360:1360) (1387:1387:1387)) + (PORT d[10] (1529:1529:1529) (1598:1598:1598)) + (PORT d[11] (914:914:914) (925:925:925)) + (PORT d[12] (1239:1239:1239) (1308:1308:1308)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1057:1057:1057)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (1843:1843:1843) (1799:1799:1799)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (858:858:858)) + (PORT datab (876:876:876) (873:873:873)) + (PORT datad (1344:1344:1344) (1338:1338:1338)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1499:1499:1499) (1563:1563:1563)) + (PORT datab (1841:1841:1841) (1820:1820:1820)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (294:294:294) (299:299:299)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2485:2485:2485) (2527:2527:2527)) + (PORT d[1] (2261:2261:2261) (2276:2276:2276)) + (PORT d[2] (2292:2292:2292) (2341:2341:2341)) + (PORT d[3] (2617:2617:2617) (2648:2648:2648)) + (PORT d[4] (3442:3442:3442) (3565:3565:3565)) + (PORT d[5] (2757:2757:2757) (2808:2808:2808)) + (PORT d[6] (2608:2608:2608) (2686:2686:2686)) + (PORT d[7] (2471:2471:2471) (2541:2541:2541)) + (PORT d[8] (2167:2167:2167) (2197:2197:2197)) + (PORT d[9] (2444:2444:2444) (2542:2542:2542)) + (PORT d[10] (1864:1864:1864) (1950:1950:1950)) + (PORT d[11] (2152:2152:2152) (2181:2181:2181)) + (PORT d[12] (1792:1792:1792) (1878:1878:1878)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (2583:2583:2583) (2585:2585:2585)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1639:1639:1639)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1402:1402:1402) (1417:1417:1417)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2247:2247:2247) (2291:2291:2291)) + (PORT d[1] (2304:2304:2304) (2335:2335:2335)) + (PORT d[2] (2829:2829:2829) (2890:2890:2890)) + (PORT d[3] (2586:2586:2586) (2665:2665:2665)) + (PORT d[4] (3690:3690:3690) (3843:3843:3843)) + (PORT d[5] (2183:2183:2183) (2216:2216:2216)) + (PORT d[6] (2322:2322:2322) (2390:2390:2390)) + (PORT d[7] (2195:2195:2195) (2259:2259:2259)) + (PORT d[8] (2453:2453:2453) (2498:2498:2498)) + (PORT d[9] (3076:3076:3076) (3201:3201:3201)) + (PORT d[10] (1855:1855:1855) (1945:1945:1945)) + (PORT d[11] (2506:2506:2506) (2570:2570:2570)) + (PORT d[12] (1745:1745:1745) (1842:1842:1842)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1618:1618:1618) (1584:1584:1584)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (3123:3123:3123) (3099:3099:3099)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1597:1597:1597) (1595:1595:1595)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1370:1370:1370) (1389:1389:1389)) + (PORT clk (1605:1605:1605) (1602:1602:1602)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3822:3822:3822) (3791:3791:3791)) + (PORT d[1] (3901:3901:3901) (3875:3875:3875)) + (PORT d[2] (3844:3844:3844) (3771:3771:3771)) + (PORT d[3] (3908:3908:3908) (3871:3871:3871)) + (PORT d[4] (3993:3993:3993) (3979:3979:3979)) + (PORT d[5] (3976:3976:3976) (4128:4128:4128)) + (PORT d[6] (4111:4111:4111) (4059:4059:4059)) + (PORT d[7] (3985:3985:3985) (3957:3957:3957)) + (PORT d[8] (3840:3840:3840) (3775:3775:3775)) + (PORT d[9] (3789:3789:3789) (3673:3673:3673)) + (PORT d[10] (3848:3848:3848) (3775:3775:3775)) + (PORT d[11] (3922:3922:3922) (3870:3870:3870)) + (PORT d[12] (4047:4047:4047) (3949:3949:3949)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1602:1602:1602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1180:1180:1180) (1186:1186:1186)) + (PORT d[1] (1930:1930:1930) (1907:1907:1907)) + (PORT d[2] (1238:1238:1238) (1252:1252:1252)) + (PORT d[3] (2313:2313:2313) (2397:2397:2397)) + (PORT d[4] (1170:1170:1170) (1190:1190:1190)) + (PORT d[5] (869:869:869) (868:868:868)) + (PORT d[6] (894:894:894) (898:898:898)) + (PORT d[7] (1114:1114:1114) (1123:1123:1123)) + (PORT d[8] (1308:1308:1308) (1301:1301:1301)) + (PORT d[9] (1133:1133:1133) (1137:1137:1137)) + (PORT d[10] (1839:1839:1839) (1930:1930:1930)) + (PORT d[11] (2084:2084:2084) (2100:2100:2100)) + (PORT d[12] (1278:1278:1278) (1353:1353:1353)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (PORT d[0] (1216:1216:1216) (1262:1262:1262)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1628:1628:1628) (1657:1657:1657)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1512:1512:1512) (1545:1545:1545)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2765:2765:2765) (2809:2809:2809)) + (PORT d[1] (1779:1779:1779) (1813:1813:1813)) + (PORT d[2] (2531:2531:2531) (2590:2590:2590)) + (PORT d[3] (3037:3037:3037) (3063:3063:3063)) + (PORT d[4] (3425:3425:3425) (3568:3568:3568)) + (PORT d[5] (2748:2748:2748) (2796:2796:2796)) + (PORT d[6] (2345:2345:2345) (2420:2420:2420)) + (PORT d[7] (2226:2226:2226) (2283:2283:2283)) + (PORT d[8] (2172:2172:2172) (2205:2205:2205)) + (PORT d[9] (2201:2201:2201) (2294:2294:2294)) + (PORT d[10] (1878:1878:1878) (1999:1999:1999)) + (PORT d[11] (2225:2225:2225) (2295:2295:2295)) + (PORT d[12] (1578:1578:1578) (1675:1675:1675)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1891:1891:1891) (1831:1831:1831)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (3129:3129:3129) (3134:3134:3134)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1603:1603:1603)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1091:1091:1091) (1098:1098:1098)) + (PORT clk (1612:1612:1612) (1610:1610:1610)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3834:3834:3834) (3814:3814:3814)) + (PORT d[1] (3959:3959:3959) (3986:3986:3986)) + (PORT d[2] (3970:3970:3970) (3939:3939:3939)) + (PORT d[3] (3961:3961:3961) (3930:3930:3930)) + (PORT d[4] (4075:4075:4075) (3984:3984:3984)) + (PORT d[5] (3984:3984:3984) (4160:4160:4160)) + (PORT d[6] (3905:3905:3905) (3998:3998:3998)) + (PORT d[7] (3983:3983:3983) (3964:3964:3964)) + (PORT d[8] (3881:3881:3881) (3786:3786:3786)) + (PORT d[9] (3762:3762:3762) (3653:3653:3653)) + (PORT d[10] (3756:3756:3756) (3662:3662:3662)) + (PORT d[11] (3932:3932:3932) (3881:3881:3881)) + (PORT d[12] (4043:4043:4043) (3916:3916:3916)) + (PORT clk (1609:1609:1609) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1604:1604:1604)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (668:668:668)) + (PORT datab (1132:1132:1132) (1153:1153:1153)) + (PORT datac (1097:1097:1097) (1111:1111:1111)) + (PORT datad (1140:1140:1140) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1470:1470:1470)) + (PORT datab (249:249:249) (325:325:325)) + (PORT datac (1346:1346:1346) (1352:1352:1352)) + (PORT datad (307:307:307) (310:310:310)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1351:1351:1351) (1364:1364:1364)) + (PORT datab (2325:2325:2325) (2343:2343:2343)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (302:302:302) (303:303:303)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1350:1350:1350)) + (PORT datab (1091:1091:1091) (1088:1088:1088)) + (PORT datac (851:851:851) (871:871:871)) + (PORT datad (303:303:303) (302:302:302)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (615:615:615)) + (PORT datab (231:231:231) (283:283:283)) + (PORT datac (1359:1359:1359) (1363:1363:1363)) + (PORT datad (1783:1783:1783) (1780:1780:1780)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (264:264:264)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1049:1049:1049) (1044:1044:1044)) + (PORT datad (222:222:222) (264:264:264)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (200:200:200)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1351:1351:1351)) + (PORT ena (1685:1685:1685) (1696:1696:1696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1266:1266:1266)) + (PORT datab (819:819:819) (826:826:826)) + (PORT datac (403:403:403) (459:459:459)) + (PORT datad (1090:1090:1090) (1099:1099:1099)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1224:1224:1224)) + (PORT datab (1320:1320:1320) (1333:1333:1333)) + (PORT datac (877:877:877) (914:914:914)) + (PORT datad (601:601:601) (598:598:598)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datac (830:830:830) (827:827:827)) + (PORT datad (1020:1020:1020) (1001:1001:1001)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (187:187:187) (220:220:220)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (1321:1321:1321) (1357:1357:1357)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1351:1351:1351) (1357:1357:1357)) + (PORT datab (1186:1186:1186) (1272:1272:1272)) + (PORT datac (1716:1716:1716) (1770:1770:1770)) + (PORT datad (1112:1112:1112) (1110:1110:1110)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (873:873:873)) + (PORT datab (189:189:189) (223:223:223)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1076:1076:1076) (1098:1098:1098)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1196:1196:1196)) + (PORT datab (1451:1451:1451) (1465:1465:1465)) + (PORT datac (1121:1121:1121) (1148:1148:1148)) + (PORT datad (1808:1808:1808) (1807:1807:1807)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (878:878:878)) + (PORT datab (1412:1412:1412) (1413:1413:1413)) + (PORT datac (1119:1119:1119) (1142:1142:1142)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1033:1033:1033)) + (PORT datab (1104:1104:1104) (1114:1114:1114)) + (PORT datac (857:857:857) (869:869:869)) + (PORT datad (844:844:844) (878:878:878)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1756:1756:1756) (1809:1809:1809)) + (PORT datab (1214:1214:1214) (1249:1249:1249)) + (PORT datac (858:858:858) (867:867:867)) + (PORT datad (1087:1087:1087) (1102:1102:1102)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (882:882:882) (921:921:921)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (935:935:935) (948:948:948)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2548:2548:2548) (2600:2600:2600)) + (PORT d[1] (1813:1813:1813) (1871:1871:1871)) + (PORT d[2] (3392:3392:3392) (3487:3487:3487)) + (PORT d[3] (1438:1438:1438) (1469:1469:1469)) + (PORT d[4] (1462:1462:1462) (1505:1505:1505)) + (PORT d[5] (1662:1662:1662) (1688:1688:1688)) + (PORT d[6] (2598:2598:2598) (2674:2674:2674)) + (PORT d[7] (1359:1359:1359) (1399:1399:1399)) + (PORT d[8] (3011:3011:3011) (3078:3078:3078)) + (PORT d[9] (1620:1620:1620) (1657:1657:1657)) + (PORT d[10] (1871:1871:1871) (1987:1987:1987)) + (PORT d[11] (2527:2527:2527) (2564:2564:2564)) + (PORT d[12] (1516:1516:1516) (1597:1597:1597)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (842:842:842) (784:784:784)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2076:2076:2076) (2032:2032:2032)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT datab (436:436:436) (479:479:479)) + (PORT datac (656:656:656) (722:722:722)) + (PORT datad (649:649:649) (696:696:696)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1157:1157:1157)) + (PORT datab (705:705:705) (753:753:753)) + (PORT datac (792:792:792) (820:820:820)) + (PORT datad (671:671:671) (708:708:708)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (685:685:685) (754:754:754)) + (PORT datac (782:782:782) (789:789:789)) + (PORT datad (838:838:838) (852:852:852)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (805:805:805)) + (PORT datad (338:338:338) (346:346:346)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1364:1364:1364)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (754:754:754)) + (PORT datab (280:280:280) (364:364:364)) + (PORT datac (772:772:772) (807:807:807)) + (PORT datad (388:388:388) (431:431:431)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (804:804:804) (841:841:841)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (641:641:641) (692:692:692)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (580:580:580)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (671:671:671)) + (PORT datab (1952:1952:1952) (2035:2035:2035)) + (PORT datac (1862:1862:1862) (1886:1886:1886)) + (PORT datad (584:584:584) (612:612:612)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (769:769:769)) + (PORT datab (886:886:886) (921:921:921)) + (PORT datac (640:640:640) (698:698:698)) + (PORT datad (1094:1094:1094) (1118:1118:1118)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (695:695:695)) + (PORT datac (633:633:633) (693:693:693)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (735:735:735)) + (PORT datab (185:185:185) (219:219:219)) + (PORT datac (570:570:570) (585:585:585)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT datab (840:840:840) (825:825:825)) + (PORT datad (911:911:911) (961:961:961)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (708:708:708)) + (PORT datad (866:866:866) (925:925:925)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (936:936:936)) + (PORT datab (685:685:685) (730:730:730)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (941:941:941)) + (PORT datac (881:881:881) (910:910:910)) + (PORT datad (649:649:649) (693:693:693)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (961:961:961)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (859:859:859) (901:901:901)) + (PORT datad (613:613:613) (655:655:655)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (465:465:465)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (572:572:572) (576:576:576)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (996:996:996)) + (PORT datad (291:291:291) (298:298:298)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (979:979:979)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datac (1573:1573:1573) (1602:1602:1602)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (956:956:956)) + (PORT datab (962:962:962) (1019:1019:1019)) + (PORT datac (1048:1048:1048) (1082:1082:1082)) + (PORT datad (836:836:836) (847:847:847)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (1189:1189:1189) (1220:1220:1220)) + (PORT datad (629:629:629) (673:673:673)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1052:1052:1052)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (840:840:840) (868:868:868)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1047:1047:1047)) + (PORT datab (1188:1188:1188) (1218:1218:1218)) + (PORT datac (895:895:895) (926:926:926)) + (PORT datad (628:628:628) (673:673:673)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~72) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1049:1049:1049)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (322:322:322) (335:335:335)) + (PORT datad (835:835:835) (847:847:847)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT datab (1078:1078:1078) (1111:1111:1111)) + (PORT datac (932:932:932) (992:992:992)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (800:800:800) (810:810:810)) + (PORT datac (841:841:841) (868:868:868)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (922:922:922) (954:954:954)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (727:727:727)) + (PORT datad (838:838:838) (851:851:851)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (765:765:765)) + (PORT datab (514:514:514) (512:512:512)) + (PORT datac (568:568:568) (585:585:585)) + (PORT datad (645:645:645) (695:695:695)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (858:858:858)) + (PORT datab (1181:1181:1181) (1213:1213:1213)) + (PORT datac (1051:1051:1051) (1084:1084:1084)) + (PORT datad (954:954:954) (1015:1015:1015)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (919:919:919) (952:952:952)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (2952:2952:2952) (3014:3014:3014)) + (PORT datac (194:194:194) (261:261:261)) + (PORT datad (3545:3545:3545) (3668:3668:3668)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1084:1084:1084)) + (PORT datab (1173:1173:1173) (1185:1185:1185)) + (PORT datad (838:838:838) (817:817:817)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (967:967:967)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datad (911:911:911) (957:957:957)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (767:767:767)) + (PORT datab (885:885:885) (923:923:923)) + (PORT datac (565:565:565) (583:583:583)) + (PORT datad (491:491:491) (479:479:479)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (614:614:614)) + (PORT datab (707:707:707) (779:779:779)) + (PORT datad (347:347:347) (351:351:351)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (640:640:640) (666:666:666)) + (PORT datac (2075:2075:2075) (2066:2066:2066)) + (PORT datad (2010:2010:2010) (2096:2096:2096)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (530:530:530) (520:520:520)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1097:1097:1097)) + (PORT datab (1345:1345:1345) (1333:1333:1333)) + (PORT datac (1516:1516:1516) (1537:1537:1537)) + (PORT datad (1522:1522:1522) (1474:1474:1474)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1184:1184:1184)) + (PORT datab (897:897:897) (897:897:897)) + (PORT datac (1461:1461:1461) (1453:1453:1453)) + (PORT datad (199:199:199) (230:230:230)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (923:923:923) (935:935:935)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2545:2545:2545) (2594:2594:2594)) + (PORT d[1] (1811:1811:1811) (1861:1861:1861)) + (PORT d[2] (3405:3405:3405) (3489:3489:3489)) + (PORT d[3] (1718:1718:1718) (1770:1770:1770)) + (PORT d[4] (1480:1480:1480) (1538:1538:1538)) + (PORT d[5] (1669:1669:1669) (1703:1703:1703)) + (PORT d[6] (2602:2602:2602) (2686:2686:2686)) + (PORT d[7] (1612:1612:1612) (1638:1638:1638)) + (PORT d[8] (3010:3010:3010) (3077:3077:3077)) + (PORT d[9] (3675:3675:3675) (3821:3821:3821)) + (PORT d[10] (1845:1845:1845) (1951:1951:1951)) + (PORT d[11] (1160:1160:1160) (1181:1181:1181)) + (PORT d[12] (1575:1575:1575) (1678:1678:1678)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1392:1392:1392) (1342:1342:1342)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2123:2123:2123) (2094:2094:2094)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1449:1449:1449) (1455:1455:1455)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2253:2253:2253) (2279:2279:2279)) + (PORT d[1] (1513:1513:1513) (1549:1549:1549)) + (PORT d[2] (2817:2817:2817) (2888:2888:2888)) + (PORT d[3] (2064:2064:2064) (2143:2143:2143)) + (PORT d[4] (3689:3689:3689) (3844:3844:3844)) + (PORT d[5] (2816:2816:2816) (2882:2882:2882)) + (PORT d[6] (2062:2062:2062) (2119:2119:2119)) + (PORT d[7] (1959:1959:1959) (2017:2017:2017)) + (PORT d[8] (2454:2454:2454) (2499:2499:2499)) + (PORT d[9] (3077:3077:3077) (3202:3202:3202)) + (PORT d[10] (1836:1836:1836) (1941:1941:1941)) + (PORT d[11] (2483:2483:2483) (2555:2555:2555)) + (PORT d[12] (1750:1750:1750) (1833:1833:1833)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1658:1658:1658) (1624:1624:1624)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (2862:2862:2862) (2837:2837:2837)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1592:1592:1592)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (862:862:862) (859:859:859)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3828:3828:3828) (3796:3796:3796)) + (PORT d[1] (3890:3890:3890) (3864:3864:3864)) + (PORT d[2] (3850:3850:3850) (3811:3811:3811)) + (PORT d[3] (3837:3837:3837) (3796:3796:3796)) + (PORT d[4] (3941:3941:3941) (3915:3915:3915)) + (PORT d[5] (4004:4004:4004) (4163:4163:4163)) + (PORT d[6] (4025:4025:4025) (4013:4013:4013)) + (PORT d[7] (3850:3850:3850) (3860:3860:3860)) + (PORT d[8] (3942:3942:3942) (3830:3830:3830)) + (PORT d[9] (3817:3817:3817) (3706:3706:3706)) + (PORT d[10] (3782:3782:3782) (3691:3691:3691)) + (PORT d[11] (3793:3793:3793) (3698:3698:3698)) + (PORT d[12] (4036:4036:4036) (3948:3948:3948)) + (PORT clk (1599:1599:1599) (1596:1596:1596)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2692:2692:2692) (2724:2724:2724)) + (PORT d[1] (2865:2865:2865) (2825:2825:2825)) + (PORT d[2] (2406:2406:2406) (2429:2429:2429)) + (PORT d[3] (1074:1074:1074) (1083:1083:1083)) + (PORT d[4] (2700:2700:2700) (2856:2856:2856)) + (PORT d[5] (2856:2856:2856) (2855:2855:2855)) + (PORT d[6] (3680:3680:3680) (3817:3817:3817)) + (PORT d[7] (1586:1586:1586) (1556:1556:1556)) + (PORT d[8] (3642:3642:3642) (3741:3741:3741)) + (PORT d[9] (4170:4170:4170) (4315:4315:4315)) + (PORT d[10] (1192:1192:1192) (1216:1216:1216)) + (PORT d[11] (3336:3336:3336) (3446:3446:3446)) + (PORT d[12] (884:884:884) (887:887:887)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (928:928:928) (844:844:844)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1227:1227:1227)) + (PORT datab (1409:1409:1409) (1464:1464:1464)) + (PORT datac (1358:1358:1358) (1369:1369:1369)) + (PORT datad (1079:1079:1079) (1073:1073:1073)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (882:882:882) (878:878:878)) + (PORT d[0] (655:655:655) (648:648:648)) (PORT clk (1638:1638:1638) (1666:1666:1666)) ) ) @@ -41760,19 +41335,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2819:2819:2819) (2973:2973:2973)) - (PORT d[1] (1497:1497:1497) (1523:1523:1523)) - (PORT d[2] (925:925:925) (939:939:939)) - (PORT d[3] (880:880:880) (895:895:895)) - (PORT d[4] (1090:1090:1090) (1067:1067:1067)) - (PORT d[5] (886:886:886) (894:894:894)) - (PORT d[6] (1439:1439:1439) (1501:1501:1501)) - (PORT d[7] (911:911:911) (907:907:907)) - (PORT d[8] (1193:1193:1193) (1230:1230:1230)) - (PORT d[9] (715:715:715) (754:754:754)) - (PORT d[10] (674:674:674) (707:707:707)) - (PORT d[11] (2301:2301:2301) (2386:2386:2386)) - (PORT d[12] (985:985:985) (1022:1022:1022)) + (PORT d[0] (2551:2551:2551) (2605:2605:2605)) + (PORT d[1] (1797:1797:1797) (1855:1855:1855)) + (PORT d[2] (3419:3419:3419) (3520:3520:3520)) + (PORT d[3] (1752:1752:1752) (1822:1822:1822)) + (PORT d[4] (1211:1211:1211) (1231:1231:1231)) + (PORT d[5] (1430:1430:1430) (1447:1447:1447)) + (PORT d[6] (1211:1211:1211) (1235:1235:1235)) + (PORT d[7] (1409:1409:1409) (1426:1426:1426)) + (PORT d[8] (3305:3305:3305) (3381:3381:3381)) + (PORT d[9] (1883:1883:1883) (1925:1925:1925)) + (PORT d[10] (1377:1377:1377) (1414:1414:1414)) + (PORT d[11] (907:907:907) (930:930:930)) + (PORT d[12] (1513:1513:1513) (1593:1593:1593)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -41785,7 +41360,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (860:860:860) (811:811:811)) + (PORT d[0] (1312:1312:1312) (1251:1251:1251)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -41799,7 +41374,7 @@ (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (1853:1853:1853) (1826:1826:1826)) + (PORT d[0] (1361:1361:1361) (1318:1318:1318)) ) ) ) @@ -41900,8 +41475,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (933:933:933) (939:939:939)) - (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (926:926:926) (940:940:940)) + (PORT clk (1637:1637:1637) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -41913,20 +41488,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2800:2800:2800) (2938:2938:2938)) - (PORT d[1] (1764:1764:1764) (1795:1795:1795)) - (PORT d[2] (1186:1186:1186) (1197:1197:1197)) - (PORT d[3] (1175:1175:1175) (1179:1179:1179)) - (PORT d[4] (1374:1374:1374) (1372:1372:1372)) - (PORT d[5] (623:623:623) (623:623:623)) - (PORT d[6] (1696:1696:1696) (1760:1760:1760)) - (PORT d[7] (2706:2706:2706) (2777:2777:2777)) - (PORT d[8] (1181:1181:1181) (1213:1213:1213)) - (PORT d[9] (933:933:933) (957:957:957)) - (PORT d[10] (669:669:669) (699:699:699)) - (PORT d[11] (2339:2339:2339) (2427:2427:2427)) - (PORT d[12] (714:714:714) (754:754:754)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (2288:2288:2288) (2338:2338:2338)) + (PORT d[1] (1540:1540:1540) (1579:1579:1579)) + (PORT d[2] (3130:3130:3130) (3217:3217:3217)) + (PORT d[3] (1755:1755:1755) (1822:1822:1822)) + (PORT d[4] (1526:1526:1526) (1551:1551:1551)) + (PORT d[5] (1899:1899:1899) (1936:1936:1936)) + (PORT d[6] (1429:1429:1429) (1464:1464:1464)) + (PORT d[7] (1647:1647:1647) (1687:1687:1687)) + (PORT d[8] (2997:2997:2997) (3052:3052:3052)) + (PORT d[9] (3636:3636:3636) (3779:3779:3779)) + (PORT d[10] (1855:1855:1855) (1950:1950:1950)) + (PORT d[11] (2231:2231:2231) (2263:2263:2263)) + (PORT d[12] (1567:1567:1567) (1667:1667:1667)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -41938,8 +41513,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (860:860:860) (812:812:812)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (1127:1127:1127) (1092:1092:1092)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -41951,8 +41526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1662:1662:1662)) - (PORT d[0] (1631:1631:1631) (1604:1604:1604)) + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT d[0] (1603:1603:1603) (1578:1578:1578)) ) ) ) @@ -41961,7 +41536,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -41971,7 +41546,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -41981,7 +41556,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -41991,7 +41566,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -41999,4419 +41574,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1021:1021:1021)) - (PORT datab (887:887:887) (930:930:930)) - (PORT datac (824:824:824) (801:801:801)) - (PORT datad (860:860:860) (863:863:863)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1306:1306:1306) (1298:1298:1298)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2300:2300:2300) (2365:2365:2365)) - (PORT d[1] (2336:2336:2336) (2336:2336:2336)) - (PORT d[2] (2373:2373:2373) (2464:2464:2464)) - (PORT d[3] (4241:4241:4241) (4317:4317:4317)) - (PORT d[4] (2716:2716:2716) (2753:2753:2753)) - (PORT d[5] (2909:2909:2909) (2914:2914:2914)) - (PORT d[6] (1369:1369:1369) (1354:1354:1354)) - (PORT d[7] (1294:1294:1294) (1288:1288:1288)) - (PORT d[8] (2307:2307:2307) (2367:2367:2367)) - (PORT d[9] (1560:1560:1560) (1529:1529:1529)) - (PORT d[10] (2347:2347:2347) (2353:2353:2353)) - (PORT d[11] (3434:3434:3434) (3555:3555:3555)) - (PORT d[12] (2305:2305:2305) (2306:2306:2306)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1831:1831:1831) (1769:1769:1769)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (1765:1765:1765) (1703:1703:1703)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1126:1126:1126)) - (PORT datab (1431:1431:1431) (1502:1502:1502)) - (PORT datac (327:327:327) (332:332:332)) - (PORT datad (1234:1234:1234) (1215:1215:1215)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1466:1466:1466) (1476:1476:1476)) - (PORT clk (1645:1645:1645) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2327:2327:2327) (2380:2380:2380)) - (PORT d[1] (1965:1965:1965) (2005:2005:2005)) - (PORT d[2] (2233:2233:2233) (2277:2277:2277)) - (PORT d[3] (1943:1943:1943) (1987:1987:1987)) - (PORT d[4] (1923:1923:1923) (1958:1958:1958)) - (PORT d[5] (2143:2143:2143) (2185:2185:2185)) - (PORT d[6] (2157:2157:2157) (2215:2215:2215)) - (PORT d[7] (3196:3196:3196) (3235:3235:3235)) - (PORT d[8] (2645:2645:2645) (2674:2674:2674)) - (PORT d[9] (1870:1870:1870) (1972:1972:1972)) - (PORT d[10] (3334:3334:3334) (3376:3376:3376)) - (PORT d[11] (2005:2005:2005) (2053:2053:2053)) - (PORT d[12] (1826:1826:1826) (1919:1919:1919)) - (PORT clk (1642:1642:1642) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1816:1816:1816) (1751:1751:1751)) - (PORT clk (1642:1642:1642) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1673:1673:1673)) - (PORT d[0] (2935:2935:2935) (2952:2952:2952)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1603:1603:1603)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1987:1987:1987) (2006:2006:2006)) - (PORT clk (1612:1612:1612) (1610:1610:1610)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4032:4032:4032) (3948:3948:3948)) - (PORT d[1] (4163:4163:4163) (4141:4141:4141)) - (PORT d[2] (4233:4233:4233) (4120:4120:4120)) - (PORT d[3] (3992:3992:3992) (3977:3977:3977)) - (PORT d[4] (4079:4079:4079) (4027:4027:4027)) - (PORT d[5] (4116:4116:4116) (4106:4106:4106)) - (PORT d[6] (4231:4231:4231) (4154:4154:4154)) - (PORT d[7] (4020:4020:4020) (3901:3901:3901)) - (PORT d[8] (4079:4079:4079) (4042:4042:4042)) - (PORT d[9] (4173:4173:4173) (4057:4057:4057)) - (PORT d[10] (4101:4101:4101) (4044:4044:4044)) - (PORT d[11] (4113:4113:4113) (4060:4060:4060)) - (PORT d[12] (4066:4066:4066) (3898:3898:3898)) - (PORT clk (1609:1609:1609) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1841:1841:1841) (1901:1901:1901)) - (PORT d[1] (2032:2032:2032) (1999:1999:1999)) - (PORT d[2] (2067:2067:2067) (2148:2148:2148)) - (PORT d[3] (1598:1598:1598) (1596:1596:1596)) - (PORT d[4] (2140:2140:2140) (2176:2176:2176)) - (PORT d[5] (2594:2594:2594) (2578:2578:2578)) - (PORT d[6] (1613:1613:1613) (1625:1625:1625)) - (PORT d[7] (1823:1823:1823) (1818:1818:1818)) - (PORT d[8] (2024:2024:2024) (2071:2071:2071)) - (PORT d[9] (1846:1846:1846) (1833:1833:1833)) - (PORT d[10] (2316:2316:2316) (2294:2294:2294)) - (PORT d[11] (4003:4003:4003) (4148:4148:4148)) - (PORT d[12] (2003:2003:2003) (1997:1997:1997)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1668:1668:1668)) - (PORT d[0] (1962:1962:1962) (1910:1910:1910)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (859:859:859)) - (PORT datab (713:713:713) (775:775:775)) - (PORT datac (1110:1110:1110) (1110:1110:1110)) - (PORT datad (1546:1546:1546) (1546:1546:1546)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1371:1371:1371) (1374:1374:1374)) - (PORT clk (1653:1653:1653) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2044:2044:2044) (2084:2084:2084)) - (PORT d[1] (2434:2434:2434) (2484:2484:2484)) - (PORT d[2] (2184:2184:2184) (2234:2234:2234)) - (PORT d[3] (2821:2821:2821) (2834:2834:2834)) - (PORT d[4] (2112:2112:2112) (2174:2174:2174)) - (PORT d[5] (3186:3186:3186) (3199:3199:3199)) - (PORT d[6] (2347:2347:2347) (2361:2361:2361)) - (PORT d[7] (2735:2735:2735) (2737:2737:2737)) - (PORT d[8] (2446:2446:2446) (2488:2488:2488)) - (PORT d[9] (2740:2740:2740) (2791:2791:2791)) - (PORT d[10] (2137:2137:2137) (2134:2134:2134)) - (PORT d[11] (2069:2069:2069) (2137:2137:2137)) - (PORT d[12] (3266:3266:3266) (3331:3331:3331)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2370:2370:2370) (2321:2321:2321)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (PORT d[0] (3196:3196:3196) (3184:3184:3184)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1610:1610:1610)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2021:2021:2021) (1988:1988:1988)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4178:4178:4178) (4052:4052:4052)) - (PORT d[1] (4135:4135:4135) (4061:4061:4061)) - (PORT d[2] (4153:4153:4153) (4015:4015:4015)) - (PORT d[3] (4095:4095:4095) (4025:4025:4025)) - (PORT d[4] (3950:3950:3950) (3909:3909:3909)) - (PORT d[5] (4139:4139:4139) (4063:4063:4063)) - (PORT d[6] (3944:3944:3944) (3864:3864:3864)) - (PORT d[7] (4095:4095:4095) (4013:4013:4013)) - (PORT d[8] (4078:4078:4078) (4028:4028:4028)) - (PORT d[9] (4043:4043:4043) (3945:3945:3945)) - (PORT d[10] (3975:3975:3975) (3864:3864:3864)) - (PORT d[11] (4166:4166:4166) (4042:4042:4042)) - (PORT d[12] (4008:4008:4008) (3886:3886:3886)) - (PORT clk (1617:1617:1617) (1614:1614:1614)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2081:2081:2081) (2158:2158:2158)) - (PORT d[1] (1020:1020:1020) (1010:1010:1010)) - (PORT d[2] (2446:2446:2446) (2469:2469:2469)) - (PORT d[3] (4243:4243:4243) (4308:4308:4308)) - (PORT d[4] (930:930:930) (946:946:946)) - (PORT d[5] (2034:2034:2034) (1999:1999:1999)) - (PORT d[6] (2635:2635:2635) (2656:2656:2656)) - (PORT d[7] (1307:1307:1307) (1283:1283:1283)) - (PORT d[8] (2560:2560:2560) (2621:2621:2621)) - (PORT d[9] (1372:1372:1372) (1367:1367:1367)) - (PORT d[10] (1867:1867:1867) (1854:1854:1854)) - (PORT d[11] (3462:3462:3462) (3595:3595:3595)) - (PORT d[12] (1576:1576:1576) (1578:1578:1578)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (1190:1190:1190) (1233:1233:1233)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1065:1065:1065)) - (PORT datab (882:882:882) (853:853:853)) - (PORT datac (923:923:923) (961:961:961)) - (PORT datad (168:168:168) (194:194:194)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (713:713:713) (779:779:779)) - (PORT datac (1754:1754:1754) (1751:1751:1751)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (1596:1596:1596) (1607:1607:1607)) - (PORT datab (2775:2775:2775) (2913:2913:2913)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (852:852:852)) - (PORT datab (834:834:834) (837:837:837)) - (PORT datac (1528:1528:1528) (1508:1508:1508)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1144:1144:1144)) - (PORT datab (2747:2747:2747) (2740:2740:2740)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (1336:1336:1336) (1346:1346:1346)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1081:1081:1081)) - (PORT datab (380:380:380) (408:408:408)) - (PORT datac (347:347:347) (354:354:354)) - (PORT datad (1045:1045:1045) (1025:1025:1025)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (1970:1970:1970) (1970:1970:1970)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (1330:1330:1330) (1317:1317:1317)) - (PORT datac (1016:1016:1016) (1003:1003:1003)) - (PORT datad (198:198:198) (229:229:229)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (657:657:657) (660:660:660)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1787:1787:1787) (1726:1726:1726)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1577:1577:1577)) - (PORT datab (1260:1260:1260) (1252:1252:1252)) - (PORT datac (188:188:188) (230:230:230)) - (PORT datad (1237:1237:1237) (1193:1193:1193)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2123:2123:2123) (2184:2184:2184)) - (PORT datab (2019:2019:2019) (2100:2100:2100)) - (PORT datac (2080:2080:2080) (2111:2111:2111)) - (PORT datad (341:341:341) (352:352:352)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1384:1384:1384) (1355:1355:1355)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datac (905:905:905) (953:953:953)) - (PORT datad (1382:1382:1382) (1428:1428:1428)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (850:850:850)) - (PORT datab (1575:1575:1575) (1550:1550:1550)) - (PORT datac (984:984:984) (1002:1002:1002)) - (PORT datad (754:754:754) (779:779:779)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (603:603:603)) - (PORT datab (1143:1143:1143) (1141:1141:1141)) - (PORT datad (813:813:813) (823:823:823)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1035:1035:1035)) - (PORT datab (569:569:569) (578:578:578)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (550:550:550) (558:558:558)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (653:653:653) (684:684:684)) - (PORT datac (1305:1305:1305) (1351:1351:1351)) - (PORT datad (561:561:561) (585:585:585)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1100:1100:1100)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (558:558:558) (580:580:580)) - (PORT datad (713:713:713) (739:739:739)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1181:1181:1181)) - (PORT datab (364:364:364) (382:382:382)) - (PORT datac (867:867:867) (922:922:922)) - (PORT datad (1246:1246:1246) (1315:1315:1315)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1117:1117:1117) (1144:1144:1144)) - (PORT datab (1429:1429:1429) (1449:1449:1449)) - (PORT datac (536:536:536) (528:528:528)) - (PORT datad (799:799:799) (789:789:789)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1279:1279:1279) (1287:1287:1287)) - (PORT datab (1962:1962:1962) (2055:2055:2055)) - (PORT datac (1514:1514:1514) (1482:1482:1482)) - (PORT datad (643:643:643) (681:681:681)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (722:722:722)) - (PORT datab (610:610:610) (596:596:596)) - (PORT datac (1481:1481:1481) (1467:1467:1467)) - (PORT datad (1363:1363:1363) (1392:1392:1392)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1085:1085:1085)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (237:237:237)) - (PORT datab (578:578:578) (600:600:600)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (323:323:323) (330:330:330)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (814:814:814) (822:822:822)) - (PORT datac (526:526:526) (524:524:524)) - (PORT datad (756:756:756) (735:735:735)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (558:558:558)) - (PORT datab (555:555:555) (552:552:552)) - (PORT datac (827:827:827) (837:837:837)) - (PORT datad (757:757:757) (741:741:741)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (268:268:268)) - (PORT datab (814:814:814) (827:827:827)) - (PORT datac (603:603:603) (617:617:617)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (995:995:995) (1021:1021:1021)) - (PORT datab (1081:1081:1081) (1076:1076:1076)) - (PORT datac (1212:1212:1212) (1181:1181:1181)) - (PORT datad (1251:1251:1251) (1263:1263:1263)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (603:603:603)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (788:788:788) (794:794:794)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (580:580:580)) - (PORT datac (585:585:585) (600:600:600)) - (PORT datad (778:778:778) (775:775:775)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (809:809:809) (814:814:814)) - (PORT datad (162:162:162) (184:184:184)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (813:813:813)) - (PORT datab (1076:1076:1076) (1063:1063:1063)) - (PORT datad (357:357:357) (367:367:367)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (510:510:510)) - (PORT datac (689:689:689) (740:740:740)) - (PORT datad (352:352:352) (401:401:401)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (678:678:678)) - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (574:574:574) (611:611:611)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (223:223:223)) - (PORT datab (184:184:184) (216:216:216)) - (PORT datad (542:542:542) (530:530:530)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (721:721:721) (755:755:755)) - (PORT datad (179:179:179) (200:200:200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1327:1327:1327) (1346:1346:1346)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1370:1370:1370) (1350:1350:1350)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) - (DELAY - (ABSOLUTE - (PORT datab (1681:1681:1681) (1713:1713:1713)) - (PORT datac (2090:2090:2090) (2214:2214:2214)) - (PORT datad (840:840:840) (849:849:849)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (382:382:382)) - (PORT datab (640:640:640) (665:665:665)) - (PORT datac (835:835:835) (860:860:860)) - (PORT datad (876:876:876) (916:916:916)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (703:703:703)) - (PORT datab (720:720:720) (791:791:791)) - (PORT datac (935:935:935) (990:990:990)) - (PORT datad (682:682:682) (747:747:747)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (708:708:708)) - (PORT datab (719:719:719) (788:788:788)) - (PORT datac (933:933:933) (989:989:989)) - (PORT datad (679:679:679) (744:744:744)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (250:250:250)) - (PORT datab (962:962:962) (1020:1020:1020)) - (PORT datac (1150:1150:1150) (1194:1194:1194)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (721:721:721)) - (PORT datab (1182:1182:1182) (1224:1224:1224)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (725:725:725)) - (PORT datab (559:559:559) (546:546:546)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1328:1328:1328) (1347:1347:1347)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1371:1371:1371) (1351:1351:1351)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (748:748:748)) - (PORT datab (673:673:673) (713:713:713)) - (PORT datac (666:666:666) (727:727:727)) - (PORT datad (928:928:928) (965:965:965)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (920:920:920) (956:956:956)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (488:488:488) (482:482:482)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1001:1001:1001)) - (PORT datac (419:419:419) (477:477:477)) - (PORT datad (852:852:852) (871:871:871)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (898:898:898)) - (PORT datab (872:872:872) (872:872:872)) - (PORT datac (600:600:600) (621:621:621)) - (PORT datad (1324:1324:1324) (1300:1300:1300)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (254:254:254)) - (PORT datab (849:849:849) (876:876:876)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (521:521:521)) - (PORT datab (865:865:865) (902:902:902)) - (PORT datac (681:681:681) (747:747:747)) - (PORT datad (651:651:651) (691:691:691)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (607:607:607) (601:601:601)) - (PORT datac (868:868:868) (912:912:912)) - (PORT datad (821:821:821) (829:829:829)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (464:464:464) (504:504:504)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1325:1325:1325) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1347:1347:1347)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (522:522:522)) - (PORT datab (897:897:897) (940:940:940)) - (PORT datac (681:681:681) (747:747:747)) - (PORT datad (654:654:654) (693:693:693)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (727:727:727)) - (PORT datab (1197:1197:1197) (1219:1219:1219)) - (PORT datac (677:677:677) (725:725:725)) - (PORT datad (291:291:291) (297:297:297)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (692:692:692) (753:753:753)) - (PORT datac (421:421:421) (482:482:482)) - (PORT datad (848:848:848) (865:865:865)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (601:601:601)) - (PORT datab (312:312:312) (331:331:331)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (637:637:637)) - (PORT datab (619:619:619) (647:647:647)) - (PORT datac (616:616:616) (639:639:639)) - (PORT datad (1380:1380:1380) (1421:1421:1421)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (1197:1197:1197) (1228:1228:1228)) - (PORT datac (636:636:636) (689:689:689)) - (PORT datad (665:665:665) (708:708:708)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1267:1267:1267)) - (PORT datab (610:610:610) (627:627:627)) - (PORT datad (557:557:557) (542:542:542)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1373:1373:1373) (1354:1354:1354)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1272:1272:1272)) - (PORT datab (932:932:932) (990:990:990)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1330:1330:1330) (1349:1349:1349)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1373:1373:1373) (1354:1354:1354)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (2589:2589:2589) (2687:2687:2687)) - (PORT datac (196:196:196) (262:262:262)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (2186:2186:2186) (2315:2315:2315)) - (PORT datad (533:533:533) (519:519:519)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1190:1190:1190) (1201:1201:1201)) - (PORT clk (1630:1630:1630) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2246:2246:2246) (2370:2370:2370)) - (PORT d[1] (2362:2362:2362) (2392:2392:2392)) - (PORT d[2] (1175:1175:1175) (1191:1191:1191)) - (PORT d[3] (1164:1164:1164) (1169:1169:1169)) - (PORT d[4] (1890:1890:1890) (1900:1900:1900)) - (PORT d[5] (1173:1173:1173) (1185:1185:1185)) - (PORT d[6] (1345:1345:1345) (1332:1332:1332)) - (PORT d[7] (2466:2466:2466) (2527:2527:2527)) - (PORT d[8] (2297:2297:2297) (2400:2400:2400)) - (PORT d[9] (715:715:715) (756:756:756)) - (PORT d[10] (676:676:676) (712:712:712)) - (PORT d[11] (1124:1124:1124) (1127:1127:1127)) - (PORT d[12] (668:668:668) (699:699:699)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1146:1146:1146) (1108:1108:1108)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1630:1630:1630) (1658:1658:1658)) - (PORT d[0] (1549:1549:1549) (1495:1495:1495)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1622:1622:1622)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (865:865:865) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (934:934:934) (939:939:939)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2538:2538:2538) (2677:2677:2677)) - (PORT d[1] (1796:1796:1796) (1824:1824:1824)) - (PORT d[2] (926:926:926) (928:928:928)) - (PORT d[3] (899:899:899) (899:899:899)) - (PORT d[4] (1332:1332:1332) (1321:1321:1321)) - (PORT d[5] (887:887:887) (885:885:885)) - (PORT d[6] (1074:1074:1074) (1052:1052:1052)) - (PORT d[7] (2727:2727:2727) (2782:2782:2782)) - (PORT d[8] (1469:1469:1469) (1502:1502:1502)) - (PORT d[9] (678:678:678) (702:702:702)) - (PORT d[10] (660:660:660) (681:681:681)) - (PORT d[11] (2311:2311:2311) (2398:2398:2398)) - (PORT d[12] (702:702:702) (737:737:737)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (867:867:867) (836:836:836)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2978:2978:2978) (2980:2980:2980)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1100:1100:1100) (1053:1053:1053)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2363:2363:2363) (2450:2450:2450)) - (PORT d[1] (3342:3342:3342) (3418:3418:3418)) - (PORT d[2] (2193:2193:2193) (2211:2211:2211)) - (PORT d[3] (3959:3959:3959) (4026:4026:4026)) - (PORT d[4] (2941:2941:2941) (3050:3050:3050)) - (PORT d[5] (4357:4357:4357) (4429:4429:4429)) - (PORT d[6] (2344:2344:2344) (2357:2357:2357)) - (PORT d[7] (1294:1294:1294) (1285:1285:1285)) - (PORT d[8] (2887:2887:2887) (2959:2959:2959)) - (PORT d[9] (1662:1662:1662) (1669:1669:1669)) - (PORT d[10] (1838:1838:1838) (1814:1814:1814)) - (PORT d[11] (3155:3155:3155) (3274:3274:3274)) - (PORT d[12] (4329:4329:4329) (4444:4444:4444)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1736:1736:1736) (1726:1726:1726)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (2227:2227:2227) (2165:2165:2165)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (960:960:960)) - (PORT datab (1142:1142:1142) (1171:1171:1171)) - (PORT datac (843:843:843) (845:845:845)) - (PORT datad (1010:1010:1010) (978:978:978)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1275:1275:1275) (1267:1267:1267)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2290:2290:2290) (2354:2354:2354)) - (PORT d[1] (2298:2298:2298) (2277:2277:2277)) - (PORT d[2] (2382:2382:2382) (2475:2475:2475)) - (PORT d[3] (1574:1574:1574) (1563:1563:1563)) - (PORT d[4] (2243:2243:2243) (2301:2301:2301)) - (PORT d[5] (2941:2941:2941) (2949:2949:2949)) - (PORT d[6] (2049:2049:2049) (2065:2065:2065)) - (PORT d[7] (1590:1590:1590) (1591:1591:1591)) - (PORT d[8] (2270:2270:2270) (2315:2315:2315)) - (PORT d[9] (1574:1574:1574) (1556:1556:1556)) - (PORT d[10] (2338:2338:2338) (2339:2339:2339)) - (PORT d[11] (3735:3735:3735) (3877:3877:3877)) - (PORT d[12] (2289:2289:2289) (2292:2292:2292)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1836:1836:1836) (1777:1777:1777)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (1998:1998:1998) (1941:1941:1941)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1396:1396:1396) (1460:1460:1460)) - (PORT datab (1111:1111:1111) (1122:1122:1122)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1296:1296:1296) (1273:1273:1273)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1383:1383:1383) (1372:1372:1372)) - (PORT clk (1652:1652:1652) (1679:1679:1679)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2317:2317:2317) (2350:2350:2350)) - (PORT d[1] (2108:2108:2108) (2115:2115:2115)) - (PORT d[2] (1911:1911:1911) (1960:1960:1960)) - (PORT d[3] (3067:3067:3067) (3079:3079:3079)) - (PORT d[4] (2142:2142:2142) (2219:2219:2219)) - (PORT d[5] (3480:3480:3480) (3506:3506:3506)) - (PORT d[6] (2330:2330:2330) (2339:2339:2339)) - (PORT d[7] (2310:2310:2310) (2319:2319:2319)) - (PORT d[8] (2724:2724:2724) (2759:2759:2759)) - (PORT d[9] (2535:2535:2535) (2595:2595:2595)) - (PORT d[10] (2698:2698:2698) (2717:2717:2717)) - (PORT d[11] (2555:2555:2555) (2620:2620:2620)) - (PORT d[12] (3239:3239:3239) (3318:3318:3318)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2602:2602:2602) (2565:2565:2565)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1652:1652:1652) (1679:1679:1679)) - (PORT d[0] (3196:3196:3196) (3184:3184:3184)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2020:2020:2020) (1987:1987:1987)) - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4191:4191:4191) (4059:4059:4059)) - (PORT d[1] (4108:4108:4108) (4082:4082:4082)) - (PORT d[2] (4214:4214:4214) (4086:4086:4086)) - (PORT d[3] (4077:4077:4077) (4001:4001:4001)) - (PORT d[4] (3956:3956:3956) (3928:3928:3928)) - (PORT d[5] (4097:4097:4097) (4012:4012:4012)) - (PORT d[6] (3962:3962:3962) (3881:3881:3881)) - (PORT d[7] (4119:4119:4119) (4038:4038:4038)) - (PORT d[8] (4217:4217:4217) (4160:4160:4160)) - (PORT d[9] (4068:4068:4068) (3996:3996:3996)) - (PORT d[10] (3941:3941:3941) (3829:3829:3829)) - (PORT d[11] (4112:4112:4112) (4036:4036:4036)) - (PORT d[12] (3982:3982:3982) (3857:3857:3857)) - (PORT clk (1616:1616:1616) (1613:1613:1613)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1610:1610:1610)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1776:1776:1776) (1834:1834:1834)) - (PORT d[1] (1547:1547:1547) (1554:1554:1554)) - (PORT d[2] (1830:1830:1830) (1909:1909:1909)) - (PORT d[3] (1769:1769:1769) (1768:1768:1768)) - (PORT d[4] (2482:2482:2482) (2511:2511:2511)) - (PORT d[5] (2126:2126:2126) (2129:2129:2129)) - (PORT d[6] (1597:1597:1597) (1613:1613:1613)) - (PORT d[7] (1861:1861:1861) (1868:1868:1868)) - (PORT d[8] (1714:1714:1714) (1753:1753:1753)) - (PORT d[9] (1875:1875:1875) (1867:1867:1867)) - (PORT d[10] (1560:1560:1560) (1557:1557:1557)) - (PORT d[11] (4007:4007:4007) (4155:4155:4155)) - (PORT d[12] (1529:1529:1529) (1530:1530:1530)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (1629:1629:1629) (1698:1698:1698)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2314:2314:2314) (2367:2367:2367)) - (PORT d[1] (2467:2467:2467) (2495:2495:2495)) - (PORT d[2] (2053:2053:2053) (2130:2130:2130)) - (PORT d[3] (1957:1957:1957) (2014:2014:2014)) - (PORT d[4] (1933:1933:1933) (1952:1952:1952)) - (PORT d[5] (2251:2251:2251) (2287:2287:2287)) - (PORT d[6] (2256:2256:2256) (2336:2336:2336)) - (PORT d[7] (3179:3179:3179) (3205:3205:3205)) - (PORT d[8] (2636:2636:2636) (2663:2663:2663)) - (PORT d[9] (2141:2141:2141) (2240:2240:2240)) - (PORT d[10] (3053:3053:3053) (3089:3089:3089)) - (PORT d[11] (1988:1988:1988) (2023:2023:2023)) - (PORT d[12] (2094:2094:2094) (2192:2192:2192)) - (PORT clk (1645:1645:1645) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1673:1673:1673)) - (PORT d[0] (2383:2383:2383) (2403:2403:2403)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1639:1639:1639)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (884:884:884) (887:887:887)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (884:884:884) (887:887:887)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (884:884:884) (887:887:887)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1496:1496:1496) (1548:1548:1548)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2591:2591:2591) (2643:2643:2643)) - (PORT d[1] (2732:2732:2732) (2767:2767:2767)) - (PORT d[2] (1830:1830:1830) (1887:1887:1887)) - (PORT d[3] (1729:1729:1729) (1779:1779:1779)) - (PORT d[4] (1952:1952:1952) (1999:1999:1999)) - (PORT d[5] (2434:2434:2434) (2448:2448:2448)) - (PORT d[6] (1983:1983:1983) (2059:2059:2059)) - (PORT d[7] (3172:3172:3172) (3208:3208:3208)) - (PORT d[8] (2926:2926:2926) (2945:2945:2945)) - (PORT d[9] (2106:2106:2106) (2193:2193:2193)) - (PORT d[10] (1766:1766:1766) (1836:1836:1836)) - (PORT d[11] (1962:1962:1962) (2017:2017:2017)) - (PORT d[12] (2226:2226:2226) (2293:2293:2293)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1867:1867:1867) (1818:1818:1818)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (2918:2918:2918) (2929:2929:2929)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1601:1601:1601)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1958:1958:1958) (1963:1963:1963)) - (PORT clk (1610:1610:1610) (1608:1608:1608)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4144:4144:4144) (4118:4118:4118)) - (PORT d[1] (4074:4074:4074) (4107:4107:4107)) - (PORT d[2] (4099:4099:4099) (4045:4045:4045)) - (PORT d[3] (3971:3971:3971) (3955:3955:3955)) - (PORT d[4] (4076:4076:4076) (4027:4027:4027)) - (PORT d[5] (4136:4136:4136) (4126:4126:4126)) - (PORT d[6] (4038:4038:4038) (4000:4000:4000)) - (PORT d[7] (4060:4060:4060) (3930:3930:3930)) - (PORT d[8] (4294:4294:4294) (4231:4231:4231)) - (PORT d[9] (4162:4162:4162) (4042:4042:4042)) - (PORT d[10] (4066:4066:4066) (4007:4007:4007)) - (PORT d[11] (4075:4075:4075) (3998:3998:3998)) - (PORT d[12] (4087:4087:4087) (3903:3903:3903)) - (PORT clk (1607:1607:1607) (1605:1605:1605)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1608:1608:1608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (859:859:859)) - (PORT datab (712:712:712) (774:774:774)) - (PORT datac (1347:1347:1347) (1362:1362:1362)) - (PORT datad (1070:1070:1070) (1069:1069:1069)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (969:969:969)) - (PORT datab (949:949:949) (986:986:986)) - (PORT datac (1512:1512:1512) (1509:1509:1509)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (759:759:759)) - (PORT datab (1619:1619:1619) (1655:1655:1655)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (1595:1595:1595) (1607:1607:1607)) - (PORT datab (2775:2775:2775) (2913:2913:2913)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (881:881:881)) - (PORT datab (837:837:837) (839:839:839)) - (PORT datac (1524:1524:1524) (1504:1504:1504)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1104:1104:1104)) - (PORT datab (1360:1360:1360) (1379:1379:1379)) - (PORT datac (2969:2969:2969) (2920:2920:2920)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (889:889:889)) - (PORT datab (380:380:380) (408:408:408)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (1045:1045:1045) (1025:1025:1025)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (242:242:242) (312:312:312)) - (PORT datac (551:551:551) (542:542:542)) - (PORT datad (355:355:355) (361:361:361)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1787:1787:1787) (1726:1726:1726)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1475:1475:1475) (1562:1562:1562)) - (PORT datab (1787:1787:1787) (1841:1841:1841)) - (PORT datac (340:340:340) (363:363:363)) - (PORT datad (1072:1072:1072) (1077:1077:1077)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1384:1384:1384) (1355:1355:1355)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (747:747:747)) - (PORT datab (692:692:692) (739:739:739)) - (PORT datac (1693:1693:1693) (1776:1776:1776)) - (PORT datad (1561:1561:1561) (1560:1560:1560)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1943:1943:1943) (2009:2009:2009)) - (PORT datab (1295:1295:1295) (1366:1366:1366)) - (PORT datac (1029:1029:1029) (1029:1029:1029)) - (PORT datad (816:816:816) (826:826:826)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1498:1498:1498)) - (PORT datab (605:605:605) (586:586:586)) - (PORT datac (951:951:951) (986:986:986)) - (PORT datad (2416:2416:2416) (2386:2386:2386)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1660:1660:1660) (1708:1708:1708)) - (PORT datab (987:987:987) (1031:1031:1031)) - (PORT datac (779:779:779) (768:768:768)) - (PORT datad (2401:2401:2401) (2358:2358:2358)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (835:835:835)) - (PORT datab (978:978:978) (1016:1016:1016)) - (PORT datac (1688:1688:1688) (1722:1722:1722)) - (PORT datad (578:578:578) (597:597:597)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1497:1497:1497)) - (PORT datab (2099:2099:2099) (2180:2180:2180)) - (PORT datac (574:574:574) (606:606:606)) - (PORT datad (912:912:912) (967:967:967)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (689:689:689)) - (PORT datab (866:866:866) (891:891:891)) - (PORT datac (1373:1373:1373) (1352:1352:1352)) - (PORT datad (595:595:595) (617:617:617)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (576:576:576)) - (PORT datab (1080:1080:1080) (1036:1036:1036)) - (PORT datac (516:516:516) (506:506:506)) - (PORT datad (587:587:587) (587:587:587)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (232:232:232)) - (PORT datab (466:466:466) (510:510:510)) - (PORT datad (584:584:584) (576:576:576)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1325:1325:1325) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1347:1347:1347)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (399:399:399)) - (PORT datab (360:360:360) (364:364:364)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (426:426:426)) - (PORT datab (886:886:886) (893:893:893)) - (PORT datac (791:791:791) (783:783:783)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (524:524:524)) - (PORT datab (867:867:867) (899:899:899)) - (PORT datac (682:682:682) (745:745:745)) - (PORT datad (656:656:656) (695:695:695)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (624:624:624)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (417:417:417) (465:465:465)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1325:1325:1325) (1344:1344:1344)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1347:1347:1347)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT datab (717:717:717) (766:766:766)) - (PORT datac (1168:1168:1168) (1191:1191:1191)) - (PORT datad (219:219:219) (277:277:277)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (721:721:721)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (675:675:675) (724:724:724)) - (PORT datad (572:572:572) (568:568:568)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (516:516:516)) - (PORT datab (1265:1265:1265) (1234:1234:1234)) - (PORT datad (299:299:299) (292:292:292)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1369:1369:1369) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1210:1210:1210)) - (PORT datab (849:849:849) (843:843:843)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (600:600:600) (622:622:622)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (675:675:675)) - (PORT datab (672:672:672) (703:703:703)) - (PORT datac (1141:1141:1141) (1155:1155:1155)) - (PORT datad (1112:1112:1112) (1124:1124:1124)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (570:570:570)) - (PORT datab (703:703:703) (741:741:741)) - (PORT datac (636:636:636) (687:687:687)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (225:225:225)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2138:2138:2138) (2278:2278:2278)) - (PORT datab (1326:1326:1326) (1386:1386:1386)) - (PORT datad (614:614:614) (654:654:654)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (357:357:357)) - (PORT datab (877:877:877) (920:920:920)) - (PORT datac (909:909:909) (950:950:950)) - (PORT datad (660:660:660) (701:701:701)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1009:1009:1009)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datad (235:235:235) (301:301:301)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (299:299:299) (398:398:398)) - (PORT datab (579:579:579) (589:589:589)) - (PORT datad (762:762:762) (742:742:742)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1326:1326:1326) (1345:1345:1345)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1368:1368:1368) (1348:1348:1348)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (235:235:235)) - (PORT datab (606:606:606) (599:599:599)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1367:1367:1367) (1349:1349:1349)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (778:778:778)) - (PORT datab (568:568:568) (578:578:578)) - (PORT datad (554:554:554) (553:553:553)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1365:1365:1365) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (683:683:683)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datac (2240:2240:2240) (2343:2343:2343)) - (PORT datad (585:585:585) (613:613:613)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (554:554:554)) - (PORT datab (2286:2286:2286) (2371:2371:2371)) - (PORT datac (855:855:855) (885:885:885)) - (PORT datad (558:558:558) (559:559:559)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1082:1082:1082)) - (PORT datab (1113:1113:1113) (1122:1122:1122)) - (PORT datac (3021:3021:3021) (3172:3172:3172)) - (PORT datad (557:557:557) (560:560:560)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (954:954:954) (966:966:966)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3080:3080:3080) (3232:3232:3232)) - (PORT d[1] (1460:1460:1460) (1495:1495:1495)) - (PORT d[2] (963:963:963) (971:971:971)) - (PORT d[3] (1481:1481:1481) (1522:1522:1522)) - (PORT d[4] (2743:2743:2743) (2830:2830:2830)) - (PORT d[5] (899:899:899) (907:907:907)) - (PORT d[6] (1457:1457:1457) (1519:1519:1519)) - (PORT d[7] (1188:1188:1188) (1181:1181:1181)) - (PORT d[8] (1133:1133:1133) (1148:1148:1148)) - (PORT d[9] (1011:1011:1011) (1067:1067:1067)) - (PORT d[10] (956:956:956) (1001:1001:1001)) - (PORT d[11] (2062:2062:2062) (2133:2133:2133)) - (PORT d[12] (1000:1000:1000) (1058:1058:1058)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1097:1097:1097) (1035:1035:1035)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2146:2146:2146) (2099:2099:2099)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (933:933:933) (932:932:932)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3090:3090:3090) (3254:3254:3254)) - (PORT d[1] (1215:1215:1215) (1249:1249:1249)) - (PORT d[2] (1570:1570:1570) (1595:1595:1595)) - (PORT d[3] (1476:1476:1476) (1511:1511:1511)) - (PORT d[4] (2752:2752:2752) (2817:2817:2817)) - (PORT d[5] (1175:1175:1175) (1198:1198:1198)) - (PORT d[6] (1212:1212:1212) (1258:1258:1258)) - (PORT d[7] (1237:1237:1237) (1250:1250:1250)) - (PORT d[8] (1433:1433:1433) (1471:1471:1471)) - (PORT d[9] (1016:1016:1016) (1076:1076:1076)) - (PORT d[10] (965:965:965) (1015:1015:1015)) - (PORT d[11] (2023:2023:2023) (2094:2094:2094)) - (PORT d[12] (1265:1265:1265) (1320:1320:1320)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1080:1080:1080)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2136:2136:2136) (2108:2108:2108)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (869:869:869) (862:862:862)) - (PORT clk (1637:1637:1637) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2485:2485:2485) (2615:2615:2615)) - (PORT d[1] (1427:1427:1427) (1438:1438:1438)) - (PORT d[2] (1257:1257:1257) (1285:1285:1285)) - (PORT d[3] (1226:1226:1226) (1262:1262:1262)) - (PORT d[4] (2463:2463:2463) (2538:2538:2538)) - (PORT d[5] (1467:1467:1467) (1492:1492:1492)) - (PORT d[6] (1404:1404:1404) (1453:1453:1453)) - (PORT d[7] (1465:1465:1465) (1474:1474:1474)) - (PORT d[8] (1420:1420:1420) (1468:1468:1468)) - (PORT d[9] (1523:1523:1523) (1581:1581:1581)) - (PORT d[10] (1240:1240:1240) (1300:1300:1300)) - (PORT d[11] (1752:1752:1752) (1814:1814:1814)) - (PORT d[12] (1282:1282:1282) (1352:1352:1352)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1155:1155:1155) (1130:1130:1130)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) - (PORT d[0] (2155:2155:2155) (2142:2142:2142)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1601:1601:1601) (1628:1628:1628)) @@ -46425,7 +41587,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (872:872:872) (875:875:875)) @@ -46434,7 +41596,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (876:876:876)) @@ -46443,7 +41605,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (876:876:876)) @@ -46453,7 +41615,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (876:876:876)) @@ -46463,26 +41625,41 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~93) + (INSTANCE Selector14\~10) (DELAY (ABSOLUTE - (PORT dataa (840:840:840) (817:817:817)) - (PORT datab (1139:1139:1139) (1179:1179:1179)) - (PORT datad (842:842:842) (831:831:831)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (599:599:599) (598:598:598)) + (PORT datac (1046:1046:1046) (1062:1062:1062)) + (PORT datad (821:821:821) (828:828:828)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1183:1183:1183)) + (PORT datab (1196:1196:1196) (1245:1245:1245)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (195:195:195) (226:226:226)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1283:1283:1283) (1319:1319:1319)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1419:1419:1419) (1435:1435:1435)) + (PORT clk (1631:1631:1631) (1657:1657:1657)) ) ) (TIMINGCHECK @@ -46491,23 +41668,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2759:2759:2759) (2871:2871:2871)) - (PORT d[1] (2684:2684:2684) (2703:2703:2703)) - (PORT d[2] (931:931:931) (943:943:943)) - (PORT d[3] (1205:1205:1205) (1215:1215:1215)) - (PORT d[4] (1924:1924:1924) (1947:1947:1947)) - (PORT d[5] (876:876:876) (884:884:884)) - (PORT d[6] (1101:1101:1101) (1092:1092:1092)) - (PORT d[7] (2454:2454:2454) (2524:2524:2524)) - (PORT d[8] (1447:1447:1447) (1488:1488:1488)) - (PORT d[9] (406:406:406) (428:428:428)) - (PORT d[10] (398:398:398) (419:419:419)) - (PORT d[11] (2578:2578:2578) (2674:2674:2674)) - (PORT d[12] (693:693:693) (716:716:716)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) + (PORT d[0] (1970:1970:1970) (2015:2015:2015)) + (PORT d[1] (1815:1815:1815) (1862:1862:1862)) + (PORT d[2] (2844:2844:2844) (2918:2918:2918)) + (PORT d[3] (2042:2042:2042) (2120:2120:2120)) + (PORT d[4] (3949:3949:3949) (4107:4107:4107)) + (PORT d[5] (2812:2812:2812) (2876:2876:2876)) + (PORT d[6] (2040:2040:2040) (2090:2090:2090)) + (PORT d[7] (1933:1933:1933) (1987:1987:1987)) + (PORT d[8] (2736:2736:2736) (2781:2781:2781)) + (PORT d[9] (3350:3350:3350) (3473:3473:3473)) + (PORT d[10] (1837:1837:1837) (1946:1946:1946)) + (PORT d[11] (2484:2484:2484) (2556:2556:2556)) + (PORT d[12] (1576:1576:1576) (1672:1672:1672)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) ) ) (TIMINGCHECK @@ -46516,11 +41693,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1143:1143:1143) (1102:1102:1102)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) + (PORT d[0] (1569:1569:1569) (1505:1505:1505)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) ) ) (TIMINGCHECK @@ -46529,60 +41706,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (1583:1583:1583) (1522:1522:1522)) + (PORT clk (1631:1631:1631) (1657:1657:1657)) + (PORT d[0] (2839:2839:2839) (2856:2856:2856)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT clk (1632:1632:1632) (1658:1658:1658)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT clk (1632:1632:1632) (1658:1658:1658)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT clk (1632:1632:1632) (1658:1658:1658)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT clk (1632:1632:1632) (1658:1658:1658)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) + (PORT clk (1590:1590:1590) (1587:1587:1587)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -46593,65 +41770,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (878:878:878)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1109:1109:1109) (1149:1149:1149)) - (PORT datad (1348:1348:1348) (1334:1334:1334)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1115:1115:1115) (1080:1080:1080)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (948:948:948) (959:959:959)) + (PORT clk (1598:1598:1598) (1594:1594:1594)) ) ) (TIMINGCHECK @@ -46660,23 +41783,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2877:2877:2877) (2953:2953:2953)) - (PORT d[1] (1951:1951:1951) (1976:1976:1976)) - (PORT d[2] (1498:1498:1498) (1544:1544:1544)) - (PORT d[3] (1410:1410:1410) (1446:1446:1446)) - (PORT d[4] (2502:2502:2502) (2567:2567:2567)) - (PORT d[5] (1454:1454:1454) (1489:1489:1489)) - (PORT d[6] (1403:1403:1403) (1422:1422:1422)) - (PORT d[7] (1786:1786:1786) (1801:1801:1801)) - (PORT d[8] (3238:3238:3238) (3291:3291:3291)) - (PORT d[9] (1314:1314:1314) (1390:1390:1390)) - (PORT d[10] (1538:1538:1538) (1589:1589:1589)) - (PORT d[11] (1732:1732:1732) (1777:1777:1777)) - (PORT d[12] (1537:1537:1537) (1603:1603:1603)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) + (PORT d[0] (3880:3880:3880) (3901:3901:3901)) + (PORT d[1] (3919:3919:3919) (3919:3919:3919)) + (PORT d[2] (3868:3868:3868) (3778:3778:3778)) + (PORT d[3] (3901:3901:3901) (3837:3837:3837)) + (PORT d[4] (3877:3877:3877) (3846:3846:3846)) + (PORT d[5] (3984:3984:3984) (4134:4134:4134)) + (PORT d[6] (3927:3927:3927) (4031:4031:4031)) + (PORT d[7] (4065:4065:4065) (4053:4053:4053)) + (PORT d[8] (3930:3930:3930) (3828:3828:3828)) + (PORT d[9] (3780:3780:3780) (3678:3678:3678)) + (PORT d[10] (3821:3821:3821) (3731:3731:3731)) + (PORT d[11] (3885:3885:3885) (3832:3832:3832)) + (PORT d[12] (3998:3998:3998) (3879:3879:3879)) + (PORT clk (1595:1595:1595) (1591:1591:1591)) ) ) (TIMINGCHECK @@ -46685,174 +41808,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1370:1370:1370) (1334:1334:1334)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (PORT d[0] (2632:2632:2632) (2634:2634:2634)) + (PORT clk (1598:1598:1598) (1594:1594:1594)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT clk (1599:1599:1599) (1595:1595:1595)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1593:1593:1593) (1592:1592:1592)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1688:1688:1688) (1685:1685:1685)) - (PORT clk (1601:1601:1601) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4140:4140:4140) (4100:4100:4100)) - (PORT d[1] (4066:4066:4066) (4031:4031:4031)) - (PORT d[2] (4099:4099:4099) (4037:4037:4037)) - (PORT d[3] (3955:3955:3955) (3939:3939:3939)) - (PORT d[4] (4028:4028:4028) (3932:3932:3932)) - (PORT d[5] (4099:4099:4099) (4068:4068:4068)) - (PORT d[6] (4141:4141:4141) (4005:4005:4005)) - (PORT d[7] (4061:4061:4061) (4022:4022:4022)) - (PORT d[8] (4124:4124:4124) (4102:4102:4102)) - (PORT d[9] (4209:4209:4209) (4171:4171:4171)) - (PORT d[10] (4161:4161:4161) (4134:4134:4134)) - (PORT d[11] (4134:4134:4134) (4073:4073:4073)) - (PORT d[12] (4078:4078:4078) (3972:3972:3972)) - (PORT clk (1598:1598:1598) (1596:1596:1596)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1599:1599:1599)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) + (PORT clk (1599:1599:1599) (1595:1595:1595)) (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) + (PORT clk (1599:1599:1599) (1595:1595:1595)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) + (PORT clk (1599:1599:1599) (1595:1595:1595)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1594:1594:1594) (1593:1593:1593)) + (PORT clk (1591:1591:1591) (1588:1588:1588)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -46863,11 +41871,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1140:1140:1140) (1109:1109:1109)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT d[0] (1435:1435:1435) (1459:1459:1459)) + (PORT d[1] (1654:1654:1654) (1623:1623:1623)) + (PORT d[2] (1147:1147:1147) (1148:1148:1148)) + (PORT d[3] (2584:2584:2584) (2676:2676:2676)) + (PORT d[4] (2076:2076:2076) (2148:2148:2148)) + (PORT d[5] (1146:1146:1146) (1145:1145:1145)) + (PORT d[6] (1160:1160:1160) (1155:1155:1155)) + (PORT d[7] (1430:1430:1430) (1450:1450:1450)) + (PORT d[8] (1577:1577:1577) (1574:1574:1574)) + (PORT d[9] (1656:1656:1656) (1687:1687:1687)) + (PORT d[10] (2285:2285:2285) (2363:2363:2363)) + (PORT d[11] (1817:1817:1817) (1836:1836:1836)) + (PORT d[12] (1554:1554:1554) (1635:1635:1635)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -46876,98 +41896,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (2878:2878:2878) (2954:2954:2954)) - (PORT d[1] (1433:1433:1433) (1454:1454:1454)) - (PORT d[2] (1508:1508:1508) (1541:1541:1541)) - (PORT d[3] (1411:1411:1411) (1440:1440:1440)) - (PORT d[4] (2462:2462:2462) (2535:2535:2535)) - (PORT d[5] (1450:1450:1450) (1482:1482:1482)) - (PORT d[6] (1429:1429:1429) (1481:1481:1481)) - (PORT d[7] (1543:1543:1543) (1569:1569:1569)) - (PORT d[8] (1420:1420:1420) (1469:1469:1469)) - (PORT d[9] (1288:1288:1288) (1360:1360:1360)) - (PORT d[10] (1270:1270:1270) (1335:1335:1335)) - (PORT d[11] (1720:1720:1720) (1776:1776:1776)) - (PORT d[12] (1283:1283:1283) (1353:1353:1353)) - (PORT clk (1633:1633:1633) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1309:1309:1309) (1250:1250:1250)) - (PORT clk (1633:1633:1633) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (PORT d[0] (2363:2363:2363) (2353:2353:2353)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1471:1471:1471) (1516:1516:1516)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1595:1595:1595) (1593:1593:1593)) + (PORT clk (1601:1601:1601) (1629:1629:1629)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -46978,108 +41930,441 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1698:1698:1698) (1695:1695:1695)) - (PORT clk (1603:1603:1603) (1600:1600:1600)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4136:4136:4136) (4113:4113:4113)) - (PORT d[1] (4031:4031:4031) (3982:3982:3982)) - (PORT d[2] (4143:4143:4143) (4073:4073:4073)) - (PORT d[3] (3977:3977:3977) (3962:3962:3962)) - (PORT d[4] (3998:3998:3998) (3956:3956:3956)) - (PORT d[5] (4063:4063:4063) (4024:4024:4024)) - (PORT d[6] (4108:4108:4108) (3971:3971:3971)) - (PORT d[7] (4041:4041:4041) (4018:4018:4018)) - (PORT d[8] (4094:4094:4094) (4068:4068:4068)) - (PORT d[9] (4136:4136:4136) (4082:4082:4082)) - (PORT d[10] (4197:4197:4197) (4167:4167:4167)) - (PORT d[11] (4160:4160:4160) (4096:4096:4096)) - (PORT d[12] (4059:4059:4059) (3968:3968:3968)) - (PORT clk (1600:1600:1600) (1597:1597:1597)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) + (PORT clk (872:872:872) (876:876:876)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1601:1601:1601)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + (PORT clk (873:873:873) (877:877:877)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1601:1601:1601)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1601:1601:1601)) + (PORT clk (873:873:873) (877:877:877)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1601:1601:1601)) + (PORT clk (873:873:873) (877:877:877)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1640:1640:1640)) + (PORT datab (1381:1381:1381) (1422:1422:1422)) + (PORT datac (1130:1130:1130) (1145:1145:1145)) + (PORT datad (1410:1410:1410) (1425:1425:1425)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1129:1129:1129)) + (PORT datab (926:926:926) (940:940:940)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (195:195:195) (224:224:224)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~12) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (363:363:363)) + (PORT datab (223:223:223) (262:262:262)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~14) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (331:331:331)) + (PORT datab (1879:1879:1879) (1935:1935:1935)) + (PORT datac (1540:1540:1540) (1514:1514:1514)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (746:746:746)) + (PORT datab (852:852:852) (870:870:870)) + (PORT datac (1733:1733:1733) (1706:1706:1706)) + (PORT datad (177:177:177) (200:200:200)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (780:780:780)) + (PORT datab (1384:1384:1384) (1386:1386:1386)) + (PORT datac (1598:1598:1598) (1614:1614:1614)) + (PORT datad (198:198:198) (239:239:239)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (860:860:860)) + (PORT datab (883:883:883) (888:888:888)) + (PORT datac (1314:1314:1314) (1289:1289:1289)) + (PORT datad (170:170:170) (195:195:195)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (263:263:263)) + (PORT datab (749:749:749) (824:824:824)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (221:221:221) (262:262:262)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1351:1351:1351)) + (PORT ena (1685:1685:1685) (1696:1696:1696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1019:1019:1019)) + (PORT datab (1003:1003:1003) (1086:1086:1086)) + (PORT datac (1550:1550:1550) (1589:1589:1589)) + (PORT datad (763:763:763) (743:743:743)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (713:713:713)) + (PORT datab (1737:1737:1737) (1816:1816:1816)) + (PORT datac (835:835:835) (872:872:872)) + (PORT datad (660:660:660) (716:716:716)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT datab (551:551:551) (544:544:544)) + (PORT datac (1086:1086:1086) (1073:1073:1073)) + (PORT datad (1118:1118:1118) (1164:1164:1164)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (2627:2627:2627) (2663:2663:2663)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (570:570:570) (592:592:592)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (371:371:371)) + (PORT datab (1263:1263:1263) (1369:1369:1369)) + (PORT datac (770:770:770) (798:798:798)) + (PORT datad (1626:1626:1626) (1641:1641:1641)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (842:842:842)) + (PORT datab (635:635:635) (646:646:646)) + (PORT datac (555:555:555) (548:548:548)) + (PORT datad (199:199:199) (231:231:231)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1498:1498:1498)) + (PORT datab (1010:1010:1010) (1019:1019:1019)) + (PORT datac (1694:1694:1694) (1694:1694:1694)) + (PORT datad (1623:1623:1623) (1626:1626:1626)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1634:1634:1634) (1599:1599:1599)) + (PORT datab (584:584:584) (603:603:603)) + (PORT datac (512:512:512) (503:503:503)) + (PORT datad (986:986:986) (973:973:973)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (756:756:756)) + (PORT datab (570:570:570) (571:571:571)) + (PORT datad (746:746:746) (733:733:733)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (634:634:634)) + (PORT datab (543:543:543) (545:545:545)) + (PORT datac (583:583:583) (589:589:589)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (808:808:808)) + (PORT datab (584:584:584) (588:588:588)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (567:567:567) (568:568:568)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (805:805:805)) + (PORT datab (531:531:531) (523:523:523)) + (PORT datac (621:621:621) (655:655:655)) + (PORT datad (1070:1070:1070) (1038:1038:1038)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (811:811:811)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (578:578:578) (569:569:569)) + (PORT datad (505:505:505) (497:497:497)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1999:1999:1999) (2048:2048:2048)) - (PORT d[1] (2191:2191:2191) (2224:2224:2224)) - (PORT d[2] (2259:2259:2259) (2315:2315:2315)) - (PORT d[3] (2146:2146:2146) (2181:2181:2181)) - (PORT d[4] (1897:1897:1897) (1929:1929:1929)) - (PORT d[5] (2232:2232:2232) (2287:2287:2287)) - (PORT d[6] (2281:2281:2281) (2364:2364:2364)) - (PORT d[7] (2348:2348:2348) (2388:2388:2388)) - (PORT d[8] (2351:2351:2351) (2363:2363:2363)) - (PORT d[9] (2152:2152:2152) (2263:2263:2263)) - (PORT d[10] (2791:2791:2791) (2826:2826:2826)) - (PORT d[11] (1943:1943:1943) (1974:1974:1974)) - (PORT d[12] (2104:2104:2104) (2206:2206:2206)) + (PORT d[0] (2711:2711:2711) (2744:2744:2744)) + (PORT d[1] (1983:1983:1983) (2006:2006:2006)) + (PORT d[2] (2442:2442:2442) (2483:2483:2483)) + (PORT d[3] (2165:2165:2165) (2220:2220:2220)) + (PORT d[4] (3164:3164:3164) (3298:3298:3298)) + (PORT d[5] (2419:2419:2419) (2443:2443:2443)) + (PORT d[6] (2616:2616:2616) (2699:2699:2699)) + (PORT d[7] (2498:2498:2498) (2570:2570:2570)) + (PORT d[8] (1949:1949:1949) (1959:1959:1959)) + (PORT d[9] (2365:2365:2365) (2416:2416:2416)) + (PORT d[10] (1846:1846:1846) (1952:1952:1952)) + (PORT d[11] (2115:2115:2115) (2169:2169:2169)) + (PORT d[12] (1763:1763:1763) (1839:1839:1839)) (PORT clk (1646:1646:1646) (1674:1674:1674)) ) ) @@ -47093,7 +42378,7 @@ (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (2415:2415:2415) (2444:2444:2444)) + (PORT d[0] (2589:2589:2589) (2589:2589:2589)) ) ) ) @@ -47160,18 +42445,203 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1118:1118:1118) (1132:1132:1132)) - (PORT datab (666:666:666) (696:696:696)) - (PORT datac (860:860:860) (852:852:852)) - (PORT datad (1118:1118:1118) (1101:1101:1101)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT d[0] (1555:1555:1555) (1590:1590:1590)) + (PORT clk (1655:1655:1655) (1682:1682:1682)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3453:3453:3453) (3460:3460:3460)) + (PORT d[1] (4284:4284:4284) (4292:4292:4292)) + (PORT d[2] (2815:2815:2815) (2815:2815:2815)) + (PORT d[3] (2700:2700:2700) (2812:2812:2812)) + (PORT d[4] (2933:2933:2933) (3071:3071:3071)) + (PORT d[5] (2701:2701:2701) (2711:2711:2711)) + (PORT d[6] (3090:3090:3090) (3166:3166:3166)) + (PORT d[7] (3577:3577:3577) (3605:3605:3605)) + (PORT d[8] (2515:2515:2515) (2571:2571:2571)) + (PORT d[9] (3025:3025:3025) (3116:3116:3116)) + (PORT d[10] (2160:2160:2160) (2281:2281:2281)) + (PORT d[11] (2176:2176:2176) (2217:2217:2217)) + (PORT d[12] (2169:2169:2169) (2290:2290:2290)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2033:2033:2033) (1993:1993:1993)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (PORT d[0] (4342:4342:4342) (4333:4333:4333)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1612:1612:1612)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1312:1312:1312) (1289:1289:1289)) + (PORT clk (1622:1622:1622) (1619:1619:1619)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3854:3854:3854) (3818:3818:3818)) + (PORT d[1] (3954:3954:3954) (3970:3970:3970)) + (PORT d[2] (3884:3884:3884) (3796:3796:3796)) + (PORT d[3] (3984:3984:3984) (3880:3880:3880)) + (PORT d[4] (3847:3847:3847) (3766:3766:3766)) + (PORT d[5] (3892:3892:3892) (3921:3921:3921)) + (PORT d[6] (3909:3909:3909) (3919:3919:3919)) + (PORT d[7] (4073:4073:4073) (4104:4104:4104)) + (PORT d[8] (3882:3882:3882) (3843:3843:3843)) + (PORT d[9] (3891:3891:3891) (3869:3869:3869)) + (PORT d[10] (3910:3910:3910) (3846:3846:3846)) + (PORT d[11] (3920:3920:3920) (3871:3871:3871)) + (PORT d[12] (3894:3894:3894) (3852:3852:3852)) + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1622:1622:1622) (1619:1619:1619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) @@ -47180,20 +42650,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2033:2033:2033) (2075:2075:2075)) - (PORT d[1] (2213:2213:2213) (2255:2255:2255)) - (PORT d[2] (2382:2382:2382) (2422:2422:2422)) - (PORT d[3] (2799:2799:2799) (2812:2812:2812)) - (PORT d[4] (1811:1811:1811) (1878:1878:1878)) - (PORT d[5] (3194:3194:3194) (3207:3207:3207)) - (PORT d[6] (2583:2583:2583) (2584:2584:2584)) - (PORT d[7] (3114:3114:3114) (3084:3084:3084)) - (PORT d[8] (1945:1945:1945) (1976:1976:1976)) - (PORT d[9] (2814:2814:2814) (2873:2873:2873)) - (PORT d[10] (2147:2147:2147) (2145:2145:2145)) - (PORT d[11] (2295:2295:2295) (2359:2359:2359)) - (PORT d[12] (2989:2989:2989) (3069:3069:3069)) - (PORT clk (1652:1652:1652) (1680:1680:1680)) + (PORT d[0] (3264:3264:3264) (3326:3326:3326)) + (PORT d[1] (3432:3432:3432) (3425:3425:3425)) + (PORT d[2] (3129:3129:3129) (3161:3161:3161)) + (PORT d[3] (3221:3221:3221) (3352:3352:3352)) + (PORT d[4] (2698:2698:2698) (2826:2826:2826)) + (PORT d[5] (2496:2496:2496) (2509:2509:2509)) + (PORT d[6] (2886:2886:2886) (2994:2994:2994)) + (PORT d[7] (4154:4154:4154) (4207:4207:4207)) + (PORT d[8] (3087:3087:3087) (3161:3161:3161)) + (PORT d[9] (3631:3631:3631) (3758:3758:3758)) + (PORT d[10] (2933:2933:2933) (3065:3065:3065)) + (PORT d[11] (2756:2756:2756) (2827:2827:2827)) + (PORT d[12] (1911:1911:1911) (2037:2037:2037)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) ) ) (TIMINGCHECK @@ -47205,8 +42675,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1652:1652:1652) (1680:1680:1680)) - (PORT d[0] (2632:2632:2632) (2627:2627:2627)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (4028:4028:4028) (4022:4022:4022)) ) ) ) @@ -47215,7 +42685,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1653:1653:1653) (1681:1681:1681)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -47225,7 +42695,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1619:1619:1619) (1646:1646:1646)) + (PORT clk (1606:1606:1606) (1633:1633:1633)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -47239,7 +42709,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (890:890:890) (893:893:893)) + (PORT clk (877:877:877) (880:880:880)) ) ) ) @@ -47248,7 +42718,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) + (PORT clk (878:878:878) (881:881:881)) ) ) ) @@ -47257,7 +42727,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) + (PORT clk (878:878:878) (881:881:881)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -47267,22 +42737,882 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) + (PORT clk (878:878:878) (881:881:881)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1343:1343:1343) (1341:1341:1341)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3455:3455:3455) (3470:3470:3470)) + (PORT d[1] (3746:3746:3746) (3764:3764:3764)) + (PORT d[2] (2855:2855:2855) (2863:2863:2863)) + (PORT d[3] (2943:2943:2943) (3062:3062:3062)) + (PORT d[4] (3179:3179:3179) (3319:3319:3319)) + (PORT d[5] (2762:2762:2762) (2787:2787:2787)) + (PORT d[6] (2841:2841:2841) (2918:2918:2918)) + (PORT d[7] (4015:4015:4015) (4036:4036:4036)) + (PORT d[8] (2818:2818:2818) (2881:2881:2881)) + (PORT d[9] (3048:3048:3048) (3154:3154:3154)) + (PORT d[10] (2535:2535:2535) (2680:2680:2680)) + (PORT d[11] (2216:2216:2216) (2274:2274:2274)) + (PORT d[12] (2262:2262:2262) (2342:2342:2342)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2000:2000:2000) (1915:1915:1915)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT d[0] (4582:4582:4582) (4573:4573:4573)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1607:1607:1607)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1306:1306:1306) (1266:1266:1266)) + (PORT clk (1616:1616:1616) (1614:1614:1614)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3907:3907:3907) (3856:3856:3856)) + (PORT d[1] (3954:3954:3954) (3960:3960:3960)) + (PORT d[2] (3818:3818:3818) (3734:3734:3734)) + (PORT d[3] (3771:3771:3771) (3679:3679:3679)) + (PORT d[4] (3976:3976:3976) (3846:3846:3846)) + (PORT d[5] (3944:3944:3944) (4022:4022:4022)) + (PORT d[6] (4009:4009:4009) (4013:4013:4013)) + (PORT d[7] (3970:3970:3970) (4006:4006:4006)) + (PORT d[8] (3861:3861:3861) (3814:3814:3814)) + (PORT d[9] (3902:3902:3902) (3873:3873:3873)) + (PORT d[10] (3784:3784:3784) (3708:3708:3708)) + (PORT d[11] (3965:3965:3965) (3914:3914:3914)) + (PORT d[12] (3878:3878:3878) (3809:3809:3809)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1616:1616:1616) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1608:1608:1608)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (822:822:822)) + (PORT datab (1502:1502:1502) (1496:1496:1496)) + (PORT datac (1075:1075:1075) (1060:1060:1060)) + (PORT datad (1118:1118:1118) (1163:1163:1163)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1104:1104:1104)) + (PORT datab (944:944:944) (988:988:988)) + (PORT datac (1462:1462:1462) (1479:1479:1479)) + (PORT datad (547:547:547) (551:551:551)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (907:907:907) (905:905:905)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2276:2276:2276) (2326:2326:2326)) + (PORT d[1] (2047:2047:2047) (2079:2079:2079)) + (PORT d[2] (3115:3115:3115) (3189:3189:3189)) + (PORT d[3] (2007:2007:2007) (2071:2071:2071)) + (PORT d[4] (3954:3954:3954) (4114:4114:4114)) + (PORT d[5] (1935:1935:1935) (1972:1972:1972)) + (PORT d[6] (1769:1769:1769) (1814:1814:1814)) + (PORT d[7] (1897:1897:1897) (1937:1937:1937)) + (PORT d[8] (2728:2728:2728) (2782:2782:2782)) + (PORT d[9] (3365:3365:3365) (3501:3501:3501)) + (PORT d[10] (1844:1844:1844) (1953:1953:1953)) + (PORT d[11] (2208:2208:2208) (2229:2229:2229)) + (PORT d[12] (1606:1606:1606) (1698:1698:1698)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1341:1341:1341) (1289:1289:1289)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (1941:1941:1941) (1922:1922:1922)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1054:1054:1054) (1043:1043:1043)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3258:3258:3258) (3318:3318:3318)) + (PORT d[1] (3182:3182:3182) (3177:3177:3177)) + (PORT d[2] (3396:3396:3396) (3421:3421:3421)) + (PORT d[3] (3511:3511:3511) (3653:3653:3653)) + (PORT d[4] (2651:2651:2651) (2792:2792:2792)) + (PORT d[5] (2494:2494:2494) (2503:2503:2503)) + (PORT d[6] (3130:3130:3130) (3242:3242:3242)) + (PORT d[7] (4423:4423:4423) (4481:4481:4481)) + (PORT d[8] (3344:3344:3344) (3430:3430:3430)) + (PORT d[9] (3592:3592:3592) (3717:3717:3717)) + (PORT d[10] (3183:3183:3183) (3322:3322:3322)) + (PORT d[11] (2747:2747:2747) (2832:2832:2832)) + (PORT d[12] (2203:2203:2203) (2339:2339:2339)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1558:1558:1558) (1475:1475:1475)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (2664:2664:2664) (2595:2595:2595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1277:1277:1277) (1295:1295:1295)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (923:923:923) (932:932:932)) + (PORT d[1] (1909:1909:1909) (1885:1885:1885)) + (PORT d[2] (1206:1206:1206) (1225:1225:1225)) + (PORT d[3] (3102:3102:3102) (3202:3202:3202)) + (PORT d[4] (2129:2129:2129) (2214:2214:2214)) + (PORT d[5] (904:904:904) (917:917:917)) + (PORT d[6] (880:880:880) (889:889:889)) + (PORT d[7] (1141:1141:1141) (1152:1152:1152)) + (PORT d[8] (1338:1338:1338) (1337:1337:1337)) + (PORT d[9] (1385:1385:1385) (1409:1409:1409)) + (PORT d[10] (2298:2298:2298) (2386:2386:2386)) + (PORT d[11] (1885:1885:1885) (1919:1919:1919)) + (PORT d[12] (1253:1253:1253) (1325:1325:1325)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1688:1688:1688) (1655:1655:1655)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (2315:2315:2315) (2267:2267:2267)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1428:1428:1428) (1444:1444:1444)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2677:2677:2677) (2697:2697:2697)) + (PORT d[1] (2598:2598:2598) (2558:2558:2558)) + (PORT d[2] (2413:2413:2413) (2424:2424:2424)) + (PORT d[3] (804:804:804) (816:816:816)) + (PORT d[4] (2376:2376:2376) (2468:2468:2468)) + (PORT d[5] (2817:2817:2817) (2803:2803:2803)) + (PORT d[6] (2975:2975:2975) (3088:3088:3088)) + (PORT d[7] (1323:1323:1323) (1294:1294:1294)) + (PORT d[8] (1091:1091:1091) (1078:1078:1078)) + (PORT d[9] (902:902:902) (915:915:915)) + (PORT d[10] (874:874:874) (886:886:886)) + (PORT d[11] (2642:2642:2642) (2663:2663:2663)) + (PORT d[12] (923:923:923) (935:935:935)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2509:2509:2509) (2430:2430:2430)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (2491:2491:2491) (2389:2389:2389)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~91) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (824:824:824)) - (PORT datab (1217:1217:1217) (1249:1249:1249)) - (PORT datac (163:163:163) (195:195:195)) - (PORT datad (1469:1469:1469) (1460:1460:1460)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) + (PORT dataa (1490:1490:1490) (1532:1532:1532)) + (PORT datab (1294:1294:1294) (1328:1328:1328)) + (PORT datac (1123:1123:1123) (1137:1137:1137)) + (PORT datad (1317:1317:1317) (1310:1310:1310)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -47290,47 +43620,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~92) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) (DELAY (ABSOLUTE - (PORT dataa (910:910:910) (909:909:909)) - (PORT datab (666:666:666) (695:695:695)) - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (287:287:287) (294:294:294)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1330:1330:1330) (1311:1311:1311)) + (PORT datab (1277:1277:1277) (1273:1273:1273)) + (PORT datac (1885:1885:1885) (1898:1898:1898)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~125) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (2374:2374:2374) (2511:2511:2511)) - (PORT datab (1289:1289:1289) (1316:1316:1316)) - (PORT datac (530:530:530) (517:517:517)) - (PORT datad (299:299:299) (297:297:297)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (862:862:862)) - (PORT datab (851:851:851) (852:852:852)) - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (583:583:583) (579:579:579)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (697:697:697) (768:768:768)) + (PORT datab (1082:1082:1082) (1099:1099:1099)) + (PORT datac (642:642:642) (688:688:688)) + (PORT datad (637:637:637) (671:671:671)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -47338,29 +43652,2111 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~111) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~114) (DELAY (ABSOLUTE - (PORT dataa (2077:2077:2077) (2056:2056:2056)) - (PORT datab (405:405:405) (418:418:418)) - (PORT datac (175:175:175) (208:208:208)) - (PORT datad (1169:1169:1169) (1220:1220:1220)) + (PORT dataa (1052:1052:1052) (1030:1030:1030)) + (PORT datab (1357:1357:1357) (1368:1368:1368)) + (PORT datac (902:902:902) (925:925:925)) + (PORT datad (1150:1150:1150) (1180:1180:1180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (870:870:870)) + (PORT datab (699:699:699) (789:789:789)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (241:241:241)) + (PORT datab (248:248:248) (320:320:320)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1667:1667:1667) (1706:1706:1706)) + (PORT datab (1111:1111:1111) (1140:1140:1140)) + (PORT datac (195:195:195) (261:261:261)) + (PORT datad (593:593:593) (635:635:635)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (309:309:309)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (299:299:299)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (301:301:301)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (299:299:299)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (312:312:312)) (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (232:232:232) (307:307:307)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (316:316:316)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (313:313:313)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (238:238:238) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (243:243:243) (317:317:317)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (232:232:232) (307:307:307)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (315:315:315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (310:310:310)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (302:302:302)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (230:230:230) (302:302:302)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (276:276:276)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (635:635:635) (694:694:694)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston_autofire_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (461:461:461) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (322:322:322)) + (PORT datac (210:210:210) (285:285:285)) + (PORT datad (211:211:211) (278:278:278)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (320:320:320)) + (PORT datab (236:236:236) (312:312:312)) + (PORT datac (314:314:314) (323:323:323)) + (PORT datad (360:360:360) (400:400:400)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (866:866:866)) + (PORT datab (248:248:248) (322:322:322)) + (PORT datac (210:210:210) (285:285:285)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datac (202:202:202) (273:273:273)) + (PORT datad (204:204:204) (264:264:264)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (236:236:236) (314:314:314)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (214:214:214) (279:279:279)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (436:436:436)) + (PORT datab (370:370:370) (417:417:417)) + (PORT datac (2952:2952:2952) (3172:3172:3172)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (1024:1024:1024) (1051:1051:1051)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (305:305:305)) + (PORT datab (227:227:227) (300:300:300)) + (PORT datac (200:200:200) (270:270:270)) + (PORT datad (203:203:203) (265:265:265)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (702:702:702)) + (PORT datab (385:385:385) (432:432:432)) + (PORT datac (210:210:210) (287:287:287)) + (PORT datad (210:210:210) (276:276:276)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (317:317:317)) + (PORT datab (234:234:234) (311:311:311)) + (PORT datac (208:208:208) (282:282:282)) + (PORT datad (212:212:212) (276:276:276)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (320:320:320)) + (PORT datab (235:235:235) (310:310:310)) + (PORT datac (209:209:209) (283:283:283)) + (PORT datad (593:593:593) (614:614:614)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (520:520:520)) + (PORT datab (590:590:590) (579:579:579)) + (PORT datac (494:494:494) (481:481:481)) + (PORT datad (560:560:560) (551:551:551)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (593:593:593)) + (PORT datab (2993:2993:2993) (3202:3202:3202)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1594:1594:1594)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_autofire_enabled\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_autofire_enabled) + (DELAY + (ABSOLUTE + (PORT clk (781:781:781) (734:734:734)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (457:457:457)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (308:308:308)) + (PORT datab (228:228:228) (301:301:301)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (310:310:310)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (299:299:299)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[6\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (302:302:302)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[7\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (297:297:297)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[8\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (313:313:313)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (926:926:926) (957:957:957)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[9\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (225:225:225) (298:298:298)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[10\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (297:297:297)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[11\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (298:298:298)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[12\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (303:303:303)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[13\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (299:299:299)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[14\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[15\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (416:416:416)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (368:368:368) (414:414:414)) + (PORT datac (202:202:202) (272:272:272)) + (PORT datad (206:206:206) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (455:455:455)) + (PORT datab (230:230:230) (304:304:304)) + (PORT datac (203:203:203) (275:275:275)) + (PORT datad (206:206:206) (268:268:268)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (308:308:308)) + (PORT datab (228:228:228) (302:302:302)) + (PORT datac (352:352:352) (390:390:390)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (229:229:229) (303:303:303)) + (PORT datac (205:205:205) (277:277:277)) + (PORT datad (206:206:206) (268:268:268)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (580:580:580) (574:574:574)) + (PORT datad (520:520:520) (504:504:504)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[16\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (303:303:303)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[17\]\~49) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (266:266:266)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1194:1194:1194) (1219:1219:1219)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire\~0) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (334:334:334)) + (PORT datab (230:230:230) (304:304:304)) + (PORT datad (206:206:206) (264:264:264)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT sload (1201:1201:1201) (1193:1193:1193)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (853:853:853)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (1291:1291:1291) (1324:1324:1324)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (718:718:718)) + (PORT datab (848:848:848) (881:881:881)) + (PORT datac (857:857:857) (905:905:905)) + (PORT datad (883:883:883) (901:901:901)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (562:562:562)) + (PORT datab (694:694:694) (782:782:782)) + (PORT datad (167:167:167) (190:190:190)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (722:722:722)) + (PORT datab (840:840:840) (871:871:871)) + (PORT datac (657:657:657) (735:735:735)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (331:331:331)) + (PORT datab (641:641:641) (704:704:704)) + (PORT datac (861:861:861) (889:889:889)) + (PORT datad (336:336:336) (345:345:345)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (964:964:964)) + (PORT datab (695:695:695) (782:782:782)) + (PORT datad (560:560:560) (566:566:566)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (293:293:293)) + (PORT datab (1972:1972:1972) (2058:2058:2058)) + (PORT datac (2323:2323:2323) (2313:2313:2313)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (764:764:764)) + (PORT datab (277:277:277) (362:362:362)) + (PORT datac (1343:1343:1343) (1362:1362:1362)) + (PORT datad (647:647:647) (677:677:677)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (804:804:804) (840:840:840)) + (PORT datad (657:657:657) (712:712:712)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (562:562:562)) + (PORT datab (589:589:589) (580:580:580)) + (PORT datad (910:910:910) (953:953:953)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (731:731:731)) + (PORT datab (437:437:437) (478:478:478)) + (PORT datad (686:686:686) (756:756:756)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (858:858:858)) + (PORT datab (686:686:686) (734:734:734)) + (PORT datac (248:248:248) (333:333:333)) + (PORT datad (659:659:659) (721:721:721)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (377:377:377)) + (PORT datab (714:714:714) (749:749:749)) + (PORT datac (654:654:654) (723:723:723)) + (PORT datad (545:545:545) (539:539:539)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (230:230:230)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1364:1364:1364)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (635:635:635)) + (PORT datab (2168:2168:2168) (2189:2189:2189)) + (PORT datac (593:593:593) (616:616:616)) + (PORT datad (1808:1808:1808) (1919:1919:1919)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (355:355:355)) + (PORT datab (207:207:207) (244:244:244)) + (PORT datad (223:223:223) (284:284:284)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1378:1378:1378) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (383:383:383)) + (PORT datab (820:820:820) (848:848:848)) + (PORT datac (364:364:364) (421:421:421)) + (PORT datad (688:688:688) (761:761:761)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT datab (666:666:666) (725:725:725)) + (PORT datad (641:641:641) (686:686:686)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (665:665:665)) + (PORT datac (646:646:646) (687:687:687)) + (PORT datad (883:883:883) (901:901:901)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (598:598:598)) + (PORT datab (324:324:324) (349:349:349)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (799:799:799)) + (PORT datab (2083:2083:2083) (2116:2116:2116)) + (PORT datac (877:877:877) (912:912:912)) + (PORT datad (1601:1601:1601) (1603:1603:1603)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (842:842:842)) + (PORT datab (785:785:785) (783:783:783)) + (PORT datac (759:759:759) (754:754:754)) + (PORT datad (555:555:555) (559:559:559)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~6) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (594:594:594)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (812:812:812) (803:803:803)) + (PORT datad (1549:1549:1549) (1601:1601:1601)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~7) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (776:776:776) (764:764:764)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1355:1355:1355)) + (PORT datab (1031:1031:1031) (1075:1075:1075)) + (PORT datac (1138:1138:1138) (1144:1144:1144)) + (PORT datad (178:178:178) (198:198:198)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1559:1559:1559) (1617:1617:1617)) - (PORT datab (382:382:382) (415:415:415)) - (PORT datac (501:501:501) (489:489:489)) - (PORT datad (1049:1049:1049) (1028:1028:1028)) + (PORT dataa (968:968:968) (982:982:982)) + (PORT datab (231:231:231) (283:283:283)) + (PORT datac (1360:1360:1360) (1366:1366:1366)) + (PORT datad (830:830:830) (838:838:838)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -47373,197 +45769,7 @@ (INSTANCE z80_\|data_pins_\|dout\[4\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (313:313:313)) - (PORT datab (392:392:392) (400:400:400)) - (PORT datad (358:358:358) (368:368:368)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1033:1033:1033)) - (PORT datab (311:311:311) (329:329:329)) - (PORT datac (490:490:490) (480:480:480)) - (PORT datad (198:198:198) (226:226:226)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (832:832:832) (819:819:819)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1804:1804:1804) (1767:1767:1767)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datac (1788:1788:1788) (1789:1789:1789)) - (PORT datad (2385:2385:2385) (2404:2404:2404)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (833:833:833)) - (PORT datab (625:625:625) (630:630:630)) - (PORT datac (1901:1901:1901) (1972:1972:1972)) - (PORT datad (1330:1330:1330) (1299:1299:1299)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (259:259:259)) - (PORT datab (847:847:847) (859:859:859)) - (PORT datac (1615:1615:1615) (1640:1640:1640)) - (PORT datad (593:593:593) (610:610:610)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (635:635:635)) - (PORT datab (363:363:363) (383:383:383)) - (PORT datac (1300:1300:1300) (1335:1335:1335)) - (PORT datad (330:330:330) (339:339:339)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2142:2142:2142) (2194:2194:2194)) - (PORT datab (1506:1506:1506) (1483:1483:1483)) - (PORT datac (1247:1247:1247) (1363:1363:1363)) - (PORT datad (1194:1194:1194) (1145:1145:1145)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) - (PORT asdata (1116:1116:1116) (1117:1117:1117)) - (PORT clrn (1408:1408:1408) (1376:1376:1376)) - (PORT ena (906:906:906) (903:903:903)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (671:671:671)) - (PORT datab (856:856:856) (857:857:857)) - (PORT datac (972:972:972) (983:983:983)) - (PORT datad (1094:1094:1094) (1125:1125:1125)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (770:770:770)) - (PORT datab (1050:1050:1050) (1048:1048:1048)) - (PORT datac (962:962:962) (937:937:937)) - (PORT datad (768:768:768) (757:757:757)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT clk (1341:1341:1341) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -47576,15 +45782,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[4\]\~17) (DELAY (ABSOLUTE - (PORT dataa (558:558:558) (570:570:570)) - (PORT datab (1082:1082:1082) (1083:1083:1083)) - (PORT datac (608:608:608) (632:632:632)) - (PORT datad (547:547:547) (546:546:546)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (231:231:231) (285:285:285)) + (PORT datac (586:586:586) (618:618:618)) + (PORT datad (216:216:216) (258:258:258)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (884:884:884)) + (PORT datab (626:626:626) (616:616:616)) + (PORT datac (1357:1357:1357) (1348:1348:1348)) + (PORT datad (719:719:719) (770:770:770)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (308:308:308)) + (PORT datad (224:224:224) (256:256:256)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT clrn (1383:1383:1383) (1357:1357:1357)) + (PORT ena (1599:1599:1599) (1565:1565:1565)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1108:1108:1108)) + (PORT datab (415:415:415) (472:472:472)) + (PORT datad (619:619:619) (666:666:666)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (769:769:769)) + (PORT datab (869:869:869) (858:858:858)) + (PORT datac (571:571:571) (596:596:596)) + (PORT datad (514:514:514) (506:506:506)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (863:863:863)) + (PORT datab (813:813:813) (811:811:811)) + (PORT datac (1040:1040:1040) (1021:1021:1021)) + (PORT datad (1052:1052:1052) (1032:1032:1032)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -47592,13 +45888,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~16) + (INSTANCE z80_\|alu_control_\|db\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (779:779:779) (808:808:808)) - (PORT datab (572:572:572) (578:578:578)) - (PORT datac (1301:1301:1301) (1331:1331:1331)) - (PORT datad (567:567:567) (574:574:574)) + (PORT dataa (1077:1077:1077) (1105:1105:1105)) + (PORT datab (362:362:362) (367:367:367)) + (PORT datad (588:588:588) (608:608:608)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (343:343:343)) + (PORT datab (647:647:647) (662:662:662)) + (PORT datac (538:538:538) (527:527:527)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -47608,27 +45918,618 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (INSTANCE z80_\|alu_control_\|db\[1\]\~22) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (223:223:223)) - (PORT datab (1039:1039:1039) (1003:1003:1003)) - (PORT datac (783:783:783) (773:773:773)) - (PORT datad (184:184:184) (207:207:207)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (531:531:531) (519:519:519)) + (PORT datad (194:194:194) (227:227:227)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~9) (DELAY (ABSOLUTE - (PORT d[0] (1369:1369:1369) (1343:1343:1343)) - (PORT clk (1631:1631:1631) (1657:1657:1657)) + (PORT dataa (806:806:806) (823:823:823)) + (PORT datac (333:333:333) (338:338:338)) + (PORT datad (1204:1204:1204) (1212:1212:1212)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (436:436:436) (481:481:481)) + (PORT datac (655:655:655) (723:723:723)) + (PORT datad (649:649:649) (697:697:697)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (704:704:704) (748:748:748)) + (PORT datac (789:789:789) (815:815:815)) + (PORT datad (674:674:674) (708:708:708)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1364:1364:1364)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (823:823:823)) + (PORT datab (922:922:922) (954:954:954)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (669:669:669)) + (PORT datab (1974:1974:1974) (2059:2059:2059)) + (PORT datac (2320:2320:2320) (2312:2312:2312)) + (PORT datad (571:571:571) (593:593:593)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (611:611:611)) + (PORT datab (711:711:711) (784:784:784)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (967:967:967)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datad (909:909:909) (955:955:955)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2040:2040:2040) (2128:2128:2128)) + (PORT datab (354:354:354) (403:403:403)) + (PORT datac (2076:2076:2076) (2077:2077:2077)) + (PORT datad (354:354:354) (387:387:387)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1583:1583:1583)) + (PORT datab (626:626:626) (682:682:682)) + (PORT datac (240:240:240) (334:334:334)) + (PORT datad (230:230:230) (293:293:293)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (934:934:934)) + (PORT datab (681:681:681) (724:724:724)) + (PORT datac (885:885:885) (916:916:916)) + (PORT datad (866:866:866) (925:925:925)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (942:942:942)) + (PORT datac (880:880:880) (910:910:910)) + (PORT datad (650:650:650) (697:697:697)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (221:221:221)) + (PORT datab (637:637:637) (687:687:687)) + (PORT datac (857:857:857) (906:906:906)) + (PORT datad (187:187:187) (212:212:212)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (752:752:752)) + (PORT datab (689:689:689) (736:736:736)) + (PORT datac (249:249:249) (331:331:331)) + (PORT datad (394:394:394) (436:436:436)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (766:766:766)) + (PORT datab (800:800:800) (836:836:836)) + (PORT datac (735:735:735) (707:707:707)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (558:558:558)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (646:646:646) (703:703:703)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1352:1352:1352)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (698:698:698) (786:786:786)) + (PORT datac (616:616:616) (652:652:652)) + (PORT datad (1337:1337:1337) (1346:1346:1346)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (756:756:756)) + (PORT datab (679:679:679) (727:727:727)) + (PORT datac (774:774:774) (811:811:811)) + (PORT datad (388:388:388) (430:430:430)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datac (251:251:251) (335:335:335)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datad (309:309:309) (319:319:319)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1667:1667:1667) (1706:1706:1706)) + (PORT datab (382:382:382) (418:418:418)) + (PORT datac (1083:1083:1083) (1111:1111:1111)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (680:680:680) (735:735:735)) + (PORT datac (228:228:228) (301:301:301)) + (PORT datad (837:837:837) (852:852:852)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (725:725:725)) + (PORT datab (681:681:681) (714:714:714)) + (PORT datac (230:230:230) (306:306:306)) + (PORT datad (650:650:650) (723:723:723)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (725:725:725)) + (PORT datab (397:397:397) (460:460:460)) + (PORT datac (1052:1052:1052) (1071:1071:1071)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (554:554:554) (562:562:562)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (568:568:568)) + (PORT datab (932:932:932) (950:950:950)) + (PORT datac (840:840:840) (843:843:843)) + (PORT datad (1322:1322:1322) (1337:1337:1337)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (698:698:698) (787:787:787)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1353:1353:1353)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4107:4107:4107) (4239:4239:4239)) + (PORT datab (3017:3017:3017) (3067:3067:3067)) + (PORT datac (586:586:586) (615:615:615)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~4) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (853:853:853)) + (PORT datab (785:785:785) (782:782:782)) + (PORT datac (809:809:809) (799:799:799)) + (PORT datad (1339:1339:1339) (1381:1381:1381)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (634:634:634) (643:643:643)) + (PORT clk (1638:1638:1638) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -47637,23 +46538,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2864:2864:2864) (2925:2925:2925)) - (PORT d[1] (1709:1709:1709) (1735:1735:1735)) - (PORT d[2] (1538:1538:1538) (1578:1578:1578)) - (PORT d[3] (1996:1996:1996) (2051:2051:2051)) - (PORT d[4] (2211:2211:2211) (2258:2258:2258)) - (PORT d[5] (1915:1915:1915) (1940:1940:1940)) - (PORT d[6] (1725:1725:1725) (1793:1793:1793)) - (PORT d[7] (1829:1829:1829) (1859:1859:1859)) - (PORT d[8] (3188:3188:3188) (3236:3236:3236)) - (PORT d[9] (1599:1599:1599) (1687:1687:1687)) - (PORT d[10] (3579:3579:3579) (3632:3632:3632)) - (PORT d[11] (2472:2472:2472) (2519:2519:2519)) - (PORT d[12] (2278:2278:2278) (2358:2358:2358)) - (PORT clk (1628:1628:1628) (1655:1655:1655)) + (PORT d[0] (2273:2273:2273) (2315:2315:2315)) + (PORT d[1] (1801:1801:1801) (1840:1840:1840)) + (PORT d[2] (3110:3110:3110) (3196:3196:3196)) + (PORT d[3] (1749:1749:1749) (1812:1812:1812)) + (PORT d[4] (1710:1710:1710) (1753:1753:1753)) + (PORT d[5] (1910:1910:1910) (1956:1956:1956)) + (PORT d[6] (1454:1454:1454) (1492:1492:1492)) + (PORT d[7] (1646:1646:1646) (1686:1686:1686)) + (PORT d[8] (3005:3005:3005) (3070:3070:3070)) + (PORT d[9] (3674:3674:3674) (3820:3820:3820)) + (PORT d[10] (1858:1858:1858) (1953:1953:1953)) + (PORT d[11] (2257:2257:2257) (2291:2291:2291)) + (PORT d[12] (1591:1591:1591) (1695:1695:1695)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -47662,11 +46563,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2149:2149:2149) (2099:2099:2099)) - (PORT clk (1628:1628:1628) (1655:1655:1655)) + (PORT d[0] (1102:1102:1102) (1054:1054:1054)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -47675,60 +46576,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1631:1631:1631) (1657:1657:1657)) - (PORT d[0] (2628:2628:2628) (2625:2625:2625)) + (PORT clk (1638:1638:1638) (1664:1664:1664)) + (PORT d[0] (1650:1650:1650) (1624:1624:1624)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1590:1590:1590) (1587:1587:1587)) + (PORT clk (1602:1602:1602) (1628:1628:1628)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -47739,108 +46640,1125 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1680:1680:1680) (1682:1682:1682)) - (PORT clk (1598:1598:1598) (1594:1594:1594)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4049:4049:4049) (3977:3977:3977)) - (PORT d[1] (3968:3968:3968) (3990:3990:3990)) - (PORT d[2] (4092:4092:4092) (4022:4022:4022)) - (PORT d[3] (3942:3942:3942) (3914:3914:3914)) - (PORT d[4] (4113:4113:4113) (4038:4038:4038)) - (PORT d[5] (4075:4075:4075) (4052:4052:4052)) - (PORT d[6] (4048:4048:4048) (3929:3929:3929)) - (PORT d[7] (4042:4042:4042) (4014:4014:4014)) - (PORT d[8] (4128:4128:4128) (4009:4009:4009)) - (PORT d[9] (4147:4147:4147) (4084:4084:4084)) - (PORT d[10] (4100:4100:4100) (4051:4051:4051)) - (PORT d[11] (4146:4146:4146) (4095:4095:4095)) - (PORT d[12] (4020:4020:4020) (3883:3883:3883)) - (PORT clk (1595:1595:1595) (1591:1591:1591)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1594:1594:1594)) + (PORT clk (873:873:873) (875:875:875)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) + (PORT clk (874:874:874) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~10) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (607:607:607)) + (PORT datac (1047:1047:1047) (1072:1072:1072)) + (PORT datad (1369:1369:1369) (1432:1432:1432)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (802:802:802) (796:796:796)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3249:3249:3249) (3300:3300:3300)) + (PORT d[1] (3178:3178:3178) (3169:3169:3169)) + (PORT d[2] (3393:3393:3393) (3440:3440:3440)) + (PORT d[3] (3515:3515:3515) (3654:3654:3654)) + (PORT d[4] (2932:2932:2932) (3071:3071:3071)) + (PORT d[5] (2483:2483:2483) (2503:2503:2503)) + (PORT d[6] (3156:3156:3156) (3271:3271:3271)) + (PORT d[7] (4401:4401:4401) (4459:4459:4459)) + (PORT d[8] (3360:3360:3360) (3446:3446:3446)) + (PORT d[9] (3592:3592:3592) (3718:3718:3718)) + (PORT d[10] (3210:3210:3210) (3351:3351:3351)) + (PORT d[11] (3000:3000:3000) (3082:3082:3082)) + (PORT d[12] (2174:2174:2174) (2304:2304:2304)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2374:2374:2374) (2324:2324:2324)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2034:2034:2034) (1990:1990:1990)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) + (PORT clk (882:882:882) (884:884:884)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1550:1550:1550) (1606:1606:1606)) - (PORT d[1] (2532:2532:2532) (2555:2555:2555)) - (PORT d[2] (2382:2382:2382) (2423:2423:2423)) - (PORT d[3] (2288:2288:2288) (2312:2312:2312)) - (PORT d[4] (2270:2270:2270) (2269:2269:2269)) - (PORT d[5] (2680:2680:2680) (2702:2702:2702)) - (PORT d[6] (2582:2582:2582) (2591:2591:2591)) - (PORT d[7] (2965:2965:2965) (2961:2961:2961)) - (PORT d[8] (2156:2156:2156) (2169:2169:2169)) - (PORT d[9] (2831:2831:2831) (2893:2893:2893)) - (PORT d[10] (2156:2156:2156) (2158:2158:2158)) - (PORT d[11] (2330:2330:2330) (2394:2394:2394)) - (PORT d[12] (2720:2720:2720) (2792:2792:2792)) + (PORT d[0] (933:933:933) (939:939:939)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2288:2288:2288) (2337:2337:2337)) + (PORT d[1] (1783:1783:1783) (1818:1818:1818)) + (PORT d[2] (3104:3104:3104) (3187:3187:3187)) + (PORT d[3] (1776:1776:1776) (1845:1845:1845)) + (PORT d[4] (1762:1762:1762) (1814:1814:1814)) + (PORT d[5] (1657:1657:1657) (1683:1683:1683)) + (PORT d[6] (2345:2345:2345) (2425:2425:2425)) + (PORT d[7] (1673:1673:1673) (1717:1717:1717)) + (PORT d[8] (2728:2728:2728) (2783:2783:2783)) + (PORT d[9] (3366:3366:3366) (3502:3502:3502)) + (PORT d[10] (1851:1851:1851) (1970:1970:1970)) + (PORT d[11] (2197:2197:2197) (2227:2227:2227)) + (PORT d[12] (1564:1564:1564) (1662:1662:1662)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1127:1127:1127) (1093:1093:1093)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT d[0] (1586:1586:1586) (1567:1567:1567)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1627:1627:1627)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2502:2502:2502) (2562:2562:2562)) + (PORT d[1] (2039:2039:2039) (2067:2067:2067)) + (PORT d[2] (2438:2438:2438) (2485:2485:2485)) + (PORT d[3] (2622:2622:2622) (2649:2649:2649)) + (PORT d[4] (3408:3408:3408) (3539:3539:3539)) + (PORT d[5] (2727:2727:2727) (2765:2765:2765)) + (PORT d[6] (2616:2616:2616) (2699:2699:2699)) + (PORT d[7] (2472:2472:2472) (2541:2541:2541)) + (PORT d[8] (2158:2158:2158) (2179:2179:2179)) + (PORT d[9] (2448:2448:2448) (2549:2549:2549)) + (PORT d[10] (1866:1866:1866) (1968:1968:1968)) + (PORT d[11] (2178:2178:2178) (2213:2213:2213)) + (PORT d[12] (1840:1840:1840) (1931:1931:1931)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2587:2587:2587) (2587:2587:2587)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1640:1640:1640)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1317:1317:1317) (1325:1325:1325)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2691:2691:2691) (2723:2723:2723)) + (PORT d[1] (2584:2584:2584) (2546:2546:2546)) + (PORT d[2] (2405:2405:2405) (2428:2428:2428)) + (PORT d[3] (1590:1590:1590) (1608:1608:1608)) + (PORT d[4] (2974:2974:2974) (3141:3141:3141)) + (PORT d[5] (2830:2830:2830) (2826:2826:2826)) + (PORT d[6] (3706:3706:3706) (3846:3846:3846)) + (PORT d[7] (1360:1360:1360) (1333:1333:1333)) + (PORT d[8] (1054:1054:1054) (1043:1043:1043)) + (PORT d[9] (4171:4171:4171) (4316:4316:4316)) + (PORT d[10] (3839:3839:3839) (4004:4004:4004)) + (PORT d[11] (3320:3320:3320) (3431:3431:3431)) + (PORT d[12] (870:870:870) (858:858:858)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2810:2810:2810) (2735:2735:2735)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (2723:2723:2723) (2625:2625:2625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~7) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (949:949:949)) + (PORT datab (1137:1137:1137) (1127:1127:1127)) + (PORT datac (1289:1289:1289) (1292:1292:1292)) + (PORT datad (361:361:361) (368:368:368)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1161:1161:1161)) + (PORT datac (1567:1567:1567) (1585:1585:1585)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1909:1909:1909) (1935:1935:1935)) + (PORT datab (1457:1457:1457) (1411:1411:1411)) + (PORT datac (1912:1912:1912) (1901:1901:1901)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1191:1191:1191) (1203:1203:1203)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1980:1980:1980) (2016:2016:2016)) + (PORT d[1] (1517:1517:1517) (1547:1547:1547)) + (PORT d[2] (2844:2844:2844) (2919:2919:2919)) + (PORT d[3] (2038:2038:2038) (2112:2112:2112)) + (PORT d[4] (3954:3954:3954) (4113:4113:4113)) + (PORT d[5] (3084:3084:3084) (3139:3139:3139)) + (PORT d[6] (2306:2306:2306) (2382:2382:2382)) + (PORT d[7] (1931:1931:1931) (1986:1986:1986)) + (PORT d[8] (1942:1942:1942) (1965:1965:1965)) + (PORT d[9] (3359:3359:3359) (3493:3493:3493)) + (PORT d[10] (1848:1848:1848) (1961:1961:1961)) + (PORT d[11] (1894:1894:1894) (1899:1899:1899)) + (PORT d[12] (1580:1580:1580) (1677:1677:1677)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1586:1586:1586) (1523:1523:1523)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1660:1660:1660)) + (PORT d[0] (2837:2837:2837) (2851:2851:2851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1590:1590:1590)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1193:1193:1193) (1192:1192:1192)) + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3811:3811:3811) (3788:3788:3788)) + (PORT d[1] (4024:4024:4024) (3937:3937:3937)) + (PORT d[2] (3890:3890:3890) (3835:3835:3835)) + (PORT d[3] (3955:3955:3955) (3896:3896:3896)) + (PORT d[4] (3944:3944:3944) (3914:3914:3914)) + (PORT d[5] (3877:3877:3877) (3870:3870:3870)) + (PORT d[6] (3906:3906:3906) (4009:4009:4009)) + (PORT d[7] (3893:3893:3893) (3918:3918:3918)) + (PORT d[8] (3962:3962:3962) (3857:3857:3857)) + (PORT d[9] (3906:3906:3906) (3853:3853:3853)) + (PORT d[10] (3790:3790:3790) (3724:3724:3724)) + (PORT d[11] (3898:3898:3898) (3816:3816:3816)) + (PORT d[12] (4094:4094:4094) (4007:4007:4007)) + (PORT clk (1595:1595:1595) (1594:1594:1594)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1591:1591:1591) (1591:1591:1591)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1405:1405:1405)) + (PORT datab (2564:2564:2564) (2579:2579:2579)) + (PORT datac (827:827:827) (825:825:825)) + (PORT datad (1322:1322:1322) (1291:1291:1291)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1902:1902:1902) (1918:1918:1918)) + (PORT datab (941:941:941) (985:985:985)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1259:1259:1259) (1254:1254:1254)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3533:3533:3533) (3606:3606:3606)) + (PORT d[1] (3703:3703:3703) (3699:3699:3699)) + (PORT d[2] (2858:2858:2858) (2875:2875:2875)) + (PORT d[3] (3206:3206:3206) (3325:3325:3325)) + (PORT d[4] (3220:3220:3220) (3357:3357:3357)) + (PORT d[5] (2734:2734:2734) (2757:2757:2757)) + (PORT d[6] (2870:2870:2870) (2963:2963:2963)) + (PORT d[7] (4114:4114:4114) (4152:4152:4152)) + (PORT d[8] (2786:2786:2786) (2851:2851:2851)) + (PORT d[9] (3316:3316:3316) (3430:3430:3430)) + (PORT d[10] (2896:2896:2896) (3015:3015:3015)) + (PORT d[11] (2485:2485:2485) (2550:2550:2550)) + (PORT d[12] (1897:1897:1897) (2011:2011:2011)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2238:2238:2238) (2164:2164:2164)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (4817:4817:4817) (4814:4814:4814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1252:1252:1252) (1209:1209:1209)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3785:3785:3785) (3743:3743:3743)) + (PORT d[1] (3956:3956:3956) (3959:3959:3959)) + (PORT d[2] (3973:3973:3973) (3845:3845:3845)) + (PORT d[3] (3870:3870:3870) (3814:3814:3814)) + (PORT d[4] (3817:3817:3817) (3747:3747:3747)) + (PORT d[5] (3920:3920:3920) (3999:3999:3999)) + (PORT d[6] (4032:4032:4032) (4047:4047:4047)) + (PORT d[7] (3966:3966:3966) (4000:4000:4000)) + (PORT d[8] (3858:3858:3858) (3796:3796:3796)) + (PORT d[9] (3911:3911:3911) (3862:3862:3862)) + (PORT d[10] (3805:3805:3805) (3722:3722:3722)) + (PORT d[11] (3955:3955:3955) (3908:3908:3908)) + (PORT d[12] (3905:3905:3905) (3863:3863:3863)) + (PORT clk (1607:1607:1607) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3143:3143:3143) (3140:3140:3140)) + (PORT d[1] (4028:4028:4028) (4056:4056:4056)) + (PORT d[2] (2578:2578:2578) (2612:2612:2612)) + (PORT d[3] (2673:2673:2673) (2764:2764:2764)) + (PORT d[4] (2706:2706:2706) (2822:2822:2822)) + (PORT d[5] (2486:2486:2486) (2498:2498:2498)) + (PORT d[6] (3086:3086:3086) (3159:3159:3159)) + (PORT d[7] (3556:3556:3556) (3575:3575:3575)) + (PORT d[8] (2501:2501:2501) (2543:2543:2543)) + (PORT d[9] (2781:2781:2781) (2873:2873:2873)) + (PORT d[10] (2391:2391:2391) (2501:2501:2501)) + (PORT d[11] (2178:2178:2178) (2225:2225:2225)) + (PORT d[12] (2189:2189:2189) (2318:2318:2318)) (PORT clk (1654:1654:1654) (1681:1681:1681)) ) ) @@ -47850,17 +47768,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (2640:2640:2640) (2655:2655:2655)) + (PORT d[0] (3482:3482:3482) (3468:3468:3468)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1655:1655:1655) (1682:1682:1682)) @@ -47870,7 +47788,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1621:1621:1621) (1647:1647:1647)) @@ -47884,7 +47802,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (892:892:892) (894:894:894)) @@ -47893,7 +47811,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (893:893:893) (895:895:895)) @@ -47902,7 +47820,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (893:893:893) (895:895:895)) @@ -47912,7 +47830,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (893:893:893) (895:895:895)) @@ -47920,330 +47838,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1300:1300:1300) (1280:1280:1280)) - (PORT clk (1639:1639:1639) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1802:1802:1802) (1849:1849:1849)) - (PORT d[1] (2798:2798:2798) (2853:2853:2853)) - (PORT d[2] (1619:1619:1619) (1651:1651:1651)) - (PORT d[3] (3350:3350:3350) (3374:3374:3374)) - (PORT d[4] (2431:2431:2431) (2518:2518:2518)) - (PORT d[5] (3783:3783:3783) (3829:3829:3829)) - (PORT d[6] (2127:2127:2127) (2130:2130:2130)) - (PORT d[7] (3433:3433:3433) (3423:3423:3423)) - (PORT d[8] (1763:1763:1763) (1812:1812:1812)) - (PORT d[9] (2281:2281:2281) (2318:2318:2318)) - (PORT d[10] (2441:2441:2441) (2454:2454:2454)) - (PORT d[11] (2602:2602:2602) (2694:2694:2694)) - (PORT d[12] (3964:3964:3964) (4053:4053:4053)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2866:2866:2866) (2844:2844:2844)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (PORT d[0] (2893:2893:2893) (2895:2895:2895)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2011:2011:2011) (1967:1967:1967)) - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4071:4071:4071) (4020:4020:4020)) - (PORT d[1] (4139:4139:4139) (4080:4080:4080)) - (PORT d[2] (4082:4082:4082) (3994:3994:3994)) - (PORT d[3] (4065:4065:4065) (3979:3979:3979)) - (PORT d[4] (3935:3935:3935) (3906:3906:3906)) - (PORT d[5] (4049:4049:4049) (3964:3964:3964)) - (PORT d[6] (4086:4086:4086) (3950:3950:3950)) - (PORT d[7] (3900:3900:3900) (3808:3808:3808)) - (PORT d[8] (4163:4163:4163) (4045:4045:4045)) - (PORT d[9] (4267:4267:4267) (4165:4165:4165)) - (PORT d[10] (3964:3964:3964) (3868:3868:3868)) - (PORT d[11] (4075:4075:4075) (4005:4005:4005)) - (PORT d[12] (3957:3957:3957) (3823:3823:3823)) - (PORT clk (1603:1603:1603) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1596:1596:1596)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1588:1588:1588) (1664:1664:1664)) - (PORT d[1] (1291:1291:1291) (1296:1296:1296)) - (PORT d[2] (2073:2073:2073) (2156:2156:2156)) - (PORT d[3] (1584:1584:1584) (1584:1584:1584)) - (PORT d[4] (2259:2259:2259) (2314:2314:2314)) - (PORT d[5] (2603:2603:2603) (2597:2597:2597)) - (PORT d[6] (1831:1831:1831) (1849:1849:1849)) - (PORT d[7] (1574:1574:1574) (1575:1575:1575)) - (PORT d[8] (2039:2039:2039) (2088:2088:2088)) - (PORT d[9] (1600:1600:1600) (1585:1585:1585)) - (PORT d[10] (2330:2330:2330) (2321:2321:2321)) - (PORT d[11] (3731:3731:3731) (3871:3871:3871)) - (PORT d[12] (1275:1275:1275) (1270:1270:1270)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1666:1666:1666)) - (PORT d[0] (1897:1897:1897) (1955:1955:1955)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) + (INSTANCE Selector12\~14) (DELAY (ABSOLUTE - (PORT dataa (1118:1118:1118) (1133:1133:1133)) - (PORT datab (670:670:670) (701:701:701)) - (PORT datac (1269:1269:1269) (1260:1260:1260)) - (PORT datad (1534:1534:1534) (1520:1520:1520)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1362:1362:1362) (1401:1401:1401)) + (PORT datab (2566:2566:2566) (2581:2581:2581)) + (PORT datac (1282:1282:1282) (1271:1271:1271)) + (PORT datad (1587:1587:1587) (1570:1570:1570)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48251,15 +47856,2873 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) + (INSTANCE Selector12\~6) (DELAY (ABSOLUTE - (PORT dataa (1118:1118:1118) (1115:1115:1115)) - (PORT datab (666:666:666) (695:695:695)) - (PORT datac (1743:1743:1743) (1727:1727:1727)) + (PORT dataa (1364:1364:1364) (1418:1418:1418)) + (PORT datab (226:226:226) (263:263:263)) + (PORT datac (154:154:154) (185:185:185)) (PORT datad (161:161:161) (182:182:182)) (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~11) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (411:411:411)) + (PORT datab (791:791:791) (769:769:769)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (317:317:317) (318:318:318)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (642:642:642)) + (PORT datab (994:994:994) (1078:1078:1078)) + (PORT datac (1349:1349:1349) (1370:1370:1370)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (841:841:841)) + (PORT datab (1388:1388:1388) (1394:1394:1394)) + (PORT datac (1165:1165:1165) (1189:1189:1189)) + (PORT datad (202:202:202) (244:244:244)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (796:796:796) (831:831:831)) + (PORT datac (550:550:550) (538:538:538)) + (PORT datad (764:764:764) (827:827:827)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1075:1075:1075) (1062:1062:1062)) + (PORT clrn (1383:1383:1383) (1357:1357:1357)) + (PORT ena (1834:1834:1834) (1793:1793:1793)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1566:1566:1566)) + (PORT datad (880:880:880) (941:941:941)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (770:770:770)) + (PORT datab (836:836:836) (854:854:854)) + (PORT datac (1124:1124:1124) (1152:1152:1152)) + (PORT datad (579:579:579) (575:575:575)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1687:1687:1687) (1756:1756:1756)) + (PORT datab (195:195:195) (231:231:231)) + (PORT datac (339:339:339) (380:380:380)) + (PORT datad (1728:1728:1728) (1789:1789:1789)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1039:1039:1039) (1056:1056:1056)) + (PORT datac (203:203:203) (273:273:273)) + (PORT datad (1088:1088:1088) (1112:1112:1112)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (323:323:323)) + (PORT datac (1933:1933:1933) (1988:1988:1988)) + (PORT datad (224:224:224) (284:284:284)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1101:1101:1101) (1084:1084:1084)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (2468:2468:2468) (2561:2561:2561)) + (PORT datab (1123:1123:1123) (1158:1158:1158)) + (PORT datac (1327:1327:1327) (1349:1349:1349)) + (PORT datad (817:817:817) (839:839:839)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1713:1713:1713) (1692:1692:1692)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (200:200:200) (258:258:258)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1124:1124:1124)) + (PORT datab (621:621:621) (649:649:649)) + (PORT datac (1322:1322:1322) (1310:1310:1310)) + (PORT datad (215:215:215) (272:272:272)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (620:620:620)) + (PORT datab (799:799:799) (814:814:814)) + (PORT datac (582:582:582) (580:580:580)) + (PORT datad (171:171:171) (199:199:199)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (617:617:617)) + (PORT datab (607:607:607) (620:620:620)) + (PORT datac (874:874:874) (892:892:892)) + (PORT datad (1397:1397:1397) (1399:1399:1399)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1363:1363:1363)) + (PORT datab (249:249:249) (322:322:322)) + (PORT datac (1381:1381:1381) (1400:1400:1400)) + (PORT datad (223:223:223) (283:283:283)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (979:979:979)) + (PORT datac (1101:1101:1101) (1130:1130:1130)) + (PORT datad (343:343:343) (388:388:388)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1532:1532:1532)) + (PORT datac (1432:1432:1432) (1469:1469:1469)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (911:911:911)) + (PORT datab (567:567:567) (559:559:559)) + (PORT datac (1010:1010:1010) (1015:1015:1015)) + (PORT datad (1656:1656:1656) (1657:1657:1657)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (857:857:857)) + (PORT datab (1599:1599:1599) (1593:1593:1593)) + (PORT datac (875:875:875) (904:904:904)) + (PORT datad (1951:1951:1951) (1979:1979:1979)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3197:3197:3197) (3208:3208:3208)) + (PORT d[1] (4024:4024:4024) (4056:4056:4056)) + (PORT d[2] (3061:3061:3061) (3055:3055:3055)) + (PORT d[3] (2448:2448:2448) (2568:2568:2568)) + (PORT d[4] (2904:2904:2904) (3030:3030:3030)) + (PORT d[5] (2598:2598:2598) (2700:2700:2700)) + (PORT d[6] (2856:2856:2856) (2948:2948:2948)) + (PORT d[7] (3591:3591:3591) (3626:3626:3626)) + (PORT d[8] (2506:2506:2506) (2557:2557:2557)) + (PORT d[9] (2759:2759:2759) (2852:2852:2852)) + (PORT d[10] (2377:2377:2377) (2487:2487:2487)) + (PORT d[11] (2148:2148:2148) (2195:2195:2195)) + (PORT d[12] (2179:2179:2179) (2310:2310:2310)) + (PORT clk (1653:1653:1653) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1681:1681:1681)) + (PORT d[0] (3530:3530:3530) (3522:3522:3522)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (895:895:895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1601:1601:1601) (1658:1658:1658)) + (PORT clk (1652:1652:1652) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3475:3475:3475) (3490:3490:3490)) + (PORT d[1] (3750:3750:3750) (3772:3772:3772)) + (PORT d[2] (2338:2338:2338) (2366:2366:2366)) + (PORT d[3] (2951:2951:2951) (3070:3070:3070)) + (PORT d[4] (2942:2942:2942) (3081:3081:3081)) + (PORT d[5] (2563:2563:2563) (2647:2647:2647)) + (PORT d[6] (2854:2854:2854) (2939:2939:2939)) + (PORT d[7] (3838:3838:3838) (3865:3865:3865)) + (PORT d[8] (2802:2802:2802) (2866:2866:2866)) + (PORT d[9] (3068:3068:3068) (3174:3174:3174)) + (PORT d[10] (2630:2630:2630) (2720:2720:2720)) + (PORT d[11] (2190:2190:2190) (2245:2245:2245)) + (PORT d[12] (1916:1916:1916) (2038:2038:2038)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2054:2054:2054) (2002:2002:2002)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1679:1679:1679)) + (PORT d[0] (4599:4599:4599) (4598:4598:4598)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1313:1313:1313) (1291:1291:1291)) + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3915:3915:3915) (3853:3853:3853)) + (PORT d[1] (3928:3928:3928) (3941:3941:3941)) + (PORT d[2] (3850:3850:3850) (3763:3763:3763)) + (PORT d[3] (3814:3814:3814) (3747:3747:3747)) + (PORT d[4] (3810:3810:3810) (3751:3751:3751)) + (PORT d[5] (3833:3833:3833) (3855:3855:3855)) + (PORT d[6] (4002:4002:4002) (4007:4007:4007)) + (PORT d[7] (4060:4060:4060) (4087:4087:4087)) + (PORT d[8] (3871:3871:3871) (3834:3834:3834)) + (PORT d[9] (3885:3885:3885) (3818:3818:3818)) + (PORT d[10] (3849:3849:3849) (3741:3741:3741)) + (PORT d[11] (3895:3895:3895) (3837:3837:3837)) + (PORT d[12] (3885:3885:3885) (3826:3826:3826)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1261:1261:1261) (1270:1270:1270)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2775:2775:2775) (2815:2815:2815)) + (PORT d[1] (1531:1531:1531) (1556:1556:1556)) + (PORT d[2] (2558:2558:2558) (2619:2619:2619)) + (PORT d[3] (2364:2364:2364) (2450:2450:2450)) + (PORT d[4] (3685:3685:3685) (3836:3836:3836)) + (PORT d[5] (2504:2504:2504) (2550:2550:2550)) + (PORT d[6] (2294:2294:2294) (2343:2343:2343)) + (PORT d[7] (2200:2200:2200) (2262:2262:2262)) + (PORT d[8] (2459:2459:2459) (2493:2493:2493)) + (PORT d[9] (2761:2761:2761) (2875:2875:2875)) + (PORT d[10] (2100:2100:2100) (2215:2215:2215)) + (PORT d[11] (2209:2209:2209) (2274:2274:2274)) + (PORT d[12] (1575:1575:1575) (1670:1670:1670)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1843:1843:1843) (1789:1789:1789)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (3127:3127:3127) (3132:3132:3132)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1601:1601:1601)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1420:1420:1420) (1411:1411:1411)) + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3834:3834:3834) (3814:3814:3814)) + (PORT d[1] (3950:3950:3950) (3964:3964:3964)) + (PORT d[2] (3969:3969:3969) (3938:3938:3938)) + (PORT d[3] (3959:3959:3959) (3909:3909:3909)) + (PORT d[4] (3985:3985:3985) (3967:3967:3967)) + (PORT d[5] (3989:3989:3989) (4141:4141:4141)) + (PORT d[6] (4092:4092:4092) (4062:4062:4062)) + (PORT d[7] (3964:3964:3964) (3928:3928:3928)) + (PORT d[8] (3933:3933:3933) (3831:3831:3831)) + (PORT d[9] (3864:3864:3864) (3816:3816:3816)) + (PORT d[10] (3803:3803:3803) (3705:3705:3705)) + (PORT d[11] (3879:3879:3879) (3816:3816:3816)) + (PORT d[12] (4016:4016:4016) (3882:3882:3882)) + (PORT clk (1607:1607:1607) (1605:1605:1605)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1602:1602:1602)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2129:2129:2129) (2135:2135:2135)) + (PORT d[1] (2020:2020:2020) (1959:1959:1959)) + (PORT d[2] (1846:1846:1846) (1843:1843:1843)) + (PORT d[3] (1086:1086:1086) (1092:1092:1092)) + (PORT d[4] (2357:2357:2357) (2422:2422:2422)) + (PORT d[5] (2288:2288:2288) (2268:2268:2268)) + (PORT d[6] (3453:3453:3453) (3573:3573:3573)) + (PORT d[7] (1635:1635:1635) (1592:1592:1592)) + (PORT d[8] (960:960:960) (972:972:972)) + (PORT d[9] (886:886:886) (899:899:899)) + (PORT d[10] (1660:1660:1660) (1676:1676:1676)) + (PORT d[11] (2071:2071:2071) (2077:2077:2077)) + (PORT d[12] (1415:1415:1415) (1446:1446:1446)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1668:1668:1668)) + (PORT d[0] (1540:1540:1540) (1556:1556:1556)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1119:1119:1119)) + (PORT datab (1131:1131:1131) (1153:1153:1153)) + (PORT datac (589:589:589) (638:638:638)) + (PORT datad (1579:1579:1579) (1568:1568:1568)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1370:1370:1370) (1387:1387:1387)) + (PORT datab (430:430:430) (481:481:481)) + (PORT datac (1601:1601:1601) (1644:1644:1644)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1252:1252:1252) (1254:1254:1254)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (928:928:928) (940:940:940)) + (PORT d[1] (1653:1653:1653) (1622:1622:1622)) + (PORT d[2] (925:925:925) (944:944:944)) + (PORT d[3] (2568:2568:2568) (2659:2659:2659)) + (PORT d[4] (2318:2318:2318) (2389:2389:2389)) + (PORT d[5] (892:892:892) (901:901:901)) + (PORT d[6] (1136:1136:1136) (1130:1130:1130)) + (PORT d[7] (1397:1397:1397) (1417:1417:1417)) + (PORT d[8] (1569:1569:1569) (1554:1554:1554)) + (PORT d[9] (1679:1679:1679) (1702:1702:1702)) + (PORT d[10] (2294:2294:2294) (2379:2379:2379)) + (PORT d[11] (1137:1137:1137) (1175:1175:1175)) + (PORT d[12] (1554:1554:1554) (1635:1635:1635)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2121:2121:2121) (2095:2095:2095)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (2211:2211:2211) (2158:2158:2158)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1510:1510:1510) (1544:1544:1544)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2398:2398:2398) (2407:2407:2407)) + (PORT d[1] (2302:2302:2302) (2251:2251:2251)) + (PORT d[2] (2128:2128:2128) (2128:2128:2128)) + (PORT d[3] (833:833:833) (852:852:852)) + (PORT d[4] (2398:2398:2398) (2533:2533:2533)) + (PORT d[5] (2542:2542:2542) (2518:2518:2518)) + (PORT d[6] (3718:3718:3718) (3826:3826:3826)) + (PORT d[7] (1324:1324:1324) (1294:1294:1294)) + (PORT d[8] (889:889:889) (884:884:884)) + (PORT d[9] (1390:1390:1390) (1402:1402:1402)) + (PORT d[10] (1920:1920:1920) (1922:1922:1922)) + (PORT d[11] (2387:2387:2387) (2407:2407:2407)) + (PORT d[12] (1197:1197:1197) (1230:1230:1230)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2258:2258:2258) (2171:2171:2171)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2727:2727:2727) (2631:2631:2631)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (948:948:948) (948:948:948)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (923:923:923) (935:935:935)) + (PORT d[1] (916:916:916) (914:914:914)) + (PORT d[2] (952:952:952) (970:970:970)) + (PORT d[3] (2041:2041:2041) (2113:2113:2113)) + (PORT d[4] (888:888:888) (905:905:905)) + (PORT d[5] (889:889:889) (885:885:885)) + (PORT d[6] (900:900:900) (902:902:902)) + (PORT d[7] (1108:1108:1108) (1115:1115:1115)) + (PORT d[8] (1344:1344:1344) (1327:1327:1327)) + (PORT d[9] (1618:1618:1618) (1636:1636:1636)) + (PORT d[10] (1546:1546:1546) (1629:1629:1629)) + (PORT d[11] (1162:1162:1162) (1202:1202:1202)) + (PORT d[12] (1251:1251:1251) (1311:1311:1311)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1374:1374:1374) (1341:1341:1341)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1835:1835:1835) (1784:1784:1784)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1294:1294:1294) (1282:1282:1282)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2412:2412:2412) (2432:2432:2432)) + (PORT d[1] (2294:2294:2294) (2243:2243:2243)) + (PORT d[2] (2144:2144:2144) (2159:2159:2159)) + (PORT d[3] (556:556:556) (560:560:560)) + (PORT d[4] (2408:2408:2408) (2526:2526:2526)) + (PORT d[5] (2557:2557:2557) (2545:2545:2545)) + (PORT d[6] (2963:2963:2963) (3092:3092:3092)) + (PORT d[7] (1060:1060:1060) (1021:1021:1021)) + (PORT d[8] (1377:1377:1377) (1385:1385:1385)) + (PORT d[9] (1338:1338:1338) (1345:1345:1345)) + (PORT d[10] (1903:1903:1903) (1923:1923:1923)) + (PORT d[11] (2392:2392:2392) (2415:2415:2415)) + (PORT d[12] (948:948:948) (970:970:970)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1639:1639:1639) (1628:1628:1628)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2199:2199:2199) (2136:2136:2136)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1390:1390:1390) (1419:1419:1419)) + (PORT datab (1010:1010:1010) (992:992:992)) + (PORT datac (1600:1600:1600) (1607:1607:1607)) + (PORT datad (1299:1299:1299) (1294:1294:1294)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1611:1611:1611) (1567:1567:1567)) + (PORT datab (1400:1400:1400) (1394:1394:1394)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1917:1917:1917) (1870:1870:1870)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (961:961:961)) + (PORT datab (638:638:638) (687:687:687)) + (PORT datac (861:861:861) (900:900:900)) + (PORT datad (371:371:371) (422:422:422)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (957:957:957)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (874:874:874) (909:909:909)) + (PORT datad (192:192:192) (222:222:222)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (662:662:662)) + (PORT datab (410:410:410) (453:453:453)) + (PORT datac (299:299:299) (312:312:312)) + (PORT datad (293:293:293) (298:298:298)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (597:597:597) (588:588:588)) + (PORT datad (886:886:886) (906:906:906)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (233:233:233)) + (PORT datab (215:215:215) (251:251:251)) + (PORT datac (862:862:862) (899:899:899)) + (PORT datad (188:188:188) (213:213:213)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (364:364:364)) + (PORT datab (326:326:326) (348:348:348)) + (PORT datad (566:566:566) (571:571:571)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1423:1423:1423) (1434:1434:1434)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datac (195:195:195) (261:261:261)) + (PORT datad (1862:1862:1862) (1876:1876:1876)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (805:805:805)) + (PORT datab (689:689:689) (760:760:760)) + (PORT datac (676:676:676) (725:725:725)) + (PORT datad (669:669:669) (705:705:705)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (243:243:243)) + (PORT datab (186:186:186) (219:219:219)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1364:1364:1364)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (906:906:906)) + (PORT datab (601:601:601) (594:594:594)) + (PORT datac (583:583:583) (604:604:604)) + (PORT datad (855:855:855) (895:895:895)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (936:936:936) (989:989:989)) + (PORT datad (414:414:414) (470:470:470)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (619:619:619)) + (PORT datab (3554:3554:3554) (3691:3691:3691)) + (PORT datac (193:193:193) (259:259:259)) + (PORT datad (2958:2958:2958) (3008:3008:3008)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (725:725:725)) + (PORT datac (640:640:640) (698:698:698)) + (PORT datad (642:642:642) (693:693:693)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (335:335:335)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datad (412:412:412) (470:470:470)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (453:453:453)) + (PORT datab (816:816:816) (842:842:842)) + (PORT datac (654:654:654) (722:722:722)) + (PORT datad (686:686:686) (755:755:755)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT datab (705:705:705) (751:751:751)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (673:673:673) (711:711:711)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT datab (681:681:681) (738:738:738)) + (PORT datac (227:227:227) (302:302:302)) + (PORT datad (645:645:645) (691:691:691)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (332:332:332)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (1585:1585:1585) (1604:1604:1604)) + (PORT datac (2050:2050:2050) (2149:2149:2149)) + (PORT datad (558:558:558) (580:580:580)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (954:954:954)) + (PORT datab (899:899:899) (948:948:948)) + (PORT datac (583:583:583) (587:587:587)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (454:454:454)) + (PORT datab (684:684:684) (754:754:754)) + (PORT datac (674:674:674) (722:722:722)) + (PORT datad (670:670:670) (708:708:708)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1223:1223:1223)) + (PORT datab (884:884:884) (935:935:935)) + (PORT datad (344:344:344) (348:348:348)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (958:958:958)) + (PORT datab (902:902:902) (949:949:949)) + (PORT datac (296:296:296) (301:301:301)) + (PORT datad (555:555:555) (564:564:564)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (683:683:683) (755:755:755)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (836:836:836) (851:851:851)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (960:960:960)) + (PORT datab (682:682:682) (739:739:739)) + (PORT datac (227:227:227) (299:299:299)) + (PORT datad (658:658:658) (716:716:716)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (810:810:810) (817:817:817)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (967:967:967)) + (PORT datab (1170:1170:1170) (1181:1181:1181)) + (PORT datad (1035:1035:1035) (1043:1043:1043)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (1001:1001:1001)) + (PORT datab (872:872:872) (851:851:851)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1375:1375:1375) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (624:624:624)) + (PORT datab (1950:1950:1950) (2032:2032:2032)) + (PORT datac (1860:1860:1860) (1886:1886:1886)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (597:597:597)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (534:534:534) (534:534:534)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1817:1817:1817) (1793:1793:1793)) + (PORT datab (1806:1806:1806) (1736:1736:1736)) + (PORT datac (1460:1460:1460) (1430:1430:1430)) + (PORT datad (1565:1565:1565) (1590:1590:1590)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (221:221:221)) + (PORT datab (1116:1116:1116) (1117:1117:1117)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (167:167:167) (190:190:190)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1097:1097:1097)) + (PORT datab (1057:1057:1057) (1065:1065:1065)) + (PORT datac (1278:1278:1278) (1251:1251:1251)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (774:774:774)) + (PORT datab (1394:1394:1394) (1395:1395:1395)) + (PORT datac (840:840:840) (845:845:845)) + (PORT datad (206:206:206) (249:249:249)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (288:288:288)) + (PORT datac (590:590:590) (625:625:625)) + (PORT datad (220:220:220) (258:258:258)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (827:827:827)) + (PORT datab (982:982:982) (942:942:942)) + (PORT datac (1354:1354:1354) (1344:1344:1344)) + (PORT datad (773:773:773) (839:839:839)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (214:214:214) (265:265:265)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1357:1357:1357)) + (PORT ena (1834:1834:1834) (1793:1793:1793)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1635:1635:1635) (1677:1677:1677)) + (PORT datab (211:211:211) (251:251:251)) + (PORT datac (784:784:784) (778:778:778)) + (PORT datad (879:879:879) (934:934:934)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1044:1044:1044)) + (PORT datac (616:616:616) (654:654:654)) + (PORT datad (636:636:636) (670:670:670)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT datac (1040:1040:1040) (1026:1026:1026)) + (PORT datad (540:540:540) (542:542:542)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1186:1186:1186)) + (PORT datab (866:866:866) (888:888:888)) + (PORT datac (1918:1918:1918) (2025:2025:2025)) + (PORT datad (1361:1361:1361) (1393:1393:1393)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1746:1746:1746) (1725:1725:1725)) + (PORT datab (892:892:892) (908:908:908)) + (PORT datac (864:864:864) (864:864:864)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2199:2199:2199) (2227:2227:2227)) + (PORT datab (600:600:600) (601:601:601)) + (PORT datac (1106:1106:1106) (1173:1173:1173)) + (PORT datad (1042:1042:1042) (1030:1030:1030)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (609:609:609)) + (PORT datab (638:638:638) (654:654:654)) + (PORT datac (809:809:809) (813:813:813)) + (PORT datad (568:568:568) (569:569:569)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (394:394:394)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1036:1036:1036) (1033:1033:1033)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1795:1795:1795) (1858:1858:1858)) + (PORT datab (603:603:603) (629:629:629)) + (PORT datac (1038:1038:1038) (1031:1031:1031)) + (PORT datad (1961:1961:1961) (1925:1925:1925)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1128:1128:1128)) + (PORT datab (766:766:766) (746:746:746)) + (PORT datac (755:755:755) (737:737:737)) + (PORT datad (1328:1328:1328) (1344:1344:1344)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1215:1215:1215)) + (PORT datab (1444:1444:1444) (1474:1474:1474)) + (PORT datac (1051:1051:1051) (1018:1018:1018)) + (PORT datad (1336:1336:1336) (1317:1317:1317)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1064:1064:1064)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1057:1057:1057) (1037:1037:1037)) + (PORT datad (597:597:597) (612:612:612)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (845:845:845)) + (PORT datab (817:817:817) (802:802:802)) + (PORT datac (1232:1232:1232) (1205:1205:1205)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (980:980:980)) + (PORT datab (247:247:247) (320:320:320)) + (PORT datac (1081:1081:1081) (1120:1120:1120)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (1263:1263:1263) (1373:1373:1373)) + (PORT datac (216:216:216) (283:283:283)) + (PORT datad (1629:1629:1629) (1647:1647:1647)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1359:1359:1359)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (952:952:952)) + (PORT datad (815:815:815) (831:831:831)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|nmi_armed) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1663:1663:1663)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (695:695:695) (696:696:696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1039:1039:1039) (1050:1050:1050)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|im1\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (185:185:185) (208:208:208)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1357:1357:1357)) + (PORT ena (1599:1599:1599) (1565:1565:1565)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (564:564:564)) + (PORT datab (417:417:417) (479:479:479)) + (PORT datac (1116:1116:1116) (1130:1130:1130)) + (PORT datad (618:618:618) (665:665:665)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1107:1107:1107)) + (PORT datab (648:648:648) (680:680:680)) + (PORT datac (1119:1119:1119) (1133:1133:1133)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (862:862:862)) + (PORT datab (246:246:246) (299:299:299)) + (PORT datac (1312:1312:1312) (1290:1290:1290)) + (PORT datad (171:171:171) (198:198:198)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48270,8 +50733,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1209:1209:1209) (1215:1215:1215)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (919:919:919) (920:920:920)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -48283,20 +50746,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2126:2126:2126) (2221:2221:2221)) - (PORT d[1] (2088:2088:2088) (2097:2097:2097)) - (PORT d[2] (1711:1711:1711) (1725:1725:1725)) - (PORT d[3] (2328:2328:2328) (2339:2339:2339)) - (PORT d[4] (1906:1906:1906) (1917:1917:1917)) - (PORT d[5] (1445:1445:1445) (1474:1474:1474)) - (PORT d[6] (1622:1622:1622) (1612:1612:1612)) - (PORT d[7] (2191:2191:2191) (2238:2238:2238)) - (PORT d[8] (2297:2297:2297) (2401:2401:2401)) - (PORT d[9] (1150:1150:1150) (1173:1173:1173)) - (PORT d[10] (1528:1528:1528) (1520:1520:1520)) - (PORT d[11] (1089:1089:1089) (1091:1091:1091)) - (PORT d[12] (944:944:944) (985:985:985)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (3263:3263:3263) (3325:3325:3325)) + (PORT d[1] (3163:3163:3163) (3156:3156:3156)) + (PORT d[2] (3132:3132:3132) (3162:3162:3162)) + (PORT d[3] (3481:3481:3481) (3614:3614:3614)) + (PORT d[4] (2447:2447:2447) (2589:2589:2589)) + (PORT d[5] (2213:2213:2213) (2238:2238:2238)) + (PORT d[6] (3139:3139:3139) (3229:3229:3229)) + (PORT d[7] (4389:4389:4389) (4436:4436:4436)) + (PORT d[8] (3060:3060:3060) (3137:3137:3137)) + (PORT d[9] (3632:3632:3632) (3759:3759:3759)) + (PORT d[10] (3175:3175:3175) (3304:3304:3304)) + (PORT d[11] (2765:2765:2765) (2846:2846:2846)) + (PORT d[12] (2218:2218:2218) (2358:2358:2358)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) ) ) (TIMINGCHECK @@ -48308,8 +50771,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1412:1412:1412) (1389:1389:1389)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (1572:1572:1572) (1498:1498:1498)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) ) ) (TIMINGCHECK @@ -48321,8 +50784,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (1847:1847:1847) (1802:1802:1802)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT d[0] (2282:2282:2282) (2228:2228:2228)) ) ) ) @@ -48331,7 +50794,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -48341,7 +50804,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -48351,7 +50814,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -48361,7 +50824,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -48371,7 +50834,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) + (PORT clk (1608:1608:1608) (1635:1635:1635)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -48385,7 +50848,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (879:879:879) (882:882:882)) ) ) ) @@ -48394,7 +50857,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) + (PORT clk (880:880:880) (883:883:883)) ) ) ) @@ -48403,7 +50866,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) + (PORT clk (880:880:880) (883:883:883)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -48413,7 +50876,160 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) + (PORT clk (880:880:880) (883:883:883)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (914:914:914) (919:919:919)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2988:2988:2988) (3040:3040:3040)) + (PORT d[1] (2880:2880:2880) (2862:2862:2862)) + (PORT d[2] (3404:3404:3404) (3445:3445:3445)) + (PORT d[3] (1594:1594:1594) (1585:1585:1585)) + (PORT d[4] (2704:2704:2704) (2858:2858:2858)) + (PORT d[5] (2601:2601:2601) (2623:2623:2623)) + (PORT d[6] (3406:3406:3406) (3532:3532:3532)) + (PORT d[7] (1610:1610:1610) (1601:1601:1601)) + (PORT d[8] (3335:3335:3335) (3421:3421:3421)) + (PORT d[9] (3899:3899:3899) (4034:4034:4034)) + (PORT d[10] (3506:3506:3506) (3652:3652:3652)) + (PORT d[11] (3049:3049:3049) (3144:3144:3144)) + (PORT d[12] (2506:2506:2506) (2654:2654:2654)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1658:1658:1658) (1653:1653:1653)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2184:2184:2184) (2133:2133:2133)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -48423,7 +51039,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1090:1090:1090) (1057:1057:1057)) + (PORT d[0] (892:892:892) (872:872:872)) (PORT clk (1646:1646:1646) (1672:1672:1672)) ) ) @@ -48436,19 +51052,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2677:2677:2677) (2786:2786:2786)) - (PORT d[1] (3046:3046:3046) (3122:3122:3122)) - (PORT d[2] (1816:1816:1816) (1814:1814:1814)) - (PORT d[3] (3668:3668:3668) (3717:3717:3717)) - (PORT d[4] (2679:2679:2679) (2768:2768:2768)) - (PORT d[5] (4106:4106:4106) (4171:4171:4171)) - (PORT d[6] (2058:2058:2058) (2054:2054:2054)) - (PORT d[7] (1597:1597:1597) (1606:1606:1606)) - (PORT d[8] (2907:2907:2907) (3000:3000:3000)) - (PORT d[9] (1706:1706:1706) (1738:1738:1738)) - (PORT d[10] (1900:1900:1900) (1898:1898:1898)) - (PORT d[11] (2895:2895:2895) (2998:2998:2998)) - (PORT d[12] (3973:3973:3973) (4063:4063:4063)) + (PORT d[0] (2989:2989:2989) (3041:3041:3041)) + (PORT d[1] (3148:3148:3148) (3128:3128:3128)) + (PORT d[2] (3426:3426:3426) (3461:3461:3461)) + (PORT d[3] (3495:3495:3495) (3639:3639:3639)) + (PORT d[4] (2441:2441:2441) (2581:2581:2581)) + (PORT d[5] (2518:2518:2518) (2535:2535:2535)) + (PORT d[6] (3145:3145:3145) (3256:3256:3256)) + (PORT d[7] (4427:4427:4427) (4488:4488:4488)) + (PORT d[8] (3361:3361:3361) (3447:3447:3447)) + (PORT d[9] (3919:3919:3919) (4055:4055:4055)) + (PORT d[10] (3236:3236:3236) (3381:3381:3381)) + (PORT d[11] (3021:3021:3021) (3104:3104:3104)) + (PORT d[12] (2174:2174:2174) (2305:2305:2305)) (PORT clk (1643:1643:1643) (1670:1670:1670)) ) ) @@ -48461,7 +51077,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1499:1499:1499) (1433:1433:1433)) + (PORT d[0] (2372:2372:2372) (2319:2319:2319)) (PORT clk (1643:1643:1643) (1670:1670:1670)) ) ) @@ -48475,7 +51091,7 @@ (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (2295:2295:2295) (2246:2246:2246)) + (PORT d[0] (2031:2031:2031) (1981:1981:1981)) ) ) ) @@ -48571,170 +51187,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1303:1303:1303) (1293:1293:1293)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2076:2076:2076) (2151:2151:2151)) - (PORT d[1] (1045:1045:1045) (1047:1047:1047)) - (PORT d[2] (2474:2474:2474) (2506:2506:2506)) - (PORT d[3] (4240:4240:4240) (4316:4316:4316)) - (PORT d[4] (895:895:895) (905:905:905)) - (PORT d[5] (1531:1531:1531) (1511:1511:1511)) - (PORT d[6] (1336:1336:1336) (1341:1341:1341)) - (PORT d[7] (1313:1313:1313) (1299:1299:1299)) - (PORT d[8] (2333:2333:2333) (2396:2396:2396)) - (PORT d[9] (1059:1059:1059) (1054:1054:1054)) - (PORT d[10] (1893:1893:1893) (1883:1883:1883)) - (PORT d[11] (3463:3463:3463) (3596:3596:3596)) - (PORT d[12] (2280:2280:2280) (2280:2280:2280)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2590:2590:2590) (2563:2563:2563)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (1726:1726:1726) (1666:1666:1666)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) (DELAY (ABSOLUTE - (PORT dataa (807:807:807) (788:788:788)) - (PORT datab (1158:1158:1158) (1192:1192:1192)) - (PORT datac (1341:1341:1341) (1368:1368:1368)) - (PORT datad (1314:1314:1314) (1327:1327:1327)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (841:841:841) (823:823:823)) + (PORT datab (1037:1037:1037) (1079:1079:1079)) + (PORT datac (749:749:749) (718:718:718)) + (PORT datad (1239:1239:1239) (1271:1271:1271)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48745,8 +51208,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1351:1351:1351) (1333:1333:1333)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (917:917:917) (929:929:929)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) ) ) (TIMINGCHECK @@ -48758,20 +51221,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1561:1561:1561) (1629:1629:1629)) - (PORT d[1] (2056:2056:2056) (2043:2043:2043)) - (PORT d[2] (2092:2092:2092) (2176:2176:2176)) - (PORT d[3] (1603:1603:1603) (1594:1594:1594)) - (PORT d[4] (2248:2248:2248) (2292:2292:2292)) - (PORT d[5] (2623:2623:2623) (2618:2618:2618)) - (PORT d[6] (1878:1878:1878) (1895:1895:1895)) - (PORT d[7] (1603:1603:1603) (1608:1608:1608)) - (PORT d[8] (2013:2013:2013) (2059:2059:2059)) - (PORT d[9] (1837:1837:1837) (1816:1816:1816)) - (PORT d[10] (2045:2045:2045) (2041:2041:2041)) - (PORT d[11] (3995:3995:3995) (4131:4131:4131)) - (PORT d[12] (2040:2040:2040) (2037:2037:2037)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (2971:2971:2971) (3005:3005:3005)) + (PORT d[1] (2894:2894:2894) (2870:2870:2870)) + (PORT d[2] (3661:3661:3661) (3720:3720:3720)) + (PORT d[3] (1846:1846:1846) (1838:1838:1838)) + (PORT d[4] (2719:2719:2719) (2876:2876:2876)) + (PORT d[5] (3239:3239:3239) (3244:3244:3244)) + (PORT d[6] (3676:3676:3676) (3812:3812:3812)) + (PORT d[7] (1136:1136:1136) (1145:1145:1145)) + (PORT d[8] (3641:3641:3641) (3740:3740:3740)) + (PORT d[9] (3872:3872:3872) (4011:4011:4011)) + (PORT d[10] (3567:3567:3567) (3726:3726:3726)) + (PORT d[11] (3307:3307:3307) (3405:3405:3405)) + (PORT d[12] (2490:2490:2490) (2639:2639:2639)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -48783,8 +51246,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1758:1758:1758) (1762:1762:1762)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (2773:2773:2773) (2703:2703:2703)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -48796,8 +51259,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (1720:1720:1720) (1667:1667:1667)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2707:2707:2707) (2616:2616:2616)) ) ) ) @@ -48806,7 +51269,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -48816,7 +51279,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -48826,7 +51289,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -48836,7 +51299,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1647:1647:1647) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -48846,7 +51309,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) + (PORT clk (1610:1610:1610) (1638:1638:1638)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -48860,7 +51323,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) + (PORT clk (881:881:881) (885:885:885)) ) ) ) @@ -48869,7 +51332,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) + (PORT clk (882:882:882) (886:886:886)) ) ) ) @@ -48878,7 +51341,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) + (PORT clk (882:882:882) (886:886:886)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -48888,22 +51351,649 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) + (PORT clk (882:882:882) (886:886:886)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1115:1115:1115) (1139:1139:1139)) - (PORT datab (1575:1575:1575) (1612:1612:1612)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (1573:1573:1573) (1589:1589:1589)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (1672:1672:1672) (1706:1706:1706)) + (PORT datab (1034:1034:1034) (1012:1012:1012)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1250:1250:1250) (1203:1203:1203)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1205:1205:1205) (1231:1231:1231)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3533:3533:3533) (3607:3607:3607)) + (PORT d[1] (3716:3716:3716) (3723:3723:3723)) + (PORT d[2] (2866:2866:2866) (2885:2885:2885)) + (PORT d[3] (2943:2943:2943) (3063:3063:3063)) + (PORT d[4] (3208:3208:3208) (3352:3352:3352)) + (PORT d[5] (2766:2766:2766) (2776:2776:2776)) + (PORT d[6] (2595:2595:2595) (2674:2674:2674)) + (PORT d[7] (3849:3849:3849) (3886:3886:3886)) + (PORT d[8] (2819:2819:2819) (2882:2882:2882)) + (PORT d[9] (3308:3308:3308) (3412:3412:3412)) + (PORT d[10] (2631:2631:2631) (2754:2754:2754)) + (PORT d[11] (2476:2476:2476) (2532:2532:2532)) + (PORT d[12] (2305:2305:2305) (2385:2385:2385)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1775:1775:1775) (1729:1729:1729)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (4813:4813:4813) (4803:4803:4803)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1603:1603:1603)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1071:1071:1071) (1046:1046:1046)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3920:3920:3920) (3856:3856:3856)) + (PORT d[1] (3944:3944:3944) (3955:3955:3955)) + (PORT d[2] (3972:3972:3972) (3851:3851:3851)) + (PORT d[3] (3954:3954:3954) (3848:3848:3848)) + (PORT d[4] (3816:3816:3816) (3725:3725:3725)) + (PORT d[5] (3922:3922:3922) (4004:4004:4004)) + (PORT d[6] (4000:4000:4000) (4002:4002:4002)) + (PORT d[7] (3944:3944:3944) (3986:3986:3986)) + (PORT d[8] (3866:3866:3866) (3800:3800:3800)) + (PORT d[9] (3875:3875:3875) (3853:3853:3853)) + (PORT d[10] (3893:3893:3893) (3828:3828:3828)) + (PORT d[11] (3892:3892:3892) (3831:3831:3831)) + (PORT d[12] (3896:3896:3896) (3846:3846:3846)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2134:2134:2134) (2143:2143:2143)) + (PORT d[1] (2263:2263:2263) (2194:2194:2194)) + (PORT d[2] (1833:1833:1833) (1830:1830:1830)) + (PORT d[3] (1100:1100:1100) (1103:1103:1103)) + (PORT d[4] (2367:2367:2367) (2428:2428:2428)) + (PORT d[5] (2301:2301:2301) (2281:2281:2281)) + (PORT d[6] (3469:3469:3469) (3590:3590:3590)) + (PORT d[7] (1336:1336:1336) (1308:1308:1308)) + (PORT d[8] (919:919:919) (926:926:926)) + (PORT d[9] (924:924:924) (940:940:940)) + (PORT d[10] (1665:1665:1665) (1684:1684:1684)) + (PORT d[11] (2374:2374:2374) (2382:2382:2382)) + (PORT d[12] (1411:1411:1411) (1423:1423:1423)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1666:1666:1666)) + (PORT d[0] (1548:1548:1548) (1527:1527:1527)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1204:1204:1204) (1220:1220:1220)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3520:3520:3520) (3579:3579:3579)) + (PORT d[1] (3462:3462:3462) (3466:3466:3466)) + (PORT d[2] (3141:3141:3141) (3159:3159:3159)) + (PORT d[3] (3221:3221:3221) (3351:3351:3351)) + (PORT d[4] (2428:2428:2428) (2567:2567:2567)) + (PORT d[5] (2506:2506:2506) (2531:2531:2531)) + (PORT d[6] (2860:2860:2860) (2964:2964:2964)) + (PORT d[7] (4128:4128:4128) (4178:4178:4178)) + (PORT d[8] (3086:3086:3086) (3160:3160:3160)) + (PORT d[9] (3321:3321:3321) (3437:3437:3437)) + (PORT d[10] (2932:2932:2932) (3063:3063:3063)) + (PORT d[11] (2725:2725:2725) (2790:2790:2790)) + (PORT d[12] (2242:2242:2242) (2301:2301:2301)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1728:1728:1728) (1633:1633:1633)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (4833:4833:4833) (4821:4821:4821)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1288:1288:1288) (1262:1262:1262)) + (PORT clk (1606:1606:1606) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3921:3921:3921) (3861:3861:3861)) + (PORT d[1] (3911:3911:3911) (3839:3839:3839)) + (PORT d[2] (3985:3985:3985) (3825:3825:3825)) + (PORT d[3] (3843:3843:3843) (3770:3770:3770)) + (PORT d[4] (3822:3822:3822) (3754:3754:3754)) + (PORT d[5] (4085:4085:4085) (4276:4276:4276)) + (PORT d[6] (3965:3965:3965) (4024:4024:4024)) + (PORT d[7] (3909:3909:3909) (3933:3933:3933)) + (PORT d[8] (3867:3867:3867) (3822:3822:3822)) + (PORT d[9] (3907:3907:3907) (3846:3846:3846)) + (PORT d[10] (3852:3852:3852) (3781:3781:3781)) + (PORT d[11] (3903:3903:3903) (3851:3851:3851)) + (PORT d[12] (3934:3934:3934) (3897:3897:3897)) + (PORT clk (1603:1603:1603) (1601:1601:1601)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1604:1604:1604)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2637:2637:2637) (2675:2675:2675)) + (PORT d[1] (4008:4008:4008) (4036:4036:4036)) + (PORT d[2] (2598:2598:2598) (2622:2622:2622)) + (PORT d[3] (2320:2320:2320) (2420:2420:2420)) + (PORT d[4] (2857:2857:2857) (2960:2960:2960)) + (PORT d[5] (2836:2836:2836) (2817:2817:2817)) + (PORT d[6] (2849:2849:2849) (2940:2940:2940)) + (PORT d[7] (3133:3133:3133) (3168:3168:3168)) + (PORT d[8] (2289:2289:2289) (2331:2331:2331)) + (PORT d[9] (2772:2772:2772) (2862:2862:2862)) + (PORT d[10] (2151:2151:2151) (2273:2273:2273)) + (PORT d[11] (2119:2119:2119) (2156:2156:2156)) + (PORT d[12] (2384:2384:2384) (2494:2494:2494)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT d[0] (3220:3220:3220) (3252:3252:3252)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1146:1146:1146) (1157:1157:1157)) + (PORT datab (1145:1145:1145) (1197:1197:1197)) + (PORT datac (979:979:979) (945:945:945)) + (PORT datad (1499:1499:1499) (1465:1465:1465)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48911,14 +52001,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~112) + (INSTANCE Selector4\~1) (DELAY (ABSOLUTE - (PORT dataa (1609:1609:1609) (1608:1608:1608)) - (PORT datab (620:620:620) (613:613:613)) - (PORT datac (572:572:572) (570:570:570)) - (PORT datad (303:303:303) (304:304:304)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (1346:1346:1346) (1385:1385:1385)) + (PORT datab (1084:1084:1084) (1072:1072:1072)) + (PORT datac (1286:1286:1286) (1292:1292:1292)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2837:2837:2837) (2847:2847:2847)) + (PORT datab (1096:1096:1096) (1075:1075:1075)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (927:927:927)) + (PORT datab (1273:1273:1273) (1235:1235:1235)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1593:1593:1593) (1618:1618:1618)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -48927,16 +52049,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~113) + (INSTANCE D\[5\]\~40) (DELAY (ABSOLUTE - (PORT dataa (2306:2306:2306) (2269:2269:2269)) - (PORT datab (643:643:643) (643:643:643)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (1091:1091:1091) (1115:1115:1115)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (1008:1008:1008) (993:993:993)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -48946,13 +52064,13 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) (DELAY (ABSOLUTE - (PORT dataa (609:609:609) (613:613:613)) - (PORT datab (1071:1071:1071) (1059:1059:1059)) - (PORT datac (198:198:198) (235:235:235)) - (PORT datad (1433:1433:1433) (1401:1401:1401)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1308:1308:1308) (1309:1309:1309)) + (PORT datab (786:786:786) (848:848:848)) + (PORT datac (1358:1358:1358) (1361:1361:1361)) + (PORT datad (203:203:203) (245:245:245)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -48962,9 +52080,9 @@ (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT clk (1341:1341:1341) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -48975,30 +52093,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT datab (400:400:400) (437:437:437)) - (PORT datac (194:194:194) (238:238:238)) - (PORT datad (202:202:202) (239:239:239)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (237:237:237) (292:292:292)) + (PORT datac (940:940:940) (984:984:984)) + (PORT datad (221:221:221) (262:262:262)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (813:813:813) (785:785:785)) - (PORT datab (550:550:550) (555:555:555)) - (PORT datac (496:496:496) (480:480:480)) - (PORT datad (1029:1029:1029) (998:998:998)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (817:817:817) (880:880:880)) + (PORT datab (721:721:721) (787:787:787)) + (PORT datac (1356:1356:1356) (1346:1346:1346)) + (PORT datad (1073:1073:1073) (1067:1067:1067)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -49008,10 +52126,84 @@ (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1574:1574:1574) (1617:1617:1617)) + (PORT clrn (1385:1385:1385) (1359:1359:1359)) + (PORT ena (764:764:764) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1941:1941:1941) (1968:1968:1968)) + (PORT datac (1119:1119:1119) (1146:1146:1146)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (623:623:623)) + (PORT datab (665:665:665) (697:697:697)) + (PORT datac (835:835:835) (872:872:872)) + (PORT datad (1720:1720:1720) (1796:1796:1796)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (616:616:616)) + (PORT datab (625:625:625) (649:649:649)) + (PORT datac (1335:1335:1335) (1337:1337:1337)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (976:976:976)) + (PORT datab (241:241:241) (310:310:310)) + (PORT datac (1084:1084:1084) (1107:1107:1107)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (PORT ena (1804:1804:1804) (1767:1767:1767)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -49023,339 +52215,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (INSTANCE z80_\|execute_\|setM1\~16) (DELAY (ABSOLUTE - (PORT dataa (1946:1946:1946) (2019:2019:2019)) - (PORT datab (1854:1854:1854) (1879:1879:1879)) - (PORT datac (1265:1265:1265) (1337:1337:1337)) - (PORT datad (815:815:815) (826:826:826)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1247:1247:1247) (1233:1233:1233)) + (PORT datab (567:567:567) (584:584:584)) + (PORT datac (1058:1058:1058) (1056:1056:1056)) + (PORT datad (837:837:837) (869:869:869)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (921:921:921)) + (PORT datab (625:625:625) (636:636:636)) + (PORT datac (1396:1396:1396) (1424:1424:1424)) + (PORT datad (929:929:929) (980:980:980)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (612:612:612)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (296:296:296) (297:297:297)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (804:804:804)) + (PORT datab (652:652:652) (686:686:686)) + (PORT datac (1672:1672:1672) (1708:1708:1708)) + (PORT datad (601:601:601) (621:621:621)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1246:1246:1246)) + (PORT datab (819:819:819) (813:813:813)) + (PORT datac (518:518:518) (503:503:503)) + (PORT datad (319:319:319) (329:329:329)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (1123:1123:1123) (1123:1123:1123)) - (PORT datab (614:614:614) (627:627:627)) - (PORT datac (1304:1304:1304) (1322:1322:1322)) - (PORT datad (306:306:306) (317:317:317)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT datac (948:948:948) (983:983:983)) - (PORT datad (551:551:551) (546:546:546)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (1722:1722:1722) (1752:1752:1752)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (1001:1001:1001) (998:998:998)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1105:1105:1105)) - (PORT datab (208:208:208) (245:245:245)) - (PORT datac (558:558:558) (584:584:584)) - (PORT datad (549:549:549) (561:561:561)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1206:1206:1206)) - (PORT datab (701:701:701) (734:734:734)) - (PORT datac (1796:1796:1796) (1749:1749:1749)) - (PORT datad (770:770:770) (751:751:751)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (610:610:610)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1352:1352:1352) (1377:1377:1377)) - (PORT datad (585:585:585) (617:617:617)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1545:1545:1545)) - (PORT datab (858:858:858) (838:838:838)) - (PORT datac (1305:1305:1305) (1294:1294:1294)) - (PORT datad (803:803:803) (785:785:785)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (629:629:629)) - (PORT datab (1224:1224:1224) (1230:1230:1230)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1575:1575:1575) (1548:1548:1548)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (241:241:241)) - (PORT datab (622:622:622) (627:627:627)) + (PORT dataa (589:589:589) (593:593:593)) + (PORT datab (857:857:857) (862:862:862)) (PORT datac (155:155:155) (185:185:185)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (791:791:791)) - (PORT datab (2167:2167:2167) (2207:2207:2207)) - (PORT datac (1357:1357:1357) (1416:1416:1416)) - (PORT datad (957:957:957) (987:987:987)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (835:835:835)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (552:552:552) (536:536:536)) - (PORT datac (549:549:549) (572:572:572)) - (PORT datad (1294:1294:1294) (1274:1274:1274)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (615:615:615) (658:658:658)) - (PORT datad (816:816:816) (835:835:835)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (683:683:683)) - (PORT datac (620:620:620) (655:655:655)) - (PORT datad (818:818:818) (832:832:832)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) - (PORT datac (622:622:622) (656:656:656)) - (PORT datad (819:819:819) (832:832:832)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (317:317:317)) - (PORT datac (617:617:617) (658:658:658)) - (PORT datad (826:826:826) (837:837:837)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT datac (640:640:640) (704:704:704)) - (PORT datad (2140:2140:2140) (2196:2196:2196)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49363,128 +52309,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (INSTANCE z80_\|execute_\|setM1\~47) (DELAY (ABSOLUTE - (PORT dataa (1109:1109:1109) (1149:1149:1149)) - (PORT datab (1388:1388:1388) (1423:1423:1423)) - (PORT datac (1482:1482:1482) (1468:1468:1468)) - (PORT datad (880:880:880) (867:867:867)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1120:1120:1120) (1120:1120:1120)) + (PORT datab (1146:1146:1146) (1147:1147:1147)) + (PORT datac (824:824:824) (826:826:826)) + (PORT datad (792:792:792) (773:773:773)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (540:540:540)) + (PORT datab (572:572:572) (584:584:584)) + (PORT datac (840:840:840) (848:848:848)) + (PORT datad (969:969:969) (939:939:939)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~54) (DELAY (ABSOLUTE - (PORT dataa (1046:1046:1046) (1035:1035:1035)) - (PORT datab (607:607:607) (615:615:615)) - (PORT datac (1073:1073:1073) (1109:1109:1109)) - (PORT datad (829:829:829) (871:871:871)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (627:627:627)) - (PORT datab (1219:1219:1219) (1224:1224:1224)) - (PORT datac (575:575:575) (567:567:567)) - (PORT datad (799:799:799) (783:783:783)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1117:1117:1117) (1120:1120:1120)) - (PORT datab (902:902:902) (908:908:908)) - (PORT datac (225:225:225) (280:280:280)) - (PORT datad (1058:1058:1058) (1058:1058:1058)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1106:1106:1106)) - (PORT datab (564:564:564) (571:571:571)) - (PORT datac (804:804:804) (787:787:787)) - (PORT datad (743:743:743) (783:783:783)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (885:885:885)) - (PORT datab (1358:1358:1358) (1351:1351:1351)) - (PORT datac (2642:2642:2642) (2660:2660:2660)) - (PORT datad (209:209:209) (272:272:272)) + (PORT dataa (338:338:338) (361:361:361)) + (PORT datab (907:907:907) (929:929:929)) + (PORT datac (864:864:864) (865:865:865)) + (PORT datad (160:160:160) (182:182:182)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1398:1398:1398)) - (PORT datab (1002:1002:1002) (981:981:981)) - (PORT datac (1145:1145:1145) (1184:1184:1184)) - (PORT datad (1897:1897:1897) (1971:1971:1971)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1015:1015:1015)) - (PORT datab (358:358:358) (369:369:369)) - (PORT datac (757:757:757) (813:813:813)) - (PORT datad (1534:1534:1534) (1544:1544:1544)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -49494,10 +52360,58 @@ (INSTANCE z80_\|execute_\|setM1\~24) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datab (855:855:855) (887:887:887)) - (PORT datac (794:794:794) (792:792:792)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (919:919:919) (961:961:961)) + (PORT datab (236:236:236) (304:304:304)) + (PORT datac (1802:1802:1802) (1850:1850:1850)) + (PORT datad (1099:1099:1099) (1129:1129:1129)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1230:1230:1230)) + (PORT datab (1162:1162:1162) (1194:1194:1194)) + (PORT datac (1321:1321:1321) (1334:1334:1334)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1032:1032:1032)) + (PORT datab (847:847:847) (868:868:868)) + (PORT datac (588:588:588) (596:596:596)) + (PORT datad (805:805:805) (820:820:820)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (899:899:899) (899:899:899)) + (PORT datac (1019:1019:1019) (995:995:995)) + (PORT datad (1235:1235:1235) (1217:1217:1217)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -49510,76 +52424,28 @@ (INSTANCE z80_\|execute_\|setM1\~28) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (506:506:506)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (563:563:563) (573:573:573)) - (PORT datad (815:815:815) (809:809:809)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1056:1056:1056)) - (PORT datab (1807:1807:1807) (1785:1785:1785)) - (PORT datac (861:861:861) (897:897:897)) - (PORT datad (1109:1109:1109) (1129:1129:1129)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (1242:1242:1242) (1301:1301:1301)) + (PORT datab (1285:1285:1285) (1372:1372:1372)) + (PORT datac (759:759:759) (755:755:755)) + (PORT datad (1140:1140:1140) (1162:1162:1162)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1592:1592:1592) (1592:1592:1592)) - (PORT datab (1898:1898:1898) (1829:1829:1829)) - (PORT datac (1502:1502:1502) (1474:1474:1474)) - (PORT datad (1478:1478:1478) (1429:1429:1429)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~29) (DELAY (ABSOLUTE - (PORT dataa (774:774:774) (799:799:799)) - (PORT datab (766:766:766) (814:814:814)) - (PORT datac (807:807:807) (845:845:845)) - (PORT datad (1181:1181:1181) (1216:1216:1216)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1052:1052:1052)) - (PORT datab (813:813:813) (822:822:822)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1192:1192:1192) (1207:1207:1207)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1295:1295:1295) (1284:1284:1284)) + (PORT datab (1060:1060:1060) (1038:1038:1038)) + (PORT datac (1260:1260:1260) (1310:1310:1310)) + (PORT datad (1017:1017:1017) (1003:1003:1003)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49587,47 +52453,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) + (INSTANCE z80_\|execute_\|setM1\~27) (DELAY (ABSOLUTE - (PORT dataa (821:821:821) (852:852:852)) - (PORT datab (1419:1419:1419) (1456:1456:1456)) - (PORT datac (1053:1053:1053) (1042:1042:1042)) - (PORT datad (1447:1447:1447) (1463:1463:1463)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1791:1791:1791) (1852:1852:1852)) + (PORT datab (1332:1332:1332) (1316:1316:1316)) + (PORT datac (572:572:572) (599:599:599)) + (PORT datad (872:872:872) (885:885:885)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1663:1663:1663)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1020:1020:1020) (997:997:997)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~34) (DELAY (ABSOLUTE - (PORT dataa (773:773:773) (793:793:793)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (778:778:778) (755:755:755)) - (PORT datad (1535:1535:1535) (1512:1512:1512)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (897:897:897)) - (PORT datab (238:238:238) (306:306:306)) - (PORT datac (1541:1541:1541) (1531:1531:1531)) - (PORT datad (860:860:860) (848:848:848)) + (PORT dataa (884:884:884) (909:909:909)) + (PORT datab (1379:1379:1379) (1405:1405:1405)) + (PORT datac (794:794:794) (795:795:795)) + (PORT datad (559:559:559) (556:556:556)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49635,16 +52501,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) + (INSTANCE z80_\|execute_\|setM1\~13) (DELAY (ABSOLUTE - (PORT dataa (1106:1106:1106) (1107:1107:1107)) - (PORT datab (1190:1190:1190) (1223:1223:1223)) - (PORT datac (831:831:831) (807:807:807)) - (PORT datad (754:754:754) (778:778:778)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1827:1827:1827) (1878:1878:1878)) + (PORT datab (1292:1292:1292) (1341:1341:1341)) + (PORT datac (886:886:886) (931:931:931)) + (PORT datad (1100:1100:1100) (1129:1129:1129)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -49654,12 +52520,60 @@ (INSTANCE z80_\|execute_\|setM1\~35) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (834:834:834) (841:841:841)) + (PORT datab (1128:1128:1128) (1123:1123:1123)) + (PORT datac (328:328:328) (341:341:341)) + (PORT datad (568:568:568) (583:583:583)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (417:417:417)) + (PORT datab (875:875:875) (886:886:886)) + (PORT datac (867:867:867) (889:889:889)) + (PORT datad (1141:1141:1141) (1165:1165:1165)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1214:1214:1214)) + (PORT datab (205:205:205) (240:240:240)) + (PORT datac (532:532:532) (531:531:531)) + (PORT datad (1120:1120:1120) (1123:1123:1123)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (265:265:265)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49667,15 +52581,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) + (INSTANCE z80_\|execute_\|setM1\~56) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (595:595:595)) - (PORT datab (1138:1138:1138) (1159:1159:1159)) - (PORT datac (1315:1315:1315) (1372:1372:1372)) - (PORT datad (571:571:571) (567:567:567)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1728:1728:1728) (1760:1760:1760)) + (PORT datab (1817:1817:1817) (1824:1824:1824)) + (PORT datac (539:539:539) (530:530:530)) + (PORT datad (1093:1093:1093) (1108:1108:1108)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49683,13 +52597,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) + (INSTANCE z80_\|execute_\|setM1\~22) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (570:570:570) (566:566:566)) - (PORT datad (1769:1769:1769) (1734:1734:1734)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1783:1783:1783) (1744:1744:1744)) + (PORT datab (606:606:606) (638:638:638)) + (PORT datac (860:860:860) (870:870:870)) + (PORT datad (568:568:568) (563:563:563)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49697,13 +52613,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) + (INSTANCE z80_\|execute_\|setM1\~23) (DELAY (ABSOLUTE - (PORT dataa (1075:1075:1075) (1081:1081:1081)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1251:1251:1251) (1218:1218:1218)) + (PORT dataa (210:210:210) (252:252:252)) + (PORT datab (1069:1069:1069) (1074:1074:1074)) + (PORT datac (1262:1262:1262) (1313:1313:1313)) + (PORT datad (158:158:158) (179:179:179)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -49713,15 +52629,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) + (INSTANCE z80_\|execute_\|setM1\~37) (DELAY (ABSOLUTE - (PORT dataa (1080:1080:1080) (1095:1095:1095)) - (PORT datab (1056:1056:1056) (1051:1051:1051)) - (PORT datac (1288:1288:1288) (1303:1303:1303)) - (PORT datad (1217:1217:1217) (1233:1233:1233)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (557:557:557) (553:553:553)) + (PORT datab (597:597:597) (610:610:610)) + (PORT datac (566:566:566) (586:586:586)) + (PORT datad (557:557:557) (556:556:556)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49732,152 +52648,12 @@ (INSTANCE z80_\|execute_\|setM1\~12) (DELAY (ABSOLUTE - (PORT dataa (1040:1040:1040) (1031:1031:1031)) - (PORT datab (1493:1493:1493) (1562:1562:1562)) - (PORT datac (1243:1243:1243) (1219:1219:1219)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (836:836:836)) - (PORT datab (1063:1063:1063) (1094:1094:1094)) - (PORT datac (615:615:615) (678:678:678)) - (PORT datad (809:809:809) (802:802:802)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (834:834:834)) - (PORT datac (1396:1396:1396) (1416:1416:1416)) - (PORT datad (777:777:777) (749:749:749)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (236:236:236)) - (PORT datab (1102:1102:1102) (1107:1107:1107)) - (PORT datac (1119:1119:1119) (1115:1115:1115)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (892:892:892)) - (PORT datab (639:639:639) (636:636:636)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (1822:1822:1822) (1821:1821:1821)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (868:868:868)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (1380:1380:1380) (1410:1410:1410)) - (PORT datad (584:584:584) (592:592:592)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1035:1035:1035)) - (PORT datab (1030:1030:1030) (1102:1102:1102)) - (PORT datac (519:519:519) (523:523:523)) - (PORT datad (760:760:760) (739:739:739)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1598:1598:1598) (1641:1641:1641)) - (PORT datab (1850:1850:1850) (1845:1845:1845)) - (PORT datac (872:872:872) (896:896:896)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (940:940:940)) - (PORT datab (923:923:923) (945:945:945)) - (PORT datac (154:154:154) (183:183:183)) - (PORT datad (870:870:870) (890:890:890)) + (PORT dataa (578:578:578) (586:586:586)) + (PORT datab (1099:1099:1099) (1088:1088:1088)) + (PORT datac (1076:1076:1076) (1055:1055:1055)) + (PORT datad (1059:1059:1059) (1057:1057:1057)) (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1367:1367:1367) (1369:1369:1369)) - (PORT datab (1287:1287:1287) (1271:1271:1271)) - (PORT datac (1350:1350:1350) (1421:1421:1421)) - (PORT datad (548:548:548) (552:552:552)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49885,61 +52661,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) + (INSTANCE z80_\|execute_\|setM1\~14) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (220:220:220)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (321:321:321) (325:325:325)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (242:242:242) (312:312:312)) - (PORT datac (617:617:617) (656:656:656)) - (PORT datad (828:828:828) (836:836:836)) + (PORT dataa (1142:1142:1142) (1133:1133:1133)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1921:1921:1921) (1860:1860:1860)) + (PORT datad (568:568:568) (582:582:582)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) + (INSTANCE z80_\|execute_\|setM1\~10) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (849:849:849) (901:901:901)) - (PORT datac (1262:1262:1262) (1245:1245:1245)) - (PORT datad (337:337:337) (338:338:338)) + (PORT dataa (1137:1137:1137) (1150:1150:1150)) + (PORT datab (1206:1206:1206) (1271:1271:1271)) + (PORT datac (1092:1092:1092) (1082:1082:1082)) + (PORT datad (1172:1172:1172) (1210:1210:1210)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -49949,28 +52693,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (INSTANCE z80_\|execute_\|setM1\~11) (DELAY (ABSOLUTE - (PORT dataa (573:573:573) (573:573:573)) - (PORT datab (1030:1030:1030) (1023:1023:1023)) - (PORT datac (836:836:836) (888:888:888)) - (PORT datad (506:506:506) (503:503:503)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT datab (1374:1374:1374) (1395:1395:1395)) + (PORT datac (852:852:852) (841:841:841)) + (PORT datad (842:842:842) (852:852:852)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (591:591:591)) + (PORT datab (345:345:345) (354:354:354)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (759:759:759) (770:770:770)) + (PORT datac (589:589:589) (594:594:594)) + (PORT datad (821:821:821) (844:844:844)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (575:575:575)) + (PORT datab (801:801:801) (781:781:781)) + (PORT datac (547:547:547) (559:559:559)) + (PORT datad (850:850:850) (868:868:868)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (2409:2409:2409) (2453:2453:2453)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) (DELAY (ABSOLUTE - (PORT datab (640:640:640) (689:689:689)) - (PORT datad (830:830:830) (838:838:838)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1141:1141:1141) (1174:1174:1174)) + (PORT datad (889:889:889) (928:928:928)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49981,9 +52787,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -49994,14 +52800,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) + (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (618:618:618) (647:647:647)) - (PORT datab (653:653:653) (687:687:687)) - (PORT datad (819:819:819) (832:832:832)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (384:384:384) (431:431:431)) + (PORT datab (1656:1656:1656) (1680:1680:1680)) + (PORT datad (1237:1237:1237) (1338:1338:1338)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50009,12 +52815,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT clrn (1686:1686:1686) (1662:1662:1662)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50025,28 +52831,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT datab (909:909:909) (960:960:960)) - (PORT datac (1140:1140:1140) (1196:1196:1196)) - (PORT datad (887:887:887) (940:940:940)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (1419:1419:1419) (1507:1507:1507)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (204:204:204) (263:263:263)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT asdata (509:509:509) (574:574:574)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1128:1128:1128)) + (PORT datab (225:225:225) (296:296:296)) + (PORT datad (203:203:203) (262:262:262)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (1372:1372:1372) (1395:1395:1395)) - (PORT datad (1092:1092:1092) (1089:1089:1089)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (607:607:607) (625:625:625)) + (PORT datad (783:783:783) (765:765:765)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50056,11 +52923,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1092:1092:1092) (1122:1122:1122)) - (PORT datab (781:781:781) (765:765:765)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (357:357:357) (369:369:369)) + (PORT datab (822:822:822) (849:849:849)) + (PORT datad (830:830:830) (833:833:833)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50070,11 +52937,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT clk (1342:1342:1342) (1352:1352:1352)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (647:647:647) (684:684:684)) - (PORT sload (1315:1315:1315) (1359:1359:1359)) - (PORT ena (1338:1338:1338) (1327:1327:1327)) + (PORT asdata (841:841:841) (861:861:861)) + (PORT sload (1151:1151:1151) (1206:1206:1206)) + (PORT ena (1597:1597:1597) (1581:1581:1581)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -50087,59 +52954,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~66) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~2) (DELAY (ABSOLUTE - (PORT datab (835:835:835) (837:837:837)) - (PORT datac (805:805:805) (817:817:817)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (2560:2560:2560) (2559:2559:2559)) - (PORT datab (1368:1368:1368) (1383:1383:1383)) - (PORT datac (1370:1370:1370) (1379:1379:1379)) - (PORT datad (287:287:287) (293:293:293)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (2429:2429:2429) (2459:2459:2459)) - (PORT datab (1783:1783:1783) (1866:1866:1866)) - (PORT datac (2569:2569:2569) (2667:2667:2667)) - (PORT datad (2260:2260:2260) (2252:2252:2252)) + (PORT dataa (595:595:595) (597:597:597)) + (PORT datab (879:879:879) (911:911:911)) + (PORT datac (657:657:657) (726:726:726)) + (PORT datad (830:830:830) (813:813:813)) (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (626:626:626) (643:643:643)) - (PORT datac (1001:1001:1001) (1003:1003:1003)) - (PORT datad (324:324:324) (332:332:332)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab combout (308:308:308) (285:285:285)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50147,73 +52970,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~69) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (2560:2560:2560) (2559:2559:2559)) - (PORT datab (883:883:883) (922:922:922)) - (PORT datac (1369:1369:1369) (1378:1378:1378)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) + (PORT dataa (846:846:846) (834:834:834)) + (PORT datab (878:878:878) (908:908:908)) + (PORT datac (856:856:856) (854:854:854)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datab (1076:1076:1076) (1097:1097:1097)) - (PORT datac (782:782:782) (785:785:785)) - (PORT datad (305:305:305) (308:308:308)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (2031:2031:2031) (2020:2020:2020)) - (PORT datab (578:578:578) (593:593:593)) - (PORT datac (1571:1571:1571) (1601:1601:1601)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (2559:2559:2559) (2556:2556:2556)) - (PORT datac (841:841:841) (883:883:883)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (368:368:368)) - (PORT datab (876:876:876) (873:873:873)) - (PORT datac (312:312:312) (314:314:314)) - (PORT datad (309:309:309) (317:317:317)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50221,121 +52986,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~95) + (INSTANCE Selector14\~15) (DELAY (ABSOLUTE - (PORT dataa (847:847:847) (863:863:863)) - (PORT datab (848:848:848) (853:853:853)) - (PORT datac (163:163:163) (198:198:198)) + (PORT dataa (1190:1190:1190) (1210:1210:1210)) + (PORT datab (930:930:930) (995:995:995)) + (PORT datac (1393:1393:1393) (1403:1403:1403)) + (PORT datad (1112:1112:1112) (1119:1119:1119)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~96) + (INSTANCE Selector14\~16) (DELAY (ABSOLUTE - (PORT dataa (1193:1193:1193) (1257:1257:1257)) - (PORT datab (405:405:405) (418:418:418)) - (PORT datac (2040:2040:2040) (2021:2021:2021)) + (PORT dataa (1126:1126:1126) (1145:1145:1145)) + (PORT datab (931:931:931) (994:994:994)) + (PORT datac (1181:1181:1181) (1137:1137:1137)) (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~126) + (INSTANCE D\[0\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1730:1730:1730) (1712:1712:1712)) - (PORT datab (2864:2864:2864) (2965:2965:2965)) - (PORT datac (571:571:571) (569:569:569)) - (PORT datad (305:305:305) (307:307:307)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (760:760:760) (729:729:729)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (577:577:577) (576:576:576)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~98) + (INSTANCE D\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1115:1115:1115) (1152:1152:1152)) - (PORT datab (625:625:625) (617:617:617)) - (PORT datac (2270:2270:2270) (2238:2238:2238)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~105) - (DELAY - (ABSOLUTE - (PORT datab (810:810:810) (813:813:813)) - (PORT datac (342:342:342) (345:345:345)) - (PORT datad (324:324:324) (330:330:330)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1165:1165:1165)) - (PORT datab (577:577:577) (590:590:590)) - (PORT datac (2006:2006:2006) (1993:1993:1993)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (2594:2594:2594) (2704:2704:2704)) - (PORT datab (1879:1879:1879) (1883:1883:1883)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (568:568:568) (585:585:585)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1139:1139:1139)) - (PORT datab (2300:2300:2300) (2288:2288:2288)) - (PORT datac (322:322:322) (330:330:330)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (952:952:952) (1018:1018:1018)) + (PORT datab (1600:1600:1600) (1628:1628:1628)) + (PORT datac (173:173:173) (204:204:204)) + (PORT datad (160:160:160) (182:182:182)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50345,12 +53050,381 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~4) (DELAY (ABSOLUTE - (PORT datab (225:225:225) (298:298:298)) - (PORT datac (793:793:793) (776:776:776)) - (PORT datad (210:210:210) (270:270:270)) + (PORT dataa (901:901:901) (951:951:951)) + (PORT datab (1056:1056:1056) (1101:1101:1101)) + (PORT datac (733:733:733) (701:701:701)) + (PORT datad (770:770:770) (745:745:745)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1039:1039:1039)) + (PORT datab (878:878:878) (931:931:931)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1262:1262:1262) (1253:1253:1253)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~12) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1012:1012:1012)) + (PORT datab (1086:1086:1086) (1098:1098:1098)) + (PORT datac (1027:1027:1027) (1004:1004:1004)) + (PORT datad (1324:1324:1324) (1296:1296:1296)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~13) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1017:1017:1017)) + (PORT datab (1316:1316:1316) (1284:1284:1284)) + (PORT datac (1557:1557:1557) (1555:1555:1555)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1091:1091:1091)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (318:318:318) (330:330:330)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1117:1117:1117)) + (PORT datab (1006:1006:1006) (1096:1096:1096)) + (PORT datac (1355:1355:1355) (1390:1390:1390)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (303:303:303) (312:312:312)) + (PORT datad (889:889:889) (902:902:902)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (839:839:839)) + (PORT datab (644:644:644) (701:701:701)) + (PORT datac (1732:1732:1732) (1704:1704:1704)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (710:710:710)) + (PORT datab (400:400:400) (461:461:461)) + (PORT datac (839:839:839) (849:849:849)) + (PORT datad (1296:1296:1296) (1292:1292:1292)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1610:1610:1610) (1568:1568:1568)) + (PORT datab (399:399:399) (464:464:464)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1361:1361:1361) (1360:1360:1360)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1120:1120:1120)) + (PORT datab (1132:1132:1132) (1154:1154:1154)) + (PORT datac (591:591:591) (639:639:639)) + (PORT datad (1580:1580:1580) (1569:1569:1569)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1373:1373:1373) (1389:1389:1389)) + (PORT datab (428:428:428) (477:477:477)) + (PORT datac (1603:1603:1603) (1645:1645:1645)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1342:1342:1342)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1112:1112:1112)) + (PORT datab (1305:1305:1305) (1278:1278:1278)) + (PORT datac (1064:1064:1064) (1069:1069:1069)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (1856:1856:1856) (1872:1872:1872)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1337:1337:1337) (1357:1357:1357)) + (PORT datab (1033:1033:1033) (1076:1076:1076)) + (PORT datac (1139:1139:1139) (1145:1145:1145)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (858:858:858)) + (PORT datab (660:660:660) (696:696:696)) + (PORT datad (818:818:818) (817:817:817)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (609:609:609)) + (PORT datab (657:657:657) (691:691:691)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (823:823:823) (812:812:812)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1645:1645:1645) (1648:1648:1648)) + (PORT datab (250:250:250) (328:328:328)) + (PORT datac (1343:1343:1343) (1348:1348:1348)) + (PORT datad (1405:1405:1405) (1423:1423:1423)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (613:613:613)) + (PORT datab (2325:2325:2325) (2346:2346:2346)) + (PORT datac (1095:1095:1095) (1118:1118:1118)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (250:250:250) (328:328:328)) + (PORT datac (1180:1180:1180) (1223:1223:1223)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1363:1363:1363) (1390:1390:1390)) + (PORT datab (651:651:651) (704:704:704)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (1241:1241:1241) (1230:1230:1230)) + (PORT datac (861:861:861) (883:883:883)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1349:1349:1349)) + (PORT datab (1093:1093:1093) (1088:1088:1088)) + (PORT datac (850:850:850) (869:869:869)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50362,12 +53436,12 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (640:640:640) (689:689:689)) - (PORT datac (618:618:618) (656:656:656)) - (PORT datad (570:570:570) (600:600:600)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (242:242:242) (315:315:315)) + (PORT datab (249:249:249) (323:323:323)) + (PORT datac (1101:1101:1101) (1131:1131:1131)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -50376,10 +53450,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50394,7 +53468,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (626:626:626) (660:660:660)) + (PORT datad (1316:1316:1316) (1309:1309:1309)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50404,10 +53478,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT clk (1339:1339:1339) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) + (PORT clrn (1375:1375:1375) (1348:1348:1348)) + (PORT ena (1445:1445:1445) (1437:1437:1437)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50422,10 +53496,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT clk (1339:1339:1339) (1349:1349:1349)) (PORT asdata (513:513:513) (581:581:581)) - (PORT clrn (1399:1399:1399) (1367:1367:1367)) - (PORT ena (1146:1146:1146) (1137:1137:1137)) + (PORT clrn (1375:1375:1375) (1348:1348:1348)) + (PORT ena (1445:1445:1445) (1437:1437:1437)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50440,9 +53514,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (844:844:844) (882:882:882)) - (PORT datab (229:229:229) (301:301:301)) - (PORT datad (203:203:203) (263:263:263)) + (PORT dataa (228:228:228) (304:304:304)) + (PORT datab (587:587:587) (624:624:624)) + (PORT datad (205:205:205) (265:265:265)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -50455,10 +53529,10 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (304:304:304)) - (PORT datab (237:237:237) (311:311:311)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (165:165:165) (190:190:190)) + (PORT dataa (543:543:543) (553:553:553)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (202:202:202) (272:272:272)) + (PORT datad (1021:1021:1021) (1045:1045:1045)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50489,9 +53563,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50505,8 +53579,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (427:427:427)) - (PORT datab (228:228:228) (299:299:299)) + (PORT dataa (379:379:379) (426:426:426)) + (PORT datab (227:227:227) (300:300:300)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -50520,9 +53594,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50550,9 +53624,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50580,9 +53654,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50591,22 +53665,6 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (PORT datab (240:240:240) (310:310:310)) - (PORT datac (200:200:200) (271:271:271)) - (PORT datad (205:205:205) (266:266:266)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) @@ -50626,9 +53684,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50642,7 +53700,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE - (PORT datad (206:206:206) (265:265:265)) + (PORT datad (205:205:205) (267:267:267)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -50653,9 +53711,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT clk (1683:1683:1683) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50664,47 +53722,45 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (PORT datab (225:225:225) (298:298:298)) + (PORT datac (213:213:213) (279:279:279)) + (PORT datad (205:205:205) (266:266:266)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (185:185:185) (219:219:219)) - (PORT datac (202:202:202) (273:273:273)) - (PORT datad (205:205:205) (263:263:263)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT datab (227:227:227) (298:298:298)) + (PORT datac (200:200:200) (270:270:270)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1367:1367:1367)) - (PORT ena (923:923:923) (893:893:893)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1684:1684:1684) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) - (PORT ena (1351:1351:1351) (1346:1346:1346)) + (PORT clrn (1398:1398:1398) (1380:1380:1380)) + (PORT ena (1277:1277:1277) (1281:1281:1281)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50719,7 +53775,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (374:374:374) (422:422:422)) + (PORT datad (229:229:229) (295:295:295)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50730,10 +53786,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) - (PORT ena (1351:1351:1351) (1346:1346:1346)) + (PORT clrn (1398:1398:1398) (1380:1380:1380)) + (PORT ena (1435:1435:1435) (1454:1454:1454)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50748,9 +53804,9 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (424:424:424) (459:459:459)) - (PORT datad (365:365:365) (409:409:409)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT datab (255:255:255) (330:330:330)) + (PORT datad (253:253:253) (329:329:329)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50761,10 +53817,28 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) - (PORT ena (798:798:798) (748:748:748)) + (PORT clrn (1398:1398:1398) (1380:1380:1380)) + (PORT ena (1435:1435:1435) (1454:1454:1454)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1684:1684:1684) (1700:1700:1700)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1398:1398:1398) (1380:1380:1380)) + (PORT ena (1277:1277:1277) (1281:1281:1281)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50779,9 +53853,9 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datab (421:421:421) (474:474:474)) - (PORT datac (239:239:239) (317:317:317)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (599:599:599) (639:639:639)) + (PORT datac (556:556:556) (585:585:585)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) @@ -50791,366 +53865,23 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (433:433:433) (483:483:483)) - (PORT datac (536:536:536) (561:561:561)) - (PORT datad (812:812:812) (835:835:835)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~4) - (DELAY - (ABSOLUTE - (PORT datad (638:638:638) (682:682:682)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (436:436:436)) - (PORT datab (603:603:603) (633:633:633)) - (PORT datad (659:659:659) (703:703:703)) - (IOPATH dataa combout (273:273:273) (273:273:273)) + (PORT datab (435:435:435) (486:486:486)) + (PORT datad (663:663:663) (711:711:711)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1367:1367:1367)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (432:432:432) (481:481:481)) - (PORT datac (547:547:547) (576:576:576)) - (PORT datad (255:255:255) (324:324:324)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (565:565:565) (590:590:590)) - (PORT datac (581:581:581) (609:609:609)) - (PORT datad (791:791:791) (820:820:820)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (624:624:624)) - (PORT datab (586:586:586) (589:589:589)) - (PORT datac (578:578:578) (633:633:633)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1688:1688:1688) (1702:1702:1702)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT ena (1102:1102:1102) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (720:720:720)) - (PORT datad (364:364:364) (401:401:401)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT ena (1131:1131:1131) (1133:1133:1133)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) - (PORT datab (237:237:237) (314:314:314)) - (PORT datad (357:357:357) (394:394:394)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (422:422:422) (472:472:472)) - (PORT datac (241:241:241) (320:320:320)) - (PORT datad (612:612:612) (633:633:633)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT datab (435:435:435) (482:482:482)) - (PORT datac (550:550:550) (576:576:576)) - (PORT datad (256:256:256) (325:325:325)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT datab (423:423:423) (474:474:474)) - (PORT datac (240:240:240) (318:318:318)) - (PORT datad (306:306:306) (320:320:320)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (631:631:631) (633:633:633)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) - (PORT sload (787:787:787) (899:899:899)) - (PORT ena (1351:1351:1351) (1346:1346:1346)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (722:722:722)) - (PORT datab (236:236:236) (312:312:312)) - (PORT datad (360:360:360) (399:399:399)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT ena (1131:1131:1131) (1133:1133:1133)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (308:308:308)) - (PORT datab (382:382:382) (428:428:428)) - (PORT datac (816:816:816) (837:837:837)) - (PORT datad (213:213:213) (280:280:280)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (326:326:326)) - (PORT datab (281:281:281) (359:359:359)) - (PORT datac (534:534:534) (558:558:558)) - (PORT datad (570:570:570) (602:602:602)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (626:626:626)) - (PORT datab (604:604:604) (658:658:658)) - (PORT datac (580:580:580) (608:608:608)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (596:596:596)) - (PORT datab (183:183:183) (214:214:214)) - (PORT datad (792:792:792) (823:823:823)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1708:1708:1708) (1724:1724:1724)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datac (616:616:616) (662:662:662)) - (PORT datad (404:404:404) (442:442:442)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (837:837:837) (849:849:849)) + (PORT datac (542:542:542) (569:569:569)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -51168,10 +53899,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (437:437:437)) - (PORT datab (695:695:695) (743:743:743)) - (PORT datac (216:216:216) (284:284:284)) - (PORT datad (465:465:465) (444:444:444)) + (PORT dataa (399:399:399) (441:441:441)) + (PORT datab (436:436:436) (487:487:487)) + (PORT datac (233:233:233) (309:309:309)) + (PORT datad (634:634:634) (586:586:586)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -51184,13 +53915,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (323:323:323) (332:332:332)) - (PORT datab (602:602:602) (601:601:601)) - (PORT datac (571:571:571) (600:600:600)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (706:706:706) (752:752:752)) + (PORT datab (608:608:608) (601:601:601)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51200,11 +53931,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (638:638:638)) - (PORT datab (573:573:573) (573:573:573)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT datab (391:391:391) (445:445:445)) + (PORT datac (773:773:773) (739:739:739)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51214,28 +53945,386 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (635:635:635) (635:635:635)) - (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (752:752:752)) + (PORT datab (437:437:437) (487:487:487)) + (PORT datad (255:255:255) (321:321:321)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (833:833:833) (851:851:851)) + (PORT datac (233:233:233) (310:310:310)) + (PORT datad (254:254:254) (320:320:320)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT datab (596:596:596) (630:630:630)) + (PORT datac (387:387:387) (435:435:435)) + (PORT datad (481:481:481) (461:461:461)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT datad (390:390:390) (441:441:441)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (639:639:639)) + (PORT datab (251:251:251) (326:326:326)) + (PORT datac (553:553:553) (583:583:583)) + (PORT datad (246:246:246) (315:315:315)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (408:408:408) (467:467:467)) + (PORT datac (234:234:234) (311:311:311)) + (PORT datad (254:254:254) (317:317:317)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (242:242:242)) + (PORT datab (559:559:559) (552:552:552)) + (PORT datac (157:157:157) (189:189:189)) + (PORT datad (658:658:658) (704:704:704)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (364:364:364)) + (PORT datab (254:254:254) (328:328:328)) + (PORT datac (564:564:564) (563:563:563)) + (PORT datad (745:745:745) (725:725:725)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT ena (842:842:842) (823:823:823)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (310:310:310)) + (PORT datab (248:248:248) (322:322:322)) + (PORT datad (231:231:231) (293:293:293)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (645:645:645)) + (PORT datac (557:557:557) (589:589:589)) + (PORT datad (504:504:504) (491:491:491)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (354:354:354)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (656:656:656) (668:668:668)) + (PORT clrn (1399:1399:1399) (1382:1382:1382)) + (PORT sload (786:786:786) (893:893:893)) + (PORT ena (1296:1296:1296) (1311:1311:1311)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (417:417:417) (478:478:478)) + (PORT datad (230:230:230) (290:290:290)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT ena (842:842:842) (823:823:823)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (454:454:454)) + (PORT datab (412:412:412) (476:476:476)) + (PORT datad (231:231:231) (293:293:293)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT ena (842:842:842) (823:823:823)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (249:249:249) (323:323:323)) + (PORT datac (358:358:358) (394:394:394)) + (PORT datad (383:383:383) (431:431:431)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (317:317:317)) + (PORT datab (262:262:262) (339:339:339)) + (PORT datac (208:208:208) (283:283:283)) + (PORT datad (229:229:229) (296:296:296)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (393:393:393)) + (PORT datab (796:796:796) (812:812:812)) + (PORT datac (334:334:334) (340:340:340)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (792:792:792) (767:767:767)) + (PORT datad (246:246:246) (315:315:315)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1382:1382:1382)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT datab (433:433:433) (481:481:481)) - (PORT datac (548:548:548) (573:573:573)) - (PORT datad (252:252:252) (321:321:321)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT datab (837:837:837) (853:853:853)) + (PORT datac (234:234:234) (312:312:312)) + (PORT datad (255:255:255) (318:318:318)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51246,9 +54335,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (625:625:625)) - (PORT datab (584:584:584) (585:585:585)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (373:373:373) (394:394:394)) + (PORT datab (793:793:793) (767:767:767)) + (PORT datad (475:475:475) (457:457:457)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -51261,9 +54350,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1708:1708:1708) (1724:1724:1724)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT clrn (1399:1399:1399) (1382:1382:1382)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51277,12 +54366,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (324:324:324)) - (PORT datab (820:820:820) (857:857:857)) - (PORT datac (744:744:744) (764:764:764)) - (PORT datad (814:814:814) (832:832:832)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (600:600:600) (640:640:640)) + (PORT datab (235:235:235) (309:309:309)) + (PORT datac (557:557:557) (586:586:586)) + (PORT datad (252:252:252) (321:321:321)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51293,7 +54382,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (268:268:268) (348:348:348)) + (PORT datab (281:281:281) (368:368:368)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51302,15 +54391,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (558:558:558) (582:582:582)) - (PORT datab (864:864:864) (877:877:877)) - (PORT datac (574:574:574) (597:597:597)) - (PORT datad (651:651:651) (612:612:612)) + (PORT dataa (579:579:579) (613:613:613)) + (PORT datab (421:421:421) (458:458:458)) + (PORT datac (668:668:668) (627:627:627)) + (PORT datad (348:348:348) (387:387:387)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51321,12 +54410,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (558:558:558) (568:568:568)) - (PORT datab (425:425:425) (461:461:461)) - (PORT datac (731:731:731) (749:749:749)) - (PORT datad (162:162:162) (184:184:184)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (626:626:626) (654:654:654)) + (PORT datab (768:768:768) (729:729:729)) + (PORT datac (795:795:795) (802:802:802)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51337,11 +54426,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1693:1693:1693)) + (PORT clk (1659:1659:1659) (1670:1670:1670)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2461:2461:2461) (2410:2410:2410)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) - (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT asdata (2055:2055:2055) (1976:1976:1976)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT sload (1134:1134:1134) (1140:1140:1140)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -51359,9 +54448,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (259:259:259) (353:353:353)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (264:264:264) (360:360:360)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -51373,11 +54462,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1693:1693:1693)) + (PORT clk (1659:1659:1659) (1670:1670:1670)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2461:2461:2461) (2410:2410:2410)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) - (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT asdata (2055:2055:2055) (1977:1977:1977)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT sload (1134:1134:1134) (1140:1140:1140)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -51395,9 +54484,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (370:370:370)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (263:263:263) (357:357:357)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -51409,10 +54498,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1693:1693:1693)) + (PORT clk (1659:1659:1659) (1670:1670:1670)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) - (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT sload (1134:1134:1134) (1140:1140:1140)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -51430,9 +54519,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (272:272:272) (352:352:352)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (263:263:263) (345:345:345)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -51444,11 +54533,43 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1693:1693:1693)) + (PORT clk (1659:1659:1659) (1670:1670:1670)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2463:2463:2463) (2407:2407:2407)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) - (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT asdata (2056:2056:2056) (1977:1977:1977)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT sload (1134:1134:1134) (1140:1140:1140)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datad (251:251:251) (319:319:319)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1670:1670:1670)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1397:1397:1397) (1380:1380:1380)) + (PORT sload (1134:1134:1134) (1140:1140:1140)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -51466,58 +54587,26 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (403:403:403) (463:463:463)) - (PORT datab (259:259:259) (352:352:352)) - (PORT datac (244:244:244) (341:341:341)) - (PORT datad (251:251:251) (320:320:320)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (270:270:270) (369:369:369)) + (PORT datab (268:268:268) (363:363:363)) + (PORT datac (260:260:260) (348:348:348)) + (PORT datad (240:240:240) (311:311:311)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (357:357:357)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1693:1693:1693)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1367:1367:1367)) - (PORT sload (1381:1381:1381) (1389:1389:1389)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (184:184:184) (216:216:216)) - (PORT datac (328:328:328) (331:331:331)) - (PORT datad (373:373:373) (408:408:408)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (185:185:185) (223:223:223)) + (PORT datac (566:566:566) (594:594:594)) + (PORT datad (471:471:471) (451:451:451)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51528,11 +54617,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (427:427:427)) - (PORT datab (446:446:446) (482:482:482)) - (PORT datad (808:808:808) (819:819:819)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT datab (253:253:253) (329:329:329)) + (PORT datac (207:207:207) (282:282:282)) + (PORT datad (248:248:248) (317:317:317)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51542,13 +54631,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (507:507:507)) - (PORT datab (246:246:246) (319:319:319)) - (PORT datac (228:228:228) (305:305:305)) - (PORT datad (612:612:612) (630:630:630)) + (PORT dataa (205:205:205) (243:243:243)) + (PORT datab (278:278:278) (358:358:358)) + (PORT datac (210:210:210) (285:285:285)) + (PORT datad (506:506:506) (492:492:492)) (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51558,13 +54647,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (395:395:395) (456:456:456)) - (PORT datac (234:234:234) (309:309:309)) - (PORT datad (201:201:201) (236:236:236)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (796:796:796) (817:817:817)) + (PORT datac (341:341:341) (356:356:356)) + (PORT datad (237:237:237) (307:307:307)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51574,11 +54663,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (833:833:833) (838:838:838)) - (PORT datab (590:590:590) (578:578:578)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (796:796:796) (773:773:773)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51589,9 +54678,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1399:1399:1399) (1382:1382:1382)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51605,11 +54694,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (273:273:273)) - (PORT datab (248:248:248) (321:321:321)) - (PORT datad (369:369:369) (421:421:421)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (238:238:238) (317:317:317)) + (PORT datab (799:799:799) (818:818:818)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51620,10 +54709,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) - (PORT ena (1351:1351:1351) (1346:1346:1346)) + (PORT clrn (1399:1399:1399) (1382:1382:1382)) + (PORT ena (1296:1296:1296) (1311:1311:1311)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51638,12 +54727,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (297:297:297)) - (PORT datab (645:645:645) (690:690:690)) - (PORT datac (573:573:573) (601:601:601)) - (PORT datad (657:657:657) (701:701:701)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (271:271:271) (364:364:364)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datac (660:660:660) (707:707:707)) + (PORT datad (252:252:252) (332:332:332)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (285:285:285)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51654,10 +54743,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datac (570:570:570) (600:600:600)) - (PORT datad (184:184:184) (211:211:211)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datac (657:657:657) (701:701:701)) + (PORT datad (560:560:560) (550:550:550)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51669,9 +54758,9 @@ (DELAY (ABSOLUTE (PORT clk (1306:1306:1306) (1319:1319:1319)) - (PORT d (851:851:851) (915:915:915)) + (PORT d (883:883:883) (935:935:935)) (PORT aload (1497:1497:1497) (1541:1541:1541)) - (PORT ena (650:650:650) (643:643:643)) + (PORT ena (781:781:781) (798:798:798)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) (IOPATH (posedge aload) q (455:455:455) (458:458:458)) ) @@ -51688,368 +54777,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1684:1684:1684) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1367:1367:1367)) - (PORT ena (923:923:923) (893:893:893)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (460:460:460)) - (PORT datab (258:258:258) (347:347:347)) - (PORT datac (237:237:237) (333:333:333)) - (PORT datad (249:249:249) (314:314:314)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (569:569:569) (596:596:596)) - (PORT datad (807:807:807) (816:816:816)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (461:461:461)) - (PORT datab (256:256:256) (351:351:351)) - (PORT datac (246:246:246) (331:331:331)) - (PORT datad (248:248:248) (317:317:317)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (377:377:377)) - (PORT datab (540:540:540) (529:529:529)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (242:242:242) (311:311:311)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (376:376:376)) - (PORT datab (266:266:266) (344:344:344)) - (PORT datac (247:247:247) (329:329:329)) - (PORT datad (248:248:248) (317:317:317)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (520:520:520)) - (PORT datab (258:258:258) (351:351:351)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (242:242:242) (312:312:312)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (445:445:445) (515:515:515)) - (PORT datac (630:630:630) (661:661:661)) - (PORT datad (618:618:618) (645:645:645)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (328:328:328)) - (PORT datac (239:239:239) (317:317:317)) - (PORT datad (382:382:382) (438:438:438)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (333:333:333) (357:357:357)) - (PORT datac (237:237:237) (315:315:315)) - (PORT datad (196:196:196) (230:230:230)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (833:833:833)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (375:375:375) (426:426:426)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT sclr (1196:1196:1196) (1234:1234:1234)) - (PORT ena (869:869:869) (854:854:854)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sclr (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) - (DELAY - (ABSOLUTE - (PORT datab (582:582:582) (591:591:591)) - (PORT datac (412:412:412) (477:477:477)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (459:459:459)) - (PORT datab (333:333:333) (353:353:353)) - (PORT datac (237:237:237) (315:315:315)) - (PORT datad (386:386:386) (434:434:434)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (271:271:271)) - (PORT datab (253:253:253) (329:329:329)) - (PORT datac (232:232:232) (309:309:309)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (837:837:837)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (373:373:373) (420:420:420)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT ena (879:879:879) (879:879:879)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (577:577:577)) - (PORT datac (411:411:411) (477:477:477)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT ena (879:879:879) (879:879:879)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (377:377:377)) - (PORT datab (257:257:257) (351:351:351)) - (PORT datac (246:246:246) (330:330:330)) - (PORT datad (248:248:248) (317:317:317)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (377:377:377)) - (PORT datac (249:249:249) (332:332:332)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (556:556:556)) - (PORT datab (320:320:320) (341:341:341)) - (PORT datac (632:632:632) (658:658:658)) - (PORT datad (618:618:618) (642:642:642)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datab (769:769:769) (781:781:781)) - (PORT datac (415:415:415) (479:479:479)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT ena (879:879:879) (879:879:879)) + (PORT clrn (1398:1398:1398) (1380:1380:1380)) + (PORT ena (1277:1277:1277) (1281:1281:1281)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52064,12 +54795,40 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (376:376:376)) - (PORT datab (260:260:260) (353:353:353)) - (PORT datac (248:248:248) (330:330:330)) - (PORT datad (243:243:243) (313:313:313)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datac (235:235:235) (329:329:329)) + (PORT datad (250:250:250) (317:317:317)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (359:359:359)) + (PORT datab (265:265:265) (355:355:355)) + (PORT datac (247:247:247) (337:337:337)) + (PORT datad (250:250:250) (314:314:314)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (573:573:573)) + (PORT datab (660:660:660) (707:707:707)) + (PORT datac (635:635:635) (664:664:664)) + (PORT datad (454:454:454) (442:442:442)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52080,28 +54839,74 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (676:676:676)) - (PORT datab (609:609:609) (600:600:600)) - (PORT datac (631:631:631) (658:658:658)) - (PORT datad (302:302:302) (312:312:312)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (267:267:267) (367:367:367)) + (PORT datab (393:393:393) (439:439:439)) + (PORT datac (236:236:236) (331:331:331)) + (PORT datad (250:250:250) (317:317:317)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datab (771:771:771) (783:783:783)) - (PORT datac (412:412:412) (481:481:481)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (564:564:564) (572:572:572)) + (PORT datab (659:659:659) (707:707:707)) + (PORT datac (633:633:633) (664:664:664)) + (PORT datad (553:553:553) (545:545:545)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (768:768:768)) + (PORT datab (660:660:660) (705:705:705)) + (PORT datac (633:633:633) (663:663:663)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (367:367:367)) + (PORT datab (705:705:705) (744:744:744)) + (PORT datac (657:657:657) (703:703:703)) + (PORT datad (328:328:328) (337:337:337)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (282:282:282) (373:373:373)) + (PORT datac (528:528:528) (543:543:543)) + (PORT datad (745:745:745) (729:729:729)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52109,13 +54914,137 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT ena (879:879:879) (879:879:879)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT sclr (1090:1090:1090) (1170:1170:1170)) + (PORT ena (1059:1059:1059) (1024:1024:1024)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (343:343:343)) + (PORT datab (264:264:264) (359:359:359)) + (PORT datac (259:259:259) (345:345:345)) + (PORT datad (249:249:249) (314:314:314)) + (IOPATH dataa combout (299:299:299) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~6) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (338:338:338)) + (PORT datad (249:249:249) (318:318:318)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (762:762:762) (748:748:748)) + (PORT datac (259:259:259) (347:347:347)) + (PORT datad (244:244:244) (328:328:328)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (298:298:298)) + (PORT datac (664:664:664) (737:737:737)) + (PORT datad (555:555:555) (548:548:548)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (362:362:362)) + (PORT datab (707:707:707) (740:740:740)) + (PORT datac (547:547:547) (567:567:567)) + (PORT datad (328:328:328) (334:334:334)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (691:691:691) (735:735:735)) + (PORT datac (563:563:563) (561:561:561)) + (PORT datad (666:666:666) (704:704:704)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (355:355:355)) + (PORT datac (773:773:773) (739:739:739)) + (PORT datad (366:366:366) (410:410:410)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1115:1115:1115) (1104:1104:1104)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52127,14 +55056,162 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (588:588:588)) - (PORT datab (580:580:580) (610:610:610)) - (PORT datad (339:339:339) (366:366:366)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (271:271:271) (369:369:369)) + (PORT datab (395:395:395) (439:439:439)) + (PORT datac (260:260:260) (348:348:348)) + (PORT datad (252:252:252) (319:319:319)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (264:264:264) (360:360:360)) + (PORT datac (258:258:258) (346:346:346)) + (PORT datad (749:749:749) (728:728:728)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (294:294:294)) + (PORT datac (669:669:669) (737:737:737)) + (PORT datad (717:717:717) (682:682:682)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1115:1115:1115) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (773:773:773)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (633:633:633) (683:683:683)) + (PORT datad (201:201:201) (258:258:258)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1115:1115:1115) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (770:770:770)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (635:635:635) (683:683:683)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1115:1115:1115) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (368:368:368)) + (PORT datab (268:268:268) (362:362:362)) + (PORT datac (259:259:259) (348:348:348)) + (PORT datad (240:240:240) (311:311:311)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (414:414:414)) + (PORT datab (692:692:692) (735:735:735)) + (PORT datad (727:727:727) (700:700:700)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52144,11 +55221,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT sload (1121:1121:1121) (1182:1182:1182)) - (PORT ena (1090:1090:1090) (1059:1059:1059)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT sload (1312:1312:1312) (1368:1368:1368)) + (PORT ena (1148:1148:1148) (1125:1125:1125)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52162,14 +55239,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (596:596:596) (584:584:584)) - (PORT datac (410:410:410) (476:476:476)) - (PORT datad (358:358:358) (391:391:391)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (387:387:387) (426:426:426)) + (PORT datac (667:667:667) (735:735:735)) + (PORT datad (906:906:906) (858:858:858)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52179,11 +55256,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT sclr (1196:1196:1196) (1234:1234:1234)) - (PORT ena (879:879:879) (879:879:879)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT sclr (1090:1090:1090) (1170:1170:1170)) + (PORT ena (1115:1115:1115) (1104:1104:1104)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52196,11 +55273,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~7) (DELAY (ABSOLUTE - (PORT datac (415:415:415) (485:485:485)) - (PORT datad (201:201:201) (259:259:259)) + (PORT datac (669:669:669) (737:737:737)) + (PORT datad (199:199:199) (256:256:256)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52211,11 +55288,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (PORT sclr (1196:1196:1196) (1234:1234:1234)) - (PORT ena (869:869:869) (854:854:854)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT sclr (1090:1090:1090) (1170:1170:1170)) + (PORT ena (1059:1059:1059) (1024:1024:1024)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52231,10 +55308,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (657:657:657)) - (PORT datab (817:817:817) (858:858:858)) - (PORT datac (377:377:377) (416:416:416)) - (PORT datad (810:810:810) (834:834:834)) + (PORT dataa (639:639:639) (674:674:674)) + (PORT datab (278:278:278) (364:364:364)) + (PORT datac (621:621:621) (643:643:643)) + (PORT datad (666:666:666) (703:703:703)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -52247,10 +55324,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (320:320:320) (336:336:336)) - (PORT datab (696:696:696) (742:742:742)) - (PORT datac (177:177:177) (209:209:209)) - (PORT datad (464:464:464) (444:444:444)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (280:280:280) (371:371:371)) + (PORT datac (559:559:559) (552:552:552)) + (PORT datad (461:461:461) (439:439:439)) (IOPATH dataa combout (307:307:307) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -52263,13 +55340,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (698:698:698) (739:739:739)) - (PORT datac (615:615:615) (657:657:657)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (272:272:272) (364:364:364)) + (PORT datab (278:278:278) (370:370:370)) + (PORT datac (203:203:203) (273:273:273)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52279,13 +55356,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (698:698:698) (739:739:739)) - (PORT datac (615:615:615) (658:658:658)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT dataa (272:272:272) (364:364:364)) + (PORT datab (279:279:279) (371:371:371)) + (PORT datac (203:203:203) (273:273:273)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52295,12 +55372,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (770:770:770) (806:806:806)) - (PORT datab (211:211:211) (248:248:248)) - (PORT datac (158:158:158) (188:188:188)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (588:588:588) (590:590:590)) + (PORT datab (692:692:692) (737:737:737)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52313,8 +55390,8 @@ (ABSOLUTE (PORT clk (1307:1307:1307) (1321:1321:1321)) (PORT d (612:612:612) (666:666:666)) - (PORT aload (1498:1498:1498) (1543:1543:1543)) - (PORT ena (849:849:849) (851:851:851)) + (PORT aload (1508:1508:1508) (1556:1556:1556)) + (PORT ena (1187:1187:1187) (1234:1234:1234)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) (IOPATH (posedge aload) q (455:455:455) (458:458:458)) ) @@ -52346,12 +55423,232 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux38\~0) + (INSTANCE sdram_\|Mux4\~3) (DELAY (ABSOLUTE - (PORT dataa (1453:1453:1453) (1466:1466:1466)) - (PORT datab (1207:1207:1207) (1218:1218:1218)) - (PORT datad (166:166:166) (193:193:193)) + (PORT dataa (679:679:679) (730:730:730)) + (PORT datac (625:625:625) (672:672:672)) + (PORT datad (635:635:635) (688:688:688)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1046:1046:1046)) + (PORT datac (1027:1027:1027) (1096:1096:1096)) + (PORT datad (980:980:980) (1069:1069:1069)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1067:1067:1067)) + (PORT datac (933:933:933) (998:998:998)) + (PORT datad (1173:1173:1173) (1192:1192:1192)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (960:960:960)) + (PORT datab (202:202:202) (235:235:235)) + (PORT datac (1114:1114:1114) (1149:1149:1149)) + (PORT datad (1224:1224:1224) (1268:1268:1268)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (1007:1007:1007) (1075:1075:1075)) + (PORT datad (960:960:960) (1027:1027:1027)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1305:1305:1305)) + (PORT datad (1125:1125:1125) (1163:1163:1163)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1369:1369:1369)) + (PORT asdata (1422:1422:1422) (1433:1433:1433)) + (PORT ena (746:746:746) (760:760:760)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1369:1369:1369)) + (PORT asdata (945:945:945) (960:960:960)) + (PORT ena (746:746:746) (760:760:760)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (687:687:687)) + (PORT datab (1140:1140:1140) (1154:1154:1154)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1369:1369:1369)) + (PORT asdata (2922:2922:2922) (2942:2942:2942)) + (PORT ena (746:746:746) (760:760:760)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1245:1245:1245)) + (PORT datab (1007:1007:1007) (1111:1111:1111)) + (PORT datac (1025:1025:1025) (1096:1096:1096)) + (PORT datad (1464:1464:1464) (1526:1526:1526)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1054:1054:1054)) + (PORT datac (837:837:837) (829:829:829)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (899:899:899)) + (PORT datab (1373:1373:1373) (1389:1389:1389)) + (PORT datad (305:305:305) (301:301:301)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1358:1358:1358)) + (PORT datab (888:888:888) (949:949:949)) + (PORT datac (1426:1426:1426) (1462:1462:1462)) + (PORT datad (225:225:225) (285:285:285)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (961:961:961)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (304:304:304) (301:301:301)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -52364,7 +55661,7 @@ (INSTANCE sdram_\|r\.rd_pending) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) + (PORT clk (1349:1349:1349) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -52373,12 +55670,162 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2646:2646:2646) (2668:2668:2668)) + (PORT datab (229:229:229) (301:301:301)) + (PORT datac (404:404:404) (465:465:465)) + (PORT datad (635:635:635) (665:665:665)) + (IOPATH dataa combout (299:299:299) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (244:244:244)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (169:169:169) (198:198:198)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (962:962:962)) + (PORT datab (985:985:985) (1044:1044:1044)) + (PORT datac (1071:1071:1071) (1066:1066:1066)) + (PORT datad (1172:1172:1172) (1188:1188:1188)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (807:807:807)) + (PORT datab (203:203:203) (237:237:237)) + (PORT datac (933:933:933) (1000:1000:1000)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT datab (894:894:894) (932:932:932)) + (PORT datac (974:974:974) (1036:1036:1036)) + (PORT datad (1226:1226:1226) (1269:1269:1269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1032:1032:1032)) + (PORT datab (932:932:932) (976:976:976)) + (PORT datac (974:974:974) (1036:1036:1036)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (960:960:960)) + (PORT datab (986:986:986) (1044:1044:1044)) + (PORT datac (1069:1069:1069) (1063:1063:1063)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (840:840:840)) + (PORT datab (248:248:248) (322:322:322)) + (PORT datac (794:794:794) (788:788:788)) + (PORT datad (769:769:769) (761:761:761)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1360:1360:1360) (1380:1380:1380)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datac (1512:1512:1512) (1573:1573:1573)) + (PORT datad (1431:1431:1431) (1470:1470:1470)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (225:225:225) (298:298:298)) + (PORT datab (226:226:226) (298:298:298)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52387,16 +55834,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (INSTANCE sdram_\|r\.rf_counter\[8\]\~32) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (893:893:893) (931:931:931)) - (PORT datac (604:604:604) (614:614:614)) - (PORT datad (1240:1240:1240) (1289:1289:1289)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (376:376:376) (384:384:384)) + (PORT datab (626:626:626) (667:667:667)) + (PORT datac (1513:1513:1513) (1573:1573:1573)) + (PORT datad (1431:1431:1431) (1470:1470:1470)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52422,9 +55869,9 @@ (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (297:297:297)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (228:228:228) (303:303:303)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52452,7 +55899,7 @@ (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (298:298:298)) + (PORT datab (227:227:227) (300:300:300)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52482,7 +55929,7 @@ (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (306:306:306)) + (PORT dataa (231:231:231) (309:309:309)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52507,14 +55954,30 @@ (HOLD sclr (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (229:229:229) (302:302:302)) + (PORT datac (203:203:203) (274:274:274)) + (PORT datad (207:207:207) (269:269:269)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (299:299:299)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (231:231:231) (310:310:310)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52542,9 +56005,9 @@ (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (300:300:300)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52572,9 +56035,9 @@ (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52627,22 +56090,6 @@ (HOLD sclr (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) - (PORT datab (227:227:227) (299:299:299)) - (PORT datac (201:201:201) (272:272:272)) - (PORT datad (205:205:205) (267:267:267)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) @@ -52673,29 +56120,13 @@ (HOLD sclr (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (310:310:310)) - (PORT datab (230:230:230) (304:304:304)) - (PORT datac (203:203:203) (275:275:275)) - (PORT datad (206:206:206) (268:268:268)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) (DELAY (ABSOLUTE - (PORT datad (206:206:206) (266:266:266)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (230:230:230) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -52718,29 +56149,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~2) + (INSTANCE sdram_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (320:320:320) (330:330:330)) - (PORT datab (228:228:228) (300:300:300)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (205:205:205) (264:264:264)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (229:229:229) (302:302:302)) + (PORT datac (201:201:201) (272:272:272)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~8) + (INSTANCE sdram_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT datab (1278:1278:1278) (1325:1325:1325)) - (PORT datac (866:866:866) (903:903:903)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (229:229:229) (303:303:303)) + (PORT datac (204:204:204) (276:276:276)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52749,11 +56184,11 @@ (INSTANCE sdram_\|Mux37\~0) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (235:235:235)) - (PORT datab (630:630:630) (641:641:641)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (320:320:320) (330:330:330)) + (PORT datab (626:626:626) (666:666:666)) + (PORT datad (181:181:181) (203:203:203)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52775,32 +56210,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~0) + (INSTANCE sdram_\|Mux4\~1) (DELAY (ABSOLUTE - (PORT dataa (715:715:715) (769:769:769)) - (PORT datab (695:695:695) (764:764:764)) - (PORT datac (594:594:594) (658:658:658)) - (PORT datad (803:803:803) (787:787:787)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (852:852:852) (907:907:907)) + (PORT datab (926:926:926) (961:961:961)) + (PORT datac (807:807:807) (835:835:835)) + (PORT datad (916:916:916) (979:979:979)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~1) + (INSTANCE sdram_\|Mux4\~4) (DELAY (ABSOLUTE - (PORT dataa (734:734:734) (822:822:822)) - (PORT datab (951:951:951) (995:995:995)) - (PORT datac (1167:1167:1167) (1240:1240:1240)) - (PORT datad (532:532:532) (521:521:521)) + (PORT dataa (1184:1184:1184) (1243:1243:1243)) + (PORT datab (1055:1055:1055) (1123:1123:1123)) + (PORT datac (164:164:164) (199:199:199)) + (PORT datad (755:755:755) (734:734:734)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52810,12 +56245,12 @@ (INSTANCE sdram_\|Mux4\~2) (DELAY (ABSOLUTE - (PORT dataa (734:734:734) (822:822:822)) - (PORT datab (951:951:951) (995:995:995)) - (PORT datac (1167:1167:1167) (1240:1240:1240)) - (PORT datad (532:532:532) (521:521:521)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (266:266:266) (341:341:341)) + (PORT datab (256:256:256) (332:332:332)) + (PORT datac (1659:1659:1659) (1708:1708:1708)) + (PORT datad (238:238:238) (310:310:310)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52823,14 +56258,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~3) + (INSTANCE sdram_\|Mux4\~5) (DELAY (ABSOLUTE - (PORT dataa (598:598:598) (606:606:606)) - (PORT datab (274:274:274) (355:355:355)) - (PORT datad (560:560:560) (565:565:565)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (601:601:601) (599:599:599)) + (PORT datab (834:834:834) (848:848:848)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52841,7 +56276,7 @@ (INSTANCE sdram_\|r\.state\[8\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT clk (1360:1360:1360) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -52852,13 +56287,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (INSTANCE sdram_\|process_0\~4) (DELAY (ABSOLUTE - (PORT dataa (1205:1205:1205) (1279:1279:1279)) - (PORT datab (990:990:990) (1064:1064:1064)) - (PORT datac (1299:1299:1299) (1308:1308:1308)) - (PORT datad (916:916:916) (970:970:970)) + (PORT datac (211:211:211) (277:277:277)) + (PORT datad (222:222:222) (280:280:280)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (957:957:957)) + (PORT datab (1025:1025:1025) (1068:1068:1068)) + (PORT datac (906:906:906) (924:924:924)) + (PORT datad (1274:1274:1274) (1263:1263:1263)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -52868,113 +56315,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~2) + (INSTANCE sdram_\|r\.act_row\[2\]\~1) (DELAY (ABSOLUTE - (PORT datac (237:237:237) (310:310:310)) - (PORT datad (259:259:259) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (335:335:335) (361:361:361)) - (PORT datac (937:937:937) (999:999:999)) - (PORT datad (918:918:918) (973:973:973)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1233:1233:1233) (1273:1273:1273)) + (PORT datab (1437:1437:1437) (1474:1474:1474)) + (PORT datac (1065:1065:1065) (1083:1083:1083)) + (PORT datad (564:564:564) (579:579:579)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (880:880:880) (873:873:873)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT asdata (1444:1444:1444) (1449:1449:1449)) - (PORT ena (880:880:880) (873:873:873)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1115:1115:1115) (1135:1135:1135)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (880:880:880) (873:873:873)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1162:1162:1162) (1175:1175:1175)) - (PORT datab (1149:1149:1149) (1166:1166:1166)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.act_row\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT asdata (1214:1214:1214) (1246:1246:1246)) - (PORT ena (880:880:880) (873:873:873)) + (PORT clk (1350:1350:1350) (1369:1369:1369)) + (PORT asdata (2004:2004:2004) (2047:2047:2047)) + (PORT ena (746:746:746) (760:760:760)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -52988,9 +56350,9 @@ (INSTANCE sdram_\|r\.act_row\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1369:1369:1369)) - (PORT asdata (2821:2821:2821) (2904:2904:2904)) - (PORT ena (880:880:880) (873:873:873)) + (PORT clk (1350:1350:1350) (1369:1369:1369)) + (PORT asdata (1211:1211:1211) (1205:1205:1205)) + (PORT ena (746:746:746) (760:760:760)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53004,9 +56366,9 @@ (INSTANCE sdram_\|Equal7\~0) (DELAY (ABSOLUTE - (PORT dataa (2539:2539:2539) (2632:2632:2632)) - (PORT datab (930:930:930) (966:966:966)) - (PORT datad (197:197:197) (253:253:253)) + (PORT dataa (1110:1110:1110) (1123:1123:1123)) + (PORT datab (1720:1720:1720) (1768:1768:1768)) + (PORT datad (199:199:199) (256:256:256)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -53019,114 +56381,11 @@ (INSTANCE sdram_\|Equal7\~2) (DELAY (ABSOLUTE - (PORT dataa (390:390:390) (421:421:421)) - (PORT datab (229:229:229) (300:300:300)) - (PORT datac (162:162:162) (194:194:194)) - (PORT datad (168:168:168) (193:193:193)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1338:1338:1338)) - (PORT datab (956:956:956) (1006:1006:1006)) - (PORT datac (935:935:935) (997:997:997)) - (PORT datad (952:952:952) (1028:1028:1028)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1236:1236:1236)) - (PORT datac (536:536:536) (538:538:538)) - (PORT datad (317:317:317) (320:320:320)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~2) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (228:228:228)) - (PORT datab (615:615:615) (604:604:604)) - (PORT datad (1257:1257:1257) (1239:1239:1239)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.wr_pending) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~8) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1119:1119:1119)) - (PORT datad (979:979:979) (1051:1051:1051)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~9) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (463:463:463)) - (PORT datab (567:567:567) (568:568:568)) - (PORT datac (610:610:610) (660:660:660)) - (PORT datad (260:260:260) (328:328:328)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux6\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1238:1238:1238)) - (PORT datab (283:283:283) (358:358:358)) - (PORT datac (177:177:177) (208:208:208)) - (PORT datad (164:164:164) (188:188:188)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (2646:2646:2646) (2666:2666:2666)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (203:203:203) (265:265:265)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53138,11 +56397,55 @@ (INSTANCE sdram_\|Mux6\~4) (DELAY (ABSOLUTE - (PORT datab (633:633:633) (681:681:681)) - (PORT datac (536:536:536) (535:535:535)) - (PORT datad (1152:1152:1152) (1192:1192:1192)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (879:879:879) (896:896:896)) + (PORT datab (721:721:721) (777:777:777)) + (PORT datad (1014:1014:1014) (1081:1081:1081)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (926:926:926)) + (PORT datab (719:719:719) (774:774:774)) + (PORT datac (845:845:845) (873:873:873)) + (PORT datad (849:849:849) (851:851:851)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT datac (1043:1043:1043) (1119:1119:1119)) + (PORT datad (1113:1113:1113) (1157:1157:1157)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (1061:1061:1061) (1123:1123:1123)) + (PORT datac (827:827:827) (893:893:893)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53152,11 +56455,11 @@ (INSTANCE sdram_\|Mux6\~2) (DELAY (ABSOLUTE - (PORT dataa (1178:1178:1178) (1233:1233:1233)) - (PORT datac (1077:1077:1077) (1120:1120:1120)) - (PORT datad (979:979:979) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1138:1138:1138) (1191:1191:1191)) + (PORT datac (1041:1041:1041) (1113:1113:1113)) + (PORT datad (1027:1027:1027) (1088:1088:1088)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53166,10 +56469,10 @@ (INSTANCE sdram_\|Mux6\~5) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (893:893:893) (940:940:940)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (901:901:901) (955:955:955)) + (PORT datad (161:161:161) (183:183:183)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -53179,13 +56482,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~3) + (INSTANCE sdram_\|process_0\~2) (DELAY (ABSOLUTE - (PORT dataa (834:834:834) (871:871:871)) - (PORT datac (740:740:740) (736:736:736)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (720:720:720) (773:773:773)) + (PORT datad (849:849:849) (851:851:851)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -53194,10 +56497,10 @@ (INSTANCE sdram_\|Mux6\~0) (DELAY (ABSOLUTE - (PORT dataa (262:262:262) (346:346:346)) - (PORT datab (667:667:667) (726:726:726)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (688:688:688) (726:726:726)) + (PORT dataa (866:866:866) (929:929:929)) + (PORT datab (1071:1071:1071) (1146:1146:1146)) + (PORT datac (176:176:176) (215:215:215)) + (PORT datad (1112:1112:1112) (1157:1157:1157)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -53210,12 +56513,12 @@ (INSTANCE sdram_\|Mux6\~1) (DELAY (ABSOLUTE - (PORT dataa (256:256:256) (338:338:338)) - (PORT datab (265:265:265) (353:353:353)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (688:688:688) (727:727:727)) + (PORT dataa (689:689:689) (735:735:735)) + (PORT datab (1422:1422:1422) (1482:1482:1482)) + (PORT datac (572:572:572) (592:592:592)) + (PORT datad (635:635:635) (692:692:692)) (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53226,10 +56529,10 @@ (INSTANCE sdram_\|Mux6\~6) (DELAY (ABSOLUTE - (PORT datab (273:273:273) (356:356:356)) - (PORT datac (563:563:563) (566:566:566)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (264:264:264) (348:348:348)) + (PORT datac (856:856:856) (873:873:873)) + (PORT datad (547:547:547) (549:549:549)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53240,7 +56543,7 @@ (INSTANCE sdram_\|r\.state\[6\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT clk (1360:1360:1360) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53251,160 +56554,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~6) + (INSTANCE sdram_\|Mux5\~7) (DELAY (ABSOLUTE - (PORT dataa (1206:1206:1206) (1283:1283:1283)) - (PORT datac (935:935:935) (999:999:999)) - (PORT datad (913:913:913) (969:969:969)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~2) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (558:558:558)) - (PORT datab (1346:1346:1346) (1353:1353:1353)) - (PORT datac (611:611:611) (661:661:661)) - (PORT datad (976:976:976) (1050:1050:1050)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~3) - (DELAY - (ABSOLUTE - (PORT datab (759:759:759) (830:830:830)) - (PORT datac (716:716:716) (791:791:791)) - (PORT datad (816:816:816) (826:826:826)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~3) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (897:897:897)) - (PORT datab (264:264:264) (349:349:349)) - (PORT datad (689:689:689) (723:723:723)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~4) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (223:223:223)) - (PORT datab (263:263:263) (346:346:346)) - (PORT datac (808:808:808) (841:841:841)) - (PORT datad (246:246:246) (317:317:317)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~5) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (844:844:844)) - (PORT datab (266:266:266) (354:354:354)) - (PORT datac (637:637:637) (697:697:697)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~0) - (DELAY - (ABSOLUTE - (PORT datab (900:900:900) (968:968:968)) - (PORT datac (1152:1152:1152) (1213:1213:1213)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~7) - (DELAY - (ABSOLUTE - (PORT datac (1161:1161:1161) (1233:1233:1233)) - (PORT datad (908:908:908) (954:954:954)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~10) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (848:848:848)) - (PORT datab (903:903:903) (973:973:973)) - (PORT datac (1152:1152:1152) (1217:1217:1217)) - (PORT datad (624:624:624) (692:692:692)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (401:401:401)) - (PORT datab (356:356:356) (367:367:367)) - (PORT datac (943:943:943) (999:999:999)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~6) - (DELAY - (ABSOLUTE - (PORT dataa (746:746:746) (734:734:734)) - (PORT datab (320:320:320) (328:328:328)) - (PORT datac (233:233:233) (314:314:314)) - (PORT datad (786:786:786) (770:770:770)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (922:922:922) (971:971:971)) + (PORT datab (893:893:893) (936:936:936)) + (PORT datac (1146:1146:1146) (1191:1191:1191)) + (PORT datad (1170:1170:1170) (1195:1195:1195)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53412,28 +56569,30 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.state\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1006:1006:1006) (1063:1063:1063)) + (PORT datab (985:985:985) (1042:1042:1042)) + (PORT datac (871:871:871) (921:921:921)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux5\~2) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (360:360:360)) - (PORT datab (1181:1181:1181) (1240:1240:1240)) - (PORT datac (872:872:872) (940:940:940)) - (PORT datad (321:321:321) (331:331:331)) + (PORT dataa (1198:1198:1198) (1223:1223:1223)) + (PORT datab (1015:1015:1015) (1082:1082:1082)) + (PORT datac (180:180:180) (214:214:214)) + (PORT datad (335:335:335) (336:336:336)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -53446,13 +56605,13 @@ (INSTANCE sdram_\|Mux5\~10) (DELAY (ABSOLUTE - (PORT dataa (718:718:718) (773:773:773)) - (PORT datab (695:695:695) (765:765:765)) - (PORT datac (699:699:699) (778:778:778)) - (PORT datad (623:623:623) (686:686:686)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1189:1189:1189) (1221:1221:1221)) + (PORT datab (1011:1011:1011) (1080:1080:1080)) + (PORT datac (897:897:897) (933:933:933)) + (PORT datad (920:920:920) (977:977:977)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53462,13 +56621,13 @@ (INSTANCE sdram_\|Mux5\~3) (DELAY (ABSOLUTE - (PORT dataa (730:730:730) (817:817:817)) - (PORT datab (946:946:946) (993:993:993)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (1149:1149:1149) (1197:1197:1197)) + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (976:976:976) (1051:1051:1051)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53478,45 +56637,13 @@ (INSTANCE sdram_\|Mux5\~4) (DELAY (ABSOLUTE - (PORT dataa (327:327:327) (344:344:344)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (1161:1161:1161) (1231:1231:1231)) - (PORT datad (648:648:648) (710:710:710)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~7) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (345:345:345)) - (PORT datab (726:726:726) (761:761:761)) - (PORT datac (808:808:808) (843:843:843)) - (PORT datad (819:819:819) (858:858:858)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~8) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (339:339:339)) - (PORT datab (264:264:264) (351:351:351)) - (PORT datac (636:636:636) (695:695:695)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1235:1235:1235) (1274:1274:1274)) + (PORT datab (985:985:985) (1067:1067:1067)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53526,12 +56653,12 @@ (INSTANCE sdram_\|Mux5\~5) (DELAY (ABSOLUTE - (PORT dataa (866:866:866) (901:901:901)) - (PORT datab (669:669:669) (728:728:728)) - (PORT datac (743:743:743) (740:740:740)) - (PORT datad (246:246:246) (316:316:316)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (870:870:870) (903:903:903)) + (PORT datab (639:639:639) (699:699:699)) + (PORT datac (925:925:925) (1002:1002:1002)) + (PORT datad (853:853:853) (857:857:857)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53542,13 +56669,13 @@ (INSTANCE sdram_\|Mux5\~6) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (452:452:452)) - (PORT datab (207:207:207) (244:244:244)) - (PORT datac (580:580:580) (598:598:598)) - (PORT datad (837:837:837) (851:851:851)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datac (173:173:173) (212:212:212)) + (PORT datad (1026:1026:1026) (1088:1088:1088)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53558,13 +56685,13 @@ (INSTANCE sdram_\|Mux5\~9) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (338:338:338)) - (PORT datab (614:614:614) (625:625:625)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1099:1099:1099) (1079:1079:1079)) + (PORT datab (254:254:254) (331:331:331)) + (PORT datac (795:795:795) (790:790:790)) + (PORT datad (800:800:800) (801:801:801)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53574,7 +56701,7 @@ (INSTANCE sdram_\|r\.state\[7\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT clk (1360:1360:1360) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53588,64 +56715,98 @@ (INSTANCE sdram_\|n\~2) (DELAY (ABSOLUTE - (PORT datab (935:935:935) (987:987:987)) - (PORT datac (874:874:874) (944:944:944)) - (PORT datad (918:918:918) (956:956:956)) + (PORT datab (923:923:923) (962:962:962)) + (PORT datac (824:824:824) (877:877:877)) + (PORT datad (916:916:916) (980:980:980)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (618:618:618)) + (PORT datab (831:831:831) (861:861:861)) + (PORT datac (862:862:862) (881:881:881)) + (PORT datad (1404:1404:1404) (1416:1416:1416)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (898:898:898) (915:915:915)) + (PORT datac (863:863:863) (880:880:880)) + (PORT datad (1403:1403:1403) (1416:1416:1416)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (912:912:912)) + (PORT datab (747:747:747) (800:800:800)) + (PORT datac (805:805:805) (836:836:836)) + (PORT datad (687:687:687) (753:753:753)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (792:792:792)) + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (862:862:862) (878:878:878)) + (PORT datad (572:572:572) (580:580:580)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux8\~3) (DELAY (ABSOLUTE - (PORT dataa (331:331:331) (356:356:356)) - (PORT datab (1150:1150:1150) (1215:1215:1215)) - (PORT datac (1454:1454:1454) (1502:1502:1502)) - (PORT datad (1459:1459:1459) (1515:1515:1515)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (715:715:715) (792:792:792)) + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (797:797:797) (797:797:797)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1351:1351:1351)) - (PORT datab (1374:1374:1374) (1411:1411:1411)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (1158:1158:1158) (1203:1203:1203)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~10) - (DELAY - (ABSOLUTE - (PORT datab (188:188:188) (222:222:222)) - (PORT datac (1077:1077:1077) (1120:1120:1120)) - (PORT datad (979:979:979) (1051:1051:1051)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (INSTANCE sdram_\|r\.init_counter\[0\]\~44) (DELAY (ABSOLUTE (IOPATH datac combout (312:312:312) (325:325:325)) @@ -53657,7 +56818,7 @@ (INSTANCE sdram_\|r\.init_counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1382:1382:1382)) + (PORT clk (1347:1347:1347) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53668,20 +56829,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~1) + (INSTANCE sdram_\|r\.init_counter\[1\]\~15) (DELAY (ABSOLUTE - (PORT datab (679:679:679) (727:727:727)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (382:382:382) (427:427:427)) + (IOPATH dataa cout (376:376:376) (275:275:275)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~2) + (INSTANCE sdram_\|r\.init_counter\[1\]\~16) (DELAY (ABSOLUTE - (PORT datab (256:256:256) (326:326:326)) + (PORT datab (239:239:239) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53695,7 +56856,7 @@ (INSTANCE sdram_\|r\.init_counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53706,7 +56867,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~4) + (INSTANCE sdram_\|r\.init_counter\[2\]\~18) (DELAY (ABSOLUTE (PORT dataa (240:240:240) (313:313:313)) @@ -53723,7 +56884,7 @@ (INSTANCE sdram_\|r\.init_counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53734,34 +56895,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~6) + (INSTANCE sdram_\|r\.init_counter\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (445:445:445)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (240:240:240) (308:308:308)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (324:324:324) (326:326:326)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.init_counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53772,7 +56923,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~8) + (INSTANCE sdram_\|r\.init_counter\[4\]\~22) (DELAY (ABSOLUTE (PORT dataa (241:241:241) (315:315:315)) @@ -53789,7 +56940,7 @@ (INSTANCE sdram_\|r\.init_counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53800,7 +56951,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~10) + (INSTANCE sdram_\|r\.init_counter\[5\]\~24) (DELAY (ABSOLUTE (PORT dataa (241:241:241) (315:315:315)) @@ -53817,7 +56968,7 @@ (INSTANCE sdram_\|r\.init_counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53828,7 +56979,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~12) + (INSTANCE sdram_\|r\.init_counter\[6\]\~26) (DELAY (ABSOLUTE (PORT datab (240:240:240) (310:310:310)) @@ -53845,7 +56996,7 @@ (INSTANCE sdram_\|r\.init_counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53856,10 +57007,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~14) + (INSTANCE sdram_\|r\.init_counter\[7\]\~28) (DELAY (ABSOLUTE - (PORT datab (258:258:258) (329:329:329)) + (PORT datab (241:241:241) (310:310:310)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53873,7 +57024,7 @@ (INSTANCE sdram_\|r\.init_counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53884,7 +57035,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~16) + (INSTANCE sdram_\|r\.init_counter\[8\]\~30) (DELAY (ABSOLUTE (PORT datab (240:240:240) (310:310:310)) @@ -53901,7 +57052,7 @@ (INSTANCE sdram_\|r\.init_counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53912,10 +57063,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~18) + (INSTANCE sdram_\|r\.init_counter\[9\]\~32) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) + (PORT datab (229:229:229) (300:300:300)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53929,7 +57080,7 @@ (INSTANCE sdram_\|r\.init_counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53940,10 +57091,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~20) + (INSTANCE sdram_\|r\.init_counter\[10\]\~34) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (314:314:314)) + (PORT dataa (229:229:229) (304:304:304)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53957,7 +57108,7 @@ (INSTANCE sdram_\|r\.init_counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -53968,37 +57119,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (437:437:437)) - (PORT datab (417:417:417) (452:452:452)) - (PORT datac (361:361:361) (402:402:402)) - (PORT datad (380:380:380) (416:416:416)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (419:419:419) (451:451:451)) - (PORT datac (388:388:388) (423:423:423)) - (PORT datad (220:220:220) (281:281:281)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~22) + (INSTANCE sdram_\|r\.init_counter\[11\]\~36) (DELAY (ABSOLUTE (PORT datab (227:227:227) (299:299:299)) @@ -54015,7 +57136,7 @@ (INSTANCE sdram_\|r\.init_counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54026,10 +57147,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~24) + (INSTANCE sdram_\|r\.init_counter\[12\]\~38) (DELAY (ABSOLUTE - (PORT dataa (228:228:228) (303:303:303)) + (PORT dataa (241:241:241) (313:313:313)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54043,7 +57164,7 @@ (INSTANCE sdram_\|r\.init_counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54054,10 +57175,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~26) + (INSTANCE sdram_\|r\.init_counter\[13\]\~40) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (298:298:298)) + (PORT datab (239:239:239) (308:308:308)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54071,7 +57192,7 @@ (INSTANCE sdram_\|r\.init_counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54082,10 +57203,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~28) + (INSTANCE sdram_\|r\.init_counter\[14\]\~42) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) + (PORT dataa (241:241:241) (315:315:315)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -54096,7 +57217,7 @@ (INSTANCE sdram_\|r\.init_counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT clk (1347:1347:1347) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54105,15 +57226,45 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (411:411:411) (450:450:450)) + (PORT datac (379:379:379) (420:420:420)) + (PORT datad (355:355:355) (390:390:390)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|process_0\~5) (DELAY (ABSOLUTE - (PORT dataa (232:232:232) (309:309:309)) + (PORT dataa (381:381:381) (427:427:427)) (PORT datab (228:228:228) (301:301:301)) - (PORT datac (204:204:204) (275:275:275)) - (PORT datad (205:205:205) (267:267:267)) + (PORT datac (203:203:203) (275:275:275)) + (PORT datad (204:204:204) (266:266:266)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (431:431:431)) + (PORT datab (552:552:552) (577:577:577)) + (PORT datac (357:357:357) (397:397:397)) + (PORT datad (361:361:361) (400:400:400)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -54126,59 +57277,13 @@ (INSTANCE sdram_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (330:330:330) (336:336:336)) - (PORT datad (364:364:364) (397:397:397)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~11) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (771:771:771)) - (PORT datab (275:275:275) (356:356:356)) - (PORT datad (686:686:686) (746:746:746)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~12) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (541:541:541)) - (PORT datab (604:604:604) (631:631:631)) - (PORT datac (1456:1456:1456) (1516:1516:1516)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1388:1388:1388) (1442:1442:1442)) - (PORT datab (1272:1272:1272) (1341:1341:1341)) - (PORT datac (525:525:525) (514:514:514)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (307:307:307) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (388:388:388) (434:434:434)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (312:312:312) (321:321:321)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54188,12 +57293,28 @@ (INSTANCE sdram_\|Mux8\~0) (DELAY (ABSOLUTE - (PORT dataa (1177:1177:1177) (1232:1232:1232)) - (PORT datab (1348:1348:1348) (1355:1355:1355)) - (PORT datac (154:154:154) (185:185:185)) - (PORT datad (799:799:799) (808:808:808)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (260:260:260) (341:341:341)) + (PORT datab (390:390:390) (446:446:446)) + (PORT datac (375:375:375) (419:419:419)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (806:806:806) (838:838:838)) + (PORT datad (551:551:551) (557:557:557)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54201,28 +57322,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~1) + (INSTANCE sdram_\|Mux8\~5) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1201:1201:1201)) - (PORT datab (894:894:894) (940:940:940)) - (PORT datac (892:892:892) (941:941:941)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~2) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (707:707:707)) - (PORT datac (1039:1039:1039) (1035:1035:1035)) - (PORT datad (806:806:806) (815:815:815)) + (PORT dataa (262:262:262) (346:346:346)) + (PORT datac (566:566:566) (563:563:563)) + (PORT datad (534:534:534) (528:528:528)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54234,7 +57339,7 @@ (INSTANCE sdram_\|r\.state\[4\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT clk (1360:1360:1360) (1380:1380:1380)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54248,12 +57353,10 @@ (INSTANCE sdram_\|Mux72\~0) (DELAY (ABSOLUTE - (PORT datab (2824:2824:2824) (2811:2811:2811)) - (PORT datac (845:845:845) (884:884:884)) - (PORT datad (254:254:254) (322:322:322)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (1581:1581:1581) (1601:1601:1601)) + (PORT datac (906:906:906) (978:978:978)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54262,12 +57365,12 @@ (INSTANCE sdram_\|Mux72\~1) (DELAY (ABSOLUTE - (PORT dataa (925:925:925) (955:955:955)) - (PORT datab (2825:2825:2825) (2812:2812:2812)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (337:337:337) (335:335:335)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (692:692:692) (728:728:728)) + (PORT datab (290:290:290) (378:378:378)) + (PORT datac (297:297:297) (310:310:310)) + (PORT datad (583:583:583) (600:600:600)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54278,8 +57381,8 @@ (INSTANCE sdram_\|Mux84\~0) (DELAY (ABSOLUTE - (PORT datac (229:229:229) (306:306:306)) - (PORT datad (689:689:689) (727:727:727)) + (PORT datac (257:257:257) (343:343:343)) + (PORT datad (226:226:226) (292:292:292)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54290,13 +57393,13 @@ (INSTANCE sdram_\|Mux84\~1) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (452:452:452)) - (PORT datab (272:272:272) (356:356:356)) - (PORT datac (236:236:236) (316:316:316)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (264:264:264) (349:349:349)) + (PORT datab (245:245:245) (316:316:316)) + (PORT datac (237:237:237) (309:309:309)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54306,11 +57409,9 @@ (INSTANCE sdram_\|Mux3\~0) (DELAY (ABSOLUTE - (PORT datab (2828:2828:2828) (2818:2818:2818)) - (PORT datac (1064:1064:1064) (1082:1082:1082)) - (PORT datad (255:255:255) (325:325:325)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1008:1008:1008) (1096:1096:1096)) + (PORT datad (1557:1557:1557) (1566:1566:1566)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54320,13 +57421,13 @@ (INSTANCE sdram_\|Mux3\~1) (DELAY (ABSOLUTE - (PORT dataa (925:925:925) (961:961:961)) - (PORT datab (2828:2828:2828) (2820:2820:2820)) - (PORT datac (291:291:291) (294:294:294)) - (PORT datad (323:323:323) (324:324:324)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (286:286:286) (373:373:373)) + (PORT datac (657:657:657) (693:693:693)) + (PORT datad (321:321:321) (319:319:319)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54336,12 +57437,10 @@ (INSTANCE sdram_\|Mux2\~0) (DELAY (ABSOLUTE - (PORT datab (2826:2826:2826) (2813:2813:2813)) - (PORT datac (1044:1044:1044) (1072:1072:1072)) - (PORT datad (258:258:258) (328:328:328)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (1383:1383:1383) (1408:1408:1408)) + (PORT datac (790:790:790) (873:873:873)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54350,13 +57449,13 @@ (INSTANCE sdram_\|Mux2\~1) (DELAY (ABSOLUTE - (PORT dataa (927:927:927) (962:962:962)) - (PORT datab (2833:2833:2833) (2819:2819:2819)) - (PORT datac (320:320:320) (331:331:331)) - (PORT datad (583:583:583) (594:594:594)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (563:563:563) (568:568:568)) + (PORT datab (290:290:290) (379:379:379)) + (PORT datac (581:581:581) (599:599:599)) + (PORT datad (1322:1322:1322) (1300:1300:1300)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54366,11 +57465,9 @@ (INSTANCE sdram_\|Mux1\~0) (DELAY (ABSOLUTE - (PORT datab (2832:2832:2832) (2818:2818:2818)) - (PORT datac (1041:1041:1041) (1073:1073:1073)) - (PORT datad (253:253:253) (320:320:320)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datac (1638:1638:1638) (1674:1674:1674)) + (PORT datad (604:604:604) (644:644:644)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54380,13 +57477,13 @@ (INSTANCE sdram_\|Mux1\~1) (DELAY (ABSOLUTE - (PORT dataa (924:924:924) (961:961:961)) - (PORT datab (2819:2819:2819) (2818:2818:2818)) - (PORT datac (567:567:567) (547:547:547)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (710:710:710) (769:769:769)) + (PORT datab (1075:1075:1075) (1049:1049:1049)) + (PORT datac (1275:1275:1275) (1246:1246:1246)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54396,11 +57493,9 @@ (INSTANCE sdram_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT datab (2821:2821:2821) (2820:2820:2820)) - (PORT datac (903:903:903) (941:941:941)) - (PORT datad (257:257:257) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datac (1638:1638:1638) (1674:1674:1674)) + (PORT datad (366:366:366) (410:410:410)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54410,13 +57505,13 @@ (INSTANCE sdram_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (927:927:927) (962:962:962)) - (PORT datab (2831:2831:2831) (2818:2818:2818)) - (PORT datac (295:295:295) (304:304:304)) - (PORT datad (568:568:568) (579:579:579)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1028:1028:1028) (1019:1019:1019)) + (PORT datab (288:288:288) (376:376:376)) + (PORT datac (655:655:655) (696:696:696)) + (PORT datad (600:600:600) (582:582:582)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54426,26 +57521,10 @@ (INSTANCE sdram_\|Mux73\~0) (DELAY (ABSOLUTE - (PORT datab (2823:2823:2823) (2814:2814:2814)) - (PORT datac (1378:1378:1378) (1423:1423:1423)) - (PORT datad (255:255:255) (322:322:322)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux73\~1) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (960:960:960)) - (PORT datab (2820:2820:2820) (2818:2818:2818)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (570:570:570) (583:583:583)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT datab (1012:1012:1012) (995:995:995)) + (PORT datac (773:773:773) (781:781:781)) + (PORT datad (183:183:183) (206:206:206)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54456,11 +57535,9 @@ (INSTANCE sdram_\|Mux74\~0) (DELAY (ABSOLUTE - (PORT datab (2827:2827:2827) (2816:2816:2816)) - (PORT datac (855:855:855) (891:891:891)) - (PORT datad (253:253:253) (321:321:321)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datac (830:830:830) (845:845:845)) + (PORT datad (217:217:217) (274:274:274)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54470,13 +57547,13 @@ (INSTANCE sdram_\|Mux74\~1) (DELAY (ABSOLUTE - (PORT dataa (925:925:925) (955:955:955)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (2789:2789:2789) (2780:2780:2780)) - (PORT datad (586:586:586) (607:607:607)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (693:693:693) (729:729:729)) + (PORT datab (805:805:805) (797:797:797)) + (PORT datac (260:260:260) (347:347:347)) + (PORT datad (547:547:547) (562:562:562)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54486,9 +57563,23 @@ (INSTANCE sdram_\|Mux75\~0) (DELAY (ABSOLUTE - (PORT datac (1406:1406:1406) (1471:1471:1471)) - (PORT datad (1269:1269:1269) (1252:1252:1252)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (690:690:690) (749:749:749)) + (PORT datab (781:781:781) (778:778:778)) + (PORT datad (184:184:184) (207:207:207)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE LED\~0) + (DELAY + (ABSOLUTE + (PORT datac (1209:1209:1209) (1206:1206:1206)) + (PORT datad (1399:1399:1399) (1402:1402:1402)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54507,9 +57598,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1702:1702:1702) (1723:1723:1723)) + (PORT clk (1678:1678:1678) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT clrn (1388:1388:1388) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54524,7 +57615,7 @@ (DELAY (ABSOLUTE (PORT clk (1332:1332:1332) (1349:1349:1349)) - (PORT d (867:867:867) (919:919:919)) + (PORT d (843:843:843) (904:904:904)) (PORT clrn (1555:1555:1555) (1589:1589:1589)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) @@ -54535,13 +57626,29 @@ (HOLD d (posedge clk) (86:86:86)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1358:1358:1358)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT datab (638:638:638) (665:665:665)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (936:936:936) (980:980:980)) + (IOPATH dataa cout (376:376:376) (275:275:275)) ) ) ) @@ -54550,7 +57657,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (300:300:300)) + (PORT datab (229:229:229) (300:300:300)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54564,10 +57671,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (189:189:189) (217:217:217)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (217:217:217) (261:261:261)) + (PORT datac (158:158:158) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54576,9 +57683,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1697:1697:1697)) + (PORT clk (1679:1679:1679) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54592,9 +57699,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (371:371:371) (423:423:423)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (401:401:401) (438:438:438)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54606,8 +57713,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datac (296:296:296) (302:302:302)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (306:306:306) (310:310:310)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54616,9 +57723,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1698:1698:1698)) + (PORT clk (1680:1680:1680) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54632,9 +57739,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (445:445:445)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (400:400:400) (437:437:437)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54646,7 +57753,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datad (522:522:522) (517:517:517)) + (PORT datad (304:304:304) (309:309:309)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54656,9 +57763,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1702:1702:1702) (1723:1723:1723)) + (PORT clk (1680:1680:1680) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54672,7 +57779,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (302:302:302)) + (PORT datab (228:228:228) (300:300:300)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54686,10 +57793,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (191:191:191) (216:216:216)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (218:218:218) (269:269:269)) + (PORT datac (156:156:156) (185:185:185)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54698,9 +57805,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1697:1697:1697)) + (PORT clk (1679:1679:1679) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54714,7 +57821,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (445:445:445)) + (PORT dataa (371:371:371) (423:423:423)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54728,8 +57835,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (293:293:293) (299:299:299)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (298:298:298) (304:304:304)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -54738,9 +57845,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1698:1698:1698)) + (PORT clk (1680:1680:1680) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54754,13 +57861,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (423:423:423)) - (PORT datab (227:227:227) (300:300:300)) - (PORT datac (359:359:359) (407:407:407)) - (PORT datad (362:362:362) (401:401:401)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (374:374:374) (425:425:425)) + (PORT datab (403:403:403) (438:438:438)) + (PORT datac (202:202:202) (274:274:274)) + (PORT datad (359:359:359) (399:399:399)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54770,7 +57877,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (399:399:399) (435:435:435)) + (PORT datab (399:399:399) (436:436:436)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54784,7 +57891,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (306:306:306) (314:314:314)) + (PORT datad (290:290:290) (297:297:297)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54794,9 +57901,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1698:1698:1698)) + (PORT clk (1680:1680:1680) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54810,9 +57917,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (368:368:368) (420:420:420)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (368:368:368) (417:417:417)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54824,8 +57931,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datac (313:313:313) (322:322:322)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (307:307:307) (315:315:315)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54834,9 +57941,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1698:1698:1698)) + (PORT clk (1680:1680:1680) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54850,7 +57957,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) + (PORT datab (230:230:230) (302:302:302)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54864,10 +57971,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (184:184:184) (217:217:217)) - (PORT datad (192:192:192) (217:217:217)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (221:221:221) (268:268:268)) + (PORT datac (158:158:158) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54876,9 +57983,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1677:1677:1677) (1697:1697:1697)) + (PORT clk (1679:1679:1679) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54892,7 +57999,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (352:352:352) (394:394:394)) + (PORT datad (366:366:366) (403:403:403)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -54903,8 +58010,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datac (322:322:322) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (309:309:309) (316:316:316)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54913,9 +58020,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1676:1676:1676) (1696:1696:1696)) + (PORT clk (1680:1680:1680) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1385:1385:1385) (1364:1364:1364)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -54929,13 +58036,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (421:421:421)) - (PORT datab (393:393:393) (430:430:430)) - (PORT datac (199:199:199) (270:270:270)) - (PORT datad (364:364:364) (400:400:400)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (407:407:407) (441:441:441)) + (PORT datab (367:367:367) (412:412:412)) + (PORT datac (369:369:369) (406:406:406)) + (PORT datad (201:201:201) (262:262:262)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54945,41 +58052,24 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (225:225:225) (297:297:297)) - (PORT datac (294:294:294) (300:300:300)) - (PORT datad (603:603:603) (632:632:632)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (184:184:184) (218:218:218)) + (PORT datac (898:898:898) (944:944:944)) + (PORT datad (202:202:202) (262:262:262)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT asdata (484:484:484) (510:510:510)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (892:892:892) (897:897:897)) - (PORT datad (211:211:211) (271:271:271)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datad (1095:1095:1095) (1112:1112:1112)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54990,7 +58080,7 @@ (DELAY (ABSOLUTE (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (1272:1272:1272) (1289:1289:1289)) + (PORT d (1434:1434:1434) (1497:1497:1497)) (PORT clrn (1553:1553:1553) (1587:1587:1587)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) @@ -55007,7 +58097,7 @@ (DELAY (ABSOLUTE (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (1275:1275:1275) (1288:1288:1288)) + (PORT d (1772:1772:1772) (1796:1796:1796)) (PORT clrn (1554:1554:1554) (1588:1588:1588)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) @@ -55018,37 +58108,6 @@ (HOLD d (posedge clk) (86:86:86)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (404:404:404)) - (PORT datab (894:894:894) (902:902:902)) - (PORT datad (197:197:197) (228:228:228)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) @@ -55062,22 +58121,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT datac (175:175:175) (206:206:206)) + (PORT datab (679:679:679) (723:723:723)) + (IOPATH datab cout (385:385:385) (280:280:280)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (305:305:305)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (982:982:982)) + (PORT datab (1119:1119:1119) (1142:1142:1142)) + (PORT datac (159:159:159) (190:190:190)) + (PORT datad (641:641:641) (686:686:686)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT clrn (1379:1379:1379) (1358:1358:1358)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55088,15 +58177,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) + (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (850:850:850) (855:855:855)) - (PORT datab (248:248:248) (329:329:329)) - (PORT datac (184:184:184) (219:219:219)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (608:608:608) (663:663:663)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (640:640:640)) + (PORT datab (887:887:887) (930:930:930)) + (PORT datac (190:190:190) (236:236:236)) + (PORT datad (198:198:198) (238:238:238)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (707:707:707)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (804:804:804)) + (PORT datab (897:897:897) (942:942:942)) + (PORT datac (225:225:225) (298:298:298)) + (PORT datad (572:572:572) (584:584:584)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (590:590:590) (634:634:634)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (582:582:582)) + (PORT datab (886:886:886) (933:933:933)) + (PORT datac (187:187:187) (235:235:235)) + (PORT datad (195:195:195) (235:235:235)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (710:710:710)) + (PORT datab (603:603:603) (660:660:660)) + (PORT datac (200:200:200) (272:272:272)) + (PORT datad (586:586:586) (631:631:631)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (276:276:276)) + (PORT datab (887:887:887) (929:929:929)) + (PORT datad (567:567:567) (577:577:577)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (324:324:324)) + (PORT datad (571:571:571) (579:579:579)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (271:271:271)) + (PORT datab (894:894:894) (939:939:939)) + (PORT datac (185:185:185) (230:230:230)) + (PORT datad (214:214:214) (275:275:275)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -55105,12 +58406,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1337:1337:1337) (1355:1355:1355)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (511:511:511) (549:549:549)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT sload (1375:1375:1375) (1412:1412:1412)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (912:912:912) (937:937:937)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (PORT sload (1417:1417:1417) (1492:1492:1492)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55141,12 +58442,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1337:1337:1337) (1355:1355:1355)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (511:511:511) (550:550:550)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT sload (1375:1375:1375) (1412:1412:1412)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (913:913:913) (939:939:939)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (PORT sload (1417:1417:1417) (1492:1492:1492)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55160,10 +58461,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~10) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (302:302:302)) + (PORT datab (241:241:241) (311:311:311)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -55177,12 +58478,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1337:1337:1337) (1355:1355:1355)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (509:509:509) (545:545:545)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT sload (1375:1375:1375) (1412:1412:1412)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (914:914:914) (939:939:939)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (PORT sload (1417:1417:1417) (1492:1492:1492)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55196,10 +58497,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~12) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (311:311:311)) + (PORT datab (228:228:228) (302:302:302)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -55213,12 +58514,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1337:1337:1337) (1355:1355:1355)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (509:509:509) (546:546:546)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT sload (1375:1375:1375) (1412:1412:1412)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (914:914:914) (940:940:940)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (PORT sload (1417:1417:1417) (1492:1492:1492)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55232,10 +58533,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~14) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (323:323:323)) + (PORT dataa (236:236:236) (314:314:314)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -55246,12 +58547,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT clk (1337:1337:1337) (1355:1355:1355)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (510:510:510) (548:548:548)) - (PORT clrn (1391:1391:1391) (1369:1369:1369)) - (PORT sload (1375:1375:1375) (1412:1412:1412)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (914:914:914) (940:940:940)) + (PORT clrn (1383:1383:1383) (1366:1366:1366)) + (PORT sload (1417:1417:1417) (1492:1492:1492)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55268,10 +58569,10 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (422:422:422)) - (PORT datab (227:227:227) (299:299:299)) - (PORT datac (200:200:200) (270:270:270)) - (PORT datad (203:203:203) (264:264:264)) + (PORT dataa (380:380:380) (427:427:427)) + (PORT datab (228:228:228) (301:301:301)) + (PORT datac (201:201:201) (273:273:273)) + (PORT datad (204:204:204) (266:266:266)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -55281,265 +58582,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) + (INSTANCE ula_\|i2s_intf_\|LessThan0\~1) (DELAY (ABSOLUTE - (PORT dataa (356:356:356) (411:411:411)) - (PORT datab (514:514:514) (502:502:502)) - (PORT datac (214:214:214) (292:292:292)) - (PORT datad (172:172:172) (199:199:199)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT datac (209:209:209) (285:285:285)) + (PORT datad (167:167:167) (194:194:194)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (452:452:452)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (302:302:302)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (449:449:449)) - (PORT datab (896:896:896) (902:902:902)) - (PORT datac (295:295:295) (298:298:298)) - (PORT datad (196:196:196) (227:227:227)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT datab (534:534:534) (565:565:565)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (405:405:405)) - (PORT datab (892:892:892) (904:904:904)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (306:306:306) (314:314:314)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT datab (228:228:228) (298:298:298)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (453:453:453)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (815:815:815) (808:808:808)) - (PORT datad (199:199:199) (230:230:230)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (270:270:270)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (403:403:403)) - (PORT datab (894:894:894) (902:902:902)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (308:308:308) (315:315:315)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (302:302:302)) - (PORT datab (226:226:226) (298:298:298)) - (PORT datac (201:201:201) (270:270:270)) - (PORT datad (511:511:511) (533:533:533)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (225:225:225) (265:265:265)) - (PORT datad (368:368:368) (413:413:413)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datac (216:216:216) (295:295:295)) - (PORT datad (223:223:223) (297:297:297)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (505:505:505)) - (PORT datab (246:246:246) (327:327:327)) - (PORT datac (822:822:822) (824:824:824)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (222:222:222) (275:275:275)) + (PORT datab (217:217:217) (264:264:264)) + (PORT datad (861:861:861) (893:893:893)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55550,7 +58613,7 @@ (DELAY (ABSOLUTE (PORT clk (1330:1330:1330) (1347:1347:1347)) - (PORT d (1369:1369:1369) (1409:1409:1409)) + (PORT d (1902:1902:1902) (1967:1967:1967)) (PORT clrn (1552:1552:1552) (1587:1587:1587)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) @@ -55566,7 +58629,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (862:862:862) (880:880:880)) + (PORT datad (596:596:596) (615:615:615)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55576,12 +58639,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT datab (1728:1728:1728) (1814:1814:1814)) - (PORT datac (2848:2848:2848) (2969:2969:2969)) - (PORT datad (2391:2391:2391) (2369:2369:2369)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (1154:1154:1154) (1220:1220:1220)) + (PORT datab (1070:1070:1070) (1062:1062:1062)) + (PORT datac (1048:1048:1048) (1043:1043:1043)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -55590,13 +58653,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (2375:2375:2375) (2516:2516:2516)) - (PORT datab (1137:1137:1137) (1186:1186:1186)) - (PORT datac (1944:1944:1944) (1968:1968:1968)) - (PORT datad (1020:1020:1020) (970:970:970)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1111:1111:1111) (1148:1148:1148)) + (PORT datab (1565:1565:1565) (1582:1582:1582)) + (PORT datac (1124:1124:1124) (1184:1184:1184)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55606,9 +58669,9 @@ (INSTANCE ula_\|pcm_outl\[13\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (910:910:910) (910:910:910)) + (PORT ena (1520:1520:1520) (1460:1460:1460)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55619,15 +58682,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (511:511:511)) - (PORT datab (249:249:249) (334:334:334)) - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (173:173:173) (201:201:201)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (233:233:233) (312:312:312)) + (PORT datab (839:839:839) (881:881:881)) + (PORT datad (1094:1094:1094) (1109:1109:1109)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1358:1358:1358)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (313:313:313)) + (PORT datab (839:839:839) (881:881:881)) + (PORT datad (1096:1096:1096) (1113:1113:1113)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1358:1358:1358)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1327:1327:1327) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (228:228:228)) + (PORT datab (212:212:212) (258:258:258)) + (PORT datac (208:208:208) (283:283:283)) + (PORT datad (212:212:212) (274:274:274)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55644,14 +58797,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (899:899:899) (933:933:933)) - (PORT datab (531:531:531) (514:514:514)) - (PORT datad (693:693:693) (657:657:657)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (839:839:839) (866:866:866)) + (PORT datab (478:478:478) (516:516:516)) + (PORT datad (709:709:709) (676:676:676)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55662,9 +58815,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1686:1686:1686) (1709:1709:1709)) + (PORT clk (1651:1651:1651) (1662:1662:1662)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55675,27 +58828,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (847:847:847) (868:868:868)) - (PORT datad (201:201:201) (259:259:259)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (442:442:442) (482:482:482)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]\~1) (DELAY (ABSOLUTE - (PORT dataa (847:847:847) (857:857:857)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (182:182:182) (216:216:216)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (896:896:896) (941:941:941)) + (PORT datac (182:182:182) (228:228:228)) + (PORT datad (215:215:215) (278:278:278)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -55704,40 +58859,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT datac (866:866:866) (887:887:887)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55752,22 +58877,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (224:224:224) (293:293:293)) - (PORT datac (861:861:861) (883:883:883)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (494:494:494) (536:536:536)) + (PORT datad (200:200:200) (258:258:258)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55782,22 +58907,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datac (845:845:845) (878:878:878)) - (PORT datad (199:199:199) (255:255:255)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (477:477:477) (523:523:523)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55812,22 +58937,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (299:299:299)) - (PORT datac (867:867:867) (889:889:889)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (493:493:493) (537:537:537)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55842,22 +58967,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT datac (859:859:859) (872:872:872)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (493:493:493) (536:536:536)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55872,22 +58997,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datac (866:866:866) (893:893:893)) - (PORT datad (200:200:200) (256:256:256)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (474:474:474) (517:517:517)) + (PORT datad (200:200:200) (258:258:258)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55902,22 +59027,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datab (222:222:222) (291:291:291)) - (PORT datac (868:868:868) (891:891:891)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (195:195:195) (262:262:262)) + (PORT datad (435:435:435) (475:475:475)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55932,22 +59057,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datac (867:867:867) (894:894:894)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (477:477:477) (526:526:526)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55962,22 +59087,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datac (867:867:867) (889:889:889)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (198:198:198) (266:266:266)) + (PORT datad (454:454:454) (495:495:495)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55992,22 +59117,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datac (869:869:869) (892:892:892)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (490:490:490) (534:534:534)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -56022,22 +59147,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datac (846:846:846) (867:867:867)) - (PORT datad (201:201:201) (259:259:259)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (197:197:197) (263:263:263)) + (PORT datad (451:451:451) (495:495:495)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -56047,119 +59172,27 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (468:468:468)) - (PORT datab (894:894:894) (905:905:905)) - (PORT datad (214:214:214) (277:277:277)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (468:468:468)) - (PORT datab (893:893:893) (905:905:905)) - (PORT datad (214:214:214) (276:276:276)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outr\~0) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (297:297:297)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (2727:2727:2727) (2696:2696:2696)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (298:298:298)) - (PORT datac (858:858:858) (874:874:874)) - (PORT datad (337:337:337) (378:378:378)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datac (198:198:198) (265:265:265)) + (PORT datad (444:444:444) (481:481:481)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -56174,24 +59207,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1308:1308:1308) (1326:1326:1326)) - (PORT datac (848:848:848) (868:868:868)) + (PORT datab (494:494:494) (538:538:538)) + (PORT datac (1123:1123:1123) (1166:1166:1166)) (PORT datad (199:199:199) (256:256:256)) (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -56201,42 +59234,64 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (553:553:553) (541:541:541)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (910:910:910) (910:910:910)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) - (PORT datac (846:846:846) (876:876:876)) - (PORT datad (1384:1384:1384) (1435:1435:1435)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1090:1090:1090) (1100:1100:1100)) + (PORT datac (610:610:610) (653:653:653)) + (PORT datad (1096:1096:1096) (1123:1123:1123)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1689:1689:1689)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (PORT ena (1109:1109:1109) (1090:1090:1090)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (504:504:504) (532:532:532)) + (PORT ena (2040:2040:2040) (1975:1975:1975)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (DELAY + (ABSOLUTE + (PORT datab (869:869:869) (897:897:897)) + (PORT datac (599:599:599) (627:627:627)) + (PORT datad (835:835:835) (864:864:864)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -56246,10 +59301,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1385:1385:1385)) + (PORT clk (1666:1666:1666) (1687:1687:1687)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1371:1371:1371)) - (PORT ena (1270:1270:1270) (1221:1221:1221)) + (PORT clrn (1385:1385:1385) (1368:1368:1368)) + (PORT ena (1128:1128:1128) (1100:1100:1100)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -56261,11 +59316,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~2) (DELAY (ABSOLUTE - (PORT datab (581:581:581) (579:579:579)) - (PORT datad (617:617:617) (641:641:641)) + (PORT datab (488:488:488) (531:531:531)) + (PORT datad (851:851:851) (888:888:888)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -56276,10 +59331,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1712:1712:1712)) + (PORT clk (1353:1353:1353) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1367:1367:1367)) - (PORT ena (1327:1327:1327) (1282:1282:1282)) + (PORT clrn (1389:1389:1389) (1368:1368:1368)) + (PORT ena (1569:1569:1569) (1530:1530:1530)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -56294,8 +59349,8 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (578:578:578) (579:579:579)) - (PORT datad (199:199:199) (256:256:256)) + (PORT datab (495:495:495) (535:535:535)) + (PORT datad (200:200:200) (257:257:257)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -56307,9 +59362,9 @@ (DELAY (ABSOLUTE (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (1040:1040:1040) (1074:1074:1074)) + (PORT d (868:868:868) (934:934:934)) (PORT clrn (1557:1557:1557) (1591:1591:1591)) - (PORT ena (793:793:793) (769:769:769)) + (PORT ena (1332:1332:1332) (1320:1320:1320)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -56323,116 +59378,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1072:1072:1072) (1068:1068:1068)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1647:1647:1647) (1622:1622:1622)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (333:333:333)) - (PORT datab (237:237:237) (306:306:306)) - (PORT datac (211:211:211) (277:277:277)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (258:258:258) (331:331:331)) - (PORT datab (256:256:256) (326:326:326)) - (PORT datac (370:370:370) (406:406:406)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (452:452:452)) - (PORT datab (246:246:246) (317:317:317)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (451:451:451)) - (PORT datab (632:632:632) (650:650:650)) - (PORT datac (567:567:567) (589:589:589)) - (PORT datad (482:482:482) (467:467:467)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (329:329:329)) - (PORT datab (262:262:262) (333:333:333)) - (PORT datac (322:322:322) (324:324:324)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (841:841:841) (826:826:826)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (1173:1173:1173) (1148:1148:1148)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -56441,25 +59391,25 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (491:491:491)) - (PORT datab (900:900:900) (926:926:926)) - (PORT datac (639:639:639) (679:679:679)) - (PORT datad (687:687:687) (719:719:719)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (452:452:452) (525:525:525)) + (PORT datab (1307:1307:1307) (1406:1406:1406)) + (PORT datac (1508:1508:1508) (1507:1507:1507)) + (PORT datad (251:251:251) (318:318:318)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT clk (1688:1688:1688) (1709:1709:1709)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -56473,25 +59423,98 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (412:412:412) (488:488:488)) - (PORT datab (896:896:896) (921:921:921)) - (PORT datac (639:639:639) (681:681:681)) - (PORT datad (684:684:684) (714:714:714)) + (PORT dataa (619:619:619) (629:629:629)) + (PORT datab (1537:1537:1537) (1532:1532:1532)) + (PORT datad (591:591:591) (605:605:605)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1324:1324:1324) (1322:1322:1322)) + (PORT ena (1145:1145:1145) (1123:1123:1123)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1125:1125:1125) (1119:1119:1119)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1688:1688:1688) (1709:1709:1709)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1385:1385:1385) (1391:1391:1391)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1688:1688:1688) (1709:1709:1709)) + (PORT asdata (1383:1383:1383) (1365:1365:1365)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (1059:1059:1059) (1073:1073:1073)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1337:1337:1337) (1353:1353:1353)) + (PORT ena (1145:1145:1145) (1123:1123:1123)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -56505,10 +59528,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (1087:1087:1087) (1064:1064:1064)) - (PORT datad (205:205:205) (266:266:266)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (206:206:206) (243:243:243)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) ) ) ) @@ -56517,13 +59539,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1662:1662:1662) (1675:1675:1675)) - (PORT asdata (468:468:468) (494:494:494)) + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) ) ) (CELL @@ -56531,8 +59553,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (405:405:405)) - (PORT datab (229:229:229) (300:300:300)) + (PORT dataa (939:939:939) (937:937:937)) + (PORT datab (222:222:222) (291:291:291)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -56546,9 +59568,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1617:1617:1617) (1564:1564:1564)) + (PORT ena (1594:1594:1594) (1556:1556:1556)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -56576,9 +59598,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1617:1617:1617) (1564:1564:1564)) + (PORT ena (1594:1594:1594) (1556:1556:1556)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -56606,9 +59628,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1617:1617:1617) (1564:1564:1564)) + (PORT ena (1594:1594:1594) (1556:1556:1556)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -56622,25 +59644,35 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (359:359:359) (390:390:390)) + (PORT datad (207:207:207) (267:267:267)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (161:161:161) (182:182:182)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1374:1374:1374)) - (PORT asdata (605:605:605) (603:603:603)) - (PORT ena (1617:1617:1617) (1564:1564:1564)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1594:1594:1594) (1556:1556:1556)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -56649,31 +59681,21 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (622:622:622) (639:639:639)) + (PORT datad (202:202:202) (261:261:261)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (994:994:994) (968:968:968)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (488:488:488)) - (PORT datab (898:898:898) (923:923:923)) - (PORT datac (641:641:641) (681:681:681)) - (PORT datad (686:686:686) (717:717:717)) + (PORT dataa (456:456:456) (519:519:519)) + (PORT datab (1309:1309:1309) (1403:1403:1403)) + (PORT datac (1508:1508:1508) (1504:1504:1504)) + (PORT datad (248:248:248) (314:314:314)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -56681,279 +59703,51 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (1213:1213:1213) (1239:1239:1239)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1320:1320:1320) (1304:1304:1304)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (888:888:888) (933:933:933)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (869:869:869) (866:866:866)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (602:602:602) (641:641:641)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (838:838:838) (824:824:824)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (916:916:916) (947:947:947)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (367:367:367)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (352:352:352) (387:387:387)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (363:363:363)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (966:966:966) (931:931:931)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT asdata (1085:1085:1085) (1073:1073:1073)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (591:591:591) (633:633:633)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1039:1039:1039) (1068:1068:1068)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (846:846:846) (822:822:822)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT asdata (1346:1346:1346) (1330:1330:1330)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -56962,9 +59756,25 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (1370:1370:1370) (1397:1397:1397)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (893:893:893) (919:919:919)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT asdata (1479:1479:1479) (1451:1451:1451)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -56973,38 +59783,12 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (600:600:600) (587:587:587)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (599:599:599) (636:636:636)) + (PORT datad (1211:1211:1211) (1221:1221:1221)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57014,9 +59798,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57025,29 +59809,19 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (856:856:856) (854:854:854)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1666:1666:1666) (1677:1677:1677)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1120:1120:1120) (1099:1099:1099)) + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT asdata (1118:1118:1118) (1110:1110:1110)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -57056,9 +59830,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (1068:1068:1068) (1081:1081:1081)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1047:1047:1047) (1055:1055:1055)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57072,11 +59846,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (281:281:281) (368:368:368)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (354:354:354) (390:390:390)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (245:245:245) (319:319:319)) + (PORT datad (238:238:238) (308:308:308)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57087,9 +59861,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (282:282:282) (368:368:368)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (157:157:157) (178:178:178)) + (PORT dataa (262:262:262) (346:346:346)) + (PORT datab (222:222:222) (292:292:292)) + (PORT datad (158:158:158) (179:179:179)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -57099,13 +59873,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[2\]\~0) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (183:183:183) (216:216:216)) + (PORT datad (756:756:756) (728:728:728)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1368:1368:1368) (1375:1375:1375)) + (PORT ena (1145:1145:1145) (1123:1123:1123)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT asdata (1396:1396:1396) (1360:1360:1360)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1522:1522:1522) (1514:1514:1514)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1360:1360:1360) (1363:1363:1363)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1271:1271:1271) (1275:1275:1275)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1673:1673:1673)) + (PORT asdata (1380:1380:1380) (1361:1361:1361)) + (PORT ena (1274:1274:1274) (1251:1251:1251)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1590:1590:1590) (1571:1571:1571)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (405:405:405)) + (PORT datab (245:245:245) (319:319:319)) + (PORT datad (237:237:237) (308:308:308)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (345:345:345)) + (PORT datab (381:381:381) (418:418:418)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (650:650:650)) + (PORT datab (318:318:318) (323:323:323)) + (PORT datac (156:156:156) (187:187:187)) (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|cindex\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (432:432:432)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (314:314:314)) + (PORT datab (240:240:240) (309:309:309)) + (PORT datad (216:216:216) (273:273:273)) + (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -57114,96 +60095,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT datad (1319:1319:1319) (1304:1304:1304)) + (PORT dataa (255:255:255) (334:334:334)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (236:236:236) (307:307:307)) + (PORT datad (173:173:173) (202:202:202)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (916:916:916) (962:962:962)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datad (601:601:601) (587:587:587)) + (PORT dataa (246:246:246) (322:322:322)) + (PORT datad (222:222:222) (280:280:280)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (918:918:918) (949:949:949)) - (PORT ena (1340:1340:1340) (1302:1302:1302)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~1) + (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (197:197:197) (241:241:241)) - (PORT datad (326:326:326) (364:364:364)) + (PORT dataa (389:389:389) (433:433:433)) + (PORT datab (243:243:243) (316:316:316)) + (PORT datad (158:158:158) (178:178:178)) (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57214,10 +60142,10 @@ (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (446:446:446)) - (PORT datab (261:261:261) (334:334:334)) - (PORT datac (224:224:224) (299:299:299)) - (PORT datad (238:238:238) (301:301:301)) + (PORT dataa (247:247:247) (324:324:324)) + (PORT datab (262:262:262) (336:336:336)) + (PORT datac (237:237:237) (307:307:307)) + (PORT datad (228:228:228) (292:292:292)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -57230,57 +60158,13 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (631:631:631)) - (PORT datab (435:435:435) (467:467:467)) - (PORT datac (154:154:154) (185:185:185)) - (PORT datad (330:330:330) (329:329:329)) + (PORT dataa (272:272:272) (352:352:352)) + (PORT datab (196:196:196) (233:233:233)) + (PORT datac (226:226:226) (300:300:300)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (451:451:451)) - (PORT datab (436:436:436) (470:470:470)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (327:327:327) (327:327:327)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (311:311:311)) - (PORT datad (224:224:224) (287:287:287)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (642:642:642)) - (PORT datab (238:238:238) (306:306:306)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57290,10 +60174,90 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (473:473:473) (467:467:467)) + (PORT dataa (518:518:518) (506:506:506)) + (PORT datab (525:525:525) (531:531:531)) + (PORT datad (494:494:494) (466:466:466)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1327:1327:1327) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (354:354:354)) + (PORT datab (254:254:254) (328:328:328)) + (PORT datac (229:229:229) (305:305:305)) + (PORT datad (173:173:173) (202:202:202)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (323:323:323)) + (PORT datab (243:243:243) (316:316:316)) + (PORT datac (358:358:358) (398:398:398)) + (PORT datad (222:222:222) (280:280:280)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (735:735:735)) + (PORT datab (386:386:386) (434:434:434)) + (PORT datac (589:589:589) (629:629:629)) + (PORT datad (510:510:510) (494:494:494)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (441:441:441)) + (PORT datab (383:383:383) (424:424:424)) + (PORT datac (311:311:311) (317:317:317)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57304,23 +60268,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1332:1332:1332) (1361:1361:1361)) - (PORT datab (212:212:212) (252:252:252)) - (PORT datac (305:305:305) (313:313:313)) - (PORT datad (186:186:186) (212:212:212)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (994:994:994) (965:965:965)) + (PORT dataa (204:204:204) (242:242:242)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1478:1478:1478) (1494:1494:1494)) + (PORT datad (330:330:330) (341:341:341)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57330,14 +60284,14 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) + (PORT clk (1688:1688:1688) (1709:1709:1709)) + (PORT asdata (1083:1083:1083) (1049:1049:1049)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -57346,9 +60300,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) - (PORT asdata (893:893:893) (923:923:923)) - (PORT ena (1180:1180:1180) (1163:1163:1163)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (877:877:877) (899:899:899)) + (PORT ena (1093:1093:1093) (1082:1082:1082)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57362,11 +60316,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (352:352:352)) - (PORT datab (1019:1019:1019) (1026:1026:1026)) - (PORT datad (167:167:167) (193:193:193)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (378:378:378) (400:400:400)) + (PORT datab (548:548:548) (554:554:554)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57377,21 +60331,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (351:351:351)) - (PORT datab (213:213:213) (255:255:255)) - (PORT datac (304:304:304) (313:313:313)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1220:1220:1220) (1200:1200:1200)) + (PORT dataa (382:382:382) (391:391:391)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (337:337:337) (334:334:334)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57401,51 +60345,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1784:1784:1784) (1772:1772:1772)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (866:866:866) (863:863:863)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (923:923:923) (963:963:963)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1825:1825:1825) (1794:1794:1794)) + (PORT ena (1327:1327:1327) (1303:1303:1303)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57459,8 +60361,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (967:967:967) (931:931:931)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (774:774:774) (766:766:766)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -57469,9 +60371,61 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT clk (1688:1688:1688) (1709:1709:1709)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (572:572:572) (601:601:601)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1145:1145:1145) (1123:1123:1123)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1361:1361:1361) (1362:1362:1362)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1688:1688:1688) (1709:1709:1709)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57482,12 +60436,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) + (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (1319:1319:1319) (1307:1307:1307)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1600:1600:1600) (1579:1579:1579)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57501,9 +60455,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datad (198:198:198) (256:256:256)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datab (351:351:351) (397:397:397)) + (PORT datad (171:171:171) (197:197:197)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57514,13 +60468,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (247:247:247)) - (PORT datab (215:215:215) (258:258:258)) - (PORT datac (795:795:795) (825:825:825)) - (PORT datad (297:297:297) (303:303:303)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1475:1475:1475) (1497:1497:1497)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (728:728:728) (696:696:696)) + (PORT datad (332:332:332) (342:342:342)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57530,75 +60484,23 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (335:335:335) (350:350:350)) - (PORT datac (560:560:560) (545:545:545)) - (PORT datad (294:294:294) (300:300:300)) + (PORT dataa (210:210:210) (251:251:251)) + (PORT datac (342:342:342) (357:357:357)) + (PORT datad (336:336:336) (338:338:338)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (539:539:539) (527:527:527)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1336:1336:1336) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1584:1584:1584) (1548:1548:1548)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (848:848:848) (823:823:823)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1378:1378:1378)) - (PORT asdata (893:893:893) (929:929:929)) - (PORT ena (1340:1340:1340) (1302:1302:1302)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1418:1418:1418) (1423:1423:1423)) + (PORT ena (1503:1503:1503) (1459:1459:1459)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57607,13 +60509,65 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (1039:1039:1039) (1027:1027:1027)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1688:1688:1688) (1709:1709:1709)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (815:815:815) (817:817:817)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1145:1145:1145) (1123:1123:1123)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (860:860:860) (858:858:858)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (811:811:811) (805:805:805)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -57622,9 +60576,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT clk (1688:1688:1688) (1709:1709:1709)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1119:1119:1119) (1089:1089:1089)) + (PORT ena (1557:1557:1557) (1517:1517:1517)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57638,9 +60592,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1378:1378:1378)) - (PORT asdata (893:893:893) (929:929:929)) - (PORT ena (1120:1120:1120) (1090:1090:1090)) + (PORT clk (1363:1363:1363) (1379:1379:1379)) + (PORT asdata (1089:1089:1089) (1088:1088:1088)) + (PORT ena (1583:1583:1583) (1543:1543:1543)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57654,9 +60608,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (351:351:351) (398:398:398)) - (PORT datad (172:172:172) (202:202:202)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (386:386:386) (426:426:426)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57667,13 +60621,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1586:1586:1586) (1650:1650:1650)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (343:343:343) (345:345:345)) - (PORT datad (346:346:346) (347:347:347)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1265:1265:1265) (1272:1272:1272)) + (PORT datab (356:356:356) (375:375:375)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (171:171:171) (201:201:201)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57683,35 +60637,21 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (351:351:351)) - (PORT datab (327:327:327) (340:340:340)) - (PORT datad (348:348:348) (351:351:351)) + (PORT dataa (616:616:616) (607:607:607)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datad (332:332:332) (343:343:343)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (851:851:851)) - (PORT datac (784:784:784) (795:795:795)) - (PORT datad (1043:1043:1043) (1048:1048:1048)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1377:1377:1377)) + (PORT clk (1362:1362:1362) (1379:1379:1379)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -57720,14 +60660,28 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (741:741:741)) + (PORT datac (647:647:647) (698:698:698)) + (PORT datad (1476:1476:1476) (1459:1459:1459)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (373:373:373) (384:384:384)) - (PORT datad (338:338:338) (336:336:336)) + (PORT dataa (193:193:193) (235:235:235)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -57741,7 +60695,7 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (2121:2121:2121) (2113:2113:2113)) + (PORT d (1707:1707:1707) (1704:1704:1704)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -57755,7 +60709,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT clk (1362:1362:1362) (1378:1378:1378)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -57769,11 +60723,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (499:499:499) (489:489:489)) - (PORT datad (1356:1356:1356) (1332:1332:1332)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (209:209:209) (247:247:247)) + (PORT datad (655:655:655) (707:707:707)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57785,7 +60739,7 @@ (DELAY (ABSOLUTE (PORT clk (1333:1333:1333) (1351:1351:1351)) - (PORT d (1430:1430:1430) (1495:1495:1495)) + (PORT d (1528:1528:1528) (1523:1523:1523)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -57799,7 +60753,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (229:229:229) (290:290:290)) + (PORT datad (226:226:226) (286:286:286)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57809,10 +60763,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -57827,10 +60781,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1366:1366:1366)) - (PORT asdata (504:504:504) (566:566:566)) - (PORT clrn (1403:1403:1403) (1369:1369:1369)) - (PORT ena (1133:1133:1133) (1118:1118:1118)) + (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT asdata (508:508:508) (571:571:571)) + (PORT clrn (1376:1376:1376) (1349:1349:1349)) + (PORT ena (1299:1299:1299) (1245:1245:1245)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -57845,7 +60799,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (229:229:229) (289:289:289)) + (PORT datad (221:221:221) (279:279:279)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -57856,9 +60810,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1360:1360:1360) (1342:1342:1342)) - (PORT datad (228:228:228) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (4011:4011:4011) (4021:4021:4021)) + (PORT datad (1344:1344:1344) (1335:1335:1335)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57868,11 +60822,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (908:908:908) (923:923:923)) - (PORT datac (3029:3029:3029) (3293:3293:3293)) - (PORT datad (553:553:553) (541:541:541)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (3048:3048:3048) (3237:3237:3237)) + (PORT datab (637:637:637) (651:651:651)) + (PORT datad (1095:1095:1095) (1092:1092:1092)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57882,9 +60836,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (910:910:910) (910:910:910)) + (PORT ena (1520:1520:1520) (1460:1460:1460)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -57898,69 +60852,11 @@ (INSTANCE sdram_\|Mux26\~4) (DELAY (ABSOLUTE - (PORT dataa (2141:2141:2141) (2278:2278:2278)) - (PORT datab (873:873:873) (871:871:871)) - (PORT datad (1320:1320:1320) (1366:1366:1366)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (909:909:909) (982:982:982)) - (PORT datad (1662:1662:1662) (1718:1718:1718)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (862:862:862)) - (PORT datab (761:761:761) (826:826:826)) - (PORT datac (716:716:716) (788:788:788)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (337:337:337)) - (PORT datac (539:539:539) (540:540:540)) - (PORT datad (258:258:258) (325:325:325)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (950:950:950) (998:998:998)) - (PORT datab (954:954:954) (988:988:988)) - (PORT datac (968:968:968) (1026:1026:1026)) - (PORT datad (552:552:552) (548:548:548)) + (PORT dataa (2002:2002:2002) (2099:2099:2099)) + (PORT datac (1747:1747:1747) (1722:1722:1722)) + (PORT datad (223:223:223) (283:283:283)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -57970,26 +60866,40 @@ (INSTANCE sdram_\|r\.bank\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1210:1210:1210) (1275:1275:1275)) - (PORT datab (1743:1743:1743) (1802:1802:1802)) - (PORT datac (911:911:911) (980:980:980)) - (PORT datad (725:725:725) (709:709:709)) + (PORT dataa (1459:1459:1459) (1525:1525:1525)) + (PORT datac (1704:1704:1704) (1752:1752:1752)) + (PORT datad (1212:1212:1212) (1294:1294:1294)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~8) + (INSTANCE sdram_\|r\.bank\[0\]\~4) (DELAY (ABSOLUTE - (PORT datab (1203:1203:1203) (1248:1248:1248)) - (PORT datac (1713:1713:1713) (1778:1778:1778)) - (PORT datad (908:908:908) (967:967:967)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (838:838:838) (880:880:880)) + (PORT datac (1158:1158:1158) (1221:1221:1221)) + (PORT datad (1463:1463:1463) (1494:1494:1494)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1276:1276:1276)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (811:811:811) (856:856:856)) + (PORT datad (793:793:793) (779:779:779)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58000,13 +60910,43 @@ (INSTANCE sdram_\|r\.bank\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (840:840:840) (867:867:867)) - (PORT datab (760:760:760) (831:831:831)) - (PORT datac (162:162:162) (197:197:197)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1193:1193:1193) (1261:1261:1261)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (794:794:794) (777:777:777)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1527:1527:1527)) + (PORT datac (1706:1706:1706) (1749:1749:1749)) + (PORT datad (1211:1211:1211) (1288:1288:1288)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1330:1330:1330)) + (PORT datab (839:839:839) (882:882:882)) + (PORT datac (1422:1422:1422) (1493:1493:1493)) + (PORT datad (1147:1147:1147) (1221:1221:1221)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58016,13 +60956,61 @@ (INSTANCE sdram_\|r\.bank\[0\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1210:1210:1210) (1275:1275:1275)) + (PORT dataa (1464:1464:1464) (1528:1528:1528)) + (PORT datab (832:832:832) (810:810:810)) + (PORT datac (1704:1704:1704) (1748:1748:1748)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1274:1274:1274)) + (PORT datab (1464:1464:1464) (1510:1510:1510)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1533:1533:1533)) (PORT datab (188:188:188) (222:222:222)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (160:160:160) (181:181:181)) + (PORT datac (1704:1704:1704) (1748:1748:1748)) + (PORT datad (1206:1206:1206) (1285:1285:1285)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1462:1462:1462) (1509:1509:1509)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (161:161:161) (182:182:182)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58033,8 +61021,8 @@ (DELAY (ABSOLUTE (PORT clk (1337:1337:1337) (1357:1357:1357)) - (PORT d (1636:1636:1636) (1697:1697:1697)) - (PORT ena (1640:1640:1640) (1571:1571:1571)) + (PORT d (1920:1920:1920) (1986:1986:1986)) + (PORT ena (1348:1348:1348) (1331:1331:1331)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -58050,11 +61038,11 @@ (INSTANCE sdram_\|Mux25\~4) (DELAY (ABSOLUTE - (PORT dataa (2141:2141:2141) (2279:2279:2279)) - (PORT datab (1327:1327:1327) (1387:1387:1387)) - (PORT datad (849:849:849) (841:841:841)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (768:768:768) (783:783:783)) + (PORT datab (1775:1775:1775) (1750:1750:1750)) + (PORT datad (1978:1978:1978) (2063:2063:2063)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58065,8 +61053,8 @@ (DELAY (ABSOLUTE (PORT clk (1338:1338:1338) (1359:1359:1359)) - (PORT d (2129:2129:2129) (2198:2198:2198)) - (PORT ena (1478:1478:1478) (1426:1426:1426)) + (PORT d (1660:1660:1660) (1743:1743:1743)) + (PORT ena (1341:1341:1341) (1321:1321:1321)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -58079,74 +61067,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~5) + (INSTANCE sdram_\|Mux71\~6) (DELAY (ABSOLUTE - (PORT dataa (976:976:976) (1062:1062:1062)) - (PORT datab (936:936:936) (988:988:988)) - (PORT datac (1069:1069:1069) (1053:1053:1053)) - (PORT datad (918:918:918) (956:956:956)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (1509:1509:1509) (1569:1569:1569)) + (PORT datab (1055:1055:1055) (1121:1121:1121)) + (PORT datac (961:961:961) (1017:1017:1017)) + (PORT datad (979:979:979) (1076:1076:1076)) + (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~0) - (DELAY - (ABSOLUTE - (PORT datab (1291:1291:1291) (1358:1358:1358)) - (PORT datac (1454:1454:1454) (1501:1501:1501)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~7) - (DELAY - (ABSOLUTE - (PORT datab (1581:1581:1581) (1681:1681:1681)) - (PORT datac (199:199:199) (269:269:269)) - (PORT datad (2418:2418:2418) (2528:2528:2528)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (691:691:691)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (168:168:168) (193:193:193)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1252:1252:1252)) - (PORT datab (1366:1366:1366) (1394:1394:1394)) - (PORT datac (1455:1455:1455) (1501:1501:1501)) - (PORT datad (1254:1254:1254) (1323:1323:1323)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58156,13 +61086,9 @@ (INSTANCE sdram_\|Mux71\~2) (DELAY (ABSOLUTE - (PORT dataa (1197:1197:1197) (1252:1252:1252)) - (PORT datab (930:930:930) (1000:1000:1000)) - (PORT datac (154:154:154) (185:185:185)) - (PORT datad (170:170:170) (198:198:198)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (1024:1024:1024) (1090:1090:1090)) + (PORT datad (1462:1462:1462) (1521:1521:1521)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58172,13 +61098,42 @@ (INSTANCE sdram_\|Mux71\~3) (DELAY (ABSOLUTE - (PORT dataa (1010:1010:1010) (1003:1003:1003)) - (PORT datab (195:195:195) (235:235:235)) - (PORT datac (946:946:946) (1027:1027:1027)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1186:1186:1186) (1242:1242:1242)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (980:980:980) (1074:1074:1074)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1235:1235:1235)) + (PORT datad (1401:1401:1401) (1416:1416:1416)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (701:701:701)) + (PORT datab (195:195:195) (233:233:233)) + (PORT datac (463:463:463) (446:446:446)) + (PORT datad (317:317:317) (314:314:314)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58188,12 +61143,44 @@ (INSTANCE sdram_\|Mux71\~4) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (908:908:908) (969:969:969)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (571:571:571) (579:579:579)) + (PORT datad (1162:1162:1162) (1204:1204:1204)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~8) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (484:484:484)) + (PORT datab (864:864:864) (854:854:854)) + (PORT datac (962:962:962) (1017:1017:1017)) + (PORT datad (584:584:584) (607:607:607)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~5) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1006:1006:1006) (1107:1107:1107)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58205,7 +61192,7 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1356:1356:1356)) - (PORT d (1348:1348:1348) (1388:1388:1388)) + (PORT d (1393:1393:1393) (1447:1447:1447)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -58220,7 +61207,7 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1356:1356:1356)) - (PORT d (1333:1333:1333) (1375:1375:1375)) + (PORT d (1393:1393:1393) (1447:1447:1447)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -58231,43 +61218,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~10) + (INSTANCE sdram_\|n\~6) (DELAY (ABSOLUTE - (PORT datac (1449:1449:1449) (1494:1494:1494)) - (PORT datad (908:908:908) (970:970:970)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~3) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (360:360:360)) - (PORT datab (1373:1373:1373) (1412:1412:1412)) - (PORT datac (1231:1231:1231) (1313:1313:1313)) - (PORT datad (327:327:327) (332:332:332)) + (PORT dataa (851:851:851) (907:907:907)) + (PORT datab (924:924:924) (964:964:964)) + (PORT datac (807:807:807) (836:836:836)) + (PORT datad (916:916:916) (982:982:982)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~5) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (463:463:463)) - (PORT datab (638:638:638) (688:688:688)) - (PORT datac (539:539:539) (540:540:540)) - (PORT datad (258:258:258) (325:325:325)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58275,153 +61234,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~4) + (INSTANCE sdram_\|Mux9\~0) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (338:338:338)) - (PORT datab (1251:1251:1251) (1312:1312:1312)) - (PORT datac (805:805:805) (806:806:806)) - (PORT datad (1335:1335:1335) (1378:1378:1378)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1352:1352:1352)) - (PORT datab (1252:1252:1252) (1307:1307:1307)) - (PORT datac (804:804:804) (804:804:804)) - (PORT datad (1158:1158:1158) (1202:1202:1202)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (645:645:645) (657:657:657)) + (PORT datab (735:735:735) (795:795:795)) + (PORT datac (718:718:718) (772:772:772)) + (PORT datad (808:808:808) (818:818:818)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (776:776:776)) - (PORT datab (273:273:273) (351:351:351)) - (PORT datac (575:575:575) (602:602:602)) - (PORT datad (688:688:688) (743:743:743)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~2) - (DELAY - (ABSOLUTE - (PORT datab (419:419:419) (450:450:450)) - (PORT datac (387:387:387) (422:422:422)) - (PORT datad (548:548:548) (569:569:569)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~3) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (439:439:439)) - (PORT datab (248:248:248) (319:319:319)) - (PORT datac (158:158:158) (188:188:188)) - (PORT datad (395:395:395) (427:427:427)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (438:438:438)) - (PORT datab (420:420:420) (453:453:453)) - (PORT datac (329:329:329) (336:336:336)) - (PORT datad (383:383:383) (417:417:417)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~4) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (395:395:395) (436:436:436)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (628:628:628) (676:676:676)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1323:1323:1323) (1363:1363:1363)) - (PORT datab (1494:1494:1494) (1550:1550:1550)) - (PORT datac (1222:1222:1222) (1279:1279:1279)) - (PORT datad (310:310:310) (320:320:320)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~0) - (DELAY - (ABSOLUTE - (PORT datab (1250:1250:1250) (1314:1314:1314)) - (PORT datad (1457:1457:1457) (1518:1518:1518)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux9\~6) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (374:374:374)) - (PORT datab (593:593:593) (601:601:601)) - (PORT datac (157:157:157) (189:189:189)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (594:594:594) (617:617:617)) + (PORT datab (898:898:898) (912:912:912)) + (PORT datac (718:718:718) (771:771:771)) + (PORT datad (600:600:600) (614:614:614)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (294:294:294)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58432,13 +61269,167 @@ (INSTANCE sdram_\|Mux9\~7) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (1154:1154:1154) (1217:1217:1217)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (714:714:714) (787:787:787)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (801:801:801) (832:832:832)) + (PORT datad (698:698:698) (760:760:760)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datac (717:717:717) (772:772:772)) + (PORT datad (695:695:695) (757:757:757)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (346:346:346)) + (PORT datab (393:393:393) (450:450:450)) + (PORT datac (376:376:376) (418:418:418)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (361:361:361)) + (PORT datab (406:406:406) (445:445:445)) + (PORT datac (374:374:374) (416:416:416)) + (PORT datad (349:349:349) (386:386:386)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (435:435:435)) + (PORT datac (376:376:376) (418:418:418)) + (PORT datad (239:239:239) (309:309:309)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (229:229:229)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datac (362:362:362) (419:419:419)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (451:451:451)) + (PORT datab (391:391:391) (445:445:445)) + (PORT datac (358:358:358) (397:397:397)) + (PORT datad (237:237:237) (307:307:307)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (432:432:432)) + (PORT datab (190:190:190) (224:224:224)) + (PORT datac (175:175:175) (205:205:205)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (613:613:613)) + (PORT datab (736:736:736) (791:791:791)) + (PORT datac (717:717:717) (768:768:768)) + (PORT datad (688:688:688) (747:747:747)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (342:342:342)) + (PORT datab (584:584:584) (616:616:616)) + (PORT datac (565:565:565) (581:581:581)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (865:865:865) (880:880:880)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58448,8 +61439,8 @@ (INSTANCE sdram_\|r\.state\[2\]) (DELAY (ABSOLUTE - (PORT clk (1328:1328:1328) (1347:1347:1347)) - (PORT d (1353:1353:1353) (1397:1397:1397)) + (PORT clk (1319:1319:1319) (1335:1335:1335)) + (PORT d (1467:1467:1467) (1530:1530:1530)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -58460,32 +61451,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~11) + (INSTANCE sdram_\|Mux10\~6) (DELAY (ABSOLUTE - (PORT dataa (903:903:903) (978:978:978)) - (PORT datab (936:936:936) (990:990:990)) - (PORT datac (1069:1069:1069) (1055:1055:1055)) - (PORT datad (919:919:919) (958:958:958)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1252:1252:1252) (1307:1307:1307)) + (PORT datab (893:893:893) (934:934:934)) + (PORT datac (969:969:969) (1031:1031:1031)) + (PORT datad (1171:1171:1171) (1194:1194:1194)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~6) + (INSTANCE sdram_\|Mux10\~10) (DELAY (ABSOLUTE - (PORT dataa (973:973:973) (1061:1061:1061)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (983:983:983) (974:974:974)) - (PORT datad (892:892:892) (958:958:958)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1508:1508:1508) (1565:1565:1565)) + (PORT datab (1008:1008:1008) (1106:1106:1106)) + (PORT datac (585:585:585) (578:578:578)) + (PORT datad (568:568:568) (581:581:581)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1312:1312:1312)) + (PORT datab (819:819:819) (874:874:874)) + (PORT datac (931:931:931) (999:999:999)) + (PORT datad (1173:1173:1173) (1190:1190:1190)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1307:1307:1307)) + (PORT datab (816:816:816) (871:871:871)) + (PORT datac (934:934:934) (995:995:995)) + (PORT datad (1162:1162:1162) (1188:1188:1188)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58495,13 +61518,13 @@ (INSTANCE sdram_\|Mux10\~5) (DELAY (ABSOLUTE - (PORT dataa (1196:1196:1196) (1251:1251:1251)) - (PORT datab (1292:1292:1292) (1359:1359:1359)) - (PORT datac (874:874:874) (942:942:942)) - (PORT datad (583:583:583) (593:593:593)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1006:1006:1006) (1063:1063:1063)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1072:1072:1072) (1067:1067:1067)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58511,12 +61534,44 @@ (INSTANCE sdram_\|Mux10\~7) (DELAY (ABSOLUTE - (PORT dataa (973:973:973) (1062:1062:1062)) - (PORT datab (1291:1291:1291) (1361:1361:1361)) - (PORT datac (874:874:874) (949:949:949)) - (PORT datad (892:892:892) (958:958:958)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (909:909:909) (958:958:958)) + (PORT datab (932:932:932) (976:976:976)) + (PORT datac (967:967:967) (1028:1028:1028)) + (PORT datad (1162:1162:1162) (1189:1189:1189)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1048:1048:1048)) + (PORT datab (906:906:906) (900:900:900)) + (PORT datac (551:551:551) (564:564:564)) + (PORT datad (566:566:566) (580:580:580)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~12) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1046:1046:1046)) + (PORT datab (1007:1007:1007) (1105:1105:1105)) + (PORT datac (572:572:572) (582:582:582)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58527,29 +61582,13 @@ (INSTANCE sdram_\|Mux10\~8) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (931:931:931) (1005:1005:1005)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~9) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (203:203:203) (236:236:236)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1008:1008:1008) (1113:1113:1113)) + (PORT datac (570:570:570) (584:584:584)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58559,8 +61598,8 @@ (INSTANCE sdram_\|r\.state\[1\]) (DELAY (ABSOLUTE - (PORT clk (1328:1328:1328) (1347:1347:1347)) - (PORT d (1146:1146:1146) (1216:1216:1216)) + (PORT clk (1319:1319:1319) (1335:1335:1335)) + (PORT d (1160:1160:1160) (1230:1230:1230)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -58599,16 +61638,50 @@ (HOLD d (posedge clk) (77:77:77)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1192:1192:1192)) + (PORT datab (982:982:982) (1060:1060:1060)) + (PORT datac (1152:1152:1152) (1180:1180:1180)) + (PORT datad (1210:1210:1210) (1238:1238:1238)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (598:598:598)) + (PORT datab (1011:1011:1011) (1083:1083:1083)) + (PORT datac (1156:1156:1156) (1185:1185:1185)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux11\~2) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (767:767:767)) - (PORT datab (713:713:713) (776:776:776)) - (PORT datad (246:246:246) (317:317:317)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (550:550:550) (549:549:549)) + (PORT datab (1005:1005:1005) (1067:1067:1067)) + (PORT datac (569:569:569) (573:573:573)) + (PORT datad (988:988:988) (1044:1044:1044)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58618,28 +61691,12 @@ (INSTANCE sdram_\|Mux11\~3) (DELAY (ABSOLUTE - (PORT dataa (1387:1387:1387) (1441:1441:1441)) - (PORT datab (597:597:597) (624:624:624)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (1307:1307:1307) (1342:1342:1342)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1343:1343:1343)) - (PORT datab (1252:1252:1252) (1314:1314:1314)) - (PORT datac (587:587:587) (589:589:589)) - (PORT datad (303:303:303) (305:305:305)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1215:1215:1215) (1296:1296:1296)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (182:182:182) (216:216:216)) + (PORT datad (1691:1691:1691) (1721:1721:1721)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58650,13 +61707,13 @@ (INSTANCE sdram_\|Mux11\~5) (DELAY (ABSOLUTE - (PORT dataa (1257:1257:1257) (1343:1343:1343)) - (PORT datab (1253:1253:1253) (1314:1314:1314)) - (PORT datac (1458:1458:1458) (1507:1507:1507)) - (PORT datad (1162:1162:1162) (1207:1207:1207)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1197:1197:1197) (1222:1222:1222)) + (PORT datab (984:984:984) (1061:1061:1061)) + (PORT datac (826:826:826) (876:876:876)) + (PORT datad (976:976:976) (1046:1046:1046)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58666,12 +61723,12 @@ (INSTANCE sdram_\|Mux11\~6) (DELAY (ABSOLUTE - (PORT dataa (907:907:907) (981:981:981)) - (PORT datab (934:934:934) (1004:1004:1004)) - (PORT datac (949:949:949) (1030:1030:1030)) - (PORT datad (895:895:895) (959:959:959)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (319:319:319) (334:334:334)) + (PORT datab (835:835:835) (862:862:862)) + (PORT datac (894:894:894) (932:932:932)) + (PORT datad (917:917:917) (976:976:976)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58682,41 +61739,9 @@ (INSTANCE sdram_\|Mux11\~7) (DELAY (ABSOLUTE - (PORT dataa (845:845:845) (869:869:869)) - (PORT datab (760:760:760) (825:825:825)) - (PORT datac (717:717:717) (793:793:793)) - (PORT datad (288:288:288) (295:295:295)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1365:1365:1365)) - (PORT datab (1150:1150:1150) (1216:1216:1216)) - (PORT datac (807:807:807) (807:807:807)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~8) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (550:550:550) (543:543:543)) + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (747:747:747) (733:733:733)) (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) @@ -58731,7 +61756,7 @@ (DELAY (ABSOLUTE (PORT clk (1326:1326:1326) (1341:1341:1341)) - (PORT d (1667:1667:1667) (1728:1728:1728)) + (PORT d (1426:1426:1426) (1501:1501:1501)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -58742,62 +61767,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~2) + (INSTANCE sdram_\|Mux24\~5) (DELAY (ABSOLUTE - (PORT dataa (717:717:717) (772:772:772)) - (PORT datab (695:695:695) (765:765:765)) - (PORT datac (698:698:698) (779:779:779)) - (PORT datad (801:801:801) (785:785:785)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (1103:1103:1103) (1120:1120:1120)) + (PORT datab (635:635:635) (664:664:664)) + (PORT datac (900:900:900) (902:902:902)) + (PORT datad (601:601:601) (612:612:612)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~7) + (INSTANCE sdram_\|Mux24\~6) (DELAY (ABSOLUTE - (PORT dataa (2837:2837:2837) (2923:2923:2923)) - (PORT datab (567:567:567) (594:594:594)) - (PORT datac (957:957:957) (1018:1018:1018)) - (PORT datad (591:591:591) (593:593:593)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (560:560:560)) - (PORT datab (901:901:901) (969:969:969)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1257:1257:1257) (1344:1344:1344)) - (PORT datab (1154:1154:1154) (1221:1221:1221)) - (PORT datac (1458:1458:1458) (1508:1508:1508)) - (PORT datad (1336:1336:1336) (1375:1375:1375)) + (PORT dataa (326:326:326) (339:339:339)) + (PORT datab (636:636:636) (664:664:664)) + (PORT datac (1209:1209:1209) (1254:1254:1254)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58808,10 +61802,10 @@ (INSTANCE sdram_\|Mux13\~4) (DELAY (ABSOLUTE - (PORT dataa (1264:1264:1264) (1353:1353:1353)) - (PORT datab (1149:1149:1149) (1214:1214:1214)) - (PORT datac (1453:1453:1453) (1500:1500:1500)) - (PORT datad (1340:1340:1340) (1380:1380:1380)) + (PORT dataa (1736:1736:1736) (1760:1760:1760)) + (PORT datab (1004:1004:1004) (1066:1066:1066)) + (PORT datac (928:928:928) (979:979:979)) + (PORT datad (986:986:986) (1043:1043:1043)) (IOPATH dataa combout (299:299:299) (306:306:306)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -58819,16 +61813,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1736:1736:1736) (1760:1760:1760)) + (PORT datab (1005:1005:1005) (1067:1067:1067)) + (PORT datac (927:927:927) (978:978:978)) + (PORT datad (988:988:988) (1043:1043:1043)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux13\~5) (DELAY (ABSOLUTE - (PORT datab (1252:1252:1252) (1307:1307:1307)) - (PORT datac (159:159:159) (190:190:190)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datac (1186:1186:1186) (1265:1265:1265)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58838,11 +61848,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1378:1378:1378)) + (PORT clk (1350:1350:1350) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (473:473:473) (502:502:502)) - (PORT sload (1491:1491:1491) (1583:1583:1583)) - (PORT ena (1138:1138:1138) (1126:1126:1126)) + (PORT asdata (856:856:856) (840:840:840)) + (PORT sload (1757:1757:1757) (1857:1857:1857)) + (PORT ena (1165:1165:1165) (1147:1147:1147)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -58853,18 +61863,30 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (796:796:796)) + (PORT datab (796:796:796) (781:781:781)) + (PORT datac (577:577:577) (622:622:622)) + (PORT datad (1700:1700:1700) (1738:1738:1738)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux24\~3) (DELAY (ABSOLUTE - (PORT dataa (2837:2837:2837) (2921:2921:2921)) - (PORT datab (567:567:567) (594:594:594)) - (PORT datac (346:346:346) (361:361:361)) - (PORT datad (591:591:591) (589:589:589)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (439:439:439) (497:497:497)) + (PORT datad (1230:1230:1230) (1298:1298:1298)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58874,13 +61896,27 @@ (INSTANCE sdram_\|Mux24\~4) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (845:845:845)) - (PORT datab (569:569:569) (596:596:596)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1023:1023:1023) (1045:1045:1045)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (656:656:656) (700:700:700)) + (PORT datab (636:636:636) (660:660:660)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (480:480:480) (468:468:468)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (598:598:598)) + (PORT datab (1506:1506:1506) (1562:1562:1562)) + (PORT datad (302:302:302) (304:304:304)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58890,11 +61926,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (974:974:974) (1022:1022:1022)) - (PORT datac (162:162:162) (194:194:194)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1205:1205:1205) (1273:1273:1273)) + (PORT datad (334:334:334) (331:331:331)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -58905,8 +61941,8 @@ (DELAY (ABSOLUTE (PORT clk (1328:1328:1328) (1344:1344:1344)) - (PORT d (1837:1837:1837) (1871:1871:1871)) - (PORT ena (1552:1552:1552) (1523:1523:1523)) + (PORT d (1548:1548:1548) (1594:1594:1594)) + (PORT ena (1773:1773:1773) (1740:1740:1740)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -58919,57 +61955,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (INSTANCE sdram_\|Mux23\~1) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~4) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (998:998:998)) - (PORT datab (227:227:227) (301:301:301)) - (PORT datac (1184:1184:1184) (1205:1205:1205)) - (PORT datad (306:306:306) (326:326:326)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (774:774:774)) - (PORT datab (713:713:713) (780:780:780)) - (PORT datac (571:571:571) (600:600:600)) - (PORT datad (248:248:248) (318:318:318)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~5) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (1002:1002:1002)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (889:889:889) (928:928:928)) - (PORT datad (803:803:803) (798:798:798)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) + (PORT dataa (1566:1566:1566) (1646:1646:1646)) + (PORT datab (648:648:648) (663:663:663)) + (PORT datac (759:759:759) (751:751:751)) + (PORT datad (1236:1236:1236) (1306:1306:1306)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -58977,32 +61971,100 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~6) + (INSTANCE sdram_\|r\.address\[1\]\~8) (DELAY (ABSOLUTE - (PORT dataa (938:938:938) (1000:1000:1000)) - (PORT datab (990:990:990) (1063:1063:1063)) - (PORT datac (156:156:156) (185:185:185)) - (PORT datad (811:811:811) (789:789:789)) - (IOPATH dataa combout (267:267:267) (269:269:269)) + (PORT dataa (1567:1567:1567) (1647:1647:1647)) + (PORT datab (1262:1262:1262) (1346:1346:1346)) + (PORT datad (778:778:778) (759:759:759)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1239:1239:1239)) + (PORT datab (1174:1174:1174) (1169:1169:1169)) + (PORT datad (1229:1229:1229) (1293:1293:1293)) + (IOPATH dataa combout (267:267:267) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1645:1645:1645)) + (PORT datab (1257:1257:1257) (1345:1345:1345)) + (PORT datac (833:833:833) (863:863:863)) + (PORT datad (1417:1417:1417) (1469:1469:1469)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (1445:1445:1445) (1503:1503:1503)) + (PORT datac (529:529:529) (517:517:517)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (825:825:825) (837:837:837)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~0) (DELAY (ABSOLUTE - (PORT dataa (1174:1174:1174) (1236:1236:1236)) - (PORT datab (998:998:998) (1049:1049:1049)) - (PORT datac (1153:1153:1153) (1230:1230:1230)) - (PORT datad (918:918:918) (956:956:956)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1216:1216:1216) (1294:1294:1294)) + (PORT datab (962:962:962) (1013:1013:1013)) + (PORT datac (1128:1128:1128) (1160:1160:1160)) + (PORT datad (978:978:978) (1039:1039:1039)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59012,11 +62074,11 @@ (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1368:1368:1368)) + (PORT clk (1352:1352:1352) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (472:472:472) (503:503:503)) - (PORT sload (1552:1552:1552) (1520:1520:1520)) - (PORT ena (1182:1182:1182) (1169:1169:1169)) + (PORT asdata (1285:1285:1285) (1264:1264:1264)) + (PORT sload (2000:2000:2000) (1981:1981:1981)) + (PORT ena (1127:1127:1127) (1111:1111:1111)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -59029,15 +62091,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~2) + (INSTANCE sdram_\|Mux23\~3) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1288:1288:1288)) - (PORT datab (332:332:332) (356:356:356)) - (PORT datac (890:890:890) (926:926:926)) - (PORT datad (908:908:908) (960:960:960)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (1335:1335:1335) (1335:1335:1335)) + (PORT datab (629:629:629) (637:637:637)) + (PORT datac (868:868:868) (893:893:893)) + (PORT datad (1682:1682:1682) (1748:1748:1748)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59045,44 +62107,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~3) + (INSTANCE sdram_\|Mux23\~4) (DELAY (ABSOLUTE - (PORT dataa (1213:1213:1213) (1289:1289:1289)) - (PORT datac (487:487:487) (478:478:478)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (608:608:608) (628:628:628)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1307:1307:1307) (1301:1301:1301)) + (PORT datad (985:985:985) (1032:1032:1032)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~1) + (INSTANCE sdram_\|Mux23\~2) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1287:1287:1287)) - (PORT datab (2416:2416:2416) (2514:2514:2514)) - (PORT datac (1607:1607:1607) (1622:1622:1622)) - (PORT datad (911:911:911) (967:967:967)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1028:1028:1028) (1082:1082:1082)) + (PORT datab (843:843:843) (861:861:861)) + (PORT datac (666:666:666) (722:722:722)) + (PORT datad (833:833:833) (873:873:873)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~1) + (INSTANCE sdram_\|Mux23\~5) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (299:299:299)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1332:1332:1332) (1333:1333:1333)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (315:315:315) (325:325:325)) + (PORT datad (984:984:984) (1034:1034:1034)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59092,12 +62158,12 @@ (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (187:187:187) (222:222:222)) - (PORT datac (935:935:935) (997:997:997)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT datab (616:616:616) (624:624:624)) + (PORT datac (1189:1189:1189) (1263:1263:1263)) + (PORT datad (565:565:565) (575:575:575)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -59107,8 +62173,8 @@ (DELAY (ABSOLUTE (PORT clk (1339:1339:1339) (1359:1359:1359)) - (PORT d (1386:1386:1386) (1431:1431:1431)) - (PORT ena (1771:1771:1771) (1743:1743:1743)) + (PORT d (1625:1625:1625) (1685:1685:1685)) + (PORT ena (2029:2029:2029) (1999:1999:1999)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59119,91 +62185,17 @@ (HOLD ena (posedge clk) (86:86:86)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1279:1279:1279)) - (PORT datab (953:953:953) (991:991:991)) - (PORT datac (935:935:935) (999:999:999)) - (PORT datad (913:913:913) (970:970:970)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (953:953:953) (989:989:989)) - (PORT datad (1185:1185:1185) (1248:1248:1248)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux21\~0) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (260:260:260)) - (PORT datab (985:985:985) (1059:1059:1059)) - (PORT datac (292:292:292) (295:295:295)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux22\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (657:657:657)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (808:808:808) (811:811:811)) - (PORT datad (589:589:589) (590:590:590)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1688:1688:1688) (1756:1756:1756)) - (PORT datab (933:933:933) (1004:1004:1004)) - (PORT datac (716:716:716) (793:793:793)) - (PORT datad (720:720:720) (795:795:795)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~11) (DELAY (ABSOLUTE - (PORT datab (746:746:746) (819:819:819)) - (PORT datac (1713:1713:1713) (1779:1779:1779)) - (PORT datad (907:907:907) (968:968:968)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1507:1507:1507) (1564:1564:1564)) + (PORT datab (1007:1007:1007) (1105:1105:1105)) + (PORT datac (961:961:961) (1016:1016:1016)) + (PORT datad (1107:1107:1107) (1135:1135:1135)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59214,12 +62206,8 @@ (INSTANCE sdram_\|r\.address\[3\]\~12) (DELAY (ABSOLUTE - (PORT dataa (840:840:840) (861:861:861)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (1714:1714:1714) (1776:1776:1776)) - (PORT datad (1135:1135:1135) (1180:1180:1180)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT datac (932:932:932) (985:985:985)) + (PORT datad (979:979:979) (1039:1039:1039)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59227,31 +62215,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~13) + (INSTANCE sdram_\|Mux21\~0) (DELAY (ABSOLUTE - (PORT dataa (1210:1210:1210) (1275:1275:1275)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1296:1296:1296) (1317:1317:1317)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (830:830:830) (823:823:823)) + (PORT datab (1201:1201:1201) (1245:1245:1245)) + (PORT datac (877:877:877) (896:896:896)) + (PORT datad (832:832:832) (820:820:820)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1488:1488:1488)) + (PORT datab (1095:1095:1095) (1086:1086:1086)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (790:790:790) (800:800:800)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1689:1689:1689) (1755:1755:1755)) - (PORT datab (933:933:933) (1002:1002:1002)) - (PORT datac (716:716:716) (791:791:791)) - (PORT datad (721:721:721) (793:793:793)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT datab (1257:1257:1257) (1293:1293:1293)) + (PORT datac (894:894:894) (934:934:934)) + (PORT datad (957:957:957) (1030:1030:1030)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59262,13 +62264,29 @@ (INSTANCE sdram_\|r\.address\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (845:845:845) (863:863:863)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (1296:1296:1296) (1316:1316:1316)) - (PORT datad (908:908:908) (967:967:967)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1192:1192:1192) (1216:1216:1216)) + (PORT datab (1259:1259:1259) (1294:1294:1294)) + (PORT datac (809:809:809) (837:837:837)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1020:1020:1020)) + (PORT datab (984:984:984) (1061:1061:1061)) + (PORT datac (893:893:893) (929:929:929)) + (PORT datad (1209:1209:1209) (1235:1235:1235)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59278,13 +62296,13 @@ (INSTANCE sdram_\|r\.address\[3\]\~16) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1131:1131:1131) (1176:1176:1176)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1191:1191:1191) (1216:1216:1216)) + (PORT datab (1179:1179:1179) (1218:1218:1218)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59292,13 +62310,61 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1330:1330:1330)) + (PORT datab (841:841:841) (882:882:882)) + (PORT datac (1159:1159:1159) (1222:1222:1222)) + (PORT datad (1463:1463:1463) (1494:1494:1494)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1254:1254:1254) (1332:1332:1332)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (1422:1422:1422) (1496:1496:1496)) + (PORT datad (794:794:794) (780:780:780)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~19) (DELAY (ABSOLUTE (PORT dataa (184:184:184) (221:221:221)) - (PORT datac (908:908:908) (978:978:978)) - (PORT datad (158:158:158) (178:178:178)) + (PORT datab (1461:1461:1461) (1513:1513:1513)) + (PORT datac (746:746:746) (726:726:726)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1274:1274:1274)) + (PORT datac (565:565:565) (585:585:585)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59309,8 +62375,8 @@ (DELAY (ABSOLUTE (PORT clk (1339:1339:1339) (1359:1359:1359)) - (PORT d (1691:1691:1691) (1769:1769:1769)) - (PORT ena (1674:1674:1674) (1638:1638:1638)) + (PORT d (1458:1458:1458) (1566:1566:1566)) + (PORT ena (1566:1566:1566) (1574:1574:1574)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59326,13 +62392,13 @@ (INSTANCE sdram_\|Mux21\~1) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (653:653:653)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (591:591:591) (593:593:593)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1470:1470:1470) (1483:1483:1483)) + (PORT datab (1365:1365:1365) (1354:1354:1354)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (793:793:793) (799:799:799)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59343,8 +62409,8 @@ (DELAY (ABSOLUTE (PORT clk (1338:1338:1338) (1358:1358:1358)) - (PORT d (1422:1422:1422) (1472:1472:1472)) - (PORT ena (1482:1482:1482) (1446:1446:1446)) + (PORT d (1151:1151:1151) (1187:1187:1187)) + (PORT ena (1447:1447:1447) (1413:1413:1413)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59355,47 +62421,33 @@ (HOLD ena (posedge clk) (86:86:86)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~7) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (889:889:889)) + (PORT datab (718:718:718) (775:775:775)) + (PORT datac (841:841:841) (876:876:876)) + (PORT datad (1025:1025:1025) (1089:1089:1089)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux20\~4) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (773:773:773)) - (PORT datab (713:713:713) (777:777:777)) - (PORT datad (245:245:245) (316:316:316)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~7) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (987:987:987)) - (PORT datab (2453:2453:2453) (2560:2560:2560)) - (PORT datac (1557:1557:1557) (1658:1658:1658)) - (PORT datad (862:862:862) (879:879:879)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~7) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (820:820:820)) - (PORT datab (839:839:839) (822:822:822)) - (PORT datac (1162:1162:1162) (1238:1238:1238)) - (PORT datad (762:762:762) (752:752:752)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1762:1762:1762) (1845:1845:1845)) + (PORT datab (565:565:565) (573:573:573)) + (PORT datac (1506:1506:1506) (1569:1569:1569)) + (PORT datad (210:210:210) (276:276:276)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59403,31 +62455,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~8) + (INSTANCE sdram_\|Mux20\~2) (DELAY (ABSOLUTE - (PORT dataa (953:953:953) (1002:1002:1002)) - (PORT datab (882:882:882) (889:889:889)) - (PORT datac (1153:1153:1153) (1234:1234:1234)) - (PORT datad (1147:1147:1147) (1199:1199:1199)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1567:1567:1567) (1647:1647:1647)) + (PORT datab (235:235:235) (310:310:310)) + (PORT datac (1035:1035:1035) (1040:1040:1040)) + (PORT datad (609:609:609) (631:631:631)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~10) + (INSTANCE sdram_\|Mux20\~3) (DELAY (ABSOLUTE - (PORT dataa (1178:1178:1178) (1244:1244:1244)) - (PORT datab (606:606:606) (632:632:632)) - (PORT datac (540:540:540) (529:529:529)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (1568:1568:1568) (1648:1648:1648)) + (PORT datac (799:799:799) (802:802:802)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59435,15 +62485,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~9) + (INSTANCE sdram_\|r\.address\[4\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1174:1174:1174) (1237:1237:1237)) - (PORT datab (608:608:608) (636:636:636)) - (PORT datac (539:539:539) (526:526:526)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (307:307:307) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (1443:1443:1443) (1502:1502:1502)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59451,16 +62499,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~11) + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (437:437:437)) - (PORT datab (833:833:833) (849:849:849)) - (PORT datac (295:295:295) (304:304:304)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (166:166:166) (189:189:189)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59470,11 +62512,11 @@ (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1379:1379:1379)) + (PORT clk (1349:1349:1349) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (628:628:628) (625:625:625)) - (PORT sload (1515:1515:1515) (1612:1612:1612)) - (PORT ena (894:894:894) (882:882:882)) + (PORT asdata (473:473:473) (501:501:501)) + (PORT sload (2006:2006:2006) (2114:2114:2114)) + (PORT ena (1346:1346:1346) (1335:1335:1335)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -59487,14 +62529,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~12) + (INSTANCE sdram_\|Mux20\~5) (DELAY (ABSOLUTE - (PORT dataa (668:668:668) (720:720:720)) - (PORT datab (1919:1919:1919) (1988:1988:1988)) - (PORT datac (2115:2115:2115) (2205:2205:2205)) - (PORT datad (801:801:801) (815:815:815)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (1152:1152:1152) (1177:1177:1177)) + (PORT datab (1202:1202:1202) (1240:1240:1240)) + (PORT datac (1377:1377:1377) (1429:1429:1429)) + (PORT datad (1232:1232:1232) (1306:1306:1306)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -59503,16 +62545,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~5) + (INSTANCE sdram_\|Mux20\~10) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (597:597:597) (623:623:623)) - (PORT datac (1458:1458:1458) (1518:1518:1518)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1150:1150:1150) (1175:1175:1175)) + (PORT datab (1442:1442:1442) (1502:1502:1502)) + (PORT datac (1377:1377:1377) (1427:1427:1427)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59522,27 +62564,57 @@ (INSTANCE sdram_\|Mux20\~6) (DELAY (ABSOLUTE - (PORT dataa (584:584:584) (586:586:586)) - (PORT datab (834:834:834) (851:851:851)) - (PORT datac (915:915:915) (966:966:966)) - (PORT datad (356:356:356) (399:399:399)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (208:208:208) (244:244:244)) + (PORT datac (405:405:405) (466:466:466)) + (PORT datad (636:636:636) (669:669:669)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[4\]\~2) + (INSTANCE sdram_\|Mux20\~7) (DELAY (ABSOLUTE - (PORT dataa (1173:1173:1173) (1236:1236:1236)) - (PORT datab (567:567:567) (588:588:588)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (1567:1567:1567) (1646:1646:1646)) + (PORT datab (1256:1256:1256) (1338:1338:1338)) + (PORT datac (338:338:338) (345:345:345)) + (PORT datad (1418:1418:1418) (1467:1467:1467)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (250:250:250)) + (PORT datab (190:190:190) (224:224:224)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1417:1417:1417) (1467:1467:1467)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT datab (234:234:234) (307:307:307)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59552,10 +62624,10 @@ (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (998:998:998) (1050:1050:1050)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (179:179:179) (200:200:200)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1494:1494:1494) (1559:1559:1559)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59567,8 +62639,8 @@ (DELAY (ABSOLUTE (PORT clk (1340:1340:1340) (1360:1360:1360)) - (PORT d (1565:1565:1565) (1579:1579:1579)) - (PORT ena (2120:2120:2120) (2104:2104:2104)) + (PORT d (1532:1532:1532) (1548:1548:1548)) + (PORT ena (2410:2410:2410) (2357:2357:2357)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59579,48 +62651,16 @@ (HOLD ena (posedge clk) (86:86:86)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (775:775:775)) - (PORT datab (714:714:714) (778:778:778)) - (PORT datac (574:574:574) (601:601:601)) - (PORT datad (247:247:247) (315:315:315)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~4) (DELAY (ABSOLUTE - (PORT dataa (1174:1174:1174) (1238:1238:1238)) - (PORT datac (539:539:539) (528:528:528)) - (PORT datad (551:551:551) (547:547:547)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1243:1243:1243)) - (PORT datab (977:977:977) (1024:1024:1024)) - (PORT datac (1156:1156:1156) (1231:1231:1231)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (203:203:203) (241:241:241)) + (PORT datac (562:562:562) (555:555:555)) + (PORT datad (1401:1401:1401) (1440:1440:1440)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59630,10 +62670,10 @@ (INSTANCE sdram_\|Mux19\~6) (DELAY (ABSOLUTE - (PORT dataa (1179:1179:1179) (1246:1246:1246)) - (PORT datab (978:978:978) (1026:1026:1026)) - (PORT datac (1153:1153:1153) (1235:1235:1235)) - (PORT datad (167:167:167) (191:191:191)) + (PORT dataa (1321:1321:1321) (1407:1407:1407)) + (PORT datab (1507:1507:1507) (1566:1566:1566)) + (PORT datac (327:327:327) (336:336:336)) + (PORT datad (1274:1274:1274) (1319:1319:1319)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -59641,17 +62681,33 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1400:1400:1400)) + (PORT datab (1503:1503:1503) (1559:1559:1559)) + (PORT datac (328:328:328) (337:337:337)) + (PORT datad (1275:1275:1275) (1316:1316:1316)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~7) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1274:1274:1274)) - (PORT datab (369:369:369) (427:427:427)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (375:375:375) (422:422:422)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1279:1279:1279) (1285:1285:1285)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59662,11 +62718,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1379:1379:1379)) + (PORT clk (1350:1350:1350) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (474:474:474) (503:503:503)) - (PORT sload (1515:1515:1515) (1612:1612:1612)) - (PORT ena (894:894:894) (882:882:882)) + (PORT asdata (625:625:625) (631:631:631)) + (PORT sload (1757:1757:1757) (1857:1857:1857)) + (PORT ena (1398:1398:1398) (1400:1400:1400)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -59679,13 +62735,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~2) + (INSTANCE sdram_\|Mux19\~1) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (823:823:823) (849:849:849)) - (PORT datac (1456:1456:1456) (1518:1518:1518)) - (PORT datad (583:583:583) (629:629:629)) + (PORT dataa (596:596:596) (614:614:614)) + (PORT datab (1092:1092:1092) (1121:1121:1121)) + (PORT datac (348:348:348) (394:394:394)) + (PORT datad (1274:1274:1274) (1316:1316:1316)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -59693,18 +62749,34 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (903:903:903)) + (PORT datab (1073:1073:1073) (1142:1142:1142)) + (PORT datac (691:691:691) (745:745:745)) + (PORT datad (1017:1017:1017) (1081:1081:1081)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~3) (DELAY (ABSOLUTE - (PORT dataa (583:583:583) (583:583:583)) - (PORT datab (980:980:980) (1025:1025:1025)) - (PORT datac (1258:1258:1258) (1241:1241:1241)) - (PORT datad (346:346:346) (395:395:395)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (577:577:577) (577:577:577)) + (PORT datab (375:375:375) (419:419:419)) + (PORT datac (561:561:561) (567:567:567)) + (PORT datad (1278:1278:1278) (1283:1283:1283)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59714,11 +62786,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1180:1180:1180) (1244:1244:1244)) - (PORT datab (602:602:602) (607:607:607)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (1505:1505:1505) (1567:1567:1567)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59728,12 +62800,12 @@ (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (999:999:999) (1055:1055:1055)) - (PORT datac (163:163:163) (197:197:197)) + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1231:1231:1231) (1301:1301:1301)) + (PORT datad (178:178:178) (199:199:199)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -59743,8 +62815,8 @@ (DELAY (ABSOLUTE (PORT clk (1337:1337:1337) (1357:1357:1357)) - (PORT d (1320:1320:1320) (1356:1356:1356)) - (PORT ena (2030:2030:2030) (1971:1971:1971)) + (PORT d (1145:1145:1145) (1194:1194:1194)) + (PORT ena (1800:1800:1800) (1793:1793:1793)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59760,9 +62832,9 @@ (INSTANCE sdram_\|Mux18\~0) (DELAY (ABSOLUTE - (PORT dataa (2228:2228:2228) (2383:2383:2383)) - (PORT datac (1144:1144:1144) (1206:1206:1206)) - (PORT datad (613:613:613) (614:614:614)) + (PORT dataa (1237:1237:1237) (1348:1348:1348)) + (PORT datac (1046:1046:1046) (1085:1085:1085)) + (PORT datad (1423:1423:1423) (1447:1447:1447)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -59775,8 +62847,8 @@ (DELAY (ABSOLUTE (PORT clk (1338:1338:1338) (1358:1358:1358)) - (PORT d (1406:1406:1406) (1451:1451:1451)) - (PORT ena (1482:1482:1482) (1446:1446:1446)) + (PORT d (1364:1364:1364) (1416:1416:1416)) + (PORT ena (1447:1447:1447) (1413:1413:1413)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59789,12 +62861,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux17\~0) + (INSTANCE sdram_\|Mux17\~2) (DELAY (ABSOLUTE - (PORT dataa (2225:2225:2225) (2380:2380:2380)) - (PORT datac (1400:1400:1400) (1411:1411:1411)) - (PORT datad (613:613:613) (613:613:613)) + (PORT dataa (1237:1237:1237) (1346:1346:1346)) + (PORT datac (814:814:814) (860:860:860)) + (PORT datad (1425:1425:1425) (1441:1441:1441)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -59807,8 +62879,8 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1356:1356:1356)) - (PORT d (1841:1841:1841) (1877:1877:1877)) - (PORT ena (1484:1484:1484) (1508:1508:1508)) + (PORT d (1750:1750:1750) (1812:1812:1812)) + (PORT ena (1648:1648:1648) (1638:1638:1638)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -59821,12 +62893,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux16\~0) + (INSTANCE sdram_\|Mux16\~2) (DELAY (ABSOLUTE - (PORT dataa (2235:2235:2235) (2391:2391:2391)) - (PORT datac (219:219:219) (288:288:288)) - (PORT datad (613:613:613) (614:614:614)) + (PORT dataa (1240:1240:1240) (1346:1346:1346)) + (PORT datac (1068:1068:1068) (1081:1081:1081)) + (PORT datad (1426:1426:1426) (1447:1447:1447)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -59839,8 +62911,8 @@ (DELAY (ABSOLUTE (PORT clk (1326:1326:1326) (1342:1342:1342)) - (PORT d (1957:1957:1957) (2019:2019:2019)) - (PORT ena (1306:1306:1306) (1295:1295:1295)) + (PORT d (1656:1656:1656) (1712:1712:1712)) + (PORT ena (1638:1638:1638) (1653:1653:1653)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -59856,11 +62928,11 @@ (INSTANCE sdram_\|Mux15\~2) (DELAY (ABSOLUTE - (PORT dataa (2237:2237:2237) (2391:2391:2391)) - (PORT datab (864:864:864) (921:921:921)) - (PORT datad (614:614:614) (619:619:619)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1232:1232:1232) (1341:1341:1341)) + (PORT datac (1310:1310:1310) (1292:1292:1292)) + (PORT datad (1423:1423:1423) (1441:1441:1441)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -59871,8 +62943,8 @@ (DELAY (ABSOLUTE (PORT clk (1328:1328:1328) (1344:1344:1344)) - (PORT d (1962:1962:1962) (2046:2046:2046)) - (PORT ena (1339:1339:1339) (1340:1340:1340)) + (PORT d (1877:1877:1877) (1918:1918:1918)) + (PORT ena (1639:1639:1639) (1642:1642:1642)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -59885,79 +62957,23 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~0) + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (650:650:650)) - (PORT datab (649:649:649) (721:721:721)) - (PORT datac (1155:1155:1155) (1214:1214:1214)) - (PORT datad (166:166:166) (187:187:187)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datad (164:164:164) (188:188:188)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~1) + (INSTANCE sdram_\|n\~5) (DELAY (ABSOLUTE - (PORT dataa (634:634:634) (645:645:645)) - (PORT datab (375:375:375) (422:422:422)) - (PORT datac (954:954:954) (1014:1014:1014)) - (PORT datad (586:586:586) (586:586:586)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[10\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (901:901:901) (970:970:970)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (472:472:472) (501:501:501)) - (PORT sload (1491:1491:1491) (1583:1583:1583)) - (PORT ena (1138:1138:1138) (1126:1126:1126)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~4) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (817:817:817)) - (PORT datab (373:373:373) (420:420:420)) - (PORT datac (624:624:624) (668:668:668)) - (PORT datad (627:627:627) (647:647:647)) + (PORT dataa (873:873:873) (889:889:889)) + (PORT datab (720:720:720) (772:772:772)) + (PORT datac (845:845:845) (877:877:877)) + (PORT datad (376:376:376) (410:410:410)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -59970,12 +62986,12 @@ (INSTANCE sdram_\|Mux14\~2) (DELAY (ABSOLUTE - (PORT dataa (641:641:641) (654:654:654)) - (PORT datab (650:650:650) (721:721:721)) - (PORT datac (1152:1152:1152) (1217:1217:1217)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (867:867:867) (924:924:924)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (175:175:175) (214:214:214)) + (PORT datad (1024:1024:1024) (1088:1088:1088)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -59986,28 +63002,94 @@ (INSTANCE sdram_\|Mux14\~3) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (372:372:372) (418:418:418)) - (PORT datac (347:347:347) (362:362:362)) - (PORT datad (591:591:591) (589:589:589)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (616:616:616) (626:626:626)) + (PORT datab (246:246:246) (319:319:319)) + (PORT datac (182:182:182) (216:216:216)) + (PORT datad (298:298:298) (291:291:291)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (472:472:472) (501:501:501)) + (PORT sload (1742:1742:1742) (1854:1854:1854)) + (PORT ena (764:764:764) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (545:545:545)) + (PORT datab (244:244:244) (316:316:316)) + (PORT datac (976:976:976) (1029:1029:1029)) + (PORT datad (592:592:592) (591:591:591)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (930:930:930)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (174:174:174) (215:215:215)) + (PORT datad (1024:1024:1024) (1089:1089:1089)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (1000:1000:1000) (1065:1065:1065)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (304:304:304) (310:310:310)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (975:975:975) (1027:1027:1027)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1213:1213:1213) (1300:1300:1300)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (162:162:162) (196:196:196)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -60017,8 +63099,8 @@ (DELAY (ABSOLUTE (PORT clk (1319:1319:1319) (1334:1334:1334)) - (PORT d (1341:1341:1341) (1380:1380:1380)) - (PORT ena (1549:1549:1549) (1506:1506:1506)) + (PORT d (1427:1427:1427) (1491:1491:1491)) + (PORT ena (1540:1540:1540) (1531:1531:1531)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -60031,14 +63113,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~18) + (INSTANCE sdram_\|r\.address\[11\]\~21) (DELAY (ABSOLUTE - (PORT datab (696:696:696) (760:760:760)) - (PORT datac (1161:1161:1161) (1230:1230:1230)) - (PORT datad (672:672:672) (730:730:730)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1319:1319:1319) (1400:1400:1400)) + (PORT datab (1502:1502:1502) (1558:1558:1558)) + (PORT datac (1004:1004:1004) (1000:1000:1000)) + (PORT datad (612:612:612) (640:640:640)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (1501:1501:1501) (1562:1562:1562)) + (PORT datac (1680:1680:1680) (1715:1715:1715)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -60048,37 +63146,26 @@ (INSTANCE sdram_\|r\.address\[11\]\~5) (DELAY (ABSOLUTE - (PORT dataa (922:922:922) (965:965:965)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (203:203:203) (274:274:274)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (1508:1508:1508) (1566:1566:1566)) + (PORT datad (532:532:532) (534:534:534)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (238:238:238)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1377:1377:1377)) + (PORT clk (1350:1350:1350) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (480:480:480) (516:516:516)) - (PORT sload (1199:1199:1199) (1301:1301:1301)) - (PORT ena (1179:1179:1179) (1184:1184:1184)) + (PORT asdata (806:806:806) (787:787:787)) + (PORT sload (1757:1757:1757) (1857:1857:1857)) + (PORT ena (1165:1165:1165) (1147:1147:1147)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -60094,11 +63181,11 @@ (INSTANCE sdram_\|Mux13\~10) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (298:298:298)) - (PORT datac (702:702:702) (786:786:786)) - (PORT datad (625:625:625) (687:687:687)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1320:1320:1320) (1404:1404:1404)) + (PORT datac (195:195:195) (262:262:262)) + (PORT datad (1469:1469:1469) (1529:1529:1529)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -60108,13 +63195,13 @@ (INSTANCE sdram_\|Mux13\~6) (DELAY (ABSOLUTE - (PORT dataa (722:722:722) (813:813:813)) - (PORT datab (837:837:837) (819:819:819)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (760:760:760) (750:750:750)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (579:579:579) (577:577:577)) + (PORT datab (1097:1097:1097) (1126:1126:1126)) + (PORT datac (1285:1285:1285) (1372:1372:1372)) + (PORT datad (297:297:297) (292:292:292)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -60124,12 +63211,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (243:243:243)) - (PORT datab (674:674:674) (748:748:748)) - (PORT datac (171:171:171) (210:210:210)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (205:205:205) (242:242:242)) + (PORT datac (1201:1201:1201) (1273:1273:1273)) + (PORT datad (296:296:296) (302:302:302)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -60138,9 +63225,9 @@ (INSTANCE sdram_\|r\.address\[11\]) (DELAY (ABSOLUTE - (PORT clk (1332:1332:1332) (1350:1350:1350)) - (PORT d (1146:1146:1146) (1213:1213:1213)) - (PORT ena (1296:1296:1296) (1252:1252:1252)) + (PORT clk (1322:1322:1322) (1337:1337:1337)) + (PORT d (1410:1410:1410) (1490:1490:1490)) + (PORT ena (2072:2072:2072) (2040:2040:2040)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) @@ -60156,12 +63243,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (197:197:197) (240:240:240)) - (PORT datab (674:674:674) (744:744:744)) - (PORT datac (170:170:170) (208:208:208)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (204:204:204) (242:242:242)) + (PORT datac (1201:1201:1201) (1273:1273:1273)) + (PORT datad (296:296:296) (303:303:303)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -60171,8 +63258,8 @@ (DELAY (ABSOLUTE (PORT clk (1324:1324:1324) (1339:1339:1339)) - (PORT d (1564:1564:1564) (1606:1606:1606)) - (PORT ena (1576:1576:1576) (1542:1542:1542)) + (PORT d (1623:1623:1623) (1674:1674:1674)) + (PORT ena (2061:2061:2061) (2033:2033:2033)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index ca61a7e..e8ca7af 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/02/2022 14:51:20" +// DATE "04/06/2022 13:58:27" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -60,14 +60,18 @@ module spectrum ( DRAM_WE_N, DRAM_CS_N, DRAM_DQ, - DRAM_ADDR); + DRAM_ADDR, + kempston, + kempston_gnd, + turbo_button, + kempston_autofire_button); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -80,7 +84,7 @@ output [3:0] VGA_B; output VGA_HS; output VGA_VS; input [3:0] SW; -output [33:0] GPIO_1; +output [31:0] GPIO_1; output buzzer_out; input raw_loader_in; output [1:0] DRAM_BA; @@ -91,8 +95,12 @@ output DRAM_CKE; output DRAM_CLK; output DRAM_WE_N; output DRAM_CS_N; -inout [15:0] DRAM_DQ; +output [15:0] DRAM_DQ; output [12:0] DRAM_ADDR; +input [4:0] kempston; +output kempston_gnd; +input turbo_button; +input kempston_autofire_button; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -123,6 +131,7 @@ output [12:0] DRAM_ADDR; // VGA_HS => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // VGA_VS => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[0] => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[3] => Location: PIN_M15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // GPIO_1[0] => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[1] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -156,8 +165,6 @@ output [12:0] DRAM_ADDR; // GPIO_1[29] => Location: PIN_L13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[30] => Location: PIN_J16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[31] => Location: PIN_K15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -182,6 +189,7 @@ output [12:0] DRAM_ADDR; // DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// kempston_gnd => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -201,10 +209,16 @@ output [12:0] DRAM_ADDR; // DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[0] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[1] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[2] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[3] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[4] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// turbo_button => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston_autofire_button => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -227,6 +241,7 @@ initial $sdf_annotate("spectrum_6_1200mv_85c_v_slow.sdo"); // synopsys translate_on wire \SW[0]~input_o ; +wire \SW[2]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; wire \DRAM_DQ[0]~input_o ; @@ -248,13 +263,69 @@ wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \turbo_button~input_o ; +wire \CLOCK_50~inputclkctrl_outclk ; +wire \debounce_turbo|r_Count[0]~21_combout ; +wire \debounce_turbo|r_Count[0]~22 ; +wire \debounce_turbo|r_Count[1]~23_combout ; +wire \debounce_turbo|r_Count[1]~24 ; +wire \debounce_turbo|r_Count[2]~25_combout ; +wire \debounce_turbo|r_Count[2]~26 ; +wire \debounce_turbo|r_Count[3]~27_combout ; +wire \debounce_turbo|r_Count[3]~28 ; +wire \debounce_turbo|r_Count[4]~29_combout ; +wire \debounce_turbo|r_Count[4]~30 ; +wire \debounce_turbo|r_Count[5]~31_combout ; +wire \debounce_turbo|r_Count[5]~32 ; +wire \debounce_turbo|r_Count[6]~33_combout ; +wire \debounce_turbo|r_Count[6]~34 ; +wire \debounce_turbo|r_Count[7]~35_combout ; +wire \debounce_turbo|r_Count[7]~36 ; +wire \debounce_turbo|r_Count[8]~37_combout ; +wire \debounce_turbo|r_Count[8]~38 ; +wire \debounce_turbo|r_Count[9]~39_combout ; +wire \debounce_turbo|r_Count[9]~40 ; +wire \debounce_turbo|r_Count[10]~41_combout ; +wire \debounce_turbo|r_Count[10]~42 ; +wire \debounce_turbo|r_Count[11]~43_combout ; +wire \debounce_turbo|r_Count[11]~44 ; +wire \debounce_turbo|r_Count[12]~45_combout ; +wire \debounce_turbo|r_Count[12]~46 ; +wire \debounce_turbo|r_Count[13]~47_combout ; +wire \debounce_turbo|r_State~7_combout ; +wire \debounce_turbo|LessThan0~0_combout ; +wire \debounce_turbo|LessThan0~1_combout ; +wire \debounce_turbo|r_Count[13]~48 ; +wire \debounce_turbo|r_Count[14]~49_combout ; +wire \debounce_turbo|r_Count[14]~50 ; +wire \debounce_turbo|r_Count[15]~51_combout ; +wire \debounce_turbo|r_Count[15]~52 ; +wire \debounce_turbo|r_Count[16]~53_combout ; +wire \debounce_turbo|r_Count[16]~54 ; +wire \debounce_turbo|r_Count[17]~55_combout ; +wire \debounce_turbo|r_Count[17]~56 ; +wire \debounce_turbo|r_Count[18]~57_combout ; +wire \debounce_turbo|r_Count[18]~58 ; +wire \debounce_turbo|r_Count[19]~59_combout ; +wire \debounce_turbo|always0~0_combout ; +wire \debounce_turbo|always0~1_combout ; +wire \debounce_turbo|r_Count[19]~60 ; +wire \debounce_turbo|r_Count[20]~61_combout ; +wire \debounce_turbo|always0~2_combout ; +wire \debounce_turbo|r_State~4_combout ; +wire \debounce_turbo|r_State~2_combout ; +wire \debounce_turbo|r_State~0_combout ; +wire \debounce_turbo|r_State~1_combout ; +wire \debounce_turbo|r_State~3_combout ; +wire \debounce_turbo|r_State~5_combout ; +wire \debounce_turbo|r_State~6_combout ; +wire \debounce_turbo|r_State~q ; +wire \turbo~0_combout ; +wire \turbo~q ; wire \ula_|clocks_|counter[0]~0_combout ; -wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -263,12 +334,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; @@ -279,16 +351,9 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Add0~9 ; -wire \ula_|video_|Add0~10_combout ; -wire \ula_|video_|vga_hc~0_combout ; -wire \ula_|video_|Add0~11 ; -wire \ula_|video_|Add0~12_combout ; -wire \ula_|video_|Add0~13 ; -wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Equal0~1_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; @@ -297,6 +362,30 @@ wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~9 ; +wire \ula_|video_|Add0~10_combout ; +wire \ula_|video_|vga_hc~0_combout ; +wire \ula_|video_|Add0~11 ; +wire \ula_|video_|Add0~12_combout ; +wire \ula_|video_|Add0~13 ; +wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Add1~11 ; +wire \ula_|video_|Add1~12_combout ; +wire \ula_|video_|vga_vc[6]~4_combout ; +wire \ula_|video_|Add1~13 ; +wire \ula_|video_|Add1~14_combout ; +wire \ula_|video_|vga_vc[7]~6_combout ; +wire \ula_|video_|Add1~15 ; +wire \ula_|video_|Add1~16_combout ; +wire \ula_|video_|vga_vc[8]~7_combout ; +wire \ula_|video_|Add1~17 ; +wire \ula_|video_|Add1~18_combout ; +wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; +wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; @@ -312,163 +401,1526 @@ wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; wire \ula_|video_|Add1~10_combout ; wire \ula_|video_|vga_vc[5]~8_combout ; -wire \ula_|video_|Add1~11 ; -wire \ula_|video_|Add1~12_combout ; -wire \ula_|video_|vga_vc[6]~4_combout ; -wire \ula_|video_|Add1~13 ; -wire \ula_|video_|Add1~14_combout ; -wire \ula_|video_|vga_vc[7]~6_combout ; -wire \ula_|video_|Add1~15 ; -wire \ula_|video_|Add1~16_combout ; -wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Add1~17 ; -wire \ula_|video_|Add1~18_combout ; -wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal3~0_combout ; -wire \ula_|video_|Equal2~0_combout ; -wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|ir_|opcode[4]~feeder_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|pla_decode_|Equal1~0_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal1~1_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; wire \z80_|pla_decode_|Equal21~0_combout ; wire \z80_|execute_|ctl_mRead~3_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_sw_1d~2_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_sw_1d~3_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~3_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~2_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_mWrite~19_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_bus_db_oe~8_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; wire \z80_|pla_decode_|Equal9~0_combout ; wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_ir_we~16_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|ctl_inc_cy~97_combout ; -wire \z80_|execute_|ctl_inc_cy~96_combout ; -wire \z80_|execute_|ctl_inc_cy~98_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~17_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|pla_decode_|Equal6~2_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~3_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~16_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_inc_cy~28_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~13_combout ; +wire \z80_|execute_|ctl_ir_we~19_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_inc_cy~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_out_hi~3_combout ; +wire \z80_|execute_|ctl_sw_2u~9_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|pla_decode_|Equal13~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_sw_2u~8_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|ctl_sw_4d~9_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|pla_decode_|Equal1~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_reg_out_hi~2_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~15_combout ; +wire \z80_|execute_|ctl_flags_pf_we~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~1_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_oe~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~50_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~49_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~51_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~48_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~17_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~22_combout ; +wire \z80_|pla_decode_|Equal5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~7_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|ctl_al_we~3_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~2_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~9_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_low[3]~2_combout ; +wire \z80_|alu_|db_low[3]~3_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~24_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~25_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~14_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~22_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~21_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~19_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~8_combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~17_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~18_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~23_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|reg_file_|db_hi_as[0]~3_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|pla_decode_|Equal1~3_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|pla_decode_|Equal2~4_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~29_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~26_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~32_combout ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~30_combout ; +wire \z80_|execute_|ctl_inc_cy~31_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|Q[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~33_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~13_combout ; +wire \z80_|reg_file_|db_lo_as[3]~14_combout ; +wire \z80_|reg_file_|db_lo_as[3]~15_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~58_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~59_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~61_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~62_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~63_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~65_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~70_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~72_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~73_combout ; +wire \z80_|reg_file_|db_lo_as[4]~16_combout ; +wire \z80_|reg_file_|db_lo_as[4]~17_combout ; +wire \z80_|reg_file_|db_lo_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~49_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; +wire \z80_|pla_decode_|Equal72~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|execute_|ctl_mWrite~20_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[0]~4_combout ; +wire \z80_|alu_control_|db[0]~23_combout ; +wire \z80_|alu_control_|db[0]~24_combout ; +wire \z80_|alu_control_|db[0]~25_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ; +wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~83_combout ; +wire \z80_|reg_file_|db_hi_as[7]~23_combout ; +wire \z80_|reg_file_|db_hi_as[7]~24_combout ; +wire \z80_|reg_file_|db_hi_as[7]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~84_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~19_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|db_hi_as[5]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~7_combout ; +wire \z80_|alu_|db_low[2]~8_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~13_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~8_combout ; +wire \z80_|reg_file_|db_lo_ds[5]~0_combout ; +wire \z80_|alu_control_|db[5]~9_combout ; +wire \z80_|alu_control_|db[5]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~48_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~53_combout ; +wire \z80_|reg_file_|db_lo_as[5]~10_combout ; +wire \z80_|reg_file_|db_lo_as[5]~11_combout ; +wire \z80_|reg_file_|db_lo_as[5]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~7_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|alu_|db_low[3]~0_combout ; +wire \z80_|alu_|db_low[3]~1_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_control_|db[2]~26_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~5_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~q ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; +wire \z80_|alu_control_|flags_cond_true~0_combout ; +wire \z80_|alu_control_|flags_cond_true~q ; +wire \z80_|execute_|ctl_reg_sel_wz~28_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~23_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~21_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~13_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|alu_control_|db[7]~14_combout ; +wire \z80_|alu_control_|db[7]~15_combout ; +wire \z80_|bus_control_|db[7]~4_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|nextM~16_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|ctl_ir_we~20_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~38_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; @@ -478,1535 +1930,104 @@ wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|execute_|ctl_mWrite~18_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_flags_alu~21_combout ; -wire \z80_|execute_|ctl_flags_alu~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_alu~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ixy_d~15_combout ; wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; wire \z80_|memory_ifc_|mwr_wr~q ; wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|execute_|ctl_mRead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pla_decode_|Equal40~2_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|pc_inc_hold~14_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_inc_cy~99_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|pla_decode_|Equal76~2_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~11_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|pla_decode_|Equal10~1_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|reg_control_|reg_sel_de2~2_combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_core_hf~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~23_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; -wire \z80_|reg_control_|reg_sel_de2~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; -wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|sw1_|db_down[3]~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~17_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~15_combout ; -wire \z80_|execute_|pc_inc_hold~16_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|execute_|ctl_inc_cy~95_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~100_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~10_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_alu_op_low~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[7]~16_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; -wire \z80_|alu_control_|db[6]~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_control_|db[7]~19_combout ; -wire \z80_|alu_control_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; -wire \z80_|reg_file_|db_hi_as[2]~10_combout ; -wire \z80_|reg_file_|db_hi_as[2]~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; -wire \z80_|reg_file_|db_hi_as[4]~13_combout ; -wire \z80_|reg_file_|db_hi_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[1]~18_combout ; -wire \z80_|alu_|db_low[1]~19_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|db_low[1]~20_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~8_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; -wire \z80_|reg_file_|db_hi_as[6]~19_combout ; -wire \z80_|reg_file_|db_hi_as[6]~20_combout ; -wire \z80_|reg_file_|db_hi_as[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~14_combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; -wire \z80_|reg_file_|db_hi_as[5]~22_combout ; -wire \z80_|reg_file_|db_hi_as[5]~23_combout ; -wire \z80_|reg_file_|db_hi_as[5]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|alu_op1[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|db_low[0]~24_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db_low[0]~25_combout ; -wire \z80_|alu_|db_low[0]~27_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~13_combout ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|alu_|db_high[0]~20_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_low[2]~11_combout ; -wire \z80_|alu_|db_low[2]~12_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~13_combout ; -wire \z80_|alu_|db_low[2]~14_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~24_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_control_|db[2]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~11_combout ; -wire \z80_|alu_control_|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_control_|db[3]~36_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|db_low[3]~5_combout ; -wire \z80_|alu_|db_low[3]~6_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~26_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; -wire \z80_|alu_|alu_op2[3]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_control_|db[4]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; -wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; -wire \z80_|alu_control_|flags_cond_true~0_combout ; -wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~7_combout ; -wire \z80_|reg_file_|db_hi_as[3]~8_combout ; -wire \z80_|reg_file_|db_hi_as[3]~9_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \D[0]~49_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \Equal5~0_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~20_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~43_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; +wire \Equal3~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; +wire \z80_|address_pins_|abus[6]~25_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; +wire \z80_|address_pins_|abus[7]~26_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; +wire \Equal3~1_combout ; +wire \Equal3~2_combout ; +wire \D[5]~26_combout ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|abus[15]~23_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~22_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~44_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~45_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \D[2]~42_combout ; -wire \D[2]~46_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|control_pins_|pin_nIORQ~1_combout ; -wire \Equal2~0_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; wire \ExtRamWE~0_combout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; -wire \z80_|address_pins_|abus[1]~25_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; -wire \z80_|address_pins_|abus[2]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; -wire \z80_|address_pins_|abus[3]~27_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; -wire \z80_|address_pins_|abus[4]~28_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; -wire \z80_|address_pins_|abus[5]~29_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; -wire \z80_|address_pins_|abus[6]~30_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; -wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \D[2]~50_combout ; -wire \D[2]~51_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \CLOCK_50~inputclkctrl_outclk ; +wire \z80_|address_pins_|abus[0]~24_combout ; +wire \z80_|address_pins_|abus[1]~27_combout ; +wire \z80_|address_pins_|abus[2]~28_combout ; +wire \z80_|address_pins_|abus[3]~29_combout ; +wire \z80_|address_pins_|abus[4]~30_combout ; +wire \z80_|address_pins_|abus[5]~31_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~16_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; -wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -2018,521 +2039,710 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[8]~1_combout ; +wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Selector0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \Selector0~1_combout ; +wire \D[7]~36_combout ; +wire \D[7]~37_combout ; +wire \D[7]~48_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[7]~6_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|setM1~59_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal5~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~47_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~48_combout ; -wire \D[2]~49_combout ; -wire \D[2]~119_combout ; -wire \D[2]~52_combout ; -wire \D[2]~53_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; +wire \Selector10~0_combout ; +wire \Selector10~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|keys[3][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~5_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~46_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~4_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~7_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~6_combout ; +wire \Selector14~17_combout ; +wire \Selector14~18_combout ; +wire \kempston[1]~input_o ; +wire \Selector10~2_combout ; +wire \Selector10~3_combout ; +wire \D[2]~13_combout ; wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|ir_|opcode[2]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|sw1_|db_down[6]~1_combout ; -wire \z80_|alu_control_|db[6]~23_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|bus_control_|db[2]~14_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_ir_we~17_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal2~3_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_66_oe~4_combout ; +wire \z80_|alu_control_|db[6]~16_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~2_combout ; +wire \z80_|alu_control_|db[6]~17_combout ; +wire \z80_|alu_control_|db[6]~18_combout ; +wire \z80_|bus_control_|db[6]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \raw_loader_in~input_o ; +wire \D[6]~28_combout ; +wire \D[6]~43_combout ; +wire \D[6]~44_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~103_combout ; -wire \D[6]~104_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~42_combout ; +wire \D[6]~45_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~100_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~101_combout ; -wire \D[6]~102_combout ; -wire \D[6]~127_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~99_combout ; -wire \D[6]~114_combout ; -wire \D[6]~115_combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Mux1~0_combout ; +wire \D[6]~41_combout ; +wire \D[6]~46_combout ; +wire \D[6]~47_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~18_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~16_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~9_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~10_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~130_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~11_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~72_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~69_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~8_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~9_combout ; +wire \kempston[3]~input_o ; +wire \Selector14~8_combout ; +wire \Selector14~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector14~19_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \Selector14~10_combout ; +wire \Selector14~11_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector14~20_combout ; +wire \Selector14~9_combout ; +wire \Selector14~12_combout ; +wire \Selector14~14_combout ; +wire \D[0]~14_combout ; +wire \z80_|bus_control_|db[0]~11_combout ; +wire \z80_|bus_control_|db[0]~12_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~29_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~16_combout ; +wire \debounce_autofire|r_Count[0]~21_combout ; +wire \debounce_autofire|r_Count[0]~22 ; +wire \debounce_autofire|r_Count[1]~23_combout ; +wire \debounce_autofire|r_Count[1]~24 ; +wire \debounce_autofire|r_Count[2]~25_combout ; +wire \debounce_autofire|r_Count[2]~26 ; +wire \debounce_autofire|r_Count[3]~27_combout ; +wire \debounce_autofire|r_Count[3]~28 ; +wire \debounce_autofire|r_Count[4]~29_combout ; +wire \debounce_autofire|r_Count[4]~30 ; +wire \debounce_autofire|r_Count[5]~31_combout ; +wire \debounce_autofire|r_Count[5]~32 ; +wire \debounce_autofire|r_Count[6]~33_combout ; +wire \debounce_autofire|r_Count[6]~34 ; +wire \debounce_autofire|r_Count[7]~35_combout ; +wire \debounce_autofire|r_Count[7]~36 ; +wire \debounce_autofire|r_Count[8]~37_combout ; +wire \debounce_autofire|r_Count[8]~38 ; +wire \debounce_autofire|r_Count[9]~39_combout ; +wire \debounce_autofire|r_Count[9]~40 ; +wire \debounce_autofire|r_Count[10]~41_combout ; +wire \debounce_autofire|r_Count[10]~42 ; +wire \debounce_autofire|r_Count[11]~43_combout ; +wire \debounce_autofire|r_Count[11]~44 ; +wire \debounce_autofire|r_Count[12]~45_combout ; +wire \debounce_autofire|r_Count[12]~46 ; +wire \debounce_autofire|r_Count[13]~47_combout ; +wire \debounce_autofire|r_Count[13]~48 ; +wire \debounce_autofire|r_Count[14]~49_combout ; +wire \debounce_autofire|r_Count[14]~50 ; +wire \debounce_autofire|r_Count[15]~51_combout ; +wire \debounce_autofire|r_Count[15]~52 ; +wire \debounce_autofire|r_Count[16]~53_combout ; +wire \debounce_autofire|r_Count[16]~54 ; +wire \debounce_autofire|r_Count[17]~55_combout ; +wire \debounce_autofire|r_Count[17]~56 ; +wire \debounce_autofire|r_Count[18]~57_combout ; +wire \debounce_autofire|r_Count[18]~58 ; +wire \debounce_autofire|r_Count[19]~59_combout ; +wire \debounce_autofire|r_Count[19]~60 ; +wire \debounce_autofire|r_Count[20]~61_combout ; +wire \kempston_autofire_button~input_o ; +wire \debounce_autofire|r_State~7_combout ; +wire \debounce_autofire|LessThan0~0_combout ; +wire \debounce_autofire|LessThan0~1_combout ; +wire \debounce_autofire|always0~0_combout ; +wire \debounce_autofire|always0~1_combout ; +wire \debounce_autofire|always0~2_combout ; +wire \debounce_autofire|r_State~4_combout ; +wire \debounce_autofire|r_State~5_combout ; +wire \debounce_autofire|r_State~2_combout ; +wire \debounce_autofire|r_State~0_combout ; +wire \debounce_autofire|r_State~1_combout ; +wire \debounce_autofire|r_State~3_combout ; +wire \debounce_autofire|r_State~6_combout ; +wire \debounce_autofire|r_State~q ; +wire \kempston_autofire_enabled~0_combout ; +wire \kempston_autofire_enabled~q ; +wire \kempston_auto_fire_counter[0]~51_combout ; +wire \kempston_auto_fire_counter[1]~17_combout ; +wire \kempston_auto_fire_counter[1]~18 ; +wire \kempston_auto_fire_counter[2]~19_combout ; +wire \kempston_auto_fire_counter[2]~20 ; +wire \kempston_auto_fire_counter[3]~21_combout ; +wire \kempston_auto_fire_counter[3]~22 ; +wire \kempston_auto_fire_counter[4]~23_combout ; +wire \kempston_auto_fire_counter[4]~24 ; +wire \kempston_auto_fire_counter[5]~25_combout ; +wire \kempston_auto_fire_counter[5]~26 ; +wire \kempston_auto_fire_counter[6]~27_combout ; +wire \kempston_auto_fire_counter[6]~28 ; +wire \kempston_auto_fire_counter[7]~29_combout ; +wire \kempston_auto_fire_counter[7]~30 ; +wire \kempston_auto_fire_counter[8]~31_combout ; +wire \kempston_auto_fire_counter[8]~32 ; +wire \kempston_auto_fire_counter[9]~33_combout ; +wire \kempston_auto_fire_counter[9]~34 ; +wire \kempston_auto_fire_counter[10]~35_combout ; +wire \kempston_auto_fire_counter[10]~36 ; +wire \kempston_auto_fire_counter[11]~37_combout ; +wire \kempston_auto_fire_counter[11]~38 ; +wire \kempston_auto_fire_counter[12]~39_combout ; +wire \kempston_auto_fire_counter[12]~40 ; +wire \kempston_auto_fire_counter[13]~41_combout ; +wire \kempston_auto_fire_counter[13]~42 ; +wire \kempston_auto_fire_counter[14]~43_combout ; +wire \kempston_auto_fire_counter[14]~44 ; +wire \kempston_auto_fire_counter[15]~45_combout ; +wire \Equal2~3_combout ; +wire \Equal2~2_combout ; +wire \Equal2~0_combout ; +wire \Equal2~1_combout ; +wire \Equal2~4_combout ; +wire \kempston_auto_fire_counter[15]~46 ; +wire \kempston_auto_fire_counter[16]~47_combout ; +wire \kempston_auto_fire_counter[16]~48 ; +wire \kempston_auto_fire_counter[17]~49_combout ; +wire \kempston_auto_fire~0_combout ; +wire \kempston_auto_fire~q ; +wire \Selector6~2_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~17_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~133_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \Selector6~3_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \Selector6~4_combout ; +wire \Selector6~5_combout ; +wire \kempston[4]~input_o ; +wire \Selector6~6_combout ; +wire \Selector6~7_combout ; +wire \D[4]~39_combout ; +wire \z80_|bus_control_|db[4]~17_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~3_combout ; +wire \z80_|alu_control_|db[1]~20_combout ; +wire \z80_|alu_control_|db[1]~21_combout ; +wire \z80_|alu_control_|db[1]~22_combout ; +wire \z80_|bus_control_|db[1]~9_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~2_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~1_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~38_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~3_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~0_combout ; +wire \kempston[2]~input_o ; +wire \Selector12~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \Selector12~7_combout ; +wire \Selector12~8_combout ; +wire \Selector12~9_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector12~15_combout ; +wire \Selector12~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~14_combout ; +wire \Selector12~6_combout ; +wire \Selector12~11_combout ; +wire \D[1]~12_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|test1~4_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~36_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; -wire \ula_|zx_keyboard_|WideOr16~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~74_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \D[3]~73_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~2_combout ; +wire \z80_|bus_control_|db[0]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector8~5_combout ; +wire \Selector8~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \Selector8~7_combout ; +wire \Selector8~8_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|key_row[3]~15_combout ; wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; wire \ula_|zx_keyboard_|keys[0][3]~q ; wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \D[3]~72_combout ; -wire \D[3]~76_combout ; -wire \D[3]~122_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~79_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~77_combout ; -wire \D[3]~80_combout ; -wire \D[3]~81_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~124_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~123_combout ; -wire \D[3]~78_combout ; -wire \D[3]~82_combout ; -wire \D[3]~108_combout ; -wire \D[3]~109_combout ; +wire \ula_|zx_keyboard_|key_row[3]~12_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~13_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~14_combout ; +wire \kempston[0]~input_o ; +wire \Selector8~4_combout ; +wire \Selector8~9_combout ; +wire \D[3]~38_combout ; +wire \z80_|bus_control_|db[3]~19_combout ; wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; -wire \D[5]~97_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~116_combout ; -wire \D[7]~117_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|ir_|opcode[3]~feeder_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~60_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~17_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|interrupts_|im1~feeder_combout ; wire \z80_|interrupts_|im1~q ; wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~57_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \D[0]~56_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~69_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~71_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~54_combout ; -wire \D[0]~55_combout ; -wire \D[0]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \D[0]~62_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~63_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~59_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~60_combout ; -wire \D[0]~61_combout ; -wire \D[0]~120_combout ; -wire \D[0]~64_combout ; -wire \D[0]~65_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|sw1_|db_down[1]~2_combout ; -wire \z80_|alu_control_|db[1]~27_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|WideOr16~0_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~34_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \D[1]~38_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \D[1]~39_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \D[1]~35_combout ; -wire \D[1]~36_combout ; -wire \D[1]~37_combout ; -wire \D[1]~118_combout ; -wire \D[1]~40_combout ; -wire \D[1]~41_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~88_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~87_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~85_combout ; -wire \D[4]~86_combout ; -wire \D[4]~89_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \D[4]~93_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \D[4]~94_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \D[4]~90_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \D[4]~91_combout ; -wire \D[4]~92_combout ; -wire \D[4]~125_combout ; -wire \D[4]~110_combout ; -wire \D[4]~111_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \z80_|alu_control_|db[5]~16_combout ; -wire \z80_|alu_control_|db[5]~17_combout ; +wire \z80_|bus_control_|db[0]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; -wire \D[5]~112_combout ; -wire \D[5]~113_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[5]~25_combout ; +wire \D[5]~27_combout ; +wire \D[5]~40_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|ena_M~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; +wire \z80_|bus_control_|db[5]~16_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~51_combout ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~47_combout ; wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~55_combout ; wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~66_combout ; -wire \D[0]~67_combout ; -wire \D[0]~121_combout ; -wire \D[1]~68_combout ; -wire \D[1]~69_combout ; -wire \D[2]~70_combout ; -wire \D[2]~71_combout ; -wire \D[3]~83_combout ; -wire \D[3]~84_combout ; -wire \D[4]~95_combout ; -wire \D[4]~96_combout ; -wire \D[5]~126_combout ; -wire \D[5]~98_combout ; -wire \D[6]~105_combout ; -wire \D[6]~106_combout ; -wire \D[7]~128_combout ; -wire \D[7]~107_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ; +wire \Selector14~15_combout ; +wire \Selector14~16_combout ; +wire \D[0]~15_combout ; +wire \D[0]~16_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ; +wire \Selector12~12_combout ; +wire \Selector12~13_combout ; +wire \D[1]~17_combout ; +wire \D[1]~18_combout ; +wire \D[2]~19_combout ; +wire \D[2]~20_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \Selector8~2_combout ; +wire \Selector8~3_combout ; +wire \D[3]~21_combout ; +wire \D[3]~22_combout ; +wire \D[4]~23_combout ; +wire \D[4]~24_combout ; +wire \D[6]~32_combout ; +wire \D[6]~33_combout ; +wire \D[6]~29_combout ; +wire \D[6]~30_combout ; +wire \D[6]~31_combout ; +wire \D[6]~50_combout ; +wire \D[6]~34_combout ; +wire \D[6]~35_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2541,54 +2751,55 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|Mux42~0_combout ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit~4_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; +wire \I2C_SDAT~input_o ; +wire \ula_|i2c_loader_|nbyte[0]~1_combout ; +wire \ula_|i2c_loader_|nbyte[0]~2_combout ; +wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state~24_combout ; wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state.Data~0_combout ; wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~6_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; -wire \I2C_SDAT~input_o ; -wire \ula_|i2c_loader_|nbyte[0]~1_combout ; -wire \ula_|i2c_loader_|nbyte[0]~2_combout ; -wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; -wire \ula_|i2c_loader_|nbyte[1]~5_combout ; +wire \ula_|i2c_loader_|nbyte[0]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; wire \ula_|i2c_loader_|thisbyte[1]~10_combout ; @@ -2596,9 +2807,9 @@ wire \ula_|i2c_loader_|thisbyte[1]~11 ; wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; -wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; +wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|state.Pause~4_combout ; @@ -2611,31 +2822,30 @@ wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~27_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~28_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg~6_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~27_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; -wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; +wire \ula_|i2c_loader_|shiftreg~25_combout ; +wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; +wire \ula_|i2c_loader_|shiftreg[7]~7_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; wire \ula_|i2c_loader_|sda_out~2_combout ; @@ -2644,16 +2854,38 @@ wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \sdram_|Mux38~0_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux38~3_combout ; +wire \sdram_|Mux38~2_combout ; wire \sdram_|r.rd_pending~q ; +wire \sdram_|n~3_combout ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux13~8_combout ; wire \sdram_|r.rf_counter[0]~12_combout ; -wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[8]~32_combout ; wire \sdram_|r.rf_counter[0]~13 ; wire \sdram_|r.rf_counter[1]~14_combout ; wire \sdram_|r.rf_counter[1]~15 ; wire \sdram_|r.rf_counter[2]~16_combout ; wire \sdram_|r.rf_counter[2]~17 ; wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[3]~19 ; wire \sdram_|r.rf_counter[4]~20_combout ; wire \sdram_|r.rf_counter[4]~21 ; @@ -2662,105 +2894,84 @@ wire \sdram_|r.rf_counter[5]~23 ; wire \sdram_|r.rf_counter[6]~24_combout ; wire \sdram_|r.rf_counter[6]~25 ; wire \sdram_|r.rf_counter[7]~26_combout ; -wire \sdram_|Equal0~1_combout ; wire \sdram_|r.rf_counter[7]~27 ; wire \sdram_|r.rf_counter[8]~28_combout ; -wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[8]~29 ; wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~1_combout ; wire \sdram_|Equal0~2_combout ; -wire \sdram_|Mux13~8_combout ; wire \sdram_|Mux37~0_combout ; wire \sdram_|r.rf_pending~q ; -wire \sdram_|Mux4~0_combout ; wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~4_combout ; wire \sdram_|Mux4~2_combout ; -wire \sdram_|Mux4~3_combout ; -wire \sdram_|r.act_row[1]~0_combout ; -wire \sdram_|process_0~2_combout ; -wire \sdram_|r.act_row[1]~1_combout ; -wire \sdram_|r.act_row[2]~feeder_combout ; -wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux4~5_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|r.act_row[2]~0_combout ; +wire \sdram_|r.act_row[2]~1_combout ; wire \sdram_|Equal7~0_combout ; wire \sdram_|Equal7~2_combout ; -wire \sdram_|Mux39~0_combout ; -wire \sdram_|Mux39~1_combout ; -wire \sdram_|Mux39~2_combout ; -wire \sdram_|r.wr_pending~q ; -wire \sdram_|Mux9~8_combout ; -wire \sdram_|Mux9~9_combout ; -wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~2_combout ; wire \sdram_|Mux6~5_combout ; -wire \sdram_|process_0~3_combout ; +wire \sdram_|process_0~2_combout ; wire \sdram_|Mux6~0_combout ; wire \sdram_|Mux6~1_combout ; wire \sdram_|Mux6~6_combout ; -wire \sdram_|r.address[3]~6_combout ; -wire \sdram_|Mux7~2_combout ; -wire \sdram_|n~3_combout ; -wire \sdram_|Mux7~3_combout ; -wire \sdram_|Mux7~4_combout ; -wire \sdram_|Mux7~5_combout ; -wire \sdram_|Mux23~0_combout ; -wire \sdram_|Mux13~7_combout ; -wire \sdram_|Mux10~10_combout ; -wire \sdram_|Mux7~1_combout ; -wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~2_combout ; wire \sdram_|Mux5~10_combout ; wire \sdram_|Mux5~3_combout ; wire \sdram_|Mux5~4_combout ; -wire \sdram_|Mux5~7_combout ; -wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~5_combout ; wire \sdram_|Mux5~6_combout ; wire \sdram_|Mux5~9_combout ; wire \sdram_|n~2_combout ; -wire \sdram_|Mux8~3_combout ; -wire \sdram_|Mux8~4_combout ; -wire \sdram_|Mux9~10_combout ; -wire \sdram_|r.init_counter[0]~0_combout ; -wire \sdram_|Add1~1_cout ; -wire \sdram_|Add1~2_combout ; -wire \sdram_|Add1~3 ; -wire \sdram_|Add1~4_combout ; -wire \sdram_|Add1~5 ; -wire \sdram_|Add1~6_combout ; -wire \sdram_|r.init_counter[3]~1_combout ; -wire \sdram_|Add1~7 ; -wire \sdram_|Add1~8_combout ; -wire \sdram_|Add1~9 ; -wire \sdram_|Add1~10_combout ; -wire \sdram_|Add1~11 ; -wire \sdram_|Add1~12_combout ; -wire \sdram_|Add1~13 ; -wire \sdram_|Add1~14_combout ; -wire \sdram_|Add1~15 ; -wire \sdram_|Add1~16_combout ; -wire \sdram_|Add1~17 ; -wire \sdram_|Add1~18_combout ; -wire \sdram_|Add1~19 ; -wire \sdram_|Add1~20_combout ; -wire \sdram_|Equal2~0_combout ; -wire \sdram_|Equal2~1_combout ; -wire \sdram_|Add1~21 ; -wire \sdram_|Add1~22_combout ; -wire \sdram_|Add1~23 ; -wire \sdram_|Add1~24_combout ; -wire \sdram_|Add1~25 ; -wire \sdram_|Add1~26_combout ; -wire \sdram_|Add1~27 ; -wire \sdram_|Add1~28_combout ; -wire \sdram_|process_0~5_combout ; -wire \sdram_|Equal2~2_combout ; -wire \sdram_|Mux9~11_combout ; -wire \sdram_|Mux9~12_combout ; -wire \sdram_|Mux9~13_combout ; -wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~6_combout ; +wire \sdram_|Mux8~7_combout ; wire \sdram_|Mux8~1_combout ; wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|r.init_counter[0]~44_combout ; +wire \sdram_|r.init_counter[1]~15_cout ; +wire \sdram_|r.init_counter[1]~16_combout ; +wire \sdram_|r.init_counter[1]~17 ; +wire \sdram_|r.init_counter[2]~18_combout ; +wire \sdram_|r.init_counter[2]~19 ; +wire \sdram_|r.init_counter[3]~20_combout ; +wire \sdram_|r.init_counter[3]~21 ; +wire \sdram_|r.init_counter[4]~22_combout ; +wire \sdram_|r.init_counter[4]~23 ; +wire \sdram_|r.init_counter[5]~24_combout ; +wire \sdram_|r.init_counter[5]~25 ; +wire \sdram_|r.init_counter[6]~26_combout ; +wire \sdram_|r.init_counter[6]~27 ; +wire \sdram_|r.init_counter[7]~28_combout ; +wire \sdram_|r.init_counter[7]~29 ; +wire \sdram_|r.init_counter[8]~30_combout ; +wire \sdram_|r.init_counter[8]~31 ; +wire \sdram_|r.init_counter[9]~32_combout ; +wire \sdram_|r.init_counter[9]~33 ; +wire \sdram_|r.init_counter[10]~34_combout ; +wire \sdram_|r.init_counter[10]~35 ; +wire \sdram_|r.init_counter[11]~36_combout ; +wire \sdram_|r.init_counter[11]~37 ; +wire \sdram_|r.init_counter[12]~38_combout ; +wire \sdram_|r.init_counter[12]~39 ; +wire \sdram_|r.init_counter[13]~40_combout ; +wire \sdram_|r.init_counter[13]~41 ; +wire \sdram_|r.init_counter[14]~42_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux8~5_combout ; wire \sdram_|Mux72~0_combout ; wire \sdram_|Mux72~1_combout ; wire \sdram_|Mux84~0_combout ; @@ -2774,13 +2985,14 @@ wire \sdram_|Mux1~1_combout ; wire \sdram_|Mux0~0_combout ; wire \sdram_|Mux0~1_combout ; wire \sdram_|Mux73~0_combout ; -wire \sdram_|Mux73~1_combout ; wire \sdram_|Mux74~0_combout ; wire \sdram_|Mux74~1_combout ; wire \sdram_|Mux75~0_combout ; +wire \LED~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|Add0~1_cout ; wire \ula_|i2s_intf_|Add0~2_combout ; wire \ula_|i2s_intf_|lrdivider~2_combout ; @@ -2811,25 +3023,10 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2843,19 +3040,33 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~9_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~10_combout ; +wire \ula_|i2s_intf_|bitcount[2]~11 ; +wire \ula_|i2s_intf_|bitcount[3]~12_combout ; +wire \ula_|i2s_intf_|bitcount[3]~13 ; +wire \ula_|i2s_intf_|bitcount[4]~14_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|LessThan0~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~18_combout ; wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg[7]~1_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; wire \ula_|i2s_intf_|shiftreg~14_combout ; @@ -2866,25 +3077,19 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; +wire \ula_|i2s_intf_|shiftreg~2_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; wire \ula_|video_|Decoder0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2893,58 +3098,51 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; -wire \ula_|video_|bits[5]~feeder_combout ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[2]~feeder_combout ; -wire \ula_|video_|bits[2]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[2]~0_combout ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; +wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan6~0_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; -wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|border[2]~feeder_combout ; -wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|video_|attr[2]~feeder_combout ; +wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; -wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|VGA_HS~_Duplicate_1_q ; +wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|Selector0~0_combout ; wire \ula_|video_|VGA_HS~q ; wire \ula_|video_|VGA_VS~_Duplicate_1_q ; @@ -2958,290 +3156,305 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire \sdram_|Mux26~4_combout ; -wire \sdram_|r.bank[0]~7_combout ; -wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~6_combout ; wire \sdram_|r.bank[0]~4_combout ; wire \sdram_|r.bank[0]~5_combout ; -wire \sdram_|r.bank[0]~6_combout ; -wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|r.bank[0]~13_combout ; +wire \sdram_|r.bank[0]~11_combout ; wire \sdram_|Mux25~4_combout ; -wire \sdram_|Mux24~5_combout ; -wire \sdram_|Mux71~0_combout ; -wire \sdram_|process_0~7_combout ; -wire \sdram_|process_0~4_combout ; -wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~6_combout ; wire \sdram_|Mux71~2_combout ; wire \sdram_|Mux71~3_combout ; +wire \sdram_|process_0~8_combout ; +wire \sdram_|process_0~3_combout ; wire \sdram_|Mux71~4_combout ; -wire \sdram_|r.bank[0]~10_combout ; -wire \sdram_|Mux9~3_combout ; -wire \sdram_|n~5_combout ; -wire \sdram_|Mux9~4_combout ; -wire \sdram_|Mux9~2_combout ; -wire \sdram_|Equal2~3_combout ; -wire \sdram_|Mux10~2_combout ; -wire \sdram_|Mux10~3_combout ; -wire \sdram_|process_0~6_combout ; -wire \sdram_|Mux10~4_combout ; -wire \sdram_|Mux9~5_combout ; -wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux24~8_combout ; +wire \sdram_|Mux71~5_combout ; +wire \sdram_|n~6_combout ; +wire \sdram_|Mux9~0_combout ; wire \sdram_|Mux9~6_combout ; wire \sdram_|Mux9~7_combout ; -wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Equal5~1_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux9~1_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Mux9~3_combout ; wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|Mux10~4_combout ; wire \sdram_|Mux10~5_combout ; wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~12_combout ; wire \sdram_|Mux10~8_combout ; -wire \sdram_|Mux10~9_combout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~8_combout ; wire \sdram_|Mux11~2_combout ; wire \sdram_|Mux11~3_combout ; -wire \sdram_|Mux11~4_combout ; wire \sdram_|Mux11~5_combout ; wire \sdram_|Mux11~6_combout ; wire \sdram_|Mux11~7_combout ; -wire \sdram_|Mux11~9_combout ; -wire \sdram_|Mux11~8_combout ; -wire \sdram_|Mux24~2_combout ; -wire \sdram_|r.address[0]~7_combout ; -wire \sdram_|r.address[0]~0_combout ; -wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux24~6_combout ; wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~9_combout ; wire \sdram_|Mux13~5_combout ; wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~2_combout ; wire \sdram_|Mux24~3_combout ; wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~0_combout ; wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~8_combout ; +wire \sdram_|r.address[1]~9_combout ; +wire \sdram_|r.address[1]~7_combout ; +wire \sdram_|r.address[1]~10_combout ; +wire \sdram_|r.address[1]~1_combout ; wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; -wire \sdram_|Mux23~4_combout ; -wire \sdram_|Equal5~0_combout ; -wire \sdram_|Mux23~5_combout ; -wire \sdram_|Mux23~6_combout ; wire \sdram_|Mux19~0_combout ; wire \sdram_|r.address[1]~_Duplicate_1_q ; -wire \sdram_|Mux23~2_combout ; wire \sdram_|Mux23~3_combout ; -wire \sdram_|Mux23~1_combout ; -wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~5_combout ; wire \sdram_|r.address[1]~SLOAD_MUX_combout ; -wire \sdram_|r.address[3]~8_combout ; -wire \sdram_|r.address[3]~9_combout ; -wire \sdram_|Mux21~0_combout ; -wire \sdram_|Mux22~0_combout ; -wire \sdram_|r.address[3]~10_combout ; wire \sdram_|r.address[3]~11_combout ; wire \sdram_|r.address[3]~12_combout ; -wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; wire \sdram_|r.address[3]~14_combout ; wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~13_combout ; wire \sdram_|r.address[3]~16_combout ; wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|r.address[3]~18_combout ; +wire \sdram_|r.address[3]~19_combout ; +wire \sdram_|r.address[3]~20_combout ; wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux24~7_combout ; wire \sdram_|Mux20~4_combout ; -wire \sdram_|Mux20~7_combout ; -wire \sdram_|Mux23~7_combout ; -wire \sdram_|Mux20~8_combout ; -wire \sdram_|Mux20~10_combout ; -wire \sdram_|Mux20~9_combout ; -wire \sdram_|Mux20~11_combout ; -wire \sdram_|r.address[4]~_Duplicate_1_q ; -wire \sdram_|Mux20~12_combout ; -wire \sdram_|Mux20~5_combout ; -wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~2_combout ; +wire \sdram_|Mux20~3_combout ; wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~_Duplicate_1feeder_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~9_combout ; wire \sdram_|r.address[4]~SLOAD_MUX_combout ; -wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~4_combout ; -wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~7_combout ; wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~2_combout ; wire \sdram_|Mux19~3_combout ; wire \sdram_|r.address[5]~3_combout ; wire \sdram_|r.address[5]~SLOAD_MUX_combout ; wire \sdram_|Mux18~0_combout ; -wire \sdram_|Mux17~0_combout ; -wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux17~2_combout ; +wire \sdram_|Mux16~2_combout ; wire \sdram_|Mux15~2_combout ; -wire \sdram_|Mux14~0_combout ; -wire \sdram_|Mux14~1_combout ; -wire \sdram_|r.address[10]~4_combout ; -wire \sdram_|r.address[10]~_Duplicate_1_q ; -wire \sdram_|n~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1feeder_combout ; +wire \sdram_|n~5_combout ; wire \sdram_|Mux14~2_combout ; wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|r.address[10]~4_combout ; wire \sdram_|r.address[10]~SLOAD_MUX_combout ; -wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~21_combout ; +wire \sdram_|r.address[11]~22_combout ; wire \sdram_|r.address[11]~5_combout ; -wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; wire \sdram_|r.address[11]~_Duplicate_2_q ; wire \sdram_|Mux13~10_combout ; wire \sdram_|Mux13~6_combout ; wire \sdram_|r.address[11]~SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1_q ; -wire [9:0] \sdram_|r.rf_counter ; -wire [12:0] \sdram_|r.address ; -wire [15:0] \ula_|pcm_outl ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [8:0] \sdram_|r.state ; +wire [1:0] \sdram_|r.bank ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; +wire [1:0] \z80_|sw1_|SYNTHESIZED_WIRE_1 ; +wire [7:0] \z80_|data_pins_|dout ; +wire [3:0] \z80_|alu_|op1_low ; +wire [20:0] \debounce_autofire|r_Count ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [9:0] \sdram_|r.rf_counter ; +wire [1:0] \sdram_|r.dq_masks ; +wire [12:0] \sdram_|r.address ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [15:0] \ula_|pcm_outl ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; +wire [17:0] kempston_auto_fire_counter; +wire [20:0] \debounce_turbo|r_Count ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; -wire [3:0] \z80_|alu_|op2_low ; +wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|dout ; -wire [8:0] \sdram_|r.state ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [2:0] \z80_|sw1_|SYNTHESIZED_WIRE_2 ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [4:0] \ula_|zx_keyboard_|key_row ; +wire [3:0] \z80_|alu_|result_lo ; +wire [3:0] \z80_|alu_|op2_high ; +wire [3:0] \z80_|alu_|op1_high ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; wire [14:0] \sdram_|r.init_counter ; -wire [1:0] \sdram_|r.bank ; wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [3:0] \z80_|alu_|result_lo ; -wire [3:0] \z80_|alu_|op2_high ; -wire [3:0] \z80_|alu_|op1_high ; -wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; -wire [7:0] \z80_|ir_|opcode ; -wire [1:0] \sdram_|r.dq_masks ; -wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [3:0] \z80_|alu_|op1_low ; wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|ir_|opcode ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -3255,96 +3468,104 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; @@ -3355,14 +3576,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3375,11 +3588,19 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3391,14 +3612,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; - // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3609,8 +3822,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~67_combout ), - .oe(\D[0]~121_combout ), + .i(\D[0]~16_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3622,8 +3835,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~69_combout ), - .oe(\D[0]~121_combout ), + .i(\D[1]~18_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3635,8 +3848,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~71_combout ), - .oe(\D[0]~121_combout ), + .i(\D[2]~20_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3648,8 +3861,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~84_combout ), - .oe(\D[0]~121_combout ), + .i(\D[3]~22_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3661,8 +3874,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~96_combout ), - .oe(\D[0]~121_combout ), + .i(\D[4]~24_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3674,8 +3887,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~98_combout ), - .oe(\D[0]~121_combout ), + .i(\D[5]~27_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3687,8 +3900,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~106_combout ), - .oe(\D[0]~121_combout ), + .i(\D[6]~35_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3700,8 +3913,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~107_combout ), - .oe(\D[0]~121_combout ), + .i(\D[7]~37_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3739,7 +3952,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3778,7 +3991,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3791,7 +4004,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\SW[2]~input_o ), + .i(\turbo~q ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3804,7 +4017,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\raw_loader_in~input_o ), + .i(!\kempston[0]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3817,7 +4030,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(gnd), + .i(!\kempston[1]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3830,7 +4043,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(gnd), + .i(!\kempston[2]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3843,7 +4056,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(gnd), + .i(!\kempston[3]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3856,7 +4069,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\LED~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4166,32 +4379,6 @@ defparam \GPIO_1[31]~output .bus_hold = "false"; defparam \GPIO_1[31]~output .open_drain_output = "false"; // synopsys translate_on -// Location: IOOBUF_X53_Y16_N9 -cycloneive_io_obuf \GPIO_1[32]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[32]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[32]~output .bus_hold = "false"; -defparam \GPIO_1[32]~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOOBUF_X53_Y15_N9 -cycloneive_io_obuf \GPIO_1[33]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[33]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[33]~output .bus_hold = "false"; -defparam \GPIO_1[33]~output .open_drain_output = "false"; -// synopsys translate_on - // Location: IOOBUF_X16_Y34_N2 cycloneive_io_obuf \buzzer_out~output ( .i(\ula_|beep~q ), @@ -4504,6 +4691,19 @@ defparam \DRAM_ADDR[12]~output .bus_hold = "false"; defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \kempston_gnd~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(kempston_gnd), + .obar()); +// synopsys translate_off +defparam \kempston_gnd~output .bus_hold = "false"; +defparam \kempston_gnd~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -4597,7 +4797,7 @@ defparam \DRAM_DQ[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y15_N2 cycloneive_io_obuf \DRAM_DQ[5]~output ( - .i(\sdram_|Mux73~1_combout ), + .i(\sdram_|Mux73~0_combout ), .oe(\sdram_|Mux84~1_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4869,7 +5069,1083 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: IOIBUF_X53_Y16_N8 +cycloneive_io_ibuf \turbo_button~input ( + .i(turbo_button), + .ibar(gnd), + .o(\turbo_button~input_o )); +// synopsys translate_off +defparam \turbo_button~input .bus_hold = "false"; +defparam \turbo_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[0]~21 ( +// Equation(s): +// \debounce_turbo|r_Count[0]~21_combout = \debounce_turbo|r_Count [0] $ (VCC) +// \debounce_turbo|r_Count[0]~22 = CARRY(\debounce_turbo|r_Count [0]) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_turbo|r_Count[0]~21_combout ), + .cout(\debounce_turbo|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_turbo|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[1]~23 ( +// Equation(s): +// \debounce_turbo|r_Count[1]~23_combout = (\debounce_turbo|r_Count [1] & (!\debounce_turbo|r_Count[0]~22 )) # (!\debounce_turbo|r_Count [1] & ((\debounce_turbo|r_Count[0]~22 ) # (GND))) +// \debounce_turbo|r_Count[1]~24 = CARRY((!\debounce_turbo|r_Count[0]~22 ) # (!\debounce_turbo|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[0]~22 ), + .combout(\debounce_turbo|r_Count[1]~23_combout ), + .cout(\debounce_turbo|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N15 +dffeas \debounce_turbo|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[2]~25 ( +// Equation(s): +// \debounce_turbo|r_Count[2]~25_combout = (\debounce_turbo|r_Count [2] & (\debounce_turbo|r_Count[1]~24 $ (GND))) # (!\debounce_turbo|r_Count [2] & (!\debounce_turbo|r_Count[1]~24 & VCC)) +// \debounce_turbo|r_Count[2]~26 = CARRY((\debounce_turbo|r_Count [2] & !\debounce_turbo|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[1]~24 ), + .combout(\debounce_turbo|r_Count[2]~25_combout ), + .cout(\debounce_turbo|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N17 +dffeas \debounce_turbo|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[3]~27 ( +// Equation(s): +// \debounce_turbo|r_Count[3]~27_combout = (\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count[2]~26 )) # (!\debounce_turbo|r_Count [3] & ((\debounce_turbo|r_Count[2]~26 ) # (GND))) +// \debounce_turbo|r_Count[3]~28 = CARRY((!\debounce_turbo|r_Count[2]~26 ) # (!\debounce_turbo|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[2]~26 ), + .combout(\debounce_turbo|r_Count[3]~27_combout ), + .cout(\debounce_turbo|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N19 +dffeas \debounce_turbo|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[4]~29 ( +// Equation(s): +// \debounce_turbo|r_Count[4]~29_combout = (\debounce_turbo|r_Count [4] & (\debounce_turbo|r_Count[3]~28 $ (GND))) # (!\debounce_turbo|r_Count [4] & (!\debounce_turbo|r_Count[3]~28 & VCC)) +// \debounce_turbo|r_Count[4]~30 = CARRY((\debounce_turbo|r_Count [4] & !\debounce_turbo|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[3]~28 ), + .combout(\debounce_turbo|r_Count[4]~29_combout ), + .cout(\debounce_turbo|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N21 +dffeas \debounce_turbo|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N22 +cycloneive_lcell_comb \debounce_turbo|r_Count[5]~31 ( +// Equation(s): +// \debounce_turbo|r_Count[5]~31_combout = (\debounce_turbo|r_Count [5] & (!\debounce_turbo|r_Count[4]~30 )) # (!\debounce_turbo|r_Count [5] & ((\debounce_turbo|r_Count[4]~30 ) # (GND))) +// \debounce_turbo|r_Count[5]~32 = CARRY((!\debounce_turbo|r_Count[4]~30 ) # (!\debounce_turbo|r_Count [5])) + + .dataa(\debounce_turbo|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[4]~30 ), + .combout(\debounce_turbo|r_Count[5]~31_combout ), + .cout(\debounce_turbo|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N23 +dffeas \debounce_turbo|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N24 +cycloneive_lcell_comb \debounce_turbo|r_Count[6]~33 ( +// Equation(s): +// \debounce_turbo|r_Count[6]~33_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count[5]~32 $ (GND))) # (!\debounce_turbo|r_Count [6] & (!\debounce_turbo|r_Count[5]~32 & VCC)) +// \debounce_turbo|r_Count[6]~34 = CARRY((\debounce_turbo|r_Count [6] & !\debounce_turbo|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[5]~32 ), + .combout(\debounce_turbo|r_Count[6]~33_combout ), + .cout(\debounce_turbo|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N25 +dffeas \debounce_turbo|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N26 +cycloneive_lcell_comb \debounce_turbo|r_Count[7]~35 ( +// Equation(s): +// \debounce_turbo|r_Count[7]~35_combout = (\debounce_turbo|r_Count [7] & (!\debounce_turbo|r_Count[6]~34 )) # (!\debounce_turbo|r_Count [7] & ((\debounce_turbo|r_Count[6]~34 ) # (GND))) +// \debounce_turbo|r_Count[7]~36 = CARRY((!\debounce_turbo|r_Count[6]~34 ) # (!\debounce_turbo|r_Count [7])) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[6]~34 ), + .combout(\debounce_turbo|r_Count[7]~35_combout ), + .cout(\debounce_turbo|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N27 +dffeas \debounce_turbo|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N28 +cycloneive_lcell_comb \debounce_turbo|r_Count[8]~37 ( +// Equation(s): +// \debounce_turbo|r_Count[8]~37_combout = (\debounce_turbo|r_Count [8] & (\debounce_turbo|r_Count[7]~36 $ (GND))) # (!\debounce_turbo|r_Count [8] & (!\debounce_turbo|r_Count[7]~36 & VCC)) +// \debounce_turbo|r_Count[8]~38 = CARRY((\debounce_turbo|r_Count [8] & !\debounce_turbo|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[7]~36 ), + .combout(\debounce_turbo|r_Count[8]~37_combout ), + .cout(\debounce_turbo|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N29 +dffeas \debounce_turbo|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N30 +cycloneive_lcell_comb \debounce_turbo|r_Count[9]~39 ( +// Equation(s): +// \debounce_turbo|r_Count[9]~39_combout = (\debounce_turbo|r_Count [9] & (!\debounce_turbo|r_Count[8]~38 )) # (!\debounce_turbo|r_Count [9] & ((\debounce_turbo|r_Count[8]~38 ) # (GND))) +// \debounce_turbo|r_Count[9]~40 = CARRY((!\debounce_turbo|r_Count[8]~38 ) # (!\debounce_turbo|r_Count [9])) + + .dataa(\debounce_turbo|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[8]~38 ), + .combout(\debounce_turbo|r_Count[9]~39_combout ), + .cout(\debounce_turbo|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N31 +dffeas \debounce_turbo|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N0 +cycloneive_lcell_comb \debounce_turbo|r_Count[10]~41 ( +// Equation(s): +// \debounce_turbo|r_Count[10]~41_combout = (\debounce_turbo|r_Count [10] & (\debounce_turbo|r_Count[9]~40 $ (GND))) # (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count[9]~40 & VCC)) +// \debounce_turbo|r_Count[10]~42 = CARRY((\debounce_turbo|r_Count [10] & !\debounce_turbo|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[9]~40 ), + .combout(\debounce_turbo|r_Count[10]~41_combout ), + .cout(\debounce_turbo|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N1 +dffeas \debounce_turbo|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N2 +cycloneive_lcell_comb \debounce_turbo|r_Count[11]~43 ( +// Equation(s): +// \debounce_turbo|r_Count[11]~43_combout = (\debounce_turbo|r_Count [11] & (!\debounce_turbo|r_Count[10]~42 )) # (!\debounce_turbo|r_Count [11] & ((\debounce_turbo|r_Count[10]~42 ) # (GND))) +// \debounce_turbo|r_Count[11]~44 = CARRY((!\debounce_turbo|r_Count[10]~42 ) # (!\debounce_turbo|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[10]~42 ), + .combout(\debounce_turbo|r_Count[11]~43_combout ), + .cout(\debounce_turbo|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N3 +dffeas \debounce_turbo|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N4 +cycloneive_lcell_comb \debounce_turbo|r_Count[12]~45 ( +// Equation(s): +// \debounce_turbo|r_Count[12]~45_combout = (\debounce_turbo|r_Count [12] & (\debounce_turbo|r_Count[11]~44 $ (GND))) # (!\debounce_turbo|r_Count [12] & (!\debounce_turbo|r_Count[11]~44 & VCC)) +// \debounce_turbo|r_Count[12]~46 = CARRY((\debounce_turbo|r_Count [12] & !\debounce_turbo|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[11]~44 ), + .combout(\debounce_turbo|r_Count[12]~45_combout ), + .cout(\debounce_turbo|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N5 +dffeas \debounce_turbo|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N6 +cycloneive_lcell_comb \debounce_turbo|r_Count[13]~47 ( +// Equation(s): +// \debounce_turbo|r_Count[13]~47_combout = (\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count[12]~46 )) # (!\debounce_turbo|r_Count [13] & ((\debounce_turbo|r_Count[12]~46 ) # (GND))) +// \debounce_turbo|r_Count[13]~48 = CARRY((!\debounce_turbo|r_Count[12]~46 ) # (!\debounce_turbo|r_Count [13])) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[12]~46 ), + .combout(\debounce_turbo|r_Count[13]~47_combout ), + .cout(\debounce_turbo|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N7 +dffeas \debounce_turbo|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_State~7 ( +// Equation(s): +// \debounce_turbo|r_State~7_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count [7] & \debounce_turbo|r_Count [5])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(\debounce_turbo|r_Count [7]), + .datad(\debounce_turbo|r_Count [5]), + .cin(gnd), + .combout(\debounce_turbo|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~7 .lut_mask = 16'hC000; +defparam \debounce_turbo|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N2 +cycloneive_lcell_comb \debounce_turbo|LessThan0~0 ( +// Equation(s): +// \debounce_turbo|LessThan0~0_combout = (!\debounce_turbo|r_State~7_combout & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_State~7_combout ), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N30 +cycloneive_lcell_comb \debounce_turbo|LessThan0~1 ( +// Equation(s): +// \debounce_turbo|LessThan0~1_combout = (!\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count [12] & ((\debounce_turbo|LessThan0~0_combout ) # (!\debounce_turbo|r_Count [11])))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [12]), + .datac(\debounce_turbo|LessThan0~0_combout ), + .datad(\debounce_turbo|r_Count [11]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~1 .lut_mask = 16'h1011; +defparam \debounce_turbo|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N8 +cycloneive_lcell_comb \debounce_turbo|r_Count[14]~49 ( +// Equation(s): +// \debounce_turbo|r_Count[14]~49_combout = (\debounce_turbo|r_Count [14] & (\debounce_turbo|r_Count[13]~48 $ (GND))) # (!\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count[13]~48 & VCC)) +// \debounce_turbo|r_Count[14]~50 = CARRY((\debounce_turbo|r_Count [14] & !\debounce_turbo|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[13]~48 ), + .combout(\debounce_turbo|r_Count[14]~49_combout ), + .cout(\debounce_turbo|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N9 +dffeas \debounce_turbo|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N10 +cycloneive_lcell_comb \debounce_turbo|r_Count[15]~51 ( +// Equation(s): +// \debounce_turbo|r_Count[15]~51_combout = (\debounce_turbo|r_Count [15] & (!\debounce_turbo|r_Count[14]~50 )) # (!\debounce_turbo|r_Count [15] & ((\debounce_turbo|r_Count[14]~50 ) # (GND))) +// \debounce_turbo|r_Count[15]~52 = CARRY((!\debounce_turbo|r_Count[14]~50 ) # (!\debounce_turbo|r_Count [15])) + + .dataa(\debounce_turbo|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[14]~50 ), + .combout(\debounce_turbo|r_Count[15]~51_combout ), + .cout(\debounce_turbo|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N11 +dffeas \debounce_turbo|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[16]~53 ( +// Equation(s): +// \debounce_turbo|r_Count[16]~53_combout = (\debounce_turbo|r_Count [16] & (\debounce_turbo|r_Count[15]~52 $ (GND))) # (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count[15]~52 & VCC)) +// \debounce_turbo|r_Count[16]~54 = CARRY((\debounce_turbo|r_Count [16] & !\debounce_turbo|r_Count[15]~52 )) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[15]~52 ), + .combout(\debounce_turbo|r_Count[16]~53_combout ), + .cout(\debounce_turbo|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_turbo|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N13 +dffeas \debounce_turbo|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[17]~55 ( +// Equation(s): +// \debounce_turbo|r_Count[17]~55_combout = (\debounce_turbo|r_Count [17] & (!\debounce_turbo|r_Count[16]~54 )) # (!\debounce_turbo|r_Count [17] & ((\debounce_turbo|r_Count[16]~54 ) # (GND))) +// \debounce_turbo|r_Count[17]~56 = CARRY((!\debounce_turbo|r_Count[16]~54 ) # (!\debounce_turbo|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[16]~54 ), + .combout(\debounce_turbo|r_Count[17]~55_combout ), + .cout(\debounce_turbo|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N15 +dffeas \debounce_turbo|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[18]~57 ( +// Equation(s): +// \debounce_turbo|r_Count[18]~57_combout = (\debounce_turbo|r_Count [18] & (\debounce_turbo|r_Count[17]~56 $ (GND))) # (!\debounce_turbo|r_Count [18] & (!\debounce_turbo|r_Count[17]~56 & VCC)) +// \debounce_turbo|r_Count[18]~58 = CARRY((\debounce_turbo|r_Count [18] & !\debounce_turbo|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[17]~56 ), + .combout(\debounce_turbo|r_Count[18]~57_combout ), + .cout(\debounce_turbo|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N17 +dffeas \debounce_turbo|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[19]~59 ( +// Equation(s): +// \debounce_turbo|r_Count[19]~59_combout = (\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count[18]~58 )) # (!\debounce_turbo|r_Count [19] & ((\debounce_turbo|r_Count[18]~58 ) # (GND))) +// \debounce_turbo|r_Count[19]~60 = CARRY((!\debounce_turbo|r_Count[18]~58 ) # (!\debounce_turbo|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[18]~58 ), + .combout(\debounce_turbo|r_Count[19]~59_combout ), + .cout(\debounce_turbo|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N19 +dffeas \debounce_turbo|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N22 +cycloneive_lcell_comb \debounce_turbo|always0~0 ( +// Equation(s): +// \debounce_turbo|always0~0_combout = (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count [17] & !\debounce_turbo|r_Count [18]))) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(\debounce_turbo|r_Count [19]), + .datac(\debounce_turbo|r_Count [17]), + .datad(\debounce_turbo|r_Count [18]), + .cin(gnd), + .combout(\debounce_turbo|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N24 +cycloneive_lcell_comb \debounce_turbo|always0~1 ( +// Equation(s): +// \debounce_turbo|always0~1_combout = (\debounce_turbo|always0~0_combout & ((\debounce_turbo|LessThan0~1_combout ) # ((!\debounce_turbo|r_Count [15]) # (!\debounce_turbo|r_Count [14])))) + + .dataa(\debounce_turbo|LessThan0~1_combout ), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|always0~0_combout ), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_turbo|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[20]~61 ( +// Equation(s): +// \debounce_turbo|r_Count[20]~61_combout = \debounce_turbo|r_Count[19]~60 $ (!\debounce_turbo|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_turbo|r_Count [20]), + .cin(\debounce_turbo|r_Count[19]~60 ), + .combout(\debounce_turbo|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_turbo|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N21 +dffeas \debounce_turbo|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N0 +cycloneive_lcell_comb \debounce_turbo|always0~2 ( +// Equation(s): +// \debounce_turbo|always0~2_combout = (\debounce_turbo|always0~1_combout & (\debounce_turbo|r_State~q $ ((!\turbo_button~input_o )))) # (!\debounce_turbo|always0~1_combout & ((\debounce_turbo|r_Count [20]) # (\debounce_turbo|r_State~q $ +// (!\turbo_button~input_o )))) + + .dataa(\debounce_turbo|always0~1_combout ), + .datab(\debounce_turbo|r_State~q ), + .datac(\turbo_button~input_o ), + .datad(\debounce_turbo|r_Count [20]), + .cin(gnd), + .combout(\debounce_turbo|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~2 .lut_mask = 16'hD7C3; +defparam \debounce_turbo|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y29_N13 +dffeas \debounce_turbo|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N10 +cycloneive_lcell_comb \debounce_turbo|r_State~4 ( +// Equation(s): +// \debounce_turbo|r_State~4_combout = (!\debounce_turbo|r_Count [0] & (!\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count [1] & !\debounce_turbo|r_Count [2]))) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(\debounce_turbo|r_Count [3]), + .datac(\debounce_turbo|r_Count [1]), + .datad(\debounce_turbo|r_Count [2]), + .cin(gnd), + .combout(\debounce_turbo|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_turbo|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N6 +cycloneive_lcell_comb \debounce_turbo|r_State~2 ( +// Equation(s): +// \debounce_turbo|r_State~2_combout = (\debounce_turbo|r_Count [20] & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_Count [20]), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_turbo|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N28 +cycloneive_lcell_comb \debounce_turbo|r_State~0 ( +// Equation(s): +// \debounce_turbo|r_State~0_combout = (!\debounce_turbo|r_Count [13] & (\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count [12] & \debounce_turbo|r_Count [15]))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|r_Count [12]), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_turbo|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~1 ( +// Equation(s): +// \debounce_turbo|r_State~1_combout = (\debounce_turbo|r_Count [7] & (\debounce_turbo|r_Count [11] & (\debounce_turbo|r_Count [5] & \debounce_turbo|r_Count [6]))) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(\debounce_turbo|r_Count [11]), + .datac(\debounce_turbo|r_Count [5]), + .datad(\debounce_turbo|r_Count [6]), + .cin(gnd), + .combout(\debounce_turbo|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N0 +cycloneive_lcell_comb \debounce_turbo|r_State~3 ( +// Equation(s): +// \debounce_turbo|r_State~3_combout = (\debounce_turbo|r_State~2_combout & (\debounce_turbo|r_State~0_combout & (\debounce_turbo|r_State~1_combout & \debounce_turbo|always0~0_combout ))) + + .dataa(\debounce_turbo|r_State~2_combout ), + .datab(\debounce_turbo|r_State~0_combout ), + .datac(\debounce_turbo|r_State~1_combout ), + .datad(\debounce_turbo|always0~0_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N8 +cycloneive_lcell_comb \debounce_turbo|r_State~5 ( +// Equation(s): +// \debounce_turbo|r_State~5_combout = (\debounce_turbo|r_State~4_combout & (!\debounce_turbo|r_Count [4] & \debounce_turbo|r_State~3_combout )) + + .dataa(\debounce_turbo|r_State~4_combout ), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(\debounce_turbo|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~5 .lut_mask = 16'h2200; +defparam \debounce_turbo|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~6 ( +// Equation(s): +// \debounce_turbo|r_State~6_combout = (\debounce_turbo|r_State~5_combout & (\turbo_button~input_o )) # (!\debounce_turbo|r_State~5_combout & ((\debounce_turbo|r_State~q ))) + + .dataa(\turbo_button~input_o ), + .datab(gnd), + .datac(\debounce_turbo|r_State~q ), + .datad(\debounce_turbo|r_State~5_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~6 .lut_mask = 16'hAAF0; +defparam \debounce_turbo|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N5 +dffeas \debounce_turbo|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_turbo|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_State .is_wysiwyg = "true"; +defparam \debounce_turbo|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N14 +cycloneive_lcell_comb \turbo~0 ( +// Equation(s): +// \turbo~0_combout = !\turbo~q + + .dataa(gnd), + .datab(gnd), + .datac(\turbo~q ), + .datad(gnd), + .cin(gnd), + .combout(\turbo~0_combout ), + .cout()); +// synopsys translate_off +defparam \turbo~0 .lut_mask = 16'h0F0F; +defparam \turbo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N15 +dffeas turbo( + .clk(!\debounce_turbo|r_State~q ), + .d(\turbo~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\turbo~q ), + .prn(vcc)); +// synopsys translate_off +defparam turbo.is_wysiwyg = "true"; +defparam turbo.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y29_N4 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4886,7 +6162,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y29_N5 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4905,34 +6181,24 @@ defparam \ula_|clocks_|counter[0] .is_wysiwyg = "true"; defparam \ula_|clocks_|counter[0] .power_up = "low"; // synopsys translate_on -// Location: IOIBUF_X25_Y34_N8 -cycloneive_io_ibuf \SW[2]~input ( - .i(SW[2]), - .ibar(gnd), - .o(\SW[2]~input_o )); -// synopsys translate_off -defparam \SW[2]~input .bus_hold = "false"; -defparam \SW[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): -// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) +// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\turbo~q ) # (!\ula_|clocks_|counter [0]))) .dataa(gnd), - .datab(\ula_|clocks_|counter [0]), + .datab(\turbo~q ), .datac(\ula_|clocks_|clk_cpu~q ), - .datad(\SW[2]~input_o ), + .datad(\ula_|clocks_|counter [0]), .cin(gnd), .combout(\ula_|clocks_|clk_cpu~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; +defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h3C0F; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4951,7 +6217,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4964,33 +6230,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -5001,7 +6240,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N12 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -5018,7 +6257,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N18 +// Location: LCCOMB_X27_Y15_N4 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -5035,7 +6274,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y32_N8 +// Location: LCCOMB_X27_Y1_N28 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -5052,7 +6291,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X26_Y32_N9 +// Location: FF_X27_Y1_N29 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -5071,7 +6310,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -5084,7 +6323,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y14_N19 +// Location: FF_X27_Y15_N5 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -5103,79 +6342,68 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: FF_X31_Y14_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Location: LCCOMB_X23_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC .dataa(gnd), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(gnd), + .datad(gnd), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y10_N1 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G7 +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~55_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), @@ -5188,21 +6416,40 @@ defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout ) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .combout(\z80_|sequencer_|ena_M~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N19 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -5218,7 +6465,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N8 +// Location: LCCOMB_X26_Y31_N0 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) @@ -5236,24 +6483,24 @@ defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N14 +// Location: LCCOMB_X30_Y31_N10 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~0_combout ), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Add0~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hC0C0; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y29_N15 +// Location: FF_X30_Y31_N11 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -5272,7 +6519,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N10 +// Location: LCCOMB_X26_Y31_N2 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -5290,7 +6537,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N22 +// Location: LCCOMB_X29_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -5307,7 +6554,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y30_N23 +// Location: FF_X29_Y31_N13 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -5326,7 +6573,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N12 +// Location: LCCOMB_X26_Y31_N4 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -5344,7 +6591,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N31 +// Location: FF_X29_Y31_N15 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5363,33 +6610,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N14 +// Location: LCCOMB_X26_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(\ula_|video_|vga_hc [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y30_N11 +// Location: FF_X26_Y31_N7 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|Add0~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -5400,7 +6647,24 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N16 +// Location: LCCOMB_X30_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N8 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -5418,7 +6682,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N7 +// Location: FF_X26_Y31_N25 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5437,169 +6701,42 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Location: LCCOMB_X30_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( // Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & !\ula_|video_|vga_hc [4]))) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Add0~10_combout ), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [4]), .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), + .combout(\ula_|video_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y30_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N22 +// Location: LCCOMB_X26_Y31_N14 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) // \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - .dataa(\ula_|video_|vga_hc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~13 ), .combout(\ula_|video_|Add0~14_combout ), .cout(\ula_|video_|Add0~15 )); // synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N3 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N26 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N24 +// Location: LCCOMB_X26_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) @@ -5617,15 +6754,15 @@ defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N28 +// Location: LCCOMB_X26_Y31_N22 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~16_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); @@ -5634,7 +6771,7 @@ defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N17 +// Location: FF_X26_Y31_N15 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5653,32 +6790,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N26 +// Location: LCCOMB_X26_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N2 +// Location: LCCOMB_X26_Y31_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -5687,7 +6824,7 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N5 +// Location: FF_X26_Y31_N31 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5706,24 +6843,134 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y29_N0 +// Location: LCCOMB_X30_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal1~0 ( // Equation(s): // \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N0 +// Location: LCCOMB_X26_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y31_N23 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N21 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N29 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) @@ -5741,312 +6988,77 @@ defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Location: LCCOMB_X31_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [0] & !\ula_|video_|vga_vc [1]))) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Add1~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N31 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [3]), .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), + .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N21 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N26 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N27 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N23 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N10 +// Location: LCCOMB_X31_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N9 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N12 +// Location: LCCOMB_X31_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N16 +// Location: LCCOMB_X27_Y31_N28 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N17 +// Location: FF_X27_Y31_N29 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -6065,7 +7077,7 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N14 +// Location: LCCOMB_X31_Y31_N20 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) @@ -6083,7 +7095,7 @@ defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N22 +// Location: LCCOMB_X27_Y31_N8 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) @@ -6100,7 +7112,7 @@ defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N23 +// Location: FF_X27_Y31_N9 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -6119,25 +7131,25 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N16 +// Location: LCCOMB_X31_Y31_N22 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) // \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~15 ), .combout(\ula_|video_|Add1~16_combout ), .cout(\ula_|video_|Add1~17 )); // synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N20 +// Location: LCCOMB_X27_Y31_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): // \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) @@ -6154,7 +7166,7 @@ defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N21 +// Location: FF_X27_Y31_N7 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -6173,41 +7185,41 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N18 +// Location: LCCOMB_X31_Y31_N24 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) +// \ula_|video_|Add1~18_combout = \ula_|video_|vga_vc [9] $ (\ula_|video_|Add1~17 ) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [9]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), + .datad(gnd), .cin(\ula_|video_|Add1~17 ), .combout(\ula_|video_|Add1~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .lut_mask = 16'h5A5A; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N8 +// Location: LCCOMB_X27_Y31_N4 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N9 +// Location: FF_X27_Y31_N5 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -6226,32 +7238,15 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N30 +// Location: LCCOMB_X27_Y31_N24 cycloneive_lcell_comb \ula_|video_|Equal2~0 ( // Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [6]))) .dataa(\ula_|video_|vga_vc [8]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), .combout(\ula_|video_|Equal2~0_combout ), .cout()); @@ -6260,13 +7255,13 @@ defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N16 +// Location: LCCOMB_X31_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) +// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal3~0_combout & (\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|Equal3~0_combout ), + .dataa(\ula_|video_|Equal3~0_combout ), + .datab(\ula_|video_|vga_vc [9]), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), @@ -6277,24 +7272,24 @@ defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N24 +// Location: LCCOMB_X27_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( // Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~0_combout ), .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N25 +// Location: FF_X27_Y31_N13 dffeas \ula_|video_|vga_vc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[0]~0_combout ), @@ -6313,15 +7308,267 @@ defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N18 +// Location: LCCOMB_X31_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N18 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N19 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h0A0C; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[2]~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N2 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [3]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~6_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~6_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N3 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N0 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) .dataa(\ula_|video_|vga_vc [0]), .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [3]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -6330,20 +7577,20 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N12 +// Location: LCCOMB_X31_Y31_N26 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(\ula_|video_|Equal2~1_combout ), - .datab(gnd), - .datac(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(gnd), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -6357,14 +7604,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X31_Y27_N2 +// Location: LCCOMB_X28_Y31_N26 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & !\SW[1]~input_o ))) - .dataa(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), .datab(\ula_|video_|vga_vc [1]), - .datac(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -6374,75 +7621,77 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|ir_|opcode[4]~feeder ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|ir_|opcode[4]~feeder_combout = \z80_|bus_control_|db[4]~18_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal0~0_combout ), + .combout(\z80_|ir_|opcode[4]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; -defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; +defparam \z80_|ir_|opcode[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N8 +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N13 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N9 +// Location: FF_X36_Y11_N21 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -6461,340 +7710,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N27 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - - .dataa(\z80_|clk_delay_|DFF_inst5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N24 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~2_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & -// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N25 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 +// Location: LCCOMB_X36_Y11_N30 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N1 +// Location: FF_X36_Y11_N31 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -6813,2615 +7746,32 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N2 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIOWrite~2_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|fMWrite~3_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~45_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N11 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~97_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~96_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~98_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~98_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), - .datab(\z80_|execute_|ctl_inc_cy~96_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(gnd), - .datad(\z80_|execute_|fMWrite~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [7]), - .datac(gnd), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N24 +// Location: LCCOMB_X37_Y14_N10 cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( // Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) +// \z80_|execute_|ctl_ir_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|ctl_ir_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h5050; defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; -defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & -// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|fMWrite~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # -// (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N21 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y11_N17 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N15 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X40_Y11_N23 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~12_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~16_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N13 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N21 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N17 +// Location: FF_X30_Y12_N5 dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~53_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|execute_|setM1~55_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -9432,24 +7782,24 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N8 +// Location: LCCOMB_X30_Y12_N8 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h0F0F; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N9 +// Location: FF_X30_Y12_N9 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -9468,7 +7818,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N7 +// Location: FF_X30_Y12_N19 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -9487,7 +7837,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N6 +// Location: LCCOMB_X30_Y12_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & @@ -9505,34385 +7855,358 @@ defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N10 +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h333B; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~0_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~0 .lut_mask = 16'h0505; +defparam \z80_|pla_decode_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [0] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0800; defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|fIOWrite~0_combout ), - .datad(\z80_|execute_|fIORead~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|execute_|fIORead~0_combout ), - .datac(\z80_|execute_|fIOWrite~1_combout ), - .datad(\z80_|execute_|fIORead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N23 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|im2~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|execute_|fMRead~4_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal40~2_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; -defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~14_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|execute_|setM1~57_combout ), - .datab(\z80_|execute_|setM1~38_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~19_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|DFFE_instED~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~31_combout ), - .datab(\z80_|execute_|ctl_mRead~32_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N19 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~33_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N29 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N11 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) - - .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), - .datab(\z80_|execute_|fIORead~3_combout ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~1_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N12 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h3000; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G9 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & -// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N13 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [5]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [3]), - .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N27 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N7 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [0]), - .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N17 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X18_Y12_N19 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N29 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N13 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N23 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\PS2_DAT~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|always1~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y10_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N13 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X21_Y8_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) - - .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N25 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N27 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N25 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N5 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) - - .dataa(\z80_|resets_|clrpc_int~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & -// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~99_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~37_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal12~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal33~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout -// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal76~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal10~1_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & -// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|fMRead~8_combout ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_sw_4d~0_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; -defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_inc_dec~3_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N25 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|setM1~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & -// ((\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|execute_|ctl_state_alu~13_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|fMRead~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~25_combout ), - .datac(\z80_|execute_|ctl_mRead~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & -// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_sw_1d~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & -// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; -defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # -// (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # -// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_1d~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(\z80_|execute_|ctl_sw_4u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .datad(\z80_|execute_|ctl_sw_4u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_2d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|fMRead~18_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~22_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|fMRead~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_2d~9_combout ), - .datac(\z80_|execute_|ctl_sw_1d~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; -defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal44~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & -// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; -defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_flags_alu~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; -defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~18_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~26_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datab(\z80_|alu_control_|db[1]~27_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Location: LCCOMB_X35_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), .datac(\z80_|sequencer_|DFFE_M2_ff~q ), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & -// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_oe~15_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ -// (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datac(\z80_|execute_|ctl_sw_2u~6_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N27 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; -defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_cy~50_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N24 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~26_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~10_combout ), - .datad(\z80_|execute_|ctl_sw_2d~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_alu_oe~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~10_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & -// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) - - .dataa(\z80_|alu_control_|db[3]~36_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # -// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) - - .dataa(\z80_|execute_|setM1~50_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(\z80_|alu_flags_|flags_xf~q ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; -defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~87_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~64_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~65_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~97_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~57_combout ), - .datad(\z80_|execute_|ctl_inc_cy~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout -// & (\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal33~2_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; -defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|pc_inc_hold~19_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; -defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|pc_inc_hold~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # -// ((\z80_|execute_|ctl_inc_cy~62_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_inc_cy~68_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~17_combout ), - .datab(\z80_|execute_|ctl_inc_cy~74_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~73_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~95_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|ctl_inc_cy~95_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datad(\z80_|execute_|ctl_inc_cy~77_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_inc_cy~78_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~15_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~70_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|ctl_inc_cy~79_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # -// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|pc_inc_hold~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_inc_cy~51_combout ), - .datac(\z80_|execute_|ctl_inc_cy~49_combout ), - .datad(\z80_|execute_|ctl_inc_cy~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_inc_cy~90_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~83_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~96_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~100_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|ctl_inc_cy~84_combout ), - .datac(\z80_|execute_|ctl_inc_cy~100_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~24_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|pc_inc_hold~29_combout ), - .datad(\z80_|execute_|pc_inc_hold~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|Q [0]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( -// Equation(s): -// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[0]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|execute_|ctl_inc_dec~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [2]), - .datab(gnd), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( -// Equation(s): -// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db_low[2]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; -defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|alu_|db[1]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & -// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(\z80_|execute_|ctl_al_we~10_combout ), - .datac(\z80_|execute_|ctl_al_we~8_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~11_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N7 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( -// Equation(s): -// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; -defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & -// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N11 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( -// Equation(s): -// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; -defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( -// Equation(s): -// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; -defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( -// Equation(s): -// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; -defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(\z80_|address_latch_|Q [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N3 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q -// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N1 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & -// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N2 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[4]~8_combout ), - .datad(\z80_|alu_|db_high[0]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N13 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( -// Equation(s): -// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( -// Equation(s): -// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db_low[1]~18_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [1]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~16_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( -// Equation(s): -// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # -// (!\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|alu_|db_low[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[1]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; -defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[1]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N9 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout -// )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_flags_alu~21_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # -// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N11 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & -// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # -// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|alu_|db_high[2]~13_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[2]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N3 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_high [2]), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( -// Equation(s): -// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; -defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db_high[2]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|alu_|db_high[2]~10_combout ), - .datac(\z80_|alu_|db_high[2]~9_combout ), - .datad(\z80_|alu_|db_high[2]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[2]~12_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|alu_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N16 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( -// Equation(s): -// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; -defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [1]), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[1]~14_combout ), - .datad(\z80_|alu_|db_high[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|db_high[1]~18_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N21 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N4 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N18 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[7]~19_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & -// ((\z80_|alu_|db[7]~20_combout ))))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~8_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N11 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|alu_|op1_high [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; -defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_high[2]~13_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[2]~14_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N31 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; -defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|op1_low [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_|alu_op2[2]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|alu_op2[2]~1_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # -// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|alu_op1[3]~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op2[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( -// Equation(s): -// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N23 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( -// Equation(s): -// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~24_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( -// Equation(s): -// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & -// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[0]~22_combout ), - .datac(\z80_|alu_|db_low[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_low[0]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N17 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # -// (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & -// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout -// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # -// (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & -// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[0]~1_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(gnd), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( -// Equation(s): -// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; -defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[0]~23_combout ), - .datad(\z80_|alu_|db_high[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|db_high[0]~24_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N19 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( -// Equation(s): -// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|result_lo [2]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( -// Equation(s): -// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( -// Equation(s): -// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|alu_|db_low[2]~12_combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; -defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( -// Equation(s): -// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[2]~10_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~11_combout ), - .datad(\z80_|alu_|db_low[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; -defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N22 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~11_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~33_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( -// Equation(s): -// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; -defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( -// Equation(s): -// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[2]~28_combout ), - .datab(\z80_|alu_control_|db[2]~24_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[2]~29_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; -defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N27 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & -// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N20 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_control_|db[0]~14_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( -// Equation(s): -// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( -// Equation(s): -// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[0]~11_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_flags_|flags_cf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout -// ))))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(\z80_|execute_|ctl_inc_cy~93_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~9_combout ), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & -// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q -// [2]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~34_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|sw1_|db_down[3]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( -// Equation(s): -// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; -defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N10 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( -// Equation(s): -// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y10_N25 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( -// Equation(s): -// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~6_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) - - .dataa(\z80_|alu_|db_low[3]~5_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|result_lo [3]), - .datad(\z80_|alu_|db_low[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( -// Equation(s): -// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; -defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[3]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N13 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[3]~7_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N21 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op1[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & -// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|alu_control_|out[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|alu_|db[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout -// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_control_|out[6]~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal10~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( // Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), + .combout(\z80_|execute_|ctl_mRead~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_sw_1d~2_combout = (\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~2_combout & +// (((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - .dataa(\z80_|pla_decode_|Equal64~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N2 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[4]~31_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( -// Equation(s): -// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[4]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; -defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N5 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [4]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|Q [5]), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [3]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [1]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [14]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X30_Y12_N19 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// (!\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; -defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .datad(\z80_|alu_|alu_parity_out~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y11_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|alu_|db_high[0]~25_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .datab(\z80_|alu_control_|db[6]~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N25 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|alu_control_|sel[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_control_|sel[1]~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N9 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N13 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [11]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & -// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y4_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [11]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N6 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N7 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N26 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\z80_|address_pins_|abus[10]~20_combout ), - .datad(\ula_|zx_keyboard_|keys[3][2]~q ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hC4F5; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~2_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N31 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; -defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) - - .dataa(\z80_|address_latch_|abusz [14]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N14 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; -defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; -defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N1 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N10 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & -// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hC4F5; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [13]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N18 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|key_row~1_combout ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'h80A0; -defparam \D[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [0]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; -defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N13 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [9]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [8]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N20 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'hF531; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N24 -cycloneive_lcell_comb \D[2]~46 ( -// Equation(s): -// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) - - .dataa(\D[2]~43_combout ), - .datab(\D[2]~45_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hF8F0; -defparam \D[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N3 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|clk_delay_|DFF_inst5~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( -// Equation(s): -// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; -defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N8 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0020; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N18 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h4000; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N16 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|address_latch_|abusz [2]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [3]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [3]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [6]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X24_Y19_N11 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N3 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ExtRamWE~0_combout ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X25_Y19_N15 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N19 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N10 -cycloneive_lcell_comb \D[2]~50 ( -// Equation(s): -// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\D[2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~50 .lut_mask = 16'hF838; -defparam \D[2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N26 -cycloneive_lcell_comb \D[2]~51 ( -// Equation(s): -// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~50_combout ), - .cin(gnd), - .combout(\D[2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~51 .lut_mask = 16'hEE30; -defparam \D[2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N24 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N8 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N25 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|vram_address[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N31 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N4 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N5 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N23 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N17 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( -// Equation(s): -// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) - - .dataa(\ula_|video_|vga_vc [8]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N7 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N18 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|vram_address[10]~2_combout ), - .datab(\ula_|video_|Add4~4_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N19 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N24 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N25 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N3 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N28 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N29 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N20 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N21 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y18_N0 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N22 -cycloneive_lcell_comb \D[2]~47 ( -// Equation(s): -// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~47 .lut_mask = 16'hE6A2; -defparam \D[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N24 -cycloneive_lcell_comb \D[2]~48 ( -// Equation(s): -// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[2]~47_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~48 .lut_mask = 16'h4B48; -defparam \D[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N16 -cycloneive_lcell_comb \D[2]~49 ( -// Equation(s): -// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[2]~47_combout ), - .datad(\D[2]~48_combout ), - .cin(gnd), - .combout(\D[2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~49 .lut_mask = 16'hC3E0; -defparam \D[2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N6 -cycloneive_lcell_comb \D[2]~119 ( -// Equation(s): -// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~51_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~51_combout ), - .datad(\D[2]~49_combout ), - .cin(gnd), - .combout(\D[2]~119_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~119 .lut_mask = 16'hF4B0; -defparam \D[2]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N20 -cycloneive_lcell_comb \D[2]~52 ( -// Equation(s): -// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[2]~46_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~52 .lut_mask = 16'hBFB3; -defparam \D[2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N26 -cycloneive_lcell_comb \D[2]~53 ( -// Equation(s): -// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~52_combout ), - .cin(gnd), - .combout(\D[2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~53 .lut_mask = 16'hF511; -defparam \D[2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout -// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\D[2]~53_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_re~combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N17 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[2]~12_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N9 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .combout(\z80_|execute_|ctl_sw_1d~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_1d~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_1d~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Location: LCCOMB_X31_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & -// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~21_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(gnd), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; -defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( -// Equation(s): -// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|sw1_|db_down[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; -defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N2 -cycloneive_lcell_comb \D[6]~103 ( -// Equation(s): -// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~103 .lut_mask = 16'hEA4A; -defparam \D[6]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N30 -cycloneive_lcell_comb \D[6]~104 ( -// Equation(s): -// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~103_combout ), - .cin(gnd), - .combout(\D[6]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~104 .lut_mask = 16'hEE30; -defparam \D[6]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N14 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hBCB0; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N12 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\D[6]~100_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'h2D28; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N0 -cycloneive_lcell_comb \D[6]~102 ( -// Equation(s): -// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~100_combout ), - .datad(\D[6]~101_combout ), - .cin(gnd), - .combout(\D[6]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~102 .lut_mask = 16'hC3E0; -defparam \D[6]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N8 -cycloneive_lcell_comb \D[6]~127 ( -// Equation(s): -// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~104_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[6]~104_combout ), - .datad(\D[6]~102_combout ), - .cin(gnd), - .combout(\D[6]~127_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~127 .lut_mask = 16'hF4B0; -defparam \D[6]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N28 -cycloneive_lcell_comb \D[6]~99 ( -// Equation(s): -// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\raw_loader_in~input_o ), - .cin(gnd), - .combout(\D[6]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~99 .lut_mask = 16'hFFCF; -defparam \D[6]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N10 -cycloneive_lcell_comb \D[6]~114 ( -// Equation(s): -// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~114_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~114 .lut_mask = 16'hFB73; -defparam \D[6]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N12 -cycloneive_lcell_comb \D[6]~115 ( -// Equation(s): -// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~114_combout ), - .cin(gnd), - .combout(\D[6]~115_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~115 .lut_mask = 16'hF511; -defparam \D[6]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & -// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[6]~115_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N15 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[6]~9_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|interrupts_|iff1~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y12_N5 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y27_N8 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal2~3_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [5]))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\ula_|video_|vga_hc [7]), - .datad(\z80_|interrupts_|iff1~q ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y27_N9 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N25 -dffeas \z80_|interrupts_|DFFE_inst44 ( +// Location: FF_X29_Y18_N25 +dffeas \z80_|decode_state_|DFFE_instED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), + .q(\z80_|decode_state_|DFFE_instED~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N16 +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -43892,24 +8215,58 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N12 +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0044; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|decode_state_|in_halt~0_combout ), - .datab(\z80_|pla_decode_|Equal77~1_combout ), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N13 +// Location: FF_X31_Y12_N29 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -43928,407 +8285,30744 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N22 +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0505; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~3 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_sw_1d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0101; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'hC000; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hA0A0; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~0_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_state_iy_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N25 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal1~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|pla_decode_|Equal3~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hDFFF; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((!\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h707F; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~3 ( +// Equation(s): +// \z80_|execute_|ixy_d~3_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (\z80_|execute_|ixy_d~8_combout ) # ((\z80_|execute_|ixy_d~16_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ixy_d~11_combout & +// ((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~12_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hBBB0; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~2 ( +// Equation(s): +// \z80_|execute_|ixy_d~2_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~2 .lut_mask = 16'h0500; +defparam \z80_|execute_|ixy_d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~10_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q +// & \z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~19 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~19_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~19 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~8_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~8 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_bus_db_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~8_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7500; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~16_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_mWrite~10_combout ))) # (!\z80_|execute_|ctl_ir_we~16_combout & (((!\z80_|execute_|ctl_ir_we~15_combout ) # +// (!\z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|nM1_int~2_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal1~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|pla_decode_|Equal47~0_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~19_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h3700; defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal12~0_combout ))) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|fMRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMWrite~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_mRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) +// \z80_|execute_|ctl_reg_in_hi~9_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) .dataa(\z80_|execute_|ctl_mRead~12_combout ), .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_reg_in_hi~9_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|nextM~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_mRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|ir_|opcode [7]), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~15_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~18_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout & (((!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h0037; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (((!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h3070; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|pla_decode_|Equal44~0_combout ))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|fMRead~29_combout ), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( // Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), + .combout(\z80_|pla_decode_|Equal52~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) - - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~30_combout ), - .datac(\z80_|execute_|fMRead~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) +// \z80_|execute_|fMRead~20_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~11_combout )))) - .dataa(\z80_|execute_|fMRead~27_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|fMRead~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~16_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|fMRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), + .combout(\z80_|execute_|fMRead~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h20A0; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X31_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|pla_decode_|Equal11~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X31_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) +// \z80_|pla_decode_|Equal10~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ctl_mRead~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|pla_decode_|Equal10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|execute_|fMRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X35_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~16_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|fMRead~15_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N10 +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|fMRead~19_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_mWrite~11_combout ))) + + .dataa(\z80_|execute_|fMRead~19_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~2_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [3])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~2 .lut_mask = 16'h0003; +defparam \z80_|pla_decode_|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~32_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal34~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & \z80_|execute_|ctl_reg_in_hi~10_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .dataa(\z80_|execute_|ctl_mRead~22_combout ), .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~17_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'h8000; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|fMRead~22_combout ))) - .dataa(\z80_|execute_|fMRead~23_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2d~8_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), .datad(\z80_|execute_|fMRead~22_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N0 +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (!\z80_|execute_|ctl_sw_1d~3_combout & (!\z80_|execute_|ctl_im_we~combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~3_combout ), + .datac(\z80_|execute_|ctl_im_we~combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # (((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) # (!\z80_|execute_|ctl_bus_db_oe~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~3_combout = (\z80_|execute_|ctl_bus_zero_oe~2_combout ) # ((\z80_|decode_state_|in_halt~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~3 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_bus_zero_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|execute_|ctl_sw_1d~4_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'h000D; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [1] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[7]~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = ((!\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_flags_bus~8_combout & !\z80_|execute_|ctl_mRead~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hFF1F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal68~2_combout & !\z80_|pla_decode_|Equal20~0_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~10_combout & (\z80_|execute_|ctl_flags_bus~11_combout & \z80_|execute_|ctl_flags_bus~14_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~10_combout ), + .datac(\z80_|execute_|ctl_flags_bus~11_combout ), + .datad(\z80_|execute_|ctl_flags_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~16_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~17_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_mRead~24_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~17_combout & (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~28 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~28_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~28 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~28_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_inc_cy~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~16_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (\z80_|execute_|ctl_reg_out_lo~6_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout )) # +// (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~13_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~19_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~19 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_ir_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|ir_|opcode [7])) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~19_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|setM1~58_combout )) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_sw_2u~6_combout ) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|setM1~58_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout & (\z80_|execute_|ctl_reg_out_lo~2_combout & ((!\z80_|execute_|ctl_sw_2u~7_combout ) # (!\z80_|execute_|rsel0~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) # (!\z80_|execute_|ctl_sw_1d~4_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~4_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~29 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~3_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~4_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|rsel3~combout ) # ((!\z80_|execute_|ctl_reg_out_lo~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~3 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_reg_out_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~9_combout = (\z80_|execute_|ctl_sw_2u~7_combout & (\z80_|ir_|opcode [0] $ (((!\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1]))))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~9 .lut_mask = 16'h9500; +defparam \z80_|execute_|ctl_sw_2u~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|execute_|ctl_mWrite~18_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_out_hi~3_combout & (!\z80_|execute_|ctl_sw_2u~9_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .datac(\z80_|execute_|ctl_sw_2u~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) # (!\z80_|execute_|ctl_ir_we~19_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|execute_|ctl_ir_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~3_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h0888; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~14_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h30F0; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_alu_oe~10_combout & (\z80_|execute_|ctl_bus_db_we~6_combout & \z80_|execute_|ctl_reg_in_lo~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~10_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~8_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~8 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_sw_2u~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal69~0_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|pla_decode_|Equal20~0_combout & (\z80_|execute_|nextM~4_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0030; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~49_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|setM1~51_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h1050; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~9_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~9 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_sw_4d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~52_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h007F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout ) # ((\z80_|execute_|ctl_sw_2u~8_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~2_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~2 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_flags_alu~22_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # (\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~14_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & \z80_|execute_|ctl_reg_out_hi~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_use_sp~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (!\z80_|ir_|opcode [5] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~14_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAFAB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_sw_2u~3_combout & !\z80_|execute_|ctl_alu_shift_oe~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|setM1~19_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|setM1~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~8 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~8_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_cf_we~7_combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~8 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~15_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) +// # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~15 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_pf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~1_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_pf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & +// (((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_flags_pf_we~1_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_flags_alu~12_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_alu~17_combout )) # (!\z80_|execute_|ctl_flags_alu~23_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~12_combout ), + .datab(\z80_|execute_|ctl_flags_alu~23_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~5_combout )))) # (!\z80_|pla_decode_|Equal48~0_combout & +// (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFD; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_ir_we~13_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~16 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & +// (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_oe~16_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & \z80_|execute_|ctl_alu_core_S~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~16_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (\z80_|execute_|ctl_flags_pf_we~1_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~23_combout & (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~23_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~50_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~50 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal1~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~5_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~19_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = ((!\z80_|execute_|ixy_d~5_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2020; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~49_combout = ((\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~49 .lut_mask = 16'hD555; +defparam \z80_|execute_|ctl_alu_shift_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~49_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~51_combout = (\z80_|execute_|ctl_ir_we~11_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~51_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~14_combout & (\z80_|execute_|ctl_alu_shift_oe~51_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0EAA; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~48_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~14_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~48 .lut_mask = 16'hBAAA; +defparam \z80_|execute_|ctl_alu_shift_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & !\z80_|execute_|ctl_reg_gp_sel~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (((\z80_|execute_|ctl_alu_shift_oe~48_combout & !\z80_|execute_|ctl_alu_bs_oe~8_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (\z80_|execute_|ctl_alu_shift_oe~35_combout & (\z80_|execute_|ctl_alu_shift_oe~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ))) # (!\z80_|execute_|ixy_d~5_combout & +// (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = ((\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~24_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_ir_we~11_combout & +// (((\z80_|execute_|ctl_ir_we~14_combout & \z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~36_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~18_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'hF400; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~47_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~26_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (\z80_|execute_|ctl_mWrite~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & \z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (\z80_|execute_|ctl_alu_shift_oe~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_alu_bs_oe~combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|alu_|db_high[3]~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~17_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_alu_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_oe~5_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_alu_oe~8_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_66_oe~4_combout ) # (\z80_|execute_|ctl_alu_oe~13_combout ))) # (!\z80_|execute_|ctl_alu_oe~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~12_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # (((!\z80_|execute_|ctl_flags_alu~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|nextM~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (((\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~17_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~11_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0F07; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~10_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hDCFC; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = (\z80_|execute_|ctl_sw_2d~12_combout ) # (((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout )) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_sw_2d~12_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~15_combout ) # ((\z80_|execute_|ctl_reg_out_hi~5_combout ) # (\z80_|execute_|ctl_sw_2d~13_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~22_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal37~0_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|fMRead~10_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h1F00; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|fMRead~11_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~9_combout )) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~9_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~27_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~27 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_sel_wz~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal47~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'hAA00; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_in_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h2323; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & ((\z80_|execute_|ctl_reg_sel_wz~16_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'hAF03; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~22_combout = (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal5~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal5~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~3_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal2~3_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal5~2 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (((\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal5~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h0233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_mRead~9_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~4_combout & (\z80_|execute_|ctl_inc_dec~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_sw_1d~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|execute_|ctl_sw_4d~5_combout & (\z80_|execute_|ctl_reg_sel_wz~22_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h3F2A; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_al_we~7_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (!\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout & (!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~3_combout = (!\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~3 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_al_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (!\z80_|execute_|ctl_mRead~4_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'h4555; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )) # (!\z80_|execute_|ctl_al_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~3_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout ))) # (!\z80_|pla_decode_|Equal77~0_combout ) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & !\z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout )) # (!\z80_|execute_|ctl_alu_oe~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_ir_we~18_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (!\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0300; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & \z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~17_combout & (!\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~2_combout = (!\z80_|execute_|ctl_mRead~3_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # ((!\z80_|execute_|ctl_al_we~2_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = ((\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_al_we~4_combout ) # (\z80_|execute_|ctl_al_we~6_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~8_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout ))) # (!\z80_|execute_|setM1~55_combout ) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~9_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N25 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~0_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h0F0D; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & \z80_|pla_decode_|Equal52~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~8_combout ) # (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_reg_gp_sel~13_combout )) # (!\z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~9 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~9 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_pf_sel[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_flags_pf_we~2_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[2] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [2] = (\z80_|bus_control_|db[2]~14_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[2]~14_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h80FF; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal21~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~2_combout = ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # (\z80_|execute_|ctl_alu_op1_oe~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~2 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_alu_op1_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_ir_we~15_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h5400; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|execute_|ctl_alu_op_low~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~4_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~18_combout & ((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~13_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~11_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~36_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[3]~5_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_low[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFEE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N17 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N25 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFCA0; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # ((\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~7_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (((\z80_|execute_|ctl_alu_op_low~17_combout ) # (!\z80_|execute_|ctl_state_alu~7_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'h5FDF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout ) # (((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h00C0; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ixy_d~3_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal21~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88C0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|db_low[3]~5_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h5540; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N5 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( +// Equation(s): +// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [3])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hF351; +defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( +// Equation(s): +// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_low[3]~3_combout ), + .datad(\z80_|alu_|result_lo [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hF0A0; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_out_lo~9_combout & (\z80_|execute_|ctl_inc_cy~29_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~35_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~24_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~24 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_sel_wz~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout = (\z80_|execute_|ctl_mRead~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~25_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~24_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~25 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_sw_4u~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ctl_inc_cy~80_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~80_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout & (\z80_|execute_|ctl_inc_cy~79_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout & \z80_|execute_|ctl_inc_cy~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal4~0_combout & \z80_|sequencer_|DFFE_T5_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_inc_cy~72_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_inc_cy~72_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|execute_|ctl_inc_cy~44_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~73_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|ctl_inc_cy~44_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_bus_inc_oe~36_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (!\z80_|execute_|ctl_sw_4u~2_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~17_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~25_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~16_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'hF4F4; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (\z80_|execute_|ctl_reg_sel_pc~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ixy_d~16_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~22_combout = (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~22 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_pc~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_reg_sel_pc~8_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~22_combout & \z80_|execute_|ctl_reg_sel_pc~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sel_pc~11_combout & (\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & \z80_|execute_|ctl_inc_cy~35_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal21~1_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h0303; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0011; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|ixy_d~8_combout & (!\z80_|pla_decode_|Equal33~2_combout & ((!\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0105; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|pc_inc_hold~16_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~20_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_reg_sel_pc~16_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~20 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_bus_inc_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~21_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|ctl_bus_inc_oe~20_combout & !\z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~21 .lut_mask = 16'h0A8A; +defparam \z80_|execute_|ctl_bus_inc_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hF0C0; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~18_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEC00; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~19_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~19 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_bus_inc_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~19_combout & \z80_|execute_|ixy_d~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~4_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~20_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) # (!\z80_|execute_|ctl_reg_in_hi~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~11_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|ctl_reg_sel_pc~13_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (\z80_|execute_|setM1~55_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~16_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~6_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|ctl_reg_sys_hilo~6_combout ) # ((!\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3310; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal35~0_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'h0055; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~8_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # ((!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_inc_dec~3_combout & +// (!\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'h8ACF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h5100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~17_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h3B00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((\z80_|execute_|ctl_al_we~3_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h00A2; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_pc~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|execute_|ctl_reg_sel_wz~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~30_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~30 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_reg_sel_wz~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (!\z80_|execute_|ctl_reg_sel_wz~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (((!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout )) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFAFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~7_combout )) # (!\z80_|execute_|setM1~48_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_al_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~8_combout = ((\z80_|execute_|ctl_sw_4d~2_combout ) # ((\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_state_alu~3_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~8 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hBF00; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = (\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'h8C8C; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = (!\z80_|execute_|ctl_mWrite~8_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'h3233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~17_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~19_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~17 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_bus_inc_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~18_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_bus_inc_oe~38_combout & \z80_|execute_|ctl_bus_inc_oe~17_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~25_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~26_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~18_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~27_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = ((\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~36_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~22_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~22 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~23_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~23 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~73_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_inc_cy~44_combout & \z80_|execute_|ctl_inc_cy~74_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~24_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_bus_inc_oe~32_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~3_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # (\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [11]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = ((\z80_|reg_file_|db_hi_as[3]~9_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = (\z80_|execute_|ctl_alu_oe~17_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~2_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|pla_decode_|Equal25~0_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h00BF; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~17_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~17 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (!\z80_|pla_decode_|Equal49~0_combout & (!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|execute_|ctl_mRead~11_combout )) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_sw_1d~7_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & \z80_|execute_|ctl_reg_gp_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mRead~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~14_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (!\z80_|execute_|ctl_66_oe~4_combout & !\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~14 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_in_hi~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~15_combout = ((\z80_|execute_|ctl_reg_in_hi~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~15 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_in_hi~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )))) # (!\z80_|execute_|setM1~32_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ctl_al_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8FAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~7_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h3F2F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & ((\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|comb~1_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|comb~1_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~4_combout )) # +// (!\z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|execute_|fMRead~9_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~11_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ))) + + .dataa(\z80_|execute_|fMRead~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|fMRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|setM1~58_combout & \z80_|execute_|ctl_sw_2u~3_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|setM1~58_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (!\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'h00BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = (((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) # (!\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~3_combout = (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal1~2_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~3_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~4_combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~4 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & \z80_|execute_|ctl_sw_2u~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h000E; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~43_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~27_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .lut_mask = 16'h8DCD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~28_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_reg_gp_sel[1]~27_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_reg_use_sp~2_combout & \z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datad(\z80_|execute_|nextM~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~43_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~28_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & \z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~41_combout = (\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h8F88; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # (\z80_|pla_decode_|Equal5~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal5~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ))) # (!\z80_|execute_|ctl_alu_op_low~16_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|ir_|opcode [5]))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~38_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|execute_|ctl_mRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~39_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout )) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~37_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .lut_mask = 16'h08AA; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~40_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~37_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h5455; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hD800; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~6_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N11 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hE400; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0A0A; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_in_hi~6_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~23_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~20_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~23 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~29_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~21_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~29 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_sel_wz~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~26_combout = (\z80_|execute_|ctl_reg_sel_wz~23_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~25_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~22_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~26 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & !\z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0008; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFEFC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~15_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|gdfx_temp1[3]~31_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hA0A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~33_combout & (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~37_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'hC040; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~10_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & ((\z80_|alu_|db_low[3]~5_combout ) # ((!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_|db_low[3]~5_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~16_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (!\z80_|execute_|fMRead~27_combout ))) # (!\z80_|execute_|ctl_flags_bus~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~13_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~7_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout & +// (\z80_|alu_|db_low[3]~5_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N13 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~32 ( +// Equation(s): +// \z80_|alu_control_|db[3]~32_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (!\z80_|execute_|ctl_66_oe~combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~32 .lut_mask = 16'h1101; +defparam \z80_|alu_control_|db[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|db[3]~32_combout & ((\z80_|bus_control_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|alu_control_|db[3]~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hD0D0; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~18_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|pc_inc_hold~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mWrite~10_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0800; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ixy_d~16_combout ) # (\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hECA8; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~3_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hEAFA; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~20_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~21_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'h777F; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hABFF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (\z80_|execute_|pc_inc_hold~37_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|pc_inc_hold~37_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~27_combout & \z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout ))) # (!\z80_|execute_|ctl_inc_cy~78_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~64_combout & \z80_|execute_|ctl_inc_cy~65_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_mWrite~18_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~3_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = ((\z80_|execute_|ctl_inc_dec~6_combout ) # ((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~0_combout ))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'hDDFD; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_alu_oe~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~32_combout & \z80_|execute_|pc_inc_hold~28_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_inc_cy~69_combout & ((!\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~36_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~67_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFF2A; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (((!\z80_|execute_|ctl_inc_cy~33_combout ) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~28_combout )) # (!\z80_|execute_|ctl_inc_cy~29_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~29_combout ), + .datab(\z80_|execute_|ctl_inc_cy~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~36_combout ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((\z80_|execute_|ctl_inc_cy~71_combout ) # (!\z80_|execute_|ctl_inc_cy~74_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~32_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~75_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hEFCC; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (!\z80_|execute_|ctl_inc_cy~81_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|pc_inc_hold~38_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0A08; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & +// (\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_inc_cy~79_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_inc_cy~42_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~42_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~44_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~30_combout = ((!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~8_combout ))) # (!\z80_|execute_|ctl_mWrite~18_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & (!\z80_|execute_|pc_inc_hold~29_combout +// & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|ctl_inc_cy~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hB0BB; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (!\z80_|execute_|ctl_inc_cy~34_combout & (((\z80_|execute_|pc_inc_hold~19_combout & !\z80_|execute_|pc_inc_hold~23_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0545; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~48_combout ) # ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # (\z80_|execute_|ctl_inc_cy~47_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~48_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~46_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & (!\z80_|execute_|pc_inc_hold~20_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|execute_|ctl_inc_cy~60_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~20_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_mRead~34_combout & +// \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~9_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (!\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|execute_|ctl_inc_cy~56_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_inc_cy~57_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~57_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~20_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~21_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~8_combout & !\z80_|execute_|pc_inc_hold~20_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h888C; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|execute_|pc_inc_hold~31_combout & \z80_|execute_|ctl_mRead~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~31_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((\z80_|execute_|ctl_inc_cy~58_combout ) # (\z80_|execute_|ctl_inc_cy~53_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|ctl_inc_cy~61_combout ), + .datac(\z80_|execute_|ctl_inc_cy~58_combout ), + .datad(\z80_|execute_|ctl_inc_cy~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~77_combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # ((!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hC4F5; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((!\z80_|execute_|pc_inc_hold~30_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~27_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~30_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~78_combout & \z80_|execute_|pc_inc_hold~28_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((\z80_|execute_|ctl_inc_cy~39_combout ) # (\z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_inc_cy~62_combout ), + .datac(\z80_|execute_|ctl_inc_cy~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_inc_cy~76_combout ) # +// (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~66_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hCCC8; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|address_latch_|Q[3]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[3]~feeder_combout = \z80_|address_latch_|abusz [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = ((\z80_|execute_|ctl_inc_dec~7_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout = (\z80_|execute_|setM1~51_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|execute_|setM1~51_combout & (((\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout +// & \z80_|execute_|rsel0~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mWrite~18_combout ) # (\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hF4F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h006A; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ctl_mRead~23_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_ir_we~18_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~18_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|pla_decode_|Equal25~0_combout & (!\z80_|pla_decode_|Equal12~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (((\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h00C8; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_mRead~3_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~21_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'h8888; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[2]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~40_combout & (\z80_|reg_file_|gdfx_temp0[2]~36_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~38_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~41_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~43_combout = ((\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[2]~43_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~33_combout ) # ((\z80_|execute_|ctl_sw_4d~8_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_sw_4d~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|gdfx_temp0[1]~27_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~26_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~31_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~33_combout = ((\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[1]~33_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datac(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ +// (\z80_|address_latch_|Q [1]))))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N13 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [2]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [1]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h6666; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~13_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[3]~63_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~14_combout = (\z80_|reg_file_|db_lo_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~14 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~15_combout = ((\z80_|reg_file_|db_lo_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~15 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~57_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~35_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~58_combout = (\z80_|reg_file_|gdfx_temp0[3]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~59_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~61_combout = (\z80_|reg_file_|gdfx_temp0[3]~58_combout & (\z80_|reg_file_|gdfx_temp0[3]~60_combout & (\z80_|reg_file_|gdfx_temp0[3]~59_combout & \z80_|reg_file_|gdfx_temp0[3]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~62_combout = (\z80_|reg_file_|gdfx_temp0[3]~55_combout & (\z80_|reg_file_|gdfx_temp0[3]~61_combout & \z80_|reg_file_|gdfx_temp0[3]~54_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~63_combout = ((\z80_|reg_file_|gdfx_temp0[3]~62_combout & ((\z80_|reg_file_|db_lo_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & ((\z80_|reg_file_|gdfx_temp0[3]~63_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8A8A; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hB3BB; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[3]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~16_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~16_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~8_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~4_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|alu_control_|db[1]~22_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = (\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N31 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [3]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~67_combout = (\z80_|reg_file_|gdfx_temp0[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~65_combout = (\z80_|reg_file_|gdfx_temp0[4]~64_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~70_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~71_combout = (\z80_|reg_file_|gdfx_temp0[4]~70_combout & (\z80_|reg_file_|gdfx_temp0[4]~69_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .lut_mask = 16'h8A00; +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~72_combout = (\z80_|reg_file_|gdfx_temp0[4]~68_combout & (\z80_|reg_file_|gdfx_temp0[4]~67_combout & (\z80_|reg_file_|gdfx_temp0[4]~65_combout & \z80_|reg_file_|gdfx_temp0[4]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~73_combout = ((\z80_|reg_file_|gdfx_temp0[4]~72_combout & ((\z80_|reg_file_|db_lo_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~16_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~17_combout = (\z80_|reg_file_|db_lo_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~17 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~18_combout = ((\z80_|reg_file_|db_lo_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~18 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N15 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~49_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_high[2]~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N3 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = ((!\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|db_low[1]~15_combout & (\z80_|alu_|db_low[1]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hB030; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|execute_|ctl_alu_core_S~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|ir_|opcode [4]) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|execute_|ctl_alu_op_low~33_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~9_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|pla_decode_|Equal73~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (\z80_|execute_|ctl_state_alu~11_combout & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|execute_|ctl_state_alu~11_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'hCC40; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal73~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hA080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~20 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~20_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~20 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~20_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h0515; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|execute_|ctl_flags_cf_cpl~0_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & !\z80_|execute_|ctl_flags_cf_cpl~1_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[0]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h3336; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDD5D; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~25_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|gdfx_temp0[0]~17_combout & \z80_|reg_file_|gdfx_temp0[0]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~23_combout = ((\z80_|reg_file_|gdfx_temp0[0]~18_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[0]~4_combout = (\z80_|reg_file_|gdfx_temp0[0]~23_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[0]~4 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~23 ( +// Equation(s): +// \z80_|alu_control_|db[0]~23_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~8_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~18_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~23 .lut_mask = 16'hF500; +defparam \z80_|alu_control_|db[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[0]~12_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~24 ( +// Equation(s): +// \z80_|alu_control_|db[0]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_cf~combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0])) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~24 .lut_mask = 16'hF531; +defparam \z80_|alu_control_|db[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~25 ( +// Equation(s): +// \z80_|alu_control_|db[0]~25_combout = ((\z80_|reg_file_|db_lo_ds[0]~4_combout & (\z80_|alu_control_|db[0]~23_combout & \z80_|alu_control_|db[0]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .datab(\z80_|alu_control_|db[0]~23_combout ), + .datac(\z80_|alu_control_|db[0]~24_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~25 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_control_|db[0]~25_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # +// (!\z80_|alu_control_|db[0]~25_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[0]~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )) # (!\z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout = (\z80_|execute_|ixy_d~14_combout & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~0_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ) # ((\z80_|execute_|ctl_flags_cf2_we~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~9_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|ir_|opcode [6] & (\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout & !\z80_|ir_|opcode [7]))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'hFFE0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [7] & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[7]~20_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|alu_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~81_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~82_combout = (\z80_|reg_file_|gdfx_temp1[7]~79_combout & (\z80_|reg_file_|gdfx_temp1[7]~80_combout & (\z80_|reg_file_|gdfx_temp1[7]~81_combout & \z80_|reg_file_|gdfx_temp1[7]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~83_combout = (\z80_|reg_file_|gdfx_temp1[7]~77_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout & (\z80_|reg_file_|gdfx_temp1[7]~82_combout & \z80_|reg_file_|gdfx_temp1[7]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~23 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~24_combout = (\z80_|reg_file_|db_hi_as[7]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~24 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_hi_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~25_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [14]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~25 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~25_combout = ((\z80_|reg_file_|db_hi_as[7]~24_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~25 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~84_combout = ((\z80_|reg_file_|gdfx_temp1[7]~83_combout & ((\z80_|reg_file_|db_hi_as[7]~25_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & ((\z80_|alu_control_|db[7]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|alu_control_|db[7]~15_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~19_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # +// (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h5432; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hFE04; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8030; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_flags_alu~20_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hF2F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_core_S~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (((!\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # (((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBBB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout & +// \z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & !\z80_|pla_decode_|Equal71~2_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h2F3F; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|execute_|ctl_flags_nf_we~2_combout ) # ((!\z80_|execute_|ctl_flags_nf_we~1_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hEEEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_control_|db[1]~22_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~18_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h10F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0E0E; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h7773; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((\z80_|pla_decode_|Equal68~2_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hCC08; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal71~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~8_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal21~1_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout )))) # +// (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (((\z80_|execute_|ctl_alu_op_low~30_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((\z80_|execute_|ctl_alu_core_hf~21_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ixy_d~5_combout & ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_core_hf~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0302; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mWrite~10_combout & !\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hCC0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout ))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((!\z80_|execute_|ctl_alu_op_low~21_combout & \z80_|execute_|ctl_alu_core_hf~32_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((!\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_core_hf~40_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(gnd), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hF0CC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[0]~25_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N19 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N7 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hC0A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0E0A; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~34_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hB2E8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|pla_decode_|Equal71~2_combout ) # (\z80_|execute_|ctl_alu_core_S~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal71~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hAAAF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~17_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[1]~17_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N29 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|alu_|op2_high [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~1_combout & \z80_|alu_|alu_op1[1]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op1[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op2[1]~1_combout )))) # (!\z80_|alu_|alu_op1[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[1]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hCE8C; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'h0088; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|alu_|db[4]~10_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[4]~10_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~60_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & \z80_|reg_file_|gdfx_temp1[4]~61_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout & \z80_|reg_file_|gdfx_temp1[4]~58_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~19_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[4]~66_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = (\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~19_combout = ((\z80_|reg_file_|db_hi_as[4]~18_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~19 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~19_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout = \z80_|address_latch_|Q [12] $ ((((\z80_|execute_|ctl_inc_dec~11_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .lut_mask = 16'h02FD; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~16_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N5 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout = \z80_|address_latch_|Q [11] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # ((\z80_|execute_|ctl_inc_dec~11_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .lut_mask = 16'h1E0F; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = (\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~16_combout = ((\z80_|reg_file_|db_hi_as[5]~15_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~16 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~52_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~53_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout ) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout & \z80_|reg_file_|gdfx_temp1[5]~50_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~16_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// (((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_control_|db[5]~12_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[5]~23_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[1]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[5]~24_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~16_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[1]~16_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[1]~17_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N5 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA280; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h5051; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|pla_decode_|Equal71~2_combout ) # ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) # +// (!\z80_|execute_|ctl_alu_core_S~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal71~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'h45C7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .lut_mask = 16'hFF88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N27 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hC088; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~11_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[2]~11_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N11 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( +// Equation(s): +// \z80_|alu_|db_low[2]~6_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [2])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( +// Equation(s): +// \z80_|alu_|db_low[2]~7_combout = (\z80_|alu_|db_low[2]~6_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[2]~6_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( +// Equation(s): +// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'hFA00; +defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~16_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|gdfx_temp1[2]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = (\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~13_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N9 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (\z80_|address_latch_|Q [7] & !\z80_|execute_|ctl_inc_dec~10_combout +// )) # (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [7] & \z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1080; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~13_combout = ((\z80_|reg_file_|db_hi_as[2]~12_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~13 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~43_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~44_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout & (\z80_|reg_file_|gdfx_temp1[2]~41_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & \z80_|reg_file_|gdfx_temp1[2]~46_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~13_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~11_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[2]~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[2]~9_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|alu_|db_low[2]~9_combout ), + .datac(gnd), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hDD88; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = ((\z80_|alu_|db_low[2]~8_combout & ((\z80_|alu_|db_low[2]~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~8_combout ), + .datad(\z80_|alu_|db_low[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hF373; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[2]~13_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N27 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|alu_|op1_high [0]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~12_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|alu_control_|db[5]~12_combout +// & (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[5]~12_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~8 ( +// Equation(s): +// \z80_|alu_control_|db[5]~8_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|flags_yf~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~8 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[5]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[5]~0_combout = (\z80_|reg_file_|gdfx_temp0[5]~53_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[5]~0 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~9 ( +// Equation(s): +// \z80_|alu_control_|db[5]~9_combout = (\z80_|alu_control_|db[5]~8_combout & (\z80_|reg_file_|db_lo_ds[5]~0_combout & ((\z80_|bus_control_|db[5]~16_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|alu_control_|db[5]~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~9 .lut_mask = 16'hD000; +defparam \z80_|alu_control_|db[5]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~12 ( +// Equation(s): +// \z80_|alu_control_|db[5]~12_combout = ((\z80_|alu_control_|db[5]~9_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[5]~9_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~12 .lut_mask = 16'hBB3B; +defparam \z80_|alu_control_|db[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~47_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~48_combout = (\z80_|reg_file_|gdfx_temp0[5]~47_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~51_combout = (\z80_|reg_file_|gdfx_temp0[5]~49_combout & (\z80_|reg_file_|gdfx_temp0[5]~48_combout & (\z80_|reg_file_|gdfx_temp0[5]~50_combout & \z80_|reg_file_|gdfx_temp0[5]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~52_combout = (\z80_|reg_file_|gdfx_temp0[5]~44_combout & (\z80_|reg_file_|gdfx_temp0[5]~51_combout & \z80_|reg_file_|gdfx_temp0[5]~45_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~53_combout = ((\z80_|reg_file_|gdfx_temp0[5]~52_combout & ((\z80_|reg_file_|db_lo_as[5]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~10_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[5]~53_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~11_combout = (\z80_|reg_file_|db_lo_as[5]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~11 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~12_combout = ((\z80_|reg_file_|db_lo_as[5]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~12 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h6555; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~26_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[6]~82_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3393; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N9 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0DD0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~89_combout & (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[7]~92_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [7]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h9A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~7_combout = ((\z80_|reg_file_|db_hi_as[0]~6_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~7 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [0] & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[0]~18_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datac(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'hD000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~7_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datac(\z80_|alu_control_|db[0]~25_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[1]~12_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[1]~16_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hBBF3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = ((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hAF0F; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[1]~15_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hC4FF; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [5] & ((\z80_|alu_|db[0]~18_combout ))))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout +// & (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'h8E82; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'h08A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~3 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout & !\z80_|ir_|opcode [4])) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .lut_mask = 16'hFF0C; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[0]~18_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[0]~18_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h396C; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h555F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_|alu_op2[0]~3_combout )))) +// # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|alu_op2[0]~3_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|alu_op1[0]~1_combout ), + .datac(\z80_|alu_|alu_op2[0]~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hFE80; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N9 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = ((!\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|alu_|op1_low [0] & (((\z80_|alu_|op2_low [0])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [0] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|alu_|db_low[0]~20_combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|result_lo [0]), + .datac(\z80_|alu_|db_low[0]~20_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hE000; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((\z80_|alu_|db_low[0]~19_combout & \z80_|alu_|db_low[0]~22_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hCF0F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N27 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[0]~20_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[4]~10_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[0]~20_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hF7B3; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'h0022; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~22_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[0]~22_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|alu_control_|db[4]~31_combout & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|alu_control_|db[4]~31_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db[4]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( +// Equation(s): +// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( +// Equation(s): +// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db_low[3]~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hF5DD; +defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|alu_|db_low[3]~4_combout & \z80_|alu_|db_low[3]~1_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|alu_|db_low[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hF333; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[3]~7_combout & (\z80_|alu_|db_low[3]~5_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N25 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h27D8; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [3]))))) # +// (!\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|alu_|op1_low [3])) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hCCE4; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFC0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF3F2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~31_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~31_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFCB8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( +// Equation(s): +// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~26 ( +// Equation(s): +// \z80_|alu_control_|db[2]~26_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~26 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~5_combout = (\z80_|reg_file_|gdfx_temp0[2]~43_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~5 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_control_|db[2]~26_combout & (\z80_|reg_file_|db_lo_ds[2]~5_combout & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[2]~26_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = ((\z80_|alu_control_|db[2]~27_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~8_combout & (((\z80_|alu_control_|db[2]~28_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|execute_|ctl_flags_pf_we~8_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hE444; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h0770; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & (!\z80_|pla_decode_|Equal62~3_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h0CFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [6]))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|Q [6]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & (\z80_|address_latch_|Q [0] & !\z80_|address_latch_|Q [3]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0010; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [10] & !\z80_|address_latch_|Q [9]))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|Q [9]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [14] & !\z80_|address_latch_|Q [12]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~7_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~7_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE4F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80A2; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h80B0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|alu_|alu_parity_out~0_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h555A; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_pf_we~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hEAAA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h7F00; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hFCFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[1]~19_combout & !\z80_|alu_|db_high[2]~13_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~18_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hCC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~5_combout & (!\z80_|alu_|db_low[2]~11_combout & (!\z80_|alu_|db_low[1]~17_combout & !\z80_|alu_|db_low[0]~23_combout ))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|alu_|db_low[2]~11_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .lut_mask = 16'hF8F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hDF00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & (((\z80_|alu_control_|sel[1]~0_combout ) # (\z80_|alu_flags_|flags_cf~combout )))) # (!\z80_|ir_|opcode [4] & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAEA4; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~28_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|pla_decode_|Equal5~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = (\z80_|execute_|ctl_reg_sel_wz~16_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h3FBF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_bus_inc_oe~19_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~23_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~23 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sel_pc~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (!\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hCCDF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~21_combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~21 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_sel_pc~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~28_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_reg_sel_pc~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [1] & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~2_combout = (\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datad(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~2 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~4_combout = ((\z80_|reg_file_|db_hi_as[1]~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~4 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~10_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~10_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [14]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = (\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = ((\z80_|reg_file_|db_hi_as[6]~21_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~71_combout & \z80_|reg_file_|gdfx_temp1[6]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|gdfx_temp1[6]~68_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~22_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|alu_control_|db[6]~18_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[6]~21_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|alu_|op2_high [2] & (((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~11_combout & (((\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'h8C0C; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|execute_|ctl_alu_res_oe~2_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hFFF8; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~12_combout & \z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[2]~11_combout ))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0415; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hF0FB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # +// (\z80_|alu_|alu_op1[3]~2_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFD40; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [3]) +// # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hEF2F; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[3]~5_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFD55; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_control_|db[7]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & \z80_|alu_|db_high[3]~7_combout )))) # (!\z80_|alu_control_|db[7]~15_combout & +// (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_control_|db[7]~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~13 ( +// Equation(s): +// \z80_|alu_control_|db[7]~13_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~13 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_out_lo~3_combout & !\z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF08; +defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~14 ( +// Equation(s): +// \z80_|alu_control_|db[7]~14_combout = (\z80_|alu_control_|db[7]~13_combout & (\z80_|reg_file_|db_lo_ds[7]~1_combout & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[7]~13_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~14 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~15 ( +// Equation(s): +// \z80_|alu_control_|db[7]~15_combout = ((\z80_|alu_control_|db[7]~14_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[7]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~15 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~4 ( +// Equation(s): +// \z80_|bus_control_|db[7]~4_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~4 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~2_combout & \z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|fMRead~27_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~27_combout ), + .datac(\z80_|execute_|ixy_d~2_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|fMRead~36_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - .dataa(\z80_|execute_|fMRead~35_combout ), - .datab(\z80_|execute_|fMRead~34_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'h0A08; defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N30 +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~16 ( +// Equation(s): +// \z80_|execute_|nextM~16_combout = (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|nextM~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|nextM~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~20_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~20 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~20_combout & (((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) # (!\z80_|execute_|ctl_ir_we~20_combout & (\z80_|execute_|ctl_ir_we~19_combout & ((\z80_|ir_|opcode [7])))) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|execute_|ctl_ir_we~20_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~38 ( +// Equation(s): +// \z80_|execute_|fMRead~38_combout = (\z80_|execute_|fMRead~29_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|fMRead~30_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~38 .lut_mask = 16'hECCC; +defparam \z80_|execute_|fMRead~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = ((\z80_|execute_|fMRead~37_combout ) # ((\z80_|execute_|fMRead~38_combout ) # (!\z80_|execute_|nextM~16_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~37_combout ), + .datac(\z80_|execute_|nextM~16_combout ), + .datad(\z80_|execute_|fMRead~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~36_combout ) # (\z80_|execute_|fMRead~31_combout ))) # (!\z80_|execute_|fMRead~8_combout ) + + .dataa(\z80_|execute_|fMRead~8_combout ), + .datab(\z80_|execute_|fMRead~28_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|fMRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (!\z80_|execute_|fMWrite~0_combout & ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|fMRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ixy_d~16_combout )) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|fMRead~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|fMRead~13_combout ))) + + .dataa(\z80_|execute_|fMRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|fMRead~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~14_combout ) # ((\z80_|execute_|fMRead~17_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|fMRead~18_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) # (!\z80_|execute_|fMRead~22_combout ) + + .dataa(\z80_|execute_|fMRead~22_combout ), + .datab(\z80_|execute_|fMRead~18_combout ), + .datac(\z80_|execute_|ctl_sw_4d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|execute_|ctl_mRead~15_combout & +// ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~25_combout ) # (((!\z80_|execute_|pc_inc_hold~17_combout & \z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|fMRead~25_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|fMWrite~2_combout ) + + .dataa(\z80_|execute_|fMWrite~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|ctl_reg_sys_hilo~6_combout ))) + + .dataa(\z80_|execute_|fMRead~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|fMRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~35_combout )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), @@ -44338,1712 +39032,1971 @@ defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~6_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~2_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|execute_|ixy_d~2_combout ), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hF500; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) +// \z80_|execute_|ctl_iorw~12_combout = ((\z80_|ir_|opcode [7]) # ((!\z80_|ir_|opcode [6]) # (!\z80_|decode_state_|DFFE_instED~q ))) # (!\z80_|pla_decode_|Equal1~0_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .combout(\z80_|execute_|ctl_iorw~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~2_combout ) # ((!\z80_|execute_|ctl_iorw~12_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (!\z80_|execute_|ctl_iorw~12_combout & ((\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .combout(\z80_|execute_|ctl_iorw~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( // Equation(s): -// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~16_combout ) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .dataa(\z80_|execute_|nextM~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_iorw~8_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .combout(\z80_|execute_|ctl_iorw~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; -defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[4][3] ( +// Location: FF_X30_Y18_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N12 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\ula_|zx_keyboard_|keys[5][3]~q ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][3]~q ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hA2F3; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & -// !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; -defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; -defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & -// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N23 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N25 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N20 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[3][3]~q ), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'h8ACF; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; -defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; -defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & -// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N5 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N30 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hCF45; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N8 -cycloneive_lcell_comb \D[3]~72 ( -// Equation(s): -// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][3]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][3]~q ), - .cin(gnd), - .combout(\D[3]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'hA2F3; -defparam \D[3]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) - - .dataa(\D[3]~74_combout ), - .datab(\D[3]~73_combout ), - .datac(\D[3]~75_combout ), - .datad(\D[3]~72_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'h8000; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N2 -cycloneive_lcell_comb \D[3]~122 ( -// Equation(s): -// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[3]~76_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[3]~122_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~122 .lut_mask = 16'hEF00; -defparam \D[3]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N28 -cycloneive_lcell_comb \D[3]~79 ( -// Equation(s): -// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~79 .lut_mask = 16'h3332; -defparam \D[3]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N20 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # -// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hF5E4; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N22 -cycloneive_lcell_comb \D[3]~80 ( -// Equation(s): -// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) - - .dataa(gnd), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~80 .lut_mask = 16'hCFC0; -defparam \D[3]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N4 -cycloneive_lcell_comb \D[3]~81 ( -// Equation(s): -// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout -// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\D[3]~80_combout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~81 .lut_mask = 16'hF0DD; -defparam \D[3]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N30 -cycloneive_lcell_comb \D[3]~124 ( -// Equation(s): -// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~124_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~124 .lut_mask = 16'hF200; -defparam \D[3]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N0 -cycloneive_lcell_comb \D[3]~123 ( -// Equation(s): -// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~123_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~123 .lut_mask = 16'hF2D0; -defparam \D[3]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N10 -cycloneive_lcell_comb \D[3]~78 ( -// Equation(s): -// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - - .dataa(\Equal2~0_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[3]~124_combout ), - .datad(\D[3]~123_combout ), - .cin(gnd), - .combout(\D[3]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~78 .lut_mask = 16'h5410; -defparam \D[3]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N6 -cycloneive_lcell_comb \D[3]~82 ( -// Equation(s): -// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[3]~79_combout ), - .datac(\D[3]~81_combout ), - .datad(\D[3]~78_combout ), - .cin(gnd), - .combout(\D[3]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~82 .lut_mask = 16'hD580; -defparam \D[3]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N26 -cycloneive_lcell_comb \D[3]~108 ( -// Equation(s): -// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[3]~122_combout ), - .datac(gnd), - .datad(\D[3]~82_combout ), - .cin(gnd), - .combout(\D[3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hFFDD; -defparam \D[3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N8 -cycloneive_lcell_comb \D[3]~109 ( -// Equation(s): -// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(\D[3]~108_combout ), - .datad(\Equal2~1_combout ), - .cin(gnd), - .combout(\D[3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~109 .lut_mask = 16'hD0D5; -defparam \D[3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[3]~109_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N5 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|alu_control_|db[3]~36_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|execute_|ctl_iorw~9_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y8_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X30_Y18_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y1_N0 +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N27 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y18_N15 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(\z80_|memory_ifc_|wait_iorq~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~13_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout & (\z80_|execute_|ctl_mWrite~14_combout & (\z80_|execute_|ctl_mWrite~12_combout & \z80_|execute_|ctl_bus_db_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = (!\z80_|execute_|ixy_d~8_combout & !\z80_|pla_decode_|Equal33~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h0303; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = ((\z80_|execute_|ctl_mWrite~16_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~15_combout ))) # (!\z80_|execute_|ctl_mWrite~15_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y15_N21 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N3 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(gnd), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|mwr_wr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFFA0; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFF0; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # ((\z80_|sequencer_|M5~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # +// (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_mWrite~8_combout & !\z80_|execute_|ctl_mRead~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0055; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~0_combout ) # ((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|fMWrite~1_combout )))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h2322; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & ((\z80_|execute_|fMWrite~2_combout ) # (!\z80_|execute_|fMWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hA200; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~6_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((\z80_|execute_|ixy_d~2_combout ) # ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~2_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h8CCC; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_alu_oe~4_combout ) # ((\z80_|execute_|ctl_reg_in_hi~6_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|pla_decode_|Equal9~1_combout & +// ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|pla_decode_|Equal3~2_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h10F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h070F; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout & \z80_|execute_|fMRead~6_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout )) # +// (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h1F13; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fIOWrite~0_combout ) # ((!\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|execute_|fMWrite~5_combout & (\z80_|execute_|fMWrite~6_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'hC8FA; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~9_combout & (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~11_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_bus_inc_oe~18_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~13_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h40C0; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|execute_|ctl_inc_cy~31_combout & (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # +// (!\z80_|execute_|fIOWrite~5_combout & (((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h88F8; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hFF40; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N17 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N17 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \Equal5~0 ( +// Equation(s): +// \Equal5~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~0 .lut_mask = 16'h0080; +defparam \Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~18_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|address_latch_|abusz [1]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h00DD; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~35_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h44F4; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N10 +cycloneive_lcell_comb \Equal3~0 ( +// Equation(s): +// \Equal3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((!\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|address_pins_|DFFE_apin_latch [1])) # (!\z80_|address_pins_|DFFE_apin_latch [0]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~0 .lut_mask = 16'h2AAA; +defparam \Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [6]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[6]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~26 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N16 +cycloneive_lcell_comb \Equal3~1 ( +// Equation(s): +// \Equal3~1_combout = (((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|address_pins_|DFFE_apin_latch [4])) # (!\z80_|address_pins_|DFFE_apin_latch [3]) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~1 .lut_mask = 16'hF7FF; +defparam \Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N0 +cycloneive_lcell_comb \Equal3~2 ( +// Equation(s): +// \Equal3~2_combout = (\Equal3~0_combout ) # ((\z80_|address_pins_|abus[6]~25_combout ) # ((\z80_|address_pins_|abus[7]~26_combout ) # (\Equal3~1_combout ))) + + .dataa(\Equal3~0_combout ), + .datab(\z80_|address_pins_|abus[6]~25_combout ), + .datac(\z80_|address_pins_|abus[7]~26_combout ), + .datad(\Equal3~1_combout ), + .cin(gnd), + .combout(\Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~2 .lut_mask = 16'hFFFE; +defparam \Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \D[5]~26 ( +// Equation(s): +// \D[5]~26_combout = (\Equal5~1_combout & ((!\Equal3~2_combout ) # (!\Equal5~0_combout ))) + + .dataa(\Equal5~1_combout ), + .datab(gnd), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\D[5]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~26 .lut_mask = 16'h0AAA; +defparam \D[5]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [15])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [15]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~23 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[15]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h1000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~24 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~27 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~28 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[3]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~30 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[5]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~17 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[8]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~16 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|address_latch_|abusz [10]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [11]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~18 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -46059,10 +41012,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46100,7 +41053,170 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: FF_X21_Y15_N25 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N23 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0088; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -46116,10 +41232,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46157,7 +41273,96 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: LCCOMB_X29_Y12_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~20_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~22_combout & \z80_|address_pins_|abus[15]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -46173,10 +41378,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46214,10 +41419,10 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) @@ -46226,52 +41431,776 @@ cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .lut_mask = 16'hBBC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N2 -cycloneive_lcell_comb \D[5]~97 ( +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( // Equation(s): -// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\D[5]~97_combout ), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[5]~97 .lut_mask = 16'h2000; -defparam \D[5]~97 .sum_lutc_input = "datac"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), +// Location: FF_X31_Y22_N13 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N29 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (!\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0400; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N29 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N11 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N27 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N17 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h9933; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N19 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] $ (VCC))) # (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0])) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N1 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N5 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(\ula_|video_|Add4~12_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N19 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & ((\ula_|video_|Add4~4_combout )))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vram_address[10]~2_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|Add4~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N25 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~12_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFAA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N31 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -46279,16 +42208,181 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hD9C8; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -46342,283 +42436,111 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N6 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \Selector0~1 ( // Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # (!\Selector0~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\Selector0~0_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector0~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hB9A8; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector0~1 .lut_mask = 16'hF838; +defparam \Selector0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N4 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \D[7]~36 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \D[7]~36_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector0~1_combout ))))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), + .datad(\Selector0~1_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\D[7]~36_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \D[7]~36 .lut_mask = 16'h5140; +defparam \D[7]~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N20 -cycloneive_lcell_comb \D[7]~116 ( +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \D[7]~37 ( // Equation(s): -// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) +// \D[7]~37_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~36_combout ) # (!\D[5]~26_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~36_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datab(\D[5]~97_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~116_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~116 .lut_mask = 16'hBFB3; -defparam \D[7]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N26 -cycloneive_lcell_comb \D[7]~117 ( -// Equation(s): -// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), + .dataa(\z80_|data_pins_|dout [7]), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [7]), - .datad(\D[7]~116_combout ), + .datac(\D[5]~26_combout ), + .datad(\D[7]~36_combout ), .cin(gnd), - .combout(\D[7]~117_combout ), + .combout(\D[7]~37_combout ), .cout()); // synopsys translate_off -defparam \D[7]~117 .lut_mask = 16'hF311; -defparam \D[7]~117 .sum_lutc_input = "datac"; +defparam \D[7]~37 .lut_mask = 16'hBB0B; +defparam \D[7]~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N0 +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \D[7]~48 ( +// Equation(s): +// \D[7]~48_combout = (\D[7]~37_combout ) # (!\D[0]~49_combout ) + + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), + .cin(gnd), + .combout(\D[7]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~48 .lut_mask = 16'hFF33; +defparam \D[7]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~48_combout )))) # (!\z80_|bus_control_|db[7]~6_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~48_combout )))) - .dataa(\z80_|bus_control_|db[7]~7_combout ), + .dataa(\z80_|bus_control_|db[7]~6_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[7]~117_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[7]~48_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N1 +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFF8; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 dffeas \z80_|data_pins_|dout[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), @@ -46637,33 +42559,33 @@ defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~6 ( // Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[7]~6_combout = ((\z80_|bus_control_|db[7]~4_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[7]~5_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[7]~4_combout ), .datad(\z80_|data_pins_|dout [7]), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), + .combout(\z80_|bus_control_|db[7]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[7]~6 .lut_mask = 16'hF575; +defparam \z80_|bus_control_|db[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N13 +// Location: FF_X29_Y17_N3 dffeas \z80_|ir_|opcode[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|bus_control_|db[7]~6_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [7]), @@ -46673,93 +42595,3266 @@ defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & \z80_|ir_|opcode [6])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~0_combout & (\z80_|execute_|ctl_mWrite~7_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((!\z80_|execute_|fIOWrite~0_combout & \z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|fIORead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~6_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~5_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0500; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~59 ( +// Equation(s): +// \z80_|execute_|setM1~59_combout = (!\z80_|execute_|ctl_mRead~11_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~59 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & (\z80_|execute_|setM1~39_combout & (!\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|setM1~59_combout ))) + + .dataa(\z80_|execute_|setM1~40_combout ), + .datab(\z80_|execute_|setM1~39_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|setM1~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0800; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_mRead~22_combout & \z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFFC0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~29_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (!\z80_|execute_|ctl_mRead~27_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ctl_mRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y17_N21 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: FF_X32_Y15_N9 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N27 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \Equal5~1 ( +// Equation(s): +// \Equal5~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~1 .lut_mask = 16'h0808; +defparam \Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \Selector10~0 ( +// Equation(s): +// \Selector10~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~0 .lut_mask = 16'hD9C8; +defparam \Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \Selector10~1 ( +// Equation(s): +// \Selector10~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector10~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector10~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector10~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\Selector10~0_combout ), + .cin(gnd), + .combout(\Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~1 .lut_mask = 16'hBBC0; +defparam \Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y29_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|clk_filter [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N17 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [1]), + .datab(\ula_|ps2_keyboard_|clk_filter [3]), + .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N1 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y21_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y20_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hC4C4; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N25 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF850; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N21 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~52_combout = (\ula_|zx_keyboard_|keys[3][2]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~52 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~51_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~54_combout = (\ula_|zx_keyboard_|keys[2][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~53_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~54 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N17 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~5 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~5_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~5 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~48 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|keys[0][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (\ula_|zx_keyboard_|keys[0][2]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[0][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[0][2]~48_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~46_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~46 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h0088; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[3][3]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N21 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~4_combout = (\ula_|zx_keyboard_|keys[0][2]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\ula_|zx_keyboard_|keys[0][2]~q & +// (((\z80_|address_pins_|abus[9]~16_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~q ), + .datab(\ula_|zx_keyboard_|keys[1][2]~q ), + .datac(\z80_|address_pins_|abus[9]~16_combout ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~4 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~60_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h0A0A; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hC888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N23 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hCCFC; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~59_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~59 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[7][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[7][2]~63_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][2]~q ))))) # (!\ula_|zx_keyboard_|keys[7][2]~63_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~66 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[6][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~66_combout & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~65_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~65 .lut_mask = 16'hFF0C; +defparam \ula_|zx_keyboard_|keys[5][0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|zx_keyboard_|keys[6][2]~67_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|zx_keyboard_|keys[6][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~7 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~7_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~22_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~7 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][2]~30_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|zx_keyboard_|keys[5][2]~55_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~55_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~57_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~57 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~129_combout = (\ula_|zx_keyboard_|keys[4][2]~57_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~129 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[4][2]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~128_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~128 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|zx_keyboard_|keys[4][2]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~6 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~6_combout = (\ula_|zx_keyboard_|keys[5][2]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~6 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [2] = (\ula_|zx_keyboard_|key_row[2]~5_combout & (\ula_|zx_keyboard_|key_row[2]~4_combout & (\ula_|zx_keyboard_|key_row[2]~7_combout & \ula_|zx_keyboard_|key_row[2]~6_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .datab(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .datac(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .datad(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [2]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \Selector14~17 ( +// Equation(s): +// \Selector14~17_combout = (\Equal5~0_combout & (((!\z80_|address_pins_|DFFE_apin_latch [0] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\Equal3~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~17_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~17 .lut_mask = 16'h40F0; +defparam \Selector14~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \Selector14~18 ( +// Equation(s): +// \Selector14~18_combout = (\Equal5~0_combout & (((!\Equal3~2_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [15]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~18_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~18 .lut_mask = 16'h0BFB; +defparam \Selector14~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N22 +cycloneive_io_ibuf \kempston[1]~input ( + .i(kempston[1]), + .ibar(gnd), + .o(\kempston[1]~input_o )); +// synopsys translate_off +defparam \kempston[1]~input .bus_hold = "false"; +defparam \kempston[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \Selector10~2 ( +// Equation(s): +// \Selector10~2_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[1]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [2])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [2]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[1]~input_o ), + .cin(gnd), + .combout(\Selector10~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~2 .lut_mask = 16'h0BCB; +defparam \Selector10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \Selector10~3 ( +// Equation(s): +// \Selector10~3_combout = (\Equal5~0_combout & (((\Selector10~2_combout )))) # (!\Equal5~0_combout & ((\Selector10~2_combout & ((\Selector10~1_combout ))) # (!\Selector10~2_combout & +// (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector10~1_combout ), + .datad(\Selector10~2_combout ), + .cin(gnd), + .combout(\Selector10~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~3 .lut_mask = 16'hFC22; +defparam \Selector10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \D[2]~13 ( +// Equation(s): +// \D[2]~13_combout = (\Equal5~1_combout & (\Selector10~3_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout +// ))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Selector10~3_combout ), + .datad(\z80_|data_pins_|dout [2]), + .cin(gnd), + .combout(\D[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~13 .lut_mask = 16'hF531; +defparam \D[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\D[2]~13_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[2]~14_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[2]~13_combout & (\z80_|bus_control_|db[2]~14_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\D[2]~13_combout ), + .datab(\z80_|bus_control_|db[2]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N23 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[2]~28_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~14 ( +// Equation(s): +// \z80_|bus_control_|db[2]~14_combout = ((\z80_|bus_control_|db[2]~13_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|bus_control_|db[0]~5_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~14 .lut_mask = 16'h8FCF; +defparam \z80_|bus_control_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N1 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~14_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hC800; defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 +// Location: LCCOMB_X29_Y14_N12 cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), .datad(\z80_|pla_decode_|Equal41~1_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N8 +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~17_combout = ((\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~17 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_ir_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[4]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~3_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~2_combout = (!\z80_|ir_|opcode [5] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal2~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal2~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( // Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # -// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_state_tbl_cb_set~2_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .dataa(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hBAAA; defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N9 +// Location: FF_X29_Y18_N15 dffeas \z80_|decode_state_|DFFE_instCB ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), @@ -46778,941 +45873,1095 @@ defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y6_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - .dataa(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|decode_state_|table_xx~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal47~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y12_N29 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_66_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [0] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[6]~8_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~16 ( +// Equation(s): +// \z80_|alu_control_|db[6]~16_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~16 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[6]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~2_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~2 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~17 ( +// Equation(s): +// \z80_|alu_control_|db[6]~17_combout = (\z80_|alu_control_|db[6]~16_combout & (\z80_|reg_file_|db_lo_ds[6]~2_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|db[6]~16_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~17 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[6]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~18 ( +// Equation(s): +// \z80_|alu_control_|db[6]~18_combout = ((\z80_|alu_control_|db[6]~17_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .datab(\z80_|alu_control_|db[6]~17_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( +// Equation(s): +// \z80_|bus_control_|db[6]~7_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'h8A8A; +defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \D[6]~28 ( +// Equation(s): +// \D[6]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~28 .lut_mask = 16'hFFCF; +defparam \D[6]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \D[6]~43 ( +// Equation(s): +// \D[6]~43_combout = (\Equal5~0_combout & (\Equal3~2_combout & ((\D[6]~28_combout )))) # (!\Equal5~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\Equal5~0_combout ), + .datab(\Equal3~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\D[6]~28_combout ), + .cin(gnd), + .combout(\D[6]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~43 .lut_mask = 16'hD850; +defparam \D[6]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[6]~44 ( +// Equation(s): +// \D[6]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\Equal5~0_combout & ((\D[6]~43_combout ))) # (!\Equal5~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[6]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\Equal5~0_combout ), + .datad(\D[6]~43_combout ), + .cin(gnd), + .combout(\D[6]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~44 .lut_mask = 16'hFB08; +defparam \D[6]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[6]~42 ( +// Equation(s): +// \D[6]~42_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[6]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~42 .lut_mask = 16'hAACC; +defparam \D[6]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[6]~45 ( +// Equation(s): +// \D[6]~45_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~44_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Equal5~0_combout & (\D[6]~44_combout )) # (!\Equal5~0_combout & +// ((\D[6]~42_combout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\D[6]~44_combout ), + .datad(\D[6]~42_combout ), + .cin(gnd), + .combout(\D[6]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~45 .lut_mask = 16'hF1E0; +defparam \D[6]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) # (!\z80_|address_pins_|abus[14]~22_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux1~0 .lut_mask = 16'hDC98; +defparam \Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[6]~41 ( +// Equation(s): +// \D[6]~41_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux1~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # (!\Mux1~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux1~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Mux1~0_combout ), + .cin(gnd), + .combout(\D[6]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~41 .lut_mask = 16'hF388; +defparam \D[6]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[6]~46 ( +// Equation(s): +// \D[6]~46_combout = (\Equal5~0_combout & (((\D[6]~45_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\D[6]~45_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\D[6]~41_combout ))))) + + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\D[6]~45_combout ), + .datad(\D[6]~41_combout ), + .cin(gnd), + .combout(\D[6]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~46 .lut_mask = 16'hF1E0; +defparam \D[6]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[6]~47 ( +// Equation(s): +// \D[6]~47_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~46_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~46_combout ), + .cin(gnd), + .combout(\D[6]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~47 .lut_mask = 16'hAF23; +defparam \D[6]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~47_combout )))) # (!\z80_|bus_control_|db[6]~8_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~47_combout )))) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[6]~47_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = ((\z80_|bus_control_|db[6]~7_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[6]~7_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~8_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~8_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N29 +dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), + .q(\z80_|ir_|opcode [6]), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~18 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) +// \z80_|execute_|ctl_ir_we~18_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|im2~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .combout(\z80_|execute_|ctl_ir_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~16 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_bus_inc_oe~16_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_bus_inc_oe~15_combout )) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_mWrite~12_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|ctl_bus_db_we~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~18_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~10 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_bus_db_we~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( // Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) +// \z80_|execute_|ctl_bus_db_we~7_combout = (((\z80_|execute_|ctl_bus_db_we~10_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_bus_db_we~6_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~10_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_ir_we~8_combout ))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~9 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|execute_|ctl_bus_db_we~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~9 .lut_mask = 16'h4440; +defparam \z80_|execute_|ctl_bus_db_we~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|execute_|ctl_bus_db_we~5_combout ) # ((\z80_|execute_|ctl_bus_db_we~4_combout ) # (\z80_|execute_|ctl_bus_db_we~9_combout ))) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout -// )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; -defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N1 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N28 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hD0DD; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; -defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & -// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; -defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & -// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N2 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~q ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'h8ACF; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & -// \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; -defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .datac(\ula_|zx_keyboard_|keys~69_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; -defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys~71_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y8_N11 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N15 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N17 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][0]~q ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'h8CAF; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N12 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), - .datab(\z80_|address_pins_|abus[9]~17_combout ), - .datac(\ula_|zx_keyboard_|key_row~2_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hD000; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) - - .dataa(\D[0]~57_combout ), - .datab(\D[0]~56_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[0]~55_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hF8F0; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -47728,10 +46977,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47769,140 +47018,879 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N12 -cycloneive_lcell_comb \D[0]~62 ( +// Location: LCCOMB_X19_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( // Equation(s): -// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\D[0]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), .cout()); // synopsys translate_off -defparam \D[0]~62 .lut_mask = 16'hEC64; -defparam \D[0]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'hFF30; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'h1204; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][1]~34_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|keys[4][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~83_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~82_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[5][0]~79_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h2080; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|zx_keyboard_|keys[5][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~10_combout = (\ula_|zx_keyboard_|keys[4][0]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) # (!\ula_|zx_keyboard_|keys[4][0]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~10 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~130_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~76_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~130 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & ((\ula_|zx_keyboard_|keys[7][0]~85_combout ) # (\ula_|zx_keyboard_|keys[7][0]~130_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N17 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~11 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~11_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][0]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~11 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg +// [5] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (!\ula_|zx_keyboard_|extended~q & ((\ula_|ps2_keyboard_|shiftreg [3]) # ((!\ula_|zx_keyboard_|keys[4][1]~29_combout ) # (!\ula_|zx_keyboard_|WideOr4~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h0B0F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~72_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~45_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~72 .lut_mask = 16'h335F; +defparam \ula_|zx_keyboard_|keys~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~71_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~71 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~73_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~72_combout & \ula_|zx_keyboard_|keys[4][3]~71_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys~72_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~73 .lut_mask = 16'h4C0C; +defparam \ula_|zx_keyboard_|keys[0][0]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys~74_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~74_combout & ((\ula_|zx_keyboard_|keys[0][0]~73_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[0][0]~73_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys~74_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hCC00; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~69_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~69 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][0]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~70_combout = (\ula_|zx_keyboard_|keys[1][0]~69_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~69_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~70 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~8 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~8_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\z80_|address_pins_|abus[9]~16_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~8 .lut_mask = 16'hDD0D; +defparam \ula_|zx_keyboard_|key_row[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~78 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[2][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~77_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~76_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~77 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~9 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~9_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~19_combout & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & +// (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~9 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [0] = (\ula_|zx_keyboard_|key_row[0]~10_combout & (\ula_|zx_keyboard_|key_row[0]~11_combout & (\ula_|zx_keyboard_|key_row[0]~8_combout & \ula_|zx_keyboard_|key_row[0]~9_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .datab(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .datac(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .datad(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [0]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y34_N22 +cycloneive_io_ibuf \kempston[3]~input ( + .i(kempston[3]), + .ibar(gnd), + .o(\kempston[3]~input_o )); +// synopsys translate_off +defparam \kempston[3]~input .bus_hold = "false"; +defparam \kempston[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \Selector14~8 ( +// Equation(s): +// \Selector14~8_combout = (\Selector14~18_combout & (((!\kempston[3]~input_o & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row [0]) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [0]), + .datab(\Selector14~18_combout ), + .datac(\kempston[3]~input_o ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~8 .lut_mask = 16'h2E33; +defparam \Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \Selector14~13 ( +// Equation(s): +// \Selector14~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\Selector14~8_combout ) # ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a +// [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~13 .lut_mask = 16'hFFEA; +defparam \Selector14~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -47918,10 +47906,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47959,27 +47947,9 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N8 -cycloneive_lcell_comb \D[0]~63 ( -// Equation(s): -// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~62_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~63 .lut_mask = 16'hE3E0; -defparam \D[0]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -47987,16 +47957,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48050,7 +48020,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y4_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), @@ -48060,16 +48030,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48108,27 +48078,176 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \Selector14~19 ( // Equation(s): -// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) +// \Selector14~19_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\Selector14~19_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hE6A2; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \Selector14~19 .lut_mask = 16'hF4B0; +defparam \Selector14~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y29_N0 +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \Selector14~10 ( +// Equation(s): +// \Selector14~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~10 .lut_mask = 16'hFA0A; +defparam \Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \Selector14~11 ( +// Equation(s): +// \Selector14~11_combout = (\Selector14~8_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((!\Selector14~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector14~10_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~11 .lut_mask = 16'hCC0A; +defparam \Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -48136,16 +48255,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48198,7 +48317,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y11_N0 +// Location: M9K_X22_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -48208,16 +48327,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48256,104 +48375,102 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N28 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \Selector14~20 ( // Equation(s): -// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) +// \Selector14~20_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'h30CA; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N10 -cycloneive_lcell_comb \D[0]~61 ( -// Equation(s): -// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) - - .dataa(\D[0]~59_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\D[0]~60_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~61_combout ), + .combout(\Selector14~20_combout ), .cout()); // synopsys translate_off -defparam \D[0]~61 .lut_mask = 16'h99A8; -defparam \D[0]~61 .sum_lutc_input = "datac"; +defparam \Selector14~20 .lut_mask = 16'hF2D0; +defparam \Selector14~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N18 -cycloneive_lcell_comb \D[0]~120 ( +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \Selector14~9 ( // Equation(s): -// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~63_combout )))) +// \Selector14~9_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector14~20_combout )) # (!\Selector14~8_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~63_combout ), - .datad(\D[0]~61_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\Selector14~20_combout ), + .datad(\Selector14~8_combout ), .cin(gnd), - .combout(\D[0]~120_combout ), + .combout(\Selector14~9_combout ), .cout()); // synopsys translate_off -defparam \D[0]~120 .lut_mask = 16'hF4B0; -defparam \D[0]~120 .sum_lutc_input = "datac"; +defparam \Selector14~9 .lut_mask = 16'hDC33; +defparam \Selector14~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N26 -cycloneive_lcell_comb \D[0]~64 ( +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \Selector14~12 ( // Equation(s): -// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) +// \Selector14~12_combout = (\Selector14~11_combout & (\Selector14~8_combout & ((\Selector14~19_combout ) # (\Selector14~9_combout )))) # (!\Selector14~11_combout & (((\Selector14~9_combout )))) - .dataa(\D[0]~58_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[0]~120_combout ), + .dataa(\Selector14~19_combout ), + .datab(\Selector14~8_combout ), + .datac(\Selector14~11_combout ), + .datad(\Selector14~9_combout ), .cin(gnd), - .combout(\D[0]~64_combout ), + .combout(\Selector14~12_combout ), .cout()); // synopsys translate_off -defparam \D[0]~64 .lut_mask = 16'hBF8F; -defparam \D[0]~64 .sum_lutc_input = "datac"; +defparam \Selector14~12 .lut_mask = 16'hCF80; +defparam \Selector14~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N16 -cycloneive_lcell_comb \D[0]~65 ( +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \Selector14~14 ( // Equation(s): -// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) +// \Selector14~14_combout = (\Selector14~12_combout & ((\Selector14~13_combout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\Selector14~13_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\Selector14~12_combout ), + .cin(gnd), + .combout(\Selector14~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~14 .lut_mask = 16'hBA00; +defparam \Selector14~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \D[0]~14 ( +// Equation(s): +// \D[0]~14_combout = (\z80_|data_pins_|dout [0] & (((\Selector14~14_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [0]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[0]~64_combout ), - .datad(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), - .combout(\D[0]~65_combout ), + .combout(\D[0]~14_combout ), .cout()); // synopsys translate_off -defparam \D[0]~65 .lut_mask = 16'hB0B3; -defparam \D[0]~65 .sum_lutc_input = "datac"; +defparam \D[0]~14 .lut_mask = 16'hAF23; +defparam \D[0]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N26 +// Location: LCCOMB_X26_Y16_N8 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & -// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[0]~12_combout & +// (((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\D[0]~65_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\D[0]~14_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), .cout()); @@ -48362,7 +48479,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N27 +// Location: FF_X26_Y16_N9 dffeas \z80_|data_pins_|dout[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), @@ -48381,50 +48498,51 @@ defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~11 ( // Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[0]~11_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|alu_control_|db[0]~25_combout ) # ((!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|execute_|ctl_bus_ff_oe~1_combout & +// (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|data_pins_|dout [0]), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|alu_control_|db[0]~25_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), + .combout(\z80_|bus_control_|db[0]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~11 .lut_mask = 16'h8ACF; +defparam \z80_|bus_control_|db[0]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~12 ( // Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[0]~12_combout = ((\z80_|bus_control_|db[0]~11_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[0]~16_combout ), - .datab(\z80_|alu_control_|db[0]~14_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|bus_control_|db[0]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), + .combout(\z80_|bus_control_|db[0]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~12 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N19 +// Location: FF_X26_Y15_N15 dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), + .d(\z80_|bus_control_|db[0]~12_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [0]), @@ -48434,2832 +48552,311 @@ defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y7_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( // Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal3~2_combout ), + .dataa(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y7_N31 -dffeas \z80_|decode_state_|DFFE_instIY1 ( +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((\z80_|alu_control_|db[4]~31_combout & \z80_|execute_|ctl_flags_bus~combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))) # +// (!\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_control_|db[4]~31_combout & ((\z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hCE0A; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # -// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~12_combout ), - .datac(\z80_|execute_|ixy_d~13_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|ixy_d~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~11_combout ), - .datac(\z80_|execute_|ctl_alu_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N0 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~20_combout ), - .datad(\z80_|alu_|db[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|alu_control_|db[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; -defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( -// Equation(s): -// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|sw1_|db_down[1]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; -defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; -defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N9 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; -defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y10_N25 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; -defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N28 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hCF45; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N12 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|key_row~0_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hB000; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; -defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & -// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N16 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), - .datab(\ula_|zx_keyboard_|keys[0][1]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hF531; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N21 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N8 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'h8ACF; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N6 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~33_combout ), - .datab(\D[1]~30_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF8F0; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N22 -cycloneive_lcell_comb \D[1]~38 ( -// Equation(s): -// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .cin(gnd), - .combout(\D[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~38 .lut_mask = 16'hE6A2; -defparam \D[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N4 -cycloneive_lcell_comb \D[1]~39 ( -// Equation(s): -// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\D[1]~38_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\D[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~39 .lut_mask = 16'hE5E0; -defparam \D[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N24 -cycloneive_lcell_comb \D[1]~35 ( -// Equation(s): -// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\D[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~35 .lut_mask = 16'hEA62; -defparam \D[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N14 -cycloneive_lcell_comb \D[1]~36 ( -// Equation(s): -// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~36 .lut_mask = 16'h44B8; -defparam \D[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \D[1]~37 ( -// Equation(s): -// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datac(\D[1]~36_combout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~37 .lut_mask = 16'hAE50; -defparam \D[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[1]~118 ( -// Equation(s): -// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[1]~39_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[1]~39_combout ), - .datad(\D[1]~37_combout ), - .cin(gnd), - .combout(\D[1]~118_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~118 .lut_mask = 16'hF4B0; -defparam \D[1]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N2 -cycloneive_lcell_comb \D[1]~40 ( -// Equation(s): -// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[1]~34_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[1]~118_combout ), - .cin(gnd), - .combout(\D[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~40 .lut_mask = 16'hBF8F; -defparam \D[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N12 -cycloneive_lcell_comb \D[1]~41 ( -// Equation(s): -// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[1]~40_combout ), - .cin(gnd), - .combout(\D[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~41 .lut_mask = 16'hAF03; -defparam \D[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & -// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[1]~41_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[1]~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[1]~10_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N1 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~1_combout ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .combout(\z80_|alu_flags_|flags_hf~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h31CE; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y9_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N16 -cycloneive_lcell_comb \D[4]~88 ( +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~29 ( // Equation(s): -// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_control_|db[4]~29_combout = (\z80_|reg_file_|gdfx_temp0[4]~73_combout & (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # +// ((!\z80_|alu_|db[4]~10_combout & \z80_|execute_|ctl_sw_2u~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .dataa(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), .cin(gnd), - .combout(\D[4]~88_combout ), + .combout(\z80_|alu_control_|db[4]~29_combout ), .cout()); // synopsys translate_off -defparam \D[4]~88 .lut_mask = 16'hD0DD; -defparam \D[4]~88 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~29 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|alu_control_|db[4]~30_combout = (!\z80_|alu_control_|db[4]~29_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_control_|db[4]~29_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h2300; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|alu_control_|db[4]~31_combout = ((\z80_|alu_control_|db[4]~30_combout & ((\z80_|bus_control_|db[4]~18_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|bus_control_|db[4]~18_combout ), + .datab(\z80_|alu_control_|db[4]~30_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h8FCF; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N28 -cycloneive_lcell_comb \D[4]~87 ( -// Equation(s): -// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\D[4]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'h8ACF; -defparam \D[4]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N21 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|Equal0~2_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N15 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N6 -cycloneive_lcell_comb \D[4]~85 ( -// Equation(s): -// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~85 .lut_mask = 16'hA2F3; -defparam \D[4]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y11_N20 -cycloneive_lcell_comb \D[4]~86 ( -// Equation(s): -// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|key_row~3_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\D[4]~85_combout ), - .cin(gnd), - .combout(\D[4]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~86 .lut_mask = 16'h8A00; -defparam \D[4]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N24 -cycloneive_lcell_comb \D[4]~89 ( -// Equation(s): -// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) - - .dataa(\D[4]~88_combout ), - .datab(\D[4]~87_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[4]~86_combout ), - .cin(gnd), - .combout(\D[4]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~89 .lut_mask = 16'hF8F0; -defparam \D[4]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N18 -cycloneive_lcell_comb \D[4]~93 ( -// Equation(s): -// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .cin(gnd), - .combout(\D[4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~93 .lut_mask = 16'hF838; -defparam \D[4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N4 -cycloneive_lcell_comb \D[4]~94 ( -// Equation(s): -// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\D[4]~93_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .cin(gnd), - .combout(\D[4]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~94 .lut_mask = 16'hCEC2; -defparam \D[4]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X22_Y21_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51267,16 +48864,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51330,83 +48927,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N8 -cycloneive_lcell_comb \D[4]~90 ( -// Equation(s): -// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .cin(gnd), - .combout(\D[4]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~90 .lut_mask = 16'hE6A2; -defparam \D[4]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 +// Location: M9K_X33_Y22_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -51416,16 +48937,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51464,104 +48985,2926 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N22 -cycloneive_lcell_comb \D[4]~91 ( +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \Selector6~0 ( // Equation(s): -// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ) # (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & ((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hCCE2; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector6~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hF388; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[4]~90_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), .cin(gnd), - .combout(\D[4]~91_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), .cout()); // synopsys translate_off -defparam \D[4]~91 .lut_mask = 16'h4B48; -defparam \D[4]~91 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N28 -cycloneive_lcell_comb \D[4]~92 ( +// Location: LCCOMB_X19_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( // Equation(s): -// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [0]))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[4]~90_combout ), - .datad(\D[4]~91_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~92_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~92 .lut_mask = 16'hC3E0; -defparam \D[4]~92 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N8 -cycloneive_lcell_comb \D[4]~125 ( +// Location: LCCOMB_X20_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~114 ( // Equation(s): -// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (((\D[4]~94_combout )))) +// \ula_|zx_keyboard_|keys[6][4]~114_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\D[4]~94_combout ), - .datad(\D[4]~92_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\D[4]~125_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~114_combout ), .cout()); // synopsys translate_off -defparam \D[4]~125 .lut_mask = 16'hF2D0; -defparam \D[4]~125 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N30 -cycloneive_lcell_comb \D[4]~110 ( +// Location: LCCOMB_X20_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~115 ( // Equation(s): -// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) +// \ula_|zx_keyboard_|keys[6][4]~115_combout = (\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~115 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~113_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~1_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~113 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N5 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~16_combout = (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][4]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~16 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[0]~21 ( +// Equation(s): +// \debounce_autofire|r_Count[0]~21_combout = \debounce_autofire|r_Count [0] $ (VCC) +// \debounce_autofire|r_Count[0]~22 = CARRY(\debounce_autofire|r_Count [0]) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_autofire|r_Count[0]~21_combout ), + .cout(\debounce_autofire|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_autofire|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[1]~23 ( +// Equation(s): +// \debounce_autofire|r_Count[1]~23_combout = (\debounce_autofire|r_Count [1] & (!\debounce_autofire|r_Count[0]~22 )) # (!\debounce_autofire|r_Count [1] & ((\debounce_autofire|r_Count[0]~22 ) # (GND))) +// \debounce_autofire|r_Count[1]~24 = CARRY((!\debounce_autofire|r_Count[0]~22 ) # (!\debounce_autofire|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[0]~22 ), + .combout(\debounce_autofire|r_Count[1]~23_combout ), + .cout(\debounce_autofire|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \debounce_autofire|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[2]~25 ( +// Equation(s): +// \debounce_autofire|r_Count[2]~25_combout = (\debounce_autofire|r_Count [2] & (\debounce_autofire|r_Count[1]~24 $ (GND))) # (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count[1]~24 & VCC)) +// \debounce_autofire|r_Count[2]~26 = CARRY((\debounce_autofire|r_Count [2] & !\debounce_autofire|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[1]~24 ), + .combout(\debounce_autofire|r_Count[2]~25_combout ), + .cout(\debounce_autofire|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \debounce_autofire|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[3]~27 ( +// Equation(s): +// \debounce_autofire|r_Count[3]~27_combout = (\debounce_autofire|r_Count [3] & (!\debounce_autofire|r_Count[2]~26 )) # (!\debounce_autofire|r_Count [3] & ((\debounce_autofire|r_Count[2]~26 ) # (GND))) +// \debounce_autofire|r_Count[3]~28 = CARRY((!\debounce_autofire|r_Count[2]~26 ) # (!\debounce_autofire|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[2]~26 ), + .combout(\debounce_autofire|r_Count[3]~27_combout ), + .cout(\debounce_autofire|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \debounce_autofire|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[4]~29 ( +// Equation(s): +// \debounce_autofire|r_Count[4]~29_combout = (\debounce_autofire|r_Count [4] & (\debounce_autofire|r_Count[3]~28 $ (GND))) # (!\debounce_autofire|r_Count [4] & (!\debounce_autofire|r_Count[3]~28 & VCC)) +// \debounce_autofire|r_Count[4]~30 = CARRY((\debounce_autofire|r_Count [4] & !\debounce_autofire|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[3]~28 ), + .combout(\debounce_autofire|r_Count[4]~29_combout ), + .cout(\debounce_autofire|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \debounce_autofire|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \debounce_autofire|r_Count[5]~31 ( +// Equation(s): +// \debounce_autofire|r_Count[5]~31_combout = (\debounce_autofire|r_Count [5] & (!\debounce_autofire|r_Count[4]~30 )) # (!\debounce_autofire|r_Count [5] & ((\debounce_autofire|r_Count[4]~30 ) # (GND))) +// \debounce_autofire|r_Count[5]~32 = CARRY((!\debounce_autofire|r_Count[4]~30 ) # (!\debounce_autofire|r_Count [5])) + + .dataa(\debounce_autofire|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[4]~30 ), + .combout(\debounce_autofire|r_Count[5]~31_combout ), + .cout(\debounce_autofire|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \debounce_autofire|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \debounce_autofire|r_Count[6]~33 ( +// Equation(s): +// \debounce_autofire|r_Count[6]~33_combout = (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count[5]~32 $ (GND))) # (!\debounce_autofire|r_Count [6] & (!\debounce_autofire|r_Count[5]~32 & VCC)) +// \debounce_autofire|r_Count[6]~34 = CARRY((\debounce_autofire|r_Count [6] & !\debounce_autofire|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[5]~32 ), + .combout(\debounce_autofire|r_Count[6]~33_combout ), + .cout(\debounce_autofire|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \debounce_autofire|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \debounce_autofire|r_Count[7]~35 ( +// Equation(s): +// \debounce_autofire|r_Count[7]~35_combout = (\debounce_autofire|r_Count [7] & (!\debounce_autofire|r_Count[6]~34 )) # (!\debounce_autofire|r_Count [7] & ((\debounce_autofire|r_Count[6]~34 ) # (GND))) +// \debounce_autofire|r_Count[7]~36 = CARRY((!\debounce_autofire|r_Count[6]~34 ) # (!\debounce_autofire|r_Count [7])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[6]~34 ), + .combout(\debounce_autofire|r_Count[7]~35_combout ), + .cout(\debounce_autofire|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N27 +dffeas \debounce_autofire|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \debounce_autofire|r_Count[8]~37 ( +// Equation(s): +// \debounce_autofire|r_Count[8]~37_combout = (\debounce_autofire|r_Count [8] & (\debounce_autofire|r_Count[7]~36 $ (GND))) # (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_Count[7]~36 & VCC)) +// \debounce_autofire|r_Count[8]~38 = CARRY((\debounce_autofire|r_Count [8] & !\debounce_autofire|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[7]~36 ), + .combout(\debounce_autofire|r_Count[8]~37_combout ), + .cout(\debounce_autofire|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N29 +dffeas \debounce_autofire|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \debounce_autofire|r_Count[9]~39 ( +// Equation(s): +// \debounce_autofire|r_Count[9]~39_combout = (\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count[8]~38 )) # (!\debounce_autofire|r_Count [9] & ((\debounce_autofire|r_Count[8]~38 ) # (GND))) +// \debounce_autofire|r_Count[9]~40 = CARRY((!\debounce_autofire|r_Count[8]~38 ) # (!\debounce_autofire|r_Count [9])) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[8]~38 ), + .combout(\debounce_autofire|r_Count[9]~39_combout ), + .cout(\debounce_autofire|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \debounce_autofire|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_Count[10]~41 ( +// Equation(s): +// \debounce_autofire|r_Count[10]~41_combout = (\debounce_autofire|r_Count [10] & (\debounce_autofire|r_Count[9]~40 $ (GND))) # (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count[9]~40 & VCC)) +// \debounce_autofire|r_Count[10]~42 = CARRY((\debounce_autofire|r_Count [10] & !\debounce_autofire|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[9]~40 ), + .combout(\debounce_autofire|r_Count[10]~41_combout ), + .cout(\debounce_autofire|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \debounce_autofire|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \debounce_autofire|r_Count[11]~43 ( +// Equation(s): +// \debounce_autofire|r_Count[11]~43_combout = (\debounce_autofire|r_Count [11] & (!\debounce_autofire|r_Count[10]~42 )) # (!\debounce_autofire|r_Count [11] & ((\debounce_autofire|r_Count[10]~42 ) # (GND))) +// \debounce_autofire|r_Count[11]~44 = CARRY((!\debounce_autofire|r_Count[10]~42 ) # (!\debounce_autofire|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[10]~42 ), + .combout(\debounce_autofire|r_Count[11]~43_combout ), + .cout(\debounce_autofire|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \debounce_autofire|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \debounce_autofire|r_Count[12]~45 ( +// Equation(s): +// \debounce_autofire|r_Count[12]~45_combout = (\debounce_autofire|r_Count [12] & (\debounce_autofire|r_Count[11]~44 $ (GND))) # (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count[11]~44 & VCC)) +// \debounce_autofire|r_Count[12]~46 = CARRY((\debounce_autofire|r_Count [12] & !\debounce_autofire|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[11]~44 ), + .combout(\debounce_autofire|r_Count[12]~45_combout ), + .cout(\debounce_autofire|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \debounce_autofire|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \debounce_autofire|r_Count[13]~47 ( +// Equation(s): +// \debounce_autofire|r_Count[13]~47_combout = (\debounce_autofire|r_Count [13] & (!\debounce_autofire|r_Count[12]~46 )) # (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|r_Count[12]~46 ) # (GND))) +// \debounce_autofire|r_Count[13]~48 = CARRY((!\debounce_autofire|r_Count[12]~46 ) # (!\debounce_autofire|r_Count [13])) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[12]~46 ), + .combout(\debounce_autofire|r_Count[13]~47_combout ), + .cout(\debounce_autofire|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \debounce_autofire|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \debounce_autofire|r_Count[14]~49 ( +// Equation(s): +// \debounce_autofire|r_Count[14]~49_combout = (\debounce_autofire|r_Count [14] & (\debounce_autofire|r_Count[13]~48 $ (GND))) # (!\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count[13]~48 & VCC)) +// \debounce_autofire|r_Count[14]~50 = CARRY((\debounce_autofire|r_Count [14] & !\debounce_autofire|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[13]~48 ), + .combout(\debounce_autofire|r_Count[14]~49_combout ), + .cout(\debounce_autofire|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \debounce_autofire|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \debounce_autofire|r_Count[15]~51 ( +// Equation(s): +// \debounce_autofire|r_Count[15]~51_combout = (\debounce_autofire|r_Count [15] & (!\debounce_autofire|r_Count[14]~50 )) # (!\debounce_autofire|r_Count [15] & ((\debounce_autofire|r_Count[14]~50 ) # (GND))) +// \debounce_autofire|r_Count[15]~52 = CARRY((!\debounce_autofire|r_Count[14]~50 ) # (!\debounce_autofire|r_Count [15])) + + .dataa(\debounce_autofire|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[14]~50 ), + .combout(\debounce_autofire|r_Count[15]~51_combout ), + .cout(\debounce_autofire|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \debounce_autofire|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[16]~53 ( +// Equation(s): +// \debounce_autofire|r_Count[16]~53_combout = (\debounce_autofire|r_Count [16] & (\debounce_autofire|r_Count[15]~52 $ (GND))) # (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count[15]~52 & VCC)) +// \debounce_autofire|r_Count[16]~54 = CARRY((\debounce_autofire|r_Count [16] & !\debounce_autofire|r_Count[15]~52 )) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[15]~52 ), + .combout(\debounce_autofire|r_Count[16]~53_combout ), + .cout(\debounce_autofire|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_autofire|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \debounce_autofire|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[17]~55 ( +// Equation(s): +// \debounce_autofire|r_Count[17]~55_combout = (\debounce_autofire|r_Count [17] & (!\debounce_autofire|r_Count[16]~54 )) # (!\debounce_autofire|r_Count [17] & ((\debounce_autofire|r_Count[16]~54 ) # (GND))) +// \debounce_autofire|r_Count[17]~56 = CARRY((!\debounce_autofire|r_Count[16]~54 ) # (!\debounce_autofire|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[16]~54 ), + .combout(\debounce_autofire|r_Count[17]~55_combout ), + .cout(\debounce_autofire|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \debounce_autofire|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[18]~57 ( +// Equation(s): +// \debounce_autofire|r_Count[18]~57_combout = (\debounce_autofire|r_Count [18] & (\debounce_autofire|r_Count[17]~56 $ (GND))) # (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count[17]~56 & VCC)) +// \debounce_autofire|r_Count[18]~58 = CARRY((\debounce_autofire|r_Count [18] & !\debounce_autofire|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[17]~56 ), + .combout(\debounce_autofire|r_Count[18]~57_combout ), + .cout(\debounce_autofire|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \debounce_autofire|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[19]~59 ( +// Equation(s): +// \debounce_autofire|r_Count[19]~59_combout = (\debounce_autofire|r_Count [19] & (!\debounce_autofire|r_Count[18]~58 )) # (!\debounce_autofire|r_Count [19] & ((\debounce_autofire|r_Count[18]~58 ) # (GND))) +// \debounce_autofire|r_Count[19]~60 = CARRY((!\debounce_autofire|r_Count[18]~58 ) # (!\debounce_autofire|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[18]~58 ), + .combout(\debounce_autofire|r_Count[19]~59_combout ), + .cout(\debounce_autofire|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \debounce_autofire|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[20]~61 ( +// Equation(s): +// \debounce_autofire|r_Count[20]~61_combout = \debounce_autofire|r_Count[19]~60 $ (!\debounce_autofire|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_autofire|r_Count [20]), + .cin(\debounce_autofire|r_Count[19]~60 ), + .combout(\debounce_autofire|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_autofire|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \debounce_autofire|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y15_N8 +cycloneive_io_ibuf \kempston_autofire_button~input ( + .i(kempston_autofire_button), + .ibar(gnd), + .o(\kempston_autofire_button~input_o )); +// synopsys translate_off +defparam \kempston_autofire_button~input .bus_hold = "false"; +defparam \kempston_autofire_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~7 ( +// Equation(s): +// \debounce_autofire|r_State~7_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [6])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [6]), + .cin(gnd), + .combout(\debounce_autofire|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~7 .lut_mask = 16'hA000; +defparam \debounce_autofire|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \debounce_autofire|LessThan0~0 ( +// Equation(s): +// \debounce_autofire|LessThan0~0_combout = (!\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_State~7_combout & !\debounce_autofire|r_Count [10]))) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(\debounce_autofire|r_Count [8]), + .datac(\debounce_autofire|r_State~7_combout ), + .datad(\debounce_autofire|r_Count [10]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \debounce_autofire|LessThan0~1 ( +// Equation(s): +// \debounce_autofire|LessThan0~1_combout = (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|LessThan0~0_combout ) # (!\debounce_autofire|r_Count [11])))) + + .dataa(\debounce_autofire|LessThan0~0_combout ), + .datab(\debounce_autofire|r_Count [11]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [13]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~1 .lut_mask = 16'h000B; +defparam \debounce_autofire|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \debounce_autofire|always0~0 ( +// Equation(s): +// \debounce_autofire|always0~0_combout = (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count [17] & !\debounce_autofire|r_Count [19]))) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(\debounce_autofire|r_Count [18]), + .datac(\debounce_autofire|r_Count [17]), + .datad(\debounce_autofire|r_Count [19]), + .cin(gnd), + .combout(\debounce_autofire|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \debounce_autofire|always0~1 ( +// Equation(s): +// \debounce_autofire|always0~1_combout = (\debounce_autofire|always0~0_combout & ((\debounce_autofire|LessThan0~1_combout ) # ((!\debounce_autofire|r_Count [15]) # (!\debounce_autofire|r_Count [14])))) + + .dataa(\debounce_autofire|LessThan0~1_combout ), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|always0~0_combout ), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_autofire|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \debounce_autofire|always0~2 ( +// Equation(s): +// \debounce_autofire|always0~2_combout = (\debounce_autofire|r_Count [20] & ((\debounce_autofire|r_State~q $ (!\kempston_autofire_button~input_o )) # (!\debounce_autofire|always0~1_combout ))) # (!\debounce_autofire|r_Count [20] & +// (\debounce_autofire|r_State~q $ ((!\kempston_autofire_button~input_o )))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_State~q ), + .datac(\kempston_autofire_button~input_o ), + .datad(\debounce_autofire|always0~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~2 .lut_mask = 16'hC3EB; +defparam \debounce_autofire|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \debounce_autofire|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \debounce_autofire|r_State~4 ( +// Equation(s): +// \debounce_autofire|r_State~4_combout = (!\debounce_autofire|r_Count [0] & (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count [1] & !\debounce_autofire|r_Count [3]))) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(\debounce_autofire|r_Count [2]), + .datac(\debounce_autofire|r_Count [1]), + .datad(\debounce_autofire|r_Count [3]), + .cin(gnd), + .combout(\debounce_autofire|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_autofire|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \debounce_autofire|r_State~5 ( +// Equation(s): +// \debounce_autofire|r_State~5_combout = (\debounce_autofire|r_State~4_combout & !\debounce_autofire|r_Count [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\debounce_autofire|r_State~4_combout ), + .datad(\debounce_autofire|r_Count [4]), + .cin(gnd), + .combout(\debounce_autofire|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~5 .lut_mask = 16'h00F0; +defparam \debounce_autofire|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \debounce_autofire|r_State~2 ( +// Equation(s): +// \debounce_autofire|r_State~2_combout = (\debounce_autofire|r_Count [20] & (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count [9] & !\debounce_autofire|r_Count [8]))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_Count [10]), + .datac(\debounce_autofire|r_Count [9]), + .datad(\debounce_autofire|r_Count [8]), + .cin(gnd), + .combout(\debounce_autofire|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_autofire|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \debounce_autofire|r_State~0 ( +// Equation(s): +// \debounce_autofire|r_State~0_combout = (!\debounce_autofire|r_Count [13] & (\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count [12] & \debounce_autofire|r_Count [15]))) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_autofire|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \debounce_autofire|r_State~1 ( +// Equation(s): +// \debounce_autofire|r_State~1_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [11]))) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(\debounce_autofire|r_Count [6]), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [11]), + .cin(gnd), + .combout(\debounce_autofire|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~3 ( +// Equation(s): +// \debounce_autofire|r_State~3_combout = (\debounce_autofire|always0~0_combout & (\debounce_autofire|r_State~2_combout & (\debounce_autofire|r_State~0_combout & \debounce_autofire|r_State~1_combout ))) + + .dataa(\debounce_autofire|always0~0_combout ), + .datab(\debounce_autofire|r_State~2_combout ), + .datac(\debounce_autofire|r_State~0_combout ), + .datad(\debounce_autofire|r_State~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_State~6 ( +// Equation(s): +// \debounce_autofire|r_State~6_combout = (\debounce_autofire|r_State~5_combout & ((\debounce_autofire|r_State~3_combout & (\kempston_autofire_button~input_o )) # (!\debounce_autofire|r_State~3_combout & ((\debounce_autofire|r_State~q ))))) # +// (!\debounce_autofire|r_State~5_combout & (((\debounce_autofire|r_State~q )))) + + .dataa(\debounce_autofire|r_State~5_combout ), + .datab(\kempston_autofire_button~input_o ), + .datac(\debounce_autofire|r_State~q ), + .datad(\debounce_autofire|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~6 .lut_mask = 16'hD8F0; +defparam \debounce_autofire|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N19 +dffeas \debounce_autofire|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_autofire|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_State .is_wysiwyg = "true"; +defparam \debounce_autofire|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N30 +cycloneive_lcell_comb \kempston_autofire_enabled~0 ( +// Equation(s): +// \kempston_autofire_enabled~0_combout = !\kempston_autofire_enabled~q + + .dataa(gnd), + .datab(gnd), + .datac(\kempston_autofire_enabled~q ), + .datad(gnd), + .cin(gnd), + .combout(\kempston_autofire_enabled~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_autofire_enabled~0 .lut_mask = 16'h0F0F; +defparam \kempston_autofire_enabled~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N31 +dffeas kempston_autofire_enabled( + .clk(!\debounce_autofire|r_State~q ), + .d(\kempston_autofire_enabled~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_autofire_enabled~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_autofire_enabled.is_wysiwyg = "true"; +defparam kempston_autofire_enabled.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[0]~51 ( +// Equation(s): +// \kempston_auto_fire_counter[0]~51_combout = \kempston_autofire_enabled~q $ (kempston_auto_fire_counter[0]) + + .dataa(\kempston_autofire_enabled~q ), + .datab(gnd), + .datac(kempston_auto_fire_counter[0]), + .datad(gnd), + .cin(gnd), + .combout(\kempston_auto_fire_counter[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0]~51 .lut_mask = 16'h5A5A; +defparam \kempston_auto_fire_counter[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N13 +dffeas \kempston_auto_fire_counter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[0]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[0]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[1]~17 ( +// Equation(s): +// \kempston_auto_fire_counter[1]~17_combout = (kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] $ (VCC))) # (!kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] & VCC)) +// \kempston_auto_fire_counter[1]~18 = CARRY((kempston_auto_fire_counter[0] & kempston_auto_fire_counter[1])) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\kempston_auto_fire_counter[1]~17_combout ), + .cout(\kempston_auto_fire_counter[1]~18 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1]~17 .lut_mask = 16'h6688; +defparam \kempston_auto_fire_counter[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N17 +dffeas \kempston_auto_fire_counter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[1]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[1]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N18 +cycloneive_lcell_comb \kempston_auto_fire_counter[2]~19 ( +// Equation(s): +// \kempston_auto_fire_counter[2]~19_combout = (kempston_auto_fire_counter[2] & (!\kempston_auto_fire_counter[1]~18 )) # (!kempston_auto_fire_counter[2] & ((\kempston_auto_fire_counter[1]~18 ) # (GND))) +// \kempston_auto_fire_counter[2]~20 = CARRY((!\kempston_auto_fire_counter[1]~18 ) # (!kempston_auto_fire_counter[2])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[1]~18 ), + .combout(\kempston_auto_fire_counter[2]~19_combout ), + .cout(\kempston_auto_fire_counter[2]~20 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2]~19 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[2]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N19 +dffeas \kempston_auto_fire_counter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[2]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \kempston_auto_fire_counter[3]~21 ( +// Equation(s): +// \kempston_auto_fire_counter[3]~21_combout = (kempston_auto_fire_counter[3] & (\kempston_auto_fire_counter[2]~20 $ (GND))) # (!kempston_auto_fire_counter[3] & (!\kempston_auto_fire_counter[2]~20 & VCC)) +// \kempston_auto_fire_counter[3]~22 = CARRY((kempston_auto_fire_counter[3] & !\kempston_auto_fire_counter[2]~20 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[2]~20 ), + .combout(\kempston_auto_fire_counter[3]~21_combout ), + .cout(\kempston_auto_fire_counter[3]~22 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3]~21 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[3]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N21 +dffeas \kempston_auto_fire_counter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[3]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N22 +cycloneive_lcell_comb \kempston_auto_fire_counter[4]~23 ( +// Equation(s): +// \kempston_auto_fire_counter[4]~23_combout = (kempston_auto_fire_counter[4] & (!\kempston_auto_fire_counter[3]~22 )) # (!kempston_auto_fire_counter[4] & ((\kempston_auto_fire_counter[3]~22 ) # (GND))) +// \kempston_auto_fire_counter[4]~24 = CARRY((!\kempston_auto_fire_counter[3]~22 ) # (!kempston_auto_fire_counter[4])) + + .dataa(kempston_auto_fire_counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[3]~22 ), + .combout(\kempston_auto_fire_counter[4]~23_combout ), + .cout(\kempston_auto_fire_counter[4]~24 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4]~23 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[4]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N23 +dffeas \kempston_auto_fire_counter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[4]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N24 +cycloneive_lcell_comb \kempston_auto_fire_counter[5]~25 ( +// Equation(s): +// \kempston_auto_fire_counter[5]~25_combout = (kempston_auto_fire_counter[5] & (\kempston_auto_fire_counter[4]~24 $ (GND))) # (!kempston_auto_fire_counter[5] & (!\kempston_auto_fire_counter[4]~24 & VCC)) +// \kempston_auto_fire_counter[5]~26 = CARRY((kempston_auto_fire_counter[5] & !\kempston_auto_fire_counter[4]~24 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[4]~24 ), + .combout(\kempston_auto_fire_counter[5]~25_combout ), + .cout(\kempston_auto_fire_counter[5]~26 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5]~25 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[5]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N25 +dffeas \kempston_auto_fire_counter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[5]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N26 +cycloneive_lcell_comb \kempston_auto_fire_counter[6]~27 ( +// Equation(s): +// \kempston_auto_fire_counter[6]~27_combout = (kempston_auto_fire_counter[6] & (!\kempston_auto_fire_counter[5]~26 )) # (!kempston_auto_fire_counter[6] & ((\kempston_auto_fire_counter[5]~26 ) # (GND))) +// \kempston_auto_fire_counter[6]~28 = CARRY((!\kempston_auto_fire_counter[5]~26 ) # (!kempston_auto_fire_counter[6])) + + .dataa(kempston_auto_fire_counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[5]~26 ), + .combout(\kempston_auto_fire_counter[6]~27_combout ), + .cout(\kempston_auto_fire_counter[6]~28 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6]~27 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[6]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N27 +dffeas \kempston_auto_fire_counter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[6]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N28 +cycloneive_lcell_comb \kempston_auto_fire_counter[7]~29 ( +// Equation(s): +// \kempston_auto_fire_counter[7]~29_combout = (kempston_auto_fire_counter[7] & (\kempston_auto_fire_counter[6]~28 $ (GND))) # (!kempston_auto_fire_counter[7] & (!\kempston_auto_fire_counter[6]~28 & VCC)) +// \kempston_auto_fire_counter[7]~30 = CARRY((kempston_auto_fire_counter[7] & !\kempston_auto_fire_counter[6]~28 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[6]~28 ), + .combout(\kempston_auto_fire_counter[7]~29_combout ), + .cout(\kempston_auto_fire_counter[7]~30 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7]~29 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[7]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N29 +dffeas \kempston_auto_fire_counter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[7]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \kempston_auto_fire_counter[8]~31 ( +// Equation(s): +// \kempston_auto_fire_counter[8]~31_combout = (kempston_auto_fire_counter[8] & (!\kempston_auto_fire_counter[7]~30 )) # (!kempston_auto_fire_counter[8] & ((\kempston_auto_fire_counter[7]~30 ) # (GND))) +// \kempston_auto_fire_counter[8]~32 = CARRY((!\kempston_auto_fire_counter[7]~30 ) # (!kempston_auto_fire_counter[8])) + + .dataa(kempston_auto_fire_counter[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[7]~30 ), + .combout(\kempston_auto_fire_counter[8]~31_combout ), + .cout(\kempston_auto_fire_counter[8]~32 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8]~31 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[8]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N31 +dffeas \kempston_auto_fire_counter[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[8]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \kempston_auto_fire_counter[9]~33 ( +// Equation(s): +// \kempston_auto_fire_counter[9]~33_combout = (kempston_auto_fire_counter[9] & (\kempston_auto_fire_counter[8]~32 $ (GND))) # (!kempston_auto_fire_counter[9] & (!\kempston_auto_fire_counter[8]~32 & VCC)) +// \kempston_auto_fire_counter[9]~34 = CARRY((kempston_auto_fire_counter[9] & !\kempston_auto_fire_counter[8]~32 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[9]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[8]~32 ), + .combout(\kempston_auto_fire_counter[9]~33_combout ), + .cout(\kempston_auto_fire_counter[9]~34 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9]~33 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[9]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N1 +dffeas \kempston_auto_fire_counter[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[9]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \kempston_auto_fire_counter[10]~35 ( +// Equation(s): +// \kempston_auto_fire_counter[10]~35_combout = (kempston_auto_fire_counter[10] & (!\kempston_auto_fire_counter[9]~34 )) # (!kempston_auto_fire_counter[10] & ((\kempston_auto_fire_counter[9]~34 ) # (GND))) +// \kempston_auto_fire_counter[10]~36 = CARRY((!\kempston_auto_fire_counter[9]~34 ) # (!kempston_auto_fire_counter[10])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[9]~34 ), + .combout(\kempston_auto_fire_counter[10]~35_combout ), + .cout(\kempston_auto_fire_counter[10]~36 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10]~35 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[10]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N3 +dffeas \kempston_auto_fire_counter[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[10]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N4 +cycloneive_lcell_comb \kempston_auto_fire_counter[11]~37 ( +// Equation(s): +// \kempston_auto_fire_counter[11]~37_combout = (kempston_auto_fire_counter[11] & (\kempston_auto_fire_counter[10]~36 $ (GND))) # (!kempston_auto_fire_counter[11] & (!\kempston_auto_fire_counter[10]~36 & VCC)) +// \kempston_auto_fire_counter[11]~38 = CARRY((kempston_auto_fire_counter[11] & !\kempston_auto_fire_counter[10]~36 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[10]~36 ), + .combout(\kempston_auto_fire_counter[11]~37_combout ), + .cout(\kempston_auto_fire_counter[11]~38 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11]~37 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[11]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N5 +dffeas \kempston_auto_fire_counter[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[11]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \kempston_auto_fire_counter[12]~39 ( +// Equation(s): +// \kempston_auto_fire_counter[12]~39_combout = (kempston_auto_fire_counter[12] & (!\kempston_auto_fire_counter[11]~38 )) # (!kempston_auto_fire_counter[12] & ((\kempston_auto_fire_counter[11]~38 ) # (GND))) +// \kempston_auto_fire_counter[12]~40 = CARRY((!\kempston_auto_fire_counter[11]~38 ) # (!kempston_auto_fire_counter[12])) + + .dataa(kempston_auto_fire_counter[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[11]~38 ), + .combout(\kempston_auto_fire_counter[12]~39_combout ), + .cout(\kempston_auto_fire_counter[12]~40 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12]~39 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[12]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N7 +dffeas \kempston_auto_fire_counter[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[12]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N8 +cycloneive_lcell_comb \kempston_auto_fire_counter[13]~41 ( +// Equation(s): +// \kempston_auto_fire_counter[13]~41_combout = (kempston_auto_fire_counter[13] & (\kempston_auto_fire_counter[12]~40 $ (GND))) # (!kempston_auto_fire_counter[13] & (!\kempston_auto_fire_counter[12]~40 & VCC)) +// \kempston_auto_fire_counter[13]~42 = CARRY((kempston_auto_fire_counter[13] & !\kempston_auto_fire_counter[12]~40 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[12]~40 ), + .combout(\kempston_auto_fire_counter[13]~41_combout ), + .cout(\kempston_auto_fire_counter[13]~42 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13]~41 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[13]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N9 +dffeas \kempston_auto_fire_counter[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[13]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N10 +cycloneive_lcell_comb \kempston_auto_fire_counter[14]~43 ( +// Equation(s): +// \kempston_auto_fire_counter[14]~43_combout = (kempston_auto_fire_counter[14] & (!\kempston_auto_fire_counter[13]~42 )) # (!kempston_auto_fire_counter[14] & ((\kempston_auto_fire_counter[13]~42 ) # (GND))) +// \kempston_auto_fire_counter[14]~44 = CARRY((!\kempston_auto_fire_counter[13]~42 ) # (!kempston_auto_fire_counter[14])) + + .dataa(kempston_auto_fire_counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[13]~42 ), + .combout(\kempston_auto_fire_counter[14]~43_combout ), + .cout(\kempston_auto_fire_counter[14]~44 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14]~43 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[14]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N11 +dffeas \kempston_auto_fire_counter[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[14]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[15]~45 ( +// Equation(s): +// \kempston_auto_fire_counter[15]~45_combout = (kempston_auto_fire_counter[15] & (\kempston_auto_fire_counter[14]~44 $ (GND))) # (!kempston_auto_fire_counter[15] & (!\kempston_auto_fire_counter[14]~44 & VCC)) +// \kempston_auto_fire_counter[15]~46 = CARRY((kempston_auto_fire_counter[15] & !\kempston_auto_fire_counter[14]~44 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[14]~44 ), + .combout(\kempston_auto_fire_counter[15]~45_combout ), + .cout(\kempston_auto_fire_counter[15]~46 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15]~45 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[15]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \kempston_auto_fire_counter[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[15]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \Equal2~3 ( +// Equation(s): +// \Equal2~3_combout = (!kempston_auto_fire_counter[14] & (!kempston_auto_fire_counter[15] & (!kempston_auto_fire_counter[13] & !kempston_auto_fire_counter[12]))) + + .dataa(kempston_auto_fire_counter[14]), + .datab(kempston_auto_fire_counter[15]), + .datac(kempston_auto_fire_counter[13]), + .datad(kempston_auto_fire_counter[12]), + .cin(gnd), + .combout(\Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~3 .lut_mask = 16'h0001; +defparam \Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \Equal2~2 ( +// Equation(s): +// \Equal2~2_combout = (!kempston_auto_fire_counter[8] & (!kempston_auto_fire_counter[9] & (!kempston_auto_fire_counter[11] & !kempston_auto_fire_counter[10]))) + + .dataa(kempston_auto_fire_counter[8]), + .datab(kempston_auto_fire_counter[9]), + .datac(kempston_auto_fire_counter[11]), + .datad(kempston_auto_fire_counter[10]), + .cin(gnd), + .combout(\Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~2 .lut_mask = 16'h0001; +defparam \Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N10 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!kempston_auto_fire_counter[0] & (!kempston_auto_fire_counter[1] & (!kempston_auto_fire_counter[3] & !kempston_auto_fire_counter[2]))) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(kempston_auto_fire_counter[3]), + .datad(kempston_auto_fire_counter[2]), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N0 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!kempston_auto_fire_counter[4] & (!kempston_auto_fire_counter[5] & (!kempston_auto_fire_counter[6] & !kempston_auto_fire_counter[7]))) + + .dataa(kempston_auto_fire_counter[4]), + .datab(kempston_auto_fire_counter[5]), + .datac(kempston_auto_fire_counter[6]), + .datad(kempston_auto_fire_counter[7]), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0001; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \Equal2~4 ( +// Equation(s): +// \Equal2~4_combout = (\Equal2~3_combout & (\Equal2~2_combout & (\Equal2~0_combout & \Equal2~1_combout ))) + + .dataa(\Equal2~3_combout ), + .datab(\Equal2~2_combout ), + .datac(\Equal2~0_combout ), .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[4]~110_combout ), + .combout(\Equal2~4_combout ), .cout()); // synopsys translate_off -defparam \D[4]~110 .lut_mask = 16'hB8FF; -defparam \D[4]~110 .sum_lutc_input = "datac"; +defparam \Equal2~4 .lut_mask = 16'h8000; +defparam \Equal2~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N4 -cycloneive_lcell_comb \D[4]~111 ( +// Location: LCCOMB_X18_Y12_N14 +cycloneive_lcell_comb \kempston_auto_fire_counter[16]~47 ( // Equation(s): -// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) +// \kempston_auto_fire_counter[16]~47_combout = (kempston_auto_fire_counter[16] & (!\kempston_auto_fire_counter[15]~46 )) # (!kempston_auto_fire_counter[16] & ((\kempston_auto_fire_counter[15]~46 ) # (GND))) +// \kempston_auto_fire_counter[16]~48 = CARRY((!\kempston_auto_fire_counter[15]~46 ) # (!kempston_auto_fire_counter[16])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[15]~46 ), + .combout(\kempston_auto_fire_counter[16]~47_combout ), + .cout(\kempston_auto_fire_counter[16]~48 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16]~47 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[16]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N15 +dffeas \kempston_auto_fire_counter[16] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[16]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[17]~49 ( +// Equation(s): +// \kempston_auto_fire_counter[17]~49_combout = \kempston_auto_fire_counter[16]~48 $ (!kempston_auto_fire_counter[17]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(kempston_auto_fire_counter[17]), + .cin(\kempston_auto_fire_counter[16]~48 ), + .combout(\kempston_auto_fire_counter[17]~49_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17]~49 .lut_mask = 16'hF00F; +defparam \kempston_auto_fire_counter[17]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N17 +dffeas \kempston_auto_fire_counter[17] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[17]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N26 +cycloneive_lcell_comb \kempston_auto_fire~0 ( +// Equation(s): +// \kempston_auto_fire~0_combout = \kempston_auto_fire~q $ (((\Equal2~4_combout & (!kempston_auto_fire_counter[16] & !kempston_auto_fire_counter[17])))) + + .dataa(\Equal2~4_combout ), + .datab(kempston_auto_fire_counter[16]), + .datac(\kempston_auto_fire~q ), + .datad(kempston_auto_fire_counter[17]), + .cin(gnd), + .combout(\kempston_auto_fire~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire~0 .lut_mask = 16'hF0D2; +defparam \kempston_auto_fire~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N27 +dffeas kempston_auto_fire( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\kempston_autofire_enabled~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_auto_fire~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_auto_fire.is_wysiwyg = "true"; +defparam kempston_auto_fire.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \Selector6~2 ( +// Equation(s): +// \Selector6~2_combout = (\Selector14~18_combout & (((\kempston_auto_fire~q & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row[4]~16_combout ) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .datab(\Selector14~18_combout ), + .datac(\kempston_auto_fire~q ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~2 .lut_mask = 16'hE233; +defparam \Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~116 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~117_combout = (\ula_|zx_keyboard_|keys[5][4]~116_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[5][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~116_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~117 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [6])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~118 .lut_mask = 16'h4242; +defparam \ula_|zx_keyboard_|keys[4][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~119_combout = (\ula_|zx_keyboard_|keys[4][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~119 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~120_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~119_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~119_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~120 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~17_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~17 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~121 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~133_combout = (\ula_|zx_keyboard_|keys[3][4]~121_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~133 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[3][4]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~122_combout = (\ula_|zx_keyboard_|keys[3][4]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & +// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~133_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .datab(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~122 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N1 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hBBAA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~124_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~123_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~124 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~125_combout = (\ula_|zx_keyboard_|keys[2][4]~124_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~124_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~125 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \Selector6~3 ( +// Equation(s): +// \Selector6~3_combout = (\ula_|zx_keyboard_|keys[3][4]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~3 .lut_mask = 16'hDD0D; +defparam \Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~126_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~126 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~127_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N19 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y23_N8 +cycloneive_lcell_comb \Selector6~4 ( +// Equation(s): +// \Selector6~4_combout = (\ula_|zx_keyboard_|keys[1][4]~q & (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[1][4]~q & +// (((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~4 .lut_mask = 16'hDD0D; +defparam \Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \Selector6~5 ( +// Equation(s): +// \Selector6~5_combout = ((\ula_|zx_keyboard_|key_row[4]~17_combout & (\Selector6~3_combout & \Selector6~4_combout ))) # (!\Selector14~17_combout ) + + .dataa(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .datab(\Selector14~17_combout ), + .datac(\Selector6~3_combout ), + .datad(\Selector6~4_combout ), + .cin(gnd), + .combout(\Selector6~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~5 .lut_mask = 16'hB333; +defparam \Selector6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y34_N15 +cycloneive_io_ibuf \kempston[4]~input ( + .i(kempston[4]), + .ibar(gnd), + .o(\kempston[4]~input_o )); +// synopsys translate_off +defparam \kempston[4]~input .bus_hold = "false"; +defparam \kempston[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \Selector6~6 ( +// Equation(s): +// \Selector6~6_combout = (\Selector6~2_combout & ((\Selector14~18_combout & ((!\kempston[4]~input_o ))) # (!\Selector14~18_combout & (\Selector6~5_combout )))) + + .dataa(\Selector6~2_combout ), + .datab(\Selector6~5_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[4]~input_o ), + .cin(gnd), + .combout(\Selector6~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~6 .lut_mask = 16'h08A8; +defparam \Selector6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \Selector6~7 ( +// Equation(s): +// \Selector6~7_combout = (\Equal5~0_combout & (((\Selector6~6_combout )))) # (!\Equal5~0_combout & ((\Selector6~6_combout & (\Selector6~1_combout )) # (!\Selector6~6_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout +// ))))) + + .dataa(\Selector6~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector6~6_combout ), + .cin(gnd), + .combout(\Selector6~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~7 .lut_mask = 16'hEE30; +defparam \Selector6~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[4]~39 ( +// Equation(s): +// \D[4]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector6~7_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[4]~110_combout ), - .datad(\z80_|data_pins_|dout [4]), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), - .combout(\D[4]~111_combout ), + .combout(\D[4]~39_combout ), .cout()); // synopsys translate_off -defparam \D[4]~111 .lut_mask = 16'hF151; -defparam \D[4]~111 .sum_lutc_input = "datac"; +defparam \D[4]~39 .lut_mask = 16'hDD0D; +defparam \D[4]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N10 +// Location: LCCOMB_X26_Y16_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & -// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~39_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) # (!\D[4]~39_combout & +// (((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) - .dataa(\D[4]~111_combout ), + .dataa(\D[4]~39_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -51570,7 +51913,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N11 +// Location: FF_X26_Y16_N25 dffeas \z80_|data_pins_|dout[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), @@ -51589,145 +51932,3743 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N18 +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~17 ( +// Equation(s): +// \z80_|bus_control_|db[4]~17_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [4]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~17 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[4]~18_combout = ((\z80_|bus_control_|db[4]~17_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~17_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( // Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[4]~18_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N23 -dffeas \z80_|ir_|opcode[4] ( +// Location: FF_X27_Y12_N15 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[4]~19_combout ), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [4]), + .q(\z80_|interrupts_|im2~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|DFFE_inst44~q & \z80_|interrupts_|im2~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [1] = (\z80_|bus_control_|db[1]~10_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~3_combout = (\z80_|reg_file_|gdfx_temp0[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~3 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~20 ( +// Equation(s): +// \z80_|alu_control_|db[1]~20_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~20 .lut_mask = 16'h88CC; +defparam \z80_|alu_control_|db[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~21 ( +// Equation(s): +// \z80_|alu_control_|db[1]~21_combout = (\z80_|reg_file_|db_lo_ds[1]~3_combout & (\z80_|alu_control_|db[1]~20_combout & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|db[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~21 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~22 ( +// Equation(s): +// \z80_|alu_control_|db[1]~22_combout = ((\z80_|alu_control_|db[1]~21_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .datab(\z80_|alu_control_|db[1]~21_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~22 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~9 ( +// Equation(s): +// \z80_|bus_control_|db[1]~9_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|alu_control_|db[1]~22_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~9 .lut_mask = 16'hA0F0; +defparam \z80_|bus_control_|db[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[5][1]~33_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~2_combout = (\ula_|zx_keyboard_|keys[5][1]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~2 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][1]~q )))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N5 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~1_combout = (\z80_|address_pins_|abus[10]~19_combout & (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~q ))) # (!\z80_|address_pins_|abus[10]~19_combout & (!\ula_|zx_keyboard_|keys[2][1]~q +// & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~1 .lut_mask = 16'hA2F3; +defparam \ula_|zx_keyboard_|key_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~38 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg +// [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0210; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr16~2_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h8B88; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & ((\ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hE2C0; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~39_combout = (\ula_|zx_keyboard_|keys[7][1]~38_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|WideOr16~6_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) # +// (!\ula_|zx_keyboard_|keys[7][1]~38_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~39 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hFCCC; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~42_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~3_combout = (\z80_|address_pins_|abus[15]~23_combout & (((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][1]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~3 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & (!\ula_|zx_keyboard_|keys[0][1]~12_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][4]~18_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N25 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~0_combout = (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~16_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & +// ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~16_combout ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~0 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [1] = (\ula_|zx_keyboard_|key_row[1]~2_combout & (\ula_|zx_keyboard_|key_row[1]~1_combout & (\ula_|zx_keyboard_|key_row[1]~3_combout & \ula_|zx_keyboard_|key_row[1]~0_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .datab(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .datac(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .datad(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [1]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y34_N1 +cycloneive_io_ibuf \kempston[2]~input ( + .i(kempston[2]), + .ibar(gnd), + .o(\kempston[2]~input_o )); +// synopsys translate_off +defparam \kempston[2]~input .bus_hold = "false"; +defparam \kempston[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \Selector12~4 ( +// Equation(s): +// \Selector12~4_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[2]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [1])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [1]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[2]~input_o ), + .cin(gnd), + .combout(\Selector12~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~4 .lut_mask = 16'h0BCB; +defparam \Selector12~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \Selector12~10 ( +// Equation(s): +// \Selector12~10_combout = (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector12~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~10 .lut_mask = 16'hFFCF; +defparam \Selector12~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \Selector12~7 ( +// Equation(s): +// \Selector12~7_combout = (\Selector12~4_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\Selector12~4_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\Selector12~4_combout ), + .cin(gnd), + .combout(\Selector12~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~7 .lut_mask = 16'hEEF0; +defparam \Selector12~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \Selector12~8 ( +// Equation(s): +// \Selector12~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\Selector12~7_combout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\Selector12~7_combout ), + .cin(gnd), + .combout(\Selector12~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~8 .lut_mask = 16'hAFA0; +defparam \Selector12~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \Selector12~9 ( +// Equation(s): +// \Selector12~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\Selector12~8_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a +// [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector12~8_combout ), + .cin(gnd), + .combout(\Selector12~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~9 .lut_mask = 16'hFE0E; +defparam \Selector12~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \Selector12~15 ( +// Equation(s): +// \Selector12~15_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~15_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~15 .lut_mask = 16'hF2D0; +defparam \Selector12~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \Selector12~5 ( +// Equation(s): +// \Selector12~5_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector12~15_combout )) # (!\Selector12~4_combout ))) + + .dataa(\Equal5~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector12~4_combout ), + .datad(\Selector12~15_combout ), + .cin(gnd), + .combout(\Selector12~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~5 .lut_mask = 16'hB5A5; +defparam \Selector12~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \Selector12~14 ( +// Equation(s): +// \Selector12~14_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\Selector12~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~14 .lut_mask = 16'hF2D0; +defparam \Selector12~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \Selector12~6 ( +// Equation(s): +// \Selector12~6_combout = (\Selector12~5_combout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\Selector12~4_combout & \Selector12~14_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Selector12~4_combout ), + .datac(\Selector12~5_combout ), + .datad(\Selector12~14_combout ), + .cin(gnd), + .combout(\Selector12~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~6 .lut_mask = 16'hF8F0; +defparam \Selector12~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \Selector12~11 ( +// Equation(s): +// \Selector12~11_combout = (\Selector12~6_combout & ((\Selector12~4_combout ) # ((\Selector12~10_combout & \Selector12~9_combout )))) + + .dataa(\Selector12~4_combout ), + .datab(\Selector12~10_combout ), + .datac(\Selector12~9_combout ), + .datad(\Selector12~6_combout ), + .cin(gnd), + .combout(\Selector12~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~11 .lut_mask = 16'hEA00; +defparam \Selector12~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[1]~12 ( +// Equation(s): +// \D[1]~12_combout = (\Equal5~1_combout & (\Selector12~11_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout +// )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector12~11_combout ), + .cin(gnd), + .combout(\D[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~12 .lut_mask = 16'hCF45; +defparam \D[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~12_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[1]~10_combout )))) # (!\D[1]~12_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[1]~10_combout ))) + + .dataa(\D[1]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N17 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = ((\z80_|bus_control_|db[1]~9_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[1]~9_combout ), + .datab(\z80_|bus_control_|db[0]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB3B; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[1]~10_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(\z80_|ir_|opcode [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|iff1~q ))))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal79~0_combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFCF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N26 +// Location: LCCOMB_X29_Y17_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) +// \z80_|interrupts_|test1~2_combout = ((\z80_|ir_|opcode [5] & ((!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|ir_|opcode [5] & (!\z80_|pla_decode_|Equal2~2_combout ))) # (!\z80_|pla_decode_|Equal2~3_combout ) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal43~0_combout ), + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h3F77; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N30 +// Location: LCCOMB_X29_Y14_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (\z80_|interrupts_|test1~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & ((!\z80_|pla_decode_|Equal3~2_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h002A; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N7 +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|interrupts_|test1~4 ( +// Equation(s): +// \z80_|interrupts_|test1~4_combout = (!\z80_|execute_|setM1~55_combout & ((\z80_|interrupts_|test1~3_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~4 .lut_mask = 16'h3323; +defparam \z80_|interrupts_|test1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_inst44~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(gnd), + .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datac(\z80_|clk_delay_|DFF_inst5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0303; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|execute_|setM1~55_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h5000; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N11 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~2 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~3 ( +// Equation(s): +// \z80_|bus_control_|db[0]~3_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~2_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~3 .lut_mask = 16'hAEAF; +defparam \z80_|bus_control_|db[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \Selector8~5 ( +// Equation(s): +// \Selector8~5_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~5 .lut_mask = 16'hCBC8; +defparam \Selector8~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \Selector8~6 ( +// Equation(s): +// \Selector8~6_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~5_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~5_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~5_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~5_combout ), + .cin(gnd), + .combout(\Selector8~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~6 .lut_mask = 16'hF388; +defparam \Selector8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \Selector8~7 ( +// Equation(s): +// \Selector8~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\Selector8~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~7 .lut_mask = 16'hAEA4; +defparam \Selector8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \Selector8~8 ( +// Equation(s): +// \Selector8~8_combout = (\Selector8~7_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\Selector8~7_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\Selector8~7_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector8~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~8 .lut_mask = 16'hACF0; +defparam \Selector8~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~134_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[0][0]~13_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [3]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~134 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~135_combout = (\ula_|zx_keyboard_|keys[6][3]~134_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~134_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~15_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][3]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~15 .lut_mask = 16'hBB0B; +defparam \ula_|zx_keyboard_|key_row[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[0][3]~94_combout & ((!\ula_|zx_keyboard_|keys[2][4]~93_combout ))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N27 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~12_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// ((\z80_|address_pins_|abus[9]~16_combout ) # ((!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~12 .lut_mask = 16'hCF45; +defparam \ula_|zx_keyboard_|key_row[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h00A0; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~46_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N23 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[2][3]~100_combout & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[2][3]~101_combout & ((\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|zx_keyboard_|keys[2][3]~99_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & +// ((\ula_|zx_keyboard_|keys[2][3]~q ))))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N15 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~13_combout = (\ula_|zx_keyboard_|keys[3][3]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[3][3]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~13 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~76_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~131_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|Selector5~1_combout ), + .datad(\ula_|zx_keyboard_|Selector5~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~131 .lut_mask = 16'hFF20; +defparam \ula_|zx_keyboard_|keys[4][3]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~105_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~131_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hB888; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|shifted~q & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hCCDC; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[4][3]~106_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & ((!\ula_|zx_keyboard_|keys[4][3]~132_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~103_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~14_combout = (\ula_|zx_keyboard_|keys[4][3]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~14 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [3] = (\ula_|zx_keyboard_|key_row[3]~15_combout & (\ula_|zx_keyboard_|key_row[3]~12_combout & (\ula_|zx_keyboard_|key_row[3]~13_combout & \ula_|zx_keyboard_|key_row[3]~14_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .datab(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .datac(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .datad(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [3]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y34_N1 +cycloneive_io_ibuf \kempston[0]~input ( + .i(kempston[0]), + .ibar(gnd), + .o(\kempston[0]~input_o )); +// synopsys translate_off +defparam \kempston[0]~input .bus_hold = "false"; +defparam \kempston[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \Selector8~4 ( +// Equation(s): +// \Selector8~4_combout = (\Selector14~18_combout & (\Selector14~17_combout & ((!\kempston[0]~input_o )))) # (!\Selector14~18_combout & (((\ula_|zx_keyboard_|key_row [3])) # (!\Selector14~17_combout ))) + + .dataa(\Selector14~18_combout ), + .datab(\Selector14~17_combout ), + .datac(\ula_|zx_keyboard_|key_row [3]), + .datad(\kempston[0]~input_o ), + .cin(gnd), + .combout(\Selector8~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~4 .lut_mask = 16'h51D9; +defparam \Selector8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \Selector8~9 ( +// Equation(s): +// \Selector8~9_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & (\Selector8~6_combout )) # (!\Selector8~4_combout & ((\Selector8~8_combout ))))) + + .dataa(\Selector8~6_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector8~8_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\Selector8~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~9 .lut_mask = 16'hEE30; +defparam \Selector8~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[3]~38 ( +// Equation(s): +// \D[3]~38_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector8~9_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), + .cin(gnd), + .combout(\D[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~38 .lut_mask = 16'hDD0D; +defparam \D[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\D[3]~38_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[3]~20_combout )))) # (!\D[3]~38_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[3]~20_combout ))) + + .dataa(\D[3]~38_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N31 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~19 ( +// Equation(s): +// \z80_|bus_control_|db[3]~19_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~19 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = ((\z80_|bus_control_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[3]~19_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[0]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|ir_|opcode[3]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[3]~feeder_combout = \z80_|bus_control_|db[3]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N13 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = (!\z80_|execute_|ctl_alu_op_low~11_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|pla_decode_|Equal56~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|setM1~41_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~60 ( +// Equation(s): +// \z80_|execute_|setM1~60_combout = (\z80_|execute_|ctl_mRead~17_combout & (((\z80_|ir_|opcode [1]) # (\z80_|ir_|opcode [2])) # (!\z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|setM1~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~60 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|setM1~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~60_combout ) # (!\z80_|execute_|setM1~42_combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~60_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~17 ( +// Equation(s): +// \z80_|execute_|nextM~17_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|fMRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~17 .lut_mask = 16'hA020; +defparam \z80_|execute_|nextM~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|nextM~5_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = ((\z80_|execute_|nextM~7_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|nextM~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|nextM~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hA080; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = (\z80_|execute_|nextM~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|nextM~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~17_combout ) # ((\z80_|execute_|nextM~8_combout ) # (\z80_|execute_|nextM~13_combout )) + + .dataa(\z80_|execute_|nextM~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|nextM~8_combout ), + .datad(\z80_|execute_|nextM~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|execute_|nextM~6_combout ) # (((\z80_|execute_|nextM~14_combout ) # (!\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ctl_mWrite~15_combout )) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|setM1~55_combout )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h1010; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N23 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FC; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N14 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y11_N25 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -51736,7 +55677,7 @@ dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .ena(\z80_|interrupts_|test1~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), @@ -51746,115 +55687,363 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X26_Y11_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|interrupts_|im1~feeder ( // Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) +// \z80_|interrupts_|im1~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), + .combout(\z80_|interrupts_|im1~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|im1~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|im1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & -// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N3 -dffeas \z80_|alu_flags_|flags_yf ( +// Location: FF_X27_Y12_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .d(\z80_|interrupts_|im1~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & -// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_yf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .dataa(\z80_|interrupts_|im1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|interrupts_|im2~q ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( // Equation(s): -// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~4_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|alu_control_|db[5]~15_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~16_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~5 ( // Equation(s): -// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) +// \z80_|bus_control_|db[0]~5_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_zero_oe~3_combout ))) - .dataa(\z80_|alu_control_|db[5]~16_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[0]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~5 .lut_mask = 16'hFFFE; +defparam \z80_|bus_control_|db[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y24_N0 +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hEE30; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51862,16 +56051,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51925,7 +56114,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y33_N0 +// Location: M9K_X33_Y6_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -51935,16 +56124,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51983,9 +56172,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51993,16 +56182,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -52055,7 +56244,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -52065,16 +56254,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -52113,361 +56302,112 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N2 -cycloneive_lcell_comb \Mux2~0 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), - .combout(\Mux2~0_combout ), + .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hB9A8; -defparam \Mux2~0 .sum_lutc_input = "datac"; +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \Mux2~1 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \Selector4~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Selector4~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), + .datad(\Selector4~0_combout ), .cin(gnd), - .combout(\Mux2~1_combout ), + .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; +defparam \Selector4~1 .lut_mask = 16'hDDA0; +defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \D[5]~25 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) +// \D[5]~25_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector4~1_combout ))))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datad(\Selector4~1_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .combout(\D[5]~25_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +defparam \D[5]~25 .lut_mask = 16'h3120; +defparam \D[5]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \D[5]~27 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) +// \D[5]~27_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~25_combout )) # (!\D[5]~26_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~25_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~26_combout ), + .datac(\D[5]~25_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\D[5]~27_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \D[5]~27 .lut_mask = 16'hA2F3; +defparam \D[5]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N30 -cycloneive_lcell_comb \D[5]~112 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[5]~40 ( // Equation(s): -// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) +// \D[5]~40_combout = (\D[5]~27_combout ) # (!\D[0]~49_combout ) - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[5]~97_combout ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[5]~27_combout ), .cin(gnd), - .combout(\D[5]~112_combout ), + .combout(\D[5]~40_combout ), .cout()); // synopsys translate_off -defparam \D[5]~112 .lut_mask = 16'hFB73; -defparam \D[5]~112 .sum_lutc_input = "datac"; +defparam \D[5]~40 .lut_mask = 16'hFF33; +defparam \D[5]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N8 -cycloneive_lcell_comb \D[5]~113 ( -// Equation(s): -// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[5]~112_combout ), - .datad(\z80_|data_pins_|dout [5]), - .cin(gnd), - .combout(\D[5]~113_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~113 .lut_mask = 16'hF151; -defparam \D[5]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 +// Location: LCCOMB_X26_Y16_N18 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~40_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[5]~16_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[5]~40_combout & (\z80_|bus_control_|db[5]~16_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[5]~113_combout ), + .dataa(\D[5]~40_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N25 +// Location: FF_X26_Y16_N19 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -52486,50 +56426,50 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|data_pins_|dout [5]), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N24 +// Location: LCCOMB_X26_Y15_N16 cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|alu_control_|db[5]~17_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[5]~14_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hA0AA; defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N25 +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Equation(s): +// \z80_|bus_control_|db[5]~16_combout = ((\z80_|bus_control_|db[5]~15_combout & ((\z80_|alu_control_|db[5]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N21 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~15_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~16_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [5]), @@ -52539,991 +56479,75 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) - - .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|nextM~3_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) - - .dataa(\z80_|execute_|nextM~7_combout ), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mWrite~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N23 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N27 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N31 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N21 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # -// (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~22_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|pla_decode_|Equal4~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) - - .dataa(\z80_|execute_|setM1~55_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~31_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|setM1~20_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~28_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & -// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|interrupts_|test1~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) - - .dataa(\z80_|execute_|setM1~8_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) - - .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~12_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N16 +// Location: LCCOMB_X31_Y15_N8 cycloneive_lcell_comb \z80_|execute_|setM1~43 ( // Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|setM1~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h1515; defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|setM1~42_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|execute_|setM1~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|setM1~50_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 +// Location: LCCOMB_X36_Y11_N28 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~55_combout )) - .dataa(gnd), + .dataa(\z80_|execute_|nextM~15_combout ), .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h4040; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N19 +// Location: FF_X36_Y11_N29 dffeas \z80_|sequencer_|T6 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), @@ -53542,59 +56566,625 @@ defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; defparam \z80_|sequencer_|T6 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( // Equation(s): -// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & -// (!\z80_|execute_|setM1~41_combout ))) +// \z80_|execute_|setM1~16_combout = (!\z80_|execute_|ctl_alu_oe~5_combout & (!\z80_|pla_decode_|Equal1~3_combout & (!\z80_|pla_decode_|Equal77~1_combout & !\z80_|pla_decode_|Equal2~4_combout ))) - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|sequencer_|T6~q ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|setM1~40_combout ), + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), + .combout(\z80_|execute_|setM1~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|interrupts_|test1~3_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~17_combout )) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h080C; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~13_combout & (\z80_|execute_|setM1~45_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|pla_decode_|Equal5~2_combout & \z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 cycloneive_lcell_comb \z80_|execute_|setM1~53 ( // Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|setM1~18_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|setM1~48_combout ))) - .dataa(\z80_|execute_|setM1~35_combout ), - .datab(\z80_|execute_|setM1~19_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~18_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~48_combout ), .cin(gnd), .combout(\z80_|execute_|setM1~53_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h8000; defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) +// \z80_|execute_|setM1~54_combout = (\z80_|execute_|setM1~43_combout & (((\z80_|execute_|setM1~42_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~43_combout & ((\z80_|sequencer_|T6~q ) # ((\z80_|execute_|setM1~42_combout & +// \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'hCCCE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~24_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hE0A0; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|fMWrite~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|setM1~57_combout & (((\z80_|execute_|ctl_reg_in_hi~6_combout & !\z80_|execute_|setM1~25_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~57_combout & +// (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|setM1~25_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (((\z80_|pla_decode_|Equal40~1_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~10_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & +// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|setM1~26_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~29_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hCCDC; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~13_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (((\z80_|execute_|setM1~31_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~32_combout )) # (!\z80_|execute_|setM1~58_combout ) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~32_combout ), + .datac(\z80_|execute_|setM1~31_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~34_combout ), + .datac(\z80_|execute_|setM1~35_combout ), + .datad(\z80_|execute_|setM1~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|execute_|ctl_mRead~9_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h2A0A; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout ) # ((\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|setM1~36_combout ) # ((\z80_|execute_|setM1~56_combout ) # (\z80_|execute_|setM1~23_combout ))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|setM1~56_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMWrite~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~12_combout ) # (((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|setM1~13_combout )) # (!\z80_|execute_|nextM~4_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|sequencer_|M5~q ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|execute_|ctl_sw_4d~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_M4_ff~q & +// (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCF0F; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|execute_|setM1~11_combout ) # (((\z80_|execute_|setM1~14_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~14_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|setM1~19_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~15_combout ) # (((!\z80_|execute_|setM1~18_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~20_combout )) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|setM1~20_combout ), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hBFBB; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|setM1~37_combout & (!\z80_|execute_|setM1~21_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~54_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h000B; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~15_combout ))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N15 +// Location: FF_X36_Y11_N7 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -53613,27 +57203,28 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & +// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hC1F0; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N29 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), +// Location: FF_X27_Y15_N23 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53642,65 +57233,156 @@ dffeas \z80_|sequencer_|DFFE_M2_ff ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .q(\z80_|resets_|clrpc_int~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y16_N20 +// Location: FF_X26_Y9_N3 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N5 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y9_N1 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y16_N21 +// Location: FF_X29_Y9_N17 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53719,332 +57401,561 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N30 -cycloneive_lcell_comb \D[0]~66 ( +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 ( // Equation(s): -// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[0]~58_combout ), - .datad(\D[0]~120_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~66_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cout()); // synopsys translate_off -defparam \D[0]~66 .lut_mask = 16'hF3C0; -defparam \D[0]~66 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N18 -cycloneive_lcell_comb \D[0]~67 ( +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 ( // Equation(s): -// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\Equal2~1_combout ), - .datad(\D[0]~66_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cin(gnd), - .combout(\D[0]~67_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), .cout()); // synopsys translate_off -defparam \D[0]~67 .lut_mask = 16'hDD0D; -defparam \D[0]~67 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .lut_mask = 16'hF388; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N24 -cycloneive_lcell_comb \D[0]~121 ( +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \Selector14~15 ( // Equation(s): -// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \Selector14~15_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # +// (!\z80_|address_pins_|abus[14]~22_combout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~121_combout ), + .combout(\Selector14~15_combout ), .cout()); // synopsys translate_off -defparam \D[0]~121 .lut_mask = 16'hFF20; -defparam \D[0]~121 .sum_lutc_input = "datac"; +defparam \Selector14~15 .lut_mask = 16'hBA98; +defparam \Selector14~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N16 -cycloneive_lcell_comb \D[1]~68 ( +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \Selector14~16 ( // Equation(s): -// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) +// \Selector14~16_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector14~15_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\Selector14~15_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector14~15_combout )))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[1]~34_combout ), - .datad(\D[1]~118_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\Selector14~15_combout ), .cin(gnd), - .combout(\D[1]~68_combout ), + .combout(\Selector14~16_combout ), .cout()); // synopsys translate_off -defparam \D[1]~68 .lut_mask = 16'hF3C0; -defparam \D[1]~68 .sum_lutc_input = "datac"; +defparam \Selector14~16 .lut_mask = 16'hBBC0; +defparam \Selector14~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N14 -cycloneive_lcell_comb \D[1]~69 ( +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \D[0]~15 ( // Equation(s): -// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) +// \D[0]~15_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & ((\Selector14~8_combout & ((\Selector14~16_combout ))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout +// )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), + .datac(\Selector14~16_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\D[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~15 .lut_mask = 16'hFA44; +defparam \D[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \D[0]~16 ( +// Equation(s): +// \D[0]~16_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~15_combout ) # (!\Equal5~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[0]~15_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Equal5~1_combout ), + .datad(\D[0]~15_combout ), + .cin(gnd), + .combout(\D[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~16 .lut_mask = 16'hBB0B; +defparam \D[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \Selector12~12 ( +// Equation(s): +// \Selector12~12_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~12_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~12 .lut_mask = 16'hD9C8; +defparam \Selector12~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N2 +cycloneive_lcell_comb \Selector12~13 ( +// Equation(s): +// \Selector12~13_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector12~12_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector12~12_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector12~12_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector12~12_combout ), + .cin(gnd), + .combout(\Selector12~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~13 .lut_mask = 16'hDDA0; +defparam \Selector12~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \D[1]~17 ( +// Equation(s): +// \D[1]~17_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & ((\Selector12~4_combout & ((\Selector12~13_combout ))) # (!\Selector12~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout +// )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .datac(\Selector12~4_combout ), + .datad(\Selector12~13_combout ), + .cin(gnd), + .combout(\D[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~17 .lut_mask = 16'hF4A4; +defparam \D[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \D[1]~18 ( +// Equation(s): +// \D[1]~18_combout = (\Equal5~1_combout & (\D[1]~17_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), .datab(\z80_|data_pins_|dout [1]), - .datac(\Equal2~1_combout ), - .datad(\D[1]~68_combout ), - .cin(gnd), - .combout(\D[1]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~69 .lut_mask = 16'hDD0D; -defparam \D[1]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N16 -cycloneive_lcell_comb \D[2]~70 ( -// Equation(s): -// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) - - .dataa(gnd), - .datab(\D[2]~46_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~70 .lut_mask = 16'hCFC0; -defparam \D[2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N14 -cycloneive_lcell_comb \D[2]~71 ( -// Equation(s): -// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~70_combout ), - .cin(gnd), - .combout(\D[2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~71 .lut_mask = 16'hF531; -defparam \D[2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N24 -cycloneive_lcell_comb \D[3]~83 ( -// Equation(s): -// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [3]), - .datad(gnd), - .cin(gnd), - .combout(\D[3]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~83 .lut_mask = 16'hF5F5; -defparam \D[3]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \D[3]~84 ( -// Equation(s): -// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) - - .dataa(\D[3]~122_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[3]~82_combout ), - .datad(\D[3]~83_combout ), - .cin(gnd), - .combout(\D[3]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~84 .lut_mask = 16'hFB00; -defparam \D[3]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N20 -cycloneive_lcell_comb \D[4]~95 ( -// Equation(s): -// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) - - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~95 .lut_mask = 16'hB8B8; -defparam \D[4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N6 -cycloneive_lcell_comb \D[4]~96 ( -// Equation(s): -// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\Equal2~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[4]~95_combout ), + .datad(\D[1]~17_combout ), .cin(gnd), - .combout(\D[4]~96_combout ), + .combout(\D[1]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~96 .lut_mask = 16'hAF23; -defparam \D[4]~96 .sum_lutc_input = "datac"; +defparam \D[1]~18 .lut_mask = 16'hCF45; +defparam \D[1]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N18 -cycloneive_lcell_comb \D[5]~126 ( +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \D[2]~19 ( // Equation(s): -// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) +// \D[2]~19_combout = (\Selector10~2_combout & (((\Selector10~1_combout ) # (\Equal5~0_combout )))) # (!\Selector10~2_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout & ((!\Equal5~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Selector10~2_combout ), + .datac(\Selector10~1_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~19 .lut_mask = 16'hCCE2; +defparam \D[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \D[2]~20 ( +// Equation(s): +// \D[2]~20_combout = (\Equal5~1_combout & (\D[2]~19_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [2]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [2]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[2]~19_combout ), + .cin(gnd), + .combout(\D[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~20 .lut_mask = 16'hCF45; +defparam \D[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \Selector8~2 ( +// Equation(s): +// \Selector8~2_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~2 .lut_mask = 16'hCBC8; +defparam \Selector8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \Selector8~3 ( +// Equation(s): +// \Selector8~3_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~2_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~2_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~2_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~2_combout ), + .cin(gnd), + .combout(\Selector8~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~3 .lut_mask = 16'hF388; +defparam \Selector8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[3]~21 ( +// Equation(s): +// \D[3]~21_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & ((\Selector8~3_combout ))) # (!\Selector8~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datac(\Selector8~3_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\D[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~21 .lut_mask = 16'hFA44; +defparam \D[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~22 ( +// Equation(s): +// \D[3]~22_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~21_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[3]~21_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[3]~21_combout ), + .cin(gnd), + .combout(\D[3]~22_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~22 .lut_mask = 16'hAF23; +defparam \D[3]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[4]~23 ( +// Equation(s): +// \D[4]~23_combout = (\Selector6~6_combout & ((\Selector6~1_combout ) # ((\Equal5~0_combout )))) # (!\Selector6~6_combout & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout & !\Equal5~0_combout )))) + + .dataa(\Selector6~1_combout ), + .datab(\Selector6~6_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~23 .lut_mask = 16'hCCB8; +defparam \D[4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[4]~24 ( +// Equation(s): +// \D[4]~24_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~23_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~23_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\D[4]~23_combout ), + .cin(gnd), + .combout(\D[4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~24 .lut_mask = 16'hDD0D; +defparam \D[4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[6]~32 ( +// Equation(s): +// \D[6]~32_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~32 .lut_mask = 16'hE3E0; +defparam \D[6]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[6]~33 ( +// Equation(s): +// \D[6]~33_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~32_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~32_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~32_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~32_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~33 .lut_mask = 16'hF838; +defparam \D[6]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \D[6]~29 ( +// Equation(s): +// \D[6]~29_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~29 .lut_mask = 16'hE6A2; +defparam \D[6]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[6]~30 ( +// Equation(s): +// \D[6]~30_combout = (\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~29_combout ))))) # (!\z80_|address_pins_|abus[15]~23_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~29_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~29_combout ), + .cin(gnd), + .combout(\D[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~30 .lut_mask = 16'h44B8; +defparam \D[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \D[6]~31 ( +// Equation(s): +// \D[6]~31_combout = (\D[6]~29_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~30_combout )))) # (!\D[6]~29_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~30_combout )))) + + .dataa(\D[6]~29_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~30_combout ), + .cin(gnd), + .combout(\D[6]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~31 .lut_mask = 16'h99A8; +defparam \D[6]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[6]~50 ( +// Equation(s): +// \D[6]~50_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~33_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~31_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~33_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .datac(\D[6]~33_combout ), + .datad(\D[6]~31_combout ), .cin(gnd), - .combout(\D[5]~126_combout ), + .combout(\D[6]~50_combout ), .cout()); // synopsys translate_off -defparam \D[5]~126 .lut_mask = 16'hFB40; -defparam \D[5]~126 .sum_lutc_input = "datac"; +defparam \D[6]~50 .lut_mask = 16'hF4B0; +defparam \D[6]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N0 -cycloneive_lcell_comb \D[5]~98 ( +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \D[6]~34 ( // Equation(s): -// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) +// \D[6]~34_combout = (\Equal5~0_combout & (\D[6]~28_combout & (\Equal3~2_combout ))) # (!\Equal5~0_combout & (((\D[6]~50_combout )))) - .dataa(\z80_|data_pins_|dout [5]), - .datab(\D[5]~97_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[5]~126_combout ), + .dataa(\D[6]~28_combout ), + .datab(\Equal3~2_combout ), + .datac(\Equal5~0_combout ), + .datad(\D[6]~50_combout ), .cin(gnd), - .combout(\D[5]~98_combout ), + .combout(\D[6]~34_combout ), .cout()); // synopsys translate_off -defparam \D[5]~98 .lut_mask = 16'hAF23; -defparam \D[5]~98 .sum_lutc_input = "datac"; +defparam \D[6]~34 .lut_mask = 16'h8F80; +defparam \D[6]~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N18 -cycloneive_lcell_comb \D[6]~105 ( +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[6]~35 ( // Equation(s): -// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) - - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~105 .lut_mask = 16'hFC30; -defparam \D[6]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N0 -cycloneive_lcell_comb \D[6]~106 ( -// Equation(s): -// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) +// \D[6]~35_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~34_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~34_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [6]), - .datab(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~105_combout ), + .datad(\D[6]~34_combout ), .cin(gnd), - .combout(\D[6]~106_combout ), + .combout(\D[6]~35_combout ), .cout()); // synopsys translate_off -defparam \D[6]~106 .lut_mask = 16'hAF23; -defparam \D[6]~106 .sum_lutc_input = "datac"; +defparam \D[6]~35 .lut_mask = 16'hAF23; +defparam \D[6]~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N10 -cycloneive_lcell_comb \D[7]~128 ( -// Equation(s): -// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~128_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~128 .lut_mask = 16'hF2D0; -defparam \D[7]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N16 -cycloneive_lcell_comb \D[7]~107 ( -// Equation(s): -// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[5]~97_combout ), - .datad(\D[7]~128_combout ), - .cin(gnd), - .combout(\D[7]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~107 .lut_mask = 16'hBB0B; -defparam \D[7]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 +// Location: LCCOMB_X36_Y11_N2 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; +defparam \z80_|nM1_int~3 .lut_mask = 16'hE0E0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N13 +// Location: FF_X36_Y11_N3 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -54063,7 +57974,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X26_Y12_N22 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -54080,7 +57991,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N5 +// Location: FF_X26_Y12_N23 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -54099,7 +58010,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N27 +// Location: FF_X26_Y12_N21 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -54118,32 +58029,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N26 +// Location: LCCOMB_X26_Y12_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|wait_mwr~q ), - .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .datab(\z80_|memory_ifc_|wait_mwr~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N2 +// Location: LCCOMB_X26_Y12_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ))) - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(\z80_|memory_ifc_|wait_mrd~q ), - .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -54165,7 +58076,24 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -54182,7 +58110,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X3_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -54201,14 +58129,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X3_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -54219,7 +58147,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N9 +// Location: FF_X3_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -54238,7 +58166,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X3_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -54256,7 +58184,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N11 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -54275,7 +58203,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X3_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -54293,7 +58221,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -54312,24 +58240,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) - - .dataa(\ula_|i2c_loader_|divider [3]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [1]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -54347,7 +58258,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -54366,7 +58277,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X3_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -54383,7 +58294,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X3_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -54402,60 +58313,41 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N30 +// Location: LCCOMB_X3_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), .datac(\ula_|i2c_loader_|divider [4]), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 -dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|scl_out~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N23 +// Location: FF_X1_Y23_N19 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -54474,7 +58366,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -54491,7 +58383,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -54510,24 +58402,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0CC0; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N31 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -54546,75 +58438,174 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: FF_X1_Y23_N5 +dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|scl_out~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N24 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hA0A0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~4_combout ), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; -defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEAAE; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X2_Y23_N15 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54633,67 +58624,135 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hCCC0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y22_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|state.Pause~0_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|nbit[0]~1_combout )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~0_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N27 +// Location: LCCOMB_X1_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|Mux42~0_combout & !\ula_|i2c_loader_|WideAnd0~combout ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0040; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~4_combout ), + .d(\ula_|i2c_loader_|nbit~5_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [0]), @@ -54703,43 +58762,7 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y25_N1 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y25_N28 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) @@ -54756,75 +58779,41 @@ defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 +// Location: LCCOMB_X2_Y22_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N4 +// Location: LCCOMB_X2_Y22_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|state~27_combout ), + .datab(\ula_|i2c_loader_|state~26_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), + .datad(\ula_|i2c_loader_|state~27_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X2_Y22_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54843,24 +58832,60 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N12 +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): // \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [1]), + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|nbit [2]), .datad(\ula_|i2c_loader_|nbit [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N13 +// Location: FF_X2_Y23_N13 dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~0_combout ), @@ -54869,7 +58894,7 @@ dffeas \ula_|i2c_loader_|nbit[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [2]), @@ -54879,32 +58904,32 @@ defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N30 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [0] & \ula_|i2c_loader_|state.Data~q ))) .dataa(\ula_|i2c_loader_|nbit [2]), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0100; defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N2 +// Location: LCCOMB_X2_Y22_N16 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Idle~0_combout ), .cout()); @@ -54913,7 +58938,7 @@ defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N16 +// Location: LCCOMB_X2_Y22_N6 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( // Equation(s): // \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) @@ -54930,25 +58955,25 @@ defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y22_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Ack~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N25 +// Location: FF_X2_Y22_N3 dffeas \ula_|i2c_loader_|state.Ack ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Ack~1_combout ), @@ -54967,121 +58992,24 @@ defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2c_loader_|nbyte~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) +// \ula_|i2c_loader_|state.Stop~0_combout = (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N6 +// Location: LCCOMB_X2_Y22_N4 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): // \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # @@ -55099,7 +59027,7 @@ defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N7 +// Location: FF_X2_Y22_N5 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -55118,24 +59046,24 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 +// Location: LCCOMB_X2_Y22_N22 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Stop~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h5FCC; defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -55153,41 +59081,41 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~5 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\I2C_SDAT~input_o ), + .datad(\ula_|i2c_loader_|nbyte [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .combout(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbyte[0]~5 .lut_mask = 16'hFAD8; +defparam \ula_|i2c_loader_|nbyte[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|nbyte[0]~5_combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h2000; defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|thisbyte[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), @@ -55206,25 +59134,25 @@ defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N20 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) // \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N21 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|thisbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), @@ -55243,25 +59171,25 @@ defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) // \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: FF_X3_Y23_N9 dffeas \ula_|i2c_loader_|thisbyte[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), @@ -55280,25 +59208,25 @@ defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X3_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) // \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N25 +// Location: FF_X3_Y23_N11 dffeas \ula_|i2c_loader_|thisbyte[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), @@ -55318,40 +59246,23 @@ defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N27 +// Location: FF_X3_Y23_N13 dffeas \ula_|i2c_loader_|thisbyte[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), @@ -55370,94 +59281,111 @@ defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N22 +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0004; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N12 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|Equal2~0_combout ) # (!\ula_|i2c_loader_|thisbyte [4]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~2_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0AAA; defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X2_Y22_N10 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Stop~q ), + .dataa(gnd), .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(gnd), + .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N26 +// Location: LCCOMB_X2_Y22_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Pause~1_combout )))) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h0ACE; defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y22_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF373; defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N20 +// Location: LCCOMB_X2_Y22_N26 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # // (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~3_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE2F0; defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N21 +// Location: FF_X2_Y22_N27 dffeas \ula_|i2c_loader_|state.Pause ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Pause~6_combout ), @@ -55476,25 +59404,25 @@ defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N30 +// Location: LCCOMB_X2_Y22_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( // Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|state.Start~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|state.Pause~q & \ula_|i2c_loader_|Mux42~0_combout ))) # // (!\ula_|i2c_loader_|state.Idle~q ) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h3BF3; defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N31 +// Location: FF_X2_Y22_N29 dffeas \ula_|i2c_loader_|state.Start ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state~25_combout ), @@ -55513,38 +59441,38 @@ defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Start .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # // ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hC3EA; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~1_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC0C3; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55586,186 +59514,152 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|shiftreg~19_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~13_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hFF10; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte [4])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|shiftreg~22_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h3530; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [3]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hF404; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h1010; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~27_combout = (\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; -defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - - .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datab(\ula_|i2c_loader_|state~24_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; -defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .lut_mask = 16'hEEE4; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~28 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~28_combout = (\ula_|i2c_loader_|shiftreg[0]~27_combout & (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Idle~q & !\ula_|i2c_loader_|WideAnd0~combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~27_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .lut_mask = 16'h0080; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N21 +// Location: FF_X2_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55775,85 +59669,136 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg~23_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [0]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; -defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h8090; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y22_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~6 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~6_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~6 .lut_mask = 16'h0033; +defparam \ula_|i2c_loader_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~6_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((!\ula_|i2c_loader_|thisbyte [0] & \ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~6_combout ), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8C88; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [1]) # ((!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state~24_combout )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'h8CBF; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~9_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state~24_combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h2E2F; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X2_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & -// !\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (!\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; -defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 +// Location: FF_X2_Y24_N17 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~24_combout ), + .d(\ula_|i2c_loader_|shiftreg~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55863,33 +59808,67 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) - .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h5030; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N11 +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~18_combout ))) # (!\ula_|i2c_loader_|shiftreg~6_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~6_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h2EFF; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hCF00; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~21_combout ), + .d(\ula_|i2c_loader_|shiftreg~20_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55899,84 +59878,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg~17_combout & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~17_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAE04; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), - .datab(\ula_|i2c_loader_|shiftreg~15_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [2]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; -defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N23 +// Location: FF_X2_Y24_N19 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~27_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55986,67 +59914,33 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE54; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|shiftreg~14_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [3]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~16_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N15 +// Location: FF_X2_Y24_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -56056,33 +59950,50 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - .dataa(\ula_|i2c_loader_|Mux35~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|shiftreg [4]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h40C0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N5 +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [4])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg [4]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hBB88; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~13_combout ), + .d(\ula_|i2c_loader_|shiftreg~12_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -56092,33 +60003,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), - .datab(\ula_|i2c_loader_|Mux35~0_combout ), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [5]), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -56128,33 +60039,33 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) +// \ula_|i2c_loader_|shiftreg[7]~7_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|shiftreg [6]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .combout(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N29 +// Location: FF_X2_Y24_N1 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .d(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -56164,16 +60075,16 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); @@ -56182,14 +60093,14 @@ defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~6_combout & !\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~6_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), @@ -56199,38 +60110,38 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h0C0E; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2F4; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56239,15 +60150,15 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56391,735 +60302,118 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux38~0 ( -// Equation(s): -// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) - - .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), - .datab(\Equal2~1_combout ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Mux39~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux38~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; -defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y12_N15 -dffeas \sdram_|r.rd_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux38~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rd_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rd_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N0 -cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( -// Equation(s): -// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) -// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\sdram_|r.rf_counter[0]~12_combout ), - .cout(\sdram_|r.rf_counter[0]~13 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; -defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N26 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.address[3]~6_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.rf_counter[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; -defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N1 -dffeas \sdram_|r.rf_counter[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N2 -cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( -// Equation(s): -// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) -// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [1]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[0]~13 ), - .combout(\sdram_|r.rf_counter[1]~14_combout ), - .cout(\sdram_|r.rf_counter[1]~15 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N3 -dffeas \sdram_|r.rf_counter[1] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[1]~14_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N4 -cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( -// Equation(s): -// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) -// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [2]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[1]~15 ), - .combout(\sdram_|r.rf_counter[2]~16_combout ), - .cout(\sdram_|r.rf_counter[2]~17 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N5 -dffeas \sdram_|r.rf_counter[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[2]~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N6 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) -// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[2]~17 ), - .combout(\sdram_|r.rf_counter[3]~18_combout ), - .cout(\sdram_|r.rf_counter[3]~19 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N7 -dffeas \sdram_|r.rf_counter[3] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[3]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N8 -cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( -// Equation(s): -// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) -// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [4]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[3]~19 ), - .combout(\sdram_|r.rf_counter[4]~20_combout ), - .cout(\sdram_|r.rf_counter[4]~21 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N9 -dffeas \sdram_|r.rf_counter[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[4]~20_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N10 -cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( -// Equation(s): -// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) -// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[4]~21 ), - .combout(\sdram_|r.rf_counter[5]~22_combout ), - .cout(\sdram_|r.rf_counter[5]~23 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N11 -dffeas \sdram_|r.rf_counter[5] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[5]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N12 -cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( -// Equation(s): -// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) -// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) - - .dataa(\sdram_|r.rf_counter [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[5]~23 ), - .combout(\sdram_|r.rf_counter[6]~24_combout ), - .cout(\sdram_|r.rf_counter[6]~25 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; -defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N13 -dffeas \sdram_|r.rf_counter[6] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N14 -cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( -// Equation(s): -// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) -// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [7]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[6]~25 ), - .combout(\sdram_|r.rf_counter[7]~26_combout ), - .cout(\sdram_|r.rf_counter[7]~27 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N15 -dffeas \sdram_|r.rf_counter[7] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[7]~26_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N24 -cycloneive_lcell_comb \sdram_|Equal0~1 ( -// Equation(s): -// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(\sdram_|r.rf_counter [7]), - .datac(\sdram_|r.rf_counter [4]), - .datad(\sdram_|r.rf_counter [6]), - .cin(gnd), - .combout(\sdram_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; -defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N16 -cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( -// Equation(s): -// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) -// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [8]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[7]~27 ), - .combout(\sdram_|r.rf_counter[8]~28_combout ), - .cout(\sdram_|r.rf_counter[8]~29 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N17 -dffeas \sdram_|r.rf_counter[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[8]~28_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal0~0 ( -// Equation(s): -// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(\sdram_|r.rf_counter [0]), - .datac(\sdram_|r.rf_counter [2]), - .datad(\sdram_|r.rf_counter [1]), - .cin(gnd), - .combout(\sdram_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; -defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N18 -cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( -// Equation(s): -// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\sdram_|r.rf_counter [9]), - .cin(\sdram_|r.rf_counter[8]~29 ), - .combout(\sdram_|r.rf_counter[9]~30_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; -defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N19 -dffeas \sdram_|r.rf_counter[9] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[9]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [9]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N22 -cycloneive_lcell_comb \sdram_|Equal0~2 ( -// Equation(s): -// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) - - .dataa(\sdram_|Equal0~1_combout ), - .datab(\sdram_|r.rf_counter [8]), - .datac(\sdram_|Equal0~0_combout ), - .datad(\sdram_|r.rf_counter [9]), - .cin(gnd), - .combout(\sdram_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; -defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N28 -cycloneive_lcell_comb \sdram_|Mux13~8 ( -// Equation(s): -// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|Mux13~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; -defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N20 -cycloneive_lcell_comb \sdram_|Mux37~0 ( -// Equation(s): -// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux13~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux37~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; -defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N21 -dffeas \sdram_|r.rf_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux37~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rf_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N14 -cycloneive_lcell_comb \sdram_|Mux4~0 ( -// Equation(s): -// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; -defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux4~1 ( -// Equation(s): -// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; -defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N2 -cycloneive_lcell_comb \sdram_|Mux4~2 ( -// Equation(s): -// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; -defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N30 +// Location: LCCOMB_X21_Y19_N4 cycloneive_lcell_comb \sdram_|Mux4~3 ( // Equation(s): -// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) +// \sdram_|Mux4~3_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [6])) - .dataa(\sdram_|Mux4~1_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux4~2_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux4~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .lut_mask = 16'hAA50; defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N31 -dffeas \sdram_|r.state[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux4~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.state [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.state[8] .is_wysiwyg = "true"; -defparam \sdram_|r.state[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N6 -cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~0 ( // Equation(s): -// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) +// \sdram_|Mux4~0_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4]))) .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.act_row[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; -defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N18 -cycloneive_lcell_comb \sdram_|process_0~2 ( -// Equation(s): -// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) - - .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|process_0~2_combout ), + .combout(\sdram_|Mux4~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; -defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux4~0 .lut_mask = 16'hAF00; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N0 -cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( // Equation(s): -// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - .dataa(\sdram_|r.act_row[1]~0_combout ), - .datab(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.state [6]), + .datab(gnd), .datac(\sdram_|r.state [7]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.act_row[1]~1_combout ), + .combout(\sdram_|r.address[3]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; -defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N9 -dffeas \sdram_|r.act_row[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\z80_|address_pins_|abus[15]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [4]), - .prn(vcc)); +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[4] .power_up = "low"; +defparam \sdram_|Mux7~2 .lut_mask = 16'h0B00; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N23 -dffeas \sdram_|r.act_row[3] ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [6] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hCC00; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h5500; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \sdram_|r.act_row[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N20 -cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( -// Equation(s): -// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\sdram_|r.act_row[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; -defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y13_N21 -dffeas \sdram_|r.act_row[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.act_row[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.act_row [2]), @@ -57129,115 +60423,80 @@ defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; defparam \sdram_|r.act_row[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N22 +// Location: FF_X21_Y14_N11 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 cycloneive_lcell_comb \sdram_|Equal7~1 ( // Equation(s): -// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & -// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\sdram_|r.act_row [3]), - .datad(\sdram_|r.act_row [2]), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\sdram_|r.act_row [2]), + .datad(\sdram_|r.act_row [3]), .cin(gnd), .combout(\sdram_|Equal7~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .lut_mask = 16'h8241; defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N3 -dffeas \sdram_|r.act_row[1] ( +// Location: FF_X21_Y14_N1 +dffeas \sdram_|r.act_row[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .asdata(\z80_|address_pins_|abus[15]~23_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.act_row [1]), + .q(\sdram_|r.act_row [4]), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[1] .power_up = "low"; +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X21_Y13_N13 -dffeas \sdram_|r.act_row[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[11]~19_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N2 -cycloneive_lcell_comb \sdram_|Equal7~0 ( -// Equation(s): -// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & -// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\sdram_|r.act_row [1]), - .datad(\sdram_|r.act_row [0]), - .cin(gnd), - .combout(\sdram_|Equal7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; -defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal7~2 ( -// Equation(s): -// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\sdram_|r.act_row [4]), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|Equal7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; -defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N4 +// Location: LCCOMB_X20_Y15_N20 cycloneive_lcell_comb \sdram_|Mux39~0 ( // Equation(s): -// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) +// \sdram_|Mux39~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux39~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .lut_mask = 16'h8402; defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N12 +// Location: LCCOMB_X20_Y15_N14 cycloneive_lcell_comb \sdram_|Mux39~1 ( // Equation(s): // \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) @@ -57254,24 +60513,24 @@ defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N24 +// Location: LCCOMB_X21_Y15_N30 cycloneive_lcell_comb \sdram_|Mux39~2 ( // Equation(s): -// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.wr_pending~q & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~23_combout ))) - .dataa(\sdram_|Mux39~1_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), .datac(\sdram_|r.wr_pending~q ), - .datad(\ExtRamWE~0_combout ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), .combout(\sdram_|Mux39~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .lut_mask = 16'hF808; defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y12_N25 +// Location: FF_X21_Y15_N31 dffeas \sdram_|r.wr_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux39~2_combout ), @@ -57290,180 +60549,44 @@ defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; defparam \sdram_|r.wr_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux38~3 ( // Equation(s): -// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) +// \sdram_|Mux38~3_combout = (!\sdram_|r.rd_pending~q & (((!\z80_|memory_ifc_|nIORQ_out~0_combout & \z80_|address_pins_|DFFE_apin_latch [15])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux9~8_combout ), + .combout(\sdram_|Mux38~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; -defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~3 .lut_mask = 16'h0073; +defparam \sdram_|Mux38~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux38~2 ( // Equation(s): -// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) +// \sdram_|Mux38~2_combout = (\Equal5~1_combout & ((\sdram_|Mux38~3_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) # (!\Equal5~1_combout & (((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|Mux38~3_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), - .combout(\sdram_|Mux9~9_combout ), + .combout(\sdram_|Mux38~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; -defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~2 .lut_mask = 16'hF888; +defparam \sdram_|Mux38~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N26 -cycloneive_lcell_comb \sdram_|Mux6~3 ( -// Equation(s): -// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux9~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; -defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N0 -cycloneive_lcell_comb \sdram_|Mux6~4 ( -// Equation(s): -// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) - - .dataa(gnd), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux6~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; -defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N6 -cycloneive_lcell_comb \sdram_|Mux6~2 ( -// Equation(s): -// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; -defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N10 -cycloneive_lcell_comb \sdram_|Mux6~5 ( -// Equation(s): -// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) - - .dataa(\sdram_|Mux6~3_combout ), - .datab(\sdram_|Mux6~4_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|Mux6~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; -defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N8 -cycloneive_lcell_comb \sdram_|process_0~3 ( -// Equation(s): -// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|process_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; -defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux6~0 ( -// Equation(s): -// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|process_0~3_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; -defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N16 -cycloneive_lcell_comb \sdram_|Mux6~1 ( -// Equation(s): -// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux6~0_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; -defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N24 -cycloneive_lcell_comb \sdram_|Mux6~6 ( -// Equation(s): -// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux6~5_combout ), - .datad(\sdram_|Mux6~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; -defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y15_N25 -dffeas \sdram_|r.state[6] ( +// Location: FF_X21_Y15_N21 +dffeas \sdram_|r.rd_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux6~6_combout ), + .d(\sdram_|Mux38~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57472,175 +60595,73 @@ dffeas \sdram_|r.state[6] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.state [6]), + .q(\sdram_|r.rd_pending~q ), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.state[6] .is_wysiwyg = "true"; -defparam \sdram_|r.state[6] .power_up = "low"; +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N12 -cycloneive_lcell_comb \sdram_|r.address[3]~6 ( -// Equation(s): -// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; -defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux7~2 ( -// Equation(s): -// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) - - .dataa(\sdram_|r.address[3]~6_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; -defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N12 +// Location: LCCOMB_X21_Y14_N22 cycloneive_lcell_comb \sdram_|n~3 ( // Equation(s): -// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) +// \sdram_|n~3_combout = (\sdram_|r.wr_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ ((!\sdram_|r.act_row [4])))) # (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) - .dataa(gnd), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Equal7~2_combout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|n~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .lut_mask = 16'h9990; defparam \sdram_|n~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N6 -cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \sdram_|n~4 ( // Equation(s): -// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.state [6]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; -defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N28 -cycloneive_lcell_comb \sdram_|Mux7~4 ( -// Equation(s): -// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) - - .dataa(\sdram_|Mux7~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux7~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; -defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N10 -cycloneive_lcell_comb \sdram_|Mux7~5 ( -// Equation(s): -// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux7~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux7~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; -defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux23~0 ( -// Equation(s): -// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) +// \sdram_|n~4_combout = (\sdram_|Equal7~1_combout & (\sdram_|n~3_combout & \sdram_|Equal7~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(gnd), + .datab(\sdram_|Equal7~1_combout ), + .datac(\sdram_|n~3_combout ), + .datad(\sdram_|Equal7~0_combout ), .cin(gnd), - .combout(\sdram_|Mux23~0_combout ), + .combout(\sdram_|n~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; -defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +defparam \sdram_|n~4 .lut_mask = 16'hC000; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \sdram_|Mux10~9 ( // Equation(s): -// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) +// \sdram_|Mux10~9_combout = (!\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|Mux13~7_combout ), + .combout(\sdram_|Mux10~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; -defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux10~9 .lut_mask = 16'h00EF; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux10~10 ( -// Equation(s): -// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.rf_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; -defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N18 +// Location: LCCOMB_X19_Y17_N20 cycloneive_lcell_comb \sdram_|Mux7~1 ( // Equation(s): -// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~9_combout ) # (!\sdram_|r.state [7])))) .dataa(\sdram_|Mux23~0_combout ), .datab(\sdram_|Mux13~7_combout ), .datac(\sdram_|r.state [7]), - .datad(\sdram_|Mux10~10_combout ), + .datad(\sdram_|Mux10~9_combout ), .cin(gnd), .combout(\sdram_|Mux7~1_combout ), .cout()); @@ -57649,24 +60670,75 @@ defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N22 +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h3F00; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.wr_pending~q & \sdram_|Mux7~3_combout ))) # (!\sdram_|r.state [6] & (\sdram_|r.state [7] $ (((\sdram_|Mux7~3_combout ))))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux7~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h250A; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.rf_pending~q & (\sdram_|r.state [6] $ (((!\sdram_|Mux7~4_combout ))))) # (!\sdram_|r.rf_pending~q & (!\sdram_|r.state [6] & (!\sdram_|n~4_combout & !\sdram_|Mux7~4_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'h8823; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \sdram_|Mux7~6 ( // Equation(s): -// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|r.state [8] & \sdram_|Mux7~5_combout ))) .dataa(\sdram_|Mux7~2_combout ), - .datab(\sdram_|Mux7~5_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux7~1_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux7~1_combout ), + .datad(\sdram_|Mux7~5_combout ), .cin(gnd), .combout(\sdram_|Mux7~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .lut_mask = 16'hFEFA; defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N23 +// Location: FF_X23_Y19_N3 dffeas \sdram_|r.state[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux7~6_combout ), @@ -57685,14 +60757,938 @@ defparam \sdram_|r.state[5] .is_wysiwyg = "true"; defparam \sdram_|r.state[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N6 +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~32_combout = ((\sdram_|r.address[3]~6_combout & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[8]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~32 .lut_mask = 16'h555D; +defparam \sdram_|r.rf_counter[8]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(\sdram_|r.rf_counter [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [2]) # ((\sdram_|r.rf_counter [0]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [2]), + .datac(\sdram_|r.rf_counter [0]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter [9] $ (\sdram_|r.rf_counter[8]~29 ) + + .dataa(\sdram_|r.rf_counter [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h5A5A; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N23 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [4]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [5]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [5]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~0_combout ) # (((\sdram_|Equal0~1_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~0_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|r.rf_counter [9]), + .datad(\sdram_|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFFBF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|r.address[3]~6_combout )) # (!\sdram_|Mux13~8_combout ))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|Equal0~2_combout )))) + + .dataa(\sdram_|Mux13~8_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h707F; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N25 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (!\sdram_|r.rf_pending~q & (\sdram_|r.rd_pending~q & (\sdram_|Equal7~2_combout & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h0040; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux4~4 ( +// Equation(s): +// \sdram_|Mux4~4_combout = (\sdram_|r.state [8] & (((!\sdram_|Mux4~0_combout & \sdram_|Mux4~1_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|Mux4~1_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux4~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~4 .lut_mask = 16'h5F44; +defparam \sdram_|Mux4~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [5] & (((\sdram_|r.state [6] & !\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [6] $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'h39FE; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux4~5 ( +// Equation(s): +// \sdram_|Mux4~5_combout = (\sdram_|Mux4~2_combout & (((\sdram_|r.state [8])))) # (!\sdram_|Mux4~2_combout & (\sdram_|Mux4~4_combout & ((\sdram_|Mux4~3_combout ) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~3_combout ), + .datab(\sdram_|Mux4~4_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~5 .lut_mask = 16'hF0C8; +defparam \sdram_|Mux4~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = (\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~0 ( +// Equation(s): +// \sdram_|r.act_row[2]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [5] & (\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [6] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \sdram_|r.act_row[2]~1 ( +// Equation(s): +// \sdram_|r.act_row[2]~1_combout = (\sdram_|process_0~4_combout & (\sdram_|r.act_row[2]~0_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.act_row[2]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~1 .lut_mask = 16'h9000; +defparam \sdram_|r.act_row[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N3 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~18_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~18_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~18_combout ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~0_combout & (\sdram_|Equal7~1_combout & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|r.act_row [4]), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h8040; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF88; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (!\sdram_|r.rf_pending~q & (!\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'h0501; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (!\sdram_|r.state [4] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'h0F00; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~4_combout )) # (!\sdram_|Mux9~5_combout ))) # (!\sdram_|r.state [6] & (((!\sdram_|r.rf_pending~q & \sdram_|Mux9~4_combout )))) + + .dataa(\sdram_|Mux9~5_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux9~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h47CC; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hAFF0; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~4_combout & (\sdram_|Mux6~3_combout ))) + + .dataa(\sdram_|Mux6~4_combout ), + .datab(\sdram_|Mux6~3_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hCC00; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [4] & (\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~2_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8C10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|Mux6~0_combout ) # (\sdram_|r.state [6]))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h6628; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFA50; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (\sdram_|r.state [4] & (!\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h00E0; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N28 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rf_pending~q & \sdram_|Mux5~7_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux5~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h4544; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 cycloneive_lcell_comb \sdram_|Mux5~2 ( // Equation(s): -// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [8] & !\sdram_|Mux4~1_combout )))) - .dataa(\sdram_|Mux4~0_combout ), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [8]), + .datac(\sdram_|Mux4~1_combout ), .datad(\sdram_|Mux13~7_combout ), .cin(gnd), .combout(\sdram_|Mux5~2_combout ), @@ -57702,143 +61698,109 @@ defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N18 +// Location: LCCOMB_X18_Y17_N22 cycloneive_lcell_comb \sdram_|Mux5~10 ( // Equation(s): -// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) +// \sdram_|Mux5~10_combout = (\sdram_|r.state [8] & (\sdram_|r.state [6] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6])) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux5~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .lut_mask = 16'h9991; defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N16 +// Location: LCCOMB_X18_Y17_N2 cycloneive_lcell_comb \sdram_|Mux5~3 ( // Equation(s): -// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|Mux4~1_combout & !\sdram_|r.state [6]))) # (!\sdram_|r.state [5]) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux4~0_combout ), - .datad(\sdram_|Mux5~10_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux4~1_combout ), + .datac(\sdram_|Mux5~10_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .lut_mask = 16'hF5F7; defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N30 +// Location: LCCOMB_X18_Y17_N0 cycloneive_lcell_comb \sdram_|Mux5~4 ( // Equation(s): -// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|r.state [4] & \sdram_|Mux5~3_combout )))) - .dataa(\sdram_|Mux5~2_combout ), - .datab(\sdram_|Mux5~3_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux5~2_combout ), + .datad(\sdram_|Mux5~3_combout ), .cin(gnd), .combout(\sdram_|Mux5~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .lut_mask = 16'hC8C0; defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N18 -cycloneive_lcell_comb \sdram_|Mux5~7 ( -// Equation(s): -// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.rd_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux5~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; -defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N4 -cycloneive_lcell_comb \sdram_|Mux5~8 ( -// Equation(s): -// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) - - .dataa(\sdram_|Mux5~7_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux5~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; -defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N26 +// Location: LCCOMB_X20_Y16_N26 cycloneive_lcell_comb \sdram_|Mux5~5 ( // Equation(s): // \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [7]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|Mux5~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .lut_mask = 16'h0D0F; defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N12 +// Location: LCCOMB_X20_Y16_N8 cycloneive_lcell_comb \sdram_|Mux5~6 ( // Equation(s): -// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~4_combout & ((\sdram_|Mux5~5_combout ) # ((\sdram_|process_0~2_combout & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~3_combout ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux5~5_combout ), + .dataa(\sdram_|Mux5~5_combout ), + .datab(\sdram_|Mux9~4_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .lut_mask = 16'h88C8; defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N20 +// Location: LCCOMB_X23_Y19_N10 cycloneive_lcell_comb \sdram_|Mux5~9 ( // Equation(s): // \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|Mux5~4_combout ), - .datac(\sdram_|Mux5~8_combout ), + .dataa(\sdram_|Mux5~8_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux5~4_combout ), .datad(\sdram_|Mux5~6_combout ), .cin(gnd), .combout(\sdram_|Mux5~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .lut_mask = 16'hF3F2; defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N21 +// Location: FF_X23_Y19_N11 dffeas \sdram_|r.state[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux5~9_combout ), @@ -57857,7 +61819,7 @@ defparam \sdram_|r.state[7] .is_wysiwyg = "true"; defparam \sdram_|r.state[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N8 +// Location: LCCOMB_X18_Y17_N16 cycloneive_lcell_comb \sdram_|n~2 ( // Equation(s): // \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) @@ -57874,78 +61836,112 @@ defparam \sdram_|n~2 .lut_mask = 16'hFFFC; defparam \sdram_|n~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Location: LCCOMB_X19_Y19_N10 +cycloneive_lcell_comb \sdram_|Mux8~6 ( // Equation(s): -// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) +// \sdram_|Mux8~6_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), .datad(\sdram_|r.state [4]), .cin(gnd), + .combout(\sdram_|Mux8~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~6 .lut_mask = 16'hB03B; +defparam \sdram_|Mux8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux8~7 ( +// Equation(s): +// \sdram_|Mux8~7_combout = (\sdram_|r.state [8] & (\sdram_|Mux8~6_combout $ ((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|Mux8~6_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|Mux8~6_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~7 .lut_mask = 16'h606E; +defparam \sdram_|Mux8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|r.state [5] $ (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [5]) # (\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7336; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N28 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [6] & (\sdram_|Mux8~1_combout & (!\sdram_|r.state [8]))) # (!\sdram_|r.state [6] & (\sdram_|r.state [8] $ (((!\sdram_|n~2_combout ) # (!\sdram_|Mux8~1_combout ))))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'h490D; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N26 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [6] & ((\sdram_|Mux9~5_combout & ((\sdram_|Mux8~2_combout ))) # (!\sdram_|Mux9~5_combout & (\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|Mux8~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux8~2_combout ), + .cin(gnd), .combout(\sdram_|Mux8~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .lut_mask = 16'hFD08; defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Location: LCCOMB_X19_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~44 ( // Equation(s): -// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux8~3_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux8~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; -defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux9~10 ( -// Equation(s): -// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) - - .dataa(gnd), - .datab(\sdram_|Mux9~9_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux9~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; -defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N28 -cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( -// Equation(s): -// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] +// \sdram_|r.init_counter[0]~44_combout = !\sdram_|r.init_counter [0] .dataa(gnd), .datab(gnd), .datac(\sdram_|r.init_counter [0]), .datad(gnd), .cin(gnd), - .combout(\sdram_|r.init_counter[0]~0_combout ), + .combout(\sdram_|r.init_counter[0]~44_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[0]~44 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y7_N29 +// Location: FF_X19_Y16_N7 dffeas \sdram_|r.init_counter[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[0]~0_combout ), + .d(\sdram_|r.init_counter[0]~44_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57961,45 +61957,45 @@ defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N2 -cycloneive_lcell_comb \sdram_|Add1~1 ( +// Location: LCCOMB_X18_Y16_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~15 ( // Equation(s): -// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) +// \sdram_|r.init_counter[1]~15_cout = CARRY(\sdram_|r.init_counter [0]) - .dataa(gnd), - .datab(\sdram_|r.init_counter [0]), + .dataa(\sdram_|r.init_counter [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), - .cout(\sdram_|Add1~1_cout )); + .cout(\sdram_|r.init_counter[1]~15_cout )); // synopsys translate_off -defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; -defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[1]~15 .lut_mask = 16'h00AA; +defparam \sdram_|r.init_counter[1]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N4 -cycloneive_lcell_comb \sdram_|Add1~2 ( +// Location: LCCOMB_X18_Y16_N4 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~16 ( // Equation(s): -// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) -// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) +// \sdram_|r.init_counter[1]~16_combout = (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter[1]~15_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter[1]~15_cout )) +// \sdram_|r.init_counter[1]~17 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|r.init_counter[1]~15_cout )) .dataa(gnd), .datab(\sdram_|r.init_counter [1]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~1_cout ), - .combout(\sdram_|Add1~2_combout ), - .cout(\sdram_|Add1~3 )); + .cin(\sdram_|r.init_counter[1]~15_cout ), + .combout(\sdram_|r.init_counter[1]~16_combout ), + .cout(\sdram_|r.init_counter[1]~17 )); // synopsys translate_off -defparam \sdram_|Add1~2 .lut_mask = 16'hC303; -defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[1]~16 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[1]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N5 +// Location: FF_X18_Y16_N5 dffeas \sdram_|r.init_counter[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~2_combout ), + .d(\sdram_|r.init_counter[1]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58015,28 +62011,28 @@ defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N6 -cycloneive_lcell_comb \sdram_|Add1~4 ( +// Location: LCCOMB_X18_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[2]~18 ( // Equation(s): -// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) -// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) +// \sdram_|r.init_counter[2]~18_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|r.init_counter[1]~17 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter[1]~17 $ (GND))) +// \sdram_|r.init_counter[2]~19 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|r.init_counter[1]~17 )) .dataa(\sdram_|r.init_counter [2]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~3 ), - .combout(\sdram_|Add1~4_combout ), - .cout(\sdram_|Add1~5 )); + .cin(\sdram_|r.init_counter[1]~17 ), + .combout(\sdram_|r.init_counter[2]~18_combout ), + .cout(\sdram_|r.init_counter[2]~19 )); // synopsys translate_off -defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[2]~18 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[2]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N7 +// Location: FF_X18_Y16_N7 dffeas \sdram_|r.init_counter[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~4_combout ), + .d(\sdram_|r.init_counter[2]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58052,45 +62048,28 @@ defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N8 -cycloneive_lcell_comb \sdram_|Add1~6 ( +// Location: LCCOMB_X18_Y16_N8 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~20 ( // Equation(s): -// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) -// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) - - .dataa(\sdram_|r.init_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|Add1~5 ), - .combout(\sdram_|Add1~6_combout ), - .cout(\sdram_|Add1~7 )); -// synopsys translate_off -defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; -defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N2 -cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( -// Equation(s): -// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout +// \sdram_|r.init_counter[3]~20_combout = (\sdram_|r.init_counter [3] & (\sdram_|r.init_counter[2]~19 & VCC)) # (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter[2]~19 )) +// \sdram_|r.init_counter[3]~21 = CARRY((!\sdram_|r.init_counter [3] & !\sdram_|r.init_counter[2]~19 )) .dataa(gnd), - .datab(gnd), - .datac(\sdram_|Add1~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.init_counter[3]~1_combout ), - .cout()); + .datab(\sdram_|r.init_counter [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.init_counter[2]~19 ), + .combout(\sdram_|r.init_counter[3]~20_combout ), + .cout(\sdram_|r.init_counter[3]~21 )); // synopsys translate_off -defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[3]~20 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[3]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X20_Y3_N3 +// Location: FF_X18_Y16_N9 dffeas \sdram_|r.init_counter[3] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[3]~1_combout ), + .d(\sdram_|r.init_counter[3]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58106,28 +62085,28 @@ defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N10 -cycloneive_lcell_comb \sdram_|Add1~8 ( +// Location: LCCOMB_X18_Y16_N10 +cycloneive_lcell_comb \sdram_|r.init_counter[4]~22 ( // Equation(s): -// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) -// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) +// \sdram_|r.init_counter[4]~22_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|r.init_counter[3]~21 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|r.init_counter[3]~21 $ (GND))) +// \sdram_|r.init_counter[4]~23 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|r.init_counter[3]~21 )) .dataa(\sdram_|r.init_counter [4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~7 ), - .combout(\sdram_|Add1~8_combout ), - .cout(\sdram_|Add1~9 )); + .cin(\sdram_|r.init_counter[3]~21 ), + .combout(\sdram_|r.init_counter[4]~22_combout ), + .cout(\sdram_|r.init_counter[4]~23 )); // synopsys translate_off -defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[4]~22 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[4]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N11 +// Location: FF_X18_Y16_N11 dffeas \sdram_|r.init_counter[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~8_combout ), + .d(\sdram_|r.init_counter[4]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58143,28 +62122,28 @@ defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N12 -cycloneive_lcell_comb \sdram_|Add1~10 ( +// Location: LCCOMB_X18_Y16_N12 +cycloneive_lcell_comb \sdram_|r.init_counter[5]~24 ( // Equation(s): -// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) -// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) +// \sdram_|r.init_counter[5]~24_combout = (\sdram_|r.init_counter [5] & (\sdram_|r.init_counter[4]~23 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|r.init_counter[4]~23 )) +// \sdram_|r.init_counter[5]~25 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|r.init_counter[4]~23 )) .dataa(\sdram_|r.init_counter [5]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~9 ), - .combout(\sdram_|Add1~10_combout ), - .cout(\sdram_|Add1~11 )); + .cin(\sdram_|r.init_counter[4]~23 ), + .combout(\sdram_|r.init_counter[5]~24_combout ), + .cout(\sdram_|r.init_counter[5]~25 )); // synopsys translate_off -defparam \sdram_|Add1~10 .lut_mask = 16'hA505; -defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[5]~24 .lut_mask = 16'hA505; +defparam \sdram_|r.init_counter[5]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N13 +// Location: FF_X18_Y16_N13 dffeas \sdram_|r.init_counter[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~10_combout ), + .d(\sdram_|r.init_counter[5]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58180,28 +62159,28 @@ defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N14 -cycloneive_lcell_comb \sdram_|Add1~12 ( +// Location: LCCOMB_X18_Y16_N14 +cycloneive_lcell_comb \sdram_|r.init_counter[6]~26 ( // Equation(s): -// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) -// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) +// \sdram_|r.init_counter[6]~26_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|r.init_counter[5]~25 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|r.init_counter[5]~25 $ (GND))) +// \sdram_|r.init_counter[6]~27 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|r.init_counter[5]~25 )) .dataa(gnd), .datab(\sdram_|r.init_counter [6]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~11 ), - .combout(\sdram_|Add1~12_combout ), - .cout(\sdram_|Add1~13 )); + .cin(\sdram_|r.init_counter[5]~25 ), + .combout(\sdram_|r.init_counter[6]~26_combout ), + .cout(\sdram_|r.init_counter[6]~27 )); // synopsys translate_off -defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[6]~26 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[6]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N15 +// Location: FF_X18_Y16_N15 dffeas \sdram_|r.init_counter[6] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~12_combout ), + .d(\sdram_|r.init_counter[6]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58217,28 +62196,28 @@ defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N16 -cycloneive_lcell_comb \sdram_|Add1~14 ( +// Location: LCCOMB_X18_Y16_N16 +cycloneive_lcell_comb \sdram_|r.init_counter[7]~28 ( // Equation(s): -// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) -// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) +// \sdram_|r.init_counter[7]~28_combout = (\sdram_|r.init_counter [7] & (\sdram_|r.init_counter[6]~27 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|r.init_counter[6]~27 )) +// \sdram_|r.init_counter[7]~29 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|r.init_counter[6]~27 )) .dataa(gnd), .datab(\sdram_|r.init_counter [7]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~13 ), - .combout(\sdram_|Add1~14_combout ), - .cout(\sdram_|Add1~15 )); + .cin(\sdram_|r.init_counter[6]~27 ), + .combout(\sdram_|r.init_counter[7]~28_combout ), + .cout(\sdram_|r.init_counter[7]~29 )); // synopsys translate_off -defparam \sdram_|Add1~14 .lut_mask = 16'hC303; -defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[7]~28 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[7]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N17 +// Location: FF_X18_Y16_N17 dffeas \sdram_|r.init_counter[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~14_combout ), + .d(\sdram_|r.init_counter[7]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58254,28 +62233,28 @@ defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N18 -cycloneive_lcell_comb \sdram_|Add1~16 ( +// Location: LCCOMB_X18_Y16_N18 +cycloneive_lcell_comb \sdram_|r.init_counter[8]~30 ( // Equation(s): -// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) -// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) +// \sdram_|r.init_counter[8]~30_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|r.init_counter[7]~29 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|r.init_counter[7]~29 $ (GND))) +// \sdram_|r.init_counter[8]~31 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|r.init_counter[7]~29 )) .dataa(gnd), .datab(\sdram_|r.init_counter [8]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~15 ), - .combout(\sdram_|Add1~16_combout ), - .cout(\sdram_|Add1~17 )); + .cin(\sdram_|r.init_counter[7]~29 ), + .combout(\sdram_|r.init_counter[8]~30_combout ), + .cout(\sdram_|r.init_counter[8]~31 )); // synopsys translate_off -defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[8]~30 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[8]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N19 +// Location: FF_X18_Y16_N19 dffeas \sdram_|r.init_counter[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~16_combout ), + .d(\sdram_|r.init_counter[8]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58291,28 +62270,28 @@ defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N20 -cycloneive_lcell_comb \sdram_|Add1~18 ( +// Location: LCCOMB_X18_Y16_N20 +cycloneive_lcell_comb \sdram_|r.init_counter[9]~32 ( // Equation(s): -// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) -// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) +// \sdram_|r.init_counter[9]~32_combout = (\sdram_|r.init_counter [9] & (\sdram_|r.init_counter[8]~31 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter[8]~31 )) +// \sdram_|r.init_counter[9]~33 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|r.init_counter[8]~31 )) .dataa(gnd), .datab(\sdram_|r.init_counter [9]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~17 ), - .combout(\sdram_|Add1~18_combout ), - .cout(\sdram_|Add1~19 )); + .cin(\sdram_|r.init_counter[8]~31 ), + .combout(\sdram_|r.init_counter[9]~32_combout ), + .cout(\sdram_|r.init_counter[9]~33 )); // synopsys translate_off -defparam \sdram_|Add1~18 .lut_mask = 16'hC303; -defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[9]~32 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[9]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N21 +// Location: FF_X18_Y16_N21 dffeas \sdram_|r.init_counter[9] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~18_combout ), + .d(\sdram_|r.init_counter[9]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58328,28 +62307,28 @@ defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N22 -cycloneive_lcell_comb \sdram_|Add1~20 ( +// Location: LCCOMB_X18_Y16_N22 +cycloneive_lcell_comb \sdram_|r.init_counter[10]~34 ( // Equation(s): -// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) -// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) +// \sdram_|r.init_counter[10]~34_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|r.init_counter[9]~33 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|r.init_counter[9]~33 $ (GND))) +// \sdram_|r.init_counter[10]~35 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|r.init_counter[9]~33 )) .dataa(\sdram_|r.init_counter [10]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~19 ), - .combout(\sdram_|Add1~20_combout ), - .cout(\sdram_|Add1~21 )); + .cin(\sdram_|r.init_counter[9]~33 ), + .combout(\sdram_|r.init_counter[10]~34_combout ), + .cout(\sdram_|r.init_counter[10]~35 )); // synopsys translate_off -defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[10]~34 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[10]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N23 +// Location: FF_X18_Y16_N23 dffeas \sdram_|r.init_counter[10] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~20_combout ), + .d(\sdram_|r.init_counter[10]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58365,62 +62344,28 @@ defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N22 -cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Location: LCCOMB_X18_Y16_N24 +cycloneive_lcell_comb \sdram_|r.init_counter[11]~36 ( // Equation(s): -// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|r.init_counter [4]), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; -defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N0 -cycloneive_lcell_comb \sdram_|Equal2~1 ( -// Equation(s): -// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [3]), - .cin(gnd), - .combout(\sdram_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; -defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y3_N24 -cycloneive_lcell_comb \sdram_|Add1~22 ( -// Equation(s): -// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) -// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) +// \sdram_|r.init_counter[11]~36_combout = (\sdram_|r.init_counter [11] & (\sdram_|r.init_counter[10]~35 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter[10]~35 )) +// \sdram_|r.init_counter[11]~37 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|r.init_counter[10]~35 )) .dataa(gnd), .datab(\sdram_|r.init_counter [11]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~21 ), - .combout(\sdram_|Add1~22_combout ), - .cout(\sdram_|Add1~23 )); + .cin(\sdram_|r.init_counter[10]~35 ), + .combout(\sdram_|r.init_counter[11]~36_combout ), + .cout(\sdram_|r.init_counter[11]~37 )); // synopsys translate_off -defparam \sdram_|Add1~22 .lut_mask = 16'hC303; -defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[11]~36 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[11]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N25 +// Location: FF_X18_Y16_N25 dffeas \sdram_|r.init_counter[11] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~22_combout ), + .d(\sdram_|r.init_counter[11]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58436,28 +62381,28 @@ defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N26 -cycloneive_lcell_comb \sdram_|Add1~24 ( +// Location: LCCOMB_X18_Y16_N26 +cycloneive_lcell_comb \sdram_|r.init_counter[12]~38 ( // Equation(s): -// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) -// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) +// \sdram_|r.init_counter[12]~38_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|r.init_counter[11]~37 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|r.init_counter[11]~37 $ (GND))) +// \sdram_|r.init_counter[12]~39 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|r.init_counter[11]~37 )) .dataa(\sdram_|r.init_counter [12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~23 ), - .combout(\sdram_|Add1~24_combout ), - .cout(\sdram_|Add1~25 )); + .cin(\sdram_|r.init_counter[11]~37 ), + .combout(\sdram_|r.init_counter[12]~38_combout ), + .cout(\sdram_|r.init_counter[12]~39 )); // synopsys translate_off -defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[12]~38 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[12]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N27 +// Location: FF_X18_Y16_N27 dffeas \sdram_|r.init_counter[12] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~24_combout ), + .d(\sdram_|r.init_counter[12]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58473,28 +62418,28 @@ defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N28 -cycloneive_lcell_comb \sdram_|Add1~26 ( +// Location: LCCOMB_X18_Y16_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[13]~40 ( // Equation(s): -// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) -// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) +// \sdram_|r.init_counter[13]~40_combout = (\sdram_|r.init_counter [13] & (\sdram_|r.init_counter[12]~39 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter[12]~39 )) +// \sdram_|r.init_counter[13]~41 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|r.init_counter[12]~39 )) .dataa(gnd), .datab(\sdram_|r.init_counter [13]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~25 ), - .combout(\sdram_|Add1~26_combout ), - .cout(\sdram_|Add1~27 )); + .cin(\sdram_|r.init_counter[12]~39 ), + .combout(\sdram_|r.init_counter[13]~40_combout ), + .cout(\sdram_|r.init_counter[13]~41 )); // synopsys translate_off -defparam \sdram_|Add1~26 .lut_mask = 16'hC303; -defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[13]~40 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[13]~40 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N29 +// Location: FF_X18_Y16_N29 dffeas \sdram_|r.init_counter[13] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~26_combout ), + .d(\sdram_|r.init_counter[13]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58510,27 +62455,27 @@ defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N30 -cycloneive_lcell_comb \sdram_|Add1~28 ( +// Location: LCCOMB_X18_Y16_N30 +cycloneive_lcell_comb \sdram_|r.init_counter[14]~42 ( // Equation(s): -// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) +// \sdram_|r.init_counter[14]~42_combout = \sdram_|r.init_counter [14] $ (\sdram_|r.init_counter[13]~41 ) .dataa(\sdram_|r.init_counter [14]), .datab(gnd), .datac(gnd), .datad(gnd), - .cin(\sdram_|Add1~27 ), - .combout(\sdram_|Add1~28_combout ), + .cin(\sdram_|r.init_counter[13]~41 ), + .combout(\sdram_|r.init_counter[14]~42_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; -defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[14]~42 .lut_mask = 16'h5A5A; +defparam \sdram_|r.init_counter[14]~42 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N31 +// Location: FF_X18_Y16_N31 dffeas \sdram_|r.init_counter[14] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~28_combout ), + .d(\sdram_|r.init_counter[14]~42_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58546,15 +62491,32 @@ defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N0 +// Location: LCCOMB_X19_Y16_N2 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0003; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y16_N0 cycloneive_lcell_comb \sdram_|process_0~5 ( // Equation(s): -// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [10] & !\sdram_|r.init_counter [9]))) - .dataa(\sdram_|r.init_counter [14]), + .dataa(\sdram_|r.init_counter [8]), .datab(\sdram_|r.init_counter [11]), - .datac(\sdram_|r.init_counter [12]), - .datad(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [10]), + .datad(\sdram_|r.init_counter [9]), .cin(gnd), .combout(\sdram_|process_0~5_combout ), .cout()); @@ -58563,129 +62525,95 @@ defparam \sdram_|process_0~5 .lut_mask = 16'h0001; defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N6 +// Location: LCCOMB_X19_Y16_N10 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter [4] & (!\sdram_|r.init_counter [2] & !\sdram_|r.init_counter [5]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|r.init_counter [4]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [5]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N0 cycloneive_lcell_comb \sdram_|Equal2~2 ( // Equation(s): -// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) +// \sdram_|Equal2~2_combout = (!\sdram_|r.init_counter [6] & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & \sdram_|Equal2~0_combout ))) - .dataa(\sdram_|Equal2~0_combout ), + .dataa(\sdram_|r.init_counter [6]), .datab(\sdram_|Equal2~1_combout ), .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [2]), + .datad(\sdram_|Equal2~0_combout ), .cin(gnd), .combout(\sdram_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .lut_mask = 16'h4000; defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~11 ( -// Equation(s): -// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(gnd), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Mux9~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; -defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux9~12 ( -// Equation(s): -// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) - - .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux9~11_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; -defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N0 -cycloneive_lcell_comb \sdram_|Mux9~13 ( -// Equation(s): -// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|n~2_combout ), - .datad(\sdram_|Mux9~12_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; -defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N2 +// Location: LCCOMB_X19_Y16_N4 cycloneive_lcell_comb \sdram_|Mux8~0 ( // Equation(s): -// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) +// \sdram_|Mux8~0_combout = (\sdram_|r.init_counter [0] & (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux9~10_combout ), - .datad(\sdram_|Mux9~13_combout ), + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), .cin(gnd), .combout(\sdram_|Mux8~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .lut_mask = 16'h0200; defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N16 -cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Location: LCCOMB_X19_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux8~4 ( // Equation(s): -// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) +// \sdram_|Mux8~4_combout = (\sdram_|r.state [5] & (((\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux8~3_combout & ((\sdram_|Mux8~1_combout ) # (\sdram_|Mux8~0_combout )))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), + .dataa(\sdram_|Mux8~3_combout ), + .datab(\sdram_|Mux8~1_combout ), .datac(\sdram_|r.state [5]), .datad(\sdram_|Mux8~0_combout ), .cin(gnd), - .combout(\sdram_|Mux8~1_combout ), + .combout(\sdram_|Mux8~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; -defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~4 .lut_mask = 16'hCAC8; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux8~5 ( // Equation(s): -// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) +// \sdram_|Mux8~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~7_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~4_combout ))) .dataa(\sdram_|r.state [7]), .datab(gnd), - .datac(\sdram_|Mux8~4_combout ), - .datad(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux8~7_combout ), + .datad(\sdram_|Mux8~4_combout ), .cin(gnd), - .combout(\sdram_|Mux8~2_combout ), + .combout(\sdram_|Mux8~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; -defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~5 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y15_N21 +// Location: FF_X23_Y19_N5 dffeas \sdram_|r.state[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux8~2_combout ), + .d(\sdram_|Mux8~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58701,49 +62629,49 @@ defparam \sdram_|r.state[4] .is_wysiwyg = "true"; defparam \sdram_|r.state[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 +// Location: LCCOMB_X23_Y19_N18 cycloneive_lcell_comb \sdram_|Mux72~0 ( // Equation(s): -// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux72~0_combout = (\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [0]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux72~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 +// Location: LCCOMB_X23_Y19_N20 cycloneive_lcell_comb \sdram_|Mux72~1 ( // Equation(s): -// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux72~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux72~0_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|r.state [4]), .datac(\sdram_|Mux72~0_combout ), - .datad(\D[0]~64_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), .combout(\sdram_|Mux72~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .lut_mask = 16'hC040; defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N0 +// Location: LCCOMB_X23_Y19_N6 cycloneive_lcell_comb \sdram_|Mux84~0 ( // Equation(s): -// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) +// \sdram_|Mux84~0_combout = (\sdram_|r.state [4]) # (\sdram_|r.state [5]) .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux84~0_combout ), .cout()); @@ -58752,245 +62680,245 @@ defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N2 +// Location: LCCOMB_X23_Y19_N28 cycloneive_lcell_comb \sdram_|Mux84~1 ( // Equation(s): -// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) +// \sdram_|Mux84~1_combout = (\sdram_|r.state [7] & (!\sdram_|r.state [8] & (\sdram_|r.state [6] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [6] & !\sdram_|Mux84~0_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|Mux84~0_combout ), .cin(gnd), .combout(\sdram_|Mux84~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .lut_mask = 16'h2004; defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 +// Location: LCCOMB_X23_Y19_N26 cycloneive_lcell_comb \sdram_|Mux3~0 ( // Equation(s): -// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux3~0_combout = (\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|data_pins_|dout [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), .combout(\sdram_|Mux3~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .lut_mask = 16'hAAFF; defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 +// Location: LCCOMB_X23_Y19_N8 cycloneive_lcell_comb \sdram_|Mux3~1 ( // Equation(s): -// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & (\sdram_|r.state [4] & ((\Selector12~11_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux3~0_combout ), - .datad(\D[1]~40_combout ), + .dataa(\sdram_|Mux3~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector12~11_combout ), .cin(gnd), .combout(\sdram_|Mux3~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .lut_mask = 16'h8808; defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 +// Location: LCCOMB_X27_Y19_N8 cycloneive_lcell_comb \sdram_|Mux2~0 ( // Equation(s): -// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux2~0_combout = (\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [2]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 +// Location: LCCOMB_X23_Y19_N30 cycloneive_lcell_comb \sdram_|Mux2~1 ( // Equation(s): -// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & (\sdram_|r.state [4] & ((\Selector10~3_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux2~0_combout ), - .datad(\D[2]~52_combout ), + .dataa(\sdram_|Mux2~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Selector10~3_combout ), + .datad(\Equal5~1_combout ), .cin(gnd), .combout(\sdram_|Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .lut_mask = 16'h8088; defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y16_N6 cycloneive_lcell_comb \sdram_|Mux1~0 ( // Equation(s): -// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux1~0_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\sdram_|Mux1~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N10 +// Location: LCCOMB_X24_Y15_N4 cycloneive_lcell_comb \sdram_|Mux1~1 ( // Equation(s): -// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux1~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux1~0_combout & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[3]~108_combout ), - .datad(\sdram_|Mux1~0_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|Mux1~0_combout ), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), .cin(gnd), .combout(\sdram_|Mux1~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .lut_mask = 16'h8808; defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N12 +// Location: LCCOMB_X25_Y16_N8 cycloneive_lcell_comb \sdram_|Mux0~0 ( // Equation(s): -// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux0~0_combout = (\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [4]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [4]), .cin(gnd), .combout(\sdram_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 +// Location: LCCOMB_X23_Y19_N12 cycloneive_lcell_comb \sdram_|Mux0~1 ( // Equation(s): -// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & (\sdram_|r.state [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux0~0_combout ), - .datad(\D[4]~110_combout ), + .dataa(\sdram_|Mux0~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), .combout(\sdram_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .lut_mask = 16'h8808; defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 +// Location: LCCOMB_X29_Y19_N4 cycloneive_lcell_comb \sdram_|Mux73~0 ( // Equation(s): -// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\D[5]~27_combout ) # (!\D[0]~49_combout ))) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[5]~27_combout ), .cin(gnd), .combout(\sdram_|Mux73~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .lut_mask = 16'hF030; defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux73~1 ( -// Equation(s): -// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux73~0_combout ), - .datad(\D[5]~112_combout ), - .cin(gnd), - .combout(\sdram_|Mux73~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; -defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N24 +// Location: LCCOMB_X26_Y16_N10 cycloneive_lcell_comb \sdram_|Mux74~0 ( // Equation(s): -// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux74~0_combout = (\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [6]), .cin(gnd), .combout(\sdram_|Mux74~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N6 +// Location: LCCOMB_X23_Y19_N14 cycloneive_lcell_comb \sdram_|Mux74~1 ( // Equation(s): -// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & (\sdram_|r.state [4] & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), + .dataa(\Equal5~1_combout ), .datab(\sdram_|Mux74~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~114_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[6]~46_combout ), .cin(gnd), .combout(\sdram_|Mux74~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .lut_mask = 16'hC040; defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X17_Y4_N28 +// Location: LCCOMB_X24_Y16_N8 cycloneive_lcell_comb \sdram_|Mux75~0 ( // Equation(s): -// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & ((\D[7]~37_combout ) # (!\D[0]~49_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\D[7]~117_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), .cin(gnd), .combout(\sdram_|Mux75~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .lut_mask = 16'hAA22; defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N8 +// Location: LCCOMB_X1_Y10_N16 +cycloneive_lcell_comb \LED~0 ( +// Equation(s): +// \LED~0_combout = (!\kempston[4]~input_o & \kempston_auto_fire~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\kempston[4]~input_o ), + .datad(\kempston_auto_fire~q ), + .cin(gnd), + .combout(\LED~0_combout ), + .cout()); +// synopsys translate_off +defparam \LED~0 .lut_mask = 16'h0F00; +defparam \LED~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -59007,7 +62935,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N9 +// Location: FF_X21_Y33_N13 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -59045,24 +62973,43 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N12 +// Location: FF_X24_Y19_N13 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N14 +// Location: LCCOMB_X25_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -59080,24 +63027,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N0 +// Location: LCCOMB_X25_Y30_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N1 +// Location: FF_X25_Y30_N29 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -59116,42 +63063,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N16 +// Location: LCCOMB_X25_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N6 +// Location: LCCOMB_X26_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N7 +// Location: FF_X26_Y30_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -59170,25 +63117,25 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N18 +// Location: LCCOMB_X25_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(\ula_|i2s_intf_|lrdivider [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N30 +// Location: LCCOMB_X26_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout @@ -59205,7 +63152,7 @@ defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N31 +// Location: FF_X26_Y30_N9 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -59224,7 +63171,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N20 +// Location: LCCOMB_X25_Y30_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -59242,24 +63189,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N4 +// Location: LCCOMB_X25_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~8_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N5 +// Location: FF_X25_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -59278,7 +63225,7 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N22 +// Location: LCCOMB_X25_Y30_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) @@ -59296,24 +63243,24 @@ defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N4 +// Location: LCCOMB_X26_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~10_combout ), + .datac(\ula_|i2s_intf_|Add0~10_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N5 +// Location: FF_X26_Y30_N7 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -59332,24 +63279,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N10 +// Location: LCCOMB_X25_Y30_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|lrdivider [4] & \ula_|i2s_intf_|lrdivider [2]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(\ula_|i2s_intf_|lrdivider [3]), - .datad(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(\ula_|i2s_intf_|lrdivider [4]), + .datad(\ula_|i2s_intf_|lrdivider [2]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N24 +// Location: LCCOMB_X25_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -59367,7 +63314,7 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N22 +// Location: LCCOMB_X26_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -59384,7 +63331,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N23 +// Location: FF_X26_Y30_N13 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -59403,42 +63350,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N26 +// Location: LCCOMB_X25_Y30_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N20 +// Location: LCCOMB_X26_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N21 +// Location: FF_X26_Y30_N11 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -59457,7 +63404,7 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N28 +// Location: LCCOMB_X25_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) @@ -59475,24 +63422,24 @@ defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N8 +// Location: LCCOMB_X25_Y30_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~16_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N9 +// Location: FF_X25_Y30_N1 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -59511,7 +63458,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N30 +// Location: LCCOMB_X25_Y30_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -59528,24 +63475,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X19_Y31_N24 +// Location: LCCOMB_X26_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~18_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y31_N25 +// Location: FF_X26_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -59564,73 +63511,54 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N6 +// Location: LCCOMB_X25_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [6] & !\ula_|i2s_intf_|lrdivider [8]))) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [8]), - .datad(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [9]), + .datab(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [8]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N2 +// Location: LCCOMB_X25_Y30_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|Equal0~0_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & !\ula_|i2s_intf_|lrdivider [1]))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|Equal0~0_combout ), - .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|lrdivider [1]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 +// Location: LCCOMB_X24_Y19_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q $ (\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(gnd), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59672,43 +63600,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 +// Location: LCCOMB_X24_Y23_N14 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -59726,303 +63618,50 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N25 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N17 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N19 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N21 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N23 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(\ula_|i2s_intf_|bitcount [0]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; -defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 +// Location: LCCOMB_X24_Y19_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): // \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add2~7_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N20 +// Location: LCCOMB_X24_Y19_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( // Equation(s): // \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) // \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~7_cout ), .combout(\ula_|i2s_intf_|Add2~8_combout ), .cout(\ula_|i2s_intf_|Add2~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N4 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( // Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|bdivider [0]) # (!\ula_|i2s_intf_|Equal1~0_combout )))) - .dataa(\ula_|i2s_intf_|bdivider [0]), + .dataa(\ula_|i2s_intf_|Equal1~0_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|Add2~8_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~20_combout ), .cout()); @@ -60031,7 +63670,7 @@ defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N5 +// Location: FF_X24_Y19_N31 dffeas \ula_|i2s_intf_|bdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~20_combout ), @@ -60050,7 +63689,7 @@ defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N22 +// Location: LCCOMB_X24_Y19_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( // Equation(s): // \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) @@ -60068,24 +63707,24 @@ defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N16 +// Location: LCCOMB_X24_Y23_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( // Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~10_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~10_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~10_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N17 +// Location: FF_X24_Y23_N31 dffeas \ula_|i2s_intf_|bdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~17_combout ), @@ -60104,42 +63743,42 @@ defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N24 +// Location: LCCOMB_X24_Y19_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( // Equation(s): // \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) // \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~11 ), .combout(\ula_|i2s_intf_|Add2~12_combout ), .cout(\ula_|i2s_intf_|Add2~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N14 +// Location: LCCOMB_X24_Y23_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( // Equation(s): // \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Add2~12_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Add2~12_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h0222; defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N15 +// Location: FF_X24_Y23_N1 dffeas \ula_|i2s_intf_|bdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~19_combout ), @@ -60158,7 +63797,7 @@ defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N26 +// Location: LCCOMB_X24_Y19_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( // Equation(s): // \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) @@ -60175,24 +63814,24 @@ defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N6 +// Location: LCCOMB_X24_Y23_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( // Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~14_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~14_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~14_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N7 +// Location: FF_X24_Y23_N25 dffeas \ula_|i2s_intf_|bdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~16_combout ), @@ -60211,78 +63850,333 @@ defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N2 +// Location: LCCOMB_X24_Y19_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & (!\ula_|i2s_intf_|bdivider [1] & \ula_|i2s_intf_|bdivider [4]))) - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(\ula_|i2s_intf_|bdivider [1]), + .datad(\ula_|i2s_intf_|bdivider [4]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0400; defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N28 +// Location: LCCOMB_X24_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (((!\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~0_combout )) # (!\ula_|i2s_intf_|bdivider [0]))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1303; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N27 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hAA00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) +// Location: FF_X24_Y23_N29 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), +// Location: LCCOMB_X24_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~9_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~9 .lut_mask = 16'hCCEC; +defparam \ula_|i2s_intf_|bitcount[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~10 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~10_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~11 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~10 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~12 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~12_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~11 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~11 )) +// \ula_|i2s_intf_|bitcount[3]~13 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~11 ), + .combout(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~14 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~14_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~13 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~13 ), + .combout(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~14 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [2]), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~1 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~1_combout = (\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]) + + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~1 .lut_mask = 16'hFF0F; +defparam \ula_|i2s_intf_|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~1_combout ))))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h0078; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -60298,15 +64192,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N16 +// Location: LCCOMB_X23_Y18_N26 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~38_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~109_combout ), + .datad(\D[3]~38_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -60315,41 +64209,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N30 +// Location: LCCOMB_X23_Y17_N0 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) +// \ula_|always0~2_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h00C0; +defparam \ula_|always0~2 .lut_mask = 16'h2020; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N2 +// Location: LCCOMB_X23_Y17_N24 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h0200; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N17 +// Location: FF_X23_Y18_N27 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -60368,538 +64262,25 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N7 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; -defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N29 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N15 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N17 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N23 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N13 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N19 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N9 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [7]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N3 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N5 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N11 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [10]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N1 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N27 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 +// Location: LCCOMB_X24_Y19_N26 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hD8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N11 +// Location: FF_X24_Y19_N27 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -60918,25 +64299,25 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N12 +// Location: LCCOMB_X24_Y19_N20 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INL [14])))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # +// (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INL [14]))))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hE4F0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N13 +// Location: FF_X24_Y19_N21 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -60955,24 +64336,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N0 +// Location: LCCOMB_X24_Y19_N14 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N1 +// Location: FF_X24_Y19_N15 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -60991,25 +64372,502 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N20 +// Location: LCCOMB_X24_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~18_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~18 .lut_mask = 16'h008C; +defparam \ula_|i2s_intf_|shiftreg[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|shiftreg[0]~18_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~18_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[7]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[7]~1_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7]~1 .lut_mask = 16'hECCC; +defparam \ula_|i2s_intf_|shiftreg[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N7 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [6]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [8]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [9]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [9]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [10]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|shiftreg [12]), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|pcm_outl [12]), + .datac(\ula_|i2s_intf_|shiftreg [11]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N21 -dffeas \ula_|i2s_intf_|shiftreg[13] ( +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), .asdata(vcc), @@ -61017,7 +64875,43 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [12])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [12]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|pcm_outl [12]), + .datad(\ula_|i2s_intf_|shiftreg [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hF3C0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -61027,33 +64921,33 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|pcm_outl [13]), .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF5A0; +defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N31 +// Location: FF_X24_Y21_N13 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .d(\ula_|i2s_intf_|shiftreg~4_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -61063,32 +64957,15 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N22 -cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( -// Equation(s): -// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[4]~111_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y19_N23 +// Location: FF_X25_Y19_N13 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[14]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[4]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -61099,33 +64976,33 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( +// Location: LCCOMB_X24_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [14]), .datad(\ula_|pcm_outl [14]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~4_combout ), + .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; -defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N25 +// Location: FF_X24_Y22_N21 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~4_combout ), + .d(\ula_|i2s_intf_|shiftreg~3_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -61135,33 +65012,33 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~3_combout ), + .combout(\ula_|i2s_intf_|shiftreg~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; -defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~2 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y33_N1 +// Location: FF_X24_Y30_N17 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~3_combout ), + .d(\ula_|i2s_intf_|shiftreg~2_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -61171,7 +65048,7 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N14 +// Location: LCCOMB_X24_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) @@ -61197,7 +65074,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -61207,1083 +65084,41 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y18_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( -// Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~41_combout ), - .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y18_N13 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N28 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N14 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N6 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N24 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N0 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N1 -dffeas \ula_|video_|attr_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N7 -dffeas \ula_|video_|attr[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( -// Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - - .dataa(gnd), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(gnd), - .datad(\ula_|video_|frame [0]), - .cin(gnd), - .combout(\ula_|video_|frame[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; -defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|frame[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( -// Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|frame[1]~4_combout ), - .cout(\ula_|video_|frame[1]~5 )); -// synopsys translate_off -defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; -defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|frame[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[1]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( -// Equation(s): -// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) -// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - - .dataa(gnd), - .datab(\ula_|video_|frame [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[1]~5 ), - .combout(\ula_|video_|frame[2]~6_combout ), - .cout(\ula_|video_|frame[2]~7 )); -// synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|frame[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[2]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( -// Equation(s): -// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) -// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - - .dataa(gnd), - .datab(\ula_|video_|frame [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[2]~7 ), - .combout(\ula_|video_|frame[3]~8_combout ), - .cout(\ula_|video_|frame[3]~9 )); -// synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|frame[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[3]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( -// Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|frame [4]), - .cin(\ula_|video_|frame[3]~9 ), - .combout(\ula_|video_|frame[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; -defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|frame[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N6 -cycloneive_lcell_comb \ula_|video_|inverted ( -// Equation(s): -// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|attr [7]), - .datad(\ula_|video_|frame [4]), - .cin(gnd), - .combout(\ula_|video_|inverted~combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|inverted .lut_mask = 16'hF000; -defparam \ula_|video_|inverted .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N29 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N5 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N26 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N27 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N29 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N14 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N15 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N24 -cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( -// Equation(s): -// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [5]), - .cin(gnd), - .combout(\ula_|video_|bits[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N12 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N13 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N20 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N21 -dffeas \ula_|video_|bits_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N14 -cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( -// Equation(s): -// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [2]), - .cin(gnd), - .combout(\ula_|video_|bits[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N15 -dffeas \ula_|video_|bits[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N18 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N19 -dffeas \ula_|video_|bits_prefetch[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N1 -dffeas \ula_|video_|bits[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N6 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N7 -dffeas \ula_|video_|bits_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N20 -cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( -// Equation(s): -// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|bits[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N21 -dffeas \ula_|video_|bits[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N24 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N25 -dffeas \ula_|video_|bits_prefetch[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N3 -dffeas \ula_|video_|bits[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N2 -cycloneive_lcell_comb \ula_|video_|Mux0~2 ( -// Equation(s): -// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), - .datac(\ula_|video_|bits [3]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Mux0~3 ( -// Equation(s): -// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), - .datac(\ula_|video_|bits [0]), - .datad(\ula_|video_|Mux0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N10 -cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( -// Equation(s): -// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - - .dataa(\ula_|video_|inverted~combout ), - .datab(\ula_|video_|Mux0~1_combout ), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|Mux0~3_combout ), - .cin(gnd), - .combout(\ula_|video_|cindex[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; -defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N17 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N4 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N5 +// Location: LCCOMB_X30_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -62302,7 +65137,24 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N19 +// Location: LCCOMB_X29_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N11 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62321,82 +65173,832 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N16 +// Location: LCCOMB_X25_Y31_N6 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N7 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N27 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N21 +dffeas \ula_|video_|attr_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N7 +dffeas \ula_|video_|attr[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N2 +cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( +// Equation(s): +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) + + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|frame [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|frame[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h3C3C; +defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y31_N3 +dffeas \ula_|video_|frame[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N14 +cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( +// Equation(s): +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) + + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|frame[1]~4_combout ), + .cout(\ula_|video_|frame[1]~5 )); +// synopsys translate_off +defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; +defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N15 +dffeas \ula_|video_|frame[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N16 +cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( +// Equation(s): +// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) +// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) + + .dataa(gnd), + .datab(\ula_|video_|frame [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[1]~5 ), + .combout(\ula_|video_|frame[2]~6_combout ), + .cout(\ula_|video_|frame[2]~7 )); +// synopsys translate_off +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N17 +dffeas \ula_|video_|frame[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N18 +cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( +// Equation(s): +// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) +// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) + + .dataa(gnd), + .datab(\ula_|video_|frame [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[2]~7 ), + .combout(\ula_|video_|frame[3]~8_combout ), + .cout(\ula_|video_|frame[3]~9 )); +// synopsys translate_off +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N19 +dffeas \ula_|video_|frame[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N20 +cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( +// Equation(s): +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame [4]), + .cin(\ula_|video_|frame[3]~9 ), + .combout(\ula_|video_|frame[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N1 +dffeas \ula_|video_|frame[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N6 +cycloneive_lcell_comb \ula_|video_|inverted ( +// Equation(s): +// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|attr [7]), + .datad(\ula_|video_|frame [4]), + .cin(gnd), + .combout(\ula_|video_|inverted~combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|inverted .lut_mask = 16'hF000; +defparam \ula_|video_|inverted .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N13 +dffeas \ula_|video_|bits_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N1 +dffeas \ula_|video_|bits[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N19 +dffeas \ula_|video_|bits_prefetch[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N31 +dffeas \ula_|video_|bits[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N15 +dffeas \ula_|video_|bits_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N22 +cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( +// Equation(s): +// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [1]), + .cin(gnd), + .combout(\ula_|video_|bits[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y31_N23 +dffeas \ula_|video_|bits[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N17 +dffeas \ula_|video_|bits_prefetch[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N21 +dffeas \ula_|video_|bits[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Mux0~2 ( +// Equation(s): +// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [1]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [3] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Mux0~3 ( +// Equation(s): +// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), + .datac(\ula_|video_|bits [0]), + .datad(\ula_|video_|Mux0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N4 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N5 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N29 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N11 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N19 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N30 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N31 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N25 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N9 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N29 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N16 +cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Equation(s): +// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~3_combout )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~1_combout ))))) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~3_combout ), + .datad(\ula_|video_|Mux0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|cindex[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h396C; +defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N26 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), + .dataa(\ula_|video_|attr [1]), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|attr [1]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N4 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y31_N20 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|video_|LessThan6~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N2 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N14 +// Location: LCCOMB_X27_Y31_N10 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): // \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~0_combout ), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~0_combout ), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N0 +// Location: LCCOMB_X26_Y31_N24 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [5]), .datab(gnd), - .datac(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), @@ -62406,84 +66008,189 @@ defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N4 +// Location: LCCOMB_X26_Y31_N30 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): // \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & // !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_hc [7]), .datac(\ula_|video_|vga_hc [9]), .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7A5E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N12 +// Location: LCCOMB_X27_Y31_N16 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [6]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h4F00; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N24 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) +// \ula_|video_|disp_enable~1_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & !\ula_|video_|LessThan2~1_combout )) - .dataa(gnd), - .datab(\ula_|video_|LessThan2~1_combout ), - .datac(\ula_|video_|LessThan3~0_combout ), - .datad(\ula_|video_|disp_enable~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), + .datac(gnd), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h0088; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N26 -cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( -// Equation(s): -// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - - .dataa(\ula_|border [1]), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), - .cin(gnd), - .combout(\ula_|video_|VGA_R[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; -defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N22 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N23 -dffeas \ula_|video_|attr_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), +// Location: FF_X24_Y19_N17 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[1]~12_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N0 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N26 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N24 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N10 +cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( +// Equation(s): +// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout )) # (!\ula_|video_|screen_en~1_combout & ((\ula_|border [1]))))) + + .dataa(\ula_|video_|cindex[1]~1_combout ), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [1]), + .datad(\ula_|video_|screen_en~1_combout ), + .cin(gnd), + .combout(\ula_|video_|VGA_R[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'h88C0; +defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N23 +dffeas \ula_|video_|attr_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62494,7 +66201,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y30_N29 +// Location: FF_X27_Y31_N27 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62513,66 +66220,49 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N28 +// Location: LCCOMB_X27_Y31_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & \ula_|video_|LessThan3~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|LessThan2~1_combout ), + .datad(\ula_|video_|LessThan3~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N6 +// Location: LCCOMB_X28_Y31_N4 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(gnd), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y27_N20 -cycloneive_lcell_comb \ula_|border[2]~feeder ( -// Equation(s): -// \ula_|border[2]~feeder_combout = \D[2]~53_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[2]~53_combout ), - .cin(gnd), - .combout(\ula_|border[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y27_N21 +// Location: FF_X24_Y19_N5 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[2]~13_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62583,79 +66273,24 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N30 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N31 -dffeas \ula_|video_|attr_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N31 -dffeas \ula_|video_|attr[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N16 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N17 +// Location: FF_X25_Y31_N25 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -62674,15 +66309,32 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N13 +// Location: LCCOMB_X28_Y31_N30 +cycloneive_lcell_comb \ula_|video_|attr[2]~feeder ( +// Equation(s): +// \ula_|video_|attr[2]~feeder_combout = \ula_|video_|attr_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|attr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N31 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), + .d(\ula_|video_|attr[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62693,48 +66345,103 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N30 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 +dffeas \ula_|video_|attr_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N5 +dffeas \ula_|video_|attr[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N4 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|attr [2]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N0 +// Location: LCCOMB_X29_Y31_N2 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|border [2]), - .datad(\ula_|video_|cindex[2]~2_combout ), + .dataa(\ula_|border [2]), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|video_|cindex[2]~2_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC088; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N18 +// Location: LCCOMB_X28_Y31_N12 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[2]~2_combout )) - .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), @@ -62744,32 +66451,15 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~65_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~65_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 +// Location: FF_X23_Y20_N25 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~14_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62780,24 +66470,24 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N8 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N9 +// Location: FF_X25_Y31_N1 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -62816,15 +66506,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N23 +// Location: LCCOMB_X28_Y31_N2 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N3 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62835,24 +66542,24 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -62871,7 +66578,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N9 +// Location: FF_X29_Y31_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62890,47 +66597,47 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N8 +// Location: LCCOMB_X29_Y31_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[2]~0_combout ), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N26 +// Location: LCCOMB_X29_Y31_N6 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[0]~3_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N12 +// Location: LCCOMB_X29_Y31_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|cindex[0]~3_combout ), - .datab(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|cindex[0]~3_combout ), .datac(gnd), .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), @@ -62941,24 +66648,7 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~2 ( -// Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; -defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y29_N1 +// Location: FF_X30_Y31_N13 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -62977,16 +66667,33 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N0 +// Location: LCCOMB_X30_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Equal0~2 ( +// Equation(s): +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9])) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h000A; +defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N12 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~1_combout & ((\ula_|video_|Equal0~2_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~1_combout & (\ula_|video_|Equal1~0_combout & // (\ula_|video_|VGA_HS~_Duplicate_1_q ))) - .dataa(\ula_|video_|Equal0~2_combout ), + .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); @@ -63014,7 +66721,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X31_Y31_N29 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -63033,21 +66740,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X31_Y31_N28 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((!\ula_|video_|Equal3~1_combout & \ula_|video_|VGA_VS~_Duplicate_1_q )))) # (!\ula_|video_|Equal2~2_combout & (!\ula_|video_|Equal3~1_combout & +// (\ula_|video_|VGA_VS~_Duplicate_1_q ))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hBA30; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63070,7 +66777,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N4 +// Location: LCCOMB_X36_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -63087,7 +66794,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N5 +// Location: FF_X36_Y11_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -63106,7 +66813,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y13_N3 +// Location: FF_X36_Y11_N1 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -63125,7 +66832,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 +// Location: LCCOMB_X36_Y11_N0 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -63142,41 +66849,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N24 +// Location: LCCOMB_X52_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF33; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N24 +// Location: LCCOMB_X23_Y18_N4 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~38_combout $ (\D[4]~39_combout )) - .dataa(\D[3]~109_combout ), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\D[4]~111_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~38_combout ), + .datac(gnd), + .datad(\D[4]~39_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA55A; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N25 +// Location: FF_X23_Y18_N5 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -63195,160 +66902,194 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N4 +// Location: LCCOMB_X29_Y8_N18 cycloneive_lcell_comb \sdram_|Mux26~4 ( // Equation(s): // \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.address[3]~6_combout ), .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), .combout(\sdram_|Mux26~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .lut_mask = 16'h0F05; defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N10 -cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( -// Equation(s): -// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.bank[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; -defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N8 -cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( -// Equation(s): -// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.bank[0]~7_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; -defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( -// Equation(s): -// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; -defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( -// Equation(s): -// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.bank[0]~4_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; -defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N4 +// Location: LCCOMB_X19_Y13_N28 cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( // Equation(s): -// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # -// (\sdram_|r.bank[0]~5_combout ))))) +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.bank[0]~5_combout ), + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.bank[0]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hA005; defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( // Equation(s): -// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) +// \sdram_|r.bank[0]~4_combout = (\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.bank[0]~8_combout ), + .combout(\sdram_|r.bank[0]~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; -defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hFC00; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N18 +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [6] & ((\sdram_|r.bank[0]~4_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'hF888; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( // Equation(s): -// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) +// \sdram_|r.bank[0]~12_combout = ((!\sdram_|r.bank[0]~5_combout & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|r.bank[0]~6_combout ) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.bank[0]~11_combout ), - .datad(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.bank[0]~6_combout ), + .datac(\sdram_|r.bank[0]~5_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'h373F; defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N2 +// Location: LCCOMB_X19_Y13_N22 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [5]) # ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hAFFF; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [7] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'h5A7A; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( // Equation(s): -// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [4]) # ((\sdram_|r.bank[0]~8_combout ) # ((\sdram_|r.state [5] & !\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.bank[0]~11_combout ), - .datac(\sdram_|r.bank[0]~6_combout ), - .datad(\sdram_|r.bank[0]~12_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~8_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'hFFF2; defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~9_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~7_combout ), + .datad(\sdram_|r.bank[0]~9_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'hB9A8; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~13 ( +// Equation(s): +// \sdram_|r.bank[0]~13_combout = ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [7])))) # (!\sdram_|r.bank[0]~5_combout ) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.bank[0]~5_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~13 .lut_mask = 16'h7FFB; +defparam \sdram_|r.bank[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N26 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.state [8] & ((\sdram_|r.bank[0]~10_combout & ((!\sdram_|r.bank[0]~13_combout ))) # (!\sdram_|r.bank[0]~10_combout & (!\sdram_|r.bank[0]~12_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~10_combout +// )))) + + .dataa(\sdram_|r.bank[0]~12_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~10_combout ), + .datad(\sdram_|r.bank[0]~13_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'h07C7; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X11_Y0_N18 dffeas \sdram_|r.bank[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -63358,7 +67099,7 @@ dffeas \sdram_|r.bank[0] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [0]), @@ -63368,20 +67109,20 @@ defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; defparam \sdram_|r.bank[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N2 +// Location: LCCOMB_X29_Y8_N26 cycloneive_lcell_comb \sdram_|Mux25~4 ( // Equation(s): // \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [10]), + .datab(\sdram_|r.address[3]~6_combout ), .datac(gnd), - .datad(\sdram_|r.address[3]~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\sdram_|Mux25~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .lut_mask = 16'h2233; defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63394,7 +67135,7 @@ dffeas \sdram_|r.bank[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [1]), @@ -63404,146 +67145,146 @@ defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; defparam \sdram_|r.bank[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux71~6 ( // Equation(s): -// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) +// \sdram_|Mux71~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [4] & \sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux24~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; -defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux71~0 ( -// Equation(s): -// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|Mux71~0_combout ), + .combout(\sdram_|Mux71~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; -defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux71~6 .lut_mask = 16'hF710; +defparam \sdram_|Mux71~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N4 -cycloneive_lcell_comb \sdram_|process_0~7 ( -// Equation(s): -// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\sdram_|r.act_row [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\sdram_|process_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; -defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N28 -cycloneive_lcell_comb \sdram_|process_0~4 ( -// Equation(s): -// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|process_0~7_combout ), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|process_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; -defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux71~1 ( -// Equation(s): -// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux71~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; -defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N28 +// Location: LCCOMB_X20_Y15_N0 cycloneive_lcell_comb \sdram_|Mux71~2 ( // Equation(s): -// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) +// \sdram_|Mux71~2_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux71~1_combout ), - .datad(\sdram_|Mux71~0_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux71~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .lut_mask = 16'h000F; defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N14 +// Location: LCCOMB_X20_Y15_N16 cycloneive_lcell_comb \sdram_|Mux71~3 ( // Equation(s): -// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) +// \sdram_|Mux71~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [7])) # (!\sdram_|Mux71~2_combout ))) # (!\sdram_|r.state [8] & ((\sdram_|Mux71~2_combout ) # ((!\sdram_|Mux4~0_combout )))) - .dataa(\sdram_|process_0~4_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux71~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux71~2_combout ), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux71~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .lut_mask = 16'hEF67; defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N4 +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \sdram_|process_0~8 ( +// Equation(s): +// \sdram_|process_0~8_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\sdram_|process_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~8 .lut_mask = 16'h0FA5; +defparam \sdram_|process_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (((\sdram_|process_0~8_combout ) # (!\sdram_|Equal7~1_combout )) # (!\sdram_|Equal7~0_combout )) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|process_0~8_combout ), + .datad(\sdram_|Equal7~1_combout ), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hF7FF; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 cycloneive_lcell_comb \sdram_|Mux71~4 ( // Equation(s): -// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) +// \sdram_|Mux71~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux71~6_combout & ((\sdram_|Mux71~3_combout ) # (\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux71~3_combout )))) - .dataa(\sdram_|Mux24~5_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|Mux71~3_combout ), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|Mux71~6_combout ), + .datab(\sdram_|Mux71~3_combout ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux71~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .lut_mask = 16'hA8CC; defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux24~8 ( +// Equation(s): +// \sdram_|Mux24~8_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~8 .lut_mask = 16'h0307; +defparam \sdram_|Mux24~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux71~5 ( +// Equation(s): +// \sdram_|Mux71~5_combout = (\sdram_|Mux71~4_combout ) # ((\sdram_|Mux24~8_combout & ((\sdram_|r.state [7]) # (\sdram_|Mux71~2_combout )))) + + .dataa(\sdram_|Mux71~4_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~8_combout ), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~5 .lut_mask = 16'hFAEA; +defparam \sdram_|Mux71~5 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y0_N11 dffeas \sdram_|r.dq_masks[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63562,7 +67303,7 @@ defparam \sdram_|r.dq_masks[0] .power_up = "low"; // Location: DDIOOUTCELL_X14_Y0_N18 dffeas \sdram_|r.dq_masks[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63578,248 +67319,248 @@ defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; defparam \sdram_|r.dq_masks[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N2 -cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \sdram_|n~6 ( // Equation(s): -// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) +// \sdram_|n~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.bank[0]~10_combout ), + .combout(\sdram_|n~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; -defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +defparam \sdram_|n~6 .lut_mask = 16'h5051; +defparam \sdram_|n~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N18 -cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Location: LCCOMB_X19_Y19_N12 +cycloneive_lcell_comb \sdram_|Mux9~0 ( // Equation(s): -// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) +// \sdram_|Mux9~0_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [7] & ((!\sdram_|r.state [4]))) # (!\sdram_|r.state [7] & ((\sdram_|n~6_combout ) # (\sdram_|r.state [4]))))) + + .dataa(\sdram_|n~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~0 .lut_mask = 16'h3E00; +defparam \sdram_|Mux9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N14 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|r.state [6] & (!\sdram_|n~2_combout & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (((\sdram_|n~6_combout )))) .dataa(\sdram_|n~2_combout ), .datab(\sdram_|r.state [6]), .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.bank[0]~10_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; -defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N30 -cycloneive_lcell_comb \sdram_|n~5 ( -// Equation(s): -// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|n~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|n~5 .lut_mask = 16'h3031; -defparam \sdram_|n~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N12 -cycloneive_lcell_comb \sdram_|Mux9~4 ( -// Equation(s): -// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) - - .dataa(\sdram_|Mux9~3_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux9~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N4 -cycloneive_lcell_comb \sdram_|Mux9~2 ( -// Equation(s): -// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux9~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; -defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N30 -cycloneive_lcell_comb \sdram_|Equal2~3 ( -// Equation(s): -// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Equal2~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; -defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N8 -cycloneive_lcell_comb \sdram_|Mux10~2 ( -// Equation(s): -// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [4]), - .cin(gnd), - .combout(\sdram_|Mux10~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; -defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N26 -cycloneive_lcell_comb \sdram_|Mux10~3 ( -// Equation(s): -// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) - - .dataa(\sdram_|r.init_counter [2]), - .datab(\sdram_|r.init_counter [3]), - .datac(\sdram_|Mux10~2_combout ), - .datad(\sdram_|r.init_counter [1]), - .cin(gnd), - .combout(\sdram_|Mux10~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; -defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N4 -cycloneive_lcell_comb \sdram_|process_0~6 ( -// Equation(s): -// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|process_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~6 .lut_mask = 16'h0010; -defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N24 -cycloneive_lcell_comb \sdram_|Mux10~4 ( -// Equation(s): -// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) - - .dataa(\sdram_|Mux10~3_combout ), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|process_0~6_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux10~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; -defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux9~5 ( -// Equation(s): -// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|n~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; -defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N20 -cycloneive_lcell_comb \sdram_|Mux7~0 ( -// Equation(s): -// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; -defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~6 ( -// Equation(s): -// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|Mux10~4_combout ), - .datac(\sdram_|Mux9~5_combout ), - .datad(\sdram_|Mux7~0_combout ), + .datad(\sdram_|n~6_combout ), .cin(gnd), .combout(\sdram_|Mux9~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .lut_mask = 16'h7340; defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N24 +// Location: LCCOMB_X19_Y19_N0 cycloneive_lcell_comb \sdram_|Mux9~7 ( // Equation(s): -// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~6_combout & ((\sdram_|r.state [6]) # ((\sdram_|r.state [5]) # (\sdram_|r.state [7])))) # (!\sdram_|Mux9~6_combout & ((\sdram_|r.state [5] $ (\sdram_|r.state [7])))) - .dataa(\sdram_|Mux9~4_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|Mux9~2_combout ), - .datad(\sdram_|Mux9~6_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux9~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux9~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .lut_mask = 16'hCFF8; defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y19_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h000F; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (!\sdram_|r.init_counter [0] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h4000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (\sdram_|process_0~5_combout & (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14]))) + + .dataa(\sdram_|process_0~5_combout ), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0002; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [6]), + .datab(gnd), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h0500; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \sdram_|Equal5~1 ( +// Equation(s): +// \sdram_|Equal5~1_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal5~0_combout & (\sdram_|r.init_counter [1] & \sdram_|process_0~6_combout ))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal5~0_combout ), + .datac(\sdram_|r.init_counter [1]), + .datad(\sdram_|process_0~6_combout ), + .cin(gnd), + .combout(\sdram_|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~1 .lut_mask = 16'h8000; +defparam \sdram_|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = (!\sdram_|r.init_counter [7] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [2] & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [7]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h4000; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (!\sdram_|Equal5~1_combout & (((!\sdram_|process_0~7_combout ) # (!\sdram_|process_0~6_combout )) # (!\sdram_|r.init_counter [3]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|process_0~6_combout ), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|process_0~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'h070F; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N6 +cycloneive_lcell_comb \sdram_|Mux9~1 ( +// Equation(s): +// \sdram_|Mux9~1_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~1 .lut_mask = 16'hFFD0; +defparam \sdram_|Mux9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N2 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|Mux9~1_combout ) # ((\sdram_|Mux7~0_combout & (!\sdram_|Equal2~3_combout & \sdram_|Mux10~2_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|Equal2~3_combout ), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux9~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'hFF20; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|Mux9~0_combout ) # ((\sdram_|Mux9~7_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~2_combout ))) + + .dataa(\sdram_|Mux9~0_combout ), + .datab(\sdram_|Mux9~7_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux9~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hEFEE; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X0_Y11_N4 dffeas \sdram_|r.state[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux9~7_combout ), + .d(\sdram_|Mux9~3_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63835,112 +67576,163 @@ defparam \sdram_|r.state[2] .is_wysiwyg = "true"; defparam \sdram_|r.state[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux10~11 ( -// Equation(s): -// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; -defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N12 +// Location: LCCOMB_X19_Y17_N12 cycloneive_lcell_comb \sdram_|Mux10~6 ( // Equation(s): -// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) +// \sdram_|Mux10~6_combout = (\sdram_|r.state [4] & (((\sdram_|r.rd_pending~q & \sdram_|r.state [6])) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & (((\sdram_|r.state [6]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Mux10~11_combout ), - .datac(\sdram_|process_0~4_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .lut_mask = 16'hD5FA; defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N26 +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((\sdram_|Mux10~2_combout & !\sdram_|Mux10~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h6676; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.state [8]) # ((\sdram_|r.state [4] & \sdram_|r.state [7])))) # (!\sdram_|r.rf_pending~q & (\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'hEEA2; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [8])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [8]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'h1120; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 cycloneive_lcell_comb \sdram_|Mux10~5 ( // Equation(s): -// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) +// \sdram_|Mux10~5_combout = (\sdram_|r.state [6] & ((\sdram_|Mux10~3_combout ) # ((!\sdram_|Mux10~4_combout )))) # (!\sdram_|r.state [6] & ((\sdram_|Mux10~4_combout & ((!\sdram_|n~4_combout ))) # (!\sdram_|Mux10~4_combout & (\sdram_|Mux10~3_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~3_combout ), + .datac(\sdram_|n~4_combout ), .datad(\sdram_|Mux10~4_combout ), .cin(gnd), .combout(\sdram_|Mux10~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .lut_mask = 16'h8DEE; defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N10 +// Location: LCCOMB_X19_Y17_N22 cycloneive_lcell_comb \sdram_|Mux10~7 ( // Equation(s): -// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & ((\sdram_|r.wr_pending~q ) # ((!\sdram_|r.rf_pending~q & \sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|r.rf_pending~q )) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .lut_mask = 16'hDACA; defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N20 +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~6_combout ) # ((!\sdram_|r.state [6] & !\sdram_|n~4_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|n~4_combout ), + .datac(\sdram_|Mux10~7_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hFFF1; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux10~12 ( +// Equation(s): +// \sdram_|Mux10~12_combout = (\sdram_|r.state [7] & (((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (\sdram_|r.state [6] & (\sdram_|process_0~3_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~12 .lut_mask = 16'hEC20; +defparam \sdram_|Mux10~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 cycloneive_lcell_comb \sdram_|Mux10~8 ( // Equation(s): -// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) +// \sdram_|Mux10~8_combout = (\sdram_|Mux10~10_combout ) # ((\sdram_|Mux10~12_combout ) # ((!\sdram_|r.state [7] & \sdram_|Mux10~5_combout ))) - .dataa(\sdram_|Mux10~7_combout ), + .dataa(\sdram_|Mux10~10_combout ), .datab(\sdram_|r.state [7]), .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~11_combout ), + .datad(\sdram_|Mux10~12_combout ), .cin(gnd), .combout(\sdram_|Mux10~8_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .lut_mask = 16'hFFBA; defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux10~9 ( -// Equation(s): -// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) - - .dataa(\sdram_|Mux10~6_combout ), - .datab(\sdram_|r.bank[0]~10_combout ), - .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux10~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; -defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y11_N11 dffeas \sdram_|r.state[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux10~9_combout ), + .d(\sdram_|Mux10~8_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63969,146 +67761,129 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux11~2 ( -// Equation(s): -// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux11~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; -defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux11~3 ( -// Equation(s): -// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|Mux11~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux11~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; -defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N26 +// Location: LCCOMB_X18_Y17_N26 cycloneive_lcell_comb \sdram_|Mux11~4 ( // Equation(s): -// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) +// \sdram_|Mux11~4_combout = (\sdram_|r.state [5] & ((\sdram_|r.state [8] $ (\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & (\sdram_|r.state [7])) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|Mux11~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux11~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .lut_mask = 16'h6EE6; defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N28 +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|r.state [6] & (((\sdram_|n~6_combout ) # (!\sdram_|r.state [8])) # (!\sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hCC4C; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (!\sdram_|Equal2~3_combout & (!\sdram_|r.state [8] & (!\sdram_|Equal5~1_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'h0001; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~2_combout ) # ((!\sdram_|Mux23~0_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|Mux11~2_combout ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 cycloneive_lcell_comb \sdram_|Mux11~5 ( // Equation(s): -// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) +// \sdram_|Mux11~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((\sdram_|r.state [8] & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux11~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .lut_mask = 16'h0C0E; defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N0 +// Location: LCCOMB_X18_Y17_N10 cycloneive_lcell_comb \sdram_|Mux11~6 ( // Equation(s): -// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) +// \sdram_|Mux11~6_combout = (\sdram_|Mux11~5_combout & (!\sdram_|r.wr_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|Mux11~5_combout ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux11~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .lut_mask = 16'h008A; defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N30 +// Location: LCCOMB_X18_Y17_N24 cycloneive_lcell_comb \sdram_|Mux11~7 ( // Equation(s): -// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) +// \sdram_|Mux11~7_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~8_combout ) # ((\sdram_|Mux11~3_combout ) # (\sdram_|Mux11~6_combout ))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~8_combout ), + .datac(\sdram_|Mux11~3_combout ), .datad(\sdram_|Mux11~6_combout ), .cin(gnd), .combout(\sdram_|Mux11~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .lut_mask = 16'hFFFE; defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux11~9 ( -// Equation(s): -// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|Mux7~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; -defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N14 -cycloneive_lcell_comb \sdram_|Mux11~8 ( -// Equation(s): -// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) - - .dataa(\sdram_|Mux11~4_combout ), - .datab(\sdram_|Mux11~5_combout ), - .datac(\sdram_|Mux11~7_combout ), - .datad(\sdram_|Mux11~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; -defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y27_N4 dffeas \sdram_|r.state[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux11~8_combout ), + .d(\sdram_|Mux11~7_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -64124,75 +67899,41 @@ defparam \sdram_|r.state[0] .is_wysiwyg = "true"; defparam \sdram_|r.state[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \sdram_|Mux24~5 ( // Equation(s): -// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) +// \sdram_|Mux24~5_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[11]~18_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q )))) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux24~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; -defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N2 -cycloneive_lcell_comb \sdram_|r.address[0]~7 ( -// Equation(s): -// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .dataa(\sdram_|process_0~4_combout ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\sdram_|Mux23~0_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~7_combout ), + .combout(\sdram_|Mux24~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; -defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~5 .lut_mask = 16'hE400; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N12 -cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \sdram_|Mux24~6 ( // Equation(s): -// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) +// \sdram_|Mux24~6_combout = (\sdram_|Mux24~5_combout ) # ((!\sdram_|n~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.address[0]~_Duplicate_1_q ), - .datad(\sdram_|r.address[0]~7_combout ), + .dataa(\sdram_|n~4_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux24~5_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~0_combout ), + .combout(\sdram_|Mux24~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; -defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~6 .lut_mask = 16'hFF04; +defparam \sdram_|Mux24~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux13~9 ( -// Equation(s): -// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux13~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; -defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N0 +// Location: LCCOMB_X21_Y16_N6 cycloneive_lcell_comb \sdram_|Mux13~4 ( // Equation(s): // \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) @@ -64209,28 +67950,45 @@ defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N2 +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 cycloneive_lcell_comb \sdram_|Mux13~5 ( // Equation(s): -// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux13~9_combout ))) - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux13~9_combout ), - .datad(\sdram_|Mux13~4_combout ), + .dataa(\sdram_|Mux13~4_combout ), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux13~9_combout ), .cin(gnd), .combout(\sdram_|Mux13~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .lut_mask = 16'hAFA0; defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N13 +// Location: FF_X20_Y14_N21 dffeas \sdram_|r.address[0]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[0]~0_combout ), - .asdata(\sdram_|Mux24~4_combout ), + .asdata(\sdram_|Mux24~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64245,54 +68003,88 @@ defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N4 +// Location: LCCOMB_X19_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & (\z80_|address_pins_|abus[11]~18_combout )) # (!\sdram_|process_0~4_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hD800; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 cycloneive_lcell_comb \sdram_|Mux24~3 ( // Equation(s): -// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) +// \sdram_|Mux24~3_combout = (\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q ) - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux24~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .lut_mask = 16'hFF55; defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N14 +// Location: LCCOMB_X21_Y14_N6 cycloneive_lcell_comb \sdram_|Mux24~4 ( // Equation(s): -// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) +// \sdram_|Mux24~4_combout = (\sdram_|r.address[0]~_Duplicate_1_q & (((!\sdram_|r.rd_pending~q & \sdram_|Mux24~3_combout )) # (!\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|n~3_combout ), + .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux24~3_combout ), - .datad(\sdram_|r.state [6]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux24~3_combout ), .cin(gnd), .combout(\sdram_|Mux24~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .lut_mask = 16'h4C0C; defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N24 +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & ((\sdram_|Mux24~4_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux24~2_combout )) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux24~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'hEE22; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux24~6_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[0]~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux24~4_combout ), - .datad(\sdram_|r.address[0]~0_combout ), + .datab(\sdram_|r.address[0]~0_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux24~6_combout ), .cin(gnd), .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64315,114 +68107,148 @@ defparam \sdram_|r.address[0] .is_wysiwyg = "true"; defparam \sdram_|r.address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N16 +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [4] & (\sdram_|process_0~4_combout & ((\sdram_|Equal7~2_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'h8880; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~8 ( +// Equation(s): +// \sdram_|r.address[1]~8_combout = (\sdram_|r.state [4]) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~8 .lut_mask = 16'hEEFF; +defparam \sdram_|r.address[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[1]~9 ( +// Equation(s): +// \sdram_|r.address[1]~9_combout = (\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~9 .lut_mask = 16'hDD00; +defparam \sdram_|r.address[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \sdram_|r.address[1]~7 ( +// Equation(s): +// \sdram_|r.address[1]~7_combout = (\sdram_|r.address[1]~_Duplicate_1_q & (((\sdram_|r.state [8]) # (!\sdram_|r.state [6])) # (!\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~7 .lut_mask = 16'hF070; +defparam \sdram_|r.address[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|r.address[1]~10 ( +// Equation(s): +// \sdram_|r.address[1]~10_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~9_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[1]~7_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[1]~9_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~10 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~8_combout & (\sdram_|r.address[1]~10_combout ))) # (!\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~7_combout & ((\sdram_|r.address[1]~8_combout ) # +// (!\sdram_|r.address[1]~10_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|r.address[1]~8_combout ), + .datac(\sdram_|r.address[1]~10_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hC580; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( // Equation(s): // \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout - .dataa(\sdram_|r.address[1]~1_combout ), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hFF00; defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux23~4 ( -// Equation(s): -// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & -// (\sdram_|r.address[1]~_Duplicate_1_q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\z80_|address_pins_|abus[12]~24_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; -defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N16 -cycloneive_lcell_comb \sdram_|Equal5~0 ( -// Equation(s): -// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Equal5~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; -defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux23~5 ( -// Equation(s): -// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux23~4_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Equal5~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; -defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux23~6 ( -// Equation(s): -// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|Mux23~5_combout ), - .datad(\sdram_|Mux24~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; -defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N2 +// Location: LCCOMB_X21_Y16_N30 cycloneive_lcell_comb \sdram_|Mux19~0 ( // Equation(s): // \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .lut_mask = 16'h9299; defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y12_N17 +// Location: FF_X25_Y16_N25 dffeas \sdram_|r.address[1]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), - .asdata(\sdram_|Mux23~6_combout ), + .asdata(\sdram_|Mux23~5_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64437,88 +68263,89 @@ defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N28 -cycloneive_lcell_comb \sdram_|Mux23~2 ( -// Equation(s): -// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux23~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; -defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N30 +// Location: LCCOMB_X20_Y17_N2 cycloneive_lcell_comb \sdram_|Mux23~3 ( // Equation(s): -// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) +// \sdram_|Mux23~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.address[1]~_Duplicate_1_q )))) # (!\sdram_|r.state [8] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[12]~21_combout ))) # (!\sdram_|process_0~4_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|Mux23~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), .cin(gnd), .combout(\sdram_|Mux23~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .lut_mask = 16'hF4B0; defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N18 -cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Location: LCCOMB_X20_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux23~4 ( // Equation(s): -// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (((\sdram_|Mux23~3_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((\sdram_|Mux23~3_combout ))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )))) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|Mux23~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hCCCA; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = ((!\sdram_|r.rd_pending~q & ((\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|Equal7~2_combout ) .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux23~1_combout ), + .combout(\sdram_|Mux23~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; -defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~2 .lut_mask = 16'h33BF; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N22 -cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( // Equation(s): -// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) +// \sdram_|Mux23~5_combout = (\sdram_|Mux23~4_combout & (((\sdram_|Mux23~2_combout ) # (\sdram_|r.state [4])) # (!\sdram_|r.state [8]))) - .dataa(gnd), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~3_combout ), - .datad(\sdram_|Mux23~1_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|Mux23~2_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.address[1]~1_combout ), + .combout(\sdram_|Mux23~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; -defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~5 .lut_mask = 16'hCCC4; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N2 +// Location: LCCOMB_X21_Y16_N4 cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|r.address[1]~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux23~5_combout )) - .dataa(\sdram_|r.address[1]~1_combout ), - .datab(\sdram_|Mux23~6_combout ), + .dataa(gnd), + .datab(\sdram_|Mux23~5_combout ), .datac(\sdram_|r.state [7]), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64541,211 +68368,211 @@ defparam \sdram_|r.address[1] .is_wysiwyg = "true"; defparam \sdram_|r.address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N10 -cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( // Equation(s): -// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[3]~8_combout ), + .combout(\sdram_|r.address[3]~11_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; -defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h5F5C; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N24 -cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( // Equation(s): -// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) +// \sdram_|r.address[3]~12_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|r.address[3]~9_combout ), + .combout(\sdram_|r.address[3]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; -defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hF000; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N26 +// Location: LCCOMB_X23_Y14_N28 cycloneive_lcell_comb \sdram_|Mux21~0 ( // Equation(s): -// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~11_combout & ((\sdram_|r.address[3]~12_combout ) # ((\sdram_|r.state [4] & \sdram_|r.address[3]~6_combout )))) - .dataa(\sdram_|r.address[3]~6_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.address[3]~9_combout ), - .datad(\sdram_|r.address[3]~8_combout ), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.address[3]~12_combout ), .cin(gnd), .combout(\sdram_|Mux21~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .lut_mask = 16'h5540; defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N18 +// Location: LCCOMB_X24_Y8_N12 cycloneive_lcell_comb \sdram_|Mux22~0 ( // Equation(s): -// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[1]~27_combout ) # ((\z80_|address_pins_|abus[13]~20_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[13]~20_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[1]~25_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[1]~27_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux22~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .lut_mask = 16'hECA0; defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N20 -cycloneive_lcell_comb \sdram_|r.address[3]~10 ( -// Equation(s): -// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.address[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; -defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N14 -cycloneive_lcell_comb \sdram_|r.address[3]~11 ( -// Equation(s): -// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|r.address[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; -defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N0 -cycloneive_lcell_comb \sdram_|r.address[3]~12 ( -// Equation(s): -// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~11_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; -defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N6 -cycloneive_lcell_comb \sdram_|r.address[3]~13 ( -// Equation(s): -// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[3]~10_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.address[3]~12_combout ), - .cin(gnd), - .combout(\sdram_|r.address[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; -defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N16 +// Location: LCCOMB_X18_Y17_N12 cycloneive_lcell_comb \sdram_|r.address[3]~14 ( // Equation(s): -// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), + .dataa(gnd), + .datab(\sdram_|r.state [4]), .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.address[3]~14_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h33CF; defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N22 +// Location: LCCOMB_X18_Y17_N30 cycloneive_lcell_comb \sdram_|r.address[3]~15 ( // Equation(s): -// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [8] & ((\sdram_|r.state [4]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4]))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~14_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.address[3]~14_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~15_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hFF9B; defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N24 +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|r.state [4])) # (!\sdram_|r.state [7]) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'h37FF; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 cycloneive_lcell_comb \sdram_|r.address[3]~16 ( // Equation(s): -// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~15_combout )))) - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [5]), .datac(\sdram_|r.address[3]~15_combout ), - .datad(\sdram_|r.state [8]), + .datad(\sdram_|r.address[3]~13_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~16_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .lut_mask = 16'hFC74; defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N26 +// Location: LCCOMB_X19_Y13_N24 cycloneive_lcell_comb \sdram_|r.address[3]~17 ( // Equation(s): -// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & (!\sdram_|r.wr_pending~q & \sdram_|r.state [4]))) - .dataa(\sdram_|r.address[3]~13_combout ), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.address[3]~16_combout ), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|r.address[3]~17_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .lut_mask = 16'hAB02; defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~18 ( +// Equation(s): +// \sdram_|r.address[3]~18_combout = (\sdram_|r.address[3]~17_combout ) # ((\sdram_|r.state [7] & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (\sdram_|r.state [5]))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[3]~17_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~18 .lut_mask = 16'hDEFE; +defparam \sdram_|r.address[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~19 ( +// Equation(s): +// \sdram_|r.address[3]~19_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout ) # (!\sdram_|n~4_combout )))) # (!\sdram_|r.state [8] & (\sdram_|r.address[3]~18_combout )) + + .dataa(\sdram_|r.address[3]~18_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.bank[0]~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~19 .lut_mask = 16'h2EEE; +defparam \sdram_|r.address[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[3]~20 ( +// Equation(s): +// \sdram_|r.address[3]~20_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~16_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~19_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[3]~16_combout ), + .datad(\sdram_|r.address[3]~19_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~20 .lut_mask = 16'h0A5F; +defparam \sdram_|r.address[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X5_Y0_N4 dffeas \sdram_|r.address[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -64755,7 +68582,7 @@ dffeas \sdram_|r.address[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [2]), @@ -64765,21 +68592,21 @@ defparam \sdram_|r.address[2] .is_wysiwyg = "true"; defparam \sdram_|r.address[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N2 +// Location: LCCOMB_X24_Y8_N4 cycloneive_lcell_comb \sdram_|Mux21~1 ( // Equation(s): -// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[2]~28_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[14]~22_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[2]~26_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[2]~28_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux21~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .lut_mask = 16'hECA0; defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -64792,7 +68619,7 @@ dffeas \sdram_|r.address[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [3]), @@ -64802,130 +68629,114 @@ defparam \sdram_|r.address[3] .is_wysiwyg = "true"; defparam \sdram_|r.address[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N22 +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \sdram_|Mux24~7 ( +// Equation(s): +// \sdram_|Mux24~7_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~7 .lut_mask = 16'hA0A8; +defparam \sdram_|Mux24~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 cycloneive_lcell_comb \sdram_|Mux20~4 ( // Equation(s): -// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) +// \sdram_|Mux20~4_combout = (\sdram_|Mux24~7_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~29_combout )))) # (!\sdram_|Mux24~7_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), + .dataa(\z80_|address_pins_|abus[3]~29_combout ), + .datab(\sdram_|Mux24~7_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), .cin(gnd), .combout(\sdram_|Mux20~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .lut_mask = 16'hFB08; defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N26 -cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \sdram_|Mux20~2 ( // Equation(s): -// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) - - .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\sdram_|Mux20~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; -defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux23~7 ( -// Equation(s): -// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; -defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux20~8 ( -// Equation(s): -// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) +// \sdram_|Mux20~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[15]~23_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[4]~_Duplicate_1_q )))) .dataa(\sdram_|r.state [4]), - .datab(\sdram_|n~3_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|Mux20~8_combout ), + .combout(\sdram_|Mux20~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; -defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~2 .lut_mask = 16'hA088; +defparam \sdram_|Mux20~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N18 -cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \sdram_|Mux20~3 ( // Equation(s): -// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|Mux20~3_combout = (\sdram_|Mux20~2_combout ) # ((!\sdram_|r.state [4] & \sdram_|Equal5~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|Mux20~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~10_combout ), + .combout(\sdram_|Mux20~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; -defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~3 .lut_mask = 16'hFF50; +defparam \sdram_|Mux20~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( // Equation(s): -// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux20~3_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux20~4_combout ), + .datad(\sdram_|Mux20~3_combout ), .cin(gnd), - .combout(\sdram_|Mux20~9_combout ), + .combout(\sdram_|r.address[4]~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; -defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \sdram_|r.address[4]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) +// \sdram_|r.address[4]~_Duplicate_1feeder_combout = \sdram_|r.address[4]~2_combout - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|Mux20~10_combout ), - .datad(\sdram_|Mux20~9_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~11_combout ), + .combout(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; -defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N5 +// Location: FF_X21_Y13_N17 dffeas \sdram_|r.address[4]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[4]~2_combout ), - .asdata(\sdram_|Mux20~11_combout ), + .d(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux20~9_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64940,89 +68751,122 @@ defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N2 -cycloneive_lcell_comb \sdram_|Mux20~12 ( -// Equation(s): -// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) - - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux20~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; -defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N4 +// Location: LCCOMB_X21_Y13_N20 cycloneive_lcell_comb \sdram_|Mux20~5 ( // Equation(s): -// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) +// \sdram_|Mux20~5_combout = ((\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [15]))) # (!\sdram_|r.state [6] & (\z80_|address_pins_|DFFE_apin_latch [3]))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\sdram_|Mux20~4_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux20~12_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux20~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .lut_mask = 16'hCFAF; defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N16 +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (((\sdram_|Mux20~5_combout )))) # (!\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [3]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\sdram_|r.state [8]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|Mux20~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'hEF23; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 cycloneive_lcell_comb \sdram_|Mux20~6 ( // Equation(s): -// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[4]~_Duplicate_1_q )))) +// \sdram_|Mux20~6_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .dataa(gnd), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|Mux20~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .lut_mask = 16'hCCC0; defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Mux20~7 ( // Equation(s): -// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) +// \sdram_|Mux20~7_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|Mux20~6_combout & !\sdram_|r.state [8]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~5_combout ), - .datac(gnd), - .datad(\sdram_|Mux20~6_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux20~6_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[4]~2_combout ), + .combout(\sdram_|Mux20~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; -defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~7 .lut_mask = 16'h4498; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N8 -cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \sdram_|Mux20~8 ( // Equation(s): -// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) +// \sdram_|Mux20~8_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~1_combout & ((\sdram_|Mux20~10_combout ) # (!\sdram_|Mux20~7_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~7_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|Mux20~10_combout ), + .datac(\sdram_|Mux20~7_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h8AF0; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|Mux20~8_combout & ((\sdram_|Mux20~10_combout ))) # (!\sdram_|Mux20~8_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[4]~2_combout ), - .datad(\sdram_|Mux20~11_combout ), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\sdram_|Mux20~8_combout ), + .datad(\sdram_|Mux20~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'hFC0C; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux20~9_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[4]~2_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux20~9_combout ), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hF5A0; defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65045,66 +68889,32 @@ defparam \sdram_|r.address[4] .is_wysiwyg = "true"; defparam \sdram_|r.address[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N26 -cycloneive_lcell_comb \sdram_|Mux19~1 ( -// Equation(s): -// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux19~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; -defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N12 +// Location: LCCOMB_X21_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~4 ( // Equation(s): -// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~6_combout )) - .dataa(\sdram_|r.state [8]), + .dataa(\sdram_|Mux20~6_combout ), .datab(gnd), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|Mux23~1_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux19~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .lut_mask = 16'hF0AA; defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux19~5 ( -// Equation(s): -// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux19~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; -defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N20 +// Location: LCCOMB_X20_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~6 ( // Equation(s): -// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) +// \sdram_|Mux19~6_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & (\sdram_|Mux19~4_combout & \sdram_|r.state [4]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux19~6_combout ), .cout()); @@ -65113,25 +68923,42 @@ defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N14 +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h6250; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 cycloneive_lcell_comb \sdram_|Mux19~7 ( // Equation(s): -// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~6_combout & (\sdram_|r.address[5]~_Duplicate_1_q & (\sdram_|Mux19~5_combout ))) # (!\sdram_|Mux19~6_combout & ((\sdram_|Mux19~5_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # +// (!\sdram_|Mux19~5_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) - .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .dataa(\sdram_|Mux19~6_combout ), .datab(\sdram_|r.address[5]~_Duplicate_1_q ), .datac(\sdram_|Mux19~5_combout ), - .datad(\sdram_|Mux19~6_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .lut_mask = 16'hD484; defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N31 +// Location: FF_X20_Y14_N11 dffeas \sdram_|r.address[5]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[5]~3_combout ), @@ -65150,72 +68977,89 @@ defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N20 +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~4_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[5]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h30AA; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 cycloneive_lcell_comb \sdram_|Mux19~2 ( // Equation(s): -// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) +// \sdram_|Mux19~2_combout = (!\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) - .dataa(\sdram_|Mux19~1_combout ), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .lut_mask = 16'h2232; defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N6 +// Location: LCCOMB_X20_Y14_N16 cycloneive_lcell_comb \sdram_|Mux19~3 ( // Equation(s): -// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q )))) +// \sdram_|Mux19~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|Mux19~2_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # (!\sdram_|Mux19~2_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|Equal7~2_combout & +// (\sdram_|r.address[5]~_Duplicate_1_q )) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [4]), - .datac(\z80_|address_pins_|abus[4]~28_combout ), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~2_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .lut_mask = 16'hEC4C; defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N30 +// Location: LCCOMB_X20_Y14_N10 cycloneive_lcell_comb \sdram_|r.address[5]~3 ( // Equation(s): -// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux19~2_combout ), + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|r.state [8]), .datac(gnd), .datad(\sdram_|Mux19~3_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N26 +// Location: LCCOMB_X20_Y14_N6 cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) .dataa(\sdram_|r.address[5]~3_combout ), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux19~7_combout ), - .datad(gnd), + .datac(gnd), + .datad(\sdram_|Mux19~7_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65238,15 +69082,15 @@ defparam \sdram_|r.address[5] .is_wysiwyg = "true"; defparam \sdram_|r.address[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N6 +// Location: LCCOMB_X24_Y8_N20 cycloneive_lcell_comb \sdram_|Mux18~0 ( // Equation(s): -// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux18~0_combout ), .cout()); @@ -65264,7 +69108,7 @@ dffeas \sdram_|r.address[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [6]), @@ -65274,33 +69118,33 @@ defparam \sdram_|r.address[6] .is_wysiwyg = "true"; defparam \sdram_|r.address[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Location: LCCOMB_X24_Y8_N24 +cycloneive_lcell_comb \sdram_|Mux17~2 ( // Equation(s): -// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux17~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux17~0_combout ), + .combout(\sdram_|Mux17~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux17~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X14_Y0_N4 dffeas \sdram_|r.address[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux17~0_combout ), + .d(\sdram_|Mux17~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [7]), @@ -65310,33 +69154,33 @@ defparam \sdram_|r.address[7] .is_wysiwyg = "true"; defparam \sdram_|r.address[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Location: LCCOMB_X24_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux16~2 ( // Equation(s): -// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux16~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux16~0_combout ), + .combout(\sdram_|Mux16~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux16~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X0_Y5_N25 dffeas \sdram_|r.address[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux16~0_combout ), + .d(\sdram_|Mux16~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [8]), @@ -65346,20 +69190,20 @@ defparam \sdram_|r.address[8] .is_wysiwyg = "true"; defparam \sdram_|r.address[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N30 +// Location: LCCOMB_X24_Y8_N8 cycloneive_lcell_comb \sdram_|Mux15~2 ( // Equation(s): -// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\sdram_|r.address[3]~8_combout ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [8]), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux15~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .lut_mask = 16'hF500; defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -65372,7 +69216,7 @@ dffeas \sdram_|r.address[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [9]), @@ -65382,61 +69226,78 @@ defparam \sdram_|r.address[9] .is_wysiwyg = "true"; defparam \sdram_|r.address[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \sdram_|r.address[10]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) +// \sdram_|r.address[10]~_Duplicate_1feeder_combout = \sdram_|r.address[10]~4_combout - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; -defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N28 -cycloneive_lcell_comb \sdram_|Mux14~1 ( -// Equation(s): -// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; -defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N10 -cycloneive_lcell_comb \sdram_|r.address[10]~4 ( -// Equation(s): -// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) - - .dataa(\sdram_|Mux14~0_combout ), - .datab(\sdram_|r.state [8]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\sdram_|Mux14~1_combout ), + .datad(\sdram_|r.address[10]~4_combout ), .cin(gnd), - .combout(\sdram_|r.address[10]~4_combout ), + .combout(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; -defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N11 +// Location: LCCOMB_X20_Y16_N2 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q ) # (\sdram_|r.address[10]~_Duplicate_1_q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.address[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h5F5C; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & !\sdram_|process_0~2_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h00AE; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((!\sdram_|process_0~4_combout & (\sdram_|r.address[10]~_Duplicate_1_q & \sdram_|Mux23~0_combout ))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux14~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y16_N25 dffeas \sdram_|r.address[10]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[10]~4_combout ), + .d(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .asdata(\sdram_|Mux14~3_combout ), .clrn(vcc), .aload(gnd), @@ -65452,71 +69313,71 @@ defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N16 -cycloneive_lcell_comb \sdram_|n~4 ( +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \sdram_|Mux14~1 ( // Equation(s): -// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~4_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - .dataa(\sdram_|Equal7~2_combout ), + .dataa(\sdram_|Equal2~3_combout ), .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|n~4_combout ), + .combout(\sdram_|Mux14~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~4 .lut_mask = 16'h5F5C; -defparam \sdram_|n~4 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N30 -cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \sdram_|Mux14~0 ( // Equation(s): -// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~2_combout )))) - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|Mux14~2_combout ), + .combout(\sdram_|Mux14~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; -defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~0 .lut_mask = 16'hEEAE; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N8 -cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( // Equation(s): -// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) - - .dataa(\sdram_|Mux14~2_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N26 -cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( -// Equation(s): -// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux14~0_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux14~1_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux14~1_combout ), + .datad(\sdram_|Mux14~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hFC30; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux14~3_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[10]~4_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[10]~4_combout ), .datac(\sdram_|Mux14~3_combout ), - .datad(\sdram_|r.address[10]~4_combout ), + .datad(gnd), .cin(gnd), .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hE4E4; defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65539,61 +69400,61 @@ defparam \sdram_|r.address[10] .is_wysiwyg = "true"; defparam \sdram_|r.address[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N28 -cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~21 ( // Equation(s): -// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) +// \sdram_|r.address[11]~21_combout = (!\sdram_|r.rd_pending~q & (((\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.wr_pending~q ))) - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.rd_pending~q ), .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.address[11]~18_combout ), + .combout(\sdram_|r.address[11]~21_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; -defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[11]~21 .lut_mask = 16'h080F; +defparam \sdram_|r.address[11]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N26 +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \sdram_|r.address[11]~22 ( +// Equation(s): +// \sdram_|r.address[11]~22_combout = (\sdram_|r.address[11]~21_combout & ((\sdram_|r.state [8]) # (\sdram_|r.state [4]))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[11]~21_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~22 .lut_mask = 16'hFC00; +defparam \sdram_|r.address[11]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 cycloneive_lcell_comb \sdram_|r.address[11]~5 ( // Equation(s): -// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.address[11]~22_combout ) # ((\sdram_|r.state [8] & !\sdram_|Equal7~2_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux24~2_combout ), + .dataa(\sdram_|r.address[11]~22_combout ), + .datab(\sdram_|r.state [8]), .datac(\sdram_|r.address[11]~_Duplicate_2_q ), - .datad(\sdram_|r.address[11]~18_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .lut_mask = 16'hA0E0; defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( -// Equation(s): -// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout - - .dataa(\sdram_|r.address[11]~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; -defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y11_N5 +// Location: FF_X20_Y14_N9 dffeas \sdram_|r.address[11]~_Duplicate_2 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .d(\sdram_|r.address[11]~5_combout ), .asdata(\sdram_|Mux13~6_combout ), .clrn(vcc), .aload(gnd), @@ -65609,54 +69470,54 @@ defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N8 +// Location: LCCOMB_X20_Y14_N14 cycloneive_lcell_comb \sdram_|Mux13~10 ( // Equation(s): // \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) - .dataa(gnd), - .datab(\sdram_|r.address[11]~_Duplicate_2_q ), - .datac(\sdram_|r.state [6]), + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux13~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .lut_mask = 16'hF050; defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N22 +// Location: LCCOMB_X20_Y14_N0 cycloneive_lcell_comb \sdram_|Mux13~6 ( // Equation(s): -// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|Equal7~2_combout & !\sdram_|r.state [6])) # (!\sdram_|process_0~4_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|Mux13~10_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux13~10_combout ), .cin(gnd), .combout(\sdram_|Mux13~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .lut_mask = 16'h3700; defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N12 +// Location: LCCOMB_X20_Y14_N4 cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65679,20 +69540,20 @@ defparam \sdram_|r.address[11] .is_wysiwyg = "true"; defparam \sdram_|r.address[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N6 +// Location: LCCOMB_X20_Y14_N2 cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65725,6 +69586,16 @@ defparam \SW[0]~input .bus_hold = "false"; defparam \SW[0]~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X25_Y34_N8 +cycloneive_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + // Location: IOIBUF_X53_Y17_N15 cycloneive_io_ibuf \SW[3]~input ( .i(SW[3]), diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 83e1ca8..3e04c0c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/02/2022 14:51:21") + (DATE "04/06/2022 13:58:28") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1504:1504:1504) (1598:1598:1598)) - (PORT oe (1712:1712:1712) (1779:1779:1779)) + (PORT i (2372:2372:2372) (2462:2462:2462)) + (PORT oe (4863:4863:4863) (5015:5015:5015)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2050:2050:2050) (2110:2110:2110)) - (PORT oe (1688:1688:1688) (1781:1781:1781)) + (PORT i (1718:1718:1718) (1802:1802:1802)) + (PORT oe (3583:3583:3583) (3656:3656:3656)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (2228:2228:2228) (2262:2262:2262)) - (PORT oe (1688:1688:1688) (1781:1781:1781)) + (PORT i (1337:1337:1337) (1397:1397:1397)) + (PORT oe (3583:3583:3583) (3656:3656:3656)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1814:1814:1814) (1854:1854:1854)) - (PORT oe (2105:2105:2105) (2195:2195:2195)) + (PORT i (1578:1578:1578) (1619:1619:1619)) + (PORT oe (3400:3400:3400) (3499:3499:3499)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1890:1890:1890) (1931:1931:1931)) - (PORT oe (2105:2105:2105) (2195:2195:2195)) + (PORT i (1624:1624:1624) (1691:1691:1691)) + (PORT oe (3400:3400:3400) (3499:3499:3499)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1532:1532:1532) (1676:1676:1676)) - (PORT oe (2346:2346:2346) (2450:2450:2450)) + (PORT i (1329:1329:1329) (1397:1397:1397)) + (PORT oe (3135:3135:3135) (3272:3272:3272)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1646:1646:1646) (1694:1694:1694)) - (PORT oe (2346:2346:2346) (2450:2450:2450)) + (PORT i (1405:1405:1405) (1507:1507:1507)) + (PORT oe (3135:3135:3135) (3272:3272:3272)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1651:1651:1651) (1747:1747:1747)) - (PORT oe (2346:2346:2346) (2450:2450:2450)) + (PORT i (1437:1437:1437) (1497:1497:1497)) + (PORT oe (3135:3135:3135) (3272:3272:3272)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1458:1458:1458) (1517:1517:1517)) - (PORT oe (2627:2627:2627) (2741:2741:2741)) + (PORT i (1171:1171:1171) (1225:1225:1225)) + (PORT oe (2940:2940:2940) (3068:3068:3068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1614:1614:1614) (1659:1659:1659)) - (PORT oe (2627:2627:2627) (2741:2741:2741)) + (PORT i (1364:1364:1364) (1413:1413:1413)) + (PORT oe (2940:2940:2940) (3068:3068:3068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1699:1699:1699) (1833:1833:1833)) - (PORT oe (2364:2364:2364) (2456:2456:2456)) + (PORT i (1467:1467:1467) (1493:1493:1493)) + (PORT oe (3206:3206:3206) (3319:3319:3319)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1560:1560:1560) (1602:1602:1602)) - (PORT oe (2627:2627:2627) (2741:2741:2741)) + (PORT i (1469:1469:1469) (1491:1491:1491)) + (PORT oe (2940:2940:2940) (3068:3068:3068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1639:1639:1639) (1709:1709:1709)) - (PORT oe (1712:1712:1712) (1796:1796:1796)) + (PORT i (2163:2163:2163) (2267:2267:2267)) + (PORT oe (3618:3618:3618) (3692:3692:3692)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1649:1649:1649) (1732:1732:1732)) - (PORT oe (2364:2364:2364) (2456:2456:2456)) + (PORT i (1598:1598:1598) (1641:1641:1641)) + (PORT oe (3206:3206:3206) (3319:3319:3319)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1435:1435:1435) (1557:1557:1557)) - (PORT oe (2114:2114:2114) (2280:2280:2280)) + (PORT i (1086:1086:1086) (1154:1154:1154)) + (PORT oe (2619:2619:2619) (2764:2764:2764)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1807:1807:1807) (1861:1861:1861)) - (PORT oe (1901:1901:1901) (1995:1995:1995)) + (PORT i (1542:1542:1542) (1579:1579:1579)) + (PORT oe (3573:3573:3573) (3648:3648:3648)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1165:1165:1165) (1241:1241:1241)) - (PORT oe (1397:1397:1397) (1462:1462:1462)) + (PORT i (1624:1624:1624) (1682:1682:1682)) + (PORT oe (1869:1869:1869) (1913:1913:1913)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1217:1217:1217) (1281:1281:1281)) - (PORT oe (1676:1676:1676) (1756:1756:1756)) + (PORT i (1429:1429:1429) (1518:1518:1518)) + (PORT oe (2686:2686:2686) (2737:2737:2737)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1447:1447:1447) (1518:1518:1518)) - (PORT oe (1644:1644:1644) (1702:1702:1702)) + (PORT i (1383:1383:1383) (1456:1456:1456)) + (PORT oe (2340:2340:2340) (2399:2399:2399)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1400:1400:1400) (1428:1428:1428)) - (PORT oe (1397:1397:1397) (1462:1462:1462)) + (PORT i (1165:1165:1165) (1242:1242:1242)) + (PORT oe (1869:1869:1869) (1913:1913:1913)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1625:1625:1625) (1682:1682:1682)) - (PORT oe (1412:1412:1412) (1478:1478:1478)) + (PORT i (1419:1419:1419) (1486:1486:1486)) + (PORT oe (2064:2064:2064) (2094:2094:2094)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1530:1530:1530)) - (PORT oe (1701:1701:1701) (1755:1755:1755)) + (PORT i (1557:1557:1557) (1627:1627:1627)) + (PORT oe (2342:2342:2342) (2374:2374:2374)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1615:1615:1615) (1704:1704:1704)) - (PORT oe (1627:1627:1627) (1676:1676:1676)) + (PORT i (1389:1389:1389) (1450:1450:1450)) + (PORT oe (2092:2092:2092) (2121:2121:2121)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1389:1389:1389) (1468:1468:1468)) - (PORT oe (1392:1392:1392) (1455:1455:1455)) + (PORT i (1623:1623:1623) (1694:1694:1694)) + (PORT oe (2372:2372:2372) (2427:2427:2427)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1446:1446:1446) (1447:1447:1447)) - (PORT oe (1534:1534:1534) (1631:1631:1631)) + (PORT i (1946:1946:1946) (1917:1917:1917)) + (PORT oe (3719:3719:3719) (3789:3789:3789)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1260:1260:1260) (1241:1241:1241)) - (PORT oe (1901:1901:1901) (1995:1995:1995)) + (PORT i (1569:1569:1569) (1477:1477:1477)) + (PORT oe (3573:3573:3573) (3648:3648:3648)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1183:1183:1183) (1166:1166:1166)) - (PORT oe (1856:1856:1856) (1947:1947:1947)) - (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (PORT i (1968:1968:1968) (1962:1962:1962)) + (PORT oe (3995:3995:3995) (4077:4077:4077)) + (IOPATH i o (2502:2502:2502) (2582:2582:2582)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1167:1167:1167) (1158:1158:1158)) - (PORT oe (1000:1000:1000) (1069:1069:1069)) + (PORT i (1941:1941:1941) (1926:1926:1926)) + (PORT oe (4286:4286:4286) (4394:4394:4394)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -377,7 +377,17 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1615:1615:1615) (1516:1516:1516)) + (PORT i (1746:1746:1746) (1668:1668:1668)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2215:2215:2215) (2341:2341:2341)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -387,7 +397,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1031:1031:1031) (1018:1018:1018)) + (PORT i (1510:1510:1510) (1624:1624:1624)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -397,8 +407,48 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1473:1473:1473) (1574:1574:1574)) - (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + (PORT i (1516:1516:1516) (1478:1478:1478)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1265:1265:1265) (1258:1258:1258)) + (IOPATH i o (2502:2502:2502) (2582:2582:2582)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1258:1258:1258) (1255:1255:1255)) + (IOPATH i o (4127:4127:4127) (4477:4477:4477)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1251:1251:1251) (1240:1240:1240)) + (IOPATH i o (2378:2378:2378) (2455:2455:2455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (319:319:319) (322:322:322)) + (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) ) @@ -452,7 +502,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1116:1116:1116) (1178:1178:1178)) + (PORT i (1035:1035:1035) (1041:1041:1041)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +512,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1137:1137:1137) (1173:1173:1173)) + (PORT i (997:997:997) (995:995:995)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +522,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (869:869:869) (884:884:884)) + (PORT i (1008:1008:1008) (996:996:996)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +532,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (820:820:820) (820:820:820)) + (PORT i (540:540:540) (536:536:536)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +542,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (576:576:576) (580:580:580)) + (PORT i (716:716:716) (701:701:701)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +552,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (555:555:555) (581:581:581)) + (PORT i (728:728:728) (700:700:700)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +562,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1290:1290:1290)) + (PORT i (1309:1309:1309) (1310:1310:1310)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +572,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1290:1290:1290)) + (PORT i (1309:1309:1309) (1310:1310:1310)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -532,7 +582,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1111:1111:1111) (1161:1161:1161)) + (PORT i (1076:1076:1076) (1094:1094:1094)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -542,7 +592,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1244:1244:1244) (1229:1229:1229)) + (PORT i (1040:1040:1040) (1057:1057:1057)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +602,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1131:1131:1131) (1197:1197:1197)) + (PORT i (1060:1060:1060) (1082:1082:1082)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -562,7 +612,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1135:1135:1135) (1193:1193:1193)) + (PORT i (1072:1072:1072) (1091:1091:1091)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -590,7 +640,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1748:1748:1748) (1663:1663:1663)) + (PORT i (1882:1882:1882) (1835:1835:1835)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -600,7 +650,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1132:1132:1132) (1158:1158:1158)) + (PORT i (1356:1356:1356) (1377:1377:1377)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -610,7 +660,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (888:888:888) (865:865:865)) + (PORT i (308:308:308) (313:313:313)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -620,7 +670,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1643:1643:1643) (1721:1721:1721)) + (PORT i (1593:1593:1593) (1644:1644:1644)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -838,8 +888,8 @@ (INSTANCE DRAM_DQ\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1255:1255:1255) (1335:1335:1335)) - (PORT oe (1717:1717:1717) (1786:1786:1786)) + (PORT i (1153:1153:1153) (1208:1208:1208)) + (PORT oe (1433:1433:1433) (1474:1474:1474)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -850,8 +900,8 @@ (INSTANCE DRAM_DQ\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1398:1398:1398) (1454:1454:1454)) - (PORT oe (1717:1717:1717) (1786:1786:1786)) + (PORT i (1427:1427:1427) (1504:1504:1504)) + (PORT oe (1433:1433:1433) (1474:1474:1474)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -862,8 +912,8 @@ (INSTANCE DRAM_DQ\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1113:1113:1113) (1148:1148:1148)) - (PORT oe (1376:1376:1376) (1434:1434:1434)) + (PORT i (1337:1337:1337) (1372:1372:1372)) + (PORT oe (1409:1409:1409) (1442:1442:1442)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -874,8 +924,8 @@ (INSTANCE DRAM_DQ\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1206:1206:1206) (1278:1278:1278)) - (PORT oe (1471:1471:1471) (1583:1583:1583)) + (PORT i (1477:1477:1477) (1575:1575:1575)) + (PORT oe (1617:1617:1617) (1743:1743:1743)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -886,8 +936,8 @@ (INSTANCE DRAM_DQ\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1183:1183:1183) (1228:1228:1228)) - (PORT oe (1200:1200:1200) (1240:1240:1240)) + (PORT i (1495:1495:1495) (1585:1585:1585)) + (PORT oe (1528:1528:1528) (1603:1603:1603)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -898,8 +948,8 @@ (INSTANCE DRAM_DQ\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1419:1419:1419) (1515:1515:1515)) - (PORT oe (1364:1364:1364) (1339:1339:1339)) + (PORT i (1442:1442:1442) (1530:1530:1530)) + (PORT oe (1257:1257:1257) (1320:1320:1320)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -910,8 +960,8 @@ (INSTANCE DRAM_DQ\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1148:1148:1148) (1200:1200:1200)) - (PORT oe (1364:1364:1364) (1339:1339:1339)) + (PORT i (975:975:975) (1055:1055:1055)) + (PORT oe (1257:1257:1257) (1320:1320:1320)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -922,8 +972,8 @@ (INSTANCE DRAM_DQ\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (558:558:558) (558:558:558)) - (PORT oe (1367:1367:1367) (1406:1406:1406)) + (PORT i (1419:1419:1419) (1473:1473:1473)) + (PORT oe (1575:1575:1575) (1681:1681:1681)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -934,7 +984,7 @@ (INSTANCE DRAM_DQ\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1686:1686:1686) (1628:1628:1628)) + (PORT i (1622:1622:1622) (1528:1528:1528)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -944,7 +994,7 @@ (INSTANCE DRAM_DQ\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1476:1476:1476) (1402:1402:1402)) + (PORT i (1589:1589:1589) (1486:1486:1486)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -954,7 +1004,7 @@ (INSTANCE DRAM_DQ\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1459:1459:1459) (1382:1382:1382)) + (PORT i (1602:1602:1602) (1499:1499:1499)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -964,7 +1014,7 @@ (INSTANCE DRAM_DQ\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1459:1459:1459) (1382:1382:1382)) + (PORT i (1602:1602:1602) (1499:1499:1499)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -974,7 +1024,7 @@ (INSTANCE DRAM_DQ\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1653:1653:1653) (1629:1629:1629)) + (PORT i (1592:1592:1592) (1501:1501:1501)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -984,7 +1034,7 @@ (INSTANCE DRAM_DQ\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1679:1679:1679) (1615:1615:1615)) + (PORT i (1623:1623:1623) (1523:1523:1523)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -994,7 +1044,7 @@ (INSTANCE DRAM_DQ\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1679:1679:1679) (1615:1615:1615)) + (PORT i (1623:1623:1623) (1523:1523:1523)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -1004,7 +1054,7 @@ (INSTANCE DRAM_DQ\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1240:1240:1240) (1200:1200:1200)) + (PORT i (1603:1603:1603) (1528:1528:1528)) (IOPATH i o (2502:2502:2502) (2582:2582:2582)) ) ) @@ -1036,6 +1086,887 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE turbo_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (481:481:481) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (154:154:154) (138:138:138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (362:362:362)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (354:354:354)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (362:362:362)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (342:342:342)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (351:351:351)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (353:353:353)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT datab (440:440:440) (507:507:507)) + (PORT datac (607:607:607) (658:658:658)) + (PORT datad (403:403:403) (465:465:465)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (393:393:393)) + (PORT datab (418:418:418) (490:490:490)) + (PORT datac (234:234:234) (319:319:319)) + (PORT datad (235:235:235) (310:310:310)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (358:358:358)) + (PORT datab (262:262:262) (351:351:351)) + (PORT datac (626:626:626) (643:643:643)) + (PORT datad (248:248:248) (320:320:320)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (339:339:339)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (260:260:260) (348:348:348)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (232:232:232) (308:308:308)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (679:679:679)) + (PORT datab (252:252:252) (335:335:335)) + (PORT datac (3699:3699:3699) (4050:4050:4050)) + (PORT datad (683:683:683) (741:741:741)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (743:743:743)) + (PORT datab (419:419:419) (488:488:488)) + (PORT datac (231:231:231) (316:316:316)) + (PORT datad (232:232:232) (308:308:308)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (358:358:358)) + (PORT datab (262:262:262) (351:351:351)) + (PORT datac (234:234:234) (318:318:318)) + (PORT datad (234:234:234) (311:311:311)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (365:365:365)) + (PORT datab (690:690:690) (745:745:745)) + (PORT datac (243:243:243) (325:325:325)) + (PORT datad (245:245:245) (318:318:318)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (640:640:640) (652:652:652)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (638:638:638) (647:647:647)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (3737:3737:3737) (4091:4091:4091)) + (PORT datad (593:593:593) (605:605:605)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1756:1756:1756)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE turbo\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE turbo) + (DELAY + (ABSOLUTE + (PORT clk (864:864:864) (796:796:796)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|counter\[0\]\~0) @@ -1050,7 +1981,7 @@ (INSTANCE ula_\|clocks_\|counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1925:1925:1925) (1951:1951:1951)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1059,23 +1990,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE SW\[2\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (551:551:551) (574:574:574)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (880:880:880) (972:972:972)) + (PORT datad (649:649:649) (725:725:725)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1086,7 +2008,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu) (DELAY (ABSOLUTE - (PORT clk (1925:1925:1925) (1951:1951:1951)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1100,16 +2022,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (720:720:720) (751:751:751)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[1\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (481:481:481) (733:733:733)) + (PORT inclk[0] (727:727:727) (752:752:752)) ) ) ) @@ -1127,8 +2040,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1565:1565:1565) (1526:1526:1526)) - (PORT datad (529:529:529) (525:525:525)) + (PORT datac (1566:1566:1566) (1527:1527:1527)) + (PORT datad (531:531:531) (524:524:524)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1139,7 +2052,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) + (PORT datad (1828:1828:1828) (1899:1899:1899)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1149,7 +2062,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1539:1539:1539)) + (PORT clk (1535:1535:1535) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1163,7 +2076,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (753:753:753) (788:788:788)) + (PORT inclk[0] (712:712:712) (740:740:740)) ) ) ) @@ -1172,9 +2085,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1540:1540:1540)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1552:1552:1552)) + (PORT clrn (1563:1563:1563) (1546:1546:1546)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -1184,69 +2097,11 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[1\]\~input) (DELAY (ABSOLUTE - (PORT dataa (1901:1901:1901) (2085:2085:2085)) - (PORT datac (1463:1463:1463) (1532:1532:1532)) - (PORT datad (1153:1153:1153) (1264:1264:1264)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1554:1554:1554)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT datac (727:727:727) (823:823:823)) - (PORT datad (308:308:308) (411:411:411)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (2148:2148:2148) (2241:2241:2241)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1481:1481:1481) (1494:1494:1494)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (2234:2234:2234) (2331:2331:2331)) + (IOPATH i o (481:481:481) (733:733:733)) ) ) ) @@ -1255,13 +2110,66 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (1470:1470:1470) (1557:1557:1557)) - (PORT datad (1650:1650:1650) (1825:1825:1825)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (1829:1829:1829) (2002:2002:2002)) + (PORT datad (1582:1582:1582) (1705:1705:1705)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1347:1347:1347)) + (PORT datac (239:239:239) (315:315:315)) + (PORT datad (972:972:972) (1036:1036:1036)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (4802:4802:4802) (4948:4948:4948)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (1216:1216:1216) (1281:1281:1281)) + (PORT datad (980:980:980) (1041:1041:1041)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -1276,7 +2184,7 @@ (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (741:741:741)) + (PORT dataa (680:680:680) (750:750:750)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1288,10 +2196,10 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (372:372:372) (407:407:407)) - (PORT datad (630:630:630) (642:642:642)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (761:761:761) (768:768:768)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -1300,7 +2208,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1314,7 +2222,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (460:460:460) (524:524:524)) + (PORT datab (655:655:655) (734:734:734)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1328,7 +2236,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (344:344:344)) + (PORT datad (809:809:809) (842:842:842)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1338,7 +2246,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1352,7 +2260,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (411:411:411) (488:488:488)) + (PORT datab (672:672:672) (743:743:743)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1366,8 +2274,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (865:865:865) (873:873:873)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1644:1644:1644) (1682:1682:1682)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1380,9 +2288,9 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (643:643:643) (698:698:698)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (643:643:643) (737:737:737)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1394,13 +2302,29 @@ (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (870:870:870) (883:883:883)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (585:585:585)) + (PORT datab (1407:1407:1407) (1558:1558:1558)) + (PORT datac (1640:1640:1640) (1700:1700:1700)) + (PORT datad (272:272:272) (352:352:352)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL @@ -1408,7 +2332,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (711:711:711)) + (PORT dataa (419:419:419) (490:490:490)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1422,8 +2346,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (876:876:876) (877:877:877)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (516:516:516) (546:546:546)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1433,10 +2357,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT datab (827:827:827) (881:881:881)) + (PORT dataa (1582:1582:1582) (1611:1611:1611)) + (PORT datab (1401:1401:1401) (1478:1478:1478)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (661:661:661) (723:723:723)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (693:693:693) (775:775:775)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1445,126 +2385,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (626:626:626) (651:651:651)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (518:518:518) (549:549:549)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT datab (1373:1373:1373) (1418:1418:1418)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (658:658:658) (673:673:673)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (731:731:731)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1457:1457:1457) (1474:1474:1474)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (542:542:542)) - (PORT datab (973:973:973) (1044:1044:1044)) - (PORT datac (708:708:708) (773:773:773)) - (PORT datad (740:740:740) (794:794:794)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1307:1307:1307)) - (PORT datab (920:920:920) (963:963:963)) - (PORT datac (651:651:651) (705:705:705)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (1079:1079:1079) (1140:1140:1140)) + (PORT dataa (416:416:416) (490:490:490)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1578,8 +2404,8 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (626:626:626) (651:651:651)) + (PORT datab (646:646:646) (668:668:668)) + (PORT datad (174:174:174) (198:198:198)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1590,8 +2416,8 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (868:868:868) (876:876:876)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1535:1535:1535) (1613:1613:1613)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1604,8 +2430,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (265:265:265) (348:348:348)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datad (670:670:670) (749:749:749)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -1615,8 +2441,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (344:344:344) (377:377:377)) - (PORT datad (627:627:627) (653:653:653)) + (PORT datab (646:646:646) (668:668:668)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1627,8 +2453,8 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1429:1429:1429) (1430:1430:1430)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (661:661:661) (677:677:677)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1641,35 +2467,23 @@ (INSTANCE ula_\|video_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (269:269:269)) - (PORT datab (1253:1253:1253) (1334:1334:1334)) - (PORT datac (909:909:909) (963:963:963)) - (PORT datad (873:873:873) (928:928:928)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (1591:1591:1591) (1646:1646:1646)) + (PORT datac (696:696:696) (764:764:764)) + (PORT datad (720:720:720) (765:765:765)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (1244:1244:1244) (1316:1316:1316)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (711:711:711) (769:769:769)) + (PORT datab (1351:1351:1351) (1394:1394:1394)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1680,39 +2494,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (656:656:656) (703:703:703)) - (PORT datab (1503:1503:1503) (1521:1521:1521)) - (PORT datad (594:594:594) (607:607:607)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (647:647:647) (669:669:669)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1541:1541:1541) (1586:1586:1586)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~4) + (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (678:678:678) (738:738:738)) + (PORT datab (705:705:705) (779:779:779)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1721,172 +2532,84 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (705:705:705)) - (PORT datab (638:638:638) (664:664:664)) - (PORT datad (1466:1466:1466) (1485:1485:1485)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[2\]) + (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (694:694:694) (728:728:728)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datab (704:704:704) (764:764:764)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (701:701:701)) - (PORT datab (1504:1504:1504) (1520:1520:1520)) - (PORT datad (597:597:597) (611:611:611)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[3\]) + (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (516:516:516) (547:547:547)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~8) + (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (965:965:965) (1008:1008:1008)) + (PORT dataa (771:771:771) (834:834:834)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (704:704:704)) - (PORT datab (669:669:669) (683:683:683)) - (PORT datad (1464:1464:1464) (1484:1484:1484)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1692:1692:1692) (1765:1765:1765)) + (PORT datab (648:648:648) (701:701:701)) + (PORT datac (732:732:732) (794:794:794)) + (PORT datad (720:720:720) (777:777:777)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (735:735:735) (804:804:804)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (612:612:612) (672:672:672)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (706:706:706)) - (PORT datab (1508:1508:1508) (1524:1524:1524)) - (PORT datad (585:585:585) (600:600:600)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (966:966:966) (1010:1010:1010)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (631:631:631) (686:686:686)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1898,11 +2621,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (701:701:701) (726:726:726)) - (PORT datab (586:586:586) (616:616:616)) - (PORT datad (775:775:775) (772:772:772)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (719:719:719) (748:748:748)) + (PORT datab (568:568:568) (584:584:584)) + (PORT datad (1643:1643:1643) (1683:1683:1683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1913,7 +2636,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1927,7 +2650,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (965:965:965) (1025:1025:1025)) + (PORT datab (948:948:948) (1001:1001:1001)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1941,9 +2664,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (699:699:699) (723:723:723)) - (PORT datab (1070:1070:1070) (1068:1068:1068)) - (PORT datad (558:558:558) (576:576:576)) + (PORT dataa (710:710:710) (738:738:738)) + (PORT datab (796:796:796) (789:789:789)) + (PORT datad (1638:1638:1638) (1675:1675:1675)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -1956,7 +2679,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1970,9 +2693,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (954:954:954) (1004:1004:1004)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (676:676:676) (729:729:729)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1984,9 +2707,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (726:726:726)) - (PORT datab (1128:1128:1128) (1126:1126:1126)) - (PORT datad (558:558:558) (578:578:578)) + (PORT dataa (708:708:708) (737:737:737)) + (PORT datab (760:760:760) (776:776:776)) + (PORT datad (1638:1638:1638) (1675:1675:1675)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -1999,7 +2722,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -2013,8 +2736,8 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (644:644:644) (702:702:702)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (770:770:770) (831:831:831)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -2024,11 +2747,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (702:702:702) (724:724:724)) - (PORT datab (586:586:586) (613:613:613)) - (PORT datad (781:781:781) (782:782:782)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (707:707:707) (735:735:735)) + (PORT datab (528:528:528) (551:551:551)) + (PORT datad (1638:1638:1638) (1675:1675:1675)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2039,7 +2762,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -2048,31 +2771,15 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (378:378:378)) - (PORT datab (715:715:715) (775:775:775)) - (PORT datac (648:648:648) (714:714:714)) - (PORT datad (1179:1179:1179) (1245:1245:1245)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (493:493:493)) - (PORT datab (290:290:290) (374:374:374)) - (PORT datac (250:250:250) (333:333:333)) - (PORT datad (421:421:421) (482:482:482)) + (PORT dataa (272:272:272) (362:362:362)) + (PORT datab (290:290:290) (375:375:375)) + (PORT datac (268:268:268) (354:354:354)) + (PORT datad (250:250:250) (325:325:325)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2085,10 +2792,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (484:484:484)) - (PORT datab (873:873:873) (896:896:896)) - (PORT datac (620:620:620) (674:674:674)) - (PORT datad (590:590:590) (603:603:603)) + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (962:962:962) (1011:1011:1011)) + (PORT datac (584:584:584) (634:634:634)) + (PORT datad (566:566:566) (571:571:571)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2101,11 +2808,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (704:704:704)) - (PORT datab (1503:1503:1503) (1523:1523:1523)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (712:712:712) (741:741:741)) + (PORT datab (531:531:531) (559:559:559)) + (PORT datad (1639:1639:1639) (1677:1677:1677)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2116,7 +2823,209 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (759:759:759) (818:818:818)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (746:746:746)) + (PORT datab (537:537:537) (557:557:557)) + (PORT datad (1642:1642:1642) (1681:1681:1681)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (648:648:648) (706:706:706)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1222:1222:1222)) + (PORT datab (561:561:561) (582:582:582)) + (PORT datac (1111:1111:1111) (1119:1119:1119)) + (PORT datad (1053:1053:1053) (1064:1064:1064)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT asdata (865:865:865) (883:883:883)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1690:1690:1690) (1763:1763:1763)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (733:733:733)) + (PORT datab (573:573:573) (598:598:598)) + (PORT datad (1637:1637:1637) (1674:1674:1674)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (944:944:944) (1001:1001:1001)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (747:747:747)) + (PORT datab (533:533:533) (549:549:549)) + (PORT datad (1643:1643:1643) (1676:1676:1676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (749:749:749)) + (PORT datab (568:568:568) (587:587:587)) + (PORT datad (1643:1643:1643) (1683:1683:1683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -2130,10 +3039,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (488:488:488)) - (PORT datab (715:715:715) (775:775:775)) - (PORT datac (648:648:648) (712:712:712)) - (PORT datad (372:372:372) (442:442:442)) + (PORT dataa (771:771:771) (838:838:838)) + (PORT datab (651:651:651) (707:707:707)) + (PORT datac (727:727:727) (785:785:785)) + (PORT datad (1662:1662:1662) (1717:1717:1717)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2146,11 +3055,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (385:385:385)) - (PORT datac (620:620:620) (674:674:674)) - (PORT datad (591:591:591) (604:604:604)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (610:610:610) (669:669:669)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (562:562:562) (567:567:567)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -2169,10 +3078,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (919:919:919) (997:997:997)) - (PORT datab (946:946:946) (1004:1004:1004)) - (PORT datac (905:905:905) (970:970:970)) - (PORT datad (1292:1292:1292) (1213:1213:1213)) + (PORT dataa (665:665:665) (739:739:739)) + (PORT datab (712:712:712) (790:790:790)) + (PORT datac (655:655:655) (724:724:724)) + (PORT datad (1468:1468:1468) (1399:1399:1399)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2182,54 +3091,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (INSTANCE z80_\|ir_\|opcode\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (1393:1393:1393) (1460:1460:1460)) - (PORT datad (1899:1899:1899) (2006:2006:2006)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (242:242:242) (284:284:284)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (784:784:784) (852:852:852)) - (PORT datab (1496:1496:1496) (1609:1609:1609)) - (PORT datac (1839:1839:1839) (1973:1973:1973)) - (PORT datad (1690:1690:1690) (1763:1763:1763)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1270:1270:1270) (1342:1342:1342)) + (PORT datab (421:421:421) (491:491:491)) + (PORT datad (983:983:983) (1038:1038:1038)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (1772:1772:1772) (1878:1878:1878)) - (PORT datad (331:331:331) (359:359:359)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (408:408:408) (485:485:485)) - (PORT datab (707:707:707) (759:759:759)) - (PORT datad (898:898:898) (912:912:912)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1258:1258:1258) (1328:1328:1328)) + (PORT datab (408:408:408) (483:483:483)) + (PORT datad (978:978:978) (1042:1042:1042)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2240,9 +3150,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -2251,284 +3161,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1418:1418:1418) (1546:1546:1546)) - (PORT datad (934:934:934) (1041:1041:1041)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1912:1912:1912) (2001:2001:2001)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datac (622:622:622) (681:681:681)) - (PORT datad (1605:1605:1605) (1758:1758:1758)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1771:1771:1771) (1874:1874:1874)) - (PORT datab (1642:1642:1642) (1796:1796:1796)) - (PORT datad (1883:1883:1883) (1955:1955:1955)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1549:1549:1549) (1644:1644:1644)) - (PORT datab (263:263:263) (310:310:310)) - (PORT datac (1465:1465:1465) (1503:1503:1503)) - (PORT datad (1184:1184:1184) (1237:1237:1237)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (855:855:855)) - (PORT datab (770:770:770) (837:837:837)) - (PORT datac (1831:1831:1831) (1966:1966:1966)) - (PORT datad (1685:1685:1685) (1757:1757:1757)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1295:1295:1295)) - (PORT datac (924:924:924) (977:977:977)) - (PORT datad (1184:1184:1184) (1237:1237:1237)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (713:713:713)) - (PORT datac (679:679:679) (726:726:726)) - (PORT datad (895:895:895) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1515:1515:1515)) - (PORT datab (2217:2217:2217) (2404:2404:2404)) - (PORT datac (387:387:387) (452:452:452)) - (PORT datad (308:308:308) (411:411:411)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1182:1182:1182) (1247:1247:1247)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datad (1180:1180:1180) (1243:1243:1243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (1537:1537:1537) (1637:1637:1637)) - (PORT datac (1180:1180:1180) (1248:1248:1248)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1263:1263:1263)) - (PORT datab (1222:1222:1222) (1236:1236:1236)) - (PORT datac (2271:2271:2271) (2399:2399:2399)) - (PORT datad (364:364:364) (396:396:396)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2287:2287:2287) (2396:2396:2396)) - (PORT datab (2178:2178:2178) (2359:2359:2359)) - (PORT datac (1216:1216:1216) (1300:1300:1300)) - (PORT datad (874:874:874) (939:939:939)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (434:434:434)) - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (1000:1000:1000) (1080:1080:1080)) - (PORT datad (1503:1503:1503) (1556:1556:1556)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (420:420:420) (502:502:502)) - (PORT datab (708:708:708) (757:757:757)) - (PORT datad (899:899:899) (915:915:915)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1247:1247:1247) (1320:1320:1320)) + (PORT datab (265:265:265) (348:348:348)) + (PORT datad (985:985:985) (1039:1039:1039)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2539,9 +3181,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -2550,2264 +3192,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2484:2484:2484) (2682:2682:2682)) - (PORT datab (1562:1562:1562) (1651:1651:1651)) - (PORT datac (1193:1193:1193) (1280:1280:1280)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2561:2561:2561) (2633:2633:2633)) - (PORT datac (2429:2429:2429) (2625:2625:2625)) - (PORT datad (1838:1838:1838) (1929:1929:1929)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1982:1982:1982) (2048:2048:2048)) - (PORT datab (2103:2103:2103) (2239:2239:2239)) - (PORT datac (1465:1465:1465) (1540:1540:1540)) - (PORT datad (209:209:209) (246:246:246)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datab (2490:2490:2490) (2690:2690:2690)) - (PORT datac (2152:2152:2152) (2252:2252:2252)) - (PORT datad (1470:1470:1470) (1560:1560:1560)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (722:722:722)) - (PORT datac (1428:1428:1428) (1511:1511:1511)) - (PORT datad (659:659:659) (735:735:735)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT datac (590:590:590) (659:659:659)) - (PORT datad (661:661:661) (738:738:738)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT datab (1181:1181:1181) (1258:1258:1258)) - (PORT datac (1491:1491:1491) (1604:1604:1604)) - (PORT datad (1204:1204:1204) (1275:1275:1275)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT datab (1624:1624:1624) (1780:1780:1780)) - (PORT datad (1680:1680:1680) (1802:1802:1802)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2561:2561:2561) (2630:2630:2630)) - (PORT datab (2468:2468:2468) (2666:2666:2666)) - (PORT datac (1469:1469:1469) (1544:1544:1544)) - (PORT datad (1838:1838:1838) (1932:1932:1932)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (258:258:258) (308:308:308)) - (PORT datab (897:897:897) (907:907:907)) - (PORT datac (1280:1280:1280) (1332:1332:1332)) - (PORT datad (793:793:793) (839:839:839)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datab (1654:1654:1654) (1808:1808:1808)) - (PORT datad (1815:1815:1815) (1894:1894:1894)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (501:501:501)) - (PORT datad (247:247:247) (319:319:319)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1699:1699:1699) (1795:1795:1795)) - (PORT datab (1125:1125:1125) (1202:1202:1202)) - (PORT datac (896:896:896) (937:937:937)) - (PORT datad (1966:1966:1966) (2037:2037:2037)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1044:1044:1044) (1135:1135:1135)) - (PORT datad (1269:1269:1269) (1357:1357:1357)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1067:1067:1067)) - (PORT datab (1506:1506:1506) (1576:1576:1576)) - (PORT datac (1078:1078:1078) (1094:1094:1094)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1081:1081:1081)) - (PORT datab (741:741:741) (845:845:845)) - (PORT datac (909:909:909) (983:983:983)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (705:705:705) (809:809:809)) - (PORT datad (697:697:697) (796:796:796)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (681:681:681)) - (PORT datab (640:640:640) (663:663:663)) - (PORT datac (341:341:341) (362:362:362)) - (PORT datad (609:609:609) (621:621:621)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1625:1625:1625) (1667:1667:1667)) - (PORT datad (616:616:616) (648:648:648)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (922:922:922)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (1049:1049:1049) (1089:1089:1089)) - (PORT datad (1211:1211:1211) (1321:1321:1321)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (745:745:745) (845:845:845)) - (PORT datac (970:970:970) (1032:1032:1032)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT datab (1607:1607:1607) (1747:1747:1747)) - (PORT datad (1859:1859:1859) (1958:1958:1958)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (286:286:286)) - (PORT datab (1368:1368:1368) (1395:1395:1395)) - (PORT datac (1649:1649:1649) (1746:1746:1746)) - (PORT datad (1692:1692:1692) (1750:1750:1750)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datac (667:667:667) (737:737:737)) - (PORT datad (669:669:669) (753:753:753)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (1044:1044:1044) (1136:1136:1136)) - (PORT datad (1269:1269:1269) (1359:1359:1359)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2136:2136:2136) (2306:2306:2306)) - (PORT datab (1472:1472:1472) (1496:1496:1496)) - (PORT datac (1120:1120:1120) (1150:1150:1150)) - (PORT datad (648:648:648) (671:671:671)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1181:1181:1181)) - (PORT datab (899:899:899) (952:952:952)) - (PORT datac (1409:1409:1409) (1473:1473:1473)) - (PORT datad (637:637:637) (678:678:678)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1859:1859:1859) (1941:1941:1941)) - (PORT datab (1653:1653:1653) (1803:1803:1803)) - (PORT datac (1713:1713:1713) (1796:1796:1796)) - (PORT datad (879:879:879) (896:896:896)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT datab (1578:1578:1578) (1721:1721:1721)) - (PORT datac (1756:1756:1756) (1850:1850:1850)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1491:1491:1491)) - (PORT datab (1499:1499:1499) (1601:1601:1601)) - (PORT datac (1236:1236:1236) (1278:1278:1278)) - (PORT datad (1212:1212:1212) (1250:1250:1250)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (1120:1120:1120) (1175:1175:1175)) - (PORT datac (1695:1695:1695) (1735:1735:1735)) - (PORT datad (989:989:989) (1018:1018:1018)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (948:948:948)) - (PORT datab (683:683:683) (708:708:708)) - (PORT datac (2084:2084:2084) (2256:2256:2256)) - (PORT datad (909:909:909) (931:931:931)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1700:1700:1700) (1791:1791:1791)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (899:899:899) (937:937:937)) - (PORT datad (928:928:928) (989:989:989)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1659:1659:1659) (1811:1811:1811)) - (PORT datad (1814:1814:1814) (1891:1891:1891)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1700:1700:1700) (1795:1795:1795)) - (PORT datab (250:250:250) (298:298:298)) - (PORT datac (898:898:898) (934:934:934)) - (PORT datad (1153:1153:1153) (1208:1208:1208)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1678:1678:1678) (1695:1695:1695)) - (PORT datab (1374:1374:1374) (1396:1396:1396)) - (PORT datac (2514:2514:2514) (2557:2557:2557)) - (PORT datad (1128:1128:1128) (1145:1145:1145)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (940:940:940)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1113:1113:1113) (1189:1189:1189)) - (PORT datad (961:961:961) (1053:1053:1053)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (510:510:510)) - (PORT datab (706:706:706) (761:761:761)) - (PORT datad (892:892:892) (915:915:915)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1079:1079:1079)) - (PORT datac (670:670:670) (776:776:776)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (2272:2272:2272) (2458:2458:2458)) - (PORT datad (1247:1247:1247) (1340:1340:1340)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (677:677:677)) - (PORT datab (1376:1376:1376) (1393:1393:1393)) - (PORT datac (1649:1649:1649) (1659:1659:1659)) - (PORT datad (908:908:908) (928:928:928)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (938:938:938)) - (PORT datab (348:348:348) (377:377:377)) - (PORT datac (614:614:614) (637:637:637)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1325:1325:1325) (1382:1382:1382)) - (PORT datab (967:967:967) (991:991:991)) - (PORT datac (1402:1402:1402) (1542:1542:1542)) - (PORT datad (1180:1180:1180) (1240:1240:1240)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (260:260:260) (343:343:343)) - (PORT datac (234:234:234) (310:310:310)) - (PORT datad (391:391:391) (462:462:462)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (503:503:503)) - (PORT datab (1696:1696:1696) (1768:1768:1768)) - (PORT datac (1831:1831:1831) (1963:1963:1963)) - (PORT datad (780:780:780) (842:842:842)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (504:504:504)) - (PORT datab (1697:1697:1697) (1767:1767:1767)) - (PORT datac (1832:1832:1832) (1964:1964:1964)) - (PORT datad (781:781:781) (840:840:840)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (505:505:505)) - (PORT datab (1700:1700:1700) (1770:1770:1770)) - (PORT datac (1842:1842:1842) (1975:1975:1975)) - (PORT datad (787:787:787) (845:845:845)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1501:1501:1501)) - (PORT datab (641:641:641) (679:679:679)) - (PORT datac (647:647:647) (693:693:693)) - (PORT datad (648:648:648) (679:679:679)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (774:774:774)) - (PORT datab (1409:1409:1409) (1519:1519:1519)) - (PORT datac (1370:1370:1370) (1480:1480:1480)) - (PORT datad (682:682:682) (744:744:744)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1272:1272:1272)) - (PORT datab (969:969:969) (1014:1014:1014)) - (PORT datac (672:672:672) (779:779:779)) - (PORT datad (693:693:693) (794:794:794)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1407:1407:1407)) - (PORT datab (1154:1154:1154) (1254:1254:1254)) - (PORT datac (671:671:671) (779:779:779)) - (PORT datad (693:693:693) (794:794:794)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (2512:2512:2512) (2579:2579:2579)) - (PORT datab (239:239:239) (277:277:277)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1711:1711:1711) (1689:1689:1689)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (935:935:935)) - (PORT datab (348:348:348) (381:381:381)) - (PORT datad (336:336:336) (362:362:362)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1633:1633:1633) (1765:1765:1765)) - (PORT datab (1559:1559:1559) (1648:1648:1648)) - (PORT datac (1677:1677:1677) (1756:1756:1756)) - (PORT datad (1743:1743:1743) (1852:1852:1852)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1190:1190:1190)) - (PORT datab (1492:1492:1492) (1531:1531:1531)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (781:781:781) (835:835:835)) - (PORT datac (973:973:973) (1029:1029:1029)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1813:1813:1813) (1882:1882:1882)) - (PORT datab (1074:1074:1074) (1139:1139:1139)) - (PORT datac (1722:1722:1722) (1803:1803:1803)) - (PORT datad (217:217:217) (256:256:256)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1474:1474:1474)) - (PORT datad (1994:1994:1994) (2071:2071:2071)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1484:1484:1484)) - (PORT datab (854:854:854) (902:902:902)) - (PORT datac (909:909:909) (971:971:971)) - (PORT datad (616:616:616) (647:647:647)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1296:1296:1296)) - (PORT datab (266:266:266) (314:314:314)) - (PORT datac (928:928:928) (983:983:983)) - (PORT datad (1184:1184:1184) (1243:1243:1243)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (591:591:591)) - (PORT datab (1349:1349:1349) (1470:1470:1470)) - (PORT datac (808:808:808) (820:820:820)) - (PORT datad (834:834:834) (910:910:910)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1860:1860:1860) (1945:1945:1945)) - (PORT datab (1656:1656:1656) (1813:1813:1813)) - (PORT datac (1723:1723:1723) (1804:1804:1804)) - (PORT datad (880:880:880) (899:899:899)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT datab (1616:1616:1616) (1771:1771:1771)) - (PORT datac (1389:1389:1389) (1456:1456:1456)) - (PORT datad (1311:1311:1311) (1374:1374:1374)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (2076:2076:2076) (2209:2209:2209)) - (PORT datad (933:933:933) (1039:1039:1039)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (985:985:985)) - (PORT datab (1376:1376:1376) (1394:1394:1394)) - (PORT datac (1649:1649:1649) (1659:1659:1659)) - (PORT datad (1168:1168:1168) (1213:1213:1213)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (935:935:935)) - (PORT datab (698:698:698) (760:760:760)) - (PORT datac (915:915:915) (959:959:959)) - (PORT datad (661:661:661) (719:719:719)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1224:1224:1224)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (873:873:873) (934:934:934)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1059:1059:1059)) - (PORT datab (1999:1999:1999) (2042:2042:2042)) - (PORT datac (1001:1001:1001) (1029:1029:1029)) - (PORT datad (1097:1097:1097) (1148:1148:1148)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) - (DELAY - (ABSOLUTE - (PORT dataa (2428:2428:2428) (2599:2599:2599)) - (PORT datab (1208:1208:1208) (1296:1296:1296)) - (PORT datac (1399:1399:1399) (1508:1508:1508)) - (PORT datad (555:555:555) (574:574:574)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (509:509:509)) - (PORT datab (767:767:767) (841:841:841)) - (PORT datac (1069:1069:1069) (1085:1085:1085)) - (PORT datad (787:787:787) (850:850:850)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2204:2204:2204) (2398:2398:2398)) - (PORT datab (686:686:686) (707:707:707)) - (PORT datac (835:835:835) (875:875:875)) - (PORT datad (1872:1872:1872) (2005:2005:2005)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1772:1772:1772) (1872:1872:1872)) - (PORT datab (739:739:739) (800:800:800)) - (PORT datac (1861:1861:1861) (1915:1915:1915)) - (PORT datad (1607:1607:1607) (1753:1753:1753)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (894:894:894)) - (PORT datab (1876:1876:1876) (2012:2012:2012)) - (PORT datac (328:328:328) (351:351:351)) - (PORT datad (1690:1690:1690) (1763:1763:1763)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (1013:1013:1013)) - (PORT datab (1893:1893:1893) (2038:2038:2038)) - (PORT datac (2174:2174:2174) (2358:2358:2358)) - (PORT datad (955:955:955) (995:995:995)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (1677:1677:1677) (1729:1729:1729)) - (PORT datad (2190:2190:2190) (2227:2227:2227)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_ir_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1356:1356:1356)) - (PORT datab (662:662:662) (720:720:720)) - (PORT datac (856:856:856) (884:884:884)) - (PORT datad (846:846:846) (874:874:874)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1482:1482:1482)) - (PORT datab (1494:1494:1494) (1558:1558:1558)) - (PORT datac (1227:1227:1227) (1257:1257:1257)) - (PORT datad (932:932:932) (1002:1002:1002)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (897:897:897) (961:961:961)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1756:1756:1756) (1851:1851:1851)) - (PORT datab (1657:1657:1657) (1809:1809:1809)) - (PORT datad (1812:1812:1812) (1893:1893:1893)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (994:994:994) (1075:1075:1075)) - (PORT datac (1310:1310:1310) (1404:1404:1404)) - (PORT datad (914:914:914) (958:958:958)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (2680:2680:2680) (2765:2765:2765)) - (PORT datab (751:751:751) (781:781:781)) - (PORT datac (998:998:998) (1052:1052:1052)) - (PORT datad (890:890:890) (939:939:939)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1052:1052:1052)) - (PORT datac (1080:1080:1080) (1095:1095:1095)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datab (1557:1557:1557) (1643:1643:1643)) - (PORT datac (1196:1196:1196) (1284:1284:1284)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (994:994:994) (1076:1076:1076)) - (PORT datab (1450:1450:1450) (1484:1484:1484)) - (PORT datac (1313:1313:1313) (1404:1404:1404)) - (PORT datad (917:917:917) (957:957:957)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1288:1288:1288)) - (PORT datab (627:627:627) (676:676:676)) - (PORT datac (1171:1171:1171) (1187:1187:1187)) - (PORT datad (1954:1954:1954) (2068:2068:2068)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1328:1328:1328)) - (PORT datab (1374:1374:1374) (1512:1512:1512)) - (PORT datac (2247:2247:2247) (2354:2354:2354)) - (PORT datad (2399:2399:2399) (2556:2556:2556)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (885:885:885)) - (PORT datab (1869:1869:1869) (2005:2005:2005)) - (PORT datac (325:325:325) (347:347:347)) - (PORT datad (1684:1684:1684) (1756:1756:1756)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1393:1393:1393)) - (PORT datab (650:650:650) (695:695:695)) - (PORT datac (2228:2228:2228) (2301:2301:2301)) - (PORT datad (2014:2014:2014) (2108:2108:2108)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1327:1327:1327)) - (PORT datab (1429:1429:1429) (1544:1544:1544)) - (PORT datac (2248:2248:2248) (2352:2352:2352)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (810:810:810) (838:838:838)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1654:1654:1654) (1725:1725:1725)) - (PORT datac (907:907:907) (930:930:930)) - (PORT datad (1391:1391:1391) (1460:1460:1460)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1571:1571:1571) (1642:1642:1642)) - (PORT datab (2001:2001:2001) (2042:2042:2042)) - (PORT datac (1133:1133:1133) (1159:1159:1159)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2683:2683:2683) (2764:2764:2764)) - (PORT datab (1030:1030:1030) (1061:1061:1061)) - (PORT datac (798:798:798) (876:876:876)) - (PORT datad (715:715:715) (740:740:740)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (624:624:624)) - (PORT datab (789:789:789) (834:834:834)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (1008:1008:1008)) - (PORT datab (1184:1184:1184) (1250:1250:1250)) - (PORT datac (1904:1904:1904) (1966:1966:1966)) - (PORT datad (644:644:644) (669:669:669)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1681:1681:1681) (1756:1756:1756)) - (PORT datab (574:574:574) (580:580:580)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (352:352:352) (375:375:375)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (418:418:418)) - (PORT datab (925:925:925) (988:988:988)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1103:1103:1103) (1103:1103:1103)) + (PORT dataa (972:972:972) (1071:1071:1071)) + (PORT datac (977:977:977) (1074:1074:1074)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datab (1374:1374:1374) (1494:1494:1494)) - (PORT datad (976:976:976) (1058:1058:1058)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (657:657:657)) - (PORT datab (814:814:814) (879:879:879)) - (PORT datac (1743:1743:1743) (1807:1807:1807)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1255:1255:1255)) - (PORT datab (805:805:805) (887:887:887)) - (PORT datac (798:798:798) (880:880:880)) - (PORT datad (889:889:889) (937:937:937)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1253:1253:1253) (1284:1284:1284)) - (PORT datac (1036:1036:1036) (1054:1054:1054)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (909:909:909)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (656:656:656)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (353:353:353) (384:384:384)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT datab (1558:1558:1558) (1645:1645:1645)) - (PORT datac (1678:1678:1678) (1754:1754:1754)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1468:1468:1468)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1209:1209:1209) (1317:1317:1317)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1935:1935:1935) (2103:2103:2103)) - (PORT datac (1169:1169:1169) (1247:1247:1247)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (295:295:295)) - (PORT datab (1549:1549:1549) (1663:1663:1663)) - (PORT datac (1712:1712:1712) (1799:1799:1799)) - (PORT datad (1313:1313:1313) (1326:1326:1326)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1524:1524:1524) (1519:1519:1519)) - (PORT datab (1191:1191:1191) (1249:1249:1249)) - (PORT datac (630:630:630) (682:682:682)) - (PORT datad (632:632:632) (687:687:687)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1044:1044:1044) (1133:1133:1133)) - (PORT datad (1271:1271:1271) (1354:1354:1354)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2306:2306:2306) (2424:2424:2424)) - (PORT datac (1346:1346:1346) (1529:1529:1529)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1886:1886:1886) (2000:2000:2000)) - (PORT datab (1612:1612:1612) (1752:1752:1752)) - (PORT datac (1469:1469:1469) (1530:1530:1530)) - (PORT datad (1053:1053:1053) (1100:1100:1100)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (658:658:658)) - (PORT datab (1360:1360:1360) (1377:1377:1377)) - (PORT datac (631:631:631) (639:639:639)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1212:1212:1212)) - (PORT datab (661:661:661) (716:716:716)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (595:595:595) (628:628:628)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1557:1557:1557)) - (PORT ena (1244:1244:1244) (1252:1252:1252)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1539:1539:1539)) - (PORT asdata (702:702:702) (770:770:770)) - (PORT clrn (1579:1579:1579) (1556:1556:1556)) - (PORT ena (1442:1442:1442) (1450:1450:1450)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (655:655:655) (727:727:727)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT asdata (567:567:567) (643:643:643)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (333:333:333)) - (PORT datad (655:655:655) (722:722:722)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1644:1644:1644)) - (PORT datac (1464:1464:1464) (1503:1503:1503)) - (PORT datad (1184:1184:1184) (1237:1237:1237)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (278:278:278)) - (PORT datab (221:221:221) (268:268:268)) - (PORT datac (996:996:996) (1082:1082:1082)) - (PORT datad (1499:1499:1499) (1549:1549:1549)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1276:1276:1276)) - (PORT datab (1869:1869:1869) (1945:1945:1945)) - (PORT datac (1029:1029:1029) (1095:1095:1095)) - (PORT datad (1021:1021:1021) (1078:1078:1078)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1764:1764:1764) (1856:1856:1856)) - (PORT datab (654:654:654) (690:690:690)) - (PORT datad (1598:1598:1598) (1743:1743:1743)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (958:958:958)) - (PORT datab (1244:1244:1244) (1298:1298:1298)) - (PORT datac (827:827:827) (870:870:870)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1017:1017:1017)) - (PORT datab (993:993:993) (1040:1040:1040)) - (PORT datac (2018:2018:2018) (2124:2124:2124)) - (PORT datad (1484:1484:1484) (1600:1600:1600)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (1506:1506:1506) (1597:1597:1597)) - (PORT datac (1719:1719:1719) (1859:1859:1859)) - (PORT datad (646:646:646) (663:663:663)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (658:658:658)) - (PORT datab (1777:1777:1777) (1839:1839:1839)) - (PORT datac (901:901:901) (951:951:951)) - (PORT datad (577:577:577) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (640:640:640)) - (PORT datab (656:656:656) (693:693:693)) - (PORT datac (1397:1397:1397) (1513:1513:1513)) - (PORT datad (1771:1771:1771) (1867:1867:1867)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (674:674:674)) - (PORT datab (1187:1187:1187) (1225:1225:1225)) - (PORT datac (905:905:905) (945:945:945)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (647:647:647)) - (PORT datab (1785:1785:1785) (1851:1851:1851)) - (PORT datac (843:843:843) (884:884:884)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datab (2599:2599:2599) (2784:2784:2784)) - (PORT datac (2013:2013:2013) (2151:2151:2151)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1681:1681:1681) (1696:1696:1696)) - (PORT datab (1665:1665:1665) (1691:1691:1691)) - (PORT datac (1340:1340:1340) (1357:1357:1357)) - (PORT datad (1137:1137:1137) (1157:1157:1157)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (966:966:966)) - (PORT datab (1226:1226:1226) (1311:1311:1311)) - (PORT datac (667:667:667) (748:748:748)) - (PORT datad (672:672:672) (721:721:721)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (763:763:763)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1172:1172:1172) (1211:1211:1211)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1266:1266:1266) (1320:1320:1320)) - (PORT datab (1090:1090:1090) (1146:1146:1146)) - (PORT datac (1387:1387:1387) (1457:1457:1457)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1553:1553:1553)) - (PORT datab (1507:1507:1507) (1626:1626:1626)) - (PORT datac (1410:1410:1410) (1520:1520:1520)) - (PORT datad (1406:1406:1406) (1453:1453:1453)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (640:640:640) (681:681:681)) - (PORT datac (1761:1761:1761) (1841:1841:1841)) - (PORT datad (650:650:650) (681:681:681)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT datac (1195:1195:1195) (1279:1279:1279)) - (PORT datad (1192:1192:1192) (1245:1245:1245)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1453:1453:1453) (1558:1558:1558)) - (PORT datab (1151:1151:1151) (1192:1192:1192)) - (PORT datac (647:647:647) (693:693:693)) - (PORT datad (1478:1478:1478) (1588:1588:1588)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT datac (1200:1200:1200) (1285:1285:1285)) - (PORT datad (1195:1195:1195) (1248:1248:1248)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (698:698:698)) - (PORT datab (247:247:247) (290:290:290)) - (PORT datac (913:913:913) (969:969:969)) - (PORT datad (845:845:845) (863:863:863)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (966:966:966)) - (PORT datab (897:897:897) (948:948:948)) - (PORT datac (882:882:882) (919:919:919)) - (PORT datad (593:593:593) (606:606:606)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1541:1541:1541)) - (PORT datad (1222:1222:1222) (1311:1311:1311)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (655:655:655)) - (PORT datab (821:821:821) (865:865:865)) - (PORT datac (1104:1104:1104) (1130:1130:1130)) - (PORT datad (2384:2384:2384) (2430:2430:2430)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1585:1585:1585) (1562:1562:1562)) - (PORT ena (1197:1197:1197) (1197:1197:1197)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (288:288:288)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1585:1585:1585) (1562:1562:1562)) - (PORT ena (1171:1171:1171) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (882:882:882) (959:959:959)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (248:248:248) (331:331:331)) - (PORT datac (1026:1026:1026) (1073:1073:1073)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) @@ -4817,16 +3209,16 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clk (1526:1526:1526) (1530:1530:1530)) + (PORT asdata (1127:1127:1127) (1165:1165:1165)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1223:1223:1223) (1226:1226:1226)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -4835,8 +3227,8 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (217:217:217) (293:293:293)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -4845,10 +3237,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT clk (1526:1526:1526) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1223:1223:1223) (1226:1226:1226)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -4863,10 +3255,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1541:1541:1541)) - (PORT asdata (566:566:566) (642:642:642)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1280:1280:1280) (1296:1296:1296)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (568:568:568) (646:646:646)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1254:1254:1254) (1275:1275:1275)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -4881,9 +3273,9 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1120:1120:1120) (1187:1187:1187)) - (PORT datab (249:249:249) (332:332:332)) - (PORT datad (1382:1382:1382) (1442:1442:1442)) + (PORT dataa (1160:1160:1160) (1246:1246:1246)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datad (435:435:435) (499:499:499)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -4891,17 +3283,109 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1610:1610:1610) (1767:1767:1767)) + (PORT datab (1245:1245:1245) (1336:1336:1336)) + (PORT datac (2396:2396:2396) (2519:2519:2519)) + (PORT datad (1247:1247:1247) (1385:1385:1385)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1363:1363:1363)) + (PORT datac (1559:1559:1559) (1714:1714:1714)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (1505:1505:1505) (1643:1643:1643)) + (PORT datad (1810:1810:1810) (1897:1897:1897)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (907:907:907) (979:979:979)) + (PORT datad (1870:1870:1870) (2002:2002:2002)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1294:1294:1294)) + (PORT datab (1229:1229:1229) (1313:1313:1313)) + (PORT datac (708:708:708) (779:779:779)) + (PORT datad (243:243:243) (296:296:296)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (993:993:993) (1073:1073:1073)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (1079:1079:1079) (1095:1095:1095)) - (PORT datad (1469:1469:1469) (1538:1538:1538)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (729:729:729) (769:769:769)) + (PORT datac (2939:2939:2939) (3072:3072:3072)) + (PORT datad (1124:1124:1124) (1159:1159:1159)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datab (1571:1571:1571) (1697:1697:1697)) + (PORT datac (1289:1289:1289) (1402:1402:1402)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datac (1052:1052:1052) (1157:1157:1157)) + (PORT datad (2076:2076:2076) (2218:2218:2218)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -4909,91 +3393,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) + (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT dataa (1309:1309:1309) (1371:1371:1371)) - (PORT datab (927:927:927) (1024:1024:1024)) - (PORT datac (1164:1164:1164) (1225:1225:1225)) - (PORT datad (1430:1430:1430) (1462:1462:1462)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1845:1845:1845)) - (PORT datab (1652:1652:1652) (1803:1803:1803)) - (PORT datac (1044:1044:1044) (1103:1103:1103)) - (PORT datad (1815:1815:1815) (1893:1893:1893)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datab (1607:1607:1607) (1746:1746:1746)) - (PORT datad (1856:1856:1856) (1958:1958:1958)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (311:311:311)) - (PORT datab (1677:1677:1677) (1826:1826:1826)) - (PORT datac (1288:1288:1288) (1378:1378:1378)) - (PORT datad (2871:2871:2871) (2927:2927:2927)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (312:312:312)) - (PORT datab (927:927:927) (1024:1024:1024)) - (PORT datac (1164:1164:1164) (1225:1225:1225)) - (PORT datad (1753:1753:1753) (1784:1784:1784)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1179:1179:1179)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1409:1409:1409) (1398:1398:1398)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datac (1484:1484:1484) (1559:1559:1559)) + (PORT datad (1217:1217:1217) (1295:1295:1295)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -5001,41 +3405,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) + (INSTANCE z80_\|execute_\|ctl_mRead\~3) (DELAY (ABSOLUTE - (PORT dataa (1622:1622:1622) (1658:1658:1658)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT dataa (448:448:448) (509:509:509)) - (PORT datad (602:602:602) (624:624:624)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (1454:1454:1454) (1538:1538:1538)) - (PORT datab (1435:1435:1435) (1471:1471:1471)) - (PORT datac (1347:1347:1347) (1529:1529:1529)) - (PORT datad (2534:2534:2534) (2622:2622:2622)) + (PORT dataa (1558:1558:1558) (1587:1587:1587)) + (PORT datab (725:725:725) (762:762:762)) + (PORT datac (2943:2943:2943) (3066:3066:3066)) + (PORT datad (1123:1123:1123) (1156:1156:1156)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -5043,337 +3419,121 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1194:1194:1194)) + (PORT datab (679:679:679) (714:714:714)) + (PORT datac (1449:1449:1449) (1513:1513:1513)) + (PORT datad (1129:1129:1129) (1153:1153:1153)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1370:1370:1370)) + (PORT datab (1689:1689:1689) (1864:1864:1864)) + (PORT datac (1228:1228:1228) (1340:1340:1340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1298:1298:1298)) + (PORT datac (1496:1496:1496) (1565:1565:1565)) + (PORT datad (2598:2598:2598) (2706:2706:2706)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (1455:1455:1455) (1620:1620:1620)) + (PORT datad (1251:1251:1251) (1383:1383:1383)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1558:1558:1558)) + (PORT datab (1277:1277:1277) (1342:1342:1342)) + (PORT datac (609:609:609) (624:624:624)) + (PORT datad (1252:1252:1252) (1367:1367:1367)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2130:2130:2130) (2347:2347:2347)) + (PORT datab (1568:1568:1568) (1699:1699:1699)) + (PORT datac (891:891:891) (940:940:940)) + (PORT datad (2016:2016:2016) (2098:2098:2098)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|decode_state_\|DFFE_instED) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (980:980:980) (1001:1001:1001)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (968:968:968) (972:972:972)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (INSTANCE z80_\|pla_decode_\|Equal6\~0) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (447:447:447)) - (PORT datab (862:862:862) (915:915:915)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1642:1642:1642)) - (PORT datab (265:265:265) (310:310:310)) - (PORT datac (1461:1461:1461) (1499:1499:1499)) - (PORT datad (1184:1184:1184) (1243:1243:1243)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1788:1788:1788)) - (PORT datab (243:243:243) (287:287:287)) - (PORT datac (1764:1764:1764) (1827:1827:1827)) - (PORT datad (810:810:810) (866:866:866)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (489:489:489)) - (PORT datab (1270:1270:1270) (1351:1351:1351)) - (PORT datac (1326:1326:1326) (1377:1377:1377)) - (PORT datad (651:651:651) (674:674:674)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT datab (654:654:654) (678:678:678)) - (PORT datac (852:852:852) (873:873:873)) - (PORT datad (866:866:866) (881:881:881)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (510:510:510)) - (PORT datab (1700:1700:1700) (1774:1774:1774)) - (PORT datac (1844:1844:1844) (1971:1971:1971)) - (PORT datad (788:788:788) (851:851:851)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT datab (1461:1461:1461) (1510:1510:1510)) - (PORT datac (1183:1183:1183) (1237:1237:1237)) - (PORT datad (1434:1434:1434) (1514:1514:1514)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (855:855:855)) - (PORT datab (768:768:768) (840:840:840)) - (PORT datac (1827:1827:1827) (1972:1972:1972)) - (PORT datad (1687:1687:1687) (1760:1760:1760)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (928:928:928)) - (PORT datab (1029:1029:1029) (1113:1113:1113)) - (PORT datac (1460:1460:1460) (1500:1500:1500)) - (PORT datad (1502:1502:1502) (1555:1555:1555)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (960:960:960)) - (PORT datab (880:880:880) (969:969:969)) - (PORT datac (1051:1051:1051) (1088:1088:1088)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT datab (631:631:631) (694:694:694)) - (PORT datac (802:802:802) (833:833:833)) - (PORT datad (852:852:852) (894:894:894)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1645:1645:1645)) - (PORT datac (1461:1461:1461) (1503:1503:1503)) - (PORT datad (1184:1184:1184) (1243:1243:1243)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1495:1495:1495) (1540:1540:1540)) - (PORT datab (958:958:958) (1015:1015:1015)) - (PORT datac (1200:1200:1200) (1255:1255:1255)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1240:1240:1240)) - (PORT datab (660:660:660) (687:687:687)) - (PORT datac (1667:1667:1667) (1700:1700:1700)) - (PORT datad (907:907:907) (984:984:984)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1812:1812:1812) (1880:1880:1880)) - (PORT datab (1075:1075:1075) (1143:1143:1143)) - (PORT datac (1721:1721:1721) (1798:1798:1798)) - (PORT datad (218:218:218) (257:257:257)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2132:2132:2132) (2307:2307:2307)) - (PORT datab (2626:2626:2626) (2718:2718:2718)) - (PORT datac (1370:1370:1370) (1475:1475:1475)) - (PORT datad (874:874:874) (899:899:899)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2265:2265:2265) (2343:2343:2343)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (623:623:623) (663:663:663)) - (PORT datad (1014:1014:1014) (1053:1053:1053)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT datab (1599:1599:1599) (1667:1667:1667)) - (PORT datac (1208:1208:1208) (1265:1265:1265)) - (PORT datad (1110:1110:1110) (1156:1156:1156)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1318:1318:1318) (1375:1375:1375)) - (PORT datab (970:970:970) (996:996:996)) - (PORT datac (1388:1388:1388) (1527:1527:1527)) - (PORT datad (1184:1184:1184) (1246:1246:1246)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (928:928:928)) - (PORT datab (1028:1028:1028) (1113:1113:1113)) - (PORT datac (1466:1466:1466) (1505:1505:1505)) - (PORT datad (1497:1497:1497) (1547:1547:1547)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (834:834:834)) - (PORT datab (606:606:606) (630:630:630)) - (PORT datac (1624:1624:1624) (1671:1671:1671)) - (PORT datad (1597:1597:1597) (1618:1618:1618)) + (PORT dataa (1738:1738:1738) (1849:1849:1849)) + (PORT datab (985:985:985) (1061:1061:1061)) + (PORT datac (680:680:680) (745:745:745)) + (PORT datad (872:872:872) (922:922:922)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -5383,12 +3543,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (703:703:703)) - (PORT datac (1119:1119:1119) (1126:1126:1126)) - (PORT datad (794:794:794) (865:865:865)) + (PORT dataa (1176:1176:1176) (1196:1196:1196)) + (PORT datac (1207:1207:1207) (1285:1285:1285)) + (PORT datad (808:808:808) (829:829:829)) (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -5397,1858 +3557,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (2137:2137:2137) (2307:2307:2307)) - (PORT datab (686:686:686) (711:711:711)) - (PORT datac (1044:1044:1044) (1121:1121:1121)) - (PORT datad (863:863:863) (904:904:904)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (407:407:407)) - (PORT datab (389:389:389) (421:421:421)) - (PORT datac (657:657:657) (706:706:706)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1421:1421:1421) (1449:1449:1449)) - (PORT datab (1932:1932:1932) (2005:2005:2005)) - (PORT datac (896:896:896) (938:938:938)) - (PORT datad (226:226:226) (261:261:261)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (3083:3083:3083) (3178:3178:3178)) - (PORT datab (849:849:849) (890:890:890)) - (PORT datac (1445:1445:1445) (1544:1544:1544)) - (PORT datad (1991:1991:1991) (2046:2046:2046)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datab (1812:1812:1812) (1916:1916:1916)) - (PORT datad (2317:2317:2317) (2381:2381:2381)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (910:910:910)) - (PORT datab (393:393:393) (426:426:426)) - (PORT datac (1765:1765:1765) (1827:1827:1827)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1249:1249:1249)) - (PORT datab (1776:1776:1776) (1843:1843:1843)) - (PORT datac (593:593:593) (619:619:619)) - (PORT datad (613:613:613) (635:635:635)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (894:894:894) (917:917:917)) - (PORT datac (935:935:935) (977:977:977)) - (PORT datad (586:586:586) (595:595:595)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1910:1910:1910) (1994:1994:1994)) - (PORT datab (1648:1648:1648) (1797:1797:1797)) - (PORT datac (611:611:611) (649:649:649)) - (PORT datad (1744:1744:1744) (1826:1826:1826)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (901:901:901)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (2016:2016:2016) (2128:2128:2128)) - (PORT datad (1098:1098:1098) (1111:1111:1111)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~14) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (275:275:275)) - (PORT datab (264:264:264) (310:310:310)) - (PORT datac (339:339:339) (366:366:366)) - (PORT datad (194:194:194) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1218:1218:1218)) - (PORT datab (662:662:662) (682:682:682)) - (PORT datac (928:928:928) (996:996:996)) - (PORT datad (1139:1139:1139) (1210:1210:1210)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1791:1791:1791)) - (PORT datab (1366:1366:1366) (1397:1397:1397)) - (PORT datac (1763:1763:1763) (1830:1830:1830)) - (PORT datad (219:219:219) (255:255:255)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (624:624:624) (657:657:657)) - (PORT datad (827:827:827) (857:857:857)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1250:1250:1250)) - (PORT datab (366:366:366) (399:399:399)) - (PORT datac (1834:1834:1834) (1907:1907:1907)) - (PORT datad (603:603:603) (616:616:616)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2560:2560:2560) (2631:2631:2631)) - (PORT datab (2467:2467:2467) (2664:2664:2664)) - (PORT datad (1837:1837:1837) (1931:1931:1931)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1916:1916:1916) (2018:2018:2018)) - (PORT datab (894:894:894) (927:927:927)) - (PORT datac (1604:1604:1604) (1723:1723:1723)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1703:1703:1703) (1792:1792:1792)) - (PORT datab (1079:1079:1079) (1158:1158:1158)) - (PORT datac (897:897:897) (935:935:935)) - (PORT datad (225:225:225) (260:260:260)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (978:978:978)) - (PORT datab (1423:1423:1423) (1444:1444:1444)) - (PORT datac (618:618:618) (657:657:657)) - (PORT datad (823:823:823) (839:839:839)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1910:1910:1910) (1993:1993:1993)) - (PORT datab (1647:1647:1647) (1796:1796:1796)) - (PORT datac (610:610:610) (648:648:648)) - (PORT datad (1744:1744:1744) (1826:1826:1826)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2257:2257:2257) (2334:2334:2334)) - (PORT datab (879:879:879) (911:911:911)) - (PORT datac (1573:1573:1573) (1705:1705:1705)) - (PORT datad (1688:1688:1688) (1747:1747:1747)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (940:940:940)) - (PORT datab (1609:1609:1609) (1651:1651:1651)) - (PORT datac (1191:1191:1191) (1251:1251:1251)) - (PORT datad (1658:1658:1658) (1714:1714:1714)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (796:796:796)) - (PORT datab (1599:1599:1599) (1668:1668:1668)) - (PORT datac (1208:1208:1208) (1265:1265:1265)) - (PORT datad (1111:1111:1111) (1156:1156:1156)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2134:2134:2134) (2303:2303:2303)) - (PORT datab (1470:1470:1470) (1496:1496:1496)) - (PORT datac (1118:1118:1118) (1150:1150:1150)) - (PORT datad (645:645:645) (670:670:670)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (988:988:988)) - (PORT datab (557:557:557) (587:587:587)) - (PORT datac (569:569:569) (575:575:575)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (221:221:221) (250:250:250)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (956:956:956)) - (PORT datab (691:691:691) (757:757:757)) - (PORT datac (1338:1338:1338) (1342:1342:1342)) - (PORT datad (1183:1183:1183) (1212:1212:1212)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (954:954:954)) - (PORT datab (1459:1459:1459) (1512:1512:1512)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (919:919:919)) - (PORT datab (689:689:689) (761:761:761)) - (PORT datac (320:320:320) (344:344:344)) - (PORT datad (842:842:842) (871:871:871)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (686:686:686)) - (PORT datab (895:895:895) (931:931:931)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (882:882:882) (910:910:910)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (506:506:506)) - (PORT datab (1099:1099:1099) (1115:1115:1115)) - (PORT datac (742:742:742) (814:814:814)) - (PORT datad (730:730:730) (803:803:803)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (659:659:659)) - (PORT datab (660:660:660) (693:693:693)) - (PORT datac (576:576:576) (604:604:604)) - (PORT datad (663:663:663) (683:683:683)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (891:891:891)) - (PORT datab (616:616:616) (645:645:645)) - (PORT datac (1506:1506:1506) (1571:1571:1571)) - (PORT datad (192:192:192) (225:225:225)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (899:899:899) (928:928:928)) - (PORT datac (570:570:570) (592:592:592)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (660:660:660)) - (PORT datab (1247:1247:1247) (1277:1277:1277)) - (PORT datad (874:874:874) (919:919:919)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1236:1236:1236)) - (PORT datab (638:638:638) (670:670:670)) - (PORT datac (200:200:200) (236:236:236)) - (PORT datad (2384:2384:2384) (2430:2430:2430)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (835:835:835)) - (PORT datab (590:590:590) (599:599:599)) - (PORT datac (836:836:836) (870:870:870)) - (PORT datad (988:988:988) (1049:1049:1049)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1280:1280:1280) (1296:1296:1296)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (235:235:235) (312:312:312)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (340:340:340)) - (PORT datad (234:234:234) (311:311:311)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (824:824:824) (842:842:842)) - (PORT datac (202:202:202) (240:240:240)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (1866:1866:1866) (2020:2020:2020)) - (PORT datac (3074:3074:3074) (3300:3300:3300)) - (PORT datad (2568:2568:2568) (2680:2680:2680)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (843:843:843) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (373:373:373)) - (PORT datab (291:291:291) (383:383:383)) - (PORT datad (249:249:249) (334:334:334)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (3310:3310:3310) (3637:3637:3637)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (302:302:302)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (240:240:240) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (375:375:375) (441:441:441)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (224:224:224) (304:304:304)) - (PORT datad (228:228:228) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (225:225:225) (304:304:304)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (346:346:346)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (225:225:225) (308:308:308)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (368:368:368)) - (PORT datab (277:277:277) (367:367:367)) - (PORT datad (249:249:249) (333:333:333)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (374:374:374)) - (PORT datab (293:293:293) (386:386:386)) - (PORT datad (250:250:250) (330:330:330)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (377:377:377)) - (PORT datab (289:289:289) (381:381:381)) - (PORT datad (247:247:247) (326:326:326)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (373:373:373)) - (PORT datab (292:292:292) (384:384:384)) - (PORT datad (250:250:250) (329:329:329)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (373:373:373)) - (PORT datab (276:276:276) (369:369:369)) - (PORT datac (384:384:384) (445:445:445)) - (PORT datad (3313:3313:3313) (3645:3645:3645)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (368:368:368)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1497:1497:1497) (1608:1608:1608)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (3641:3641:3641) (3987:3987:3987)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (703:703:703) (765:765:765)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (613:613:613) (718:718:718)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (1312:1312:1312) (1370:1370:1370)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (PORT ena (1685:1685:1685) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (1237:1237:1237) (1318:1318:1318)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (1368:1368:1368) (1443:1443:1443)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (PORT ena (1425:1425:1425) (1453:1453:1453)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (1184:1184:1184) (1233:1233:1233)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (PORT ena (1425:1425:1425) (1453:1453:1453)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (608:608:608) (699:699:699)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (PORT ena (1425:1425:1425) (1453:1453:1453)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (1274:1274:1274) (1331:1331:1331)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (416:416:416)) - (PORT datab (930:930:930) (1010:1010:1010)) - (PORT datac (251:251:251) (336:336:336)) - (PORT datad (944:944:944) (1019:1019:1019)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (879:879:879)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (927:927:927) (986:986:986)) - (PORT datad (264:264:264) (344:344:344)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (422:422:422)) - (PORT datab (985:985:985) (1056:1056:1056)) - (PORT datad (264:264:264) (344:344:344)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (985:985:985)) - (PORT datab (960:960:960) (1023:1023:1023)) - (PORT datad (755:755:755) (838:838:838)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (311:311:311) (327:327:327)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (692:692:692)) - (PORT datab (3347:3347:3347) (3682:3682:3682)) - (PORT datac (1498:1498:1498) (1609:1609:1609)) - (PORT datad (185:185:185) (215:215:215)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (714:714:714)) - (PORT datab (877:877:877) (947:947:947)) - (PORT datad (704:704:704) (775:775:775)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (795:795:795)) - (PORT datab (791:791:791) (877:877:877)) - (PORT datac (707:707:707) (797:797:797)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (814:814:814)) - (PORT datad (750:750:750) (828:828:828)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (717:717:717)) - (PORT datad (699:699:699) (766:766:766)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (PORT ena (1489:1489:1489) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (409:409:409)) - (PORT datab (677:677:677) (741:741:741)) - (PORT datac (912:912:912) (970:970:970)) - (PORT datad (268:268:268) (348:348:348)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (690:690:690)) - (PORT datab (762:762:762) (850:850:850)) - (PORT datac (182:182:182) (219:219:219)) - (PORT datad (1129:1129:1129) (1155:1155:1155)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (436:436:436)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1901:1901:1901) (2085:2085:2085)) - (PORT datab (1495:1495:1495) (1563:1563:1563)) - (PORT datad (1153:1153:1153) (1262:1262:1262)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1931:1931:1931) (1907:1907:1907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (949:949:949) (997:997:997)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) - (PORT asdata (568:568:568) (646:646:646)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (728:728:728)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1278:1278:1278) (1382:1382:1382)) - (PORT datab (977:977:977) (1078:1078:1078)) - (PORT datac (624:624:624) (676:676:676)) - (PORT datad (886:886:886) (918:918:918)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1916:1916:1916) (2016:2016:2016)) - (PORT datab (1192:1192:1192) (1204:1204:1204)) - (PORT datac (1608:1608:1608) (1722:1722:1722)) - (PORT datad (856:856:856) (886:886:886)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1916:1916:1916) (2016:2016:2016)) - (PORT datab (893:893:893) (925:925:925)) - (PORT datac (1608:1608:1608) (1721:1721:1721)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1915:1915:1915) (2019:2019:2019)) - (PORT datab (1746:1746:1746) (1780:1780:1780)) - (PORT datac (1605:1605:1605) (1722:1722:1722)) - (PORT datad (856:856:856) (890:890:890)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (300:300:300)) - (PORT datac (256:256:256) (311:311:311)) - (PORT datad (245:245:245) (296:296:296)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (667:667:667)) - (PORT datac (1675:1675:1675) (1746:1746:1746)) - (PORT datad (1137:1137:1137) (1176:1176:1176)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (683:683:683)) - (PORT datac (621:621:621) (640:640:640)) - (PORT datad (1221:1221:1221) (1279:1279:1279)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (700:700:700)) - (PORT datab (1445:1445:1445) (1504:1504:1504)) - (PORT datac (586:586:586) (606:606:606)) - (PORT datad (1117:1117:1117) (1138:1138:1138)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (686:686:686)) - (PORT datab (939:939:939) (980:980:980)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (887:887:887) (909:909:909)) + (PORT dataa (1733:1733:1733) (1843:1843:1843)) + (PORT datab (982:982:982) (1054:1054:1054)) + (PORT datac (675:675:675) (737:737:737)) + (PORT datad (868:868:868) (918:918:918)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -7258,717 +3573,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT datab (1493:1493:1493) (1554:1554:1554)) - (PORT datac (1223:1223:1223) (1253:1253:1253)) - (PORT datad (1403:1403:1403) (1470:1470:1470)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1394:1394:1394)) - (PORT datab (1605:1605:1605) (1734:1734:1734)) - (PORT datac (622:622:622) (664:664:664)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1978:1978:1978) (2137:2137:2137)) - (PORT datab (2591:2591:2591) (2768:2768:2768)) - (PORT datad (1697:1697:1697) (1792:1792:1792)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1523:1523:1523)) - (PORT datab (976:976:976) (983:983:983)) - (PORT datac (868:868:868) (907:907:907)) - (PORT datad (918:918:918) (955:955:955)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (2356:2356:2356) (2462:2462:2462)) - (PORT datac (1864:1864:1864) (1892:1892:1892)) - (PORT datad (1772:1772:1772) (1886:1886:1886)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1020:1020:1020)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1271:1271:1271)) - (PORT datab (627:627:627) (649:649:649)) - (PORT datac (902:902:902) (931:931:931)) - (PORT datad (859:859:859) (879:879:879)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (891:891:891) (925:925:925)) - (PORT datac (619:619:619) (660:660:660)) - (PORT datad (620:620:620) (668:668:668)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (907:907:907)) - (PORT datab (1517:1517:1517) (1628:1628:1628)) - (PORT datac (622:622:622) (674:674:674)) - (PORT datad (1219:1219:1219) (1277:1277:1277)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (185:185:185) (224:224:224)) - (PORT datad (1252:1252:1252) (1309:1309:1309)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (2733:2733:2733) (2908:2908:2908)) - (PORT datac (1737:1737:1737) (1813:1813:1813)) - (PORT datad (839:839:839) (867:867:867)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1578:1578:1578) (1687:1687:1687)) - (PORT datab (2007:2007:2007) (2122:2122:2122)) - (PORT datac (2198:2198:2198) (2304:2304:2304)) - (PORT datad (1762:1762:1762) (1853:1853:1853)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1771:1771:1771) (1876:1876:1876)) - (PORT datab (356:356:356) (392:392:392)) - (PORT datac (1865:1865:1865) (1919:1919:1919)) - (PORT datad (1599:1599:1599) (1746:1746:1746)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2343:2343:2343) (2509:2509:2509)) - (PORT datab (1128:1128:1128) (1167:1167:1167)) - (PORT datac (1549:1549:1549) (1649:1649:1649)) - (PORT datad (1983:1983:1983) (2085:2085:2085)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (931:931:931)) - (PORT datab (822:822:822) (869:869:869)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (1639:1639:1639) (1711:1711:1711)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (650:650:650) (707:707:707)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1214:1214:1214)) - (PORT datab (849:849:849) (876:876:876)) - (PORT datac (1180:1180:1180) (1245:1245:1245)) - (PORT datad (894:894:894) (941:941:941)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1536:1536:1536) (1600:1600:1600)) - (PORT datab (1096:1096:1096) (1128:1128:1128)) - (PORT datac (1717:1717:1717) (1793:1793:1793)) - (PORT datad (1165:1165:1165) (1203:1203:1203)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1531:1531:1531) (1599:1599:1599)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (1264:1264:1264) (1333:1333:1333)) - (PORT datad (1159:1159:1159) (1219:1219:1219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (348:348:348)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (248:248:248) (306:306:306)) - (PORT datad (1436:1436:1436) (1458:1458:1458)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (632:632:632)) - (PORT datab (853:853:853) (859:859:859)) - (PORT datac (371:371:371) (388:388:388)) - (PORT datad (899:899:899) (949:949:949)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (615:615:615)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (1119:1119:1119) (1151:1151:1151)) - (PORT datad (880:880:880) (918:918:918)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1164:1164:1164)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1166:1166:1166)) - (PORT datab (2009:2009:2009) (2098:2098:2098)) - (PORT datac (1374:1374:1374) (1482:1482:1482)) - (PORT datad (1892:1892:1892) (1950:1950:1950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1682:1682:1682) (1789:1789:1789)) - (PORT datab (654:654:654) (672:672:672)) - (PORT datac (1764:1764:1764) (1827:1827:1827)) - (PORT datad (1054:1054:1054) (1101:1101:1101)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1793:1793:1793)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (1763:1763:1763) (1832:1832:1832)) - (PORT datad (1052:1052:1052) (1102:1102:1102)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1238:1238:1238)) - (PORT datab (886:886:886) (929:929:929)) - (PORT datac (942:942:942) (998:998:998)) - (PORT datad (944:944:944) (995:995:995)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (436:436:436)) - (PORT datab (948:948:948) (982:982:982)) - (PORT datac (584:584:584) (628:628:628)) - (PORT datad (223:223:223) (253:253:253)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (962:962:962)) - (PORT datab (942:942:942) (963:963:963)) - (PORT datac (638:638:638) (669:669:669)) - (PORT datad (1172:1172:1172) (1244:1244:1244)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1052:1052:1052)) - (PORT datab (987:987:987) (1030:1030:1030)) - (PORT datac (1171:1171:1171) (1219:1219:1219)) - (PORT datad (986:986:986) (1036:1036:1036)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (673:673:673)) - (PORT datab (1462:1462:1462) (1514:1514:1514)) - (PORT datac (830:830:830) (908:908:908)) - (PORT datad (1914:1914:1914) (1984:1984:1984)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datac (1322:1322:1322) (1471:1471:1471)) - (PORT datad (2189:2189:2189) (2361:2361:2361)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (881:881:881)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (1159:1159:1159) (1177:1177:1177)) - (PORT datad (639:639:639) (677:677:677)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (999:999:999)) - (PORT datab (1472:1472:1472) (1516:1516:1516)) - (PORT datac (1410:1410:1410) (1502:1502:1502)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (645:645:645)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (826:826:826) (838:838:838)) - (PORT datad (789:789:789) (845:845:845)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2078:2078:2078)) - (PORT datab (611:611:611) (626:626:626)) - (PORT datac (831:831:831) (870:870:870)) - (PORT datad (705:705:705) (742:742:742)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1665:1665:1665) (1731:1731:1731)) - (PORT datab (1778:1778:1778) (1843:1843:1843)) - (PORT datac (897:897:897) (948:948:948)) - (PORT datad (703:703:703) (737:737:737)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (936:936:936)) - (PORT datab (1991:1991:1991) (2053:2053:2053)) - (PORT datac (1786:1786:1786) (1813:1813:1813)) - (PORT datad (1444:1444:1444) (1438:1438:1438)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (644:644:644)) - (PORT datab (740:740:740) (777:777:777)) - (PORT datac (1151:1151:1151) (1208:1208:1208)) - (PORT datad (804:804:804) (817:817:817)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (658:658:658)) - (PORT datab (742:742:742) (780:780:780)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (607:607:607) (632:632:632)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (376:376:376)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1656:1656:1656) (1674:1674:1674)) - (PORT datab (832:832:832) (856:856:856)) - (PORT datac (874:874:874) (900:900:900)) - (PORT datad (583:583:583) (602:602:602)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1662:1662:1662) (1727:1727:1727)) - (PORT datab (609:609:609) (623:623:623)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (1964:1964:1964) (2030:2030:2030)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (874:874:874)) - (PORT datab (1111:1111:1111) (1163:1163:1163)) - (PORT datac (760:760:760) (817:817:817)) - (PORT datad (648:648:648) (669:669:669)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (816:816:816)) - (PORT datab (2351:2351:2351) (2480:2480:2480)) - (PORT datac (750:750:750) (859:859:859)) - (PORT datad (1843:1843:1843) (1894:1894:1894)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (615:615:615) (668:668:668)) - (PORT datac (355:355:355) (385:385:385)) - (PORT datad (820:820:820) (847:847:847)) + (PORT dataa (906:906:906) (936:936:936)) + (PORT datab (2523:2523:2523) (2632:2632:2632)) + (PORT datac (1501:1501:1501) (1545:1545:1545)) + (PORT datad (1168:1168:1168) (1198:1198:1198)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -7981,8 +3592,95 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) (DELAY (ABSOLUTE - (PORT datac (2110:2110:2110) (2222:2222:2222)) - (PORT datad (1649:1649:1649) (1827:1827:1827)) + (PORT dataa (1221:1221:1221) (1327:1327:1327)) + (PORT datad (2392:2392:2392) (2524:2524:2524)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1254:1254:1254)) + (PORT datab (426:426:426) (506:506:506)) + (PORT datad (436:436:436) (503:503:503)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1170:1170:1170)) + (PORT datab (1231:1231:1231) (1310:1310:1310)) + (PORT datad (315:315:315) (326:326:326)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (1332:1332:1332) (1402:1402:1402)) + (PORT datac (1502:1502:1502) (1540:1540:1540)) + (PORT datad (1167:1167:1167) (1194:1194:1194)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1673:1673:1673)) + (PORT datac (1749:1749:1749) (1885:1885:1885)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1361:1361:1361)) + (PORT datab (354:354:354) (389:389:389)) + (PORT datac (1557:1557:1557) (1714:1714:1714)) + (PORT datad (1416:1416:1416) (1491:1491:1491)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -7990,15 +3688,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (886:886:886) (924:924:924)) - (PORT datad (364:364:364) (387:387:387)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1817:1817:1817) (1912:1912:1912)) + (PORT datab (1952:1952:1952) (2047:2047:2047)) + (PORT datac (1429:1429:1429) (1521:1521:1521)) + (PORT datad (657:657:657) (703:703:703)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8006,13 +3704,398 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~3) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (389:389:389)) - (PORT datab (613:613:613) (635:635:635)) - (PORT datac (585:585:585) (595:595:595)) - (PORT datad (816:816:816) (824:824:824)) + (PORT dataa (1404:1404:1404) (1470:1470:1470)) + (PORT datab (1220:1220:1220) (1262:1262:1262)) + (PORT datac (1149:1149:1149) (1196:1196:1196)) + (PORT datad (828:828:828) (861:861:861)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1016:1016:1016)) + (PORT datab (1441:1441:1441) (1511:1511:1511)) + (PORT datac (1453:1453:1453) (1526:1526:1526)) + (PORT datad (1029:1029:1029) (1119:1119:1119)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1603:1603:1603) (1703:1703:1703)) + (PORT datab (1483:1483:1483) (1651:1651:1651)) + (PORT datad (1255:1255:1255) (1388:1388:1388)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2612:2612:2612) (2697:2697:2697)) + (PORT datab (1480:1480:1480) (1568:1568:1568)) + (PORT datac (1259:1259:1259) (1347:1347:1347)) + (PORT datad (1321:1321:1321) (1402:1402:1402)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (762:762:762)) + (PORT datab (1129:1129:1129) (1244:1244:1244)) + (PORT datac (1105:1105:1105) (1196:1196:1196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (958:958:958)) + (PORT datab (1098:1098:1098) (1224:1224:1224)) + (PORT datac (1684:1684:1684) (1781:1781:1781)) + (PORT datad (899:899:899) (930:930:930)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT datab (1422:1422:1422) (1500:1500:1500)) + (PORT datac (214:214:214) (257:257:257)) + (PORT datad (985:985:985) (1083:1083:1083)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1351:1351:1351)) + (PORT datab (243:243:243) (290:290:290)) + (PORT datac (1391:1391:1391) (1466:1466:1466)) + (PORT datad (985:985:985) (1083:1083:1083)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1918:1918:1918) (1959:1959:1959)) + (PORT datab (1216:1216:1216) (1272:1272:1272)) + (PORT datad (928:928:928) (968:968:968)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1293:1293:1293)) + (PORT datac (1199:1199:1199) (1284:1284:1284)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1680:1680:1680) (1732:1732:1732)) + (PORT datab (269:269:269) (331:331:331)) + (PORT datac (708:708:708) (774:774:774)) + (PORT datad (249:249:249) (300:300:300)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (597:597:597)) + (PORT datab (665:665:665) (721:721:721)) + (PORT datac (2606:2606:2606) (2699:2699:2699)) + (PORT datad (1349:1349:1349) (1385:1385:1385)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (376:376:376)) + (PORT datac (1200:1200:1200) (1284:1284:1284)) + (PORT datad (983:983:983) (1037:1037:1037)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (280:280:280)) + (PORT datab (2981:2981:2981) (3109:3109:3109)) + (PORT datac (1174:1174:1174) (1223:1223:1223)) + (PORT datad (690:690:690) (720:720:720)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1255:1255:1255)) + (PORT datab (1335:1335:1335) (1448:1448:1448)) + (PORT datac (539:539:539) (556:556:556)) + (PORT datad (633:633:633) (679:679:679)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1150:1150:1150)) + (PORT datac (1634:1634:1634) (1816:1816:1816)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~3) + (DELAY + (ABSOLUTE + (PORT datac (1196:1196:1196) (1296:1296:1296)) + (PORT datad (1223:1223:1223) (1333:1333:1333)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (1425:1425:1425) (1521:1521:1521)) + (PORT datad (1209:1209:1209) (1299:1299:1299)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1440:1440:1440) (1554:1554:1554)) + (PORT datad (1627:1627:1627) (1725:1725:1725)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (1572:1572:1572) (1697:1697:1697)) + (PORT datac (1407:1407:1407) (1473:1473:1473)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1099:1099:1099)) + (PORT datab (1195:1195:1195) (1248:1248:1248)) + (PORT datac (1406:1406:1406) (1439:1439:1439)) + (PORT datad (1839:1839:1839) (1886:1886:1886)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1237:1237:1237)) + (PORT datab (890:890:890) (920:920:920)) + (PORT datac (1813:1813:1813) (1879:1879:1879)) + (PORT datad (1295:1295:1295) (1368:1368:1368)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1417:1417:1417)) + (PORT datab (700:700:700) (777:777:777)) + (PORT datad (667:667:667) (743:743:743)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1151:1151:1151)) + (PORT datab (1251:1251:1251) (1328:1328:1328)) + (PORT datac (1626:1626:1626) (1826:1826:1826)) + (PORT datad (2008:2008:2008) (2036:2036:2036)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1582:1582:1582)) + (PORT datab (897:897:897) (929:929:929)) + (PORT datac (1511:1511:1511) (1556:1556:1556)) + (PORT datad (1758:1758:1758) (1800:1800:1800)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -8022,15 +4105,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (INSTANCE z80_\|execute_\|ixy_d\~9) (DELAY (ABSOLUTE - (PORT dataa (276:276:276) (346:346:346)) - (PORT datab (1766:1766:1766) (1810:1810:1810)) - (PORT datac (251:251:251) (310:310:310)) - (PORT datad (225:225:225) (265:265:265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (949:949:949) (1003:1003:1003)) + (PORT datab (706:706:706) (750:750:750)) + (PORT datac (1691:1691:1691) (1786:1786:1786)) + (PORT datad (542:542:542) (565:565:565)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (677:677:677)) + (PORT datab (593:593:593) (622:622:622)) + (PORT datac (616:616:616) (633:633:633)) + (PORT datad (223:223:223) (260:260:260)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (599:599:599)) + (PORT datab (647:647:647) (667:667:667)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (842:842:842) (871:871:871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1116:1116:1116)) + (PORT datac (2027:2027:2027) (2142:2142:2142)) + (PORT datad (940:940:940) (1023:1023:1023)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8038,13 +4167,277 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (INSTANCE z80_\|execute_\|ixy_d\~10) (DELAY (ABSOLUTE - (PORT dataa (927:927:927) (1008:1008:1008)) - (PORT datab (964:964:964) (1028:1028:1028)) - (PORT datac (1904:1904:1904) (1967:1967:1967)) - (PORT datad (644:644:644) (671:671:671)) + (PORT dataa (770:770:770) (864:864:864)) + (PORT datab (1303:1303:1303) (1409:1409:1409)) + (PORT datac (647:647:647) (732:732:732)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1133:1133:1133)) + (PORT datab (565:565:565) (597:597:597)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2320:2320:2320) (2443:2443:2443)) + (PORT datab (1332:1332:1332) (1447:1447:1447)) + (PORT datac (1144:1144:1144) (1219:1219:1219)) + (PORT datad (1832:1832:1832) (1992:1992:1992)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1152:1152:1152)) + (PORT datac (1639:1639:1639) (1834:1834:1834)) + (PORT datad (999:999:999) (1109:1109:1109)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1426:1426:1426)) + (PORT datab (886:886:886) (915:915:915)) + (PORT datac (443:443:443) (518:518:518)) + (PORT datad (1156:1156:1156) (1198:1198:1198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1739:1739:1739) (1849:1849:1849)) + (PORT datab (710:710:710) (780:780:780)) + (PORT datac (954:954:954) (1026:1026:1026)) + (PORT datad (2639:2639:2639) (2724:2724:2724)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1372:1372:1372)) + (PORT datab (1278:1278:1278) (1396:1396:1396)) + (PORT datac (1664:1664:1664) (1837:1837:1837)) + (PORT datad (392:392:392) (420:420:420)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1683:1683:1683)) + (PORT datab (1576:1576:1576) (1717:1717:1717)) + (PORT datac (819:819:819) (834:834:834)) + (PORT datad (1049:1049:1049) (1080:1080:1080)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1447:1447:1447)) + (PORT datab (864:864:864) (891:891:891)) + (PORT datac (718:718:718) (821:821:821)) + (PORT datad (1222:1222:1222) (1332:1332:1332)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (700:700:700)) + (PORT datab (864:864:864) (892:892:892)) + (PORT datac (1392:1392:1392) (1425:1425:1425)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1886:1886:1886)) + (PORT datab (1714:1714:1714) (1812:1812:1812)) + (PORT datac (1007:1007:1007) (1082:1082:1082)) + (PORT datad (849:849:849) (867:867:867)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (907:907:907) (978:978:978)) + (PORT datad (1870:1870:1870) (2001:2001:2001)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (623:623:623)) + (PORT datab (2973:2973:2973) (3100:3100:3100)) + (PORT datac (1380:1380:1380) (1409:1409:1409)) + (PORT datad (693:693:693) (725:725:725)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1776:1776:1776) (1889:1889:1889)) + (PORT datad (1583:1583:1583) (1710:1710:1710)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (717:717:717)) + (PORT datab (575:575:575) (595:595:595)) + (PORT datac (871:871:871) (913:913:913)) + (PORT datad (1401:1401:1401) (1450:1450:1450)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1331:1331:1331)) + (PORT datab (955:955:955) (970:970:970)) + (PORT datac (861:861:861) (879:879:879)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1429:1429:1429)) + (PORT datab (884:884:884) (913:913:913)) + (PORT datac (443:443:443) (519:519:519)) + (PORT datad (1159:1159:1159) (1198:1198:1198)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8054,369 +4447,674 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) (DELAY (ABSOLUTE - (PORT dataa (958:958:958) (1056:1056:1056)) - (PORT datab (1415:1415:1415) (1547:1547:1547)) - (PORT datac (943:943:943) (1040:1040:1040)) - (PORT datad (818:818:818) (824:824:824)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (717:717:717)) - (PORT datab (1612:1612:1612) (1652:1652:1652)) - (PORT datac (1279:1279:1279) (1317:1317:1317)) - (PORT datad (1153:1153:1153) (1159:1159:1159)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (1943:1943:1943) (2004:2004:2004)) - (PORT datad (2062:2062:2062) (2197:2197:2197)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (266:266:266)) - (PORT datab (1497:1497:1497) (1573:1573:1573)) - (PORT datac (1953:1953:1953) (2008:2008:2008)) - (PORT datad (206:206:206) (244:244:244)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1982:1982:1982) (2045:2045:2045)) - (PORT datab (2098:2098:2098) (2238:2238:2238)) - (PORT datac (1468:1468:1468) (1539:1539:1539)) - (PORT datad (211:211:211) (249:249:249)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1990:1990:1990) (2089:2089:2089)) - (PORT datab (1214:1214:1214) (1264:1264:1264)) - (PORT datac (1724:1724:1724) (1792:1792:1792)) - (PORT datad (935:935:935) (979:979:979)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1544:1544:1544)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1386:1386:1386) (1421:1421:1421)) - (PORT datad (614:614:614) (649:649:649)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1199:1199:1199)) - (PORT datab (1612:1612:1612) (1652:1652:1652)) - (PORT datac (885:885:885) (930:930:930)) - (PORT datad (893:893:893) (940:940:940)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (178:178:178) (215:215:215)) - (PORT datad (211:211:211) (242:242:242)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT datab (2102:2102:2102) (2242:2242:2242)) - (PORT datac (1464:1464:1464) (1539:1539:1539)) - (PORT datad (208:208:208) (246:246:246)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (1474:1474:1474) (1558:1558:1558)) - (PORT datac (2114:2114:2114) (2223:2223:2223)) - (PORT datad (1649:1649:1649) (1828:1828:1828)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1004:1004:1004)) - (PORT datab (1085:1085:1085) (1111:1111:1111)) - (PORT datac (644:644:644) (684:684:684)) - (PORT datad (629:629:629) (644:644:644)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (629:629:629)) - (PORT datab (917:917:917) (949:949:949)) - (PORT datac (586:586:586) (598:598:598)) - (PORT datad (1627:1627:1627) (1648:1648:1648)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2329:2329:2329)) - (PORT datab (1611:1611:1611) (1741:1741:1741)) - (PORT datac (847:847:847) (879:879:879)) - (PORT datad (871:871:871) (887:887:887)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (686:686:686)) - (PORT datab (874:874:874) (906:906:906)) - (PORT datac (1698:1698:1698) (1732:1732:1732)) - (PORT datad (1500:1500:1500) (1556:1556:1556)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1213:1213:1213)) - (PORT datab (624:624:624) (655:655:655)) - (PORT datac (657:657:657) (701:701:701)) - (PORT datad (1183:1183:1183) (1213:1213:1213)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1005:1005:1005) (1109:1109:1109)) + (PORT datac (710:710:710) (802:802:802)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (INSTANCE z80_\|pla_decode_\|Equal46\~0) (DELAY (ABSOLUTE - (PORT dataa (1234:1234:1234) (1292:1292:1292)) - (PORT datab (986:986:986) (1027:1027:1027)) - (PORT datac (1677:1677:1677) (1709:1709:1709)) - (PORT datad (1375:1375:1375) (1426:1426:1426)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (1011:1011:1011) (1072:1072:1072)) - (PORT datac (1770:1770:1770) (1905:1905:1905)) - (PORT datad (1375:1375:1375) (1425:1425:1425)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1014:1014:1014)) - (PORT datab (946:946:946) (992:992:992)) - (PORT datad (890:890:890) (963:963:963)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (271:271:271)) - (PORT datab (989:989:989) (1051:1051:1051)) - (PORT datac (804:804:804) (824:824:824)) - (PORT datad (1395:1395:1395) (1406:1406:1406)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1775:1775:1775) (1871:1871:1871)) - (PORT datab (1638:1638:1638) (1787:1787:1787)) - (PORT datad (1885:1885:1885) (1952:1952:1952)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1146:1146:1146)) - (PORT datac (1745:1745:1745) (1882:1882:1882)) - (PORT datad (635:635:635) (694:694:694)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1159:1159:1159)) - (PORT datab (921:921:921) (984:984:984)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (566:566:566) (581:581:581)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1917:1917:1917) (2022:2022:2022)) - (PORT datab (1506:1506:1506) (1587:1587:1587)) - (PORT datac (1606:1606:1606) (1725:1725:1725)) - (PORT datad (857:857:857) (891:891:891)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (2089:2089:2089) (2234:2234:2234)) + (PORT datab (1577:1577:1577) (1677:1677:1677)) + (PORT datac (2099:2099:2099) (2270:2270:2270)) + (PORT datad (1001:1001:1001) (1109:1109:1109)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1424:1424:1424)) + (PORT datab (286:286:286) (377:377:377)) + (PORT datac (1166:1166:1166) (1182:1182:1182)) + (PORT datad (1155:1155:1155) (1198:1198:1198)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1194:1194:1194)) + (PORT datab (1458:1458:1458) (1546:1546:1546)) + (PORT datac (1709:1709:1709) (1725:1725:1725)) + (PORT datad (387:387:387) (408:408:408)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (1021:1021:1021)) + (PORT datab (1562:1562:1562) (1657:1657:1657)) + (PORT datac (860:860:860) (912:912:912)) + (PORT datad (909:909:909) (980:980:980)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1371:1371:1371)) + (PORT datab (1280:1280:1280) (1398:1398:1398)) + (PORT datac (1667:1667:1667) (1837:1837:1837)) + (PORT datad (392:392:392) (419:419:419)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1423:1423:1423)) + (PORT datab (1581:1581:1581) (1721:1721:1721)) + (PORT datac (1467:1467:1467) (1496:1496:1496)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (412:412:412)) + (PORT datab (628:628:628) (643:643:643)) + (PORT datac (642:642:642) (689:689:689)) + (PORT datad (876:876:876) (903:903:903)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT datab (732:732:732) (833:833:833)) + (PORT datad (385:385:385) (417:417:417)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1329:1329:1329)) + (PORT datab (1252:1252:1252) (1326:1326:1326)) + (PORT datad (1237:1237:1237) (1310:1310:1310)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1266:1266:1266)) + (PORT datac (2068:2068:2068) (2251:2251:2251)) + (PORT datad (1708:1708:1708) (1804:1804:1804)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1770:1770:1770) (1859:1859:1859)) + (PORT datab (1260:1260:1260) (1349:1349:1349)) + (PORT datad (1718:1718:1718) (1791:1791:1791)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1774:1774:1774) (1859:1859:1859)) + (PORT datab (1235:1235:1235) (1313:1313:1313)) + (PORT datac (2079:2079:2079) (2188:2188:2188)) + (PORT datad (1723:1723:1723) (1793:1793:1793)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1811:1811:1811)) + (PORT datab (248:248:248) (290:290:290)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (384:384:384)) + (PORT datab (1761:1761:1761) (1832:1832:1832)) + (PORT datac (1742:1742:1742) (1818:1818:1818)) + (PORT datad (1237:1237:1237) (1315:1315:1315)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1771:1771:1771) (1857:1857:1857)) + (PORT datab (658:658:658) (689:689:689)) + (PORT datac (2074:2074:2074) (2183:2183:2183)) + (PORT datad (1719:1719:1719) (1788:1788:1788)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1329:1329:1329)) + (PORT datab (1252:1252:1252) (1325:1325:1325)) + (PORT datad (1237:1237:1237) (1310:1310:1310)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (934:934:934) (957:957:957)) + (PORT datac (802:802:802) (825:825:825)) + (PORT datad (1221:1221:1221) (1304:1304:1304)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (442:442:442)) + (PORT datab (372:372:372) (399:399:399)) + (PORT datac (571:571:571) (595:595:595)) + (PORT datad (944:944:944) (1008:1008:1008)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (660:660:660)) + (PORT datab (2975:2975:2975) (3104:3104:3104)) + (PORT datac (909:909:909) (968:968:968)) + (PORT datad (690:690:690) (723:723:723)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1247:1247:1247)) + (PORT datab (2974:2974:2974) (3098:3098:3098)) + (PORT datac (586:586:586) (616:616:616)) + (PORT datad (693:693:693) (723:723:723)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1371:1371:1371)) + (PORT datab (1280:1280:1280) (1398:1398:1398)) + (PORT datac (1666:1666:1666) (1836:1836:1836)) + (PORT datad (340:340:340) (364:364:364)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (921:921:921)) + (PORT datab (271:271:271) (337:337:337)) + (PORT datac (709:709:709) (779:779:779)) + (PORT datad (259:259:259) (309:309:309)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1729:1729:1729)) + (PORT datab (272:272:272) (332:332:332)) + (PORT datac (708:708:708) (774:774:774)) + (PORT datad (264:264:264) (308:308:308)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (750:750:750)) + (PORT datab (270:270:270) (330:330:330)) + (PORT datac (709:709:709) (778:778:778)) + (PORT datad (260:260:260) (310:310:310)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (917:917:917)) + (PORT datab (845:845:845) (903:903:903)) + (PORT datac (610:610:610) (659:659:659)) + (PORT datad (640:640:640) (696:696:696)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (624:624:624)) + (PORT datab (2975:2975:2975) (3101:3101:3101)) + (PORT datac (1380:1380:1380) (1412:1412:1412)) + (PORT datad (688:688:688) (729:729:729)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1603:1603:1603)) + (PORT datab (1406:1406:1406) (1442:1442:1442)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1351:1351:1351) (1334:1334:1334)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2136:2136:2136) (2285:2285:2285)) + (PORT datad (970:970:970) (1056:1056:1056)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1845:1845:1845) (1897:1897:1897)) + (PORT datab (1276:1276:1276) (1339:1339:1339)) + (PORT datac (1645:1645:1645) (1660:1660:1660)) + (PORT datad (1150:1150:1150) (1174:1174:1174)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (400:400:400)) + (PORT datab (1278:1278:1278) (1339:1339:1339)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2106:2106:2106) (2267:2267:2267)) + (PORT datab (2646:2646:2646) (2747:2747:2747)) + (PORT datac (1902:1902:1902) (1989:1989:1989)) + (PORT datad (200:200:200) (228:228:228)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (446:446:446)) + (PORT datab (939:939:939) (961:961:961)) + (PORT datac (1442:1442:1442) (1475:1475:1475)) + (PORT datad (355:355:355) (375:375:375)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (1186:1186:1186) (1214:1214:1214)) + (PORT datac (1443:1443:1443) (1476:1476:1476)) + (PORT datad (215:215:215) (241:241:241)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1335:1335:1335)) + (PORT datab (401:401:401) (479:479:479)) + (PORT datad (985:985:985) (1042:1042:1042)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT datab (1215:1215:1215) (1343:1343:1343)) + (PORT datad (2027:2027:2027) (2164:2164:2164)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (690:690:690)) + (PORT datab (270:270:270) (320:320:320)) + (PORT datac (1931:1931:1931) (1981:1981:1981)) + (PORT datad (885:885:885) (906:906:906)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M5T3_9) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (735:735:735)) + (PORT datab (2031:2031:2031) (2121:2121:2121)) + (PORT datad (1590:1590:1590) (1702:1702:1702)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1577:1577:1577) (1599:1599:1599)) + (PORT datab (1460:1460:1460) (1524:1524:1524)) + (PORT datac (859:859:859) (878:878:878)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1376:1376:1376)) + (PORT datab (1458:1458:1458) (1527:1527:1527)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (637:637:637) (696:696:696)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1427:1427:1427)) + (PORT datab (885:885:885) (917:917:917)) + (PORT datac (443:443:443) (518:518:518)) + (PORT datad (1157:1157:1157) (1198:1198:1198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1151:1151:1151)) + (PORT datab (1254:1254:1254) (1329:1329:1329)) + (PORT datac (1628:1628:1628) (1816:1816:1816)) + (PORT datad (2009:2009:2009) (2040:2040:2040)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (949:949:949)) + (PORT datab (752:752:752) (851:851:851)) + (PORT datac (673:673:673) (782:782:782)) + (PORT datad (262:262:262) (308:308:308)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8427,10 +5125,312 @@ (INSTANCE z80_\|execute_\|ctl_state_alu\~7) (DELAY (ABSOLUTE - (PORT dataa (1474:1474:1474) (1533:1533:1533)) - (PORT datab (1245:1245:1245) (1280:1280:1280)) - (PORT datac (931:931:931) (1004:1004:1004)) - (PORT datad (845:845:845) (854:854:854)) + (PORT dataa (1718:1718:1718) (1791:1791:1791)) + (PORT datab (1206:1206:1206) (1240:1240:1240)) + (PORT datac (1128:1128:1128) (1166:1166:1166)) + (PORT datad (244:244:244) (281:281:281)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1135:1135:1135)) + (PORT datab (2131:2131:2131) (2174:2174:2174)) + (PORT datac (573:573:573) (589:589:589)) + (PORT datad (244:244:244) (281:281:281)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1377:1377:1377)) + (PORT datab (1270:1270:1270) (1388:1388:1388)) + (PORT datac (1659:1659:1659) (1825:1825:1825)) + (PORT datad (393:393:393) (425:425:425)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1372:1372:1372)) + (PORT datab (1276:1276:1276) (1394:1394:1394)) + (PORT datac (1663:1663:1663) (1835:1835:1835)) + (PORT datad (394:394:394) (423:423:423)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (996:996:996)) + (PORT datab (1190:1190:1190) (1216:1216:1216)) + (PORT datac (1051:1051:1051) (1159:1159:1159)) + (PORT datad (2076:2076:2076) (2218:2218:2218)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (964:964:964)) + (PORT datab (896:896:896) (928:928:928)) + (PORT datac (1514:1514:1514) (1557:1557:1557)) + (PORT datad (1757:1757:1757) (1804:1804:1804)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1204:1204:1204)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1306:1306:1306) (1341:1341:1341)) + (PORT datad (244:244:244) (280:280:280)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1419:1419:1419)) + (PORT datab (284:284:284) (375:375:375)) + (PORT datac (1167:1167:1167) (1178:1178:1178)) + (PORT datad (1155:1155:1155) (1192:1192:1192)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1695:1695:1695)) + (PORT datab (2156:2156:2156) (2311:2311:2311)) + (PORT datac (1126:1126:1126) (1162:1162:1162)) + (PORT datad (1104:1104:1104) (1161:1161:1161)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1236:1236:1236)) + (PORT datab (882:882:882) (937:937:937)) + (PORT datac (933:933:933) (980:980:980)) + (PORT datad (1135:1135:1135) (1173:1173:1173)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (953:953:953)) + (PORT datab (282:282:282) (345:345:345)) + (PORT datac (673:673:673) (786:786:786)) + (PORT datad (1380:1380:1380) (1407:1407:1407)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2191:2191:2191) (2299:2299:2299)) + (PORT datab (1440:1440:1440) (1467:1467:1467)) + (PORT datac (1509:1509:1509) (1600:1600:1600)) + (PORT datad (913:913:913) (928:928:928)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1429:1429:1429)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (1166:1166:1166) (1178:1178:1178)) + (PORT datad (1159:1159:1159) (1199:1199:1199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1957:1957:1957) (2024:2024:2024)) + (PORT datab (953:953:953) (986:986:986)) + (PORT datac (1509:1509:1509) (1598:1598:1598)) + (PORT datad (2152:2152:2152) (2251:2251:2251)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (699:699:699)) + (PORT datab (902:902:902) (936:936:936)) + (PORT datac (925:925:925) (963:963:963)) + (PORT datad (894:894:894) (918:918:918)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (720:720:720) (787:787:787)) + (PORT datac (1836:1836:1836) (2007:2007:2007)) + (PORT datad (1736:1736:1736) (1849:1849:1849)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (416:416:416)) + (PORT datab (269:269:269) (331:331:331)) + (PORT datac (709:709:709) (775:775:775)) + (PORT datad (249:249:249) (300:300:300)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1340:1340:1340)) + (PORT datab (1242:1242:1242) (1313:1313:1313)) + (PORT datac (2038:2038:2038) (2087:2087:2087)) + (PORT datad (1404:1404:1404) (1429:1429:1429)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1018:1018:1018)) + (PORT datab (1430:1430:1430) (1464:1464:1464)) + (PORT datac (1420:1420:1420) (1466:1466:1466)) + (PORT datad (1235:1235:1235) (1290:1290:1290)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8440,63 +5440,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (1965:1965:1965) (2057:2057:2057)) - (PORT datac (1434:1434:1434) (1491:1491:1491)) - (PORT datad (1510:1510:1510) (1653:1653:1653)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1364:1364:1364) (1466:1466:1466)) - (PORT datab (1561:1561:1561) (1650:1650:1650)) - (PORT datac (2446:2446:2446) (2642:2642:2642)) - (PORT datad (1222:1222:1222) (1355:1355:1355)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1651:1651:1651) (1723:1723:1723)) - (PORT datab (935:935:935) (964:964:964)) - (PORT datac (2570:2570:2570) (2619:2619:2619)) - (PORT datad (771:771:771) (818:818:818)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1479:1479:1479) (1540:1540:1540)) - (PORT datab (603:603:603) (620:620:620)) - (PORT datac (1131:1131:1131) (1166:1166:1166)) - (PORT datad (578:578:578) (596:596:596)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (627:627:627) (653:653:653)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (721:721:721) (783:783:783)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8504,47 +5456,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) (DELAY (ABSOLUTE - (PORT dataa (1475:1475:1475) (1536:1536:1536)) - (PORT datab (1418:1418:1418) (1464:1464:1464)) - (PORT datac (928:928:928) (1006:1006:1006)) - (PORT datad (1413:1413:1413) (1432:1432:1432)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1777:1777:1777) (1900:1900:1900)) - (PORT datab (217:217:217) (256:256:256)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (797:797:797)) - (PORT datab (1182:1182:1182) (1233:1233:1233)) - (PORT datac (1221:1221:1221) (1278:1278:1278)) - (PORT datad (894:894:894) (946:946:946)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1441:1441:1441) (1472:1472:1472)) + (PORT datac (723:723:723) (821:821:821)) + (PORT datad (1792:1792:1792) (1909:1909:1909)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8552,13 +5470,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) (DELAY (ABSOLUTE - (PORT dataa (817:817:817) (896:896:896)) - (PORT datab (1880:1880:1880) (2010:2010:2010)) - (PORT datac (329:329:329) (351:351:351)) - (PORT datad (1691:1691:1691) (1766:1766:1766)) + (PORT dataa (1887:1887:1887) (1971:1971:1971)) + (PORT datab (927:927:927) (970:970:970)) + (PORT datac (1722:1722:1722) (1804:1804:1804)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (651:651:651) (709:709:709)) + (PORT datac (1090:1090:1090) (1128:1128:1128)) + (PORT datad (324:324:324) (347:347:347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (973:973:973) (1027:1027:1027)) + (PORT datac (313:313:313) (343:343:343)) + (PORT datad (584:584:584) (604:604:604)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1199:1199:1199)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (794:794:794) (809:809:809)) + (PORT datad (1099:1099:1099) (1106:1106:1106)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8571,13 +5537,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (2180:2180:2180) (2359:2359:2359)) - (PORT datab (1395:1395:1395) (1458:1458:1458)) - (PORT datac (1425:1425:1425) (1436:1436:1436)) - (PORT datad (2268:2268:2268) (2359:2359:2359)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (1761:1761:1761) (1866:1866:1866)) + (PORT datab (960:960:960) (973:973:973)) + (PORT datac (1771:1771:1771) (1901:1901:1901)) + (PORT datad (2046:2046:2046) (2143:2143:2143)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -8587,90 +5553,42 @@ (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (1302:1302:1302) (1373:1373:1373)) - (PORT datab (1199:1199:1199) (1239:1239:1239)) - (PORT datac (650:650:650) (720:720:720)) - (PORT datad (1152:1152:1152) (1181:1181:1181)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1404:1404:1404) (1423:1423:1423)) + (PORT datac (846:846:846) (871:871:871)) + (PORT datad (1487:1487:1487) (1576:1576:1576)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1449:1449:1449)) + (PORT datab (1456:1456:1456) (1500:1500:1500)) + (PORT datac (189:189:189) (230:230:230)) + (PORT datad (1482:1482:1482) (1573:1573:1573)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) (DELAY (ABSOLUTE - (PORT dataa (1459:1459:1459) (1482:1482:1482)) - (PORT datab (1177:1177:1177) (1245:1245:1245)) - (PORT datac (653:653:653) (721:721:721)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) - (DELAY - (ABSOLUTE - (PORT dataa (2144:2144:2144) (2265:2265:2265)) - (PORT datab (1689:1689:1689) (1868:1868:1868)) - (PORT datac (1147:1147:1147) (1206:1206:1206)) - (PORT datad (1953:1953:1953) (2015:2015:2015)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (894:894:894)) - (PORT datab (919:919:919) (952:952:952)) - (PORT datac (564:564:564) (581:581:581)) - (PORT datad (1104:1104:1104) (1103:1103:1103)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (938:938:938)) - (PORT datab (1034:1034:1034) (1098:1098:1098)) - (PORT datac (1178:1178:1178) (1210:1210:1210)) - (PORT datad (634:634:634) (667:667:667)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (687:687:687)) - (PORT datab (662:662:662) (710:710:710)) - (PORT datac (629:629:629) (681:681:681)) - (PORT datad (1142:1142:1142) (1152:1152:1152)) + (PORT dataa (1765:1765:1765) (1869:1869:1869)) + (PORT datab (1404:1404:1404) (1428:1428:1428)) + (PORT datac (930:930:930) (938:938:938)) + (PORT datad (1025:1025:1025) (1080:1080:1080)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8680,13 +5598,203 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (670:670:670)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1177:1177:1177) (1212:1212:1212)) - (PORT datad (560:560:560) (587:587:587)) + (PORT dataa (1430:1430:1430) (1448:1448:1448)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (841:841:841) (869:869:869)) + (PORT datad (1026:1026:1026) (1081:1081:1081)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1431:1431:1431) (1472:1472:1472)) + (PORT datab (953:953:953) (985:985:985)) + (PORT datac (845:845:845) (873:873:873)) + (PORT datad (1808:1808:1808) (1892:1892:1892)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (667:667:667)) + (PORT datab (707:707:707) (752:752:752)) + (PORT datac (1220:1220:1220) (1262:1262:1262)) + (PORT datad (1657:1657:1657) (1733:1733:1733)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT datab (865:865:865) (901:901:901)) + (PORT datac (790:790:790) (822:822:822)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2152:2152:2152) (2277:2277:2277)) + (PORT datab (2120:2120:2120) (2264:2264:2264)) + (PORT datac (940:940:940) (1007:1007:1007)) + (PORT datad (1318:1318:1318) (1489:1489:1489)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (880:880:880)) + (PORT datab (1034:1034:1034) (1054:1054:1054)) + (PORT datac (869:869:869) (910:910:910)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (857:857:857)) + (PORT datab (927:927:927) (960:960:960)) + (PORT datac (611:611:611) (676:676:676)) + (PORT datad (551:551:551) (569:569:569)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1079:1079:1079)) + (PORT datab (1101:1101:1101) (1110:1110:1110)) + (PORT datac (1394:1394:1394) (1483:1483:1483)) + (PORT datad (2008:2008:2008) (2038:2038:2038)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1135:1135:1135)) + (PORT datab (914:914:914) (966:966:966)) + (PORT datac (607:607:607) (658:658:658)) + (PORT datad (637:637:637) (694:694:694)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1162:1162:1162)) + (PORT datab (859:859:859) (910:910:910)) + (PORT datac (649:649:649) (714:714:714)) + (PORT datad (1402:1402:1402) (1451:1451:1451)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1370:1370:1370)) + (PORT datab (1279:1279:1279) (1397:1397:1397)) + (PORT datac (1665:1665:1665) (1836:1836:1836)) + (PORT datad (340:340:340) (363:363:363)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1194:1194:1194)) + (PORT datab (1111:1111:1111) (1135:1135:1135)) + (PORT datac (650:650:650) (716:716:716)) + (PORT datad (595:595:595) (624:624:624)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (367:367:367)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (652:652:652) (714:714:714)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8694,158 +5802,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1325:1325:1325) (1384:1384:1384)) - (PORT datab (1536:1536:1536) (1559:1559:1559)) - (PORT datac (1403:1403:1403) (1539:1539:1539)) - (PORT datad (2538:2538:2538) (2656:2656:2656)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1532:1532:1532)) - (PORT datab (1506:1506:1506) (1597:1597:1597)) - (PORT datac (1663:1663:1663) (1679:1679:1679)) - (PORT datad (1485:1485:1485) (1617:1617:1617)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1306:1306:1306)) - (PORT datab (672:672:672) (706:706:706)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (678:678:678) (701:701:701)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2311:2311:2311) (2479:2479:2479)) - (PORT datab (2245:2245:2245) (2328:2328:2328)) - (PORT datac (1401:1401:1401) (1542:1542:1542)) - (PORT datad (1158:1158:1158) (1220:1220:1220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1759:1759:1759) (1850:1850:1850)) - (PORT datab (1660:1660:1660) (1809:1809:1809)) - (PORT datac (1036:1036:1036) (1100:1100:1100)) - (PORT datad (1815:1815:1815) (1892:1892:1892)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1550:1550:1550)) - (PORT datab (1149:1149:1149) (1188:1188:1188)) - (PORT datac (809:809:809) (820:820:820)) - (PORT datad (1490:1490:1490) (1622:1622:1622)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1127:1127:1127)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (1714:1714:1714) (1797:1797:1797)) - (PORT datad (1525:1525:1525) (1626:1626:1626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~2) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (691:691:691)) - (PORT datac (2229:2229:2229) (2297:2297:2297)) - (PORT datad (1684:1684:1684) (1744:1744:1744)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (670:670:670)) - (PORT datab (1492:1492:1492) (1549:1549:1549)) - (PORT datac (1215:1215:1215) (1263:1263:1263)) - (PORT datad (558:558:558) (582:582:582)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1853:1853:1853) (1956:1956:1956)) - (PORT datab (895:895:895) (912:912:912)) - (PORT datac (850:850:850) (899:899:899)) - (PORT datad (1512:1512:1512) (1544:1544:1544)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (1285:1285:1285) (1348:1348:1348)) + (PORT datab (394:394:394) (429:429:429)) + (PORT datac (1106:1106:1106) (1149:1149:1149)) + (PORT datad (1402:1402:1402) (1425:1425:1425)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -8854,13 +5820,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) (DELAY (ABSOLUTE - (PORT dataa (1106:1106:1106) (1144:1144:1144)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1215:1215:1215) (1263:1263:1263)) - (PORT datad (914:914:914) (954:954:954)) + (PORT dataa (928:928:928) (965:965:965)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1440:1440:1440) (1535:1535:1535)) + (PORT datad (1104:1104:1104) (1161:1161:1161)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1784:1784:1784) (1888:1888:1888)) + (PORT datab (1710:1710:1710) (1810:1810:1810)) + (PORT datac (1009:1009:1009) (1083:1083:1083)) + (PORT datad (847:847:847) (865:865:865)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (421:421:421)) + (PORT datab (564:564:564) (586:586:586)) + (PORT datac (1904:1904:1904) (2047:2047:2047)) + (PORT datad (1800:1800:1800) (1912:1912:1912)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8873,10 +5871,150 @@ (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) + (PORT dataa (1527:1527:1527) (1600:1600:1600)) + (PORT datab (395:395:395) (426:426:426)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1107:1107:1107) (1163:1163:1163)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1900:1900:1900) (1990:1990:1990)) + (PORT datab (1094:1094:1094) (1221:1221:1221)) + (PORT datac (1463:1463:1463) (1531:1531:1531)) + (PORT datad (899:899:899) (933:933:933)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1884:1884:1884)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (850:850:850) (866:866:866)) + (PORT datad (951:951:951) (1015:1015:1015)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1107:1107:1107)) + (PORT datab (1780:1780:1780) (1911:1911:1911)) + (PORT datac (1853:1853:1853) (1971:1971:1971)) + (PORT datad (610:610:610) (664:664:664)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (812:812:812)) + (PORT datab (1492:1492:1492) (1578:1578:1578)) + (PORT datac (915:915:915) (947:947:947)) + (PORT datad (1809:1809:1809) (1891:1891:1891)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1848:1848:1848)) + (PORT datab (1837:1837:1837) (2019:2019:2019)) + (PORT datac (920:920:920) (957:957:957)) + (PORT datad (2247:2247:2247) (2369:2369:2369)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1699:1699:1699) (1875:1875:1875)) + (PORT datac (1239:1239:1239) (1351:1351:1351)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1126:1126:1126)) + (PORT datab (1092:1092:1092) (1217:1217:1217)) + (PORT datac (1679:1679:1679) (1775:1775:1775)) + (PORT datad (811:811:811) (828:828:828)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (2083:2083:2083)) + (PORT datab (846:846:846) (908:908:908)) + (PORT datac (371:371:371) (398:398:398)) + (PORT datad (1799:1799:1799) (1911:1911:1911)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) (PORT datab (197:197:197) (236:236:236)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (172:172:172) (198:198:198)) + (PORT datac (802:802:802) (814:814:814)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -8886,13 +6024,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (705:705:705)) - (PORT datab (384:384:384) (412:412:412)) - (PORT datac (1156:1156:1156) (1181:1181:1181)) - (PORT datad (941:941:941) (985:985:985)) + (PORT dataa (939:939:939) (969:969:969)) + (PORT datab (846:846:846) (891:891:891)) + (PORT datac (881:881:881) (916:916:916)) + (PORT datad (1140:1140:1140) (1143:1143:1143)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -8905,122 +6043,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) (DELAY (ABSOLUTE - (PORT dataa (1248:1248:1248) (1328:1328:1328)) - (PORT datab (986:986:986) (1055:1055:1055)) - (PORT datac (840:840:840) (878:878:878)) - (PORT datad (1355:1355:1355) (1447:1447:1447)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (936:936:936)) - (PORT datab (1220:1220:1220) (1268:1268:1268)) - (PORT datac (1208:1208:1208) (1289:1289:1289)) - (PORT datad (683:683:683) (740:740:740)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (2075:2075:2075) (2210:2210:2210)) - (PORT datab (1511:1511:1511) (1577:1577:1577)) - (PORT datac (590:590:590) (639:639:639)) - (PORT datad (2101:2101:2101) (2201:2201:2201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (976:976:976)) - (PORT datab (251:251:251) (299:299:299)) - (PORT datac (1219:1219:1219) (1264:1264:1264)) - (PORT datad (1755:1755:1755) (1827:1827:1827)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (296:296:296)) - (PORT datab (645:645:645) (664:664:664)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1069:1069:1069)) - (PORT datab (877:877:877) (902:902:902)) - (PORT datac (1046:1046:1046) (1134:1134:1134)) - (PORT datad (1269:1269:1269) (1355:1355:1355)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (913:913:913)) - (PORT datab (636:636:636) (660:660:660)) - (PORT datac (1654:1654:1654) (1746:1746:1746)) - (PORT datad (1116:1116:1116) (1186:1186:1186)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (791:791:791)) - (PORT datab (1248:1248:1248) (1307:1307:1307)) - (PORT datac (1288:1288:1288) (1402:1402:1402)) - (PORT datad (896:896:896) (946:946:946)) + (PORT dataa (1206:1206:1206) (1290:1290:1290)) + (PORT datab (1512:1512:1512) (1590:1590:1590)) + (PORT datac (926:926:926) (963:963:963)) + (PORT datad (1219:1219:1219) (1293:1293:1293)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -9030,125 +6056,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (427:427:427)) - (PORT datab (1208:1208:1208) (1268:1268:1268)) - (PORT datac (959:959:959) (1038:1038:1038)) - (PORT datad (1924:1924:1924) (2082:2082:2082)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1318:1318:1318) (1375:1375:1375)) - (PORT datab (1540:1540:1540) (1661:1661:1661)) - (PORT datac (2217:2217:2217) (2299:2299:2299)) - (PORT datad (919:919:919) (967:967:967)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2766:2766:2766)) - (PORT datab (1244:1244:1244) (1298:1298:1298)) - (PORT datac (873:873:873) (937:937:937)) - (PORT datad (2161:2161:2161) (2331:2331:2331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1265:1265:1265) (1296:1296:1296)) - (PORT datac (1421:1421:1421) (1419:1419:1419)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (671:671:671)) - (PORT datab (1250:1250:1250) (1279:1279:1279)) - (PORT datac (1879:1879:1879) (2050:2050:2050)) - (PORT datad (1649:1649:1649) (1832:1832:1832)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (1359:1359:1359) (1475:1475:1475)) + (PORT datab (982:982:982) (1022:1022:1022)) + (PORT datac (2333:2333:2333) (2437:2437:2437)) + (PORT datad (1745:1745:1745) (1798:1798:1798)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1274:1274:1274)) - (PORT datab (571:571:571) (582:582:582)) - (PORT datac (2046:2046:2046) (2173:2173:2173)) - (PORT datad (1308:1308:1308) (1448:1448:1448)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1012:1012:1012) (1114:1114:1114)) + (PORT datad (993:993:993) (1086:1086:1086)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (686:686:686) (703:703:703)) - (PORT datac (878:878:878) (936:936:936)) - (PORT datad (312:312:312) (329:329:329)) + (PORT dataa (944:944:944) (987:987:987)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (561:561:561) (570:570:570)) + (PORT datad (1165:1165:1165) (1226:1226:1226)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1672:1672:1672)) - (PORT datab (1493:1493:1493) (1610:1610:1610)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (694:694:694) (748:748:748)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9156,28 +6100,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (INSTANCE z80_\|pla_decode_\|Equal48\~0) (DELAY (ABSOLUTE - (PORT datac (2148:2148:2148) (2195:2195:2195)) - (PORT datad (1421:1421:1421) (1470:1470:1470)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1275:1275:1275)) - (PORT datab (1443:1443:1443) (1483:1483:1483)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (1433:1433:1433) (1518:1518:1518)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (2614:2614:2614) (2701:2701:2701)) + (PORT datab (1480:1480:1480) (1572:1572:1572)) + (PORT datac (1261:1261:1261) (1350:1350:1350)) + (PORT datad (1318:1318:1318) (1402:1402:1402)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -9187,12 +6119,12 @@ (INSTANCE z80_\|pla_decode_\|Equal69\~0) (DELAY (ABSOLUTE - (PORT dataa (1981:1981:1981) (2045:2045:2045)) - (PORT datab (2097:2097:2097) (2238:2238:2238)) - (PORT datac (1468:1468:1468) (1539:1539:1539)) - (PORT datad (211:211:211) (249:249:249)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (2618:2618:2618) (2700:2700:2700)) + (PORT datab (1479:1479:1479) (1568:1568:1568)) + (PORT datac (1264:1264:1264) (1348:1348:1348)) + (PORT datad (1319:1319:1319) (1397:1397:1397)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9200,13 +6132,477 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1873:1873:1873) (1941:1941:1941)) - (PORT datab (1345:1345:1345) (1486:1486:1486)) - (PORT datac (2046:2046:2046) (2172:2172:2172)) - (PORT datad (2102:2102:2102) (2203:2203:2203)) + (PORT dataa (352:352:352) (385:385:385)) + (PORT datab (928:928:928) (936:936:936)) + (PORT datac (1571:1571:1571) (1675:1675:1675)) + (PORT datad (623:623:623) (651:651:651)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1142:1142:1142) (1180:1180:1180)) + (PORT datad (1673:1673:1673) (1727:1727:1727)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1824:1824:1824) (1890:1890:1890)) + (PORT datab (1424:1424:1424) (1433:1433:1433)) + (PORT datac (1738:1738:1738) (1800:1800:1800)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (769:769:769)) + (PORT datab (1099:1099:1099) (1172:1172:1172)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (688:688:688) (757:757:757)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (718:718:718) (821:821:821)) + (PORT datad (383:383:383) (413:413:413)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datac (1254:1254:1254) (1345:1345:1345)) + (PORT datad (1217:1217:1217) (1336:1336:1336)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1254:1254:1254)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (1008:1008:1008) (1084:1084:1084)) + (PORT datad (1267:1267:1267) (1351:1351:1351)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (888:888:888)) + (PORT datab (681:681:681) (754:754:754)) + (PORT datac (1112:1112:1112) (1144:1144:1144)) + (PORT datad (1344:1344:1344) (1364:1364:1364)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (379:379:379)) + (PORT datab (922:922:922) (978:978:978)) + (PORT datac (1143:1143:1143) (1193:1193:1193)) + (PORT datad (532:532:532) (541:541:541)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1684:1684:1684)) + (PORT datac (962:962:962) (1030:1030:1030)) + (PORT datad (1190:1190:1190) (1306:1306:1306)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2228:2228:2228) (2321:2321:2321)) + (PORT datab (947:947:947) (989:989:989)) + (PORT datac (956:956:956) (981:981:981)) + (PORT datad (882:882:882) (922:922:922)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1539:1539:1539) (1650:1650:1650)) + (PORT datad (1192:1192:1192) (1308:1308:1308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1223:1223:1223)) + (PORT datab (685:685:685) (747:747:747)) + (PORT datac (1118:1118:1118) (1152:1152:1152)) + (PORT datad (1186:1186:1186) (1216:1216:1216)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (976:976:976)) + (PORT datab (995:995:995) (1100:1100:1100)) + (PORT datac (1226:1226:1226) (1304:1304:1304)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1472:1472:1472) (1535:1535:1535)) + (PORT datab (2071:2071:2071) (2150:2150:2150)) + (PORT datac (1320:1320:1320) (1415:1415:1415)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1294:1294:1294)) + (PORT datac (1494:1494:1494) (1561:1561:1561)) + (PORT datad (2599:2599:2599) (2706:2706:2706)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1294:1294:1294)) + (PORT datab (744:744:744) (802:802:802)) + (PORT datac (1712:1712:1712) (1798:1798:1798)) + (PORT datad (1358:1358:1358) (1397:1397:1397)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1371:1371:1371)) + (PORT datab (1266:1266:1266) (1384:1384:1384)) + (PORT datac (1654:1654:1654) (1826:1826:1826)) + (PORT datad (339:339:339) (363:363:363)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1292:1292:1292)) + (PORT datab (1397:1397:1397) (1449:1449:1449)) + (PORT datac (1799:1799:1799) (1853:1853:1853)) + (PORT datad (1129:1129:1129) (1176:1176:1176)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (940:940:940)) + (PORT datab (406:406:406) (436:436:436)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1246:1246:1246)) + (PORT datab (729:729:729) (768:768:768)) + (PORT datac (1235:1235:1235) (1255:1255:1255)) + (PORT datad (1872:1872:1872) (1997:1997:1997)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (873:873:873)) + (PORT datab (1951:1951:1951) (1993:1993:1993)) + (PORT datac (1454:1454:1454) (1529:1529:1529)) + (PORT datad (1622:1622:1622) (1648:1648:1648)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (252:252:252)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (579:579:579) (610:610:610)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datac (1195:1195:1195) (1297:1297:1297)) + (PORT datad (387:387:387) (415:415:415)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1763:1763:1763)) + (PORT datad (1223:1223:1223) (1330:1330:1330)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (767:767:767)) + (PORT datab (1100:1100:1100) (1171:1171:1171)) + (PORT datac (1616:1616:1616) (1690:1690:1690)) + (PORT datad (689:689:689) (753:753:753)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1538:1538:1538)) + (PORT datab (1027:1027:1027) (1079:1079:1079)) + (PORT datac (1504:1504:1504) (1527:1527:1527)) + (PORT datad (1207:1207:1207) (1259:1259:1259)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1702:1702:1702)) + (PORT datab (1485:1485:1485) (1658:1658:1658)) + (PORT datad (1253:1253:1253) (1386:1386:1386)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1918:1918:1918) (1960:1960:1960)) + (PORT datab (965:965:965) (1011:1011:1011)) + (PORT datac (1943:1943:1943) (2015:2015:2015)) + (PORT datad (1174:1174:1174) (1236:1236:1236)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1483:1483:1483)) + (PORT datab (1392:1392:1392) (1495:1495:1495)) + (PORT datac (1400:1400:1400) (1416:1416:1416)) + (PORT datad (1343:1343:1343) (1442:1442:1442)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1243:1243:1243)) + (PORT datab (893:893:893) (924:924:924)) + (PORT datac (1812:1812:1812) (1882:1882:1882)) + (PORT datad (1290:1290:1290) (1364:1364:1364)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1239:1239:1239)) + (PORT datab (1848:1848:1848) (1912:1912:1912)) + (PORT datac (1500:1500:1500) (1540:1540:1540)) + (PORT datad (1288:1288:1288) (1360:1360:1360)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -9216,31 +6612,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) (DELAY (ABSOLUTE - (PORT dataa (1755:1755:1755) (1823:1823:1823)) - (PORT datab (924:924:924) (949:949:949)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (621:621:621) (652:652:652)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (641:641:641) (662:662:662)) - (PORT datac (603:603:603) (623:623:623)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (940:940:940) (993:993:993)) + (PORT datab (1524:1524:1524) (1594:1594:1594)) + (PORT datac (1652:1652:1652) (1708:1708:1708)) + (PORT datad (1936:1936:1936) (2036:2036:2036)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9248,29 +6628,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) (DELAY (ABSOLUTE - (PORT dataa (995:995:995) (1066:1066:1066)) - (PORT datab (876:876:876) (900:900:900)) - (PORT datac (1640:1640:1640) (1827:1827:1827)) - (PORT datad (2138:2138:2138) (2305:2305:2305)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (915:915:915) (948:948:948)) + (PORT datab (1228:1228:1228) (1310:1310:1310)) + (PORT datac (618:618:618) (663:663:663)) + (PORT datad (240:240:240) (292:292:292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) (DELAY (ABSOLUTE - (PORT dataa (1112:1112:1112) (1152:1152:1152)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (863:863:863) (899:899:899)) + (PORT dataa (856:856:856) (866:866:866)) + (PORT datab (666:666:666) (702:702:702)) + (PORT datac (1402:1402:1402) (1435:1435:1435)) + (PORT datad (1808:1808:1808) (1891:1891:1891)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~13) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (953:953:953)) + (PORT datab (271:271:271) (334:334:334)) + (PORT datac (1089:1089:1089) (1107:1107:1107)) + (PORT datad (259:259:259) (307:307:307)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1153:1153:1153)) + (PORT datab (1026:1026:1026) (1145:1145:1145)) + (PORT datac (1638:1638:1638) (1828:1828:1828)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~58) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (626:626:626)) + (PORT datab (736:736:736) (833:833:833)) + (PORT datac (1191:1191:1191) (1283:1283:1283)) + (PORT datad (1588:1588:1588) (1652:1652:1652)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -9278,17 +6706,367 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (961:961:961)) + (PORT datab (643:643:643) (694:694:694)) + (PORT datac (871:871:871) (905:905:905)) + (PORT datad (1172:1172:1172) (1192:1192:1192)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (862:862:862) (901:901:901)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (940:940:940)) + (PORT datac (860:860:860) (868:868:868)) + (PORT datad (1135:1135:1135) (1144:1144:1144)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1242:1242:1242)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (635:635:635) (682:682:682)) + (PORT datad (1176:1176:1176) (1248:1248:1248)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~29) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1057:1057:1057)) + (PORT datab (1144:1144:1144) (1179:1179:1179)) + (PORT datac (1149:1149:1149) (1185:1185:1185)) + (PORT datad (2197:2197:2197) (2275:2275:2275)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1099:1099:1099)) + (PORT datab (995:995:995) (1099:1099:1099)) + (PORT datac (917:917:917) (935:935:935)) + (PORT datad (187:187:187) (222:222:222)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (795:795:795)) + (PORT datab (408:408:408) (439:439:439)) + (PORT datac (1626:1626:1626) (1651:1651:1651)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1699:1699:1699)) + (PORT datab (1278:1278:1278) (1423:1423:1423)) + (PORT datac (1455:1455:1455) (1620:1620:1620)) + (PORT datad (862:862:862) (899:899:899)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1005:1005:1005)) + (PORT datab (1858:1858:1858) (2004:2004:2004)) + (PORT datac (2264:2264:2264) (2329:2329:2329)) + (PORT datad (1177:1177:1177) (1229:1229:1229)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (933:933:933)) + (PORT datab (750:750:750) (821:821:821)) + (PORT datac (1736:1736:1736) (1797:1797:1797)) + (PORT datad (866:866:866) (882:882:882)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2348:2348:2348) (2562:2562:2562)) + (PORT datab (727:727:727) (761:761:761)) + (PORT datac (1323:1323:1323) (1391:1391:1391)) + (PORT datad (1870:1870:1870) (1996:1996:1996)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1226:1226:1226) (1294:1294:1294)) + (PORT datab (1247:1247:1247) (1286:1286:1286)) + (PORT datac (699:699:699) (737:737:737)) + (PORT datad (926:926:926) (985:985:985)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1083:1083:1083)) + (PORT datab (932:932:932) (962:962:962)) + (PORT datac (624:624:624) (681:681:681)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1904:1904:1904) (2042:2042:2042)) + (PORT datab (1311:1311:1311) (1413:1413:1413)) + (PORT datac (935:935:935) (980:980:980)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (564:564:564)) + (PORT datab (868:868:868) (883:883:883)) + (PORT datac (1058:1058:1058) (1084:1084:1084)) + (PORT datad (1402:1402:1402) (1440:1440:1440)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (770:770:770)) + (PORT datab (717:717:717) (795:795:795)) + (PORT datac (1061:1061:1061) (1072:1072:1072)) + (PORT datad (1174:1174:1174) (1204:1204:1204)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1535:1535:1535) (1560:1560:1560)) + (PORT datab (924:924:924) (948:948:948)) + (PORT datac (944:944:944) (990:990:990)) + (PORT datad (931:931:931) (942:942:942)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1694:1694:1694) (1763:1763:1763)) + (PORT datab (1709:1709:1709) (1745:1745:1745)) + (PORT datac (844:844:844) (878:878:878)) + (PORT datad (1561:1561:1561) (1659:1659:1659)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1615:1615:1615) (1693:1693:1693)) + (PORT datab (1807:1807:1807) (1889:1889:1889)) + (PORT datac (1349:1349:1349) (1411:1411:1411)) + (PORT datad (571:571:571) (579:579:579)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (911:911:911)) + (PORT datab (1006:1006:1006) (1090:1090:1090)) + (PORT datac (1009:1009:1009) (1086:1086:1086)) + (PORT datad (812:812:812) (831:831:831)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1415:1415:1415)) + (PORT datab (1566:1566:1566) (1696:1696:1696)) + (PORT datac (1807:1807:1807) (1909:1909:1909)) + (PORT datad (343:343:343) (367:367:367)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (922:922:922)) + (PORT datab (230:230:230) (280:280:280)) + (PORT datac (1357:1357:1357) (1394:1394:1394)) + (PORT datad (1074:1074:1074) (1101:1101:1101)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (352:352:352)) - (PORT datab (251:251:251) (304:304:304)) - (PORT datac (1170:1170:1170) (1219:1219:1219)) - (PORT datad (248:248:248) (302:302:302)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (1550:1550:1550) (1602:1602:1602)) + (PORT datab (965:965:965) (1008:1008:1008)) + (PORT datac (1887:1887:1887) (1918:1918:1918)) + (PORT datad (1174:1174:1174) (1233:1233:1233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9299,10 +7077,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) (DELAY (ABSOLUTE - (PORT dataa (1554:1554:1554) (1689:1689:1689)) - (PORT datab (1993:1993:1993) (2047:2047:2047)) - (PORT datac (873:873:873) (939:939:939)) - (PORT datad (1697:1697:1697) (1792:1792:1792)) + (PORT dataa (1754:1754:1754) (1821:1821:1821)) + (PORT datab (1521:1521:1521) (1651:1651:1651)) + (PORT datac (1491:1491:1491) (1653:1653:1653)) + (PORT datad (2202:2202:2202) (2322:2322:2322)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -9315,13 +7093,13 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (1238:1238:1238) (1290:1290:1290)) - (PORT datab (616:616:616) (641:641:641)) - (PORT datac (619:619:619) (670:670:670)) - (PORT datad (890:890:890) (915:915:915)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (630:630:630) (649:649:649)) + (PORT datab (836:836:836) (850:850:850)) + (PORT datac (618:618:618) (686:686:686)) + (PORT datad (1216:1216:1216) (1283:1283:1283)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -9331,686 +7109,42 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) (DELAY (ABSOLUTE - (PORT dataa (1847:1847:1847) (1963:1963:1963)) - (PORT datab (926:926:926) (986:986:986)) - (PORT datad (638:638:638) (671:671:671)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT datab (722:722:722) (792:792:792)) + (PORT datac (1102:1102:1102) (1125:1125:1125)) + (PORT datad (635:635:635) (654:654:654)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1154:1154:1154) (1181:1181:1181)) - (PORT datac (320:320:320) (344:344:344)) - (PORT datad (663:663:663) (726:726:726)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (227:227:227) (267:267:267)) - (PORT datac (613:613:613) (637:637:637)) + (PORT dataa (1160:1160:1160) (1164:1164:1164)) + (PORT datab (344:344:344) (379:379:379)) + (PORT datac (836:836:836) (859:859:859)) + (PORT datad (601:601:601) (623:623:623)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1960:1960:1960)) - (PORT datab (674:674:674) (708:708:708)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (903:903:903) (947:947:947)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1091:1091:1091)) - (PORT datab (1843:1843:1843) (1936:1936:1936)) - (PORT datac (990:990:990) (1056:1056:1056)) - (PORT datad (1223:1223:1223) (1265:1265:1265)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2284:2284:2284) (2463:2463:2463)) - (PORT datab (1844:1844:1844) (1935:1935:1935)) - (PORT datac (867:867:867) (913:913:913)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (886:886:886)) - (PORT datab (1403:1403:1403) (1513:1513:1513)) - (PORT datac (650:650:650) (711:711:711)) - (PORT datad (671:671:671) (755:755:755)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (348:348:348)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (247:247:247) (306:306:306)) - (PORT datad (1203:1203:1203) (1275:1275:1275)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (857:857:857)) - (PORT datab (630:630:630) (708:708:708)) - (PORT datac (832:832:832) (885:885:885)) - (PORT datad (661:661:661) (724:724:724)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (1562:1562:1562) (1606:1606:1606)) - (PORT datac (2770:2770:2770) (2816:2816:2816)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (703:703:703)) - (PORT datab (377:377:377) (403:403:403)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (896:896:896) (921:921:921)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1375:1375:1375)) - (PORT datab (1004:1004:1004) (1054:1054:1054)) - (PORT datac (959:959:959) (1026:1026:1026)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1372:1372:1372)) - (PORT datab (1005:1005:1005) (1052:1052:1052)) - (PORT datac (959:959:959) (1023:1023:1023)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1461:1461:1461) (1557:1557:1557)) - (PORT datab (1071:1071:1071) (1131:1131:1131)) - (PORT datac (1183:1183:1183) (1237:1237:1237)) - (PORT datad (1422:1422:1422) (1471:1471:1471)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (656:656:656)) - (PORT datab (204:204:204) (244:244:244)) - (PORT datac (1380:1380:1380) (1388:1388:1388)) - (PORT datad (1256:1256:1256) (1311:1311:1311)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1542:1542:1542) (1647:1647:1647)) - (PORT datab (1761:1761:1761) (1804:1804:1804)) - (PORT datac (605:605:605) (628:628:628)) - (PORT datad (631:631:631) (654:654:654)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT datab (688:688:688) (737:737:737)) - (PORT datac (381:381:381) (410:410:410)) - (PORT datad (853:853:853) (891:891:891)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (939:939:939)) - (PORT datab (1244:1244:1244) (1260:1260:1260)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (1433:1433:1433) (1449:1449:1449)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (925:925:925)) - (PORT datab (684:684:684) (737:737:737)) - (PORT datac (875:875:875) (914:914:914)) - (PORT datad (1472:1472:1472) (1513:1513:1513)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (671:671:671)) - (PORT datab (684:684:684) (737:737:737)) - (PORT datac (1663:1663:1663) (1676:1676:1676)) - (PORT datad (367:367:367) (388:388:388)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (673:673:673)) - (PORT datab (1692:1692:1692) (1710:1710:1710)) - (PORT datac (836:836:836) (839:839:839)) - (PORT datad (827:827:827) (859:859:859)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (669:669:669)) - (PORT datab (901:901:901) (931:931:931)) - (PORT datac (1661:1661:1661) (1674:1674:1674)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (637:637:637) (657:657:657)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1496:1496:1496)) - (PORT datac (1960:1960:1960) (2130:2130:2130)) - (PORT datad (1151:1151:1151) (1205:1205:1205)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1873:1873:1873)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datac (880:880:880) (894:894:894)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (979:979:979)) - (PORT datac (1035:1035:1035) (1109:1109:1109)) - (PORT datad (617:617:617) (626:626:626)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1681:1681:1681) (1791:1791:1791)) - (PORT datab (1812:1812:1812) (1917:1917:1917)) - (PORT datac (1337:1337:1337) (1365:1365:1365)) - (PORT datad (637:637:637) (687:687:687)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (974:974:974)) - (PORT datab (1062:1062:1062) (1114:1114:1114)) - (PORT datac (1488:1488:1488) (1575:1575:1575)) - (PORT datad (1194:1194:1194) (1262:1262:1262)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (250:250:250)) - (PORT datab (1520:1520:1520) (1602:1602:1602)) - (PORT datac (1087:1087:1087) (1105:1105:1105)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (960:960:960)) - (PORT datab (1658:1658:1658) (1699:1699:1699)) - (PORT datac (1280:1280:1280) (1331:1331:1331)) - (PORT datad (1594:1594:1594) (1614:1614:1614)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (668:668:668)) - (PORT datac (1213:1213:1213) (1256:1256:1256)) - (PORT datad (886:886:886) (936:936:936)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1479:1479:1479)) - (PORT datab (646:646:646) (667:667:667)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (939:939:939) (976:976:976)) - (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) (DELAY (ABSOLUTE - (PORT datac (588:588:588) (596:596:596)) - (PORT datad (863:863:863) (883:883:883)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (830:830:830) (842:842:842)) + (PORT dataa (717:717:717) (791:791:791)) + (PORT datab (1256:1256:1256) (1335:1335:1335)) + (PORT datac (643:643:643) (716:716:716)) + (PORT datad (2264:2264:2264) (2302:2302:2302)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (366:366:366) (387:387:387)) - (PORT datac (593:593:593) (608:608:608)) - (PORT datad (614:614:614) (631:631:631)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1357:1357:1357)) - (PORT datab (1610:1610:1610) (1651:1651:1651)) - (PORT datac (968:968:968) (1039:1039:1039)) - (PORT datad (2195:2195:2195) (2176:2176:2176)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (859:859:859)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (965:965:965) (1009:1009:1009)) - (PORT datad (1114:1114:1114) (1140:1140:1140)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1199:1199:1199)) - (PORT datab (902:902:902) (932:932:932)) - (PORT datac (956:956:956) (1022:1022:1022)) - (PORT datad (196:196:196) (233:233:233)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1279:1279:1279) (1383:1383:1383)) - (PORT datab (637:637:637) (659:659:659)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (955:955:955) (1046:1046:1046)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT datab (1245:1245:1245) (1295:1295:1295)) - (PORT datac (935:935:935) (984:984:984)) - (PORT datad (898:898:898) (966:966:966)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1219:1219:1219)) - (PORT datab (911:911:911) (944:944:944)) - (PORT datac (1136:1136:1136) (1156:1156:1156)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (1342:1342:1342) (1372:1372:1372)) - (PORT datad (1144:1144:1144) (1175:1175:1175)) (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (670:670:670)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (817:817:817) (835:835:835)) - (PORT datad (822:822:822) (842:842:842)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (675:675:675)) - (PORT datab (983:983:983) (1074:1074:1074)) - (PORT datac (1087:1087:1087) (1097:1097:1097)) - (PORT datad (1806:1806:1806) (1916:1916:1916)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10018,89 +7152,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (652:652:652) (674:674:674)) - (PORT datab (947:947:947) (979:979:979)) - (PORT datac (371:371:371) (399:399:399)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (618:618:618) (631:631:631)) - (PORT datac (871:871:871) (877:877:877)) - (PORT datad (577:577:577) (595:595:595)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1376:1376:1376)) - (PORT datab (978:978:978) (1026:1026:1026)) - (PORT datac (966:966:966) (1015:1015:1015)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT dataa (1276:1276:1276) (1362:1362:1362)) - (PORT datab (973:973:973) (1025:1025:1025)) - (PORT datac (974:974:974) (1023:1023:1023)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (536:536:536) (565:565:565)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (969:969:969)) - (PORT datab (2629:2629:2629) (2685:2685:2685)) - (PORT datac (187:187:187) (228:228:228)) - (PORT datad (1382:1382:1382) (1417:1417:1417)) + (PORT dataa (858:858:858) (874:874:874)) + (PORT datab (619:619:619) (644:644:644)) + (PORT datac (590:590:590) (603:603:603)) + (PORT datad (914:914:914) (963:963:963)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -10110,110 +7168,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~8) (DELAY (ABSOLUTE - (PORT dataa (1904:1904:1904) (2087:2087:2087)) - (PORT datab (1498:1498:1498) (1565:1565:1565)) - (PORT datad (1153:1153:1153) (1185:1185:1185)) + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1129:1129:1129) (1168:1168:1168)) + (PORT datac (906:906:906) (947:947:947)) + (PORT datad (814:814:814) (815:815:815)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1931:1931:1931) (1907:1907:1907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1652:1652:1652) (1684:1684:1684)) - (PORT datab (1728:1728:1728) (1737:1737:1737)) - (PORT datac (1191:1191:1191) (1239:1239:1239)) - (PORT datad (1223:1223:1223) (1265:1265:1265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) (DELAY (ABSOLUTE - (PORT dataa (1220:1220:1220) (1242:1242:1242)) - (PORT datab (1206:1206:1206) (1263:1263:1263)) - (PORT datac (1663:1663:1663) (1680:1680:1680)) - (PORT datad (577:577:577) (596:596:596)) + (PORT dataa (631:631:631) (706:706:706)) + (PORT datac (688:688:688) (784:784:784)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1541:1541:1541)) - (PORT datab (957:957:957) (1012:1012:1012)) - (PORT datac (1200:1200:1200) (1254:1254:1254)) - (PORT datad (1188:1188:1188) (1238:1238:1238)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) (DELAY (ABSOLUTE - (PORT dataa (618:618:618) (653:653:653)) - (PORT datab (1866:1866:1866) (1943:1943:1943)) - (PORT datac (1028:1028:1028) (1092:1092:1092)) - (PORT datad (2619:2619:2619) (2697:2697:2697)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1223:1223:1223) (1275:1275:1275)) - (PORT datab (1259:1259:1259) (1303:1303:1303)) - (PORT datac (863:863:863) (935:935:935)) - (PORT datad (890:890:890) (967:967:967)) + (PORT dataa (1038:1038:1038) (1109:1109:1109)) + (PORT datab (587:587:587) (609:609:609)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (202:202:202) (233:233:233)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (395:395:395)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (925:925:925) (968:968:968)) + (PORT datad (1436:1436:1436) (1453:1453:1453)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10221,12 +7228,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (INSTANCE z80_\|execute_\|setM1\~49) (DELAY (ABSOLUTE - (PORT datab (908:908:908) (944:944:944)) - (PORT datac (636:636:636) (655:655:655)) - (PORT datad (196:196:196) (221:221:221)) + (PORT datab (856:856:856) (900:900:900)) + (PORT datac (1990:1990:1990) (2053:2053:2053)) + (PORT datad (1807:1807:1807) (1897:1897:1897)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT datab (1101:1101:1101) (1165:1165:1165)) + (PORT datac (788:788:788) (826:826:826)) + (PORT datad (1111:1111:1111) (1156:1156:1156)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -10235,13 +7256,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (INSTANCE z80_\|execute_\|setM1\~52) (DELAY (ABSOLUTE - (PORT datab (232:232:232) (283:283:283)) - (PORT datac (2706:2706:2706) (2903:2903:2903)) - (PORT datad (218:218:218) (253:253:253)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (657:657:657) (672:672:672)) + (PORT datab (960:960:960) (996:996:996)) + (PORT datac (849:849:849) (896:896:896)) + (PORT datad (667:667:667) (718:718:718)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10249,31 +7272,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~9) (DELAY (ABSOLUTE - (PORT dataa (1596:1596:1596) (1646:1646:1646)) - (PORT datab (1499:1499:1499) (1573:1573:1573)) - (PORT datac (1471:1471:1471) (1570:1570:1570)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1329:1329:1329)) - (PORT datab (984:984:984) (1057:1057:1057)) - (PORT datac (1948:1948:1948) (2028:2028:2028)) - (PORT datad (1356:1356:1356) (1450:1450:1450)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT datab (1272:1272:1272) (1389:1389:1389)) + (PORT datac (1661:1661:1661) (1831:1831:1831)) + (PORT datad (393:393:393) (424:424:424)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10281,237 +7286,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (1478:1478:1478) (1539:1539:1539)) - (PORT datab (1303:1303:1303) (1403:1403:1403)) - (PORT datac (929:929:929) (1005:1005:1005)) - (PORT datad (1508:1508:1508) (1652:1652:1652)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1003:1003:1003)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (592:592:592) (642:642:642)) - (PORT datad (1235:1235:1235) (1275:1275:1275)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1525:1525:1525) (1588:1588:1588)) - (PORT datab (901:901:901) (934:934:934)) - (PORT datac (1455:1455:1455) (1495:1495:1495)) - (PORT datad (682:682:682) (736:736:736)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (956:956:956) (974:974:974)) - (PORT datac (625:625:625) (647:647:647)) - (PORT datad (575:575:575) (606:606:606)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (725:725:725)) - (PORT datab (1120:1120:1120) (1176:1176:1176)) - (PORT datac (1928:1928:1928) (1998:1998:1998)) - (PORT datad (809:809:809) (845:845:845)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (989:989:989)) - (PORT datab (556:556:556) (587:587:587)) - (PORT datac (963:963:963) (1008:1008:1008)) - (PORT datad (929:929:929) (951:951:951)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (376:376:376)) - (PORT datab (249:249:249) (290:290:290)) - (PORT datac (963:963:963) (1005:1005:1005)) - (PORT datad (929:929:929) (948:948:948)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1101:1101:1101)) - (PORT datab (783:783:783) (890:890:890)) - (PORT datac (726:726:726) (838:838:838)) - (PORT datad (626:626:626) (675:675:675)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1286:1286:1286)) - (PORT datab (342:342:342) (372:372:372)) - (PORT datac (1901:1901:1901) (2064:2064:2064)) - (PORT datad (617:617:617) (629:629:629)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (278:278:278)) - (PORT datab (397:397:397) (437:437:437)) - (PORT datac (975:975:975) (1014:1014:1014)) - (PORT datad (812:812:812) (837:837:837)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (1213:1213:1213) (1257:1257:1257)) - (PORT datad (323:323:323) (347:347:347)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1627:1627:1627) (1675:1675:1675)) - (PORT datab (1195:1195:1195) (1246:1246:1246)) - (PORT datac (1289:1289:1289) (1403:1403:1403)) - (PORT datad (691:691:691) (746:746:746)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (614:614:614) (638:638:638)) - (PORT datac (1132:1132:1132) (1151:1151:1151)) - (PORT datad (696:696:696) (744:744:744)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (726:726:726) (791:791:791)) - (PORT datab (668:668:668) (719:719:719)) - (PORT datac (639:639:639) (684:684:684)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (1154:1154:1154) (1175:1175:1175)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1277:1277:1277) (1396:1396:1396)) + (PORT datac (1664:1664:1664) (1837:1837:1837)) + (PORT datad (391:391:391) (421:421:421)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10522,10 +7303,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (639:639:639)) - (PORT datab (1176:1176:1176) (1220:1220:1220)) - (PORT datac (1428:1428:1428) (1462:1462:1462)) - (PORT datad (862:862:862) (888:888:888)) + (PORT dataa (1293:1293:1293) (1334:1334:1334)) + (PORT datab (1417:1417:1417) (1431:1431:1431)) + (PORT datac (1163:1163:1163) (1241:1241:1241)) + (PORT datad (656:656:656) (693:693:693)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -10538,881 +7319,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (239:239:239) (291:291:291)) - (PORT datab (986:986:986) (1028:1028:1028)) - (PORT datac (645:645:645) (702:702:702)) - (PORT datad (319:319:319) (331:331:331)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT datab (3601:3601:3601) (3704:3704:3704)) - (PORT datad (1514:1514:1514) (1586:1586:1586)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (641:641:641)) - (PORT datab (1172:1172:1172) (1203:1203:1203)) - (PORT datac (626:626:626) (659:659:659)) - (PORT datad (828:828:828) (846:846:846)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1853:1853:1853) (1955:1955:1955)) - (PORT datab (899:899:899) (946:946:946)) - (PORT datac (894:894:894) (920:920:920)) - (PORT datad (854:854:854) (879:879:879)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datab (672:672:672) (700:700:700)) - (PORT datad (1120:1120:1120) (1145:1145:1145)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT datab (885:885:885) (918:918:918)) - (PORT datac (1069:1069:1069) (1130:1130:1130)) - (PORT datad (1496:1496:1496) (1538:1538:1538)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (390:390:390)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (552:552:552) (564:564:564)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1826:1826:1826)) - (PORT datab (1263:1263:1263) (1332:1332:1332)) - (PORT datac (1375:1375:1375) (1403:1403:1403)) - (PORT datad (588:588:588) (608:608:608)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2328:2328:2328)) - (PORT datab (879:879:879) (911:911:911)) - (PORT datac (1575:1575:1575) (1707:1707:1707)) - (PORT datad (1688:1688:1688) (1747:1747:1747)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (972:972:972)) - (PORT datab (1342:1342:1342) (1395:1395:1395)) - (PORT datac (866:866:866) (929:929:929)) - (PORT datad (1427:1427:1427) (1449:1449:1449)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (725:725:725)) - (PORT datab (1471:1471:1471) (1517:1517:1517)) - (PORT datac (849:849:849) (874:874:874)) - (PORT datad (669:669:669) (723:723:723)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1315:1315:1315)) - (PORT datab (936:936:936) (978:978:978)) - (PORT datac (1411:1411:1411) (1475:1475:1475)) - (PORT datad (1767:1767:1767) (1823:1823:1823)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (859:859:859) (876:876:876)) - (PORT datad (327:327:327) (351:351:351)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (655:655:655) (688:688:688)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (975:975:975)) - (PORT datab (986:986:986) (1041:1041:1041)) - (PORT datac (871:871:871) (933:933:933)) - (PORT datad (885:885:885) (915:915:915)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1793:1793:1793) (1875:1875:1875)) - (PORT datab (1527:1527:1527) (1572:1572:1572)) - (PORT datac (1068:1068:1068) (1127:1127:1127)) - (PORT datad (856:856:856) (879:879:879)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1222:1222:1222)) - (PORT datab (882:882:882) (915:915:915)) - (PORT datac (1069:1069:1069) (1128:1128:1128)) - (PORT datad (1492:1492:1492) (1533:1533:1533)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1832:1832:1832)) - (PORT datab (1926:1926:1926) (1967:1967:1967)) - (PORT datac (1557:1557:1557) (1584:1584:1584)) - (PORT datad (1049:1049:1049) (1102:1102:1102)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (287:287:287)) - (PORT datab (237:237:237) (282:282:282)) - (PORT datac (1015:1015:1015) (1061:1061:1061)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1650:1650:1650) (1827:1827:1827)) - (PORT datac (1232:1232:1232) (1346:1346:1346)) - (PORT datad (1116:1116:1116) (1144:1144:1144)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1446:1446:1446)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (825:825:825) (841:841:841)) - (PORT datad (838:838:838) (886:886:886)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1230:1230:1230)) - (PORT datac (917:917:917) (956:956:956)) - (PORT datad (859:859:859) (899:899:899)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1383:1383:1383)) - (PORT datab (933:933:933) (971:971:971)) - (PORT datac (1396:1396:1396) (1536:1536:1536)) - (PORT datad (1181:1181:1181) (1244:1244:1244)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (978:978:978)) - (PORT datab (1540:1540:1540) (1664:1664:1664)) - (PORT datac (2216:2216:2216) (2296:2296:2296)) - (PORT datad (1530:1530:1530) (1622:1622:1622)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (1184:1184:1184) (1245:1245:1245)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1822:1822:1822)) - (PORT datab (355:355:355) (385:385:385)) - (PORT datac (1228:1228:1228) (1341:1341:1341)) - (PORT datad (604:604:604) (639:639:639)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (641:641:641)) - (PORT datab (966:966:966) (999:999:999)) - (PORT datac (663:663:663) (694:694:694)) - (PORT datad (594:594:594) (614:614:614)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (901:901:901)) - (PORT datab (211:211:211) (255:255:255)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1560:1560:1560) (1654:1654:1654)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (631:631:631)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (628:628:628) (658:658:658)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (643:643:643) (669:669:669)) - (PORT datac (823:823:823) (829:829:829)) - (PORT datad (1688:1688:1688) (1742:1742:1742)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (393:393:393)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1204:1204:1204) (1257:1257:1257)) - (PORT datad (1048:1048:1048) (1082:1082:1082)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT dataa (1360:1360:1360) (1460:1460:1460)) - (PORT datab (1167:1167:1167) (1197:1197:1197)) - (PORT datad (1607:1607:1607) (1719:1719:1719)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1598:1598:1598) (1645:1645:1645)) - (PORT datab (1618:1618:1618) (1773:1773:1773)) - (PORT datac (872:872:872) (933:933:933)) - (PORT datad (1311:1311:1311) (1374:1374:1374)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (440:440:440)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datac (1467:1467:1467) (1528:1528:1528)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1502:1502:1502)) - (PORT datab (1104:1104:1104) (1116:1116:1116)) - (PORT datac (1503:1503:1503) (1564:1564:1564)) - (PORT datad (635:635:635) (657:657:657)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (647:647:647)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (617:617:617) (656:656:656)) - (PORT datad (631:631:631) (650:650:650)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1293:1293:1293)) - (PORT datab (2419:2419:2419) (2477:2477:2477)) - (PORT datac (1675:1675:1675) (1710:1710:1710)) - (PORT datad (985:985:985) (1038:1038:1038)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1100:1100:1100)) - (PORT datab (759:759:759) (866:866:866)) - (PORT datac (608:608:608) (629:629:629)) - (PORT datad (884:884:884) (917:917:917)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1204:1204:1204)) - (PORT datab (372:372:372) (397:397:397)) - (PORT datac (920:920:920) (973:973:973)) - (PORT datad (818:818:818) (865:865:865)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (242:242:242) (289:289:289)) - (PORT datac (202:202:202) (247:247:247)) - (PORT datad (868:868:868) (925:925:925)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1598:1598:1598)) - (PORT datab (1027:1027:1027) (1116:1116:1116)) - (PORT datac (337:337:337) (366:366:366)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1398:1398:1398) (1425:1425:1425)) - (PORT datab (1123:1123:1123) (1145:1145:1145)) - (PORT datac (1387:1387:1387) (1417:1417:1417)) - (PORT datad (337:337:337) (362:362:362)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (955:955:955)) - (PORT datab (705:705:705) (772:772:772)) - (PORT datac (665:665:665) (748:748:748)) - (PORT datad (575:575:575) (591:591:591)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (500:500:500)) - (PORT datab (269:269:269) (353:353:353)) - (PORT datac (1395:1395:1395) (1507:1507:1507)) - (PORT datad (1175:1175:1175) (1258:1258:1258)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1596:1596:1596) (1729:1729:1729)) - (PORT datab (1938:1938:1938) (2043:2043:2043)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (2588:2588:2588) (2666:2666:2666)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2229:2229:2229) (2274:2274:2274)) - (PORT datab (2486:2486:2486) (2693:2693:2693)) - (PORT datac (2230:2230:2230) (2299:2299:2299)) - (PORT datad (1642:1642:1642) (1694:1694:1694)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1286:1286:1286)) - (PORT datab (879:879:879) (905:905:905)) - (PORT datac (2230:2230:2230) (2302:2302:2302)) - (PORT datad (2452:2452:2452) (2652:2652:2652)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (2068:2068:2068) (2112:2112:2112)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (865:865:865)) - (PORT datab (828:828:828) (846:846:846)) - (PORT datac (1565:1565:1565) (1694:1694:1694)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (400:400:400)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (1200:1200:1200) (1252:1252:1252)) - (PORT datad (861:861:861) (911:911:911)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) - (DELAY - (ABSOLUTE - (PORT datac (858:858:858) (869:869:869)) - (PORT datad (1351:1351:1351) (1366:1366:1366)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1515:1515:1515)) - (PORT datab (1191:1191:1191) (1239:1239:1239)) - (PORT datac (1752:1752:1752) (1874:1874:1874)) - (PORT datad (1446:1446:1446) (1521:1521:1521)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (947:947:947)) - (PORT datab (683:683:683) (705:705:705)) - (PORT datac (2071:2071:2071) (2251:2251:2251)) - (PORT datad (1432:1432:1432) (1451:1451:1451)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (844:844:844)) - (PORT datab (887:887:887) (909:909:909)) - (PORT datad (1197:1197:1197) (1224:1224:1224)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (306:306:306) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (842:842:842)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (788:788:788) (792:792:792)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1149:1149:1149)) - (PORT datab (922:922:922) (983:983:983)) - (PORT datac (1898:1898:1898) (2064:2064:2064)) - (PORT datad (1207:1207:1207) (1289:1289:1289)) + (PORT dataa (1216:1216:1216) (1262:1262:1262)) + (PORT datab (1636:1636:1636) (1661:1661:1661)) + (PORT datac (1173:1173:1173) (1214:1214:1214)) + (PORT datad (316:316:316) (338:338:338)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -11422,1231 +7332,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (895:895:895) (939:939:939)) - (PORT datab (457:457:457) (532:532:532)) - (PORT datac (420:420:420) (489:489:489)) - (PORT datad (984:984:984) (1034:1034:1034)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1830:1830:1830) (1974:1974:1974)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (678:678:678) (727:727:727)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1151:1151:1151)) - (PORT datab (1237:1237:1237) (1272:1272:1272)) - (PORT datac (1201:1201:1201) (1255:1255:1255)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (759:759:759)) - (PORT datab (1508:1508:1508) (1551:1551:1551)) - (PORT datac (1985:1985:1985) (2041:2041:2041)) - (PORT datad (1440:1440:1440) (1501:1501:1501)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (933:933:933)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (316:316:316) (335:335:335)) - (PORT datad (590:590:590) (623:623:623)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (2828:2828:2828) (3036:3036:3036)) - (PORT datab (1101:1101:1101) (1114:1114:1114)) - (PORT datac (1504:1504:1504) (1566:1566:1566)) - (PORT datad (1269:1269:1269) (1342:1342:1342)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (900:900:900)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1558:1558:1558) (1654:1654:1654)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1284:1284:1284)) - (PORT datab (1396:1396:1396) (1445:1445:1445)) - (PORT datac (1194:1194:1194) (1232:1232:1232)) - (PORT datad (1411:1411:1411) (1507:1507:1507)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1304:1304:1304)) - (PORT datab (865:865:865) (920:920:920)) - (PORT datac (1734:1734:1734) (1769:1769:1769)) - (PORT datad (823:823:823) (888:888:888)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (790:790:790)) - (PORT datac (1371:1371:1371) (1479:1479:1479)) - (PORT datad (672:672:672) (752:752:752)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1120:1120:1120)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (1374:1374:1374) (1452:1452:1452)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (773:773:773)) - (PORT datab (666:666:666) (735:735:735)) - (PORT datac (1203:1203:1203) (1259:1259:1259)) - (PORT datad (1108:1108:1108) (1151:1151:1151)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1172:1172:1172)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (2260:2260:2260) (2337:2337:2337)) - (PORT datac (1572:1572:1572) (1704:1704:1704)) - (PORT datad (1683:1683:1683) (1743:1743:1743)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1491:1491:1491)) - (PORT datab (1113:1113:1113) (1143:1143:1143)) - (PORT datac (321:321:321) (347:347:347)) - (PORT datad (606:606:606) (641:641:641)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1380:1380:1380)) - (PORT datab (980:980:980) (1076:1076:1076)) - (PORT datac (892:892:892) (917:917:917)) - (PORT datad (615:615:615) (665:665:665)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (661:661:661)) - (PORT datab (1481:1481:1481) (1539:1539:1539)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (1257:1257:1257) (1315:1315:1315)) + (PORT dataa (583:583:583) (600:600:600)) + (PORT datab (1201:1201:1201) (1229:1229:1229)) + (PORT datac (1714:1714:1714) (1772:1772:1772)) + (PORT datad (1171:1171:1171) (1220:1220:1220)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1063:1063:1063)) - (PORT datab (906:906:906) (923:923:923)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (890:890:890) (926:926:926)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (233:233:233) (284:284:284)) - (PORT datac (865:865:865) (890:890:890)) - (PORT datad (217:217:217) (249:249:249)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2362:2362:2362) (2435:2435:2435)) - (PORT datab (2736:2736:2736) (2936:2936:2936)) - (PORT datad (869:869:869) (926:926:926)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (668:668:668)) - (PORT datab (632:632:632) (661:661:661)) - (PORT datac (624:624:624) (652:652:652)) - (PORT datad (1153:1153:1153) (1193:1193:1193)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (664:664:664)) - (PORT datab (641:641:641) (658:658:658)) - (PORT datac (649:649:649) (669:669:669)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (1429:1429:1429) (1578:1578:1578)) - (PORT datab (948:948:948) (1000:1000:1000)) - (PORT datac (1287:1287:1287) (1342:1342:1342)) - (PORT datad (1181:1181:1181) (1244:1244:1244)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (973:973:973)) - (PORT datab (1342:1342:1342) (1392:1392:1392)) - (PORT datac (326:326:326) (353:353:353)) - (PORT datad (1427:1427:1427) (1449:1449:1449)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (656:656:656) (678:678:678)) - (PORT datac (928:928:928) (941:941:941)) - (PORT datad (180:180:180) (211:211:211)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (914:914:914)) - (PORT datab (1416:1416:1416) (1546:1546:1546)) - (PORT datac (565:565:565) (575:575:575)) - (PORT datad (936:936:936) (1040:1040:1040)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1375:1375:1375)) - (PORT datab (1855:1855:1855) (2010:2010:2010)) - (PORT datac (1899:1899:1899) (2062:2062:2062)) - (PORT datad (1056:1056:1056) (1088:1088:1088)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (294:294:294)) - (PORT datab (908:908:908) (935:935:935)) - (PORT datac (1721:1721:1721) (1807:1807:1807)) - (PORT datad (644:644:644) (655:655:655)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1022:1022:1022)) - (PORT datab (1458:1458:1458) (1479:1479:1479)) - (PORT datac (1863:1863:1863) (1883:1883:1883)) - (PORT datad (891:891:891) (942:942:942)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (899:899:899) (963:963:963)) - (PORT datac (1275:1275:1275) (1353:1353:1353)) - (PORT datad (819:819:819) (820:820:820)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1011:1011:1011)) - (PORT datab (1539:1539:1539) (1661:1661:1661)) - (PORT datac (2217:2217:2217) (2294:2294:2294)) - (PORT datad (1527:1527:1527) (1620:1620:1620)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (950:950:950) (1002:1002:1002)) - (PORT datab (1222:1222:1222) (1268:1268:1268)) - (PORT datac (825:825:825) (834:834:834)) - (PORT datad (586:586:586) (604:604:604)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1191:1191:1191) (1202:1202:1202)) - (PORT datac (550:550:550) (570:570:570)) - (PORT datad (623:623:623) (657:657:657)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1148:1148:1148) (1198:1198:1198)) - (PORT datab (1473:1473:1473) (1535:1535:1535)) - (PORT datac (1063:1063:1063) (1084:1084:1084)) - (PORT datad (1433:1433:1433) (1485:1485:1485)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (842:842:842) (885:885:885)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (433:433:433)) - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (1189:1189:1189) (1253:1253:1253)) - (PORT datad (646:646:646) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (875:875:875)) - (PORT datab (1717:1717:1717) (1789:1789:1789)) - (PORT datad (1811:1811:1811) (1901:1901:1901)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (846:846:846)) - (PORT datab (887:887:887) (908:908:908)) - (PORT datad (1196:1196:1196) (1223:1223:1223)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (841:841:841)) - (PORT datab (248:248:248) (331:331:331)) - (PORT datac (787:787:787) (792:792:792)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datac (1412:1412:1412) (1417:1417:1417)) - (PORT datad (1852:1852:1852) (1892:1892:1892)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (287:287:287)) - (PORT datac (1407:1407:1407) (1415:1415:1415)) - (PORT datad (1854:1854:1854) (1894:1894:1894)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (991:991:991) (1026:1026:1026)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1717:1717:1717) (1793:1793:1793)) - (PORT datac (821:821:821) (841:841:841)) - (PORT datad (1809:1809:1809) (1899:1899:1899)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (994:994:994) (1029:1029:1029)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (319:319:319)) - (PORT datab (1080:1080:1080) (1115:1115:1115)) - (PORT datad (360:360:360) (421:421:421)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1479:1479:1479) (1540:1540:1540)) - (PORT datab (1114:1114:1114) (1149:1149:1149)) - (PORT datac (926:926:926) (1002:1002:1002)) - (PORT datad (579:579:579) (597:597:597)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (437:437:437)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (204:204:204) (249:249:249)) - (PORT datad (1311:1311:1311) (1345:1345:1345)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (2034:2034:2034) (2206:2206:2206)) - (PORT datab (1368:1368:1368) (1522:1522:1522)) - (PORT datac (1094:1094:1094) (1159:1159:1159)) - (PORT datad (902:902:902) (911:911:911)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1003:1003:1003)) - (PORT datab (1101:1101:1101) (1135:1135:1135)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (876:876:876) (901:901:901)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1199:1199:1199)) - (PORT datab (961:961:961) (1031:1031:1031)) - (PORT datac (1199:1199:1199) (1282:1282:1282)) - (PORT datad (2867:2867:2867) (2961:2961:2961)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1363:1363:1363) (1378:1378:1378)) - (PORT datad (644:644:644) (658:658:658)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2294:2294:2294) (2473:2473:2473)) - (PORT datab (1742:1742:1742) (1828:1828:1828)) - (PORT datac (1441:1441:1441) (1490:1490:1490)) - (PORT datad (1101:1101:1101) (1143:1143:1143)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1146:1146:1146)) - (PORT datab (1219:1219:1219) (1250:1250:1250)) - (PORT datac (1199:1199:1199) (1241:1241:1241)) - (PORT datad (2219:2219:2219) (2243:2243:2243)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1207:1207:1207)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (838:838:838) (886:886:886)) - (PORT datad (2017:2017:2017) (2045:2045:2045)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1272:1272:1272)) - (PORT datab (1362:1362:1362) (1402:1402:1402)) - (PORT datac (892:892:892) (931:931:931)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1355:1355:1355)) - (PORT datad (870:870:870) (922:922:922)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (986:986:986)) - (PORT datab (653:653:653) (692:692:692)) - (PORT datac (1951:1951:1951) (2031:2031:2031)) - (PORT datad (1598:1598:1598) (1743:1743:1743)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (975:975:975)) - (PORT datab (978:978:978) (1029:1029:1029)) - (PORT datac (1362:1362:1362) (1399:1399:1399)) - (PORT datad (597:597:597) (611:611:611)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1210:1210:1210)) - (PORT datab (654:654:654) (692:692:692)) - (PORT datac (923:923:923) (937:937:937)) - (PORT datad (855:855:855) (865:865:865)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (301:301:301)) - (PORT datab (928:928:928) (974:974:974)) - (PORT datac (1453:1453:1453) (1529:1529:1529)) - (PORT datad (845:845:845) (857:857:857)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (574:574:574) (585:585:585)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (720:720:720)) - (PORT datab (1610:1610:1610) (1651:1651:1651)) - (PORT datac (1280:1280:1280) (1319:1319:1319)) - (PORT datad (891:891:891) (939:939:939)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (634:634:634)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (614:614:614) (636:636:636)) - (PORT datad (913:913:913) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (386:386:386)) - (PORT datab (1199:1199:1199) (1267:1267:1267)) - (PORT datac (1595:1595:1595) (1618:1618:1618)) - (PORT datad (972:972:972) (1026:1026:1026)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (622:622:622) (668:668:668)) - (PORT datad (869:869:869) (889:889:889)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1286:1286:1286)) - (PORT datab (1475:1475:1475) (1512:1512:1512)) - (PORT datac (1132:1132:1132) (1166:1166:1166)) - (PORT datad (1185:1185:1185) (1228:1228:1228)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (381:381:381)) - (PORT datab (1367:1367:1367) (1378:1378:1378)) - (PORT datac (1077:1077:1077) (1101:1101:1101)) - (PORT datad (1342:1342:1342) (1364:1364:1364)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (741:741:741)) - (PORT datab (919:919:919) (951:951:951)) - (PORT datad (1175:1175:1175) (1224:1224:1224)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) - (DELAY - (ABSOLUTE - (PORT dataa (2212:2212:2212) (2402:2402:2402)) - (PORT datab (1581:1581:1581) (1722:1722:1722)) - (PORT datac (1487:1487:1487) (1611:1611:1611)) - (PORT datad (861:861:861) (890:890:890)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1871:1871:1871)) - (PORT datab (1184:1184:1184) (1250:1250:1250)) - (PORT datac (1904:1904:1904) (1967:1967:1967)) - (PORT datad (1103:1103:1103) (1118:1118:1118)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (401:401:401)) - (PORT datab (641:641:641) (670:670:670)) - (PORT datac (635:635:635) (656:656:656)) - (PORT datad (592:592:592) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1171:1171:1171)) - (PORT datab (882:882:882) (919:919:919)) - (PORT datac (1764:1764:1764) (1841:1841:1841)) - (PORT datad (1133:1133:1133) (1176:1176:1176)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1028:1028:1028)) - (PORT datab (890:890:890) (914:914:914)) - (PORT datac (933:933:933) (977:977:977)) - (PORT datad (1405:1405:1405) (1453:1453:1453)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1187:1187:1187) (1232:1232:1232)) - (PORT datad (616:616:616) (660:660:660)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1278:1278:1278)) - (PORT datab (971:971:971) (1028:1028:1028)) - (PORT datac (871:871:871) (935:935:935)) - (PORT datad (1211:1211:1211) (1261:1261:1261)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (605:605:605) (631:631:631)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) (DELAY (ABSOLUTE - (PORT dataa (1244:1244:1244) (1332:1332:1332)) - (PORT datab (983:983:983) (1057:1057:1057)) - (PORT datac (644:644:644) (684:684:684)) - (PORT datad (1355:1355:1355) (1453:1453:1453)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (983:983:983) (1082:1082:1082)) + (PORT datab (1158:1158:1158) (1188:1188:1188)) + (PORT datac (2045:2045:2045) (2175:2175:2175)) + (PORT datad (904:904:904) (972:972:972)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (971:971:971)) - (PORT datab (1396:1396:1396) (1491:1491:1491)) - (PORT datac (646:646:646) (684:684:684)) - (PORT datad (359:359:359) (387:387:387)) + (PORT dataa (1420:1420:1420) (1489:1489:1489)) + (PORT datab (695:695:695) (751:751:751)) + (PORT datac (605:605:605) (662:662:662)) + (PORT datad (1060:1060:1060) (1056:1056:1056)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -12656,345 +7380,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (1912:1912:1912) (1997:1997:1997)) - (PORT datab (1642:1642:1642) (1792:1792:1792)) - (PORT datac (607:607:607) (647:647:647)) - (PORT datad (1742:1742:1742) (1827:1827:1827)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (684:684:684) (736:736:736)) + (PORT datad (345:345:345) (369:369:369)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1111:1111:1111) (1149:1149:1149)) - (PORT datab (933:933:933) (967:967:967)) - (PORT datac (2220:2220:2220) (2323:2323:2323)) - (PORT datad (1600:1600:1600) (1743:1743:1743)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1383:1383:1383)) - (PORT datab (934:934:934) (970:970:970)) - (PORT datac (2216:2216:2216) (2296:2296:2296)) - (PORT datad (1503:1503:1503) (1626:1626:1626)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1067:1067:1067)) - (PORT datab (877:877:877) (898:898:898)) - (PORT datac (210:210:210) (250:250:250)) - (PORT datad (202:202:202) (229:229:229)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (699:699:699)) - (PORT datab (1206:1206:1206) (1268:1268:1268)) - (PORT datac (1250:1250:1250) (1284:1284:1284)) - (PORT datad (568:568:568) (578:578:578)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1039:1039:1039)) - (PORT datab (1167:1167:1167) (1188:1188:1188)) - (PORT datac (1404:1404:1404) (1438:1438:1438)) - (PORT datad (912:912:912) (940:940:940)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (677:677:677)) - (PORT datab (921:921:921) (977:977:977)) - (PORT datac (1473:1473:1473) (1537:1537:1537)) - (PORT datad (1145:1145:1145) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (933:933:933)) - (PORT datab (1131:1131:1131) (1170:1170:1170)) - (PORT datac (367:367:367) (395:395:395)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (414:414:414) (443:443:443)) + (PORT datab (604:604:604) (620:620:620)) + (PORT datac (673:673:673) (707:707:707)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1285:1285:1285)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (186:186:186) (225:225:225)) - (PORT datad (2031:2031:2031) (2148:2148:2148)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (237:237:237) (281:281:281)) - (PORT datac (208:208:208) (249:249:249)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (3682:3682:3682) (3765:3765:3765)) - (PORT datab (960:960:960) (1060:1060:1060)) - (PORT datac (1232:1232:1232) (1308:1308:1308)) - (PORT datad (669:669:669) (723:723:723)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1998:1998:1998) (2157:2157:2157)) - (PORT datab (1471:1471:1471) (1519:1519:1519)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (1320:1320:1320) (1494:1494:1494)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (790:790:790)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (1592:1592:1592) (1634:1634:1634)) - (PORT datad (1467:1467:1467) (1572:1572:1572)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1102:1102:1102)) - (PORT datab (786:786:786) (892:892:892)) - (PORT datac (1471:1471:1471) (1536:1536:1536)) - (PORT datad (633:633:633) (692:692:692)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2044:2044:2044) (2134:2134:2134)) - (PORT datab (1124:1124:1124) (1155:1155:1155)) - (PORT datac (860:860:860) (892:892:892)) - (PORT datad (666:666:666) (722:722:722)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1100:1100:1100)) - (PORT datab (759:759:759) (866:866:866)) - (PORT datac (1473:1473:1473) (1536:1536:1536)) - (PORT datad (893:893:893) (939:939:939)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1473:1473:1473) (1522:1522:1522)) - (PORT datac (1014:1014:1014) (1048:1048:1048)) - (PORT datad (607:607:607) (642:642:642)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (997:997:997)) - (PORT datab (1257:1257:1257) (1285:1285:1285)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (867:867:867) (902:902:902)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1728:1728:1728) (1837:1837:1837)) - (PORT datac (1359:1359:1359) (1427:1427:1427)) - (PORT datad (1691:1691:1691) (1791:1791:1791)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (649:649:649)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1066:1066:1066) (1088:1088:1088)) - (PORT datad (841:841:841) (877:877:877)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (672:672:672)) - (PORT datab (1188:1188:1188) (1223:1223:1223)) - (PORT datac (506:506:506) (518:518:518)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (653:653:653) (697:697:697)) + (PORT datac (928:928:928) (962:962:962)) + (PORT datad (893:893:893) (916:916:916)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) (DELAY (ABSOLUTE - (PORT dataa (957:957:957) (1055:1055:1055)) - (PORT datab (1495:1495:1495) (1572:1572:1572)) - (PORT datac (190:190:190) (232:232:232)) - (PORT datad (205:205:205) (242:242:242)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1583:1583:1583) (1769:1769:1769)) + (PORT datac (1549:1549:1549) (1691:1691:1691)) + (PORT datad (687:687:687) (752:752:752)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13005,11 +7439,39 @@ (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) (DELAY (ABSOLUTE - (PORT dataa (1404:1404:1404) (1572:1572:1572)) - (PORT datac (1211:1211:1211) (1292:1292:1292)) - (PORT datad (1320:1320:1320) (1484:1484:1484)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1560:1560:1560) (1637:1637:1637)) + (PORT datab (1349:1349:1349) (1459:1459:1459)) + (PORT datad (1016:1016:1016) (1138:1138:1138)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (2972:2972:2972) (3099:3099:3099)) + (PORT datac (910:910:910) (979:979:979)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2420:2420:2420) (2568:2568:2568)) + (PORT datab (663:663:663) (692:692:692)) + (PORT datac (1260:1260:1260) (1346:1346:1346)) + (PORT datad (1321:1321:1321) (1402:1402:1402)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13019,28 +7481,28 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) (DELAY (ABSOLUTE - (PORT dataa (1404:1404:1404) (1567:1567:1567)) - (PORT datab (1663:1663:1663) (1731:1731:1731)) - (PORT datac (1737:1737:1737) (1850:1850:1850)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1242:1242:1242) (1314:1314:1314)) + (PORT datab (1272:1272:1272) (1376:1376:1376)) + (PORT datac (818:818:818) (822:822:822)) + (PORT datad (620:620:620) (663:663:663)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) (DELAY (ABSOLUTE - (PORT dataa (1403:1403:1403) (1571:1571:1571)) - (PORT datab (2575:2575:2575) (2767:2767:2767)) - (PORT datac (1204:1204:1204) (1249:1249:1249)) - (PORT datad (887:887:887) (915:915:915)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (713:713:713) (792:792:792)) + (PORT datac (1151:1151:1151) (1177:1177:1177)) + (PORT datad (1173:1173:1173) (1202:1202:1202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13051,12 +7513,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) (DELAY (ABSOLUTE - (PORT dataa (1241:1241:1241) (1265:1265:1265)) - (PORT datab (618:618:618) (643:643:643)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (350:350:350) (390:390:390)) + (PORT datab (1105:1105:1105) (1137:1137:1137)) + (PORT datac (196:196:196) (229:229:229)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13064,30 +7526,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1682:1682:1682) (1783:1783:1783)) - (PORT datab (2598:2598:2598) (2784:2784:2784)) - (PORT datac (1652:1652:1652) (1819:1819:1819)) - (PORT datad (1573:1573:1573) (1595:1595:1595)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1265:1265:1265) (1319:1319:1319)) - (PORT datab (1090:1090:1090) (1145:1145:1145)) - (PORT datac (1586:1586:1586) (1738:1738:1738)) - (PORT datad (1474:1474:1474) (1508:1508:1508)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1392:1392:1392) (1400:1400:1400)) + (PORT datab (1623:1623:1623) (1756:1756:1756)) + (PORT datac (907:907:907) (980:980:980)) + (PORT datad (650:650:650) (700:700:700)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13096,13 +7542,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) + (INSTANCE z80_\|pla_decode_\|Equal10\~1) (DELAY (ABSOLUTE - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (1089:1089:1089) (1133:1133:1133)) - (PORT datad (218:218:218) (256:256:256)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT datac (1560:1560:1560) (1661:1661:1661)) + (PORT datad (1255:1255:1255) (1387:1387:1387)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1746:1746:1746) (1793:1793:1793)) + (PORT datab (1486:1486:1486) (1656:1656:1656)) + (PORT datac (1391:1391:1391) (1450:1450:1450)) + (PORT datad (188:188:188) (222:222:222)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (900:900:900)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1465:1465:1465) (1549:1549:1549)) + (PORT datad (1084:1084:1084) (1110:1110:1110)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13110,31 +7586,539 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) (DELAY (ABSOLUTE - (PORT dataa (1475:1475:1475) (1530:1530:1530)) - (PORT datab (1552:1552:1552) (1583:1583:1583)) - (PORT datac (1503:1503:1503) (1583:1583:1583)) - (PORT datad (1969:1969:1969) (2022:2022:2022)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (639:639:639) (659:659:659)) + (PORT datab (849:849:849) (897:897:897)) + (PORT datac (1652:1652:1652) (1699:1699:1699)) + (PORT datad (1506:1506:1506) (1550:1550:1550)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1895:1895:1895) (1956:1956:1956)) + (PORT datab (1654:1654:1654) (1684:1684:1684)) + (PORT datac (711:711:711) (755:755:755)) + (PORT datad (621:621:621) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1560:1560:1560) (1639:1639:1639)) + (PORT datac (1318:1318:1318) (1431:1431:1431)) + (PORT datad (1418:1418:1418) (1468:1468:1468)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (887:887:887)) + (PORT datab (969:969:969) (1005:1005:1005)) + (PORT datac (1887:1887:1887) (1916:1916:1916)) + (PORT datad (1176:1176:1176) (1231:1231:1231)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (841:841:841)) + (PORT datab (862:862:862) (884:884:884)) + (PORT datac (586:586:586) (605:605:605)) + (PORT datad (828:828:828) (843:843:843)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (205:205:205) (248:248:248)) + (PORT datac (823:823:823) (866:866:866)) + (PORT datad (1432:1432:1432) (1491:1491:1491)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1919:1919:1919) (1955:1955:1955)) + (PORT datab (1212:1212:1212) (1268:1268:1268)) + (PORT datac (876:876:876) (901:901:901)) + (PORT datad (834:834:834) (863:863:863)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (638:638:638) (688:688:688)) + (PORT datac (1003:1003:1003) (1032:1032:1032)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1111:1111:1111)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (730:730:730) (820:820:820)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (1092:1092:1092) (1112:1112:1112)) + (PORT datad (1054:1054:1054) (1061:1061:1061)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (2618:2618:2618) (2706:2706:2706)) + (PORT datab (692:692:692) (737:737:737)) + (PORT datac (1476:1476:1476) (1528:1528:1528)) + (PORT datad (1320:1320:1320) (1396:1396:1396)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2143:2143:2143) (2167:2167:2167)) + (PORT datab (677:677:677) (755:755:755)) + (PORT datac (1109:1109:1109) (1145:1145:1145)) + (PORT datad (1342:1342:1342) (1364:1364:1364)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1204:1204:1204)) + (PORT datab (917:917:917) (942:942:942)) + (PORT datac (1176:1176:1176) (1217:1217:1217)) + (PORT datad (2375:2375:2375) (2378:2378:2378)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1015:1015:1015)) + (PORT datab (1894:1894:1894) (2026:2026:2026)) + (PORT datac (910:910:910) (967:967:967)) + (PORT datad (716:716:716) (799:799:799)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1601:1601:1601) (1742:1742:1742)) + (PORT datab (1577:1577:1577) (1679:1679:1679)) + (PORT datac (1072:1072:1072) (1099:1099:1099)) + (PORT datad (630:630:630) (652:652:652)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (456:456:456)) + (PORT datab (1460:1460:1460) (1546:1546:1546)) + (PORT datac (656:656:656) (690:690:690)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (693:693:693)) + (PORT datab (942:942:942) (965:965:965)) + (PORT datac (551:551:551) (557:557:557)) + (PORT datad (614:614:614) (628:628:628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (898:898:898)) + (PORT datab (1370:1370:1370) (1420:1420:1420)) + (PORT datac (179:179:179) (218:218:218)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2059:2059:2059) (2175:2175:2175)) + (PORT datab (1544:1544:1544) (1669:1669:1669)) + (PORT datac (1139:1139:1139) (1215:1215:1215)) + (PORT datad (1570:1570:1570) (1584:1584:1584)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1122:1122:1122)) + (PORT datab (1498:1498:1498) (1562:1562:1562)) + (PORT datac (849:849:849) (866:866:866)) + (PORT datad (1134:1134:1134) (1147:1147:1147)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1403:1403:1403)) + (PORT datab (2424:2424:2424) (2550:2550:2550)) + (PORT datac (1153:1153:1153) (1213:1213:1213)) + (PORT datad (195:195:195) (231:231:231)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (721:721:721)) + (PORT datac (637:637:637) (662:662:662)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (960:960:960)) + (PORT datab (1848:1848:1848) (1918:1918:1918)) + (PORT datac (1513:1513:1513) (1556:1556:1556)) + (PORT datad (1675:1675:1675) (1725:1725:1725)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT datab (1140:1140:1140) (1160:1160:1160)) + (PORT datac (502:502:502) (515:515:515)) + (PORT datad (1092:1092:1092) (1122:1122:1122)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) (DELAY (ABSOLUTE - (PORT dataa (944:944:944) (982:982:982)) - (PORT datab (685:685:685) (707:707:707)) - (PORT datac (623:623:623) (648:648:648)) - (PORT datad (195:195:195) (220:220:220)) + (PORT dataa (869:869:869) (881:881:881)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (182:182:182) (221:221:221)) + (PORT datad (899:899:899) (936:936:936)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1006:1006:1006)) + (PORT datab (1759:1759:1759) (1865:1865:1865)) + (PORT datac (946:946:946) (1010:1010:1010)) + (PORT datad (1636:1636:1636) (1698:1698:1698)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1395:1395:1395)) + (PORT datab (1759:1759:1759) (1866:1866:1866)) + (PORT datac (1523:1523:1523) (1638:1638:1638)) + (PORT datad (1222:1222:1222) (1286:1286:1286)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1375:1375:1375)) + (PORT datab (737:737:737) (835:835:835)) + (PORT datac (976:976:976) (1074:1074:1074)) + (PORT datad (994:994:994) (1020:1020:1020)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (310:310:310)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datad (1076:1076:1076) (1094:1094:1094)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1601:1601:1601) (1746:1746:1746)) + (PORT datab (1582:1582:1582) (1698:1698:1698)) + (PORT datac (609:609:609) (656:656:656)) + (PORT datad (613:613:613) (666:666:666)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1005:1005:1005)) + (PORT datab (1897:1897:1897) (2027:2027:2027)) + (PORT datac (907:907:907) (963:963:963)) + (PORT datad (718:718:718) (799:799:799)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1535:1535:1535) (1581:1581:1581)) + (PORT datab (919:919:919) (965:965:965)) + (PORT datac (919:919:919) (951:951:951)) + (PORT datad (1808:1808:1808) (1894:1894:1894)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1184:1184:1184)) + (PORT datab (1846:1846:1846) (1931:1931:1931)) + (PORT datac (1190:1190:1190) (1239:1239:1239)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (707:707:707)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (835:835:835) (876:876:876)) + (PORT datad (531:531:531) (537:537:537)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1195:1195:1195)) + (PORT datab (1379:1379:1379) (1425:1425:1425)) + (PORT datac (1518:1518:1518) (1583:1583:1583)) + (PORT datad (1075:1075:1075) (1093:1093:1093)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13145,10 +8129,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (256:256:256)) - (PORT datab (648:648:648) (674:674:674)) - (PORT datac (902:902:902) (952:952:952)) - (PORT datad (923:923:923) (972:972:972)) + (PORT dataa (1337:1337:1337) (1334:1334:1334)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (617:617:617) (644:644:644)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -13161,179 +8145,9 @@ (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) (DELAY (ABSOLUTE - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (1346:1346:1346) (1374:1374:1374)) - (PORT datad (825:825:825) (853:853:853)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (907:907:907)) - (PORT datab (1078:1078:1078) (1132:1132:1132)) - (PORT datac (515:515:515) (534:534:534)) - (PORT datad (522:522:522) (533:533:533)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1320:1320:1320) (1381:1381:1381)) - (PORT datab (2246:2246:2246) (2335:2335:2335)) - (PORT datac (1395:1395:1395) (1531:1531:1531)) - (PORT datad (908:908:908) (933:933:933)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1222:1222:1222)) - (PORT datab (1197:1197:1197) (1273:1273:1273)) - (PORT datac (877:877:877) (942:942:942)) - (PORT datad (1209:1209:1209) (1259:1259:1259)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (986:986:986)) - (PORT datab (935:935:935) (974:974:974)) - (PORT datac (1208:1208:1208) (1267:1267:1267)) - (PORT datad (580:580:580) (609:609:609)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1367:1367:1367)) - (PORT datab (1760:1760:1760) (1823:1823:1823)) - (PORT datac (780:780:780) (832:832:832)) - (PORT datad (2119:2119:2119) (2113:2113:2113)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1164:1164:1164)) - (PORT datab (1248:1248:1248) (1297:1297:1297)) - (PORT datad (900:900:900) (967:967:967)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1008:1008:1008)) - (PORT datab (667:667:667) (689:689:689)) - (PORT datac (844:844:844) (882:882:882)) - (PORT datad (865:865:865) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (1146:1146:1146) (1171:1171:1171)) - (PORT datac (202:202:202) (240:240:240)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (705:705:705)) - (PORT datab (344:344:344) (376:376:376)) - (PORT datac (1158:1158:1158) (1183:1183:1183)) - (PORT datad (942:942:942) (987:987:987)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1155:1155:1155)) - (PORT datab (660:660:660) (713:713:713)) - (PORT datac (904:904:904) (922:922:922)) - (PORT datad (820:820:820) (840:840:840)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (240:240:240) (286:286:286)) - (PORT datac (211:211:211) (254:254:254)) + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (384:384:384) (413:413:413)) + (PORT datac (878:878:878) (904:904:904)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -13342,127 +8156,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) (DELAY (ABSOLUTE - (PORT dataa (1301:1301:1301) (1320:1320:1320)) - (PORT datab (2020:2020:2020) (2143:2143:2143)) - (PORT datac (1955:1955:1955) (2058:2058:2058)) - (PORT datad (1295:1295:1295) (1376:1376:1376)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1262:1262:1262)) - (PORT datab (1197:1197:1197) (1269:1269:1269)) - (PORT datac (1021:1021:1021) (1050:1050:1050)) - (PORT datad (315:315:315) (333:333:333)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2144:2144:2144) (2265:2265:2265)) - (PORT datab (1690:1690:1690) (1867:1867:1867)) - (PORT datac (604:604:604) (619:619:619)) - (PORT datad (2025:2025:2025) (2071:2071:2071)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (2076:2076:2076) (2173:2173:2173)) - (PORT datab (1169:1169:1169) (1260:1260:1260)) - (PORT datac (1442:1442:1442) (1488:1488:1488)) - (PORT datad (1368:1368:1368) (1396:1396:1396)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (942:942:942)) - (PORT datab (677:677:677) (721:721:721)) - (PORT datac (1761:1761:1761) (1841:1841:1841)) - (PORT datad (1762:1762:1762) (1819:1819:1819)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1482:1482:1482)) - (PORT datab (910:910:910) (937:937:937)) - (PORT datac (1440:1440:1440) (1519:1519:1519)) - (PORT datad (838:838:838) (870:870:870)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (961:961:961)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (619:619:619) (672:672:672)) - (PORT datad (598:598:598) (648:648:648)) + (PORT dataa (841:841:841) (934:934:934)) + (PORT datab (885:885:885) (903:903:903)) + (PORT datac (1055:1055:1055) (1102:1102:1102)) + (PORT datad (1086:1086:1086) (1124:1124:1124)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (911:911:911)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (812:812:812) (847:847:847)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13470,563 +8172,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (693:693:693)) - (PORT datab (661:661:661) (693:693:693)) - (PORT datac (634:634:634) (677:677:677)) - (PORT datad (348:348:348) (370:370:370)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1319:1319:1319)) - (PORT datab (1236:1236:1236) (1274:1274:1274)) - (PORT datac (625:625:625) (679:679:679)) - (PORT datad (1191:1191:1191) (1247:1247:1247)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (950:950:950) (979:979:979)) - (PORT datad (624:624:624) (649:649:649)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2353:2353:2353) (2461:2461:2461)) - (PORT datab (976:976:976) (1005:1005:1005)) - (PORT datac (1088:1088:1088) (1104:1104:1104)) - (PORT datad (1772:1772:1772) (1890:1890:1890)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (907:907:907) (918:918:918)) - (PORT datac (1188:1188:1188) (1230:1230:1230)) - (PORT datad (1430:1430:1430) (1500:1500:1500)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datac (1693:1693:1693) (1727:1727:1727)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (672:672:672)) - (PORT datab (578:578:578) (605:605:605)) - (PORT datac (1476:1476:1476) (1572:1572:1572)) - (PORT datad (1639:1639:1639) (1701:1701:1701)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1315:1315:1315)) - (PORT datab (1165:1165:1165) (1196:1196:1196)) - (PORT datac (912:912:912) (969:969:969)) - (PORT datad (314:314:314) (333:333:333)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1047:1047:1047) (1053:1053:1053)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1758:1758:1758) (1900:1900:1900)) - (PORT datab (902:902:902) (950:950:950)) - (PORT datac (1212:1212:1212) (1261:1261:1261)) - (PORT datad (2454:2454:2454) (2652:2652:2652)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (664:664:664) (686:686:686)) - (PORT datac (185:185:185) (223:223:223)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1193:1193:1193) (1290:1290:1290)) - (PORT datab (1597:1597:1597) (1747:1747:1747)) - (PORT datac (1512:1512:1512) (1646:1646:1646)) - (PORT datad (1772:1772:1772) (1860:1860:1860)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (2076:2076:2076) (2171:2171:2171)) - (PORT datab (1273:1273:1273) (1341:1341:1341)) - (PORT datac (1497:1497:1497) (1578:1578:1578)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (420:420:420)) - (PORT datab (1273:1273:1273) (1342:1342:1342)) - (PORT datac (1152:1152:1152) (1193:1193:1193)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (601:601:601) (645:645:645)) - (PORT datac (1369:1369:1369) (1405:1405:1405)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (725:725:725)) - (PORT datab (952:952:952) (1009:1009:1009)) - (PORT datac (1500:1500:1500) (1582:1582:1582)) - (PORT datad (1167:1167:1167) (1248:1248:1248)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (1458:1458:1458) (1477:1477:1477)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1377:1377:1377)) - (PORT datab (1178:1178:1178) (1247:1247:1247)) - (PORT datac (1503:1503:1503) (1562:1562:1562)) - (PORT datad (642:642:642) (693:693:693)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (1217:1217:1217) (1266:1266:1266)) - (PORT datac (1500:1500:1500) (1564:1564:1564)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1389:1389:1389) (1465:1465:1465)) - (PORT datab (1685:1685:1685) (1852:1852:1852)) - (PORT datac (982:982:982) (980:980:980)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1140:1140:1140) (1183:1183:1183)) - (PORT datab (662:662:662) (713:713:713)) - (PORT datac (627:627:627) (681:681:681)) - (PORT datad (640:640:640) (676:676:676)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1655:1655:1655) (1726:1726:1726)) - (PORT datab (1375:1375:1375) (1391:1391:1391)) - (PORT datac (1118:1118:1118) (1174:1174:1174)) - (PORT datad (624:624:624) (643:643:643)) + (PORT dataa (925:925:925) (961:961:961)) + (PORT datab (1417:1417:1417) (1473:1473:1473)) + (PORT datac (1652:1652:1652) (1707:1707:1707)) + (PORT datad (1487:1487:1487) (1555:1555:1555)) (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (1183:1183:1183) (1210:1210:1210)) - (PORT datab (1380:1380:1380) (1398:1398:1398)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (257:257:257)) - (PORT datab (663:663:663) (690:690:690)) - (PORT datac (188:188:188) (229:229:229)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (384:384:384)) - (PORT datab (811:811:811) (819:819:819)) - (PORT datac (1421:1421:1421) (1484:1484:1484)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (1256:1256:1256) (1322:1322:1322)) + (PORT datab (951:951:951) (987:987:987)) + (PORT datac (1107:1107:1107) (1146:1146:1146)) + (PORT datad (1934:1934:1934) (2036:2036:2036)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (1645:1645:1645) (1680:1680:1680)) - (PORT datab (1246:1246:1246) (1316:1316:1316)) - (PORT datac (1499:1499:1499) (1579:1579:1579)) - (PORT datad (2049:2049:2049) (2131:2131:2131)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (1066:1066:1066) (1146:1146:1146)) + (PORT datab (919:919:919) (992:992:992)) + (PORT datac (1106:1106:1106) (1143:1143:1143)) + (PORT datad (2265:2265:2265) (2302:2302:2302)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (285:285:285)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (552:552:552) (565:565:565)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1799:1799:1799) (1901:1901:1901)) - (PORT datab (1594:1594:1594) (1745:1745:1745)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1620:1620:1620) (1635:1635:1635)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1533:1533:1533) (1601:1601:1601)) - (PORT datab (1750:1750:1750) (1829:1829:1829)) - (PORT datac (1522:1522:1522) (1600:1600:1600)) - (PORT datad (337:337:337) (356:356:356)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (761:761:761)) - (PORT datab (915:915:915) (968:968:968)) - (PORT datac (1718:1718:1718) (1796:1796:1796)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1531:1531:1531) (1599:1599:1599)) - (PORT datab (1097:1097:1097) (1130:1130:1130)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1896:1896:1896) (1969:1969:1969)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (761:761:761)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1068:1068:1068) (1100:1100:1100)) - (PORT datad (1691:1691:1691) (1730:1730:1730)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1483:1483:1483)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (631:631:631) (655:655:655)) - (PORT datad (1901:1901:1901) (1974:1974:1974)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (690:690:690)) - (PORT datab (610:610:610) (635:635:635)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1482:1482:1482)) - (PORT datab (979:979:979) (1023:1023:1023)) - (PORT datac (1196:1196:1196) (1241:1241:1241)) - (PORT datad (1188:1188:1188) (1214:1214:1214)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1204:1204:1204)) - (PORT datab (1148:1148:1148) (1184:1184:1184)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) (DELAY (ABSOLUTE - (PORT dataa (1749:1749:1749) (1821:1821:1821)) - (PORT datab (1396:1396:1396) (1445:1445:1445)) - (PORT datac (1206:1206:1206) (1248:1248:1248)) - (PORT datad (1501:1501:1501) (1578:1578:1578)) + (PORT dataa (938:938:938) (968:968:968)) + (PORT datab (907:907:907) (922:922:922)) + (PORT datac (1186:1186:1186) (1234:1234:1234)) + (PORT datad (1409:1409:1409) (1429:1429:1429)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14039,12 +8255,60 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) (DELAY (ABSOLUTE - (PORT dataa (1747:1747:1747) (1821:1821:1821)) - (PORT datab (1398:1398:1398) (1449:1449:1449)) - (PORT datac (1474:1474:1474) (1513:1513:1513)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1532:1532:1532) (1578:1578:1578)) + (PORT datab (1445:1445:1445) (1467:1467:1467)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (911:911:911) (925:925:925)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1675:1675:1675)) + (PORT datab (1290:1290:1290) (1292:1292:1292)) + (PORT datac (1749:1749:1749) (1883:1883:1883)) + (PORT datad (637:637:637) (688:688:688)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (1621:1621:1621) (1754:1754:1754)) + (PORT datab (1721:1721:1721) (1762:1762:1762)) + (PORT datac (1102:1102:1102) (1143:1143:1143)) + (PORT datad (1733:1733:1733) (1842:1842:1842)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1172:1172:1172)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1116:1116:1116) (1172:1172:1172)) + (PORT datad (798:798:798) (804:804:804)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14055,10 +8319,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) (DELAY (ABSOLUTE - (PORT dataa (1260:1260:1260) (1306:1306:1306)) - (PORT datab (1543:1543:1543) (1626:1626:1626)) - (PORT datac (912:912:912) (982:982:982)) - (PORT datad (959:959:959) (1003:1003:1003)) + (PORT dataa (1151:1151:1151) (1192:1192:1192)) + (PORT datab (681:681:681) (718:718:718)) + (PORT datac (1131:1131:1131) (1165:1165:1165)) + (PORT datad (1105:1105:1105) (1161:1161:1161)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14071,44 +8335,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1240:1240:1240)) - (PORT datab (994:994:994) (1040:1040:1040)) - (PORT datac (909:909:909) (977:977:977)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (984:984:984)) - (PORT datab (1911:1911:1911) (2074:2074:2074)) - (PORT datac (1899:1899:1899) (2060:2060:2060)) - (PORT datad (1058:1058:1058) (1086:1086:1086)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1286:1286:1286)) - (PORT datab (1215:1215:1215) (1233:1233:1233)) - (PORT datac (833:833:833) (881:881:881)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1132:1132:1132) (1205:1205:1205)) + (PORT datab (1094:1094:1094) (1119:1119:1119)) + (PORT datac (1130:1130:1130) (1168:1168:1168)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14119,12 +8351,76 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (624:624:624) (649:649:649)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (367:367:367) (408:408:408)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (769:769:769) (783:783:783)) + (PORT datad (601:601:601) (627:627:627)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1531:1531:1531)) + (PORT datab (921:921:921) (951:951:951)) + (PORT datac (1695:1695:1695) (1732:1732:1732)) + (PORT datad (964:964:964) (1058:1058:1058)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (954:954:954)) + (PORT datab (1592:1592:1592) (1691:1691:1691)) + (PORT datac (619:619:619) (686:686:686)) + (PORT datad (887:887:887) (907:907:907)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (724:724:724)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (858:858:858) (880:880:880)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (308:308:308)) + (PORT datab (1679:1679:1679) (1718:1718:1718)) + (PORT datac (1916:1916:1916) (2000:2000:2000)) + (PORT datad (342:342:342) (353:353:353)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14135,10 +8431,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (926:926:926)) - (PORT datab (875:875:875) (918:918:918)) - (PORT datac (635:635:635) (664:664:664)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (1101:1101:1101) (1123:1123:1123)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (985:985:985) (987:987:987)) + (PORT datad (195:195:195) (220:220:220)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14148,15 +8444,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~50) (DELAY (ABSOLUTE - (PORT dataa (2896:2896:2896) (2954:2954:2954)) - (PORT datab (1052:1052:1052) (1116:1116:1116)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (2591:2591:2591) (2649:2649:2649)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1045:1045:1045) (1183:1183:1183)) + (PORT datab (1473:1473:1473) (1564:1564:1564)) + (PORT datac (560:560:560) (571:571:571)) + (PORT datad (893:893:893) (899:899:899)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14164,15 +8460,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1270:1270:1270)) - (PORT datab (1101:1101:1101) (1135:1135:1135)) - (PORT datac (1363:1363:1363) (1380:1380:1380)) - (PORT datad (1191:1191:1191) (1245:1245:1245)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1260:1260:1260) (1356:1356:1356)) + (PORT datab (902:902:902) (942:942:942)) + (PORT datac (1171:1171:1171) (1226:1226:1226)) + (PORT datad (1161:1161:1161) (1191:1191:1191)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14180,15 +8476,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) (DELAY (ABSOLUTE - (PORT dataa (1384:1384:1384) (1464:1464:1464)) - (PORT datab (628:628:628) (673:673:673)) - (PORT datac (611:611:611) (637:637:637)) - (PORT datad (697:697:697) (744:744:744)) + (PORT dataa (1361:1361:1361) (1449:1449:1449)) + (PORT datab (642:642:642) (696:696:696)) + (PORT datac (1261:1261:1261) (1352:1352:1352)) + (PORT datad (628:628:628) (656:656:656)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1587:1587:1587)) + (PORT datab (1233:1233:1233) (1294:1294:1294)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1129:1129:1129) (1176:1176:1176)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (806:806:806) (814:814:814)) + (PORT datad (335:335:335) (354:354:354)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1461:1461:1461)) + (PORT datab (916:916:916) (988:988:988)) + (PORT datac (1652:1652:1652) (1712:1712:1712)) + (PORT datad (1488:1488:1488) (1556:1556:1556)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (944:944:944)) + (PORT datab (1190:1190:1190) (1265:1265:1265)) + (PORT datac (932:932:932) (950:950:950)) + (PORT datad (913:913:913) (945:945:945)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14196,13 +8552,535 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (853:853:853) (883:883:883)) - (PORT datab (877:877:877) (946:946:946)) - (PORT datac (2034:2034:2034) (2072:2072:2072)) - (PORT datad (821:821:821) (867:867:867)) + (PORT dataa (611:611:611) (652:652:652)) + (PORT datab (907:907:907) (925:925:925)) + (PORT datac (916:916:916) (949:949:949)) + (PORT datad (1807:1807:1807) (1896:1896:1896)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (857:857:857) (901:901:901)) + (PORT datac (631:631:631) (669:669:669)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (830:830:830)) + (PORT datab (1496:1496:1496) (1556:1556:1556)) + (PORT datac (1290:1290:1290) (1403:1403:1403)) + (PORT datad (925:925:925) (942:942:942)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (832:832:832)) + (PORT datab (922:922:922) (966:966:966)) + (PORT datac (808:808:808) (819:819:819)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (965:965:965)) + (PORT datab (1443:1443:1443) (1506:1506:1506)) + (PORT datac (1247:1247:1247) (1308:1308:1308)) + (PORT datad (1042:1042:1042) (1057:1057:1057)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1586:1586:1586) (1605:1605:1605)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~51) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (402:402:402)) + (PORT datab (2163:2163:2163) (2293:2293:2293)) + (PORT datac (1532:1532:1532) (1659:1659:1659)) + (PORT datad (1753:1753:1753) (1887:1887:1887)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1191:1191:1191) (1272:1272:1272)) + (PORT datac (1113:1113:1113) (1173:1173:1173)) + (PORT datad (196:196:196) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1561:1561:1561) (1690:1690:1690)) + (PORT datac (351:351:351) (378:378:378)) + (PORT datad (1790:1790:1790) (1874:1874:1874)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1675:1675:1675)) + (PORT datab (1678:1678:1678) (1721:1721:1721)) + (PORT datac (622:622:622) (663:663:663)) + (PORT datad (1568:1568:1568) (1662:1662:1662)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (590:590:590) (599:599:599)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1865:1865:1865) (1966:1966:1966)) + (PORT datab (882:882:882) (905:905:905)) + (PORT datac (2364:2364:2364) (2512:2512:2512)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1623:1623:1623)) + (PORT datab (1197:1197:1197) (1221:1221:1221)) + (PORT datac (830:830:830) (850:850:850)) + (PORT datad (314:314:314) (333:333:333)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (692:692:692) (719:719:719)) + (PORT datac (576:576:576) (585:585:585)) + (PORT datad (890:890:890) (930:930:930)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1087:1087:1087)) + (PORT datab (702:702:702) (742:742:742)) + (PORT datac (602:602:602) (664:664:664)) + (PORT datad (1141:1141:1141) (1142:1142:1142)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (733:733:733)) + (PORT datab (1390:1390:1390) (1430:1430:1430)) + (PORT datac (1293:1293:1293) (1288:1288:1288)) + (PORT datad (1156:1156:1156) (1232:1232:1232)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1193:1193:1193)) + (PORT datab (1112:1112:1112) (1135:1135:1135)) + (PORT datac (1515:1515:1515) (1580:1580:1580)) + (PORT datad (1144:1144:1144) (1172:1172:1172)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1379:1379:1379) (1422:1422:1422)) + (PORT datac (633:633:633) (695:695:695)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1286:1286:1286)) + (PORT datab (1246:1246:1246) (1298:1298:1298)) + (PORT datac (817:817:817) (830:830:830)) + (PORT datad (1062:1062:1062) (1106:1106:1106)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (910:910:910) (932:932:932)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1441:1441:1441)) + (PORT datab (1524:1524:1524) (1615:1615:1615)) + (PORT datac (846:846:846) (871:871:871)) + (PORT datad (1023:1023:1023) (1080:1080:1080)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1127:1127:1127)) + (PORT datab (220:220:220) (257:257:257)) + (PORT datac (1412:1412:1412) (1455:1455:1455)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (969:969:969)) + (PORT datab (680:680:680) (699:699:699)) + (PORT datac (589:589:589) (604:604:604)) + (PORT datad (643:643:643) (656:656:656)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (592:592:592) (599:599:599)) + (PORT datad (185:185:185) (217:217:217)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (585:585:585)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (768:768:768) (802:802:802)) + (PORT datad (847:847:847) (869:869:869)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1132:1132:1132)) + (PORT datab (748:748:748) (801:801:801)) + (PORT datac (1727:1727:1727) (1785:1785:1785)) + (PORT datad (1374:1374:1374) (1390:1390:1390)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (2073:2073:2073) (2186:2186:2186)) + (PORT datab (1400:1400:1400) (1425:1425:1425)) + (PORT datac (1772:1772:1772) (1899:1899:1899)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1132:1132:1132)) + (PORT datab (962:962:962) (975:975:975)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (712:712:712) (762:762:762)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (663:663:663)) + (PORT datab (1519:1519:1519) (1611:1611:1611)) + (PORT datac (934:934:934) (944:944:944)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1868:1868:1868)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (938:938:938) (1003:1003:1003)) + (PORT datad (1024:1024:1024) (1086:1086:1086)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1519:1519:1519) (1613:1613:1613)) + (PORT datac (1729:1729:1729) (1823:1823:1823)) + (PORT datad (853:853:853) (863:863:863)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (634:634:634)) + (PORT datab (1456:1456:1456) (1500:1500:1500)) + (PORT datac (941:941:941) (1004:1004:1004)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (908:908:908) (948:948:948)) + (PORT datad (583:583:583) (620:620:620)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (914:914:914)) + (PORT datab (1176:1176:1176) (1233:1233:1233)) + (PORT datac (1349:1349:1349) (1376:1376:1376)) + (PORT datad (1340:1340:1340) (1388:1388:1388)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14212,42 +9090,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (2352:2352:2352) (2460:2460:2460)) - (PORT datab (979:979:979) (1005:1005:1005)) - (PORT datac (1863:1863:1863) (1892:1892:1892)) - (PORT datad (1775:1775:1775) (1890:1890:1890)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1179:1179:1179) (1246:1246:1246)) - (PORT datad (1693:1693:1693) (1817:1817:1817)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (2042:2042:2042) (2132:2132:2132)) - (PORT datab (661:661:661) (679:679:679)) - (PORT datac (861:861:861) (893:893:893)) - (PORT datad (666:666:666) (723:723:723)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (945:945:945) (1008:1008:1008)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (923:923:923) (969:969:969)) + (PORT datad (224:224:224) (265:265:265)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14256,94 +9106,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~17) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (859:859:859) (874:874:874)) - (PORT datad (340:340:340) (363:363:363)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (866:866:866) (892:892:892)) + (PORT datab (1557:1557:1557) (1673:1673:1673)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1279:1279:1279) (1383:1383:1383)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (1882:1882:1882) (2069:2069:2069)) - (PORT datab (1503:1503:1503) (1598:1598:1598)) - (PORT datac (1200:1200:1200) (1277:1277:1277)) - (PORT datad (613:613:613) (652:652:652)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (591:591:591) (609:609:609)) - (PORT datad (832:832:832) (884:884:884)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1622:1622:1622) (1656:1656:1656)) - (PORT datab (1011:1011:1011) (1122:1122:1122)) - (PORT datac (2246:2246:2246) (2401:2401:2401)) - (PORT datad (640:640:640) (657:657:657)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (399:399:399)) - (PORT datab (886:886:886) (926:926:926)) - (PORT datac (2213:2213:2213) (2293:2293:2293)) - (PORT datad (1158:1158:1158) (1220:1220:1220)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (649:649:649)) - (PORT datab (610:610:610) (643:643:643)) - (PORT datac (1089:1089:1089) (1103:1103:1103)) - (PORT datad (1426:1426:1426) (1497:1497:1497)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (2047:2047:2047) (2141:2141:2141)) + (PORT datab (705:705:705) (759:759:759)) + (PORT datac (1941:1941:1941) (1985:1985:1985)) + (PORT datad (1314:1314:1314) (1347:1347:1347)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14352,16 +9138,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (970:970:970) (1047:1047:1047)) - (PORT datab (1328:1328:1328) (1357:1357:1357)) - (PORT datac (1395:1395:1395) (1452:1452:1452)) - (PORT datad (180:180:180) (211:211:211)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (254:254:254) (313:313:313)) + (PORT datab (625:625:625) (654:654:654)) + (PORT datac (1912:1912:1912) (1997:1997:1997)) + (PORT datad (1653:1653:1653) (1681:1681:1681)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1726:1726:1726)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (882:882:882) (914:914:914)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (674:674:674)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (189:189:189) (233:233:233)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1106:1106:1106)) + (PORT datab (1192:1192:1192) (1252:1252:1252)) + (PORT datac (893:893:893) (936:936:936)) + (PORT datad (1452:1452:1452) (1569:1569:1569)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14371,1242 +9205,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) (DELAY (ABSOLUTE - (PORT dataa (1158:1158:1158) (1195:1195:1195)) - (PORT datab (908:908:908) (926:926:926)) - (PORT datac (616:616:616) (647:647:647)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1546:1546:1546)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (953:953:953)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (606:606:606) (625:625:625)) - (PORT datad (1433:1433:1433) (1446:1446:1446)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (955:955:955)) - (PORT datab (968:968:968) (1012:1012:1012)) - (PORT datac (766:766:766) (778:778:778)) - (PORT datad (180:180:180) (210:210:210)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (661:661:661)) - (PORT datab (1887:1887:1887) (1914:1914:1914)) - (PORT datac (951:951:951) (996:996:996)) - (PORT datad (1256:1256:1256) (1314:1314:1314)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (574:574:574) (617:617:617)) - (PORT datad (1077:1077:1077) (1104:1104:1104)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (396:396:396)) - (PORT datab (632:632:632) (663:663:663)) - (PORT datac (612:612:612) (624:624:624)) - (PORT datad (624:624:624) (639:639:639)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (950:950:950)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (1118:1118:1118) (1174:1174:1174)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (904:904:904)) - (PORT datab (2215:2215:2215) (2381:2381:2381)) - (PORT datac (1232:1232:1232) (1373:1373:1373)) - (PORT datad (2798:2798:2798) (2994:2994:2994)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (638:638:638)) - (PORT datab (687:687:687) (717:717:717)) - (PORT datac (934:934:934) (966:966:966)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (631:631:631)) - (PORT datac (895:895:895) (905:905:905)) - (PORT datad (841:841:841) (853:853:853)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1988:1988:1988) (2068:2068:2068)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datad (869:869:869) (931:931:931)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1589:1589:1589) (1566:1566:1566)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1475:1475:1475)) - (PORT datab (1193:1193:1193) (1241:1241:1241)) - (PORT datac (846:846:846) (891:891:891)) - (PORT datad (1379:1379:1379) (1380:1380:1380)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT dataa (1682:1682:1682) (1803:1803:1803)) - (PORT datac (632:632:632) (678:678:678)) - (PORT datad (1446:1446:1446) (1513:1513:1513)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1183:1183:1183) (1262:1262:1262)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1554:1554:1554)) - (PORT datab (656:656:656) (705:705:705)) - (PORT datad (1630:1630:1630) (1739:1739:1739)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT dataa (1285:1285:1285) (1362:1362:1362)) - (PORT datab (897:897:897) (934:934:934)) - (PORT datac (1431:1431:1431) (1496:1496:1496)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1464:1464:1464) (1531:1531:1531)) - (PORT datac (876:876:876) (924:924:924)) - (PORT datad (1249:1249:1249) (1317:1317:1317)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1014:1014:1014) (1056:1056:1056)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1381:1381:1381)) - (PORT datab (894:894:894) (929:929:929)) - (PORT datac (1433:1433:1433) (1499:1499:1499)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1016:1016:1016) (1059:1059:1059)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1468:1468:1468) (1530:1530:1530)) - (PORT datac (879:879:879) (925:925:925)) - (PORT datad (1241:1241:1241) (1311:1311:1311)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (977:977:977)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (893:893:893) (937:937:937)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (842:842:842)) - (PORT datab (249:249:249) (332:332:332)) - (PORT datac (787:787:787) (792:792:792)) - (PORT datad (199:199:199) (237:237:237)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1462:1462:1462) (1531:1531:1531)) - (PORT datac (860:860:860) (902:902:902)) - (PORT datad (1246:1246:1246) (1318:1318:1318)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (841:841:841)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datac (787:787:787) (791:791:791)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1466:1466:1466) (1528:1528:1528)) - (PORT datac (844:844:844) (888:888:888)) - (PORT datad (1241:1241:1241) (1313:1313:1313)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1468:1468:1468) (1532:1532:1532)) - (PORT datac (861:861:861) (900:900:900)) - (PORT datad (1254:1254:1254) (1327:1327:1327)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1423:1423:1423) (1482:1482:1482)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1465:1465:1465) (1532:1532:1532)) - (PORT datac (841:841:841) (888:888:888)) - (PORT datad (1245:1245:1245) (1318:1318:1318)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1421:1421:1421) (1478:1478:1478)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (1057:1057:1057)) - (PORT datab (966:966:966) (1013:1013:1013)) - (PORT datad (357:357:357) (414:414:414)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (854:854:854) (911:911:911)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1527:1527:1527)) - (PORT datab (1198:1198:1198) (1246:1246:1246)) - (PORT datac (1748:1748:1748) (1867:1867:1867)) - (PORT datad (1449:1449:1449) (1522:1522:1522)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (1615:1615:1615) (1723:1723:1723)) - (PORT datac (1085:1085:1085) (1141:1141:1141)) - (PORT datad (346:346:346) (373:373:373)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (1612:1612:1612) (1721:1721:1721)) - (PORT datac (1083:1083:1083) (1140:1140:1140)) - (PORT datad (343:343:343) (371:371:371)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datab (1611:1611:1611) (1718:1718:1718)) - (PORT datad (1731:1731:1731) (1794:1794:1794)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1529:1529:1529)) - (PORT datab (1784:1784:1784) (1902:1902:1902)) - (PORT datac (337:337:337) (362:362:362)) - (PORT datad (1160:1160:1160) (1205:1205:1205)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1411:1411:1411) (1470:1470:1470)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datab (1610:1610:1610) (1716:1716:1716)) - (PORT datac (1084:1084:1084) (1136:1136:1136)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1497:1497:1497) (1513:1513:1513)) - (PORT datab (376:376:376) (408:408:408)) - (PORT datac (1753:1753:1753) (1874:1874:1874)) - (PORT datad (1153:1153:1153) (1198:1198:1198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (552:552:552)) - (PORT datab (498:498:498) (554:554:554)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (599:599:599) (636:636:636)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1476:1476:1476)) - (PORT datab (1193:1193:1193) (1241:1241:1241)) - (PORT datac (341:341:341) (367:367:367)) - (PORT datad (1380:1380:1380) (1380:1380:1380)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1514:1514:1514) (1527:1527:1527)) - (PORT datab (371:371:371) (402:402:402)) - (PORT datac (1398:1398:1398) (1441:1441:1441)) - (PORT datad (1158:1158:1158) (1204:1204:1204)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (706:706:706)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2055:2055:2055) (2081:2081:2081)) - (PORT datab (1404:1404:1404) (1511:1511:1511)) - (PORT datac (2090:2090:2090) (2260:2260:2260)) - (PORT datad (875:875:875) (901:901:901)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1073:1073:1073)) - (PORT datab (1268:1268:1268) (1350:1350:1350)) - (PORT datac (1926:1926:1926) (1930:1930:1930)) - (PORT datad (363:363:363) (385:385:385)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datac (588:588:588) (636:636:636)) - (PORT datad (822:822:822) (847:847:847)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (721:721:721)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (860:860:860) (875:875:875)) - (PORT datad (642:642:642) (659:659:659)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (964:964:964) (1041:1041:1041)) - (PORT datac (916:916:916) (968:968:968)) - (PORT datad (1214:1214:1214) (1282:1282:1282)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (950:950:950) (983:983:983)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1034:1034:1034)) - (PORT datac (915:915:915) (966:966:966)) - (PORT datad (1213:1213:1213) (1277:1277:1277)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (959:959:959) (999:999:999)) - (PORT datad (880:880:880) (921:921:921)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1526:1526:1526)) - (PORT datab (1196:1196:1196) (1249:1249:1249)) - (PORT datac (341:341:341) (369:369:369)) - (PORT datad (582:582:582) (643:643:643)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1526:1526:1526)) - (PORT datab (611:611:611) (683:683:683)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (1156:1156:1156) (1205:1205:1205)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1439:1439:1439) (1498:1498:1498)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1506:1506:1506) (1523:1523:1523)) - (PORT datab (609:609:609) (680:680:680)) - (PORT datac (340:340:340) (366:366:366)) - (PORT datad (1150:1150:1150) (1203:1203:1203)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1444:1444:1444) (1503:1503:1503)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1511:1511:1511) (1527:1527:1527)) - (PORT datab (1197:1197:1197) (1246:1246:1246)) - (PORT datac (341:341:341) (368:368:368)) - (PORT datad (582:582:582) (639:639:639)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (705:705:705)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (626:626:626) (663:663:663)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1429:1429:1429) (1476:1476:1476)) - (PORT datab (1197:1197:1197) (1247:1247:1247)) - (PORT datac (850:850:850) (893:893:893)) - (PORT datad (1383:1383:1383) (1381:1381:1381)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1488:1488:1488) (1561:1561:1561)) - (PORT datab (902:902:902) (929:929:929)) - (PORT datad (1637:1637:1637) (1751:1751:1751)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1609:1609:1609) (1656:1656:1656)) - (PORT datac (887:887:887) (932:932:932)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1674:1674:1674) (1748:1748:1748)) - (PORT datab (392:392:392) (418:418:418)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (886:886:886) (902:902:902)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1558:1558:1558)) - (PORT datab (908:908:908) (935:935:935)) - (PORT datad (1629:1629:1629) (1743:1743:1743)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1414:1414:1414) (1474:1474:1474)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1031:1031:1031)) - (PORT datab (1291:1291:1291) (1331:1331:1331)) - (PORT datad (874:874:874) (906:906:906)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (1320:1320:1320) (1335:1335:1335)) - (PORT datac (335:335:335) (358:358:358)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (672:672:672)) - (PORT datab (555:555:555) (576:576:576)) - (PORT datac (825:825:825) (840:840:840)) - (PORT datad (1032:1032:1032) (1101:1101:1101)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (385:385:385)) - (PORT datab (1380:1380:1380) (1398:1398:1398)) - (PORT datac (1123:1123:1123) (1180:1180:1180)) - (PORT datad (622:622:622) (640:640:640)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (732:732:732)) - (PORT datab (891:891:891) (930:930:930)) - (PORT datac (1215:1215:1215) (1263:1263:1263)) - (PORT datad (560:560:560) (577:577:577)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) + (PORT dataa (1211:1211:1211) (1327:1327:1327)) (PORT datab (875:875:875) (893:893:893)) - (PORT datac (344:344:344) (372:372:372)) - (PORT datad (1110:1110:1110) (1122:1122:1122)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (615:615:615) (641:641:641)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (593:593:593)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (962:962:962)) - (PORT datab (1357:1357:1357) (1408:1408:1408)) - (PORT datac (1375:1375:1375) (1378:1378:1378)) - (PORT datad (793:793:793) (845:845:845)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (658:658:658)) - (PORT datab (1361:1361:1361) (1409:1409:1409)) - (PORT datac (412:412:412) (449:449:449)) - (PORT datad (209:209:209) (242:242:242)) + (PORT datac (2173:2173:2173) (2262:2262:2262)) + (PORT datad (1470:1470:1470) (1572:1572:1572)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -15616,16 +9218,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) (DELAY (ABSOLUTE - (PORT dataa (1495:1495:1495) (1563:1563:1563)) - (PORT datab (841:841:841) (869:869:869)) - (PORT datac (809:809:809) (891:891:891)) - (PORT datad (837:837:837) (886:886:886)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (646:646:646) (661:661:661)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1005:1005:1005) (1030:1030:1030)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -15635,13 +9237,13 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (994:994:994)) - (PORT datab (1403:1403:1403) (1460:1460:1460)) - (PORT datac (1085:1085:1085) (1138:1138:1138)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1534:1534:1534) (1584:1584:1584)) + (PORT datab (896:896:896) (955:955:955)) + (PORT datac (1366:1366:1366) (1364:1364:1364)) + (PORT datad (372:372:372) (401:401:401)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -15651,12 +9253,12 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) (DELAY (ABSOLUTE - (PORT dataa (1124:1124:1124) (1165:1165:1165)) - (PORT datab (1867:1867:1867) (1942:1942:1942)) - (PORT datac (842:842:842) (905:905:905)) - (PORT datad (626:626:626) (662:662:662)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1234:1234:1234) (1295:1295:1295)) + (PORT datab (1382:1382:1382) (1435:1435:1435)) + (PORT datac (1798:1798:1798) (1854:1854:1854)) + (PORT datad (371:371:371) (401:401:401)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15667,11 +9269,11 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) (DELAY (ABSOLUTE - (PORT dataa (1190:1190:1190) (1209:1209:1209)) - (PORT datab (1474:1474:1474) (1514:1514:1514)) - (PORT datac (1094:1094:1094) (1102:1102:1102)) - (PORT datad (1208:1208:1208) (1297:1297:1297)) - (IOPATH dataa combout (337:337:337) (338:338:338)) + (PORT dataa (1245:1245:1245) (1308:1308:1308)) + (PORT datab (940:940:940) (1014:1014:1014)) + (PORT datac (1966:1966:1966) (2013:2013:2013)) + (PORT datad (636:636:636) (685:685:685)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -15683,12 +9285,12 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) (DELAY (ABSOLUTE - (PORT dataa (1236:1236:1236) (1289:1289:1289)) - (PORT datab (1163:1163:1163) (1196:1196:1196)) - (PORT datac (917:917:917) (959:959:959)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (665:665:665) (722:722:722)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1692:1692:1692) (1745:1745:1745)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15699,1204 +9301,10 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) (DELAY (ABSOLUTE - (PORT dataa (854:854:854) (896:896:896)) - (PORT datab (814:814:814) (835:835:835)) - (PORT datac (1604:1604:1604) (1624:1624:1624)) - (PORT datad (1091:1091:1091) (1104:1104:1104)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1081:1081:1081)) - (PORT datab (643:643:643) (686:686:686)) - (PORT datac (880:880:880) (916:916:916)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1506:1506:1506) (1583:1583:1583)) - (PORT datab (645:645:645) (676:676:676)) - (PORT datac (924:924:924) (965:965:965)) - (PORT datad (1191:1191:1191) (1244:1244:1244)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1363:1363:1363) (1381:1381:1381)) - (PORT datad (584:584:584) (632:632:632)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1468:1468:1468)) - (PORT datab (376:376:376) (404:404:404)) - (PORT datac (631:631:631) (672:672:672)) - (PORT datad (695:695:695) (746:746:746)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1011:1011:1011)) - (PORT datab (845:845:845) (882:882:882)) - (PORT datac (544:544:544) (563:563:563)) - (PORT datad (1121:1121:1121) (1121:1121:1121)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1168:1168:1168)) - (PORT datab (927:927:927) (955:955:955)) - (PORT datac (1207:1207:1207) (1250:1250:1250)) - (PORT datad (1220:1220:1220) (1269:1269:1269)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1132:1132:1132)) - (PORT datab (613:613:613) (653:653:653)) - (PORT datac (186:186:186) (227:227:227)) - (PORT datad (836:836:836) (844:844:844)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (2020:2020:2020) (2146:2146:2146)) - (PORT datac (1954:1954:1954) (2061:2061:2061)) - (PORT datad (1620:1620:1620) (1793:1793:1793)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1426:1426:1426)) - (PORT datab (1201:1201:1201) (1270:1270:1270)) - (PORT datac (1175:1175:1175) (1230:1230:1230)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datac (842:842:842) (866:866:866)) - (PORT datad (625:625:625) (636:636:636)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (592:592:592)) - (PORT datab (387:387:387) (415:415:415)) - (PORT datac (1088:1088:1088) (1123:1123:1123)) - (PORT datad (809:809:809) (841:841:841)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1660:1660:1660)) - (PORT datab (1645:1645:1645) (1688:1688:1688)) - (PORT datac (1674:1674:1674) (1745:1745:1745)) - (PORT datad (1153:1153:1153) (1190:1190:1190)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (717:717:717)) - (PORT datab (1418:1418:1418) (1466:1466:1466)) - (PORT datac (927:927:927) (1002:1002:1002)) - (PORT datad (320:320:320) (342:342:342)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (453:453:453)) - (PORT datab (381:381:381) (414:414:414)) - (PORT datac (948:948:948) (997:997:997)) - (PORT datad (902:902:902) (929:929:929)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (924:924:924)) - (PORT datab (1172:1172:1172) (1217:1217:1217)) - (PORT datad (586:586:586) (617:617:617)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (665:665:665)) - (PORT datab (400:400:400) (448:448:448)) - (PORT datac (903:903:903) (950:950:950)) - (PORT datad (1154:1154:1154) (1178:1178:1178)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1171:1171:1171)) - (PORT datad (1850:1850:1850) (1892:1892:1892)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1190:1190:1190)) - (PORT datab (1154:1154:1154) (1186:1186:1186)) - (PORT datac (1365:1365:1365) (1404:1404:1404)) - (PORT datad (1108:1108:1108) (1127:1127:1127)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (413:413:413)) - (PORT datab (1708:1708:1708) (1765:1765:1765)) - (PORT datac (1580:1580:1580) (1686:1686:1686)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (1414:1414:1414) (1421:1421:1421)) - (PORT datad (1852:1852:1852) (1893:1893:1893)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1191:1191:1191)) - (PORT datab (1155:1155:1155) (1186:1186:1186)) - (PORT datac (1366:1366:1366) (1405:1405:1405)) - (PORT datad (826:826:826) (842:842:842)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (681:681:681) (708:708:708)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (413:413:413)) - (PORT datab (1709:1709:1709) (1766:1766:1766)) - (PORT datac (1579:1579:1579) (1681:1681:1681)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (325:325:325)) - (PORT datab (1404:1404:1404) (1519:1519:1519)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1374:1374:1374)) - (PORT datac (1019:1019:1019) (1043:1043:1043)) - (PORT datad (1368:1368:1368) (1412:1412:1412)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1174:1174:1174)) - (PORT datab (371:371:371) (403:403:403)) - (PORT datad (1851:1851:1851) (1894:1894:1894)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1369:1369:1369)) - (PORT datac (1018:1018:1018) (1041:1041:1041)) - (PORT datad (1364:1364:1364) (1407:1407:1407)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1699:1699:1699) (1727:1727:1727)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (905:905:905) (954:954:954)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1172:1172:1172)) - (PORT datab (368:368:368) (402:402:402)) - (PORT datad (1853:1853:1853) (1893:1893:1893)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (663:663:663)) - (PORT datab (940:940:940) (1000:1000:1000)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (1281:1281:1281) (1368:1368:1368)) - (PORT datab (1005:1005:1005) (1055:1055:1055)) - (PORT datac (915:915:915) (968:968:968)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1394:1394:1394)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (1112:1112:1112) (1132:1132:1132)) - (PORT datad (596:596:596) (654:654:654)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (838:838:838)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (859:859:859) (867:867:867)) - (PORT datad (1351:1351:1351) (1364:1364:1364)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (970:970:970) (999:999:999)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1256:1256:1256)) - (PORT datab (676:676:676) (714:714:714)) - (PORT datad (959:959:959) (992:992:992)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (1275:1275:1275) (1362:1362:1362)) - (PORT datab (1010:1010:1010) (1056:1056:1056)) - (PORT datac (916:916:916) (969:969:969)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (969:969:969) (1001:1001:1001)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (197:197:197) (236:236:236)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1527:1527:1527)) - (PORT datab (1196:1196:1196) (1250:1250:1250)) - (PORT datac (1752:1752:1752) (1873:1873:1873)) - (PORT datad (543:543:543) (551:551:551)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1136:1136:1136) (1158:1158:1158)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1742:1742:1742) (1856:1856:1856)) - (PORT datab (1391:1391:1391) (1393:1393:1393)) - (PORT datac (1113:1113:1113) (1130:1130:1130)) - (PORT datad (1127:1127:1127) (1128:1128:1128)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1151:1151:1151) (1170:1170:1170)) - (PORT datab (624:624:624) (692:692:692)) - (PORT datac (1345:1345:1345) (1352:1352:1352)) - (PORT datad (823:823:823) (830:830:830)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1134:1134:1134) (1155:1155:1155)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1395:1395:1395)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (1113:1113:1113) (1134:1134:1134)) - (PORT datad (597:597:597) (655:655:655)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datad (211:211:211) (244:244:244)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (696:696:696)) - (PORT datab (660:660:660) (673:673:673)) - (PORT datac (762:762:762) (771:771:771)) - (PORT datad (596:596:596) (645:645:645)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT dataa (1296:1296:1296) (1377:1377:1377)) - (PORT datac (840:840:840) (891:891:891)) - (PORT datad (1367:1367:1367) (1411:1411:1411)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1381:1381:1381)) - (PORT datac (861:861:861) (899:899:899)) - (PORT datad (1371:1371:1371) (1413:1413:1413)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1380:1380:1380)) - (PORT datac (861:861:861) (899:899:899)) - (PORT datad (1371:1371:1371) (1413:1413:1413)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1201:1201:1201) (1221:1221:1221)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (676:676:676) (712:712:712)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1381:1381:1381)) - (PORT datac (841:841:841) (888:888:888)) - (PORT datad (1369:1369:1369) (1414:1414:1414)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (449:449:449) (481:481:481)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1109:1109:1109) (1118:1118:1118)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1107:1107:1107) (1116:1116:1116)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (312:312:312)) - (PORT datab (1080:1080:1080) (1119:1119:1119)) - (PORT datad (362:362:362) (415:415:415)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (701:701:701)) - (PORT datab (642:642:642) (676:676:676)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1879:1879:1879) (1937:1937:1937)) - (PORT datab (1816:1816:1816) (1903:1903:1903)) - (PORT datac (209:209:209) (252:252:252)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (892:892:892)) - (PORT datab (878:878:878) (922:922:922)) - (PORT datac (538:538:538) (540:540:540)) - (PORT datad (617:617:617) (645:645:645)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1222:1222:1222)) - (PORT datab (1045:1045:1045) (1100:1100:1100)) - (PORT datac (695:695:695) (747:747:747)) - (PORT datad (1116:1116:1116) (1134:1134:1134)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1256:1256:1256)) - (PORT datab (677:677:677) (742:742:742)) - (PORT datac (546:546:546) (556:556:556)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (548:548:548)) - (PORT datab (646:646:646) (698:698:698)) - (PORT datac (641:641:641) (670:670:670)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1518:1518:1518)) - (PORT datab (576:576:576) (596:596:596)) - (PORT datad (642:642:642) (669:669:669)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (460:460:460)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (607:607:607) (629:629:629)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1052:1052:1052)) - (PORT datab (442:442:442) (513:513:513)) - (PORT datac (1170:1170:1170) (1219:1219:1219)) - (PORT datad (423:423:423) (496:496:496)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1867:1867:1867)) - (PORT datab (1235:1235:1235) (1271:1271:1271)) - (PORT datac (1201:1201:1201) (1255:1255:1255)) - (PORT datad (985:985:985) (1038:1038:1038)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (910:910:910) (962:962:962)) - (PORT datad (182:182:182) (214:214:214)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1762:1762:1762) (1747:1747:1747)) - (PORT datab (1212:1212:1212) (1248:1248:1248)) - (PORT datac (634:634:634) (657:657:657)) - (PORT datad (825:825:825) (876:876:876)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (685:685:685)) - (PORT datab (647:647:647) (666:666:666)) - (PORT datad (880:880:880) (928:928:928)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (963:963:963)) - (PORT datab (1141:1141:1141) (1159:1159:1159)) - (PORT datac (1626:1626:1626) (1670:1670:1670)) - (PORT datad (878:878:878) (910:910:910)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (371:371:371)) - (PORT datab (915:915:915) (950:950:950)) - (PORT datac (1075:1075:1075) (1082:1082:1082)) - (PORT datad (1088:1088:1088) (1108:1108:1108)) + (PORT dataa (601:601:601) (613:613:613)) + (PORT datab (1161:1161:1161) (1190:1190:1190)) + (PORT datac (1554:1554:1554) (1560:1560:1560)) + (PORT datad (518:518:518) (534:534:534)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16906,31 +9314,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (INSTANCE z80_\|alu_\|db\[7\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1162:1162:1162) (1199:1199:1199)) - (PORT datab (826:826:826) (911:911:911)) - (PORT datac (1135:1135:1135) (1158:1158:1158)) - (PORT datad (788:788:788) (836:836:836)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1136:1136:1136)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (997:997:997) (1023:1023:1023)) - (PORT datad (886:886:886) (940:940:940)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (943:943:943) (988:988:988)) + (PORT datac (909:909:909) (961:961:961)) + (PORT datad (656:656:656) (703:703:703)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16938,205 +9328,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (INSTANCE z80_\|address_latch_\|abusz\[14\]) (DELAY (ABSOLUTE - (PORT dataa (1004:1004:1004) (1084:1084:1084)) - (PORT datab (954:954:954) (1049:1049:1049)) - (PORT datac (1094:1094:1094) (1101:1101:1101)) - (PORT datad (195:195:195) (232:232:232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (947:947:947)) - (PORT datab (837:837:837) (839:839:839)) - (PORT datac (413:413:413) (484:484:484)) - (PORT datad (636:636:636) (716:716:716)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1162:1162:1162)) - (PORT datab (392:392:392) (471:471:471)) - (PORT datac (1098:1098:1098) (1115:1115:1115)) - (PORT datad (640:640:640) (718:718:718)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (636:636:636)) - (PORT datab (1622:1622:1622) (1684:1684:1684)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (862:862:862) (899:899:899)) + (PORT dataa (678:678:678) (712:712:712)) + (PORT datac (629:629:629) (646:646:646)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT dataa (728:728:728) (795:795:795)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (983:983:983) (1020:1020:1020)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1469:1469:1469) (1520:1520:1520)) - (PORT datab (636:636:636) (670:670:670)) - (PORT datac (1209:1209:1209) (1261:1261:1261)) - (PORT datad (653:653:653) (675:675:675)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (453:453:453)) - (PORT datab (293:293:293) (385:385:385)) - (PORT datad (251:251:251) (325:325:325)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (700:700:700)) - (PORT datab (1035:1035:1035) (1050:1050:1050)) - (PORT datac (1203:1203:1203) (1278:1278:1278)) - (PORT datad (2028:2028:2028) (2053:2053:2053)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1105:1105:1105)) - (PORT datab (783:783:783) (893:893:893)) - (PORT datac (1472:1472:1472) (1539:1539:1539)) - (PORT datad (893:893:893) (943:943:943)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (830:830:830)) - (PORT datab (2475:2475:2475) (2536:2536:2536)) - (PORT datac (1334:1334:1334) (1380:1380:1380)) - (PORT datad (707:707:707) (810:810:810)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (867:867:867)) - (PORT datab (655:655:655) (692:692:692)) - (PORT datac (845:845:845) (859:859:859)) - (PORT datad (831:831:831) (863:863:863)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1085:1085:1085)) - (PORT datab (899:899:899) (926:926:926)) - (PORT datac (925:925:925) (1014:1014:1014)) - (PORT datad (194:194:194) (228:228:228)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (926:926:926) (999:999:999)) + (PORT datab (1496:1496:1496) (1557:1557:1557)) + (PORT datac (791:791:791) (799:799:799)) + (PORT datad (921:921:921) (982:982:982)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17144,93 +9356,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (INSTANCE z80_\|execute_\|fMRead\~10) (DELAY (ABSOLUTE - (PORT dataa (1046:1046:1046) (1122:1122:1122)) - (PORT datab (196:196:196) (234:234:234)) + (PORT dataa (603:603:603) (632:632:632)) + (PORT datab (1000:1000:1000) (1048:1048:1048)) + (PORT datac (711:711:711) (758:758:758)) + (PORT datad (541:541:541) (556:556:556)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (795:795:795)) + (PORT datab (1000:1000:1000) (1044:1044:1044)) + (PORT datac (635:635:635) (680:680:680)) (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1258:1258:1258)) - (PORT datab (1956:1956:1956) (2026:2026:2026)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (575:575:575) (577:577:577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1423:1423:1423) (1498:1498:1498)) - (PORT datab (1500:1500:1500) (1572:1572:1572)) - (PORT datac (866:866:866) (926:926:926)) - (PORT datad (1174:1174:1174) (1212:1212:1212)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1205:1205:1205)) - (PORT datab (873:873:873) (884:884:884)) - (PORT datac (670:670:670) (726:726:726)) - (PORT datad (1092:1092:1092) (1114:1114:1114)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1724:1724:1724) (1770:1770:1770)) - (PORT datab (1956:1956:1956) (2027:2027:2027)) - (PORT datac (609:609:609) (664:664:664)) - (PORT datad (828:828:828) (846:846:846)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1195:1195:1195) (1241:1241:1241)) - (PORT datab (704:704:704) (759:759:759)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (683:683:683) (746:746:746)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17238,47 +9388,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (INSTANCE z80_\|execute_\|fMRead\~9) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (614:614:614) (645:645:645)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1261:1261:1261) (1306:1306:1306)) + (PORT datab (999:999:999) (1045:1045:1045)) + (PORT datac (1076:1076:1076) (1084:1084:1084)) + (PORT datad (1108:1108:1108) (1123:1123:1123)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) (DELAY (ABSOLUTE - (PORT dataa (2201:2201:2201) (2281:2281:2281)) - (PORT datab (1459:1459:1459) (1512:1512:1512)) - (PORT datac (730:730:730) (781:781:781)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (981:981:981) (1046:1046:1046)) + (PORT datac (180:180:180) (218:218:218)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~27) (DELAY (ABSOLUTE - (PORT dataa (1006:1006:1006) (1082:1082:1082)) - (PORT datab (957:957:957) (1052:1052:1052)) - (PORT datac (599:599:599) (626:626:626)) - (PORT datad (1185:1185:1185) (1214:1214:1214)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (1441:1441:1441) (1473:1473:1473)) + (PORT datab (923:923:923) (968:968:968)) + (PORT datac (652:652:652) (754:754:754)) + (PORT datad (1794:1794:1794) (1909:1909:1909)) + (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT datab (1572:1572:1572) (1702:1702:1702)) + (PORT datac (1412:1412:1412) (1479:1479:1479)) + (PORT datad (1138:1138:1138) (1156:1156:1156)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17286,705 +9448,65 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (636:636:636)) - (PORT datab (580:580:580) (603:603:603)) - (PORT datac (2168:2168:2168) (2243:2243:2243)) - (PORT datad (533:533:533) (549:549:549)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1199:1199:1199) (1235:1235:1235)) + (PORT datab (644:644:644) (659:659:659)) + (PORT datac (856:856:856) (909:909:909)) + (PORT datad (1134:1134:1134) (1157:1157:1157)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (955:955:955)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (1494:1494:1494) (1581:1581:1581)) + (PORT datac (823:823:823) (866:866:866)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (884:884:884)) + (PORT datad (829:829:829) (844:844:844)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) (DELAY (ABSOLUTE - (PORT dataa (1375:1375:1375) (1410:1410:1410)) - (PORT datab (757:757:757) (812:812:812)) - (PORT datac (2169:2169:2169) (2240:2240:2240)) - (PORT datad (1276:1276:1276) (1310:1310:1310)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1068:1068:1068)) - (PORT datab (1342:1342:1342) (1431:1431:1431)) - (PORT datac (728:728:728) (781:781:781)) - (PORT datad (915:915:915) (953:953:953)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) + (PORT dataa (857:857:857) (876:876:876)) (PORT datab (236:236:236) (281:281:281)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (899:899:899)) - (PORT datab (777:777:777) (885:885:885)) - (PORT datac (628:628:628) (674:674:674)) - (PORT datad (707:707:707) (811:811:811)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~15) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (642:642:642)) - (PORT datab (744:744:744) (781:781:781)) - (PORT datac (1960:1960:1960) (2018:2018:2018)) - (PORT datad (808:808:808) (821:821:821)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~16) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (853:853:853)) - (PORT datab (779:779:779) (885:885:885)) - (PORT datac (754:754:754) (860:860:860)) - (PORT datad (1842:1842:1842) (1891:1891:1891)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (720:720:720)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (525:525:525) (536:536:536)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1178:1178:1178)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (809:809:809) (833:833:833)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1655:1655:1655) (1672:1672:1672)) - (PORT datab (1989:1989:1989) (2051:2051:2051)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (1449:1449:1449) (1444:1444:1444)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT datab (777:777:777) (881:881:881)) - (PORT datac (751:751:751) (853:853:853)) - (PORT datad (1014:1014:1014) (1034:1034:1034)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (827:827:827)) - (PORT datab (2350:2350:2350) (2475:2475:2475)) - (PORT datac (751:751:751) (853:853:853)) - (PORT datad (649:649:649) (694:694:694)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) - (DELAY - (ABSOLUTE - (PORT datab (1154:1154:1154) (1254:1254:1254)) - (PORT datac (908:908:908) (984:984:984)) - (PORT datad (695:695:695) (796:796:796)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) - (DELAY - (ABSOLUTE - (PORT dataa (2509:2509:2509) (2581:2581:2581)) - (PORT datab (930:930:930) (981:981:981)) - (PORT datac (1138:1138:1138) (1158:1158:1158)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (935:935:935)) - (PORT datab (776:776:776) (881:881:881)) - (PORT datac (751:751:751) (854:854:854)) - (PORT datad (563:563:563) (572:572:572)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (240:240:240)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (207:207:207) (237:237:237)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT datab (390:390:390) (430:430:430)) - (PORT datad (887:887:887) (895:895:895)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1104:1104:1104)) - (PORT datab (452:452:452) (487:487:487)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1994:1994:1994) (2001:2001:2001)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1075:1075:1075)) - (PORT datab (1343:1343:1343) (1437:1437:1437)) - (PORT datac (2168:2168:2168) (2246:2246:2246)) - (PORT datad (914:914:914) (958:958:958)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (389:389:389)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1584:1584:1584) (1620:1620:1620)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (726:726:726)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (882:882:882) (905:905:905)) - (PORT datad (1416:1416:1416) (1450:1450:1450)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1449:1449:1449) (1484:1484:1484)) - (PORT datac (344:344:344) (368:368:368)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (899:899:899)) - (PORT datab (2351:2351:2351) (2480:2480:2480)) - (PORT datac (628:628:628) (672:672:672)) - (PORT datad (671:671:671) (769:769:769)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (718:718:718)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (524:524:524) (535:535:535)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (237:237:237) (282:282:282)) - (PORT datac (727:727:727) (782:782:782)) - (PORT datad (217:217:217) (251:251:251)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (439:439:439)) - (PORT datab (296:296:296) (390:390:390)) - (PORT datac (1137:1137:1137) (1168:1168:1168)) - (PORT datad (250:250:250) (323:323:323)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT dataa (2200:2200:2200) (2281:2281:2281)) - (PORT datab (236:236:236) (278:278:278)) - (PORT datac (602:602:602) (659:659:659)) - (PORT datad (1039:1039:1039) (1034:1034:1034)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (1452:1452:1452) (1485:1485:1485)) - (PORT datac (1451:1451:1451) (1488:1488:1488)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (594:594:594)) - (PORT datab (550:550:550) (563:563:563)) - (PORT datac (1357:1357:1357) (1370:1370:1370)) - (PORT datad (647:647:647) (674:674:674)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (584:584:584)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (634:634:634) (678:678:678)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (607:607:607) (648:648:648)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (902:902:902)) - (PORT datab (2019:2019:2019) (2038:2038:2038)) - (PORT datac (811:811:811) (824:824:824)) - (PORT datad (887:887:887) (895:895:895)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (262:262:262)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (212:212:212) (244:244:244)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1970:1970:1970) (2029:2029:2029)) - (PORT datac (826:826:826) (890:890:890)) - (PORT datad (544:544:544) (549:549:549)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (415:415:415)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (608:608:608) (631:631:631)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (219:219:219) (258:258:258)) (PORT datac (193:193:193) (226:226:226)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (658:658:658)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (336:336:336) (360:360:360)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1241:1241:1241)) - (PORT datab (451:451:451) (487:487:487)) - (PORT datac (746:746:746) (800:800:800)) - (PORT datad (1929:1929:1929) (1986:1986:1986)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1218:1218:1218) (1238:1238:1238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1992:1992:1992) (2003:2003:2003)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (957:957:957)) - (PORT datab (948:948:948) (988:988:988)) - (PORT datac (952:952:952) (1040:1040:1040)) - (PORT datad (1244:1244:1244) (1337:1337:1337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (920:920:920)) - (PORT datab (555:555:555) (584:584:584)) - (PORT datac (2651:2651:2651) (2699:2699:2699)) - (PORT datad (325:325:325) (347:347:347)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1107:1107:1107)) - (PORT datab (787:787:787) (896:896:896)) - (PORT datac (722:722:722) (831:831:831)) - (PORT datad (1631:1631:1631) (1626:1626:1626)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (546:546:546) (547:547:547)) - (PORT datad (1991:1991:1991) (2002:2002:2002)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1360:1360:1360)) - (PORT datab (1487:1487:1487) (1548:1548:1548)) - (PORT datac (611:611:611) (675:675:675)) - (PORT datad (827:827:827) (876:876:876)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (906:906:906)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (1102:1102:1102) (1091:1091:1091)) - (PORT datad (362:362:362) (397:397:397)) + (PORT datad (1144:1144:1144) (1174:1174:1174)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -17994,519 +9516,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) (DELAY (ABSOLUTE - (PORT dataa (2510:2510:2510) (2578:2578:2578)) - (PORT datab (968:968:968) (1013:1013:1013)) - (PORT datac (1329:1329:1329) (1335:1335:1335)) - (PORT datad (869:869:869) (880:880:880)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (476:476:476)) - (PORT datab (968:968:968) (1011:1011:1011)) - (PORT datac (1340:1340:1340) (1390:1390:1390)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (475:475:475)) - (PORT datab (896:896:896) (921:921:921)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (389:389:389)) - (PORT datab (388:388:388) (429:429:429)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (886:886:886) (895:895:895)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (1994:1994:1994) (2001:2001:2001)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (1398:1398:1398) (1449:1449:1449)) - (PORT datac (1373:1373:1373) (1416:1416:1416)) - (PORT datad (1070:1070:1070) (1118:1118:1118)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (990:990:990) (1026:1026:1026)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (990:990:990) (1026:1026:1026)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (664:664:664)) - (PORT datab (941:941:941) (1002:1002:1002)) - (PORT datad (216:216:216) (285:285:285)) + (PORT dataa (1197:1197:1197) (1255:1255:1255)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datad (1079:1079:1079) (1143:1143:1143)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (679:679:679) (694:694:694)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (448:448:448)) - (PORT datab (941:941:941) (971:971:971)) - (PORT datac (952:952:952) (1001:1001:1001)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (920:920:920)) - (PORT datab (889:889:889) (924:924:924)) - (PORT datac (807:807:807) (828:828:828)) - (PORT datad (558:558:558) (581:581:581)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1257:1257:1257) (1295:1295:1295)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1260:1260:1260) (1299:1299:1299)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1050:1050:1050)) - (PORT datab (965:965:965) (1007:1007:1007)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (978:978:978) (1023:1023:1023)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (637:637:637) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (979:979:979)) - (PORT datab (934:934:934) (981:981:981)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1132:1132:1132) (1209:1209:1209)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1562:1562:1562)) - (PORT datab (665:665:665) (715:715:715)) - (PORT datad (1640:1640:1640) (1755:1755:1755)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (631:631:631) (671:671:671)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1005:1005:1005) (1051:1051:1051)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (957:957:957) (994:994:994)) - (PORT datad (880:880:880) (927:927:927)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1153:1153:1153) (1205:1205:1205)) - (PORT ena (1204:1204:1204) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1497:1497:1497) (1521:1521:1521)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (744:744:744)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (587:587:587) (604:604:604)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1256:1256:1256) (1290:1290:1290)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1257:1257:1257) (1292:1292:1292)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (708:708:708)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (625:625:625) (661:661:661)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT asdata (1551:1551:1551) (1646:1646:1646)) - (PORT ena (1256:1256:1256) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (912:912:912)) - (PORT datab (1255:1255:1255) (1305:1305:1305)) - (PORT datad (635:635:635) (652:652:652)) - (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) (DELAY (ABSOLUTE - (PORT dataa (643:643:643) (685:685:685)) - (PORT datab (803:803:803) (863:863:863)) - (PORT datac (602:602:602) (611:611:611)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1327:1327:1327) (1388:1388:1388)) + (PORT datab (1241:1241:1241) (1298:1298:1298)) + (PORT datac (988:988:988) (1040:1040:1040)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (935:935:935)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (906:906:906) (956:956:956)) + (PORT datad (1158:1158:1158) (1199:1199:1199)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~22) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (638:638:638) (681:681:681)) + (PORT datac (1570:1570:1570) (1640:1640:1640)) + (PORT datad (566:566:566) (574:574:574)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18516,317 +9576,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (INSTANCE z80_\|pla_decode_\|Equal5\~2) (DELAY (ABSOLUTE - (PORT dataa (844:844:844) (867:867:867)) - (PORT datab (1027:1027:1027) (1075:1075:1075)) - (PORT datac (339:339:339) (360:360:360)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1174:1174:1174)) - (PORT datab (1389:1389:1389) (1427:1427:1427)) - (PORT datac (932:932:932) (1001:1001:1001)) - (PORT datad (1353:1353:1353) (1389:1389:1389)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2598:2598:2598) (2655:2655:2655)) - (PORT datab (203:203:203) (244:244:244)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (1110:1110:1110) (1142:1142:1142)) - (PORT datad (1438:1438:1438) (1486:1486:1486)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (710:710:710)) - (PORT datab (940:940:940) (967:967:967)) - (PORT datac (1128:1128:1128) (1173:1173:1173)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1209:1209:1209)) - (PORT datac (912:912:912) (935:935:935)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1206:1206:1206)) - (PORT datab (943:943:943) (970:970:970)) - (PORT datac (1105:1105:1105) (1135:1135:1135)) - (PORT datad (1434:1434:1434) (1479:1479:1479)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (493:493:493)) - (PORT datac (568:568:568) (586:586:586)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (690:690:690) (717:717:717)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (690:690:690) (717:717:717)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (665:665:665)) - (PORT datab (946:946:946) (1002:1002:1002)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1265:1265:1265) (1314:1314:1314)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1265:1265:1265) (1316:1316:1316)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (312:312:312)) - (PORT datab (1085:1085:1085) (1113:1113:1113)) - (PORT datad (357:357:357) (417:417:417)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (919:919:919) (943:943:943)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (919:919:919) (943:943:943)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (457:457:457)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (417:417:417) (444:444:444)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1412:1412:1412) (1427:1427:1427)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1376:1376:1376)) - (PORT datab (1003:1003:1003) (1047:1047:1047)) - (PORT datad (892:892:892) (942:942:942)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1471:1471:1471) (1507:1507:1507)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1489:1489:1489) (1614:1614:1614)) - (PORT datab (1521:1521:1521) (1656:1656:1656)) - (PORT datac (2142:2142:2142) (2142:2142:2142)) - (PORT datad (646:646:646) (662:662:662)) + (PORT dataa (1816:1816:1816) (1908:1908:1908)) + (PORT datab (2116:2116:2116) (2267:2267:2267)) + (PORT datac (592:592:592) (610:610:610)) + (PORT datad (1468:1468:1468) (1543:1543:1543)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -18836,1403 +9592,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (284:284:284)) - (PORT datab (736:736:736) (799:799:799)) - (PORT datac (897:897:897) (948:948:948)) - (PORT datad (1169:1169:1169) (1226:1226:1226)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (952:952:952)) - (PORT datab (644:644:644) (665:665:665)) - (PORT datac (1286:1286:1286) (1331:1331:1331)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (829:829:829) (884:884:884)) - (PORT datac (710:710:710) (803:803:803)) - (PORT datad (644:644:644) (666:666:666)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (942:942:942)) - (PORT datab (1388:1388:1388) (1430:1430:1430)) - (PORT datac (205:205:205) (241:241:241)) - (PORT datad (172:172:172) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (207:207:207) (245:245:245)) - (PORT datad (1277:1277:1277) (1328:1328:1328)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1277:1277:1277)) - (PORT datac (2040:2040:2040) (2164:2164:2164)) - (PORT datad (1304:1304:1304) (1444:1444:1444)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (693:693:693)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (546:546:546) (555:555:555)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (2136:2136:2136)) - (PORT datab (1507:1507:1507) (1522:1522:1522)) - (PORT datac (1089:1089:1089) (1120:1120:1120)) - (PORT datad (1570:1570:1570) (1713:1713:1713)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1803:1803:1803) (1900:1900:1900)) - (PORT datab (1596:1596:1596) (1748:1748:1748)) - (PORT datac (3144:3144:3144) (3233:3233:3233)) - (PORT datad (1902:1902:1902) (2090:2090:2090)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1474:1474:1474) (1525:1525:1525)) - (PORT datab (1976:1976:1976) (2075:2075:2075)) - (PORT datac (1520:1520:1520) (1551:1551:1551)) - (PORT datad (1771:1771:1771) (1858:1858:1858)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (1561:1561:1561) (1627:1627:1627)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (643:643:643)) - (PORT datab (602:602:602) (655:655:655)) - (PORT datac (616:616:616) (660:660:660)) - (PORT datad (343:343:343) (363:363:363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (665:665:665) (693:693:693)) - (PORT datac (1025:1025:1025) (1030:1030:1030)) - (PORT datad (584:584:584) (607:607:607)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (975:975:975)) - (PORT datab (657:657:657) (694:694:694)) - (PORT datac (1759:1759:1759) (1816:1816:1816)) - (PORT datad (562:562:562) (580:580:580)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (638:638:638)) - (PORT datab (656:656:656) (696:696:696)) - (PORT datac (178:178:178) (217:217:217)) - (PORT datad (943:943:943) (992:992:992)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT datac (555:555:555) (591:591:591)) - (PORT datad (1085:1085:1085) (1092:1092:1092)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2156:2156:2156)) - (PORT datab (1422:1422:1422) (1488:1488:1488)) - (PORT datad (1323:1323:1323) (1495:1495:1495)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (1021:1021:1021)) - (PORT datab (993:993:993) (1042:1042:1042)) - (PORT datac (1464:1464:1464) (1524:1524:1524)) - (PORT datad (1227:1227:1227) (1313:1313:1313)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (965:965:965) (1025:1025:1025)) - (PORT datac (912:912:912) (977:977:977)) - (PORT datad (958:958:958) (998:998:998)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1890:1890:1890)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (584:584:584) (639:639:639)) - (PORT datad (1583:1583:1583) (1570:1570:1570)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1386:1386:1386) (1474:1474:1474)) - (PORT datab (1349:1349:1349) (1521:1521:1521)) - (PORT datac (1103:1103:1103) (1126:1126:1126)) - (PORT datad (1358:1358:1358) (1519:1519:1519)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datab (642:642:642) (688:688:688)) - (PORT datad (333:333:333) (358:358:358)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1128:1128:1128)) - (PORT datab (820:820:820) (850:850:850)) - (PORT datac (558:558:558) (591:591:591)) - (PORT datad (546:546:546) (551:551:551)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1074:1074:1074)) - (PORT datab (881:881:881) (904:904:904)) - (PORT datac (1049:1049:1049) (1138:1138:1138)) - (PORT datad (1271:1271:1271) (1360:1360:1360)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (734:734:734)) - (PORT datab (924:924:924) (980:980:980)) - (PORT datac (1471:1471:1471) (1536:1536:1536)) - (PORT datad (1149:1149:1149) (1181:1181:1181)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1132:1132:1132)) - (PORT datab (360:360:360) (393:393:393)) - (PORT datac (555:555:555) (590:590:590)) - (PORT datad (1061:1061:1061) (1074:1074:1074)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (601:601:601) (626:626:626)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (861:861:861) (894:894:894)) - (PORT datad (593:593:593) (607:607:607)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (694:694:694)) - (PORT datab (1536:1536:1536) (1599:1599:1599)) - (PORT datac (961:961:961) (990:990:990)) - (PORT datad (1384:1384:1384) (1458:1458:1458)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (893:893:893)) - (PORT datab (563:563:563) (581:581:581)) - (PORT datac (801:801:801) (807:807:807)) - (PORT datad (831:831:831) (859:859:859)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (340:340:340)) - (PORT datab (1770:1770:1770) (1810:1810:1810)) - (PORT datac (255:255:255) (312:312:312)) - (PORT datad (1200:1200:1200) (1271:1271:1271)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1728:1728:1728) (1834:1834:1834)) - (PORT datab (887:887:887) (890:890:890)) - (PORT datac (859:859:859) (902:902:902)) - (PORT datad (1842:1842:1842) (2007:2007:2007)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1729:1729:1729) (1835:1835:1835)) - (PORT datab (1714:1714:1714) (1825:1825:1825)) - (PORT datac (859:859:859) (903:903:903)) - (PORT datad (2100:2100:2100) (2296:2296:2296)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (250:250:250)) - (PORT datab (221:221:221) (269:269:269)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (201:201:201) (229:229:229)) + (PORT dataa (357:357:357) (400:400:400)) + (PORT datab (614:614:614) (651:651:651)) + (PORT datac (200:200:200) (237:237:237)) + (PORT datad (921:921:921) (963:963:963)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (719:719:719) (745:745:745)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (718:718:718) (747:747:747)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (982:982:982)) - (PORT datab (937:937:937) (984:984:984)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1270:1270:1270) (1302:1302:1302)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1271:1271:1271) (1304:1304:1304)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1056:1056:1056)) - (PORT datab (968:968:968) (1014:1014:1014)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (999:999:999) (1040:1040:1040)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1562:1562:1562)) - (PORT datab (657:657:657) (709:709:709)) - (PORT datad (1632:1632:1632) (1751:1751:1751)) - (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1772:1772:1772) (1847:1847:1847)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1916:1916:1916) (1967:1967:1967)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (700:700:700)) - (PORT datab (498:498:498) (553:553:553)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT asdata (1475:1475:1475) (1524:1524:1524)) - (PORT ena (1256:1256:1256) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (921:921:921)) - (PORT datab (672:672:672) (692:692:692)) - (PORT datad (1219:1219:1219) (1269:1269:1269)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (913:913:913) (927:927:927)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (972:972:972)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (917:917:917) (961:961:961)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1003:1003:1003) (1054:1054:1054)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1001:1001:1001) (1054:1054:1054)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (706:706:706)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (625:625:625) (656:656:656)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (666:666:666)) - (PORT datab (831:831:831) (898:898:898)) - (PORT datac (578:578:578) (588:588:588)) - (PORT datad (591:591:591) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (843:843:843)) - (PORT datab (1032:1032:1032) (1063:1063:1063)) - (PORT datac (813:813:813) (859:859:859)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1040:1040:1040)) - (PORT datac (960:960:960) (1021:1021:1021)) - (PORT datad (1216:1216:1216) (1283:1283:1283)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1164:1164:1164) (1183:1183:1183)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1036:1036:1036)) - (PORT datab (992:992:992) (1052:1052:1052)) - (PORT datac (1247:1247:1247) (1332:1332:1332)) - (PORT datad (1118:1118:1118) (1138:1138:1138)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (1926:1926:1926) (1967:1967:1967)) + (PORT datab (1148:1148:1148) (1185:1185:1185)) + (PORT datac (1146:1146:1146) (1185:1185:1185)) + (PORT datad (1925:1925:1925) (1953:1953:1953)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) (DELAY (ABSOLUTE - (PORT dataa (1491:1491:1491) (1578:1578:1578)) - (PORT datab (588:588:588) (620:620:620)) - (PORT datad (574:574:574) (600:600:600)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1029:1029:1029) (1114:1114:1114)) + (PORT datab (627:627:627) (649:649:649)) + (PORT datac (1538:1538:1538) (1668:1668:1668)) + (PORT datad (1102:1102:1102) (1120:1120:1120)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) (DELAY (ABSOLUTE - (PORT datab (979:979:979) (1030:1030:1030)) - (PORT datac (935:935:935) (999:999:999)) - (PORT datad (1216:1216:1216) (1283:1283:1283)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1181:1181:1181) (1228:1228:1228)) + (PORT datab (1461:1461:1461) (1489:1489:1489)) + (PORT datac (1114:1114:1114) (1146:1146:1146)) + (PORT datad (1508:1508:1508) (1559:1559:1559)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1793:1793:1793) (1856:1856:1856)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (917:917:917) (937:937:937)) + (PORT datad (1423:1423:1423) (1450:1450:1450)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) (DELAY (ABSOLUTE - (PORT datab (973:973:973) (1024:1024:1024)) - (PORT datac (931:931:931) (993:993:993)) - (PORT datad (1213:1213:1213) (1277:1277:1277)) + (PORT dataa (238:238:238) (289:289:289)) + (PORT datab (651:651:651) (704:704:704)) + (PORT datac (893:893:893) (945:945:945)) + (PORT datad (896:896:896) (956:956:956)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (565:565:565) (592:592:592)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1019:1019:1019) (1071:1071:1071)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1018:1018:1018) (1071:1071:1071)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1051:1051:1051)) - (PORT datab (965:965:965) (1008:1008:1008)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (914:914:914) (930:930:930)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (914:914:914) (930:930:930)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (978:978:978)) - (PORT datab (931:931:931) (977:977:977)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1218:1218:1218) (1256:1256:1256)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1558:1558:1558)) - (PORT datab (659:659:659) (703:703:703)) - (PORT datad (1630:1630:1630) (1743:1743:1743)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1214:1214:1214) (1253:1253:1253)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1211:1211:1211) (1250:1250:1250)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (712:712:712)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (623:623:623) (658:658:658)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (697:697:697) (721:721:721)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (968:968:968)) - (PORT datab (959:959:959) (996:996:996)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1223:1223:1223) (1248:1248:1248)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1227:1227:1227) (1258:1258:1258)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (520:520:520)) - (PORT datab (498:498:498) (554:554:554)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1229:1229:1229) (1261:1261:1261)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1035:1035:1035)) - (PORT datab (1291:1291:1291) (1330:1330:1330)) - (PORT datad (1490:1490:1490) (1545:1545:1545)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (369:369:369)) - (PORT datab (654:654:654) (670:670:670)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (382:382:382)) - (PORT datab (615:615:615) (642:642:642)) - (PORT datac (632:632:632) (658:658:658)) - (PORT datad (613:613:613) (637:637:637)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (847:847:847)) - (PORT datab (405:405:405) (445:445:445)) - (PORT datac (1349:1349:1349) (1373:1373:1373)) - (PORT datad (593:593:593) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (895:895:895) (905:905:905)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (1250:1250:1250) (1323:1323:1323)) - (PORT datad (563:563:563) (584:584:584)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (327:327:327)) - (PORT datab (589:589:589) (623:623:623)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (405:405:405)) - (PORT datac (883:883:883) (935:935:935)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (179:179:179) (218:218:218)) - (PORT datad (603:603:603) (621:621:621)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20240,47 +9688,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (236:236:236) (288:288:288)) - (PORT datab (680:680:680) (738:738:738)) - (PORT datac (1196:1196:1196) (1238:1238:1238)) - (PORT datad (1772:1772:1772) (1834:1834:1834)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (908:908:908) (948:948:948)) + (PORT datab (1000:1000:1000) (1060:1060:1060)) + (PORT datac (1625:1625:1625) (1656:1656:1656)) + (PORT datad (631:631:631) (682:682:682)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (860:860:860)) - (PORT datab (1104:1104:1104) (1147:1147:1147)) - (PORT datac (1002:1002:1002) (1071:1071:1071)) - (PORT datad (847:847:847) (873:873:873)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1078:1078:1078) (1094:1094:1094)) + (PORT datad (343:343:343) (363:363:363)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (944:944:944)) + (PORT datab (628:628:628) (665:665:665)) + (PORT datac (855:855:855) (878:878:878)) + (PORT datad (561:561:561) (587:587:587)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (941:941:941)) - (PORT datab (916:916:916) (948:948:948)) - (PORT datac (338:338:338) (357:357:357)) - (PORT datad (854:854:854) (893:893:893)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (968:968:968) (1035:1035:1035)) + (PORT datab (1634:1634:1634) (1659:1659:1659)) + (PORT datac (1183:1183:1183) (1225:1225:1225)) + (PORT datad (946:946:946) (980:980:980)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20291,58 +9753,322 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (453:453:453)) - (PORT datab (1472:1472:1472) (1490:1490:1490)) - (PORT datac (1016:1016:1016) (1077:1077:1077)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (647:647:647) (693:693:693)) + (PORT datab (2028:2028:2028) (2071:2071:2071)) + (PORT datac (1456:1456:1456) (1525:1525:1525)) + (PORT datad (928:928:928) (945:945:945)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1033:1033:1033)) + (PORT datab (1229:1229:1229) (1256:1256:1256)) + (PORT datac (1153:1153:1153) (1236:1236:1236)) + (PORT datad (1150:1150:1150) (1170:1170:1170)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1481:1481:1481) (1505:1505:1505)) + (PORT datab (374:374:374) (397:397:397)) + (PORT datac (1422:1422:1422) (1480:1480:1480)) + (PORT datad (1121:1121:1121) (1190:1190:1190)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (763:763:763)) + (PORT datab (657:657:657) (713:713:713)) + (PORT datac (1710:1710:1710) (1755:1755:1755)) + (PORT datad (1160:1160:1160) (1199:1199:1199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (872:872:872)) + (PORT datac (690:690:690) (799:799:799)) + (PORT datad (962:962:962) (1055:1055:1055)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1580:1580:1580)) + (PORT datab (897:897:897) (929:929:929)) + (PORT datac (1513:1513:1513) (1557:1557:1557)) + (PORT datad (1759:1759:1759) (1804:1804:1804)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (374:374:374)) - (PORT datab (663:663:663) (676:676:676)) - (PORT datac (551:551:551) (566:566:566)) - (PORT datad (616:616:616) (633:633:633)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1211:1211:1211) (1274:1274:1274)) + (PORT datab (1260:1260:1260) (1377:1377:1377)) + (PORT datac (1648:1648:1648) (1819:1819:1819)) + (PORT datad (397:397:397) (426:426:426)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (INSTANCE z80_\|execute_\|ctl_al_we\~4) (DELAY (ABSOLUTE - (PORT dataa (1147:1147:1147) (1215:1215:1215)) - (PORT datab (1209:1209:1209) (1278:1278:1278)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (827:827:827) (839:839:839)) + (PORT dataa (404:404:404) (435:435:435)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (1194:1194:1194) (1234:1234:1234)) + (PORT datad (382:382:382) (412:412:412)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1239:1239:1239)) + (PORT datab (1847:1847:1847) (1912:1912:1912)) + (PORT datac (1506:1506:1506) (1541:1541:1541)) + (PORT datad (1295:1295:1295) (1364:1364:1364)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1278:1278:1278)) + (PORT datac (1761:1761:1761) (1845:1845:1845)) + (PORT datad (1131:1131:1131) (1154:1154:1154)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (422:422:422)) + (PORT datab (918:918:918) (969:969:969)) + (PORT datac (608:608:608) (627:627:627)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1383:1383:1383)) + (PORT datab (1960:1960:1960) (2010:2010:2010)) + (PORT datac (792:792:792) (822:822:822)) + (PORT datad (2106:2106:2106) (2137:2137:2137)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1856:1856:1856)) + (PORT datab (1757:1757:1757) (1827:1827:1827)) + (PORT datac (2074:2074:2074) (2182:2182:2182)) + (PORT datad (1232:1232:1232) (1305:1305:1305)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (1735:1735:1735) (1780:1780:1780)) + (PORT datac (1149:1149:1149) (1176:1176:1176)) + (PORT datad (1330:1330:1330) (1363:1363:1363)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1280:1280:1280)) + (PORT datab (585:585:585) (608:608:608)) + (PORT datac (652:652:652) (702:702:702)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1810:1810:1810) (1863:1863:1863)) + (PORT datab (1124:1124:1124) (1167:1167:1167)) + (PORT datac (1121:1121:1121) (1144:1144:1144)) + (PORT datad (1670:1670:1670) (1693:1693:1693)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1190:1190:1190)) + (PORT datab (596:596:596) (625:625:625)) + (PORT datac (1134:1134:1134) (1160:1160:1160)) + (PORT datad (225:225:225) (260:260:260)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (741:741:741)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1106:1106:1106) (1133:1133:1133)) + (PORT datad (658:658:658) (680:680:680)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1336:1336:1336)) + (PORT datab (991:991:991) (1048:1048:1048)) + (PORT datac (580:580:580) (634:634:634)) + (PORT datad (1470:1470:1470) (1539:1539:1539)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) + (INSTANCE z80_\|address_latch_\|Q\[14\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -20352,626 +10078,65 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (900:900:900) (908:908:908)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (900:900:900) (911:911:911)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (318:318:318)) - (PORT datab (1081:1081:1081) (1113:1113:1113)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1215:1215:1215) (1256:1256:1256)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1217:1217:1217) (1254:1254:1254)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (462:462:462)) - (PORT datab (452:452:452) (481:481:481)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (621:621:621) (651:651:651)) - (PORT datac (1318:1318:1318) (1334:1334:1334)) - (PORT datad (1133:1133:1133) (1166:1166:1166)) + (PORT dataa (1532:1532:1532) (1562:1562:1562)) + (PORT datab (2538:2538:2538) (2566:2566:2566)) + (PORT datac (945:945:945) (994:994:994)) + (PORT datad (931:931:931) (945:945:945)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (596:596:596)) - (PORT datab (1148:1148:1148) (1164:1164:1164)) - (PORT datac (1083:1083:1083) (1082:1082:1082)) - (PORT datad (819:819:819) (843:843:843)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (835:835:835)) - (PORT datab (390:390:390) (417:417:417)) - (PORT datac (1069:1069:1069) (1074:1074:1074)) - (PORT datad (1075:1075:1075) (1109:1109:1109)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (685:685:685)) - (PORT datab (1345:1345:1345) (1363:1363:1363)) - (PORT datac (653:653:653) (717:717:717)) - (PORT datad (1140:1140:1140) (1170:1170:1170)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (952:952:952)) - (PORT datab (882:882:882) (913:913:913)) - (PORT datac (1082:1082:1082) (1120:1120:1120)) - (PORT datad (836:836:836) (859:859:859)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (911:911:911)) - (PORT datab (599:599:599) (619:619:619)) - (PORT datac (802:802:802) (820:820:820)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (952:952:952)) - (PORT datab (903:903:903) (934:934:934)) - (PORT datac (806:806:806) (826:826:826)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (954:954:954)) - (PORT datab (891:891:891) (915:915:915)) - (PORT datac (862:862:862) (932:932:932)) - (PORT datad (1058:1058:1058) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1695:1695:1695) (1745:1745:1745)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) (DELAY (ABSOLUTE - (PORT datad (1005:1005:1005) (1047:1047:1047)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (847:847:847)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (710:710:710)) - (PORT datab (244:244:244) (289:289:289)) - (PORT datad (547:547:547) (596:596:596)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1690:1690:1690) (1722:1722:1722)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1694:1694:1694) (1745:1745:1745)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1687:1687:1687) (1719:1719:1719)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (759:759:759)) - (PORT datab (676:676:676) (718:718:718)) - (PORT datad (629:629:629) (658:658:658)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (458:458:458)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1445:1445:1445) (1462:1462:1462)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1445:1445:1445) (1465:1465:1465)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (661:661:661)) - (PORT datab (941:941:941) (1000:1000:1000)) - (PORT datad (216:216:216) (284:284:284)) + (PORT dataa (1522:1522:1522) (1674:1674:1674)) + (PORT datab (1832:1832:1832) (2023:2023:2023)) + (PORT datac (1749:1749:1749) (1883:1883:1883)) + (PORT datad (1529:1529:1529) (1629:1629:1629)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (622:622:622)) - (PORT datab (801:801:801) (823:823:823)) - (PORT datac (647:647:647) (685:685:685)) - (PORT datad (828:828:828) (870:870:870)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (704:704:704)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (622:622:622) (661:661:661)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (899:899:899)) - (PORT datab (353:353:353) (392:392:392)) - (PORT datac (1132:1132:1132) (1184:1184:1184)) - (PORT datad (670:670:670) (701:701:701)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (672:672:672) (695:695:695)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) (DELAY (ABSOLUTE - (PORT dataa (1469:1469:1469) (1520:1520:1520)) - (PORT datab (820:820:820) (835:835:835)) - (PORT datad (653:653:653) (675:675:675)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (912:912:912) (928:928:928)) + (PORT datab (954:954:954) (1013:1013:1013)) + (PORT datac (889:889:889) (915:915:915)) + (PORT datad (1490:1490:1490) (1513:1513:1513)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (607:607:607) (630:630:630)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (704:704:704) (782:782:782)) - (PORT datad (796:796:796) (798:798:798)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1209:1209:1209) (1265:1265:1265)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1132:1132:1132)) - (PORT datad (634:634:634) (652:652:652)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1250:1250:1250)) - (PORT datab (904:904:904) (935:935:935)) - (PORT datac (384:384:384) (452:452:452)) - (PORT datad (911:911:911) (971:971:971)) + (PORT datab (691:691:691) (715:715:715)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (891:891:891) (930:930:930)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (390:390:390) (464:464:464)) - (PORT datad (189:189:189) (222:222:222)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20979,14 +10144,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (INSTANCE z80_\|pla_decode_\|Equal62\~2) (DELAY (ABSOLUTE - (PORT dataa (1543:1543:1543) (1611:1611:1611)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (432:432:432) (479:479:479)) - (PORT datad (319:319:319) (341:341:341)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datac (1127:1127:1127) (1186:1186:1186)) + (PORT datad (1027:1027:1027) (1133:1133:1133)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (492:492:492)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (903:903:903) (942:942:942)) + (PORT datad (421:421:421) (486:486:486)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1371:1371:1371)) + (PORT datab (1733:1733:1733) (1812:1812:1812)) + (PORT datac (1131:1131:1131) (1186:1186:1186)) + (PORT datad (1024:1024:1024) (1129:1129:1129)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20995,445 +10188,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT datac (880:880:880) (934:934:934)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (892:892:892) (909:909:909)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1387:1387:1387) (1394:1394:1394)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1035:1035:1035)) - (PORT datab (1288:1288:1288) (1327:1327:1327)) - (PORT datad (831:831:831) (901:901:901)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1200:1200:1200) (1214:1214:1214)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (957:957:957) (998:998:998)) - (PORT datad (879:879:879) (924:924:924)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1245:1245:1245) (1259:1259:1259)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1245:1245:1245) (1259:1259:1259)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (706:706:706)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (621:621:621) (655:655:655)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1206:1206:1206) (1211:1211:1211)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1386:1386:1386) (1392:1392:1392)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (513:513:513)) - (PORT datab (498:498:498) (557:557:557)) - (PORT datad (622:622:622) (662:662:662)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (674:674:674)) - (PORT datab (845:845:845) (862:862:862)) - (PORT datac (584:584:584) (597:597:597)) - (PORT datad (575:575:575) (585:585:585)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1426:1426:1426) (1436:1436:1436)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1076:1076:1076) (1088:1088:1088)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1056:1056:1056)) - (PORT datab (964:964:964) (1012:1012:1012)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1210:1210:1210) (1217:1217:1217)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1556:1556:1556)) - (PORT datab (656:656:656) (706:706:706)) - (PORT datad (1631:1631:1631) (1740:1740:1740)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (709:709:709) (736:736:736)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (709:709:709) (736:736:736)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (977:977:977)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (899:899:899) (938:938:938)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (672:672:672)) - (PORT datab (674:674:674) (694:694:694)) - (PORT datac (855:855:855) (905:905:905)) - (PORT datad (319:319:319) (339:339:339)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (579:579:579)) - (PORT datab (400:400:400) (438:438:438)) - (PORT datac (1346:1346:1346) (1369:1369:1369)) - (PORT datad (569:569:569) (587:587:587)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (694:694:694)) - (PORT datab (621:621:621) (667:667:667)) - (PORT datad (582:582:582) (592:592:592)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (403:403:403) (482:482:482)) - (PORT datad (585:585:585) (610:610:610)) + (PORT dataa (971:971:971) (1046:1046:1046)) + (PORT datab (707:707:707) (763:763:763)) + (PORT datac (1491:1491:1491) (1589:1589:1589)) + (PORT datad (1500:1500:1500) (1593:1593:1593)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1542:1542:1542)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1392:1392:1392) (1448:1448:1448)) + (PORT datad (1090:1090:1090) (1101:1101:1101)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (535:535:535)) + (PORT datab (2099:2099:2099) (2168:2168:2168)) + (PORT datac (1127:1127:1127) (1186:1186:1186)) + (PORT datad (1025:1025:1025) (1131:1131:1131)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21441,328 +10236,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (508:508:508)) - (PORT datab (905:905:905) (932:932:932)) - (PORT datac (415:415:415) (484:484:484)) - (PORT datad (188:188:188) (218:218:218)) + (PORT dataa (255:255:255) (315:315:315)) + (PORT datab (858:858:858) (886:886:886)) + (PORT datac (1500:1500:1500) (1562:1562:1562)) + (PORT datad (1096:1096:1096) (1134:1134:1134)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (909:909:909) (948:948:948)) + (PORT datac (637:637:637) (668:668:668)) + (PORT datad (600:600:600) (639:639:639)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (611:611:611)) + (PORT datab (1035:1035:1035) (1047:1047:1047)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (190:190:190) (224:224:224)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1540:1540:1540) (1609:1609:1609)) - (PORT datab (380:380:380) (414:414:414)) - (PORT datac (435:435:435) (484:484:484)) - (PORT datad (359:359:359) (378:378:378)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (883:883:883) (940:940:940)) - (PORT datad (333:333:333) (350:350:350)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (503:503:503)) - (PORT datab (904:904:904) (930:930:930)) - (PORT datac (414:414:414) (483:483:483)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (2165:2165:2165) (2195:2195:2195)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (2167:2167:2167) (2197:2197:2197)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]) (DELAY (ABSOLUTE - (PORT dataa (918:918:918) (982:982:982)) - (PORT datab (932:932:932) (982:982:982)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1965:1965:1965) (2001:2001:2001)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1563:1563:1563)) - (PORT datab (662:662:662) (714:714:714)) - (PORT datad (1637:1637:1637) (1748:1748:1748)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (959:959:959) (984:984:984)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (961:961:961) (982:982:982)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1058:1058:1058)) - (PORT datab (964:964:964) (1012:1012:1012)) - (PORT datad (353:353:353) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1767:1767:1767) (1800:1800:1800)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1768:1768:1768) (1802:1802:1802)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (711:711:711)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (622:622:622) (656:656:656)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1910:1910:1910) (1926:1926:1926)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1990:1990:1990) (2006:2006:2006)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (514:514:514)) - (PORT datab (497:497:497) (558:558:558)) - (PORT datad (621:621:621) (655:655:655)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1990:1990:1990) (2008:2008:2008)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1111:1111:1111)) - (PORT datab (882:882:882) (895:895:895)) - (PORT datac (824:824:824) (834:834:834)) - (PORT datad (1128:1128:1128) (1146:1146:1146)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1167:1167:1167) (1252:1252:1252)) + (PORT datab (714:714:714) (758:758:758)) + (PORT datac (1577:1577:1577) (1594:1594:1594)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21770,91 +10300,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (715:715:715)) - (PORT datab (1096:1096:1096) (1104:1104:1104)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (950:950:950) (981:981:981)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1034:1034:1034)) - (PORT datab (1288:1288:1288) (1327:1327:1327)) - (PORT datad (844:844:844) (907:907:907)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (2137:2137:2137) (2157:2157:2157)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (327:327:327)) - (PORT datab (957:957:957) (993:993:993)) - (PORT datad (879:879:879) (921:921:921)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (701:701:701)) - (PORT datab (651:651:651) (704:704:704)) - (PORT datac (614:614:614) (661:661:661)) - (PORT datad (632:632:632) (653:653:653)) + (PORT dataa (1458:1458:1458) (1527:1527:1527)) + (PORT datab (1191:1191:1191) (1267:1267:1267)) + (PORT datac (1209:1209:1209) (1271:1271:1271)) + (PORT datad (1798:1798:1798) (1823:1823:1823)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -21862,488 +10314,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (636:636:636)) - (PORT datab (654:654:654) (706:706:706)) - (PORT datac (844:844:844) (895:895:895)) - (PORT datad (172:172:172) (196:196:196)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1408:1408:1408)) - (PORT datab (643:643:643) (692:692:692)) - (PORT datac (543:543:543) (567:567:567)) - (PORT datad (373:373:373) (401:401:401)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1137:1137:1137) (1157:1157:1157)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1648:1648:1648)) - (PORT datab (588:588:588) (621:621:621)) - (PORT datad (575:575:575) (600:600:600)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (565:565:565) (592:592:592)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (589:589:589)) - (PORT datab (711:711:711) (747:747:747)) - (PORT datac (381:381:381) (458:458:458)) - (PORT datad (623:623:623) (682:682:682)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (521:521:521)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (519:519:519) (550:550:550)) - (PORT datad (1502:1502:1502) (1569:1569:1569)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (903:903:903) (949:949:949)) - (PORT datac (795:795:795) (815:815:815)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (591:591:591)) - (PORT datab (712:712:712) (749:749:749)) - (PORT datac (380:380:380) (454:454:454)) - (PORT datad (624:624:624) (682:682:682)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (508:508:508)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (963:963:963) (1022:1022:1022)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (962:962:962) (1021:1021:1021)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1057:1057:1057)) - (PORT datab (969:969:969) (1008:1008:1008)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (678:678:678) (714:714:714)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (678:678:678) (714:714:714)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (982:982:982)) - (PORT datab (937:937:937) (981:981:981)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (893:893:893) (927:927:927)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1710:1710:1710) (1763:1763:1763)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (700:700:700)) - (PORT datab (501:501:501) (558:558:558)) - (PORT datad (620:620:620) (655:655:655)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1710:1710:1710) (1761:1761:1761)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1144:1144:1144)) - (PORT datab (705:705:705) (763:763:763)) - (PORT datac (1078:1078:1078) (1114:1114:1114)) - (PORT datad (188:188:188) (223:223:223)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1291:1291:1291)) - (PORT datab (808:808:808) (845:845:845)) - (PORT datac (818:818:818) (868:868:868)) - (PORT datad (804:804:804) (813:813:813)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1330:1330:1330)) - (PORT datab (985:985:985) (1056:1056:1056)) - (PORT datac (647:647:647) (686:686:686)) - (PORT datad (1360:1360:1360) (1453:1453:1453)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (388:388:388)) - (PORT datab (889:889:889) (946:946:946)) - (PORT datac (612:612:612) (646:646:646)) - (PORT datad (933:933:933) (987:987:987)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (970:970:970)) - (PORT datab (287:287:287) (346:346:346)) - (PORT datad (853:853:853) (856:856:856)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datab (285:285:285) (345:345:345)) - (PORT datad (854:854:854) (856:856:856)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) (DELAY (ABSOLUTE - (PORT dataa (2000:2000:2000) (2162:2162:2162)) - (PORT datac (1090:1090:1090) (1122:1122:1122)) - (PORT datad (1323:1323:1323) (1497:1497:1497)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (1580:1580:1580) (1683:1683:1683)) + (PORT datac (1558:1558:1558) (1700:1700:1700)) + (PORT datad (651:651:651) (698:698:698)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -22353,12 +10333,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (945:945:945) (967:967:967)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (888:888:888) (937:937:937)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (653:653:653) (700:700:700)) + (PORT datab (1336:1336:1336) (1384:1384:1384)) + (PORT datac (1002:1002:1002) (1027:1027:1027)) + (PORT datad (314:314:314) (334:334:334)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22366,13 +10346,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datac (698:698:698) (765:765:765)) - (PORT datad (855:855:855) (908:908:908)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (239:239:239) (288:288:288)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1613:1613:1613) (1765:1765:1765)) + (PORT datab (1371:1371:1371) (1395:1395:1395)) + (PORT datac (1383:1383:1383) (1423:1423:1423)) + (PORT datad (1273:1273:1273) (1357:1357:1357)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22380,13 +10376,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) (DELAY (ABSOLUTE - (PORT datab (224:224:224) (265:265:265)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1323:1323:1323) (1378:1378:1378)) + (PORT dataa (636:636:636) (671:671:671)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (615:615:615) (653:653:653)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (965:965:965)) + (PORT datab (1230:1230:1230) (1309:1309:1309)) + (PORT datac (901:901:901) (933:933:933)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1527:1527:1527)) + (PORT datab (660:660:660) (703:703:703)) + (PORT datac (1214:1214:1214) (1276:1276:1276)) + (PORT datad (1351:1351:1351) (1352:1352:1352)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2208:2208:2208) (2424:2424:2424)) + (PORT datab (984:984:984) (1064:1064:1064)) + (PORT datac (1509:1509:1509) (1543:1543:1543)) + (PORT datad (1172:1172:1172) (1236:1236:1236)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1310:1310:1310)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1425:1425:1425) (1491:1491:1491)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (929:929:929) (974:974:974)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (1401:1401:1401) (1424:1424:1424)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22394,91 +10472,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) (DELAY (ABSOLUTE - (PORT dataa (1541:1541:1541) (1629:1629:1629)) - (PORT datab (1591:1591:1591) (1670:1670:1670)) - (PORT datac (857:857:857) (918:918:918)) - (PORT datad (398:398:398) (467:467:467)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (507:507:507)) - (PORT datab (587:587:587) (606:606:606)) - (PORT datac (849:849:849) (909:909:909)) - (PORT datad (239:239:239) (282:282:282)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (662:662:662) (679:679:679)) - (PORT ena (1474:1474:1474) (1475:1475:1475)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (663:663:663)) - (PORT datab (1117:1117:1117) (1151:1151:1151)) - (PORT datad (847:847:847) (870:870:870)) + (PORT dataa (950:950:950) (1015:1015:1015)) + (PORT datab (1896:1896:1896) (2024:2024:2024)) + (PORT datac (914:914:914) (971:971:971)) + (PORT datad (718:718:718) (797:797:797)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (662:662:662)) - (PORT datab (1316:1316:1316) (1369:1369:1369)) - (PORT datac (209:209:209) (247:247:247)) - (PORT datad (841:841:841) (848:848:848)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (252:252:252) (311:311:311)) - (PORT datad (347:347:347) (371:371:371)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (933:933:933) (971:971:971)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (928:928:928) (983:983:983)) + (PORT datad (1369:1369:1369) (1395:1395:1395)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -22488,10 +10507,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (419:419:419)) - (PORT datab (1011:1011:1011) (1072:1072:1072)) - (PORT datac (1687:1687:1687) (1750:1750:1750)) - (PORT datad (1175:1175:1175) (1233:1233:1233)) + (PORT dataa (239:239:239) (290:290:290)) + (PORT datab (1157:1157:1157) (1198:1198:1198)) + (PORT datac (1291:1291:1291) (1405:1405:1405)) + (PORT datad (925:925:925) (941:941:941)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -22501,16 +10520,154 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (586:586:586) (607:607:607)) - (PORT datac (918:918:918) (934:934:934)) - (PORT datad (852:852:852) (859:859:859)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1787:1787:1787) (1839:1839:1839)) + (PORT datab (1447:1447:1447) (1469:1469:1469)) + (PORT datac (630:630:630) (666:666:666)) + (PORT datad (910:910:910) (923:923:923)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (969:969:969)) + (PORT datab (1447:1447:1447) (1470:1470:1470)) + (PORT datac (885:885:885) (929:929:929)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1818:1818:1818) (1920:1920:1920)) + (PORT datab (1563:1563:1563) (1693:1693:1693)) + (PORT datad (216:216:216) (241:241:241)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1205:1205:1205)) + (PORT datab (2276:2276:2276) (2317:2317:2317)) + (PORT datac (1130:1130:1130) (1165:1165:1165)) + (PORT datad (1979:1979:1979) (2101:2101:2101)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1206:1206:1206)) + (PORT datab (1237:1237:1237) (1284:1284:1284)) + (PORT datac (1128:1128:1128) (1167:1167:1167)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (896:896:896)) + (PORT datab (379:379:379) (402:402:402)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (441:441:441)) + (PORT datab (2145:2145:2145) (2210:2210:2210)) + (PORT datac (1175:1175:1175) (1254:1254:1254)) + (PORT datad (1368:1368:1368) (1417:1417:1417)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (389:389:389)) + (PORT datab (1350:1350:1350) (1386:1386:1386)) + (PORT datac (361:361:361) (381:381:381)) + (PORT datad (881:881:881) (938:938:938)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1490:1490:1490)) + (PORT datab (831:831:831) (869:869:869)) + (PORT datac (569:569:569) (588:588:588)) + (PORT datad (909:909:909) (934:934:934)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (947:947:947) (1009:1009:1009)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -22520,23 +10677,23 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) (DELAY (ABSOLUTE - (PORT datab (593:593:593) (612:612:612)) - (PORT datac (250:250:250) (307:307:307)) - (PORT datad (858:858:858) (860:860:860)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1453:1453:1453) (1482:1482:1482)) + (PORT datab (837:837:837) (874:874:874)) + (PORT datad (904:904:904) (964:964:964)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT clk (1516:1516:1516) (1520:1520:1520)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -22550,1685 +10707,39 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (921:921:921)) - (PORT datab (1005:1005:1005) (1064:1064:1064)) - (PORT datac (1691:1691:1691) (1755:1755:1755)) - (PORT datad (1168:1168:1168) (1225:1225:1225)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1024:1024:1024)) - (PORT datab (1075:1075:1075) (1139:1139:1139)) - (PORT datac (867:867:867) (925:925:925)) - (PORT datad (646:646:646) (678:678:678)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (731:731:731)) - (PORT datab (660:660:660) (692:692:692)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (913:913:913) (955:955:955)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (725:725:725)) - (PORT datab (663:663:663) (713:713:713)) - (PORT datac (627:627:627) (659:659:659)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1454:1454:1454) (1593:1593:1593)) - (PORT datab (927:927:927) (972:972:972)) - (PORT datac (587:587:587) (604:604:604)) - (PORT datad (1544:1544:1544) (1686:1686:1686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (951:951:951)) - (PORT datab (989:989:989) (1033:1033:1033)) - (PORT datac (1425:1425:1425) (1436:1436:1436)) - (PORT datad (651:651:651) (670:670:670)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1306:1306:1306)) - (PORT datab (621:621:621) (668:668:668)) - (PORT datac (1465:1465:1465) (1520:1520:1520)) - (PORT datad (628:628:628) (636:636:636)) + (PORT dataa (1721:1721:1721) (1772:1772:1772)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (2071:2071:2071) (2177:2177:2177)) + (PORT datad (215:215:215) (240:240:240)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1281:1281:1281)) - (PORT datab (1244:1244:1244) (1294:1294:1294)) - (PORT datac (877:877:877) (941:941:941)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1306:1306:1306)) - (PORT datab (1263:1263:1263) (1349:1349:1349)) - (PORT datac (2128:2128:2128) (2214:2214:2214)) - (PORT datad (1440:1440:1440) (1511:1511:1511)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (408:408:408)) - (PORT datab (654:654:654) (669:669:669)) - (PORT datac (357:357:357) (377:377:377)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (392:392:392)) - (PORT datab (337:337:337) (369:369:369)) - (PORT datac (870:870:870) (876:876:876)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (293:293:293)) - (PORT datab (893:893:893) (901:901:901)) - (PORT datac (366:366:366) (393:393:393)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (998:998:998)) - (PORT datab (218:218:218) (255:255:255)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (610:610:610) (646:646:646)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1381:1381:1381)) - (PORT datab (674:674:674) (719:719:719)) - (PORT datac (640:640:640) (688:688:688)) - (PORT datad (913:913:913) (955:955:955)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (661:661:661)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (699:699:699)) - (PORT datab (247:247:247) (288:288:288)) - (PORT datac (828:828:828) (858:858:858)) - (PORT datad (843:843:843) (860:860:860)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (508:508:508)) - (PORT datab (867:867:867) (892:892:892)) - (PORT datac (604:604:604) (651:651:651)) - (PORT datad (566:566:566) (585:585:585)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1252:1252:1252)) - (PORT datab (574:574:574) (587:587:587)) - (PORT datac (861:861:861) (886:886:886)) - (PORT datad (1797:1797:1797) (1884:1884:1884)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1255:1255:1255)) - (PORT datab (572:572:572) (588:588:588)) - (PORT datac (858:858:858) (886:886:886)) - (PORT datad (1798:1798:1798) (1887:1887:1887)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (298:298:298)) - (PORT datab (554:554:554) (571:571:571)) - (PORT datac (228:228:228) (266:266:266)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (214:214:214) (259:259:259)) - (PORT datad (204:204:204) (235:235:235)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (825:825:825) (834:834:834)) - (PORT datac (556:556:556) (572:572:572)) - (PORT datad (330:330:330) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT asdata (690:690:690) (711:711:711)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1079:1079:1079)) - (PORT datab (664:664:664) (707:707:707)) - (PORT datac (633:633:633) (680:680:680)) - (PORT datad (584:584:584) (611:611:611)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datac (625:625:625) (657:657:657)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (992:992:992) (1100:1100:1100)) - (PORT datab (1591:1591:1591) (1671:1671:1671)) - (PORT datac (857:857:857) (917:917:917)) - (PORT datad (421:421:421) (491:491:491)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (710:710:710) (805:805:805)) - (PORT datad (847:847:847) (895:895:895)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (943:943:943)) - (PORT datab (1389:1389:1389) (1433:1433:1433)) - (PORT datac (204:204:204) (242:242:242)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (514:514:514)) - (PORT datab (270:270:270) (325:325:325)) - (PORT datad (605:605:605) (628:628:628)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (886:886:886)) - (PORT datab (812:812:812) (875:875:875)) - (PORT datac (607:607:607) (626:626:626)) - (PORT datad (617:617:617) (630:630:630)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (843:843:843) (913:913:913)) - (PORT datad (662:662:662) (672:672:672)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1717:1717:1717) (1813:1813:1813)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1717:1717:1717) (1813:1813:1813)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (976:976:976)) - (PORT datab (932:932:932) (975:975:975)) - (PORT datad (214:214:214) (282:282:282)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1677:1677:1677) (1751:1751:1751)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1074:1074:1074) (1150:1150:1150)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1053:1053:1053)) - (PORT datab (967:967:967) (1008:1008:1008)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1419:1419:1419) (1492:1492:1492)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1488:1488:1488) (1562:1562:1562)) - (PORT datab (663:663:663) (712:712:712)) - (PORT datad (1638:1638:1638) (1752:1752:1752)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (957:957:957) (989:989:989)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (956:956:956) (987:987:987)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (970:970:970)) - (PORT datab (956:956:956) (998:998:998)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1182:1182:1182) (1255:1255:1255)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1429:1429:1429) (1502:1502:1502)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (689:689:689)) - (PORT datab (456:456:456) (531:531:531)) - (PORT datad (627:627:627) (664:664:664)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1431:1431:1431) (1502:1502:1502)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1431:1431:1431) (1503:1503:1503)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (706:706:706)) - (PORT datab (239:239:239) (320:320:320)) - (PORT datad (626:626:626) (662:662:662)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1427:1427:1427) (1500:1500:1500)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1033:1033:1033)) - (PORT datab (1290:1290:1290) (1329:1329:1329)) - (PORT datad (808:808:808) (878:878:878)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (403:403:403)) - (PORT datab (862:862:862) (914:914:914)) - (PORT datac (576:576:576) (606:606:606)) - (PORT datad (807:807:807) (828:828:828)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (614:614:614)) - (PORT datab (839:839:839) (859:859:859)) - (PORT datac (619:619:619) (659:659:659)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT datab (902:902:902) (944:944:944)) - (PORT datad (877:877:877) (887:887:887)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (510:510:510)) - (PORT datab (213:213:213) (259:259:259)) - (PORT datac (584:584:584) (636:636:636)) - (PORT datad (673:673:673) (710:710:710)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (761:761:761) (801:801:801)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (621:621:621) (663:663:663)) - (PORT datad (560:560:560) (586:586:586)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (538:538:538) (569:569:569)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (606:606:606) (648:648:648)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (395:395:395) (466:466:466)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1539:1539:1539) (1609:1609:1609)) - (PORT datab (534:534:534) (553:553:553)) - (PORT datac (434:434:434) (481:481:481)) - (PORT datad (345:345:345) (369:369:369)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1357:1357:1357) (1408:1408:1408)) - (PORT datac (420:420:420) (460:460:460)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1067:1067:1067)) - (PORT datab (879:879:879) (898:898:898)) - (PORT datac (1268:1268:1268) (1345:1345:1345)) - (PORT datad (1057:1057:1057) (1068:1068:1068)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (721:721:721)) - (PORT datab (1094:1094:1094) (1099:1099:1099)) - (PORT datac (994:994:994) (1030:1030:1030)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (743:743:743) (837:837:837)) - (PORT datac (199:199:199) (234:234:234)) - (PORT datad (227:227:227) (256:256:256)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (882:882:882) (933:933:933)) - (PORT datac (1359:1359:1359) (1403:1403:1403)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (674:674:674)) - (PORT datab (413:413:413) (463:463:463)) - (PORT datac (855:855:855) (912:912:912)) - (PORT datad (242:242:242) (285:285:285)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (728:728:728)) - (PORT datab (860:860:860) (903:903:903)) - (PORT datac (2033:2033:2033) (2070:2070:2070)) - (PORT datad (836:836:836) (928:928:928)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (445:445:445)) - (PORT datab (1316:1316:1316) (1370:1370:1370)) - (PORT datac (609:609:609) (627:627:627)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (915:915:915)) - (PORT datab (354:354:354) (389:389:389)) - (PORT datac (610:610:610) (623:623:623)) - (PORT datad (640:640:640) (654:654:654)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (949:949:949)) - (PORT datab (600:600:600) (621:621:621)) - (PORT datac (196:196:196) (230:230:230)) - (PORT datad (809:809:809) (832:832:832)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (744:744:744)) - (PORT datab (874:874:874) (931:931:931)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (217:217:217) (255:255:255)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1036:1036:1036)) - (PORT datab (1285:1285:1285) (1323:1323:1323)) - (PORT datad (1367:1367:1367) (1447:1447:1447)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (905:905:905) (935:935:935)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (326:326:326)) - (PORT datab (959:959:959) (996:996:996)) - (PORT datad (880:880:880) (920:920:920)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (966:966:966) (1015:1015:1015)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (969:969:969) (1017:1017:1017)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (711:711:711)) - (PORT datab (378:378:378) (450:450:450)) - (PORT datad (620:620:620) (653:653:653)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (1052:1052:1052) (1055:1055:1055)) - (PORT datad (328:328:328) (344:344:344)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1215:1215:1215) (1257:1257:1257)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1488:1488:1488) (1562:1562:1562)) - (PORT datab (662:662:662) (713:713:713)) - (PORT datad (1636:1636:1636) (1747:1747:1747)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (846:846:846)) - (PORT datab (915:915:915) (949:949:949)) - (PORT datac (338:338:338) (359:359:359)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (644:644:644)) - (PORT datab (645:645:645) (697:697:697)) - (PORT datac (1345:1345:1345) (1373:1373:1373)) - (PORT datad (375:375:375) (406:406:406)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (866:866:866) (878:878:878)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (608:608:608)) - (PORT datab (622:622:622) (664:664:664)) - (PORT datac (425:425:425) (498:498:498)) - (PORT datad (563:563:563) (590:590:590)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (520:520:520)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (584:584:584) (613:613:613)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1538:1538:1538) (1606:1606:1606)) - (PORT datab (586:586:586) (605:605:605)) - (PORT datac (435:435:435) (481:481:481)) - (PORT datad (348:348:348) (372:372:372)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (902:902:902) (948:948:948)) - (PORT datac (775:775:775) (783:783:783)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datab (711:711:711) (744:744:744)) - (PORT datac (392:392:392) (466:466:466)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (887:887:887)) - (PORT datad (867:867:867) (907:907:907)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1199:1199:1199)) - (PORT datab (399:399:399) (474:474:474)) - (PORT datac (670:670:670) (691:691:691)) - (PORT datad (1153:1153:1153) (1200:1200:1200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (548:548:548) (605:605:605)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1542:1542:1542) (1611:1611:1611)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (431:431:431) (485:485:485)) - (PORT datad (526:526:526) (542:542:542)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (638:638:638)) - (PORT datab (400:400:400) (442:442:442)) - (PORT datac (1344:1344:1344) (1372:1372:1372)) - (PORT datad (551:551:551) (569:569:569)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1249:1249:1249)) - (PORT datab (882:882:882) (895:895:895)) - (PORT datac (567:567:567) (583:583:583)) - (PORT datad (1058:1058:1058) (1064:1064:1064)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (721:721:721)) - (PORT datab (1094:1094:1094) (1103:1103:1103)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (813:813:813) (871:871:871)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (491:491:491)) - (PORT datab (1860:1860:1860) (1955:1955:1955)) - (PORT datac (1054:1054:1054) (1101:1101:1101)) - (PORT datad (244:244:244) (315:315:315)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (861:861:861)) - (PORT datab (385:385:385) (404:404:404)) - (PORT datac (252:252:252) (308:308:308)) - (PORT datad (343:343:343) (357:357:357)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (431:431:431)) - (PORT datab (591:591:591) (610:610:610)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (857:857:857) (859:859:859)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (436:436:436)) - (PORT datab (285:285:285) (345:345:345)) - (PORT datad (856:856:856) (862:862:862)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (835:835:835) (870:870:870)) + (PORT datac (570:570:570) (586:586:586)) + (PORT datad (905:905:905) (965:965:965)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (869:869:869)) + (PORT datad (908:908:908) (970:970:970)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -24238,7 +10749,7 @@ (INSTANCE z80_\|alu_\|op1_high\[3\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT clk (1516:1516:1516) (1520:1520:1520)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -24251,29 +10762,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) (DELAY (ABSOLUTE - (PORT dataa (868:868:868) (926:926:926)) - (PORT datab (716:716:716) (777:777:777)) - (PORT datad (886:886:886) (910:910:910)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (703:703:703)) - (PORT datab (606:606:606) (624:624:624)) - (PORT datac (249:249:249) (307:307:307)) - (PORT datad (554:554:554) (572:572:572)) + (PORT dataa (916:916:916) (945:945:945)) + (PORT datab (1202:1202:1202) (1299:1299:1299)) + (PORT datac (1944:1944:1944) (2011:2011:2011)) + (PORT datad (902:902:902) (939:939:939)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24281,107 +10778,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) (DELAY (ABSOLUTE - (PORT datab (885:885:885) (899:899:899)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (608:608:608)) - (PORT datab (718:718:718) (786:786:786)) - (PORT datac (966:966:966) (1066:1066:1066)) - (PORT datad (995:995:995) (1046:1046:1046)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (723:723:723)) - (PORT datab (618:618:618) (649:649:649)) - (PORT datac (628:628:628) (663:663:663)) - (PORT datad (356:356:356) (387:387:387)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (532:532:532)) - (PORT datab (870:870:870) (896:896:896)) - (PORT datac (519:519:519) (536:536:536)) - (PORT datad (399:399:399) (466:466:466)) + (PORT dataa (1109:1109:1109) (1138:1138:1138)) + (PORT datab (700:700:700) (725:725:725)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (802:802:802) (809:809:809)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (497:497:497)) - (PORT datab (1023:1023:1023) (1072:1072:1072)) - (PORT datac (819:819:819) (866:866:866)) - (PORT datad (625:625:625) (636:636:636)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24389,103 +10794,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) (DELAY (ABSOLUTE - (PORT dataa (375:375:375) (399:399:399)) - (PORT datab (1228:1228:1228) (1318:1318:1318)) - (PORT datac (696:696:696) (757:757:757)) - (PORT datad (886:886:886) (912:912:912)) + (PORT dataa (1651:1651:1651) (1726:1726:1726)) + (PORT datab (1097:1097:1097) (1166:1166:1166)) + (PORT datac (629:629:629) (663:663:663)) + (PORT datad (685:685:685) (750:750:750)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (383:383:383) (414:414:414)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (663:663:663)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (585:585:585) (600:600:600)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (456:456:456)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (328:328:328) (349:349:349)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT datab (646:646:646) (675:675:675)) - (PORT datac (810:810:810) (825:825:825)) - (PORT datad (655:655:655) (668:668:668)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (861:861:861)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (350:350:350) (366:366:366)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (668:668:668) (691:691:691)) - (PORT datac (842:842:842) (879:879:879)) - (PORT datad (931:931:931) (964:964:964)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24493,521 +10810,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (1005:1005:1005)) - (PORT datab (216:216:216) (260:260:260)) - (PORT datac (547:547:547) (557:557:557)) - (PORT datad (1236:1236:1236) (1277:1277:1277)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1342:1342:1342)) - (PORT datab (2282:2282:2282) (2366:2366:2366)) - (PORT datac (1180:1180:1180) (1239:1239:1239)) - (PORT datad (1331:1331:1331) (1363:1363:1363)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (622:622:622)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1252:1252:1252) (1287:1287:1287)) - (PORT datad (952:952:952) (991:991:991)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (556:556:556)) - (PORT datab (854:854:854) (864:864:864)) - (PORT datac (547:547:547) (558:558:558)) - (PORT datad (610:610:610) (649:649:649)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (844:844:844) (872:872:872)) - (PORT datac (829:829:829) (842:842:842)) - (PORT datad (1173:1173:1173) (1229:1229:1229)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1899:1899:1899)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1834:1834:1834) (1965:1965:1965)) - (PORT datad (1601:1601:1601) (1748:1748:1748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1649:1649:1649) (1760:1760:1760)) - (PORT datac (1397:1397:1397) (1433:1433:1433)) - (PORT datad (2275:2275:2275) (2370:2370:2370)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (362:362:362)) - (PORT datab (1863:1863:1863) (1958:1958:1958)) - (PORT datac (1087:1087:1087) (1133:1133:1133)) - (PORT datad (246:246:246) (318:318:318)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (359:359:359)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (952:952:952) (1016:1016:1016)) - (PORT datac (1076:1076:1076) (1122:1122:1122)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1608:1608:1608) (1639:1639:1639)) - (PORT datab (964:964:964) (1002:1002:1002)) - (PORT datac (1030:1030:1030) (1064:1064:1064)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (694:694:694)) - (PORT datab (286:286:286) (344:344:344)) - (PORT datac (201:201:201) (239:239:239)) - (PORT datad (549:549:549) (567:567:567)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (884:884:884) (897:897:897)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (436:436:436) (530:530:530)) - (PORT datab (1590:1590:1590) (1672:1672:1672)) - (PORT datac (858:858:858) (922:922:922)) - (PORT datad (599:599:599) (660:660:660)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT asdata (669:669:669) (691:691:691)) - (PORT ena (1535:1535:1535) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (510:510:510)) - (PORT datab (586:586:586) (606:606:606)) - (PORT datac (850:850:850) (911:911:911)) - (PORT datad (240:240:240) (284:284:284)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (912:912:912)) - (PORT datab (367:367:367) (387:387:387)) - (PORT datad (598:598:598) (630:630:630)) + (PORT dataa (919:919:919) (972:972:972)) + (PORT datab (604:604:604) (618:618:618)) + (PORT datac (1984:1984:1984) (2057:2057:2057)) + (PORT datad (656:656:656) (676:676:676)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (859:859:859)) - (PORT datab (669:669:669) (685:685:685)) - (PORT datac (574:574:574) (583:583:583)) - (PORT datad (342:342:342) (354:354:354)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (991:991:991)) - (PORT datab (1072:1072:1072) (1137:1137:1137)) - (PORT datac (580:580:580) (650:650:650)) - (PORT datad (642:642:642) (673:673:673)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (726:726:726)) - (PORT datab (999:999:999) (1052:1052:1052)) - (PORT datac (627:627:627) (664:664:664)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (723:723:723)) - (PORT datab (665:665:665) (708:708:708)) - (PORT datac (575:575:575) (604:604:604)) - (PORT datad (972:972:972) (1013:1013:1013)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (628:628:628) (662:662:662)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (528:528:528)) - (PORT datab (591:591:591) (625:625:625)) - (PORT datac (435:435:435) (513:513:513)) - (PORT datad (830:830:830) (856:856:856)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (304:304:304)) - (PORT datab (554:554:554) (570:570:570)) - (PORT datac (554:554:554) (586:586:586)) - (PORT datad (1081:1081:1081) (1087:1087:1087)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) (DELAY (ABSOLUTE - (PORT dataa (866:866:866) (892:892:892)) - (PORT datab (1082:1082:1082) (1083:1083:1083)) - (PORT datac (801:801:801) (808:808:808)) - (PORT datad (782:782:782) (795:795:795)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (217:217:217) (261:261:261)) - (PORT datad (831:831:831) (859:859:859)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (217:217:217) (258:258:258)) - (PORT datad (832:832:832) (857:857:857)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1591:1591:1591)) - (PORT datab (1459:1459:1459) (1480:1480:1480)) - (PORT datac (1862:1862:1862) (1880:1880:1880)) - (PORT datad (1327:1327:1327) (1360:1360:1360)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1137:1137:1137)) - (PORT datab (1392:1392:1392) (1450:1450:1450)) - (PORT datac (798:798:798) (814:814:814)) - (PORT datad (1298:1298:1298) (1369:1369:1369)) + (PORT dataa (722:722:722) (771:771:771)) + (PORT datab (1595:1595:1595) (1710:1710:1710)) + (PORT datac (1544:1544:1544) (1685:1685:1685)) + (PORT datad (1542:1542:1542) (1642:1642:1642)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -25017,47 +10842,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) (DELAY (ABSOLUTE - (PORT dataa (1937:1937:1937) (2026:2026:2026)) - (PORT datab (212:212:212) (256:256:256)) - (PORT datac (1953:1953:1953) (2056:2056:2056)) - (PORT datad (1615:1615:1615) (1688:1688:1688)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (854:854:854) (917:917:917)) + (PORT datab (1067:1067:1067) (1089:1089:1089)) + (PORT datac (772:772:772) (784:784:784)) + (PORT datad (822:822:822) (889:889:889)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1152:1152:1152)) - (PORT datab (370:370:370) (396:396:396)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (824:824:824) (863:863:863)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (343:343:343) (381:381:381)) + (PORT datab (601:601:601) (618:618:618)) + (PORT datac (543:543:543) (563:563:563)) + (PORT datad (1344:1344:1344) (1425:1425:1425)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (528:528:528) (540:540:540)) - (PORT datad (580:580:580) (593:593:593)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (1871:1871:1871) (2039:2039:2039)) + (PORT datab (1543:1543:1543) (1671:1671:1671)) + (PORT datac (817:817:817) (835:835:835)) + (PORT datad (1851:1851:1851) (1930:1930:1930)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -25065,45 +10890,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (INSTANCE z80_\|pla_decode_\|Equal21\~2) (DELAY (ABSOLUTE - (PORT datab (1770:1770:1770) (1810:1810:1810)) - (PORT datac (1173:1173:1173) (1220:1220:1220)) - (PORT datad (1440:1440:1440) (1461:1461:1461)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1425:1425:1425) (1503:1503:1503)) + (PORT datac (218:218:218) (262:262:262)) + (PORT datad (986:986:986) (1086:1086:1086)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (340:340:340)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (254:254:254) (313:313:313)) - (PORT datad (1200:1200:1200) (1271:1271:1271)) + (PORT dataa (857:857:857) (897:897:897)) + (PORT datab (966:966:966) (1008:1008:1008)) + (PORT datac (1944:1944:1944) (2015:2015:2015)) + (PORT datad (1176:1176:1176) (1235:1235:1235)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2211:2211:2211) (2401:2401:2401)) - (PORT datab (1578:1578:1578) (1721:1721:1721)) - (PORT datac (1756:1756:1756) (1850:1850:1850)) - (PORT datad (857:857:857) (888:888:888)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -25111,109 +10920,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (1859:1859:1859) (1955:1955:1955)) - (PORT datac (605:605:605) (631:631:631)) - (PORT datad (944:944:944) (992:992:992)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1804:1804:1804) (1902:1902:1902)) - (PORT datab (1429:1429:1429) (1461:1461:1461)) - (PORT datac (1430:1430:1430) (1464:1464:1464)) - (PORT datad (2319:2319:2319) (2472:2472:2472)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1547:1547:1547) (1642:1642:1642)) - (PORT datab (1225:1225:1225) (1267:1267:1267)) - (PORT datac (1428:1428:1428) (1462:1462:1462)) - (PORT datad (1636:1636:1636) (1711:1711:1711)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1464:1464:1464) (1499:1499:1499)) - (PORT datab (684:684:684) (724:724:724)) - (PORT datac (1191:1191:1191) (1233:1233:1233)) - (PORT datad (1662:1662:1662) (1693:1693:1693)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (671:671:671)) - (PORT datab (2007:2007:2007) (2122:2122:2122)) - (PORT datac (1547:1547:1547) (1649:1649:1649)) - (PORT datad (2319:2319:2319) (2472:2472:2472)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1643:1643:1643)) - (PORT datab (680:680:680) (721:721:721)) - (PORT datac (1534:1534:1534) (1622:1622:1622)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (681:681:681) (728:728:728)) - (PORT datac (2002:2002:2002) (2034:2034:2034)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1128:1128:1128) (1164:1164:1164)) + (PORT datab (923:923:923) (985:985:985)) + (PORT datac (380:380:380) (415:415:415)) + (PORT datad (613:613:613) (634:634:634)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -25223,3413 +10936,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_alu_op_low) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (378:378:378)) - (PORT datab (375:375:375) (401:401:401)) - (PORT datac (317:317:317) (348:348:348)) - (PORT datad (875:875:875) (912:912:912)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (698:698:698)) - (PORT datab (643:643:643) (669:669:669)) - (PORT datac (1186:1186:1186) (1232:1232:1232)) - (PORT datad (366:366:366) (388:388:388)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (986:986:986)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (1404:1404:1404) (1439:1439:1439)) - (PORT datad (619:619:619) (649:649:649)) + (PORT dataa (661:661:661) (702:702:702)) + (PORT datab (893:893:893) (935:935:935)) + (PORT datac (1566:1566:1566) (1576:1576:1576)) + (PORT datad (179:179:179) (209:209:209)) (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (704:704:704)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1184:1184:1184) (1224:1224:1224)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (680:680:680)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (581:581:581) (598:598:598)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1590:1590:1590)) - (PORT datab (1459:1459:1459) (1480:1480:1480)) - (PORT datac (1045:1045:1045) (1092:1092:1092)) - (PORT datad (1326:1326:1326) (1360:1360:1360)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (927:927:927) (983:983:983)) - (PORT datac (900:900:900) (967:967:967)) - (PORT datad (2255:2255:2255) (2330:2330:2330)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1389:1389:1389)) - (PORT datab (1282:1282:1282) (1317:1317:1317)) - (PORT datac (903:903:903) (968:968:968)) - (PORT datad (1147:1147:1147) (1224:1224:1224)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1478:1478:1478)) - (PORT datab (991:991:991) (1033:1033:1033)) - (PORT datac (382:382:382) (406:406:406)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (399:399:399)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (523:523:523) (528:528:528)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (896:896:896)) - (PORT datab (650:650:650) (675:675:675)) - (PORT datac (342:342:342) (365:365:365)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (882:882:882)) - (PORT datab (639:639:639) (683:683:683)) - (PORT datac (811:811:811) (813:813:813)) - (PORT datad (1234:1234:1234) (1284:1284:1284)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (704:704:704)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (554:554:554) (564:564:564)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (584:584:584) (600:600:600)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (549:549:549)) - (PORT datab (1591:1591:1591) (1671:1671:1671)) - (PORT datac (998:998:998) (1082:1082:1082)) - (PORT datad (844:844:844) (897:897:897)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (726:726:726) (802:802:802)) - (PORT datac (204:204:204) (242:242:242)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (712:712:712)) - (PORT datab (1350:1350:1350) (1417:1417:1417)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (674:674:674)) - (PORT datab (413:413:413) (463:463:463)) - (PORT datac (854:854:854) (913:913:913)) - (PORT datad (244:244:244) (285:285:285)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (878:878:878)) - (PORT datab (1313:1313:1313) (1370:1370:1370)) - (PORT datac (768:768:768) (840:840:840)) - (PORT datad (753:753:753) (788:788:788)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (915:915:915)) - (PORT datab (354:354:354) (384:384:384)) - (PORT datac (570:570:570) (580:580:580)) - (PORT datad (640:640:640) (657:657:657)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (692:692:692)) - (PORT datab (288:288:288) (346:346:346)) - (PORT datad (853:853:853) (857:857:857)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (1027:1027:1027) (1080:1080:1080)) - (PORT datac (998:998:998) (1082:1082:1082)) - (PORT datad (598:598:598) (658:658:658)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (524:524:524)) - (PORT datab (593:593:593) (621:621:621)) - (PORT datac (435:435:435) (509:509:509)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (867:867:867) (892:892:892)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (587:587:587) (604:604:604)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (302:302:302)) - (PORT datab (256:256:256) (302:302:302)) - (PORT datac (525:525:525) (539:539:539)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (455:455:455)) - (PORT datab (394:394:394) (418:418:418)) - (PORT datac (381:381:381) (403:403:403)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (407:407:407)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (587:587:587) (602:602:602)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (612:612:612) (629:629:629)) - (PORT datac (184:184:184) (224:224:224)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT asdata (558:558:558) (589:589:589)) - (PORT ena (1535:1535:1535) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (379:379:379) (448:448:448)) - (PORT datad (845:845:845) (867:867:867)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (961:961:961)) - (PORT datab (715:715:715) (786:786:786)) - (PORT datac (1555:1555:1555) (1630:1630:1630)) - (PORT datad (399:399:399) (466:466:466)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (500:500:500)) - (PORT datad (602:602:602) (625:625:625)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (836:836:836)) - (PORT datab (1100:1100:1100) (1140:1140:1140)) - (PORT datac (379:379:379) (412:412:412)) - (PORT datad (895:895:895) (920:920:920)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (808:808:808)) - (PORT datab (676:676:676) (693:693:693)) - (PORT datac (345:345:345) (369:369:369)) - (PORT datad (327:327:327) (345:345:345)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1118:1118:1118)) - (PORT datab (884:884:884) (901:901:901)) - (PORT datac (1027:1027:1027) (1078:1078:1078)) - (PORT datad (981:981:981) (1014:1014:1014)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (683:683:683)) - (PORT datab (1094:1094:1094) (1101:1101:1101)) - (PORT datac (530:530:530) (542:542:542)) - (PORT datad (658:658:658) (677:677:677)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (662:662:662)) - (PORT datab (676:676:676) (735:735:735)) - (PORT datac (1314:1314:1314) (1328:1328:1328)) - (PORT datad (1142:1142:1142) (1172:1172:1172)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1027:1027:1027) (1032:1032:1032)) - (PORT datab (1108:1108:1108) (1163:1163:1163)) - (PORT datad (1085:1085:1085) (1076:1076:1076)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (384:384:384) (458:458:458)) - (PORT datac (379:379:379) (440:440:440)) - (PORT datad (386:386:386) (446:446:446)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1041:1041:1041)) - (PORT datab (2280:2280:2280) (2375:2375:2375)) - (PORT datad (2190:2190:2190) (2361:2361:2361)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (605:605:605) (655:655:655)) - (PORT datac (802:802:802) (820:820:820)) - (PORT datad (1419:1419:1419) (1423:1423:1423)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1395:1395:1395) (1451:1451:1451)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1286:1286:1286)) - (PORT datab (947:947:947) (992:992:992)) - (PORT datac (1206:1206:1206) (1235:1235:1235)) - (PORT datad (1186:1186:1186) (1199:1199:1199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (346:346:346)) - (PORT datab (1765:1765:1765) (1806:1806:1806)) - (PORT datac (247:247:247) (305:305:305)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (671:671:671)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1094:1094:1094) (1107:1107:1107)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (885:885:885)) - (PORT datab (910:910:910) (959:959:959)) - (PORT datac (827:827:827) (862:862:862)) - (PORT datad (816:816:816) (839:839:839)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (906:906:906)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (630:630:630) (665:665:665)) - (PORT datad (625:625:625) (641:641:641)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (864:864:864)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (885:885:885) (913:913:913)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (328:328:328)) - (PORT datab (1135:1135:1135) (1215:1215:1215)) - (PORT datad (1221:1221:1221) (1258:1258:1258)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (547:547:547) (582:582:582)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (923:923:923) (953:953:953)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (847:847:847)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1256:1256:1256)) - (PORT datab (682:682:682) (747:747:747)) - (PORT datad (875:875:875) (945:945:945)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (625:625:625) (679:679:679)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (547:547:547) (582:582:582)) - (PORT ena (1275:1275:1275) (1314:1314:1314)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (787:787:787)) - (PORT datab (729:729:729) (781:781:781)) - (PORT datad (1021:1021:1021) (1061:1061:1061)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (680:680:680)) - (PORT datab (611:611:611) (638:638:638)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (412:412:412)) - (PORT datab (612:612:612) (639:639:639)) - (PORT datac (309:309:309) (325:325:325)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (262:262:262)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (816:816:816) (831:831:831)) - (PORT datad (1118:1118:1118) (1134:1134:1134)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1241:1241:1241) (1251:1251:1251)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1126:1126:1126)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (1117:1117:1117) (1141:1141:1141)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (624:624:624) (639:639:639)) - (PORT datac (666:666:666) (695:695:695)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (450:450:450)) - (PORT datab (626:626:626) (654:654:654)) - (PORT datac (1197:1197:1197) (1250:1250:1250)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1140:1140:1140)) - (PORT datad (880:880:880) (895:895:895)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1362:1362:1362)) - (PORT datad (370:370:370) (394:394:394)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT asdata (934:934:934) (951:951:951)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (PORT ena (2020:2020:2020) (2056:2056:2056)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (673:673:673)) - (PORT datab (614:614:614) (636:636:636)) - (PORT datac (590:590:590) (657:657:657)) - (PORT datad (665:665:665) (729:729:729)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (617:617:617) (639:639:639)) - (PORT datac (613:613:613) (666:666:666)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (950:950:950) (978:978:978)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (950:950:950) (976:976:976)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (316:316:316)) - (PORT datab (1080:1080:1080) (1115:1115:1115)) - (PORT datad (355:355:355) (415:415:415)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1773:1773:1773) (1846:1846:1846)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1773:1773:1773) (1845:1845:1845)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (244:244:244) (292:292:292)) - (PORT datad (211:211:211) (244:244:244)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1770:1770:1770) (1824:1824:1824)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1253:1253:1253)) - (PORT datab (675:675:675) (717:717:717)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1772:1772:1772) (1824:1824:1824)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (456:456:456)) - (PORT datab (195:195:195) (234:234:234)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1111:1111:1111) (1133:1133:1133)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (327:327:327)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (1377:1377:1377) (1480:1480:1480)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (953:953:953) (981:981:981)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (953:953:953) (981:981:981)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (661:661:661)) - (PORT datab (942:942:942) (999:999:999)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (849:849:849)) - (PORT datab (643:643:643) (660:660:660)) - (PORT datac (593:593:593) (636:636:636)) - (PORT datad (620:620:620) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1238:1238:1238)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1221:1221:1221) (1239:1239:1239)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (459:459:459)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (417:417:417) (449:449:449)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (699:699:699)) - (PORT datab (864:864:864) (869:869:869)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (896:896:896)) - (PORT datab (400:400:400) (430:430:430)) - (PORT datac (1133:1133:1133) (1187:1187:1187)) - (PORT datad (666:666:666) (703:703:703)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1521:1521:1521)) - (PORT datab (675:675:675) (709:709:709)) - (PORT datad (326:326:326) (344:344:344)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (635:635:635)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (606:606:606) (629:629:629)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (894:894:894)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1210:1210:1210) (1264:1264:1264)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1140:1140:1140)) - (PORT datad (625:625:625) (641:641:641)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1181:1181:1181)) - (PORT datab (1473:1473:1473) (1524:1524:1524)) - (PORT datac (1184:1184:1184) (1245:1245:1245)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (623:623:623)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (624:624:624) (671:671:671)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1466:1466:1466) (1490:1490:1490)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1462:1462:1462) (1486:1486:1486)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (308:308:308)) - (PORT datab (1080:1080:1080) (1120:1120:1120)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1250:1250:1250)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1249:1249:1249)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (463:463:463)) - (PORT datab (449:449:449) (477:477:477)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1192:1192:1192) (1211:1211:1211)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1274:1274:1274) (1361:1361:1361)) - (PORT datab (1009:1009:1009) (1055:1055:1055)) - (PORT datad (895:895:895) (946:946:946)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1870:1870:1870) (1916:1916:1916)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (322:322:322)) - (PORT datab (1137:1137:1137) (1215:1215:1215)) - (PORT datad (855:855:855) (880:880:880)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (970:970:970) (997:997:997)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (958:958:958) (996:996:996)) - (PORT ena (1275:1275:1275) (1314:1314:1314)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1226:1226:1226)) - (PORT datab (725:725:725) (775:775:775)) - (PORT datad (1020:1020:1020) (1061:1061:1061)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (958:958:958) (999:999:999)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1252:1252:1252)) - (PORT datab (676:676:676) (740:740:740)) - (PORT datad (656:656:656) (714:714:714)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (692:692:692)) - (PORT datab (643:643:643) (692:692:692)) - (PORT datac (572:572:572) (583:583:583)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1247:1247:1247) (1278:1278:1278)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (640:640:640) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (660:660:660)) - (PORT datab (942:942:942) (998:998:998)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (649:649:649)) - (PORT datab (327:327:327) (355:355:355)) - (PORT datac (341:341:341) (363:363:363)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (685:685:685)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datac (1136:1136:1136) (1185:1185:1185)) - (PORT datad (522:522:522) (540:540:540)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (848:848:848) (860:860:860)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1518:1518:1518)) - (PORT datab (384:384:384) (417:417:417)) - (PORT datad (643:643:643) (665:665:665)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (734:734:734)) - (PORT datab (332:332:332) (360:360:360)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (874:874:874)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1197:1197:1197) (1251:1251:1251)) - (PORT datad (383:383:383) (403:403:403)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datab (802:802:802) (828:828:828)) - (PORT datad (1064:1064:1064) (1089:1089:1089)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (876:876:876) (905:905:905)) - (PORT datac (623:623:623) (669:669:669)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (579:579:579) (585:585:585)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1247:1247:1247)) - (PORT datab (907:907:907) (936:936:936)) - (PORT datac (385:385:385) (451:451:451)) - (PORT datad (914:914:914) (972:972:972)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (894:894:894) (915:915:915)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (694:694:694)) - (PORT datab (622:622:622) (668:668:668)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (608:608:608) (648:648:648)) - (PORT datad (418:418:418) (490:490:490)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (406:406:406)) - (PORT datab (403:403:403) (433:433:433)) - (PORT datac (434:434:434) (479:479:479)) - (PORT datad (1502:1502:1502) (1569:1569:1569)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (656:656:656)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (550:550:550) (571:571:571)) - (PORT datad (1321:1321:1321) (1374:1374:1374)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (909:909:909)) - (PORT datab (873:873:873) (928:928:928)) - (PORT datac (632:632:632) (677:677:677)) - (PORT datad (805:805:805) (833:833:833)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1808:1808:1808) (1853:1853:1853)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (572:572:572) (589:589:589)) - (PORT datad (220:220:220) (259:259:259)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (912:912:912)) - (PORT datad (809:809:809) (836:836:836)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (1225:1225:1225) (1265:1265:1265)) - (PORT datac (878:878:878) (918:918:918)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (900:900:900)) - (PORT datab (1164:1164:1164) (1207:1207:1207)) - (PORT datac (1156:1156:1156) (1177:1177:1177)) - (PORT datad (612:612:612) (661:661:661)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1256:1256:1256)) - (PORT datab (676:676:676) (714:714:714)) - (PORT datad (1092:1092:1092) (1117:1117:1117)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT asdata (1354:1354:1354) (1395:1395:1395)) - (PORT ena (1263:1263:1263) (1252:1252:1252)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1381:1381:1381)) - (PORT datab (920:920:920) (933:933:933)) - (PORT datad (1369:1369:1369) (1414:1414:1414)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1193:1193:1193) (1215:1215:1215)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1187:1187:1187) (1217:1217:1217)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1189:1189:1189) (1217:1217:1217)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (464:464:464)) - (PORT datab (450:450:450) (488:488:488)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (832:832:832)) - (PORT datab (631:631:631) (666:666:666)) - (PORT datad (614:614:614) (639:639:639)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (992:992:992) (1028:1028:1028)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (990:990:990) (1027:1027:1027)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (459:459:459)) - (PORT datab (245:245:245) (293:293:293)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1181:1181:1181) (1196:1196:1196)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1178:1178:1178) (1193:1193:1193)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (330:330:330)) - (PORT datab (1409:1409:1409) (1523:1523:1523)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (605:605:605) (642:642:642)) - (PORT datac (377:377:377) (418:418:418)) - (PORT datad (312:312:312) (331:331:331)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (676:676:676)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (522:522:522) (536:536:536)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1068:1068:1068)) - (PORT datab (1183:1183:1183) (1199:1199:1199)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (660:660:660) (693:693:693)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1154:1154:1154) (1163:1163:1163)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1517:1517:1517)) - (PORT datab (1185:1185:1185) (1225:1225:1225)) - (PORT datad (651:651:651) (673:673:673)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (370:370:370)) - (PORT datac (665:665:665) (694:694:694)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (444:444:444)) - (PORT datab (220:220:220) (257:257:257)) - (PORT datac (1193:1193:1193) (1246:1246:1246)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (880:880:880) (936:936:936)) - (PORT datad (786:786:786) (788:788:788)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1451:1451:1451) (1493:1493:1493)) - (PORT datab (1095:1095:1095) (1151:1151:1151)) - (PORT datac (670:670:670) (690:690:690)) - (PORT datad (1103:1103:1103) (1138:1138:1138)) - (IOPATH dataa combout (350:350:350) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (746:746:746)) - (PORT datab (1400:1400:1400) (1451:1451:1451)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (1354:1354:1354) (1397:1397:1397)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1457:1457:1457) (1516:1516:1516)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1460:1460:1460) (1519:1519:1519)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (462:462:462)) - (PORT datab (449:449:449) (476:476:476)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (989:989:989) (1030:1030:1030)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1378:1378:1378) (1437:1437:1437)) - (PORT ena (841:841:841) (847:847:847)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1254:1254:1254)) - (PORT datab (678:678:678) (743:743:743)) - (PORT datad (876:876:876) (941:941:941)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1476:1476:1476) (1497:1497:1497)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1423:1423:1423) (1461:1461:1461)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (768:768:768)) - (PORT datab (677:677:677) (714:714:714)) - (PORT datad (632:632:632) (658:658:658)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1422:1422:1422) (1461:1461:1461)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (461:461:461)) - (PORT datab (195:195:195) (234:234:234)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (911:911:911) (922:922:922)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (965:965:965)) - (PORT datab (1338:1338:1338) (1383:1383:1383)) - (PORT datac (840:840:840) (853:853:853)) - (PORT datad (840:840:840) (891:891:891)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (375:375:375)) - (PORT datab (619:619:619) (654:654:654)) - (PORT datad (319:319:319) (337:337:337)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (931:931:931) (962:962:962)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (587:587:587) (620:620:620)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (318:318:318)) - (PORT datab (1080:1080:1080) (1113:1113:1113)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1247:1247:1247)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (641:641:641) (675:675:675)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (940:940:940) (1003:1003:1003)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (525:525:525) (543:543:543)) - (PORT datab (371:371:371) (391:391:391)) - (PORT datac (833:833:833) (839:839:839)) - (PORT datad (313:313:313) (322:322:322)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (843:843:843)) - (PORT datab (573:573:573) (588:588:588)) - (PORT datac (1136:1136:1136) (1189:1189:1189)) - (PORT datad (665:665:665) (698:698:698)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (850:850:850) (858:858:858)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1517:1517:1517)) - (PORT datab (384:384:384) (414:414:414)) - (PORT datad (644:644:644) (664:664:664)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (735:735:735)) - (PORT datac (217:217:217) (294:294:294)) - (PORT datad (334:334:334) (353:353:353)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (446:446:446)) - (PORT datab (1227:1227:1227) (1282:1282:1282)) - (PORT datac (178:178:178) (215:215:215)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1359:1359:1359)) - (PORT datad (533:533:533) (544:544:544)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (565:565:565) (575:575:575)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (745:745:745)) - (PORT datab (1138:1138:1138) (1179:1179:1179)) - (PORT datac (669:669:669) (689:689:689)) - (PORT datad (1408:1408:1408) (1445:1445:1445)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (1399:1399:1399) (1450:1450:1450)) - (PORT datac (1371:1371:1371) (1414:1414:1414)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (678:678:678)) - (PORT datab (615:615:615) (637:637:637)) - (PORT datac (592:592:592) (659:659:659)) - (PORT datad (667:667:667) (730:730:730)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1239:1239:1239) (1295:1295:1295)) - (PORT datac (880:880:880) (914:914:914)) - (PORT datad (215:215:215) (249:249:249)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (368:368:368)) - (PORT datab (707:707:707) (740:740:740)) - (PORT datac (1132:1132:1132) (1184:1184:1184)) - (PORT datad (367:367:367) (391:391:391)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (630:630:630)) - (PORT datab (412:412:412) (440:440:440)) - (PORT datac (542:542:542) (555:555:555)) - (PORT datad (611:611:611) (637:637:637)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (1115:1115:1115) (1142:1142:1142)) - (PORT datac (844:844:844) (866:866:866)) - (PORT datad (341:341:341) (362:362:362)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (300:300:300)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (572:572:572) (590:590:590)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (744:744:744) (833:833:833)) - (PORT datac (206:206:206) (244:244:244)) - (PORT datad (220:220:220) (248:248:248)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (945:945:945)) - (PORT datab (674:674:674) (710:710:710)) - (PORT datac (1356:1356:1356) (1400:1400:1400)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT asdata (889:889:889) (895:895:895)) - (PORT ena (1615:1615:1615) (1626:1626:1626)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (979:979:979)) - (PORT datab (1586:1586:1586) (1671:1671:1671)) - (PORT datac (857:857:857) (920:920:920)) - (PORT datad (419:419:419) (492:492:492)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (873:873:873)) - (PORT datab (262:262:262) (317:317:317)) - (PORT datac (849:849:849) (911:911:911)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (874:874:874)) - (PORT datab (880:880:880) (945:945:945)) - (PORT datad (741:741:741) (783:783:783)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (1309:1309:1309) (1365:1365:1365)) - (PORT datac (209:209:209) (249:249:249)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28640,13 +10955,13 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) (DELAY (ABSOLUTE - (PORT dataa (924:924:924) (999:999:999)) - (PORT datab (1075:1075:1075) (1142:1142:1142)) - (PORT datac (885:885:885) (962:962:962)) - (PORT datad (648:648:648) (680:680:680)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (957:957:957) (1021:1021:1021)) + (PORT datab (1200:1200:1200) (1249:1249:1249)) + (PORT datac (877:877:877) (942:942:942)) + (PORT datad (1050:1050:1050) (1128:1128:1128)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28656,13 +10971,27 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) (DELAY (ABSOLUTE - (PORT dataa (673:673:673) (726:726:726)) - (PORT datab (844:844:844) (863:863:863)) - (PORT datac (626:626:626) (661:661:661)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1071:1071:1071) (1104:1104:1104)) + (PORT datab (857:857:857) (876:876:876)) + (PORT datac (613:613:613) (644:644:644)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT datab (1203:1203:1203) (1256:1256:1256)) + (PORT datac (1140:1140:1140) (1175:1175:1175)) + (PORT datad (823:823:823) (838:838:838)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28672,9 +11001,9 @@ (INSTANCE z80_\|alu_\|op2_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT clk (1517:1517:1517) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -28685,119 +11014,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (INSTANCE z80_\|alu_\|db_low\[3\]\~2) (DELAY (ABSOLUTE - (PORT dataa (668:668:668) (724:724:724)) - (PORT datab (849:849:849) (909:909:909)) - (PORT datac (819:819:819) (834:834:834)) - (PORT datad (635:635:635) (671:671:671)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (665:665:665)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (536:536:536)) - (PORT datab (592:592:592) (622:622:622)) - (PORT datac (651:651:651) (713:713:713)) - (PORT datad (832:832:832) (855:855:855)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (387:387:387)) - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (180:180:180) (209:209:209)) + (PORT dataa (1375:1375:1375) (1489:1489:1489)) + (PORT datab (1718:1718:1718) (1749:1749:1749)) + (PORT datac (359:359:359) (424:424:424)) + (PORT datad (679:679:679) (728:728:728)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (390:390:390)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (344:344:344) (373:373:373)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (719:719:719)) - (PORT datab (857:857:857) (902:902:902)) - (PORT datac (2037:2037:2037) (2075:2075:2075)) - (PORT datad (827:827:827) (920:920:920)) - (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (953:953:953) (1017:1017:1017)) - (PORT datac (663:663:663) (701:701:701)) - (PORT datad (629:629:629) (658:658:658)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28805,544 +11030,119 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (INSTANCE z80_\|alu_\|db_low\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1608:1608:1608) (1638:1638:1638)) - (PORT datab (724:724:724) (761:761:761)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (970:970:970) (1003:1003:1003)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (514:514:514)) - (PORT datab (266:266:266) (322:322:322)) - (PORT datad (605:605:605) (629:629:629)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (647:647:647)) - (PORT datab (587:587:587) (595:595:595)) - (PORT datac (850:850:850) (906:906:906)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (925:925:925) (946:946:946)) + (PORT datab (634:634:634) (654:654:654)) + (PORT datac (1297:1297:1297) (1364:1364:1364)) + (PORT datad (884:884:884) (899:899:899)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) (DELAY (ABSOLUTE - (PORT dataa (577:577:577) (594:594:594)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1677:1677:1677) (1734:1734:1734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (965:965:965)) + (PORT datac (806:806:806) (841:841:841)) + (PORT datad (374:374:374) (429:429:429)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2224:2224:2224) (2316:2316:2316)) (PORT datab (227:227:227) (269:269:269)) - (PORT datac (843:843:843) (914:914:914)) - (PORT datad (777:777:777) (827:827:827)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (729:729:729)) - (PORT datab (1152:1152:1152) (1160:1160:1160)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (538:538:538) (551:551:551)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1889:1889:1889)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (885:885:885) (932:932:932)) - (PORT datad (330:330:330) (354:354:354)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1134:1134:1134)) - (PORT datab (1396:1396:1396) (1456:1456:1456)) - (PORT datac (796:796:796) (811:811:811)) - (PORT datad (563:563:563) (577:577:577)) + (PORT datac (918:918:918) (934:934:934)) + (PORT datad (186:186:186) (218:218:218)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (823:823:823)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (1051:1051:1051) (1079:1079:1079)) - (PORT datad (1041:1041:1041) (1076:1076:1076)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (268:268:268)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (601:601:601) (617:617:617)) - (PORT datad (589:589:589) (602:602:602)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (990:990:990)) - (PORT datab (932:932:932) (968:968:968)) - (PORT datac (1207:1207:1207) (1265:1265:1265)) - (PORT datad (620:620:620) (652:652:652)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (859:859:859) (877:877:877)) - (PORT datad (619:619:619) (659:659:659)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (1534:1534:1534) (1581:1581:1581)) - (PORT datac (1206:1206:1206) (1250:1250:1250)) - (PORT datad (685:685:685) (739:739:739)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) - (DELAY - (ABSOLUTE - (PORT datac (186:186:186) (225:225:225)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (827:827:827)) - (PORT datab (362:362:362) (398:398:398)) - (PORT datac (521:521:521) (537:537:537)) - (PORT datad (812:812:812) (823:823:823)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (663:663:663)) - (PORT datab (666:666:666) (681:681:681)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (640:640:640)) - (PORT datab (1418:1418:1418) (1463:1463:1463)) - (PORT datac (1454:1454:1454) (1487:1487:1487)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1281:1281:1281)) - (PORT datab (1419:1419:1419) (1462:1462:1462)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (831:831:831) (848:848:848)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1013:1013:1013)) - (PORT datab (1181:1181:1181) (1227:1227:1227)) - (PORT datac (632:632:632) (648:648:648)) - (PORT datad (1362:1362:1362) (1411:1411:1411)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (848:848:848)) - (PORT datab (1395:1395:1395) (1453:1453:1453)) - (PORT datac (1074:1074:1074) (1096:1096:1096)) - (PORT datad (1683:1683:1683) (1743:1743:1743)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1811:1811:1811) (1879:1879:1879)) - (PORT datab (676:676:676) (715:715:715)) - (PORT datac (1045:1045:1045) (1109:1109:1109)) - (PORT datad (333:333:333) (359:359:359)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (875:875:875)) - (PORT datab (631:631:631) (658:658:658)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (617:617:617) (665:665:665)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (570:570:570)) - (PORT datab (641:641:641) (662:662:662)) - (PORT datac (570:570:570) (588:588:588)) - (PORT datad (321:321:321) (344:344:344)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (946:946:946)) - (PORT datab (1101:1101:1101) (1148:1148:1148)) - (PORT datac (813:813:813) (870:870:870)) - (PORT datad (589:589:589) (601:601:601)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (943:943:943)) - (PORT datab (440:440:440) (502:502:502)) - (PORT datac (322:322:322) (346:346:346)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT datab (956:956:956) (1019:1019:1019)) - (PORT datac (686:686:686) (722:722:722)) - (PORT datad (935:935:935) (962:962:962)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (710:710:710)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (616:616:616) (639:639:639)) - (PORT datad (1569:1569:1569) (1593:1593:1593)) - (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (879:879:879)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (222:222:222) (303:303:303)) - (PORT datad (174:174:174) (199:199:199)) + (PORT datac (1209:1209:1209) (1285:1285:1285)) + (PORT datad (2183:2183:2183) (2383:2383:2383)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1395:1395:1395)) + (PORT datab (971:971:971) (1027:1027:1027)) + (PORT datac (983:983:983) (1037:1037:1037)) + (PORT datad (1203:1203:1203) (1284:1284:1284)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1379:1379:1379)) + (PORT datab (1102:1102:1102) (1129:1129:1129)) + (PORT datad (991:991:991) (1084:1084:1084)) (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (880:880:880)) - (PORT datab (350:350:350) (384:384:384)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1571:1571:1571) (1597:1597:1597)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1404:1404:1404) (1572:1572:1572)) - (PORT datab (2576:2576:2576) (2768:2768:2768)) - (PORT datac (1211:1211:1211) (1292:1292:1292)) - (PORT datad (1321:1321:1321) (1487:1487:1487)) + (PORT dataa (1306:1306:1306) (1445:1445:1445)) + (PORT datab (908:908:908) (952:952:952)) + (PORT datac (936:936:936) (1031:1031:1031)) + (PORT datad (1386:1386:1386) (1511:1511:1511)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (436:436:436)) - (PORT datab (642:642:642) (698:698:698)) - (PORT datac (1721:1721:1721) (1770:1770:1770)) - (PORT datad (842:842:842) (847:847:847)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (688:688:688)) - (PORT datab (673:673:673) (705:705:705)) - (PORT datad (1121:1121:1121) (1149:1149:1149)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1852:1852:1852) (1960:1960:1960)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (811:811:811) (834:834:834)) - (PORT datad (1186:1186:1186) (1218:1218:1218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1152:1152:1152)) - (PORT datab (850:850:850) (888:888:888)) - (PORT datac (1161:1161:1161) (1194:1194:1194)) - (PORT datad (1113:1113:1113) (1135:1135:1135)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29350,31 +11150,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (250:250:250) (340:340:340)) - (PORT datab (260:260:260) (342:342:342)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (853:853:853) (853:853:853)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1071:1071:1071)) - (PORT datab (877:877:877) (903:903:903)) - (PORT datac (1043:1043:1043) (1136:1136:1136)) - (PORT datad (1269:1269:1269) (1356:1356:1356)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (852:852:852) (893:893:893)) + (PORT datac (930:930:930) (980:980:980)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29382,185 +11164,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (283:283:283)) - (PORT datab (1397:1397:1397) (1493:1493:1493)) - (PORT datac (1951:1951:1951) (2029:2029:2029)) - (PORT datad (909:909:909) (935:935:935)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (994:994:994) (1065:1065:1065)) - (PORT datac (1181:1181:1181) (1238:1238:1238)) - (PORT datad (1433:1433:1433) (1519:1519:1519)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1166:1166:1166)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (638:638:638) (669:669:669)) - (PORT datad (883:883:883) (915:915:915)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (689:689:689)) - (PORT datab (1238:1238:1238) (1272:1272:1272)) - (PORT datac (185:185:185) (224:224:224)) - (PORT datad (633:633:633) (665:665:665)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (665:665:665)) - (PORT datab (628:628:628) (640:640:640)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (320:320:320) (341:341:341)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT datac (962:962:962) (1026:1026:1026)) - (PORT datad (841:841:841) (860:860:860)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (629:629:629) (639:639:639)) - (PORT datac (207:207:207) (246:246:246)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (941:941:941)) - (PORT datab (1982:1982:1982) (2090:2090:2090)) - (PORT datac (1348:1348:1348) (1372:1372:1372)) - (PORT datad (2100:2100:2100) (2296:2296:2296)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (906:906:906)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (217:217:217) (260:260:260)) - (PORT datad (196:196:196) (229:229:229)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (914:914:914)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1205:1205:1205) (1266:1266:1266)) - (PORT datad (904:904:904) (932:932:932)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (1175:1175:1175) (1240:1240:1240)) - (PORT datad (184:184:184) (215:215:215)) + (PORT dataa (1772:1772:1772) (1857:1857:1857)) + (PORT datab (1757:1757:1757) (1827:1827:1827)) + (PORT datac (2074:2074:2074) (2182:2182:2182)) + (PORT datad (968:968:968) (1013:1013:1013)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1307:1307:1307)) - (PORT datab (684:684:684) (724:724:724)) - (PORT datac (794:794:794) (837:837:837)) - (PORT datad (1662:1662:1662) (1693:1693:1693)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29568,29 +11180,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) (DELAY (ABSOLUTE - (PORT dataa (590:590:590) (607:607:607)) - (PORT datab (815:815:815) (829:829:829)) - (PORT datac (585:585:585) (610:610:610)) - (PORT datad (651:651:651) (668:668:668)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (673:673:673) (690:690:690)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (619:619:619) (643:643:643)) + (PORT dataa (1458:1458:1458) (1568:1568:1568)) + (PORT datab (933:933:933) (956:956:956)) + (PORT datac (803:803:803) (825:825:825)) + (PORT datad (1218:1218:1218) (1300:1300:1300)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -29600,77 +11196,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~24) (DELAY (ABSOLUTE - (PORT dataa (1355:1355:1355) (1407:1407:1407)) - (PORT datab (927:927:927) (984:984:984)) - (PORT datac (1048:1048:1048) (1096:1096:1096)) - (PORT datad (1421:1421:1421) (1444:1444:1444)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (847:847:847) (877:877:877)) + (PORT datab (863:863:863) (911:911:911)) + (PORT datac (1684:1684:1684) (1755:1755:1755)) + (PORT datad (1780:1780:1780) (1866:1866:1866)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (INSTANCE z80_\|execute_\|fMRead\~8) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (401:401:401)) - (PORT datab (629:629:629) (655:655:655)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (834:834:834) (861:861:861)) + (PORT datab (698:698:698) (764:764:764)) + (PORT datac (1434:1434:1434) (1463:1463:1463)) + (PORT datad (796:796:796) (846:846:846)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (730:730:730)) - (PORT datab (988:988:988) (1020:1020:1020)) - (PORT datac (2018:2018:2018) (2126:2126:2126)) - (PORT datad (326:326:326) (345:345:345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (826:826:826)) - (PORT datac (215:215:215) (257:257:257)) - (PORT datad (831:831:831) (857:857:857)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (345:345:345) (376:376:376)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (613:613:613) (625:625:625)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29678,15 +11228,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~7) (DELAY (ABSOLUTE - (PORT dataa (621:621:621) (648:648:648)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (575:575:575) (577:577:577)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (1198:1198:1198) (1238:1238:1238)) + (PORT datab (882:882:882) (939:939:939)) + (PORT datac (903:903:903) (952:952:952)) + (PORT datad (1164:1164:1164) (1199:1199:1199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1265:1265:1265)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (780:780:780) (854:854:854)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29694,13 +11260,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1153:1153:1153)) - (PORT datab (1198:1198:1198) (1239:1239:1239)) - (PORT datac (1173:1173:1173) (1228:1228:1228)) - (PORT datad (1368:1368:1368) (1397:1397:1397)) + (PORT dataa (714:714:714) (763:763:763)) + (PORT datab (714:714:714) (790:790:790)) + (PORT datac (1915:1915:1915) (1978:1978:1978)) + (PORT datad (1060:1060:1060) (1128:1128:1128)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -29710,433 +11276,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M4T2_3) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1151:1151:1151)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (528:528:528) (546:546:546)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT datab (847:847:847) (854:854:854)) - (PORT datac (1082:1082:1082) (1133:1133:1133)) - (PORT datad (828:828:828) (834:834:834)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (829:829:829)) - (PORT datab (897:897:897) (933:933:933)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (965:965:965)) - (PORT datab (912:912:912) (924:924:924)) - (PORT datac (1409:1409:1409) (1449:1449:1449)) - (PORT datad (873:873:873) (900:900:900)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1258:1258:1258)) - (PORT datab (887:887:887) (920:920:920)) - (PORT datac (1132:1132:1132) (1158:1158:1158)) - (PORT datad (950:950:950) (979:979:979)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1284:1284:1284)) - (PORT datab (1418:1418:1418) (1466:1466:1466)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (532:532:532) (548:548:548)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (702:702:702)) - (PORT datab (652:652:652) (733:733:733)) - (PORT datac (1060:1060:1060) (1092:1092:1092)) - (PORT datad (543:543:543) (547:547:547)) + (PORT dataa (1080:1080:1080) (1128:1128:1128)) + (PORT datab (1508:1508:1508) (1603:1603:1603)) + (PORT datac (1513:1513:1513) (1591:1591:1591)) + (PORT datad (578:578:578) (595:595:595)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (746:746:746)) - (PORT datab (1346:1346:1346) (1366:1366:1366)) - (PORT datac (956:956:956) (1016:1016:1016)) - (PORT datad (374:374:374) (392:392:392)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (1175:1175:1175) (1216:1216:1216)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (590:590:590) (618:618:618)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (606:606:606)) - (PORT datab (829:829:829) (843:843:843)) - (PORT datac (563:563:563) (578:578:578)) - (PORT datad (562:562:562) (578:578:578)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1024:1024:1024) (1052:1052:1052)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1024:1024:1024) (1053:1053:1053)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (464:464:464)) - (PORT datab (450:450:450) (485:485:485)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1257:1257:1257)) - (PORT datab (852:852:852) (879:879:879)) - (PORT datad (594:594:594) (619:619:619)) - (IOPATH dataa combout (301:301:301) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1191:1191:1191) (1216:1216:1216)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1010:1010:1010) (1041:1041:1041)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1012:1012:1012) (1044:1044:1044)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (329:329:329)) - (PORT datab (1408:1408:1408) (1522:1522:1522)) - (PORT datad (216:216:216) (284:284:284)) + (PORT dataa (1478:1478:1478) (1560:1560:1560)) + (PORT datab (781:781:781) (868:868:868)) + (PORT datac (694:694:694) (784:784:784)) + (PORT datad (935:935:935) (1001:1001:1001)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT datab (681:681:681) (743:743:743)) - (PORT datad (608:608:608) (631:631:631)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (969:969:969) (995:995:995)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1189:1189:1189) (1215:1215:1215)) - (PORT ena (1275:1275:1275) (1314:1314:1314)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (787:787:787)) - (PORT datab (725:725:725) (775:775:775)) - (PORT datad (1020:1020:1020) (1061:1061:1061)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1197:1197:1197) (1218:1218:1218)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1195:1195:1195) (1219:1219:1219)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (667:667:667)) - (PORT datab (947:947:947) (1004:1004:1004)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M5T2_3) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1083:1083:1083) (1130:1130:1130)) + (PORT datab (606:606:606) (633:633:633)) + (PORT datac (1511:1511:1511) (1588:1588:1588)) + (PORT datad (610:610:610) (645:645:645)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1052:1052:1052)) + (PORT datab (1441:1441:1441) (1474:1474:1474)) + (PORT datac (694:694:694) (788:788:788)) + (PORT datad (743:743:743) (830:830:830)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) (DELAY (ABSOLUTE (PORT dataa (665:665:665) (697:697:697)) - (PORT datab (636:636:636) (670:670:670)) - (PORT datac (376:376:376) (420:420:420)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1486:1486:1486) (1517:1517:1517)) + (PORT datad (1639:1639:1639) (1659:1659:1659)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30144,60 +11356,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (811:811:811) (832:832:832)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (638:638:638) (670:670:670)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1182:1182:1182) (1199:1199:1199)) - (PORT datac (1095:1095:1095) (1092:1092:1092)) - (PORT datad (659:659:659) (693:693:693)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1517:1517:1517)) - (PORT datab (670:670:670) (708:708:708)) - (PORT datad (839:839:839) (834:834:834)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (480:480:480)) - (PORT datac (666:666:666) (693:693:693)) - (PORT datad (331:331:331) (347:347:347)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30205,104 +11372,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (511:511:511)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (591:591:591)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (1211:1211:1211) (1265:1265:1265)) - (PORT datad (625:625:625) (637:637:637)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1133:1133:1133)) - (PORT datad (860:860:860) (861:861:861)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (509:509:509)) - (PORT datab (392:392:392) (466:466:466)) - (PORT datac (243:243:243) (322:322:322)) - (PORT datad (237:237:237) (305:305:305)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (527:527:527)) - (PORT datab (420:420:420) (490:490:490)) - (PORT datac (392:392:392) (467:467:467)) - (PORT datad (239:239:239) (308:308:308)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1365:1365:1365)) - (PORT datab (705:705:705) (774:774:774)) - (PORT datac (594:594:594) (664:664:664)) - (PORT datad (239:239:239) (309:309:309)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (1261:1261:1261) (1305:1305:1305)) + (PORT datab (1047:1047:1047) (1126:1126:1126)) + (PORT datac (980:980:980) (1025:1025:1025)) + (PORT datad (539:539:539) (553:553:553)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -30311,15 +11388,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla5M1T5_2) (DELAY (ABSOLUTE - (PORT dataa (425:425:425) (509:509:509)) - (PORT datab (411:411:411) (493:493:493)) - (PORT datac (550:550:550) (609:609:609)) - (PORT datad (376:376:376) (439:439:439)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (2596:2596:2596) (2742:2742:2742)) + (PORT datac (607:607:607) (640:640:640)) + (PORT datad (1184:1184:1184) (1274:1274:1274)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (372:372:372)) + (PORT datab (1461:1461:1461) (1460:1460:1460)) + (PORT datac (978:978:978) (1022:1022:1022)) + (PORT datad (1021:1021:1021) (1091:1091:1091)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30327,13 +11418,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) (DELAY (ABSOLUTE - (PORT dataa (868:868:868) (895:895:895)) - (PORT datab (822:822:822) (844:844:844)) - (PORT datac (609:609:609) (631:631:631)) - (PORT datad (629:629:629) (662:662:662)) + (PORT dataa (667:667:667) (721:721:721)) + (PORT datab (1048:1048:1048) (1127:1127:1127)) + (PORT datac (976:976:976) (1020:1020:1020)) + (PORT datad (574:574:574) (587:587:587)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1118:1118:1118)) + (PORT datab (1049:1049:1049) (1133:1133:1133)) + (PORT datac (975:975:975) (1018:1018:1018)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1045:1045:1045)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (196:196:196) (222:222:222)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30343,44 +11466,463 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1069:1069:1069)) - (PORT datab (684:684:684) (720:720:720)) - (PORT datad (623:623:623) (638:638:638)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1591:1591:1591) (1660:1660:1660)) + (PORT datab (1803:1803:1803) (1862:1862:1862)) + (PORT datac (1438:1438:1438) (1463:1463:1463)) + (PORT datad (672:672:672) (729:729:729)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) (DELAY (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1553:1553:1553)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + (PORT dataa (1624:1624:1624) (1752:1752:1752)) + (PORT datab (1689:1689:1689) (1774:1774:1774)) + (PORT datac (1101:1101:1101) (1140:1140:1140)) + (PORT datad (1735:1735:1735) (1840:1840:1840)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (1023:1023:1023)) - (PORT datab (637:637:637) (662:662:662)) - (PORT datac (843:843:843) (877:877:877)) - (PORT datad (636:636:636) (678:678:678)) + (PORT dataa (1923:1923:1923) (1952:1952:1952)) + (PORT datab (1273:1273:1273) (1380:1380:1380)) + (PORT datac (1690:1690:1690) (1714:1714:1714)) + (PORT datad (730:730:730) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (912:912:912)) + (PORT datab (1349:1349:1349) (1382:1382:1382)) + (PORT datac (996:996:996) (1029:1029:1029)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (831:831:831)) + (PORT datab (1970:1970:1970) (2040:2040:2040)) + (PORT datad (636:636:636) (730:730:730)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (380:380:380)) + (PORT datab (1472:1472:1472) (1509:1509:1509)) + (PORT datac (1320:1320:1320) (1360:1360:1360)) + (PORT datad (185:185:185) (218:218:218)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T4_3\~0) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (849:849:849)) + (PORT datac (675:675:675) (772:772:772)) + (PORT datad (1444:1444:1444) (1467:1467:1467)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1081:1081:1081)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (788:788:788) (817:817:817)) + (PORT datad (634:634:634) (648:648:648)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1587:1587:1587)) + (PORT datab (834:834:834) (844:844:844)) + (PORT datac (1150:1150:1150) (1177:1177:1177)) + (PORT datad (1165:1165:1165) (1216:1216:1216)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1068:1068:1068)) + (PORT datab (1721:1721:1721) (1793:1793:1793)) + (PORT datac (1103:1103:1103) (1164:1164:1164)) + (PORT datad (803:803:803) (816:816:816)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~16) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (884:884:884)) + (PORT datab (866:866:866) (884:884:884)) + (PORT datac (820:820:820) (838:838:838)) + (PORT datad (212:212:212) (244:244:244)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1262:1262:1262)) + (PORT datab (604:604:604) (629:629:629)) + (PORT datac (676:676:676) (691:691:691)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1365:1365:1365)) + (PORT datab (1234:1234:1234) (1274:1274:1274)) + (PORT datac (1415:1415:1415) (1452:1452:1452)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (685:685:685)) + (PORT datab (997:997:997) (1050:1050:1050)) + (PORT datac (674:674:674) (701:701:701)) + (PORT datad (1168:1168:1168) (1220:1220:1220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (977:977:977)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (285:285:285)) + (PORT datab (709:709:709) (737:737:737)) + (PORT datac (874:874:874) (904:904:904)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~22) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (309:309:309)) + (PORT datab (1273:1273:1273) (1361:1361:1361)) + (PORT datac (950:950:950) (1071:1071:1071)) + (PORT datad (1130:1130:1130) (1154:1154:1154)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (400:400:400)) + (PORT datab (248:248:248) (290:290:290)) + (PORT datac (675:675:675) (703:703:703)) + (PORT datad (920:920:920) (972:972:972)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (550:550:550) (566:566:566)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (639:639:639)) + (PORT datab (1233:1233:1233) (1281:1281:1281)) + (PORT datac (1635:1635:1635) (1655:1655:1655)) + (PORT datad (644:644:644) (681:681:681)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (897:897:897)) + (PORT datab (961:961:961) (1016:1016:1016)) + (PORT datac (1110:1110:1110) (1139:1139:1139)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1573:1573:1573) (1679:1679:1679)) + (PORT datab (1131:1131:1131) (1172:1172:1172)) + (PORT datac (1498:1498:1498) (1561:1561:1561)) + (PORT datad (1569:1569:1569) (1662:1662:1662)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (889:889:889)) + (PORT datab (1837:1837:1837) (1929:1929:1929)) + (PORT datac (781:781:781) (855:855:855)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (690:690:690)) + (PORT datab (1119:1119:1119) (1154:1154:1154)) + (PORT datac (822:822:822) (875:875:875)) + (PORT datad (830:830:830) (878:878:878)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT datab (1217:1217:1217) (1268:1268:1268)) + (PORT datac (1130:1130:1130) (1157:1157:1157)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (885:885:885)) + (PORT datab (1216:1216:1216) (1270:1270:1270)) + (PORT datad (931:931:931) (966:966:966)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1581:1581:1581)) + (PORT datab (1849:1849:1849) (1918:1918:1918)) + (PORT datac (1514:1514:1514) (1557:1557:1557)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (680:680:680)) + (PORT datab (568:568:568) (604:604:604)) + (PORT datac (347:347:347) (370:370:370)) + (PORT datad (1066:1066:1066) (1089:1089:1089)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (832:832:832)) + (PORT datab (661:661:661) (718:718:718)) + (PORT datac (660:660:660) (712:712:712)) + (PORT datad (668:668:668) (719:719:719)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (741:741:741)) + (PORT datab (936:936:936) (979:979:979)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (619:619:619) (653:653:653)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30390,85 +11932,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~21) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (631:631:631)) - (PORT datab (2626:2626:2626) (2719:2719:2719)) - (PORT datac (2090:2090:2090) (2263:2263:2263)) - (PORT datad (1434:1434:1434) (1452:1452:1452)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (604:604:604)) - (PORT datab (608:608:608) (677:677:677)) - (PORT datad (1145:1145:1145) (1180:1180:1180)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (446:446:446)) - (PORT datac (721:721:721) (815:815:815)) - (PORT datad (268:268:268) (348:348:348)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (990:990:990) (1052:1052:1052)) + (PORT datab (907:907:907) (951:951:951)) + (PORT datac (1272:1272:1272) (1325:1325:1325)) + (PORT datad (1167:1167:1167) (1239:1239:1239)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1240:1240:1240) (1269:1269:1269)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1545:1545:1545)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1364:1364:1364) (1421:1421:1421)) - (PORT datac (853:853:853) (901:901:901)) - (PORT datad (232:232:232) (309:309:309)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (736:736:736) (834:834:834)) + (PORT datac (975:975:975) (1071:1071:1071)) + (PORT datad (990:990:990) (1088:1088:1088)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30476,47 +11962,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (352:352:352)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (983:983:983) (1029:1029:1029)) - (PORT datad (837:837:837) (875:875:875)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1021:1021:1021) (1068:1068:1068)) - (PORT datab (1361:1361:1361) (1418:1418:1418)) - (PORT datac (607:607:607) (631:631:631)) - (PORT datad (920:920:920) (974:974:974)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (914:914:914)) - (PORT datab (641:641:641) (700:700:700)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (636:636:636) (677:677:677)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (1751:1751:1751) (1806:1806:1806)) + (PORT datab (2051:2051:2051) (2112:2112:2112)) + (PORT datac (1227:1227:1227) (1300:1300:1300)) + (PORT datad (837:837:837) (853:853:853)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (1510:1510:1510) (1606:1606:1606)) + (PORT datac (1759:1759:1759) (1827:1827:1827)) + (PORT datad (1180:1180:1180) (1257:1257:1257)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30524,95 +11994,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~19) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1066:1066:1066)) - (PORT datab (2171:2171:2171) (2355:2355:2355)) - (PORT datac (1335:1335:1335) (1387:1387:1387)) - (PORT datad (1335:1335:1335) (1492:1492:1492)) + (PORT dataa (1151:1151:1151) (1233:1233:1233)) + (PORT datab (727:727:727) (790:790:790)) + (PORT datac (865:865:865) (912:912:912)) + (PORT datad (1441:1441:1441) (1459:1459:1459)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1026:1026:1026) (1071:1071:1071)) - (PORT datab (932:932:932) (993:993:993)) - (PORT datac (607:607:607) (627:627:627)) - (PORT datad (837:837:837) (870:870:870)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (918:918:918)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (636:636:636) (681:681:681)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (387:387:387)) - (PORT datab (258:258:258) (300:300:300)) - (PORT datac (364:364:364) (389:389:389)) - (PORT datad (575:575:575) (588:588:588)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1867:1867:1867) (1883:1883:1883)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (414:414:414)) - (PORT datab (355:355:355) (391:391:391)) - (PORT datac (321:321:321) (346:346:346)) - (PORT datad (193:193:193) (218:218:218)) + (PORT dataa (864:864:864) (897:897:897)) + (PORT datab (1139:1139:1139) (1210:1210:1210)) + (PORT datac (1440:1440:1440) (1532:1532:1532)) + (PORT datad (1208:1208:1208) (1244:1244:1244)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30620,26 +12026,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) (DELAY (ABSOLUTE - (PORT datab (1247:1247:1247) (1295:1295:1295)) - (PORT datad (788:788:788) (792:792:792)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1483:1483:1483) (1570:1570:1570)) + (PORT datab (2039:2039:2039) (2143:2143:2143)) + (PORT datad (1180:1180:1180) (1228:1228:1228)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (509:509:509) (518:518:518)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (1502:1502:1502) (1585:1585:1585)) + (PORT datab (1248:1248:1248) (1320:1320:1320)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1794:1794:1794) (1875:1875:1875)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -30649,216 +12056,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (473:473:473)) - (PORT datab (966:966:966) (1019:1019:1019)) - (PORT datac (957:957:957) (996:996:996)) - (PORT datad (930:930:930) (961:961:961)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1008:1008:1008)) - (PORT datab (792:792:792) (810:810:810)) - (PORT datac (831:831:831) (846:846:846)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1277:1277:1277)) - (PORT datab (1010:1010:1010) (1070:1070:1070)) - (PORT datac (1149:1149:1149) (1202:1202:1202)) - (PORT datad (1136:1136:1136) (1189:1189:1189)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (2229:2229:2229) (2339:2339:2339)) + (PORT datab (1731:1731:1731) (1749:1749:1749)) + (PORT datac (1721:1721:1721) (1805:1805:1805)) + (PORT datad (1858:1858:1858) (1927:1927:1927)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (701:701:701)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (538:538:538) (560:560:560)) - (PORT datad (348:348:348) (372:372:372)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (866:866:866)) - (PORT datab (626:626:626) (642:642:642)) - (PORT datac (556:556:556) (572:572:572)) - (PORT datad (542:542:542) (555:555:555)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (1147:1147:1147) (1156:1156:1156)) - (PORT datac (312:312:312) (331:331:331)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (662:662:662)) - (PORT datab (1297:1297:1297) (1354:1354:1354)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (699:699:699)) - (PORT datab (941:941:941) (1002:1002:1002)) - (PORT datac (1172:1172:1172) (1234:1234:1234)) - (PORT datad (786:786:786) (778:778:778)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (827:827:827)) - (PORT datab (677:677:677) (738:738:738)) - (PORT datac (656:656:656) (722:722:722)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (727:727:727)) - (PORT datab (986:986:986) (1058:1058:1058)) - (PORT datad (504:504:504) (504:504:504)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1360:1360:1360)) - (PORT datab (995:995:995) (1071:1071:1071)) - (PORT datac (1112:1112:1112) (1137:1137:1137)) - (PORT datad (1570:1570:1570) (1618:1618:1618)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30869,10 +12075,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) (DELAY (ABSOLUTE - (PORT dataa (1476:1476:1476) (1520:1520:1520)) - (PORT datab (1155:1155:1155) (1181:1181:1181)) - (PORT datac (1087:1087:1087) (1097:1097:1097)) - (PORT datad (600:600:600) (614:614:614)) + (PORT dataa (1887:1887:1887) (1973:1973:1973)) + (PORT datab (387:387:387) (407:407:407)) + (PORT datac (897:897:897) (936:936:936)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30885,10 +12091,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (667:667:667)) - (PORT datab (227:227:227) (267:267:267)) - (PORT datac (613:613:613) (637:637:637)) - (PORT datad (173:173:173) (197:197:197)) + (PORT dataa (907:907:907) (943:943:943)) + (PORT datab (650:650:650) (675:675:675)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (830:830:830) (858:858:858)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -30898,27 +12104,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) (DELAY (ABSOLUTE - (PORT dataa (963:963:963) (1037:1037:1037)) - (PORT datac (957:957:957) (1023:1023:1023)) - (PORT datad (1214:1214:1214) (1280:1280:1280)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (990:990:990) (1083:1083:1083)) + (PORT datab (1031:1031:1031) (1113:1113:1113)) + (PORT datac (1373:1373:1373) (1486:1486:1486)) + (PORT datad (920:920:920) (966:966:966)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (692:692:692)) - (PORT datab (1444:1444:1444) (1500:1500:1500)) - (PORT datac (590:590:590) (630:630:630)) - (PORT datad (582:582:582) (612:612:612)) + (PORT dataa (674:674:674) (696:696:696)) + (PORT datab (1801:1801:1801) (1857:1857:1857)) + (PORT datac (1442:1442:1442) (1467:1467:1467)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1694:1694:1694)) + (PORT datab (1786:1786:1786) (1917:1917:1917)) + (PORT datac (1764:1764:1764) (1858:1858:1858)) + (PORT datad (1760:1760:1760) (1895:1895:1895)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1557:1557:1557)) + (PORT datab (1635:1635:1635) (1661:1661:1661)) + (PORT datac (1184:1184:1184) (1225:1225:1225)) + (PORT datad (920:920:920) (933:933:933)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1131:1131:1131)) + (PORT datab (986:986:986) (1043:1043:1043)) + (PORT datac (1223:1223:1223) (1301:1301:1301)) + (PORT datad (1472:1472:1472) (1537:1537:1537)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (428:428:428)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (906:906:906) (956:956:956)) + (PORT datad (1159:1159:1159) (1198:1198:1198)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -30927,32 +12199,323 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~6) (DELAY (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (752:752:752) (788:788:788)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1281:1281:1281) (1378:1378:1378)) + (PORT datab (1028:1028:1028) (1123:1123:1123)) + (PORT datad (947:947:947) (1032:1032:1032)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (690:690:690)) - (PORT datab (622:622:622) (668:668:668)) - (PORT datad (598:598:598) (635:635:635)) + (PORT dataa (694:694:694) (762:762:762)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (661:661:661) (715:715:715)) + (PORT datad (929:929:929) (969:969:969)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (974:974:974)) + (PORT datac (606:606:606) (628:628:628)) + (PORT datad (624:624:624) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1507:1507:1507)) + (PORT datad (1121:1121:1121) (1194:1194:1194)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1160:1160:1160)) + (PORT datab (1570:1570:1570) (1699:1699:1699)) + (PORT datac (1290:1290:1290) (1404:1404:1404)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~8) + (DELAY + (ABSOLUTE + (PORT datab (1095:1095:1095) (1222:1222:1222)) + (PORT datac (802:802:802) (821:821:821)) + (PORT datad (1874:1874:1874) (1947:1947:1947)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (984:984:984)) + (PORT datab (844:844:844) (880:880:880)) + (PORT datac (965:965:965) (997:997:997)) + (PORT datad (663:663:663) (724:724:724)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1220:1220:1220)) + (PORT datab (654:654:654) (729:729:729)) + (PORT datac (1171:1171:1171) (1164:1164:1164)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (276:276:276)) + (PORT datab (1445:1445:1445) (1515:1515:1515)) + (PORT datac (864:864:864) (910:910:910)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (634:634:634)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (622:622:622) (678:678:678)) + (PORT datad (2002:2002:2002) (2032:2032:2032)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (866:866:866)) + (PORT datab (889:889:889) (924:924:924)) + (PORT datac (689:689:689) (795:795:795)) + (PORT datad (657:657:657) (676:676:676)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datab (993:993:993) (1043:1043:1043)) + (PORT datac (366:366:366) (394:394:394)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (953:953:953)) + (PORT datab (635:635:635) (678:678:678)) + (PORT datac (1571:1571:1571) (1642:1642:1642)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (699:699:699)) + (PORT datab (994:994:994) (1043:1043:1043)) + (PORT datac (599:599:599) (610:610:610)) + (PORT datad (617:617:617) (651:651:651)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (932:932:932)) + (PORT datab (225:225:225) (267:267:267)) + (PORT datac (1722:1722:1722) (1801:1801:1801)) + (PORT datad (1858:1858:1858) (1924:1924:1924)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~30) + (DELAY + (ABSOLUTE + (PORT dataa (2293:2293:2293) (2372:2372:2372)) + (PORT datab (760:760:760) (859:859:859)) + (PORT datac (652:652:652) (759:759:759)) + (PORT datad (1798:1798:1798) (1917:1917:1917)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1887:1887:1887) (1967:1967:1967)) + (PORT datab (411:411:411) (430:430:430)) + (PORT datac (896:896:896) (935:935:935)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (871:871:871)) + (PORT datab (679:679:679) (757:757:757)) + (PORT datac (994:994:994) (1085:1085:1085)) + (PORT datad (1365:1365:1365) (1404:1404:1404)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (855:855:855)) + (PORT datab (1455:1455:1455) (1548:1548:1548)) + (PORT datac (1006:1006:1006) (1029:1029:1029)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (766:766:766) (789:789:789)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (994:994:994)) + (PORT datac (354:354:354) (391:391:391)) + (PORT datad (644:644:644) (701:701:701)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -30962,9 +12525,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30973,16 +12536,199 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (417:417:417)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (334:334:334) (353:353:353)) + (PORT datad (1237:1237:1237) (1300:1300:1300)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (664:664:664)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (616:616:616) (637:637:637)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2613:2613:2613) (2702:2702:2702)) + (PORT datac (1264:1264:1264) (1351:1351:1351)) + (PORT datad (1319:1319:1319) (1400:1400:1400)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (677:677:677) (757:757:757)) + (PORT datac (639:639:639) (697:697:697)) + (PORT datad (1253:1253:1253) (1369:1369:1369)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (290:290:290)) + (PORT datab (915:915:915) (976:976:976)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1487:1487:1487) (1555:1555:1555)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (978:978:978)) + (PORT datab (1079:1079:1079) (1089:1089:1089)) + (PORT datac (1106:1106:1106) (1130:1130:1130)) + (PORT datad (351:351:351) (375:375:375)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1839:1839:1839) (1955:1955:1955)) + (PORT datab (993:993:993) (1042:1042:1042)) + (PORT datac (1196:1196:1196) (1237:1237:1237)) + (PORT datad (840:840:840) (848:848:848)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (672:672:672) (700:700:700)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (447:447:447)) + (PORT datab (683:683:683) (737:737:737)) + (PORT datac (538:538:538) (539:539:539)) + (PORT datad (876:876:876) (910:910:910)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (739:739:739)) + (PORT datac (355:355:355) (388:388:388)) + (PORT datad (566:566:566) (575:575:575)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (890:890:890) (906:906:906)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (687:687:687) (743:743:743)) + (PORT datac (358:358:358) (391:391:391)) + (PORT datad (564:564:564) (571:571:571)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (581:581:581)) - (PORT datab (592:592:592) (627:627:627)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1515:1515:1515) (1611:1611:1611)) + (PORT datab (1308:1308:1308) (1422:1422:1422)) + (PORT datad (1163:1163:1163) (1199:1199:1199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -30992,24 +12738,332 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) (DELAY (ABSOLUTE - (PORT dataa (474:474:474) (523:523:523)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1498:1498:1498) (1562:1562:1562)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (428:428:428) (493:493:493)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1144:1144:1144) (1165:1165:1165)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1156:1156:1156)) + (PORT datab (916:916:916) (945:945:945)) + (PORT datac (1639:1639:1639) (1833:1833:1833)) + (PORT datad (880:880:880) (906:906:906)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (696:696:696)) + (PORT datab (1681:1681:1681) (1718:1718:1718)) + (PORT datac (1695:1695:1695) (1768:1768:1768)) + (PORT datad (1698:1698:1698) (1732:1732:1732)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1289:1289:1289)) + (PORT datab (949:949:949) (1017:1017:1017)) + (PORT datac (902:902:902) (922:922:922)) + (PORT datad (1209:1209:1209) (1222:1222:1222)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1376:1376:1376)) + (PORT datab (880:880:880) (933:933:933)) + (PORT datac (1197:1197:1197) (1297:1297:1297)) + (PORT datad (1123:1123:1123) (1169:1169:1169)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1470:1470:1470)) + (PORT datab (881:881:881) (940:940:940)) + (PORT datac (937:937:937) (1032:1032:1032)) + (PORT datad (1386:1386:1386) (1509:1509:1509)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (923:923:923)) + (PORT datab (746:746:746) (815:815:815)) + (PORT datac (910:910:910) (981:981:981)) + (PORT datad (1436:1436:1436) (1531:1531:1531)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (1011:1011:1011) (1064:1064:1064)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (954:954:954)) + (PORT datac (1199:1199:1199) (1284:1284:1284)) + (PORT datad (1380:1380:1380) (1407:1407:1407)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (678:678:678)) + (PORT datab (1196:1196:1196) (1225:1225:1225)) + (PORT datac (1229:1229:1229) (1275:1275:1275)) + (PORT datad (782:782:782) (805:805:805)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (610:610:610)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (844:844:844) (858:858:858)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (670:670:670)) + (PORT datab (645:645:645) (699:699:699)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (619:619:619) (642:642:642)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (944:944:944)) + (PORT datab (1195:1195:1195) (1242:1242:1242)) + (PORT datac (611:611:611) (637:637:637)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1707:1707:1707) (1746:1746:1746)) + (PORT datab (1510:1510:1510) (1607:1607:1607)) + (PORT datac (1760:1760:1760) (1829:1829:1829)) + (PORT datad (2026:2026:2026) (2076:2076:2076)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1804:1804:1804)) + (PORT datab (1219:1219:1219) (1281:1281:1281)) + (PORT datac (696:696:696) (789:789:789)) + (PORT datad (743:743:743) (828:828:828)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1073:1073:1073)) + (PORT datab (1201:1201:1201) (1238:1238:1238)) + (PORT datac (904:904:904) (953:953:953)) + (PORT datad (1900:1900:1900) (1905:1905:1905)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (930:930:930)) + (PORT datac (866:866:866) (902:902:902)) + (PORT datad (861:861:861) (910:910:910)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (875:875:875) (898:898:898)) + (PORT datac (628:628:628) (650:650:650)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (680:680:680)) + (PORT datad (614:614:614) (635:635:635)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1247:1247:1247)) + (PORT datab (1310:1310:1310) (1421:1421:1421)) + (PORT datac (1148:1148:1148) (1171:1171:1171)) + (PORT datad (1122:1122:1122) (1143:1143:1143)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT datac (880:880:880) (938:938:938)) - (PORT datad (349:349:349) (365:365:365)) + (PORT datac (1195:1195:1195) (1224:1224:1224)) + (PORT datad (596:596:596) (606:606:606)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31020,10 +13074,10 @@ (INSTANCE z80_\|address_latch_\|Q\[11\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31038,8 +13092,134 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT datac (415:415:415) (481:481:481)) - (PORT datad (341:341:341) (363:363:363)) + (PORT datab (709:709:709) (786:786:786)) + (PORT datad (602:602:602) (647:647:647)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (549:549:549)) + (PORT datab (403:403:403) (434:434:434)) + (PORT datac (1159:1159:1159) (1194:1194:1194)) + (PORT datad (629:629:629) (667:667:667)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1140:1140:1140)) + (PORT datab (934:934:934) (1002:1002:1002)) + (PORT datac (906:906:906) (947:947:947)) + (PORT datad (771:771:771) (785:785:785)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (424:424:424)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1269:1269:1269)) + (PORT datab (1517:1517:1517) (1572:1572:1572)) + (PORT datac (1191:1191:1191) (1239:1239:1239)) + (PORT datad (511:511:511) (525:525:525)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1394:1394:1394)) + (PORT datab (957:957:957) (1007:1007:1007)) + (PORT datac (982:982:982) (1038:1038:1038)) + (PORT datad (838:838:838) (846:846:846)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (284:284:284)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (1676:1676:1676) (1720:1720:1720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (825:825:825) (840:840:840)) + (PORT datac (882:882:882) (927:927:927)) + (PORT datad (1322:1322:1322) (1339:1339:1339)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1059:1059:1059)) + (PORT datab (1437:1437:1437) (1477:1477:1477)) + (PORT datac (888:888:888) (937:937:937)) + (PORT datad (1160:1160:1160) (1210:1210:1210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31047,14 +13227,18390 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~17) (DELAY (ABSOLUTE - (PORT dataa (1176:1176:1176) (1262:1262:1262)) - (PORT datab (390:390:390) (410:410:410)) - (PORT datad (553:553:553) (555:555:555)) + (PORT dataa (2418:2418:2418) (2563:2563:2563)) + (PORT datab (1346:1346:1346) (1485:1485:1485)) + (PORT datac (851:851:851) (897:897:897)) + (PORT datad (927:927:927) (986:986:986)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (969:969:969)) + (PORT datac (1653:1653:1653) (1707:1707:1707)) + (PORT datad (1191:1191:1191) (1260:1260:1260)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1217:1217:1217)) + (PORT datab (614:614:614) (640:640:640)) + (PORT datac (1689:1689:1689) (1742:1742:1742)) + (PORT datad (623:623:623) (676:676:676)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (618:618:618)) + (PORT datab (1783:1783:1783) (1915:1915:1915)) + (PORT datac (1169:1169:1169) (1195:1195:1195)) + (PORT datad (1346:1346:1346) (1504:1504:1504)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (893:893:893)) + (PORT datab (613:613:613) (634:634:634)) + (PORT datac (616:616:616) (644:644:644)) + (PORT datad (1105:1105:1105) (1120:1120:1120)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1153:1153:1153)) + (PORT datab (207:207:207) (247:247:247)) + (PORT datac (599:599:599) (643:643:643)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (1543:1543:1543) (1670:1670:1670)) + (PORT datac (1253:1253:1253) (1293:1293:1293)) + (PORT datad (2028:2028:2028) (2132:2132:2132)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1145:1145:1145)) + (PORT datab (613:613:613) (660:660:660)) + (PORT datac (1142:1142:1142) (1182:1182:1182)) + (PORT datad (915:915:915) (949:949:949)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1585:1585:1585)) + (PORT datab (940:940:940) (958:958:958)) + (PORT datac (353:353:353) (369:369:369)) + (PORT datad (324:324:324) (344:344:344)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~15) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (950:950:950)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (792:792:792)) + (PORT datab (1654:1654:1654) (1681:1681:1681)) + (PORT datac (1149:1149:1149) (1212:1212:1212)) + (PORT datad (903:903:903) (965:965:965)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1216:1216:1216)) + (PORT datab (954:954:954) (990:990:990)) + (PORT datac (1686:1686:1686) (1738:1738:1738)) + (PORT datad (626:626:626) (676:676:676)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1549:1549:1549)) + (PORT datab (1383:1383:1383) (1433:1433:1433)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (894:894:894) (930:930:930)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1203:1203:1203)) + (PORT datab (231:231:231) (279:279:279)) + (PORT datac (844:844:844) (877:877:877)) + (PORT datad (870:870:870) (908:908:908)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1298:1298:1298)) + (PORT datab (1214:1214:1214) (1253:1253:1253)) + (PORT datac (913:913:913) (937:937:937)) + (PORT datad (1720:1720:1720) (1754:1754:1754)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1720:1720:1720) (1779:1779:1779)) + (PORT datab (615:615:615) (641:641:641)) + (PORT datac (755:755:755) (789:789:789)) + (PORT datad (312:312:312) (324:324:324)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (407:407:407) (441:441:441)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1591:1591:1591) (1658:1658:1658)) + (PORT datab (1804:1804:1804) (1861:1861:1861)) + (PORT datac (1404:1404:1404) (1439:1439:1439)) + (PORT datad (1839:1839:1839) (1889:1889:1889)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (679:679:679)) + (PORT datab (674:674:674) (688:688:688)) + (PORT datac (624:624:624) (658:658:658)) + (PORT datad (1127:1127:1127) (1145:1145:1145)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (960:960:960)) + (PORT datab (1193:1193:1193) (1238:1238:1238)) + (PORT datac (1147:1147:1147) (1169:1169:1169)) + (PORT datad (621:621:621) (659:659:659)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (946:946:946)) + (PORT datab (224:224:224) (265:265:265)) + (PORT datad (1159:1159:1159) (1205:1205:1205)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (1706:1706:1706) (1755:1755:1755)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1167:1167:1167)) + (PORT datab (1502:1502:1502) (1540:1540:1540)) + (PORT datac (673:673:673) (697:697:697)) + (PORT datad (911:911:911) (934:934:934)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (881:881:881)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (573:573:573) (590:590:590)) + (PORT datad (1089:1089:1089) (1093:1093:1093)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (723:723:723) (764:764:764)) + (PORT datac (911:911:911) (970:970:970)) + (PORT datad (1869:1869:1869) (2001:2001:2001)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2233:2233:2233) (2412:2412:2412)) + (PORT datab (619:619:619) (646:646:646)) + (PORT datad (1501:1501:1501) (1594:1594:1594)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1330:1330:1330)) + (PORT datab (2646:2646:2646) (2748:2748:2748)) + (PORT datac (1226:1226:1226) (1319:1319:1319)) + (PORT datad (1579:1579:1579) (1727:1727:1727)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1293:1293:1293)) + (PORT datab (746:746:746) (855:855:855)) + (PORT datad (1194:1194:1194) (1277:1277:1277)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datac (871:871:871) (905:905:905)) + (PORT datad (902:902:902) (928:928:928)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (895:895:895)) + (PORT datab (658:658:658) (685:685:685)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (890:890:890) (941:941:941)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (1142:1142:1142) (1159:1159:1159)) + (PORT datac (583:583:583) (599:599:599)) + (PORT datad (322:322:322) (335:335:335)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (833:833:833)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (627:627:627) (662:662:662)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1872:1872:1872) (1974:1974:1974)) + (PORT datab (1340:1340:1340) (1460:1460:1460)) + (PORT datac (674:674:674) (736:736:736)) + (PORT datad (867:867:867) (916:916:916)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1362:1362:1362)) + (PORT datab (1587:1587:1587) (1747:1747:1747)) + (PORT datac (1904:1904:1904) (1992:1992:1992)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (2109:2109:2109) (2269:2269:2269)) + (PORT datab (664:664:664) (709:709:709)) + (PORT datac (1760:1760:1760) (1913:1913:1913)) + (PORT datad (1415:1415:1415) (1486:1486:1486)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (2109:2109:2109) (2271:2271:2271)) + (PORT datab (2739:2739:2739) (2867:2867:2867)) + (PORT datac (1759:1759:1759) (1914:1914:1914)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1733:1733:1733) (1848:1848:1848)) + (PORT datab (983:983:983) (1058:1058:1058)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1416:1416:1416) (1489:1489:1489)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1535:1535:1535)) + (PORT datab (1195:1195:1195) (1240:1240:1240)) + (PORT datac (953:953:953) (1022:1022:1022)) + (PORT datad (835:835:835) (844:844:844)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1183:1183:1183)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datac (1660:1660:1660) (1743:1743:1743)) + (PORT datad (1215:1215:1215) (1304:1304:1304)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (971:971:971)) + (PORT datab (1085:1085:1085) (1103:1103:1103)) + (PORT datac (737:737:737) (736:736:736)) + (PORT datad (1069:1069:1069) (1078:1078:1078)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (978:978:978) (1041:1041:1041)) + (PORT datac (526:526:526) (540:540:540)) + (PORT datad (315:315:315) (333:333:333)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (366:366:366)) + (PORT datab (369:369:369) (388:388:388)) + (PORT datac (315:315:315) (334:334:334)) + (PORT datad (543:543:543) (553:553:553)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1281:1281:1281)) + (PORT datac (621:621:621) (649:649:649)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (900:900:900)) + (PORT datab (986:986:986) (1058:1058:1058)) + (PORT datac (931:931:931) (972:972:972)) + (PORT datad (1718:1718:1718) (1748:1748:1748)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (1895:1895:1895) (1984:1984:1984)) + (PORT datad (958:958:958) (1000:1000:1000)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (907:907:907)) + (PORT datab (1350:1350:1350) (1385:1385:1385)) + (PORT datac (978:978:978) (1074:1074:1074)) + (PORT datad (1239:1239:1239) (1343:1343:1343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (627:627:627)) + (PORT datab (1194:1194:1194) (1220:1220:1220)) + (PORT datac (1231:1231:1231) (1275:1275:1275)) + (PORT datad (1313:1313:1313) (1344:1344:1344)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1294:1294:1294)) + (PORT datab (1084:1084:1084) (1191:1191:1191)) + (PORT datac (1106:1106:1106) (1164:1164:1164)) + (PORT datad (2076:2076:2076) (2218:2218:2218)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1252:1252:1252)) + (PORT datab (270:270:270) (318:318:318)) + (PORT datac (1379:1379:1379) (1451:1451:1451)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (677:677:677)) + (PORT datab (226:226:226) (268:268:268)) + (PORT datac (924:924:924) (941:941:941)) + (PORT datad (926:926:926) (965:965:965)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (406:406:406)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (841:841:841) (845:845:845)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1694:1694:1694) (1753:1753:1753)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (907:907:907) (941:941:941)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1009:1009:1009)) + (PORT datab (854:854:854) (861:861:861)) + (PORT datac (2057:2057:2057) (2150:2150:2150)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1309:1309:1309)) + (PORT datab (1499:1499:1499) (1536:1536:1536)) + (PORT datac (1229:1229:1229) (1274:1274:1274)) + (PORT datad (1159:1159:1159) (1184:1184:1184)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1960:1960:1960)) + (PORT datab (994:994:994) (1041:1041:1041)) + (PORT datad (872:872:872) (917:917:917)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1741:1741:1741) (1826:1826:1826)) + (PORT datab (987:987:987) (1058:1058:1058)) + (PORT datac (534:534:534) (548:548:548)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1009:1009:1009)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1881:1881:1881)) + (PORT datab (921:921:921) (966:966:966)) + (PORT datac (901:901:901) (967:967:967)) + (PORT datad (934:934:934) (1029:1029:1029)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (332:332:332) (359:359:359)) + (PORT datad (923:923:923) (961:961:961)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (341:341:341)) + (PORT datab (1192:1192:1192) (1231:1231:1231)) + (PORT datac (1382:1382:1382) (1468:1468:1468)) + (PORT datad (708:708:708) (813:813:813)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1432:1432:1432)) + (PORT datab (231:231:231) (279:279:279)) + (PORT datac (843:843:843) (862:862:862)) + (PORT datad (1131:1131:1131) (1174:1174:1174)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1233:1233:1233)) + (PORT datab (581:581:581) (610:610:610)) + (PORT datad (1136:1136:1136) (1206:1206:1206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1296:1296:1296)) + (PORT datab (749:749:749) (860:860:860)) + (PORT datad (1192:1192:1192) (1276:1276:1276)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (306:306:306) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (338:338:338)) + (PORT datab (1191:1191:1191) (1229:1229:1229)) + (PORT datac (1382:1382:1382) (1466:1466:1466)) + (PORT datad (711:711:711) (812:812:812)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (965:965:965)) + (PORT datab (1267:1267:1267) (1346:1346:1346)) + (PORT datad (639:639:639) (681:681:681)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (341:341:341)) + (PORT datab (1192:1192:1192) (1232:1232:1232)) + (PORT datac (1382:1382:1382) (1470:1470:1470)) + (PORT datad (707:707:707) (815:815:815)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1233:1233:1233)) + (PORT datab (589:589:589) (615:615:615)) + (PORT datad (1136:1136:1136) (1207:1207:1207)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (342:342:342)) + (PORT datab (1195:1195:1195) (1233:1233:1233)) + (PORT datac (1382:1382:1382) (1470:1470:1470)) + (PORT datad (707:707:707) (812:812:812)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (962:962:962)) + (PORT datab (1270:1270:1270) (1346:1346:1346)) + (PORT datad (633:633:633) (675:675:675)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1098:1098:1098)) + (PORT datab (542:542:542) (564:564:564)) + (PORT datac (848:848:848) (926:926:926)) + (PORT datad (519:519:519) (526:526:526)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (988:988:988)) + (PORT datac (1093:1093:1093) (1158:1158:1158)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2316:2316:2316) (2436:2436:2436)) + (PORT datab (1543:1543:1543) (1667:1667:1667)) + (PORT datac (865:865:865) (884:884:884)) + (PORT datad (2031:2031:2031) (2135:2135:2135)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (996:996:996)) + (PORT datab (1219:1219:1219) (1294:1294:1294)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1130:1130:1130) (1166:1166:1166)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datac (665:665:665) (696:696:696)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1263:1263:1263)) + (PORT datab (1033:1033:1033) (1105:1105:1105)) + (PORT datad (642:642:642) (665:665:665)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1579:1579:1579)) + (PORT datab (1497:1497:1497) (1576:1576:1576)) + (PORT datac (1382:1382:1382) (1448:1448:1448)) + (PORT datad (632:632:632) (689:689:689)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (689:689:689)) + (PORT datac (1109:1109:1109) (1179:1179:1179)) + (PORT datad (194:194:194) (229:229:229)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~23) + (DELAY + (ABSOLUTE + (PORT datab (1183:1183:1183) (1220:1220:1220)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~29) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (700:700:700)) + (PORT datab (722:722:722) (791:791:791)) + (PORT datac (1102:1102:1102) (1122:1122:1122)) + (PORT datad (179:179:179) (209:209:209)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~26) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (362:362:362) (391:391:391)) + (PORT datac (619:619:619) (669:669:669)) + (PORT datad (609:609:609) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (427:427:427)) + (PORT datab (711:711:711) (763:763:763)) + (PORT datad (645:645:645) (697:697:697)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1574:1574:1574)) + (PORT datab (1501:1501:1501) (1574:1574:1574)) + (PORT datac (1378:1378:1378) (1442:1442:1442)) + (PORT datad (634:634:634) (691:691:691)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (424:424:424)) + (PORT datab (830:830:830) (838:838:838)) + (PORT datac (1052:1052:1052) (1091:1091:1091)) + (PORT datad (814:814:814) (824:824:824)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1385:1385:1385) (1476:1476:1476)) + (PORT datab (1543:1543:1543) (1633:1633:1633)) + (PORT datac (348:348:348) (386:386:386)) + (PORT datad (1524:1524:1524) (1607:1607:1607)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1653:1653:1653)) + (PORT datab (1546:1546:1546) (1634:1634:1634)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (702:702:702) (798:798:798)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1881:1881:1881)) + (PORT datab (921:921:921) (967:967:967)) + (PORT datac (901:901:901) (967:967:967)) + (PORT datad (934:934:934) (1029:1029:1029)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (968:968:968)) + (PORT datab (1268:1268:1268) (1340:1340:1340)) + (PORT datad (1208:1208:1208) (1218:1218:1218)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1643:1643:1643)) + (PORT datab (1543:1543:1543) (1624:1624:1624)) + (PORT datac (351:351:351) (386:386:386)) + (PORT datad (705:705:705) (803:803:803)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (891:891:891) (896:896:896)) + (PORT datad (205:205:205) (235:235:235)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1646:1646:1646)) + (PORT datab (1546:1546:1546) (1626:1626:1626)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (1233:1233:1233) (1360:1360:1360)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1139:1139:1139)) + (PORT datab (1240:1240:1240) (1273:1273:1273)) + (PORT datac (492:492:492) (511:511:511)) + (PORT datad (576:576:576) (611:611:611)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1228:1228:1228)) + (PORT datab (1084:1084:1084) (1093:1093:1093)) + (PORT datad (1137:1137:1137) (1213:1213:1213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (970:970:970)) + (PORT datab (1264:1264:1264) (1337:1337:1337)) + (PORT datad (643:643:643) (685:685:685)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1210:1210:1210) (1241:1241:1241)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (970:970:970)) + (PORT datab (1263:1263:1263) (1337:1337:1337)) + (PORT datad (633:633:633) (675:675:675)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1211:1211:1211) (1244:1244:1244)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (897:897:897)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (838:838:838) (848:848:848)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (578:578:578)) + (PORT datac (1141:1141:1141) (1188:1188:1188)) + (PORT datad (1137:1137:1137) (1213:1213:1213)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1805:1805:1805) (1892:1892:1892)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (581:581:581) (615:615:615)) + (PORT datac (1145:1145:1145) (1196:1196:1196)) + (PORT datad (1137:1137:1137) (1210:1210:1210)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1805:1805:1805) (1892:1892:1892)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1231:1231:1231)) + (PORT datab (581:581:581) (613:613:613)) + (PORT datad (1137:1137:1137) (1212:1212:1212)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (908:908:908)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (986:986:986)) + (PORT datac (1094:1094:1094) (1157:1157:1157)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1652:1652:1652)) + (PORT datab (398:398:398) (431:431:431)) + (PORT datac (1507:1507:1507) (1600:1600:1600)) + (PORT datad (704:704:704) (804:804:804)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1851:1851:1851) (1958:1958:1958)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1558:1558:1558) (1654:1654:1654)) + (PORT datab (397:397:397) (428:428:428)) + (PORT datac (1511:1511:1511) (1601:1601:1601)) + (PORT datad (704:704:704) (801:801:801)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1853:1853:1853) (1959:1959:1959)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (754:754:754)) + (PORT datab (668:668:668) (711:711:711)) + (PORT datad (356:356:356) (414:414:414)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (964:964:964)) + (PORT datab (1272:1272:1272) (1346:1346:1346)) + (PORT datad (1209:1209:1209) (1218:1218:1218)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1347:1347:1347) (1401:1401:1401)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1475:1475:1475) (1566:1566:1566)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1650:1650:1650)) + (PORT datab (1274:1274:1274) (1405:1405:1405)) + (PORT datac (1507:1507:1507) (1598:1598:1598)) + (PORT datad (362:362:362) (393:393:393)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (983:983:983)) + (PORT datab (896:896:896) (938:938:938)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1645:1645:1645)) + (PORT datab (1542:1542:1542) (1626:1626:1626)) + (PORT datac (1358:1358:1358) (1438:1438:1438)) + (PORT datad (364:364:364) (390:390:390)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (956:956:956) (978:978:978)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (430:430:430)) + (PORT datab (711:711:711) (765:765:765)) + (PORT datad (644:644:644) (701:701:701)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (962:962:962) (983:983:983)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datab (464:464:464) (504:504:504)) + (PORT datad (1157:1157:1157) (1213:1213:1213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT datab (635:635:635) (689:689:689)) + (PORT datac (1102:1102:1102) (1175:1175:1175)) + (PORT datad (193:193:193) (227:227:227)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1202:1202:1202) (1222:1222:1222)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (925:925:925)) + (PORT datab (1236:1236:1236) (1262:1262:1262)) + (PORT datad (860:860:860) (865:865:865)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (410:410:410)) + (PORT datab (638:638:638) (655:655:655)) + (PORT datac (344:344:344) (368:368:368)) + (PORT datad (604:604:604) (641:641:641)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1220:1220:1220)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (605:605:605) (660:660:660)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1467:1467:1467) (1463:1463:1463)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (852:852:852) (898:898:898)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (403:403:403)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (592:592:592) (616:616:616)) + (PORT datad (579:579:579) (587:587:587)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (963:963:963)) + (PORT datab (1101:1101:1101) (1135:1135:1135)) + (PORT datac (907:907:907) (958:958:958)) + (PORT datad (901:901:901) (944:944:944)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1544:1544:1544)) + (PORT datab (937:937:937) (1010:1010:1010)) + (PORT datac (597:597:597) (658:658:658)) + (PORT datad (612:612:612) (669:669:669)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (953:953:953)) + (PORT datab (848:848:848) (892:892:892)) + (PORT datad (1141:1141:1141) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1563:1563:1563)) + (PORT datab (923:923:923) (951:951:951)) + (PORT datac (946:946:946) (995:995:995)) + (PORT datad (905:905:905) (956:956:956)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1363:1363:1363) (1384:1384:1384)) + (PORT datab (884:884:884) (925:925:925)) + (PORT datac (937:937:937) (980:980:980)) + (PORT datad (1191:1191:1191) (1250:1250:1250)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1558:1558:1558)) + (PORT datab (1462:1462:1462) (1495:1495:1495)) + (PORT datac (1650:1650:1650) (1738:1738:1738)) + (PORT datad (797:797:797) (847:847:847)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (586:586:586)) + (PORT datab (983:983:983) (1024:1024:1024)) + (PORT datac (495:495:495) (503:503:503)) + (PORT datad (1079:1079:1079) (1076:1076:1076)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (701:701:701)) + (PORT datab (1112:1112:1112) (1138:1138:1138)) + (PORT datac (756:756:756) (766:766:766)) + (PORT datad (775:775:775) (835:835:835)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1177:1177:1177)) + (PORT datab (346:346:346) (380:380:380)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (558:558:558) (562:562:562)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (952:952:952) (976:976:976)) + (PORT datac (867:867:867) (882:882:882)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (1273:1273:1273) (1379:1379:1379)) + (PORT datac (1212:1212:1212) (1277:1277:1277)) + (PORT datad (1419:1419:1419) (1483:1483:1483)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (657:657:657) (703:703:703)) + (PORT datac (901:901:901) (933:933:933)) + (PORT datad (1195:1195:1195) (1273:1273:1273)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (270:270:270)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1054:1054:1054)) + (PORT datab (869:869:869) (898:898:898)) + (PORT datac (1859:1859:1859) (1856:1856:1856)) + (PORT datad (1111:1111:1111) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1130:1130:1130)) + (PORT datab (578:578:578) (604:604:604)) + (PORT datac (682:682:682) (742:742:742)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (601:601:601)) + (PORT datab (896:896:896) (907:907:907)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (822:822:822)) + (PORT datab (708:708:708) (790:790:790)) + (PORT datac (1415:1415:1415) (1429:1429:1429)) + (PORT datad (1112:1112:1112) (1130:1130:1130)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (275:275:275)) + (PORT datab (946:946:946) (972:972:972)) + (PORT datac (1110:1110:1110) (1136:1136:1136)) + (PORT datad (1407:1407:1407) (1461:1461:1461)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1514:1514:1514)) + (PORT datab (1167:1167:1167) (1198:1198:1198)) + (PORT datac (1416:1416:1416) (1484:1484:1484)) + (PORT datad (626:626:626) (666:666:666)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1413:1413:1413) (1487:1487:1487)) + (PORT datad (196:196:196) (237:237:237)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1303:1303:1303)) + (PORT datab (1829:1829:1829) (1892:1892:1892)) + (PORT datac (618:618:618) (647:647:647)) + (PORT datad (1048:1048:1048) (1107:1107:1107)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1342:1342:1342)) + (PORT datab (751:751:751) (851:851:851)) + (PORT datac (697:697:697) (800:800:800)) + (PORT datad (1222:1222:1222) (1251:1251:1251)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1112:1112:1112)) + (PORT datac (1238:1238:1238) (1325:1325:1325)) + (PORT datad (222:222:222) (260:260:260)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (261:261:261)) + (PORT datab (1751:1751:1751) (1801:1801:1801)) + (PORT datac (1451:1451:1451) (1615:1615:1615)) + (PORT datad (806:806:806) (821:821:821)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (871:871:871)) + (PORT datab (1524:1524:1524) (1560:1560:1560)) + (PORT datac (1083:1083:1083) (1088:1088:1088)) + (PORT datad (319:319:319) (341:341:341)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1441:1441:1441)) + (PORT datab (882:882:882) (941:941:941)) + (PORT datac (1254:1254:1254) (1346:1346:1346)) + (PORT datad (1013:1013:1013) (1138:1138:1138)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1037:1037:1037)) + (PORT datab (999:999:999) (1030:1030:1030)) + (PORT datac (1625:1625:1625) (1664:1664:1664)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1203:1203:1203)) + (PORT datab (894:894:894) (948:948:948)) + (PORT datac (1412:1412:1412) (1488:1488:1488)) + (PORT datad (1187:1187:1187) (1199:1199:1199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1703:1703:1703)) + (PORT datab (933:933:933) (960:960:960)) + (PORT datac (806:806:806) (828:828:828)) + (PORT datad (1218:1218:1218) (1303:1303:1303)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1112:1112:1112)) + (PORT datab (1303:1303:1303) (1409:1409:1409)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (545:545:545) (565:565:565)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (680:680:680)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (920:920:920) (943:943:943)) + (PORT datad (608:608:608) (649:649:649)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (390:390:390)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (610:610:610) (616:616:616)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1442:1442:1442)) + (PORT datab (909:909:909) (950:950:950)) + (PORT datac (1253:1253:1253) (1344:1344:1344)) + (PORT datad (1016:1016:1016) (1139:1139:1139)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (717:717:717)) + (PORT datab (908:908:908) (963:963:963)) + (PORT datac (566:566:566) (592:592:592)) + (PORT datad (588:588:588) (608:608:608)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (655:655:655) (677:677:677)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (833:833:833) (865:865:865)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (638:638:638)) + (PORT datab (627:627:627) (644:644:644)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (875:875:875) (921:921:921)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (887:887:887) (938:938:938)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1363:1363:1363)) + (PORT datab (588:588:588) (607:607:607)) + (PORT datac (1208:1208:1208) (1245:1245:1245)) + (PORT datad (1737:1737:1737) (1795:1795:1795)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1242:1242:1242)) + (PORT datab (426:426:426) (502:502:502)) + (PORT datad (438:438:438) (498:498:498)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (963:963:963)) + (PORT datab (1720:1720:1720) (1795:1795:1795)) + (PORT datac (1274:1274:1274) (1324:1324:1324)) + (PORT datad (974:974:974) (1027:1027:1027)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (929:929:929) (998:998:998)) + (PORT datac (641:641:641) (690:690:690)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (905:905:905)) + (PORT datab (1162:1162:1162) (1176:1176:1176)) + (PORT datac (1346:1346:1346) (1374:1374:1374)) + (PORT datad (882:882:882) (905:905:905)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1157:1157:1157)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1454:1454:1454) (1505:1505:1505)) + (PORT datad (343:343:343) (366:366:366)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1068:1068:1068)) + (PORT datab (1096:1096:1096) (1143:1143:1143)) + (PORT datac (905:905:905) (954:954:954)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT datab (1361:1361:1361) (1428:1428:1428)) + (PORT datad (1336:1336:1336) (1389:1389:1389)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1486:1486:1486)) + (PORT datab (361:361:361) (394:394:394)) + (PORT datac (1141:1141:1141) (1208:1208:1208)) + (PORT datad (1064:1064:1064) (1100:1100:1100)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (749:749:749)) + (PORT datab (1473:1473:1473) (1509:1509:1509)) + (PORT datac (874:874:874) (900:900:900)) + (PORT datad (1225:1225:1225) (1250:1250:1250)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (909:909:909)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (1166:1166:1166) (1173:1173:1173)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (817:817:817)) + (PORT datab (1830:1830:1830) (1892:1892:1892)) + (PORT datac (682:682:682) (759:759:759)) + (PORT datad (1224:1224:1224) (1302:1302:1302)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (195:195:195) (230:230:230)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (381:381:381)) + (PORT datab (585:585:585) (605:605:605)) + (PORT datac (636:636:636) (685:685:685)) + (PORT datad (547:547:547) (559:559:559)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (262:262:262)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (906:906:906) (933:933:933)) + (PORT datad (588:588:588) (617:617:617)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (641:641:641) (689:689:689)) + (PORT datad (317:317:317) (335:335:335)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1443:1443:1443)) + (PORT datab (880:880:880) (938:938:938)) + (PORT datac (936:936:936) (1032:1032:1032)) + (PORT datad (1388:1388:1388) (1510:1510:1510)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (654:654:654) (673:673:673)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (833:833:833) (861:861:861)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (637:637:637)) + (PORT datad (875:875:875) (921:921:921)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1218:1218:1218)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (1100:1100:1100) (1124:1124:1124)) + (PORT datad (1168:1168:1168) (1186:1186:1186)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1189:1189:1189)) + (PORT datab (1795:1795:1795) (1857:1857:1857)) + (PORT datac (1484:1484:1484) (1515:1515:1515)) + (PORT datad (1456:1456:1456) (1522:1522:1522)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (935:935:935)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (1668:1668:1668) (1703:1703:1703)) + (PORT datad (1456:1456:1456) (1525:1525:1525)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (799:799:799)) + (PORT datab (1464:1464:1464) (1462:1462:1462)) + (PORT datac (1627:1627:1627) (1654:1654:1654)) + (PORT datad (631:631:631) (644:644:644)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (712:712:712)) + (PORT datab (972:972:972) (1028:1028:1028)) + (PORT datac (1215:1215:1215) (1268:1268:1268)) + (PORT datad (1202:1202:1202) (1282:1282:1282)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1381:1381:1381) (1391:1391:1391)) + (PORT datad (1159:1159:1159) (1197:1197:1197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (950:950:950)) + (PORT datab (1011:1011:1011) (1054:1054:1054)) + (PORT datac (971:971:971) (1026:1026:1026)) + (PORT datad (1020:1020:1020) (1094:1094:1094)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1006:1006:1006)) + (PORT datab (209:209:209) (252:252:252)) + (PORT datac (918:918:918) (958:958:958)) + (PORT datad (900:900:900) (933:933:933)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (417:417:417)) + (PORT datab (1760:1760:1760) (1818:1818:1818)) + (PORT datac (1126:1126:1126) (1134:1134:1134)) + (PORT datad (545:545:545) (556:556:556)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (896:896:896)) + (PORT datab (867:867:867) (903:903:903)) + (PORT datac (1726:1726:1726) (1786:1786:1786)) + (PORT datad (614:614:614) (636:636:636)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1237:1237:1237)) + (PORT datab (1201:1201:1201) (1235:1235:1235)) + (PORT datac (905:905:905) (951:951:951)) + (PORT datad (602:602:602) (617:617:617)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (479:479:479)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (968:968:968) (1000:1000:1000)) + (PORT datad (585:585:585) (603:603:603)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (479:479:479)) + (PORT datab (1954:1954:1954) (2006:2006:2006)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1434:1434:1434) (1530:1530:1530)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1242:1242:1242)) + (PORT datab (1237:1237:1237) (1278:1278:1278)) + (PORT datac (1416:1416:1416) (1453:1453:1453)) + (PORT datad (871:871:871) (912:912:912)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1477:1477:1477)) + (PORT datab (1804:1804:1804) (1863:1863:1863)) + (PORT datac (1442:1442:1442) (1467:1467:1467)) + (PORT datad (672:672:672) (729:729:729)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1276:1276:1276)) + (PORT datab (681:681:681) (723:723:723)) + (PORT datac (1635:1635:1635) (1657:1657:1657)) + (PORT datad (1117:1117:1117) (1177:1177:1177)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1188:1188:1188)) + (PORT datab (880:880:880) (894:894:894)) + (PORT datac (351:351:351) (379:379:379)) + (PORT datad (605:605:605) (616:616:616)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1362:1362:1362)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (641:641:641) (690:690:690)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (478:478:478)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1625:1625:1625) (1665:1665:1665)) + (PORT datad (586:586:586) (606:606:606)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1472:1472:1472)) + (PORT datab (459:459:459) (536:536:536)) + (PORT datac (1127:1127:1127) (1203:1203:1203)) + (PORT datad (395:395:395) (463:463:463)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1470:1470:1470)) + (PORT datab (998:998:998) (1028:1028:1028)) + (PORT datac (813:813:813) (846:846:846)) + (PORT datad (588:588:588) (604:604:604)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1570:1570:1570)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (943:943:943) (999:999:999)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (978:978:978)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (928:928:928) (965:965:965)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1439:1439:1439)) + (PORT datab (1524:1524:1524) (1560:1560:1560)) + (PORT datac (834:834:834) (845:845:845)) + (PORT datad (1194:1194:1194) (1276:1276:1276)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (682:682:682)) + (PORT datab (222:222:222) (270:270:270)) + (PORT datac (1384:1384:1384) (1435:1435:1435)) + (PORT datad (835:835:835) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (821:821:821)) + (PORT datab (1835:1835:1835) (1893:1893:1893)) + (PORT datac (1209:1209:1209) (1258:1258:1258)) + (PORT datad (1128:1128:1128) (1194:1194:1194)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (833:833:833) (851:851:851)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (942:942:942)) + (PORT datab (911:911:911) (984:984:984)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (581:581:581) (595:595:595)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (720:720:720)) + (PORT datad (805:805:805) (806:806:806)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1362:1362:1362) (1431:1431:1431)) + (PORT datab (1361:1361:1361) (1431:1431:1431)) + (PORT datac (1116:1116:1116) (1171:1171:1171)) + (PORT datad (1359:1359:1359) (1414:1414:1414)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datac (871:871:871) (905:905:905)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1214:1214:1214)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (2230:2230:2230) (2271:2271:2271)) + (PORT datad (1159:1159:1159) (1205:1205:1205)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1263:1263:1263)) + (PORT datab (1244:1244:1244) (1282:1282:1282)) + (PORT datac (983:983:983) (1041:1041:1041)) + (PORT datad (877:877:877) (942:942:942)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (732:732:732) (770:770:770)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (2485:2485:2485) (2527:2527:2527)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1295:1295:1295)) + (PORT datab (2818:2818:2818) (2933:2933:2933)) + (PORT datac (1500:1500:1500) (1565:1565:1565)) + (PORT datad (548:548:548) (560:560:560)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1374:1374:1374)) + (PORT datab (1710:1710:1710) (1774:1774:1774)) + (PORT datac (1195:1195:1195) (1300:1300:1300)) + (PORT datad (1121:1121:1121) (1167:1167:1167)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (925:925:925)) + (PORT datab (689:689:689) (751:751:751)) + (PORT datac (1525:1525:1525) (1625:1625:1625)) + (PORT datad (903:903:903) (944:944:944)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1168:1168:1168)) + (PORT datab (1176:1176:1176) (1191:1191:1191)) + (PORT datac (815:815:815) (849:849:849)) + (PORT datad (1233:1233:1233) (1285:1285:1285)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (700:700:700)) + (PORT datab (932:932:932) (998:998:998)) + (PORT datac (1491:1491:1491) (1548:1548:1548)) + (PORT datad (887:887:887) (930:930:930)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1022:1022:1022)) + (PORT datab (932:932:932) (967:967:967)) + (PORT datac (1752:1752:1752) (1833:1833:1833)) + (PORT datad (977:977:977) (1053:1053:1053)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (647:647:647) (665:665:665)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1301:1301:1301)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (877:877:877) (906:906:906)) + (PORT datad (627:627:627) (640:640:640)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (385:385:385)) + (PORT datab (1196:1196:1196) (1226:1226:1226)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (1084:1084:1084) (1142:1142:1142)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (1190:1190:1190) (1222:1222:1222)) + (PORT datac (1093:1093:1093) (1153:1153:1153)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (992:992:992)) + (PORT datab (1264:1264:1264) (1337:1337:1337)) + (PORT datad (1208:1208:1208) (1215:1215:1215)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1194:1194:1194)) + (PORT datad (1172:1172:1172) (1208:1208:1208)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1501:1501:1501) (1568:1568:1568)) + (PORT datab (234:234:234) (279:279:279)) + (PORT datac (1472:1472:1472) (1537:1537:1537)) + (PORT datad (1234:1234:1234) (1360:1360:1360)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1514:1514:1514) (1575:1575:1575)) + (PORT datab (1498:1498:1498) (1572:1572:1572)) + (PORT datac (1384:1384:1384) (1449:1449:1449)) + (PORT datad (332:332:332) (349:349:349)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1227:1227:1227)) + (PORT datab (236:236:236) (282:282:282)) + (PORT datac (1110:1110:1110) (1181:1181:1181)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1827:1827:1827) (1962:1962:1962)) + (PORT datab (682:682:682) (792:792:792)) + (PORT datac (2257:2257:2257) (2333:2333:2333)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (844:844:844)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (612:612:612) (655:655:655)) + (PORT datad (1430:1430:1430) (1511:1511:1511)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (364:364:364) (392:392:392)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (803:803:803) (811:811:811)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT datab (668:668:668) (727:727:727)) + (PORT datac (677:677:677) (727:727:727)) + (PORT datad (370:370:370) (400:400:400)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1224:1224:1224)) + (PORT datac (1112:1112:1112) (1181:1181:1181)) + (PORT datad (194:194:194) (227:227:227)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (610:610:610)) + (PORT datab (644:644:644) (653:653:653)) + (PORT datac (905:905:905) (927:927:927)) + (PORT datad (584:584:584) (594:594:594)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT datab (722:722:722) (795:795:795)) + (PORT datac (734:734:734) (831:831:831)) + (PORT datad (652:652:652) (687:687:687)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (908:908:908)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1570:1570:1570)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (1470:1470:1470) (1536:1536:1536)) + (PORT datad (671:671:671) (768:768:768)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1573:1573:1573)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (1470:1470:1470) (1539:1539:1539)) + (PORT datad (673:673:673) (769:769:769)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1704:1704:1704)) + (PORT datab (427:427:427) (459:459:459)) + (PORT datac (582:582:582) (586:586:586)) + (PORT datad (390:390:390) (413:413:413)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (703:703:703)) + (PORT datab (239:239:239) (285:285:285)) + (PORT datac (515:515:515) (526:526:526)) + (PORT datad (325:325:325) (348:348:348)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (1123:1123:1123) (1187:1187:1187)) + (PORT datac (1160:1160:1160) (1187:1187:1187)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (340:340:340) (360:360:360)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (268:268:268)) + (PORT datac (1167:1167:1167) (1192:1192:1192)) + (PORT datad (1085:1085:1085) (1143:1143:1143)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1265:1265:1265) (1293:1293:1293)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (278:278:278)) + (PORT datab (1197:1197:1197) (1227:1227:1227)) + (PORT datac (1095:1095:1095) (1158:1158:1158)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1262:1262:1262) (1289:1289:1289)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1045:1045:1045)) + (PORT datab (741:741:741) (776:776:776)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1221:1221:1221)) + (PORT datab (1171:1171:1171) (1225:1225:1225)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1489:1489:1489)) + (PORT datab (1452:1452:1452) (1522:1522:1522)) + (PORT datac (194:194:194) (240:240:240)) + (PORT datad (1460:1460:1460) (1535:1535:1535)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (538:538:538) (568:568:568)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1477:1477:1477)) + (PORT datab (1029:1029:1029) (1025:1025:1025)) + (PORT datad (810:810:810) (811:811:811)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1230:1230:1230)) + (PORT datac (1114:1114:1114) (1183:1183:1183)) + (PORT datad (196:196:196) (231:231:231)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (999:999:999) (1050:1050:1050)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (630:630:630) (677:677:677)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1227:1227:1227)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (1110:1110:1110) (1181:1181:1181)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (734:734:734)) + (PORT datab (724:724:724) (773:773:773)) + (PORT datad (364:364:364) (424:424:424)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (627:627:627) (674:674:674)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (986:986:986)) + (PORT datab (1272:1272:1272) (1347:1347:1347)) + (PORT datad (1209:1209:1209) (1216:1216:1216)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (277:277:277)) + (PORT datab (1501:1501:1501) (1574:1574:1574)) + (PORT datac (1475:1475:1475) (1535:1535:1535)) + (PORT datad (1507:1507:1507) (1610:1610:1610)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (996:996:996) (1047:1047:1047)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (696:696:696)) + (PORT datab (680:680:680) (731:731:731)) + (PORT datad (894:894:894) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (827:827:827)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (812:812:812)) + (PORT datab (1503:1503:1503) (1577:1577:1577)) + (PORT datac (197:197:197) (243:243:243)) + (PORT datad (1429:1429:1429) (1486:1486:1486)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (808:808:808)) + (PORT datab (1498:1498:1498) (1571:1571:1571)) + (PORT datac (194:194:194) (236:236:236)) + (PORT datad (1427:1427:1427) (1483:1483:1483)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1159:1159:1159) (1186:1186:1186)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (721:721:721)) + (PORT datab (421:421:421) (461:461:461)) + (PORT datad (386:386:386) (415:415:415)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT datab (663:663:663) (724:724:724)) + (PORT datac (676:676:676) (731:731:731)) + (PORT datad (369:369:369) (406:406:406)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1160:1160:1160) (1184:1184:1184)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (933:933:933) (957:957:957)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (646:646:646)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (839:839:839) (868:868:868)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (986:986:986)) + (PORT datab (1261:1261:1261) (1341:1341:1341)) + (PORT datad (632:632:632) (675:675:675)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (986:986:986)) + (PORT datab (1262:1262:1262) (1339:1339:1339)) + (PORT datad (643:643:643) (685:685:685)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (985:985:985)) + (PORT datab (1272:1272:1272) (1347:1347:1347)) + (PORT datad (634:634:634) (675:675:675)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1242:1242:1242) (1262:1262:1262)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (990:990:990)) + (PORT datab (1272:1272:1272) (1344:1344:1344)) + (PORT datad (641:641:641) (682:682:682)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1242:1242:1242) (1262:1262:1262)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (999:999:999)) + (PORT datab (966:966:966) (1017:1017:1017)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (581:581:581) (605:605:605)) + (PORT datad (339:339:339) (358:358:358)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (929:929:929)) + (PORT datab (882:882:882) (889:889:889)) + (PORT datac (922:922:922) (952:952:952)) + (PORT datad (576:576:576) (587:587:587)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (447:447:447)) + (PORT datab (957:957:957) (990:990:990)) + (PORT datad (631:631:631) (680:680:680)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (889:889:889) (902:902:902)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (447:447:447)) + (PORT datab (960:960:960) (991:991:991)) + (PORT datad (639:639:639) (685:685:685)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1307:1307:1307)) + (PORT datab (660:660:660) (701:701:701)) + (PORT datad (648:648:648) (673:673:673)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (447:447:447)) + (PORT datab (668:668:668) (726:726:726)) + (PORT datad (564:564:564) (571:571:571)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (452:452:452)) + (PORT datab (662:662:662) (724:724:724)) + (PORT datad (566:566:566) (575:575:575)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (665:665:665) (681:681:681)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (724:724:724)) + (PORT datab (667:667:667) (691:691:691)) + (PORT datac (1215:1215:1215) (1266:1266:1266)) + (PORT datad (644:644:644) (667:667:667)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (631:631:631) (677:677:677)) + (PORT datad (1078:1078:1078) (1110:1110:1110)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1182:1182:1182) (1208:1208:1208)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1182:1182:1182) (1207:1207:1207)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1038:1038:1038)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (704:704:704) (741:741:741)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1205:1205:1205) (1227:1227:1227)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1479:1479:1479)) + (PORT datab (838:838:838) (850:850:850)) + (PORT datad (809:809:809) (813:813:813)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1441:1441:1441) (1456:1456:1456)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (904:904:904) (941:941:941)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (737:737:737)) + (PORT datab (727:727:727) (774:774:774)) + (PORT datad (360:360:360) (419:419:419)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (955:955:955) (983:983:983)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (480:480:480)) + (PORT datab (418:418:418) (454:454:454)) + (PORT datad (386:386:386) (412:412:412)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (957:957:957) (980:980:980)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (933:933:933) (957:957:957)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (904:904:904) (944:944:944)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1441:1441:1441) (1458:1458:1458)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (717:717:717)) + (PORT datab (677:677:677) (727:727:727)) + (PORT datad (890:890:890) (918:918:918)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (701:701:701)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (891:891:891) (905:905:905)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1188:1188:1188) (1209:1209:1209)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1188:1188:1188) (1210:1210:1210)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (994:994:994)) + (PORT datab (962:962:962) (1011:1011:1011)) + (PORT datad (215:215:215) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (596:596:596) (623:623:623)) + (PORT datad (316:316:316) (336:336:336)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (866:866:866)) + (PORT datab (866:866:866) (881:881:881)) + (PORT datac (558:558:558) (572:572:572)) + (PORT datad (600:600:600) (615:615:615)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (876:876:876) (886:886:886)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1304:1304:1304)) + (PORT datab (1130:1130:1130) (1137:1137:1137)) + (PORT datad (649:649:649) (670:670:670)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (326:326:326)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (664:664:664) (681:681:681)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (723:723:723)) + (PORT datab (567:567:567) (586:586:586)) + (PORT datac (226:226:226) (271:271:271)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (712:712:712)) + (PORT datad (775:775:775) (790:790:790)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (359:359:359)) + (PORT datab (578:578:578) (599:599:599)) + (PORT datac (630:630:630) (677:677:677)) + (PORT datad (1077:1077:1077) (1109:1109:1109)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (723:723:723)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (224:224:224) (269:269:269)) + (PORT datad (1029:1029:1029) (1022:1022:1022)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (713:713:713)) + (PORT datad (852:852:852) (855:855:855)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (662:662:662)) + (PORT datad (245:245:245) (318:318:318)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datab (660:660:660) (712:712:712)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1151:1151:1151)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (853:853:853) (872:872:872)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1254:1254:1254) (1306:1306:1306)) + (PORT datab (823:823:823) (859:859:859)) + (PORT datad (645:645:645) (668:668:668)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (331:331:331)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (663:663:663) (679:679:679)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (724:724:724)) + (PORT datab (829:829:829) (850:850:850)) + (PORT datac (225:225:225) (269:269:269)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (802:802:802) (827:827:827)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1147:1147:1147) (1156:1156:1156)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (910:910:910) (935:935:935)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1707:1707:1707)) + (PORT datab (850:850:850) (877:877:877)) + (PORT datad (394:394:394) (420:420:420)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (912:912:912) (935:935:935)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~58) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (235:235:235)) + (PORT datad (938:938:938) (958:958:958)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1194:1194:1194) (1212:1212:1212)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (846:846:846) (865:865:865)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (459:459:459)) + (PORT datab (836:836:836) (853:853:853)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (935:935:935) (962:962:962)) + (PORT ena (1226:1226:1226) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (931:931:931) (960:960:960)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (885:885:885) (909:909:909)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1286:1286:1286) (1318:1318:1318)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (731:731:731)) + (PORT datab (417:417:417) (483:483:483)) + (PORT datad (687:687:687) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (372:372:372)) + (PORT datab (624:624:624) (639:639:639)) + (PORT datac (557:557:557) (563:563:563)) + (PORT datad (845:845:845) (856:856:856)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (595:595:595) (608:608:608)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (968:968:968) (987:987:987)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1045:1045:1045)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (701:701:701) (746:746:746)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (630:630:630)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (589:589:589) (601:601:601)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (858:858:858)) + (PORT datab (652:652:652) (683:683:683)) + (PORT datac (882:882:882) (886:886:886)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (393:393:393)) + (PORT datab (1136:1136:1136) (1147:1147:1147)) + (PORT datac (384:384:384) (413:413:413)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (397:397:397)) + (PORT datab (377:377:377) (413:413:413)) + (PORT datac (1305:1305:1305) (1292:1292:1292)) + (PORT datad (616:616:616) (633:633:633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (750:750:750)) + (PORT datab (268:268:268) (320:320:320)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (764:764:764) (780:780:780)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1479:1479:1479) (1541:1541:1541)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (869:869:869)) + (PORT datab (1234:1234:1234) (1268:1268:1268)) + (PORT datad (859:859:859) (877:877:877)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1941:1941:1941) (2022:2022:2022)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1942:1942:1942) (2022:2022:2022)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (755:755:755)) + (PORT datab (670:670:670) (714:714:714)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (536:536:536) (566:566:566)) + (PORT ena (2046:2046:2046) (2144:2144:2144)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1772:1772:1772) (1839:1839:1839)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (734:734:734)) + (PORT datab (458:458:458) (504:504:504)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1620:1620:1620) (1689:1689:1689)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1617:1617:1617) (1686:1686:1686)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (976:976:976)) + (PORT datab (896:896:896) (929:929:929)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (895:895:895)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (546:546:546) (569:569:569)) + (PORT datad (801:801:801) (849:849:849)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1482:1482:1482) (1550:1550:1550)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1451:1451:1451)) + (PORT datab (1366:1366:1366) (1446:1446:1446)) + (PORT datad (871:871:871) (897:897:897)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1523:1523:1523)) + (PORT asdata (1192:1192:1192) (1252:1252:1252)) + (PORT ena (1490:1490:1490) (1524:1524:1524)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1483:1483:1483) (1547:1547:1547)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (969:969:969)) + (PORT datab (876:876:876) (966:966:966)) + (PORT datad (992:992:992) (1049:1049:1049)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1218:1218:1218) (1275:1275:1275)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1218:1218:1218) (1275:1275:1275)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (904:904:904)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (837:837:837) (854:854:854)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (888:888:888)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (366:366:366) (393:393:393)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (708:708:708)) + (PORT datab (237:237:237) (281:281:281)) + (PORT datac (372:372:372) (398:398:398)) + (PORT datad (599:599:599) (615:615:615)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1014:1014:1014)) + (PORT datab (906:906:906) (987:987:987)) + (PORT datac (560:560:560) (583:583:583)) + (PORT datad (660:660:660) (700:700:700)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (717:717:717) (745:745:745)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1247:1247:1247)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (1271:1271:1271) (1376:1376:1376)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (630:630:630)) + (PORT datac (1101:1101:1101) (1119:1119:1119)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (887:887:887) (910:910:910)) + (PORT datad (351:351:351) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1535:1535:1535)) + (PORT ena (1964:1964:1964) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datad (246:246:246) (319:319:319)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (1077:1077:1077) (1108:1108:1108)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (703:703:703)) + (PORT datac (633:633:633) (654:654:654)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1569:1569:1569) (1588:1588:1588)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (922:922:922) (940:940:940)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (998:998:998)) + (PORT datab (963:963:963) (1015:1015:1015)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (688:688:688) (717:717:717)) + (PORT ena (1179:1179:1179) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (884:884:884) (903:903:903)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (887:887:887) (907:907:907)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (462:462:462)) + (PORT datab (834:834:834) (846:846:846)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (883:883:883)) + (PORT datad (330:330:330) (348:348:348)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1529:1529:1529) (1551:1551:1551)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1527:1527:1527) (1549:1549:1549)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1045:1045:1045)) + (PORT datab (740:740:740) (780:780:780)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1177:1177:1177)) + (PORT datab (1145:1145:1145) (1164:1164:1164)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1129:1129:1129) (1128:1128:1128)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1430:1430:1430) (1432:1432:1432)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (428:428:428) (462:462:462)) + (PORT datad (390:390:390) (417:417:417)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (635:635:635) (667:667:667)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (985:985:985) (1009:1009:1009)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (737:737:737)) + (PORT datab (418:418:418) (485:485:485)) + (PORT datad (686:686:686) (732:732:732)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (643:643:643)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (905:905:905) (928:928:928)) + (PORT datad (629:629:629) (642:642:642)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (886:886:886)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1052:1052:1052) (1054:1054:1054)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (920:920:920) (934:934:934)) + (PORT datac (633:633:633) (644:644:644)) + (PORT datad (1418:1418:1418) (1446:1446:1446)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (679:679:679) (705:705:705)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1300:1300:1300)) + (PORT datab (655:655:655) (670:670:670)) + (PORT datad (650:650:650) (675:675:675)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (663:663:663) (683:683:683)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (723:723:723)) + (PORT datab (810:810:810) (825:825:825)) + (PORT datac (225:225:225) (269:269:269)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datac (1193:1193:1193) (1221:1221:1221)) + (PORT datad (552:552:552) (561:561:561)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (692:692:692)) + (PORT datab (632:632:632) (700:700:700)) + (PORT datac (238:238:238) (328:328:328)) + (PORT datad (622:622:622) (637:637:637)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1311:1311:1311) (1339:1339:1339)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1315:1315:1315) (1344:1344:1344)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1038:1038:1038)) + (PORT datab (743:743:743) (786:786:786)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1168:1168:1168) (1185:1185:1185)) + (PORT ena (1226:1226:1226) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1165:1165:1165) (1181:1181:1181)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (234:234:234) (279:279:279)) + (PORT datad (210:210:210) (241:241:241)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1160:1160:1160) (1180:1180:1180)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (1014:1014:1014)) + (PORT datac (796:796:796) (828:828:828)) + (PORT datad (601:601:601) (628:628:628)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (809:809:809)) + (PORT datab (1367:1367:1367) (1398:1398:1398)) + (PORT datac (1048:1048:1048) (1129:1129:1129)) + (PORT datad (713:713:713) (772:772:772)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (680:680:680)) + (PORT datab (1170:1170:1170) (1204:1204:1204)) + (PORT datac (1149:1149:1149) (1177:1177:1177)) + (PORT datad (827:827:827) (835:835:835)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (889:889:889)) + (PORT datab (1717:1717:1717) (1745:1745:1745)) + (PORT datac (1348:1348:1348) (1452:1452:1452)) + (PORT datad (689:689:689) (739:739:739)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (536:536:536) (567:567:567)) + (PORT ena (1671:1671:1671) (1717:1717:1717)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (345:345:345)) + (PORT datab (280:280:280) (341:341:341)) + (PORT datac (1254:1254:1254) (1299:1299:1299)) + (PORT datad (244:244:244) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (969:969:969)) + (PORT datab (841:841:841) (860:860:860)) + (PORT datac (606:606:606) (645:645:645)) + (PORT datad (781:781:781) (829:829:829)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (642:642:642)) + (PORT datab (681:681:681) (714:714:714)) + (PORT datac (1046:1046:1046) (1072:1072:1072)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1491:1491:1491)) + (PORT datab (839:839:839) (859:859:859)) + (PORT datac (632:632:632) (657:657:657)) + (PORT datad (915:915:915) (974:974:974)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (804:804:804)) + (PORT datac (1048:1048:1048) (1128:1128:1128)) + (PORT datad (711:711:711) (771:771:771)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (422:422:422)) + (PORT datab (882:882:882) (942:942:942)) + (PORT datac (1468:1468:1468) (1500:1500:1500)) + (PORT datad (226:226:226) (265:265:265)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (904:904:904) (945:945:945)) + (PORT datad (337:337:337) (365:365:365)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2567:2567:2567)) + (PORT datab (959:959:959) (1000:1000:1000)) + (PORT datac (1184:1184:1184) (1264:1264:1264)) + (PORT datad (1217:1217:1217) (1295:1295:1295)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (756:756:756)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (926:926:926) (963:963:963)) + (PORT datad (656:656:656) (698:698:698)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (636:636:636) (679:679:679)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (831:831:831)) + (PORT datab (644:644:644) (667:667:667)) + (PORT datac (636:636:636) (665:665:665)) + (PORT datad (531:531:531) (539:539:539)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~0) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (532:532:532)) + (PORT datab (2098:2098:2098) (2171:2171:2171)) + (PORT datac (1131:1131:1131) (1191:1191:1191)) + (PORT datad (1023:1023:1023) (1128:1128:1128)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (902:902:902)) + (PORT datab (1088:1088:1088) (1116:1116:1116)) + (PORT datac (611:611:611) (676:676:676)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1296:1296:1296)) + (PORT datab (1835:1835:1835) (1895:1895:1895)) + (PORT datac (1362:1362:1362) (1393:1393:1393)) + (PORT datad (1227:1227:1227) (1305:1305:1305)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1173:1173:1173)) + (PORT datab (1089:1089:1089) (1116:1116:1116)) + (PORT datac (614:614:614) (674:674:674)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (537:537:537)) + (PORT datab (2096:2096:2096) (2170:2170:2170)) + (PORT datac (1126:1126:1126) (1187:1187:1187)) + (PORT datad (1025:1025:1025) (1130:1130:1130)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (898:898:898)) + (PORT datab (860:860:860) (875:875:875)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (957:957:957)) + (PORT datad (957:957:957) (1062:1062:1062)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (892:892:892)) + (PORT datab (893:893:893) (937:937:937)) + (PORT datac (630:630:630) (666:666:666)) + (PORT datad (611:611:611) (631:631:631)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (875:875:875) (921:921:921)) + (PORT datac (865:865:865) (882:882:882)) + (PORT datad (213:213:213) (247:247:247)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2316:2316:2316) (2437:2437:2437)) + (PORT datab (843:843:843) (864:864:864)) + (PORT datac (1296:1296:1296) (1411:1411:1411)) + (PORT datad (1401:1401:1401) (1447:1447:1447)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (895:895:895)) + (PORT datab (1228:1228:1228) (1263:1263:1263)) + (PORT datac (626:626:626) (663:663:663)) + (PORT datad (615:615:615) (636:636:636)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1358:1358:1358)) + (PORT datab (357:357:357) (391:391:391)) + (PORT datac (1557:1557:1557) (1711:1711:1711)) + (PORT datad (1418:1418:1418) (1491:1491:1491)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (965:965:965)) + (PORT datab (1199:1199:1199) (1296:1296:1296)) + (PORT datac (1945:1945:1945) (2013:2013:2013)) + (PORT datad (898:898:898) (936:936:936)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (640:640:640) (708:708:708)) + (PORT datac (584:584:584) (623:623:623)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1603:1603:1603)) + (PORT datab (1213:1213:1213) (1267:1267:1267)) + (PORT datac (358:358:358) (380:380:380)) + (PORT datad (927:927:927) (963:963:963)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1337:1337:1337) (1352:1352:1352)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1516:1516:1516) (1615:1615:1615)) + (PORT datad (1566:1566:1566) (1661:1661:1661)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (406:406:406)) + (PORT datab (936:936:936) (976:976:976)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1815:1815:1815) (1814:1814:1814)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (922:922:922)) + (PORT datab (933:933:933) (974:974:974)) + (PORT datac (602:602:602) (620:620:620)) + (PORT datad (1828:1828:1828) (1898:1898:1898)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~20) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1067:1067:1067)) + (PORT datab (1009:1009:1009) (1110:1110:1110)) + (PORT datad (2097:2097:2097) (2243:2243:2243)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (883:883:883)) + (PORT datab (854:854:854) (915:915:915)) + (PORT datac (602:602:602) (623:623:623)) + (PORT datad (878:878:878) (919:919:919)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (547:547:547) (576:576:576)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (997:997:997)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datac (208:208:208) (251:251:251)) + (PORT datad (1389:1389:1389) (1443:1443:1443)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (458:458:458)) + (PORT datab (881:881:881) (913:913:913)) + (PORT datac (343:343:343) (369:369:369)) + (PORT datad (1010:1010:1010) (1068:1068:1068)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (991:991:991)) + (PORT datab (671:671:671) (693:693:693)) + (PORT datac (1299:1299:1299) (1337:1337:1337)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (642:642:642) (667:667:667)) + (PORT datac (603:603:603) (622:622:622)) + (PORT datad (612:612:612) (660:660:660)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (539:539:539) (570:570:570)) + (PORT ena (1190:1190:1190) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1269:1269:1269)) + (PORT datab (1182:1182:1182) (1219:1219:1219)) + (PORT datad (580:580:580) (598:598:598)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1199:1199:1199) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (543:543:543) (597:597:597)) + (PORT datad (601:601:601) (622:622:622)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (1171:1171:1171) (1261:1261:1261)) + (PORT datac (180:180:180) (219:219:219)) + (PORT datad (583:583:583) (597:597:597)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (737:737:737)) + (PORT datab (343:343:343) (374:374:374)) + (PORT datac (208:208:208) (248:248:248)) + (PORT datad (607:607:607) (629:629:629)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1514:1514:1514) (1541:1541:1541)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1196:1196:1196) (1227:1227:1227)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (226:226:226) (268:268:268)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1809:1809:1809) (1838:1838:1838)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1810:1810:1810) (1839:1839:1839)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1041:1041:1041)) + (PORT datab (740:740:740) (780:780:780)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (2306:2306:2306) (2350:2350:2350)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (2278:2278:2278) (2302:2302:2302)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datad (661:661:661) (711:711:711)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (2803:2803:2803) (2797:2797:2797)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (394:394:394)) + (PORT datad (938:938:938) (962:962:962)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (315:315:315) (334:334:334)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1179:1179:1179) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (2553:2553:2553) (2567:2567:2567)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (456:456:456)) + (PORT datab (383:383:383) (457:457:457)) + (PORT datad (639:639:639) (653:653:653)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1477:1477:1477)) + (PORT datab (839:839:839) (852:852:852)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (864:864:864) (866:866:866)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (373:373:373)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (2628:2628:2628) (2644:2644:2644)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (963:963:963) (991:991:991)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (736:736:736)) + (PORT datab (727:727:727) (767:767:767)) + (PORT datad (382:382:382) (441:441:441)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (658:658:658)) + (PORT datab (870:870:870) (889:889:889)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (930:930:930)) + (PORT datab (951:951:951) (986:986:986)) + (PORT datac (596:596:596) (616:616:616)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1718:1718:1718) (1746:1746:1746)) + (PORT datab (890:890:890) (903:903:903)) + (PORT datac (873:873:873) (902:902:902)) + (PORT datad (1136:1136:1136) (1145:1145:1145)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (674:674:674)) + (PORT datac (559:559:559) (577:577:577)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1241:1241:1241)) + (PORT datab (707:707:707) (749:749:749)) + (PORT datac (918:918:918) (930:930:930)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (735:735:735)) + (PORT datab (602:602:602) (617:617:617)) + (PORT datac (909:909:909) (942:942:942)) + (PORT datad (835:835:835) (830:830:830)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (528:528:528) (541:541:541)) + (PORT datad (353:353:353) (374:374:374)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1219:1219:1219)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datac (592:592:592) (613:613:613)) + (PORT datad (400:400:400) (447:447:447)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1185:1185:1185)) + (PORT datab (1352:1352:1352) (1463:1463:1463)) + (PORT datac (1461:1461:1461) (1528:1528:1528)) + (PORT datad (1062:1062:1062) (1086:1086:1086)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (992:992:992)) + (PORT datab (215:215:215) (257:257:257)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1167:1167:1167) (1229:1229:1229)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1580:1580:1580)) + (PORT datab (963:963:963) (1020:1020:1020)) + (PORT datac (1687:1687:1687) (1746:1746:1746)) + (PORT datad (215:215:215) (240:240:240)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (309:309:309)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (201:201:201) (230:230:230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1296:1296:1296)) + (PORT datab (1211:1211:1211) (1223:1223:1223)) + (PORT datac (935:935:935) (978:978:978)) + (PORT datad (1331:1331:1331) (1336:1336:1336)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (849:849:849)) + (PORT datab (637:637:637) (662:662:662)) + (PORT datac (838:838:838) (851:851:851)) + (PORT datad (542:542:542) (547:547:547)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1253:1253:1253)) + (PORT datac (2400:2400:2400) (2523:2523:2523)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1336:1336:1336) (1367:1367:1367)) + (PORT datab (924:924:924) (972:972:972)) + (PORT datad (793:793:793) (791:791:791)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1381:1381:1381)) + (PORT datab (658:658:658) (711:711:711)) + (PORT datac (618:618:618) (636:636:636)) + (PORT datad (1741:1741:1741) (1799:1799:1799)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (655:655:655)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (514:514:514) (528:528:528)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (695:695:695)) + (PORT datab (1971:1971:1971) (2032:2032:2032)) + (PORT datac (814:814:814) (830:830:830)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1147:1147:1147)) + (PORT datab (858:858:858) (871:871:871)) + (PORT datac (631:631:631) (646:646:646)) + (PORT datad (697:697:697) (762:762:762)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1620:1620:1620) (1753:1753:1753)) + (PORT datab (1144:1144:1144) (1204:1204:1204)) + (PORT datac (1810:1810:1810) (1924:1924:1924)) + (PORT datad (1650:1650:1650) (1753:1753:1753)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (956:956:956)) + (PORT datab (638:638:638) (664:664:664)) + (PORT datac (202:202:202) (245:245:245)) + (PORT datad (840:840:840) (889:889:889)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1145:1145:1145) (1182:1182:1182)) + (PORT datac (1054:1054:1054) (1068:1068:1068)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1132:1132:1132)) + (PORT datab (1027:1027:1027) (1143:1143:1143)) + (PORT datac (1216:1216:1216) (1293:1293:1293)) + (PORT datad (880:880:880) (901:901:901)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~1) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (1399:1399:1399) (1472:1472:1472)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1821:1821:1821) (1890:1890:1890)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (698:698:698)) + (PORT datab (1971:1971:1971) (2031:2031:2031)) + (PORT datac (330:330:330) (365:365:365)) + (PORT datad (890:890:890) (918:918:918)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1163:1163:1163) (1217:1217:1217)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1677:1677:1677) (1775:1775:1775)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (908:908:908)) + (PORT datab (239:239:239) (320:320:320)) + (PORT datad (840:840:840) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (992:992:992) (1051:1051:1051)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1448:1448:1448)) + (PORT datab (1365:1365:1365) (1445:1445:1445)) + (PORT datad (871:871:871) (897:897:897)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1013:1013:1013) (1061:1061:1061)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1013:1013:1013) (1064:1064:1064)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (982:982:982)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (863:863:863) (895:895:895)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (984:984:984) (1027:1027:1027)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (925:925:925)) + (PORT datab (1233:1233:1233) (1269:1269:1269)) + (PORT datad (911:911:911) (931:931:931)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (665:665:665) (686:686:686)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (327:327:327)) + (PORT datab (457:457:457) (498:498:498)) + (PORT datad (1156:1156:1156) (1206:1206:1206)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1694:1694:1694) (1774:1774:1774)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1694:1694:1694) (1771:1771:1771)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (752:752:752)) + (PORT datab (671:671:671) (717:717:717)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (867:867:867)) + (PORT datab (372:372:372) (396:396:396)) + (PORT datac (616:616:616) (662:662:662)) + (PORT datad (784:784:784) (852:852:852)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1523:1523:1523)) + (PORT asdata (1544:1544:1544) (1603:1603:1603)) + (PORT ena (1490:1490:1490) (1524:1524:1524)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (991:991:991) (1048:1048:1048)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (970:970:970)) + (PORT datab (851:851:851) (954:954:954)) + (PORT datad (991:991:991) (1049:1049:1049)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (443:443:443)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (893:893:893) (915:915:915)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1879:1879:1879) (1962:1962:1962)) + (PORT datab (1315:1315:1315) (1420:1420:1420)) + (PORT datad (1164:1164:1164) (1194:1194:1194)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (487:487:487)) + (PORT datac (1146:1146:1146) (1169:1169:1169)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (712:712:712)) + (PORT datac (641:641:641) (660:660:660)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (671:671:671)) + (PORT datab (896:896:896) (911:911:911)) + (PORT datac (881:881:881) (927:927:927)) + (PORT datad (691:691:691) (749:749:749)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (393:393:393)) + (PORT datab (398:398:398) (437:437:437)) + (PORT datac (1162:1162:1162) (1200:1200:1200)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (756:756:756)) + (PORT datab (605:605:605) (652:652:652)) + (PORT datac (616:616:616) (668:668:668)) + (PORT datad (826:826:826) (847:847:847)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1036:1036:1036)) + (PORT datab (638:638:638) (674:674:674)) + (PORT datac (912:912:912) (963:963:963)) + (PORT datad (654:654:654) (701:701:701)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (267:267:267) (321:321:321)) + (PORT datac (814:814:814) (833:833:833)) + (PORT datad (894:894:894) (933:933:933)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (869:869:869)) + (PORT datac (891:891:891) (917:917:917)) + (PORT datad (1213:1213:1213) (1252:1252:1252)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1212:1212:1212)) + (PORT datac (605:605:605) (646:646:646)) + (PORT datad (813:813:813) (822:822:822)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1210:1210:1210)) + (PORT datab (612:612:612) (655:655:655)) + (PORT datac (831:831:831) (837:837:837)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (612:612:612) (654:654:654)) + (PORT datad (514:514:514) (528:528:528)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1160:1160:1160)) + (PORT datab (261:261:261) (342:342:342)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1809:1809:1809)) + (PORT datab (1020:1020:1020) (1114:1114:1114)) + (PORT datac (1370:1370:1370) (1419:1419:1419)) + (PORT datad (1433:1433:1433) (1514:1514:1514)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1301:1301:1301)) + (PORT datab (1748:1748:1748) (1799:1799:1799)) + (PORT datac (1454:1454:1454) (1621:1621:1621)) + (PORT datad (189:189:189) (223:223:223)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1589:1589:1589) (1734:1734:1734)) + (PORT datab (2048:2048:2048) (2150:2150:2150)) + (PORT datac (1126:1126:1126) (1163:1163:1163)) + (PORT datad (1100:1100:1100) (1161:1161:1161)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (878:878:878)) + (PORT datab (735:735:735) (802:802:802)) + (PORT datac (595:595:595) (614:614:614)) + (PORT datad (1081:1081:1081) (1102:1102:1102)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1381:1381:1381)) + (PORT datab (1727:1727:1727) (1752:1752:1752)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (630:630:630) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1563:1563:1563)) + (PORT datab (2046:2046:2046) (2147:2147:2147)) + (PORT datac (2362:2362:2362) (2509:2509:2509)) + (PORT datad (387:387:387) (405:405:405)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (378:378:378) (401:401:401)) + (PORT datac (851:851:851) (874:874:874)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1104:1104:1104)) + (PORT datab (895:895:895) (915:915:915)) + (PORT datac (867:867:867) (916:916:916)) + (PORT datad (1033:1033:1033) (1062:1062:1062)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (606:606:606)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (633:633:633) (662:662:662)) + (PORT datad (654:654:654) (708:708:708)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (383:383:383)) + (PORT datab (233:233:233) (278:278:278)) + (PORT datac (533:533:533) (537:537:537)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (886:886:886)) + (PORT datab (1000:1000:1000) (1066:1066:1066)) + (PORT datac (2267:2267:2267) (2409:2409:2409)) + (PORT datad (1757:1757:1757) (1881:1881:1881)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (888:888:888)) + (PORT datab (1164:1164:1164) (1205:1205:1205)) + (PORT datac (2266:2266:2266) (2411:2411:2411)) + (PORT datad (1756:1756:1756) (1885:1885:1885)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (889:889:889)) + (PORT datab (1180:1180:1180) (1219:1219:1219)) + (PORT datac (2266:2266:2266) (2410:2410:2410)) + (PORT datad (1756:1756:1756) (1883:1883:1883)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (915:915:915)) + (PORT datac (774:774:774) (785:785:785)) + (PORT datad (1034:1034:1034) (1051:1051:1051)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (955:955:955) (1006:1006:1006)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (536:536:536)) + (PORT datab (2097:2097:2097) (2166:2166:2166)) + (PORT datac (1127:1127:1127) (1184:1184:1184)) + (PORT datad (1028:1028:1028) (1134:1134:1134)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (662:662:662)) + (PORT datab (2979:2979:2979) (3106:3106:3106)) + (PORT datac (568:568:568) (583:583:583)) + (PORT datad (1340:1340:1340) (1383:1383:1383)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1017:1017:1017)) + (PORT datab (620:620:620) (646:646:646)) + (PORT datad (507:507:507) (522:522:522)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1001:1001:1001)) + (PORT datab (1478:1478:1478) (1557:1557:1557)) + (PORT datac (2332:2332:2332) (2440:2440:2440)) + (PORT datad (1745:1745:1745) (1802:1802:1802)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1105:1105:1105)) + (PORT datab (874:874:874) (922:922:922)) + (PORT datac (866:866:866) (915:915:915)) + (PORT datad (1088:1088:1088) (1120:1120:1120)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (312:312:312)) + (PORT datab (960:960:960) (1016:1016:1016)) + (PORT datac (613:613:613) (627:627:627)) + (PORT datad (836:836:836) (845:845:845)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1742:1742:1742) (1825:1825:1825)) + (PORT datab (1546:1546:1546) (1654:1654:1654)) + (PORT datac (351:351:351) (378:378:378)) + (PORT datad (2479:2479:2479) (2584:2584:2584)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (931:931:931) (960:960:960)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (229:229:229) (270:270:270)) + (PORT datac (802:802:802) (798:798:798)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (892:892:892)) + (PORT datab (873:873:873) (943:943:943)) + (PORT datac (2267:2267:2267) (2412:2412:2412)) + (PORT datad (1757:1757:1757) (1887:1887:1887)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1001:1001:1001)) + (PORT datab (917:917:917) (961:961:961)) + (PORT datac (2331:2331:2331) (2438:2438:2438)) + (PORT datad (1442:1442:1442) (1517:1517:1517)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1704:1704:1704) (1753:1753:1753)) + (PORT datab (947:947:947) (1020:1020:1020)) + (PORT datac (945:945:945) (1014:1014:1014)) + (PORT datad (1635:1635:1635) (1701:1701:1701)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (884:884:884) (907:907:907)) + (PORT datac (315:315:315) (342:342:342)) + (PORT datad (214:214:214) (249:249:249)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1339:1339:1339)) + (PORT datab (427:427:427) (483:483:483)) + (PORT datac (349:349:349) (378:378:378)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1177:1177:1177)) + (PORT datab (800:800:800) (828:828:828)) + (PORT datac (610:610:610) (675:675:675)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1165:1165:1165) (1217:1217:1217)) + (PORT datad (518:518:518) (525:525:525)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (815:815:815) (826:826:826)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (884:884:884)) + (PORT datab (609:609:609) (648:648:648)) + (PORT datac (1307:1307:1307) (1381:1381:1381)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1755:1755:1755) (1815:1815:1815)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (561:561:561) (578:578:578)) + (PORT datad (611:611:611) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (858:858:858) (943:943:943)) + (PORT datac (1717:1717:1717) (1775:1775:1775)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1750:1750:1750) (1808:1808:1808)) + (PORT datab (1443:1443:1443) (1484:1484:1484)) + (PORT datac (608:608:608) (634:634:634)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (268:268:268)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (814:814:814) (866:866:866)) + (PORT datad (222:222:222) (251:251:251)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1002:1002:1002) (1030:1030:1030)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1476:1476:1476)) + (PORT datab (1716:1716:1716) (1764:1764:1764)) + (PORT datac (359:359:359) (385:385:385)) + (PORT datad (1180:1180:1180) (1205:1205:1205)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (657:657:657) (711:711:711)) + (PORT datac (1392:1392:1392) (1457:1457:1457)) + (PORT datad (1097:1097:1097) (1132:1132:1132)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (612:612:612)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (1195:1195:1195) (1213:1213:1213)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (626:626:626) (693:693:693)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (997:997:997)) + (PORT datab (1414:1414:1414) (1480:1480:1480)) + (PORT datac (362:362:362) (386:386:386)) + (PORT datad (1182:1182:1182) (1203:1203:1203)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datab (1242:1242:1242) (1340:1340:1340)) + (PORT datac (896:896:896) (957:957:957)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (308:308:308)) + (PORT datab (939:939:939) (996:996:996)) + (PORT datac (525:525:525) (543:543:543)) + (PORT datad (923:923:923) (981:981:981)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (265:265:265)) + (PORT datab (1156:1156:1156) (1191:1191:1191)) + (PORT datac (837:837:837) (880:880:880)) + (PORT datad (658:658:658) (709:709:709)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (934:934:934)) + (PORT datab (882:882:882) (910:910:910)) + (PORT datac (411:411:411) (449:449:449)) + (PORT datad (1010:1010:1010) (1065:1065:1065)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (407:407:407)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (221:221:221) (249:249:249)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (698:698:698)) + (PORT datab (684:684:684) (738:738:738)) + (PORT datac (963:963:963) (1025:1025:1025)) + (PORT datad (1419:1419:1419) (1496:1496:1496)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (2135:2135:2135) (2284:2284:2284)) + (PORT datab (1448:1448:1448) (1506:1506:1506)) + (PORT datac (981:981:981) (1074:1074:1074)) + (PORT datad (1424:1424:1424) (1498:1498:1498)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (412:412:412)) + (PORT datab (400:400:400) (427:427:427)) + (PORT datac (1192:1192:1192) (1207:1207:1207)) + (PORT datad (339:339:339) (359:359:359)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1356:1356:1356)) + (PORT datab (1098:1098:1098) (1140:1140:1140)) + (PORT datac (333:333:333) (361:361:361)) + (PORT datad (1161:1161:1161) (1189:1189:1189)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1356:1356:1356)) + (PORT datab (1577:1577:1577) (1688:1688:1688)) + (PORT datac (1501:1501:1501) (1638:1638:1638)) + (PORT datad (1157:1157:1157) (1187:1187:1187)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (958:958:958)) + (PORT datab (1318:1318:1318) (1360:1360:1360)) + (PORT datac (337:337:337) (364:364:364)) + (PORT datad (1216:1216:1216) (1284:1284:1284)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1252:1252:1252) (1322:1322:1322)) + (PORT datac (615:615:615) (683:683:683)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1319:1319:1319)) + (PORT datab (904:904:904) (946:946:946)) + (PORT datac (1503:1503:1503) (1640:1640:1640)) + (PORT datad (1230:1230:1230) (1314:1314:1314)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (202:202:202) (247:247:247)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (765:765:765)) + (PORT datab (1594:1594:1594) (1708:1708:1708)) + (PORT datac (1547:1547:1547) (1688:1688:1688)) + (PORT datad (1542:1542:1542) (1718:1718:1718)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1103:1103:1103) (1170:1170:1170)) + (PORT datac (818:818:818) (866:866:866)) + (PORT datad (1175:1175:1175) (1203:1203:1203)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (853:853:853)) + (PORT datab (1190:1190:1190) (1211:1211:1211)) + (PORT datac (532:532:532) (545:545:545)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (893:893:893)) + (PORT datab (859:859:859) (901:901:901)) + (PORT datad (1510:1510:1510) (1557:1557:1557)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (373:373:373)) + (PORT datab (1215:1215:1215) (1271:1271:1271)) + (PORT datac (1945:1945:1945) (2016:2016:2016)) + (PORT datad (928:928:928) (969:969:969)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (470:470:470)) + (PORT datab (636:636:636) (673:673:673)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (339:339:339) (360:360:360)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (769:769:769) (826:826:826)) + (PORT datac (365:365:365) (399:399:399)) + (PORT datad (790:790:790) (788:788:788)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (658:658:658) (693:693:693)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (869:869:869)) + (PORT datac (595:595:595) (635:635:635)) + (PORT datad (908:908:908) (970:970:970)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (674:674:674)) + (PORT datab (830:830:830) (872:872:872)) + (PORT datac (1421:1421:1421) (1450:1450:1450)) + (PORT datad (1110:1110:1110) (1142:1142:1142)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (951:951:951) (1010:1010:1010)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (769:769:769)) + (PORT datab (1236:1236:1236) (1290:1290:1290)) + (PORT datac (1164:1164:1164) (1215:1215:1215)) + (PORT datad (1047:1047:1047) (1125:1125:1125)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (855:855:855) (880:880:880)) + (PORT datac (1140:1140:1140) (1172:1172:1172)) + (PORT datad (874:874:874) (902:902:902)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (865:865:865)) + (PORT datac (398:398:398) (460:460:460)) + (PORT datad (368:368:368) (427:427:427)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (732:732:732) (788:788:788)) + (PORT datac (676:676:676) (729:729:729)) + (PORT datad (1051:1051:1051) (1126:1126:1126)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1120:1120:1120)) + (PORT datab (235:235:235) (277:277:277)) + (PORT datac (795:795:795) (801:801:801)) + (PORT datad (826:826:826) (840:840:840)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (419:419:419)) + (PORT datab (576:576:576) (598:598:598)) + (PORT datac (1361:1361:1361) (1381:1381:1381)) + (PORT datad (1131:1131:1131) (1200:1200:1200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (265:265:265)) + (PORT datab (876:876:876) (905:905:905)) + (PORT datac (1765:1765:1765) (1884:1884:1884)) + (PORT datad (1357:1357:1357) (1370:1370:1370)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2267:2267:2267) (2306:2306:2306)) + (PORT datab (2862:2862:2862) (2989:2989:2989)) + (PORT datac (972:972:972) (1039:1039:1039)) + (PORT datad (1353:1353:1353) (1367:1367:1367)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (934:934:934)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1325:1325:1325)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (814:814:814) (885:885:885)) + (PORT datad (605:605:605) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1065:1065:1065)) + (PORT datab (260:260:260) (341:341:341)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (915:915:915)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (880:880:880) (897:897:897)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (896:896:896)) + (PORT datac (850:850:850) (889:889:889)) + (PORT datad (863:863:863) (925:925:925)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (943:943:943)) + (PORT datac (616:616:616) (628:628:628)) + (PORT datad (362:362:362) (389:389:389)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (915:915:915)) + (PORT datab (1202:1202:1202) (1257:1257:1257)) + (PORT datac (1151:1151:1151) (1179:1179:1179)) + (PORT datad (822:822:822) (839:839:839)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (1143:1143:1143) (1176:1176:1176)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (719:719:719)) + (PORT datab (703:703:703) (760:760:760)) + (PORT datac (575:575:575) (604:604:604)) + (PORT datad (1035:1035:1035) (1052:1052:1052)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (264:264:264)) + (PORT datac (603:603:603) (612:612:612)) + (PORT datad (362:362:362) (386:386:386)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (262:262:262)) + (PORT datab (748:748:748) (806:806:806)) + (PORT datac (1048:1048:1048) (1127:1127:1127)) + (PORT datad (697:697:697) (755:755:755)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (910:910:910)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (339:339:339) (359:359:359)) + (PORT datad (190:190:190) (226:226:226)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (807:807:807)) + (PORT datab (1353:1353:1353) (1372:1372:1372)) + (PORT datac (1225:1225:1225) (1346:1346:1346)) + (PORT datad (667:667:667) (718:718:718)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (354:354:354)) + (PORT datab (287:287:287) (349:349:349)) + (PORT datad (246:246:246) (289:289:289)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (442:442:442)) + (PORT datab (392:392:392) (422:422:422)) + (PORT datac (1398:1398:1398) (1449:1449:1449)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1459:1459:1459)) + (PORT datac (1119:1119:1119) (1171:1171:1171)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (890:890:890) (903:903:903)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1827:1827:1827) (1910:1910:1910)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1827:1827:1827) (1909:1909:1909)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (905:905:905)) + (PORT datab (416:416:416) (502:502:502)) + (PORT datad (838:838:838) (853:853:853)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (2043:2043:2043) (2144:2144:2144)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (817:817:817) (874:874:874)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (748:748:748)) + (PORT datab (672:672:672) (717:717:717)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1660:1660:1660) (1702:1702:1702)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1199:1199:1199)) + (PORT datab (1237:1237:1237) (1263:1263:1263)) + (PORT datad (861:861:861) (878:878:878)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2046:2046:2046) (2144:2144:2144)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1727:1727:1727) (1806:1806:1806)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (704:704:704)) + (PORT datab (457:457:457) (504:504:504)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1444:1444:1444) (1514:1514:1514)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1444:1444:1444) (1514:1514:1514)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (978:978:978)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datad (864:864:864) (894:894:894)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (864:864:864)) + (PORT datab (557:557:557) (592:592:592)) + (PORT datac (987:987:987) (1031:1031:1031)) + (PORT datad (355:355:355) (385:385:385)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1187:1187:1187) (1228:1228:1228)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1446:1446:1446)) + (PORT datab (1368:1368:1368) (1449:1449:1449)) + (PORT datad (870:870:870) (894:894:894)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1829:1829:1829) (1915:1915:1915)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1183:1183:1183) (1224:1224:1224)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (972:972:972)) + (PORT datab (652:652:652) (743:743:743)) + (PORT datad (991:991:991) (1047:1047:1047)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (416:416:416)) + (PORT datab (794:794:794) (835:835:835)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (602:602:602)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (638:638:638) (673:673:673)) + (PORT datad (816:816:816) (866:866:866)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1239:1239:1239)) + (PORT datab (1314:1314:1314) (1418:1418:1418)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (359:359:359)) + (PORT datac (1100:1100:1100) (1117:1117:1117)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (746:746:746)) + (PORT datab (711:711:711) (789:789:789)) + (PORT datac (815:815:815) (841:841:841)) + (PORT datad (600:600:600) (645:645:645)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1194:1194:1194) (1236:1236:1236)) + (PORT datac (663:663:663) (703:703:703)) + (PORT datad (370:370:370) (397:397:397)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datac (1191:1191:1191) (1217:1217:1217)) + (PORT datad (603:603:603) (619:619:619)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1664:1664:1664) (1739:1739:1739)) + (PORT datab (655:655:655) (701:701:701)) + (PORT datac (1073:1073:1073) (1116:1116:1116)) + (PORT datad (642:642:642) (700:700:700)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (711:711:711)) + (PORT datad (329:329:329) (352:352:352)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1152:1152:1152)) + (PORT datab (651:651:651) (697:697:697)) + (PORT datac (866:866:866) (925:925:925)) + (PORT datad (1624:1624:1624) (1694:1694:1694)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (691:691:691)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (918:918:918) (968:968:968)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (703:703:703) (732:732:732)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1246:1246:1246)) + (PORT datab (1309:1309:1309) (1415:1415:1415)) + (PORT datad (1072:1072:1072) (1106:1106:1106)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (394:394:394)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (1105:1105:1105) (1124:1124:1124)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (686:686:686)) + (PORT datab (1193:1193:1193) (1230:1230:1230)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (375:375:375) (400:400:400)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (939:939:939) (974:974:974)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (939:939:939) (973:973:973)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (328:328:328)) + (PORT datab (244:244:244) (290:290:290)) + (PORT datad (555:555:555) (562:562:562)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1476:1476:1476) (1502:1502:1502)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1476:1476:1476) (1503:1503:1503)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (977:977:977)) + (PORT datab (896:896:896) (932:932:932)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (903:903:903) (914:914:914)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (458:458:458) (497:497:497)) + (PORT datad (1153:1153:1153) (1204:1204:1204)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (951:951:951) (994:994:994)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (951:951:951) (992:992:992)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (754:754:754)) + (PORT datab (669:669:669) (714:714:714)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (967:967:967) (1020:1020:1020)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (924:924:924)) + (PORT datab (1235:1235:1235) (1261:1261:1261)) + (PORT datad (862:862:862) (875:875:875)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (637:637:637)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (541:541:541) (569:569:569)) + (PORT datad (577:577:577) (615:615:615)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (972:972:972) (1023:1023:1023)) + (PORT ena (1471:1471:1471) (1443:1443:1443)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (857:857:857)) + (PORT datab (1177:1177:1177) (1217:1217:1217)) + (PORT datad (1321:1321:1321) (1366:1366:1366)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1368:1368:1368) (1440:1440:1440)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1366:1366:1366) (1439:1439:1439)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (905:905:905)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (840:840:840) (849:849:849)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1121:1121:1121)) + (PORT datab (637:637:637) (685:685:685)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (577:577:577) (594:594:594)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (750:750:750)) + (PORT datab (666:666:666) (687:687:687)) + (PORT datac (619:619:619) (669:669:669)) + (PORT datad (629:629:629) (668:668:668)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (750:750:750)) + (PORT datab (798:798:798) (816:816:816)) + (PORT datac (920:920:920) (972:972:972)) + (PORT datad (1484:1484:1484) (1552:1552:1552)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (981:981:981)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (367:367:367) (406:406:406)) + (PORT datad (321:321:321) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (377:377:377)) + (PORT datab (371:371:371) (416:416:416)) + (PORT datac (1351:1351:1351) (1382:1382:1382)) + (PORT datad (1525:1525:1525) (1547:1547:1547)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (655:655:655)) + (PORT datab (1372:1372:1372) (1425:1425:1425)) + (PORT datac (571:571:571) (593:593:593)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (677:677:677)) + (PORT datab (1176:1176:1176) (1233:1233:1233)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (327:327:327) (353:353:353)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (829:829:829) (864:864:864)) + (PORT datac (632:632:632) (658:658:658)) + (PORT datad (913:913:913) (970:970:970)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (1076:1076:1076) (1163:1163:1163)) + (PORT datac (868:868:868) (938:938:938)) + (PORT datad (1124:1124:1124) (1196:1196:1196)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (939:939:939)) + (PORT datab (226:226:226) (267:267:267)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (926:926:926)) + (PORT datab (897:897:897) (965:965:965)) + (PORT datac (828:828:828) (860:860:860)) + (PORT datad (871:871:871) (877:877:877)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (881:881:881)) + (PORT datab (394:394:394) (422:422:422)) + (PORT datac (598:598:598) (612:612:612)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (925:925:925)) + (PORT datab (395:395:395) (422:422:422)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1677:1677:1677) (1734:1734:1734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1283:1283:1283)) + (PORT datab (1204:1204:1204) (1256:1256:1256)) + (PORT datac (673:673:673) (737:737:737)) + (PORT datad (1047:1047:1047) (1127:1127:1127)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (916:916:916)) + (PORT datab (855:855:855) (878:878:878)) + (PORT datac (1138:1138:1138) (1173:1173:1173)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1487:1487:1487)) + (PORT datab (1717:1717:1717) (1746:1746:1746)) + (PORT datac (869:869:869) (939:939:939)) + (PORT datad (380:380:380) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (280:280:280) (340:340:340)) + (PORT datad (244:244:244) (286:286:286)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (341:341:341)) + (PORT datab (570:570:570) (585:585:585)) + (PORT datac (1251:1251:1251) (1294:1294:1294)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (965:965:965)) + (PORT datac (380:380:380) (437:437:437)) + (PORT datad (785:785:785) (837:837:837)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1268:1268:1268)) + (PORT datab (899:899:899) (907:907:907)) + (PORT datac (816:816:816) (833:833:833)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (701:701:701) (728:728:728)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1540:1540:1540) (1612:1612:1612)) + (PORT datab (1314:1314:1314) (1418:1418:1418)) + (PORT datad (1164:1164:1164) (1193:1193:1193)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1211:1211:1211)) + (PORT datab (600:600:600) (671:671:671)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (890:890:890) (913:913:913)) + (PORT datad (543:543:543) (557:557:557)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1535:1535:1535)) + (PORT ena (1964:1964:1964) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (689:689:689)) + (PORT datab (927:927:927) (981:981:981)) + (PORT datac (612:612:612) (646:646:646)) + (PORT datad (1031:1031:1031) (1050:1050:1050)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (912:912:912)) + (PORT datab (1057:1057:1057) (1087:1087:1087)) + (PORT datac (241:241:241) (328:328:328)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (371:371:371)) + (PORT datab (397:397:397) (437:437:437)) + (PORT datac (1155:1155:1155) (1195:1195:1195)) + (PORT datad (569:569:569) (590:590:590)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1705:1705:1705) (1755:1755:1755)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1451:1451:1451)) + (PORT datab (1365:1365:1365) (1446:1446:1446)) + (PORT datad (870:870:870) (899:899:899)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1207:1207:1207) (1259:1259:1259)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1210:1210:1210) (1263:1263:1263)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (910:910:910)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (841:841:841) (856:856:856)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (928:928:928) (941:941:941)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1706:1706:1706) (1752:1752:1752)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (968:968:968)) + (PORT datab (652:652:652) (743:743:743)) + (PORT datad (993:993:993) (1050:1050:1050)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1843:1843:1843) (1900:1900:1900)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1842:1842:1842) (1899:1899:1899)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (978:978:978)) + (PORT datab (898:898:898) (931:931:931)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (915:915:915) (929:929:929)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (458:458:458) (504:504:504)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (910:910:910) (941:941:941)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1455:1455:1455) (1536:1536:1536)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (753:753:753)) + (PORT datab (672:672:672) (718:718:718)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1467:1467:1467) (1513:1513:1513)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (908:908:908)) + (PORT datab (1241:1241:1241) (1274:1274:1274)) + (PORT datad (892:892:892) (907:907:907)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (824:824:824)) + (PORT datab (639:639:639) (681:681:681)) + (PORT datac (779:779:779) (834:834:834)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (369:369:369) (407:407:407)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (695:695:695)) + (PORT datab (645:645:645) (697:697:697)) + (PORT datac (689:689:689) (718:718:718)) + (PORT datad (592:592:592) (625:625:625)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (757:757:757)) + (PORT datab (908:908:908) (979:979:979)) + (PORT datac (911:911:911) (962:962:962)) + (PORT datad (597:597:597) (623:623:623)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (269:269:269) (325:325:325)) + (PORT datac (1134:1134:1134) (1152:1152:1152)) + (PORT datad (901:901:901) (943:943:943)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1701:1701:1701) (1725:1725:1725)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (893:893:893) (910:910:910)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (616:616:616)) + (PORT datab (675:675:675) (705:705:705)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (832:832:832) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1481:1481:1481)) + (PORT datab (620:620:620) (660:660:660)) + (PORT datac (803:803:803) (837:837:837)) + (PORT datad (838:838:838) (866:866:866)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (943:943:943) (1004:1004:1004)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (262:262:262) (343:343:343)) + (PORT datac (236:236:236) (311:311:311)) + (PORT datad (236:236:236) (304:304:304)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (497:497:497)) + (PORT datab (262:262:262) (344:344:344)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (623:623:623)) + (PORT datab (714:714:714) (802:802:802)) + (PORT datac (1145:1145:1145) (1194:1194:1194)) + (PORT datad (546:546:546) (563:563:563)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (839:839:839)) + (PORT datab (851:851:851) (859:859:859)) + (PORT datac (637:637:637) (660:660:660)) + (PORT datad (775:775:775) (832:832:832)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (280:280:280)) + (PORT datab (244:244:244) (326:326:326)) + (PORT datac (682:682:682) (738:738:738)) + (PORT datad (1165:1165:1165) (1175:1175:1175)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (953:953:953)) + (PORT datab (893:893:893) (914:914:914)) + (PORT datac (1084:1084:1084) (1122:1122:1122)) + (PORT datad (1137:1137:1137) (1155:1155:1155)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (600:600:600)) + (PORT datab (1111:1111:1111) (1166:1166:1166)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (575:575:575) (569:569:569)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (399:399:399)) + (PORT datab (242:242:242) (287:287:287)) + (PORT datac (674:674:674) (702:702:702)) + (PORT datad (565:565:565) (579:579:579)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1703:1703:1703)) + (PORT datab (427:427:427) (459:459:459)) + (PORT datad (771:771:771) (795:795:795)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1161:1161:1161) (1182:1182:1182)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (937:937:937) (960:960:960)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (700:700:700) (715:715:715)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (214:214:214) (240:240:240)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (459:459:459)) + (PORT datab (836:836:836) (851:851:851)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (626:626:626) (660:660:660)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1545:1545:1545) (1565:1565:1565)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (731:731:731)) + (PORT datab (387:387:387) (460:460:460)) + (PORT datad (687:687:687) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (365:365:365)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (563:563:563) (582:582:582)) + (PORT datad (789:789:789) (793:793:793)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1295:1295:1295) (1325:1325:1325)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1297:1297:1297) (1327:1327:1327)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (999:999:999)) + (PORT datab (963:963:963) (1015:1015:1015)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (394:394:394)) + (PORT datab (665:665:665) (698:698:698)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (929:929:929)) + (PORT datab (951:951:951) (986:986:986)) + (PORT datac (831:831:831) (844:844:844)) + (PORT datad (586:586:586) (603:603:603)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (671:671:671) (691:691:691)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1299:1299:1299)) + (PORT datab (973:973:973) (979:979:979)) + (PORT datad (649:649:649) (674:674:674)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (326:326:326)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (663:663:663) (680:680:680)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (720:720:720)) + (PORT datab (634:634:634) (649:649:649)) + (PORT datac (227:227:227) (272:272:272)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datac (1195:1195:1195) (1224:1224:1224)) + (PORT datad (529:529:529) (540:540:540)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (267:267:267) (363:363:363)) + (PORT datab (859:859:859) (884:884:884)) + (PORT datac (1099:1099:1099) (1165:1165:1165)) + (PORT datad (1364:1364:1364) (1395:1395:1395)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1254:1254:1254) (1282:1282:1282)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1255:1255:1255) (1284:1284:1284)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1045:1045:1045)) + (PORT datab (740:740:740) (781:781:781)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (801:801:801) (810:810:810)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1415:1415:1415) (1428:1428:1428)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (462:462:462)) + (PORT datab (423:423:423) (459:459:459)) + (PORT datad (387:387:387) (414:414:414)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1520:1520:1520) (1543:1543:1543)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (993:993:993) (1036:1036:1036)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (962:962:962)) + (PORT datab (680:680:680) (731:731:731)) + (PORT datad (600:600:600) (652:652:652)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1705:1705:1705)) + (PORT datab (630:630:630) (658:658:658)) + (PORT datac (882:882:882) (926:926:926)) + (PORT datad (1068:1068:1068) (1072:1072:1072)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1203:1203:1203) (1240:1240:1240)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (450:450:450)) + (PORT datab (711:711:711) (763:763:763)) + (PORT datad (636:636:636) (686:686:686)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (695:695:695)) + (PORT datab (598:598:598) (612:612:612)) + (PORT datac (571:571:571) (595:595:595)) + (PORT datad (606:606:606) (617:617:617)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1256:1256:1256) (1274:1274:1274)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1257:1257:1257) (1276:1276:1276)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1000:1000:1000)) + (PORT datab (966:966:966) (1018:1018:1018)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (991:991:991) (1033:1033:1033)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1517:1517:1517) (1540:1540:1540)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (735:735:735)) + (PORT datab (421:421:421) (485:485:485)) + (PORT datad (688:688:688) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (368:368:368)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (925:925:925)) + (PORT datab (920:920:920) (943:943:943)) + (PORT datac (918:918:918) (946:946:946)) + (PORT datad (887:887:887) (901:901:901)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (536:536:536) (567:567:567)) + (PORT ena (1190:1190:1190) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1268:1268:1268)) + (PORT datab (940:940:940) (988:988:988)) + (PORT datad (582:582:582) (598:598:598)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1199:1199:1199) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (668:668:668)) + (PORT datac (316:316:316) (336:336:336)) + (PORT datad (355:355:355) (415:415:415)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1441:1441:1441)) + (PORT datab (632:632:632) (702:702:702)) + (PORT datac (1097:1097:1097) (1164:1164:1164)) + (PORT datad (833:833:833) (846:846:846)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (480:480:480)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (633:633:633) (655:655:655)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (657:657:657) (693:693:693)) + (PORT datad (608:608:608) (631:631:631)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (1222:1222:1222) (1253:1253:1253)) + (PORT datad (639:639:639) (661:661:661)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1291:1291:1291)) + (PORT datab (1213:1213:1213) (1307:1307:1307)) + (PORT datac (591:591:591) (647:647:647)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (695:695:695)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (645:645:645) (708:708:708)) + (PORT datad (540:540:540) (553:553:553)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1199:1199:1199) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1223:1223:1223) (1253:1253:1253)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1221:1221:1221) (1252:1252:1252)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1046:1046:1046)) + (PORT datab (741:741:741) (777:777:777)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1236:1236:1236) (1259:1259:1259)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1236:1236:1236) (1262:1262:1262)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1000:1000:1000)) + (PORT datab (967:967:967) (1018:1018:1018)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1223:1223:1223) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1401:1401:1401)) + (PORT datab (646:646:646) (665:665:665)) + (PORT datac (214:214:214) (289:289:289)) + (PORT datad (771:771:771) (793:793:793)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1239:1239:1239) (1275:1275:1275)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1202:1202:1202) (1229:1229:1229)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (957:957:957)) + (PORT datab (680:680:680) (727:727:727)) + (PORT datad (380:380:380) (443:443:443)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1160:1160:1160) (1165:1165:1165)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1386:1386:1386) (1381:1381:1381)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (477:477:477)) + (PORT datab (425:425:425) (463:463:463)) + (PORT datad (386:386:386) (416:416:416)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1388:1388:1388) (1381:1381:1381)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datad (932:932:932) (957:957:957)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1203:1203:1203) (1232:1232:1232)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1240:1240:1240) (1275:1275:1275)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (732:732:732)) + (PORT datab (390:390:390) (467:467:467)) + (PORT datad (687:687:687) (727:727:727)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (899:899:899) (924:924:924)) + (PORT datac (597:597:597) (617:617:617)) + (PORT datad (861:861:861) (881:881:881)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (601:601:601) (618:618:618)) + (PORT datac (599:599:599) (618:618:618)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (609:609:609)) + (PORT datab (842:842:842) (863:863:863)) + (PORT datac (1082:1082:1082) (1103:1103:1103)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (870:870:870) (888:888:888)) + (PORT ena (1190:1190:1190) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1262:1262:1262)) + (PORT datab (923:923:923) (982:982:982)) + (PORT datad (585:585:585) (603:603:603)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (333:333:333)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (601:601:601) (626:626:626)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (1069:1069:1069) (1087:1087:1087)) + (PORT datac (657:657:657) (692:692:692)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT datac (1351:1351:1351) (1346:1346:1346)) + (PORT datad (1841:1841:1841) (1843:1843:1843)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (716:716:716) (738:738:738)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (689:689:689)) + (PORT datab (928:928:928) (981:981:981)) + (PORT datac (613:613:613) (646:646:646)) + (PORT datad (1031:1031:1031) (1050:1050:1050)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1188:1188:1188) (1235:1235:1235)) + (PORT datac (362:362:362) (388:388:388)) + (PORT datad (369:369:369) (398:398:398)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1214:1214:1214) (1231:1231:1231)) + (PORT ena (1471:1471:1471) (1443:1443:1443)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1213:1213:1213) (1240:1240:1240)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1213:1213:1213) (1239:1239:1239)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (907:907:907)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (837:837:837) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1193:1193:1193) (1217:1217:1217)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1194:1194:1194) (1217:1217:1217)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1231:1231:1231)) + (PORT datab (581:581:581) (610:610:610)) + (PORT datad (1141:1141:1141) (1207:1207:1207)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (839:839:839)) + (PORT datab (245:245:245) (290:290:290)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (979:979:979) (990:990:990)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (981:981:981) (992:992:992)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (463:463:463) (500:500:500)) + (PORT datad (1156:1156:1156) (1206:1206:1206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (992:992:992) (1025:1025:1025)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (989:989:989) (1023:1023:1023)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (975:975:975)) + (PORT datab (897:897:897) (928:928:928)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1702:1702:1702) (1716:1716:1716)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1175:1175:1175) (1207:1207:1207)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (755:755:755)) + (PORT datab (668:668:668) (708:708:708)) + (PORT datad (399:399:399) (467:467:467)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1216:1216:1216) (1232:1232:1232)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (923:923:923)) + (PORT datab (1238:1238:1238) (1265:1265:1265)) + (PORT datad (865:865:865) (879:879:879)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (412:412:412)) + (PORT datab (637:637:637) (665:665:665)) + (PORT datac (341:341:341) (372:372:372)) + (PORT datad (604:604:604) (642:642:642)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (660:660:660) (751:751:751)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (711:711:711)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (373:373:373) (404:404:404)) + (PORT datad (625:625:625) (637:637:637)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (936:936:936)) + (PORT datab (615:615:615) (652:652:652)) + (PORT datac (215:215:215) (248:248:248)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1245:1245:1245)) + (PORT datab (268:268:268) (324:324:324)) + (PORT datac (567:567:567) (591:591:591)) + (PORT datad (899:899:899) (939:939:939)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (389:389:389) (417:417:417)) + (PORT datac (1401:1401:1401) (1448:1448:1448)) + (PORT datad (593:593:593) (612:612:612)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1377:1377:1377) (1414:1414:1414)) + (PORT datac (363:363:363) (396:396:396)) + (PORT datad (1524:1524:1524) (1552:1552:1552)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (639:639:639)) + (PORT datac (650:650:650) (679:679:679)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (983:983:983)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (674:674:674) (690:690:690)) + (PORT datad (242:242:242) (281:281:281)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (738:738:738)) + (PORT datab (1197:1197:1197) (1242:1242:1242)) + (PORT datac (2792:2792:2792) (2903:2903:2903)) + (PORT datad (814:814:814) (834:834:834)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1538:1538:1538) (1609:1609:1609)) + (PORT datab (963:963:963) (1037:1037:1037)) + (PORT datac (2790:2790:2790) (2900:2900:2900)) + (PORT datad (1212:1212:1212) (1250:1250:1250)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~3) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1496:1496:1496) (1568:1568:1568)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (424:424:424)) + (PORT datac (1399:1399:1399) (1448:1448:1448)) + (PORT datad (750:750:750) (753:753:753)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (388:388:388) (421:421:421)) + (PORT datac (1350:1350:1350) (1379:1379:1379)) + (PORT datad (1525:1525:1525) (1551:1551:1551)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (865:865:865)) + (PORT datab (906:906:906) (931:931:931)) + (PORT datac (399:399:399) (460:460:460)) + (PORT datad (368:368:368) (426:426:426)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (907:907:907)) + (PORT datac (612:612:612) (623:623:623)) + (PORT datad (358:358:358) (384:384:384)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (913:913:913)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (582:582:582) (596:596:596)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (950:950:950) (958:958:958)) + (PORT ena (1677:1677:1677) (1734:1734:1734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (347:347:347)) + (PORT datab (279:279:279) (339:339:339)) + (PORT datac (1254:1254:1254) (1299:1299:1299)) + (PORT datad (243:243:243) (284:284:284)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (987:987:987)) + (PORT datab (1720:1720:1720) (1750:1750:1750)) + (PORT datac (1344:1344:1344) (1447:1447:1447)) + (PORT datad (371:371:371) (430:430:430)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (969:969:969)) + (PORT datab (614:614:614) (669:669:669)) + (PORT datac (797:797:797) (851:851:851)) + (PORT datad (806:806:806) (809:809:809)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (637:637:637) (653:653:653)) + (PORT datac (646:646:646) (672:672:672)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1104:1104:1104)) + (PORT datab (900:900:900) (936:936:936)) + (PORT datac (1171:1171:1171) (1223:1223:1223)) + (PORT datad (816:816:816) (830:830:830)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datac (1142:1142:1142) (1176:1176:1176)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (502:502:502)) + (PORT datab (1711:1711:1711) (1740:1740:1740)) + (PORT datac (676:676:676) (729:729:729)) + (PORT datad (1522:1522:1522) (1638:1638:1638)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (410:410:410)) + (PORT datac (1398:1398:1398) (1447:1447:1447)) + (PORT datad (320:320:320) (343:343:343)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1254:1254:1254)) + (PORT datab (1138:1138:1138) (1168:1168:1168)) + (PORT datac (341:341:341) (363:363:363)) + (PORT datad (600:600:600) (619:619:619)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (354:354:354)) + (PORT datab (286:286:286) (348:348:348)) + (PORT datad (245:245:245) (288:288:288)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (635:635:635)) + (PORT datab (338:338:338) (371:371:371)) + (PORT datac (1293:1293:1293) (1359:1359:1359)) + (PORT datad (816:816:816) (831:831:831)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (686:686:686)) + (PORT datab (928:928:928) (993:993:993)) + (PORT datac (605:605:605) (616:616:616)) + (PORT datad (628:628:628) (649:649:649)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (457:457:457)) + (PORT datab (882:882:882) (980:980:980)) + (PORT datac (915:915:915) (966:966:966)) + (PORT datad (660:660:660) (702:702:702)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (992:992:992)) + (PORT datab (267:267:267) (322:322:322)) + (PORT datac (813:813:813) (821:821:821)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1201:1201:1201)) + (PORT datac (1154:1154:1154) (1229:1229:1229)) + (PORT datad (892:892:892) (907:907:907)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (906:906:906)) + (PORT datab (900:900:900) (907:907:907)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1674:1674:1674) (1683:1683:1683)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (680:680:680) (713:713:713)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (828:828:828) (872:872:872)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (927:927:927)) + (PORT datab (642:642:642) (678:678:678)) + (PORT datac (1167:1167:1167) (1221:1221:1221)) + (PORT datad (826:826:826) (836:836:836)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1142:1142:1142) (1169:1169:1169)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (860:860:860)) + (PORT datab (417:417:417) (480:480:480)) + (PORT datac (360:360:360) (426:426:426)) + (PORT datad (877:877:877) (892:892:892)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1416:1416:1416)) + (PORT datab (717:717:717) (780:780:780)) + (PORT datac (638:638:638) (703:703:703)) + (PORT datad (861:861:861) (865:865:865)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datab (668:668:668) (689:689:689)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1143:1143:1143)) + (PORT datab (714:714:714) (776:776:776)) + (PORT datac (641:641:641) (706:706:706)) + (PORT datad (633:633:633) (650:650:650)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (831:831:831) (861:861:861)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT datac (591:591:591) (611:611:611)) + (PORT datad (401:401:401) (444:444:444)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (374:374:374)) + (PORT datab (987:987:987) (1028:1028:1028)) + (PORT datad (640:640:640) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (987:987:987)) + (PORT datab (610:610:610) (615:615:615)) + (PORT datac (1075:1075:1075) (1085:1085:1085)) + (PORT datad (546:546:546) (561:561:561)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (680:680:680) (739:739:739)) + (PORT datad (1095:1095:1095) (1166:1166:1166)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1178:1178:1178)) + (PORT datab (897:897:897) (910:910:910)) + (PORT datac (870:870:870) (906:906:906)) + (PORT datad (1139:1139:1139) (1149:1149:1149)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (394:394:394)) + (PORT datab (709:709:709) (735:735:735)) + (PORT datac (623:623:623) (640:640:640)) + (PORT datad (343:343:343) (364:364:364)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (654:654:654)) + (PORT datab (378:378:378) (411:411:411)) + (PORT datac (538:538:538) (542:542:542)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1091:1091:1091)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (1234:1234:1234) (1281:1281:1281)) + (PORT datad (583:583:583) (605:605:605)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (761:761:761)) + (PORT datab (622:622:622) (652:652:652)) + (PORT datac (2210:2210:2210) (2286:2286:2286)) + (PORT datad (624:624:624) (653:653:653)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1579:1579:1579)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (850:850:850) (861:861:861)) + (PORT datad (1053:1053:1053) (1062:1062:1062)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (907:907:907)) + (PORT datab (1138:1138:1138) (1155:1155:1155)) + (PORT datac (2210:2210:2210) (2291:2291:2291)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (759:759:759)) + (PORT datab (662:662:662) (693:693:693)) + (PORT datac (593:593:593) (619:619:619)) + (PORT datad (1543:1543:1543) (1532:1532:1532)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1958:1958:1958)) + (PORT datab (1908:1908:1908) (2021:2021:2021)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (465:465:465) (540:540:540)) + (PORT datac (1126:1126:1126) (1207:1207:1207)) + (PORT datad (1305:1305:1305) (1428:1428:1428)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2299:2299:2299) (2269:2269:2269)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1572:1572:1572) (1566:1566:1566)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (367:367:367)) + (PORT datab (633:633:633) (704:704:704)) + (PORT datac (665:665:665) (725:725:725)) + (PORT datad (371:371:371) (439:439:439)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (461:461:461)) + (PORT datab (644:644:644) (691:691:691)) + (PORT datac (574:574:574) (627:627:627)) + (PORT datad (409:409:409) (468:468:468)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (686:686:686)) + (PORT datab (694:694:694) (758:758:758)) + (PORT datac (241:241:241) (329:329:329)) + (PORT datad (822:822:822) (866:866:866)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (801:801:801)) + (PORT datab (699:699:699) (780:780:780)) + (PORT datac (664:664:664) (739:739:739)) + (PORT datad (646:646:646) (703:703:703)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (667:667:667)) + (PORT datab (884:884:884) (898:898:898)) + (PORT datac (1079:1079:1079) (1100:1100:1100)) + (PORT datad (603:603:603) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1379:1379:1379)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (902:902:902) (939:939:939)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1563:1563:1563) (1545:1545:1545)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (904:904:904)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (223:223:223) (303:303:303)) + (PORT datad (413:413:413) (477:477:477)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1136:1136:1136) (1155:1155:1155)) + (PORT datac (2214:2214:2214) (2292:2292:2292)) + (PORT datad (414:414:414) (478:478:478)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (359:359:359) (391:391:391)) + (PORT datac (606:606:606) (616:616:616)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1413:1413:1413) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (363:363:363)) + (PORT datad (771:771:771) (829:829:829)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (904:904:904)) + (PORT datab (1137:1137:1137) (1154:1154:1154)) + (PORT datac (593:593:593) (616:616:616)) + (PORT datad (649:649:649) (709:709:709)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1574:1574:1574)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (2214:2214:2214) (2292:2292:2292)) + (PORT datad (627:627:627) (655:655:655)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (583:583:583) (592:592:592)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (855:855:855) (917:917:917)) + (PORT datac (548:548:548) (572:572:572)) + (PORT datad (1043:1043:1043) (1050:1050:1050)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1032:1032:1032)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (1394:1394:1394) (1471:1471:1471)) + (PORT datad (987:987:987) (1088:1088:1088)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT datab (1494:1494:1494) (1627:1627:1627)) + (PORT datac (1376:1376:1376) (1473:1473:1473)) + (PORT datad (1208:1208:1208) (1300:1300:1300)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1084:1084:1084)) + (PORT datab (849:849:849) (854:854:854)) + (PORT datac (1080:1080:1080) (1087:1087:1087)) + (PORT datad (871:871:871) (887:887:887)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (880:880:880) (940:940:940)) + (PORT datad (579:579:579) (602:602:602)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (213:213:213) (246:246:246)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_3) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (466:466:466)) + (PORT datab (343:343:343) (375:375:375)) + (PORT datac (342:342:342) (363:363:363)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1178:1178:1178)) + (PORT datab (868:868:868) (900:900:900)) + (PORT datac (1772:1772:1772) (1869:1869:1869)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1366:1366:1366)) + (PORT datab (830:830:830) (873:873:873)) + (PORT datac (985:985:985) (1040:1040:1040)) + (PORT datad (1086:1086:1086) (1122:1122:1122)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (812:812:812) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1084:1084:1084)) + (PORT datab (880:880:880) (968:968:968)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (360:360:360) (393:393:393)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1601:1601:1601) (1712:1712:1712)) + (PORT datab (274:274:274) (361:361:361)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2084:2084:2084) (2217:2217:2217)) + (PORT datab (931:931:931) (1010:1010:1010)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~28) + (DELAY + (ABSOLUTE + (PORT dataa (2230:2230:2230) (2341:2341:2341)) + (PORT datab (760:760:760) (857:857:857)) + (PORT datac (1722:1722:1722) (1802:1802:1802)) + (PORT datad (1798:1798:1798) (1917:1917:1917)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (945:945:945)) + (PORT datab (1153:1153:1153) (1210:1210:1210)) + (PORT datac (1217:1217:1217) (1267:1267:1267)) + (PORT datad (329:329:329) (341:341:341)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1241:1241:1241)) + (PORT datab (1172:1172:1172) (1192:1192:1192)) + (PORT datad (620:620:620) (653:653:653)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (428:428:428)) + (PORT datab (967:967:967) (1019:1019:1019)) + (PORT datac (1068:1068:1068) (1113:1113:1113)) + (PORT datad (203:203:203) (233:233:233)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (314:314:314)) + (PORT datab (1423:1423:1423) (1489:1489:1489)) + (PORT datac (1501:1501:1501) (1565:1565:1565)) + (PORT datad (1096:1096:1096) (1137:1137:1137)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1173:1173:1173) (1216:1216:1216)) + (PORT datac (1134:1134:1134) (1178:1178:1178)) + (PORT datad (1055:1055:1055) (1083:1083:1083)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~23) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (870:870:870)) + (PORT datab (987:987:987) (1091:1091:1091)) + (PORT datac (363:363:363) (392:392:392)) + (PORT datad (383:383:383) (414:414:414)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (701:701:701)) + (PORT datab (860:860:860) (906:906:906)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (924:924:924) (962:962:962)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~21) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (946:946:946) (1006:1006:1006)) + (PORT datac (564:564:564) (597:597:597)) + (PORT datad (600:600:600) (627:627:627)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1199:1199:1199)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (856:856:856) (875:875:875)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (990:990:990)) + (PORT datac (355:355:355) (387:387:387)) + (PORT datad (645:645:645) (697:697:697)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (716:716:716) (739:739:739)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1243:1243:1243)) + (PORT datab (403:403:403) (449:449:449)) + (PORT datad (1271:1271:1271) (1375:1375:1375)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1137:1137:1137) (1160:1160:1160)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (327:327:327) (345:345:345)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (243:243:243) (322:322:322)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1190:1190:1190) (1232:1232:1232)) + (PORT datac (350:350:350) (378:378:378)) + (PORT datad (369:369:369) (394:394:394)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (890:890:890) (913:913:913)) + (PORT datad (324:324:324) (336:336:336)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1535:1535:1535)) + (PORT ena (1964:1964:1964) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (906:906:906)) + (PORT datab (1061:1061:1061) (1089:1089:1089)) + (PORT datac (238:238:238) (321:321:321)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (794:794:794)) + (PORT datab (1384:1384:1384) (1454:1454:1454)) + (PORT datac (617:617:617) (667:667:667)) + (PORT datad (1481:1481:1481) (1521:1521:1521)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (686:686:686)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (728:728:728) (790:790:790)) + (PORT datad (588:588:588) (629:629:629)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (973:973:973) (989:989:989)) + (PORT ena (1957:1957:1957) (1949:1949:1949)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1272:1272:1272) (1364:1364:1364)) + (PORT datab (695:695:695) (747:747:747)) + (PORT datad (1354:1354:1354) (1362:1362:1362)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (404:404:404)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (1106:1106:1106) (1125:1125:1125)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (597:597:597)) + (PORT datab (1195:1195:1195) (1235:1235:1235)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (370:370:370) (393:393:393)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1184:1184:1184) (1216:1216:1216)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1215:1215:1215)) + (PORT datab (634:634:634) (689:689:689)) + (PORT datad (353:353:353) (377:377:377)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (892:892:892) (915:915:915)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (891:891:891) (913:913:913)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datad (554:554:554) (560:560:560)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1175:1175:1175) (1237:1237:1237)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1237:1237:1237) (1302:1302:1302)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (899:899:899)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (838:838:838) (849:849:849)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (900:900:900) (916:916:916)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (459:459:459) (501:501:501)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1721:1721:1721) (1782:1782:1782)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1718:1718:1718) (1780:1780:1780)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (983:983:983)) + (PORT datab (902:902:902) (939:939:939)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (2023:2023:2023) (2065:2065:2065)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (917:917:917)) + (PORT datab (1237:1237:1237) (1273:1273:1273)) + (PORT datad (548:548:548) (573:573:573)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (678:678:678) (702:702:702)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (674:674:674) (698:698:698)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (399:399:399)) + (PORT datab (869:869:869) (872:872:872)) + (PORT datac (767:767:767) (798:798:798)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (672:672:672)) + (PORT datab (548:548:548) (559:559:559)) + (PORT datac (1043:1043:1043) (1102:1102:1102)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (642:642:642)) + (PORT datab (645:645:645) (697:697:697)) + (PORT datac (689:689:689) (713:713:713)) + (PORT datad (338:338:338) (358:358:358)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1011:1011:1011)) + (PORT datab (905:905:905) (974:974:974)) + (PORT datac (587:587:587) (621:621:621)) + (PORT datad (660:660:660) (701:701:701)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1150:1150:1150)) + (PORT datab (268:268:268) (321:321:321)) + (PORT datac (176:176:176) (211:211:211)) + (PORT datad (903:903:903) (942:942:942)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (417:417:417)) + (PORT datab (369:369:369) (414:414:414)) + (PORT datac (1397:1397:1397) (1450:1450:1450)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (453:453:453)) + (PORT datab (1380:1380:1380) (1412:1412:1412)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1526:1526:1526) (1552:1552:1552)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (502:502:502)) + (PORT datab (1723:1723:1723) (1754:1754:1754)) + (PORT datac (1351:1351:1351) (1453:1453:1453)) + (PORT datad (1127:1127:1127) (1197:1197:1197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (952:952:952)) + (PORT datab (614:614:614) (631:631:631)) + (PORT datac (1298:1298:1298) (1368:1368:1368)) + (PORT datad (861:861:861) (885:885:885)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (921:921:921)) + (PORT datab (396:396:396) (425:425:425)) + (PORT datac (896:896:896) (961:961:961)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (688:688:688)) + (PORT datab (648:648:648) (662:662:662)) + (PORT datac (606:606:606) (630:630:630)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1448:1448:1448)) + (PORT datab (1205:1205:1205) (1255:1255:1255)) + (PORT datac (861:861:861) (876:876:876)) + (PORT datad (820:820:820) (832:832:832)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (1136:1136:1136) (1166:1166:1166)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (492:492:492)) + (PORT datab (905:905:905) (931:931:931)) + (PORT datac (806:806:806) (825:825:825)) + (PORT datad (379:379:379) (439:439:439)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (1080:1080:1080) (1164:1164:1164)) + (PORT datac (869:869:869) (936:936:936)) + (PORT datad (1127:1127:1127) (1197:1197:1197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (650:650:650)) + (PORT datab (395:395:395) (422:422:422)) + (PORT datac (834:834:834) (863:863:863)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (879:879:879)) + (PORT datab (203:203:203) (243:243:243)) + (PORT datac (210:210:210) (253:253:253)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (285:285:285)) + (PORT datab (668:668:668) (685:685:685)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1487:1487:1487)) + (PORT datab (418:418:418) (480:480:480)) + (PORT datac (1684:1684:1684) (1716:1716:1716)) + (PORT datad (882:882:882) (932:932:932)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (348:348:348)) + (PORT datab (271:271:271) (334:334:334)) + (PORT datad (244:244:244) (287:287:287)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (452:452:452)) + (PORT datac (1397:1397:1397) (1451:1451:1451)) + (PORT datad (750:750:750) (756:756:756)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (423:423:423)) + (PORT datab (1561:1561:1561) (1586:1586:1586)) + (PORT datac (1350:1350:1350) (1378:1378:1378)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (849:849:849)) + (PORT datab (1377:1377:1377) (1430:1430:1430)) + (PORT datac (869:869:869) (879:879:879)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (398:398:398)) + (PORT datab (1175:1175:1175) (1235:1235:1235)) + (PORT datac (600:600:600) (619:619:619)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (1060:1060:1060)) + (PORT datab (426:426:426) (484:484:484)) + (PORT datac (1286:1286:1286) (1302:1302:1302)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (999:999:999) (995:995:995)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (1195:1195:1195) (1210:1210:1210)) + (PORT datac (678:678:678) (735:735:735)) + (PORT datad (681:681:681) (732:732:732)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (949:949:949)) + (PORT datab (1169:1169:1169) (1191:1191:1191)) + (PORT datac (862:862:862) (872:872:872)) + (PORT datad (836:836:836) (847:847:847)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (372:372:372)) + (PORT datab (707:707:707) (740:740:740)) + (PORT datac (646:646:646) (668:668:668)) + (PORT datad (342:342:342) (364:364:364)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (250:250:250)) + (PORT datab (243:243:243) (287:287:287)) + (PORT datac (575:575:575) (587:587:587)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1474:1474:1474)) + (PORT datac (233:233:233) (286:286:286)) + (PORT datad (1451:1451:1451) (1538:1538:1538)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1081:1081:1081)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (624:624:624) (640:640:640)) + (PORT datad (920:920:920) (965:965:965)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1475:1475:1475)) + (PORT datab (1461:1461:1461) (1493:1493:1493)) + (PORT datac (1378:1378:1378) (1490:1490:1490)) + (PORT datad (805:805:805) (816:816:816)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1569:1569:1569)) + (PORT datab (1303:1303:1303) (1410:1410:1410)) + (PORT datac (2028:2028:2028) (2141:2141:2141)) + (PORT datad (842:842:842) (871:871:871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1260:1260:1260)) + (PORT datab (1144:1144:1144) (1208:1208:1208)) + (PORT datac (1198:1198:1198) (1307:1307:1307)) + (PORT datad (2338:2338:2338) (2445:2445:2445)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1273:1273:1273)) + (PORT datab (1446:1446:1446) (1521:1521:1521)) + (PORT datac (865:865:865) (916:916:916)) + (PORT datad (692:692:692) (755:755:755)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1668:1668:1668) (1859:1859:1859)) + (PORT datab (1254:1254:1254) (1330:1330:1330)) + (PORT datac (995:995:995) (1110:1110:1110)) + (PORT datad (1000:1000:1000) (1104:1104:1104)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (627:627:627)) + (PORT datab (593:593:593) (604:604:604)) + (PORT datac (1352:1352:1352) (1416:1416:1416)) + (PORT datad (1592:1592:1592) (1654:1654:1654)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1118:1118:1118)) + (PORT datab (644:644:644) (707:707:707)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (994:994:994) (1090:1090:1090)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (691:691:691)) + (PORT datab (372:372:372) (394:394:394)) + (PORT datac (618:618:618) (670:670:670)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (431:431:431)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (571:571:571) (583:583:583)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (705:705:705)) + (PORT datab (386:386:386) (406:406:406)) + (PORT datac (1171:1171:1171) (1214:1214:1214)) + (PORT datad (615:615:615) (642:642:642)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1587:1587:1587)) + (PORT datab (1330:1330:1330) (1403:1403:1403)) + (PORT datac (866:866:866) (893:893:893)) + (PORT datad (1169:1169:1169) (1196:1196:1196)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (893:893:893)) + (PORT datab (689:689:689) (750:750:750)) + (PORT datac (1158:1158:1158) (1236:1236:1236)) + (PORT datad (895:895:895) (911:911:911)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1074:1074:1074)) + (PORT datac (973:973:973) (1068:1068:1068)) + (PORT datad (991:991:991) (1084:1084:1084)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (744:744:744)) + (PORT datac (2044:2044:2044) (2097:2097:2097)) + (PORT datad (893:893:893) (910:910:910)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (893:893:893)) + (PORT datab (1079:1079:1079) (1162:1162:1162)) + (PORT datac (1261:1261:1261) (1297:1297:1297)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1156:1156:1156)) + (PORT datab (895:895:895) (917:917:917)) + (PORT datac (1251:1251:1251) (1294:1294:1294)) + (PORT datad (1568:1568:1568) (1587:1587:1587)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (308:308:308)) + (PORT datab (878:878:878) (913:913:913)) + (PORT datad (568:568:568) (589:589:589)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (925:925:925)) + (PORT datab (874:874:874) (915:915:915)) + (PORT datac (651:651:651) (700:700:700)) + (PORT datad (895:895:895) (908:908:908)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (659:659:659)) + (PORT datab (383:383:383) (415:415:415)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (656:656:656) (697:697:697)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1109:1109:1109) (1154:1154:1154)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (643:643:643)) + (PORT datab (634:634:634) (691:691:691)) + (PORT datac (1096:1096:1096) (1111:1111:1111)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1196:1196:1196)) + (PORT datab (657:657:657) (731:731:731)) + (PORT datac (637:637:637) (667:667:667)) + (PORT datad (1415:1415:1415) (1415:1415:1415)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (280:280:280)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1417:1417:1417) (1490:1490:1490)) + (PORT datad (1124:1124:1124) (1144:1144:1144)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (960:960:960)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (601:601:601) (647:647:647)) + (PORT datad (574:574:574) (589:589:589)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (743:743:743)) + (PORT datab (1219:1219:1219) (1273:1273:1273)) + (PORT datac (1133:1133:1133) (1161:1161:1161)) + (PORT datad (623:623:623) (658:658:658)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (690:690:690)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1161:1161:1161) (1240:1240:1240)) + (PORT datad (893:893:893) (907:907:907)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (646:646:646)) + (PORT datab (860:860:860) (907:907:907)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (924:924:924) (962:962:962)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (918:918:918)) + (PORT datab (2172:2172:2172) (2342:2342:2342)) + (PORT datac (1559:1559:1559) (1744:1744:1744)) + (PORT datad (1897:1897:1897) (2012:2012:2012)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (1593:1593:1593) (1774:1774:1774)) + (PORT datac (1141:1141:1141) (1169:1169:1169)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1578:1578:1578) (1718:1718:1718)) + (PORT datac (1288:1288:1288) (1383:1383:1383)) + (PORT datad (1582:1582:1582) (1719:1719:1719)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1535:1535:1535)) + (PORT datab (1194:1194:1194) (1233:1233:1233)) + (PORT datac (879:879:879) (932:932:932)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1956:1956:1956) (2051:2051:2051)) + (PORT datab (945:945:945) (991:991:991)) + (PORT datac (1612:1612:1612) (1657:1657:1657)) + (PORT datad (918:918:918) (942:942:942)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1223:1223:1223)) + (PORT datac (1292:1292:1292) (1388:1388:1388)) + (PORT datad (1554:1554:1554) (1681:1681:1681)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1397:1397:1397) (1448:1448:1448)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (384:384:384)) + (PORT datab (985:985:985) (1061:1061:1061)) + (PORT datac (678:678:678) (742:742:742)) + (PORT datad (1707:1707:1707) (1803:1803:1803)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1619:1619:1619)) + (PORT datab (672:672:672) (690:690:690)) + (PORT datac (1082:1082:1082) (1124:1124:1124)) + (PORT datad (1096:1096:1096) (1123:1123:1123)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1128:1128:1128)) + (PORT datab (1115:1115:1115) (1133:1133:1133)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1346:1346:1346) (1387:1387:1387)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1563:1563:1563) (1598:1598:1598)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (560:560:560) (634:634:634)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1563:1563:1563) (1598:1598:1598)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (296:296:296)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1593:1593:1593) (1635:1635:1635)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1541:1541:1541)) + (PORT asdata (567:567:567) (646:646:646)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1593:1593:1593) (1635:1635:1635)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (341:341:341)) + (PORT datad (223:223:223) (295:295:295)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (966:966:966)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (193:193:193) (225:225:225)) + (PORT datad (899:899:899) (925:925:925)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (847:847:847) (874:874:874)) + (PORT datac (1718:1718:1718) (1715:1715:1715)) + (PORT datad (1217:1217:1217) (1247:1247:1247)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1959:1959:1959) (2001:2001:2001)) + (PORT datab (1439:1439:1439) (1494:1494:1494)) + (PORT datac (1855:1855:1855) (1888:1888:1888)) + (PORT datad (873:873:873) (882:882:882)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (665:665:665)) + (PORT datab (650:650:650) (679:679:679)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (637:637:637) (648:648:648)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (195:195:195) (228:228:228)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1075:1075:1075)) + (PORT datab (616:616:616) (639:639:639)) + (PORT datac (1739:1739:1739) (1802:1802:1802)) + (PORT datad (595:595:595) (619:619:619)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (1120:1120:1120) (1143:1143:1143)) + (PORT datac (562:562:562) (582:582:582)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1487:1487:1487) (1502:1502:1502)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1530:1530:1530)) + (PORT asdata (1306:1306:1306) (1378:1378:1378)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1223:1223:1223) (1226:1226:1226)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT asdata (947:947:947) (1011:1011:1011)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1221:1221:1221)) + (PORT datac (1132:1132:1132) (1198:1198:1198)) + (PORT datad (221:221:221) (292:292:292)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (1689:1689:1689) (1798:1798:1798)) + (PORT datad (1932:1932:1932) (2117:2117:2117)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2140:2140:2140) (2292:2292:2292)) + (PORT datab (1044:1044:1044) (1164:1164:1164)) + (PORT datac (981:981:981) (1070:1070:1070)) + (PORT datad (1460:1460:1460) (1581:1581:1581)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1629:1629:1629)) + (PORT datad (1565:1565:1565) (1659:1659:1659)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (268:268:268)) + (PORT datab (822:822:822) (839:839:839)) + (PORT datac (1067:1067:1067) (1094:1094:1094)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (909:909:909)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (639:639:639) (668:668:668)) + (PORT datad (590:590:590) (610:610:610)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1656:1656:1656)) + (PORT datab (573:573:573) (597:597:597)) + (PORT datac (815:815:815) (853:853:853)) + (PORT datad (1161:1161:1161) (1212:1212:1212)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (684:684:684)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (633:633:633) (660:660:660)) + (PORT datad (948:948:948) (1032:1032:1032)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1240:1240:1240)) + (PORT datab (1170:1170:1170) (1187:1187:1187)) + (PORT datac (1126:1126:1126) (1176:1176:1176)) + (PORT datad (573:573:573) (591:591:591)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1628:1628:1628)) + (PORT datab (1056:1056:1056) (1074:1074:1074)) + (PORT datac (1287:1287:1287) (1400:1400:1400)) + (PORT datad (1142:1142:1142) (1183:1183:1183)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (825:825:825)) + (PORT datab (1496:1496:1496) (1556:1556:1556)) + (PORT datac (892:892:892) (943:943:943)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (747:747:747)) + (PORT datab (1194:1194:1194) (1241:1241:1241)) + (PORT datac (573:573:573) (591:591:591)) + (PORT datad (1231:1231:1231) (1265:1265:1265)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2140:2140:2140) (2291:2291:2291)) + (PORT datab (1400:1400:1400) (1445:1445:1445)) + (PORT datac (1045:1045:1045) (1075:1075:1075)) + (PORT datad (971:971:971) (1060:1060:1060)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (943:943:943)) + (PORT datab (1258:1258:1258) (1304:1304:1304)) + (PORT datac (612:612:612) (635:635:635)) + (PORT datad (784:784:784) (804:804:804)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1622:1622:1622)) + (PORT datac (977:977:977) (1066:1066:1066)) + (PORT datad (2094:2094:2094) (2238:2238:2238)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1418:1418:1418)) + (PORT datab (284:284:284) (374:374:374)) + (PORT datac (1167:1167:1167) (1179:1179:1179)) + (PORT datad (1155:1155:1155) (1191:1191:1191)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1228:1228:1228) (1217:1217:1217)) + (PORT datac (1078:1078:1078) (1102:1102:1102)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1274:1274:1274)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (610:610:610) (631:631:631)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1786:1786:1786) (1866:1866:1866)) + (PORT datab (966:966:966) (1013:1013:1013)) + (PORT datac (615:615:615) (624:624:624)) + (PORT datad (1516:1516:1516) (1553:1553:1553)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (394:394:394)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (592:592:592)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1056:1056:1056) (1068:1068:1068)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1592:1592:1592) (1661:1661:1661)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (788:788:788) (860:860:860)) + (PORT datad (1840:1840:1840) (1890:1890:1890)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (688:688:688)) + (PORT datab (377:377:377) (399:399:399)) + (PORT datac (1068:1068:1068) (1108:1108:1108)) + (PORT datad (842:842:842) (878:878:878)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1223:1223:1223)) + (PORT datab (2537:2537:2537) (2642:2642:2642)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1332:1332:1332) (1343:1343:1343)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1215:1215:1215)) + (PORT datab (1163:1163:1163) (1208:1208:1208)) + (PORT datac (1214:1214:1214) (1289:1289:1289)) + (PORT datad (1206:1206:1206) (1262:1262:1262)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1145:1145:1145) (1194:1194:1194)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1534:1534:1534)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (710:710:710) (770:770:770)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (465:465:465)) + (PORT datad (1256:1256:1256) (1328:1328:1328)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1272:1272:1272)) + (PORT datab (1162:1162:1162) (1210:1210:1210)) + (PORT datac (1211:1211:1211) (1291:1291:1291)) + (PORT datad (1623:1623:1623) (1664:1664:1664)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (929:929:929)) + (PORT datac (943:943:943) (984:984:984)) + (PORT datad (1213:1213:1213) (1229:1229:1229)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (563:563:563)) + (PORT datab (556:556:556) (577:577:577)) + (PORT datad (863:863:863) (917:917:917)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31064,11 +31620,11 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (1382:1382:1382) (1568:1568:1568)) - (PORT datac (1328:1328:1328) (1469:1469:1469)) - (PORT datad (2533:2533:2533) (2621:2621:2621)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1522:1522:1522) (1626:1626:1626)) + (PORT datab (938:938:938) (1011:1011:1011)) + (PORT datad (1498:1498:1498) (1593:1593:1593)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31078,10 +31634,10 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1163:1163:1163)) - (PORT datab (924:924:924) (979:979:979)) - (PORT datac (820:820:820) (846:846:846)) - (PORT datad (1655:1655:1655) (1830:1830:1830)) + (PORT dataa (864:864:864) (916:916:916)) + (PORT datab (2172:2172:2172) (2345:2345:2345)) + (PORT datac (1140:1140:1140) (1171:1171:1171)) + (PORT datad (802:802:802) (810:810:810)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -31094,12 +31650,12 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1914:1914:1914) (2085:2085:2085)) - (PORT datac (2116:2116:2116) (2227:2227:2227)) - (PORT datad (1650:1650:1650) (1834:1834:1834)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1515:1515:1515) (1643:1643:1643)) + (PORT datab (827:827:827) (874:874:874)) + (PORT datac (1854:1854:1854) (1974:1974:1974)) + (PORT datad (1755:1755:1755) (1874:1874:1874)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31107,14 +31663,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1184:1184:1184) (1229:1229:1229)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) + (PORT asdata (1172:1172:1172) (1215:1215:1215)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31127,24 +31683,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT datac (1399:1399:1399) (1483:1483:1483)) - (PORT datad (1955:1955:1955) (2153:2153:2153)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (369:369:369) (392:392:392)) + (PORT datab (540:540:540) (559:559:559)) + (PORT datad (863:863:863) (918:918:918)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (961:961:961) (1001:1001:1001)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1480:1480:1480)) + (PORT datab (1122:1122:1122) (1187:1187:1187)) + (PORT datac (1126:1126:1126) (1187:1187:1187)) + (PORT datad (1141:1141:1141) (1208:1208:1208)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1180:1180:1180) (1258:1258:1258)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datad (566:566:566) (578:578:578)) + (PORT dataa (880:880:880) (936:936:936)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (196:196:196) (221:221:221)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -31153,14 +31747,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT clk (1524:1524:1524) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (753:753:753) (819:819:819)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) + (PORT asdata (936:936:936) (990:990:990)) + (PORT sload (1231:1231:1231) (1309:1309:1309)) + (PORT ena (2105:2105:2105) (2109:2109:2109)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31173,104 +31767,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) + (INSTANCE z80_\|address_pins_\|abus\[6\]\~25) (DELAY (ABSOLUTE - (PORT dataa (2315:2315:2315) (2530:2530:2530)) - (PORT datad (1404:1404:1404) (1520:1520:1520)) + (PORT dataa (1332:1332:1332) (1475:1475:1475)) + (PORT datac (875:875:875) (953:953:953)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (303:303:303) (420:420:420)) - (PORT datac (915:915:915) (973:973:973)) - (PORT datad (643:643:643) (704:704:704)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (640:640:640)) - (PORT datab (1304:1304:1304) (1358:1358:1358)) - (PORT datac (728:728:728) (812:812:812)) - (PORT datad (618:618:618) (638:638:638)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (436:436:436)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (221:221:221) (266:266:266)) + (PORT datab (634:634:634) (659:659:659)) + (PORT datad (864:864:864) (915:915:915)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (PORT asdata (942:942:942) (989:989:989)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE z80_\|address_pins_\|abus\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (716:716:716)) - (PORT datab (2772:2772:2772) (2956:2956:2956)) - (PORT datac (648:648:648) (682:682:682)) - (PORT datad (637:637:637) (706:706:706)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (367:367:367)) - (PORT datab (955:955:955) (1021:1021:1021)) - (PORT datac (1004:1004:1004) (1065:1065:1065)) - (PORT datad (262:262:262) (340:340:340)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (234:234:234) (310:310:310)) + (PORT datad (2373:2373:2373) (2488:2488:2488)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31278,27 +31825,133 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1065:1065:1065) (1138:1138:1138)) - (PORT datac (266:266:266) (360:360:360)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (383:383:383) (411:411:411)) + (PORT datab (886:886:886) (952:952:952)) + (PORT datad (346:346:346) (362:362:362)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (949:949:949) (1005:1005:1005)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (940:940:940)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (947:947:947) (1004:1004:1004)) + (PORT sload (1231:1231:1231) (1309:1309:1309)) + (PORT ena (2105:2105:2105) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (942:942:942)) + (PORT datab (337:337:337) (367:367:367)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (584:584:584) (672:672:672)) + (PORT sload (1231:1231:1231) (1309:1309:1309)) + (PORT ena (2105:2105:2105) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1235:1235:1235)) + (PORT datab (1107:1107:1107) (1189:1189:1189)) + (PORT datac (1129:1129:1129) (1199:1199:1199)) + (PORT datad (1308:1308:1308) (1432:1432:1432)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (INSTANCE Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (299:299:299) (419:419:419)) - (PORT datac (911:911:911) (974:974:974)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (356:356:356) (387:387:387)) + (PORT datac (1098:1098:1098) (1129:1129:1129)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31306,148 +31959,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (INSTANCE D\[5\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1228:1228:1228) (1254:1254:1254)) - (PORT datac (699:699:699) (766:766:766)) - (PORT datad (614:614:614) (688:688:688)) + (PORT dataa (417:417:417) (452:452:452)) + (PORT datac (364:364:364) (395:395:395)) + (PORT datad (1087:1087:1087) (1153:1153:1153)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (869:869:869)) - (PORT datab (336:336:336) (364:364:364)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (772:772:772) (854:854:854)) - (PORT datac (461:461:461) (534:534:534)) - (PORT datad (928:928:928) (988:988:988)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1071:1071:1071)) - (PORT datab (656:656:656) (730:730:730)) - (PORT datac (702:702:702) (766:766:766)) - (PORT datad (1186:1186:1186) (1205:1205:1205)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1062:1062:1062)) - (PORT datab (770:770:770) (851:851:851)) - (PORT datac (697:697:697) (772:772:772)) - (PORT datad (969:969:969) (1035:1035:1035)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (838:838:838)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (562:562:562) (579:579:579)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (1121:1121:1121) (1187:1187:1187)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (650:650:650) (668:668:668)) + (PORT datab (892:892:892) (960:960:960)) + (PORT datad (570:570:570) (574:574:574)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31457,11 +31990,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (895:895:895) (951:951:951)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) + (PORT asdata (902:902:902) (966:966:966)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31474,12 +32007,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~23) (DELAY (ABSOLUTE - (PORT datac (1681:1681:1681) (1850:1850:1850)) - (PORT datad (2616:2616:2616) (2812:2812:2812)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2416:2416:2416) (2538:2538:2538)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31489,9 +32022,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (350:350:350) (377:377:377)) - (PORT datad (1120:1120:1120) (1184:1184:1184)) + (PORT dataa (557:557:557) (570:570:570)) + (PORT datab (639:639:639) (665:665:665)) + (PORT datad (859:859:859) (917:917:917)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -31503,11 +32036,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (928:928:928) (977:977:977)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) + (PORT asdata (1735:1735:1735) (1808:1808:1808)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31523,214 +32056,23 @@ (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) (DELAY (ABSOLUTE - (PORT dataa (2421:2421:2421) (2631:2631:2631)) - (PORT datad (1663:1663:1663) (1788:1788:1788)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (1293:1293:1293) (1369:1369:1369)) - (PORT datac (707:707:707) (797:797:797)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (948:948:948) (1035:1035:1035)) + (PORT datac (1471:1471:1471) (1591:1591:1591)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (871:871:871)) - (PORT datab (699:699:699) (763:763:763)) - (PORT datac (704:704:704) (770:770:770)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT datac (680:680:680) (750:750:750)) - (PORT datad (740:740:740) (823:823:823)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (817:817:817)) - (PORT datab (1292:1292:1292) (1364:1364:1364)) - (PORT datac (707:707:707) (793:793:793)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (762:762:762) (842:842:842)) - (PORT datad (206:206:206) (236:236:236)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (396:396:396)) - (PORT datac (848:848:848) (867:867:867)) - (PORT datad (709:709:709) (783:783:783)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (757:757:757)) - (PORT datac (984:984:984) (1047:1047:1047)) - (PORT datad (652:652:652) (732:732:732)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (942:942:942)) - (PORT datab (605:605:605) (646:646:646)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (712:712:712)) - (PORT datab (1468:1468:1468) (1492:1492:1492)) - (PORT datac (912:912:912) (969:969:969)) - (PORT datad (362:362:362) (421:421:421)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datad (1120:1120:1120) (1184:1184:1184)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (726:726:726) (799:799:799)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (1811:1811:1811) (1928:1928:1928)) - (PORT datac (2265:2265:2265) (2463:2463:2463)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (397:397:397)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (1124:1124:1124) (1188:1188:1188)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (807:807:807) (833:833:833)) + (PORT datab (814:814:814) (849:849:849)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31740,11 +32082,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (741:741:741) (815:815:815)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) + (PORT asdata (1262:1262:1262) (1310:1310:1310)) + (PORT sload (1742:1742:1742) (1823:1823:1823)) + (PORT ena (1431:1431:1431) (1435:1435:1435)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31757,505 +32099,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (436:436:436)) - (PORT datab (764:764:764) (853:853:853)) - (PORT datac (695:695:695) (784:784:784)) - (PORT datad (346:346:346) (371:371:371)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT datab (426:426:426) (500:500:500)) - (PORT datac (745:745:745) (821:821:821)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (259:259:259)) - (PORT datab (769:769:769) (850:850:850)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1971:1971:1971) (2134:2134:2134)) - (PORT datac (2268:2268:2268) (2463:2463:2463)) - (PORT datad (668:668:668) (730:730:730)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (1011:1011:1011)) - (PORT datab (983:983:983) (1055:1055:1055)) - (PORT datad (204:204:204) (233:233:233)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1104:1104:1104)) - (PORT datab (287:287:287) (378:378:378)) - (PORT datac (245:245:245) (328:328:328)) - (PORT datad (709:709:709) (788:788:788)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1139:1139:1139)) - (PORT datab (956:956:956) (1026:1026:1026)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (436:436:436)) - (PORT datab (631:631:631) (655:655:655)) - (PORT datad (794:794:794) (817:817:817)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (634:634:634) (705:705:705)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1412:1412:1412) (1526:1526:1526)) + (PORT datac (242:242:242) (321:321:321)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datac (2534:2534:2534) (2773:2773:2773)) - (PORT datad (1184:1184:1184) (1290:1290:1290)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (825:825:825)) - (PORT datab (932:932:932) (1013:1013:1013)) - (PORT datac (754:754:754) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (992:992:992)) - (PORT datab (738:738:738) (804:804:804)) - (PORT datac (695:695:695) (782:782:782)) - (PORT datad (355:355:355) (387:387:387)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (471:471:471) (550:550:550)) - (PORT datad (633:633:633) (650:650:650)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (572:572:572)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (813:813:813)) - (PORT datad (750:750:750) (828:828:828)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (441:441:441)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1258:1258:1258)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datad (319:319:319) (337:337:337)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (736:736:736) (808:808:808)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2312:2312:2312) (2526:2526:2526)) - (PORT datad (1425:1425:1425) (1538:1538:1538)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1257:1257:1257)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (734:734:734) (795:795:795)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (931:931:931) (1029:1029:1029)) - (PORT datad (2391:2391:2391) (2584:2584:2584)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (785:785:785)) - (PORT datab (676:676:676) (757:757:757)) - (PORT datac (673:673:673) (715:715:715)) - (PORT datad (1494:1494:1494) (1586:1586:1586)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (2355:2355:2355) (2578:2578:2578)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1533:1533:1533)) - (PORT asdata (569:569:569) (649:649:649)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (232:232:232) (306:306:306)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (994:994:994) (1049:1049:1049)) - (PORT datad (230:230:230) (303:303:303)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2634:2634:2634) (2764:2764:2764)) - (PORT datab (1939:1939:1939) (2080:2080:2080)) - (PORT datac (2770:2770:2770) (3002:3002:3002)) - (PORT datad (2212:2212:2212) (2284:2284:2284)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1973:1973:1973) (2138:2138:2138)) - (PORT datac (2265:2265:2265) (2462:2462:2462)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -32264,953 +32114,26 @@ (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (2634:2634:2634) (2769:2769:2769)) - (PORT datab (1937:1937:1937) (2082:2082:2082)) - (PORT datac (2770:2770:2770) (3003:3003:3003)) - (PORT datad (2214:2214:2214) (2287:2287:2287)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1206:1206:1206) (1274:1274:1274)) + (PORT datab (1163:1163:1163) (1210:1210:1210)) + (PORT datac (1212:1212:1212) (1292:1292:1292)) + (PORT datad (1623:1623:1623) (1665:1665:1665)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (462:462:462)) - (PORT datab (1257:1257:1257) (1295:1295:1295)) - (PORT datac (1233:1233:1233) (1265:1265:1265)) - (PORT datad (1391:1391:1391) (1417:1417:1417)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1921:1921:1921) (2116:2116:2116)) - (PORT datac (1982:1982:1982) (2198:2198:2198)) - (PORT datad (1426:1426:1426) (1533:1533:1533)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (253:253:253)) - (PORT datab (616:616:616) (630:630:630)) - (PORT datad (908:908:908) (944:944:944)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (995:995:995) (1050:1050:1050)) - (PORT sload (1199:1199:1199) (1276:1276:1276)) - (PORT ena (1212:1212:1212) (1237:1237:1237)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2422:2422:2422) (2631:2631:2631)) - (PORT datac (1069:1069:1069) (1151:1151:1151)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1695:1695:1695) (1773:1773:1773)) - (PORT datad (325:325:325) (351:351:351)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (938:938:938) (1005:1005:1005)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1227:1227:1227)) - (PORT datad (2391:2391:2391) (2584:2584:2584)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (891:891:891)) - (PORT datab (1716:1716:1716) (1784:1784:1784)) - (PORT datad (875:875:875) (908:908:908)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1270:1270:1270) (1328:1328:1328)) - (PORT sload (1357:1357:1357) (1408:1408:1408)) - (PORT ena (1406:1406:1406) (1406:1406:1406)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (345:345:345)) - (PORT datad (2385:2385:2385) (2578:2578:2578)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (1658:1658:1658) (1733:1733:1733)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (899:899:899) (959:959:959)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (282:282:282) (364:364:364)) - (PORT datad (377:377:377) (439:439:439)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1695:1695:1695) (1769:1769:1769)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (959:959:959) (1008:1008:1008)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datac (1237:1237:1237) (1358:1358:1358)) - (PORT datad (2381:2381:2381) (2572:2572:2572)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (561:561:561)) - (PORT datab (1692:1692:1692) (1769:1769:1769)) - (PORT datad (316:316:316) (329:329:329)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (588:588:588) (666:666:666)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datac (1495:1495:1495) (1601:1601:1601)) - (PORT datad (2387:2387:2387) (2578:2578:2578)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1094:1094:1094)) - (PORT datab (898:898:898) (948:948:948)) - (PORT datad (1691:1691:1691) (1747:1747:1747)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1266:1266:1266) (1347:1347:1347)) - (PORT sload (1357:1357:1357) (1408:1408:1408)) - (PORT ena (1406:1406:1406) (1406:1406:1406)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (2419:2419:2419) (2625:2625:2625)) - (PORT datac (245:245:245) (324:324:324)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1325:1325:1325) (1393:1393:1393)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2362:2362:2362) (2570:2570:2570)) - (PORT d[1] (2582:2582:2582) (2663:2663:2663)) - (PORT d[2] (1885:1885:1885) (2005:2005:2005)) - (PORT d[3] (1262:1262:1262) (1338:1338:1338)) - (PORT d[4] (2266:2266:2266) (2355:2355:2355)) - (PORT d[5] (1286:1286:1286) (1366:1366:1366)) - (PORT d[6] (1452:1452:1452) (1480:1480:1480)) - (PORT d[7] (2355:2355:2355) (2491:2491:2491)) - (PORT d[8] (2239:2239:2239) (2395:2395:2395)) - (PORT d[9] (1053:1053:1053) (1110:1110:1110)) - (PORT d[10] (1026:1026:1026) (1074:1074:1074)) - (PORT d[11] (1436:1436:1436) (1501:1501:1501)) - (PORT d[12] (756:756:756) (816:816:816)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1782:1782:1782) (1767:1767:1767)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (1825:1825:1825) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT asdata (2020:2020:2020) (2056:2056:2056)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1760:1760:1760) (1806:1806:1806)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1013:1013:1013)) - (PORT datab (895:895:895) (947:947:947)) - (PORT datac (1141:1141:1141) (1200:1200:1200)) - (PORT datad (964:964:964) (1019:1019:1019)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1919:1919:1919) (2115:2115:2115)) - (PORT datac (1982:1982:1982) (2200:2200:2200)) - (PORT datad (1422:1422:1422) (1531:1531:1531)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1512:1512:1512) (1551:1551:1551)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1938:1938:1938) (2080:2080:2080)) - (PORT d[1] (2501:2501:2501) (2527:2527:2527)) - (PORT d[2] (2588:2588:2588) (2765:2765:2765)) - (PORT d[3] (1139:1139:1139) (1178:1178:1178)) - (PORT d[4] (2415:2415:2415) (2565:2565:2565)) - (PORT d[5] (3170:3170:3170) (3226:3226:3226)) - (PORT d[6] (2192:2192:2192) (2289:2289:2289)) - (PORT d[7] (1851:1851:1851) (1867:1867:1867)) - (PORT d[8] (2510:2510:2510) (2632:2632:2632)) - (PORT d[9] (1705:1705:1705) (1750:1750:1750)) - (PORT d[10] (2512:2512:2512) (2611:2611:2611)) - (PORT d[11] (4013:4013:4013) (4323:4323:4323)) - (PORT d[12] (2512:2512:2512) (2564:2564:2564)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2002:2002:2002) (1964:1964:1964)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (PORT d[0] (2197:2197:2197) (2152:2152:2152)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (462:462:462)) - (PORT datab (1257:1257:1257) (1300:1300:1300)) - (PORT datac (1234:1234:1234) (1270:1270:1270)) - (PORT datad (1392:1392:1392) (1420:1420:1420)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1920:1920:1920) (2115:2115:2115)) - (PORT datac (1982:1982:1982) (2197:2197:2197)) - (PORT datad (1425:1425:1425) (1529:1529:1529)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (852:852:852) (854:854:854)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2917:2917:2917) (3108:3108:3108)) - (PORT d[1] (3323:3323:3323) (3498:3498:3498)) - (PORT d[2] (1499:1499:1499) (1573:1573:1573)) - (PORT d[3] (3966:3966:3966) (4139:4139:4139)) - (PORT d[4] (2897:2897:2897) (3086:3086:3086)) - (PORT d[5] (4427:4427:4427) (4564:4564:4564)) - (PORT d[6] (2208:2208:2208) (2294:2294:2294)) - (PORT d[7] (3987:3987:3987) (4071:4071:4071)) - (PORT d[8] (1521:1521:1521) (1551:1551:1551)) - (PORT d[9] (2130:2130:2130) (2218:2218:2218)) - (PORT d[10] (2303:2303:2303) (2371:2371:2371)) - (PORT d[11] (3139:3139:3139) (3345:3345:3345)) - (PORT d[12] (4131:4131:4131) (4403:4403:4403)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1928:1928:1928) (1901:1901:1901)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2721:2721:2721) (2738:2738:2738)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1492:1492:1492) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (944:944:944) (997:997:997)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (465:465:465)) - (PORT datab (1252:1252:1252) (1298:1298:1298)) - (PORT datac (1232:1232:1232) (1268:1268:1268)) - (PORT datad (1391:1391:1391) (1418:1418:1418)) + (PORT dataa (2097:2097:2097) (2228:2228:2228)) + (PORT datab (998:998:998) (1054:1054:1054)) + (PORT datac (1756:1756:1756) (1816:1816:1816)) + (PORT datad (217:217:217) (252:252:252)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -33223,6227 +32146,323 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1915:1915:1915) (2111:2111:2111)) - (PORT datac (1984:1984:1984) (2198:2198:2198)) - (PORT datad (1420:1420:1420) (1527:1527:1527)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1308:1308:1308) (1374:1374:1374)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2112:2112:2112) (2310:2310:2310)) - (PORT d[1] (2254:2254:2254) (2334:2334:2334)) - (PORT d[2] (1596:1596:1596) (1699:1699:1699)) - (PORT d[3] (2501:2501:2501) (2593:2593:2593)) - (PORT d[4] (2291:2291:2291) (2367:2367:2367)) - (PORT d[5] (1576:1576:1576) (1652:1652:1652)) - (PORT d[6] (1720:1720:1720) (1763:1763:1763)) - (PORT d[7] (2216:2216:2216) (2273:2273:2273)) - (PORT d[8] (2483:2483:2483) (2655:2655:2655)) - (PORT d[9] (1067:1067:1067) (1146:1146:1146)) - (PORT d[10] (1734:1734:1734) (1816:1816:1816)) - (PORT d[11] (1425:1425:1425) (1474:1474:1474)) - (PORT d[12] (1019:1019:1019) (1090:1090:1090)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1513:1513:1513) (1529:1529:1529)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2023:2023:2023) (2001:2001:2001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1125:1125:1125)) - (PORT datab (1546:1546:1546) (1595:1595:1595)) - (PORT datac (1417:1417:1417) (1491:1491:1491)) - (PORT datad (1479:1479:1479) (1560:1560:1560)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1351:1351:1351)) - (PORT datab (1832:1832:1832) (1977:1977:1977)) - (PORT datac (1662:1662:1662) (1715:1715:1715)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (463:463:463)) - (PORT datab (1250:1250:1250) (1293:1293:1293)) - (PORT datac (1232:1232:1232) (1265:1265:1265)) - (PORT datad (1387:1387:1387) (1415:1415:1415)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (950:950:950) (1036:1036:1036)) + (PORT datac (1472:1472:1472) (1595:1595:1595)) + (PORT datad (1170:1170:1170) (1274:1274:1274)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~24) (DELAY (ABSOLUTE - (PORT inclk[0] (154:154:154) (138:138:138)) + (PORT datab (1125:1125:1125) (1189:1189:1189)) + (PORT datad (1308:1308:1308) (1432:1432:1432)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~27) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (541:541:541)) - (PORT datab (973:973:973) (1044:1044:1044)) - (PORT datac (711:711:711) (774:774:774)) - (PORT datad (740:740:740) (796:796:796)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1336:1336:1336) (1482:1482:1482)) + (PORT datac (1124:1124:1124) (1185:1185:1185)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1481:1481:1481)) + (PORT datad (1139:1139:1139) (1205:1205:1205)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datad (2373:2373:2373) (2488:2488:2488)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (1107:1107:1107) (1190:1190:1190)) + (PORT datad (1307:1307:1307) (1432:1432:1432)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1483:1483:1483)) + (PORT datac (1128:1128:1128) (1200:1200:1200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (875:875:875) (935:935:935)) + (PORT datad (310:310:310) (328:328:328)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT asdata (996:996:996) (1046:1046:1046)) - (PORT ena (817:817:817) (814:814:814)) + (PORT clk (1525:1525:1525) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (933:933:933) (988:988:988)) + (PORT sload (1276:1276:1276) (1363:1363:1363)) + (PORT ena (1928:1928:1928) (1942:1942:1942)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (INSTANCE z80_\|address_pins_\|abus\[8\]\~17) (DELAY (ABSOLUTE - (PORT datad (885:885:885) (926:926:926)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (911:911:911) (966:966:966)) + (PORT dataa (644:644:644) (710:710:710)) + (PORT datac (1923:1923:1923) (2049:2049:2049)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) (DELAY (ABSOLUTE - (PORT datac (915:915:915) (971:971:971)) - (PORT datad (883:883:883) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (1011:1011:1011)) - (PORT datab (911:911:911) (982:982:982)) - (PORT datad (876:876:876) (933:933:933)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1341:1341:1341)) - (PORT datab (629:629:629) (682:682:682)) + (PORT dataa (387:387:387) (415:415:415)) + (PORT datab (876:876:876) (937:937:937)) + (PORT datad (314:314:314) (334:334:334)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) (DELAY (ABSOLUTE - (PORT dataa (744:744:744) (808:808:808)) + (PORT clk (1525:1525:1525) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1276:1276:1276) (1363:1363:1363)) + (PORT ena (1928:1928:1928) (1942:1942:1942)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2171:2171:2171) (2320:2320:2320)) + (PORT datad (244:244:244) (316:316:316)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (756:756:756)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (941:941:941) (983:983:983)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (946:946:946) (928:928:928)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1009:1009:1009)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (946:946:946) (928:928:928)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT datab (959:959:959) (1008:1008:1008)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (946:946:946) (928:928:928)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (781:781:781)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (960:960:960) (1021:1021:1021)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (447:447:447) (541:541:541)) - (PORT datab (970:970:970) (1040:1040:1040)) - (PORT datac (712:712:712) (775:775:775)) - (PORT datad (738:738:738) (793:793:793)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1173:1173:1173)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1015:1015:1015)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (542:542:542)) - (PORT datab (979:979:979) (1050:1050:1050)) - (PORT datac (707:707:707) (769:769:769)) - (PORT datad (744:744:744) (801:801:801)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (375:375:375)) - (PORT datab (378:378:378) (404:404:404)) - (PORT datad (742:742:742) (802:802:802)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datac (920:920:920) (981:981:981)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1014:1014:1014)) - (PORT datac (182:182:182) (220:220:220)) + (PORT dataa (342:342:342) (379:379:379)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datad (849:849:849) (899:899:899)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT clk (1525:1525:1525) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) + (PORT asdata (583:583:583) (666:666:666)) + (PORT sload (1276:1276:1276) (1363:1363:1363)) + (PORT ena (1928:1928:1928) (1942:1942:1942)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1277:1277:1277) (1338:1338:1338)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2788:2788:2788) (2939:2939:2939)) - (PORT d[1] (2965:2965:2965) (3112:3112:3112)) - (PORT d[2] (1934:1934:1934) (2074:2074:2074)) - (PORT d[3] (2167:2167:2167) (2291:2291:2291)) - (PORT d[4] (2059:2059:2059) (2183:2183:2183)) - (PORT d[5] (1870:1870:1870) (1973:1973:1973)) - (PORT d[6] (2323:2323:2323) (2459:2459:2459)) - (PORT d[7] (1899:1899:1899) (1971:1971:1971)) - (PORT d[8] (3189:3189:3189) (3291:3291:3291)) - (PORT d[9] (2017:2017:2017) (2163:2163:2163)) - (PORT d[10] (3596:3596:3596) (3781:3781:3781)) - (PORT d[11] (2378:2378:2378) (2513:2513:2513)) - (PORT d[12] (1977:1977:1977) (2130:2130:2130)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1790:1790:1790) (1802:1802:1802)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3272:3272:3272) (3205:3205:3205)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1867:1867:1867) (1911:1911:1911)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4490:4490:4490) (4600:4600:4600)) - (PORT d[1] (4410:4410:4410) (4523:4523:4523)) - (PORT d[2] (4538:4538:4538) (4602:4602:4602)) - (PORT d[3] (4281:4281:4281) (4370:4370:4370)) - (PORT d[4] (4381:4381:4381) (4456:4456:4456)) - (PORT d[5] (4418:4418:4418) (4548:4548:4548)) - (PORT d[6] (4415:4415:4415) (4506:4506:4506)) - (PORT d[7] (4377:4377:4377) (4507:4507:4507)) - (PORT d[8] (4645:4645:4645) (4750:4750:4750)) - (PORT d[9] (4429:4429:4429) (4513:4513:4513)) - (PORT d[10] (4448:4448:4448) (4509:4509:4509)) - (PORT d[11] (4414:4414:4414) (4551:4551:4551)) - (PORT d[12] (4365:4365:4365) (4449:4449:4449)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~19) (DELAY (ABSOLUTE - (PORT datad (1452:1452:1452) (1517:1517:1517)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (288:288:288)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1252:1252:1252)) - (PORT datab (1269:1269:1269) (1318:1318:1318)) - (PORT datac (1435:1435:1435) (1491:1491:1491)) - (PORT datad (1131:1131:1131) (1204:1204:1204)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datac (796:796:796) (844:844:844)) + (PORT datad (2143:2143:2143) (2273:2273:2273)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1222:1222:1222) (1232:1232:1232)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3085:3085:3085) (3257:3257:3257)) - (PORT d[1] (2119:2119:2119) (2225:2225:2225)) - (PORT d[2] (1627:1627:1627) (1738:1738:1738)) - (PORT d[3] (1538:1538:1538) (1637:1637:1637)) - (PORT d[4] (2666:2666:2666) (2815:2815:2815)) - (PORT d[5] (1574:1574:1574) (1655:1655:1655)) - (PORT d[6] (2028:2028:2028) (2134:2134:2134)) - (PORT d[7] (1881:1881:1881) (1932:1932:1932)) - (PORT d[8] (3473:3473:3473) (3592:3592:3592)) - (PORT d[9] (1702:1702:1702) (1822:1822:1822)) - (PORT d[10] (1648:1648:1648) (1760:1760:1760)) - (PORT d[11] (1603:1603:1603) (1685:1685:1685)) - (PORT d[12] (1677:1677:1677) (1804:1804:1804)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1434:1434:1434) (1404:1404:1404)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (2896:2896:2896) (2932:2932:2932)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1800:1800:1800)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1527:1527:1527) (1568:1568:1568)) - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4450:4450:4450) (4537:4537:4537)) - (PORT d[1] (4347:4347:4347) (4424:4424:4424)) - (PORT d[2] (4406:4406:4406) (4467:4467:4467)) - (PORT d[3] (4294:4294:4294) (4374:4374:4374)) - (PORT d[4] (4350:4350:4350) (4425:4425:4425)) - (PORT d[5] (4369:4369:4369) (4474:4474:4474)) - (PORT d[6] (4390:4390:4390) (4426:4426:4426)) - (PORT d[7] (4335:4335:4335) (4462:4462:4462)) - (PORT d[8] (4444:4444:4444) (4576:4576:4576)) - (PORT d[9] (4472:4472:4472) (4577:4577:4577)) - (PORT d[10] (4487:4487:4487) (4606:4606:4606)) - (PORT d[11] (4466:4466:4466) (4582:4582:4582)) - (PORT d[12] (4367:4367:4367) (4452:4452:4452)) - (PORT clk (1807:1807:1807) (1802:1802:1802)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3185:3185:3185) (3417:3417:3417)) - (PORT d[1] (3332:3332:3332) (3484:3484:3484)) - (PORT d[2] (1430:1430:1430) (1497:1497:1497)) - (PORT d[3] (3934:3934:3934) (4092:4092:4092)) - (PORT d[4] (2918:2918:2918) (3104:3104:3104)) - (PORT d[5] (4421:4421:4421) (4553:4553:4553)) - (PORT d[6] (2796:2796:2796) (2911:2911:2911)) - (PORT d[7] (1726:1726:1726) (1774:1774:1774)) - (PORT d[8] (1980:1980:1980) (2009:2009:2009)) - (PORT d[9] (2141:2141:2141) (2210:2210:2210)) - (PORT d[10] (2312:2312:2312) (2391:2391:2391)) - (PORT d[11] (3101:3101:3101) (3331:3331:3331)) - (PORT d[12] (4277:4277:4277) (4540:4540:4540)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (1940:1940:1940) (1958:1958:1958)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~47) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) (DELAY (ABSOLUTE - (PORT dataa (926:926:926) (1021:1021:1021)) - (PORT datab (305:305:305) (397:397:397)) - (PORT datac (887:887:887) (916:916:916)) - (PORT datad (1045:1045:1045) (1066:1066:1066)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1950:1950:1950) (2052:2052:2052)) - (PORT d[1] (2560:2560:2560) (2687:2687:2687)) - (PORT d[2] (2359:2359:2359) (2509:2509:2509)) - (PORT d[3] (3005:3005:3005) (3111:3111:3111)) - (PORT d[4] (2278:2278:2278) (2362:2362:2362)) - (PORT d[5] (3097:3097:3097) (3185:3185:3185)) - (PORT d[6] (2841:2841:2841) (2965:2965:2965)) - (PORT d[7] (3148:3148:3148) (3225:3225:3225)) - (PORT d[8] (2385:2385:2385) (2466:2466:2466)) - (PORT d[9] (3043:3043:3043) (3176:3176:3176)) - (PORT d[10] (2289:2289:2289) (2338:2338:2338)) - (PORT d[11] (2469:2469:2469) (2631:2631:2631)) - (PORT d[12] (3226:3226:3226) (3408:3408:3408)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2959:2959:2959) (2871:2871:2871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1122:1122:1122)) - (PORT datab (1468:1468:1468) (1531:1531:1531)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1667:1667:1667) (1758:1758:1758)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (807:807:807) (834:834:834)) + (PORT datab (363:363:363) (396:396:396)) + (PORT datad (584:584:584) (598:598:598)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1231:1231:1231)) - (PORT datab (307:307:307) (400:400:400)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1483:1483:1483)) - (PORT datab (2298:2298:2298) (2535:2535:2535)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1308:1308:1308)) - (PORT datab (635:635:635) (668:668:668)) - (PORT datac (844:844:844) (889:889:889)) - (PORT datad (327:327:327) (350:350:350)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2195:2195:2195) (2276:2276:2276)) - (PORT datab (637:637:637) (668:668:668)) - (PORT datac (1697:1697:1697) (1792:1792:1792)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (1431:1431:1431) (1450:1450:1450)) - (PORT datac (1093:1093:1093) (1122:1122:1122)) - (PORT datad (344:344:344) (358:358:358)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1163:1163:1163)) - (PORT datab (1474:1474:1474) (1564:1564:1564)) - (PORT datac (2114:2114:2114) (2227:2227:2227)) - (PORT datad (1651:1651:1651) (1831:1831:1831)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1762:1762:1762)) - (PORT datab (537:537:537) (564:564:564)) - (PORT datac (1014:1014:1014) (1023:1023:1023)) - (PORT datad (1124:1124:1124) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) + (PORT asdata (1216:1216:1216) (1271:1271:1271)) + (PORT sload (1742:1742:1742) (1823:1823:1823)) + (PORT ena (1431:1431:1431) (1435:1435:1435)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1166:1166:1166)) - (PORT datab (245:245:245) (289:289:289)) - (PORT datac (847:847:847) (855:855:855)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datac (1091:1091:1091) (1119:1119:1119)) - (PORT datad (224:224:224) (259:259:259)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (470:470:470)) - (PORT datab (253:253:253) (303:303:303)) - (PORT datac (340:340:340) (362:362:362)) - (PORT datad (217:217:217) (254:254:254)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (621:621:621) (634:634:634)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1207:1207:1207)) - (PORT datab (2915:2915:2915) (2999:2999:2999)) - (PORT datac (1369:1369:1369) (1427:1427:1427)) - (PORT datad (800:800:800) (850:850:850)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (PORT ena (2213:2213:2213) (2213:2213:2213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1858:1858:1858) (1939:1939:1939)) - (PORT datab (1661:1661:1661) (1809:1809:1809)) - (PORT datac (1723:1723:1723) (1805:1805:1805)) - (PORT datad (882:882:882) (900:900:900)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (711:711:711)) - (PORT datab (826:826:826) (874:874:874)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (611:611:611) (623:623:623)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (958:958:958)) - (PORT datab (1170:1170:1170) (1229:1229:1229)) - (PORT datac (1138:1138:1138) (1178:1178:1178)) - (PORT datad (1161:1161:1161) (1197:1197:1197)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (377:377:377)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (867:867:867) (893:893:893)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (892:892:892)) - (PORT datac (794:794:794) (839:839:839)) - (PORT datad (815:815:815) (833:833:833)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (954:954:954)) - (PORT datab (902:902:902) (931:931:931)) - (PORT datac (806:806:806) (822:822:822)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (639:639:639)) - (PORT datab (1166:1166:1166) (1208:1208:1208)) - (PORT datac (909:909:909) (953:953:953)) - (PORT datad (585:585:585) (613:613:613)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1349:1349:1349) (1369:1369:1369)) - (PORT datac (628:628:628) (663:663:663)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (884:884:884)) - (PORT datab (668:668:668) (707:707:707)) - (PORT datac (825:825:825) (860:860:860)) - (PORT datad (819:819:819) (837:837:837)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (855:855:855)) - (PORT datac (354:354:354) (381:381:381)) - (PORT datad (849:849:849) (871:871:871)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (950:950:950)) - (PORT datab (637:637:637) (657:657:657)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (594:594:594) (606:606:606)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1160:1160:1160)) - (PORT datab (246:246:246) (293:293:293)) - (PORT datad (1182:1182:1182) (1220:1220:1220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1316:1316:1316) (1375:1375:1375)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2397:2397:2397) (2589:2589:2589)) - (PORT d[1] (2605:2605:2605) (2682:2682:2682)) - (PORT d[2] (1244:1244:1244) (1312:1312:1312)) - (PORT d[3] (1263:1263:1263) (1323:1323:1323)) - (PORT d[4] (2021:2021:2021) (2110:2110:2110)) - (PORT d[5] (1254:1254:1254) (1323:1323:1323)) - (PORT d[6] (1478:1478:1478) (1511:1511:1511)) - (PORT d[7] (2356:2356:2356) (2492:2492:2492)) - (PORT d[8] (2505:2505:2505) (2668:2668:2668)) - (PORT d[9] (775:775:775) (840:840:840)) - (PORT d[10] (1752:1752:1752) (1831:1831:1831)) - (PORT d[11] (1174:1174:1174) (1217:1217:1217)) - (PORT d[12] (728:728:728) (783:783:783)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1797:1797:1797) (1781:1781:1781)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (1825:1825:1825) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (961:961:961) (961:961:961)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2420:2420:2420) (2630:2630:2630)) - (PORT d[1] (1241:1241:1241) (1313:1313:1313)) - (PORT d[2] (1662:1662:1662) (1741:1741:1741)) - (PORT d[3] (1596:1596:1596) (1691:1691:1691)) - (PORT d[4] (2978:2978:2978) (3155:3155:3155)) - (PORT d[5] (1264:1264:1264) (1317:1317:1317)) - (PORT d[6] (1560:1560:1560) (1657:1657:1657)) - (PORT d[7] (1291:1291:1291) (1338:1338:1338)) - (PORT d[8] (1256:1256:1256) (1319:1319:1319)) - (PORT d[9] (1080:1080:1080) (1170:1170:1170)) - (PORT d[10] (1071:1071:1071) (1158:1158:1158)) - (PORT d[11] (2213:2213:2213) (2338:2338:2338)) - (PORT d[12] (1088:1088:1088) (1179:1179:1179)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1220:1220:1220) (1163:1163:1163)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2327:2327:2327) (2302:2302:2302)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1310:1310:1310) (1368:1368:1368)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2700:2700:2700) (2899:2899:2899)) - (PORT d[1] (2882:2882:2882) (2995:2995:2995)) - (PORT d[2] (1236:1236:1236) (1287:1287:1287)) - (PORT d[3] (979:979:979) (1033:1033:1033)) - (PORT d[4] (2053:2053:2053) (2138:2138:2138)) - (PORT d[5] (951:951:951) (1003:1003:1003)) - (PORT d[6] (1440:1440:1440) (1451:1451:1451)) - (PORT d[7] (2650:2650:2650) (2803:2803:2803)) - (PORT d[8] (2518:2518:2518) (2699:2699:2699)) - (PORT d[9] (743:743:743) (798:798:798)) - (PORT d[10] (755:755:755) (811:811:811)) - (PORT d[11] (2821:2821:2821) (3003:3003:3003)) - (PORT d[12] (715:715:715) (752:752:752)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1241:1241:1241) (1217:1217:1217)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1869:1869:1869)) - (PORT d[0] (1450:1450:1450) (1417:1417:1417)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1828:1828:1828)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (986:986:986) (991:991:991)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (677:677:677) (699:699:699)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2669:2669:2669) (2901:2901:2901)) - (PORT d[1] (1288:1288:1288) (1360:1360:1360)) - (PORT d[2] (1665:1665:1665) (1743:1743:1743)) - (PORT d[3] (1565:1565:1565) (1640:1640:1640)) - (PORT d[4] (2970:2970:2970) (3148:3148:3148)) - (PORT d[5] (1271:1271:1271) (1329:1329:1329)) - (PORT d[6] (1509:1509:1509) (1602:1602:1602)) - (PORT d[7] (1615:1615:1615) (1649:1649:1649)) - (PORT d[8] (1553:1553:1553) (1653:1653:1653)) - (PORT d[9] (1383:1383:1383) (1478:1478:1478)) - (PORT d[10] (1335:1335:1335) (1424:1424:1424)) - (PORT d[11] (1876:1876:1876) (1999:1999:1999)) - (PORT d[12] (1381:1381:1381) (1486:1486:1486)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1214:1214:1214)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2701:2701:2701) (2725:2725:2725)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1532:1532:1532)) - (PORT datab (1228:1228:1228) (1286:1286:1286)) - (PORT datad (1444:1444:1444) (1432:1432:1432)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1583:1583:1583)) - (PORT datab (1831:1831:1831) (1977:1977:1977)) - (PORT datac (1437:1437:1437) (1482:1482:1482)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1260:1260:1260) (1277:1277:1277)) - (PORT clk (1852:1852:1852) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2793:2793:2793) (2950:2950:2950)) - (PORT d[1] (1830:1830:1830) (1942:1942:1942)) - (PORT d[2] (1907:1907:1907) (2035:2035:2035)) - (PORT d[3] (2153:2153:2153) (2289:2289:2289)) - (PORT d[4] (2370:2370:2370) (2502:2502:2502)) - (PORT d[5] (1869:1869:1869) (1972:1972:1972)) - (PORT d[6] (2343:2343:2343) (2464:2464:2464)) - (PORT d[7] (2215:2215:2215) (2277:2277:2277)) - (PORT d[8] (3168:3168:3168) (3268:3268:3268)) - (PORT d[9] (1739:1739:1739) (1883:1883:1883)) - (PORT d[10] (1634:1634:1634) (1763:1763:1763)) - (PORT d[11] (2386:2386:2386) (2535:2535:2535)) - (PORT d[12] (2455:2455:2455) (2610:2610:2610)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1782:1782:1782) (1793:1793:1793)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (PORT d[0] (3271:3271:3271) (3211:3211:3211)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1805:1805:1805)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1887:1887:1887) (1934:1934:1934)) - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4443:4443:4443) (4548:4548:4548)) - (PORT d[1] (4421:4421:4421) (4559:4559:4559)) - (PORT d[2] (4547:4547:4547) (4625:4625:4625)) - (PORT d[3] (4250:4250:4250) (4323:4323:4323)) - (PORT d[4] (4357:4357:4357) (4435:4435:4435)) - (PORT d[5] (4381:4381:4381) (4503:4503:4503)) - (PORT d[6] (4351:4351:4351) (4470:4470:4470)) - (PORT d[7] (4377:4377:4377) (4506:4506:4506)) - (PORT d[8] (4630:4630:4630) (4748:4748:4748)) - (PORT d[9] (4422:4422:4422) (4527:4527:4527)) - (PORT d[10] (4416:4416:4416) (4515:4515:4515)) - (PORT d[11] (4442:4442:4442) (4583:4583:4583)) - (PORT d[12] (4386:4386:4386) (4473:4473:4473)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1807:1807:1807)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1270:1270:1270)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2794:2794:2794) (2951:2951:2951)) - (PORT d[1] (1828:1828:1828) (1938:1938:1938)) - (PORT d[2] (2259:2259:2259) (2395:2395:2395)) - (PORT d[3] (2157:2157:2157) (2295:2295:2295)) - (PORT d[4] (2357:2357:2357) (2500:2500:2500)) - (PORT d[5] (1865:1865:1865) (1964:1964:1964)) - (PORT d[6] (1845:1845:1845) (1965:1965:1965)) - (PORT d[7] (1871:1871:1871) (1918:1918:1918)) - (PORT d[8] (3142:3142:3142) (3254:3254:3254)) - (PORT d[9] (1716:1716:1716) (1858:1858:1858)) - (PORT d[10] (3925:3925:3925) (4111:4111:4111)) - (PORT d[11] (2389:2389:2389) (2540:2540:2540)) - (PORT d[12] (1686:1686:1686) (1819:1819:1819)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1704:1704:1704) (1656:1656:1656)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (2935:2935:2935) (2984:2984:2984)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1853:1853:1853) (1917:1917:1917)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4455:4455:4455) (4544:4544:4544)) - (PORT d[1] (4366:4366:4366) (4482:4482:4482)) - (PORT d[2] (4416:4416:4416) (4497:4497:4497)) - (PORT d[3] (4264:4264:4264) (4327:4327:4327)) - (PORT d[4] (4354:4354:4354) (4419:4419:4419)) - (PORT d[5] (4403:4403:4403) (4526:4526:4526)) - (PORT d[6] (4425:4425:4425) (4522:4522:4522)) - (PORT d[7] (4346:4346:4346) (4468:4468:4468)) - (PORT d[8] (4655:4655:4655) (4776:4776:4776)) - (PORT d[9] (4485:4485:4485) (4573:4573:4573)) - (PORT d[10] (4462:4462:4462) (4577:4577:4577)) - (PORT d[11] (4470:4470:4470) (4590:4590:4590)) - (PORT d[12] (4386:4386:4386) (4471:4471:4471)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2492:2492:2492) (2622:2622:2622)) - (PORT d[1] (2647:2647:2647) (2790:2790:2790)) - (PORT d[2] (2231:2231:2231) (2391:2391:2391)) - (PORT d[3] (2097:2097:2097) (2237:2237:2237)) - (PORT d[4] (1753:1753:1753) (1859:1859:1859)) - (PORT d[5] (2146:2146:2146) (2271:2271:2271)) - (PORT d[6] (2408:2408:2408) (2553:2553:2553)) - (PORT d[7] (3417:3417:3417) (3493:3493:3493)) - (PORT d[8] (2875:2875:2875) (2972:2972:2972)) - (PORT d[9] (2055:2055:2055) (2224:2224:2224)) - (PORT d[10] (1917:1917:1917) (2062:2062:2062)) - (PORT d[11] (2114:2114:2114) (2235:2235:2235)) - (PORT d[12] (2265:2265:2265) (2423:2423:2423)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2593:2593:2593) (2672:2672:2672)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1225:1225:1225)) - (PORT datab (307:307:307) (399:399:399)) - (PORT datac (1148:1148:1148) (1222:1222:1222)) - (PORT datad (1447:1447:1447) (1525:1525:1525)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1960:1960:1960) (2070:2070:2070)) - (PORT d[1] (3002:3002:3002) (3172:3172:3172)) - (PORT d[2] (2265:2265:2265) (2363:2363:2363)) - (PORT d[3] (3641:3641:3641) (3796:3796:3796)) - (PORT d[4] (2594:2594:2594) (2773:2773:2773)) - (PORT d[5] (4146:4146:4146) (4262:4262:4262)) - (PORT d[6] (2765:2765:2765) (2873:2873:2873)) - (PORT d[7] (3716:3716:3716) (3795:3795:3795)) - (PORT d[8] (2020:2020:2020) (2071:2071:2071)) - (PORT d[9] (2145:2145:2145) (2236:2236:2236)) - (PORT d[10] (2368:2368:2368) (2463:2463:2463)) - (PORT d[11] (2810:2810:2810) (2995:2995:2995)) - (PORT d[12] (3841:3841:3841) (4091:4091:4091)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) - (PORT d[0] (2266:2266:2266) (2242:2242:2242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1342:1342:1342)) - (PORT datab (1229:1229:1229) (1288:1288:1288)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1047:1047:1047) (1066:1066:1066)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1237:1237:1237)) - (PORT datab (309:309:309) (401:401:401)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1483:1483:1483)) - (PORT datab (2298:2298:2298) (2535:2535:2535)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~99) - (DELAY - (ABSOLUTE - (PORT datab (1221:1221:1221) (1330:1330:1330)) - (PORT datac (2534:2534:2534) (2774:2774:2774)) - (PORT datad (1462:1462:1462) (1583:1583:1583)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (1558:1558:1558) (1597:1597:1597)) - (PORT datab (435:435:435) (477:477:477)) - (PORT datac (597:597:597) (599:599:599)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (2243:2243:2243) (2321:2321:2321)) - (PORT datab (436:436:436) (477:477:477)) - (PORT datac (1209:1209:1209) (1322:1322:1322)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1886:1886:1886) (1930:1930:1930)) - (PORT datab (426:426:426) (464:464:464)) - (PORT datac (349:349:349) (377:377:377)) - (PORT datad (1129:1129:1129) (1163:1163:1163)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (252:252:252) (303:303:303)) - (PORT datac (575:575:575) (628:628:628)) - (PORT datad (216:216:216) (251:251:251)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (694:694:694) (717:717:717)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (INSTANCE z80_\|address_pins_\|abus\[11\]\~18) (DELAY (ABSOLUTE - (PORT dataa (779:779:779) (847:847:847)) - (PORT datac (1845:1845:1845) (1972:1972:1972)) - (PORT datad (1691:1691:1691) (1766:1766:1766)) - (IOPATH dataa combout (303:303:303) (308:308:308)) + (PORT datab (651:651:651) (725:725:725)) + (PORT datac (1094:1094:1094) (1213:1213:1213)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) (DELAY (ABSOLUTE - (PORT dataa (1757:1757:1757) (1850:1850:1850)) - (PORT datab (1655:1655:1655) (1806:1806:1806)) - (PORT datac (1039:1039:1039) (1104:1104:1104)) - (PORT datad (1816:1816:1816) (1892:1892:1892)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (608:608:608)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (614:614:614) (677:677:677)) - (PORT datad (1147:1147:1147) (1181:1181:1181)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1698:1698:1698)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (366:366:366) (433:433:433)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (760:760:760) (855:855:855)) - (PORT datad (307:307:307) (414:414:414)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (806:806:806) (835:835:835)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datad (589:589:589) (604:604:604)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1224:1224:1224) (1228:1228:1228)) + (PORT asdata (1176:1176:1176) (1236:1236:1236)) + (PORT sload (1742:1742:1742) (1823:1823:1823)) + (PORT ena (1431:1431:1431) (1435:1435:1435)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (883:883:883)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (1149:1149:1149) (1212:1212:1212)) - (PORT datad (1552:1552:1552) (1679:1679:1679)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1560:1560:1560) (1552:1552:1552)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1861:1861:1861) (1999:1999:1999)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (PORT ena (993:993:993) (1000:1000:1000)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (459:459:459)) - (PORT datab (294:294:294) (388:388:388)) - (PORT datad (252:252:252) (326:326:326)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2306:2306:2306) (2453:2453:2453)) - (PORT datab (1239:1239:1239) (1285:1285:1285)) - (PORT datac (1152:1152:1152) (1203:1203:1203)) - (PORT datad (1219:1219:1219) (1229:1229:1229)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (703:703:703) (722:722:722)) - (PORT datad (905:905:905) (936:936:936)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1544:1544:1544) (1649:1649:1649)) - (PORT datab (634:634:634) (661:661:661)) - (PORT datac (1250:1250:1250) (1279:1279:1279)) - (PORT datad (632:632:632) (654:654:654)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datac (1378:1378:1378) (1490:1490:1490)) + (PORT datad (237:237:237) (304:304:304)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (270:270:270)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (590:590:590) (610:610:610)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (949:949:949)) - (PORT datab (631:631:631) (656:656:656)) - (PORT datac (835:835:835) (860:860:860)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (935:935:935)) - (PORT datab (1457:1457:1457) (1548:1548:1548)) - (PORT datac (589:589:589) (657:657:657)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (716:716:716)) - (PORT datab (861:861:861) (893:893:893)) - (PORT datac (854:854:854) (895:895:895)) - (PORT datad (1006:1006:1006) (1056:1056:1056)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1204:1204:1204)) - (PORT datab (1249:1249:1249) (1294:1294:1294)) - (PORT datac (1289:1289:1289) (1340:1340:1340)) - (PORT datad (1967:1967:1967) (2036:2036:2036)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (945:945:945)) - (PORT datab (1896:1896:1896) (1915:1915:1915)) - (PORT datac (1165:1165:1165) (1201:1201:1201)) - (PORT datad (827:827:827) (850:850:850)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (492:492:492)) - (PORT datab (1030:1030:1030) (1095:1095:1095)) - (PORT datac (1325:1325:1325) (1379:1379:1379)) - (PORT datad (1076:1076:1076) (1126:1126:1126)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (677:677:677)) - (PORT datab (1463:1463:1463) (1517:1517:1517)) - (PORT datac (1482:1482:1482) (1554:1554:1554)) - (PORT datad (1619:1619:1619) (1692:1692:1692)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (2969:2969:2969) (3039:3039:3039)) - (PORT datab (641:641:641) (702:702:702)) - (PORT datac (613:613:613) (625:625:625)) - (PORT datad (215:215:215) (241:241:241)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (478:478:478)) - (PORT datab (895:895:895) (922:922:922)) - (PORT datac (1121:1121:1121) (1142:1142:1142)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (645:645:645)) - (PORT datab (644:644:644) (686:686:686)) - (PORT datac (188:188:188) (228:228:228)) - (PORT datad (1149:1149:1149) (1174:1174:1174)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1207:1207:1207)) - (PORT datab (916:916:916) (951:951:951)) - (PORT datac (188:188:188) (231:231:231)) - (PORT datad (1147:1147:1147) (1187:1187:1187)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (921:921:921)) - (PORT datab (1617:1617:1617) (1648:1648:1648)) - (PORT datac (1115:1115:1115) (1177:1177:1177)) - (PORT datad (1411:1411:1411) (1437:1437:1437)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (886:886:886) (911:911:911)) - (PORT datac (648:648:648) (694:694:694)) - (PORT datad (1181:1181:1181) (1217:1217:1217)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (944:944:944)) - (PORT datab (1282:1282:1282) (1314:1314:1314)) - (PORT datac (648:648:648) (693:693:693)) - (PORT datad (1402:1402:1402) (1434:1434:1434)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1502:1502:1502)) - (PORT datab (1085:1085:1085) (1133:1133:1133)) - (PORT datac (651:651:651) (687:687:687)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1015:1015:1015)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (654:654:654) (703:703:703)) - (PORT datac (610:610:610) (654:654:654)) - (PORT datad (624:624:624) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1183:1183:1183)) - (PORT datab (954:954:954) (995:995:995)) - (PORT datac (602:602:602) (625:625:625)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (952:952:952)) - (PORT datab (673:673:673) (691:691:691)) - (PORT datac (958:958:958) (973:973:973)) - (PORT datad (1082:1082:1082) (1103:1103:1103)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (1455:1455:1455) (1545:1545:1545)) - (PORT datac (1016:1016:1016) (1022:1022:1022)) - (PORT datad (509:509:509) (525:525:525)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (577:577:577)) - (PORT datac (977:977:977) (1064:1064:1064)) - (PORT datad (614:614:614) (684:684:684)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (774:774:774) (853:853:853)) - (PORT datac (679:679:679) (730:730:730)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (431:431:431)) - (PORT datab (763:763:763) (849:849:849)) - (PORT datac (702:702:702) (763:763:763)) - (PORT datad (193:193:193) (229:229:229)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (870:870:870)) - (PORT datab (200:200:200) (238:238:238)) - (PORT datad (591:591:591) (603:603:603)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (820:820:820)) - (PORT datac (935:935:935) (1021:1021:1021)) - (PORT datad (904:904:904) (975:975:975)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (879:879:879)) - (PORT datab (652:652:652) (684:684:684)) - (PORT datac (896:896:896) (981:981:981)) - (PORT datad (267:267:267) (345:345:345)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (376:376:376)) - (PORT datab (931:931:931) (1011:1011:1011)) - (PORT datac (928:928:928) (989:989:989)) - (PORT datad (753:753:753) (839:839:839)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (1020:1020:1020)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) - (DELAY - (ABSOLUTE - (PORT datab (789:789:789) (873:873:873)) - (PORT datac (683:683:683) (751:751:751)) - (PORT datad (735:735:735) (817:817:817)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (412:412:412)) - (PORT datab (740:740:740) (807:807:807)) - (PORT datac (888:888:888) (952:952:952)) - (PORT datad (199:199:199) (235:235:235)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (399:399:399)) - (PORT datab (624:624:624) (685:685:685)) - (PORT datac (677:677:677) (727:727:727)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (870:870:870)) - (PORT datab (416:416:416) (496:496:496)) - (PORT datad (936:936:936) (1016:1016:1016)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1227:1227:1227) (1254:1254:1254)) - (PORT datab (632:632:632) (647:647:647)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1342:1342:1342)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datac (882:882:882) (907:907:907)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1137:1137:1137)) - (PORT datac (848:848:848) (867:867:867)) - (PORT datad (708:708:708) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT datab (740:740:740) (830:830:830)) - (PORT datac (1262:1262:1262) (1334:1334:1334)) - (PORT datad (969:969:969) (1032:1032:1032)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1060:1060:1060) (1130:1130:1130)) - (PORT datac (759:759:759) (838:838:838)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (303:303:303) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (855:855:855)) - (PORT datac (971:971:971) (1051:1051:1051)) - (PORT datad (645:645:645) (724:724:724)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (948:948:948)) - (PORT datab (888:888:888) (920:920:920)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (395:395:395)) - (PORT datab (1062:1062:1062) (1131:1131:1131)) - (PORT datac (708:708:708) (773:773:773)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1087:1087:1087)) - (PORT datab (920:920:920) (962:962:962)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1214:1214:1214)) - (PORT datab (714:714:714) (771:771:771)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1236:1236:1236) (1327:1327:1327)) - (PORT datac (984:984:984) (1047:1047:1047)) - (PORT datad (651:651:651) (732:732:732)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (705:705:705) (774:774:774)) - (PORT datad (204:204:204) (235:235:235)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (923:923:923) (952:952:952)) - (PORT datad (573:573:573) (604:604:604)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1138:1138:1138)) - (PORT datab (420:420:420) (502:502:502)) - (PORT datac (998:998:998) (1056:1056:1056)) - (PORT datad (603:603:603) (663:663:663)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (404:404:404)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (665:665:665) (729:729:729)) - (PORT datad (635:635:635) (652:652:652)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (907:907:907)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (711:711:711) (785:785:785)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (663:663:663)) - (PORT datab (759:759:759) (844:844:844)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (909:909:909) (965:965:965)) - (PORT datac (217:217:217) (293:293:293)) - (PORT datad (1398:1398:1398) (1439:1439:1439)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1327:1327:1327)) - (PORT datab (1300:1300:1300) (1375:1375:1375)) - (PORT datac (685:685:685) (784:784:784)) - (PORT datad (717:717:717) (806:806:806)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1326:1326:1326)) - (PORT datac (985:985:985) (1050:1050:1050)) - (PORT datad (653:653:653) (736:736:736)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1125:1125:1125)) - (PORT datab (948:948:948) (1016:1016:1016)) - (PORT datac (900:900:900) (914:914:914)) - (PORT datad (729:729:729) (803:803:803)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (619:619:619) (630:630:630)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (588:588:588)) - (PORT datab (887:887:887) (942:942:942)) - (PORT datac (616:616:616) (637:637:637)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (973:973:973) (1052:1052:1052)) - (PORT datad (462:462:462) (533:533:533)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (751:751:751)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datac (2427:2427:2427) (2603:2603:2603)) - (PORT datad (882:882:882) (935:935:935)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (920:920:920)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (344:344:344) (365:365:365)) - (PORT datad (615:615:615) (626:626:626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1131:1131:1131)) - (PORT datab (1259:1259:1259) (1374:1374:1374)) - (PORT datac (2575:2575:2575) (2806:2806:2806)) - (PORT datad (635:635:635) (671:671:671)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1113:1113:1113)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2540:2540:2540) (2718:2718:2718)) - (PORT d[1] (3611:3611:3611) (3828:3828:3828)) - (PORT d[2] (2390:2390:2390) (2485:2485:2485)) - (PORT d[3] (4294:4294:4294) (4502:4502:4502)) - (PORT d[4] (3192:3192:3192) (3431:3431:3431)) - (PORT d[5] (4755:4755:4755) (4922:4922:4922)) - (PORT d[6] (2539:2539:2539) (2642:2642:2642)) - (PORT d[7] (1407:1407:1407) (1444:1444:1444)) - (PORT d[8] (2834:2834:2834) (2992:2992:2992)) - (PORT d[9] (1811:1811:1811) (1840:1840:1840)) - (PORT d[10] (1723:1723:1723) (1759:1759:1759)) - (PORT d[11] (3413:3413:3413) (3683:3683:3683)) - (PORT d[12] (4600:4600:4600) (4890:4890:4890)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1678:1678:1678) (1622:1622:1622)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2247:2247:2247) (2230:2230:2230)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1276:1276:1276)) - (PORT datab (667:667:667) (705:705:705)) - (PORT datac (1386:1386:1386) (1467:1467:1467)) - (PORT datad (1101:1101:1101) (1113:1113:1113)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1145:1145:1145) (1137:1137:1137)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1692:1692:1692) (1821:1821:1821)) - (PORT d[1] (2831:2831:2831) (2904:2904:2904)) - (PORT d[2] (2412:2412:2412) (2479:2479:2479)) - (PORT d[3] (4272:4272:4272) (4479:4479:4479)) - (PORT d[4] (990:990:990) (1023:1023:1023)) - (PORT d[5] (2242:2242:2242) (2271:2271:2271)) - (PORT d[6] (2540:2540:2540) (2643:2643:2643)) - (PORT d[7] (1371:1371:1371) (1386:1386:1386)) - (PORT d[8] (2806:2806:2806) (2960:2960:2960)) - (PORT d[9] (1487:1487:1487) (1517:1517:1517)) - (PORT d[10] (1989:1989:1989) (2026:2026:2026)) - (PORT d[11] (3414:3414:3414) (3684:3684:3684)) - (PORT d[12] (4681:4681:4681) (4989:4989:4989)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2538:2538:2538) (2548:2548:2548)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (2226:2226:2226) (2231:2231:2231)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (743:743:743) (772:772:772)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3064:3064:3064) (3319:3319:3319)) - (PORT d[1] (1624:1624:1624) (1726:1726:1726)) - (PORT d[2] (1003:1003:1003) (1056:1056:1056)) - (PORT d[3] (954:954:954) (1004:1004:1004)) - (PORT d[4] (3267:3267:3267) (3445:3445:3445)) - (PORT d[5] (969:969:969) (999:999:999)) - (PORT d[6] (1577:1577:1577) (1697:1697:1697)) - (PORT d[7] (987:987:987) (1009:1009:1009)) - (PORT d[8] (1275:1275:1275) (1343:1343:1343)) - (PORT d[9] (1064:1064:1064) (1130:1130:1130)) - (PORT d[10] (1030:1030:1030) (1088:1088:1088)) - (PORT d[11] (2187:2187:2187) (2344:2344:2344)) - (PORT d[12] (1076:1076:1076) (1160:1160:1160)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (956:956:956) (917:917:917)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2993:2993:2993) (3045:3045:3045)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (997:997:997) (1025:1025:1025)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3012:3012:3012) (3251:3251:3251)) - (PORT d[1] (1609:1609:1609) (1697:1697:1697)) - (PORT d[2] (983:983:983) (1016:1016:1016)) - (PORT d[3] (961:961:961) (994:994:994)) - (PORT d[4] (1434:1434:1434) (1457:1457:1457)) - (PORT d[5] (948:948:948) (977:977:977)) - (PORT d[6] (1862:1862:1862) (1998:1998:1998)) - (PORT d[7] (940:940:940) (959:959:959)) - (PORT d[8] (1274:1274:1274) (1339:1339:1339)) - (PORT d[9] (752:752:752) (813:813:813)) - (PORT d[10] (755:755:755) (815:815:815)) - (PORT d[11] (2517:2517:2517) (2676:2676:2676)) - (PORT d[12] (773:773:773) (837:837:837)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (682:682:682) (624:624:624)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (1782:1782:1782) (1777:1777:1777)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2263:2263:2263) (2427:2427:2427)) - (PORT d[1] (2806:2806:2806) (2855:2855:2855)) - (PORT d[2] (2405:2405:2405) (2483:2483:2483)) - (PORT d[3] (4558:4558:4558) (4765:4765:4765)) - (PORT d[4] (1002:1002:1002) (1050:1050:1050)) - (PORT d[5] (2195:2195:2195) (2238:2238:2238)) - (PORT d[6] (924:924:924) (944:944:944)) - (PORT d[7] (1330:1330:1330) (1332:1332:1332)) - (PORT d[8] (2826:2826:2826) (2976:2976:2976)) - (PORT d[9] (1473:1473:1473) (1523:1523:1523)) - (PORT d[10] (1998:1998:1998) (2047:2047:2047)) - (PORT d[11] (3718:3718:3718) (4008:4008:4008)) - (PORT d[12] (4709:4709:4709) (5022:5022:5022)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (1305:1305:1305) (1337:1337:1337)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1966:1966:1966) (2027:2027:2027)) - (PORT datab (1520:1520:1520) (1598:1598:1598)) - (PORT datac (885:885:885) (908:908:908)) - (PORT datad (1061:1061:1061) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (915:915:915) (934:934:934)) - (PORT datac (1386:1386:1386) (1466:1466:1466)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1589:1589:1589)) - (PORT datab (1130:1130:1130) (1152:1152:1152)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1801:1801:1801) (1899:1899:1899)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1489:1489:1489)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2489:2489:2489) (2600:2600:2600)) - (PORT d[1] (2698:2698:2698) (2838:2838:2838)) - (PORT d[2] (2572:2572:2572) (2698:2698:2698)) - (PORT d[3] (3356:3356:3356) (3488:3488:3488)) - (PORT d[4] (2297:2297:2297) (2449:2449:2449)) - (PORT d[5] (3794:3794:3794) (3901:3901:3901)) - (PORT d[6] (2564:2564:2564) (2676:2676:2676)) - (PORT d[7] (3403:3403:3403) (3457:3457:3457)) - (PORT d[8] (2931:2931:2931) (3032:3032:3032)) - (PORT d[9] (2737:2737:2737) (2834:2834:2834)) - (PORT d[10] (2604:2604:2604) (2714:2714:2714)) - (PORT d[11] (2512:2512:2512) (2702:2702:2702)) - (PORT d[12] (3523:3523:3523) (3743:3743:3743)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2846:2846:2846) (2893:2893:2893)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (3535:3535:3535) (3484:3484:3484)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2458:2458:2458) (2451:2451:2451)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4479:4479:4479) (4514:4514:4514)) - (PORT d[1] (4465:4465:4465) (4517:4517:4517)) - (PORT d[2] (4544:4544:4544) (4551:4551:4551)) - (PORT d[3] (4403:4403:4403) (4415:4415:4415)) - (PORT d[4] (4292:4292:4292) (4432:4432:4432)) - (PORT d[5] (4375:4375:4375) (4440:4440:4440)) - (PORT d[6] (4446:4446:4446) (4486:4486:4486)) - (PORT d[7] (4358:4358:4358) (4399:4399:4399)) - (PORT d[8] (4409:4409:4409) (4489:4489:4489)) - (PORT d[9] (4419:4419:4419) (4498:4498:4498)) - (PORT d[10] (4270:4270:4270) (4305:4305:4305)) - (PORT d[11] (4393:4393:4393) (4493:4493:4493)) - (PORT d[12] (4247:4247:4247) (4253:4253:4253)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (2618:2618:2618) (2852:2852:2852)) - (PORT datab (2469:2469:2469) (2595:2595:2595)) - (PORT datac (1575:1575:1575) (1686:1686:1686)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1395:1395:1395) (1438:1438:1438)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1950:1950:1950) (2069:2069:2069)) - (PORT d[1] (3022:3022:3022) (3167:3167:3167)) - (PORT d[2] (1806:1806:1806) (1910:1910:1910)) - (PORT d[3] (3658:3658:3658) (3808:3808:3808)) - (PORT d[4] (2619:2619:2619) (2778:2778:2778)) - (PORT d[5] (4118:4118:4118) (4230:4230:4230)) - (PORT d[6] (2735:2735:2735) (2827:2827:2827)) - (PORT d[7] (1984:1984:1984) (2046:2046:2046)) - (PORT d[8] (1994:1994:1994) (2040:2040:2040)) - (PORT d[9] (2437:2437:2437) (2548:2548:2548)) - (PORT d[10] (2646:2646:2646) (2757:2757:2757)) - (PORT d[11] (2789:2789:2789) (2994:2994:2994)) - (PORT d[12] (4582:4582:4582) (4832:4832:4832)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1561:1561:1561) (1515:1515:1515)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3203:3203:3203) (3240:3240:3240)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2190:2190:2190) (2181:2181:2181)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4546:4546:4546) (4580:4580:4580)) - (PORT d[1] (4461:4461:4461) (4513:4513:4513)) - (PORT d[2] (4466:4466:4466) (4476:4476:4476)) - (PORT d[3] (4422:4422:4422) (4460:4460:4460)) - (PORT d[4] (4363:4363:4363) (4523:4523:4523)) - (PORT d[5] (4348:4348:4348) (4415:4415:4415)) - (PORT d[6] (4445:4445:4445) (4467:4467:4467)) - (PORT d[7] (4345:4345:4345) (4449:4449:4449)) - (PORT d[8] (4480:4480:4480) (4560:4560:4560)) - (PORT d[9] (4577:4577:4577) (4641:4641:4641)) - (PORT d[10] (4311:4311:4311) (4390:4390:4390)) - (PORT d[11] (4436:4436:4436) (4532:4532:4532)) - (PORT d[12] (4251:4251:4251) (4274:4274:4274)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2469:2469:2469) (2602:2602:2602)) - (PORT d[1] (2377:2377:2377) (2524:2524:2524)) - (PORT d[2] (2274:2274:2274) (2431:2431:2431)) - (PORT d[3] (2180:2180:2180) (2330:2330:2330)) - (PORT d[4] (2086:2086:2086) (2172:2172:2172)) - (PORT d[5] (2417:2417:2417) (2540:2540:2540)) - (PORT d[6] (2442:2442:2442) (2606:2606:2606)) - (PORT d[7] (3149:3149:3149) (3211:3211:3211)) - (PORT d[8] (2864:2864:2864) (2942:2942:2942)) - (PORT d[9] (2362:2362:2362) (2550:2550:2550)) - (PORT d[10] (3296:3296:3296) (3440:3440:3440)) - (PORT d[11] (2098:2098:2098) (2200:2200:2200)) - (PORT d[12] (2283:2283:2283) (2461:2461:2461)) - (PORT clk (1859:1859:1859) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (PORT d[0] (2575:2575:2575) (2667:2667:2667)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1848:1848:1848)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1012:1012:1012)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1012:1012:1012)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1012:1012:1012)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (2613:2613:2613) (2845:2845:2845)) - (PORT datab (2470:2470:2470) (2597:2597:2597)) - (PORT datac (1305:1305:1305) (1374:1374:1374)) - (PORT datad (1662:1662:1662) (1719:1719:1719)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1292:1292:1292)) - (PORT datab (741:741:741) (851:851:851)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1965:1965:1965) (2023:2023:2023)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1550:1550:1550) (1580:1580:1580)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (2783:2783:2783) (2886:2886:2886)) - (PORT datab (938:938:938) (1032:1032:1032)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (1506:1506:1506) (1530:1530:1530)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (297:297:297)) - (PORT datab (859:859:859) (885:885:885)) - (PORT datac (623:623:623) (656:656:656)) - (PORT datad (1129:1129:1129) (1160:1160:1160)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (420:420:420) (450:450:450)) - (PORT datac (363:363:363) (431:431:431)) - (PORT datad (386:386:386) (412:412:412)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1315:1315:1315)) - (PORT datab (372:372:372) (397:397:397)) - (PORT datac (825:825:825) (876:876:876)) - (PORT datad (567:567:567) (578:578:578)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1940:1940:1940) (1962:1962:1962)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2328:2328:2328)) - (PORT datac (1575:1575:1575) (1707:1707:1707)) - (PORT datad (1688:1688:1688) (1747:1747:1747)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (897:897:897)) - (PORT datab (1870:1870:1870) (1946:1946:1946)) - (PORT datac (1151:1151:1151) (1176:1176:1176)) - (PORT datad (624:624:624) (661:661:661)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (678:678:678)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (1170:1170:1170) (1209:1209:1209)) - (PORT datad (844:844:844) (899:899:899)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (458:458:458)) - (PORT datab (603:603:603) (621:621:621)) - (PORT datad (1132:1132:1132) (1160:1160:1160)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1500:1500:1500) (1546:1546:1546)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2373:2373:2373) (2567:2567:2567)) - (PORT d[1] (2551:2551:2551) (2651:2651:2651)) - (PORT d[2] (1549:1549:1549) (1634:1634:1634)) - (PORT d[3] (1265:1265:1265) (1340:1340:1340)) - (PORT d[4] (2004:2004:2004) (2083:2083:2083)) - (PORT d[5] (1260:1260:1260) (1335:1335:1335)) - (PORT d[6] (1712:1712:1712) (1742:1742:1742)) - (PORT d[7] (2350:2350:2350) (2481:2481:2481)) - (PORT d[8] (2475:2475:2475) (2633:2633:2633)) - (PORT d[9] (1038:1038:1038) (1095:1095:1095)) - (PORT d[10] (1743:1743:1743) (1843:1843:1843)) - (PORT d[11] (1460:1460:1460) (1528:1528:1528)) - (PORT d[12] (1011:1011:1011) (1068:1068:1068)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1776:1776:1776) (1775:1775:1775)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2106:2106:2106) (2095:2095:2095)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1472:1472:1472) (1514:1514:1514)) + (PORT d[0] (1278:1278:1278) (1312:1312:1312)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -39456,19 +32475,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2336:2336:2336) (2510:2510:2510)) - (PORT d[1] (1981:1981:1981) (2064:2064:2064)) - (PORT d[2] (1851:1851:1851) (1954:1954:1954)) - (PORT d[3] (2217:2217:2217) (2311:2311:2311)) - (PORT d[4] (2028:2028:2028) (2096:2096:2096)) - (PORT d[5] (1586:1586:1586) (1680:1680:1680)) - (PORT d[6] (1724:1724:1724) (1771:1771:1771)) - (PORT d[7] (2272:2272:2272) (2376:2376:2376)) - (PORT d[8] (2487:2487:2487) (2660:2660:2660)) - (PORT d[9] (1183:1183:1183) (1248:1248:1248)) - (PORT d[10] (1648:1648:1648) (1719:1719:1719)) - (PORT d[11] (1194:1194:1194) (1243:1243:1243)) - (PORT d[12] (1050:1050:1050) (1129:1129:1129)) + (PORT d[0] (1262:1262:1262) (1331:1331:1331)) + (PORT d[1] (1212:1212:1212) (1237:1237:1237)) + (PORT d[2] (1271:1271:1271) (1322:1322:1322)) + (PORT d[3] (3082:3082:3082) (3281:3281:3281)) + (PORT d[4] (1956:1956:1956) (2111:2111:2111)) + (PORT d[5] (1272:1272:1272) (1312:1312:1312)) + (PORT d[6] (1230:1230:1230) (1267:1267:1267)) + (PORT d[7] (1564:1564:1564) (1636:1636:1636)) + (PORT d[8] (1722:1722:1722) (1799:1799:1799)) + (PORT d[9] (1787:1787:1787) (1851:1851:1851)) + (PORT d[10] (2180:2180:2180) (2343:2343:2343)) + (PORT d[11] (1692:1692:1692) (1782:1782:1782)) + (PORT d[12] (1656:1656:1656) (1809:1809:1809)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -39481,7 +32500,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1540:1540:1540) (1561:1561:1561)) + (PORT d[0] (2032:2032:2032) (2055:2055:2055)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -39495,7 +32514,7 @@ (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (1987:1987:1987) (1984:1984:1984)) + (PORT d[0] (2616:2616:2616) (2631:2631:2631)) ) ) ) @@ -39591,13 +32610,254 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (538:538:538) (569:569:569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1011:1011:1011) (1066:1066:1066)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (2096:2096:2096) (2229:2229:2229)) + (PORT datab (1000:1000:1000) (1056:1056:1056)) + (PORT datac (1757:1757:1757) (1816:1816:1816)) + (PORT datad (218:218:218) (253:253:253)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1390:1390:1390)) + (PORT datab (1520:1520:1520) (1621:1621:1621)) + (PORT datad (1234:1234:1234) (1303:1303:1303)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1187:1187:1187) (1224:1224:1224)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2600:2600:2600) (2703:2703:2703)) + (PORT d[1] (2784:2784:2784) (2796:2796:2796)) + (PORT d[2] (2301:2301:2301) (2377:2377:2377)) + (PORT d[3] (862:862:862) (890:890:890)) + (PORT d[4] (2343:2343:2343) (2564:2564:2564)) + (PORT d[5] (2790:2790:2790) (2837:2837:2837)) + (PORT d[6] (4037:4037:4037) (4243:4243:4243)) + (PORT d[7] (1417:1417:1417) (1423:1423:1423)) + (PORT d[8] (1185:1185:1185) (1217:1217:1217)) + (PORT d[9] (932:932:932) (960:960:960)) + (PORT d[10] (968:968:968) (1021:1021:1021)) + (PORT d[11] (2849:2849:2849) (2976:2976:2976)) + (PORT d[12] (1858:1858:1858) (1904:1904:1904)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2752:2752:2752) (2713:2713:2713)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (3004:3004:3004) (2955:2955:2955)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (2098:2098:2098) (2224:2224:2224)) + (PORT datab (1000:1000:1000) (1057:1057:1057)) + (PORT datac (1760:1760:1760) (1813:1813:1813)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1524:1524:1524) (1626:1626:1626)) + (PORT datac (1219:1219:1219) (1348:1348:1348)) + (PORT datad (1233:1233:1233) (1301:1301:1301)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (914:914:914) (933:933:933)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1217:1217:1217) (1199:1199:1199)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -39609,20 +32869,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2902:2902:2902) (3119:3119:3119)) - (PORT d[1] (3573:3573:3573) (3763:3763:3763)) - (PORT d[2] (1956:1956:1956) (2034:2034:2034)) - (PORT d[3] (3972:3972:3972) (4152:4152:4152)) - (PORT d[4] (3177:3177:3177) (3389:3389:3389)) - (PORT d[5] (4728:4728:4728) (4845:4845:4845)) - (PORT d[6] (2221:2221:2221) (2292:2292:2292)) - (PORT d[7] (1688:1688:1688) (1718:1718:1718)) - (PORT d[8] (3114:3114:3114) (3291:3291:3291)) - (PORT d[9] (1819:1819:1819) (1883:1883:1883)) - (PORT d[10] (2034:2034:2034) (2098:2098:2098)) - (PORT d[11] (3078:3078:3078) (3310:3310:3310)) - (PORT d[12] (4587:4587:4587) (4856:4856:4856)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (3218:3218:3218) (3366:3366:3366)) + (PORT d[1] (3138:3138:3138) (3202:3202:3202)) + (PORT d[2] (3967:3967:3967) (4131:4131:4131)) + (PORT d[3] (1479:1479:1479) (1555:1555:1555)) + (PORT d[4] (2661:2661:2661) (2910:2910:2910)) + (PORT d[5] (3233:3233:3233) (3334:3334:3334)) + (PORT d[6] (3724:3724:3724) (3961:3961:3961)) + (PORT d[7] (1705:1705:1705) (1751:1751:1751)) + (PORT d[8] (3906:3906:3906) (4176:4176:4176)) + (PORT d[9] (4191:4191:4191) (4486:4486:4486)) + (PORT d[10] (3831:3831:3831) (4152:4152:4152)) + (PORT d[11] (1177:1177:1177) (1228:1228:1228)) + (PORT d[12] (2684:2684:2684) (2937:2937:2937)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -39634,8 +32894,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2278:2278:2278) (2264:2264:2264)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1825:1825:1825) (1875:1875:1875)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -39647,8 +32907,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2520:2520:2520) (2539:2539:2539)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2401:2401:2401) (2380:2380:2380)) ) ) ) @@ -39657,7 +32917,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -39667,7 +32927,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -39677,7 +32937,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -39687,7 +32947,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -39695,159 +32955,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1187:1187:1187) (1212:1212:1212)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2569:2569:2569) (2756:2756:2756)) - (PORT d[1] (3637:3637:3637) (3813:3813:3813)) - (PORT d[2] (2109:2109:2109) (2190:2190:2190)) - (PORT d[3] (4259:4259:4259) (4451:4451:4451)) - (PORT d[4] (3209:3209:3209) (3444:3444:3444)) - (PORT d[5] (4699:4699:4699) (4855:4855:4855)) - (PORT d[6] (2574:2574:2574) (2667:2667:2667)) - (PORT d[7] (1420:1420:1420) (1439:1439:1439)) - (PORT d[8] (3134:3134:3134) (3310:3310:3310)) - (PORT d[9] (1832:1832:1832) (1888:1888:1888)) - (PORT d[10] (2003:2003:2003) (2057:2057:2057)) - (PORT d[11] (3398:3398:3398) (3651:3651:3651)) - (PORT d[12] (4571:4571:4571) (4836:4836:4836)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1591:1591:1591) (1527:1527:1527)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2499:2499:2499) (2455:2455:2455)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -39861,7 +32968,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -39870,7 +32977,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39879,7 +32986,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39889,7 +32996,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39899,59 +33006,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (844:844:844)) - (PORT datab (1180:1180:1180) (1276:1276:1276)) - (PORT datac (1196:1196:1196) (1251:1251:1251)) - (PORT datad (1097:1097:1097) (1132:1132:1132)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) + (PORT datac (195:195:195) (228:228:228)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1245:1245:1245) (1338:1338:1338)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1985:1985:1985) (2039:2039:2039)) + (PORT datab (1274:1274:1274) (1328:1328:1328)) + (PORT datac (923:923:923) (978:978:978)) + (PORT datad (1666:1666:1666) (1729:1729:1729)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1234:1234:1234) (1290:1290:1290)) - (PORT datab (1272:1272:1272) (1332:1332:1332)) - (PORT datac (1738:1738:1738) (1814:1814:1814)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (2634:2634:2634) (2764:2764:2764)) - (PORT datab (1940:1940:1940) (2085:2085:2085)) - (PORT datac (2774:2774:2774) (3006:3006:3006)) - (PORT datad (2211:2211:2211) (2282:2282:2282)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (1413:1413:1413) (1528:1528:1528)) + (PORT datac (244:244:244) (325:325:325)) + (PORT datad (884:884:884) (949:949:949)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1585:1585:1585) (1668:1668:1668)) - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (1298:1298:1298) (1336:1336:1336)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -39960,23 +33087,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3186:3186:3186) (3418:3418:3418)) - (PORT d[1] (3339:3339:3339) (3475:3475:3475)) - (PORT d[2] (2251:2251:2251) (2357:2357:2357)) - (PORT d[3] (3642:3642:3642) (3797:3797:3797)) - (PORT d[4] (2928:2928:2928) (3138:3138:3138)) - (PORT d[5] (4390:4390:4390) (4507:4507:4507)) - (PORT d[6] (1780:1780:1780) (1859:1859:1859)) - (PORT d[7] (1974:1974:1974) (2019:2019:2019)) - (PORT d[8] (2011:2011:2011) (2055:2055:2055)) - (PORT d[9] (2117:2117:2117) (2203:2203:2203)) - (PORT d[10] (2341:2341:2341) (2430:2430:2430)) - (PORT d[11] (2795:2795:2795) (3008:3008:3008)) - (PORT d[12] (4293:4293:4293) (4549:4549:4549)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (1817:1817:1817) (1888:1888:1888)) + (PORT d[1] (2038:2038:2038) (2075:2075:2075)) + (PORT d[2] (1311:1311:1311) (1365:1365:1365)) + (PORT d[3] (3348:3348:3348) (3550:3550:3550)) + (PORT d[4] (1968:1968:1968) (2123:2123:2123)) + (PORT d[5] (959:959:959) (996:996:996)) + (PORT d[6] (959:959:959) (1001:1001:1001)) + (PORT d[7] (1200:1200:1200) (1265:1265:1265)) + (PORT d[8] (1721:1721:1721) (1783:1783:1783)) + (PORT d[9] (1802:1802:1802) (1855:1855:1855)) + (PORT d[10] (2503:2503:2503) (2690:2690:2690)) + (PORT d[11] (2004:2004:2004) (2098:2098:2098)) + (PORT d[12] (1666:1666:1666) (1803:1803:1803)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -39985,11 +33112,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1653:1653:1653) (1635:1635:1635)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (1863:1863:1863) (1835:1835:1835)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -39998,60 +33125,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (PORT d[0] (2870:2870:2870) (2886:2886:2886)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2259:2259:2259) (2277:2277:2277)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1813:1813:1813) (1811:1811:1811)) + (PORT clk (1807:1807:1807) (1834:1834:1834)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40062,108 +33189,92 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2178:2178:2178) (2158:2158:2158)) - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4523:4523:4523) (4579:4579:4579)) - (PORT d[1] (4471:4471:4471) (4537:4537:4537)) - (PORT d[2] (4520:4520:4520) (4549:4549:4549)) - (PORT d[3] (4434:4434:4434) (4448:4448:4448)) - (PORT d[4] (4399:4399:4399) (4562:4562:4562)) - (PORT d[5] (4336:4336:4336) (4388:4388:4388)) - (PORT d[6] (4419:4419:4419) (4461:4461:4461)) - (PORT d[7] (4386:4386:4386) (4436:4436:4436)) - (PORT d[8] (4545:4545:4545) (4646:4646:4646)) - (PORT d[9] (4542:4542:4542) (4602:4602:4602)) - (PORT d[10] (4589:4589:4589) (4649:4649:4649)) - (PORT d[11] (4439:4439:4439) (4545:4545:4545)) - (PORT d[12] (4288:4288:4288) (4293:4293:4293)) - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (992:992:992) (997:997:997)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (993:993:993) (998:998:998)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1075:1075:1075)) + (PORT datab (1587:1587:1587) (1635:1635:1635)) + (PORT datac (1476:1476:1476) (1557:1557:1557)) + (PORT datad (1251:1251:1251) (1331:1331:1331)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1353:1353:1353)) + (PORT datab (1816:1816:1816) (1884:1884:1884)) + (PORT datac (1387:1387:1387) (1431:1431:1431)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1682:1682:1682) (1815:1815:1815)) - (PORT d[1] (1648:1648:1648) (1686:1686:1686)) - (PORT d[2] (2268:2268:2268) (2431:2431:2431)) - (PORT d[3] (1863:1863:1863) (1918:1918:1918)) - (PORT d[4] (2378:2378:2378) (2506:2506:2506)) - (PORT d[5] (2549:2549:2549) (2590:2590:2590)) - (PORT d[6] (1990:1990:1990) (2063:2063:2063)) - (PORT d[7] (2031:2031:2031) (2099:2099:2099)) - (PORT d[8] (2125:2125:2125) (2219:2219:2219)) - (PORT d[9] (2009:2009:2009) (2078:2078:2078)) - (PORT d[10] (1655:1655:1655) (1716:1716:1716)) - (PORT d[11] (4351:4351:4351) (4669:4669:4669)) - (PORT d[12] (2155:2155:2155) (2206:2206:2206)) + (PORT d[0] (2282:2282:2282) (2345:2345:2345)) + (PORT d[1] (2186:2186:2186) (2203:2203:2203)) + (PORT d[2] (1989:1989:1989) (2022:2022:2022)) + (PORT d[3] (1174:1174:1174) (1217:1217:1217)) + (PORT d[4] (2551:2551:2551) (2690:2690:2690)) + (PORT d[5] (2435:2435:2435) (2453:2453:2453)) + (PORT d[6] (3702:3702:3702) (3892:3892:3892)) + (PORT d[7] (1720:1720:1720) (1724:1724:1724)) + (PORT d[8] (1257:1257:1257) (1274:1274:1274)) + (PORT d[9] (1584:1584:1584) (1662:1662:1662)) + (PORT d[10] (1795:1795:1795) (1851:1851:1851)) + (PORT d[11] (1701:1701:1701) (1786:1786:1786)) + (PORT d[12] (1562:1562:1562) (1628:1628:1628)) (PORT clk (1856:1856:1856) (1882:1882:1882)) ) ) @@ -40177,7 +33288,7 @@ (DELAY (ABSOLUTE (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (2116:2116:2116) (2085:2085:2085)) + (PORT d[0] (1667:1667:1667) (1687:1687:1687)) ) ) ) @@ -40243,13 +33354,544 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (4389:4389:4389) (4567:4567:4567)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (2000:2000:2000) (2071:2071:2071)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2097:2097:2097) (2228:2228:2228)) + (PORT datab (997:997:997) (1054:1054:1054)) + (PORT datac (1756:1756:1756) (1816:1816:1816)) + (PORT datad (217:217:217) (251:251:251)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (663:663:663) (726:726:726)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (587:587:587)) + (PORT datab (1409:1409:1409) (1559:1559:1559)) + (PORT datac (1641:1641:1641) (1702:1702:1702)) + (PORT datad (272:272:272) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1668:1668:1668) (1703:1703:1703)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (722:722:722) (771:771:771)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1384:1384:1384) (1463:1463:1463)) + (PORT datad (721:721:721) (771:771:771)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1503:1503:1503)) + (PORT datab (731:731:731) (802:802:802)) + (PORT datad (721:721:721) (772:772:772)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1248:1248:1248)) + (PORT datab (1375:1375:1375) (1493:1493:1493)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT datab (626:626:626) (699:699:699)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1304:1304:1304)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (737:737:737)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (888:888:888) (889:889:889)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (841:841:841) (904:904:904)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (680:680:680) (700:700:700)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (724:724:724)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1346:1346:1346) (1347:1347:1347)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (814:814:814)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (397:397:397)) + (PORT datac (606:606:606) (621:621:621)) + (PORT datad (925:925:925) (982:982:982)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (585:585:585)) + (PORT datab (1411:1411:1411) (1560:1560:1560)) + (PORT datac (1643:1643:1643) (1707:1707:1707)) + (PORT datad (275:275:275) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (798:798:798) (845:845:845)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1036:1036:1036)) + (PORT datac (320:320:320) (351:351:351)) + (PORT datad (347:347:347) (371:371:371)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (592:592:592)) + (PORT datab (1407:1407:1407) (1564:1564:1564)) + (PORT datac (1641:1641:1641) (1703:1703:1703)) + (PORT datad (275:275:275) (356:356:356)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (588:588:588)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (972:972:972) (965:965:965)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (324:324:324) (355:355:355)) + (PORT datad (926:926:926) (989:989:989)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1037:1037:1037)) + (PORT datad (345:345:345) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1562:1562:1562) (1663:1663:1663)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (1542:1542:1542) (1597:1597:1597)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) ) ) (TIMINGCHECK @@ -40261,20 +33903,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1624:1624:1624) (1739:1739:1739)) - (PORT d[1] (2987:2987:2987) (3136:3136:3136)) - (PORT d[2] (2558:2558:2558) (2693:2693:2693)) - (PORT d[3] (3334:3334:3334) (3467:3467:3467)) - (PORT d[4] (2606:2606:2606) (2786:2786:2786)) - (PORT d[5] (3822:3822:3822) (3934:3934:3934)) - (PORT d[6] (2246:2246:2246) (2338:2338:2338)) - (PORT d[7] (3413:3413:3413) (3468:3468:3468)) - (PORT d[8] (2931:2931:2931) (3033:3033:3033)) - (PORT d[9] (2477:2477:2477) (2573:2573:2573)) - (PORT d[10] (2626:2626:2626) (2737:2737:2737)) - (PORT d[11] (2491:2491:2491) (2679:2679:2679)) - (PORT d[12] (4641:4641:4641) (4882:4882:4882)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (3709:3709:3709) (3843:3843:3843)) + (PORT d[1] (4318:4318:4318) (4447:4447:4447)) + (PORT d[2] (3267:3267:3267) (3395:3395:3395)) + (PORT d[3] (3158:3158:3158) (3390:3390:3390)) + (PORT d[4] (3183:3183:3183) (3450:3450:3450)) + (PORT d[5] (3060:3060:3060) (3230:3230:3230)) + (PORT d[6] (3068:3068:3068) (3241:3241:3241)) + (PORT d[7] (4376:4376:4376) (4586:4586:4586)) + (PORT d[8] (2982:2982:2982) (3153:3153:3153)) + (PORT d[9] (2769:2769:2769) (2980:2980:2980)) + (PORT d[10] (2730:2730:2730) (3000:3000:3000)) + (PORT d[11] (2383:2383:2383) (2510:2510:2510)) + (PORT d[12] (2039:2039:2039) (2260:2260:2260)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) ) ) (TIMINGCHECK @@ -40286,8 +33928,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2847:2847:2847) (2894:2894:2894)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (2236:2236:2236) (2216:2216:2216)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) ) ) (TIMINGCHECK @@ -40299,8 +33941,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3233:3233:3233) (3186:3186:3186)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (5003:5003:5003) (4909:4909:4909)) ) ) ) @@ -40309,7 +33951,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -40319,7 +33961,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -40329,7 +33971,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -40339,7 +33981,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -40349,7 +33991,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) + (PORT clk (1824:1824:1824) (1820:1820:1820)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40363,8 +34005,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1943:1943:1943) (1936:1936:1936)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT d[0] (1436:1436:1436) (1454:1454:1454)) + (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) (TIMINGCHECK @@ -40376,20 +34018,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4480:4480:4480) (4505:4505:4505)) - (PORT d[1] (4433:4433:4433) (4489:4489:4489)) - (PORT d[2] (4515:4515:4515) (4513:4513:4513)) - (PORT d[3] (4207:4207:4207) (4267:4267:4267)) - (PORT d[4] (4326:4326:4326) (4470:4470:4470)) - (PORT d[5] (4354:4354:4354) (4405:4405:4405)) - (PORT d[6] (4409:4409:4409) (4469:4469:4469)) - (PORT d[7] (4149:4149:4149) (4196:4196:4196)) - (PORT d[8] (4390:4390:4390) (4446:4446:4446)) - (PORT d[9] (4387:4387:4387) (4446:4446:4446)) - (PORT d[10] (4288:4288:4288) (4373:4373:4373)) - (PORT d[11] (4468:4468:4468) (4585:4585:4585)) - (PORT d[12] (4406:4406:4406) (4382:4382:4382)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT d[0] (4205:4205:4205) (4290:4290:4290)) + (PORT d[1] (4273:4273:4273) (4458:4458:4458)) + (PORT d[2] (4102:4102:4102) (4182:4182:4182)) + (PORT d[3] (4090:4090:4090) (4128:4128:4128)) + (PORT d[4] (4141:4141:4141) (4179:4179:4179)) + (PORT d[5] (4398:4398:4398) (4597:4597:4597)) + (PORT d[6] (4328:4328:4328) (4519:4519:4519)) + (PORT d[7] (4480:4480:4480) (4639:4639:4639)) + (PORT d[8] (4196:4196:4196) (4247:4247:4247)) + (PORT d[9] (4204:4204:4204) (4293:4293:4293)) + (PORT d[10] (4098:4098:4098) (4163:4163:4163)) + (PORT d[11] (4235:4235:4235) (4314:4314:4314)) + (PORT d[12] (4184:4184:4184) (4228:4228:4228)) + (PORT clk (1830:1830:1830) (1822:1822:1822)) ) ) (TIMINGCHECK @@ -40401,7 +34043,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) ) @@ -40410,7 +34052,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -40420,7 +34062,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) @@ -40430,7 +34072,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -40440,7 +34082,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -40450,7 +34092,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1812:1812:1812)) + (PORT clk (1826:1826:1826) (1822:1822:1822)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40464,20 +34106,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1665:1665:1665) (1779:1779:1779)) - (PORT d[1] (2703:2703:2703) (2833:2833:2833)) - (PORT d[2] (2113:2113:2113) (2246:2246:2246)) - (PORT d[3] (3328:3328:3328) (3453:3453:3453)) - (PORT d[4] (2296:2296:2296) (2448:2448:2448)) - (PORT d[5] (3758:3758:3758) (3880:3880:3880)) - (PORT d[6] (2543:2543:2543) (2630:2630:2630)) - (PORT d[7] (3441:3441:3441) (3488:3488:3488)) - (PORT d[8] (2926:2926:2926) (3023:3023:3023)) - (PORT d[9] (2768:2768:2768) (2881:2881:2881)) - (PORT d[10] (2335:2335:2335) (2395:2395:2395)) - (PORT d[11] (2478:2478:2478) (2654:2654:2654)) - (PORT d[12] (3520:3520:3520) (3735:3735:3735)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (2594:2594:2594) (2693:2693:2693)) + (PORT d[1] (2461:2461:2461) (2483:2483:2483)) + (PORT d[2] (2316:2316:2316) (2388:2388:2388)) + (PORT d[3] (902:902:902) (935:935:935)) + (PORT d[4] (2614:2614:2614) (2828:2828:2828)) + (PORT d[5] (2783:2783:2783) (2824:2824:2824)) + (PORT d[6] (4030:4030:4030) (4216:4216:4216)) + (PORT d[7] (1467:1467:1467) (1480:1480:1480)) + (PORT d[8] (1488:1488:1488) (1521:1521:1521)) + (PORT d[9] (1469:1469:1469) (1534:1534:1534)) + (PORT d[10] (658:658:658) (690:690:690)) + (PORT d[11] (2561:2561:2561) (2687:2687:2687)) + (PORT d[12] (1787:1787:1787) (1844:1844:1844)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -40489,8 +34131,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (PORT d[0] (2653:2653:2653) (2588:2588:2588)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (PORT d[0] (1095:1095:1095) (1112:1112:1112)) ) ) ) @@ -40499,7 +34141,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT clk (1848:1848:1848) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -40509,7 +34151,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1850:1850:1850)) + (PORT clk (1810:1810:1810) (1836:1836:1836)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40523,7 +34165,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1009:1009:1009) (1013:1013:1013)) + (PORT clk (995:995:995) (999:999:999)) ) ) ) @@ -40532,7 +34174,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1010:1010:1010) (1014:1014:1014)) + (PORT clk (996:996:996) (1000:1000:1000)) ) ) ) @@ -40541,7 +34183,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1010:1010:1010) (1014:1014:1014)) + (PORT clk (996:996:996) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -40551,21 +34193,21 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1010:1010:1010) (1014:1014:1014)) + (PORT clk (996:996:996) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (INSTANCE Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1288:1288:1288)) - (PORT datab (724:724:724) (782:782:782)) - (PORT datac (1333:1333:1333) (1353:1353:1353)) - (PORT datad (1400:1400:1400) (1484:1484:1484)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (948:948:948) (1037:1037:1037)) + (PORT datab (950:950:950) (1009:1009:1009)) + (PORT datac (1666:1666:1666) (1698:1698:1698)) + (PORT datad (1395:1395:1395) (1435:1435:1435)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -40574,48 +34216,277 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (701:701:701) (765:765:765)) - (PORT datab (1092:1092:1092) (1091:1091:1091)) - (PORT datac (1528:1528:1528) (1658:1658:1658)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (1922:1922:1922) (1986:1986:1986)) + (PORT datab (1228:1228:1228) (1267:1267:1267)) + (PORT datac (1758:1758:1758) (1828:1828:1828)) + (PORT datad (1410:1410:1410) (1449:1449:1449)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1524:1524:1524) (1563:1563:1563)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3814:3814:3814) (4007:4007:4007)) + (PORT d[1] (3759:3759:3759) (3869:3869:3869)) + (PORT d[2] (3397:3397:3397) (3501:3501:3501)) + (PORT d[3] (3498:3498:3498) (3752:3752:3752)) + (PORT d[4] (3472:3472:3472) (3768:3768:3768)) + (PORT d[5] (2962:2962:2962) (3067:3067:3067)) + (PORT d[6] (3092:3092:3092) (3270:3270:3270)) + (PORT d[7] (4484:4484:4484) (4711:4711:4711)) + (PORT d[8] (3304:3304:3304) (3520:3520:3520)) + (PORT d[9] (3614:3614:3614) (3836:3836:3836)) + (PORT d[10] (3140:3140:3140) (3423:3423:3423)) + (PORT d[11] (2935:2935:2935) (3078:3078:3078)) + (PORT d[12] (2171:2171:2171) (2332:2332:2332)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2395:2395:2395) (2407:2407:2407)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (5285:5285:5285) (5387:5387:5387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1374:1374:1374) (1378:1378:1378)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4263:4263:4263) (4317:4317:4317)) + (PORT d[1] (4248:4248:4248) (4422:4422:4422)) + (PORT d[2] (4119:4119:4119) (4218:4218:4218)) + (PORT d[3] (4113:4113:4113) (4136:4136:4136)) + (PORT d[4] (4133:4133:4133) (4161:4161:4161)) + (PORT d[5] (4212:4212:4212) (4409:4409:4409)) + (PORT d[6] (4225:4225:4225) (4521:4521:4521)) + (PORT d[7] (4241:4241:4241) (4397:4397:4397)) + (PORT d[8] (4118:4118:4118) (4165:4165:4165)) + (PORT d[9] (4188:4188:4188) (4257:4257:4257)) + (PORT d[10] (4147:4147:4147) (4197:4197:4197)) + (PORT d[11] (4247:4247:4247) (4292:4292:4292)) + (PORT d[12] (4201:4201:4201) (4265:4265:4265)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1610:1610:1610)) + (PORT datab (1166:1166:1166) (1239:1239:1239)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (1530:1530:1530) (1567:1567:1567)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~116) + (INSTANCE D\[7\]\~36) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (973:973:973) (999:999:999)) - (PORT datad (615:615:615) (641:641:641)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1184:1184:1184) (1244:1244:1244)) + (PORT datab (1695:1695:1695) (1769:1769:1769)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~117) + (INSTANCE D\[7\]\~37) (DELAY (ABSOLUTE - (PORT dataa (1229:1229:1229) (1241:1241:1241)) - (PORT datab (2477:2477:2477) (2583:2583:2583)) - (PORT datac (1187:1187:1187) (1273:1273:1273)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (669:669:669) (736:736:736)) + (PORT datab (2229:2229:2229) (2318:2318:2318)) + (PORT datac (1368:1368:1368) (1422:1422:1422)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (843:843:843) (875:875:875)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -40625,25 +34496,41 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (398:398:398)) - (PORT datab (431:431:431) (467:467:467)) - (PORT datac (1157:1157:1157) (1229:1229:1229)) - (PORT datad (1131:1131:1131) (1158:1158:1158)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (903:903:903) (909:909:909)) + (PORT datab (256:256:256) (315:315:315)) + (PORT datac (1484:1484:1484) (1531:1531:1531)) + (PORT datad (2098:2098:2098) (2140:2140:2140)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1209:1209:1209)) + (PORT datab (1593:1593:1593) (1775:1775:1775)) + (PORT datac (1473:1473:1473) (1520:1520:1520)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|data_pins_\|dout\[7\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT clk (1520:1520:1520) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -40654,16 +34541,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (INSTANCE z80_\|bus_control_\|db\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (420:420:420) (454:454:454)) - (PORT datac (594:594:594) (602:602:602)) - (PORT datad (240:240:240) (310:310:310)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (272:272:272) (328:328:328)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (625:625:625) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -40673,10 +34560,10 @@ (INSTANCE z80_\|ir_\|opcode\[7\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (675:675:675) (698:698:698)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1430:1430:1430) (1462:1462:1462)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (841:841:841) (847:847:847)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -40688,11 +34575,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT datac (1095:1095:1095) (1167:1167:1167)) - (PORT datad (1964:1964:1964) (2035:2035:2035)) + (PORT datab (983:983:983) (1061:1061:1061)) + (PORT datac (679:679:679) (742:742:742)) + (PORT datad (1705:1705:1705) (1803:1803:1803)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40700,47 +34589,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) (DELAY (ABSOLUTE - (PORT dataa (2561:2561:2561) (2630:2630:2630)) - (PORT datab (2099:2099:2099) (2235:2235:2235)) - (PORT datac (2435:2435:2435) (2634:2634:2634)) - (PORT datad (1838:1838:1838) (1932:1932:1932)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1582:1582:1582) (1716:1716:1716)) + (PORT datab (1699:1699:1699) (1758:1758:1758)) + (PORT datac (1609:1609:1609) (1656:1656:1656)) + (PORT datad (2362:2362:2362) (2450:2450:2450)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1616:1616:1616) (1664:1664:1664)) - (PORT datab (568:568:568) (584:584:584)) - (PORT datac (848:848:848) (863:863:863)) - (PORT datad (172:172:172) (198:198:198)) + (PORT dataa (1638:1638:1638) (1692:1692:1692)) + (PORT datab (2151:2151:2151) (2221:2221:2221)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (2201:2201:2201) (2266:2266:2266)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (221:221:221) (265:265:265)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (893:893:893) (956:956:956)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (699:699:699)) - (PORT datab (856:856:856) (930:930:930)) - (PORT datac (1457:1457:1457) (1472:1472:1472)) - (PORT datad (1160:1160:1160) (1214:1214:1214)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40748,49 +34637,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (2288:2288:2288) (2394:2394:2394)) - (PORT datab (2179:2179:2179) (2358:2358:2358)) - (PORT datac (1178:1178:1178) (1292:1292:1292)) - (PORT datad (819:819:819) (892:892:892)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (855:855:855)) - (PORT datab (770:770:770) (837:837:837)) - (PORT datac (1830:1830:1830) (1968:1968:1968)) - (PORT datad (1686:1686:1686) (1757:1757:1757)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1959:1959:1959) (2051:2051:2051)) + (PORT datab (2153:2153:2153) (2226:2226:2226)) + (PORT datac (1744:1744:1744) (1774:1774:1774)) + (PORT datad (2203:2203:2203) (2269:2269:2269)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40798,184 +34653,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (INSTANCE z80_\|execute_\|fIORead\~3) (DELAY (ABSOLUTE - (PORT dataa (930:930:930) (1012:1012:1012)) - (PORT datab (1179:1179:1179) (1247:1247:1247)) - (PORT datac (1905:1905:1905) (1971:1971:1971)) - (PORT datad (1431:1431:1431) (1464:1464:1464)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (929:929:929) (946:946:946)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (968:968:968) (972:972:972)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (674:674:674)) - (PORT datab (968:968:968) (1029:1029:1029)) - (PORT datad (359:359:359) (423:423:423)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (959:959:959)) - (PORT datab (989:989:989) (1031:1031:1031)) - (PORT datac (617:617:617) (643:643:643)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (674:674:674)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (1172:1172:1172) (1212:1212:1212)) - (PORT datad (839:839:839) (895:895:895)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1508:1508:1508) (1611:1611:1611)) - (PORT datab (1253:1253:1253) (1278:1278:1278)) - (PORT datac (1153:1153:1153) (1183:1183:1183)) - (PORT datad (1488:1488:1488) (1524:1524:1524)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1178:1178:1178) (1217:1217:1217)) + (PORT datad (180:180:180) (209:209:209)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datab (1453:1453:1453) (1487:1487:1487)) - (PORT datac (508:508:508) (517:517:517)) - (PORT datad (952:952:952) (989:989:989)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (617:617:617) (659:659:659)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (382:382:382) (410:410:410)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (525:525:525) (533:533:533)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1019:1019:1019)) - (PORT datab (931:931:931) (1012:1012:1012)) - (PORT datac (252:252:252) (337:337:337)) - (PORT datad (268:268:268) (347:347:347)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (738:738:738) (815:815:815)) - (PORT datad (1023:1023:1023) (1090:1090:1090)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (437:437:437)) - (PORT datab (337:337:337) (366:366:366)) - (PORT datac (734:734:734) (821:821:821)) - (PORT datad (581:581:581) (597:597:597)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40983,422 +34669,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (771:771:771) (850:850:850)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (418:418:418)) - (PORT datab (680:680:680) (747:747:747)) - (PORT datac (912:912:912) (975:975:975)) - (PORT datad (946:946:946) (1019:1019:1019)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (838:838:838)) - (PORT datab (771:771:771) (853:853:853)) - (PORT datac (697:697:697) (771:771:771)) - (PORT datad (966:966:966) (1032:1032:1032)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT datab (1063:1063:1063) (1128:1128:1128)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (684:684:684)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (710:710:710) (772:772:772)) - (PORT datad (520:520:520) (531:531:531)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (376:376:376)) - (PORT datab (775:775:775) (855:855:855)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (947:947:947) (978:978:978)) - (PORT datac (785:785:785) (819:819:819)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (573:573:573)) - (PORT datab (1005:1005:1005) (1093:1093:1093)) - (PORT datac (669:669:669) (725:725:725)) - (PORT datad (618:618:618) (686:686:686)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (573:573:573)) - (PORT datac (755:755:755) (829:829:829)) - (PORT datad (392:392:392) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1127:1127:1127)) - (PORT datac (901:901:901) (915:915:915)) - (PORT datad (729:729:729) (803:803:803)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (246:246:246)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datad (576:576:576) (586:586:586)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (620:620:620)) - (PORT datab (1063:1063:1063) (1128:1128:1128)) - (PORT datac (731:731:731) (807:807:807)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (559:559:559) (578:578:578)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (233:233:233) (282:282:282)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (931:931:931) (977:977:977)) - (PORT datad (617:617:617) (661:661:661)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (817:817:817)) - (PORT datab (1016:1016:1016) (1083:1083:1083)) - (PORT datac (962:962:962) (1040:1040:1040)) - (PORT datad (577:577:577) (602:602:602)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1396:1396:1396)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (706:706:706)) - (PORT datac (1000:1000:1000) (1060:1060:1060)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (735:735:735) (825:825:825)) - (PORT datab (970:970:970) (1056:1056:1056)) - (PORT datac (753:753:753) (841:841:841)) - (PORT datad (904:904:904) (978:978:978)) + (PORT dataa (909:909:909) (932:932:932)) + (PORT datab (690:690:690) (737:737:737)) + (PORT datac (1110:1110:1110) (1168:1168:1168)) + (PORT datad (597:597:597) (627:627:627)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~69) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (584:584:584)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (937:937:937) (1017:1017:1017)) - (PORT datad (192:192:192) (225:225:225)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (905:905:905)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (606:606:606) (617:617:617)) - (PORT datad (714:714:714) (785:785:785)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (425:425:425) (501:501:501)) - (PORT datac (745:745:745) (823:823:823)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1137:1137:1137)) - (PORT datab (593:593:593) (663:663:663)) - (PORT datac (1004:1004:1004) (1060:1060:1060)) - (PORT datad (609:609:609) (666:666:666)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (688:688:688)) - (PORT datab (750:750:750) (829:829:829)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (262:262:262) (341:341:341)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1812:1812:1812) (1848:1848:1848)) + (PORT datac (959:959:959) (1025:1025:1025)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41406,168 +34699,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (INSTANCE z80_\|execute_\|setM1\~59) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (245:245:245)) - (PORT datab (744:744:744) (816:816:816)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1478:1478:1478) (1551:1551:1551)) - (PORT datac (2279:2279:2279) (2486:2486:2486)) - (PORT datad (872:872:872) (942:942:942)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (814:814:814)) - (PORT datac (962:962:962) (1038:1038:1038)) - (PORT datad (578:578:578) (600:600:600)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (1295:1295:1295) (1399:1399:1399)) - (PORT datab (1016:1016:1016) (1082:1082:1082)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (436:436:436)) - (PORT datab (739:739:739) (806:806:806)) - (PORT datac (888:888:888) (956:956:956)) - (PORT datad (198:198:198) (235:235:235)) + (PORT dataa (1027:1027:1027) (1149:1149:1149)) + (PORT datab (1711:1711:1711) (1757:1757:1757)) + (PORT datac (1626:1626:1626) (1824:1824:1824)) + (PORT datad (882:882:882) (907:907:907)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1399:1399:1399)) - (PORT datab (957:957:957) (996:996:996)) - (PORT datad (592:592:592) (615:615:615)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (2799:2799:2799) (3004:3004:3004)) - (PORT datac (215:215:215) (290:290:290)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41575,26 +34715,252 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) + (INSTANCE z80_\|execute_\|setM1\~41) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (931:931:931)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (2354:2354:2354) (2577:2577:2577)) - (PORT datad (621:621:621) (631:631:631)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1106:1106:1106) (1105:1105:1105)) + (PORT datad (579:579:579) (602:602:602)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (560:560:560)) + (PORT datab (1478:1478:1478) (1574:1574:1574)) + (PORT datac (1218:1218:1218) (1309:1309:1309)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) (DELAY (ABSOLUTE - (PORT d[0] (1207:1207:1207) (1245:1245:1245)) + (PORT dataa (934:934:934) (997:997:997)) + (PORT datab (248:248:248) (297:297:297)) + (PORT datac (1543:1543:1543) (1571:1571:1571)) + (PORT datad (654:654:654) (671:671:671)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1332:1332:1332)) + (PORT datab (1717:1717:1717) (1765:1765:1765)) + (PORT datac (363:363:363) (390:390:390)) + (PORT datad (1218:1218:1218) (1307:1307:1307)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (887:887:887)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1125:1125:1125) (1181:1181:1181)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (435:435:435)) + (PORT datab (1162:1162:1162) (1218:1218:1218)) + (PORT datac (1144:1144:1144) (1154:1154:1154)) + (PORT datad (656:656:656) (713:713:713)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (983:983:983) (1043:1043:1043)) + (PORT datac (1407:1407:1407) (1437:1437:1437)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1324:1324:1324) (1365:1365:1365)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1539:1539:1539)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (2003:2003:2003) (2031:2031:2031)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (985:985:985) (1073:1073:1073)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1563:1563:1563) (1545:1545:1545)) + (PORT ena (1458:1458:1458) (1463:1463:1463)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1091:1091:1091) (1160:1160:1160)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (1090:1090:1090) (1162:1162:1162)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (619:619:619)) + (PORT datab (1161:1161:1161) (1228:1228:1228)) + (PORT datac (1130:1130:1130) (1197:1197:1197)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1328:1328:1328)) + (PORT datab (1163:1163:1163) (1212:1212:1212)) + (PORT datac (1131:1131:1131) (1177:1177:1177)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1209:1209:1209) (1270:1270:1270)) (PORT clk (1843:1843:1843) (1871:1871:1871)) ) ) @@ -41604,22 +34970,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2687:2687:2687) (2899:2899:2899)) - (PORT d[1] (2871:2871:2871) (2966:2966:2966)) - (PORT d[2] (1020:1020:1020) (1070:1070:1070)) - (PORT d[3] (974:974:974) (1029:1029:1029)) - (PORT d[4] (2049:2049:2049) (2146:2146:2146)) - (PORT d[5] (972:972:972) (1026:1026:1026)) - (PORT d[6] (1699:1699:1699) (1745:1745:1745)) - (PORT d[7] (2654:2654:2654) (2813:2813:2813)) - (PORT d[8] (2491:2491:2491) (2668:2668:2668)) - (PORT d[9] (756:756:756) (799:799:799)) - (PORT d[10] (747:747:747) (789:789:789)) - (PORT d[11] (2820:2820:2820) (3002:3002:3002)) - (PORT d[12] (430:430:430) (463:463:463)) + (PORT d[0] (995:995:995) (1040:1040:1040)) + (PORT d[1] (1269:1269:1269) (1326:1326:1326)) + (PORT d[2] (1006:1006:1006) (1044:1044:1044)) + (PORT d[3] (2781:2781:2781) (2932:2932:2932)) + (PORT d[4] (1252:1252:1252) (1314:1314:1314)) + (PORT d[5] (2152:2152:2152) (2248:2248:2248)) + (PORT d[6] (922:922:922) (959:959:959)) + (PORT d[7] (924:924:924) (977:977:977)) + (PORT d[8] (1134:1134:1134) (1170:1170:1170)) + (PORT d[9] (1495:1495:1495) (1553:1553:1553)) + (PORT d[10] (1955:1955:1955) (2133:2133:2133)) + (PORT d[11] (2280:2280:2280) (2387:2387:2387)) + (PORT d[12] (1360:1360:1360) (1475:1475:1475)) (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) @@ -41629,10 +34995,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1529:1529:1529) (1497:1497:1497)) + (PORT d[0] (1737:1737:1737) (1706:1706:1706)) (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) @@ -41642,17 +35008,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (1469:1469:1469) (1447:1447:1447)) + (PORT d[0] (2000:2000:2000) (2004:2004:2004)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41662,7 +35028,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41672,7 +35038,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41682,7 +35048,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41692,7 +35058,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1803:1803:1803) (1830:1830:1830)) @@ -41706,7 +35072,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (988:988:988) (993:993:993)) @@ -41715,7 +35081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) (DELAY (ABSOLUTE (PORT clk (989:989:989) (994:994:994)) @@ -41724,7 +35090,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (989:989:989) (994:994:994)) @@ -41734,7 +35100,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (989:989:989) (994:994:994)) @@ -41742,12 +35108,6221 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1291:1291:1291) (1358:1358:1358)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (671:671:671) (709:709:709)) + (PORT d[1] (1279:1279:1279) (1316:1316:1316)) + (PORT d[2] (1326:1326:1326) (1397:1397:1397)) + (PORT d[3] (2492:2492:2492) (2661:2661:2661)) + (PORT d[4] (1257:1257:1257) (1322:1322:1322)) + (PORT d[5] (2125:2125:2125) (2217:2217:2217)) + (PORT d[6] (1884:1884:1884) (2017:2017:2017)) + (PORT d[7] (1212:1212:1212) (1263:1263:1263)) + (PORT d[8] (1393:1393:1393) (1433:1433:1433)) + (PORT d[9] (1507:1507:1507) (1580:1580:1580)) + (PORT d[10] (1989:1989:1989) (2151:2151:2151)) + (PORT d[11] (984:984:984) (1056:1056:1056)) + (PORT d[12] (1373:1373:1373) (1504:1504:1504)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1765:1765:1765) (1766:1766:1766)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (2149:2149:2149) (2144:2144:2144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1208:1208:1208) (1250:1250:1250)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (982:982:982) (1038:1038:1038)) + (PORT d[1] (1268:1268:1268) (1296:1296:1296)) + (PORT d[2] (986:986:986) (1035:1035:1035)) + (PORT d[3] (2483:2483:2483) (2625:2625:2625)) + (PORT d[4] (952:952:952) (997:997:997)) + (PORT d[5] (941:941:941) (980:980:980)) + (PORT d[6] (1852:1852:1852) (1978:1978:1978)) + (PORT d[7] (1204:1204:1204) (1255:1255:1255)) + (PORT d[8] (1401:1401:1401) (1435:1435:1435)) + (PORT d[9] (1741:1741:1741) (1825:1825:1825)) + (PORT d[10] (1865:1865:1865) (2003:2003:2003)) + (PORT d[11] (1232:1232:1232) (1318:1318:1318)) + (PORT d[12] (1320:1320:1320) (1419:1419:1419)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1769:1769:1769) (1719:1719:1719)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2279:2279:2279) (2264:2264:2264)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1261:1261:1261) (1331:1331:1331)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2898:2898:2898) (3019:3019:3019)) + (PORT d[1] (2821:2821:2821) (2858:2858:2858)) + (PORT d[2] (2624:2624:2624) (2719:2719:2719)) + (PORT d[3] (1970:1970:1970) (2047:2047:2047)) + (PORT d[4] (3473:3473:3473) (3759:3759:3759)) + (PORT d[5] (3082:3082:3082) (3145:3145:3145)) + (PORT d[6] (2902:2902:2902) (3092:3092:3092)) + (PORT d[7] (959:959:959) (1001:1001:1001)) + (PORT d[8] (1452:1452:1452) (1486:1486:1486)) + (PORT d[9] (4507:4507:4507) (4803:4803:4803)) + (PORT d[10] (4180:4180:4180) (4510:4510:4510)) + (PORT d[11] (3619:3619:3619) (3841:3841:3841)) + (PORT d[12] (1413:1413:1413) (1419:1419:1419)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1999:1999:1999) (1945:1945:1945)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (1398:1398:1398) (1357:1357:1357)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1280:1280:1280)) + (PORT datab (1494:1494:1494) (1568:1568:1568)) + (PORT datac (1577:1577:1577) (1632:1632:1632)) + (PORT datad (1335:1335:1335) (1350:1350:1350)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1473:1473:1473)) + (PORT datab (1277:1277:1277) (1374:1374:1374)) + (PORT datac (1953:1953:1953) (2048:2048:2048)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1296:1296:1296) (1366:1366:1366)) + (PORT clk (1862:1862:1862) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2673:2673:2673) (2781:2781:2781)) + (PORT d[1] (2244:2244:2244) (2356:2356:2356)) + (PORT d[2] (2750:2750:2750) (2894:2894:2894)) + (PORT d[3] (2861:2861:2861) (2992:2992:2992)) + (PORT d[4] (3687:3687:3687) (4010:4010:4010)) + (PORT d[5] (2963:2963:2963) (3074:3074:3074)) + (PORT d[6] (3293:3293:3293) (3400:3400:3400)) + (PORT d[7] (2712:2712:2712) (2857:2857:2857)) + (PORT d[8] (2331:2331:2331) (2442:2442:2442)) + (PORT d[9] (2661:2661:2661) (2840:2840:2840)) + (PORT d[10] (2024:2024:2024) (2216:2216:2216)) + (PORT d[11] (2375:2375:2375) (2507:2507:2507)) + (PORT d[12] (2201:2201:2201) (2391:2391:2391)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2044:2044:2044) (2083:2083:2083)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT d[0] (3741:3741:3741) (3791:3791:3791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1226:1226:1226) (1240:1240:1240)) + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4206:4206:4206) (4343:4343:4343)) + (PORT d[1] (4289:4289:4289) (4496:4496:4496)) + (PORT d[2] (4252:4252:4252) (4350:4350:4350)) + (PORT d[3] (4244:4244:4244) (4337:4337:4337)) + (PORT d[4] (4164:4164:4164) (4250:4250:4250)) + (PORT d[5] (4168:4168:4168) (4329:4329:4329)) + (PORT d[6] (4273:4273:4273) (4568:4568:4568)) + (PORT d[7] (4280:4280:4280) (4385:4385:4385)) + (PORT d[8] (4234:4234:4234) (4215:4215:4215)) + (PORT d[9] (4134:4134:4134) (4185:4185:4185)) + (PORT d[10] (4052:4052:4052) (4112:4112:4112)) + (PORT d[11] (4145:4145:4145) (4217:4217:4217)) + (PORT d[12] (4307:4307:4307) (4292:4292:4292)) + (PORT clk (1823:1823:1823) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1939:1939:1939) (2003:2003:2003)) + (PORT d[1] (1588:1588:1588) (1605:1605:1605)) + (PORT d[2] (1420:1420:1420) (1454:1454:1454)) + (PORT d[3] (3510:3510:3510) (3709:3709:3709)) + (PORT d[4] (2090:2090:2090) (2225:2225:2225)) + (PORT d[5] (1955:1955:1955) (1979:1979:1979)) + (PORT d[6] (3427:3427:3427) (3618:3618:3618)) + (PORT d[7] (1722:1722:1722) (1745:1745:1745)) + (PORT d[8] (1287:1287:1287) (1309:1309:1309)) + (PORT d[9] (1315:1315:1315) (1359:1359:1359)) + (PORT d[10] (1227:1227:1227) (1265:1265:1265)) + (PORT d[11] (1728:1728:1728) (1816:1816:1816)) + (PORT d[12] (1556:1556:1556) (1630:1630:1630)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1383:1383:1383) (1400:1400:1400)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1551:1551:1551) (1614:1614:1614)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2400:2400:2400) (2498:2498:2498)) + (PORT d[1] (2515:2515:2515) (2622:2622:2622)) + (PORT d[2] (2765:2765:2765) (2930:2930:2930)) + (PORT d[3] (2539:2539:2539) (2707:2707:2707)) + (PORT d[4] (3975:3975:3975) (4317:4317:4317)) + (PORT d[5] (3017:3017:3017) (3162:3162:3162)) + (PORT d[6] (2528:2528:2528) (2645:2645:2645)) + (PORT d[7] (2410:2410:2410) (2549:2549:2549)) + (PORT d[8] (1835:1835:1835) (1906:1906:1906)) + (PORT d[9] (3321:3321:3321) (3533:3533:3533)) + (PORT d[10] (1998:1998:1998) (2203:2203:2203)) + (PORT d[11] (2703:2703:2703) (2835:2835:2835)) + (PORT d[12] (1934:1934:1934) (2122:2122:2122)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2022:2022:2022) (2001:2001:2001)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3471:3471:3471) (3424:3424:3424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1158:1158:1158)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4097:4097:4097) (4228:4228:4228)) + (PORT d[1] (4171:4171:4171) (4282:4282:4282)) + (PORT d[2] (4245:4245:4245) (4381:4381:4381)) + (PORT d[3] (4224:4224:4224) (4317:4317:4317)) + (PORT d[4] (4301:4301:4301) (4392:4392:4392)) + (PORT d[5] (4273:4273:4273) (4585:4585:4585)) + (PORT d[6] (4237:4237:4237) (4529:4529:4529)) + (PORT d[7] (4249:4249:4249) (4365:4365:4365)) + (PORT d[8] (4215:4215:4215) (4200:4200:4200)) + (PORT d[9] (4238:4238:4238) (4255:4255:4255)) + (PORT d[10] (4252:4252:4252) (4359:4359:4359)) + (PORT d[11] (4197:4197:4197) (4279:4279:4279)) + (PORT d[12] (4193:4193:4193) (4244:4244:4244)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2296:2296:2296) (2377:2377:2377)) + (PORT d[1] (2238:2238:2238) (2253:2253:2253)) + (PORT d[2] (2005:2005:2005) (2058:2058:2058)) + (PORT d[3] (1143:1143:1143) (1188:1188:1188)) + (PORT d[4] (2571:2571:2571) (2706:2706:2706)) + (PORT d[5] (2455:2455:2455) (2474:2474:2474)) + (PORT d[6] (3178:3178:3178) (3374:3374:3374)) + (PORT d[7] (1440:1440:1440) (1447:1447:1447)) + (PORT d[8] (1004:1004:1004) (1027:1027:1027)) + (PORT d[9] (974:974:974) (1023:1023:1023)) + (PORT d[10] (1781:1781:1781) (1851:1851:1851)) + (PORT d[11] (2257:2257:2257) (2360:2360:2360)) + (PORT d[12] (1252:1252:1252) (1336:1336:1336)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (1706:1706:1706) (1691:1691:1691)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1035:1035:1035)) + (PORT datab (950:950:950) (1006:1006:1006)) + (PORT datac (1437:1437:1437) (1476:1476:1476)) + (PORT datad (1573:1573:1573) (1642:1642:1642)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1533:1533:1533)) + (PORT datab (1166:1166:1166) (1241:1241:1241)) + (PORT datac (1663:1663:1663) (1805:1805:1805)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (842:842:842) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (374:374:374)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datad (262:262:262) (344:344:344)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3135:3135:3135) (3397:3397:3397)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (224:224:224) (297:297:297)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (300:300:300)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (297:297:297)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (341:341:341)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (224:224:224) (303:303:303)) + (PORT datad (225:225:225) (297:297:297)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (259:259:259)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datac (220:220:220) (297:297:297)) + (PORT datad (224:224:224) (295:295:295)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (375:375:375)) + (PORT datab (411:411:411) (475:475:475)) + (PORT datad (247:247:247) (328:328:328)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (374:374:374)) + (PORT datab (278:278:278) (374:374:374)) + (PORT datad (247:247:247) (329:329:329)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (386:386:386)) + (PORT datab (282:282:282) (377:377:377)) + (PORT datad (248:248:248) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (387:387:387)) + (PORT datab (280:280:280) (375:375:375)) + (PORT datad (246:246:246) (326:326:326)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (368:368:368)) + (PORT datab (273:273:273) (368:368:368)) + (PORT datac (3268:3268:3268) (3567:3567:3567)) + (PORT datad (260:260:260) (339:339:339)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (366:366:366)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (1111:1111:1111) (1164:1164:1164)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (3424:3424:3424) (3746:3746:3746)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (359:359:359) (419:419:419)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (610:610:610) (708:708:708)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1573:1573:1573) (1667:1667:1667)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (PORT ena (1223:1223:1223) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1433:1433:1433) (1472:1472:1472)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (974:974:974) (967:967:967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1051:1051:1051) (1114:1114:1114)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1066:1066:1066) (1148:1148:1148)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (PORT ena (1534:1534:1534) (1521:1521:1521)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (771:771:771)) + (PORT datac (701:701:701) (780:780:780)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1824:1824:1824) (1867:1867:1867)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (974:974:974) (967:967:967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (421:421:421) (489:489:489)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (974:974:974) (967:967:967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (820:820:820)) + (PORT datab (952:952:952) (1024:1024:1024)) + (PORT datac (700:700:700) (769:769:769)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (855:855:855)) + (PORT datab (1172:1172:1172) (1238:1238:1238)) + (PORT datac (254:254:254) (339:339:339)) + (PORT datad (690:690:690) (761:761:761)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (404:404:404)) + (PORT datab (433:433:433) (514:514:514)) + (PORT datad (1428:1428:1428) (1499:1499:1499)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3305:3305:3305) (3605:3605:3605)) + (PORT datab (210:210:210) (252:252:252)) + (PORT datac (1108:1108:1108) (1160:1160:1160)) + (PORT datad (600:600:600) (614:614:614)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (374:374:374)) + (PORT datab (729:729:729) (799:799:799)) + (PORT datac (269:269:269) (368:368:368)) + (PORT datad (1429:1429:1429) (1502:1502:1502)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (848:848:848)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1143:1143:1143) (1201:1201:1201)) + (PORT datad (410:410:410) (477:477:477)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (814:814:814)) + (PORT datab (238:238:238) (282:282:282)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1310:1310:1310) (1353:1353:1353)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (688:688:688) (764:764:764)) + (PORT datac (271:271:271) (373:373:373)) + (PORT datad (253:253:253) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (860:860:860)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (617:617:617) (663:663:663)) + (PORT datad (690:690:690) (766:766:766)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (780:780:780)) + (PORT datab (702:702:702) (774:774:774)) + (PORT datad (624:624:624) (660:660:660)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (412:412:412)) + (PORT datab (362:362:362) (393:393:393)) + (PORT datad (449:449:449) (525:525:525)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datab (690:690:690) (764:764:764)) + (PORT datac (269:269:269) (371:371:371)) + (PORT datad (252:252:252) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (713:713:713)) + (PORT datab (694:694:694) (775:775:775)) + (PORT datac (348:348:348) (371:371:371)) + (PORT datad (361:361:361) (377:377:377)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (487:487:487) (567:567:567)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (331:331:331)) + (PORT datab (1703:1703:1703) (1789:1789:1789)) + (PORT datac (2220:2220:2220) (2417:2417:2417)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (768:768:768)) + (PORT datac (706:706:706) (782:782:782)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (396:396:396)) + (PORT datab (365:365:365) (396:396:396)) + (PORT datad (448:448:448) (529:529:529)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1014:1014:1014)) + (PORT datab (1025:1025:1025) (1100:1100:1100)) + (PORT datac (636:636:636) (674:674:674)) + (PORT datad (924:924:924) (982:982:982)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1077:1077:1077)) + (PORT datab (1285:1285:1285) (1358:1358:1358)) + (PORT datad (679:679:679) (757:757:757)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (727:727:727)) + (PORT datab (209:209:209) (253:253:253)) + (PORT datad (607:607:607) (629:629:629)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (460:460:460)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datac (3820:3820:3820) (4056:4056:4056)) + (PORT datad (3190:3190:3190) (3353:3353:3353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT datac (692:692:692) (763:763:763)) + (PORT datad (405:405:405) (473:473:473)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1050:1050:1050)) + (PORT datab (1000:1000:1000) (1067:1067:1067)) + (PORT datac (941:941:941) (1012:1012:1012)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1054:1054:1054)) + (PORT datac (966:966:966) (1027:1027:1027)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (798:798:798)) + (PORT datac (941:941:941) (1012:1012:1012)) + (PORT datad (408:408:408) (471:471:471)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (744:744:744) (827:827:827)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (413:413:413)) + (PORT datab (688:688:688) (760:760:760)) + (PORT datac (208:208:208) (248:248:248)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT datab (748:748:748) (828:828:828)) + (PORT datac (850:850:850) (874:874:874)) + (PORT datad (944:944:944) (1031:1031:1031)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1012:1012:1012) (1076:1076:1076)) + (PORT datab (1283:1283:1283) (1355:1355:1355)) + (PORT datac (1018:1018:1018) (1116:1116:1116)) + (PORT datad (1034:1034:1034) (1136:1136:1136)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (389:389:389)) + (PORT datab (751:751:751) (815:815:815)) + (PORT datad (922:922:922) (962:962:962)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (742:742:742) (828:828:828)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT datab (759:759:759) (860:860:860)) + (PORT datac (665:665:665) (731:731:731)) + (PORT datad (1437:1437:1437) (1501:1501:1501)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (752:752:752) (815:815:815)) + (PORT datac (850:850:850) (870:870:870)) + (PORT datad (722:722:722) (789:789:789)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (385:385:385)) + (PORT datab (639:639:639) (659:659:659)) + (PORT datad (607:607:607) (620:620:620)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (364:364:364)) + (PORT datab (884:884:884) (949:949:949)) + (PORT datac (283:283:283) (376:376:376)) + (PORT datad (708:708:708) (783:783:783)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1106:1106:1106)) + (PORT datab (736:736:736) (805:805:805)) + (PORT datac (1090:1090:1090) (1130:1130:1130)) + (PORT datad (720:720:720) (811:811:811)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (853:853:853)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (927:927:927) (992:992:992)) + (PORT datac (666:666:666) (736:736:736)) + (PORT datad (728:728:728) (829:829:829)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (668:668:668)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datac (1502:1502:1502) (1547:1547:1547)) + (PORT datad (2003:2003:2003) (2105:2105:2105)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (1276:1276:1276) (1351:1351:1351)) + (PORT datad (676:676:676) (754:754:754)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (744:744:744)) + (PORT datab (395:395:395) (419:419:419)) + (PORT datac (608:608:608) (618:618:618)) + (PORT datad (963:963:963) (1021:1021:1021)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1009:1009:1009) (1076:1076:1076)) + (PORT datad (872:872:872) (888:888:888)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (862:862:862)) + (PORT datab (734:734:734) (802:802:802)) + (PORT datac (244:244:244) (326:326:326)) + (PORT datad (734:734:734) (809:809:809)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (380:380:380)) + (PORT datab (880:880:880) (941:941:941)) + (PORT datac (282:282:282) (372:372:372)) + (PORT datad (712:712:712) (787:787:787)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (418:418:418)) + (PORT datab (694:694:694) (767:767:767)) + (PORT datac (209:209:209) (247:247:247)) + (PORT datad (1432:1432:1432) (1505:1505:1505)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1105:1105:1105)) + (PORT datab (602:602:602) (613:613:613)) + (PORT datad (595:595:595) (611:611:611)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (487:487:487)) + (PORT datab (2116:2116:2116) (2266:2266:2266)) + (PORT datac (2005:2005:2005) (2080:2080:2080)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (604:604:604) (643:643:643)) + (PORT datad (609:609:609) (622:622:622)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1669:1669:1669) (1781:1781:1781)) + (PORT datab (940:940:940) (1028:1028:1028)) + (PORT datac (366:366:366) (397:397:397)) + (PORT datad (1092:1092:1092) (1158:1158:1158)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1640:1640:1640)) + (PORT datab (940:940:940) (1029:1029:1029)) + (PORT datac (363:363:363) (397:397:397)) + (PORT datad (1089:1089:1089) (1156:1156:1156)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1514:1514:1514)) + (PORT datab (1678:1678:1678) (1699:1699:1699)) + (PORT datac (1417:1417:1417) (1479:1479:1479)) + (PORT datad (1523:1523:1523) (1648:1648:1648)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (999:999:999) (1025:1025:1025)) + (PORT datac (324:324:324) (353:353:353)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (938:938:938)) + (PORT datab (1896:1896:1896) (1931:1931:1931)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (668:668:668) (746:746:746)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1445:1445:1445)) + (PORT datab (343:343:343) (378:378:378)) + (PORT datac (1483:1483:1483) (1532:1532:1532)) + (PORT datad (228:228:228) (276:276:276)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1476:1476:1476)) + (PORT datac (234:234:234) (287:287:287)) + (PORT datad (1064:1064:1064) (1107:1107:1107)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (970:970:970)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (382:382:382) (427:427:427)) + (PORT datad (246:246:246) (293:293:293)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1537:1537:1537)) + (PORT ena (1830:1830:1830) (1880:1880:1880)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1372:1372:1372)) + (PORT datab (1697:1697:1697) (1873:1873:1873)) + (PORT datac (1238:1238:1238) (1350:1350:1350)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1155:1155:1155)) + (PORT datab (1403:1403:1403) (1476:1476:1476)) + (PORT datac (1637:1637:1637) (1830:1830:1830)) + (PORT datad (1823:1823:1823) (1893:1893:1893)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (868:868:868)) + (PORT datab (861:861:861) (885:885:885)) + (PORT datac (1109:1109:1109) (1183:1183:1183)) + (PORT datad (610:610:610) (623:623:623)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1212:1212:1212)) + (PORT datab (361:361:361) (396:396:396)) + (PORT datac (606:606:606) (668:668:668)) + (PORT datad (1160:1160:1160) (1197:1197:1197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1989:1989:1989) (1994:1994:1994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (982:982:982)) + (PORT datad (1872:1872:1872) (2002:2002:2002)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (862:862:862)) + (PORT datab (268:268:268) (330:330:330)) + (PORT datac (708:708:708) (774:774:774)) + (PORT datad (248:248:248) (299:299:299)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1413:1413:1413)) + (PORT datab (635:635:635) (655:655:655)) + (PORT datac (1122:1122:1122) (1203:1203:1203)) + (PORT datad (1256:1256:1256) (1306:1306:1306)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1565:1565:1565) (1697:1697:1697)) + (PORT datac (888:888:888) (938:938:938)) + (PORT datad (2016:2016:2016) (2101:2101:2101)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT datab (702:702:702) (818:818:818)) + (PORT datad (715:715:715) (812:812:812)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (816:816:816)) + (PORT datab (270:270:270) (333:333:333)) + (PORT datac (808:808:808) (848:848:848)) + (PORT datad (257:257:257) (304:304:304)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1045:1045:1045)) + (PORT datab (636:636:636) (704:704:704)) + (PORT datad (1497:1497:1497) (1590:1590:1590)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (713:713:713)) + (PORT datab (576:576:576) (605:605:605)) + (PORT datac (883:883:883) (921:921:921)) + (PORT datad (805:805:805) (811:811:811)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (1550:1550:1550) (1651:1651:1651)) + (PORT datac (680:680:680) (734:734:734)) + (PORT datad (1158:1158:1158) (1170:1170:1170)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1200:1200:1200)) + (PORT datab (894:894:894) (916:916:916)) + (PORT datac (873:873:873) (909:909:909)) + (PORT datad (1138:1138:1138) (1154:1154:1154)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (898:898:898)) + (PORT datab (338:338:338) (369:369:369)) + (PORT datac (675:675:675) (703:703:703)) + (PORT datad (342:342:342) (362:362:362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (576:576:576) (587:587:587)) + (PORT datad (218:218:218) (252:252:252)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (320:320:320)) + (PORT datab (907:907:907) (965:965:965)) + (PORT datac (1409:1409:1409) (1433:1433:1433)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (992:992:992) (1036:1036:1036)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1011:1011:1011) (1077:1077:1077)) + (PORT d[1] (1051:1051:1051) (1117:1117:1117)) + (PORT d[2] (1284:1284:1284) (1340:1340:1340)) + (PORT d[3] (2196:2196:2196) (2345:2345:2345)) + (PORT d[4] (998:998:998) (1037:1037:1037)) + (PORT d[5] (1837:1837:1837) (1908:1908:1908)) + (PORT d[6] (1589:1589:1589) (1703:1703:1703)) + (PORT d[7] (1218:1218:1218) (1286:1286:1286)) + (PORT d[8] (1393:1393:1393) (1446:1446:1446)) + (PORT d[9] (1437:1437:1437) (1482:1482:1482)) + (PORT d[10] (1666:1666:1666) (1825:1825:1825)) + (PORT d[11] (754:754:754) (810:810:810)) + (PORT d[12] (1333:1333:1333) (1458:1458:1458)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1502:1502:1502) (1486:1486:1486)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1873:1873:1873) (1846:1846:1846)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (698:698:698) (718:718:718)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1287:1287:1287) (1368:1368:1368)) + (PORT d[1] (2235:2235:2235) (2359:2359:2359)) + (PORT d[2] (3681:3681:3681) (3911:3911:3911)) + (PORT d[3] (1915:1915:1915) (2049:2049:2049)) + (PORT d[4] (1279:1279:1279) (1357:1357:1357)) + (PORT d[5] (1826:1826:1826) (1906:1906:1906)) + (PORT d[6] (1307:1307:1307) (1388:1388:1388)) + (PORT d[7] (1539:1539:1539) (1600:1600:1600)) + (PORT d[8] (3549:3549:3549) (3752:3752:3752)) + (PORT d[9] (2040:2040:2040) (2159:2159:2159)) + (PORT d[10] (1814:1814:1814) (1946:1946:1946)) + (PORT d[11] (998:998:998) (1058:1058:1058)) + (PORT d[12] (1634:1634:1634) (1765:1765:1765)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1480:1480:1480) (1455:1455:1455)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1778:1778:1778) (1761:1761:1761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (2496:2496:2496) (2597:2597:2597)) + (PORT datac (662:662:662) (738:738:738)) + (PORT datad (1510:1510:1510) (1650:1650:1650)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1524:1524:1524)) + (PORT datab (1341:1341:1341) (1379:1379:1379)) + (PORT datac (639:639:639) (660:660:660)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (963:963:963)) + (PORT datab (1255:1255:1255) (1328:1328:1328)) + (PORT datac (939:939:939) (976:976:976)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1022:1022:1022) (1040:1040:1040)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1284:1284:1284) (1363:1363:1363)) + (PORT d[1] (2243:2243:2243) (2382:2382:2382)) + (PORT d[2] (1270:1270:1270) (1317:1317:1317)) + (PORT d[3] (2185:2185:2185) (2328:2328:2328)) + (PORT d[4] (1266:1266:1266) (1337:1337:1337)) + (PORT d[5] (1232:1232:1232) (1272:1272:1272)) + (PORT d[6] (1531:1531:1531) (1631:1631:1631)) + (PORT d[7] (1501:1501:1501) (1585:1585:1585)) + (PORT d[8] (3552:3552:3552) (3755:3755:3755)) + (PORT d[9] (2042:2042:2042) (2163:2163:2163)) + (PORT d[10] (1613:1613:1613) (1745:1745:1745)) + (PORT d[11] (972:972:972) (1026:1026:1026)) + (PORT d[12] (1338:1338:1338) (1468:1468:1468)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1436:1436:1436) (1380:1380:1380)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2014:2014:2014) (1988:1988:1988)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (987:987:987) (1008:1008:1008)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1297:1297:1297) (1364:1364:1364)) + (PORT d[1] (2268:2268:2268) (2410:2410:2410)) + (PORT d[2] (1289:1289:1289) (1339:1339:1339)) + (PORT d[3] (2463:2463:2463) (2609:2609:2609)) + (PORT d[4] (1254:1254:1254) (1311:1311:1311)) + (PORT d[5] (1863:1863:1863) (1939:1939:1939)) + (PORT d[6] (1561:1561:1561) (1671:1671:1671)) + (PORT d[7] (1191:1191:1191) (1256:1256:1256)) + (PORT d[8] (3553:3553:3553) (3756:3756:3756)) + (PORT d[9] (1457:1457:1457) (1522:1522:1522)) + (PORT d[10] (1653:1653:1653) (1795:1795:1795)) + (PORT d[11] (986:986:986) (1028:1028:1028)) + (PORT d[12] (1337:1337:1337) (1467:1467:1467)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1200:1200:1200) (1178:1178:1178)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2034:2034:2034) (2014:2014:2014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (960:960:960)) + (PORT datab (948:948:948) (965:965:965)) + (PORT datad (1456:1456:1456) (1522:1522:1522)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1736:1736:1736)) + (PORT datab (1984:1984:1984) (2027:2027:2027)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (319:319:319) (336:336:336)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2685:2685:2685) (2802:2802:2802)) + (PORT d[1] (2447:2447:2447) (2530:2530:2530)) + (PORT d[2] (2475:2475:2475) (2617:2617:2617)) + (PORT d[3] (2822:2822:2822) (2958:2958:2958)) + (PORT d[4] (3706:3706:3706) (4011:4011:4011)) + (PORT d[5] (2973:2973:2973) (3107:3107:3107)) + (PORT d[6] (2830:2830:2830) (2945:2945:2945)) + (PORT d[7] (2670:2670:2670) (2854:2854:2854)) + (PORT d[8] (2326:2326:2326) (2433:2433:2433)) + (PORT d[9] (2642:2642:2642) (2830:2830:2830)) + (PORT d[10] (2008:2008:2008) (2190:2190:2190)) + (PORT d[11] (2324:2324:2324) (2409:2409:2409)) + (PORT d[12] (1926:1926:1926) (2093:2093:2093)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (2798:2798:2798) (2863:2863:2863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1504:1504:1504) (1587:1587:1587)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2427:2427:2427) (2536:2536:2536)) + (PORT d[1] (2493:2493:2493) (2605:2605:2605)) + (PORT d[2] (3062:3062:3062) (3228:3228:3228)) + (PORT d[3] (2803:2803:2803) (3000:3000:3000)) + (PORT d[4] (3975:3975:3975) (4317:4317:4317)) + (PORT d[5] (2368:2368:2368) (2477:2477:2477)) + (PORT d[6] (2521:2521:2521) (2626:2626:2626)) + (PORT d[7] (2372:2372:2372) (2534:2534:2534)) + (PORT d[8] (2637:2637:2637) (2773:2773:2773)) + (PORT d[9] (3329:3329:3329) (3532:3532:3532)) + (PORT d[10] (2003:2003:2003) (2185:2185:2185)) + (PORT d[11] (2716:2716:2716) (2865:2865:2865)) + (PORT d[12] (1884:1884:1884) (2069:2069:2069)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1756:1756:1756) (1774:1774:1774)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (3419:3419:3419) (3446:3446:3446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1805:1805:1805)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1474:1474:1474) (1506:1506:1506)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4111:4111:4111) (4231:4231:4231)) + (PORT d[1] (4204:4204:4204) (4318:4318:4318)) + (PORT d[2] (4133:4133:4133) (4227:4227:4227)) + (PORT d[3] (4215:4215:4215) (4294:4294:4294)) + (PORT d[4] (4312:4312:4312) (4428:4428:4428)) + (PORT d[5] (4283:4283:4283) (4614:4614:4614)) + (PORT d[6] (4442:4442:4442) (4583:4583:4583)) + (PORT d[7] (4306:4306:4306) (4402:4402:4402)) + (PORT d[8] (4117:4117:4117) (4168:4168:4168)) + (PORT d[9] (4079:4079:4079) (4053:4053:4053)) + (PORT d[10] (4140:4140:4140) (4198:4198:4198)) + (PORT d[11] (4214:4214:4214) (4273:4273:4273)) + (PORT d[12] (4360:4360:4360) (4361:4361:4361)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1268:1268:1268) (1338:1338:1338)) + (PORT d[1] (2087:2087:2087) (2131:2131:2131)) + (PORT d[2] (1333:1333:1333) (1395:1395:1395)) + (PORT d[3] (2508:2508:2508) (2683:2683:2683)) + (PORT d[4] (1258:1258:1258) (1323:1323:1323)) + (PORT d[5] (938:938:938) (975:975:975)) + (PORT d[6] (965:965:965) (1011:1011:1011)) + (PORT d[7] (1193:1193:1193) (1252:1252:1252)) + (PORT d[8] (1402:1402:1402) (1454:1454:1454)) + (PORT d[9] (1216:1216:1216) (1259:1259:1259)) + (PORT d[10] (1990:1990:1990) (2152:2152:2152)) + (PORT d[11] (2250:2250:2250) (2333:2333:2333)) + (PORT d[12] (1379:1379:1379) (1516:1516:1516)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1867:1867:1867)) + (PORT d[0] (1359:1359:1359) (1357:1357:1357)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1868:1868:1868)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1639:1639:1639) (1727:1727:1727)) + (PORT clk (1860:1860:1860) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2991:2991:2991) (3120:3120:3120)) + (PORT d[1] (1923:1923:1923) (2019:2019:2019)) + (PORT d[2] (2737:2737:2737) (2892:2892:2892)) + (PORT d[3] (3280:3280:3280) (3407:3407:3407)) + (PORT d[4] (3688:3688:3688) (4011:4011:4011)) + (PORT d[5] (2963:2963:2963) (3075:3075:3075)) + (PORT d[6] (2544:2544:2544) (2644:2644:2644)) + (PORT d[7] (2403:2403:2403) (2572:2572:2572)) + (PORT d[8] (2331:2331:2331) (2443:2443:2443)) + (PORT d[9] (2375:2375:2375) (2547:2547:2547)) + (PORT d[10] (2035:2035:2035) (2222:2222:2222)) + (PORT d[11] (2411:2411:2411) (2566:2566:2566)) + (PORT d[12] (1697:1697:1697) (1874:1874:1874)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2056:2056:2056) (2030:2030:2030)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (PORT d[0] (3482:3482:3482) (3430:3430:3430)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1176:1176:1176) (1198:1198:1198)) + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4124:4124:4124) (4261:4261:4261)) + (PORT d[1] (4264:4264:4264) (4468:4468:4468)) + (PORT d[2] (4278:4278:4278) (4394:4394:4394)) + (PORT d[3] (4271:4271:4271) (4371:4371:4371)) + (PORT d[4] (4399:4399:4399) (4428:4428:4428)) + (PORT d[5] (4294:4294:4294) (4643:4643:4643)) + (PORT d[6] (4213:4213:4213) (4514:4514:4514)) + (PORT d[7] (4303:4303:4303) (4402:4402:4402)) + (PORT d[8] (4172:4172:4172) (4153:4153:4153)) + (PORT d[9] (4045:4045:4045) (4053:4053:4053)) + (PORT d[10] (4033:4033:4033) (4060:4060:4060)) + (PORT d[11] (4226:4226:4226) (4315:4315:4315)) + (PORT d[12] (4347:4347:4347) (4348:4348:4348)) + (PORT clk (1821:1821:1821) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (757:757:757)) + (PORT datab (1231:1231:1231) (1269:1269:1269)) + (PORT datac (1183:1183:1183) (1213:1213:1213)) + (PORT datad (1230:1230:1230) (1278:1278:1278)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1566:1566:1566) (1643:1643:1643)) + (PORT datab (278:278:278) (364:364:364)) + (PORT datac (1461:1461:1461) (1522:1522:1522)) + (PORT datad (327:327:327) (350:350:350)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1526:1526:1526)) + (PORT datab (2521:2521:2521) (2610:2610:2610)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (317:317:317) (338:338:338)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1509:1509:1509)) + (PORT datab (1183:1183:1183) (1226:1226:1226)) + (PORT datac (913:913:913) (955:955:955)) + (PORT datad (323:323:323) (340:340:340)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (690:690:690)) + (PORT datab (255:255:255) (314:314:314)) + (PORT datac (1482:1482:1482) (1530:1530:1530)) + (PORT datad (1924:1924:1924) (1963:1963:1963)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (291:291:291)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1126:1126:1126) (1179:1179:1179)) + (PORT datad (247:247:247) (293:293:293)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1537:1537:1537)) + (PORT ena (1830:1830:1830) (1880:1880:1880)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1430:1430:1430)) + (PORT datab (883:883:883) (913:913:913)) + (PORT datac (444:444:444) (520:520:520)) + (PORT datad (1160:1160:1160) (1200:1200:1200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1357:1357:1357)) + (PORT datab (1438:1438:1438) (1496:1496:1496)) + (PORT datac (939:939:939) (1039:1039:1039)) + (PORT datad (652:652:652) (679:679:679)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (899:899:899) (918:918:918)) + (PORT datad (1105:1105:1105) (1110:1110:1110)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1434:1434:1434) (1528:1528:1528)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1497:1497:1497)) + (PORT datab (1283:1283:1283) (1422:1422:1422)) + (PORT datac (1867:1867:1867) (1999:1999:1999)) + (PORT datad (1210:1210:1210) (1244:1244:1244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (964:964:964)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1162:1162:1162) (1203:1203:1203)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1348:1348:1348)) + (PORT datab (1574:1574:1574) (1640:1640:1640)) + (PORT datac (1220:1220:1220) (1284:1284:1284)) + (PORT datad (1936:1936:1936) (2038:2038:2038)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (996:996:996)) + (PORT datab (1524:1524:1524) (1592:1592:1592)) + (PORT datac (1213:1213:1213) (1250:1250:1250)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1162:1162:1162)) + (PORT datab (1201:1201:1201) (1247:1247:1247)) + (PORT datac (935:935:935) (980:980:980)) + (PORT datad (925:925:925) (986:986:986)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1907:1907:1907) (2042:2042:2042)) + (PORT datab (1314:1314:1314) (1413:1413:1413)) + (PORT datac (936:936:936) (977:977:977)) + (PORT datad (1184:1184:1184) (1249:1249:1249)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (955:955:955) (1015:1015:1015)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1030:1030:1030)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2757:2757:2757) (2871:2871:2871)) + (PORT d[1] (1970:1970:1970) (2094:2094:2094)) + (PORT d[2] (3675:3675:3675) (3898:3898:3898)) + (PORT d[3] (1552:1552:1552) (1634:1634:1634)) + (PORT d[4] (1575:1575:1575) (1673:1673:1673)) + (PORT d[5] (1806:1806:1806) (1887:1887:1887)) + (PORT d[6] (2818:2818:2818) (2928:2928:2928)) + (PORT d[7] (1458:1458:1458) (1559:1559:1559)) + (PORT d[8] (3243:3243:3243) (3423:3423:3423)) + (PORT d[9] (1741:1741:1741) (1834:1834:1834)) + (PORT d[10] (2020:2020:2020) (2229:2229:2229)) + (PORT d[11] (2722:2722:2722) (2820:2820:2820)) + (PORT d[12] (1639:1639:1639) (1788:1788:1788)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (917:917:917) (868:868:868)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2288:2288:2288) (2284:2284:2284)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT datab (469:469:469) (547:547:547)) + (PORT datac (720:720:720) (804:804:804)) + (PORT datad (697:697:697) (783:783:783)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1308:1308:1308)) + (PORT datab (771:771:771) (844:844:844)) + (PORT datac (855:855:855) (920:920:920)) + (PORT datad (720:720:720) (794:794:794)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (832:832:832)) + (PORT datac (850:850:850) (871:871:871)) + (PORT datad (920:920:920) (962:962:962)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (909:909:909)) + (PORT datad (360:360:360) (388:388:388)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (851:851:851)) + (PORT datab (315:315:315) (412:412:412)) + (PORT datac (855:855:855) (912:912:912)) + (PORT datad (413:413:413) (485:485:485)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (266:266:266)) + (PORT datab (890:890:890) (953:953:953)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (703:703:703) (779:779:779)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (333:333:333) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (647:647:647)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (759:759:759)) + (PORT datab (2119:2119:2119) (2270:2270:2270)) + (PORT datac (2006:2006:2006) (2083:2083:2083)) + (PORT datad (633:633:633) (687:687:687)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (864:864:864)) + (PORT datab (952:952:952) (1021:1021:1021)) + (PORT datac (699:699:699) (766:766:766)) + (PORT datad (1185:1185:1185) (1242:1242:1242)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (770:770:770)) + (PORT datac (703:703:703) (780:780:780)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (812:812:812)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (617:617:617) (666:666:666)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT datab (915:915:915) (932:932:932)) + (PORT datad (979:979:979) (1064:1064:1064)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (798:798:798)) + (PORT datad (947:947:947) (1024:1024:1024)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1059:1059:1059)) + (PORT datab (741:741:741) (828:828:828)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1054:1054:1054)) + (PORT datac (965:965:965) (1026:1026:1026)) + (PORT datad (706:706:706) (786:786:786)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1068:1068:1068)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (940:940:940) (1016:1016:1016)) + (PORT datad (666:666:666) (740:740:740)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (520:520:520)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (626:626:626) (649:649:649)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1106:1106:1106)) + (PORT datad (316:316:316) (334:334:334)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1077:1077:1077)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (1692:1692:1692) (1798:1798:1798)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1074:1074:1074)) + (PORT datab (1052:1052:1052) (1151:1151:1151)) + (PORT datac (1141:1141:1141) (1217:1217:1217)) + (PORT datad (909:909:909) (953:953:953)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (1285:1285:1285) (1358:1358:1358)) + (PORT datad (679:679:679) (757:757:757)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1184:1184:1184)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (911:911:911) (960:960:960)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1181:1181:1181)) + (PORT datab (1284:1284:1284) (1356:1356:1356)) + (PORT datac (981:981:981) (1036:1036:1036)) + (PORT datad (678:678:678) (757:757:757)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~72) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1186:1186:1186)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (348:348:348) (374:374:374)) + (PORT datad (909:909:909) (953:953:953)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT datab (1172:1172:1172) (1252:1252:1252)) + (PORT datac (1019:1019:1019) (1120:1120:1120)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (859:859:859) (887:887:887)) + (PORT datac (911:911:911) (961:961:961)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (1009:1009:1009) (1072:1072:1072)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (751:751:751) (819:819:819)) + (PORT datad (920:920:920) (962:962:962)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (860:860:860)) + (PORT datab (546:546:546) (571:571:571)) + (PORT datac (617:617:617) (666:666:666)) + (PORT datad (690:690:690) (766:766:766)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (966:966:966)) + (PORT datab (1275:1275:1275) (1351:1351:1351)) + (PORT datac (1144:1144:1144) (1220:1220:1220)) + (PORT datad (1038:1038:1038) (1141:1141:1141)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (1005:1005:1005) (1070:1070:1070)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (3182:3182:3182) (3335:3335:3335)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (3843:3843:3843) (4045:4045:4045)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1226:1226:1226)) + (PORT datab (1274:1274:1274) (1325:1325:1325)) + (PORT datad (907:907:907) (925:925:925)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1107:1107:1107)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datad (978:978:978) (1063:1063:1063)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (862:862:862)) + (PORT datab (952:952:952) (1022:1022:1022)) + (PORT datac (615:615:615) (663:663:663)) + (PORT datad (522:522:522) (535:535:535)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (693:693:693)) + (PORT datab (762:762:762) (868:868:868)) + (PORT datad (371:371:371) (394:394:394)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (694:694:694) (749:749:749)) + (PORT datac (2243:2243:2243) (2311:2311:2311)) + (PORT datad (2170:2170:2170) (2360:2360:2360)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (575:575:575) (584:584:584)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1213:1213:1213)) + (PORT datab (1448:1448:1448) (1508:1508:1508)) + (PORT datac (1627:1627:1627) (1729:1729:1729)) + (PORT datad (1645:1645:1645) (1661:1661:1661)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1339:1339:1339)) + (PORT datab (964:964:964) (990:990:990)) + (PORT datac (1578:1578:1578) (1632:1632:1632)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (990:990:990) (1022:1022:1022)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2755:2755:2755) (2866:2866:2866)) + (PORT d[1] (1967:1967:1967) (2088:2088:2088)) + (PORT d[2] (3689:3689:3689) (3898:3898:3898)) + (PORT d[3] (1862:1862:1862) (1981:1981:1981)) + (PORT d[4] (1594:1594:1594) (1706:1706:1706)) + (PORT d[5] (1813:1813:1813) (1910:1910:1910)) + (PORT d[6] (2823:2823:2823) (2949:2949:2949)) + (PORT d[7] (1737:1737:1737) (1833:1833:1833)) + (PORT d[8] (3243:3243:3243) (3423:3423:3423)) + (PORT d[9] (3980:3980:3980) (4212:4212:4212)) + (PORT d[10] (1992:1992:1992) (2193:2193:2193)) + (PORT d[11] (1251:1251:1251) (1305:1305:1305)) + (PORT d[12] (1704:1704:1704) (1861:1861:1861)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1517:1517:1517) (1507:1507:1507)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2337:2337:2337) (2337:2337:2337)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1630:1630:1630)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2436:2436:2436) (2535:2535:2535)) + (PORT d[1] (1636:1636:1636) (1732:1732:1732)) + (PORT d[2] (3049:3049:3049) (3226:3226:3226)) + (PORT d[3] (2235:2235:2235) (2404:2404:2404)) + (PORT d[4] (3974:3974:3974) (4319:4319:4319)) + (PORT d[5] (3038:3038:3038) (3183:3183:3183)) + (PORT d[6] (2232:2232:2232) (2345:2345:2345)) + (PORT d[7] (2113:2113:2113) (2261:2261:2261)) + (PORT d[8] (2638:2638:2638) (2774:2774:2774)) + (PORT d[9] (3330:3330:3330) (3533:3533:3533)) + (PORT d[10] (1982:1982:1982) (2166:2166:2166)) + (PORT d[11] (2692:2692:2692) (2838:2838:2838)) + (PORT d[12] (1889:1889:1889) (2062:2062:2062)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1801:1801:1801) (1815:1815:1815)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (3133:3133:3133) (3156:3156:3156)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (922:922:922) (946:946:946)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4113:4113:4113) (4233:4233:4233)) + (PORT d[1] (4194:4194:4194) (4328:4328:4328)) + (PORT d[2] (4141:4141:4141) (4265:4265:4265)) + (PORT d[3] (4135:4135:4135) (4218:4218:4218)) + (PORT d[4] (4258:4258:4258) (4351:4351:4351)) + (PORT d[5] (4319:4319:4319) (4667:4667:4667)) + (PORT d[6] (4337:4337:4337) (4453:4453:4453)) + (PORT d[7] (4151:4151:4151) (4292:4292:4292)) + (PORT d[8] (4234:4234:4234) (4221:4221:4221)) + (PORT d[9] (4109:4109:4109) (4088:4088:4088)) + (PORT d[10] (4056:4056:4056) (4117:4117:4117)) + (PORT d[11] (4078:4078:4078) (4079:4079:4079)) + (PORT d[12] (4346:4346:4346) (4363:4363:4363)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2903:2903:2903) (3029:3029:3029)) + (PORT d[1] (3106:3106:3106) (3142:3142:3142)) + (PORT d[2] (2608:2608:2608) (2704:2704:2704)) + (PORT d[3] (1163:1163:1163) (1202:1202:1202)) + (PORT d[4] (2921:2921:2921) (3198:3198:3198)) + (PORT d[5] (3087:3087:3087) (3152:3152:3152)) + (PORT d[6] (3990:3990:3990) (4244:4244:4244)) + (PORT d[7] (1711:1711:1711) (1713:1713:1713)) + (PORT d[8] (3924:3924:3924) (4175:4175:4175)) + (PORT d[9] (4517:4517:4517) (4792:4792:4792)) + (PORT d[10] (1285:1285:1285) (1368:1368:1368)) + (PORT d[11] (3609:3609:3609) (3824:3824:3824)) + (PORT d[12] (952:952:952) (969:969:969)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1001:1001:1001) (954:954:954)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1387:1387:1387)) + (PORT datab (1523:1523:1523) (1625:1625:1625)) + (PORT datac (1467:1467:1467) (1536:1536:1536)) + (PORT datad (1160:1160:1160) (1184:1184:1184)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (947:947:947) (971:971:971)) + (PORT d[0] (698:698:698) (719:719:719)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -41760,19 +41335,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3042:3042:3042) (3290:3290:3290)) - (PORT d[1] (1608:1608:1608) (1696:1696:1696)) - (PORT d[2] (994:994:994) (1040:1040:1040)) - (PORT d[3] (946:946:946) (995:995:995)) - (PORT d[4] (1164:1164:1164) (1193:1193:1193)) - (PORT d[5] (957:957:957) (1004:1004:1004)) - (PORT d[6] (1556:1556:1556) (1674:1674:1674)) - (PORT d[7] (976:976:976) (1018:1018:1018)) - (PORT d[8] (1289:1289:1289) (1377:1377:1377)) - (PORT d[9] (775:775:775) (838:838:838)) - (PORT d[10] (729:729:729) (784:784:784)) - (PORT d[11] (2477:2477:2477) (2650:2650:2650)) - (PORT d[12] (1069:1069:1069) (1134:1134:1134)) + (PORT d[0] (2761:2761:2761) (2876:2876:2876)) + (PORT d[1] (1952:1952:1952) (2075:2075:2075)) + (PORT d[2] (3703:3703:3703) (3935:3935:3935)) + (PORT d[3] (1899:1899:1899) (2036:2036:2036)) + (PORT d[4] (1303:1303:1303) (1369:1369:1369)) + (PORT d[5] (1548:1548:1548) (1617:1617:1617)) + (PORT d[6] (1306:1306:1306) (1390:1390:1390)) + (PORT d[7] (1513:1513:1513) (1578:1578:1578)) + (PORT d[8] (3565:3565:3565) (3759:3759:3759)) + (PORT d[9] (2028:2028:2028) (2134:2134:2134)) + (PORT d[10] (1485:1485:1485) (1568:1568:1568)) + (PORT d[11] (977:977:977) (1034:1034:1034)) + (PORT d[12] (1635:1635:1635) (1784:1784:1784)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -41785,7 +41360,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (940:940:940) (896:896:896)) + (PORT d[0] (1429:1429:1429) (1388:1388:1388)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -41799,7 +41374,7 @@ (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2042:2042:2042) (2033:2033:2033)) + (PORT d[0] (1505:1505:1505) (1490:1490:1490)) ) ) ) @@ -41900,8 +41475,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1001:1001:1001) (1045:1045:1045)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (993:993:993) (1028:1028:1028)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) ) ) (TIMINGCHECK @@ -41913,20 +41488,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3024:3024:3024) (3251:3251:3251)) - (PORT d[1] (1903:1903:1903) (2000:2000:2000)) - (PORT d[2] (1280:1280:1280) (1322:1322:1322)) - (PORT d[3] (1267:1267:1267) (1318:1318:1318)) - (PORT d[4] (1471:1471:1471) (1527:1527:1527)) - (PORT d[5] (661:661:661) (688:688:688)) - (PORT d[6] (1836:1836:1836) (1967:1967:1967)) - (PORT d[7] (2929:2929:2929) (3085:3085:3085)) - (PORT d[8] (1275:1275:1275) (1340:1340:1340)) - (PORT d[9] (1006:1006:1006) (1059:1059:1059)) - (PORT d[10] (723:723:723) (773:773:773)) - (PORT d[11] (2518:2518:2518) (2677:2677:2677)) - (PORT d[12] (772:772:772) (836:836:836)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (2472:2472:2472) (2584:2584:2584)) + (PORT d[1] (1671:1671:1671) (1770:1770:1770)) + (PORT d[2] (3388:3388:3388) (3597:3597:3597)) + (PORT d[3] (1900:1900:1900) (2043:2043:2043)) + (PORT d[4] (1641:1641:1641) (1723:1723:1723)) + (PORT d[5] (2061:2061:2061) (2135:2135:2135)) + (PORT d[6] (1548:1548:1548) (1630:1630:1630)) + (PORT d[7] (1773:1773:1773) (1890:1890:1890)) + (PORT d[8] (3230:3230:3230) (3392:3392:3392)) + (PORT d[9] (3939:3939:3939) (4184:4184:4184)) + (PORT d[10] (1998:1998:1998) (2186:2186:2186)) + (PORT d[11] (2402:2402:2402) (2499:2499:2499)) + (PORT d[12] (1690:1690:1690) (1866:1866:1866)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -41938,8 +41513,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (942:942:942) (897:897:897)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1227:1227:1227) (1193:1193:1193)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -41951,8 +41526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (1808:1808:1808) (1808:1808:1808)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1775:1775:1775) (1781:1781:1781)) ) ) ) @@ -41961,7 +41536,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -41971,7 +41546,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -41981,7 +41556,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -41991,7 +41566,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -41999,4419 +41574,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1055:1055:1055) (1145:1145:1145)) - (PORT datab (960:960:960) (1036:1036:1036)) - (PORT datac (887:887:887) (907:907:907)) - (PORT datad (932:932:932) (969:969:969)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1406:1406:1406) (1432:1432:1432)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2471:2471:2471) (2605:2605:2605)) - (PORT d[1] (2523:2523:2523) (2576:2576:2576)) - (PORT d[2] (2567:2567:2567) (2747:2747:2747)) - (PORT d[3] (4593:4593:4593) (4820:4820:4820)) - (PORT d[4] (2930:2930:2930) (3056:3056:3056)) - (PORT d[5] (3148:3148:3148) (3203:3203:3203)) - (PORT d[6] (1481:1481:1481) (1477:1477:1477)) - (PORT d[7] (1396:1396:1396) (1430:1430:1430)) - (PORT d[8] (2490:2490:2490) (2615:2615:2615)) - (PORT d[9] (1697:1697:1697) (1729:1729:1729)) - (PORT d[10] (2540:2540:2540) (2643:2643:2643)) - (PORT d[11] (3702:3702:3702) (3993:3993:3993)) - (PORT d[12] (2490:2490:2490) (2565:2565:2565)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1996:1996:1996) (1955:1955:1955)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (1950:1950:1950) (1919:1919:1919)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1219:1219:1219)) - (PORT datab (1550:1550:1550) (1670:1670:1670)) - (PORT datac (349:349:349) (375:375:375)) - (PORT datad (1314:1314:1314) (1366:1366:1366)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1654:1654:1654)) - (PORT clk (1860:1860:1860) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2492:2492:2492) (2623:2623:2623)) - (PORT d[1] (2117:2117:2117) (2250:2250:2250)) - (PORT d[2] (2413:2413:2413) (2548:2548:2548)) - (PORT d[3] (2100:2100:2100) (2226:2226:2226)) - (PORT d[4] (2068:2068:2068) (2175:2175:2175)) - (PORT d[5] (2319:2319:2319) (2438:2438:2438)) - (PORT d[6] (2333:2333:2333) (2448:2448:2448)) - (PORT d[7] (3448:3448:3448) (3532:3532:3532)) - (PORT d[8] (2854:2854:2854) (2949:2949:2949)) - (PORT d[9] (2032:2032:2032) (2198:2198:2198)) - (PORT d[10] (3609:3609:3609) (3784:3784:3784)) - (PORT d[11] (2147:2147:2147) (2282:2282:2282)) - (PORT d[12] (1982:1982:1982) (2139:2139:2139)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1972:1972:1972) (1939:1939:1939)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (PORT d[0] (3223:3223:3223) (3296:3296:3296)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2151:2151:2151) (2201:2201:2201)) - (PORT clk (1825:1825:1825) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4343:4343:4343) (4403:4403:4403)) - (PORT d[1] (4498:4498:4498) (4585:4585:4585)) - (PORT d[2] (4548:4548:4548) (4611:4611:4611)) - (PORT d[3] (4307:4307:4307) (4402:4402:4402)) - (PORT d[4] (4392:4392:4392) (4483:4483:4483)) - (PORT d[5] (4431:4431:4431) (4542:4542:4542)) - (PORT d[6] (4555:4555:4555) (4660:4660:4660)) - (PORT d[7] (4287:4287:4287) (4335:4335:4335)) - (PORT d[8] (4389:4389:4389) (4493:4493:4493)) - (PORT d[9] (4480:4480:4480) (4525:4525:4525)) - (PORT d[10] (4429:4429:4429) (4529:4529:4529)) - (PORT d[11] (4427:4427:4427) (4554:4554:4554)) - (PORT d[12] (4332:4332:4332) (4318:4318:4318)) - (PORT clk (1821:1821:1821) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1978:1978:1978) (2105:2105:2105)) - (PORT d[1] (2195:2195:2195) (2216:2216:2216)) - (PORT d[2] (2233:2233:2233) (2405:2405:2405)) - (PORT d[3] (1730:1730:1730) (1765:1765:1765)) - (PORT d[4] (2301:2301:2301) (2429:2429:2429)) - (PORT d[5] (2806:2806:2806) (2865:2865:2865)) - (PORT d[6] (1746:1746:1746) (1828:1828:1828)) - (PORT d[7] (1972:1972:1972) (2011:2011:2011)) - (PORT d[8] (2183:2183:2183) (2302:2302:2302)) - (PORT d[9] (2006:2006:2006) (2072:2072:2072)) - (PORT d[10] (2505:2505:2505) (2578:2578:2578)) - (PORT d[11] (4321:4321:4321) (4631:4631:4631)) - (PORT d[12] (2164:2164:2164) (2232:2232:2232)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (2147:2147:2147) (2137:2137:2137)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (978:978:978)) - (PORT datab (772:772:772) (880:880:880)) - (PORT datac (1200:1200:1200) (1239:1239:1239)) - (PORT datad (1667:1667:1667) (1720:1720:1720)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1483:1483:1483) (1518:1518:1518)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2205:2205:2205) (2306:2306:2306)) - (PORT d[1] (2632:2632:2632) (2785:2785:2785)) - (PORT d[2] (2362:2362:2362) (2492:2492:2492)) - (PORT d[3] (3051:3051:3051) (3158:3158:3158)) - (PORT d[4] (2271:2271:2271) (2411:2411:2411)) - (PORT d[5] (3452:3452:3452) (3554:3554:3554)) - (PORT d[6] (2543:2543:2543) (2661:2661:2661)) - (PORT d[7] (2952:2952:2952) (3038:3038:3038)) - (PORT d[8] (2643:2643:2643) (2727:2727:2727)) - (PORT d[9] (2971:2971:2971) (3112:3112:3112)) - (PORT d[10] (2322:2322:2322) (2378:2378:2378)) - (PORT d[11] (2215:2215:2215) (2364:2364:2364)) - (PORT d[12] (3539:3539:3539) (3735:3735:3735)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2575:2575:2575) (2593:2593:2593)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (3571:3571:3571) (3500:3500:3500)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2190:2190:2190) (2175:2175:2175)) - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4505:4505:4505) (4525:4525:4525)) - (PORT d[1] (4469:4469:4469) (4501:4501:4501)) - (PORT d[2] (4469:4469:4469) (4476:4476:4476)) - (PORT d[3] (4421:4421:4421) (4437:4437:4437)) - (PORT d[4] (4275:4275:4275) (4372:4372:4372)) - (PORT d[5] (4447:4447:4447) (4521:4521:4521)) - (PORT d[6] (4240:4240:4240) (4335:4335:4335)) - (PORT d[7] (4388:4388:4388) (4448:4448:4448)) - (PORT d[8] (4382:4382:4382) (4489:4489:4489)) - (PORT d[9] (4346:4346:4346) (4404:4404:4404)) - (PORT d[10] (4279:4279:4279) (4347:4347:4347)) - (PORT d[11] (4488:4488:4488) (4529:4529:4529)) - (PORT d[12] (4294:4294:4294) (4294:4294:4294)) - (PORT clk (1830:1830:1830) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2240:2240:2240) (2401:2401:2401)) - (PORT d[1] (1094:1094:1094) (1093:1093:1093)) - (PORT d[2] (2654:2654:2654) (2732:2732:2732)) - (PORT d[3] (4596:4596:4596) (4810:4810:4810)) - (PORT d[4] (1006:1006:1006) (1054:1054:1054)) - (PORT d[5] (2205:2205:2205) (2223:2223:2223)) - (PORT d[6] (2849:2849:2849) (2950:2950:2950)) - (PORT d[7] (1412:1412:1412) (1409:1409:1409)) - (PORT d[8] (2768:2768:2768) (2898:2898:2898)) - (PORT d[9] (1486:1486:1486) (1518:1518:1518)) - (PORT d[10] (2026:2026:2026) (2083:2083:2083)) - (PORT d[11] (3734:3734:3734) (3998:3998:3998)) - (PORT d[12] (1704:1704:1704) (1711:1711:1711)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1879:1879:1879)) - (PORT d[0] (1336:1336:1336) (1345:1345:1345)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1202:1202:1202)) - (PORT datab (947:947:947) (970:970:970)) - (PORT datac (998:998:998) (1057:1057:1057)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (772:772:772) (884:884:884)) - (PORT datac (1893:1893:1893) (1938:1938:1938)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (1727:1727:1727) (1787:1787:1787)) - (PORT datab (3006:3006:3006) (3258:3258:3258)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (966:966:966)) - (PORT datab (902:902:902) (924:924:924)) - (PORT datac (1649:1649:1649) (1666:1666:1666)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1288:1288:1288)) - (PORT datab (2963:2963:2963) (3072:3072:3072)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (1441:1441:1441) (1491:1491:1491)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1194:1194:1194)) - (PORT datab (424:424:424) (459:459:459)) - (PORT datac (371:371:371) (400:400:400)) - (PORT datad (1127:1127:1127) (1155:1155:1155)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (253:253:253) (299:299:299)) - (PORT datac (220:220:220) (264:264:264)) - (PORT datad (2132:2132:2132) (2201:2201:2201)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1434:1434:1434) (1471:1471:1471)) - (PORT datac (1092:1092:1092) (1123:1123:1123)) - (PORT datad (217:217:217) (254:254:254)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (714:714:714) (741:741:741)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1683:1683:1683) (1793:1793:1793)) - (PORT datab (1366:1366:1366) (1396:1396:1396)) - (PORT datac (208:208:208) (251:251:251)) - (PORT datad (1331:1331:1331) (1338:1338:1338)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2302:2302:2302) (2437:2437:2437)) - (PORT datab (2181:2181:2181) (2361:2361:2361)) - (PORT datac (2247:2247:2247) (2350:2350:2350)) - (PORT datad (365:365:365) (398:398:398)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datac (996:996:996) (1081:1081:1081)) - (PORT datad (1502:1502:1502) (1553:1553:1553)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (948:948:948)) - (PORT datab (1697:1697:1697) (1728:1728:1728)) - (PORT datac (1067:1067:1067) (1109:1109:1109)) - (PORT datad (812:812:812) (861:861:861)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (662:662:662)) - (PORT datab (1244:1244:1244) (1274:1274:1274)) - (PORT datad (871:871:871) (916:916:916)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1153:1153:1153)) - (PORT datab (609:609:609) (654:654:654)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (597:597:597) (613:613:613)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (719:719:719)) - (PORT datab (700:700:700) (775:775:775)) - (PORT datac (1424:1424:1424) (1508:1508:1508)) - (PORT datad (601:601:601) (661:661:661)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1234:1234:1234)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (610:610:610) (637:637:637)) - (PORT datad (772:772:772) (823:823:823)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1333:1333:1333)) - (PORT datab (390:390:390) (423:423:423)) - (PORT datac (956:956:956) (1024:1024:1024)) - (PORT datad (1355:1355:1355) (1444:1444:1444)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1284:1284:1284)) - (PORT datab (1539:1539:1539) (1640:1640:1640)) - (PORT datac (578:578:578) (588:588:588)) - (PORT datad (863:863:863) (880:880:880)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1463:1463:1463)) - (PORT datab (2126:2126:2126) (2263:2263:2263)) - (PORT datac (1615:1615:1615) (1658:1658:1658)) - (PORT datad (695:695:695) (742:742:742)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (791:791:791)) - (PORT datab (649:649:649) (670:670:670)) - (PORT datac (1593:1593:1593) (1630:1630:1630)) - (PORT datad (1465:1465:1465) (1570:1570:1570)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1216:1216:1216)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (PORT datab (627:627:627) (678:678:678)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (349:349:349) (364:364:364)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (874:874:874) (925:925:925)) - (PORT datac (570:570:570) (586:586:586)) - (PORT datad (809:809:809) (832:832:832)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (621:621:621)) - (PORT datab (601:601:601) (620:620:620)) - (PORT datac (899:899:899) (936:936:936)) - (PORT datad (809:809:809) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (297:297:297)) - (PORT datab (874:874:874) (928:928:928)) - (PORT datac (650:650:650) (693:693:693)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1133:1133:1133)) - (PORT datab (1173:1173:1173) (1212:1212:1212)) - (PORT datac (1315:1315:1315) (1328:1328:1328)) - (PORT datad (1358:1358:1358) (1425:1425:1425)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (661:661:661)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (851:851:851) (873:873:873)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (649:649:649)) - (PORT datac (630:630:630) (662:662:662)) - (PORT datad (838:838:838) (858:858:858)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (883:883:883) (909:909:909)) - (PORT datad (177:177:177) (203:203:203)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (910:910:910)) - (PORT datab (1157:1157:1157) (1201:1201:1201)) - (PORT datad (384:384:384) (414:414:414)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (573:573:573)) - (PORT datac (751:751:751) (825:825:825)) - (PORT datad (387:387:387) (454:454:454)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (764:764:764)) - (PORT datac (977:977:977) (1063:1063:1063)) - (PORT datad (614:614:614) (686:686:686)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (578:578:578) (587:587:587)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (774:774:774) (851:851:851)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) - (DELAY - (ABSOLUTE - (PORT datab (1813:1813:1813) (1930:1930:1930)) - (PORT datac (2265:2265:2265) (2466:2466:2466)) - (PORT datad (915:915:915) (970:970:970)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (422:422:422)) - (PORT datab (682:682:682) (750:750:750)) - (PORT datac (916:916:916) (978:978:978)) - (PORT datad (948:948:948) (1021:1021:1021)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (792:792:792)) - (PORT datab (793:793:793) (875:875:875)) - (PORT datac (1034:1034:1034) (1097:1097:1097)) - (PORT datad (738:738:738) (822:822:822)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (796:796:796)) - (PORT datab (792:792:792) (873:873:873)) - (PORT datac (1031:1031:1031) (1096:1096:1096)) - (PORT datad (735:735:735) (819:819:819)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (1063:1063:1063) (1131:1131:1131)) - (PORT datac (1262:1262:1262) (1333:1333:1333)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (816:816:816)) - (PORT datab (1297:1297:1297) (1371:1371:1371)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (812:812:812)) - (PORT datab (607:607:607) (611:611:611)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1547:1547:1547) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (837:837:837)) - (PORT datab (726:726:726) (804:804:804)) - (PORT datac (739:739:739) (817:817:817)) - (PORT datad (1023:1023:1023) (1086:1086:1086)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (995:995:995) (1074:1074:1074)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (522:522:522) (541:541:541)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1126:1126:1126)) - (PORT datac (461:461:461) (535:535:535)) - (PORT datad (928:928:928) (988:988:988)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (988:988:988)) - (PORT datab (945:945:945) (1001:1001:1001)) - (PORT datac (641:641:641) (696:696:696)) - (PORT datad (1431:1431:1431) (1449:1449:1449)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (281:281:281)) - (PORT datab (921:921:921) (969:969:969)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (591:591:591)) - (PORT datab (930:930:930) (1017:1017:1017)) - (PORT datac (753:753:753) (840:840:840)) - (PORT datad (703:703:703) (775:775:775)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (652:652:652) (674:674:674)) - (PORT datac (937:937:937) (1024:1024:1024)) - (PORT datad (888:888:888) (925:925:925)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (500:500:500) (572:572:572)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (594:594:594)) - (PORT datab (970:970:970) (1057:1057:1057)) - (PORT datac (753:753:753) (842:842:842)) - (PORT datad (702:702:702) (779:779:779)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (820:820:820)) - (PORT datab (1305:1305:1305) (1362:1362:1362)) - (PORT datac (732:732:732) (817:817:817)) - (PORT datad (312:312:312) (329:329:329)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (767:767:767) (847:847:847)) - (PORT datac (462:462:462) (540:540:540)) - (PORT datad (925:925:925) (984:984:984)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (674:674:674)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (724:724:724)) - (PORT datab (669:669:669) (741:741:741)) - (PORT datac (672:672:672) (714:714:714)) - (PORT datad (1494:1494:1494) (1585:1585:1585)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (1299:1299:1299) (1375:1375:1375)) - (PORT datac (685:685:685) (784:784:784)) - (PORT datad (717:717:717) (806:806:806)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1397:1397:1397)) - (PORT datab (659:659:659) (682:682:682)) - (PORT datad (593:593:593) (616:616:616)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1401:1401:1401)) - (PORT datab (1016:1016:1016) (1083:1083:1083)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (2798:2798:2798) (3000:3000:3000)) - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (2352:2352:2352) (2576:2576:2576)) - (PORT datad (570:570:570) (582:582:582)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1278:1278:1278) (1317:1317:1317)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2420:2420:2420) (2614:2614:2614)) - (PORT d[1] (2542:2542:2542) (2641:2641:2641)) - (PORT d[2] (1265:1265:1265) (1333:1333:1333)) - (PORT d[3] (1256:1256:1256) (1301:1301:1301)) - (PORT d[4] (2037:2037:2037) (2116:2116:2116)) - (PORT d[5] (1268:1268:1268) (1326:1326:1326)) - (PORT d[6] (1448:1448:1448) (1473:1473:1473)) - (PORT d[7] (2668:2668:2668) (2814:2814:2814)) - (PORT d[8] (2486:2486:2486) (2658:2658:2658)) - (PORT d[9] (774:774:774) (839:839:839)) - (PORT d[10] (732:732:732) (787:787:787)) - (PORT d[11] (1198:1198:1198) (1240:1240:1240)) - (PORT d[12] (723:723:723) (773:773:773)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1249:1249:1249) (1220:1220:1220)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (1711:1711:1711) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1001:1001:1001) (1024:1024:1024)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2737:2737:2737) (2961:2961:2961)) - (PORT d[1] (1936:1936:1936) (2018:2018:2018)) - (PORT d[2] (998:998:998) (1029:1029:1029)) - (PORT d[3] (969:969:969) (994:994:994)) - (PORT d[4] (1425:1425:1425) (1469:1469:1469)) - (PORT d[5] (958:958:958) (992:992:992)) - (PORT d[6] (1158:1158:1158) (1170:1170:1170)) - (PORT d[7] (2950:2950:2950) (3104:3104:3104)) - (PORT d[8] (1588:1588:1588) (1675:1675:1675)) - (PORT d[9] (737:737:737) (777:777:777)) - (PORT d[10] (715:715:715) (752:752:752)) - (PORT d[11] (2487:2487:2487) (2667:2667:2667)) - (PORT d[12] (760:760:760) (814:814:814)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (948:948:948) (922:922:922)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (3281:3281:3281) (3342:3342:3342)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1192:1192:1192) (1163:1163:1163)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2546:2546:2546) (2729:2729:2729)) - (PORT d[1] (3618:3618:3618) (3824:3824:3824)) - (PORT d[2] (2381:2381:2381) (2458:2458:2458)) - (PORT d[3] (4288:4288:4288) (4492:4492:4492)) - (PORT d[4] (3170:3170:3170) (3405:3405:3405)) - (PORT d[5] (4727:4727:4727) (4889:4889:4889)) - (PORT d[6] (2532:2532:2532) (2627:2627:2627)) - (PORT d[7] (1392:1392:1392) (1407:1407:1407)) - (PORT d[8] (3122:3122:3122) (3282:3282:3282)) - (PORT d[9] (1802:1802:1802) (1840:1840:1840)) - (PORT d[10] (1997:1997:1997) (2034:2034:2034)) - (PORT d[11] (3401:3401:3401) (3659:3659:3659)) - (PORT d[12] (4693:4693:4693) (4992:4992:4992)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1888:1888:1888) (1943:1943:1943)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2445:2445:2445) (2405:2405:2405)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1077:1077:1077)) - (PORT datab (1231:1231:1231) (1326:1326:1326)) - (PORT datac (912:912:912) (954:954:954)) - (PORT datad (1090:1090:1090) (1094:1094:1094)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1370:1370:1370) (1410:1410:1410)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2461:2461:2461) (2613:2613:2613)) - (PORT d[1] (2479:2479:2479) (2511:2511:2511)) - (PORT d[2] (2577:2577:2577) (2775:2775:2775)) - (PORT d[3] (1707:1707:1707) (1744:1744:1744)) - (PORT d[4] (2415:2415:2415) (2564:2564:2564)) - (PORT d[5] (3183:3183:3183) (3261:3261:3261)) - (PORT d[6] (2218:2218:2218) (2320:2320:2320)) - (PORT d[7] (1719:1719:1719) (1754:1754:1754)) - (PORT d[8] (2452:2452:2452) (2554:2554:2554)) - (PORT d[9] (1710:1710:1710) (1761:1761:1761)) - (PORT d[10] (2530:2530:2530) (2628:2628:2628)) - (PORT d[11] (4031:4031:4031) (4326:4326:4326)) - (PORT d[12] (2475:2475:2475) (2545:2545:2545)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2002:2002:2002) (1964:1964:1964)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2204:2204:2204) (2160:2160:2160)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1636:1636:1636)) - (PORT datab (1198:1198:1198) (1226:1226:1226)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1384:1384:1384) (1422:1422:1422)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1498:1498:1498) (1529:1529:1529)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2502:2502:2502) (2600:2600:2600)) - (PORT d[1] (2280:2280:2280) (2376:2376:2376)) - (PORT d[2] (2063:2063:2063) (2187:2187:2187)) - (PORT d[3] (3319:3319:3319) (3431:3431:3431)) - (PORT d[4] (2302:2302:2302) (2458:2458:2458)) - (PORT d[5] (3776:3776:3776) (3885:3885:3885)) - (PORT d[6] (2525:2525:2525) (2638:2638:2638)) - (PORT d[7] (2494:2494:2494) (2555:2555:2555)) - (PORT d[8] (2947:2947:2947) (3049:3049:3049)) - (PORT d[9] (2749:2749:2749) (2863:2863:2863)) - (PORT d[10] (2929:2929:2929) (3041:3041:3041)) - (PORT d[11] (2742:2742:2742) (2907:2907:2907)) - (PORT d[12] (3512:3512:3512) (3716:3716:3716)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2834:2834:2834) (2862:2862:2862)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (3571:3571:3571) (3500:3500:3500)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2189:2189:2189) (2175:2175:2175)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4520:4520:4520) (4545:4545:4545)) - (PORT d[1] (4445:4445:4445) (4516:4516:4516)) - (PORT d[2] (4525:4525:4525) (4596:4596:4596)) - (PORT d[3] (4398:4398:4398) (4408:4408:4408)) - (PORT d[4] (4281:4281:4281) (4404:4404:4404)) - (PORT d[5] (4393:4393:4393) (4465:4465:4465)) - (PORT d[6] (4259:4259:4259) (4355:4355:4355)) - (PORT d[7] (4414:4414:4414) (4478:4478:4478)) - (PORT d[8] (4545:4545:4545) (4666:4666:4666)) - (PORT d[9] (4382:4382:4382) (4434:4434:4434)) - (PORT d[10] (4247:4247:4247) (4300:4300:4300)) - (PORT d[11] (4433:4433:4433) (4558:4558:4558)) - (PORT d[12] (4266:4266:4266) (4271:4271:4271)) - (PORT clk (1827:1827:1827) (1820:1820:1820)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1902:1902:1902) (2025:2025:2025)) - (PORT d[1] (1666:1666:1666) (1705:1705:1705)) - (PORT d[2] (1974:1974:1974) (2139:2139:2139)) - (PORT d[3] (1912:1912:1912) (1969:1969:1969)) - (PORT d[4] (2671:2671:2671) (2790:2790:2790)) - (PORT d[5] (2298:2298:2298) (2357:2357:2357)) - (PORT d[6] (1731:1731:1731) (1793:1793:1793)) - (PORT d[7] (2013:2013:2013) (2076:2076:2076)) - (PORT d[8] (1842:1842:1842) (1934:1934:1934)) - (PORT d[9] (2037:2037:2037) (2110:2110:2110)) - (PORT d[10] (1682:1682:1682) (1747:1747:1747)) - (PORT d[11] (4325:4325:4325) (4639:4639:4639)) - (PORT d[12] (1649:1649:1649) (1703:1703:1703)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (1818:1818:1818) (1849:1849:1849)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2479:2479:2479) (2628:2628:2628)) - (PORT d[1] (2661:2661:2661) (2805:2805:2805)) - (PORT d[2] (2218:2218:2218) (2383:2383:2383)) - (PORT d[3] (2113:2113:2113) (2258:2258:2258)) - (PORT d[4] (2079:2079:2079) (2164:2164:2164)) - (PORT d[5] (2439:2439:2439) (2558:2558:2558)) - (PORT d[6] (2443:2443:2443) (2606:2606:2606)) - (PORT d[7] (3431:3431:3431) (3496:3496:3496)) - (PORT d[8] (2846:2846:2846) (2932:2932:2932)) - (PORT d[9] (2326:2326:2326) (2495:2495:2495)) - (PORT d[10] (3304:3304:3304) (3449:3449:3449)) - (PORT d[11] (2127:2127:2127) (2238:2238:2238)) - (PORT d[12] (2274:2274:2274) (2444:2444:2444)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2586:2586:2586) (2674:2674:2674)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1617:1617:1617) (1708:1708:1708)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2779:2779:2779) (2918:2918:2918)) - (PORT d[1] (2949:2949:2949) (3110:3110:3110)) - (PORT d[2] (1977:1977:1977) (2112:2112:2112)) - (PORT d[3] (1867:1867:1867) (1994:1994:1994)) - (PORT d[4] (2099:2099:2099) (2223:2223:2223)) - (PORT d[5] (2640:2640:2640) (2717:2717:2717)) - (PORT d[6] (2148:2148:2148) (2291:2291:2291)) - (PORT d[7] (3421:3421:3421) (3502:3502:3502)) - (PORT d[8] (3155:3155:3155) (3258:3258:3258)) - (PORT d[9] (2282:2282:2282) (2439:2439:2439)) - (PORT d[10] (1914:1914:1914) (2041:2041:2041)) - (PORT d[11] (2100:2100:2100) (2231:2231:2231)) - (PORT d[12] (2417:2417:2417) (2564:2564:2564)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2032:2032:2032) (1996:1996:1996)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3200:3200:3200) (3274:3274:3274)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2121:2121:2121) (2166:2166:2166)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4469:4469:4469) (4578:4578:4578)) - (PORT d[1] (4411:4411:4411) (4529:4529:4529)) - (PORT d[2] (4405:4405:4405) (4501:4501:4501)) - (PORT d[3] (4285:4285:4285) (4378:4378:4378)) - (PORT d[4] (4390:4390:4390) (4479:4479:4479)) - (PORT d[5] (4452:4452:4452) (4565:4565:4565)) - (PORT d[6] (4355:4355:4355) (4476:4476:4476)) - (PORT d[7] (4330:4330:4330) (4373:4373:4373)) - (PORT d[8] (4626:4626:4626) (4732:4732:4732)) - (PORT d[9] (4460:4460:4460) (4519:4519:4519)) - (PORT d[10] (4392:4392:4392) (4490:4490:4490)) - (PORT d[11] (4393:4393:4393) (4515:4515:4515)) - (PORT d[12] (4353:4353:4353) (4336:4336:4336)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (978:978:978)) - (PORT datab (772:772:772) (879:879:879)) - (PORT datac (1450:1450:1450) (1528:1528:1528)) - (PORT datad (1149:1149:1149) (1208:1208:1208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1095:1095:1095)) - (PORT datab (1028:1028:1028) (1086:1086:1086)) - (PORT datac (1634:1634:1634) (1682:1682:1682)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (855:855:855)) - (PORT datab (1736:1736:1736) (1857:1857:1857)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (1727:1727:1727) (1788:1788:1788)) - (PORT datab (3006:3006:3006) (3259:3259:3259)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (952:952:952)) - (PORT datab (904:904:904) (927:927:927)) - (PORT datac (1645:1645:1645) (1661:1661:1661)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1251:1251:1251)) - (PORT datab (1465:1465:1465) (1529:1529:1529)) - (PORT datac (3210:3210:3210) (3305:3305:3305)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (424:424:424) (459:459:459)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1128:1128:1128) (1155:1155:1155)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (596:596:596) (602:602:602)) - (PORT datad (384:384:384) (411:411:411)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1731:1731:1731)) - (PORT datab (1942:1942:1942) (2048:2048:2048)) - (PORT datac (365:365:365) (407:407:407)) - (PORT datad (1162:1162:1162) (1219:1219:1219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (849:849:849)) - (PORT datab (767:767:767) (837:837:837)) - (PORT datac (1838:1838:1838) (1974:1974:1974)) - (PORT datad (1691:1691:1691) (1759:1759:1759)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2118:2118:2118) (2286:2286:2286)) - (PORT datab (1408:1408:1408) (1515:1515:1515)) - (PORT datac (1119:1119:1119) (1147:1147:1147)) - (PORT datad (878:878:878) (904:904:904)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1656:1656:1656)) - (PORT datab (641:641:641) (673:673:673)) - (PORT datac (1029:1029:1029) (1091:1091:1091)) - (PORT datad (2619:2619:2619) (2695:2695:2695)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1812:1812:1812) (1882:1882:1882)) - (PORT datab (1076:1076:1076) (1143:1143:1143)) - (PORT datac (829:829:829) (850:850:850)) - (PORT datad (2598:2598:2598) (2658:2658:2658)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (938:938:938)) - (PORT datab (1059:1059:1059) (1129:1129:1129)) - (PORT datac (1832:1832:1832) (1913:1913:1913)) - (PORT datad (626:626:626) (665:665:665)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1622:1622:1622) (1655:1655:1655)) - (PORT datab (2274:2274:2274) (2434:2434:2434)) - (PORT datac (617:617:617) (675:675:675)) - (PORT datad (986:986:986) (1083:1083:1083)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (768:768:768)) - (PORT datab (947:947:947) (968:968:968)) - (PORT datac (1488:1488:1488) (1481:1481:1481)) - (PORT datad (637:637:637) (690:690:690)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (645:645:645)) - (PORT datab (1172:1172:1172) (1176:1176:1176)) - (PORT datac (553:553:553) (580:580:580)) - (PORT datad (640:640:640) (656:656:656)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (501:501:501) (575:575:575)) - (PORT datad (632:632:632) (650:650:650)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (441:441:441)) - (PORT datab (383:383:383) (413:413:413)) - (PORT datad (188:188:188) (221:221:221)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (477:477:477)) - (PORT datab (947:947:947) (1001:1001:1001)) - (PORT datac (849:849:849) (861:861:861)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (595:595:595)) - (PORT datab (932:932:932) (1014:1014:1014)) - (PORT datac (754:754:754) (837:837:837)) - (PORT datad (707:707:707) (775:775:775)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (702:702:702)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (456:456:456) (525:525:525)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT datab (785:785:785) (866:866:866)) - (PORT datac (1271:1271:1271) (1329:1329:1329)) - (PORT datad (241:241:241) (310:310:310)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (818:818:818)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (729:729:729) (816:816:816)) - (PORT datad (620:620:620) (641:641:641)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (578:578:578)) - (PORT datab (1381:1381:1381) (1376:1376:1376)) - (PORT datad (316:316:316) (326:326:326)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1270:1270:1270) (1344:1344:1344)) - (PORT datab (912:912:912) (941:941:941)) - (PORT datac (606:606:606) (657:657:657)) - (PORT datad (645:645:645) (700:700:700)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (755:755:755)) - (PORT datab (722:722:722) (807:807:807)) - (PORT datac (1231:1231:1231) (1295:1295:1295)) - (PORT datad (1207:1207:1207) (1281:1281:1281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (647:647:647)) - (PORT datab (754:754:754) (844:844:844)) - (PORT datac (685:685:685) (783:783:783)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2314:2314:2314) (2533:2533:2533)) - (PORT datab (1430:1430:1430) (1559:1559:1559)) - (PORT datad (666:666:666) (718:718:718)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (401:401:401)) - (PORT datab (954:954:954) (1025:1025:1025)) - (PORT datac (1000:1000:1000) (1060:1060:1060)) - (PORT datad (711:711:711) (787:787:787)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1139:1139:1139)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (259:259:259) (337:337:337)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (440:440:440)) - (PORT datab (631:631:631) (657:657:657)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (653:653:653) (667:667:667)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (871:871:871)) - (PORT datab (612:612:612) (637:637:637)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (751:751:751)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datac (2427:2427:2427) (2603:2603:2603)) - (PORT datad (633:633:633) (684:684:684)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (622:622:622)) - (PORT datab (2465:2465:2465) (2646:2646:2646)) - (PORT datac (928:928:928) (975:975:975)) - (PORT datad (597:597:597) (633:633:633)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1204:1204:1204)) - (PORT datab (1206:1206:1206) (1216:1216:1216)) - (PORT datac (3269:3269:3269) (3535:3535:3535)) - (PORT datad (596:596:596) (633:633:633)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1025:1025:1025) (1033:1033:1033)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3329:3329:3329) (3586:3586:3586)) - (PORT d[1] (1573:1573:1573) (1649:1649:1649)) - (PORT d[2] (1037:1037:1037) (1080:1080:1080)) - (PORT d[3] (1599:1599:1599) (1696:1696:1696)) - (PORT d[4] (2959:2959:2959) (3149:3149:3149)) - (PORT d[5] (970:970:970) (999:999:999)) - (PORT d[6] (1576:1576:1576) (1694:1694:1694)) - (PORT d[7] (1281:1281:1281) (1303:1303:1303)) - (PORT d[8] (1219:1219:1219) (1280:1280:1280)) - (PORT d[9] (1098:1098:1098) (1184:1184:1184)) - (PORT d[10] (1037:1037:1037) (1112:1112:1112)) - (PORT d[11] (2217:2217:2217) (2342:2342:2342)) - (PORT d[12] (1083:1083:1083) (1173:1173:1173)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1145:1145:1145)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2363:2363:2363) (2340:2340:2340)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1004:1004:1004) (1015:1015:1015)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3337:3337:3337) (3609:3609:3609)) - (PORT d[1] (1306:1306:1306) (1388:1388:1388)) - (PORT d[2] (1698:1698:1698) (1789:1789:1789)) - (PORT d[3] (1595:1595:1595) (1675:1675:1675)) - (PORT d[4] (2970:2970:2970) (3138:3138:3138)) - (PORT d[5] (1270:1270:1270) (1328:1328:1328)) - (PORT d[6] (1305:1305:1305) (1402:1402:1402)) - (PORT d[7] (1331:1331:1331) (1362:1362:1362)) - (PORT d[8] (1550:1550:1550) (1637:1637:1637)) - (PORT d[9] (1103:1103:1103) (1195:1195:1195)) - (PORT d[10] (1045:1045:1045) (1128:1128:1128)) - (PORT d[11] (2177:2177:2177) (2321:2321:2321)) - (PORT d[12] (1373:1373:1373) (1464:1464:1464)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1223:1223:1223) (1198:1198:1198)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2348:2348:2348) (2353:2353:2353)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (956:956:956)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2672:2672:2672) (2905:2905:2905)) - (PORT d[1] (1536:1536:1536) (1605:1605:1605)) - (PORT d[2] (1356:1356:1356) (1434:1434:1434)) - (PORT d[3] (1321:1321:1321) (1406:1406:1406)) - (PORT d[4] (2655:2655:2655) (2825:2825:2825)) - (PORT d[5] (1588:1588:1588) (1655:1655:1655)) - (PORT d[6] (1518:1518:1518) (1625:1625:1625)) - (PORT d[7] (1580:1580:1580) (1612:1612:1612)) - (PORT d[8] (1535:1535:1535) (1634:1634:1634)) - (PORT d[9] (1648:1648:1648) (1754:1754:1754)) - (PORT d[10] (1343:1343:1343) (1445:1445:1445)) - (PORT d[11] (1880:1880:1880) (2005:2005:2005)) - (PORT d[12] (1391:1391:1391) (1503:1503:1503)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1260:1260:1260) (1255:1255:1255)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2386:2386:2386) (2419:2419:2419)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1837:1837:1837)) @@ -46425,7 +41587,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (995:995:995) (1000:1000:1000)) @@ -46434,7 +41596,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -46443,7 +41605,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -46453,7 +41615,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -46463,26 +41625,41 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~93) + (INSTANCE Selector14\~10) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (927:927:927)) - (PORT datab (1237:1237:1237) (1338:1338:1338)) - (PORT datad (912:912:912) (935:935:935)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (640:640:640) (669:669:669)) + (PORT datac (1123:1123:1123) (1187:1187:1187)) + (PORT datad (884:884:884) (922:922:922)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1339:1339:1339)) + (PORT datab (1293:1293:1293) (1367:1367:1367)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (215:215:215) (250:250:250)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1378:1378:1378) (1455:1455:1455)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1528:1528:1528) (1590:1590:1590)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -46491,23 +41668,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2978:2978:2978) (3192:3192:3192)) - (PORT d[1] (2894:2894:2894) (2985:2985:2985)) - (PORT d[2] (1003:1003:1003) (1051:1051:1051)) - (PORT d[3] (1298:1298:1298) (1337:1337:1337)) - (PORT d[4] (2072:2072:2072) (2172:2172:2172)) - (PORT d[5] (945:945:945) (991:991:991)) - (PORT d[6] (1183:1183:1183) (1217:1217:1217)) - (PORT d[7] (2655:2655:2655) (2814:2814:2814)) - (PORT d[8] (1565:1565:1565) (1650:1650:1650)) - (PORT d[9] (437:437:437) (473:473:473)) - (PORT d[10] (428:428:428) (460:460:460)) - (PORT d[11] (2780:2780:2780) (2977:2977:2977)) - (PORT d[12] (751:751:751) (792:792:792)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) + (PORT d[0] (2126:2126:2126) (2233:2233:2233)) + (PORT d[1] (1971:1971:1971) (2089:2089:2089)) + (PORT d[2] (3076:3076:3076) (3263:3263:3263)) + (PORT d[3] (2212:2212:2212) (2378:2378:2378)) + (PORT d[4] (4257:4257:4257) (4618:4618:4618)) + (PORT d[5] (3034:3034:3034) (3178:3178:3178)) + (PORT d[6] (2204:2204:2204) (2310:2310:2310)) + (PORT d[7] (2085:2085:2085) (2229:2229:2229)) + (PORT d[8] (2946:2946:2946) (3087:3087:3087)) + (PORT d[9] (3628:3628:3628) (3837:3837:3837)) + (PORT d[10] (1984:1984:1984) (2184:2184:2184)) + (PORT d[11] (2692:2692:2692) (2838:2838:2838)) + (PORT d[12] (1696:1696:1696) (1870:1870:1870)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -46516,11 +41693,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1248:1248:1248) (1217:1217:1217)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) + (PORT d[0] (1705:1705:1705) (1664:1664:1664)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -46529,60 +41706,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (1747:1747:1747) (1726:1726:1726)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) + (PORT d[0] (3157:3157:3157) (3128:3128:3128)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) + (PORT clk (1799:1799:1799) (1798:1798:1798)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46593,65 +41770,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (999:999:999)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1205:1205:1205) (1303:1303:1303)) - (PORT datad (1455:1455:1455) (1474:1474:1474)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1180:1180:1180)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (1020:1020:1020) (1063:1063:1063)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) ) ) (TIMINGCHECK @@ -46660,23 +41783,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3089:3089:3089) (3264:3264:3264)) - (PORT d[1] (2104:2104:2104) (2210:2210:2210)) - (PORT d[2] (1617:1617:1617) (1719:1719:1719)) - (PORT d[3] (1520:1520:1520) (1615:1615:1615)) - (PORT d[4] (2696:2696:2696) (2843:2843:2843)) - (PORT d[5] (1573:1573:1573) (1654:1654:1654)) - (PORT d[6] (1510:1510:1510) (1578:1578:1578)) - (PORT d[7] (1930:1930:1930) (1965:1965:1965)) - (PORT d[8] (3501:3501:3501) (3625:3625:3625)) - (PORT d[9] (1426:1426:1426) (1546:1546:1546)) - (PORT d[10] (1668:1668:1668) (1771:1771:1771)) - (PORT d[11] (1859:1859:1859) (1961:1961:1961)) - (PORT d[12] (1669:1669:1669) (1783:1783:1783)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) + (PORT d[0] (4176:4176:4176) (4333:4333:4333)) + (PORT d[1] (4220:4220:4220) (4394:4394:4394)) + (PORT d[2] (4160:4160:4160) (4244:4244:4244)) + (PORT d[3] (4208:4208:4208) (4285:4285:4285)) + (PORT d[4] (4178:4178:4178) (4279:4279:4279)) + (PORT d[5] (4295:4295:4295) (4600:4600:4600)) + (PORT d[6] (4240:4240:4240) (4537:4537:4537)) + (PORT d[7] (4386:4386:4386) (4494:4494:4494)) + (PORT d[8] (4221:4221:4221) (4224:4224:4224)) + (PORT d[9] (4068:4068:4068) (4043:4043:4043)) + (PORT d[10] (4099:4099:4099) (4152:4152:4152)) + (PORT d[11] (4177:4177:4177) (4257:4257:4257)) + (PORT d[12] (4299:4299:4299) (4300:4300:4300)) + (PORT clk (1805:1805:1805) (1800:1800:1800)) ) ) (TIMINGCHECK @@ -46685,174 +41808,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1494:1494:1494) (1487:1487:1487)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (2934:2934:2934) (2899:2899:2899)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1801:1801:1801)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1828:1828:1828) (1871:1871:1871)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4466:4466:4466) (4538:4538:4538)) - (PORT d[1] (4377:4377:4377) (4452:4452:4452)) - (PORT d[2] (4406:4406:4406) (4485:4485:4485)) - (PORT d[3] (4268:4268:4268) (4360:4360:4360)) - (PORT d[4] (4331:4331:4331) (4392:4392:4392)) - (PORT d[5] (4400:4400:4400) (4521:4521:4521)) - (PORT d[6] (4441:4441:4441) (4502:4502:4502)) - (PORT d[7] (4358:4358:4358) (4460:4460:4460)) - (PORT d[8] (4443:4443:4443) (4575:4575:4575)) - (PORT d[9] (4525:4525:4525) (4647:4647:4647)) - (PORT d[10] (4496:4496:4496) (4633:4633:4633)) - (PORT d[11] (4458:4458:4458) (4561:4561:4561)) - (PORT d[12] (4363:4363:4363) (4422:4422:4422)) - (PORT clk (1809:1809:1809) (1803:1803:1803)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1805:1805:1805) (1803:1803:1803)) + (PORT clk (1801:1801:1801) (1800:1800:1800)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46863,11 +41871,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1223:1223:1223) (1232:1232:1232)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (1545:1545:1545) (1645:1645:1645)) + (PORT d[1] (1786:1786:1786) (1811:1811:1811)) + (PORT d[2] (1230:1230:1230) (1281:1281:1281)) + (PORT d[3] (2804:2804:2804) (2976:2976:2976)) + (PORT d[4] (2236:2236:2236) (2386:2386:2386)) + (PORT d[5] (1237:1237:1237) (1272:1272:1272)) + (PORT d[6] (1249:1249:1249) (1285:1285:1285)) + (PORT d[7] (1536:1536:1536) (1606:1606:1606)) + (PORT d[8] (1693:1693:1693) (1749:1749:1749)) + (PORT d[9] (1786:1786:1786) (1851:1851:1851)) + (PORT d[10] (2465:2465:2465) (2631:2631:2631)) + (PORT d[11] (1962:1962:1962) (2053:2053:2053)) + (PORT d[12] (1678:1678:1678) (1832:1832:1832)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -46876,98 +41896,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (3089:3089:3089) (3264:3264:3264)) - (PORT d[1] (1541:1541:1541) (1607:1607:1607)) - (PORT d[2] (1629:1629:1629) (1719:1719:1719)) - (PORT d[3] (1525:1525:1525) (1604:1604:1604)) - (PORT d[4] (2654:2654:2654) (2816:2816:2816)) - (PORT d[5] (1569:1569:1569) (1645:1645:1645)) - (PORT d[6] (1544:1544:1544) (1658:1658:1658)) - (PORT d[7] (1663:1663:1663) (1702:1702:1702)) - (PORT d[8] (1535:1535:1535) (1635:1635:1635)) - (PORT d[9] (1398:1398:1398) (1514:1514:1514)) - (PORT d[10] (1375:1375:1375) (1487:1487:1487)) - (PORT d[11] (1846:1846:1846) (1959:1959:1959)) - (PORT d[12] (1391:1391:1391) (1504:1504:1504)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1426:1426:1426) (1391:1391:1391)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (2602:2602:2602) (2625:2625:2625)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1650:1650:1650) (1633:1633:1633)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) + (PORT clk (1810:1810:1810) (1837:1837:1837)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46978,108 +41930,441 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1838:1838:1838) (1888:1888:1888)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4461:4461:4461) (4563:4563:4563)) - (PORT d[1] (4338:4338:4338) (4416:4416:4416)) - (PORT d[2] (4451:4451:4451) (4534:4534:4534)) - (PORT d[3] (4291:4291:4291) (4385:4385:4385)) - (PORT d[4] (4329:4329:4329) (4390:4390:4390)) - (PORT d[5] (4364:4364:4364) (4463:4463:4463)) - (PORT d[6] (4404:4404:4404) (4467:4467:4467)) - (PORT d[7] (4337:4337:4337) (4441:4441:4441)) - (PORT d[8] (4412:4412:4412) (4536:4536:4536)) - (PORT d[9] (4443:4443:4443) (4552:4552:4552)) - (PORT d[10] (4533:4533:4533) (4643:4643:4643)) - (PORT d[11] (4480:4480:4480) (4587:4587:4587)) - (PORT d[12] (4342:4342:4342) (4404:4404:4404)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (995:995:995) (1000:1000:1000)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1746:1746:1746) (1820:1820:1820)) + (PORT datab (1485:1485:1485) (1584:1584:1584)) + (PORT datac (1215:1215:1215) (1256:1256:1256)) + (PORT datad (1519:1519:1519) (1587:1587:1587)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1267:1267:1267)) + (PORT datab (1002:1002:1002) (1030:1030:1030)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~12) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (412:412:412)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~14) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (2033:2033:2033) (2163:2163:2163)) + (PORT datac (1658:1658:1658) (1700:1700:1700)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (817:817:817)) + (PORT datab (922:922:922) (974:974:974)) + (PORT datac (1865:1865:1865) (1896:1896:1896)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (863:863:863)) + (PORT datab (1510:1510:1510) (1556:1556:1556)) + (PORT datac (1718:1718:1718) (1751:1751:1751)) + (PORT datad (221:221:221) (266:266:266)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (950:950:950)) + (PORT datab (941:941:941) (971:971:971)) + (PORT datac (1413:1413:1413) (1435:1435:1435)) + (PORT datad (185:185:185) (216:216:216)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (289:289:289)) + (PORT datab (810:810:810) (917:917:917)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (246:246:246) (291:291:291)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1537:1537:1537)) + (PORT ena (1830:1830:1830) (1880:1880:1880)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1124:1124:1124)) + (PORT datab (1097:1097:1097) (1224:1224:1224)) + (PORT datac (1683:1683:1683) (1781:1781:1781)) + (PORT datad (813:813:813) (831:831:831)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (800:800:800)) + (PORT datab (1895:1895:1895) (2026:2026:2026)) + (PORT datac (912:912:912) (969:969:969)) + (PORT datad (716:716:716) (798:798:798)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT datab (595:595:595) (607:607:607)) + (PORT datac (1169:1169:1169) (1195:1195:1195)) + (PORT datad (1205:1205:1205) (1277:1277:1277)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (2849:2849:2849) (2981:2981:2981)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (612:612:612) (667:667:667)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (417:417:417)) + (PORT datab (1372:1372:1372) (1537:1537:1537)) + (PORT datac (830:830:830) (908:908:908)) + (PORT datad (1751:1751:1751) (1871:1871:1871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (931:931:931)) + (PORT datab (676:676:676) (711:711:711)) + (PORT datac (594:594:594) (611:611:611)) + (PORT datad (220:220:220) (255:255:255)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1594:1594:1594) (1660:1660:1660)) + (PORT datab (1090:1090:1090) (1141:1141:1141)) + (PORT datac (1822:1822:1822) (1903:1903:1903)) + (PORT datad (1765:1765:1765) (1819:1819:1819)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1793:1793:1793)) + (PORT datab (634:634:634) (686:686:686)) + (PORT datac (551:551:551) (565:565:565)) + (PORT datad (1062:1062:1062) (1098:1098:1098)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (849:849:849)) + (PORT datab (612:612:612) (637:637:637)) + (PORT datad (804:804:804) (811:811:811)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (714:714:714)) + (PORT datab (587:587:587) (608:608:608)) + (PORT datac (627:627:627) (662:662:662)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (896:896:896)) + (PORT datab (631:631:631) (645:645:645)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (616:616:616) (633:633:633)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (909:909:909)) + (PORT datab (565:565:565) (580:580:580)) + (PORT datac (680:680:680) (739:739:739)) + (PORT datad (1158:1158:1158) (1169:1169:1169)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (907:907:907)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (619:619:619) (640:640:640)) + (PORT datad (530:530:530) (553:553:553)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2135:2135:2135) (2270:2270:2270)) - (PORT d[1] (2360:2360:2360) (2503:2503:2503)) - (PORT d[2] (2439:2439:2439) (2591:2591:2591)) - (PORT d[3] (2316:2316:2316) (2447:2447:2447)) - (PORT d[4] (2038:2038:2038) (2142:2142:2142)) - (PORT d[5] (2419:2419:2419) (2559:2559:2559)) - (PORT d[6] (2470:2470:2470) (2638:2638:2638)) - (PORT d[7] (2535:2535:2535) (2601:2601:2601)) - (PORT d[8] (2536:2536:2536) (2603:2603:2603)) - (PORT d[9] (2337:2337:2337) (2521:2521:2521)) - (PORT d[10] (3019:3019:3019) (3165:3165:3165)) - (PORT d[11] (2078:2078:2078) (2172:2172:2172)) - (PORT d[12] (2284:2284:2284) (2462:2462:2462)) + (PORT d[0] (2928:2928:2928) (3051:3051:3051)) + (PORT d[1] (2140:2140:2140) (2224:2224:2224)) + (PORT d[2] (2635:2635:2635) (2784:2784:2784)) + (PORT d[3] (2334:2334:2334) (2472:2472:2472)) + (PORT d[4] (3404:3404:3404) (3708:3708:3708)) + (PORT d[5] (2606:2606:2606) (2712:2712:2712)) + (PORT d[6] (2839:2839:2839) (2959:2959:2959)) + (PORT d[7] (2698:2698:2698) (2890:2890:2890)) + (PORT d[8] (2083:2083:2083) (2170:2170:2170)) + (PORT d[9] (2545:2545:2545) (2691:2691:2691)) + (PORT d[10] (1989:1989:1989) (2190:2190:2190)) + (PORT d[11] (2288:2288:2288) (2411:2411:2411)) + (PORT d[12] (1889:1889:1889) (2049:2049:2049)) (PORT clk (1860:1860:1860) (1886:1886:1886)) ) ) @@ -47093,7 +42378,7 @@ (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1886:1886:1886)) - (PORT d[0] (2624:2624:2624) (2721:2721:2721)) + (PORT d[0] (2803:2803:2803) (2873:2873:2873)) ) ) ) @@ -47160,18 +42445,203 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1289:1289:1289)) - (PORT datab (720:720:720) (782:782:782)) - (PORT datac (933:933:933) (942:942:942)) - (PORT datad (1202:1202:1202) (1232:1232:1232)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (1668:1668:1668) (1774:1774:1774)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3743:3743:3743) (3863:3863:3863)) + (PORT d[1] (4648:4648:4648) (4797:4797:4797)) + (PORT d[2] (3048:3048:3048) (3144:3144:3144)) + (PORT d[3] (2913:2913:2913) (3163:3163:3163)) + (PORT d[4] (3168:3168:3168) (3439:3439:3439)) + (PORT d[5] (2928:2928:2928) (3013:3013:3013)) + (PORT d[6] (3347:3347:3347) (3516:3516:3516)) + (PORT d[7] (3863:3863:3863) (4045:4045:4045)) + (PORT d[8] (2699:2699:2699) (2873:2873:2873)) + (PORT d[9] (3273:3273:3273) (3490:3490:3490)) + (PORT d[10] (2329:2329:2329) (2567:2567:2567)) + (PORT d[11] (2347:2347:2347) (2456:2456:2456)) + (PORT d[12] (2339:2339:2339) (2564:2564:2564)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2208:2208:2208) (2241:2241:2241)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (4733:4733:4733) (4815:4815:4815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1821:1821:1821)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1411:1411:1411) (1426:1426:1426)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4143:4143:4143) (4264:4264:4264)) + (PORT d[1] (4254:4254:4254) (4440:4440:4440)) + (PORT d[2] (4182:4182:4182) (4230:4230:4230)) + (PORT d[3] (4296:4296:4296) (4320:4320:4320)) + (PORT d[4] (4153:4153:4153) (4183:4183:4183)) + (PORT d[5] (4181:4181:4181) (4349:4349:4349)) + (PORT d[6] (4208:4208:4208) (4379:4379:4379)) + (PORT d[7] (4392:4392:4392) (4575:4575:4575)) + (PORT d[8] (4170:4170:4170) (4217:4217:4217)) + (PORT d[9] (4183:4183:4183) (4269:4269:4269)) + (PORT d[10] (4224:4224:4224) (4268:4268:4268)) + (PORT d[11] (4207:4207:4207) (4284:4284:4284)) + (PORT d[12] (4185:4185:4185) (4246:4246:4246)) + (PORT clk (1831:1831:1831) (1823:1823:1823)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -47180,20 +42650,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2194:2194:2194) (2311:2311:2311)) - (PORT d[1] (2390:2390:2390) (2538:2538:2538)) - (PORT d[2] (2577:2577:2577) (2693:2693:2693)) - (PORT d[3] (3028:3028:3028) (3132:3132:3132)) - (PORT d[4] (1942:1942:1942) (2079:2079:2079)) - (PORT d[5] (3464:3464:3464) (3577:3577:3577)) - (PORT d[6] (2798:2798:2798) (2911:2911:2911)) - (PORT d[7] (3363:3363:3363) (3428:3428:3428)) - (PORT d[8] (2099:2099:2099) (2185:2185:2185)) - (PORT d[9] (3054:3054:3054) (3173:3173:3173)) - (PORT d[10] (2331:2331:2331) (2396:2396:2396)) - (PORT d[11] (2463:2463:2463) (2612:2612:2612)) - (PORT d[12] (3239:3239:3239) (3438:3438:3438)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (3526:3526:3526) (3702:3702:3702)) + (PORT d[1] (3723:3723:3723) (3811:3811:3811)) + (PORT d[2] (3391:3391:3391) (3505:3505:3505)) + (PORT d[3] (3482:3482:3482) (3740:3740:3740)) + (PORT d[4] (2925:2925:2925) (3167:3167:3167)) + (PORT d[5] (2710:2710:2710) (2783:2783:2783)) + (PORT d[6] (3126:3126:3126) (3315:3315:3315)) + (PORT d[7] (4490:4490:4490) (4722:4722:4722)) + (PORT d[8] (3321:3321:3321) (3511:3511:3511)) + (PORT d[9] (3931:3931:3931) (4159:4159:4159)) + (PORT d[10] (3169:3169:3169) (3461:3461:3461)) + (PORT d[11] (2978:2978:2978) (3135:3135:3135)) + (PORT d[12] (2055:2055:2055) (2281:2281:2281)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -47205,8 +42675,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1867:1867:1867) (1892:1892:1892)) - (PORT d[0] (2930:2930:2930) (2859:2859:2859)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (4473:4473:4473) (4350:4350:4350)) ) ) ) @@ -47215,7 +42685,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1868:1868:1868) (1893:1893:1893)) + (PORT clk (1855:1855:1855) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -47225,7 +42695,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1855:1855:1855)) + (PORT clk (1817:1817:1817) (1843:1843:1843)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -47239,7 +42709,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1015:1015:1015) (1018:1018:1018)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) ) ) ) @@ -47248,7 +42718,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) ) ) ) @@ -47257,7 +42727,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -47267,21 +42737,881 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1445:1445:1445) (1458:1458:1458)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3743:3743:3743) (3863:3863:3863)) + (PORT d[1] (4063:4063:4063) (4190:4190:4190)) + (PORT d[2] (3094:3094:3094) (3192:3192:3192)) + (PORT d[3] (3181:3181:3181) (3412:3412:3412)) + (PORT d[4] (3436:3436:3436) (3712:3712:3712)) + (PORT d[5] (2996:2996:2996) (3096:3096:3096)) + (PORT d[6] (3077:3077:3077) (3232:3232:3232)) + (PORT d[7] (4336:4336:4336) (4534:4534:4534)) + (PORT d[8] (3029:3029:3029) (3202:3202:3202)) + (PORT d[9] (3296:3296:3296) (3516:3516:3516)) + (PORT d[10] (2722:2722:2722) (3000:3000:3000)) + (PORT d[11] (2389:2389:2389) (2522:2522:2522)) + (PORT d[12] (2439:2439:2439) (2617:2617:2617)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2176:2176:2176) (2135:2135:2135)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (5094:5094:5094) (4987:4987:4987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1816:1816:1816)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1409:1409:1409) (1410:1410:1410)) + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4195:4195:4195) (4268:4268:4268)) + (PORT d[1] (4263:4263:4263) (4441:4441:4441)) + (PORT d[2] (4112:4112:4112) (4211:4211:4211)) + (PORT d[3] (4063:4063:4063) (4075:4075:4075)) + (PORT d[4] (4290:4290:4290) (4278:4278:4278)) + (PORT d[5] (4244:4244:4244) (4463:4463:4463)) + (PORT d[6] (4324:4324:4324) (4514:4514:4514)) + (PORT d[7] (4280:4280:4280) (4458:4458:4458)) + (PORT d[8] (4149:4149:4149) (4199:4199:4199)) + (PORT d[9] (4196:4196:4196) (4270:4270:4270)) + (PORT d[10] (4089:4089:4089) (4135:4135:4135)) + (PORT d[11] (4266:4266:4266) (4308:4308:4308)) + (PORT d[12] (4166:4166:4166) (4210:4210:4210)) + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1818:1818:1818)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (921:921:921)) + (PORT datab (1614:1614:1614) (1683:1683:1683)) + (PORT datac (1157:1157:1157) (1175:1175:1175)) + (PORT datad (1209:1209:1209) (1289:1289:1289)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1238:1238:1238)) + (PORT datab (1017:1017:1017) (1095:1095:1095)) + (PORT datac (1567:1567:1567) (1600:1600:1600)) + (PORT datad (583:583:583) (610:610:610)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (976:976:976) (1010:1010:1010)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2460:2460:2460) (2587:2587:2587)) + (PORT d[1] (2223:2223:2223) (2350:2350:2350)) + (PORT d[2] (3373:3373:3373) (3562:3562:3562)) + (PORT d[3] (2175:2175:2175) (2319:2319:2319)) + (PORT d[4] (4262:4262:4262) (4627:4627:4627)) + (PORT d[5] (2100:2100:2100) (2195:2195:2195)) + (PORT d[6] (1913:1913:1913) (1999:1999:1999)) + (PORT d[7] (2048:2048:2048) (2168:2168:2168)) + (PORT d[8] (2936:2936:2936) (3093:3093:3093)) + (PORT d[9] (3642:3642:3642) (3872:3872:3872)) + (PORT d[10] (1991:1991:1991) (2193:2193:2193)) + (PORT d[11] (2379:2379:2379) (2477:2477:2477)) + (PORT d[12] (1728:1728:1728) (1910:1910:1910)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1455:1455:1455) (1431:1431:1431)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (2137:2137:2137) (2149:2149:2149)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1134:1134:1134) (1138:1138:1138)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3520:3520:3520) (3692:3692:3692)) + (PORT d[1] (3450:3450:3450) (3536:3536:3536)) + (PORT d[2] (3680:3680:3680) (3802:3802:3802)) + (PORT d[3] (3797:3797:3797) (4073:4073:4073)) + (PORT d[4] (2880:2880:2880) (3122:3122:3122)) + (PORT d[5] (2707:2707:2707) (2778:2778:2778)) + (PORT d[6] (3391:3391:3391) (3597:3597:3597)) + (PORT d[7] (4783:4783:4783) (5030:5030:5030)) + (PORT d[8] (3602:3602:3602) (3844:3844:3844)) + (PORT d[9] (3887:3887:3887) (4153:4153:4153)) + (PORT d[10] (3443:3443:3443) (3750:3750:3750)) + (PORT d[11] (2968:2968:2968) (3140:3140:3140)) + (PORT d[12] (2374:2374:2374) (2602:2602:2602)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1699:1699:1699) (1624:1624:1624)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2921:2921:2921) (2925:2925:2925)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1377:1377:1377) (1441:1441:1441)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (987:987:987) (1047:1047:1047)) + (PORT d[1] (2064:2064:2064) (2106:2106:2106)) + (PORT d[2] (1298:1298:1298) (1364:1364:1364)) + (PORT d[3] (3371:3371:3371) (3575:3575:3575)) + (PORT d[4] (2292:2292:2292) (2462:2462:2462)) + (PORT d[5] (974:974:974) (1033:1033:1033)) + (PORT d[6] (947:947:947) (1006:1006:1006)) + (PORT d[7] (1221:1221:1221) (1288:1288:1288)) + (PORT d[8] (1433:1433:1433) (1495:1495:1495)) + (PORT d[9] (1491:1491:1491) (1540:1540:1540)) + (PORT d[10] (2477:2477:2477) (2659:2659:2659)) + (PORT d[11] (2032:2032:2032) (2130:2130:2130)) + (PORT d[12] (1353:1353:1353) (1487:1487:1487)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1840:1840:1840) (1816:1816:1816)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2541:2541:2541) (2551:2551:2551)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1541:1541:1541) (1571:1571:1571)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2889:2889:2889) (2997:2997:2997)) + (PORT d[1] (2815:2815:2815) (2842:2842:2842)) + (PORT d[2] (2616:2616:2616) (2696:2696:2696)) + (PORT d[3] (868:868:868) (909:909:909)) + (PORT d[4] (2574:2574:2574) (2776:2776:2776)) + (PORT d[5] (3047:3047:3047) (3091:3091:3091)) + (PORT d[6] (3224:3224:3224) (3407:3407:3407)) + (PORT d[7] (1426:1426:1426) (1450:1450:1450)) + (PORT d[8] (1166:1166:1166) (1200:1200:1200)) + (PORT d[9] (971:971:971) (1015:1015:1015)) + (PORT d[10] (940:940:940) (998:998:998)) + (PORT d[11] (2860:2860:2860) (2986:2986:2986)) + (PORT d[12] (998:998:998) (1031:1031:1031)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2730:2730:2730) (2688:2688:2688)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2742:2742:2742) (2694:2694:2694)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~91) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) (DELAY (ABSOLUTE - (PORT dataa (897:897:897) (931:931:931)) - (PORT datab (1317:1317:1317) (1343:1343:1343)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (1569:1569:1569) (1584:1584:1584)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1611:1611:1611) (1693:1693:1693)) + (PORT datab (1406:1406:1406) (1506:1506:1506)) + (PORT datac (1205:1205:1205) (1260:1260:1260)) + (PORT datad (1417:1417:1417) (1454:1454:1454)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -47290,47 +43620,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~92) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) (DELAY (ABSOLUTE - (PORT dataa (975:975:975) (990:990:990)) - (PORT datab (721:721:721) (781:781:781)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1441:1441:1441) (1485:1485:1485)) + (PORT datab (1374:1374:1374) (1443:1443:1443)) + (PORT datac (2039:2039:2039) (2108:2108:2108)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~125) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (2570:2570:2570) (2815:2815:2815)) - (PORT datab (1396:1396:1396) (1468:1468:1468)) - (PORT datac (570:570:570) (585:585:585)) - (PORT datad (318:318:318) (337:337:337)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (976:976:976)) - (PORT datab (920:920:920) (940:940:940)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (632:632:632) (657:657:657)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (768:768:768) (853:853:853)) + (PORT datab (1174:1174:1174) (1239:1239:1239)) + (PORT datac (706:706:706) (772:772:772)) + (PORT datad (689:689:689) (755:755:755)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47338,29 +43652,2111 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~111) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~114) (DELAY (ABSOLUTE - (PORT dataa (2246:2246:2246) (2318:2318:2318)) - (PORT datab (436:436:436) (473:473:473)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1262:1262:1262) (1331:1331:1331)) + (PORT dataa (1137:1137:1137) (1156:1156:1156)) + (PORT datab (1472:1472:1472) (1540:1540:1540)) + (PORT datac (981:981:981) (1055:1055:1055)) + (PORT datad (1251:1251:1251) (1333:1333:1333)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (985:985:985)) + (PORT datab (768:768:768) (869:869:869)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (273:273:273) (358:358:358)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1797:1797:1797) (1916:1916:1916)) + (PORT datab (1194:1194:1194) (1255:1255:1255)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (643:643:643) (698:698:698)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (344:344:344)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (355:355:355)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (337:337:337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston_autofire_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (481:481:481) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (359:359:359)) + (PORT datac (233:233:233) (318:318:318)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (358:358:358)) + (PORT datab (261:261:261) (349:349:349)) + (PORT datac (340:340:340) (362:362:362)) + (PORT datad (392:392:392) (452:452:452)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (960:960:960)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (234:234:234) (318:318:318)) + (PORT datad (235:235:235) (314:314:314)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (262:262:262) (352:352:352)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (234:234:234) (312:312:312)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (494:494:494)) + (PORT datab (399:399:399) (465:465:465)) + (PORT datac (3381:3381:3381) (3693:3693:3693)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (341:341:341)) + (PORT datab (250:250:250) (335:335:335)) + (PORT datac (223:223:223) (301:301:301)) + (PORT datad (225:225:225) (297:297:297)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (792:792:792)) + (PORT datab (418:418:418) (487:487:487)) + (PORT datac (231:231:231) (318:318:318)) + (PORT datad (233:233:233) (310:310:310)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (354:354:354)) + (PORT datab (260:260:260) (348:348:348)) + (PORT datac (232:232:232) (315:315:315)) + (PORT datad (232:232:232) (308:308:308)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (357:357:357)) + (PORT datab (260:260:260) (347:347:347)) + (PORT datac (232:232:232) (315:315:315)) + (PORT datad (636:636:636) (689:689:689)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (581:581:581)) + (PORT datab (635:635:635) (654:654:654)) + (PORT datac (525:525:525) (535:535:535)) + (PORT datad (605:605:605) (621:621:621)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (664:664:664)) + (PORT datab (3428:3428:3428) (3730:3730:3730)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1733:1733:1733)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_autofire_enabled\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_autofire_enabled) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (809:809:809)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (517:517:517)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (251:251:251) (337:337:337)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (263:263:263) (346:346:346)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[6\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[7\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[8\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (350:350:350)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[9\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (334:334:334)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[10\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[11\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[12\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[13\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[14\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[15\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (468:468:468)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (393:393:393) (466:466:466)) + (PORT datac (224:224:224) (303:303:303)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (514:514:514)) + (PORT datab (254:254:254) (340:340:340)) + (PORT datac (226:226:226) (306:306:306)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (380:380:380) (441:441:441)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (226:226:226) (307:307:307)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (625:625:625) (639:639:639)) + (PORT datad (554:554:554) (566:566:566)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[16\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (339:339:339)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[17\]\~49) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (377:377:377)) + (PORT datab (254:254:254) (340:340:340)) + (PORT datad (226:226:226) (297:297:297)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT sload (1334:1334:1334) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (968:968:968)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1399:1399:1399) (1464:1464:1464)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (806:806:806)) + (PORT datab (929:929:929) (992:992:992)) + (PORT datac (947:947:947) (1006:1006:1006)) + (PORT datad (959:959:959) (1016:1016:1016)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (632:632:632)) + (PORT datab (761:761:761) (866:866:866)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (821:821:821)) + (PORT datab (904:904:904) (984:984:984)) + (PORT datac (713:713:713) (823:823:823)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (370:370:370)) + (PORT datab (694:694:694) (775:775:775)) + (PORT datac (932:932:932) (990:990:990)) + (PORT datad (361:361:361) (379:379:379)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1079:1079:1079)) + (PORT datab (762:762:762) (865:865:865)) + (PORT datad (604:604:604) (616:616:616)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (329:329:329)) + (PORT datab (2128:2128:2128) (2313:2313:2313)) + (PORT datac (2500:2500:2500) (2555:2555:2555)) + (PORT datad (217:217:217) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (856:856:856)) + (PORT datab (312:312:312) (410:410:410)) + (PORT datac (1479:1479:1479) (1523:1523:1523)) + (PORT datad (700:700:700) (762:762:762)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (889:889:889) (952:952:952)) + (PORT datad (736:736:736) (810:810:810)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (633:633:633)) + (PORT datab (632:632:632) (654:654:654)) + (PORT datad (978:978:978) (1057:1057:1057)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (822:822:822)) + (PORT datab (470:470:470) (544:544:544)) + (PORT datad (756:756:756) (855:855:855)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (962:962:962)) + (PORT datab (749:749:749) (825:825:825)) + (PORT datac (282:282:282) (375:375:375)) + (PORT datad (721:721:721) (811:811:811)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (425:425:425)) + (PORT datab (762:762:762) (839:839:839)) + (PORT datac (718:718:718) (801:801:801)) + (PORT datad (593:593:593) (606:606:606)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (728:728:728)) + (PORT datab (2339:2339:2339) (2440:2440:2440)) + (PORT datac (642:642:642) (700:700:700)) + (PORT datad (1959:1959:1959) (2162:2162:2162)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (396:396:396)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datad (247:247:247) (318:318:318)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (431:431:431)) + (PORT datab (885:885:885) (953:953:953)) + (PORT datac (395:395:395) (473:473:473)) + (PORT datad (758:758:758) (860:860:860)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT datab (723:723:723) (799:799:799)) + (PORT datad (690:690:690) (778:778:778)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (749:749:749)) + (PORT datac (706:706:706) (770:770:770)) + (PORT datad (959:959:959) (1016:1016:1016)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (653:653:653)) + (PORT datab (352:352:352) (386:386:386)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (908:908:908)) + (PORT datab (2246:2246:2246) (2362:2362:2362)) + (PORT datac (951:951:951) (1027:1027:1027)) + (PORT datad (1730:1730:1730) (1779:1779:1779)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (939:939:939)) + (PORT datab (843:843:843) (855:855:855)) + (PORT datac (822:822:822) (850:850:850)) + (PORT datad (598:598:598) (628:628:628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~6) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (651:651:651)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (876:876:876) (892:892:892)) + (PORT datad (1680:1680:1680) (1783:1783:1783)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~7) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (842:842:842) (848:848:848)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1506:1506:1506)) + (PORT datab (1115:1115:1115) (1223:1223:1223)) + (PORT datac (1237:1237:1237) (1260:1260:1260)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1678:1678:1678) (1784:1784:1784)) - (PORT datab (426:426:426) (465:465:465)) - (PORT datac (536:536:536) (545:545:545)) - (PORT datad (1131:1131:1131) (1161:1161:1161)) + (PORT dataa (1046:1046:1046) (1089:1089:1089)) + (PORT datab (255:255:255) (314:314:314)) + (PORT datac (1483:1483:1483) (1532:1532:1532)) + (PORT datad (897:897:897) (929:929:929)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -47373,197 +45769,7 @@ (INSTANCE z80_\|data_pins_\|dout\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (351:351:351)) - (PORT datab (420:420:420) (454:454:454)) - (PORT datad (386:386:386) (415:415:415)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1161:1161:1161)) - (PORT datab (335:335:335) (364:364:364)) - (PORT datac (525:525:525) (531:531:531)) - (PORT datad (218:218:218) (250:250:250)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (903:903:903) (914:914:914)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1940:1940:1940) (1962:1962:1962)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datac (1946:1946:1946) (2006:2006:2006)) - (PORT datad (2593:2593:2593) (2646:2646:2646)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (951:951:951)) - (PORT datab (684:684:684) (704:704:704)) - (PORT datac (2073:2073:2073) (2242:2242:2242)) - (PORT datad (1433:1433:1433) (1451:1451:1451)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datab (911:911:911) (925:925:925)) - (PORT datac (1751:1751:1751) (1844:1844:1844)) - (PORT datad (635:635:635) (684:684:684)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (699:699:699)) - (PORT datab (388:388:388) (432:432:432)) - (PORT datac (1409:1409:1409) (1477:1477:1477)) - (PORT datad (351:351:351) (382:382:382)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2309:2309:2309) (2429:2429:2429)) - (PORT datab (1622:1622:1622) (1658:1658:1658)) - (PORT datac (1347:1347:1347) (1529:1529:1529)) - (PORT datad (1271:1271:1271) (1279:1279:1279)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1203:1203:1203) (1245:1245:1245)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (PORT ena (993:993:993) (1000:1000:1000)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (746:746:746)) - (PORT datab (925:925:925) (959:959:959)) - (PORT datac (1056:1056:1056) (1099:1099:1099)) - (PORT datad (1179:1179:1179) (1228:1228:1228)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (868:868:868)) - (PORT datab (1152:1152:1152) (1165:1165:1165)) - (PORT datac (1037:1037:1037) (1033:1033:1033)) - (PORT datad (823:823:823) (844:844:844)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT clk (1520:1520:1520) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -47576,15 +45782,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[4\]\~17) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (648:648:648)) - (PORT datab (1173:1173:1173) (1220:1220:1220)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (590:590:590) (621:621:621)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (256:256:256) (316:316:316)) + (PORT datac (637:637:637) (696:696:696)) + (PORT datad (244:244:244) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (969:969:969)) + (PORT datab (669:669:669) (692:692:692)) + (PORT datac (1462:1462:1462) (1482:1482:1482)) + (PORT datad (779:779:779) (848:848:848)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (280:280:280) (344:344:344)) + (PORT datad (245:245:245) (284:284:284)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1733:1733:1733) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1242:1242:1242)) + (PORT datab (459:459:459) (534:534:534)) + (PORT datad (678:678:678) (732:732:732)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (859:859:859)) + (PORT datab (945:945:945) (968:968:968)) + (PORT datac (609:609:609) (673:673:673)) + (PORT datad (549:549:549) (564:564:564)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (952:952:952)) + (PORT datab (894:894:894) (916:916:916)) + (PORT datac (1119:1119:1119) (1127:1127:1127)) + (PORT datad (1137:1137:1137) (1155:1155:1155)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47592,13 +45888,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~16) + (INSTANCE z80_\|alu_control_\|db\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (843:843:843) (895:895:895)) - (PORT datab (619:619:619) (657:657:657)) - (PORT datac (1400:1400:1400) (1464:1464:1464)) - (PORT datad (616:616:616) (628:628:628)) + (PORT dataa (1162:1162:1162) (1267:1267:1267)) + (PORT datab (388:388:388) (407:407:407)) + (PORT datad (642:642:642) (687:687:687)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (389:389:389)) + (PORT datab (708:708:708) (741:741:741)) + (PORT datac (575:575:575) (607:607:607)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -47608,642 +45918,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (INSTANCE z80_\|alu_control_\|db\[1\]\~22) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datab (1116:1116:1116) (1138:1138:1138)) - (PORT datac (843:843:843) (863:863:863)) - (PORT datad (202:202:202) (229:229:229)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (572:572:572) (580:580:580)) + (PORT datad (216:216:216) (252:252:252)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1475:1475:1475) (1500:1500:1500)) - (PORT clk (1844:1844:1844) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3077:3077:3077) (3235:3235:3235)) - (PORT d[1] (1841:1841:1841) (1953:1953:1953)) - (PORT d[2] (1661:1661:1661) (1762:1762:1762)) - (PORT d[3] (2157:2157:2157) (2296:2296:2296)) - (PORT d[4] (2379:2379:2379) (2508:2508:2508)) - (PORT d[5] (2076:2076:2076) (2143:2143:2143)) - (PORT d[6] (1866:1866:1866) (1988:1988:1988)) - (PORT d[7] (1974:1974:1974) (2008:2008:2008)) - (PORT d[8] (3446:3446:3446) (3559:3559:3559)) - (PORT d[9] (1737:1737:1737) (1876:1876:1876)) - (PORT d[10] (3876:3876:3876) (4076:4076:4076)) - (PORT d[11] (2655:2655:2655) (2799:2799:2799)) - (PORT d[12] (2471:2471:2471) (2621:2621:2621)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2338:2338:2338) (2292:2292:2292)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (2885:2885:2885) (2929:2929:2929)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1799:1799:1799) (1798:1798:1798)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1821:1821:1821) (1865:1865:1865)) - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4361:4361:4361) (4440:4440:4440)) - (PORT d[1] (4289:4289:4289) (4412:4412:4412)) - (PORT d[2] (4396:4396:4396) (4476:4476:4476)) - (PORT d[3] (4255:4255:4255) (4328:4328:4328)) - (PORT d[4] (4433:4433:4433) (4506:4506:4506)) - (PORT d[5] (4377:4377:4377) (4495:4495:4495)) - (PORT d[6] (4340:4340:4340) (4393:4393:4393)) - (PORT d[7] (4339:4339:4339) (4447:4447:4447)) - (PORT d[8] (4420:4420:4420) (4484:4484:4484)) - (PORT d[9] (4471:4471:4471) (4559:4559:4559)) - (PORT d[10] (4423:4423:4423) (4538:4538:4538)) - (PORT d[11] (4470:4470:4470) (4589:4589:4589)) - (PORT d[12] (4307:4307:4307) (4348:4348:4348)) - (PORT clk (1805:1805:1805) (1800:1800:1800)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1663:1663:1663) (1779:1779:1779)) - (PORT d[1] (2732:2732:2732) (2838:2838:2838)) - (PORT d[2] (2573:2573:2573) (2708:2708:2708)) - (PORT d[3] (2470:2470:2470) (2584:2584:2584)) - (PORT d[4] (2444:2444:2444) (2531:2531:2531)) - (PORT d[5] (2902:2902:2902) (3012:3012:3012)) - (PORT d[6] (2795:2795:2795) (2926:2926:2926)) - (PORT d[7] (3199:3199:3199) (3295:3295:3295)) - (PORT d[8] (2328:2328:2328) (2401:2401:2401)) - (PORT d[9] (3071:3071:3071) (3209:3209:3209)) - (PORT d[10] (2336:2336:2336) (2406:2406:2406)) - (PORT d[11] (2497:2497:2497) (2660:2660:2660)) - (PORT d[12] (2947:2947:2947) (3126:3126:3126)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (2872:2872:2872) (2960:2960:2960)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1398:1398:1398) (1419:1419:1419)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1941:1941:1941) (2052:2052:2052)) - (PORT d[1] (3029:3029:3029) (3163:3163:3163)) - (PORT d[2] (1746:1746:1746) (1840:1840:1840)) - (PORT d[3] (3627:3627:3627) (3762:3762:3762)) - (PORT d[4] (2618:2618:2618) (2777:2777:2777)) - (PORT d[5] (4105:4105:4105) (4233:4233:4233)) - (PORT d[6] (2302:2302:2302) (2398:2398:2398)) - (PORT d[7] (3712:3712:3712) (3787:3787:3787)) - (PORT d[8] (1894:1894:1894) (1995:1995:1995)) - (PORT d[9] (2469:2469:2469) (2541:2541:2541)) - (PORT d[10] (2650:2650:2650) (2739:2739:2739)) - (PORT d[11] (2800:2800:2800) (3007:3007:3007)) - (PORT d[12] (4296:4296:4296) (4557:4557:4557)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3119:3119:3119) (3165:3165:3165)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (3232:3232:3232) (3186:3186:3186)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2181:2181:2181) (2164:2164:2164)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4392:4392:4392) (4469:4469:4469)) - (PORT d[1] (4472:4472:4472) (4532:4532:4532)) - (PORT d[2] (4387:4387:4387) (4471:4471:4471)) - (PORT d[3] (4388:4388:4388) (4400:4400:4400)) - (PORT d[4] (4258:4258:4258) (4352:4352:4352)) - (PORT d[5] (4349:4349:4349) (4405:4405:4405)) - (PORT d[6] (4400:4400:4400) (4441:4441:4441)) - (PORT d[7] (4176:4176:4176) (4227:4227:4227)) - (PORT d[8] (4465:4465:4465) (4525:4525:4525)) - (PORT d[9] (4604:4604:4604) (4650:4650:4650)) - (PORT d[10] (4270:4270:4270) (4329:4329:4329)) - (PORT d[11] (4396:4396:4396) (4516:4516:4516)) - (PORT d[12] (4242:4242:4242) (4248:4248:4248)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1707:1707:1707) (1838:1838:1838)) - (PORT d[1] (1389:1389:1389) (1409:1409:1409)) - (PORT d[2] (2239:2239:2239) (2416:2416:2416)) - (PORT d[3] (1717:1717:1717) (1771:1771:1771)) - (PORT d[4] (2431:2431:2431) (2579:2579:2579)) - (PORT d[5] (2815:2815:2815) (2865:2865:2865)) - (PORT d[6] (1980:1980:1980) (2073:2073:2073)) - (PORT d[7] (1698:1698:1698) (1754:1754:1754)) - (PORT d[8] (2198:2198:2198) (2300:2300:2300)) - (PORT d[9] (1738:1738:1738) (1793:1793:1793)) - (PORT d[10] (2522:2522:2522) (2606:2606:2606)) - (PORT d[11] (4027:4027:4027) (4320:4320:4320)) - (PORT d[12] (1372:1372:1372) (1411:1411:1411)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (2104:2104:2104) (2139:2139:2139)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) + (INSTANCE z80_\|bus_control_\|db\[1\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1290:1290:1290)) - (PORT datab (725:725:725) (787:787:787)) - (PORT datac (1356:1356:1356) (1394:1394:1394)) - (PORT datad (1654:1654:1654) (1694:1694:1694)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (869:869:869) (904:904:904)) + (PORT datac (360:360:360) (380:380:380)) + (PORT datad (1292:1292:1292) (1343:1343:1343)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48251,14 +45948,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1241:1241:1241)) - (PORT datab (720:720:720) (781:781:781)) - (PORT datac (1876:1876:1876) (1912:1912:1912)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (308:308:308)) + (PORT datab (469:469:469) (548:548:548)) + (PORT datac (719:719:719) (804:804:804)) + (PORT datad (696:696:696) (783:783:783)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -48266,11 +45961,574 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) (DELAY (ABSOLUTE - (PORT d[0] (1300:1300:1300) (1346:1346:1346)) + (PORT datab (770:770:770) (839:839:839)) + (PORT datac (853:853:853) (916:916:916)) + (PORT datad (723:723:723) (794:794:794)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (933:933:933)) + (PORT datab (1009:1009:1009) (1072:1072:1072)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (752:752:752)) + (PORT datab (2131:2131:2131) (2314:2314:2314)) + (PORT datac (2499:2499:2499) (2554:2554:2554)) + (PORT datad (616:616:616) (672:672:672)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (691:691:691)) + (PORT datab (766:766:766) (873:873:873)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1102:1102:1102)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datad (977:977:977) (1058:1058:1058)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2202:2202:2202) (2392:2392:2392)) + (PORT datab (386:386:386) (455:455:455)) + (PORT datac (2243:2243:2243) (2324:2324:2324)) + (PORT datad (382:382:382) (441:441:441)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1722:1722:1722) (1783:1783:1783)) + (PORT datab (688:688:688) (764:764:764)) + (PORT datac (268:268:268) (367:367:367)) + (PORT datad (253:253:253) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1048:1048:1048)) + (PORT datab (738:738:738) (822:822:822)) + (PORT datac (969:969:969) (1032:1032:1032)) + (PORT datad (946:946:946) (1024:1024:1024)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1056:1056:1056)) + (PORT datac (965:965:965) (1025:1025:1025)) + (PORT datad (706:706:706) (791:791:791)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (691:691:691) (776:776:776)) + (PORT datac (940:940:940) (1005:1005:1005)) + (PORT datad (205:205:205) (234:234:234)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (851:851:851)) + (PORT datab (751:751:751) (828:828:828)) + (PORT datac (282:282:282) (373:373:373)) + (PORT datad (420:420:420) (491:491:491)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (862:862:862)) + (PORT datab (885:885:885) (948:948:948)) + (PORT datac (792:792:792) (790:790:790)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (628:628:628)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (692:692:692) (775:775:775)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (765:765:765) (866:866:866)) + (PORT datac (668:668:668) (735:735:735)) + (PORT datad (1475:1475:1475) (1505:1505:1505)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (858:858:858)) + (PORT datab (741:741:741) (819:819:819)) + (PORT datac (857:857:857) (917:917:917)) + (PORT datad (414:414:414) (484:484:484)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (284:284:284) (378:378:378)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datad (334:334:334) (354:354:354)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1916:1916:1916)) + (PORT datab (411:411:411) (470:470:470)) + (PORT datac (1165:1165:1165) (1222:1222:1222)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (826:826:826)) + (PORT datac (254:254:254) (337:337:337)) + (PORT datad (919:919:919) (963:963:963)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (818:818:818)) + (PORT datab (731:731:731) (803:803:803)) + (PORT datac (254:254:254) (340:340:340)) + (PORT datad (725:725:725) (803:803:803)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (817:817:817)) + (PORT datab (435:435:435) (518:518:518)) + (PORT datac (1144:1144:1144) (1207:1207:1207)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (599:599:599) (614:614:614)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (633:633:633)) + (PORT datab (1014:1014:1014) (1085:1085:1085)) + (PORT datac (913:913:913) (951:951:951)) + (PORT datad (1438:1438:1438) (1505:1505:1505)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (766:766:766) (867:867:867)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4440:4440:4440) (4673:4673:4673)) + (PORT datab (3252:3252:3252) (3396:3396:3396)) + (PORT datac (637:637:637) (693:693:693)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~4) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (959:959:959)) + (PORT datab (843:843:843) (855:855:855)) + (PORT datac (873:873:873) (888:888:888)) + (PORT datad (1446:1446:1446) (1553:1553:1553)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (677:677:677) (704:704:704)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -48280,22 +46538,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2285:2285:2285) (2467:2467:2467)) - (PORT d[1] (2246:2246:2246) (2325:2325:2325)) - (PORT d[2] (1845:1845:1845) (1951:1951:1951)) - (PORT d[3] (2514:2514:2514) (2600:2600:2600)) - (PORT d[4] (2048:2048:2048) (2130:2130:2130)) - (PORT d[5] (1563:1563:1563) (1637:1637:1637)) - (PORT d[6] (1751:1751:1751) (1801:1801:1801)) - (PORT d[7] (2365:2365:2365) (2488:2488:2488)) - (PORT d[8] (2486:2486:2486) (2660:2660:2660)) - (PORT d[9] (1246:1246:1246) (1313:1313:1313)) - (PORT d[10] (1642:1642:1642) (1713:1713:1713)) - (PORT d[11] (1161:1161:1161) (1207:1207:1207)) - (PORT d[12] (1023:1023:1023) (1096:1096:1096)) + (PORT d[0] (2458:2458:2458) (2557:2557:2557)) + (PORT d[1] (1958:1958:1958) (2061:2061:2061)) + (PORT d[2] (3366:3366:3366) (3573:3573:3573)) + (PORT d[3] (1894:1894:1894) (2029:2029:2029)) + (PORT d[4] (1845:1845:1845) (1948:1948:1948)) + (PORT d[5] (2068:2068:2068) (2145:2145:2145)) + (PORT d[6] (1574:1574:1574) (1661:1661:1661)) + (PORT d[7] (1773:1773:1773) (1887:1887:1887)) + (PORT d[8] (3238:3238:3238) (3414:3414:3414)) + (PORT d[9] (3979:3979:3979) (4211:4211:4211)) + (PORT d[10] (2006:2006:2006) (2191:2191:2191)) + (PORT d[11] (2430:2430:2430) (2532:2532:2532)) + (PORT d[12] (1718:1718:1718) (1898:1898:1898)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48305,10 +46563,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1539:1539:1539) (1561:1561:1561)) + (PORT d[0] (1201:1201:1201) (1158:1158:1158)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48318,17 +46576,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2040:2040:2040) (2017:2017:2017)) + (PORT d[0] (1820:1820:1820) (1837:1837:1837)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48338,7 +46596,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48348,7 +46606,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48358,7 +46616,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48368,7 +46626,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -48382,7 +46640,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -48391,7 +46649,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -48400,7 +46658,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -48408,12 +46666,4370 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~10) + (DELAY + (ABSOLUTE + (PORT datab (666:666:666) (682:682:682)) + (PORT datac (1125:1125:1125) (1218:1218:1218)) + (PORT datad (1481:1481:1481) (1599:1599:1599)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (861:861:861) (872:872:872)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3511:3511:3511) (3670:3670:3670)) + (PORT d[1] (3445:3445:3445) (3524:3524:3524)) + (PORT d[2] (3677:3677:3677) (3821:3821:3821)) + (PORT d[3] (3801:3801:3801) (4081:4081:4081)) + (PORT d[4] (3186:3186:3186) (3455:3455:3455)) + (PORT d[5] (2694:2694:2694) (2781:2781:2781)) + (PORT d[6] (3419:3419:3419) (3629:3629:3629)) + (PORT d[7] (4759:4759:4759) (5005:5005:5005)) + (PORT d[8] (3618:3618:3618) (3834:3834:3834)) + (PORT d[9] (3888:3888:3888) (4154:4154:4154)) + (PORT d[10] (3471:3471:3471) (3786:3786:3786)) + (PORT d[11] (3244:3244:3244) (3411:3411:3411)) + (PORT d[12] (2341:2341:2341) (2585:2585:2585)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2593:2593:2593) (2578:2578:2578)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2250:2250:2250) (2222:2222:2222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1004:1004:1004) (1027:1027:1027)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2471:2471:2471) (2583:2583:2583)) + (PORT d[1] (1937:1937:1937) (2036:2036:2036)) + (PORT d[2] (3360:3360:3360) (3561:3561:3561)) + (PORT d[3] (1923:1923:1923) (2069:2069:2069)) + (PORT d[4] (1899:1899:1899) (2021:2021:2021)) + (PORT d[5] (1788:1788:1788) (1856:1856:1856)) + (PORT d[6] (2543:2543:2543) (2649:2649:2649)) + (PORT d[7] (1801:1801:1801) (1922:1922:1922)) + (PORT d[8] (2936:2936:2936) (3094:3094:3094)) + (PORT d[9] (3643:3643:3643) (3873:3873:3873)) + (PORT d[10] (2007:2007:2007) (2192:2192:2192)) + (PORT d[11] (2366:2366:2366) (2481:2481:2481)) + (PORT d[12] (1687:1687:1687) (1860:1860:1860)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1227:1227:1227) (1194:1194:1194)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (1757:1757:1757) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2705:2705:2705) (2831:2831:2831)) + (PORT d[1] (2202:2202:2202) (2290:2290:2290)) + (PORT d[2] (2631:2631:2631) (2767:2767:2767)) + (PORT d[3] (2831:2831:2831) (2959:2959:2959)) + (PORT d[4] (3671:3671:3671) (3974:3974:3974)) + (PORT d[5] (2942:2942:2942) (3056:3056:3056)) + (PORT d[6] (2838:2838:2838) (2958:2958:2958)) + (PORT d[7] (2670:2670:2670) (2857:2857:2857)) + (PORT d[8] (2318:2318:2318) (2411:2411:2411)) + (PORT d[9] (2646:2646:2646) (2838:2838:2838)) + (PORT d[10] (2010:2010:2010) (2196:2196:2196)) + (PORT d[11] (2355:2355:2355) (2461:2461:2461)) + (PORT d[12] (1976:1976:1976) (2153:2153:2153)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (2871:2871:2871) (2802:2802:2802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1421:1421:1421) (1457:1457:1457)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2903:2903:2903) (3028:3028:3028)) + (PORT d[1] (2801:2801:2801) (2834:2834:2834)) + (PORT d[2] (2607:2607:2607) (2703:2703:2703)) + (PORT d[3] (1723:1723:1723) (1798:1798:1798)) + (PORT d[4] (3230:3230:3230) (3519:3519:3519)) + (PORT d[5] (3059:3059:3059) (3120:3120:3120)) + (PORT d[6] (4018:4018:4018) (4276:4276:4276)) + (PORT d[7] (1465:1465:1465) (1474:1474:1474)) + (PORT d[8] (1126:1126:1126) (1158:1158:1158)) + (PORT d[9] (4517:4517:4517) (4792:4792:4792)) + (PORT d[10] (4152:4152:4152) (4478:4478:4478)) + (PORT d[11] (3591:3591:3591) (3808:3808:3808)) + (PORT d[12] (938:938:938) (950:950:950)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3058:3058:3058) (3012:3012:3012)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2996:2996:2996) (2964:2964:2964)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~7) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1073:1073:1073)) + (PORT datab (1208:1208:1208) (1277:1277:1277)) + (PORT datac (1380:1380:1380) (1421:1421:1421)) + (PORT datad (391:391:391) (414:414:414)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1304:1304:1304)) + (PORT datac (1704:1704:1704) (1794:1794:1794)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2064:2064:2064) (2151:2151:2151)) + (PORT datab (1553:1553:1553) (1601:1601:1601)) + (PORT datac (2069:2069:2069) (2116:2116:2116)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1284:1284:1284) (1308:1308:1308)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2138:2138:2138) (2231:2231:2231)) + (PORT d[1] (1634:1634:1634) (1729:1729:1729)) + (PORT d[2] (3077:3077:3077) (3264:3264:3264)) + (PORT d[3] (2207:2207:2207) (2366:2366:2366)) + (PORT d[4] (4261:4261:4261) (4626:4626:4626)) + (PORT d[5] (3331:3331:3331) (3477:3477:3477)) + (PORT d[6] (2504:2504:2504) (2621:2621:2621)) + (PORT d[7] (2083:2083:2083) (2221:2221:2221)) + (PORT d[8] (2082:2082:2082) (2181:2181:2181)) + (PORT d[9] (3636:3636:3636) (3859:3859:3859)) + (PORT d[10] (1995:1995:1995) (2200:2200:2200)) + (PORT d[11] (2035:2035:2035) (2124:2124:2124)) + (PORT d[12] (1700:1700:1700) (1877:1877:1877)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1726:1726:1726) (1682:1682:1682)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (3147:3147:3147) (3124:3124:3124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1289:1289:1289) (1329:1329:1329)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4098:4098:4098) (4215:4215:4215)) + (PORT d[1] (4338:4338:4338) (4406:4406:4406)) + (PORT d[2] (4186:4186:4186) (4325:4325:4325)) + (PORT d[3] (4270:4270:4270) (4352:4352:4352)) + (PORT d[4] (4260:4260:4260) (4352:4352:4352)) + (PORT d[5] (4164:4164:4164) (4287:4287:4287)) + (PORT d[6] (4217:4217:4217) (4512:4512:4512)) + (PORT d[7] (4199:4199:4199) (4363:4363:4363)) + (PORT d[8] (4254:4254:4254) (4239:4239:4239)) + (PORT d[9] (4195:4195:4195) (4264:4264:4264)) + (PORT d[10] (4071:4071:4071) (4136:4136:4136)) + (PORT d[11] (4195:4195:4195) (4246:4246:4246)) + (PORT d[12] (4407:4407:4407) (4410:4410:4410)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1546:1546:1546)) + (PORT datab (2773:2773:2773) (2863:2863:2863)) + (PORT datac (889:889:889) (934:934:934)) + (PORT datad (1420:1420:1420) (1458:1458:1458)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2144:2144:2144)) + (PORT datab (1015:1015:1015) (1092:1092:1092)) + (PORT datac (224:224:224) (261:261:261)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1355:1355:1355) (1384:1384:1384)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3818:3818:3818) (4013:4013:4013)) + (PORT d[1] (4013:4013:4013) (4117:4117:4117)) + (PORT d[2] (3095:3095:3095) (3188:3188:3188)) + (PORT d[3] (3467:3467:3467) (3706:3706:3706)) + (PORT d[4] (3479:3479:3479) (3765:3765:3765)) + (PORT d[5] (2966:2966:2966) (3051:3051:3051)) + (PORT d[6] (3110:3110:3110) (3279:3279:3279)) + (PORT d[7] (4449:4449:4449) (4657:4657:4657)) + (PORT d[8] (2994:2994:2994) (3190:3190:3190)) + (PORT d[9] (3588:3588:3588) (3826:3826:3826)) + (PORT d[10] (3131:3131:3131) (3402:3402:3402)) + (PORT d[11] (2682:2682:2682) (2831:2831:2831)) + (PORT d[12] (2042:2042:2042) (2248:2248:2248)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2433:2433:2433) (2433:2433:2433)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (5248:5248:5248) (5352:5352:5352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1345:1345:1345) (1361:1361:1361)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4069:4069:4069) (4188:4188:4188)) + (PORT d[1] (4265:4265:4265) (4439:4439:4439)) + (PORT d[2] (4272:4272:4272) (4320:4320:4320)) + (PORT d[3] (4173:4173:4173) (4261:4261:4261)) + (PORT d[4] (4121:4121:4121) (4157:4157:4157)) + (PORT d[5] (4220:4220:4220) (4418:4418:4418)) + (PORT d[6] (4351:4351:4351) (4541:4541:4541)) + (PORT d[7] (4275:4275:4275) (4450:4450:4450)) + (PORT d[8] (4139:4139:4139) (4184:4184:4184)) + (PORT d[9] (4196:4196:4196) (4266:4266:4266)) + (PORT d[10] (4110:4110:4110) (4149:4149:4149)) + (PORT d[11] (4256:4256:4256) (4319:4319:4319)) + (PORT d[12] (4198:4198:4198) (4259:4259:4259)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3404:3404:3404) (3510:3510:3510)) + (PORT d[1] (4370:4370:4370) (4521:4521:4521)) + (PORT d[2] (2784:2784:2784) (2905:2905:2905)) + (PORT d[3] (2884:2884:2884) (3104:3104:3104)) + (PORT d[4] (2917:2917:2917) (3169:3169:3169)) + (PORT d[5] (2688:2688:2688) (2776:2776:2776)) + (PORT d[6] (3341:3341:3341) (3499:3499:3499)) + (PORT d[7] (3842:3842:3842) (4026:4026:4026)) + (PORT d[8] (2685:2685:2685) (2840:2840:2840)) + (PORT d[9] (3004:3004:3004) (3239:3239:3239)) + (PORT d[10] (2578:2578:2578) (2817:2817:2817)) + (PORT d[11] (2352:2352:2352) (2471:2471:2471)) + (PORT d[12] (2358:2358:2358) (2582:2582:2582)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (3766:3766:3766) (3836:3836:3836)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1541:1541:1541)) + (PORT datab (2774:2774:2774) (2866:2866:2866)) + (PORT datac (1380:1380:1380) (1406:1406:1406)) + (PORT datad (1683:1683:1683) (1769:1769:1769)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1560:1560:1560)) + (PORT datab (249:249:249) (291:291:291)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~11) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (462:462:462)) + (PORT datab (857:857:857) (864:864:864)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (340:340:340) (361:361:361)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (699:699:699)) + (PORT datab (1072:1072:1072) (1201:1201:1201)) + (PORT datac (1459:1459:1459) (1515:1515:1515)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (938:938:938)) + (PORT datab (1514:1514:1514) (1568:1568:1568)) + (PORT datac (1252:1252:1252) (1302:1302:1302)) + (PORT datad (225:225:225) (271:271:271)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (858:858:858) (917:917:917)) + (PORT datac (595:595:595) (604:604:604)) + (PORT datad (827:827:827) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1173:1173:1173) (1169:1169:1169)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1989:1989:1989) (1994:1994:1994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1594:1594:1594) (1734:1734:1734)) + (PORT datad (957:957:957) (1055:1055:1055)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (866:866:866)) + (PORT datab (906:906:906) (956:956:956)) + (PORT datac (1212:1212:1212) (1292:1292:1292)) + (PORT datad (628:628:628) (640:640:640)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1958:1958:1958)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (366:366:366) (430:430:430)) + (PORT datad (1871:1871:1871) (1981:1981:1981)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1124:1124:1124) (1182:1182:1182)) + (PORT datac (225:225:225) (306:306:306)) + (PORT datad (1178:1178:1178) (1240:1240:1240)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (361:361:361)) + (PORT datac (2095:2095:2095) (2215:2215:2215)) + (PORT datad (246:246:246) (318:318:318)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1198:1198:1198) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (2679:2679:2679) (2836:2836:2836)) + (PORT datab (1206:1206:1206) (1305:1305:1305)) + (PORT datac (1433:1433:1433) (1492:1492:1492)) + (PORT datad (875:875:875) (931:931:931)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1928:1928:1928) (1927:1927:1927)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (289:289:289)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1261:1261:1261)) + (PORT datab (664:664:664) (727:727:727)) + (PORT datac (1422:1422:1422) (1476:1476:1476)) + (PORT datad (236:236:236) (305:305:305)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (698:698:698)) + (PORT datab (863:863:863) (905:905:905)) + (PORT datac (635:635:635) (653:653:653)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (689:689:689)) + (PORT datab (651:651:651) (706:706:706)) + (PORT datac (933:933:933) (994:994:994)) + (PORT datad (1500:1500:1500) (1593:1593:1593)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1547:1547:1547)) + (PORT datab (275:275:275) (360:360:360)) + (PORT datac (1494:1494:1494) (1590:1590:1590)) + (PORT datad (245:245:245) (317:317:317)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (337:337:337)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1086:1086:1086)) + (PORT datac (1226:1226:1226) (1297:1297:1297)) + (PORT datad (375:375:375) (440:440:440)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1743:1743:1743)) + (PORT datac (1545:1545:1545) (1649:1649:1649)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1017:1017:1017)) + (PORT datab (604:604:604) (622:622:622)) + (PORT datac (1087:1087:1087) (1142:1142:1142)) + (PORT datad (1794:1794:1794) (1830:1830:1830)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (947:947:947)) + (PORT datab (1730:1730:1730) (1782:1782:1782)) + (PORT datac (939:939:939) (1007:1007:1007)) + (PORT datad (2115:2115:2115) (2235:2235:2235)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3460:3460:3460) (3588:3588:3588)) + (PORT d[1] (4366:4366:4366) (4514:4514:4514)) + (PORT d[2] (3311:3311:3311) (3436:3436:3436)) + (PORT d[3] (2638:2638:2638) (2853:2853:2853)) + (PORT d[4] (3137:3137:3137) (3393:3393:3393)) + (PORT d[5] (2802:2802:2802) (3001:3001:3001)) + (PORT d[6] (3092:3092:3092) (3256:3256:3256)) + (PORT d[7] (3879:3879:3879) (4087:4087:4087)) + (PORT d[8] (2689:2689:2689) (2854:2854:2854)) + (PORT d[9] (2982:2982:2982) (3198:3198:3198)) + (PORT d[10] (2565:2565:2565) (2795:2795:2795)) + (PORT d[11] (2321:2321:2321) (2418:2418:2418)) + (PORT d[12] (2348:2348:2348) (2591:2591:2591)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (3820:3820:3820) (3903:3903:3903)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1716:1716:1716) (1858:1858:1858)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3764:3764:3764) (3880:3880:3880)) + (PORT d[1] (4068:4068:4068) (4202:4202:4202)) + (PORT d[2] (2527:2527:2527) (2629:2629:2629)) + (PORT d[3] (3190:3190:3190) (3442:3442:3442)) + (PORT d[4] (3176:3176:3176) (3453:3453:3453)) + (PORT d[5] (2767:2767:2767) (2939:2939:2939)) + (PORT d[6] (3090:3090:3090) (3249:3249:3249)) + (PORT d[7] (4148:4148:4148) (4335:4335:4335)) + (PORT d[8] (3013:3013:3013) (3204:3204:3204)) + (PORT d[9] (3318:3318:3318) (3539:3539:3539)) + (PORT d[10] (2830:2830:2830) (3053:3053:3053)) + (PORT d[11] (2361:2361:2361) (2489:2489:2489)) + (PORT d[12] (2060:2060:2060) (2285:2285:2285)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2233:2233:2233) (2243:2243:2243)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (5014:5014:5014) (5095:5095:5095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1818:1818:1818)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1413:1413:1413) (1450:1450:1450)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4203:4203:4203) (4260:4260:4260)) + (PORT d[1] (4234:4234:4234) (4421:4421:4421)) + (PORT d[2] (4145:4145:4145) (4224:4224:4224)) + (PORT d[3] (4111:4111:4111) (4152:4152:4152)) + (PORT d[4] (4110:4110:4110) (4169:4169:4169)) + (PORT d[5] (4123:4123:4123) (4293:4293:4293)) + (PORT d[6] (4320:4320:4320) (4509:4509:4509)) + (PORT d[7] (4381:4381:4381) (4548:4548:4548)) + (PORT d[8] (4158:4158:4158) (4225:4225:4225)) + (PORT d[9] (4179:4179:4179) (4240:4240:4240)) + (PORT d[10] (4143:4143:4143) (4164:4164:4164)) + (PORT d[11] (4193:4193:4193) (4268:4268:4268)) + (PORT d[12] (4177:4177:4177) (4218:4218:4218)) + (PORT clk (1827:1827:1827) (1820:1820:1820)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1351:1351:1351) (1423:1423:1423)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3001:3001:3001) (3112:3112:3112)) + (PORT d[1] (1651:1651:1651) (1739:1739:1739)) + (PORT d[2] (2765:2765:2765) (2929:2929:2929)) + (PORT d[3] (2561:2561:2561) (2726:2726:2726)) + (PORT d[4] (3970:3970:3970) (4308:4308:4308)) + (PORT d[5] (2701:2701:2701) (2838:2838:2838)) + (PORT d[6] (2478:2478:2478) (2586:2586:2586)) + (PORT d[7] (2375:2375:2375) (2540:2540:2540)) + (PORT d[8] (2645:2645:2645) (2764:2764:2764)) + (PORT d[9] (2987:2987:2987) (3185:3185:3185)) + (PORT d[10] (2266:2266:2266) (2488:2488:2488)) + (PORT d[11] (2394:2394:2394) (2524:2524:2524)) + (PORT d[12] (1694:1694:1694) (1868:1868:1868)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2002:2002:2002) (1984:1984:1984)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3480:3480:3480) (3429:3429:3429)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1532:1532:1532) (1553:1553:1553)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4123:4123:4123) (4259:4259:4259)) + (PORT d[1] (4256:4256:4256) (4444:4444:4444)) + (PORT d[2] (4277:4277:4277) (4388:4388:4388)) + (PORT d[3] (4272:4272:4272) (4370:4370:4370)) + (PORT d[4] (4303:4303:4303) (4399:4399:4399)) + (PORT d[5] (4293:4293:4293) (4624:4624:4624)) + (PORT d[6] (4419:4419:4419) (4552:4552:4552)) + (PORT d[7] (4289:4289:4289) (4385:4385:4385)) + (PORT d[8] (4224:4224:4224) (4226:4226:4226)) + (PORT d[9] (4157:4157:4157) (4228:4228:4228)) + (PORT d[10] (4086:4086:4086) (4127:4127:4127)) + (PORT d[11] (4174:4174:4174) (4248:4248:4248)) + (PORT d[12] (4319:4319:4319) (4300:4300:4300)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2291:2291:2291) (2367:2367:2367)) + (PORT d[1] (2181:2181:2181) (2208:2208:2208)) + (PORT d[2] (1998:1998:1998) (2045:2045:2045)) + (PORT d[3] (1176:1176:1176) (1217:1217:1217)) + (PORT d[4] (2537:2537:2537) (2694:2694:2694)) + (PORT d[5] (2470:2470:2470) (2511:2511:2511)) + (PORT d[6] (3733:3733:3733) (3943:3943:3943)) + (PORT d[7] (1763:1763:1763) (1767:1767:1767)) + (PORT d[8] (1032:1032:1032) (1060:1060:1060)) + (PORT d[9] (952:952:952) (1010:1010:1010)) + (PORT d[10] (1804:1804:1804) (1872:1872:1872)) + (PORT d[11] (2242:2242:2242) (2320:2320:2320)) + (PORT d[12] (1528:1528:1528) (1601:1601:1601)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1740:1740:1740) (1700:1700:1700)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1264:1264:1264)) + (PORT datab (1231:1231:1231) (1269:1269:1269)) + (PORT datac (639:639:639) (718:718:718)) + (PORT datad (1704:1704:1704) (1749:1749:1749)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1569:1569:1569)) + (PORT datab (466:466:466) (539:539:539)) + (PORT datac (1718:1718:1718) (1842:1842:1842)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1340:1340:1340) (1411:1411:1411)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (993:993:993) (1059:1059:1059)) + (PORT d[1] (1784:1784:1784) (1818:1818:1818)) + (PORT d[2] (992:992:992) (1049:1049:1049)) + (PORT d[3] (2787:2787:2787) (2975:2975:2975)) + (PORT d[4] (2496:2496:2496) (2636:2636:2636)) + (PORT d[5] (960:960:960) (997:997:997)) + (PORT d[6] (1223:1223:1223) (1258:1258:1258)) + (PORT d[7] (1502:1502:1502) (1586:1586:1586)) + (PORT d[8] (1685:1685:1685) (1740:1740:1740)) + (PORT d[9] (1810:1810:1810) (1877:1877:1877)) + (PORT d[10] (2473:2473:2473) (2652:2652:2652)) + (PORT d[11] (1231:1231:1231) (1318:1318:1318)) + (PORT d[12] (1679:1679:1679) (1833:1833:1833)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2304:2304:2304) (2324:2324:2324)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2425:2425:2425) (2443:2443:2443)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1624:1624:1624) (1726:1726:1726)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2586:2586:2586) (2671:2671:2671)) + (PORT d[1] (2494:2494:2494) (2520:2520:2520)) + (PORT d[2] (2307:2307:2307) (2364:2364:2364)) + (PORT d[3] (901:901:901) (949:949:949)) + (PORT d[4] (2594:2594:2594) (2821:2821:2821)) + (PORT d[5] (2748:2748:2748) (2771:2771:2771)) + (PORT d[6] (4022:4022:4022) (4207:4207:4207)) + (PORT d[7] (1426:1426:1426) (1450:1450:1450)) + (PORT d[8] (959:959:959) (978:978:978)) + (PORT d[9] (1497:1497:1497) (1566:1566:1566)) + (PORT d[10] (2086:2086:2086) (2151:2151:2151)) + (PORT d[11] (2583:2583:2583) (2709:2709:2709)) + (PORT d[12] (1295:1295:1295) (1355:1355:1355)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2455:2455:2455) (2393:2393:2393)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (3001:3001:3001) (2952:2952:2952)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1014:1014:1014) (1051:1051:1051)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (988:988:988) (1051:1051:1051)) + (PORT d[1] (981:981:981) (1017:1017:1017)) + (PORT d[2] (1019:1019:1019) (1075:1075:1075)) + (PORT d[3] (2212:2212:2212) (2367:2367:2367)) + (PORT d[4] (951:951:951) (1003:1003:1003)) + (PORT d[5] (953:953:953) (987:987:987)) + (PORT d[6] (967:967:967) (1002:1002:1002)) + (PORT d[7] (1186:1186:1186) (1245:1245:1245)) + (PORT d[8] (1439:1439:1439) (1497:1497:1497)) + (PORT d[9] (1738:1738:1738) (1800:1800:1800)) + (PORT d[10] (1670:1670:1670) (1832:1832:1832)) + (PORT d[11] (1257:1257:1257) (1348:1348:1348)) + (PORT d[12] (1351:1351:1351) (1468:1468:1468)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1495:1495:1495) (1495:1495:1495)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2024:2024:2024) (1999:1999:1999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1393:1393:1393) (1418:1418:1418)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2599:2599:2599) (2703:2703:2703)) + (PORT d[1] (2484:2484:2484) (2490:2490:2490)) + (PORT d[2] (2323:2323:2323) (2401:2401:2401)) + (PORT d[3] (597:597:597) (618:618:618)) + (PORT d[4] (2605:2605:2605) (2819:2819:2819)) + (PORT d[5] (2762:2762:2762) (2804:2804:2804)) + (PORT d[6] (3210:3210:3210) (3404:3404:3404)) + (PORT d[7] (1137:1137:1137) (1143:1143:1143)) + (PORT d[8] (1478:1478:1478) (1534:1534:1534)) + (PORT d[9] (1442:1442:1442) (1499:1499:1499)) + (PORT d[10] (2068:2068:2068) (2152:2152:2152)) + (PORT d[11] (2589:2589:2589) (2720:2720:2720)) + (PORT d[12] (1020:1020:1020) (1083:1083:1083)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1786:1786:1786) (1831:1831:1831)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2420:2420:2420) (2379:2379:2379)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1584:1584:1584)) + (PORT datab (1085:1085:1085) (1129:1129:1129)) + (PORT datac (1733:1733:1733) (1822:1822:1822)) + (PORT datad (1396:1396:1396) (1426:1426:1426)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1734:1734:1734) (1780:1780:1780)) + (PORT datab (1496:1496:1496) (1596:1596:1596)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (2079:2079:2079) (2106:2106:2106)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1065:1065:1065)) + (PORT datab (692:692:692) (777:777:777)) + (PORT datac (941:941:941) (1015:1015:1015)) + (PORT datad (405:405:405) (474:474:474)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1067:1067:1067)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (942:942:942) (1015:1015:1015)) + (PORT datad (213:213:213) (245:245:245)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (746:746:746)) + (PORT datab (442:442:442) (508:508:508)) + (PORT datac (320:320:320) (351:351:351)) + (PORT datad (314:314:314) (331:331:331)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (639:639:639) (662:662:662)) + (PORT datad (962:962:962) (1020:1020:1020)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (258:258:258)) + (PORT datab (236:236:236) (278:278:278)) + (PORT datac (942:942:942) (1014:1014:1014)) + (PORT datad (206:206:206) (235:235:235)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (412:412:412)) + (PORT datab (354:354:354) (386:386:386)) + (PORT datad (610:610:610) (622:622:622)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1588:1588:1588)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (2005:2005:2005) (2107:2107:2107)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (909:909:909)) + (PORT datab (756:756:756) (844:844:844)) + (PORT datac (739:739:739) (811:811:811)) + (PORT datad (718:718:718) (791:791:791)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (269:269:269)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (1017:1017:1017)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (635:635:635) (677:677:677)) + (PORT datad (925:925:925) (985:985:985)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1022:1022:1022) (1097:1097:1097)) + (PORT datad (449:449:449) (525:525:525)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (695:695:695)) + (PORT datab (3848:3848:3848) (4091:4091:4091)) + (PORT datac (213:213:213) (289:289:289)) + (PORT datad (3189:3189:3189) (3351:3351:3351)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (822:822:822)) + (PORT datac (699:699:699) (767:767:767)) + (PORT datad (687:687:687) (762:762:762)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (372:372:372)) + (PORT datab (209:209:209) (250:250:250)) + (PORT datad (448:448:448) (524:524:524)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (512:512:512)) + (PORT datab (881:881:881) (948:948:948)) + (PORT datac (718:718:718) (800:800:800)) + (PORT datad (755:755:755) (854:854:854)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT datab (771:771:771) (842:842:842)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (722:722:722) (796:796:796)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT datab (741:741:741) (830:830:830)) + (PORT datac (253:253:253) (338:338:338)) + (PORT datad (713:713:713) (778:778:778)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (371:371:371)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (1702:1702:1702) (1787:1787:1787)) + (PORT datac (2219:2219:2219) (2415:2415:2415)) + (PORT datad (607:607:607) (654:654:654)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1072:1072:1072)) + (PORT datab (981:981:981) (1073:1073:1073)) + (PORT datac (626:626:626) (648:648:648)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (513:513:513)) + (PORT datab (750:750:750) (839:839:839)) + (PORT datac (736:736:736) (808:808:808)) + (PORT datad (719:719:719) (793:793:793)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1364:1364:1364)) + (PORT datab (976:976:976) (1041:1041:1041)) + (PORT datad (367:367:367) (391:391:391)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1077:1077:1077)) + (PORT datab (983:983:983) (1074:1074:1074)) + (PORT datac (315:315:315) (333:333:333)) + (PORT datad (605:605:605) (620:620:620)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (747:747:747) (833:833:833)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (919:919:919) (965:965:965)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1078:1078:1078)) + (PORT datab (742:742:742) (831:831:831)) + (PORT datac (253:253:253) (335:335:335)) + (PORT datad (720:720:720) (788:788:788)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (243:243:243)) + (PORT datab (880:880:880) (904:904:904)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1103:1103:1103)) + (PORT datab (1271:1271:1271) (1321:1321:1321)) + (PORT datad (1127:1127:1127) (1181:1181:1181)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1110:1110:1110)) + (PORT datab (941:941:941) (962:962:962)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (700:700:700)) + (PORT datab (2117:2117:2117) (2268:2268:2268)) + (PORT datac (2005:2005:2005) (2082:2082:2082)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (672:672:672)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (574:574:574) (590:590:590)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1967:1967:1967) (2020:2020:2020)) + (PORT datab (1953:1953:1953) (1955:1955:1955)) + (PORT datac (1564:1564:1564) (1595:1595:1595)) + (PORT datad (1700:1700:1700) (1782:1782:1782)) + (IOPATH dataa combout (350:350:350) (367:367:367)) + (IOPATH datab combout (350:350:350) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1195:1195:1195) (1255:1255:1255)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1208:1208:1208)) + (PORT datab (1132:1132:1132) (1213:1213:1213)) + (PORT datac (1384:1384:1384) (1412:1412:1412)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (873:873:873)) + (PORT datab (1519:1519:1519) (1569:1569:1569)) + (PORT datac (904:904:904) (923:923:923)) + (PORT datad (230:230:230) (276:276:276)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (320:320:320)) + (PORT datac (632:632:632) (706:706:706)) + (PORT datad (243:243:243) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (911:911:911)) + (PORT datab (1058:1058:1058) (1073:1073:1073)) + (PORT datac (1459:1459:1459) (1478:1478:1478)) + (PORT datad (846:846:846) (921:921:921)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (247:247:247) (294:294:294)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1989:1989:1989) (1994:1994:1994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1784:1784:1784) (1892:1892:1892)) + (PORT datab (235:235:235) (278:278:278)) + (PORT datac (853:853:853) (872:872:872)) + (PORT datad (953:953:953) (1017:1017:1017)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT datab (1103:1103:1103) (1169:1169:1169)) + (PORT datac (684:684:684) (725:725:725)) + (PORT datad (691:691:691) (751:751:751)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT datac (1126:1126:1126) (1129:1129:1129)) + (PORT datad (581:581:581) (604:604:604)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1334:1334:1334)) + (PORT datab (927:927:927) (982:982:982)) + (PORT datac (2092:2092:2092) (2240:2240:2240)) + (PORT datad (1472:1472:1472) (1548:1548:1548)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1881:1881:1881) (1923:1923:1923)) + (PORT datab (965:965:965) (1009:1009:1009)) + (PORT datac (930:930:930) (953:953:953)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2380:2380:2380) (2493:2493:2493)) + (PORT datab (643:643:643) (682:682:682)) + (PORT datac (1198:1198:1198) (1308:1308:1308)) + (PORT datad (1130:1130:1130) (1175:1175:1175)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (669:669:669)) + (PORT datab (690:690:690) (737:737:737)) + (PORT datac (879:879:879) (893:893:893)) + (PORT datad (608:608:608) (625:625:625)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (436:436:436)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1111:1111:1111) (1171:1171:1171)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1954:1954:1954) (2052:2052:2052)) + (PORT datab (656:656:656) (711:711:711)) + (PORT datac (1113:1113:1113) (1169:1169:1169)) + (PORT datad (2119:2119:2119) (2147:2147:2147)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1252:1252:1252)) + (PORT datab (825:825:825) (842:842:842)) + (PORT datac (805:805:805) (823:823:823)) + (PORT datad (1427:1427:1427) (1479:1479:1479)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1353:1353:1353)) + (PORT datab (1556:1556:1556) (1621:1621:1621)) + (PORT datac (1135:1135:1135) (1151:1151:1151)) + (PORT datad (1451:1451:1451) (1474:1474:1474)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1179:1179:1179)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1141:1141:1141) (1171:1171:1171)) + (PORT datad (646:646:646) (668:668:668)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (947:947:947)) + (PORT datab (876:876:876) (888:888:888)) + (PORT datac (1324:1324:1324) (1366:1366:1366)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1090:1090:1090)) + (PORT datab (273:273:273) (359:359:359)) + (PORT datac (1199:1199:1199) (1287:1287:1287)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (1372:1372:1372) (1543:1543:1543)) + (PORT datac (238:238:238) (316:316:316)) + (PORT datad (1755:1755:1755) (1877:1877:1877)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1563:1563:1563) (1546:1546:1546)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (1043:1043:1043)) + (PORT datad (868:868:868) (931:931:931)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|nmi_armed) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1844:1844:1844)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (766:766:766) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1130:1130:1130) (1176:1176:1176)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|im1\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (202:202:202) (230:230:230)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1733:1733:1733) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (634:634:634)) + (PORT datab (461:461:461) (541:541:541)) + (PORT datac (1219:1219:1219) (1262:1262:1262)) + (PORT datad (676:676:676) (731:731:731)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1241:1241:1241)) + (PORT datab (709:709:709) (754:754:754)) + (PORT datac (1222:1222:1222) (1265:1265:1265)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (952:952:952)) + (PORT datab (273:273:273) (332:332:332)) + (PORT datac (1411:1411:1411) (1435:1435:1435)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (989:989:989) (1003:1003:1003)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3525:3525:3525) (3701:3701:3701)) + (PORT d[1] (3429:3429:3429) (3513:3513:3513)) + (PORT d[2] (3394:3394:3394) (3511:3511:3511)) + (PORT d[3] (3766:3766:3766) (4026:4026:4026)) + (PORT d[4] (2650:2650:2650) (2896:2896:2896)) + (PORT d[5] (2398:2398:2398) (2478:2478:2478)) + (PORT d[6] (3402:3402:3402) (3580:3580:3580)) + (PORT d[7] (4748:4748:4748) (4976:4976:4976)) + (PORT d[8] (3292:3292:3292) (3514:3514:3514)) + (PORT d[9] (3932:3932:3932) (4160:4160:4160)) + (PORT d[10] (3434:3434:3434) (3728:3728:3728)) + (PORT d[11] (2987:2987:2987) (3159:3159:3159)) + (PORT d[12] (2390:2390:2390) (2642:2642:2642)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1713:1713:1713) (1650:1650:1650)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (2508:2508:2508) (2510:2510:2510)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (985:985:985) (1010:1010:1010)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3226:3226:3226) (3381:3381:3381)) + (PORT d[1] (3121:3121:3121) (3182:3182:3182)) + (PORT d[2] (3690:3690:3690) (3825:3825:3825)) + (PORT d[3] (1731:1731:1731) (1774:1774:1774)) + (PORT d[4] (2937:2937:2937) (3200:3200:3200)) + (PORT d[5] (2819:2819:2819) (2909:2909:2909)) + (PORT d[6] (3693:3693:3693) (3923:3923:3923)) + (PORT d[7] (1737:1737:1737) (1793:1793:1793)) + (PORT d[8] (3590:3590:3590) (3837:3837:3837)) + (PORT d[9] (4222:4222:4222) (4471:4471:4471)) + (PORT d[10] (3794:3794:3794) (4126:4126:4126)) + (PORT d[11] (3296:3296:3296) (3491:3491:3491)) + (PORT d[12] (2704:2704:2704) (2953:2953:2953)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1807:1807:1807) (1857:1857:1857)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2404:2404:2404) (2385:2385:2385)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -48423,7 +51039,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1174:1174:1174) (1169:1169:1169)) + (PORT d[0] (965:965:965) (968:968:968)) (PORT clk (1860:1860:1860) (1888:1888:1888)) ) ) @@ -48436,19 +51052,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2884:2884:2884) (3084:3084:3084)) - (PORT d[1] (3296:3296:3296) (3485:3485:3485)) - (PORT d[2] (1967:1967:1967) (2035:2035:2035)) - (PORT d[3] (3971:3971:3971) (4151:4151:4151)) - (PORT d[4] (2885:2885:2885) (3085:3085:3085)) - (PORT d[5] (4454:4454:4454) (4597:4597:4597)) - (PORT d[6] (2220:2220:2220) (2291:2291:2291)) - (PORT d[7] (1721:1721:1721) (1766:1766:1766)) - (PORT d[8] (3141:3141:3141) (3324:3324:3324)) - (PORT d[9] (1847:1847:1847) (1916:1916:1916)) - (PORT d[10] (2061:2061:2061) (2130:2130:2130)) - (PORT d[11] (3118:3118:3118) (3322:3322:3322)) - (PORT d[12] (4307:4307:4307) (4577:4577:4577)) + (PORT d[0] (3227:3227:3227) (3382:3382:3382)) + (PORT d[1] (3414:3414:3414) (3478:3478:3478)) + (PORT d[2] (3713:3713:3713) (3838:3838:3838)) + (PORT d[3] (3780:3780:3780) (4058:4058:4058)) + (PORT d[4] (2638:2638:2638) (2900:2900:2900)) + (PORT d[5] (2731:2731:2731) (2790:2790:2790)) + (PORT d[6] (3407:3407:3407) (3612:3612:3612)) + (PORT d[7] (4787:4787:4787) (5037:5037:5037)) + (PORT d[8] (3619:3619:3619) (3835:3835:3835)) + (PORT d[9] (4243:4243:4243) (4495:4495:4495)) + (PORT d[10] (3498:3498:3498) (3819:3819:3819)) + (PORT d[11] (3267:3267:3267) (3442:3442:3442)) + (PORT d[12] (2341:2341:2341) (2586:2586:2586)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -48461,7 +51077,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1635:1635:1635) (1573:1573:1573)) + (PORT d[0] (2591:2591:2591) (2575:2575:2575)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -48475,7 +51091,7 @@ (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2528:2528:2528) (2508:2508:2508)) + (PORT d[0] (2247:2247:2247) (2219:2219:2219)) ) ) ) @@ -48571,170 +51187,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1400:1400:1400) (1441:1441:1441)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2389:2389:2389)) - (PORT d[1] (1122:1122:1122) (1125:1125:1125)) - (PORT d[2] (2684:2684:2684) (2759:2759:2759)) - (PORT d[3] (4593:4593:4593) (4819:4819:4819)) - (PORT d[4] (965:965:965) (1020:1020:1020)) - (PORT d[5] (1653:1653:1653) (1677:1677:1677)) - (PORT d[6] (1443:1443:1443) (1505:1505:1505)) - (PORT d[7] (1417:1417:1417) (1425:1425:1425)) - (PORT d[8] (2517:2517:2517) (2647:2647:2647)) - (PORT d[9] (1142:1142:1142) (1167:1167:1167)) - (PORT d[10] (2053:2053:2053) (2116:2116:2116)) - (PORT d[11] (3735:3735:3735) (3999:3999:3999)) - (PORT d[12] (2464:2464:2464) (2535:2535:2535)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2814:2814:2814) (2818:2818:2818)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (1909:1909:1909) (1894:1894:1894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) (DELAY (ABSOLUTE - (PORT dataa (857:857:857) (885:885:885)) - (PORT datab (1257:1257:1257) (1321:1321:1321)) - (PORT datac (1457:1457:1457) (1543:1543:1543)) - (PORT datad (1415:1415:1415) (1470:1470:1470)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (907:907:907) (915:915:915)) + (PORT datab (1124:1124:1124) (1211:1211:1211)) + (PORT datac (802:802:802) (810:810:810)) + (PORT datad (1340:1340:1340) (1406:1406:1406)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48745,8 +51208,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1461:1461:1461) (1498:1498:1498)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (989:989:989) (1029:1029:1029)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -48758,20 +51221,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1675:1675:1675) (1799:1799:1799)) - (PORT d[1] (2219:2219:2219) (2269:2269:2269)) - (PORT d[2] (2260:2260:2260) (2441:2441:2441)) - (PORT d[3] (1737:1737:1737) (1761:1761:1761)) - (PORT d[4] (2421:2421:2421) (2555:2555:2555)) - (PORT d[5] (2836:2836:2836) (2889:2889:2889)) - (PORT d[6] (2028:2028:2028) (2126:2126:2126)) - (PORT d[7] (1728:1728:1728) (1790:1790:1790)) - (PORT d[8] (2170:2170:2170) (2268:2268:2268)) - (PORT d[9] (1998:1998:1998) (2050:2050:2050)) - (PORT d[10] (2212:2212:2212) (2291:2291:2291)) - (PORT d[11] (4313:4313:4313) (4609:4609:4609)) - (PORT d[12] (2203:2203:2203) (2259:2259:2259)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (3210:3210:3210) (3342:3342:3342)) + (PORT d[1] (3136:3136:3136) (3194:3194:3194)) + (PORT d[2] (3968:3968:3968) (4136:4136:4136)) + (PORT d[3] (2001:2001:2001) (2070:2070:2070)) + (PORT d[4] (2943:2943:2943) (3223:3223:3223)) + (PORT d[5] (3520:3520:3520) (3590:3590:3590)) + (PORT d[6] (3986:3986:3986) (4237:4237:4237)) + (PORT d[7] (1223:1223:1223) (1277:1277:1277)) + (PORT d[8] (3923:3923:3923) (4174:4174:4174)) + (PORT d[9] (4191:4191:4191) (4487:4487:4487)) + (PORT d[10] (3858:3858:3858) (4185:4185:4185)) + (PORT d[11] (3578:3578:3578) (3778:3778:3778)) + (PORT d[12] (2685:2685:2685) (2937:2937:2937)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48783,8 +51246,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1909:1909:1909) (1957:1957:1957)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (3016:3016:3016) (2994:2994:2994)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48796,8 +51259,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (1899:1899:1899) (1859:1859:1859)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2978:2978:2978) (2947:2947:2947)) ) ) ) @@ -48806,7 +51269,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -48816,7 +51279,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -48826,7 +51289,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48836,7 +51299,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48846,7 +51309,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -48860,7 +51323,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) @@ -48869,7 +51332,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) @@ -48878,7 +51341,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -48888,22 +51351,649 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1194:1194:1194) (1262:1262:1262)) - (PORT datab (1708:1708:1708) (1802:1802:1802)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1682:1682:1682) (1783:1783:1783)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (1806:1806:1806) (1885:1885:1885)) + (PORT datab (1118:1118:1118) (1162:1162:1162)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1347:1347:1347) (1336:1336:1336)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1292:1292:1292) (1365:1365:1365)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3818:3818:3818) (4013:4013:4013)) + (PORT d[1] (4032:4032:4032) (4143:4143:4143)) + (PORT d[2] (3105:3105:3105) (3220:3220:3220)) + (PORT d[3] (3182:3182:3182) (3413:3413:3413)) + (PORT d[4] (3466:3466:3466) (3759:3759:3759)) + (PORT d[5] (3001:3001:3001) (3070:3070:3070)) + (PORT d[6] (2812:2812:2812) (2948:2948:2948)) + (PORT d[7] (4158:4158:4158) (4362:4362:4362)) + (PORT d[8] (3030:3030:3030) (3203:3203:3203)) + (PORT d[9] (3580:3580:3580) (3805:3805:3805)) + (PORT d[10] (2841:2841:2841) (3108:3108:3108)) + (PORT d[11] (2673:2673:2673) (2807:2807:2807)) + (PORT d[12] (2485:2485:2485) (2667:2667:2667)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1928:1928:1928) (1942:1942:1942)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (5245:5245:5245) (5346:5346:5346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1161:1161:1161)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4210:4210:4210) (4283:4283:4283)) + (PORT d[1] (4252:4252:4252) (4439:4439:4439)) + (PORT d[2] (4275:4275:4275) (4331:4331:4331)) + (PORT d[3] (4262:4262:4262) (4288:4288:4288)) + (PORT d[4] (4122:4122:4122) (4133:4133:4133)) + (PORT d[5] (4222:4222:4222) (4438:4438:4438)) + (PORT d[6] (4311:4311:4311) (4503:4503:4503)) + (PORT d[7] (4253:4253:4253) (4426:4426:4426)) + (PORT d[8] (4145:4145:4145) (4203:4203:4203)) + (PORT d[9] (4160:4160:4160) (4245:4245:4245)) + (PORT d[10] (4194:4194:4194) (4240:4240:4240)) + (PORT d[11] (4190:4190:4190) (4246:4246:4246)) + (PORT d[12] (4190:4190:4190) (4237:4237:4237)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2297:2297:2297) (2378:2378:2378)) + (PORT d[1] (2451:2451:2451) (2480:2480:2480)) + (PORT d[2] (1984:1984:1984) (2035:2035:2035)) + (PORT d[3] (1187:1187:1187) (1234:1234:1234)) + (PORT d[4] (2548:2548:2548) (2681:2681:2681)) + (PORT d[5] (2483:2483:2483) (2506:2506:2506)) + (PORT d[6] (3750:3750:3750) (3934:3934:3934)) + (PORT d[7] (1439:1439:1439) (1446:1446:1446)) + (PORT d[8] (990:990:990) (1030:1030:1030)) + (PORT d[9] (996:996:996) (1044:1044:1044)) + (PORT d[10] (1809:1809:1809) (1883:1883:1883)) + (PORT d[11] (2570:2570:2570) (2680:2680:2680)) + (PORT d[12] (1527:1527:1527) (1571:1571:1571)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (1691:1691:1691) (1707:1707:1707)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1294:1294:1294) (1353:1353:1353)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3806:3806:3806) (3984:3984:3984)) + (PORT d[1] (3754:3754:3754) (3857:3857:3857)) + (PORT d[2] (3404:3404:3404) (3506:3506:3506)) + (PORT d[3] (3481:3481:3481) (3739:3739:3739)) + (PORT d[4] (2622:2622:2622) (2872:2872:2872)) + (PORT d[5] (2719:2719:2719) (2812:2812:2812)) + (PORT d[6] (3098:3098:3098) (3283:3283:3283)) + (PORT d[7] (4462:4462:4462) (4689:4689:4689)) + (PORT d[8] (3320:3320:3320) (3510:3510:3510)) + (PORT d[9] (3593:3593:3593) (3836:3836:3836)) + (PORT d[10] (3168:3168:3168) (3460:3460:3460)) + (PORT d[11] (2943:2943:2943) (3089:3089:3089)) + (PORT d[12] (2418:2418:2418) (2570:2570:2570)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1881:1881:1881) (1817:1817:1817)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (5380:5380:5380) (5254:5254:5254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1386:1386:1386) (1413:1413:1413)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4212:4212:4212) (4290:4290:4290)) + (PORT d[1] (4206:4206:4206) (4314:4314:4314)) + (PORT d[2] (4290:4290:4290) (4320:4320:4320)) + (PORT d[3] (4144:4144:4144) (4163:4163:4163)) + (PORT d[4] (4125:4125:4125) (4163:4163:4163)) + (PORT d[5] (4399:4399:4399) (4775:4775:4775)) + (PORT d[6] (4274:4274:4274) (4458:4458:4458)) + (PORT d[7] (4213:4213:4213) (4376:4376:4376)) + (PORT d[8] (4147:4147:4147) (4214:4214:4214)) + (PORT d[9] (4192:4192:4192) (4273:4273:4273)) + (PORT d[10] (4148:4148:4148) (4202:4202:4202)) + (PORT d[11] (4194:4194:4194) (4252:4252:4252)) + (PORT d[12] (4228:4228:4228) (4297:4297:4297)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2853:2853:2853) (2974:2974:2974)) + (PORT d[1] (4349:4349:4349) (4498:4498:4498)) + (PORT d[2] (2808:2808:2808) (2944:2944:2944)) + (PORT d[3] (2497:2497:2497) (2704:2704:2704)) + (PORT d[4] (3076:3076:3076) (3317:3317:3317)) + (PORT d[5] (3063:3063:3063) (3131:3131:3131)) + (PORT d[6] (3084:3084:3084) (3269:3269:3269)) + (PORT d[7] (3381:3381:3381) (3572:3572:3572)) + (PORT d[8] (2448:2448:2448) (2587:2587:2587)) + (PORT d[9] (2990:2990:2990) (3199:3199:3199)) + (PORT d[10] (2315:2315:2315) (2557:2557:2557)) + (PORT d[11] (2281:2281:2281) (2377:2377:2377)) + (PORT d[12] (2568:2568:2568) (2777:2777:2777)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (3596:3596:3596) (3520:3520:3520)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1291:1291:1291)) + (PORT datab (1237:1237:1237) (1326:1326:1326)) + (PORT datac (1047:1047:1047) (1040:1040:1040)) + (PORT datad (1615:1615:1615) (1631:1631:1631)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48911,14 +52001,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~112) + (INSTANCE Selector4\~1) (DELAY (ABSOLUTE - (PORT dataa (1742:1742:1742) (1794:1794:1794)) - (PORT datab (667:667:667) (692:692:692)) - (PORT datac (628:628:628) (640:640:640)) - (PORT datad (319:319:319) (340:340:340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1456:1456:1456) (1537:1537:1537)) + (PORT datab (1162:1162:1162) (1194:1194:1194)) + (PORT datac (1385:1385:1385) (1437:1437:1437)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (3077:3077:3077) (3143:3143:3143)) + (PORT datab (1186:1186:1186) (1190:1190:1190)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1019:1019:1019)) + (PORT datab (1384:1384:1384) (1388:1388:1388)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (1728:1728:1728) (1791:1791:1791)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -48927,16 +52049,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~113) + (INSTANCE D\[5\]\~40) (DELAY (ABSOLUTE - (PORT dataa (2496:2496:2496) (2561:2561:2561)) - (PORT datab (700:700:700) (722:722:722)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (1174:1174:1174) (1248:1248:1248)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1084:1084:1084) (1099:1099:1099)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -48946,13 +52064,13 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (690:690:690)) - (PORT datab (1158:1158:1158) (1194:1194:1194)) - (PORT datac (219:219:219) (257:257:257)) - (PORT datad (1559:1559:1559) (1584:1584:1584)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1405:1405:1405) (1441:1441:1441)) + (PORT datab (855:855:855) (937:937:937)) + (PORT datac (1481:1481:1481) (1529:1529:1529)) + (PORT datad (227:227:227) (272:272:272)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -48962,9 +52080,9 @@ (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT clk (1520:1520:1520) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -48975,30 +52093,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT datab (431:431:431) (490:490:490)) - (PORT datac (218:218:218) (263:263:263)) - (PORT datad (227:227:227) (264:264:264)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (262:262:262) (323:323:323)) + (PORT datac (1018:1018:1018) (1093:1093:1093)) + (PORT datad (245:245:245) (291:291:291)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (873:873:873) (882:882:882)) - (PORT datab (592:592:592) (613:613:613)) - (PORT datac (532:532:532) (547:547:547)) - (PORT datad (1104:1104:1104) (1122:1122:1122)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (886:886:886) (970:970:970)) + (PORT datab (787:787:787) (866:866:866)) + (PORT datac (1461:1461:1461) (1480:1480:1480)) + (PORT datad (1157:1157:1157) (1192:1192:1192)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49008,10 +52126,84 @@ (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1709:1709:1709) (1778:1778:1778)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2114:2114:2114) (2227:2227:2227)) + (PORT datac (1203:1203:1203) (1284:1284:1284)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (695:695:695)) + (PORT datab (724:724:724) (764:764:764)) + (PORT datac (911:911:911) (967:967:967)) + (PORT datad (1869:1869:1869) (1997:1997:1997)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (676:676:676)) + (PORT datab (667:667:667) (728:728:728)) + (PORT datac (1451:1451:1451) (1495:1495:1495)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1086:1086:1086)) + (PORT datab (265:265:265) (347:347:347)) + (PORT datac (1202:1202:1202) (1273:1273:1273)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1940:1940:1940) (1962:1962:1962)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -49023,139 +52215,109 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (INSTANCE z80_\|execute_\|setM1\~16) (DELAY (ABSOLUTE - (PORT dataa (2126:2126:2126) (2295:2295:2295)) - (PORT datab (2009:2009:2009) (2098:2098:2098)) - (PORT datac (1374:1374:1374) (1481:1481:1481)) - (PORT datad (877:877:877) (904:904:904)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1340:1340:1340) (1387:1387:1387)) + (PORT datab (619:619:619) (644:644:644)) + (PORT datac (1139:1139:1139) (1180:1180:1180)) + (PORT datad (904:904:904) (975:975:975)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1028:1028:1028)) + (PORT datab (676:676:676) (699:699:699)) + (PORT datac (1508:1508:1508) (1599:1599:1599)) + (PORT datad (1006:1006:1006) (1064:1064:1064)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (685:685:685)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (315:315:315) (335:335:335)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (917:917:917)) + (PORT datab (703:703:703) (764:764:764)) + (PORT datac (1808:1808:1808) (1909:1909:1909)) + (PORT datad (641:641:641) (699:699:699)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1409:1409:1409)) + (PORT datab (877:877:877) (916:916:916)) + (PORT datac (553:553:553) (568:568:568)) + (PORT datad (343:343:343) (365:365:365)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (1208:1208:1208) (1251:1251:1251)) - (PORT datab (660:660:660) (700:700:700)) - (PORT datac (1413:1413:1413) (1458:1458:1458)) - (PORT datad (334:334:334) (357:357:357)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (638:638:638) (665:665:665)) + (PORT datab (925:925:925) (952:952:952)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) + (INSTANCE z80_\|execute_\|setM1\~47) (DELAY (ABSOLUTE - (PORT datac (1029:1029:1029) (1089:1089:1089)) - (PORT datad (603:603:603) (614:614:614)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1871:1871:1871) (1947:1947:1947)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (1085:1085:1085) (1121:1121:1121)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1239:1239:1239)) - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (611:611:611) (641:641:641)) - (PORT datad (596:596:596) (616:616:616)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (1216:1216:1216) (1268:1268:1268)) + (PORT datab (1244:1244:1244) (1285:1285:1285)) + (PORT datac (891:891:891) (942:942:942)) + (PORT datad (848:848:848) (876:876:876)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1281:1281:1281) (1354:1354:1354)) - (PORT datab (757:757:757) (812:812:812)) - (PORT datac (1936:1936:1936) (1953:1953:1953)) - (PORT datad (827:827:827) (852:852:852)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (683:683:683)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1472:1472:1472) (1542:1542:1542)) - (PORT datad (632:632:632) (697:697:697)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1686:1686:1686) (1728:1728:1728)) - (PORT datab (924:924:924) (949:949:949)) - (PORT datac (1405:1405:1405) (1437:1437:1437)) - (PORT datad (869:869:869) (884:884:884)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (692:692:692)) - (PORT datab (1323:1323:1323) (1377:1377:1377)) - (PORT datac (213:213:213) (245:245:245)) - (PORT datad (1699:1699:1699) (1713:1713:1713)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49163,328 +52325,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) + (INSTANCE z80_\|execute_\|setM1\~53) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (658:658:658) (707:707:707)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (890:890:890)) - (PORT datab (2358:2358:2358) (2453:2453:2453)) - (PORT datac (1473:1473:1473) (1589:1589:1589)) - (PORT datad (1034:1034:1034) (1093:1093:1093)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (941:941:941)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (588:588:588) (602:602:602)) - (PORT datac (587:587:587) (646:646:646)) - (PORT datad (1400:1400:1400) (1419:1419:1419)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (679:679:679) (727:727:727)) - (PORT datad (889:889:889) (908:908:908)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (774:774:774)) - (PORT datac (683:683:683) (724:724:724)) - (PORT datad (890:890:890) (904:904:904)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (354:354:354)) - (PORT datac (685:685:685) (725:725:725)) - (PORT datad (891:891:891) (904:904:904)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datac (680:680:680) (727:727:727)) - (PORT datad (893:893:893) (910:910:910)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT datac (695:695:695) (789:789:789)) - (PORT datad (2317:2317:2317) (2438:2438:2438)) + (PORT dataa (589:589:589) (604:604:604)) + (PORT datab (615:615:615) (661:661:661)) + (PORT datac (910:910:910) (952:952:952)) + (PORT datad (1044:1044:1044) (1045:1045:1045)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1283:1283:1283)) - (PORT datab (1491:1491:1491) (1605:1605:1605)) - (PORT datac (1593:1593:1593) (1631:1631:1631)) - (PORT datad (953:953:953) (980:980:980)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~54) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1176:1176:1176)) - (PORT datab (662:662:662) (691:691:691)) - (PORT datac (1163:1163:1163) (1238:1238:1238)) - (PORT datad (898:898:898) (985:985:985)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (689:689:689)) - (PORT datab (1319:1319:1319) (1372:1372:1372)) - (PORT datac (624:624:624) (642:642:642)) - (PORT datad (866:866:866) (881:881:881)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1259:1259:1259)) - (PORT datab (974:974:974) (1000:1000:1000)) - (PORT datac (255:255:255) (313:313:313)) - (PORT datad (1134:1134:1134) (1181:1181:1181)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1254:1254:1254)) - (PORT datab (606:606:606) (649:649:649)) - (PORT datac (872:872:872) (901:901:901)) - (PORT datad (807:807:807) (862:862:862)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (1002:1002:1002)) - (PORT datab (1460:1460:1460) (1527:1527:1527)) - (PORT datac (2859:2859:2859) (2966:2966:2966)) - (PORT datad (229:229:229) (304:304:304)) + (PORT dataa (357:357:357) (403:403:403)) + (PORT datab (972:972:972) (1030:1030:1030)) + (PORT datac (930:930:930) (954:954:954)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1419:1419:1419) (1546:1546:1546)) - (PORT datab (1084:1084:1084) (1106:1106:1106)) - (PORT datac (1238:1238:1238) (1330:1330:1330)) - (PORT datad (2052:2052:2052) (2171:2171:2171)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1150:1150:1150)) - (PORT datab (384:384:384) (410:410:410)) - (PORT datac (820:820:820) (894:894:894)) - (PORT datad (1655:1655:1655) (1717:1717:1717)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49494,10 +52360,58 @@ (INSTANCE z80_\|execute_\|setM1\~24) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (927:927:927) (989:989:989)) - (PORT datac (864:864:864) (890:890:890)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (998:998:998) (1081:1081:1081)) + (PORT datab (259:259:259) (340:340:340)) + (PORT datac (1964:1964:1964) (2044:2044:2044)) + (PORT datad (1190:1190:1190) (1261:1261:1261)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1369:1369:1369)) + (PORT datab (1243:1243:1243) (1338:1338:1338)) + (PORT datac (1428:1428:1428) (1523:1523:1523)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1137:1137:1137)) + (PORT datab (921:921:921) (958:958:958)) + (PORT datac (639:639:639) (666:666:666)) + (PORT datad (870:870:870) (922:922:922)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (968:968:968) (1008:1008:1008)) + (PORT datac (1088:1088:1088) (1107:1107:1107)) + (PORT datad (1330:1330:1330) (1333:1333:1333)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -49510,76 +52424,28 @@ (INSTANCE z80_\|execute_\|setM1\~28) (DELAY (ABSOLUTE - (PORT dataa (541:541:541) (570:570:570)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (611:611:611) (630:630:630)) - (PORT datad (875:875:875) (908:908:908)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1172:1172:1172)) - (PORT datab (1952:1952:1952) (2000:2000:2000)) - (PORT datac (939:939:939) (1020:1020:1020)) - (PORT datad (1208:1208:1208) (1249:1249:1249)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1344:1344:1344) (1436:1436:1436)) + (PORT datab (1393:1393:1393) (1505:1505:1505)) + (PORT datac (812:812:812) (849:849:849)) + (PORT datad (1233:1233:1233) (1285:1285:1285)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1722:1722:1722) (1767:1767:1767)) - (PORT datab (2033:2033:2033) (2073:2073:2073)) - (PORT datac (1628:1628:1628) (1671:1671:1671)) - (PORT datad (1597:1597:1597) (1619:1619:1619)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~29) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (886:886:886)) - (PORT datab (832:832:832) (896:896:896)) - (PORT datac (869:869:869) (939:939:939)) - (PORT datad (1271:1271:1271) (1354:1354:1354)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1190:1190:1190)) - (PORT datab (884:884:884) (932:932:932)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1296:1296:1296) (1353:1353:1353)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1384:1384:1384) (1443:1443:1443)) + (PORT datab (1127:1127:1127) (1145:1145:1145)) + (PORT datac (1371:1371:1371) (1467:1467:1467)) + (PORT datad (1097:1097:1097) (1131:1131:1131)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49587,64 +52453,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) + (INSTANCE z80_\|execute_\|setM1\~27) (DELAY (ABSOLUTE - (PORT dataa (880:880:880) (942:942:942)) - (PORT datab (1536:1536:1536) (1590:1590:1590)) - (PORT datac (1141:1141:1141) (1163:1163:1163)) - (PORT datad (1571:1571:1571) (1615:1615:1615)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1949:1949:1949) (2046:2046:2046)) + (PORT datab (1433:1433:1433) (1467:1467:1467)) + (PORT datac (624:624:624) (676:676:676)) + (PORT datad (945:945:945) (1000:1000:1000)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1781:1781:1781) (1842:1842:1842)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1086:1086:1086) (1118:1118:1118)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~34) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (883:883:883)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (845:845:845) (843:843:843)) - (PORT datad (1659:1659:1659) (1685:1685:1685)) - (IOPATH dataa combout (303:303:303) (299:299:299)) + (PORT dataa (948:948:948) (1020:1020:1020)) + (PORT datab (1495:1495:1495) (1555:1555:1555)) + (PORT datac (863:863:863) (896:896:896)) + (PORT datad (607:607:607) (623:623:623)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1993:1993:1993) (2079:2079:2079)) + (PORT datab (1406:1406:1406) (1502:1502:1502)) + (PORT datac (965:965:965) (1047:1047:1047)) + (PORT datad (1191:1191:1191) (1262:1262:1262)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (988:988:988)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datac (1656:1656:1656) (1675:1675:1675)) - (PORT datad (928:928:928) (961:961:961)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1254:1254:1254)) - (PORT datab (1283:1283:1283) (1356:1356:1356)) - (PORT datac (899:899:899) (912:912:912)) - (PORT datad (812:812:812) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49654,12 +52520,60 @@ (INSTANCE z80_\|execute_\|setM1\~35) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (893:893:893) (944:944:944)) + (PORT datab (1224:1224:1224) (1270:1270:1270)) + (PORT datac (356:356:356) (382:382:382)) + (PORT datad (613:613:613) (655:655:655)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (471:471:471)) + (PORT datab (949:949:949) (1019:1019:1019)) + (PORT datac (946:946:946) (998:998:998)) + (PORT datad (1234:1234:1234) (1287:1287:1287)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1329:1329:1329)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (572:572:572) (591:591:591)) + (PORT datad (1209:1209:1209) (1278:1278:1278)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (292:292:292)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49667,15 +52581,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) + (INSTANCE z80_\|execute_\|setM1\~56) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (662:662:662)) - (PORT datab (1239:1239:1239) (1284:1284:1284)) - (PORT datac (1420:1420:1420) (1516:1516:1516)) - (PORT datad (610:610:610) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1879:1879:1879) (1973:1973:1973)) + (PORT datab (1953:1953:1953) (2083:2083:2083)) + (PORT datac (583:583:583) (597:597:597)) + (PORT datad (1178:1178:1178) (1226:1226:1226)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49683,13 +52597,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) + (INSTANCE z80_\|execute_\|setM1\~22) (DELAY (ABSOLUTE - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (607:607:607) (632:632:632)) - (PORT datad (1915:1915:1915) (1966:1966:1966)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1926:1926:1926) (1950:1950:1950)) + (PORT datab (656:656:656) (704:704:704)) + (PORT datac (936:936:936) (979:979:979)) + (PORT datad (616:616:616) (630:630:630)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49697,13 +52613,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) + (INSTANCE z80_\|execute_\|setM1\~23) (DELAY (ABSOLUTE - (PORT dataa (1167:1167:1167) (1219:1219:1219)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1354:1354:1354) (1355:1355:1355)) + (PORT dataa (230:230:230) (278:278:278)) + (PORT datab (1154:1154:1154) (1179:1179:1179)) + (PORT datac (1373:1373:1373) (1469:1469:1469)) + (PORT datad (172:172:172) (198:198:198)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -49713,15 +52629,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) + (INSTANCE z80_\|execute_\|setM1\~37) (DELAY (ABSOLUTE - (PORT dataa (1152:1152:1152) (1228:1228:1228)) - (PORT datab (1143:1143:1143) (1197:1197:1197)) - (PORT datac (1388:1388:1388) (1456:1456:1456)) - (PORT datad (1311:1311:1311) (1375:1375:1375)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (598:598:598) (619:619:619)) + (PORT datab (641:641:641) (691:691:691)) + (PORT datac (613:613:613) (634:634:634)) + (PORT datad (604:604:604) (620:620:620)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49732,152 +52648,12 @@ (INSTANCE z80_\|execute_\|setM1\~12) (DELAY (ABSOLUTE - (PORT dataa (1124:1124:1124) (1140:1140:1140)) - (PORT datab (1614:1614:1614) (1768:1768:1768)) - (PORT datac (1340:1340:1340) (1376:1376:1376)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (938:938:938)) - (PORT datab (1149:1149:1149) (1249:1249:1249)) - (PORT datac (666:666:666) (774:774:774)) - (PORT datad (876:876:876) (897:897:897)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (949:949:949)) - (PORT datac (1502:1502:1502) (1602:1602:1602)) - (PORT datad (838:838:838) (846:846:846)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (1193:1193:1193) (1237:1237:1237)) - (PORT datac (1207:1207:1207) (1228:1228:1228)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (979:979:979)) - (PORT datab (685:685:685) (706:706:706)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (1969:1969:1969) (2022:2022:2022)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (970:970:970)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1488:1488:1488) (1575:1575:1575)) - (PORT datad (633:633:633) (645:645:645)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1166:1166:1166)) - (PORT datab (1111:1111:1111) (1226:1226:1226)) - (PORT datac (565:565:565) (580:580:580)) - (PORT datad (818:818:818) (823:823:823)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1729:1729:1729) (1815:1815:1815)) - (PORT datab (1999:1999:1999) (2067:2067:2067)) - (PORT datac (939:939:939) (999:999:999)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1047:1047:1047)) - (PORT datab (1000:1000:1000) (1036:1036:1036)) - (PORT datac (170:170:170) (201:201:201)) - (PORT datad (937:937:937) (978:978:978)) + (PORT dataa (628:628:628) (655:655:655)) + (PORT datab (1195:1195:1195) (1223:1223:1223)) + (PORT datac (1161:1161:1161) (1182:1182:1182)) + (PORT datad (1145:1145:1145) (1184:1184:1184)) (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1471:1471:1471) (1555:1555:1555)) - (PORT datab (1379:1379:1379) (1419:1419:1419)) - (PORT datac (1473:1473:1473) (1586:1586:1586)) - (PORT datad (591:591:591) (624:624:624)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49885,61 +52661,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) + (INSTANCE z80_\|execute_\|setM1\~14) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (346:346:346) (362:362:362)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (680:680:680) (726:726:726)) - (PORT datad (894:894:894) (909:909:909)) + (PORT dataa (1233:1233:1233) (1273:1273:1273)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (2066:2066:2066) (2111:2111:2111)) + (PORT datad (613:613:613) (656:656:656)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) + (INSTANCE z80_\|execute_\|setM1\~10) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (915:915:915) (992:992:992)) - (PORT datac (1353:1353:1353) (1387:1387:1387)) - (PORT datad (360:360:360) (381:381:381)) + (PORT dataa (1230:1230:1230) (1301:1301:1301)) + (PORT datab (1309:1309:1309) (1419:1419:1419)) + (PORT datac (1183:1183:1183) (1222:1222:1222)) + (PORT datad (1272:1272:1272) (1370:1370:1370)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -49949,28 +52693,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (INSTANCE z80_\|execute_\|setM1\~11) (DELAY (ABSOLUTE - (PORT dataa (621:621:621) (652:652:652)) - (PORT datab (1116:1116:1116) (1149:1149:1149)) - (PORT datac (905:905:905) (992:992:992)) - (PORT datad (546:546:546) (553:553:553)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT datab (1494:1494:1494) (1578:1578:1578)) + (PORT datac (920:920:920) (944:944:944)) + (PORT datad (909:909:909) (950:950:950)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (665:665:665)) + (PORT datab (371:371:371) (394:394:394)) + (PORT datac (200:200:200) (238:238:238)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (814:814:814) (861:861:861)) + (PORT datac (637:637:637) (662:662:662)) + (PORT datad (899:899:899) (931:931:931)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (648:648:648)) + (PORT datab (863:863:863) (880:880:880)) + (PORT datac (587:587:587) (630:630:630)) + (PORT datad (923:923:923) (967:967:967)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (2597:2597:2597) (2742:2742:2742)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) (DELAY (ABSOLUTE - (PORT datab (705:705:705) (765:765:765)) - (PORT datad (895:895:895) (911:911:911)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1268:1268:1268) (1348:1348:1348)) + (PORT datad (972:972:972) (1033:1033:1033)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49981,9 +52787,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -49994,14 +52800,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) + (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (661:661:661) (724:724:724)) - (PORT datab (720:720:720) (764:764:764)) - (PORT datad (890:890:890) (904:904:904)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (409:409:409) (485:485:485)) + (PORT datab (1783:1783:1783) (1915:1915:1915)) + (PORT datad (1344:1344:1344) (1503:1503:1503)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50009,12 +52815,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1904:1904:1904) (1884:1884:1884)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50025,28 +52831,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT datab (982:982:982) (1081:1081:1081)) - (PORT datac (1243:1243:1243) (1342:1342:1342)) - (PORT datad (957:957:957) (1051:1051:1051)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (1537:1537:1537) (1666:1666:1666)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (224:224:224) (295:295:295)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT asdata (564:564:564) (641:641:641)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1274:1274:1274)) + (PORT datab (248:248:248) (333:333:333)) + (PORT datad (223:223:223) (294:294:294)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (1482:1482:1482) (1540:1540:1540)) - (PORT datad (1185:1185:1185) (1227:1227:1227)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (672:672:672) (713:713:713)) + (PORT datad (838:838:838) (847:847:847)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50056,11 +52923,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1177:1177:1177) (1260:1260:1260)) - (PORT datab (837:837:837) (857:857:857)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (382:382:382) (410:410:410)) + (PORT datab (888:888:888) (956:956:956)) + (PORT datad (897:897:897) (934:934:934)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50070,11 +52937,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (707:707:707) (769:769:769)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) + (PORT asdata (917:917:917) (971:971:971)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50087,59 +52954,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~66) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~2) (DELAY (ABSOLUTE - (PORT datab (902:902:902) (924:924:924)) - (PORT datac (872:872:872) (926:926:926)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (2781:2781:2781) (2888:2888:2888)) - (PORT datab (1476:1476:1476) (1559:1559:1559)) - (PORT datac (1480:1480:1480) (1521:1521:1521)) - (PORT datad (308:308:308) (323:323:323)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (2634:2634:2634) (2765:2765:2765)) - (PORT datab (1935:1935:1935) (2079:2079:2079)) - (PORT datac (2771:2771:2771) (3001:3001:3001)) - (PORT datad (2441:2441:2441) (2545:2545:2545)) + (PORT dataa (641:641:641) (666:666:666)) + (PORT datab (956:956:956) (1029:1029:1029)) + (PORT datac (713:713:713) (817:817:817)) + (PORT datad (898:898:898) (904:904:904)) (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (709:709:709)) - (PORT datac (1085:1085:1085) (1132:1132:1132)) - (PORT datad (350:350:350) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (342:342:342) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50147,73 +52970,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~69) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (2782:2782:2782) (2888:2888:2888)) - (PORT datab (949:949:949) (1041:1041:1041)) - (PORT datac (1479:1479:1479) (1520:1520:1520)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (910:910:910) (934:934:934)) + (PORT datab (955:955:955) (1026:1026:1026)) + (PORT datac (929:929:929) (954:954:954)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datab (1161:1161:1161) (1224:1224:1224)) - (PORT datac (844:844:844) (887:887:887)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (2196:2196:2196) (2279:2279:2279)) - (PORT datab (635:635:635) (666:666:666)) - (PORT datac (1696:1696:1696) (1794:1794:1794)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (2780:2780:2780) (2885:2885:2885)) - (PORT datac (912:912:912) (1002:1002:1002)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (409:409:409)) - (PORT datab (946:946:946) (982:982:982)) - (PORT datac (332:332:332) (348:348:348)) - (PORT datad (334:334:334) (351:351:351)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50221,121 +52986,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~95) + (INSTANCE Selector14\~15) (DELAY (ABSOLUTE - (PORT dataa (917:917:917) (978:978:978)) - (PORT datab (917:917:917) (942:942:942)) - (PORT datac (181:181:181) (218:218:218)) + (PORT dataa (1279:1279:1279) (1345:1345:1345)) + (PORT datab (1007:1007:1007) (1111:1111:1111)) + (PORT datac (1507:1507:1507) (1558:1558:1558)) + (PORT datad (1206:1206:1206) (1261:1261:1261)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~96) + (INSTANCE Selector14\~16) (DELAY (ABSOLUTE - (PORT dataa (1289:1289:1289) (1374:1374:1374)) - (PORT datab (436:436:436) (474:474:474)) - (PORT datac (2209:2209:2209) (2279:2279:2279)) + (PORT dataa (1207:1207:1207) (1255:1255:1255)) + (PORT datab (1008:1008:1008) (1109:1109:1109)) + (PORT datac (1260:1260:1260) (1276:1276:1276)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~126) + (INSTANCE D\[0\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1874:1874:1874) (1923:1923:1923)) - (PORT datab (3091:3091:3091) (3312:3312:3312)) - (PORT datac (627:627:627) (639:639:639)) - (PORT datad (321:321:321) (343:343:343)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (817:817:817) (825:825:825)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (617:617:617) (644:644:644)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~98) + (INSTANCE D\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1201:1201:1201) (1291:1291:1291)) - (PORT datab (672:672:672) (697:697:697)) - (PORT datac (2459:2459:2459) (2525:2525:2525)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~105) - (DELAY - (ABSOLUTE - (PORT datab (873:873:873) (921:921:921)) - (PORT datac (364:364:364) (389:389:389)) - (PORT datad (349:349:349) (365:365:365)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1328:1328:1328)) - (PORT datab (636:636:636) (664:664:664)) - (PORT datac (2169:2169:2169) (2244:2244:2244)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (2802:2802:2802) (3046:3046:3046)) - (PORT datab (2034:2034:2034) (2097:2097:2097)) - (PORT datac (180:180:180) (219:219:219)) - (PORT datad (615:615:615) (641:641:641)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1207:1207:1207) (1304:1304:1304)) - (PORT datab (2479:2479:2479) (2586:2586:2586)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (1030:1030:1030) (1119:1119:1119)) + (PORT datab (1732:1732:1732) (1813:1813:1813)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50345,12 +53050,381 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~4) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (857:857:857) (879:879:879)) - (PORT datad (230:230:230) (303:303:303)) + (PORT dataa (979:979:979) (1066:1066:1066)) + (PORT datab (1141:1141:1141) (1220:1220:1220)) + (PORT datac (778:778:778) (792:792:792)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1146:1146:1146)) + (PORT datab (948:948:948) (1043:1043:1043)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1357:1357:1357) (1395:1395:1395)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1118:1118:1118)) + (PORT datab (1168:1168:1168) (1239:1239:1239)) + (PORT datac (1107:1107:1107) (1139:1139:1139)) + (PORT datad (1421:1421:1421) (1463:1463:1463)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1122:1122:1122)) + (PORT datab (1409:1409:1409) (1443:1443:1443)) + (PORT datac (1673:1673:1673) (1756:1756:1756)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1224:1224:1224)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (343:343:343) (363:363:363)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1232:1232:1232)) + (PORT datab (1087:1087:1087) (1216:1216:1216)) + (PORT datac (1464:1464:1464) (1518:1518:1518)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (326:326:326) (354:354:354)) + (PORT datad (966:966:966) (988:988:988)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (939:939:939)) + (PORT datab (695:695:695) (785:785:785)) + (PORT datac (1864:1864:1864) (1894:1894:1894)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (801:801:801)) + (PORT datab (436:436:436) (517:517:517)) + (PORT datac (904:904:904) (914:914:914)) + (PORT datad (1393:1393:1393) (1424:1424:1424)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1732:1732:1732) (1780:1780:1780)) + (PORT datab (435:435:435) (517:517:517)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1458:1458:1458) (1558:1558:1558)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1265:1265:1265)) + (PORT datab (1232:1232:1232) (1270:1270:1270)) + (PORT datac (641:641:641) (719:719:719)) + (PORT datad (1704:1704:1704) (1749:1749:1749)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1572:1572:1572)) + (PORT datab (464:464:464) (535:535:535)) + (PORT datac (1721:1721:1721) (1844:1844:1844)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1500:1500:1500)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1265:1265:1265)) + (PORT datab (1412:1412:1412) (1444:1444:1444)) + (PORT datac (1142:1142:1142) (1173:1173:1173)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (2006:2006:2006) (2095:2095:2095)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1508:1508:1508)) + (PORT datab (1117:1117:1117) (1224:1224:1224)) + (PORT datac (1237:1237:1237) (1262:1262:1262)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (960:960:960)) + (PORT datab (710:710:710) (788:788:788)) + (PORT datad (882:882:882) (895:895:895)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (678:678:678)) + (PORT datab (706:706:706) (783:783:783)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (886:886:886) (916:916:916)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1843:1843:1843)) + (PORT datab (278:278:278) (366:366:366)) + (PORT datac (1458:1458:1458) (1518:1518:1518)) + (PORT datad (1522:1522:1522) (1592:1592:1592)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (682:682:682)) + (PORT datab (2520:2520:2520) (2611:2611:2611)) + (PORT datac (1179:1179:1179) (1223:1223:1223)) + (PORT datad (182:182:182) (214:214:214)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (1281:1281:1281) (1370:1370:1370)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1559:1559:1559)) + (PORT datab (695:695:695) (768:768:768)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (1342:1342:1342) (1380:1380:1380)) + (PORT datac (936:936:936) (973:973:973)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1508:1508:1508)) + (PORT datab (1185:1185:1185) (1226:1226:1226)) + (PORT datac (912:912:912) (953:953:953)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50362,12 +53436,12 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (706:706:706) (760:760:760)) - (PORT datac (668:668:668) (739:739:739)) - (PORT datad (617:617:617) (675:675:675)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (266:266:266) (354:354:354)) + (PORT datab (275:275:275) (362:362:362)) + (PORT datac (1225:1225:1225) (1299:1299:1299)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -50376,10 +53450,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50394,7 +53468,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (673:673:673) (730:730:730)) + (PORT datad (1405:1405:1405) (1466:1466:1466)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50404,10 +53478,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT clk (1518:1518:1518) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50422,10 +53496,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT asdata (569:569:569) (648:648:648)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT asdata (567:567:567) (647:647:647)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50440,9 +53514,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (915:915:915) (998:998:998)) - (PORT datab (253:253:253) (338:338:338)) - (PORT datad (224:224:224) (295:295:295)) + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (630:630:630) (703:703:703)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50455,10 +53529,10 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (249:249:249) (340:340:340)) - (PORT datab (259:259:259) (348:348:348)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (180:180:180) (210:210:210)) + (PORT dataa (580:580:580) (620:620:620)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (1090:1090:1090) (1162:1162:1162)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50489,9 +53563,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50505,7 +53579,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (406:406:406) (480:480:480)) + (PORT dataa (403:403:403) (479:479:479)) (PORT datab (251:251:251) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) @@ -50520,9 +53594,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50550,9 +53624,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50580,9 +53654,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50591,22 +53665,6 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (264:264:264) (347:347:347)) - (PORT datac (223:223:223) (302:302:302)) - (PORT datad (225:225:225) (297:297:297)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) @@ -50626,9 +53684,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50642,7 +53700,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -50653,9 +53711,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50664,47 +53722,45 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (235:235:235) (311:311:311)) + (PORT datad (224:224:224) (297:297:297)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (224:224:224) (305:305:305)) - (PORT datad (225:225:225) (295:295:295)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (222:222:222) (301:301:301)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) - (PORT ena (1023:1023:1023) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1902:1902:1902) (1923:1923:1923)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1414:1414:1414) (1389:1389:1389)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50719,7 +53775,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (410:410:410) (477:477:477)) + (PORT datad (256:256:256) (330:330:330)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50730,10 +53786,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1597:1597:1597) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50748,9 +53804,9 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (453:453:453) (522:522:522)) - (PORT datad (395:395:395) (465:465:465)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datab (282:282:282) (369:369:369)) + (PORT datad (286:286:286) (369:369:369)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50761,10 +53817,28 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) - (PORT ena (881:881:881) (820:820:820)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1597:1597:1597) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1902:1902:1902) (1923:1923:1923)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1414:1414:1414) (1389:1389:1389)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50779,9 +53853,9 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datab (455:455:455) (531:531:531)) - (PORT datac (266:266:266) (353:353:353)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (641:641:641) (716:716:716)) + (PORT datac (604:604:604) (665:665:665)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) @@ -50791,366 +53865,23 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (471:471:471) (542:542:542)) - (PORT datac (574:574:574) (630:630:630)) - (PORT datad (871:871:871) (934:934:934)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~4) - (DELAY - (ABSOLUTE - (PORT datad (701:701:701) (764:764:764)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (494:494:494)) - (PORT datab (652:652:652) (716:716:716)) - (PORT datad (718:718:718) (781:781:781)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT datab (472:472:472) (547:547:547)) + (PORT datad (730:730:730) (802:802:802)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (469:469:469) (541:541:541)) - (PORT datac (593:593:593) (652:652:652)) - (PORT datad (281:281:281) (362:362:362)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (605:605:605) (665:665:665)) - (PORT datac (628:628:628) (682:682:682)) - (PORT datad (856:856:856) (911:911:911)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (687:687:687)) - (PORT datab (642:642:642) (659:659:659)) - (PORT datac (634:634:634) (701:701:701)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1904:1904:1904) (1924:1924:1924)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1561:1561:1561)) - (PORT ena (1204:1204:1204) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (807:807:807)) - (PORT datad (388:388:388) (450:450:450)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1561:1561:1561)) - (PORT ena (1235:1235:1235) (1239:1239:1239)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (262:262:262) (351:351:351)) - (PORT datad (381:381:381) (445:445:445)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (456:456:456) (528:528:528)) - (PORT datac (269:269:269) (358:358:358)) - (PORT datad (668:668:668) (706:706:706)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT datab (473:473:473) (541:541:541)) - (PORT datac (595:595:595) (653:653:653)) - (PORT datad (282:282:282) (363:363:363)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT datab (457:457:457) (530:530:530)) - (PORT datac (268:268:268) (356:356:356)) - (PORT datad (336:336:336) (359:359:359)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (688:688:688) (708:708:708)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sload (875:875:875) (1000:1000:1000)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (809:809:809)) - (PORT datab (260:260:260) (350:350:350)) - (PORT datad (384:384:384) (449:449:449)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1561:1561:1561)) - (PORT ena (1235:1235:1235) (1239:1239:1239)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (407:407:407) (482:482:482)) - (PORT datac (887:887:887) (938:938:938)) - (PORT datad (236:236:236) (314:314:314)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (364:364:364)) - (PORT datab (308:308:308) (401:401:401)) - (PORT datac (572:572:572) (628:628:628)) - (PORT datad (619:619:619) (673:673:673)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (690:690:690)) - (PORT datab (661:661:661) (732:732:732)) - (PORT datac (627:627:627) (680:680:680)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (667:667:667)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (857:857:857) (913:913:913)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1927:1927:1927) (1950:1950:1950)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datac (668:668:668) (736:736:736)) - (PORT datad (436:436:436) (501:501:501)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (899:899:899) (962:962:962)) + (PORT datac (585:585:585) (643:643:643)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -51168,10 +53899,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (418:418:418) (494:494:494)) - (PORT datab (754:754:754) (826:826:826)) - (PORT datac (239:239:239) (316:316:316)) - (PORT datad (508:508:508) (502:502:502)) + (PORT dataa (430:430:430) (498:498:498)) + (PORT datab (473:473:473) (547:547:547)) + (PORT datac (261:261:261) (347:347:347)) + (PORT datad (682:682:682) (664:664:664)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51184,13 +53915,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (376:376:376)) - (PORT datab (646:646:646) (667:667:667)) - (PORT datac (618:618:618) (676:676:676)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (769:769:769) (848:848:848)) + (PORT datab (657:657:657) (677:677:677)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51200,11 +53931,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (712:712:712)) - (PORT datab (626:626:626) (641:641:641)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT datab (424:424:424) (497:497:497)) + (PORT datac (830:830:830) (829:829:829)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51214,28 +53945,386 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT asdata (689:689:689) (712:712:712)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (848:848:848)) + (PORT datab (474:474:474) (550:550:550)) + (PORT datad (280:280:280) (360:360:360)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (895:895:895) (965:965:965)) + (PORT datac (261:261:261) (349:349:349)) + (PORT datad (279:279:279) (359:359:359)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT datab (642:642:642) (706:706:706)) + (PORT datac (421:421:421) (491:491:491)) + (PORT datad (511:511:511) (521:521:521)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT datad (430:430:430) (498:498:498)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (716:716:716)) + (PORT datab (278:278:278) (365:365:365)) + (PORT datac (601:601:601) (663:663:663)) + (PORT datad (272:272:272) (354:354:354)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (528:528:528)) + (PORT datac (262:262:262) (350:350:350)) + (PORT datad (279:279:279) (355:355:355)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (269:269:269)) + (PORT datab (605:605:605) (620:620:620)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (725:725:725) (796:796:796)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (411:411:411)) + (PORT datab (280:280:280) (368:368:368)) + (PORT datac (609:609:609) (635:635:635)) + (PORT datad (800:800:800) (807:807:807)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (922:922:922) (904:904:904)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datad (254:254:254) (329:329:329)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (722:722:722)) + (PORT datac (605:605:605) (670:670:670)) + (PORT datad (539:539:539) (546:546:546)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (393:393:393)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (716:716:716) (747:747:747)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT sload (873:873:873) (990:990:990)) + (PORT ena (1439:1439:1439) (1421:1421:1421)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (458:458:458) (539:539:539)) + (PORT datad (252:252:252) (326:326:326)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (922:922:922) (904:904:904)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (512:512:512)) + (PORT datab (453:453:453) (536:536:536)) + (PORT datad (253:253:253) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (922:922:922) (904:904:904)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (275:275:275) (361:361:361)) + (PORT datac (386:386:386) (445:445:445)) + (PORT datad (422:422:422) (488:488:488)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (356:356:356)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (232:232:232) (316:316:316)) + (PORT datad (255:255:255) (331:331:331)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (443:443:443)) + (PORT datab (866:866:866) (912:912:912)) + (PORT datac (361:361:361) (382:382:382)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (850:850:850) (858:858:858)) + (PORT datad (272:272:272) (354:354:354)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT datab (471:471:471) (540:540:540)) - (PORT datac (593:593:593) (650:650:650)) - (PORT datad (278:278:278) (360:360:360)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT datab (900:900:900) (966:966:966)) + (PORT datac (263:263:263) (351:351:351)) + (PORT datad (280:280:280) (356:356:356)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51246,9 +54335,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (689:689:689)) - (PORT datab (639:639:639) (655:655:655)) - (PORT datad (175:175:175) (200:200:200)) + (PORT dataa (404:404:404) (444:444:444)) + (PORT datab (850:850:850) (858:858:858)) + (PORT datad (501:501:501) (512:512:512)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51261,9 +54350,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1927:1927:1927) (1950:1950:1950)) + (PORT clk (1534:1534:1534) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51277,12 +54366,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (362:362:362)) - (PORT datab (886:886:886) (951:951:951)) - (PORT datac (804:804:804) (848:848:848)) - (PORT datad (872:872:872) (930:930:930)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (642:642:642) (717:717:717)) + (PORT datab (260:260:260) (348:348:348)) + (PORT datac (605:605:605) (666:666:666)) + (PORT datad (278:278:278) (360:360:360)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51293,7 +54382,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (296:296:296) (389:389:389)) + (PORT datab (317:317:317) (418:418:418)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51302,13 +54391,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (655:655:655)) - (PORT datab (936:936:936) (980:980:980)) - (PORT datac (623:623:623) (676:676:676)) - (PORT datad (708:708:708) (690:690:690)) + (PORT dataa (620:620:620) (690:690:690)) + (PORT datab (453:453:453) (510:510:510)) + (PORT datac (729:729:729) (706:706:706)) + (PORT datad (375:375:375) (432:432:432)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51321,12 +54410,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (640:640:640)) - (PORT datab (457:457:457) (514:514:514)) - (PORT datac (786:786:786) (833:833:833)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (679:679:679) (741:741:741)) + (PORT datab (823:823:823) (820:820:820)) + (PORT datac (851:851:851) (907:907:907)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51337,11 +54426,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2650:2650:2650) (2671:2671:2671)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT asdata (2197:2197:2197) (2211:2211:2211)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51359,9 +54448,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (293:293:293) (394:394:394)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (289:289:289) (399:399:399)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51373,11 +54462,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2650:2650:2650) (2671:2671:2671)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT asdata (2197:2197:2197) (2211:2211:2211)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51395,9 +54484,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (412:412:412)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (301:301:301) (402:402:402)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51409,10 +54498,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51430,9 +54519,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (299:299:299) (395:395:395)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (289:289:289) (386:386:386)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51444,11 +54533,43 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2652:2652:2652) (2668:2668:2668)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT asdata (2198:2198:2198) (2213:2213:2213)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datad (276:276:276) (358:358:358)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1876:1876:1876) (1889:1889:1889)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51466,58 +54587,26 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (430:430:430) (520:520:520)) - (PORT datab (294:294:294) (394:394:394)) - (PORT datac (269:269:269) (375:375:375)) - (PORT datad (277:277:277) (359:359:359)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (295:295:295) (407:407:407)) + (PORT datab (304:304:304) (406:406:406)) + (PORT datac (295:295:295) (393:393:393)) + (PORT datad (263:263:263) (346:346:346)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (405:405:405)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (349:349:349) (374:374:374)) - (PORT datad (401:401:401) (464:464:464)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datac (612:612:612) (667:667:667)) + (PORT datad (502:502:502) (510:510:510)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51528,11 +54617,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (409:409:409) (485:485:485)) - (PORT datab (477:477:477) (546:546:546)) - (PORT datad (869:869:869) (920:920:920)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT datab (279:279:279) (368:368:368)) + (PORT datac (231:231:231) (315:315:315)) + (PORT datad (274:274:274) (356:356:356)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51542,13 +54631,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) (DELAY (ABSOLUTE - (PORT dataa (553:553:553) (572:572:572)) - (PORT datab (273:273:273) (357:357:357)) - (PORT datac (255:255:255) (340:340:340)) - (PORT datad (668:668:668) (704:704:704)) + (PORT dataa (225:225:225) (269:269:269)) + (PORT datab (305:305:305) (401:401:401)) + (PORT datac (231:231:231) (316:316:316)) + (PORT datad (541:541:541) (547:547:547)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51558,13 +54647,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (432:432:432) (515:515:515)) - (PORT datac (261:261:261) (346:346:346)) - (PORT datad (220:220:220) (258:258:258)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (866:866:866) (917:917:917)) + (PORT datac (367:367:367) (400:400:400)) + (PORT datad (263:263:263) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51574,11 +54663,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (910:910:910) (941:941:941)) - (PORT datab (630:630:630) (649:649:649)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (854:854:854) (863:863:863)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51589,9 +54678,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1534:1534:1534) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51605,11 +54694,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (249:249:249) (302:302:302)) - (PORT datab (274:274:274) (359:359:359)) - (PORT datad (405:405:405) (476:476:476)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (263:263:263) (356:356:356)) + (PORT datab (869:869:869) (918:918:918)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51620,10 +54709,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1534:1534:1534) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (1439:1439:1439) (1421:1421:1421)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51638,12 +54727,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (701:701:701) (768:768:768)) - (PORT datac (620:620:620) (679:679:679)) - (PORT datad (717:717:717) (779:779:779)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (298:298:298) (403:403:403)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datac (717:717:717) (801:801:801)) + (PORT datad (285:285:285) (372:372:372)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51654,10 +54743,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datac (617:617:617) (676:676:676)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (713:713:713) (796:796:796)) + (PORT datad (601:601:601) (618:618:618)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51669,9 +54758,9 @@ (DELAY (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) - (PORT d (958:958:958) (1002:1002:1002)) + (PORT d (993:993:993) (1024:1024:1024)) (PORT aload (1697:1697:1697) (1760:1760:1760)) - (PORT ena (723:723:723) (714:714:714)) + (PORT ena (873:873:873) (869:869:869)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -51688,368 +54777,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1902:1902:1902) (1923:1923:1923)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) - (PORT ena (1023:1023:1023) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (516:516:516)) - (PORT datab (290:290:290) (389:389:389)) - (PORT datac (264:264:264) (368:368:368)) - (PORT datad (275:275:275) (353:353:353)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (616:616:616) (672:672:672)) - (PORT datad (868:868:868) (917:917:917)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (517:517:517)) - (PORT datab (292:292:292) (393:393:393)) - (PORT datac (276:276:276) (370:370:370)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (419:419:419)) - (PORT datab (584:584:584) (592:592:592)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (269:269:269) (349:349:349)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (418:418:418)) - (PORT datab (294:294:294) (385:385:385)) - (PORT datac (278:278:278) (369:369:369)) - (PORT datad (274:274:274) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (586:586:586)) - (PORT datab (293:293:293) (393:393:393)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (269:269:269) (349:349:349)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (493:493:493) (580:580:580)) - (PORT datac (679:679:679) (744:744:744)) - (PORT datad (662:662:662) (723:723:723)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT datab (280:280:280) (368:368:368)) - (PORT datac (265:265:265) (353:353:353)) - (PORT datad (417:417:417) (491:491:491)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (365:365:365) (400:400:400)) - (PORT datac (264:264:264) (352:352:352)) - (PORT datad (215:215:215) (253:253:253)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (936:936:936)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (410:410:410) (480:480:480)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sclr (1298:1298:1298) (1370:1370:1370)) - (PORT ena (949:949:949) (938:938:938)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sclr (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) - (DELAY - (ABSOLUTE - (PORT datab (629:629:629) (656:656:656)) - (PORT datac (457:457:457) (542:542:542)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (516:516:516)) - (PORT datab (365:365:365) (396:396:396)) - (PORT datac (266:266:266) (352:352:352)) - (PORT datad (420:420:420) (487:487:487)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (300:300:300)) - (PORT datab (281:281:281) (369:369:369)) - (PORT datac (258:258:258) (346:346:346)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (940:940:940)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (409:409:409) (478:478:478)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (649:649:649)) - (PORT datac (456:456:456) (542:542:542)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (418:418:418)) - (PORT datab (293:293:293) (393:393:393)) - (PORT datac (277:277:277) (370:370:370)) - (PORT datad (274:274:274) (355:355:355)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (418:418:418)) - (PORT datac (279:279:279) (373:373:373)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (625:625:625)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (681:681:681) (740:740:740)) - (PORT datad (662:662:662) (720:720:720)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (334:334:334)) - (PORT datab (831:831:831) (881:881:881)) - (PORT datac (460:460:460) (539:539:539)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1414:1414:1414) (1389:1389:1389)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52064,12 +54795,40 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (303:303:303) (418:418:418)) - (PORT datab (295:295:295) (395:395:395)) - (PORT datac (277:277:277) (371:371:371)) - (PORT datad (270:270:270) (351:351:351)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT datac (270:270:270) (367:367:367)) + (PORT datad (274:274:274) (356:356:356)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (398:398:398)) + (PORT datab (295:295:295) (399:399:399)) + (PORT datac (281:281:281) (381:381:381)) + (PORT datad (274:274:274) (352:352:352)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (644:644:644)) + (PORT datab (722:722:722) (794:794:794)) + (PORT datac (687:687:687) (752:752:752)) + (PORT datad (481:481:481) (496:496:496)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52080,12 +54839,138 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT dataa (687:687:687) (761:761:761)) - (PORT datab (657:657:657) (669:669:669)) - (PORT datac (679:679:679) (740:740:740)) - (PORT datad (329:329:329) (349:349:349)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (293:293:293) (405:405:405)) + (PORT datab (424:424:424) (496:496:496)) + (PORT datac (269:269:269) (371:371:371)) + (PORT datad (274:274:274) (356:356:356)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (643:643:643)) + (PORT datab (720:720:720) (794:794:794)) + (PORT datac (684:684:684) (752:752:752)) + (PORT datad (601:601:601) (611:611:611)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (861:861:861)) + (PORT datab (721:721:721) (793:793:793)) + (PORT datac (685:685:685) (751:751:751)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (406:406:406)) + (PORT datab (766:766:766) (836:836:836)) + (PORT datac (714:714:714) (799:799:799)) + (PORT datad (351:351:351) (380:380:380)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (317:317:317) (417:417:417)) + (PORT datac (565:565:565) (610:610:610)) + (PORT datad (801:801:801) (810:810:810)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1184:1184:1184) (1287:1287:1287)) + (PORT ena (1162:1162:1162) (1136:1136:1136)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (384:384:384)) + (PORT datab (304:304:304) (407:407:407)) + (PORT datac (293:293:293) (394:394:394)) + (PORT datad (273:273:273) (353:353:353)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~6) + (DELAY + (ABSOLUTE + (PORT datab (288:288:288) (379:379:379)) + (PORT datad (274:274:274) (357:357:357)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (821:821:821) (843:843:843)) + (PORT datac (294:294:294) (392:392:392)) + (PORT datad (265:265:265) (361:361:361)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52093,20 +54978,196 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) (DELAY (ABSOLUTE (PORT dataa (247:247:247) (335:335:335)) - (PORT datab (832:832:832) (884:884:884)) - (PORT datac (457:457:457) (542:542:542)) - (PORT datad (174:174:174) (200:200:200)) + (PORT datac (740:740:740) (820:820:820)) + (PORT datad (603:603:603) (613:613:613)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (401:401:401)) + (PORT datab (768:768:768) (833:833:833)) + (PORT datac (584:584:584) (638:638:638)) + (PORT datad (352:352:352) (377:377:377)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (751:751:751) (835:835:835)) + (PORT datac (607:607:607) (633:633:633)) + (PORT datad (728:728:728) (792:792:792)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (374:374:374) (395:395:395)) + (PORT datac (830:830:830) (829:829:829)) + (PORT datad (397:397:397) (458:458:458)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (408:408:408)) + (PORT datab (425:425:425) (497:497:497)) + (PORT datac (295:295:295) (393:393:393)) + (PORT datad (276:276:276) (358:358:358)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (303:303:303) (409:409:409)) + (PORT datac (292:292:292) (395:395:395)) + (PORT datad (813:813:813) (819:819:819)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (329:329:329)) + (PORT datac (744:744:744) (817:817:817)) + (PORT datad (774:774:774) (767:767:767)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (861:861:861)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (685:685:685) (758:758:758)) + (PORT datad (220:220:220) (289:289:289)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (860:860:860)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (688:688:688) (758:758:758)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) @@ -52115,7 +55176,7 @@ (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52127,14 +55188,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (656:656:656)) - (PORT datab (622:622:622) (686:686:686)) - (PORT datad (360:360:360) (411:411:411)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (295:295:295) (407:407:407)) + (PORT datab (304:304:304) (405:405:405)) + (PORT datac (295:295:295) (392:392:392)) + (PORT datad (263:263:263) (346:346:346)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (471:471:471)) + (PORT datab (751:751:751) (813:813:813)) + (PORT datad (782:782:782) (790:790:790)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52144,11 +55221,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1556:1556:1556)) - (PORT sload (1218:1218:1218) (1319:1319:1319)) - (PORT ena (1180:1180:1180) (1175:1175:1175)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT sload (1423:1423:1423) (1516:1516:1516)) + (PORT ena (1250:1250:1250) (1250:1250:1250)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52162,14 +55239,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (637:637:637) (656:656:656)) - (PORT datac (454:454:454) (537:537:537)) - (PORT datad (386:386:386) (445:445:445)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (417:417:417) (477:477:477)) + (PORT datac (744:744:744) (821:821:821)) + (PORT datad (970:970:970) (970:970:970)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52182,8 +55259,8 @@ (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sclr (1298:1298:1298) (1370:1370:1370)) - (PORT ena (961:961:961) (968:968:968)) + (PORT sclr (1184:1184:1184) (1287:1287:1287)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52196,11 +55273,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~7) (DELAY (ABSOLUTE - (PORT datac (461:461:461) (545:545:545)) - (PORT datad (221:221:221) (290:290:290)) + (PORT datac (745:745:745) (818:818:818)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52214,8 +55291,8 @@ (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sclr (1298:1298:1298) (1370:1370:1370)) - (PORT ena (949:949:949) (938:938:938)) + (PORT sclr (1184:1184:1184) (1287:1287:1287)) + (PORT ena (1162:1162:1162) (1136:1136:1136)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52231,10 +55308,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (674:674:674) (733:733:733)) - (PORT datab (883:883:883) (952:952:952)) - (PORT datac (406:406:406) (468:468:468)) - (PORT datad (869:869:869) (932:932:932)) + (PORT dataa (693:693:693) (748:748:748)) + (PORT datab (313:313:313) (408:408:408)) + (PORT datac (668:668:668) (727:727:727)) + (PORT datad (728:728:728) (790:790:790)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -52247,10 +55324,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (381:381:381)) - (PORT datab (755:755:755) (824:824:824)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (507:507:507) (501:501:501)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (315:315:315) (415:415:415)) + (PORT datac (602:602:602) (622:622:622)) + (PORT datad (503:503:503) (496:496:496)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -52263,13 +55340,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (758:758:758) (822:822:822)) - (PORT datac (668:668:668) (731:731:731)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (299:299:299) (404:404:404)) + (PORT datab (313:313:313) (414:414:414)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52279,13 +55356,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (758:758:758) (822:822:822)) - (PORT datac (668:668:668) (732:732:732)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (298:298:298) (404:404:404)) + (PORT datab (314:314:314) (415:415:415)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52295,12 +55372,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (894:894:894)) - (PORT datab (231:231:231) (274:274:274)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (632:632:632) (664:664:664)) + (PORT datab (752:752:752) (836:836:836)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52313,8 +55390,8 @@ (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) (PORT d (691:691:691) (730:730:730)) - (PORT aload (1698:1698:1698) (1763:1763:1763)) - (PORT ena (942:942:942) (938:938:938)) + (PORT aload (1710:1710:1710) (1775:1775:1775)) + (PORT ena (1322:1322:1322) (1330:1330:1330)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52346,12 +55423,232 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux38\~0) + (INSTANCE sdram_\|Mux4\~3) (DELAY (ABSOLUTE - (PORT dataa (1565:1565:1565) (1641:1641:1641)) - (PORT datab (1300:1300:1300) (1343:1343:1343)) - (PORT datad (181:181:181) (212:212:212)) + (PORT dataa (731:731:731) (831:831:831)) + (PORT datac (670:670:670) (753:753:753)) + (PORT datad (683:683:683) (770:770:770)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1182:1182:1182)) + (PORT datac (1108:1108:1108) (1223:1223:1223)) + (PORT datad (1073:1073:1073) (1190:1190:1190)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1200:1200:1200)) + (PORT datac (1012:1012:1012) (1103:1103:1103)) + (PORT datad (1262:1262:1262) (1351:1351:1351)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1073:1073:1073)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1195:1195:1195) (1282:1282:1282)) + (PORT datad (1327:1327:1327) (1435:1435:1435)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (1085:1085:1085) (1193:1193:1193)) + (PORT datad (1034:1034:1034) (1129:1129:1129)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1480:1480:1480)) + (PORT datad (1211:1211:1211) (1299:1299:1299)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (1534:1534:1534) (1598:1598:1598)) + (PORT ena (821:821:821) (835:835:835)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (1034:1034:1034) (1068:1068:1068)) + (PORT ena (821:821:821) (835:835:835)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (764:764:764)) + (PORT datab (1222:1222:1222) (1288:1288:1288)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (3176:3176:3176) (3259:3259:3259)) + (PORT ena (821:821:821) (835:835:835)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1403:1403:1403)) + (PORT datab (1103:1103:1103) (1236:1236:1236)) + (PORT datac (1105:1105:1105) (1223:1223:1223)) + (PORT datad (1590:1590:1590) (1708:1708:1708)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1191:1191:1191)) + (PORT datac (909:909:909) (923:923:923)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1007:1007:1007)) + (PORT datab (1478:1478:1478) (1547:1547:1547)) + (PORT datad (321:321:321) (336:336:336)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1499:1499:1499)) + (PORT datab (951:951:951) (1038:1038:1038)) + (PORT datac (1543:1543:1543) (1657:1657:1657)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1058:1058:1058)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (321:321:321) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -52364,7 +55661,7 @@ (INSTANCE sdram_\|r\.rd_pending) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) + (PORT clk (1532:1532:1532) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -52373,12 +55670,162 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2867:2867:2867) (2954:2954:2954)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (446:446:446) (526:526:526)) + (PORT datad (682:682:682) (745:745:745)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1076:1076:1076)) + (PORT datab (1060:1060:1060) (1162:1162:1162)) + (PORT datac (1168:1168:1168) (1176:1176:1176)) + (PORT datad (1262:1262:1262) (1353:1353:1353)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (900:900:900)) + (PORT datab (222:222:222) (262:262:262)) + (PORT datac (1012:1012:1012) (1106:1106:1106)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT datab (958:958:958) (1039:1039:1039)) + (PORT datac (1057:1057:1057) (1164:1164:1164)) + (PORT datad (1329:1329:1329) (1435:1435:1435)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1145:1145:1145)) + (PORT datab (1004:1004:1004) (1086:1086:1086)) + (PORT datac (1057:1057:1057) (1164:1164:1164)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1073:1073:1073)) + (PORT datab (1061:1061:1061) (1161:1161:1161)) + (PORT datac (1166:1166:1166) (1172:1172:1172)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (942:942:942)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (853:853:853) (876:876:876)) + (PORT datad (830:830:830) (856:856:856)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1558:1558:1558)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datac (1633:1633:1633) (1743:1743:1743)) + (PORT datad (1538:1538:1538) (1626:1626:1626)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52387,16 +55834,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (INSTANCE sdram_\|r\.rf_counter\[8\]\~32) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (969:969:969) (1051:1051:1051)) - (PORT datac (661:661:661) (684:684:684)) - (PORT datad (1347:1347:1347) (1447:1447:1447)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (405:405:405) (430:430:430)) + (PORT datab (681:681:681) (747:747:747)) + (PORT datac (1633:1633:1633) (1743:1743:1743)) + (PORT datad (1538:1538:1538) (1627:1627:1627)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52422,9 +55869,9 @@ (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (251:251:251) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52452,7 +55899,7 @@ (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (335:335:335)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52482,7 +55929,7 @@ (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) + (PORT dataa (253:253:253) (345:345:345)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52507,14 +55954,30 @@ (HOLD sclr (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (225:225:225) (306:306:306)) + (PORT datad (226:226:226) (300:300:300)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (336:336:336)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (253:253:253) (346:346:346)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52542,9 +56005,9 @@ (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (337:337:337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52572,9 +56035,9 @@ (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52627,22 +56090,6 @@ (HOLD sclr (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) @@ -52673,29 +56120,13 @@ (HOLD sclr (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (347:347:347)) - (PORT datab (254:254:254) (340:340:340)) - (PORT datac (226:226:226) (306:306:306)) - (PORT datad (228:228:228) (300:300:300)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (254:254:254) (344:344:344)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -52718,29 +56149,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~2) + (INSTANCE sdram_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (374:374:374)) - (PORT datab (252:252:252) (336:336:336)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (224:224:224) (303:303:303)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~8) + (INSTANCE sdram_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT datab (1384:1384:1384) (1487:1487:1487)) - (PORT datac (941:941:941) (1018:1018:1018)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (225:225:225) (307:307:307)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52749,11 +56184,11 @@ (INSTANCE sdram_\|Mux37\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (688:688:688) (717:717:717)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (680:680:680) (746:746:746)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52775,32 +56210,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~0) + (INSTANCE sdram_\|Mux4\~1) (DELAY (ABSOLUTE - (PORT dataa (774:774:774) (867:867:867)) - (PORT datab (765:765:765) (851:851:851)) - (PORT datac (642:642:642) (726:726:726)) - (PORT datad (862:862:862) (889:889:889)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (919:919:919) (1022:1022:1022)) + (PORT datab (998:998:998) (1094:1094:1094)) + (PORT datac (875:875:875) (937:937:937)) + (PORT datad (994:994:994) (1084:1084:1084)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~1) + (INSTANCE sdram_\|Mux4\~4) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (928:928:928)) - (PORT datab (1028:1028:1028) (1104:1104:1104)) - (PORT datac (1269:1269:1269) (1392:1392:1392)) - (PORT datad (571:571:571) (585:585:585)) + (PORT dataa (1278:1278:1278) (1401:1401:1401)) + (PORT datab (1139:1139:1139) (1253:1253:1253)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (815:815:815) (830:830:830)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52810,12 +56245,12 @@ (INSTANCE sdram_\|Mux4\~2) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (928:928:928)) - (PORT datab (1028:1028:1028) (1103:1103:1103)) - (PORT datac (1269:1269:1269) (1391:1391:1391)) - (PORT datad (571:571:571) (585:585:585)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (294:294:294) (384:384:384)) + (PORT datab (283:283:283) (371:371:371)) + (PORT datac (1791:1791:1791) (1881:1881:1881)) + (PORT datad (262:262:262) (345:345:345)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52823,14 +56258,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~3) + (INSTANCE sdram_\|Mux4\~5) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (305:305:305) (398:398:398)) - (PORT datad (604:604:604) (636:636:636)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (647:647:647) (683:683:683)) + (PORT datab (908:908:908) (966:966:966)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52841,7 +56276,7 @@ (INSTANCE sdram_\|r\.state\[8\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -52852,13 +56287,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (INSTANCE sdram_\|process_0\~4) (DELAY (ABSOLUTE - (PORT dataa (1303:1303:1303) (1433:1433:1433)) - (PORT datab (1067:1067:1067) (1184:1184:1184)) - (PORT datac (1412:1412:1412) (1458:1458:1458)) - (PORT datad (995:995:995) (1084:1084:1084)) + (PORT datac (233:233:233) (309:309:309)) + (PORT datad (244:244:244) (314:314:314)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1087:1087:1087)) + (PORT datab (1106:1106:1106) (1205:1205:1205)) + (PORT datac (970:970:970) (1046:1046:1046)) + (PORT datad (1369:1369:1369) (1431:1431:1431)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52868,113 +56315,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~2) + (INSTANCE sdram_\|r\.act_row\[2\]\~1) (DELAY (ABSOLUTE - (PORT datac (264:264:264) (345:345:345)) - (PORT datad (285:285:285) (364:364:364)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (364:364:364) (399:399:399)) - (PORT datac (1029:1029:1029) (1132:1132:1132)) - (PORT datad (996:996:996) (1087:1087:1087)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1326:1326:1326) (1408:1408:1408)) + (PORT datab (1550:1550:1550) (1647:1647:1647)) + (PORT datac (1152:1152:1152) (1221:1221:1221)) + (PORT datad (610:610:610) (651:651:651)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (966:966:966) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (1576:1576:1576) (1606:1606:1606)) - (PORT ena (966:966:966) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1215:1215:1215) (1258:1258:1258)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (966:966:966) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1305:1305:1305)) - (PORT datab (1250:1250:1250) (1293:1293:1293)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.act_row\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (1323:1323:1323) (1390:1390:1390)) - (PORT ena (966:966:966) (964:964:964)) + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (2174:2174:2174) (2294:2294:2294)) + (PORT ena (821:821:821) (835:835:835)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -52988,9 +56350,9 @@ (INSTANCE sdram_\|r\.act_row\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (3043:3043:3043) (3212:3212:3212)) - (PORT ena (966:966:966) (964:964:964)) + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (1310:1310:1310) (1369:1369:1369)) + (PORT ena (821:821:821) (835:835:835)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53004,9 +56366,9 @@ (INSTANCE sdram_\|Equal7\~0) (DELAY (ABSOLUTE - (PORT dataa (2732:2732:2732) (2911:2911:2911)) - (PORT datab (1007:1007:1007) (1081:1081:1081)) - (PORT datad (216:216:216) (284:284:284)) + (PORT dataa (1192:1192:1192) (1253:1253:1253)) + (PORT datab (1857:1857:1857) (1985:1985:1985)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53019,114 +56381,11 @@ (INSTANCE sdram_\|Equal7\~2) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (468:468:468)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1442:1442:1442) (1496:1496:1496)) - (PORT datab (1034:1034:1034) (1124:1124:1124)) - (PORT datac (1028:1028:1028) (1131:1131:1131)) - (PORT datad (1030:1030:1030) (1145:1145:1145)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1281:1281:1281) (1388:1388:1388)) - (PORT datac (582:582:582) (600:600:600)) - (PORT datad (340:340:340) (361:361:361)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (253:253:253)) - (PORT datab (661:661:661) (681:681:681)) - (PORT datad (1354:1354:1354) (1381:1381:1381)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.wr_pending) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~8) - (DELAY - (ABSOLUTE - (PORT datac (1172:1172:1172) (1258:1258:1258)) - (PORT datad (1054:1054:1054) (1165:1165:1165)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~9) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (522:522:522)) - (PORT datab (614:614:614) (638:638:638)) - (PORT datac (668:668:668) (744:744:744)) - (PORT datad (286:286:286) (365:365:365)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux6\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1283:1283:1283) (1389:1389:1389)) - (PORT datab (311:311:311) (401:401:401)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (2866:2866:2866) (2957:2957:2957)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (225:225:225) (297:297:297)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53138,11 +56397,55 @@ (INSTANCE sdram_\|Mux6\~4) (DELAY (ABSOLUTE - (PORT datab (692:692:692) (771:771:771)) - (PORT datac (580:580:580) (597:597:597)) - (PORT datad (1249:1249:1249) (1337:1337:1337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (952:952:952) (1004:1004:1004)) + (PORT datab (785:785:785) (882:882:882)) + (PORT datad (1092:1092:1092) (1198:1198:1198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1045:1045:1045)) + (PORT datab (783:783:783) (878:878:878)) + (PORT datac (910:910:910) (981:981:981)) + (PORT datad (919:919:919) (953:953:953)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT datac (1128:1128:1128) (1241:1241:1241)) + (PORT datad (1196:1196:1196) (1268:1268:1268)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1133:1133:1133) (1245:1245:1245)) + (PORT datac (906:906:906) (1006:1006:1006)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53152,11 +56455,11 @@ (INSTANCE sdram_\|Mux6\~2) (DELAY (ABSOLUTE - (PORT dataa (1279:1279:1279) (1385:1385:1385)) - (PORT datac (1172:1172:1172) (1258:1258:1258)) - (PORT datad (1055:1055:1055) (1166:1166:1166)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1224:1224:1224) (1309:1309:1309)) + (PORT datac (1125:1125:1125) (1235:1235:1235)) + (PORT datad (1099:1099:1099) (1205:1205:1205)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53166,10 +56469,10 @@ (INSTANCE sdram_\|Mux6\~5) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (969:969:969) (1043:1043:1043)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (962:962:962) (1084:1084:1084)) + (PORT datad (175:175:175) (202:202:202)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -53179,13 +56482,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~3) + (INSTANCE sdram_\|process_0\~2) (DELAY (ABSOLUTE - (PORT dataa (900:900:900) (988:988:988)) - (PORT datac (793:793:793) (832:832:832)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (784:784:784) (878:878:878)) + (PORT datad (919:919:919) (952:952:952)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53194,10 +56497,10 @@ (INSTANCE sdram_\|Mux6\~0) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (388:388:388)) - (PORT datab (724:724:724) (811:811:811)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (738:738:738) (805:805:805)) + (PORT dataa (944:944:944) (1046:1046:1046)) + (PORT datab (1159:1159:1159) (1273:1273:1273)) + (PORT datac (196:196:196) (240:240:240)) + (PORT datad (1195:1195:1195) (1269:1269:1269)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -53210,12 +56513,12 @@ (INSTANCE sdram_\|Mux6\~1) (DELAY (ABSOLUTE - (PORT dataa (283:283:283) (378:378:378)) - (PORT datab (299:299:299) (395:395:395)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (739:739:739) (807:807:807)) + (PORT dataa (740:740:740) (835:835:835)) + (PORT datab (1533:1533:1533) (1632:1632:1632)) + (PORT datac (619:619:619) (663:663:663)) + (PORT datad (683:683:683) (774:774:774)) (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53226,10 +56529,10 @@ (INSTANCE sdram_\|Mux6\~6) (DELAY (ABSOLUTE - (PORT datab (304:304:304) (399:399:399)) - (PORT datac (605:605:605) (644:644:644)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (291:291:291) (389:389:389)) + (PORT datac (929:929:929) (943:943:943)) + (PORT datad (593:593:593) (622:622:622)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53240,7 +56543,7 @@ (INSTANCE sdram_\|r\.state\[6\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53251,160 +56554,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~6) + (INSTANCE sdram_\|Mux5\~7) (DELAY (ABSOLUTE - (PORT dataa (1305:1305:1305) (1435:1435:1435)) - (PORT datac (1028:1028:1028) (1132:1132:1132)) - (PORT datad (990:990:990) (1085:1085:1085)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~2) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (628:628:628)) - (PORT datab (1461:1461:1461) (1510:1510:1510)) - (PORT datac (668:668:668) (746:746:746)) - (PORT datad (1051:1051:1051) (1164:1164:1164)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~3) - (DELAY - (ABSOLUTE - (PORT datab (828:828:828) (934:934:934)) - (PORT datac (781:781:781) (892:892:892)) - (PORT datad (869:869:869) (909:909:909)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~3) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1007:1007:1007)) - (PORT datab (297:297:297) (391:391:391)) - (PORT datad (739:739:739) (802:802:802)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~4) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (297:297:297) (388:388:388)) - (PORT datac (870:870:870) (951:951:951)) - (PORT datad (275:275:275) (355:355:355)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~5) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (963:963:963)) - (PORT datab (300:300:300) (396:396:396)) - (PORT datac (690:690:690) (777:777:777)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~0) - (DELAY - (ABSOLUTE - (PORT datab (992:992:992) (1065:1065:1065)) - (PORT datac (1256:1256:1256) (1350:1350:1350)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~7) - (DELAY - (ABSOLUTE - (PORT datac (1261:1261:1261) (1385:1385:1385)) - (PORT datad (986:986:986) (1059:1059:1059)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~10) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (958:958:958)) - (PORT datab (995:995:995) (1070:1070:1070)) - (PORT datac (1256:1256:1256) (1357:1357:1357)) - (PORT datad (685:685:685) (768:768:768)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (450:450:450)) - (PORT datab (382:382:382) (407:407:407)) - (PORT datac (1029:1029:1029) (1106:1106:1106)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~6) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (830:830:830)) - (PORT datab (344:344:344) (369:369:369)) - (PORT datac (259:259:259) (349:349:349)) - (PORT datad (838:838:838) (843:843:843)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (996:996:996) (1079:1079:1079)) + (PORT datab (957:957:957) (1040:1040:1040)) + (PORT datac (1234:1234:1234) (1333:1333:1333)) + (PORT datad (1261:1261:1261) (1354:1354:1354)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53412,28 +56569,30 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.state\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1089:1089:1089) (1196:1196:1196)) + (PORT datab (1065:1065:1065) (1151:1151:1151)) + (PORT datac (953:953:953) (1030:1030:1030)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux5\~2) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (401:401:401)) - (PORT datab (1287:1287:1287) (1386:1386:1386)) - (PORT datac (961:961:961) (1031:1031:1031)) - (PORT datad (347:347:347) (368:368:368)) + (PORT dataa (1304:1304:1304) (1399:1399:1399)) + (PORT datab (1096:1096:1096) (1202:1202:1202)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (359:359:359) (379:379:379)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -53446,13 +56605,13 @@ (INSTANCE sdram_\|Mux5\~10) (DELAY (ABSOLUTE - (PORT dataa (777:777:777) (870:870:870)) - (PORT datab (765:765:765) (853:853:853)) - (PORT datac (766:766:766) (877:877:877)) - (PORT datad (675:675:675) (776:776:776)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1294:1294:1294) (1397:1397:1397)) + (PORT datab (1092:1092:1092) (1200:1200:1200)) + (PORT datac (966:966:966) (1059:1059:1059)) + (PORT datad (998:998:998) (1081:1081:1081)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53462,13 +56621,13 @@ (INSTANCE sdram_\|Mux5\~3) (DELAY (ABSOLUTE - (PORT dataa (801:801:801) (923:923:923)) - (PORT datab (1024:1024:1024) (1102:1102:1102)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1232:1232:1232) (1336:1336:1336)) + (PORT datab (229:229:229) (269:269:269)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1058:1058:1058) (1167:1167:1167)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53478,45 +56637,13 @@ (INSTANCE sdram_\|Mux5\~4) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (389:389:389)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1262:1262:1262) (1383:1383:1383)) - (PORT datad (711:711:711) (805:805:805)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~7) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (388:388:388)) - (PORT datab (775:775:775) (845:845:845)) - (PORT datac (870:870:870) (953:953:953)) - (PORT datad (889:889:889) (964:964:964)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~8) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (297:297:297) (392:392:392)) - (PORT datac (689:689:689) (775:775:775)) - (PORT datad (275:275:275) (357:357:357)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1336:1336:1336) (1448:1448:1448)) + (PORT datab (1074:1074:1074) (1178:1178:1178)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53526,12 +56653,12 @@ (INSTANCE sdram_\|Mux5\~5) (DELAY (ABSOLUTE - (PORT dataa (932:932:932) (1011:1011:1011)) - (PORT datab (726:726:726) (812:812:812)) - (PORT datac (796:796:796) (836:836:836)) - (PORT datad (274:274:274) (354:354:354)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (937:937:937) (1019:1019:1019)) + (PORT datab (693:693:693) (785:785:785)) + (PORT datac (997:997:997) (1113:1113:1113)) + (PORT datad (923:923:923) (959:959:959)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53542,13 +56669,13 @@ (INSTANCE sdram_\|Mux5\~6) (DELAY (ABSOLUTE - (PORT dataa (431:431:431) (511:511:511)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (631:631:631) (672:672:672)) - (PORT datad (914:914:914) (945:945:945)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datac (194:194:194) (236:236:236)) + (PORT datad (1098:1098:1098) (1204:1204:1204)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53558,13 +56685,13 @@ (INSTANCE sdram_\|Mux5\~9) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (379:379:379)) - (PORT datab (669:669:669) (707:707:707)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1189:1189:1189) (1188:1188:1188)) + (PORT datab (281:281:281) (370:370:370)) + (PORT datac (853:853:853) (886:886:886)) + (PORT datad (857:857:857) (902:902:902)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53574,7 +56701,7 @@ (INSTANCE sdram_\|r\.state\[7\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53588,64 +56715,98 @@ (INSTANCE sdram_\|n\~2) (DELAY (ABSOLUTE - (PORT datab (1023:1023:1023) (1112:1112:1112)) - (PORT datac (948:948:948) (1070:1070:1070)) - (PORT datad (994:994:994) (1080:1080:1080)) + (PORT datab (999:999:999) (1093:1093:1093)) + (PORT datac (887:887:887) (982:982:982)) + (PORT datad (994:994:994) (1083:1083:1083)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (675:675:675)) + (PORT datab (889:889:889) (983:983:983)) + (PORT datac (928:928:928) (1008:1008:1008)) + (PORT datad (1516:1516:1516) (1584:1584:1584)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (961:961:961) (1037:1037:1037)) + (PORT datac (929:929:929) (1006:1006:1006)) + (PORT datad (1515:1515:1515) (1583:1583:1583)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1046:1046:1046)) + (PORT datab (809:809:809) (911:911:911)) + (PORT datac (862:862:862) (953:953:953)) + (PORT datad (742:742:742) (849:849:849)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (894:894:894)) + (PORT datab (214:214:214) (260:260:260)) + (PORT datac (928:928:928) (1002:1002:1002)) + (PORT datad (612:612:612) (632:632:632)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux8\~3) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (396:396:396)) - (PORT datab (1264:1264:1264) (1347:1347:1347)) - (PORT datac (1576:1576:1576) (1655:1655:1655)) - (PORT datad (1570:1570:1570) (1693:1693:1693)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (773:773:773) (894:894:894)) + (PORT datab (214:214:214) (260:260:260)) + (PORT datac (849:849:849) (870:870:870)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1517:1517:1517)) - (PORT datab (1478:1478:1478) (1602:1602:1602)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1253:1253:1253) (1313:1313:1313)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~10) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1172:1172:1172) (1258:1258:1258)) - (PORT datad (1055:1055:1055) (1165:1165:1165)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (INSTANCE sdram_\|r\.init_counter\[0\]\~44) (DELAY (ABSOLUTE (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53657,7 +56818,7 @@ (INSTANCE sdram_\|r\.init_counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1561:1561:1561)) + (PORT clk (1530:1530:1530) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53668,20 +56829,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~1) + (INSTANCE sdram_\|r\.init_counter\[1\]\~15) (DELAY (ABSOLUTE - (PORT datab (734:734:734) (825:825:825)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (409:409:409) (485:485:485)) + (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~2) + (INSTANCE sdram_\|r\.init_counter\[1\]\~16) (DELAY (ABSOLUTE - (PORT datab (282:282:282) (364:364:364)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53695,7 +56856,7 @@ (INSTANCE sdram_\|r\.init_counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53706,7 +56867,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~4) + (INSTANCE sdram_\|r\.init_counter\[2\]\~18) (DELAY (ABSOLUTE (PORT dataa (264:264:264) (351:351:351)) @@ -53723,7 +56884,7 @@ (INSTANCE sdram_\|r\.init_counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53734,34 +56895,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~6) + (INSTANCE sdram_\|r\.init_counter\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (437:437:437) (497:497:497)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (263:263:263) (345:345:345)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (345:345:345) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.init_counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53772,7 +56923,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~8) + (INSTANCE sdram_\|r\.init_counter\[4\]\~22) (DELAY (ABSOLUTE (PORT dataa (265:265:265) (353:353:353)) @@ -53789,7 +56940,7 @@ (INSTANCE sdram_\|r\.init_counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53800,7 +56951,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~10) + (INSTANCE sdram_\|r\.init_counter\[5\]\~24) (DELAY (ABSOLUTE (PORT dataa (265:265:265) (353:353:353)) @@ -53817,7 +56968,7 @@ (INSTANCE sdram_\|r\.init_counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53828,7 +56979,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~12) + (INSTANCE sdram_\|r\.init_counter\[6\]\~26) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -53845,7 +56996,7 @@ (INSTANCE sdram_\|r\.init_counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53856,10 +57007,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~14) + (INSTANCE sdram_\|r\.init_counter\[7\]\~28) (DELAY (ABSOLUTE - (PORT datab (284:284:284) (367:367:367)) + (PORT datab (264:264:264) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53873,7 +57024,7 @@ (INSTANCE sdram_\|r\.init_counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53884,7 +57035,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~16) + (INSTANCE sdram_\|r\.init_counter\[8\]\~30) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -53901,7 +57052,7 @@ (INSTANCE sdram_\|r\.init_counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53912,10 +57063,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~18) + (INSTANCE sdram_\|r\.init_counter\[9\]\~32) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) + (PORT datab (251:251:251) (336:336:336)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53929,7 +57080,7 @@ (INSTANCE sdram_\|r\.init_counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53940,10 +57091,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~20) + (INSTANCE sdram_\|r\.init_counter\[10\]\~34) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (352:352:352)) + (PORT dataa (252:252:252) (342:342:342)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53957,7 +57108,7 @@ (INSTANCE sdram_\|r\.init_counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53968,37 +57119,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (496:496:496)) - (PORT datab (447:447:447) (515:515:515)) - (PORT datac (387:387:387) (456:456:456)) - (PORT datad (407:407:407) (472:472:472)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (449:449:449) (514:514:514)) - (PORT datac (416:416:416) (481:481:481)) - (PORT datad (244:244:244) (315:315:315)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~22) + (INSTANCE sdram_\|r\.init_counter\[11\]\~36) (DELAY (ABSOLUTE (PORT datab (250:250:250) (335:335:335)) @@ -54015,7 +57136,7 @@ (INSTANCE sdram_\|r\.init_counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54026,10 +57147,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~24) + (INSTANCE sdram_\|r\.init_counter\[12\]\~38) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) + (PORT dataa (265:265:265) (351:351:351)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54043,7 +57164,7 @@ (INSTANCE sdram_\|r\.init_counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54054,10 +57175,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~26) + (INSTANCE sdram_\|r\.init_counter\[13\]\~40) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) + (PORT datab (263:263:263) (345:345:345)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54071,7 +57192,7 @@ (INSTANCE sdram_\|r\.init_counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54082,10 +57203,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~28) + (INSTANCE sdram_\|r\.init_counter\[14\]\~42) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) + (PORT dataa (266:266:266) (353:353:353)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -54096,7 +57217,7 @@ (INSTANCE sdram_\|r\.init_counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54105,15 +57226,45 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (444:444:444) (503:503:503)) + (PORT datac (410:410:410) (470:470:470)) + (PORT datad (381:381:381) (435:435:435)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|process_0\~5) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) + (PORT dataa (405:405:405) (480:480:480)) (PORT datab (252:252:252) (337:337:337)) - (PORT datac (224:224:224) (306:306:306)) - (PORT datad (227:227:227) (299:299:299)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (226:226:226) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (483:483:483)) + (PORT datab (591:591:591) (654:654:654)) + (PORT datac (383:383:383) (445:445:445)) + (PORT datad (391:391:391) (449:449:449)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -54126,59 +57277,13 @@ (INSTANCE sdram_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) + (PORT dataa (415:415:415) (486:486:486)) (PORT datab (197:197:197) (236:236:236)) - (PORT datac (353:353:353) (381:381:381)) - (PORT datad (388:388:388) (451:451:451)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~11) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (865:865:865)) - (PORT datab (304:304:304) (399:399:399)) - (PORT datad (752:752:752) (835:835:835)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~12) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (608:608:608)) - (PORT datab (662:662:662) (714:714:714)) - (PORT datac (1575:1575:1575) (1693:1693:1693)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1632:1632:1632)) - (PORT datab (1378:1378:1378) (1503:1503:1503)) - (PORT datac (566:566:566) (574:574:574)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (338:338:338) (357:357:357)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54188,11 +57293,27 @@ (INSTANCE sdram_\|Mux8\~0) (DELAY (ABSOLUTE - (PORT dataa (1278:1278:1278) (1384:1384:1384)) - (PORT datab (1463:1463:1463) (1512:1512:1512)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (862:862:862) (878:878:878)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (286:286:286) (382:382:382)) + (PORT datab (428:428:428) (498:498:498)) + (PORT datac (404:404:404) (469:469:469)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (863:863:863) (954:954:954)) + (PORT datad (582:582:582) (629:629:629)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54201,28 +57322,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~1) + (INSTANCE sdram_\|Mux8\~5) (DELAY (ABSOLUTE - (PORT dataa (1217:1217:1217) (1339:1339:1339)) - (PORT datab (975:975:975) (1056:1056:1056)) - (PORT datac (968:968:968) (1042:1042:1042)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~2) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (811:811:811)) - (PORT datac (1118:1118:1118) (1180:1180:1180)) - (PORT datad (873:873:873) (903:903:903)) + (PORT dataa (288:288:288) (386:386:386)) + (PORT datac (607:607:607) (639:639:639)) + (PORT datad (572:572:572) (598:598:598)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54234,7 +57339,7 @@ (INSTANCE sdram_\|r\.state\[4\]) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54248,12 +57353,10 @@ (INSTANCE sdram_\|Mux72\~0) (DELAY (ABSOLUTE - (PORT datab (3068:3068:3068) (3183:3183:3183)) - (PORT datac (902:902:902) (1002:1002:1002)) - (PORT datad (278:278:278) (362:362:362)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (1710:1710:1710) (1782:1782:1782)) + (PORT datac (979:979:979) (1078:1078:1078)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54262,12 +57365,12 @@ (INSTANCE sdram_\|Mux72\~1) (DELAY (ABSOLUTE - (PORT dataa (1025:1025:1025) (1085:1085:1085)) - (PORT datab (3069:3069:3069) (3185:3185:3185)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (360:360:360) (379:379:379)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (755:755:755) (796:796:796)) + (PORT datab (326:326:326) (424:424:424)) + (PORT datac (314:314:314) (345:345:345)) + (PORT datad (627:627:627) (676:676:676)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54278,8 +57381,8 @@ (INSTANCE sdram_\|Mux84\~0) (DELAY (ABSOLUTE - (PORT datac (252:252:252) (338:338:338)) - (PORT datad (739:739:739) (806:806:806)) + (PORT datac (291:291:291) (382:382:382)) + (PORT datad (251:251:251) (327:327:327)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54290,13 +57393,13 @@ (INSTANCE sdram_\|Mux84\~1) (DELAY (ABSOLUTE - (PORT dataa (429:429:429) (511:511:511)) - (PORT datab (303:303:303) (398:398:398)) - (PORT datac (261:261:261) (351:351:351)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (290:290:290) (389:389:389)) + (PORT datab (271:271:271) (354:354:354)) + (PORT datac (262:262:262) (343:343:343)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54306,11 +57409,9 @@ (INSTANCE sdram_\|Mux3\~0) (DELAY (ABSOLUTE - (PORT datab (3069:3069:3069) (3191:3191:3191)) - (PORT datac (1141:1141:1141) (1223:1223:1223)) - (PORT datad (280:280:280) (365:365:365)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1083:1083:1083) (1208:1208:1208)) + (PORT datad (1685:1685:1685) (1743:1743:1743)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54320,13 +57421,13 @@ (INSTANCE sdram_\|Mux3\~1) (DELAY (ABSOLUTE - (PORT dataa (1024:1024:1024) (1092:1092:1092)) - (PORT datab (3070:3070:3070) (3193:3193:3193)) - (PORT datac (312:312:312) (331:331:331)) - (PORT datad (343:343:343) (365:365:365)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (323:323:323) (419:419:419)) + (PORT datac (720:720:720) (756:756:756)) + (PORT datad (342:342:342) (361:361:361)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54336,12 +57437,10 @@ (INSTANCE sdram_\|Mux2\~0) (DELAY (ABSOLUTE - (PORT datab (3070:3070:3070) (3185:3185:3185)) - (PORT datac (1121:1121:1121) (1216:1216:1216)) - (PORT datad (283:283:283) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (1493:1493:1493) (1543:1543:1543)) + (PORT datac (855:855:855) (962:962:962)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54350,13 +57449,13 @@ (INSTANCE sdram_\|Mux2\~1) (DELAY (ABSOLUTE - (PORT dataa (1027:1027:1027) (1093:1093:1093)) - (PORT datab (3073:3073:3073) (3192:3192:3192)) - (PORT datac (347:347:347) (370:370:370)) - (PORT datad (628:628:628) (674:674:674)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (600:600:600) (634:634:634)) + (PORT datab (327:327:327) (424:424:424)) + (PORT datac (627:627:627) (673:673:673)) + (PORT datad (1431:1431:1431) (1448:1448:1448)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54366,11 +57465,9 @@ (INSTANCE sdram_\|Mux1\~0) (DELAY (ABSOLUTE - (PORT datab (3073:3073:3073) (3191:3191:3191)) - (PORT datac (1123:1123:1123) (1214:1214:1214)) - (PORT datad (280:280:280) (360:360:360)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (1775:1775:1775) (1836:1836:1836)) + (PORT datad (651:651:651) (718:718:718)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54380,13 +57477,13 @@ (INSTANCE sdram_\|Mux1\~1) (DELAY (ABSOLUTE - (PORT dataa (1024:1024:1024) (1093:1093:1093)) - (PORT datab (3064:3064:3064) (3191:3191:3191)) - (PORT datac (609:609:609) (617:617:617)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (768:768:768) (864:864:864)) + (PORT datab (1153:1153:1153) (1204:1204:1204)) + (PORT datac (1380:1380:1380) (1407:1407:1407)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54396,11 +57493,9 @@ (INSTANCE sdram_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT datab (3064:3064:3064) (3190:3190:3190)) - (PORT datac (972:972:972) (1042:1042:1042)) - (PORT datad (282:282:282) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (1775:1775:1775) (1836:1836:1836)) + (PORT datad (396:396:396) (465:465:465)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54410,13 +57505,13 @@ (INSTANCE sdram_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (1027:1027:1027) (1093:1093:1093)) - (PORT datab (3072:3072:3072) (3191:3191:3191)) - (PORT datac (312:312:312) (340:340:340)) - (PORT datad (608:608:608) (655:655:655)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1112:1112:1112) (1132:1132:1132)) + (PORT datab (322:322:322) (417:417:417)) + (PORT datac (718:718:718) (759:759:759)) + (PORT datad (643:643:643) (655:655:655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54426,26 +57521,10 @@ (INSTANCE sdram_\|Mux73\~0) (DELAY (ABSOLUTE - (PORT datab (3066:3066:3066) (3187:3187:3187)) - (PORT datac (1488:1488:1488) (1592:1592:1592)) - (PORT datad (279:279:279) (362:362:362)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux73\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1090:1090:1090)) - (PORT datab (3063:3063:3063) (3193:3193:3193)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (611:611:611) (659:659:659)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT datab (1088:1088:1088) (1101:1101:1101)) + (PORT datac (835:835:835) (875:875:875)) + (PORT datad (201:201:201) (228:228:228)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54456,11 +57535,9 @@ (INSTANCE sdram_\|Mux74\~0) (DELAY (ABSOLUTE - (PORT datab (3072:3072:3072) (3189:3189:3189)) - (PORT datac (922:922:922) (1010:1010:1010)) - (PORT datad (277:277:277) (361:361:361)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (890:890:890) (924:924:924)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54470,13 +57547,13 @@ (INSTANCE sdram_\|Mux74\~1) (DELAY (ABSOLUTE - (PORT dataa (1025:1025:1025) (1085:1085:1085)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (3027:3027:3027) (3147:3147:3147)) - (PORT datad (635:635:635) (683:683:683)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (756:756:756) (796:796:796)) + (PORT datab (867:867:867) (909:909:909)) + (PORT datac (294:294:294) (387:387:387)) + (PORT datad (592:592:592) (638:638:638)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54486,9 +57563,23 @@ (INSTANCE sdram_\|Mux75\~0) (DELAY (ABSOLUTE - (PORT datac (1505:1505:1505) (1638:1638:1638)) - (PORT datad (1359:1359:1359) (1405:1405:1405)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (744:744:744) (841:841:841)) + (PORT datab (845:845:845) (876:876:876)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE LED\~0) + (DELAY + (ABSOLUTE + (PORT datac (1303:1303:1303) (1368:1368:1368)) + (PORT datad (1496:1496:1496) (1562:1562:1562)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54507,9 +57598,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1921:1921:1921) (1947:1947:1947)) + (PORT clk (1896:1896:1896) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1556:1556:1556)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54524,7 +57615,7 @@ (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (976:976:976) (1002:1002:1002)) + (PORT d (953:953:953) (987:987:987)) (PORT clrn (1750:1750:1750) (1800:1800:1800)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -54535,13 +57626,29 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT datab (684:684:684) (751:751:751)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (1012:1012:1012) (1100:1100:1100)) + (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) ) @@ -54550,7 +57657,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (336:336:336)) + (PORT datab (251:251:251) (335:335:335)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54564,10 +57671,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (210:210:210) (240:240:240)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (238:238:238) (289:289:289)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54576,9 +57683,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1917:1917:1917)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1563:1563:1563) (1555:1555:1555)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54592,9 +57699,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (480:480:480)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (429:429:429) (498:498:498)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54606,8 +57713,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datac (315:315:315) (334:334:334)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (330:330:330) (344:344:344)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54616,9 +57723,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54632,9 +57739,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (435:435:435) (503:503:503)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (430:430:430) (497:497:497)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54646,7 +57753,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datad (557:557:557) (571:571:571)) + (PORT datad (328:328:328) (343:343:343)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54656,9 +57763,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1921:1921:1921) (1947:1947:1947)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1556:1556:1556)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54672,7 +57779,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54686,10 +57793,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (239:239:239) (292:292:292)) + (PORT datac (172:172:172) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54698,9 +57805,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1917:1917:1917)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1563:1563:1563) (1555:1555:1555)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54714,7 +57821,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (438:438:438) (505:505:505)) + (PORT dataa (399:399:399) (480:480:480)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54728,8 +57835,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (314:314:314) (330:330:330)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (317:317:317) (336:336:336)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -54738,9 +57845,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54754,13 +57861,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (480:480:480)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (395:395:395) (461:461:461)) - (PORT datad (394:394:394) (457:457:457)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (401:401:401) (482:482:482)) + (PORT datab (433:433:433) (499:499:499)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (388:388:388) (455:455:455)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54770,7 +57877,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (426:426:426) (495:495:495)) + (PORT datab (429:429:429) (498:498:498)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54784,7 +57891,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (348:348:348)) + (PORT datad (310:310:310) (329:329:329)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54794,9 +57901,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54810,9 +57917,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (477:477:477)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (397:397:397) (473:473:473)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54824,8 +57931,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datac (335:335:335) (357:357:357)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54834,9 +57941,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54850,7 +57957,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (253:253:253) (338:338:338)) + (PORT datab (252:252:252) (337:337:337)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54864,10 +57971,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datad (210:210:210) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (242:242:242) (296:296:296)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54876,9 +57983,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1917:1917:1917)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1563:1563:1563) (1555:1555:1555)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54892,7 +57999,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (383:383:383) (441:441:441)) + (PORT datad (398:398:398) (459:459:459)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -54903,8 +58010,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datac (343:343:343) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (333:333:333) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54913,9 +58020,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1893:1893:1893) (1916:1916:1916)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1562:1562:1562) (1554:1554:1554)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54929,13 +58036,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (478:478:478)) - (PORT datab (422:422:422) (482:482:482)) - (PORT datac (222:222:222) (301:301:301)) - (PORT datad (393:393:393) (456:456:456)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (434:434:434) (502:502:502)) + (PORT datab (396:396:396) (469:469:469)) + (PORT datac (397:397:397) (462:462:462)) + (PORT datad (222:222:222) (294:294:294)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54945,41 +58052,24 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (248:248:248) (333:333:333)) - (PORT datac (317:317:317) (336:336:336)) - (PORT datad (650:650:650) (712:712:712)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (975:975:975) (1059:1059:1059)) + (PORT datad (223:223:223) (294:294:294)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT asdata (535:535:535) (565:565:565)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (962:962:962) (999:999:999)) - (PORT datad (231:231:231) (304:304:304)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datad (1181:1181:1181) (1271:1271:1271)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54990,7 +58080,7 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (1379:1379:1379) (1433:1433:1433)) + (PORT d (1567:1567:1567) (1679:1679:1679)) (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -55007,7 +58097,7 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (1386:1386:1386) (1428:1428:1428)) + (PORT d (1931:1931:1931) (2013:2013:2013)) (PORT clrn (1749:1749:1749) (1799:1799:1799)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -55018,37 +58108,6 @@ (HOLD d (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (458:458:458)) - (PORT datab (965:965:965) (1004:1004:1004)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) @@ -55062,22 +58121,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT datac (193:193:193) (226:226:226)) + (PORT datab (738:738:738) (824:824:824)) + (IOPATH datab cout (446:446:446) (318:318:318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1099:1099:1099)) + (PORT datab (1206:1206:1206) (1305:1305:1305)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (701:701:701) (782:782:782)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55088,15 +58177,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) + (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (945:945:945)) - (PORT datab (277:277:277) (369:369:369)) - (PORT datac (204:204:204) (241:241:241)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (664:664:664) (753:753:753)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (719:719:719)) + (PORT datab (968:968:968) (1061:1061:1061)) + (PORT datac (215:215:215) (263:263:263)) + (PORT datad (214:214:214) (259:259:259)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (809:809:809)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (911:911:911)) + (PORT datab (978:978:978) (1072:1072:1072)) + (PORT datac (248:248:248) (331:331:331)) + (PORT datad (620:620:620) (660:660:660)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (641:641:641) (724:724:724)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (635:635:635)) + (PORT datab (967:967:967) (1064:1064:1064)) + (PORT datac (211:211:211) (261:261:261)) + (PORT datad (212:212:212) (256:256:256)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (812:812:812)) + (PORT datab (659:659:659) (750:750:750)) + (PORT datac (221:221:221) (302:302:302)) + (PORT datad (637:637:637) (720:720:720)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (304:304:304)) + (PORT datab (967:967:967) (1060:1060:1060)) + (PORT datad (615:615:615) (654:654:654)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (364:364:364)) + (PORT datad (619:619:619) (656:656:656)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (299:299:299)) + (PORT datab (976:976:976) (1069:1069:1069)) + (PORT datac (209:209:209) (256:256:256)) + (PORT datad (234:234:234) (309:309:309)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -55105,12 +58406,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (570:570:570) (611:611:611)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1002:1002:1002) (1050:1050:1050)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55141,12 +58442,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (570:570:570) (612:612:612)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1003:1003:1003) (1051:1051:1051)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55160,10 +58461,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~10) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) + (PORT datab (264:264:264) (347:347:347)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55177,12 +58478,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (567:567:567) (608:608:608)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1003:1003:1003) (1052:1052:1052)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55196,10 +58497,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~12) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (348:348:348)) + (PORT datab (252:252:252) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55213,12 +58514,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (568:568:568) (608:608:608)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1003:1003:1003) (1053:1053:1053)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55232,10 +58533,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~14) (DELAY (ABSOLUTE - (PORT dataa (270:270:270) (366:366:366)) + (PORT dataa (262:262:262) (355:355:355)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -55246,12 +58547,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (568:568:568) (610:610:610)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1004:1004:1004) (1054:1054:1054)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55268,10 +58569,10 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (409:409:409) (479:479:479)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (301:301:301)) - (PORT datad (225:225:225) (296:296:296)) + (PORT dataa (404:404:404) (480:480:480)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (226:226:226) (298:298:298)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -55281,265 +58582,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) + (INSTANCE ula_\|i2s_intf_\|LessThan0\~1) (DELAY (ABSOLUTE - (PORT dataa (384:384:384) (461:461:461)) - (PORT datab (551:551:551) (565:565:565)) - (PORT datac (238:238:238) (326:326:326)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datac (232:232:232) (317:317:317)) + (PORT datad (182:182:182) (213:213:213)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (507:507:507)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (505:505:505)) - (PORT datab (966:966:966) (1004:1004:1004)) - (PORT datac (318:318:318) (335:335:335)) - (PORT datad (217:217:217) (252:252:252)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT datab (573:573:573) (642:642:642)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (459:459:459)) - (PORT datab (962:962:962) (1006:1006:1006)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (331:331:331) (353:353:353)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (509:509:509)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (879:879:879) (891:891:891)) - (PORT datad (219:219:219) (255:255:255)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (457:457:457)) - (PORT datab (965:965:965) (1004:1004:1004)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (333:333:333) (353:353:353)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (339:339:339)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (223:223:223) (302:302:302)) - (PORT datad (549:549:549) (606:606:606)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (246:246:246) (293:293:293)) - (PORT datad (391:391:391) (462:462:462)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datac (241:241:241) (330:330:330)) - (PORT datad (251:251:251) (332:332:332)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (569:569:569)) - (PORT datab (276:276:276) (367:367:367)) - (PORT datac (881:881:881) (906:906:906)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (241:241:241) (303:303:303)) + (PORT datab (244:244:244) (297:297:297)) + (PORT datad (939:939:939) (1019:1019:1019)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55550,7 +58613,7 @@ (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (1492:1492:1492) (1572:1572:1572)) + (PORT d (2073:2073:2073) (2219:2219:2219)) (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -55566,7 +58629,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (931:931:931) (990:990:990)) + (PORT datad (643:643:643) (695:695:695)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55576,12 +58639,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT datab (1869:1869:1869) (2024:2024:2024)) - (PORT datac (3075:3075:3075) (3301:3301:3301)) - (PORT datad (2569:2569:2569) (2679:2679:2679)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (1248:1248:1248) (1333:1333:1333)) + (PORT datab (1163:1163:1163) (1207:1207:1207)) + (PORT datac (1134:1134:1134) (1180:1180:1180)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -55590,13 +58653,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (2571:2571:2571) (2819:2819:2819)) - (PORT datab (1226:1226:1226) (1334:1334:1334)) - (PORT datac (2100:2100:2100) (2229:2229:2229)) - (PORT datad (1093:1093:1093) (1082:1082:1082)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1203:1203:1203) (1271:1271:1271)) + (PORT datab (1691:1691:1691) (1786:1786:1786)) + (PORT datac (1213:1213:1213) (1289:1289:1289)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55606,9 +58669,9 @@ (INSTANCE ula_\|pcm_outl\[13\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (997:997:997) (1007:1007:1007)) + (PORT ena (1653:1653:1653) (1635:1635:1635)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55619,15 +58682,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (551:551:551) (575:575:575)) - (PORT datab (279:279:279) (373:373:373)) - (PORT datac (242:242:242) (331:331:331)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (256:256:256) (349:349:349)) + (PORT datab (912:912:912) (982:982:982)) + (PORT datad (1180:1180:1180) (1268:1268:1268)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (349:349:349)) + (PORT datab (912:912:912) (982:982:982)) + (PORT datad (1181:1181:1181) (1270:1270:1270)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (218:218:218) (295:295:295)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1442:1442:1442) (1438:1438:1438)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (253:253:253)) + (PORT datab (238:238:238) (290:290:290)) + (PORT datac (231:231:231) (315:315:315)) + (PORT datad (233:233:233) (308:308:308)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55644,14 +58797,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (985:985:985) (1054:1054:1054)) - (PORT datab (567:567:567) (582:582:582)) - (PORT datad (752:752:752) (742:742:742)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (904:904:904) (961:961:961)) + (PORT datab (517:517:517) (586:586:586)) + (PORT datad (768:768:768) (761:761:761)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55662,9 +58815,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1908:1908:1908) (1928:1928:1928)) + (PORT clk (1868:1868:1868) (1876:1876:1876)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55675,27 +58828,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (928:928:928) (981:981:981)) - (PORT datad (220:220:220) (290:290:290)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (217:217:217) (295:295:295)) + (PORT datad (482:482:482) (547:547:547)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]\~1) (DELAY (ABSOLUTE - (PORT dataa (911:911:911) (946:946:946)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datac (202:202:202) (239:239:239)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (238:238:238) (298:298:298)) + (PORT datab (977:977:977) (1071:1071:1071)) + (PORT datac (207:207:207) (254:254:254)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -55704,40 +58859,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT datac (945:945:945) (999:999:999)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55752,22 +58877,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (329:329:329)) - (PORT datac (941:941:941) (995:995:995)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (536:536:536) (605:605:605)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55782,22 +58907,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datac (925:925:925) (991:991:991)) - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (517:517:517) (592:592:592)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55812,22 +58937,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (248:248:248) (336:336:336)) - (PORT datac (946:946:946) (1001:1001:1001)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (534:534:534) (608:608:608)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55842,22 +58967,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT datac (939:939:939) (985:985:985)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (535:535:535) (604:604:604)) + (PORT datad (218:218:218) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55872,22 +58997,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datac (946:946:946) (1005:1005:1005)) - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (513:513:513) (587:587:587)) + (PORT datad (220:220:220) (289:289:289)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55902,22 +59027,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datac (949:949:949) (1004:1004:1004)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (473:473:473) (539:539:539)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55932,22 +59057,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datac (948:948:948) (1006:1006:1006)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (516:516:516) (595:595:595)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55962,22 +59087,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datac (947:947:947) (1002:1002:1002)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (219:219:219) (296:296:296)) + (PORT datad (495:495:495) (559:559:559)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55992,22 +59117,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datac (950:950:950) (1004:1004:1004)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (531:531:531) (600:600:600)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56022,22 +59147,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datac (927:927:927) (980:980:980)) - (PORT datad (221:221:221) (291:291:291)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (217:217:217) (293:293:293)) + (PORT datad (491:491:491) (560:560:560)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56047,119 +59172,27 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (530:530:530)) - (PORT datab (964:964:964) (1007:1007:1007)) - (PORT datad (235:235:235) (310:310:310)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (530:530:530)) - (PORT datab (964:964:964) (1006:1006:1006)) - (PORT datad (234:234:234) (310:310:310)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outr\~0) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (334:334:334)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1539:1539:1539)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2947:2947:2947) (2964:2964:2964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (938:938:938) (987:987:987)) - (PORT datad (368:368:368) (428:428:428)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (484:484:484) (545:545:545)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56174,24 +59207,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1401:1401:1401) (1507:1507:1507)) - (PORT datac (929:929:929) (981:981:981)) + (PORT datab (535:535:535) (608:608:608)) + (PORT datac (1209:1209:1209) (1305:1305:1305)) (PORT datad (218:218:218) (287:287:287)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56201,42 +59234,64 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (595:595:595) (610:610:610)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (997:997:997) (1007:1007:1007)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (354:354:354)) - (PORT datac (926:926:926) (989:989:989)) - (PORT datad (1495:1495:1495) (1587:1587:1587)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1175:1175:1175) (1251:1251:1251)) + (PORT datac (657:657:657) (734:734:734)) + (PORT datad (1182:1182:1182) (1276:1276:1276)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1886:1886:1886) (1908:1908:1908)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (PORT ena (1205:1205:1205) (1192:1192:1192)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (558:558:558) (589:589:589)) + (PORT ena (2210:2210:2210) (2208:2208:2208)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (DELAY + (ABSOLUTE + (PORT datab (941:941:941) (1017:1017:1017)) + (PORT datac (656:656:656) (707:707:707)) + (PORT datad (903:903:903) (977:977:977)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -56246,10 +59301,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1884:1884:1884) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1564:1564:1564) (1558:1558:1558)) + (PORT ena (1225:1225:1225) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56261,11 +59316,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~2) (DELAY (ABSOLUTE - (PORT datab (619:619:619) (640:640:640)) - (PORT datad (664:664:664) (716:716:716)) + (PORT datab (528:528:528) (601:601:601)) + (PORT datad (916:916:916) (1010:1010:1010)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -56276,10 +59331,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1932:1932:1932)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1558:1558:1558)) - (PORT ena (1437:1437:1437) (1422:1422:1422)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56294,8 +59349,8 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (615:615:615) (638:638:638)) - (PORT datad (218:218:218) (287:287:287)) + (PORT datab (536:536:536) (605:605:605)) + (PORT datad (219:219:219) (288:288:288)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -56307,9 +59362,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1138:1138:1138) (1176:1176:1176)) + (PORT d (960:960:960) (1023:1023:1023)) (PORT clrn (1752:1752:1752) (1802:1802:1802)) - (PORT ena (867:867:867) (864:864:864)) + (PORT ena (1453:1453:1453) (1490:1490:1490)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -56323,116 +59378,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1169:1169:1169) (1173:1173:1173)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1802:1802:1802) (1799:1799:1799)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (371:371:371)) - (PORT datab (261:261:261) (342:342:342)) - (PORT datac (234:234:234) (309:309:309)) - (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (371:371:371)) - (PORT datab (282:282:282) (365:365:365)) - (PORT datac (395:395:395) (452:452:452)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (511:511:511)) - (PORT datab (270:270:270) (355:355:355)) - (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (506:506:506)) - (PORT datab (678:678:678) (734:734:734)) - (PORT datac (607:607:607) (669:669:669)) - (PORT datad (515:515:515) (528:528:528)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (371:371:371)) - (PORT datab (288:288:288) (373:373:373)) - (PORT datac (344:344:344) (366:366:366)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (897:897:897) (930:930:930)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (1266:1266:1266) (1303:1303:1303)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -56441,25 +59391,25 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (545:545:545)) - (PORT datab (978:978:978) (1051:1051:1051)) - (PORT datac (708:708:708) (773:773:773)) - (PORT datad (743:743:743) (801:801:801)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (513:513:513) (592:592:592)) + (PORT datab (1410:1410:1410) (1563:1563:1563)) + (PORT datac (1639:1639:1639) (1703:1703:1703)) + (PORT datad (275:275:275) (357:357:357)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56473,25 +59423,98 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (443:443:443) (543:543:543)) - (PORT datab (973:973:973) (1046:1046:1046)) - (PORT datac (708:708:708) (775:775:775)) - (PORT datad (740:740:740) (796:796:796)) + (PORT dataa (664:664:664) (717:717:717)) + (PORT datab (1662:1662:1662) (1711:1711:1711)) + (PORT datad (638:638:638) (683:683:683)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1438:1438:1438) (1470:1470:1470)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1207:1207:1207) (1254:1254:1254)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1510:1510:1510) (1556:1556:1556)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT asdata (1486:1486:1486) (1503:1503:1503)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1142:1142:1142) (1195:1195:1195)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1453:1453:1453) (1491:1491:1491)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56505,10 +59528,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (1176:1176:1176) (1194:1194:1194)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (228:228:228) (269:269:269)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) ) ) ) @@ -56517,13 +59539,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1878:1878:1878) (1891:1891:1891)) - (PORT asdata (517:517:517) (548:548:548)) + (PORT clk (1541:1541:1541) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -56531,8 +59553,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (389:389:389) (459:459:459)) - (PORT datab (251:251:251) (336:336:336)) + (PORT dataa (999:999:999) (1057:1057:1057)) + (PORT datab (243:243:243) (326:326:326)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -56546,9 +59568,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56576,9 +59598,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56606,9 +59628,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56622,25 +59644,35 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (380:380:380) (439:439:439)) + (PORT datad (227:227:227) (299:299:299)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) - (PORT asdata (661:661:661) (675:675:675)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -56649,31 +59681,21 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (663:663:663) (721:721:721)) + (PORT datad (222:222:222) (293:293:293)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1069:1069:1069) (1058:1058:1058)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (444:444:444) (543:543:543)) - (PORT datab (975:975:975) (1047:1047:1047)) - (PORT datac (710:710:710) (775:775:775)) - (PORT datad (742:742:742) (800:800:800)) + (PORT dataa (517:517:517) (586:586:586)) + (PORT datab (1411:1411:1411) (1560:1560:1560)) + (PORT datac (1638:1638:1638) (1700:1700:1700)) + (PORT datad (273:273:273) (353:353:353)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -56681,279 +59703,51 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1321:1321:1321) (1397:1397:1397)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1432:1432:1432) (1427:1427:1427)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (973:973:973) (1033:1033:1033)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (933:933:933) (975:975:975)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (650:650:650) (704:704:704)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (894:894:894) (929:929:929)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (991:991:991) (1050:1050:1050)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (408:408:408)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (378:378:378) (431:431:431)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (404:404:404)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1044:1044:1044) (1032:1032:1032)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1185:1185:1185) (1195:1195:1195)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (645:645:645) (702:702:702)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1127:1127:1127) (1176:1176:1176)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (910:910:910) (917:917:917)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1459:1459:1459) (1485:1485:1485)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -56962,9 +59756,25 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1488:1488:1488) (1559:1559:1559)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (979:979:979) (1025:1025:1025)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1607:1607:1607) (1642:1642:1642)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56973,38 +59783,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (645:645:645) (655:655:655)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (643:643:643) (702:702:702)) + (PORT datad (1310:1310:1310) (1346:1346:1346)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57014,9 +59798,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57025,29 +59809,19 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (925:925:925) (942:942:942)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1216:1216:1216) (1226:1226:1226)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -57056,9 +59830,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1153:1153:1153) (1205:1205:1205)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1134:1134:1134) (1182:1182:1182)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57072,11 +59846,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (309:309:309) (409:409:409)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (381:381:381) (435:435:435)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (271:271:271) (357:357:357)) + (PORT datad (261:261:261) (342:342:342)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57087,9 +59861,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (309:309:309) (409:409:409)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (289:289:289) (386:386:386)) + (PORT datab (244:244:244) (326:326:326)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -57099,13 +59873,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[2\]\~0) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (200:200:200) (239:239:239)) + (PORT datad (811:811:811) (812:812:812)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1496:1496:1496) (1537:1537:1537)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1495:1495:1495) (1532:1532:1532)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1653:1653:1653) (1703:1703:1703)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1459:1459:1459) (1511:1511:1511)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1386:1386:1386) (1423:1423:1423)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1484:1484:1484) (1500:1500:1500)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1719:1719:1719) (1746:1746:1746)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (460:460:460)) + (PORT datab (271:271:271) (357:357:357)) + (PORT datad (262:262:262) (345:345:345)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (386:386:386)) + (PORT datab (410:410:410) (468:468:468)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (737:737:737)) + (PORT datab (337:337:337) (360:360:360)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|cindex\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (484:484:484)) + (PORT datad (188:188:188) (217:217:217)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datab (263:263:263) (345:345:345)) + (PORT datad (237:237:237) (306:306:306)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -57114,96 +60095,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT datad (1431:1431:1431) (1427:1427:1427)) + (PORT dataa (283:283:283) (376:376:376)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (263:263:263) (343:343:343)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (999:999:999) (1058:1058:1058)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datad (645:645:645) (655:655:655)) + (PORT dataa (271:271:271) (360:360:360)) + (PORT datad (243:243:243) (314:314:314)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (998:998:998) (1057:1057:1057)) - (PORT ena (1452:1452:1452) (1445:1445:1445)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~1) + (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datad (351:351:351) (406:406:406)) + (PORT dataa (416:416:416) (490:490:490)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57214,10 +60142,10 @@ (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (501:501:501)) - (PORT datab (289:289:289) (374:374:374)) - (PORT datac (249:249:249) (334:334:334)) - (PORT datad (264:264:264) (337:337:337)) + (PORT dataa (272:272:272) (363:363:363)) + (PORT datab (290:290:290) (376:376:376)) + (PORT datac (263:263:263) (343:343:343)) + (PORT datad (252:252:252) (328:328:328)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -57230,57 +60158,13 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (705:705:705)) - (PORT datab (467:467:467) (530:530:530)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (350:350:350) (372:372:372)) + (PORT dataa (300:300:300) (395:395:395)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (251:251:251) (335:335:335)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (504:504:504)) - (PORT datab (468:468:468) (533:533:533)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (348:348:348) (370:370:370)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (348:348:348)) - (PORT datad (248:248:248) (321:321:321)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (727:727:727)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57290,10 +60174,90 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (511:511:511) (525:525:525)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (553:553:553) (568:568:568)) + (PORT datab (565:565:565) (583:583:583)) + (PORT datad (526:526:526) (522:522:522)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1442:1442:1442) (1438:1438:1438)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (397:397:397)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (254:254:254) (339:339:339)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (361:361:361)) + (PORT datab (269:269:269) (353:353:353)) + (PORT datac (385:385:385) (449:449:449)) + (PORT datad (244:244:244) (314:314:314)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (820:820:820)) + (PORT datab (416:416:416) (482:482:482)) + (PORT datac (634:634:634) (700:700:700)) + (PORT datad (555:555:555) (571:571:571)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (490:490:490)) + (PORT datab (410:410:410) (475:475:475)) + (PORT datac (332:332:332) (351:351:351)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57304,23 +60268,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1435:1435:1435) (1539:1539:1539)) - (PORT datab (236:236:236) (279:279:279)) - (PORT datac (325:325:325) (348:348:348)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1068:1068:1068) (1056:1056:1056)) + (PORT dataa (224:224:224) (268:268:268)) + (PORT datab (216:216:216) (262:262:262)) + (PORT datac (1606:1606:1606) (1684:1684:1684)) + (PORT datad (356:356:356) (379:379:379)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57330,14 +60284,14 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT asdata (1174:1174:1174) (1180:1180:1180)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -57346,9 +60300,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (970:970:970) (1019:1019:1019)) - (PORT ena (1289:1289:1289) (1289:1289:1289)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT asdata (953:953:953) (1007:1007:1007)) + (PORT ena (1192:1192:1192) (1191:1191:1191)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57362,11 +60316,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (395:395:395)) - (PORT datab (1103:1103:1103) (1116:1116:1116)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (407:407:407) (448:448:448)) + (PORT datab (593:593:593) (619:619:619)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57377,21 +60331,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (395:395:395)) - (PORT datab (237:237:237) (282:282:282)) - (PORT datac (325:325:325) (348:348:348)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1310:1310:1310) (1352:1352:1352)) + (PORT dataa (410:410:410) (435:435:435)) + (PORT datac (201:201:201) (239:239:239)) + (PORT datad (361:361:361) (379:379:379)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57401,51 +60345,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1944:1944:1944) (1933:1933:1933)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (930:930:930) (973:973:973)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1010:1010:1010) (1067:1067:1067)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1974:1974:1974) (2015:2015:2015)) + (PORT ena (1442:1442:1442) (1438:1438:1438)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57459,8 +60361,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1045:1045:1045) (1032:1032:1032)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (842:842:842) (852:852:852)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -57469,9 +60371,61 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (626:626:626) (669:669:669)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1459:1459:1459) (1511:1511:1511)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57482,12 +60436,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) + (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1430:1430:1430) (1470:1470:1470)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1733:1733:1733) (1770:1770:1770)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57501,9 +60455,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datad (218:218:218) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (378:378:378) (443:443:443)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57514,13 +60468,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (240:240:240) (285:285:285)) - (PORT datac (859:859:859) (931:931:931)) - (PORT datad (318:318:318) (335:335:335)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1588:1588:1588) (1694:1694:1694)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (781:781:781) (783:783:783)) + (PORT datad (358:358:358) (378:378:378)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57530,75 +60484,23 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (394:394:394)) - (PORT datac (603:603:603) (618:618:618)) - (PORT datad (315:315:315) (331:331:331)) + (PORT dataa (232:232:232) (279:279:279)) + (PORT datac (370:370:370) (397:397:397)) + (PORT datad (360:360:360) (381:381:381)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (578:578:578) (598:598:598)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1726:1726:1726) (1702:1702:1702)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (912:912:912) (918:918:918)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (973:973:973) (1033:1033:1033)) - (PORT ena (1452:1452:1452) (1445:1445:1445)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1530:1530:1530) (1570:1570:1570)) + (PORT ena (1642:1642:1642) (1632:1632:1632)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57607,13 +60509,65 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (1119:1119:1119) (1146:1146:1146)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (889:889:889) (928:928:928)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (929:929:929) (945:945:945)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (876:876:876) (886:886:886)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -57622,9 +60576,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57638,9 +60592,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (974:974:974) (1030:1030:1030)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1188:1188:1188) (1223:1223:1223)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57654,9 +60608,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (379:379:379) (445:445:445)) - (PORT datad (187:187:187) (222:222:222)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (414:414:414) (476:476:476)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57667,13 +60621,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1720:1720:1720) (1842:1842:1842)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (364:364:364) (389:389:389)) - (PORT datad (369:369:369) (393:393:393)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1358:1358:1358) (1420:1420:1420)) + (PORT datab (383:383:383) (414:414:414)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57683,35 +60637,21 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (393:393:393)) - (PORT datab (348:348:348) (385:385:385)) - (PORT datad (371:371:371) (397:397:397)) + (PORT dataa (660:660:660) (694:694:694)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (358:358:358) (379:379:379)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (960:960:960)) - (PORT datac (851:851:851) (897:897:897)) - (PORT datad (1129:1129:1129) (1171:1171:1171)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -57720,14 +60660,28 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (812:812:812)) + (PORT datac (696:696:696) (765:765:765)) + (PORT datad (1593:1593:1593) (1636:1636:1636)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (401:401:401) (435:435:435)) - (PORT datad (362:362:362) (380:380:380)) + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -57741,7 +60695,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (2297:2297:2297) (2325:2325:2325)) + (PORT d (1857:1857:1857) (1908:1908:1908)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -57755,7 +60709,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT clk (1541:1541:1541) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -57769,11 +60723,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (381:381:381)) - (PORT datab (527:527:527) (549:549:549)) - (PORT datad (1470:1470:1470) (1488:1488:1488)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (231:231:231) (273:273:273)) + (PORT datad (720:720:720) (777:777:777)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57785,7 +60739,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1566:1566:1566) (1671:1671:1671)) + (PORT d (1667:1667:1667) (1712:1712:1712)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -57799,7 +60753,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (252:252:252) (325:325:325)) + (PORT datad (248:248:248) (320:320:320)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57809,10 +60763,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -57827,10 +60781,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT asdata (558:558:558) (632:632:632)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (562:562:562) (636:636:636)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -57845,7 +60799,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (252:252:252) (324:324:324)) + (PORT datad (243:243:243) (313:313:313)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57856,9 +60810,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1472:1472:1472) (1513:1513:1513)) - (PORT datad (250:250:250) (324:324:324)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (4333:4333:4333) (4475:4475:4475)) + (PORT datad (1446:1446:1446) (1474:1474:1474)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57868,11 +60822,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (973:973:973) (1037:1037:1037)) - (PORT datac (3465:3465:3465) (3837:3837:3837)) - (PORT datad (596:596:596) (610:610:610)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (3483:3483:3483) (3768:3768:3768)) + (PORT datab (682:682:682) (735:735:735)) + (PORT datad (1183:1183:1183) (1230:1230:1230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57882,9 +60836,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (997:997:997) (1007:1007:1007)) + (PORT ena (1653:1653:1653) (1635:1635:1635)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57898,69 +60852,11 @@ (INSTANCE sdram_\|Mux26\~4) (DELAY (ABSOLUTE - (PORT dataa (2317:2317:2317) (2532:2532:2532)) - (PORT datab (938:938:938) (974:974:974)) - (PORT datad (1425:1425:1425) (1536:1536:1536)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (989:989:989) (1111:1111:1111)) - (PORT datad (1785:1785:1785) (1929:1929:1929)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (953:953:953)) - (PORT datab (830:830:830) (930:930:930)) - (PORT datac (782:782:782) (889:889:889)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (292:292:292) (378:378:378)) - (PORT datac (585:585:585) (604:604:604)) - (PORT datad (284:284:284) (364:364:364)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1121:1121:1121)) - (PORT datab (1035:1035:1035) (1089:1089:1089)) - (PORT datac (1056:1056:1056) (1136:1136:1136)) - (PORT datad (599:599:599) (611:611:611)) + (PORT dataa (2172:2172:2172) (2322:2322:2322)) + (PORT datac (1891:1891:1891) (1929:1929:1929)) + (PORT datad (245:245:245) (317:317:317)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57970,26 +60866,40 @@ (INSTANCE sdram_\|r\.bank\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1427:1427:1427)) - (PORT datab (1874:1874:1874) (2002:2002:2002)) - (PORT datac (992:992:992) (1110:1110:1110)) - (PORT datad (778:778:778) (811:811:811)) + (PORT dataa (1578:1578:1578) (1710:1710:1710)) + (PORT datac (1837:1837:1837) (1945:1945:1945)) + (PORT datad (1315:1315:1315) (1431:1431:1431)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~8) + (INSTANCE sdram_\|r\.bank\[0\]\~4) (DELAY (ABSOLUTE - (PORT datab (1299:1299:1299) (1369:1369:1369)) - (PORT datac (1841:1841:1841) (1973:1973:1973)) - (PORT datad (995:995:995) (1099:1099:1099)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (910:910:910) (978:978:978)) + (PORT datac (1257:1257:1257) (1361:1361:1361)) + (PORT datad (1577:1577:1577) (1678:1678:1678)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1422:1422:1422)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (881:881:881) (948:948:948)) + (PORT datad (851:851:851) (881:881:881)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58000,13 +60910,43 @@ (INSTANCE sdram_\|r\.bank\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (897:897:897) (958:958:958)) - (PORT datab (829:829:829) (935:935:935)) + (PORT dataa (1288:1288:1288) (1407:1407:1407)) + (PORT datab (208:208:208) (250:250:250)) (PORT datac (180:180:180) (217:217:217)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (851:851:851) (884:884:884)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1578:1578:1578) (1712:1712:1712)) + (PORT datac (1839:1839:1839) (1941:1941:1941)) + (PORT datad (1315:1315:1315) (1426:1426:1426)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1472:1472:1472)) + (PORT datab (910:910:910) (982:982:982)) + (PORT datac (1541:1541:1541) (1673:1673:1673)) + (PORT datad (1247:1247:1247) (1360:1360:1360)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58016,13 +60956,61 @@ (INSTANCE sdram_\|r\.bank\[0\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1316:1316:1316) (1427:1427:1427)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1584:1584:1584) (1713:1713:1713)) + (PORT datab (888:888:888) (919:919:919)) + (PORT datac (1837:1837:1837) (1940:1940:1940)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1421:1421:1421)) + (PORT datab (1574:1574:1574) (1707:1707:1707)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1718:1718:1718)) + (PORT datab (207:207:207) (247:247:247)) + (PORT datac (1837:1837:1837) (1941:1941:1941)) + (PORT datad (1309:1309:1309) (1423:1423:1423)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1572:1572:1572) (1707:1707:1707)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58033,8 +61021,8 @@ (DELAY (ABSOLUTE (PORT clk (1514:1514:1514) (1539:1539:1539)) - (PORT d (1777:1777:1777) (1875:1875:1875)) - (PORT ena (1774:1774:1774) (1775:1775:1775)) + (PORT d (2089:2089:2089) (2206:2206:2206)) + (PORT ena (1461:1461:1461) (1494:1494:1494)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58050,11 +61038,11 @@ (INSTANCE sdram_\|Mux25\~4) (DELAY (ABSOLUTE - (PORT dataa (2317:2317:2317) (2534:2534:2534)) - (PORT datab (1431:1431:1431) (1561:1561:1561)) - (PORT datad (913:913:913) (939:939:939)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (825:825:825) (883:883:883)) + (PORT datab (1919:1919:1919) (1962:1962:1962)) + (PORT datad (2145:2145:2145) (2277:2277:2277)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58065,8 +61053,8 @@ (DELAY (ABSOLUTE (PORT clk (1516:1516:1516) (1540:1540:1540)) - (PORT d (2321:2321:2321) (2432:2432:2432)) - (PORT ena (1597:1597:1597) (1608:1608:1608)) + (PORT d (1811:1811:1811) (1934:1934:1934)) + (PORT ena (1453:1453:1453) (1487:1487:1487)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58079,74 +61067,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~5) + (INSTANCE sdram_\|Mux71\~6) (DELAY (ABSOLUTE - (PORT dataa (1066:1066:1066) (1202:1202:1202)) - (PORT datab (1024:1024:1024) (1113:1113:1113)) - (PORT datac (1152:1152:1152) (1196:1196:1196)) - (PORT datad (994:994:994) (1081:1081:1081)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1631:1631:1631) (1756:1756:1756)) + (PORT datab (1139:1139:1139) (1252:1252:1252)) + (PORT datac (1030:1030:1030) (1149:1149:1149)) + (PORT datad (1072:1072:1072) (1197:1197:1197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~0) - (DELAY - (ABSOLUTE - (PORT datab (1399:1399:1399) (1527:1527:1527)) - (PORT datac (1575:1575:1575) (1656:1656:1656)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~7) - (DELAY - (ABSOLUTE - (PORT datab (1709:1709:1709) (1882:1882:1882)) - (PORT datac (221:221:221) (300:300:300)) - (PORT datad (2617:2617:2617) (2813:2813:2813)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (772:772:772)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1422:1422:1422)) - (PORT datab (1474:1474:1474) (1580:1580:1580)) - (PORT datac (1576:1576:1576) (1657:1657:1657)) - (PORT datad (1362:1362:1362) (1488:1488:1488)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58156,13 +61086,9 @@ (INSTANCE sdram_\|Mux71\~2) (DELAY (ABSOLUTE - (PORT dataa (1306:1306:1306) (1421:1421:1421)) - (PORT datab (1020:1020:1020) (1139:1139:1139)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (1104:1104:1104) (1217:1217:1217)) + (PORT datad (1589:1589:1589) (1704:1704:1704)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58172,13 +61098,42 @@ (INSTANCE sdram_\|Mux71\~3) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1128:1128:1128)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1032:1032:1032) (1159:1159:1159)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1278:1278:1278) (1400:1400:1400)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (1070:1070:1070) (1196:1196:1196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1352:1352:1352)) + (PORT datad (1506:1506:1506) (1605:1605:1605)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (789:789:789)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (488:488:488) (500:500:500)) + (PORT datad (334:334:334) (351:351:351)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58188,12 +61143,44 @@ (INSTANCE sdram_\|Mux71\~4) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (996:996:996) (1103:1103:1103)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (625:625:625) (647:647:647)) + (PORT datad (1253:1253:1253) (1356:1356:1356)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~8) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (549:549:549)) + (PORT datab (939:939:939) (952:952:952)) + (PORT datac (1032:1032:1032) (1150:1150:1150)) + (PORT datad (628:628:628) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~5) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1102:1102:1102) (1233:1233:1233)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58205,7 +61192,7 @@ (DELAY (ABSOLUTE (PORT clk (1513:1513:1513) (1537:1537:1537)) - (PORT d (1467:1467:1467) (1545:1545:1545)) + (PORT d (1509:1509:1509) (1602:1602:1602)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58220,7 +61207,7 @@ (DELAY (ABSOLUTE (PORT clk (1513:1513:1513) (1537:1537:1537)) - (PORT d (1454:1454:1454) (1530:1530:1530)) + (PORT d (1509:1509:1509) (1602:1602:1602)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58231,43 +61218,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~10) + (INSTANCE sdram_\|n\~6) (DELAY (ABSOLUTE - (PORT datac (1570:1570:1570) (1649:1649:1649)) - (PORT datad (996:996:996) (1103:1103:1103)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~3) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (399:399:399)) - (PORT datab (1477:1477:1477) (1604:1604:1604)) - (PORT datac (1329:1329:1329) (1470:1470:1470)) - (PORT datad (353:353:353) (368:368:368)) + (PORT dataa (918:918:918) (1021:1021:1021)) + (PORT datab (999:999:999) (1096:1096:1096)) + (PORT datac (875:875:875) (938:938:938)) + (PORT datad (994:994:994) (1085:1085:1085)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~5) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (521:521:521)) - (PORT datab (698:698:698) (778:778:778)) - (PORT datac (586:586:586) (604:604:604)) - (PORT datad (285:285:285) (364:364:364)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58275,153 +61234,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~4) + (INSTANCE sdram_\|Mux9\~0) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (378:378:378)) - (PORT datab (1370:1370:1370) (1466:1466:1466)) - (PORT datac (882:882:882) (893:893:893)) - (PORT datad (1440:1440:1440) (1565:1565:1565)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1518:1518:1518)) - (PORT datab (1371:1371:1371) (1460:1460:1460)) - (PORT datac (881:881:881) (891:891:891)) - (PORT datad (1253:1253:1253) (1312:1312:1312)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (870:870:870)) - (PORT datab (302:302:302) (394:394:394)) - (PORT datac (631:631:631) (680:680:680)) - (PORT datad (754:754:754) (832:832:832)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (696:696:696) (717:717:717)) + (PORT datab (790:790:790) (876:876:876)) + (PORT datac (775:775:775) (878:878:878)) + (PORT datad (863:863:863) (936:936:936)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~2) - (DELAY - (ABSOLUTE - (PORT datab (449:449:449) (513:513:513)) - (PORT datac (415:415:415) (481:481:481)) - (PORT datad (588:588:588) (645:645:645)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~3) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (498:498:498)) - (PORT datab (272:272:272) (357:357:357)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (425:425:425) (483:483:483)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (497:497:497)) - (PORT datab (450:450:450) (516:516:516)) - (PORT datac (353:353:353) (381:381:381)) - (PORT datad (411:411:411) (473:473:473)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~4) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (423:423:423) (493:493:493)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (683:683:683) (766:766:766)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1547:1547:1547)) - (PORT datab (1604:1604:1604) (1732:1732:1732)) - (PORT datac (1336:1336:1336) (1427:1427:1427)) - (PORT datad (332:332:332) (354:354:354)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~0) - (DELAY - (ABSOLUTE - (PORT datab (1369:1369:1369) (1466:1466:1466)) - (PORT datad (1568:1568:1568) (1695:1695:1695)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux9\~6) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (423:423:423)) - (PORT datab (643:643:643) (685:685:685)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (639:639:639) (675:675:675)) + (PORT datab (961:961:961) (1036:1036:1036)) + (PORT datac (776:776:776) (877:877:877)) + (PORT datad (656:656:656) (671:671:671)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58432,13 +61269,167 @@ (INSTANCE sdram_\|Mux9\~7) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1269:1269:1269) (1350:1350:1350)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (772:772:772) (889:889:889)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (858:858:858) (948:948:948)) + (PORT datad (755:755:755) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datac (775:775:775) (878:878:878)) + (PORT datad (752:752:752) (834:834:834)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (386:386:386)) + (PORT datab (431:431:431) (502:502:502)) + (PORT datac (404:404:404) (469:469:469)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (402:402:402)) + (PORT datab (439:439:439) (499:499:499)) + (PORT datac (405:405:405) (466:466:466)) + (PORT datad (376:376:376) (431:431:431)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (488:488:488)) + (PORT datac (404:404:404) (469:469:469)) + (PORT datad (262:262:262) (344:344:344)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (399:399:399) (468:468:468)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (509:509:509)) + (PORT datab (429:429:429) (501:501:501)) + (PORT datac (384:384:384) (445:445:445)) + (PORT datad (260:260:260) (342:342:342)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (482:482:482)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (671:671:671)) + (PORT datab (791:791:791) (872:872:872)) + (PORT datac (775:775:775) (873:873:873)) + (PORT datad (743:743:743) (844:844:844)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (385:385:385)) + (PORT datab (624:624:624) (691:691:691)) + (PORT datac (609:609:609) (652:652:652)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (931:931:931) (1005:1005:1005)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58448,8 +61439,8 @@ (INSTANCE sdram_\|r\.state\[2\]) (DELAY (ABSOLUTE - (PORT clk (1498:1498:1498) (1529:1529:1529)) - (PORT d (1472:1472:1472) (1557:1557:1557)) + (PORT clk (1489:1489:1489) (1513:1513:1513)) + (PORT d (1600:1600:1600) (1700:1700:1700)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58460,32 +61451,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~11) + (INSTANCE sdram_\|Mux10\~6) (DELAY (ABSOLUTE - (PORT dataa (981:981:981) (1112:1112:1112)) - (PORT datab (1023:1023:1023) (1115:1115:1115)) - (PORT datac (1152:1152:1152) (1199:1199:1199)) - (PORT datad (995:995:995) (1083:1083:1083)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1357:1357:1357) (1482:1482:1482)) + (PORT datab (958:958:958) (1039:1039:1039)) + (PORT datac (1050:1050:1050) (1161:1161:1161)) + (PORT datad (1262:1262:1262) (1353:1353:1353)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~6) + (INSTANCE sdram_\|Mux10\~10) (DELAY (ABSOLUTE - (PORT dataa (1063:1063:1063) (1201:1201:1201)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (1060:1060:1060) (1092:1092:1092)) - (PORT datad (968:968:968) (1089:1089:1089)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1630:1630:1630) (1751:1751:1751)) + (PORT datab (1103:1103:1103) (1232:1232:1232)) + (PORT datac (634:634:634) (645:645:645)) + (PORT datad (612:612:612) (634:634:634)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1483:1483:1483)) + (PORT datab (880:880:880) (983:983:983)) + (PORT datac (1011:1011:1011) (1104:1104:1104)) + (PORT datad (1262:1262:1262) (1352:1352:1352)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1478:1478:1478)) + (PORT datab (878:878:878) (981:981:981)) + (PORT datac (1012:1012:1012) (1101:1101:1101)) + (PORT datad (1261:1261:1261) (1348:1348:1348)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58495,13 +61518,13 @@ (INSTANCE sdram_\|Mux10\~5) (DELAY (ABSOLUTE - (PORT dataa (1306:1306:1306) (1421:1421:1421)) - (PORT datab (1399:1399:1399) (1528:1528:1528)) - (PORT datac (948:948:948) (1069:1069:1069)) - (PORT datad (635:635:635) (671:671:671)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1089:1089:1089) (1196:1196:1196)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1168:1168:1168) (1176:1176:1176)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58511,12 +61534,44 @@ (INSTANCE sdram_\|Mux10\~7) (DELAY (ABSOLUTE - (PORT dataa (1062:1062:1062) (1202:1202:1202)) - (PORT datab (1398:1398:1398) (1531:1531:1531)) - (PORT datac (948:948:948) (1074:1074:1074)) - (PORT datad (968:968:968) (1089:1089:1089)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (992:992:992) (1071:1071:1071)) + (PORT datab (1005:1005:1005) (1086:1086:1086)) + (PORT datac (1049:1049:1049) (1156:1156:1156)) + (PORT datad (1261:1261:1261) (1348:1348:1348)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1060:1060:1060) (1185:1185:1185)) + (PORT datab (984:984:984) (1016:1016:1016)) + (PORT datac (590:590:590) (614:614:614)) + (PORT datad (609:609:609) (633:633:633)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1182:1182:1182)) + (PORT datab (1103:1103:1103) (1231:1231:1231)) + (PORT datac (625:625:625) (649:649:649)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58527,29 +61582,13 @@ (INSTANCE sdram_\|Mux10\~8) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (1021:1021:1021) (1144:1144:1144)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1104:1104:1104) (1239:1239:1239)) + (PORT datac (618:618:618) (631:631:631)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58559,8 +61598,8 @@ (INSTANCE sdram_\|r\.state\[1\]) (DELAY (ABSOLUTE - (PORT clk (1498:1498:1498) (1529:1529:1529)) - (PORT d (1253:1253:1253) (1356:1356:1356)) + (PORT clk (1489:1489:1489) (1513:1513:1513)) + (PORT d (1273:1273:1273) (1377:1377:1377)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58599,16 +61638,50 @@ (HOLD d (posedge clk) (83:83:83)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1332:1332:1332)) + (PORT datab (1071:1071:1071) (1170:1170:1170)) + (PORT datac (1255:1255:1255) (1352:1352:1352)) + (PORT datad (1308:1308:1308) (1406:1406:1406)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (661:661:661)) + (PORT datab (1093:1093:1093) (1203:1203:1203)) + (PORT datac (1260:1260:1260) (1357:1357:1357)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux11\~2) (DELAY (ABSOLUTE - (PORT dataa (743:743:743) (861:861:861)) - (PORT datab (780:780:780) (870:870:870)) - (PORT datad (273:273:273) (356:356:356)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (591:591:591) (613:613:613)) + (PORT datab (1079:1079:1079) (1175:1175:1175)) + (PORT datac (617:617:617) (636:636:636)) + (PORT datad (1064:1064:1064) (1157:1157:1157)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58618,28 +61691,12 @@ (INSTANCE sdram_\|Mux11\~3) (DELAY (ABSOLUTE - (PORT dataa (1511:1511:1511) (1631:1631:1631)) - (PORT datab (655:655:655) (707:707:707)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1409:1409:1409) (1518:1518:1518)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1360:1360:1360) (1508:1508:1508)) - (PORT datab (1372:1372:1372) (1466:1466:1466)) - (PORT datac (626:626:626) (666:666:666)) - (PORT datad (323:323:323) (345:345:345)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1316:1316:1316) (1447:1447:1447)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (1836:1836:1836) (1947:1947:1947)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58650,13 +61707,13 @@ (INSTANCE sdram_\|Mux11\~5) (DELAY (ABSOLUTE - (PORT dataa (1359:1359:1359) (1509:1509:1509)) - (PORT datab (1372:1372:1372) (1466:1466:1466)) - (PORT datac (1581:1581:1581) (1661:1661:1661)) - (PORT datad (1257:1257:1257) (1317:1317:1317)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1303:1303:1303) (1398:1398:1398)) + (PORT datab (1072:1072:1072) (1171:1171:1171)) + (PORT datac (889:889:889) (984:984:984)) + (PORT datad (1058:1058:1058) (1161:1161:1161)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58666,12 +61723,12 @@ (INSTANCE sdram_\|Mux11\~6) (DELAY (ABSOLUTE - (PORT dataa (985:985:985) (1116:1116:1116)) - (PORT datab (1024:1024:1024) (1143:1143:1143)) - (PORT datac (1035:1035:1035) (1162:1162:1162)) - (PORT datad (971:971:971) (1090:1090:1090)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (337:337:337) (374:374:374)) + (PORT datab (904:904:904) (969:969:969)) + (PORT datac (961:961:961) (1058:1058:1058)) + (PORT datad (995:995:995) (1086:1086:1086)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58682,42 +61739,10 @@ (INSTANCE sdram_\|Mux11\~7) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (960:960:960)) - (PORT datab (829:829:829) (930:930:930)) - (PORT datac (783:783:783) (893:893:893)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1549:1549:1549)) - (PORT datab (1264:1264:1264) (1350:1350:1350)) - (PORT datac (883:883:883) (894:894:894)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~8) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (597:597:597) (604:604:604)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (798:798:798) (810:810:810)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -58731,7 +61756,7 @@ (DELAY (ABSOLUTE (PORT clk (1495:1495:1495) (1520:1520:1520)) - (PORT d (1809:1809:1809) (1935:1935:1935)) + (PORT d (1562:1562:1562) (1673:1673:1673)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58742,62 +61767,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~2) + (INSTANCE sdram_\|Mux24\~5) (DELAY (ABSOLUTE - (PORT dataa (776:776:776) (869:869:869)) - (PORT datab (765:765:765) (852:852:852)) - (PORT datac (764:764:764) (877:877:877)) - (PORT datad (860:860:860) (888:888:888)) - (IOPATH dataa combout (303:303:303) (299:299:299)) + (PORT dataa (1190:1190:1190) (1263:1263:1263)) + (PORT datab (689:689:689) (755:755:755)) + (PORT datac (966:966:966) (1030:1030:1030)) + (PORT datad (649:649:649) (666:666:666)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~7) + (INSTANCE sdram_\|Mux24\~6) (DELAY (ABSOLUTE - (PORT dataa (3061:3061:3061) (3225:3225:3225)) - (PORT datab (612:612:612) (668:668:668)) - (PORT datac (1038:1038:1038) (1141:1141:1141)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (632:632:632)) - (PORT datab (993:993:993) (1068:1068:1068)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1510:1510:1510)) - (PORT datab (1269:1269:1269) (1353:1353:1353)) - (PORT datac (1581:1581:1581) (1661:1661:1661)) - (PORT datad (1441:1441:1441) (1561:1561:1561)) + (PORT dataa (349:349:349) (382:382:382)) + (PORT datab (689:689:689) (755:755:755)) + (PORT datac (1308:1308:1308) (1392:1392:1392)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58808,10 +61802,10 @@ (INSTANCE sdram_\|Mux13\~4) (DELAY (ABSOLUTE - (PORT dataa (1367:1367:1367) (1518:1518:1518)) - (PORT datab (1264:1264:1264) (1346:1346:1346)) - (PORT datac (1575:1575:1575) (1654:1654:1654)) - (PORT datad (1444:1444:1444) (1567:1567:1567)) + (PORT dataa (1877:1877:1877) (1991:1991:1991)) + (PORT datab (1077:1077:1077) (1173:1173:1173)) + (PORT datac (996:996:996) (1112:1112:1112)) + (PORT datad (1062:1062:1062) (1156:1156:1156)) (IOPATH dataa combout (337:337:337) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -58819,16 +61813,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1877:1877:1877) (1991:1991:1991)) + (PORT datab (1078:1078:1078) (1174:1174:1174)) + (PORT datac (995:995:995) (1111:1111:1111)) + (PORT datad (1063:1063:1063) (1157:1157:1157)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux13\~5) (DELAY (ABSOLUTE - (PORT datab (1371:1371:1371) (1460:1460:1460)) - (PORT datac (175:175:175) (208:208:208)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datac (1283:1283:1283) (1408:1408:1408)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58838,11 +61848,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1560:1560:1560)) + (PORT clk (1531:1531:1531) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (523:523:523) (557:557:557)) - (PORT sload (1639:1639:1639) (1751:1751:1751)) - (PORT ena (1247:1247:1247) (1254:1254:1254)) + (PORT asdata (923:923:923) (937:937:937)) + (PORT sload (1918:1918:1918) (2069:2069:2069)) + (PORT ena (1276:1276:1276) (1258:1258:1258)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -58853,18 +61863,30 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (891:891:891)) + (PORT datab (848:848:848) (890:890:890)) + (PORT datac (623:623:623) (691:691:691)) + (PORT datad (1840:1840:1840) (1924:1924:1924)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux24\~3) (DELAY (ABSOLUTE - (PORT dataa (3061:3061:3061) (3223:3223:3223)) - (PORT datab (613:613:613) (668:668:668)) - (PORT datac (380:380:380) (405:405:405)) - (PORT datad (632:632:632) (657:657:657)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (481:481:481) (562:562:562)) + (PORT datad (1330:1330:1330) (1467:1467:1467)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58874,13 +61896,27 @@ (INSTANCE sdram_\|Mux24\~4) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (956:956:956)) - (PORT datab (614:614:614) (671:671:671)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1100:1100:1100) (1185:1185:1185)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (706:706:706) (789:789:789)) + (PORT datab (689:689:689) (751:751:751)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (512:512:512) (525:525:525)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (656:656:656)) + (PORT datab (1638:1638:1638) (1747:1747:1747)) + (PORT datad (322:322:322) (344:344:344)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58890,11 +61926,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (1063:1063:1063) (1134:1134:1134)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1306:1306:1306) (1425:1425:1425)) + (PORT datad (358:358:358) (375:375:375)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58905,8 +61941,8 @@ (DELAY (ABSOLUTE (PORT clk (1497:1497:1497) (1522:1522:1522)) - (PORT d (2000:2000:2000) (2102:2102:2102)) - (PORT ena (1672:1672:1672) (1717:1717:1717)) + (PORT d (1682:1682:1682) (1777:1777:1777)) + (PORT ena (1912:1912:1912) (1959:1959:1959)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58919,57 +61955,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (INSTANCE sdram_\|Mux23\~1) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (257:257:257)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1137:1137:1137)) - (PORT datab (251:251:251) (337:337:337)) - (PORT datac (1288:1288:1288) (1347:1347:1347)) - (PORT datad (333:333:333) (361:361:361)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (867:867:867)) - (PORT datab (780:780:780) (874:874:874)) - (PORT datac (627:627:627) (678:678:678)) - (PORT datad (275:275:275) (357:357:357)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1138:1138:1138)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (957:957:957) (1041:1041:1041)) - (PORT datad (864:864:864) (898:898:898)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1699:1699:1699) (1817:1817:1817)) + (PORT datab (691:691:691) (742:742:742)) + (PORT datac (817:817:817) (841:841:841)) + (PORT datad (1340:1340:1340) (1475:1475:1475)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58977,32 +61971,100 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~6) + (INSTANCE sdram_\|r\.address\[1\]\~8) (DELAY (ABSOLUTE - (PORT dataa (1033:1033:1033) (1138:1138:1138)) - (PORT datab (1067:1067:1067) (1184:1184:1184)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (886:886:886) (884:884:884)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1701:1701:1701) (1818:1818:1818)) + (PORT datab (1367:1367:1367) (1519:1519:1519)) + (PORT datad (843:843:843) (859:859:859)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1356:1356:1356)) + (PORT datab (1260:1260:1260) (1338:1338:1338)) + (PORT datad (1329:1329:1329) (1462:1462:1462)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1700:1700:1700) (1816:1816:1816)) + (PORT datab (1363:1363:1363) (1517:1517:1517)) + (PORT datac (897:897:897) (973:973:973)) + (PORT datad (1535:1535:1535) (1659:1659:1659)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (1565:1565:1565) (1695:1695:1695)) + (PORT datac (573:573:573) (581:581:581)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (890:890:890) (941:941:941)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~0) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1361:1361:1361)) - (PORT datab (1090:1090:1090) (1165:1165:1165)) - (PORT datac (1257:1257:1257) (1368:1368:1368)) - (PORT datad (1000:1000:1000) (1053:1053:1053)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1315:1315:1315) (1445:1445:1445)) + (PORT datab (1034:1034:1034) (1151:1151:1151)) + (PORT datac (1214:1214:1214) (1307:1307:1307)) + (PORT datad (1054:1054:1054) (1152:1152:1152)) + (IOPATH dataa combout (350:350:350) (367:367:367)) + (IOPATH datab combout (350:350:350) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59012,11 +62074,11 @@ (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (523:523:523) (558:558:558)) - (PORT sload (1747:1747:1747) (1674:1674:1674)) - (PORT ena (1291:1291:1291) (1292:1292:1292)) + (PORT asdata (1394:1394:1394) (1420:1420:1420)) + (PORT sload (2223:2223:2223) (2152:2152:2152)) + (PORT ena (1223:1223:1223) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -59029,15 +62091,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~2) + (INSTANCE sdram_\|Mux23\~3) (DELAY (ABSOLUTE - (PORT dataa (1311:1311:1311) (1441:1441:1441)) - (PORT datab (360:360:360) (395:395:395)) - (PORT datac (957:957:957) (1039:1039:1039)) - (PORT datad (989:989:989) (1074:1074:1074)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1432:1432:1432) (1522:1522:1522)) + (PORT datab (675:675:675) (705:705:705)) + (PORT datac (931:931:931) (999:999:999)) + (PORT datad (1817:1817:1817) (1943:1943:1943)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59045,44 +62107,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~3) + (INSTANCE sdram_\|Mux23\~4) (DELAY (ABSOLUTE - (PORT dataa (1312:1312:1312) (1442:1442:1442)) - (PORT datac (518:518:518) (537:537:537)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (660:660:660) (701:701:701)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1402:1402:1402) (1480:1480:1480)) + (PORT datad (1058:1058:1058) (1172:1172:1172)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~1) + (INSTANCE sdram_\|Mux23\~2) (DELAY (ABSOLUTE - (PORT dataa (1308:1308:1308) (1440:1440:1440)) - (PORT datab (2607:2607:2607) (2785:2785:2785)) - (PORT datac (1734:1734:1734) (1812:1812:1812)) - (PORT datad (991:991:991) (1080:1080:1080)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1105:1105:1105) (1221:1221:1221)) + (PORT datab (912:912:912) (939:939:939)) + (PORT datac (717:717:717) (801:801:801)) + (PORT datad (896:896:896) (967:967:967)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~1) + (INSTANCE sdram_\|Mux23\~5) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1429:1429:1429) (1520:1520:1520)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (342:342:342) (363:363:363)) + (PORT datad (1058:1058:1058) (1173:1173:1173)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59092,12 +62158,12 @@ (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1028:1028:1028) (1131:1131:1131)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (666:666:666) (699:699:699)) + (PORT datac (1286:1286:1286) (1406:1406:1406)) + (PORT datad (606:606:606) (649:649:649)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -59107,8 +62173,8 @@ (DELAY (ABSOLUTE (PORT clk (1516:1516:1516) (1540:1540:1540)) - (PORT d (1503:1503:1503) (1609:1609:1609)) - (PORT ena (1911:1911:1911) (1938:1938:1938)) + (PORT d (1764:1764:1764) (1872:1872:1872)) + (PORT ena (2195:2195:2195) (2247:2247:2247)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59119,91 +62185,17 @@ (HOLD ena (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1437:1437:1437)) - (PORT datab (1036:1036:1036) (1094:1094:1094)) - (PORT datac (1028:1028:1028) (1133:1133:1133)) - (PORT datad (990:990:990) (1085:1085:1085)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (1036:1036:1036) (1091:1091:1091)) - (PORT datad (1280:1280:1280) (1394:1394:1394)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux21\~0) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (287:287:287)) - (PORT datab (1062:1062:1062) (1180:1180:1180)) - (PORT datac (314:314:314) (333:333:333)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux22\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (748:748:748)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (879:879:879) (894:894:894)) - (PORT datad (635:635:635) (660:660:660)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1813:1813:1813) (1972:1972:1972)) - (PORT datab (1021:1021:1021) (1144:1144:1144)) - (PORT datac (781:781:781) (894:894:894)) - (PORT datad (790:790:790) (895:895:895)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~11) (DELAY (ABSOLUTE - (PORT datab (816:816:816) (925:925:925)) - (PORT datac (1840:1840:1840) (1973:1973:1973)) - (PORT datad (994:994:994) (1103:1103:1103)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1630:1630:1630) (1751:1751:1751)) + (PORT datab (1102:1102:1102) (1231:1231:1231)) + (PORT datac (1030:1030:1030) (1149:1149:1149)) + (PORT datad (1194:1194:1194) (1280:1280:1280)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59214,12 +62206,8 @@ (INSTANCE sdram_\|r\.address\[3\]\~12) (DELAY (ABSOLUTE - (PORT dataa (897:897:897) (953:953:953)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1841:1841:1841) (1971:1971:1971)) - (PORT datad (1238:1238:1238) (1284:1284:1284)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT datac (1001:1001:1001) (1118:1118:1118)) + (PORT datad (1054:1054:1054) (1152:1152:1152)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59227,31 +62215,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~13) + (INSTANCE sdram_\|Mux21\~0) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1427:1427:1427)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1396:1396:1396) (1469:1469:1469)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (893:893:893) (919:919:919)) + (PORT datab (1300:1300:1300) (1366:1366:1366)) + (PORT datac (953:953:953) (999:999:999)) + (PORT datad (903:903:903) (922:922:922)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1624:1624:1624)) + (PORT datab (1165:1165:1165) (1219:1219:1219)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (853:853:853) (888:888:888)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1812:1812:1812) (1971:1971:1971)) - (PORT datab (1021:1021:1021) (1141:1141:1141)) - (PORT datac (782:782:782) (892:892:892)) - (PORT datad (790:790:790) (893:893:893)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (1359:1359:1359) (1468:1468:1468)) + (PORT datac (962:962:962) (1056:1056:1056)) + (PORT datad (1044:1044:1044) (1136:1136:1136)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59262,13 +62264,29 @@ (INSTANCE sdram_\|r\.address\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (954:954:954)) - (PORT datab (199:199:199) (236:236:236)) - (PORT datac (1395:1395:1395) (1469:1469:1469)) - (PORT datad (994:994:994) (1100:1100:1100)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1297:1297:1297) (1393:1393:1393)) + (PORT datab (1360:1360:1360) (1469:1469:1469)) + (PORT datac (877:877:877) (938:938:938)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1128:1128:1128)) + (PORT datab (1072:1072:1072) (1171:1171:1171)) + (PORT datac (960:960:960) (1055:1055:1055)) + (PORT datad (1307:1307:1307) (1403:1403:1403)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59278,13 +62296,13 @@ (INSTANCE sdram_\|r\.address\[3\]\~16) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1233:1233:1233) (1279:1279:1279)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1296:1296:1296) (1393:1393:1393)) + (PORT datab (1269:1269:1269) (1363:1363:1363)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59292,13 +62310,61 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1473:1473:1473)) + (PORT datab (913:913:913) (980:980:980)) + (PORT datac (1258:1258:1258) (1362:1362:1362)) + (PORT datad (1577:1577:1577) (1678:1678:1678)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1475:1475:1475)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (1539:1539:1539) (1675:1675:1675)) + (PORT datad (851:851:851) (884:884:884)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~19) (DELAY (ABSOLUTE (PORT dataa (201:201:201) (245:245:245)) - (PORT datac (988:988:988) (1107:1107:1107)) - (PORT datad (172:172:172) (197:197:197)) + (PORT datab (1572:1572:1572) (1710:1710:1710)) + (PORT datac (810:810:810) (816:816:816)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1421:1421:1421)) + (PORT datac (612:612:612) (652:652:652)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59309,8 +62375,8 @@ (DELAY (ABSOLUTE (PORT clk (1516:1516:1516) (1540:1540:1540)) - (PORT d (1841:1841:1841) (1973:1973:1973)) - (PORT ena (1809:1809:1809) (1846:1846:1846)) + (PORT d (1594:1594:1594) (1730:1730:1730)) + (PORT ena (1696:1696:1696) (1760:1760:1760)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59326,13 +62392,13 @@ (INSTANCE sdram_\|Mux21\~1) (DELAY (ABSOLUTE - (PORT dataa (696:696:696) (743:743:743)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (194:194:194) (226:226:226)) - (PORT datad (638:638:638) (663:663:663)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1594:1594:1594) (1619:1619:1619)) + (PORT datab (1466:1466:1466) (1516:1516:1516)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (855:855:855) (886:886:886)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59343,8 +62409,8 @@ (DELAY (ABSOLUTE (PORT clk (1515:1515:1515) (1539:1539:1539)) - (PORT d (1556:1556:1556) (1651:1651:1651)) - (PORT ena (1611:1611:1611) (1629:1629:1629)) + (PORT d (1247:1247:1247) (1336:1336:1336)) + (PORT ena (1569:1569:1569) (1588:1588:1588)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59355,47 +62421,33 @@ (HOLD ena (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~7) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (997:997:997)) + (PORT datab (782:782:782) (882:882:882)) + (PORT datac (906:906:906) (984:984:984)) + (PORT datad (1097:1097:1097) (1205:1205:1205)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux20\~4) (DELAY (ABSOLUTE - (PORT dataa (748:748:748) (867:867:867)) - (PORT datab (781:781:781) (871:871:871)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1114:1114:1114)) - (PORT datab (2651:2651:2651) (2850:2850:2850)) - (PORT datac (1684:1684:1684) (1854:1854:1854)) - (PORT datad (931:931:931) (983:983:983)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~7) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (926:926:926)) - (PORT datab (897:897:897) (930:930:930)) - (PORT datac (1265:1265:1265) (1390:1390:1390)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1910:1910:1910) (2069:2069:2069)) + (PORT datab (601:601:601) (647:647:647)) + (PORT datac (1632:1632:1632) (1746:1746:1746)) + (PORT datad (233:233:233) (309:309:309)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59403,31 +62455,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~8) + (INSTANCE sdram_\|Mux20\~2) (DELAY (ABSOLUTE - (PORT dataa (1032:1032:1032) (1126:1126:1126)) - (PORT datab (959:959:959) (1003:1003:1003)) - (PORT datac (1256:1256:1256) (1370:1370:1370)) - (PORT datad (1256:1256:1256) (1321:1321:1321)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1700:1700:1700) (1818:1818:1818)) + (PORT datab (259:259:259) (347:347:347)) + (PORT datac (1106:1106:1106) (1165:1165:1165)) + (PORT datad (653:653:653) (705:705:705)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~10) + (INSTANCE sdram_\|Mux20\~3) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1370:1370:1370)) - (PORT datab (658:658:658) (687:687:687)) - (PORT datac (589:589:589) (593:593:593)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1701:1701:1701) (1819:1819:1819)) + (PORT datac (861:861:861) (900:900:900)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59435,15 +62485,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~9) + (INSTANCE sdram_\|r\.address\[4\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1362:1362:1362)) - (PORT datab (660:660:660) (691:691:691)) - (PORT datac (588:588:588) (590:590:590)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (341:341:341) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (1563:1563:1563) (1694:1694:1694)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59451,16 +62499,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~11) + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (406:406:406) (492:492:492)) - (PORT datab (904:904:904) (946:946:946)) - (PORT datac (312:312:312) (339:339:339)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59470,11 +62512,11 @@ (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT clk (1530:1530:1530) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (684:684:684) (700:700:700)) - (PORT sload (1665:1665:1665) (1784:1784:1784)) - (PORT ena (980:980:980) (972:972:972)) + (PORT asdata (523:523:523) (557:557:557)) + (PORT sload (2191:2191:2191) (2334:2334:2334)) + (PORT ena (1460:1460:1460) (1483:1483:1483)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -59487,14 +62529,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~12) + (INSTANCE sdram_\|Mux20\~5) (DELAY (ABSOLUTE - (PORT dataa (714:714:714) (813:813:813)) - (PORT datab (2069:2069:2069) (2248:2248:2248)) - (PORT datac (2283:2283:2283) (2471:2471:2471)) - (PORT datad (867:867:867) (902:902:902)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (1241:1241:1241) (1319:1319:1319)) + (PORT datab (1297:1297:1297) (1404:1404:1404)) + (PORT datac (1487:1487:1487) (1575:1575:1575)) + (PORT datad (1336:1336:1336) (1474:1474:1474)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59503,16 +62545,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~5) + (INSTANCE sdram_\|Mux20\~10) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (654:654:654) (706:706:706)) - (PORT datac (1578:1578:1578) (1695:1695:1695)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1240:1240:1240) (1316:1316:1316)) + (PORT datab (1562:1562:1562) (1695:1695:1695)) + (PORT datac (1488:1488:1488) (1573:1573:1573)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59522,27 +62564,57 @@ (INSTANCE sdram_\|Mux20\~6) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (658:658:658)) - (PORT datab (905:905:905) (948:948:948)) - (PORT datac (994:994:994) (1085:1085:1085)) - (PORT datad (378:378:378) (448:448:448)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (447:447:447) (526:526:526)) + (PORT datad (683:683:683) (749:749:749)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[4\]\~2) + (INSTANCE sdram_\|Mux20\~7) (DELAY (ABSOLUTE - (PORT dataa (1283:1283:1283) (1363:1363:1363)) - (PORT datab (616:616:616) (667:667:667)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1700:1700:1700) (1817:1817:1817)) + (PORT datab (1361:1361:1361) (1511:1511:1511)) + (PORT datac (365:365:365) (387:387:387)) + (PORT datad (1536:1536:1536) (1655:1655:1655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1535:1535:1535) (1655:1655:1655)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (345:345:345)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59552,10 +62624,10 @@ (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (1089:1089:1089) (1165:1165:1165)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1621:1621:1621) (1722:1722:1722)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59567,8 +62639,8 @@ (DELAY (ABSOLUTE (PORT clk (1517:1517:1517) (1542:1542:1542)) - (PORT d (1700:1700:1700) (1761:1761:1761)) - (PORT ena (2295:2295:2295) (2346:2346:2346)) + (PORT d (1665:1665:1665) (1726:1726:1726)) + (PORT ena (2611:2611:2611) (2649:2649:2649)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59579,48 +62651,16 @@ (HOLD ena (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (869:869:869)) - (PORT datab (781:781:781) (872:872:872)) - (PORT datac (630:630:630) (679:679:679)) - (PORT datad (274:274:274) (354:354:354)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~4) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1367:1367:1367)) - (PORT datac (589:589:589) (593:593:593)) - (PORT datad (598:598:598) (611:611:611)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1289:1289:1289) (1364:1364:1364)) - (PORT datab (1055:1055:1055) (1148:1148:1148)) - (PORT datac (1259:1259:1259) (1369:1369:1369)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (223:223:223) (267:267:267)) + (PORT datac (602:602:602) (620:620:620)) + (PORT datad (1515:1515:1515) (1610:1610:1610)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59630,10 +62670,10 @@ (INSTANCE sdram_\|Mux19\~6) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1371:1371:1371)) - (PORT datab (1057:1057:1057) (1150:1150:1150)) - (PORT datac (1257:1257:1257) (1371:1371:1371)) - (PORT datad (181:181:181) (211:211:211)) + (PORT dataa (1437:1437:1437) (1591:1591:1591)) + (PORT datab (1637:1637:1637) (1751:1751:1751)) + (PORT datac (350:350:350) (379:379:379)) + (PORT datad (1376:1376:1376) (1465:1465:1465)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -59641,17 +62681,33 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1585:1585:1585)) + (PORT datab (1637:1637:1637) (1743:1743:1743)) + (PORT datac (352:352:352) (381:381:381)) + (PORT datad (1376:1376:1376) (1462:1462:1462)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~7) (DELAY (ABSOLUTE - (PORT dataa (1377:1377:1377) (1426:1426:1426)) - (PORT datab (404:404:404) (482:482:482)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (407:407:407) (479:479:479)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1367:1367:1367) (1437:1437:1437)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59662,11 +62718,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT clk (1531:1531:1531) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (524:524:524) (559:559:559)) - (PORT sload (1665:1665:1665) (1784:1784:1784)) - (PORT ena (980:980:980) (972:972:972)) + (PORT asdata (676:676:676) (702:702:702)) + (PORT sload (1918:1918:1918) (2069:2069:2069)) + (PORT ena (1521:1521:1521) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -59679,13 +62735,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~2) + (INSTANCE sdram_\|Mux19\~1) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (889:889:889) (939:939:939)) - (PORT datac (1575:1575:1575) (1696:1696:1696)) - (PORT datad (635:635:635) (714:714:714)) + (PORT dataa (639:639:639) (672:672:672)) + (PORT datab (1182:1182:1182) (1258:1258:1258)) + (PORT datac (378:378:378) (445:445:445)) + (PORT datad (1376:1376:1376) (1462:1462:1462)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -59693,18 +62749,34 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1019:1019:1019)) + (PORT datab (1160:1160:1160) (1269:1269:1269)) + (PORT datac (751:751:751) (844:844:844)) + (PORT datad (1093:1093:1093) (1198:1198:1198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~3) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (656:656:656)) - (PORT datab (1058:1058:1058) (1148:1148:1148)) - (PORT datac (1348:1348:1348) (1386:1386:1386)) - (PORT datad (380:380:380) (445:445:445)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (617:617:617) (645:645:645)) + (PORT datab (406:406:406) (476:476:476)) + (PORT datac (613:613:613) (623:623:623)) + (PORT datad (1366:1366:1366) (1436:1436:1436)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59714,11 +62786,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1290:1290:1290) (1371:1371:1371)) - (PORT datab (642:642:642) (688:688:688)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1636:1636:1636) (1751:1751:1751)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59728,12 +62800,12 @@ (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1091:1091:1091) (1170:1170:1170)) - (PORT datac (181:181:181) (218:218:218)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1333:1333:1333) (1457:1457:1457)) + (PORT datad (195:195:195) (220:220:220)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -59743,8 +62815,8 @@ (DELAY (ABSOLUTE (PORT clk (1514:1514:1514) (1539:1539:1539)) - (PORT d (1443:1443:1443) (1520:1520:1520)) - (PORT ena (2198:2198:2198) (2202:2202:2202)) + (PORT d (1250:1250:1250) (1340:1340:1340)) + (PORT ena (1955:1955:1955) (2028:2028:2028)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59760,9 +62832,9 @@ (INSTANCE sdram_\|Mux18\~0) (DELAY (ABSOLUTE - (PORT dataa (2415:2415:2415) (2626:2626:2626)) - (PORT datac (1237:1237:1237) (1358:1358:1358)) - (PORT datad (667:667:667) (699:699:699)) + (PORT dataa (1338:1338:1338) (1486:1486:1486)) + (PORT datac (1130:1130:1130) (1202:1202:1202)) + (PORT datad (1551:1551:1551) (1578:1578:1578)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59775,8 +62847,8 @@ (DELAY (ABSOLUTE (PORT clk (1515:1515:1515) (1539:1539:1539)) - (PORT d (1527:1527:1527) (1623:1623:1623)) - (PORT ena (1611:1611:1611) (1629:1629:1629)) + (PORT d (1490:1490:1490) (1582:1582:1582)) + (PORT ena (1569:1569:1569) (1588:1588:1588)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59789,12 +62861,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux17\~0) + (INSTANCE sdram_\|Mux17\~2) (DELAY (ABSOLUTE - (PORT dataa (2411:2411:2411) (2624:2624:2624)) - (PORT datac (1497:1497:1497) (1597:1597:1597)) - (PORT datad (667:667:667) (698:698:698)) + (PORT dataa (1338:1338:1338) (1484:1484:1484)) + (PORT datac (873:873:873) (953:953:953)) + (PORT datad (1553:1553:1553) (1573:1573:1573)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59807,8 +62879,8 @@ (DELAY (ABSOLUTE (PORT clk (1513:1513:1513) (1537:1537:1537)) - (PORT d (1993:1993:1993) (2101:2101:2101)) - (PORT ena (1609:1609:1609) (1676:1676:1676)) + (PORT d (1907:1907:1907) (2009:2009:2009)) + (PORT ena (1784:1784:1784) (1824:1824:1824)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59821,12 +62893,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux16\~0) + (INSTANCE sdram_\|Mux16\~2) (DELAY (ABSOLUTE - (PORT dataa (2422:2422:2422) (2635:2635:2635)) - (PORT datac (243:243:243) (322:322:322)) - (PORT datad (667:667:667) (698:698:698)) + (PORT dataa (1341:1341:1341) (1483:1483:1483)) + (PORT datac (1154:1154:1154) (1207:1207:1207)) + (PORT datad (1553:1553:1553) (1578:1578:1578)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59839,8 +62911,8 @@ (DELAY (ABSOLUTE (PORT clk (1495:1495:1495) (1520:1520:1520)) - (PORT d (2142:2142:2142) (2266:2266:2266)) - (PORT ena (1415:1415:1415) (1456:1456:1456)) + (PORT d (1804:1804:1804) (1915:1915:1915)) + (PORT ena (1774:1774:1774) (1848:1848:1848)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -59856,11 +62928,11 @@ (INSTANCE sdram_\|Mux15\~2) (DELAY (ABSOLUTE - (PORT dataa (2424:2424:2424) (2635:2635:2635)) - (PORT datab (933:933:933) (1032:1032:1032)) - (PORT datad (667:667:667) (702:702:702)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1333:1333:1333) (1479:1479:1479)) + (PORT datac (1411:1411:1411) (1464:1464:1464)) + (PORT datad (1551:1551:1551) (1573:1573:1573)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59871,8 +62943,8 @@ (DELAY (ABSOLUTE (PORT clk (1497:1497:1497) (1522:1522:1522)) - (PORT d (2142:2142:2142) (2261:2261:2261)) - (PORT ena (1453:1453:1453) (1505:1505:1505)) + (PORT d (2038:2038:2038) (2128:2128:2128)) + (PORT ena (1775:1775:1775) (1850:1850:1850)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -59885,79 +62957,23 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~0) + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (737:737:737)) - (PORT datab (711:711:711) (800:800:800)) - (PORT datac (1260:1260:1260) (1352:1352:1352)) - (PORT datad (181:181:181) (207:207:207)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~1) + (INSTANCE sdram_\|n\~5) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (729:729:729)) - (PORT datab (407:407:407) (478:478:478)) - (PORT datac (1035:1035:1035) (1137:1137:1137)) - (PORT datad (627:627:627) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[10\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (993:993:993) (1068:1068:1068)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1560:1560:1560)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (523:523:523) (557:557:557)) - (PORT sload (1639:1639:1639) (1751:1751:1751)) - (PORT ena (1247:1247:1247) (1254:1254:1254)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~4) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (923:923:923)) - (PORT datab (406:406:406) (476:476:476)) - (PORT datac (676:676:676) (747:747:747)) - (PORT datad (675:675:675) (725:725:725)) + (PORT dataa (947:947:947) (996:996:996)) + (PORT datab (784:784:784) (877:877:877)) + (PORT datac (911:911:911) (985:985:985)) + (PORT datad (404:404:404) (466:466:466)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -59970,12 +62986,12 @@ (INSTANCE sdram_\|Mux14\~2) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (740:740:740)) - (PORT datab (712:712:712) (801:801:801)) - (PORT datac (1257:1257:1257) (1357:1357:1357)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (946:946:946) (1047:1047:1047)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1097:1097:1097) (1206:1206:1206)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59986,28 +63002,94 @@ (INSTANCE sdram_\|Mux14\~3) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (406:406:406) (474:474:474)) - (PORT datac (381:381:381) (407:407:407)) - (PORT datad (632:632:632) (657:657:657)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (666:666:666) (705:705:705)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (202:202:202) (238:238:238)) + (PORT datad (315:315:315) (325:325:325)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (556:556:556)) + (PORT sload (1900:1900:1900) (2061:2061:2061)) + (PORT ena (842:842:842) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (609:609:609)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (1050:1050:1050) (1142:1142:1142)) + (PORT datad (639:639:639) (664:664:664)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1049:1049:1049)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1097:1097:1097) (1204:1204:1204)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (1073:1073:1073) (1173:1173:1173)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (327:327:327) (344:344:344)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (1064:1064:1064) (1139:1139:1139)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1315:1315:1315) (1450:1450:1450)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (179:179:179) (216:216:216)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -60017,8 +63099,8 @@ (DELAY (ABSOLUTE (PORT clk (1488:1488:1488) (1513:1513:1513)) - (PORT d (1458:1458:1458) (1539:1539:1539)) - (PORT ena (1669:1669:1669) (1698:1698:1698)) + (PORT d (1561:1561:1561) (1677:1677:1677)) + (PORT ena (1666:1666:1666) (1721:1721:1721)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -60031,14 +63113,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~18) + (INSTANCE sdram_\|r\.address\[11\]\~21) (DELAY (ABSOLUTE - (PORT datab (766:766:766) (848:848:848)) - (PORT datac (1262:1262:1262) (1381:1381:1381)) - (PORT datad (735:735:735) (822:822:822)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1437:1437:1437) (1585:1585:1585)) + (PORT datab (1636:1636:1636) (1742:1742:1742)) + (PORT datac (1083:1083:1083) (1121:1121:1121)) + (PORT datad (661:661:661) (724:724:724)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (1634:1634:1634) (1746:1746:1746)) + (PORT datac (1822:1822:1822) (1913:1913:1913)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -60048,37 +63146,26 @@ (INSTANCE sdram_\|r\.address\[11\]\~5) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1091:1091:1091)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1639:1639:1639) (1751:1751:1751)) + (PORT datad (577:577:577) (595:595:595)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1559:1559:1559)) + (PORT clk (1531:1531:1531) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (530:530:530) (570:570:570)) - (PORT sload (1322:1322:1322) (1457:1457:1457)) - (PORT ena (1290:1290:1290) (1318:1318:1318)) + (PORT asdata (869:869:869) (879:879:879)) + (PORT sload (1918:1918:1918) (2069:2069:2069)) + (PORT ena (1276:1276:1276) (1258:1258:1258)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -60094,11 +63181,11 @@ (INSTANCE sdram_\|Mux13\~10) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (334:334:334)) - (PORT datac (768:768:768) (884:884:884)) - (PORT datad (677:677:677) (777:777:777)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1437:1437:1437) (1588:1588:1588)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (1599:1599:1599) (1709:1709:1709)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -60108,13 +63195,13 @@ (INSTANCE sdram_\|Mux13\~6) (DELAY (ABSOLUTE - (PORT dataa (793:793:793) (920:920:920)) - (PORT datab (895:895:895) (926:926:926)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (818:818:818) (836:836:836)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (619:619:619) (643:643:643)) + (PORT datab (1186:1186:1186) (1263:1263:1263)) + (PORT datac (1402:1402:1402) (1552:1552:1552)) + (PORT datad (319:319:319) (329:329:329)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -60124,12 +63211,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (270:270:270)) - (PORT datab (737:737:737) (847:847:847)) - (PORT datac (189:189:189) (231:231:231)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (1302:1302:1302) (1422:1422:1422)) + (PORT datad (321:321:321) (338:338:338)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -60138,9 +63225,9 @@ (INSTANCE sdram_\|r\.address\[11\]) (DELAY (ABSOLUTE - (PORT clk (1502:1502:1502) (1530:1530:1530)) - (PORT d (1252:1252:1252) (1354:1354:1354)) - (PORT ena (1396:1396:1396) (1412:1412:1412)) + (PORT clk (1491:1491:1491) (1515:1515:1515)) + (PORT d (1544:1544:1544) (1627:1627:1627)) + (PORT ena (2237:2237:2237) (2280:2280:2280)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -60156,12 +63243,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (267:267:267)) - (PORT datab (738:738:738) (843:843:843)) - (PORT datac (187:187:187) (229:229:229)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (226:226:226) (268:268:268)) + (PORT datac (1302:1302:1302) (1422:1422:1422)) + (PORT datad (321:321:321) (339:339:339)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -60171,8 +63258,8 @@ (DELAY (ABSOLUTE (PORT clk (1493:1493:1493) (1518:1518:1518)) - (PORT d (1706:1706:1706) (1798:1798:1798)) - (PORT ena (1700:1700:1700) (1737:1737:1737)) + (PORT d (1762:1762:1762) (1884:1884:1884)) + (PORT ena (2226:2226:2226) (2288:2288:2288)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 749c3f8..b37083f 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/02/2022 14:51:20" +// DATE "04/06/2022 13:58:28" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -60,14 +60,18 @@ module spectrum ( DRAM_WE_N, DRAM_CS_N, DRAM_DQ, - DRAM_ADDR); + DRAM_ADDR, + kempston, + kempston_gnd, + turbo_button, + kempston_autofire_button); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -inout I2C_SCLK; -inout I2C_SDAT; +output I2C_SCLK; +output I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -80,7 +84,7 @@ output [3:0] VGA_B; output VGA_HS; output VGA_VS; input [3:0] SW; -output [33:0] GPIO_1; +output [31:0] GPIO_1; output buzzer_out; input raw_loader_in; output [1:0] DRAM_BA; @@ -91,8 +95,12 @@ output DRAM_CKE; output DRAM_CLK; output DRAM_WE_N; output DRAM_CS_N; -inout [15:0] DRAM_DQ; +output [15:0] DRAM_DQ; output [12:0] DRAM_ADDR; +input [4:0] kempston; +output kempston_gnd; +input turbo_button; +input kempston_autofire_button; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -123,6 +131,7 @@ output [12:0] DRAM_ADDR; // VGA_HS => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // VGA_VS => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[0] => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[3] => Location: PIN_M15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // GPIO_1[0] => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[1] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -156,8 +165,6 @@ output [12:0] DRAM_ADDR; // GPIO_1[29] => Location: PIN_L13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[30] => Location: PIN_J16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[31] => Location: PIN_K15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -// GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -182,6 +189,7 @@ output [12:0] DRAM_ADDR; // DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// kempston_gnd => Location: PIN_B3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -201,10 +209,16 @@ output [12:0] DRAM_ADDR; // DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default -// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[0] => Location: PIN_B4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[1] => Location: PIN_A4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[2] => Location: PIN_B5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[3] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston[4] => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default // CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// turbo_button => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// kempston_autofire_button => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default // KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default // PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -227,6 +241,7 @@ initial $sdf_annotate("spectrum_min_1200mv_0c_v_fast.sdo"); // synopsys translate_on wire \SW[0]~input_o ; +wire \SW[2]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; wire \DRAM_DQ[0]~input_o ; @@ -248,13 +263,69 @@ wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \turbo_button~input_o ; +wire \CLOCK_50~inputclkctrl_outclk ; +wire \debounce_turbo|r_Count[0]~21_combout ; +wire \debounce_turbo|r_Count[0]~22 ; +wire \debounce_turbo|r_Count[1]~23_combout ; +wire \debounce_turbo|r_Count[1]~24 ; +wire \debounce_turbo|r_Count[2]~25_combout ; +wire \debounce_turbo|r_Count[2]~26 ; +wire \debounce_turbo|r_Count[3]~27_combout ; +wire \debounce_turbo|r_Count[3]~28 ; +wire \debounce_turbo|r_Count[4]~29_combout ; +wire \debounce_turbo|r_Count[4]~30 ; +wire \debounce_turbo|r_Count[5]~31_combout ; +wire \debounce_turbo|r_Count[5]~32 ; +wire \debounce_turbo|r_Count[6]~33_combout ; +wire \debounce_turbo|r_Count[6]~34 ; +wire \debounce_turbo|r_Count[7]~35_combout ; +wire \debounce_turbo|r_Count[7]~36 ; +wire \debounce_turbo|r_Count[8]~37_combout ; +wire \debounce_turbo|r_Count[8]~38 ; +wire \debounce_turbo|r_Count[9]~39_combout ; +wire \debounce_turbo|r_Count[9]~40 ; +wire \debounce_turbo|r_Count[10]~41_combout ; +wire \debounce_turbo|r_Count[10]~42 ; +wire \debounce_turbo|r_Count[11]~43_combout ; +wire \debounce_turbo|r_Count[11]~44 ; +wire \debounce_turbo|r_Count[12]~45_combout ; +wire \debounce_turbo|r_Count[12]~46 ; +wire \debounce_turbo|r_Count[13]~47_combout ; +wire \debounce_turbo|r_State~7_combout ; +wire \debounce_turbo|LessThan0~0_combout ; +wire \debounce_turbo|LessThan0~1_combout ; +wire \debounce_turbo|r_Count[13]~48 ; +wire \debounce_turbo|r_Count[14]~49_combout ; +wire \debounce_turbo|r_Count[14]~50 ; +wire \debounce_turbo|r_Count[15]~51_combout ; +wire \debounce_turbo|r_Count[15]~52 ; +wire \debounce_turbo|r_Count[16]~53_combout ; +wire \debounce_turbo|r_Count[16]~54 ; +wire \debounce_turbo|r_Count[17]~55_combout ; +wire \debounce_turbo|r_Count[17]~56 ; +wire \debounce_turbo|r_Count[18]~57_combout ; +wire \debounce_turbo|r_Count[18]~58 ; +wire \debounce_turbo|r_Count[19]~59_combout ; +wire \debounce_turbo|always0~0_combout ; +wire \debounce_turbo|always0~1_combout ; +wire \debounce_turbo|r_Count[19]~60 ; +wire \debounce_turbo|r_Count[20]~61_combout ; +wire \debounce_turbo|always0~2_combout ; +wire \debounce_turbo|r_State~4_combout ; +wire \debounce_turbo|r_State~2_combout ; +wire \debounce_turbo|r_State~0_combout ; +wire \debounce_turbo|r_State~1_combout ; +wire \debounce_turbo|r_State~3_combout ; +wire \debounce_turbo|r_State~5_combout ; +wire \debounce_turbo|r_State~6_combout ; +wire \debounce_turbo|r_State~q ; +wire \turbo~0_combout ; +wire \turbo~q ; wire \ula_|clocks_|counter[0]~0_combout ; -wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \KEY[1]~input_o ; -wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -263,12 +334,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \KEY[1]~input_o ; +wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; @@ -279,16 +351,9 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; +wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Add0~9 ; -wire \ula_|video_|Add0~10_combout ; -wire \ula_|video_|vga_hc~0_combout ; -wire \ula_|video_|Add0~11 ; -wire \ula_|video_|Add0~12_combout ; -wire \ula_|video_|Add0~13 ; -wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Equal0~0_combout ; wire \ula_|video_|Equal0~1_combout ; wire \ula_|video_|Add0~15 ; wire \ula_|video_|Add0~16_combout ; @@ -297,6 +362,30 @@ wire \ula_|video_|Add0~17 ; wire \ula_|video_|Add0~18_combout ; wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add0~9 ; +wire \ula_|video_|Add0~10_combout ; +wire \ula_|video_|vga_hc~0_combout ; +wire \ula_|video_|Add0~11 ; +wire \ula_|video_|Add0~12_combout ; +wire \ula_|video_|Add0~13 ; +wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Add1~11 ; +wire \ula_|video_|Add1~12_combout ; +wire \ula_|video_|vga_vc[6]~4_combout ; +wire \ula_|video_|Add1~13 ; +wire \ula_|video_|Add1~14_combout ; +wire \ula_|video_|vga_vc[7]~6_combout ; +wire \ula_|video_|Add1~15 ; +wire \ula_|video_|Add1~16_combout ; +wire \ula_|video_|vga_vc[8]~7_combout ; +wire \ula_|video_|Add1~17 ; +wire \ula_|video_|Add1~18_combout ; +wire \ula_|video_|vga_vc[9]~9_combout ; +wire \ula_|video_|Equal2~0_combout ; +wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Add1~1 ; wire \ula_|video_|Add1~2_combout ; wire \ula_|video_|vga_vc[1]~1_combout ; @@ -312,163 +401,1526 @@ wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; wire \ula_|video_|Add1~10_combout ; wire \ula_|video_|vga_vc[5]~8_combout ; -wire \ula_|video_|Add1~11 ; -wire \ula_|video_|Add1~12_combout ; -wire \ula_|video_|vga_vc[6]~4_combout ; -wire \ula_|video_|Add1~13 ; -wire \ula_|video_|Add1~14_combout ; -wire \ula_|video_|vga_vc[7]~6_combout ; -wire \ula_|video_|Add1~15 ; -wire \ula_|video_|Add1~16_combout ; -wire \ula_|video_|vga_vc[8]~7_combout ; -wire \ula_|video_|Add1~17 ; -wire \ula_|video_|Add1~18_combout ; -wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal3~0_combout ; -wire \ula_|video_|Equal2~0_combout ; -wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|Add1~0_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; wire \SW[1]~input_o ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|ir_|opcode[4]~feeder_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|pla_decode_|Equal1~0_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal1~1_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_state_alu~2_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; wire \z80_|pla_decode_|Equal21~0_combout ; wire \z80_|execute_|ctl_mRead~3_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_sw_1d~2_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_sw_1d~3_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~3_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~2_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_mWrite~19_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_bus_db_oe~8_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; wire \z80_|pla_decode_|Equal9~0_combout ; wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_ir_we~16_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|execute_|fMWrite~0_combout ; -wire \z80_|execute_|ctl_inc_cy~97_combout ; -wire \z80_|execute_|ctl_inc_cy~96_combout ; -wire \z80_|execute_|ctl_inc_cy~98_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|fMWrite~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|execute_|ctl_mWrite~17_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|pla_decode_|Equal6~2_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~2_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; +wire \z80_|execute_|ctl_bus_db_oe~5_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~3_combout ; +wire \z80_|execute_|ctl_bus_db_oe~combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op_low~13_combout ; +wire \z80_|execute_|ctl_alu_op_low~12_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~16_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_alu_op_low~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_inc_cy~28_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~13_combout ; +wire \z80_|execute_|ctl_ir_we~19_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_inc_cy~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_out_hi~3_combout ; +wire \z80_|execute_|ctl_sw_2u~9_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|pla_decode_|Equal13~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_sw_2u~8_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|ctl_sw_4d~9_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|pla_decode_|Equal1~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_reg_out_hi~2_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~15_combout ; +wire \z80_|execute_|ctl_flags_pf_we~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~1_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_oe~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~50_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~49_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~51_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~48_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~17_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~22_combout ; +wire \z80_|pla_decode_|Equal5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~7_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|ctl_al_we~3_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_al_we~2_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~9_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_low[3]~2_combout ; +wire \z80_|alu_|db_low[3]~3_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~24_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~25_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~14_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_reg_gp_we~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~22_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~21_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~19_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~8_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_sw_4d~8_combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~17_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~18_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~23_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|reg_file_|db_hi_as[0]~3_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~14_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|pla_decode_|Equal1~3_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|pla_decode_|Equal2~4_combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~23_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~29_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~26_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~32_combout ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|pc_inc_hold~38_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~37_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~30_combout ; +wire \z80_|execute_|ctl_inc_cy~31_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|Q[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~33_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~13_combout ; +wire \z80_|reg_file_|db_lo_as[3]~14_combout ; +wire \z80_|reg_file_|db_lo_as[3]~15_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~58_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~59_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~61_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~62_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~63_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~65_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~70_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~72_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~73_combout ; +wire \z80_|reg_file_|db_lo_as[4]~16_combout ; +wire \z80_|reg_file_|db_lo_as[4]~17_combout ; +wire \z80_|reg_file_|db_lo_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~49_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~14_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|alu_op1[1]~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; +wire \z80_|pla_decode_|Equal72~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|execute_|ctl_mWrite~20_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~23_combout ; +wire \z80_|reg_file_|db_lo_ds[0]~4_combout ; +wire \z80_|alu_control_|db[0]~23_combout ; +wire \z80_|alu_control_|db[0]~24_combout ; +wire \z80_|alu_control_|db[0]~25_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ; +wire \z80_|execute_|ctl_flags_cf2_we~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~77_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~79_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~83_combout ; +wire \z80_|reg_file_|db_hi_as[7]~23_combout ; +wire \z80_|reg_file_|db_hi_as[7]~24_combout ; +wire \z80_|reg_file_|db_hi_as[7]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~84_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|pla_decode_|Equal71~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|execute_|ctl_flags_nf_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|execute_|ctl_alu_core_hf~39_combout ; +wire \z80_|execute_|ctl_alu_core_hf~40_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|alu_op2[1]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~19_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|db_hi_as[5]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|db_low[2]~6_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~7_combout ; +wire \z80_|alu_|db_low[2]~8_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~13_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~8_combout ; +wire \z80_|reg_file_|db_lo_ds[5]~0_combout ; +wire \z80_|alu_control_|db[5]~9_combout ; +wire \z80_|alu_control_|db[5]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~48_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~53_combout ; +wire \z80_|reg_file_|db_lo_as[5]~10_combout ; +wire \z80_|reg_file_|db_lo_as[5]~11_combout ; +wire \z80_|reg_file_|db_lo_as[5]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~7_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db_low[1]~13_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ; +wire \z80_|alu_|db_low[0]~18_combout ; +wire \z80_|alu_|db_low[0]~19_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_low[0]~20_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|alu_|db_low[3]~0_combout ; +wire \z80_|alu_|db_low[3]~1_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~19_combout ; +wire \z80_|alu_control_|db[2]~26_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~5_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~q ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; +wire \z80_|alu_control_|flags_cond_true~0_combout ; +wire \z80_|alu_control_|flags_cond_true~q ; +wire \z80_|execute_|ctl_reg_sel_wz~28_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~23_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~21_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~2_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~13_combout ; +wire \z80_|reg_file_|db_lo_ds[7]~1_combout ; +wire \z80_|alu_control_|db[7]~14_combout ; +wire \z80_|alu_control_|db[7]~15_combout ; +wire \z80_|bus_control_|db[7]~4_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|nextM~16_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|ctl_ir_we~20_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~38_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|pin_control_|bus_db_pin_re~2_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; @@ -478,1535 +1930,104 @@ wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|execute_|ctl_mWrite~18_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_flags_alu~21_combout ; -wire \z80_|execute_|ctl_flags_alu~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_flags_alu~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ixy_d~15_combout ; wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; wire \z80_|memory_ifc_|mwr_wr~q ; wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|execute_|ctl_mRead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|execute_|setM1~57_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|pla_decode_|Equal40~2_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|pc_inc_hold~14_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_inc_cy~99_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|pla_decode_|Equal76~2_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~11_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|pla_decode_|Equal10~1_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|reg_control_|reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|setM1~56_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|reg_control_|reg_sel_de2~2_combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_reg_gp_we~9_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~7_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_we~8_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_core_hf~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~39_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~23_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_flags_alu~19_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|alu_|db_high[3]~0_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; -wire \z80_|reg_control_|reg_sel_de2~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; -wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; -wire \z80_|alu_|db[3]~13_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|sw1_|db_down[3]~3_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|execute_|pc_inc_hold~25_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|pc_inc_hold~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~17_combout ; -wire \z80_|execute_|pc_inc_hold~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~20_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|pc_inc_hold~15_combout ; -wire \z80_|execute_|pc_inc_hold~16_combout ; -wire \z80_|execute_|pc_inc_hold~21_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~22_combout ; -wire \z80_|execute_|pc_inc_hold~23_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~24_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|execute_|ctl_inc_cy~95_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; -wire \z80_|execute_|pc_inc_hold~27_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|pc_inc_hold~26_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|ctl_inc_cy~100_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_low[2]~9_combout ; -wire \z80_|alu_|db_low[2]~10_combout ; -wire \z80_|alu_|db_high[3]~1_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~38_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|execute_|ctl_alu_op_low~40_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[7]~16_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[7]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; -wire \z80_|alu_control_|db[6]~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_control_|db[7]~19_combout ; -wire \z80_|alu_control_|db[7]~20_combout ; -wire \z80_|alu_control_|db[7]~37_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; -wire \z80_|reg_file_|db_hi_as[2]~10_combout ; -wire \z80_|reg_file_|db_hi_as[2]~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[2]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; -wire \z80_|alu_|db[4]~8_combout ; -wire \z80_|alu_|db[4]~10_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; -wire \z80_|reg_file_|db_hi_as[4]~13_combout ; -wire \z80_|reg_file_|db_hi_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[1]~18_combout ; -wire \z80_|alu_|db_low[1]~19_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|db_low[1]~20_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~8_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; -wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; -wire \z80_|reg_file_|db_hi_as[6]~19_combout ; -wire \z80_|reg_file_|db_hi_as[6]~20_combout ; -wire \z80_|reg_file_|db_hi_as[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; -wire \z80_|alu_|db[6]~21_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~14_combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db[5]~23_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; -wire \z80_|reg_file_|db_hi_as[5]~22_combout ; -wire \z80_|reg_file_|db_hi_as[5]~23_combout ; -wire \z80_|reg_file_|db_hi_as[5]~24_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; -wire \z80_|alu_|db[7]~19_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|alu_op1[3]~0_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|alu_op2[2]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|db_low[0]~24_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db_low[0]~25_combout ; -wire \z80_|alu_|db_low[0]~27_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~13_combout ; -wire \z80_|execute_|ctl_alu_core_hf~14_combout ; -wire \z80_|execute_|ctl_alu_core_hf~15_combout ; -wire \z80_|execute_|ctl_alu_core_hf~16_combout ; -wire \z80_|execute_|ctl_alu_core_hf~17_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_alu_op_low~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|alu_|db_high[0]~20_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_low[2]~11_combout ; -wire \z80_|alu_|db_low[2]~12_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|alu_|db_low[2]~13_combout ; -wire \z80_|alu_|db_low[2]~14_combout ; -wire \z80_|alu_|db[2]~11_combout ; -wire \z80_|alu_|db[2]~12_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|alu_control_|db[2]~24_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_control_|db[2]~30_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|alu_|db[0]~17_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~11_combout ; -wire \z80_|alu_control_|db[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|Q[1]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|alu_control_|db[3]~36_combout ; -wire \z80_|alu_|db[3]~14_combout ; -wire \z80_|alu_|db_low[3]~4_combout ; -wire \z80_|alu_|db_low[3]~5_combout ; -wire \z80_|alu_|db_low[3]~6_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~26_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; -wire \z80_|alu_|alu_op2[3]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \z80_|alu_control_|db[4]~33_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; -wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; -wire \z80_|alu_control_|flags_cond_true~0_combout ; -wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|reg_file_|db_hi_as[3]~7_combout ; -wire \z80_|reg_file_|db_hi_as[3]~8_combout ; -wire \z80_|reg_file_|db_hi_as[3]~9_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \D[0]~49_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \Equal5~0_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~20_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~43_combout ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; +wire \Equal3~0_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; +wire \z80_|address_pins_|abus[6]~25_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; +wire \z80_|address_pins_|abus[7]~26_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; +wire \Equal3~1_combout ; +wire \Equal3~2_combout ; +wire \D[5]~26_combout ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|abus[15]~23_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~22_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~44_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~24_combout ; wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~45_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \D[2]~42_combout ; -wire \D[2]~46_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|control_pins_|pin_nIORQ~1_combout ; -wire \Equal2~0_combout ; -wire \z80_|address_pins_|abus[13]~23_combout ; +wire \z80_|address_pins_|abus[13]~20_combout ; wire \ExtRamWE~0_combout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; -wire \z80_|address_pins_|abus[1]~25_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; -wire \z80_|address_pins_|abus[2]~26_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ; -wire \z80_|address_pins_|abus[3]~27_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ; -wire \z80_|address_pins_|abus[4]~28_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ; -wire \z80_|address_pins_|abus[5]~29_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; -wire \z80_|address_pins_|abus[6]~30_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; -wire \z80_|address_pins_|abus[7]~31_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \D[2]~50_combout ; -wire \D[2]~51_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; -wire \CLOCK_50~inputclkctrl_outclk ; +wire \z80_|address_pins_|abus[0]~24_combout ; +wire \z80_|address_pins_|abus[1]~27_combout ; +wire \z80_|address_pins_|abus[2]~28_combout ; +wire \z80_|address_pins_|abus[3]~29_combout ; +wire \z80_|address_pins_|abus[4]~30_combout ; +wire \z80_|address_pins_|abus[5]~31_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~16_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~18_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; wire \~GND~combout ; +wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; -wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -2018,521 +2039,710 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[8]~1_combout ; +wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Selector0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \Selector0~1_combout ; +wire \D[7]~36_combout ; +wire \D[7]~37_combout ; +wire \D[7]~48_combout ; +wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; +wire \z80_|bus_control_|db[7]~6_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~9_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|setM1~59_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal5~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~47_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~48_combout ; -wire \D[2]~49_combout ; -wire \D[2]~119_combout ; -wire \D[2]~52_combout ; -wire \D[2]~53_combout ; -wire \z80_|pin_control_|bus_db_pin_re~2_combout ; -wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[0]~6_combout ; +wire \Selector10~0_combout ; +wire \Selector10~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|keys[3][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~5_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~46_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~4_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~7_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|keys[4][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|key_row[2]~6_combout ; +wire \Selector14~17_combout ; +wire \Selector14~18_combout ; +wire \kempston[1]~input_o ; +wire \Selector10~2_combout ; +wire \Selector10~3_combout ; +wire \D[2]~13_combout ; wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|ir_|opcode[2]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|alu_control_|db[6]~13_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; -wire \z80_|sw1_|db_down[6]~1_combout ; -wire \z80_|alu_control_|db[6]~23_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|bus_control_|db[2]~14_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_ir_we~17_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal2~3_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_66_oe~4_combout ; +wire \z80_|alu_control_|db[6]~16_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~2_combout ; +wire \z80_|alu_control_|db[6]~17_combout ; +wire \z80_|alu_control_|db[6]~18_combout ; +wire \z80_|bus_control_|db[6]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \raw_loader_in~input_o ; +wire \D[6]~28_combout ; +wire \D[6]~43_combout ; +wire \D[6]~44_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~103_combout ; -wire \D[6]~104_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~42_combout ; +wire \D[6]~45_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~100_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~101_combout ; -wire \D[6]~102_combout ; -wire \D[6]~127_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~99_combout ; -wire \D[6]~114_combout ; -wire \D[6]~115_combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Mux1~0_combout ; +wire \D[6]~41_combout ; +wire \D[6]~46_combout ; +wire \D[6]~47_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|execute_|ctl_ir_we~18_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~16_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~9_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~10_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~130_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~11_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys~74_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~72_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~69_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~8_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|key_row[0]~9_combout ; +wire \kempston[3]~input_o ; +wire \Selector14~8_combout ; +wire \Selector14~13_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector14~19_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \Selector14~10_combout ; +wire \Selector14~11_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector14~20_combout ; +wire \Selector14~9_combout ; +wire \Selector14~12_combout ; +wire \Selector14~14_combout ; +wire \D[0]~14_combout ; +wire \z80_|bus_control_|db[0]~11_combout ; +wire \z80_|bus_control_|db[0]~12_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~29_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~16_combout ; +wire \debounce_autofire|r_Count[0]~21_combout ; +wire \debounce_autofire|r_Count[0]~22 ; +wire \debounce_autofire|r_Count[1]~23_combout ; +wire \debounce_autofire|r_Count[1]~24 ; +wire \debounce_autofire|r_Count[2]~25_combout ; +wire \debounce_autofire|r_Count[2]~26 ; +wire \debounce_autofire|r_Count[3]~27_combout ; +wire \debounce_autofire|r_Count[3]~28 ; +wire \debounce_autofire|r_Count[4]~29_combout ; +wire \debounce_autofire|r_Count[4]~30 ; +wire \debounce_autofire|r_Count[5]~31_combout ; +wire \debounce_autofire|r_Count[5]~32 ; +wire \debounce_autofire|r_Count[6]~33_combout ; +wire \debounce_autofire|r_Count[6]~34 ; +wire \debounce_autofire|r_Count[7]~35_combout ; +wire \debounce_autofire|r_Count[7]~36 ; +wire \debounce_autofire|r_Count[8]~37_combout ; +wire \debounce_autofire|r_Count[8]~38 ; +wire \debounce_autofire|r_Count[9]~39_combout ; +wire \debounce_autofire|r_Count[9]~40 ; +wire \debounce_autofire|r_Count[10]~41_combout ; +wire \debounce_autofire|r_Count[10]~42 ; +wire \debounce_autofire|r_Count[11]~43_combout ; +wire \debounce_autofire|r_Count[11]~44 ; +wire \debounce_autofire|r_Count[12]~45_combout ; +wire \debounce_autofire|r_Count[12]~46 ; +wire \debounce_autofire|r_Count[13]~47_combout ; +wire \debounce_autofire|r_Count[13]~48 ; +wire \debounce_autofire|r_Count[14]~49_combout ; +wire \debounce_autofire|r_Count[14]~50 ; +wire \debounce_autofire|r_Count[15]~51_combout ; +wire \debounce_autofire|r_Count[15]~52 ; +wire \debounce_autofire|r_Count[16]~53_combout ; +wire \debounce_autofire|r_Count[16]~54 ; +wire \debounce_autofire|r_Count[17]~55_combout ; +wire \debounce_autofire|r_Count[17]~56 ; +wire \debounce_autofire|r_Count[18]~57_combout ; +wire \debounce_autofire|r_Count[18]~58 ; +wire \debounce_autofire|r_Count[19]~59_combout ; +wire \debounce_autofire|r_Count[19]~60 ; +wire \debounce_autofire|r_Count[20]~61_combout ; +wire \kempston_autofire_button~input_o ; +wire \debounce_autofire|r_State~7_combout ; +wire \debounce_autofire|LessThan0~0_combout ; +wire \debounce_autofire|LessThan0~1_combout ; +wire \debounce_autofire|always0~0_combout ; +wire \debounce_autofire|always0~1_combout ; +wire \debounce_autofire|always0~2_combout ; +wire \debounce_autofire|r_State~4_combout ; +wire \debounce_autofire|r_State~5_combout ; +wire \debounce_autofire|r_State~2_combout ; +wire \debounce_autofire|r_State~0_combout ; +wire \debounce_autofire|r_State~1_combout ; +wire \debounce_autofire|r_State~3_combout ; +wire \debounce_autofire|r_State~6_combout ; +wire \debounce_autofire|r_State~q ; +wire \kempston_autofire_enabled~0_combout ; +wire \kempston_autofire_enabled~q ; +wire \kempston_auto_fire_counter[0]~51_combout ; +wire \kempston_auto_fire_counter[1]~17_combout ; +wire \kempston_auto_fire_counter[1]~18 ; +wire \kempston_auto_fire_counter[2]~19_combout ; +wire \kempston_auto_fire_counter[2]~20 ; +wire \kempston_auto_fire_counter[3]~21_combout ; +wire \kempston_auto_fire_counter[3]~22 ; +wire \kempston_auto_fire_counter[4]~23_combout ; +wire \kempston_auto_fire_counter[4]~24 ; +wire \kempston_auto_fire_counter[5]~25_combout ; +wire \kempston_auto_fire_counter[5]~26 ; +wire \kempston_auto_fire_counter[6]~27_combout ; +wire \kempston_auto_fire_counter[6]~28 ; +wire \kempston_auto_fire_counter[7]~29_combout ; +wire \kempston_auto_fire_counter[7]~30 ; +wire \kempston_auto_fire_counter[8]~31_combout ; +wire \kempston_auto_fire_counter[8]~32 ; +wire \kempston_auto_fire_counter[9]~33_combout ; +wire \kempston_auto_fire_counter[9]~34 ; +wire \kempston_auto_fire_counter[10]~35_combout ; +wire \kempston_auto_fire_counter[10]~36 ; +wire \kempston_auto_fire_counter[11]~37_combout ; +wire \kempston_auto_fire_counter[11]~38 ; +wire \kempston_auto_fire_counter[12]~39_combout ; +wire \kempston_auto_fire_counter[12]~40 ; +wire \kempston_auto_fire_counter[13]~41_combout ; +wire \kempston_auto_fire_counter[13]~42 ; +wire \kempston_auto_fire_counter[14]~43_combout ; +wire \kempston_auto_fire_counter[14]~44 ; +wire \kempston_auto_fire_counter[15]~45_combout ; +wire \Equal2~3_combout ; +wire \Equal2~2_combout ; +wire \Equal2~0_combout ; +wire \Equal2~1_combout ; +wire \Equal2~4_combout ; +wire \kempston_auto_fire_counter[15]~46 ; +wire \kempston_auto_fire_counter[16]~47_combout ; +wire \kempston_auto_fire_counter[16]~48 ; +wire \kempston_auto_fire_counter[17]~49_combout ; +wire \kempston_auto_fire~0_combout ; +wire \kempston_auto_fire~q ; +wire \Selector6~2_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|key_row[4]~17_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~133_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \Selector6~3_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \Selector6~4_combout ; +wire \Selector6~5_combout ; +wire \kempston[4]~input_o ; +wire \Selector6~6_combout ; +wire \Selector6~7_combout ; +wire \D[4]~39_combout ; +wire \z80_|bus_control_|db[4]~17_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|reg_file_|db_lo_ds[1]~3_combout ; +wire \z80_|alu_control_|db[1]~20_combout ; +wire \z80_|alu_control_|db[1]~21_combout ; +wire \z80_|alu_control_|db[1]~22_combout ; +wire \z80_|bus_control_|db[1]~9_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~2_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~1_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~38_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~3_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|key_row[1]~0_combout ; +wire \kempston[2]~input_o ; +wire \Selector12~4_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \Selector12~7_combout ; +wire \Selector12~8_combout ; +wire \Selector12~9_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector12~15_combout ; +wire \Selector12~5_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \Selector12~14_combout ; +wire \Selector12~6_combout ; +wire \Selector12~11_combout ; +wire \D[1]~12_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; wire \z80_|interrupts_|iff1~0_combout ; wire \z80_|interrupts_|iff1~1_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; wire \z80_|interrupts_|iff1~q ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|test1~4_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|fMRead~37_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~36_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; -wire \ula_|zx_keyboard_|WideOr16~1_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~74_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \D[3]~73_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~2_combout ; +wire \z80_|bus_control_|db[0]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector8~5_combout ; +wire \Selector8~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \Selector8~7_combout ; +wire \Selector8~8_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~134_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|key_row[3]~15_combout ; wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; wire \ula_|zx_keyboard_|keys[0][3]~q ; wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \D[3]~72_combout ; -wire \D[3]~76_combout ; -wire \D[3]~122_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~79_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~77_combout ; -wire \D[3]~80_combout ; -wire \D[3]~81_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~124_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~123_combout ; -wire \D[3]~78_combout ; -wire \D[3]~82_combout ; -wire \D[3]~108_combout ; -wire \D[3]~109_combout ; +wire \ula_|zx_keyboard_|key_row[3]~12_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~13_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~131_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|key_row[3]~14_combout ; +wire \kempston[0]~input_o ; +wire \Selector8~4_combout ; +wire \Selector8~9_combout ; +wire \D[3]~38_combout ; +wire \z80_|bus_control_|db[3]~19_combout ; wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; -wire \D[5]~97_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~116_combout ; -wire \D[7]~117_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|ir_|opcode[3]~feeder_combout ; +wire \z80_|execute_|ctl_alu_op_low~11_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~60_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~17_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|interrupts_|im1~feeder_combout ; wire \z80_|interrupts_|im1~q ; wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|execute_|ctl_bus_db_oe~2_combout ; -wire \z80_|execute_|ctl_bus_db_oe~5_combout ; -wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; -wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~57_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \D[0]~56_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~69_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~71_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \D[0]~54_combout ; -wire \D[0]~55_combout ; -wire \D[0]~58_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \D[0]~62_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~63_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~59_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~60_combout ; -wire \D[0]~61_combout ; -wire \D[0]~120_combout ; -wire \D[0]~64_combout ; -wire \D[0]~65_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|alu_|db[7]~9_combout ; -wire \z80_|alu_|db[1]~15_combout ; -wire \z80_|alu_|db[1]~16_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|sw1_|db_down[1]~2_combout ; -wire \z80_|alu_control_|db[1]~27_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|WideOr16~0_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~34_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \D[1]~38_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \D[1]~39_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \D[1]~35_combout ; -wire \D[1]~36_combout ; -wire \D[1]~37_combout ; -wire \D[1]~118_combout ; -wire \D[1]~40_combout ; -wire \D[1]~41_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~88_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \D[4]~87_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~85_combout ; -wire \D[4]~86_combout ; -wire \D[4]~89_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \D[4]~93_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \D[4]~94_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \D[4]~90_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \D[4]~91_combout ; -wire \D[4]~92_combout ; -wire \D[4]~125_combout ; -wire \D[4]~110_combout ; -wire \D[4]~111_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \z80_|alu_control_|db[5]~16_combout ; -wire \z80_|alu_control_|db[5]~17_combout ; +wire \z80_|bus_control_|db[0]~5_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; -wire \D[5]~112_combout ; -wire \D[5]~113_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[5]~25_combout ; +wire \D[5]~27_combout ; +wire \D[5]~40_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|ena_M~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; +wire \z80_|bus_control_|db[5]~16_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~51_combout ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~47_combout ; wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~55_combout ; wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~66_combout ; -wire \D[0]~67_combout ; -wire \D[0]~121_combout ; -wire \D[1]~68_combout ; -wire \D[1]~69_combout ; -wire \D[2]~70_combout ; -wire \D[2]~71_combout ; -wire \D[3]~83_combout ; -wire \D[3]~84_combout ; -wire \D[4]~95_combout ; -wire \D[4]~96_combout ; -wire \D[5]~126_combout ; -wire \D[5]~98_combout ; -wire \D[6]~105_combout ; -wire \D[6]~106_combout ; -wire \D[7]~128_combout ; -wire \D[7]~107_combout ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ; +wire \Selector14~15_combout ; +wire \Selector14~16_combout ; +wire \D[0]~15_combout ; +wire \D[0]~16_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ; +wire \Selector12~12_combout ; +wire \Selector12~13_combout ; +wire \D[1]~17_combout ; +wire \D[1]~18_combout ; +wire \D[2]~19_combout ; +wire \D[2]~20_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \Selector8~2_combout ; +wire \Selector8~3_combout ; +wire \D[3]~21_combout ; +wire \D[3]~22_combout ; +wire \D[4]~23_combout ; +wire \D[4]~24_combout ; +wire \D[6]~32_combout ; +wire \D[6]~33_combout ; +wire \D[6]~29_combout ; +wire \D[6]~30_combout ; +wire \D[6]~31_combout ; +wire \D[6]~50_combout ; +wire \D[6]~34_combout ; +wire \D[6]~35_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2541,54 +2751,55 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|Mux42~0_combout ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit~4_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; +wire \I2C_SDAT~input_o ; +wire \ula_|i2c_loader_|nbyte[0]~1_combout ; +wire \ula_|i2c_loader_|nbyte[0]~2_combout ; +wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state~24_combout ; wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; wire \ula_|i2c_loader_|state.Data~0_combout ; wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~6_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|state.Ack~0_combout ; wire \ula_|i2c_loader_|state.Ack~1_combout ; wire \ula_|i2c_loader_|state.Ack~q ; -wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; -wire \I2C_SDAT~input_o ; -wire \ula_|i2c_loader_|nbyte[0]~1_combout ; -wire \ula_|i2c_loader_|nbyte[0]~2_combout ; -wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; -wire \ula_|i2c_loader_|nbyte[1]~5_combout ; +wire \ula_|i2c_loader_|nbyte[0]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; wire \ula_|i2c_loader_|thisbyte[1]~10_combout ; @@ -2596,9 +2807,9 @@ wire \ula_|i2c_loader_|thisbyte[1]~11 ; wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; -wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; +wire \ula_|i2c_loader_|Equal2~0_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|state.Pause~4_combout ; @@ -2611,31 +2822,30 @@ wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~27_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~28_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg~6_combout ; wire \ula_|i2c_loader_|shiftreg~22_combout ; wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~27_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; -wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; +wire \ula_|i2c_loader_|shiftreg~25_combout ; +wire \ula_|i2c_loader_|Mux35~0_combout ; +wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; +wire \ula_|i2c_loader_|shiftreg[7]~7_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; wire \ula_|i2c_loader_|sda_out~2_combout ; @@ -2644,16 +2854,38 @@ wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \sdram_|Mux38~0_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux38~3_combout ; +wire \sdram_|Mux38~2_combout ; wire \sdram_|r.rd_pending~q ; +wire \sdram_|n~3_combout ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux13~8_combout ; wire \sdram_|r.rf_counter[0]~12_combout ; -wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[8]~32_combout ; wire \sdram_|r.rf_counter[0]~13 ; wire \sdram_|r.rf_counter[1]~14_combout ; wire \sdram_|r.rf_counter[1]~15 ; wire \sdram_|r.rf_counter[2]~16_combout ; wire \sdram_|r.rf_counter[2]~17 ; wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[3]~19 ; wire \sdram_|r.rf_counter[4]~20_combout ; wire \sdram_|r.rf_counter[4]~21 ; @@ -2662,105 +2894,84 @@ wire \sdram_|r.rf_counter[5]~23 ; wire \sdram_|r.rf_counter[6]~24_combout ; wire \sdram_|r.rf_counter[6]~25 ; wire \sdram_|r.rf_counter[7]~26_combout ; -wire \sdram_|Equal0~1_combout ; wire \sdram_|r.rf_counter[7]~27 ; wire \sdram_|r.rf_counter[8]~28_combout ; -wire \sdram_|Equal0~0_combout ; wire \sdram_|r.rf_counter[8]~29 ; wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~1_combout ; wire \sdram_|Equal0~2_combout ; -wire \sdram_|Mux13~8_combout ; wire \sdram_|Mux37~0_combout ; wire \sdram_|r.rf_pending~q ; -wire \sdram_|Mux4~0_combout ; wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~4_combout ; wire \sdram_|Mux4~2_combout ; -wire \sdram_|Mux4~3_combout ; -wire \sdram_|r.act_row[1]~0_combout ; -wire \sdram_|process_0~2_combout ; -wire \sdram_|r.act_row[1]~1_combout ; -wire \sdram_|r.act_row[2]~feeder_combout ; -wire \sdram_|Equal7~1_combout ; +wire \sdram_|Mux4~5_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|r.act_row[2]~0_combout ; +wire \sdram_|r.act_row[2]~1_combout ; wire \sdram_|Equal7~0_combout ; wire \sdram_|Equal7~2_combout ; -wire \sdram_|Mux39~0_combout ; -wire \sdram_|Mux39~1_combout ; -wire \sdram_|Mux39~2_combout ; -wire \sdram_|r.wr_pending~q ; -wire \sdram_|Mux9~8_combout ; -wire \sdram_|Mux9~9_combout ; -wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux6~3_combout ; wire \sdram_|Mux6~2_combout ; wire \sdram_|Mux6~5_combout ; -wire \sdram_|process_0~3_combout ; +wire \sdram_|process_0~2_combout ; wire \sdram_|Mux6~0_combout ; wire \sdram_|Mux6~1_combout ; wire \sdram_|Mux6~6_combout ; -wire \sdram_|r.address[3]~6_combout ; -wire \sdram_|Mux7~2_combout ; -wire \sdram_|n~3_combout ; -wire \sdram_|Mux7~3_combout ; -wire \sdram_|Mux7~4_combout ; -wire \sdram_|Mux7~5_combout ; -wire \sdram_|Mux23~0_combout ; -wire \sdram_|Mux13~7_combout ; -wire \sdram_|Mux10~10_combout ; -wire \sdram_|Mux7~1_combout ; -wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~2_combout ; wire \sdram_|Mux5~10_combout ; wire \sdram_|Mux5~3_combout ; wire \sdram_|Mux5~4_combout ; -wire \sdram_|Mux5~7_combout ; -wire \sdram_|Mux5~8_combout ; wire \sdram_|Mux5~5_combout ; wire \sdram_|Mux5~6_combout ; wire \sdram_|Mux5~9_combout ; wire \sdram_|n~2_combout ; -wire \sdram_|Mux8~3_combout ; -wire \sdram_|Mux8~4_combout ; -wire \sdram_|Mux9~10_combout ; -wire \sdram_|r.init_counter[0]~0_combout ; -wire \sdram_|Add1~1_cout ; -wire \sdram_|Add1~2_combout ; -wire \sdram_|Add1~3 ; -wire \sdram_|Add1~4_combout ; -wire \sdram_|Add1~5 ; -wire \sdram_|Add1~6_combout ; -wire \sdram_|r.init_counter[3]~1_combout ; -wire \sdram_|Add1~7 ; -wire \sdram_|Add1~8_combout ; -wire \sdram_|Add1~9 ; -wire \sdram_|Add1~10_combout ; -wire \sdram_|Add1~11 ; -wire \sdram_|Add1~12_combout ; -wire \sdram_|Add1~13 ; -wire \sdram_|Add1~14_combout ; -wire \sdram_|Add1~15 ; -wire \sdram_|Add1~16_combout ; -wire \sdram_|Add1~17 ; -wire \sdram_|Add1~18_combout ; -wire \sdram_|Add1~19 ; -wire \sdram_|Add1~20_combout ; -wire \sdram_|Equal2~0_combout ; -wire \sdram_|Equal2~1_combout ; -wire \sdram_|Add1~21 ; -wire \sdram_|Add1~22_combout ; -wire \sdram_|Add1~23 ; -wire \sdram_|Add1~24_combout ; -wire \sdram_|Add1~25 ; -wire \sdram_|Add1~26_combout ; -wire \sdram_|Add1~27 ; -wire \sdram_|Add1~28_combout ; -wire \sdram_|process_0~5_combout ; -wire \sdram_|Equal2~2_combout ; -wire \sdram_|Mux9~11_combout ; -wire \sdram_|Mux9~12_combout ; -wire \sdram_|Mux9~13_combout ; -wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~6_combout ; +wire \sdram_|Mux8~7_combout ; wire \sdram_|Mux8~1_combout ; wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|r.init_counter[0]~44_combout ; +wire \sdram_|r.init_counter[1]~15_cout ; +wire \sdram_|r.init_counter[1]~16_combout ; +wire \sdram_|r.init_counter[1]~17 ; +wire \sdram_|r.init_counter[2]~18_combout ; +wire \sdram_|r.init_counter[2]~19 ; +wire \sdram_|r.init_counter[3]~20_combout ; +wire \sdram_|r.init_counter[3]~21 ; +wire \sdram_|r.init_counter[4]~22_combout ; +wire \sdram_|r.init_counter[4]~23 ; +wire \sdram_|r.init_counter[5]~24_combout ; +wire \sdram_|r.init_counter[5]~25 ; +wire \sdram_|r.init_counter[6]~26_combout ; +wire \sdram_|r.init_counter[6]~27 ; +wire \sdram_|r.init_counter[7]~28_combout ; +wire \sdram_|r.init_counter[7]~29 ; +wire \sdram_|r.init_counter[8]~30_combout ; +wire \sdram_|r.init_counter[8]~31 ; +wire \sdram_|r.init_counter[9]~32_combout ; +wire \sdram_|r.init_counter[9]~33 ; +wire \sdram_|r.init_counter[10]~34_combout ; +wire \sdram_|r.init_counter[10]~35 ; +wire \sdram_|r.init_counter[11]~36_combout ; +wire \sdram_|r.init_counter[11]~37 ; +wire \sdram_|r.init_counter[12]~38_combout ; +wire \sdram_|r.init_counter[12]~39 ; +wire \sdram_|r.init_counter[13]~40_combout ; +wire \sdram_|r.init_counter[13]~41 ; +wire \sdram_|r.init_counter[14]~42_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux8~5_combout ; wire \sdram_|Mux72~0_combout ; wire \sdram_|Mux72~1_combout ; wire \sdram_|Mux84~0_combout ; @@ -2774,13 +2985,14 @@ wire \sdram_|Mux1~1_combout ; wire \sdram_|Mux0~0_combout ; wire \sdram_|Mux0~1_combout ; wire \sdram_|Mux73~0_combout ; -wire \sdram_|Mux73~1_combout ; wire \sdram_|Mux74~0_combout ; wire \sdram_|Mux74~1_combout ; wire \sdram_|Mux75~0_combout ; +wire \LED~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; +wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|Add0~1_cout ; wire \ula_|i2s_intf_|Add0~2_combout ; wire \ula_|i2s_intf_|lrdivider~2_combout ; @@ -2811,25 +3023,10 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; -wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; -wire \ula_|i2s_intf_|bitcount[4]~15_combout ; -wire \ula_|i2s_intf_|bitcount[0]~6 ; -wire \ula_|i2s_intf_|bitcount[1]~7_combout ; -wire \ula_|i2s_intf_|bitcount[1]~8 ; -wire \ula_|i2s_intf_|bitcount[2]~9_combout ; -wire \ula_|i2s_intf_|bitcount[2]~10 ; -wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|bitcount[3]~12 ; -wire \ula_|i2s_intf_|bitcount[4]~13_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2843,19 +3040,33 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|bitcount[4]~9_combout ; +wire \ula_|i2s_intf_|bitcount[0]~6 ; +wire \ula_|i2s_intf_|bitcount[1]~7_combout ; +wire \ula_|i2s_intf_|bitcount[1]~8 ; +wire \ula_|i2s_intf_|bitcount[2]~10_combout ; +wire \ula_|i2s_intf_|bitcount[2]~11 ; +wire \ula_|i2s_intf_|bitcount[3]~12_combout ; +wire \ula_|i2s_intf_|bitcount[3]~13 ; +wire \ula_|i2s_intf_|bitcount[4]~14_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|LessThan0~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; -wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; -wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|pcm_outr~0_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~18_combout ; wire \AUD_ADCDAT~input_o ; -wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; -wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; +wire \ula_|i2s_intf_|shiftreg[7]~1_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; wire \ula_|i2s_intf_|shiftreg~14_combout ; @@ -2866,25 +3077,19 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; -wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; -wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; -wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; +wire \ula_|i2s_intf_|shiftreg~2_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|border[1]~feeder_combout ; -wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|Decoder0~1_combout ; wire \ula_|video_|Decoder0~0_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2893,58 +3098,51 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[6]~feeder_combout ; -wire \ula_|video_|Decoder0~2_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[4]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[5]~feeder_combout ; -wire \ula_|video_|bits[5]~feeder_combout ; -wire \ula_|video_|bits_prefetch[7]~feeder_combout ; -wire \ula_|video_|Mux0~0_combout ; -wire \ula_|video_|Mux0~1_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[2]~feeder_combout ; -wire \ula_|video_|bits[2]~feeder_combout ; +wire \ula_|video_|Decoder0~2_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; -wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[2]~0_combout ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; +wire \ula_|video_|bits_prefetch[5]~feeder_combout ; +wire \ula_|video_|Mux0~0_combout ; +wire \ula_|video_|Mux0~1_combout ; +wire \ula_|video_|cindex[1]~0_combout ; wire \ula_|video_|cindex[1]~1_combout ; -wire \ula_|video_|LessThan2~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan6~0_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|disp_enable~1_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; +wire \ula_|video_|screen_en~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; -wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|border[2]~feeder_combout ; -wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|video_|attr[2]~feeder_combout ; +wire \ula_|video_|attr_prefetch[5]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; -wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; +wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; wire \ula_|video_|VGA_B[1]~2_combout ; -wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|VGA_HS~_Duplicate_1_q ; +wire \ula_|video_|Equal0~2_combout ; wire \ula_|video_|Selector0~0_combout ; wire \ula_|video_|VGA_HS~q ; wire \ula_|video_|VGA_VS~_Duplicate_1_q ; @@ -2958,290 +3156,305 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire \sdram_|Mux26~4_combout ; -wire \sdram_|r.bank[0]~7_combout ; -wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~6_combout ; wire \sdram_|r.bank[0]~4_combout ; wire \sdram_|r.bank[0]~5_combout ; -wire \sdram_|r.bank[0]~6_combout ; -wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~8_combout ; wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|r.bank[0]~13_combout ; +wire \sdram_|r.bank[0]~11_combout ; wire \sdram_|Mux25~4_combout ; -wire \sdram_|Mux24~5_combout ; -wire \sdram_|Mux71~0_combout ; -wire \sdram_|process_0~7_combout ; -wire \sdram_|process_0~4_combout ; -wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~6_combout ; wire \sdram_|Mux71~2_combout ; wire \sdram_|Mux71~3_combout ; +wire \sdram_|process_0~8_combout ; +wire \sdram_|process_0~3_combout ; wire \sdram_|Mux71~4_combout ; -wire \sdram_|r.bank[0]~10_combout ; -wire \sdram_|Mux9~3_combout ; -wire \sdram_|n~5_combout ; -wire \sdram_|Mux9~4_combout ; -wire \sdram_|Mux9~2_combout ; -wire \sdram_|Equal2~3_combout ; -wire \sdram_|Mux10~2_combout ; -wire \sdram_|Mux10~3_combout ; -wire \sdram_|process_0~6_combout ; -wire \sdram_|Mux10~4_combout ; -wire \sdram_|Mux9~5_combout ; -wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux24~8_combout ; +wire \sdram_|Mux71~5_combout ; +wire \sdram_|n~6_combout ; +wire \sdram_|Mux9~0_combout ; wire \sdram_|Mux9~6_combout ; wire \sdram_|Mux9~7_combout ; -wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Equal5~1_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux9~1_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Mux9~3_combout ; wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|Mux10~4_combout ; wire \sdram_|Mux10~5_combout ; wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~12_combout ; wire \sdram_|Mux10~8_combout ; -wire \sdram_|Mux10~9_combout ; wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~8_combout ; wire \sdram_|Mux11~2_combout ; wire \sdram_|Mux11~3_combout ; -wire \sdram_|Mux11~4_combout ; wire \sdram_|Mux11~5_combout ; wire \sdram_|Mux11~6_combout ; wire \sdram_|Mux11~7_combout ; -wire \sdram_|Mux11~9_combout ; -wire \sdram_|Mux11~8_combout ; -wire \sdram_|Mux24~2_combout ; -wire \sdram_|r.address[0]~7_combout ; -wire \sdram_|r.address[0]~0_combout ; -wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux24~6_combout ; wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~9_combout ; wire \sdram_|Mux13~5_combout ; wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~2_combout ; wire \sdram_|Mux24~3_combout ; wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~0_combout ; wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~8_combout ; +wire \sdram_|r.address[1]~9_combout ; +wire \sdram_|r.address[1]~7_combout ; +wire \sdram_|r.address[1]~10_combout ; +wire \sdram_|r.address[1]~1_combout ; wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; -wire \sdram_|Mux23~4_combout ; -wire \sdram_|Equal5~0_combout ; -wire \sdram_|Mux23~5_combout ; -wire \sdram_|Mux23~6_combout ; wire \sdram_|Mux19~0_combout ; wire \sdram_|r.address[1]~_Duplicate_1_q ; -wire \sdram_|Mux23~2_combout ; wire \sdram_|Mux23~3_combout ; -wire \sdram_|Mux23~1_combout ; -wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~5_combout ; wire \sdram_|r.address[1]~SLOAD_MUX_combout ; -wire \sdram_|r.address[3]~8_combout ; -wire \sdram_|r.address[3]~9_combout ; -wire \sdram_|Mux21~0_combout ; -wire \sdram_|Mux22~0_combout ; -wire \sdram_|r.address[3]~10_combout ; wire \sdram_|r.address[3]~11_combout ; wire \sdram_|r.address[3]~12_combout ; -wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; wire \sdram_|r.address[3]~14_combout ; wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~13_combout ; wire \sdram_|r.address[3]~16_combout ; wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|r.address[3]~18_combout ; +wire \sdram_|r.address[3]~19_combout ; +wire \sdram_|r.address[3]~20_combout ; wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux24~7_combout ; wire \sdram_|Mux20~4_combout ; -wire \sdram_|Mux20~7_combout ; -wire \sdram_|Mux23~7_combout ; -wire \sdram_|Mux20~8_combout ; -wire \sdram_|Mux20~10_combout ; -wire \sdram_|Mux20~9_combout ; -wire \sdram_|Mux20~11_combout ; -wire \sdram_|r.address[4]~_Duplicate_1_q ; -wire \sdram_|Mux20~12_combout ; -wire \sdram_|Mux20~5_combout ; -wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~2_combout ; +wire \sdram_|Mux20~3_combout ; wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~_Duplicate_1feeder_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~9_combout ; wire \sdram_|r.address[4]~SLOAD_MUX_combout ; -wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~4_combout ; -wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~5_combout ; wire \sdram_|Mux19~7_combout ; wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~1_combout ; wire \sdram_|Mux19~2_combout ; wire \sdram_|Mux19~3_combout ; wire \sdram_|r.address[5]~3_combout ; wire \sdram_|r.address[5]~SLOAD_MUX_combout ; wire \sdram_|Mux18~0_combout ; -wire \sdram_|Mux17~0_combout ; -wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux17~2_combout ; +wire \sdram_|Mux16~2_combout ; wire \sdram_|Mux15~2_combout ; -wire \sdram_|Mux14~0_combout ; -wire \sdram_|Mux14~1_combout ; -wire \sdram_|r.address[10]~4_combout ; -wire \sdram_|r.address[10]~_Duplicate_1_q ; -wire \sdram_|n~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1feeder_combout ; +wire \sdram_|n~5_combout ; wire \sdram_|Mux14~2_combout ; wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|r.address[10]~4_combout ; wire \sdram_|r.address[10]~SLOAD_MUX_combout ; -wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~21_combout ; +wire \sdram_|r.address[11]~22_combout ; wire \sdram_|r.address[11]~5_combout ; -wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; wire \sdram_|r.address[11]~_Duplicate_2_q ; wire \sdram_|Mux13~10_combout ; wire \sdram_|Mux13~6_combout ; wire \sdram_|r.address[11]~SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; wire \sdram_|r.address[11]~_Duplicate_1_q ; -wire [9:0] \sdram_|r.rf_counter ; -wire [12:0] \sdram_|r.address ; -wire [15:0] \ula_|pcm_outl ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [8:0] \sdram_|r.state ; +wire [1:0] \sdram_|r.bank ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; +wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; +wire [1:0] \z80_|sw1_|SYNTHESIZED_WIRE_1 ; +wire [7:0] \z80_|data_pins_|dout ; +wire [3:0] \z80_|alu_|op1_low ; +wire [20:0] \debounce_autofire|r_Count ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [9:0] \sdram_|r.rf_counter ; +wire [1:0] \sdram_|r.dq_masks ; +wire [12:0] \sdram_|r.address ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [15:0] \ula_|pcm_outl ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; +wire [17:0] kempston_auto_fire_counter; +wire [20:0] \debounce_turbo|r_Count ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; -wire [3:0] \z80_|alu_|op2_low ; +wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|dout ; -wire [8:0] \sdram_|r.state ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [2:0] \z80_|sw1_|SYNTHESIZED_WIRE_2 ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [4:0] \ula_|zx_keyboard_|key_row ; +wire [3:0] \z80_|alu_|result_lo ; +wire [3:0] \z80_|alu_|op2_high ; +wire [3:0] \z80_|alu_|op1_high ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; wire [14:0] \sdram_|r.init_counter ; -wire [1:0] \sdram_|r.bank ; wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [3:0] \z80_|alu_|result_lo ; -wire [3:0] \z80_|alu_|op2_high ; -wire [3:0] \z80_|alu_|op1_high ; -wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; -wire [7:0] \z80_|ir_|opcode ; -wire [1:0] \sdram_|r.dq_masks ; -wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [3:0] \z80_|alu_|op1_low ; wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|ir_|opcode ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -3255,96 +3468,104 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; @@ -3355,14 +3576,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3375,11 +3588,19 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3391,14 +3612,6 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; - // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3609,8 +3822,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~67_combout ), - .oe(\D[0]~121_combout ), + .i(\D[0]~16_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3622,8 +3835,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~69_combout ), - .oe(\D[0]~121_combout ), + .i(\D[1]~18_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3635,8 +3848,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~71_combout ), - .oe(\D[0]~121_combout ), + .i(\D[2]~20_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3648,8 +3861,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~84_combout ), - .oe(\D[0]~121_combout ), + .i(\D[3]~22_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3661,8 +3874,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~96_combout ), - .oe(\D[0]~121_combout ), + .i(\D[4]~24_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3674,8 +3887,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~98_combout ), - .oe(\D[0]~121_combout ), + .i(\D[5]~27_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3687,8 +3900,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~106_combout ), - .oe(\D[0]~121_combout ), + .i(\D[6]~35_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3700,8 +3913,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~107_combout ), - .oe(\D[0]~121_combout ), + .i(\D[7]~37_combout ), + .oe(\D[0]~49_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3739,7 +3952,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3778,7 +3991,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(gnd), + .i(\raw_loader_in~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3791,7 +4004,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\SW[2]~input_o ), + .i(\turbo~q ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3804,7 +4017,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\raw_loader_in~input_o ), + .i(!\kempston[0]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3817,7 +4030,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(gnd), + .i(!\kempston[1]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3830,7 +4043,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(gnd), + .i(!\kempston[2]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3843,7 +4056,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(gnd), + .i(!\kempston[3]~input_o ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3856,7 +4069,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\LED~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4166,32 +4379,6 @@ defparam \GPIO_1[31]~output .bus_hold = "false"; defparam \GPIO_1[31]~output .open_drain_output = "false"; // synopsys translate_on -// Location: IOOBUF_X53_Y16_N9 -cycloneive_io_obuf \GPIO_1[32]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[32]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[32]~output .bus_hold = "false"; -defparam \GPIO_1[32]~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOOBUF_X53_Y15_N9 -cycloneive_io_obuf \GPIO_1[33]~output ( - .i(gnd), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(GPIO_1[33]), - .obar()); -// synopsys translate_off -defparam \GPIO_1[33]~output .bus_hold = "false"; -defparam \GPIO_1[33]~output .open_drain_output = "false"; -// synopsys translate_on - // Location: IOOBUF_X16_Y34_N2 cycloneive_io_obuf \buzzer_out~output ( .i(\ula_|beep~q ), @@ -4504,6 +4691,19 @@ defparam \DRAM_ADDR[12]~output .bus_hold = "false"; defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X3_Y34_N2 +cycloneive_io_obuf \kempston_gnd~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(kempston_gnd), + .obar()); +// synopsys translate_off +defparam \kempston_gnd~output .bus_hold = "false"; +defparam \kempston_gnd~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -4597,7 +4797,7 @@ defparam \DRAM_DQ[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y15_N2 cycloneive_io_obuf \DRAM_DQ[5]~output ( - .i(\sdram_|Mux73~1_combout ), + .i(\sdram_|Mux73~0_combout ), .oe(\sdram_|Mux84~1_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -4869,7 +5069,1083 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: IOIBUF_X53_Y16_N8 +cycloneive_io_ibuf \turbo_button~input ( + .i(turbo_button), + .ibar(gnd), + .o(\turbo_button~input_o )); +// synopsys translate_off +defparam \turbo_button~input .bus_hold = "false"; +defparam \turbo_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[0]~21 ( +// Equation(s): +// \debounce_turbo|r_Count[0]~21_combout = \debounce_turbo|r_Count [0] $ (VCC) +// \debounce_turbo|r_Count[0]~22 = CARRY(\debounce_turbo|r_Count [0]) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_turbo|r_Count[0]~21_combout ), + .cout(\debounce_turbo|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_turbo|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[1]~23 ( +// Equation(s): +// \debounce_turbo|r_Count[1]~23_combout = (\debounce_turbo|r_Count [1] & (!\debounce_turbo|r_Count[0]~22 )) # (!\debounce_turbo|r_Count [1] & ((\debounce_turbo|r_Count[0]~22 ) # (GND))) +// \debounce_turbo|r_Count[1]~24 = CARRY((!\debounce_turbo|r_Count[0]~22 ) # (!\debounce_turbo|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[0]~22 ), + .combout(\debounce_turbo|r_Count[1]~23_combout ), + .cout(\debounce_turbo|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N15 +dffeas \debounce_turbo|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[2]~25 ( +// Equation(s): +// \debounce_turbo|r_Count[2]~25_combout = (\debounce_turbo|r_Count [2] & (\debounce_turbo|r_Count[1]~24 $ (GND))) # (!\debounce_turbo|r_Count [2] & (!\debounce_turbo|r_Count[1]~24 & VCC)) +// \debounce_turbo|r_Count[2]~26 = CARRY((\debounce_turbo|r_Count [2] & !\debounce_turbo|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[1]~24 ), + .combout(\debounce_turbo|r_Count[2]~25_combout ), + .cout(\debounce_turbo|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N17 +dffeas \debounce_turbo|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[3]~27 ( +// Equation(s): +// \debounce_turbo|r_Count[3]~27_combout = (\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count[2]~26 )) # (!\debounce_turbo|r_Count [3] & ((\debounce_turbo|r_Count[2]~26 ) # (GND))) +// \debounce_turbo|r_Count[3]~28 = CARRY((!\debounce_turbo|r_Count[2]~26 ) # (!\debounce_turbo|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[2]~26 ), + .combout(\debounce_turbo|r_Count[3]~27_combout ), + .cout(\debounce_turbo|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N19 +dffeas \debounce_turbo|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[4]~29 ( +// Equation(s): +// \debounce_turbo|r_Count[4]~29_combout = (\debounce_turbo|r_Count [4] & (\debounce_turbo|r_Count[3]~28 $ (GND))) # (!\debounce_turbo|r_Count [4] & (!\debounce_turbo|r_Count[3]~28 & VCC)) +// \debounce_turbo|r_Count[4]~30 = CARRY((\debounce_turbo|r_Count [4] & !\debounce_turbo|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[3]~28 ), + .combout(\debounce_turbo|r_Count[4]~29_combout ), + .cout(\debounce_turbo|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N21 +dffeas \debounce_turbo|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N22 +cycloneive_lcell_comb \debounce_turbo|r_Count[5]~31 ( +// Equation(s): +// \debounce_turbo|r_Count[5]~31_combout = (\debounce_turbo|r_Count [5] & (!\debounce_turbo|r_Count[4]~30 )) # (!\debounce_turbo|r_Count [5] & ((\debounce_turbo|r_Count[4]~30 ) # (GND))) +// \debounce_turbo|r_Count[5]~32 = CARRY((!\debounce_turbo|r_Count[4]~30 ) # (!\debounce_turbo|r_Count [5])) + + .dataa(\debounce_turbo|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[4]~30 ), + .combout(\debounce_turbo|r_Count[5]~31_combout ), + .cout(\debounce_turbo|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N23 +dffeas \debounce_turbo|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N24 +cycloneive_lcell_comb \debounce_turbo|r_Count[6]~33 ( +// Equation(s): +// \debounce_turbo|r_Count[6]~33_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count[5]~32 $ (GND))) # (!\debounce_turbo|r_Count [6] & (!\debounce_turbo|r_Count[5]~32 & VCC)) +// \debounce_turbo|r_Count[6]~34 = CARRY((\debounce_turbo|r_Count [6] & !\debounce_turbo|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[5]~32 ), + .combout(\debounce_turbo|r_Count[6]~33_combout ), + .cout(\debounce_turbo|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N25 +dffeas \debounce_turbo|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N26 +cycloneive_lcell_comb \debounce_turbo|r_Count[7]~35 ( +// Equation(s): +// \debounce_turbo|r_Count[7]~35_combout = (\debounce_turbo|r_Count [7] & (!\debounce_turbo|r_Count[6]~34 )) # (!\debounce_turbo|r_Count [7] & ((\debounce_turbo|r_Count[6]~34 ) # (GND))) +// \debounce_turbo|r_Count[7]~36 = CARRY((!\debounce_turbo|r_Count[6]~34 ) # (!\debounce_turbo|r_Count [7])) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[6]~34 ), + .combout(\debounce_turbo|r_Count[7]~35_combout ), + .cout(\debounce_turbo|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N27 +dffeas \debounce_turbo|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N28 +cycloneive_lcell_comb \debounce_turbo|r_Count[8]~37 ( +// Equation(s): +// \debounce_turbo|r_Count[8]~37_combout = (\debounce_turbo|r_Count [8] & (\debounce_turbo|r_Count[7]~36 $ (GND))) # (!\debounce_turbo|r_Count [8] & (!\debounce_turbo|r_Count[7]~36 & VCC)) +// \debounce_turbo|r_Count[8]~38 = CARRY((\debounce_turbo|r_Count [8] & !\debounce_turbo|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[7]~36 ), + .combout(\debounce_turbo|r_Count[8]~37_combout ), + .cout(\debounce_turbo|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N29 +dffeas \debounce_turbo|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N30 +cycloneive_lcell_comb \debounce_turbo|r_Count[9]~39 ( +// Equation(s): +// \debounce_turbo|r_Count[9]~39_combout = (\debounce_turbo|r_Count [9] & (!\debounce_turbo|r_Count[8]~38 )) # (!\debounce_turbo|r_Count [9] & ((\debounce_turbo|r_Count[8]~38 ) # (GND))) +// \debounce_turbo|r_Count[9]~40 = CARRY((!\debounce_turbo|r_Count[8]~38 ) # (!\debounce_turbo|r_Count [9])) + + .dataa(\debounce_turbo|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[8]~38 ), + .combout(\debounce_turbo|r_Count[9]~39_combout ), + .cout(\debounce_turbo|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y29_N31 +dffeas \debounce_turbo|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N0 +cycloneive_lcell_comb \debounce_turbo|r_Count[10]~41 ( +// Equation(s): +// \debounce_turbo|r_Count[10]~41_combout = (\debounce_turbo|r_Count [10] & (\debounce_turbo|r_Count[9]~40 $ (GND))) # (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count[9]~40 & VCC)) +// \debounce_turbo|r_Count[10]~42 = CARRY((\debounce_turbo|r_Count [10] & !\debounce_turbo|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[9]~40 ), + .combout(\debounce_turbo|r_Count[10]~41_combout ), + .cout(\debounce_turbo|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N1 +dffeas \debounce_turbo|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N2 +cycloneive_lcell_comb \debounce_turbo|r_Count[11]~43 ( +// Equation(s): +// \debounce_turbo|r_Count[11]~43_combout = (\debounce_turbo|r_Count [11] & (!\debounce_turbo|r_Count[10]~42 )) # (!\debounce_turbo|r_Count [11] & ((\debounce_turbo|r_Count[10]~42 ) # (GND))) +// \debounce_turbo|r_Count[11]~44 = CARRY((!\debounce_turbo|r_Count[10]~42 ) # (!\debounce_turbo|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[10]~42 ), + .combout(\debounce_turbo|r_Count[11]~43_combout ), + .cout(\debounce_turbo|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N3 +dffeas \debounce_turbo|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N4 +cycloneive_lcell_comb \debounce_turbo|r_Count[12]~45 ( +// Equation(s): +// \debounce_turbo|r_Count[12]~45_combout = (\debounce_turbo|r_Count [12] & (\debounce_turbo|r_Count[11]~44 $ (GND))) # (!\debounce_turbo|r_Count [12] & (!\debounce_turbo|r_Count[11]~44 & VCC)) +// \debounce_turbo|r_Count[12]~46 = CARRY((\debounce_turbo|r_Count [12] & !\debounce_turbo|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[11]~44 ), + .combout(\debounce_turbo|r_Count[12]~45_combout ), + .cout(\debounce_turbo|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N5 +dffeas \debounce_turbo|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N6 +cycloneive_lcell_comb \debounce_turbo|r_Count[13]~47 ( +// Equation(s): +// \debounce_turbo|r_Count[13]~47_combout = (\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count[12]~46 )) # (!\debounce_turbo|r_Count [13] & ((\debounce_turbo|r_Count[12]~46 ) # (GND))) +// \debounce_turbo|r_Count[13]~48 = CARRY((!\debounce_turbo|r_Count[12]~46 ) # (!\debounce_turbo|r_Count [13])) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[12]~46 ), + .combout(\debounce_turbo|r_Count[13]~47_combout ), + .cout(\debounce_turbo|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N7 +dffeas \debounce_turbo|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y29_N12 +cycloneive_lcell_comb \debounce_turbo|r_State~7 ( +// Equation(s): +// \debounce_turbo|r_State~7_combout = (\debounce_turbo|r_Count [6] & (\debounce_turbo|r_Count [7] & \debounce_turbo|r_Count [5])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [6]), + .datac(\debounce_turbo|r_Count [7]), + .datad(\debounce_turbo|r_Count [5]), + .cin(gnd), + .combout(\debounce_turbo|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~7 .lut_mask = 16'hC000; +defparam \debounce_turbo|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N2 +cycloneive_lcell_comb \debounce_turbo|LessThan0~0 ( +// Equation(s): +// \debounce_turbo|LessThan0~0_combout = (!\debounce_turbo|r_State~7_combout & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_State~7_combout ), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N30 +cycloneive_lcell_comb \debounce_turbo|LessThan0~1 ( +// Equation(s): +// \debounce_turbo|LessThan0~1_combout = (!\debounce_turbo|r_Count [13] & (!\debounce_turbo|r_Count [12] & ((\debounce_turbo|LessThan0~0_combout ) # (!\debounce_turbo|r_Count [11])))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [12]), + .datac(\debounce_turbo|LessThan0~0_combout ), + .datad(\debounce_turbo|r_Count [11]), + .cin(gnd), + .combout(\debounce_turbo|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|LessThan0~1 .lut_mask = 16'h1011; +defparam \debounce_turbo|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N8 +cycloneive_lcell_comb \debounce_turbo|r_Count[14]~49 ( +// Equation(s): +// \debounce_turbo|r_Count[14]~49_combout = (\debounce_turbo|r_Count [14] & (\debounce_turbo|r_Count[13]~48 $ (GND))) # (!\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count[13]~48 & VCC)) +// \debounce_turbo|r_Count[14]~50 = CARRY((\debounce_turbo|r_Count [14] & !\debounce_turbo|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[13]~48 ), + .combout(\debounce_turbo|r_Count[14]~49_combout ), + .cout(\debounce_turbo|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N9 +dffeas \debounce_turbo|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N10 +cycloneive_lcell_comb \debounce_turbo|r_Count[15]~51 ( +// Equation(s): +// \debounce_turbo|r_Count[15]~51_combout = (\debounce_turbo|r_Count [15] & (!\debounce_turbo|r_Count[14]~50 )) # (!\debounce_turbo|r_Count [15] & ((\debounce_turbo|r_Count[14]~50 ) # (GND))) +// \debounce_turbo|r_Count[15]~52 = CARRY((!\debounce_turbo|r_Count[14]~50 ) # (!\debounce_turbo|r_Count [15])) + + .dataa(\debounce_turbo|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[14]~50 ), + .combout(\debounce_turbo|r_Count[15]~51_combout ), + .cout(\debounce_turbo|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_turbo|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N11 +dffeas \debounce_turbo|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N12 +cycloneive_lcell_comb \debounce_turbo|r_Count[16]~53 ( +// Equation(s): +// \debounce_turbo|r_Count[16]~53_combout = (\debounce_turbo|r_Count [16] & (\debounce_turbo|r_Count[15]~52 $ (GND))) # (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count[15]~52 & VCC)) +// \debounce_turbo|r_Count[16]~54 = CARRY((\debounce_turbo|r_Count [16] & !\debounce_turbo|r_Count[15]~52 )) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[15]~52 ), + .combout(\debounce_turbo|r_Count[16]~53_combout ), + .cout(\debounce_turbo|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_turbo|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N13 +dffeas \debounce_turbo|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N14 +cycloneive_lcell_comb \debounce_turbo|r_Count[17]~55 ( +// Equation(s): +// \debounce_turbo|r_Count[17]~55_combout = (\debounce_turbo|r_Count [17] & (!\debounce_turbo|r_Count[16]~54 )) # (!\debounce_turbo|r_Count [17] & ((\debounce_turbo|r_Count[16]~54 ) # (GND))) +// \debounce_turbo|r_Count[17]~56 = CARRY((!\debounce_turbo|r_Count[16]~54 ) # (!\debounce_turbo|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[16]~54 ), + .combout(\debounce_turbo|r_Count[17]~55_combout ), + .cout(\debounce_turbo|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N15 +dffeas \debounce_turbo|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N16 +cycloneive_lcell_comb \debounce_turbo|r_Count[18]~57 ( +// Equation(s): +// \debounce_turbo|r_Count[18]~57_combout = (\debounce_turbo|r_Count [18] & (\debounce_turbo|r_Count[17]~56 $ (GND))) # (!\debounce_turbo|r_Count [18] & (!\debounce_turbo|r_Count[17]~56 & VCC)) +// \debounce_turbo|r_Count[18]~58 = CARRY((\debounce_turbo|r_Count [18] & !\debounce_turbo|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[17]~56 ), + .combout(\debounce_turbo|r_Count[18]~57_combout ), + .cout(\debounce_turbo|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_turbo|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N17 +dffeas \debounce_turbo|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N18 +cycloneive_lcell_comb \debounce_turbo|r_Count[19]~59 ( +// Equation(s): +// \debounce_turbo|r_Count[19]~59_combout = (\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count[18]~58 )) # (!\debounce_turbo|r_Count [19] & ((\debounce_turbo|r_Count[18]~58 ) # (GND))) +// \debounce_turbo|r_Count[19]~60 = CARRY((!\debounce_turbo|r_Count[18]~58 ) # (!\debounce_turbo|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_turbo|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_turbo|r_Count[18]~58 ), + .combout(\debounce_turbo|r_Count[19]~59_combout ), + .cout(\debounce_turbo|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_turbo|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N19 +dffeas \debounce_turbo|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N22 +cycloneive_lcell_comb \debounce_turbo|always0~0 ( +// Equation(s): +// \debounce_turbo|always0~0_combout = (!\debounce_turbo|r_Count [16] & (!\debounce_turbo|r_Count [19] & (!\debounce_turbo|r_Count [17] & !\debounce_turbo|r_Count [18]))) + + .dataa(\debounce_turbo|r_Count [16]), + .datab(\debounce_turbo|r_Count [19]), + .datac(\debounce_turbo|r_Count [17]), + .datad(\debounce_turbo|r_Count [18]), + .cin(gnd), + .combout(\debounce_turbo|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~0 .lut_mask = 16'h0001; +defparam \debounce_turbo|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N24 +cycloneive_lcell_comb \debounce_turbo|always0~1 ( +// Equation(s): +// \debounce_turbo|always0~1_combout = (\debounce_turbo|always0~0_combout & ((\debounce_turbo|LessThan0~1_combout ) # ((!\debounce_turbo|r_Count [15]) # (!\debounce_turbo|r_Count [14])))) + + .dataa(\debounce_turbo|LessThan0~1_combout ), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|always0~0_combout ), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_turbo|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N20 +cycloneive_lcell_comb \debounce_turbo|r_Count[20]~61 ( +// Equation(s): +// \debounce_turbo|r_Count[20]~61_combout = \debounce_turbo|r_Count[19]~60 $ (!\debounce_turbo|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_turbo|r_Count [20]), + .cin(\debounce_turbo|r_Count[19]~60 ), + .combout(\debounce_turbo|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_turbo|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y28_N21 +dffeas \debounce_turbo|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N0 +cycloneive_lcell_comb \debounce_turbo|always0~2 ( +// Equation(s): +// \debounce_turbo|always0~2_combout = (\debounce_turbo|always0~1_combout & (\debounce_turbo|r_State~q $ ((!\turbo_button~input_o )))) # (!\debounce_turbo|always0~1_combout & ((\debounce_turbo|r_Count [20]) # (\debounce_turbo|r_State~q $ +// (!\turbo_button~input_o )))) + + .dataa(\debounce_turbo|always0~1_combout ), + .datab(\debounce_turbo|r_State~q ), + .datac(\turbo_button~input_o ), + .datad(\debounce_turbo|r_Count [20]), + .cin(gnd), + .combout(\debounce_turbo|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|always0~2 .lut_mask = 16'hD7C3; +defparam \debounce_turbo|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y29_N13 +dffeas \debounce_turbo|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_turbo|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_turbo|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_turbo|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N10 +cycloneive_lcell_comb \debounce_turbo|r_State~4 ( +// Equation(s): +// \debounce_turbo|r_State~4_combout = (!\debounce_turbo|r_Count [0] & (!\debounce_turbo|r_Count [3] & (!\debounce_turbo|r_Count [1] & !\debounce_turbo|r_Count [2]))) + + .dataa(\debounce_turbo|r_Count [0]), + .datab(\debounce_turbo|r_Count [3]), + .datac(\debounce_turbo|r_Count [1]), + .datad(\debounce_turbo|r_Count [2]), + .cin(gnd), + .combout(\debounce_turbo|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_turbo|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N6 +cycloneive_lcell_comb \debounce_turbo|r_State~2 ( +// Equation(s): +// \debounce_turbo|r_State~2_combout = (\debounce_turbo|r_Count [20] & (!\debounce_turbo|r_Count [10] & (!\debounce_turbo|r_Count [9] & !\debounce_turbo|r_Count [8]))) + + .dataa(\debounce_turbo|r_Count [20]), + .datab(\debounce_turbo|r_Count [10]), + .datac(\debounce_turbo|r_Count [9]), + .datad(\debounce_turbo|r_Count [8]), + .cin(gnd), + .combout(\debounce_turbo|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_turbo|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y28_N28 +cycloneive_lcell_comb \debounce_turbo|r_State~0 ( +// Equation(s): +// \debounce_turbo|r_State~0_combout = (!\debounce_turbo|r_Count [13] & (\debounce_turbo|r_Count [14] & (!\debounce_turbo|r_Count [12] & \debounce_turbo|r_Count [15]))) + + .dataa(\debounce_turbo|r_Count [13]), + .datab(\debounce_turbo|r_Count [14]), + .datac(\debounce_turbo|r_Count [12]), + .datad(\debounce_turbo|r_Count [15]), + .cin(gnd), + .combout(\debounce_turbo|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_turbo|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~1 ( +// Equation(s): +// \debounce_turbo|r_State~1_combout = (\debounce_turbo|r_Count [7] & (\debounce_turbo|r_Count [11] & (\debounce_turbo|r_Count [5] & \debounce_turbo|r_Count [6]))) + + .dataa(\debounce_turbo|r_Count [7]), + .datab(\debounce_turbo|r_Count [11]), + .datac(\debounce_turbo|r_Count [5]), + .datad(\debounce_turbo|r_Count [6]), + .cin(gnd), + .combout(\debounce_turbo|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N0 +cycloneive_lcell_comb \debounce_turbo|r_State~3 ( +// Equation(s): +// \debounce_turbo|r_State~3_combout = (\debounce_turbo|r_State~2_combout & (\debounce_turbo|r_State~0_combout & (\debounce_turbo|r_State~1_combout & \debounce_turbo|always0~0_combout ))) + + .dataa(\debounce_turbo|r_State~2_combout ), + .datab(\debounce_turbo|r_State~0_combout ), + .datac(\debounce_turbo|r_State~1_combout ), + .datad(\debounce_turbo|always0~0_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_turbo|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y29_N8 +cycloneive_lcell_comb \debounce_turbo|r_State~5 ( +// Equation(s): +// \debounce_turbo|r_State~5_combout = (\debounce_turbo|r_State~4_combout & (!\debounce_turbo|r_Count [4] & \debounce_turbo|r_State~3_combout )) + + .dataa(\debounce_turbo|r_State~4_combout ), + .datab(\debounce_turbo|r_Count [4]), + .datac(gnd), + .datad(\debounce_turbo|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~5 .lut_mask = 16'h2200; +defparam \debounce_turbo|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N4 +cycloneive_lcell_comb \debounce_turbo|r_State~6 ( +// Equation(s): +// \debounce_turbo|r_State~6_combout = (\debounce_turbo|r_State~5_combout & (\turbo_button~input_o )) # (!\debounce_turbo|r_State~5_combout & ((\debounce_turbo|r_State~q ))) + + .dataa(\turbo_button~input_o ), + .datab(gnd), + .datac(\debounce_turbo|r_State~q ), + .datad(\debounce_turbo|r_State~5_combout ), + .cin(gnd), + .combout(\debounce_turbo|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_turbo|r_State~6 .lut_mask = 16'hAAF0; +defparam \debounce_turbo|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N5 +dffeas \debounce_turbo|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_turbo|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_turbo|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_turbo|r_State .is_wysiwyg = "true"; +defparam \debounce_turbo|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y27_N14 +cycloneive_lcell_comb \turbo~0 ( +// Equation(s): +// \turbo~0_combout = !\turbo~q + + .dataa(gnd), + .datab(gnd), + .datac(\turbo~q ), + .datad(gnd), + .cin(gnd), + .combout(\turbo~0_combout ), + .cout()); +// synopsys translate_off +defparam \turbo~0 .lut_mask = 16'h0F0F; +defparam \turbo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y27_N15 +dffeas turbo( + .clk(!\debounce_turbo|r_State~q ), + .d(\turbo~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\turbo~q ), + .prn(vcc)); +// synopsys translate_off +defparam turbo.is_wysiwyg = "true"; +defparam turbo.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y29_N4 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4886,7 +6162,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y29_N5 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4905,34 +6181,24 @@ defparam \ula_|clocks_|counter[0] .is_wysiwyg = "true"; defparam \ula_|clocks_|counter[0] .power_up = "low"; // synopsys translate_on -// Location: IOIBUF_X25_Y34_N8 -cycloneive_io_ibuf \SW[2]~input ( - .i(SW[2]), - .ibar(gnd), - .o(\SW[2]~input_o )); -// synopsys translate_off -defparam \SW[2]~input .bus_hold = "false"; -defparam \SW[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): -// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) +// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\turbo~q ) # (!\ula_|clocks_|counter [0]))) .dataa(gnd), - .datab(\ula_|clocks_|counter [0]), + .datab(\turbo~q ), .datac(\ula_|clocks_|clk_cpu~q ), - .datad(\SW[2]~input_o ), + .datad(\ula_|clocks_|counter [0]), .cin(gnd), .combout(\ula_|clocks_|clk_cpu~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; +defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h3C0F; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4951,7 +6217,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4964,33 +6230,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: IOIBUF_X0_Y16_N8 -cycloneive_io_ibuf \KEY[1]~input ( - .i(KEY[1]), - .ibar(gnd), - .o(\KEY[1]~input_o )); -// synopsys translate_off -defparam \KEY[1]~input .bus_hold = "false"; -defparam \KEY[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( -// Equation(s): -// \z80_|interrupts_|nmi_armed~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; -defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -5001,7 +6240,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N12 +// Location: LCCOMB_X52_Y14_N4 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -5018,7 +6257,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N18 +// Location: LCCOMB_X27_Y15_N4 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -5035,7 +6274,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y32_N8 +// Location: LCCOMB_X27_Y1_N28 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -5052,7 +6291,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X26_Y32_N9 +// Location: FF_X27_Y1_N29 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -5071,7 +6310,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G10 +// Location: CLKCTRL_G16 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -5084,7 +6323,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X52_Y14_N19 +// Location: FF_X27_Y15_N5 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -5103,79 +6342,68 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y14_N0 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); +// Location: IOIBUF_X0_Y16_N8 +cycloneive_io_ibuf \KEY[1]~input ( + .i(KEY[1]), + .ibar(gnd), + .o(\KEY[1]~input_o )); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \KEY[1]~input .bus_hold = "false"; +defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: FF_X31_Y14_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Location: LCCOMB_X23_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|nmi_armed~feeder_combout = VCC .dataa(gnd), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(gnd), + .datad(gnd), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .combout(\z80_|interrupts_|nmi_armed~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; +defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y10_N1 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: CLKCTRL_G7 +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~55_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), @@ -5188,21 +6416,40 @@ defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( // Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout ) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .combout(\z80_|sequencer_|ena_M~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N19 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -5218,7 +6465,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N8 +// Location: LCCOMB_X26_Y31_N0 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) @@ -5236,24 +6483,24 @@ defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N14 +// Location: LCCOMB_X30_Y31_N10 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): // \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~0_combout ), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Add0~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hC0C0; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y29_N15 +// Location: FF_X30_Y31_N11 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -5272,7 +6519,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N10 +// Location: LCCOMB_X26_Y31_N2 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -5290,7 +6537,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N22 +// Location: LCCOMB_X29_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -5307,7 +6554,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y30_N23 +// Location: FF_X29_Y31_N13 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -5326,7 +6573,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N12 +// Location: LCCOMB_X26_Y31_N4 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -5344,7 +6591,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N31 +// Location: FF_X29_Y31_N15 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5363,33 +6610,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N14 +// Location: LCCOMB_X26_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(\ula_|video_|vga_hc [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [3]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X30_Y30_N11 +// Location: FF_X26_Y31_N7 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~6_combout ), + .d(\ula_|video_|Add0~6_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -5400,7 +6647,24 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N16 +// Location: LCCOMB_X30_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N8 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -5418,7 +6682,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N7 +// Location: FF_X26_Y31_N25 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5437,169 +6701,42 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Location: LCCOMB_X30_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( // Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) +// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & !\ula_|video_|vga_hc [4]))) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [5]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Add0~10_combout ), - .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [4]), .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), + .combout(\ula_|video_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N20 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y30_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N22 +// Location: LCCOMB_X26_Y31_N14 cycloneive_lcell_comb \ula_|video_|Add0~14 ( // Equation(s): // \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) // \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - .dataa(\ula_|video_|vga_hc [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~13 ), .combout(\ula_|video_|Add0~14_combout ), .cout(\ula_|video_|Add0~15 )); // synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X29_Y30_N3 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N26 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N24 +// Location: LCCOMB_X26_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add0~16 ( // Equation(s): // \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) @@ -5617,15 +6754,15 @@ defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N28 +// Location: LCCOMB_X26_Y31_N22 cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( // Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~16_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~16_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~2_combout ), .cout()); @@ -5634,7 +6771,7 @@ defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N17 +// Location: FF_X26_Y31_N15 dffeas \ula_|video_|vga_hc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5653,32 +6790,32 @@ defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N26 +// Location: LCCOMB_X26_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add0~18 ( // Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) .dataa(gnd), - .datab(\ula_|video_|vga_hc [9]), + .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|vga_hc [9]), .cin(\ula_|video_|Add0~17 ), .combout(\ula_|video_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N2 +// Location: LCCOMB_X26_Y31_N20 cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( // Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) .dataa(gnd), - .datab(\ula_|video_|Add0~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(gnd), - .datad(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~18_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~1_combout ), .cout()); @@ -5687,7 +6824,7 @@ defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y30_N5 +// Location: FF_X26_Y31_N31 dffeas \ula_|video_|vga_hc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -5706,24 +6843,134 @@ defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y29_N0 +// Location: LCCOMB_X30_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal1~0 ( // Equation(s): // \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hFF7F; defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N0 +// Location: LCCOMB_X26_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Add0~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y31_N23 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N21 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N29 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N6 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) @@ -5741,312 +6988,77 @@ defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Location: LCCOMB_X31_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( // Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [0] & !\ula_|video_|vga_vc [1]))) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N30 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Add1~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N31 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [3]), .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), + .combout(\ula_|video_|Equal3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N21 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N26 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N27 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N23 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N10 +// Location: LCCOMB_X31_Y31_N16 cycloneive_lcell_comb \ula_|video_|Add1~10 ( // Equation(s): // \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) // \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~9 ), .combout(\ula_|video_|Add1~10_combout ), .cout(\ula_|video_|Add1~11 )); // synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N8 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y30_N9 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[5]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y29_N12 +// Location: LCCOMB_X31_Y31_N18 cycloneive_lcell_comb \ula_|video_|Add1~12 ( // Equation(s): // \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) // \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~11 ), .combout(\ula_|video_|Add1~12_combout ), .cout(\ula_|video_|Add1~13 )); // synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N16 +// Location: LCCOMB_X27_Y31_N28 cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( // Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Add1~12_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[6]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N17 +// Location: FF_X27_Y31_N29 dffeas \ula_|video_|vga_vc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[6]~4_combout ), @@ -6065,7 +7077,7 @@ defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N14 +// Location: LCCOMB_X31_Y31_N20 cycloneive_lcell_comb \ula_|video_|Add1~14 ( // Equation(s): // \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) @@ -6083,7 +7095,7 @@ defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N22 +// Location: LCCOMB_X27_Y31_N8 cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( // Equation(s): // \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) @@ -6100,7 +7112,7 @@ defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N23 +// Location: FF_X27_Y31_N9 dffeas \ula_|video_|vga_vc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[7]~6_combout ), @@ -6119,25 +7131,25 @@ defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N16 +// Location: LCCOMB_X31_Y31_N22 cycloneive_lcell_comb \ula_|video_|Add1~16 ( // Equation(s): // \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) // \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~15 ), .combout(\ula_|video_|Add1~16_combout ), .cout(\ula_|video_|Add1~17 )); // synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N20 +// Location: LCCOMB_X27_Y31_N6 cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( // Equation(s): // \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) @@ -6154,7 +7166,7 @@ defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N21 +// Location: FF_X27_Y31_N7 dffeas \ula_|video_|vga_vc[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[8]~7_combout ), @@ -6173,41 +7185,41 @@ defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y29_N18 +// Location: LCCOMB_X31_Y31_N24 cycloneive_lcell_comb \ula_|video_|Add1~18 ( // Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) +// \ula_|video_|Add1~18_combout = \ula_|video_|vga_vc [9] $ (\ula_|video_|Add1~17 ) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [9]), .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), + .datad(gnd), .cin(\ula_|video_|Add1~17 ), .combout(\ula_|video_|Add1~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .lut_mask = 16'h5A5A; defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N8 +// Location: LCCOMB_X27_Y31_N4 cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( // Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~18_combout ), .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Add1~18_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[9]~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y30_N9 +// Location: FF_X27_Y31_N5 dffeas \ula_|video_|vga_vc[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[9]~9_combout ), @@ -6226,32 +7238,15 @@ defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N10 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N30 +// Location: LCCOMB_X27_Y31_N24 cycloneive_lcell_comb \ula_|video_|Equal2~0 ( // Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [6]))) .dataa(\ula_|video_|vga_vc [8]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [6]), .cin(gnd), .combout(\ula_|video_|Equal2~0_combout ), .cout()); @@ -6260,13 +7255,13 @@ defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N16 +// Location: LCCOMB_X31_Y31_N4 cycloneive_lcell_comb \ula_|video_|Equal3~1 ( // Equation(s): -// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) +// \ula_|video_|Equal3~1_combout = (\ula_|video_|Equal3~0_combout & (\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|Equal3~0_combout ), + .dataa(\ula_|video_|Equal3~0_combout ), + .datab(\ula_|video_|vga_vc [9]), .datac(\ula_|video_|vga_vc [5]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), @@ -6277,24 +7272,24 @@ defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N24 +// Location: LCCOMB_X27_Y31_N12 cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( // Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~0_combout ), .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y30_N25 +// Location: FF_X27_Y31_N13 dffeas \ula_|video_|vga_vc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[0]~0_combout ), @@ -6313,15 +7308,267 @@ defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N18 +// Location: LCCOMB_X31_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N18 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N19 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h0A0C; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[2]~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N2 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [3]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~6_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~6_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N3 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y31_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N0 cycloneive_lcell_comb \ula_|video_|Equal2~1 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [3]))) .dataa(\ula_|video_|vga_vc [0]), .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [3]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), .cout()); @@ -6330,20 +7577,20 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N12 +// Location: LCCOMB_X31_Y31_N26 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(\ula_|video_|Equal2~1_combout ), - .datab(gnd), - .datac(\ula_|video_|vga_vc [5]), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~1_combout ), + .datac(gnd), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -6357,14 +7604,14 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X31_Y27_N2 +// Location: LCCOMB_X28_Y31_N26 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & !\SW[1]~input_o ))) - .dataa(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), .datab(\ula_|video_|vga_vc [1]), - .datac(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), @@ -6374,75 +7621,77 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|ir_|opcode[4]~feeder ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) +// \z80_|ir_|opcode[4]~feeder_combout = \z80_|bus_control_|db[4]~18_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal0~0_combout ), + .combout(\z80_|ir_|opcode[4]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; -defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; +defparam \z80_|ir_|opcode[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N8 +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N13 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N9 +// Location: FF_X36_Y11_N21 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -6461,340 +7710,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N27 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - - .dataa(\z80_|clk_delay_|DFF_inst5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N17 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N24 -cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & -// \z80_|pla_decode_|Equal3~2_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~2_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & -// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N25 -dffeas \z80_|decode_state_|DFFE_inst4 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_inst4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 +// Location: LCCOMB_X36_Y11_N30 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N1 +// Location: FF_X36_Y11_N31 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -6813,2615 +7746,32 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( -// Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|fMRead~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N2 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( -// Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( -// Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|fIOWrite~3_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( -// Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIOWrite~2_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|fMWrite~3_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & -// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~45_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N11 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(gnd), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( -// Equation(s): -// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~97_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~96_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~98_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~98_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), - .datab(\z80_|execute_|ctl_inc_cy~96_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( -// Equation(s): -// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N18 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(gnd), - .datad(\z80_|execute_|fMWrite~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|fMWrite~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [7]), - .datac(gnd), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N24 +// Location: LCCOMB_X37_Y14_N10 cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( // Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) +// \z80_|execute_|ctl_ir_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|ctl_ir_we~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h5050; defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # -// (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; -defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & -// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|fMWrite~6_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # -// (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMWrite~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; -defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N8 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & -// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; -defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_iorw~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|nextM~4_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y11_N21 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X38_Y11_N17 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N15 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X40_Y11_N23 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & -// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~12_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~15_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~16_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y14_N13 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mwr~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N21 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|mwr_wr~q ), - .datac(\z80_|execute_|fIOWrite~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N17 +// Location: FF_X30_Y12_N5 dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~53_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|execute_|setM1~55_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -9432,24 +7782,24 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N8 +// Location: LCCOMB_X30_Y12_N8 cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): // \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h0F0F; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N9 +// Location: FF_X30_Y12_N9 dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), @@ -9468,7 +7818,7 @@ defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N7 +// Location: FF_X30_Y12_N19 dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -9487,7 +7837,7 @@ defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N6 +// Location: LCCOMB_X30_Y12_N18 cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & @@ -9505,34385 +7855,358 @@ defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N10 +// Location: LCCOMB_X34_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h333B; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~0_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~0 .lut_mask = 16'h0505; +defparam \z80_|pla_decode_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [0] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0800; defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|fIOWrite~0_combout ), - .datad(\z80_|execute_|fIORead~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|execute_|fIORead~0_combout ), - .datac(\z80_|execute_|fIOWrite~1_combout ), - .datad(\z80_|execute_|fIORead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N23 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|im2~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|fMWrite~0_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~57 ( -// Equation(s): -// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; -defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_ir_we~6_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) - - .dataa(\z80_|execute_|fMRead~4_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~13_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal40~2_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; -defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~14_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|execute_|setM1~57_combout ), - .datab(\z80_|execute_|setM1~38_combout ), - .datac(\z80_|execute_|setM1~37_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|decode_state_|table_xx~0_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~1_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~19_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datab(\z80_|execute_|ctl_mRead~16_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|decode_state_|DFFE_instED~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_mRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~31_combout ), - .datab(\z80_|execute_|ctl_mRead~32_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mRead~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N19 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~33_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N29 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y11_N11 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_mrd~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) - - .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), - .datab(\z80_|execute_|fIORead~3_combout ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~1_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N12 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h3000; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G9 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & -// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N25 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N13 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [5]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [4]), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [3]), - .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N27 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N7 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X17_Y27_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|clk_filter [0]), - .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X17_Y27_N17 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X18_Y12_N19 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N29 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N13 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N23 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|bit_count [1]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) - - .dataa(\ula_|ps2_keyboard_|bit_count [2]), - .datab(\ula_|ps2_keyboard_|bit_count [1]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\PS2_DAT~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|bit_count [0]), - .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|always1~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y10_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N27 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N13 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X21_Y8_N21 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N31 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X20_Y8_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X19_Y10_N23 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|Equal0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X18_Y12_N24 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) - - .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X18_Y12_N25 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N27 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N25 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N4 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N5 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N1 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y12_N27 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) - - .dataa(\z80_|resets_|clrpc_int~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .datad(\z80_|execute_|fMRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & -// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ixy_d~16_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_mRead~7_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~99_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|ctl_inc_cy~50_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & -// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) - - .dataa(\z80_|execute_|setM1~37_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal12~0_combout ), - .datad(\z80_|execute_|ctl_mRead~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|pla_decode_|Equal33~2_combout ), - .datac(\z80_|execute_|pc_inc_hold~33_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout -// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout -// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|ir_|opcode [7]), - .datac(\z80_|pla_decode_|Equal46~0_combout ), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_bus~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal76~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal76~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_bus~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|decode_state_|table_xx~0_combout ), - .datab(\z80_|pla_decode_|Equal41~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_iorw~10_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal10~1_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datac(\z80_|execute_|ctl_mRead~20_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~1_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~46_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & -// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|fMRead~8_combout ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal52~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), - .datab(\z80_|execute_|ctl_sw_4d~2_combout ), - .datac(\z80_|execute_|ctl_sw_4d~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_sw_4d~0_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; -defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_inc_dec~3_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|execute_|ctl_al_we~5_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|pla_decode_|Equal1~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y14_N25 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal77~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # -// (!\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~56 ( -// Equation(s): -// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_sw_2u~4_combout ), - .datad(\z80_|execute_|setM1~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & -// ((\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(\z80_|execute_|ctl_state_alu~13_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & -// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) - - .dataa(\z80_|execute_|fMRead~10_combout ), - .datab(\z80_|execute_|fMRead~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~2_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~25_combout ), - .datac(\z80_|execute_|ctl_mRead~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [4]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datab(\z80_|execute_|setM1~48_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & -// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & -// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~8_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_sw_1d~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & -// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal4~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|decode_state_|DFFE_instCB~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [7]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; -defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N12 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # -// (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_mRead~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~3_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_flags_oe~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(gnd), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # -// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_sw_1d~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal2~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal12~1_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datac(\z80_|execute_|ctl_sw_4u~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .datad(\z80_|execute_|ctl_sw_4u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_2d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datad(\z80_|execute_|ctl_sw_2d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|fMRead~18_combout ), - .datad(\z80_|execute_|fMRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal19~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~22_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datac(\z80_|execute_|fMRead~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_2d~9_combout ), - .datac(\z80_|execute_|ctl_sw_1d~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; -defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal44~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~7_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & -// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; -defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_flags_alu~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_flags_alu~22_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal1~5_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; -defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), .datab(\z80_|sequencer_|DFFE_M3_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & -// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~1_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_alu~18_combout ), - .datac(\z80_|execute_|ctl_flags_alu~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~26_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datab(\z80_|execute_|ctl_flags_bus~13_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_flags_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datab(\z80_|alu_control_|db[1]~27_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|nextM~11_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Location: LCCOMB_X35_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( // Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout -// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_flags_alu~20_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ctl_mRead~24_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), .datac(\z80_|sequencer_|DFFE_M2_ff~q ), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) -// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout -// & (\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mWrite~17_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & -// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_oe~15_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( -// Equation(s): -// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; -defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|nextM~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ -// (!\z80_|execute_|comb~0_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datac(\z80_|execute_|ctl_sw_2u~6_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~3_combout ), - .datac(\z80_|execute_|setM1~30_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~15_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N27 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|bank_hl_de2~q ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; -defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|reg_control_|bank_hl_de1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|decode_state_|DFFE_instIY1~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_cy~50_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_sw_4u~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N24 -cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( -// Equation(s): -// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & -// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_|db_low[3]~26_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~8_combout ), - .datac(\z80_|execute_|ctl_sw_2d~10_combout ), - .datad(\z80_|execute_|ctl_sw_2d~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~12_combout ), - .datac(\z80_|execute_|ctl_sw_2d~11_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|execute_|ctl_mWrite~11_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datab(\z80_|execute_|ctl_alu_oe~9_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_alu_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~10_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & -// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) - - .dataa(\z80_|alu_control_|db[3]~36_combout ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_flags_alu~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # -// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) - - .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N19 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) - - .dataa(\z80_|execute_|setM1~50_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(\z80_|alu_flags_|flags_xf~q ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N0 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; -defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) - - .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) - - .dataa(\z80_|reg_control_|bank_exx~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_de~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; -defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # -// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~87_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_apin_mux~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~8_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~64_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~65_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) - - .dataa(\z80_|execute_|fMRead~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_cy~99_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~97_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~57_combout ), - .datad(\z80_|execute_|ctl_inc_cy~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout -// & (\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal33~2_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; -defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & -// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|pc_inc_hold~19_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) - - .dataa(\z80_|pla_decode_|Equal25~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; -defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|pc_inc_hold~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; -defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # -// ((\z80_|execute_|ctl_inc_cy~62_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~25_combout ), - .datab(\z80_|execute_|ctl_inc_cy~68_combout ), - .datac(\z80_|execute_|ctl_inc_cy~62_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|pla_decode_|Equal24~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; -defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; -defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|pc_inc_hold~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; -defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) - - .dataa(\z80_|execute_|pc_inc_hold~17_combout ), - .datab(\z80_|execute_|ctl_inc_cy~74_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~20_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_inc_cy~73_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~95_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~20_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|pc_inc_hold~15_combout ), - .datad(\z80_|execute_|ctl_inc_cy~95_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~18_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datad(\z80_|execute_|ctl_inc_cy~77_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~27_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_inc_cy~78_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~15_combout ), - .datac(\z80_|execute_|pc_inc_hold~25_combout ), - .datad(\z80_|execute_|pc_inc_hold~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|ctl_inc_cy~70_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|ctl_inc_cy~79_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # -// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), - .datab(\z80_|execute_|pc_inc_hold~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~34_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|pc_inc_hold~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; -defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|pc_inc_hold~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~54_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~56_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), - .datab(\z80_|execute_|ctl_inc_cy~51_combout ), - .datac(\z80_|execute_|ctl_inc_cy~49_combout ), - .datad(\z80_|execute_|ctl_inc_cy~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), - .datab(\z80_|execute_|ctl_inc_cy~88_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_inc_cy~90_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~83_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~96_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~100_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|ctl_inc_cy~84_combout ), - .datac(\z80_|execute_|ctl_inc_cy~100_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~24_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), - .datad(\z80_|execute_|ctl_inc_cy~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|pc_inc_hold~29_combout ), - .datad(\z80_|execute_|pc_inc_hold~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ctl_inc_cy~52_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|pc_inc_hold~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~32_combout ), - .datad(\z80_|execute_|pc_inc_hold~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|Q [0]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( -// Equation(s): -// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[0]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|fIOWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .datac(\z80_|execute_|ctl_inc_dec~8_combout ), - .datad(\z80_|execute_|ctl_inc_dec~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datab(\z80_|execute_|ctl_inc_dec~5_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [2]), - .datab(gnd), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( -// Equation(s): -// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[3]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( -// Equation(s): -// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db_low[2]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( -// Equation(s): -// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal20~0_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y8_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # -// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|pla_decode_|Equal62~2_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & -// \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), - .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; -defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|alu_|db[1]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~14_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~1_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & -// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) - - .dataa(\z80_|execute_|ctl_al_we~9_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), - .datab(\z80_|execute_|ctl_mRead~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_al_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(\z80_|execute_|ctl_al_we~10_combout ), - .datac(\z80_|execute_|ctl_al_we~8_combout ), - .datad(\z80_|execute_|ctl_sw_4d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~11_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N7 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( -// Equation(s): -// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; -defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & -// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N11 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( -// Equation(s): -// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; -defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( -// Equation(s): -// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; -defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( -// Equation(s): -// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[7]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; -defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(gnd), - .datab(\z80_|address_latch_|Q [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N3 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q -// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [9]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N1 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [10]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & -// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) - - .dataa(\z80_|address_latch_|Q [9]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [10]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( -// Equation(s): -// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N2 -cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( -// Equation(s): -// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[4]~8_combout ), - .datad(\z80_|alu_|db_high[0]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; -defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N13 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [12]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_oe~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( -// Equation(s): -// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( -// Equation(s): -// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[1]~16_combout ), - .datac(\z80_|alu_|db_low[1]~18_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [1]), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~16_combout ), - .datab(\z80_|alu_|db_low[1]~15_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( -// Equation(s): -// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # -// (!\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|alu_|db_low[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[1]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; -defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[1]~19_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N9 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout -// )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y6_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datab(\z80_|execute_|ctl_flags_alu~21_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # -// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N11 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_mRead~25_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; -defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [1])))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|alu_op2[1]~2_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & -// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # -// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # -// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|alu_|db_high[2]~13_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datad(\z80_|alu_|db_low[2]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N3 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_high [2]), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( -// Equation(s): -// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; -defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db_high[2]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|alu_|db_high[2]~10_combout ), - .datac(\z80_|alu_|db_high[2]~9_combout ), - .datad(\z80_|alu_|db_high[2]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_high[2]~12_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X24_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|alu_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [14]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N16 -cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( -// Equation(s): -// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N26 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db[5]~24_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_high[1]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( -// Equation(s): -// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; -defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [1]), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[1]~14_combout ), - .datad(\z80_|alu_|db_high[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|db_high[1]~18_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N4 -cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( -// Equation(s): -// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[5]~23_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(\z80_|reg_control_|reg_sel_af~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N21 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [13]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [13]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; -defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N4 -cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( -// Equation(s): -// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[7]~37_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N18 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[7]~19_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & -// ((\z80_|alu_|db[7]~20_combout ))))) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~8_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[3]~7_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N11 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|alu_|op1_high [3]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; -defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_high[2]~13_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[2]~14_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N31 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; -defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [2]))))) - - .dataa(\z80_|alu_|op1_low [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_|alu_op2[2]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|alu_op2[2]~1_combout ), - .datab(\z80_|alu_|op1_high [2]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_S~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # -// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|alu_op1[3]~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op2[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal0~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[1]~16_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[0]~18_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(gnd), - .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( -// Equation(s): -// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N23 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( -// Equation(s): -// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|db_low[0]~24_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; -defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( -// Equation(s): -// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & -// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[0]~22_combout ), - .datac(\z80_|alu_|db_low[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_low[0]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N17 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # -// (!\z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & -// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; -defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout -// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_state_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # -// (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & -// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[0]~1_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [0]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N16 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[3]~14_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) - - .dataa(\z80_|alu_|db[4]~10_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datac(gnd), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( -// Equation(s): -// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|bus_control_|db[3]~21_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; -defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~21_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[0]~23_combout ), - .datad(\z80_|alu_|db_high[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datac(\z80_|alu_|db_high[0]~24_combout ), - .datad(\z80_|alu_|db_high[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(\z80_|alu_|db_high[0]~25_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_high [0]), - .datad(\z80_|alu_|op1_low [0]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_S~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y9_N19 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( -// Equation(s): -// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(gnd), - .datab(\z80_|alu_|result_lo [2]), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; -defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( -// Equation(s): -// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; -defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( -// Equation(s): -// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|alu_|db_low[2]~12_combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; -defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( -// Equation(s): -// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|db_low[2]~10_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|alu_|db_low[2]~11_combout ), - .datad(\z80_|alu_|db_low[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; -defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( -// Equation(s): -// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N22 -cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( -// Equation(s): -// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~11_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_|db[2]~12_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~33_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N13 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [3]), - .datac(\z80_|alu_|op1_low [2]), - .datad(\z80_|alu_|op1_low [1]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( -// Equation(s): -// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|alu_flags_|flags_hf2~q ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; -defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datac(\z80_|execute_|rsel3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal39~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( -// Equation(s): -// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[2]~28_combout ), - .datab(\z80_|alu_control_|db[2]~24_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[2]~29_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; -defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datad(\z80_|alu_control_|db[2]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N27 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [2]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N21 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & -// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N29 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X30_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N31 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout +// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N15 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [8]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N20 -cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( -// Equation(s): -// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_control_|db[0]~14_combout ), - .datab(\z80_|alu_|db[0]~17_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_|db[7]~9_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( -// Equation(s): -// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~10_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( -// Equation(s): -// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[0]~11_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_flags_|flags_cf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y17_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), - .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [0]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout -// ))))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(\z80_|execute_|ctl_inc_cy~93_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y16_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N3 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[1]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~9_combout ), - .datac(\z80_|execute_|ctl_inc_dec~7_combout ), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & -// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~81_combout ), - .datac(\z80_|execute_|ctl_inc_cy~93_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q -// [2]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[3]~34_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|sw1_|db_down[3]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( -// Equation(s): -// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_|db[3]~14_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; -defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( -// Equation(s): -// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|alu_|db[3]~13_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|alu_control_|db[3]~36_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; -defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( -// Equation(s): -// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[2]~12_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N10 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( -// Equation(s): -// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db[3]~14_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datad(\z80_|alu_|db_low[3]~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; -defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y10_N25 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( -// Equation(s): -// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|alu_|op2_low [3]), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; -defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|alu_|db_low[3]~6_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) - - .dataa(\z80_|alu_|db_low[3]~5_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|result_lo [3]), - .datad(\z80_|alu_|db_low[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( -// Equation(s): -// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[3]~0_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; -defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_low[3]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N13 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .datab(\z80_|alu_|db_high[3]~7_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y9_N21 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) - - .dataa(\z80_|alu_|op2_low [3]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|alu_|op2_high [3]), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; -defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datad(\z80_|alu_|alu_op1[3]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & -// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[3]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .datad(\z80_|alu_|op2_high [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db[7]~20_combout ), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) - - .dataa(\z80_|bus_control_|db[3]~21_combout ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) - - .dataa(\z80_|alu_|db_high[3]~4_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|db_high[3]~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .datab(\z80_|alu_|db_high[3]~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[3]~6_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout -// ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal61~2_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datab(\z80_|pla_decode_|Equal73~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datad(\z80_|pla_decode_|Equal68~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_state_alu~3_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y7_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & -// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [2]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_66_oe~combout ), - .datad(\z80_|alu_control_|out[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_|db[7]~20_combout ), - .datad(\z80_|alu_|db[0]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout -// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_control_|out[6]~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal20~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y8_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|execute_|ctl_state_alu~12_combout ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|pla_decode_|Equal10~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( // Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal1~1_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~2_combout ))) - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), + .combout(\z80_|execute_|ctl_mRead~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y8_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Location: LCCOMB_X36_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_sw_1d~2_combout = (\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~2_combout & +// (((!\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) - .dataa(\z80_|pla_decode_|Equal64~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~18_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y6_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_state_alu~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y7_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; -defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y7_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y7_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N2 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y8_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y8_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y8_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datad(\z80_|alu_|db[4]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[4]~31_combout ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( -// Equation(s): -// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|alu_control_|db[4]~32_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; -defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y17_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y17_N29 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datab(\z80_|alu_control_|db[4]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y16_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # -// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N5 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [4]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|Q [5]), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|Q [7]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) - - .dataa(\z80_|address_latch_|Q [0]), - .datab(\z80_|address_latch_|Q [3]), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|Q [1]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [14]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|pla_decode_|Equal62~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|pla_decode_|Equal79~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X30_Y12_N19 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// (!\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datac(\z80_|pla_decode_|Equal62~3_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; -defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), - .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y9_N2 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .datad(\z80_|alu_|alu_parity_out~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datab(\z80_|execute_|ctl_flags_bus~combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~19_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y11_N25 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) - - .dataa(\z80_|alu_|db_low[2]~14_combout ), - .datab(\z80_|alu_|db_low[0]~27_combout ), - .datac(\z80_|alu_|db_low[3]~26_combout ), - .datad(\z80_|alu_|db_low[1]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|alu_|db_high[0]~25_combout ), - .datac(\z80_|alu_|db_high[2]~13_combout ), - .datad(\z80_|alu_|db_high[3]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .datab(\z80_|alu_control_|db[6]~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N25 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// !\z80_|alu_control_|sel[1]~0_combout )))) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|alu_control_|sel[1]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_control_|sel[1]~0_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y11_N9 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; -defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N13 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [11]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & -// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y4_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [11]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N6 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [10]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N7 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N26 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\z80_|address_pins_|abus[10]~20_combout ), - .datad(\ula_|zx_keyboard_|keys[3][2]~q ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hC4F5; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~2_combout ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N31 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; -defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; -defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & -// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|address_latch_|abusz [15]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) - - .dataa(\z80_|address_latch_|abusz [14]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N14 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; -defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; -defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N1 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N10 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & -// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hC4F5; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [13]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; -defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[5][2]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N23 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N18 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|key_row~1_combout ), - .datad(\ula_|zx_keyboard_|keys[4][2]~q ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'h80A0; -defparam \D[2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [0]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; -defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; -defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N13 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [9]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [8]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N20 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'hF531; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N24 -cycloneive_lcell_comb \D[2]~46 ( -// Equation(s): -// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) - - .dataa(\D[2]~43_combout ), - .datab(\D[2]~45_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~46_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hF8F0; -defparam \D[2]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N3 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|clk_delay_|DFF_inst5~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( -// Equation(s): -// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y14_N1 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( -// Equation(s): -// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|memory_ifc_|iorq~0_combout ), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; -defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N8 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h0020; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [13]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N18 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) - - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h4000; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [1]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N16 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|address_latch_|abusz [2]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [3]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [3]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|address_latch_|abusz [5]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N9 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [6]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N10 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N26 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|address_latch_|abusz [7]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y12_N27 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y12_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X24_Y19_N11 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N3 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ExtRamWE~0_combout ), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N0 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X25_Y19_N15 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X25_Y19_N19 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y8_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N10 -cycloneive_lcell_comb \D[2]~50 ( -// Equation(s): -// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .cin(gnd), - .combout(\D[2]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~50 .lut_mask = 16'hF838; -defparam \D[2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N26 -cycloneive_lcell_comb \D[2]~51 ( -// Equation(s): -// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~50_combout ), - .cin(gnd), - .combout(\D[2]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~51 .lut_mask = 16'hEE30; -defparam \D[2]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N24 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N30 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N8 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N25 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), - .cin(gnd), - .combout(\ula_|video_|vram_address[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N31 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N4 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N5 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N23 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N17 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N8 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N15 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N16 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N17 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N18 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y29_N19 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N28 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N2 -cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( -// Equation(s): -// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[8]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N29 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N22 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) - - .dataa(\ula_|video_|vga_vc [8]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N6 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|Add4~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N7 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N18 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|vram_address[10]~2_combout ), - .datab(\ula_|video_|Add4~4_combout ), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y29_N19 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N24 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [2]), - .datad(\ula_|video_|Add4~12_combout ), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N25 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y29_N2 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y29_N3 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[8]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N28 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N29 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N20 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y19_N21 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y18_N0 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ExtRamWE~0_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~53_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N22 -cycloneive_lcell_comb \D[2]~47 ( -// Equation(s): -// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~47 .lut_mask = 16'hE6A2; -defparam \D[2]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N24 -cycloneive_lcell_comb \D[2]~48 ( -// Equation(s): -// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[2]~47_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~48 .lut_mask = 16'h4B48; -defparam \D[2]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N16 -cycloneive_lcell_comb \D[2]~49 ( -// Equation(s): -// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[2]~47_combout ), - .datad(\D[2]~48_combout ), - .cin(gnd), - .combout(\D[2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~49 .lut_mask = 16'hC3E0; -defparam \D[2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N6 -cycloneive_lcell_comb \D[2]~119 ( -// Equation(s): -// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~51_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[2]~51_combout ), - .datad(\D[2]~49_combout ), - .cin(gnd), - .combout(\D[2]~119_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~119 .lut_mask = 16'hF4B0; -defparam \D[2]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N20 -cycloneive_lcell_comb \D[2]~52 ( -// Equation(s): -// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[2]~46_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~52 .lut_mask = 16'hBFB3; -defparam \D[2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N26 -cycloneive_lcell_comb \D[2]~53 ( -// Equation(s): -// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~52_combout ), - .cin(gnd), - .combout(\D[2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~53 .lut_mask = 16'hF511; -defparam \D[2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout -// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\D[2]~53_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|pin_control_|bus_db_pin_re~combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|execute_|fIORead~3_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .datac(\z80_|execute_|fMRead~36_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y12_N17 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|alu_control_|db[2]~30_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N10 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[2]~12_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y13_N9 -dffeas \z80_|ir_|opcode[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), .datac(\z80_|execute_|ctl_state_alu~2_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .combout(\z80_|execute_|ctl_sw_1d~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_1d~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_1d~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Location: LCCOMB_X31_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datab(\z80_|pla_decode_|Equal47~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( -// Equation(s): -// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datab(\z80_|alu_control_|db[6]~12_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & -// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(\z80_|alu_control_|db[6]~21_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; -defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), - .datab(gnd), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; -defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( -// Equation(s): -// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(\z80_|alu_control_|db[6]~13_combout ), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), - .datad(\z80_|sw1_|db_down[6]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; -defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|alu_control_|db[6]~23_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N2 -cycloneive_lcell_comb \D[6]~103 ( -// Equation(s): -// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~103 .lut_mask = 16'hEA4A; -defparam \D[6]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N30 -cycloneive_lcell_comb \D[6]~104 ( -// Equation(s): -// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~103_combout ), - .cin(gnd), - .combout(\D[6]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~104 .lut_mask = 16'hEE30; -defparam \D[6]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~115_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N14 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\z80_|address_pins_|abus[14]~22_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hBCB0; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N12 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\D[6]~100_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'h2D28; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N0 -cycloneive_lcell_comb \D[6]~102 ( -// Equation(s): -// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~100_combout ), - .datad(\D[6]~101_combout ), - .cin(gnd), - .combout(\D[6]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~102 .lut_mask = 16'hC3E0; -defparam \D[6]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N8 -cycloneive_lcell_comb \D[6]~127 ( -// Equation(s): -// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~104_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[6]~104_combout ), - .datad(\D[6]~102_combout ), - .cin(gnd), - .combout(\D[6]~127_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~127 .lut_mask = 16'hF4B0; -defparam \D[6]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N28 -cycloneive_lcell_comb \D[6]~99 ( -// Equation(s): -// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\raw_loader_in~input_o ), - .cin(gnd), - .combout(\D[6]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~99 .lut_mask = 16'hFFCF; -defparam \D[6]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N10 -cycloneive_lcell_comb \D[6]~114 ( -// Equation(s): -// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~114_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~114 .lut_mask = 16'hFB73; -defparam \D[6]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N12 -cycloneive_lcell_comb \D[6]~115 ( -// Equation(s): -// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\D[6]~114_combout ), - .cin(gnd), - .combout(\D[6]~115_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~115 .lut_mask = 16'hF511; -defparam \D[6]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & -// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[6]~115_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[6]~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N15 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N14 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[6]~9_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) +// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # -// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|interrupts_|iff1~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y12_N5 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y27_N8 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal2~3_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|ir_|opcode [5]))) - .dataa(\ula_|video_|Equal2~2_combout ), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\ula_|video_|vga_hc [7]), - .datad(\z80_|interrupts_|iff1~q ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y27_N9 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); // synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N25 -dffeas \z80_|interrupts_|DFFE_inst44 ( +// Location: FF_X29_Y18_N25 +dffeas \z80_|decode_state_|DFFE_instED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), + .q(\z80_|decode_state_|DFFE_instED~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(gnd), - .datad(\z80_|decode_state_|in_halt~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N16 +// Location: LCCOMB_X36_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal77~0_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0002; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -43892,24 +8215,58 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y11_N12 +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( +// Equation(s): +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|decode_state_|in_halt~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0044; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|decode_state_|in_halt~0_combout ), - .datab(\z80_|pla_decode_|Equal77~1_combout ), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N13 +// Location: FF_X31_Y12_N29 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -43928,407 +8285,30744 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N22 +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) + + .dataa(gnd), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h0505; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~3 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_sw_1d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0101; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'hC000; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hA0A0; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~0_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_state_iy_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~55_combout & !\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N25 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal1~1_combout ) # (!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|pla_decode_|Equal3~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hDFFF; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// (((!\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h707F; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N25 +dffeas \z80_|decode_state_|DFFE_inst4 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~1_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_inst4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~3 ( +// Equation(s): +// \z80_|execute_|ixy_d~3_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~3 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( +// Equation(s): +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|ir_|opcode [6] & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (\z80_|execute_|ixy_d~8_combout ) # ((\z80_|execute_|ixy_d~16_combout ) # ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ixy_d~11_combout & +// ((\z80_|execute_|ixy_d~12_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~12_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hBBB0; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~2 ( +// Equation(s): +// \z80_|execute_|ixy_d~2_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~2 .lut_mask = 16'h0500; +defparam \z80_|execute_|ixy_d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~13_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~10_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|ixy_d~14_combout ))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q +// & \z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~19 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~19_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~19 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~8_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~8 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_bus_db_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~8_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h7500; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~4_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~16_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_mWrite~10_combout ))) # (!\z80_|execute_|ctl_ir_we~16_combout & (((!\z80_|execute_|ctl_ir_we~15_combout ) # +// (!\z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|nM1_int~2_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3])) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal1~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal9~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|pla_decode_|Equal47~0_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal77~0_combout ), + .dataa(\z80_|execute_|ctl_mRead~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~19_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h3700; defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal12~0_combout ))) - .dataa(\z80_|execute_|ctl_mRead~21_combout ), - .datab(\z80_|execute_|fMRead~7_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMWrite~0_combout ), + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal12~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_mRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y8_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~3_combout ), - .datab(\z80_|execute_|fMRead~4_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) +// \z80_|execute_|ctl_reg_in_hi~9_combout = ((!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) .dataa(\z80_|execute_|ctl_mRead~12_combout ), .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~21_combout & (\z80_|execute_|ctl_reg_in_hi~9_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - .dataa(\z80_|pla_decode_|Equal41~2_combout ), - .datab(\z80_|execute_|nextM~4_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_mRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Location: LCCOMB_X36_Y11_N14 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~15_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|ir_|opcode [7]), + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N15 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~15_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~18_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout & (((!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h0037; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (((!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h3070; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|pla_decode_|Equal44~0_combout ))) - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|fMRead~29_combout ), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( // Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) +// \z80_|pla_decode_|Equal52~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), + .combout(\z80_|pla_decode_|Equal52~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X35_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) - - .dataa(\z80_|execute_|fMRead~28_combout ), - .datab(\z80_|execute_|fMRead~30_combout ), - .datac(\z80_|execute_|fMRead~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( -// Equation(s): -// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~37_combout ), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; -defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X35_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) +// \z80_|execute_|fMRead~20_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~11_combout )))) - .dataa(\z80_|execute_|fMRead~27_combout ), - .datab(\z80_|execute_|fMRead~6_combout ), - .datac(\z80_|execute_|fMRead~32_combout ), - .datad(\z80_|execute_|fMRead~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~16_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|pc_inc_hold~33_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|fMRead~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), + .combout(\z80_|execute_|fMRead~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h20A0; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X31_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|pc_inc_hold~14_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mRead~21_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|pla_decode_|Equal11~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X31_Y19_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) +// \z80_|pla_decode_|Equal10~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~6_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datab(\z80_|execute_|ctl_mRead~2_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|pla_decode_|Equal10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X35_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|execute_|fMRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~12_combout ), + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|pla_decode_|Equal3~1_combout ), .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y6_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X35_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|fMWrite~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|execute_|fMRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y6_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~16_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|fMRead~15_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N10 +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|execute_|ctl_ir_we~9_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|fMRead~19_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_mWrite~11_combout ))) + + .dataa(\z80_|execute_|fMRead~19_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~2_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [3])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~2 .lut_mask = 16'h0003; +defparam \z80_|pla_decode_|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~2_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~2_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (((!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~32_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal34~0_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & \z80_|execute_|ctl_reg_in_hi~10_combout ))) - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .dataa(\z80_|execute_|ctl_mRead~22_combout ), .datab(\z80_|execute_|fMRead~21_combout ), - .datac(\z80_|execute_|fMRead~17_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'h8000; defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( // Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|fMRead~22_combout ))) - .dataa(\z80_|execute_|fMRead~23_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2d~8_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), .datad(\z80_|execute_|fMRead~22_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N0 +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (!\z80_|execute_|ctl_sw_1d~3_combout & (!\z80_|execute_|ctl_im_we~combout & \z80_|execute_|ctl_sw_2d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~3_combout ), + .datac(\z80_|execute_|ctl_im_we~combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # (((\z80_|execute_|ctl_bus_db_oe~4_combout & \z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = ((\z80_|execute_|ctl_bus_db_oe~5_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) # (!\z80_|execute_|ctl_bus_db_oe~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~3_combout = (\z80_|execute_|ctl_bus_zero_oe~2_combout ) # ((\z80_|decode_state_|in_halt~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~3 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_bus_zero_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|execute_|ctl_bus_db_oe~7_combout ) # (!\z80_|execute_|ctl_sw_1d~4_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'h000D; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [1] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[7]~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal44~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = ((!\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_flags_bus~8_combout & !\z80_|execute_|ctl_mRead~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'hFF1F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal68~2_combout & !\z80_|pla_decode_|Equal20~0_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal68~2_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~10_combout & (\z80_|execute_|ctl_flags_bus~11_combout & \z80_|execute_|ctl_flags_bus~14_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~10_combout ), + .datac(\z80_|execute_|ctl_flags_bus~11_combout ), + .datad(\z80_|execute_|ctl_flags_bus~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~16_combout = (\z80_|execute_|ctl_flags_xy_we~13_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~17_combout = (\z80_|execute_|ixy_d~4_combout & (!\z80_|execute_|ctl_mRead~24_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~4_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal2~2_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~17_combout & (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~28 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~28_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~28 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~28_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_inc_cy~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~16_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h00EA; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_reg_out_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (\z80_|execute_|ctl_reg_out_lo~6_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~30_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~1_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout )) # +// (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~13_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~19_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~19 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_ir_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|ir_|opcode [7])) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~19_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|setM1~58_combout )) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_sw_2u~6_combout ) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|setM1~58_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout & (\z80_|execute_|ctl_reg_out_lo~2_combout & ((!\z80_|execute_|ctl_sw_2u~7_combout ) # (!\z80_|execute_|rsel0~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) # (!\z80_|execute_|ctl_sw_1d~4_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~4_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h7333; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~29 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~3_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~4_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|rsel3~combout ) # ((!\z80_|execute_|ctl_reg_out_lo~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~3 .lut_mask = 16'h4C5F; +defparam \z80_|execute_|ctl_reg_out_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~9_combout = (\z80_|execute_|ctl_sw_2u~7_combout & (\z80_|ir_|opcode [0] $ (((!\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1]))))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~9 .lut_mask = 16'h9500; +defparam \z80_|execute_|ctl_sw_2u~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & +// (((!\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|execute_|ctl_mWrite~18_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~4_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_alu_oe~4_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout & (\z80_|execute_|ctl_reg_out_hi~3_combout & (!\z80_|execute_|ctl_sw_2u~9_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~3_combout ), + .datac(\z80_|execute_|ctl_sw_2u~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) # (!\z80_|execute_|ctl_ir_we~19_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|execute_|ctl_ir_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~3_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~4_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h5557; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h0888; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~14_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ixy_d~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h30F0; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_ir_we~8_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_alu_oe~10_combout & (\z80_|execute_|ctl_bus_db_we~6_combout & \z80_|execute_|ctl_reg_in_lo~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~10_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~8_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~8 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_sw_2u~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF5F5; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal69~0_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0015; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|pla_decode_|Equal20~0_combout & (\z80_|execute_|nextM~4_combout & !\z80_|execute_|ctl_ir_we~12_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0030; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~49_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|setM1~51_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h1050; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~9_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~9 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_sw_4d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~6_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~52_combout ))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h007F; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout ) # ((\z80_|execute_|ctl_sw_2u~8_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_flags_alu~21_combout & \z80_|execute_|ctl_flags_alu~19_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_alu~21_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal56~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~2_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~2 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal1~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBF0; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_flags_alu~22_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~22_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # (\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0A00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~13_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~14_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & \z80_|execute_|ctl_reg_out_hi~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|nextM~12_combout & \z80_|execute_|ctl_reg_use_sp~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (!\z80_|ir_|opcode [5] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h1300; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~16_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & \z80_|execute_|ctl_sw_2d~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_sw_2d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|execute_|ctl_reg_use_sp~1_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~14_combout & ((\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAFAB; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h007F; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & \z80_|execute_|ctl_alu_op_low~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_sw_2u~3_combout & !\z80_|execute_|ctl_alu_shift_oe~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|setM1~19_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|setM1~19_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~8 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~8_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_cf_we~7_combout & \z80_|execute_|ctl_flags_use_cf2~13_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~8 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_pf_sel[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_alu_op_low~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~15_combout = (\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) +// # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~15 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & (((!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_flags_pf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~1_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_flags_pf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & +// (((!\z80_|execute_|ctl_mWrite~19_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & (\z80_|execute_|ctl_flags_pf_we~1_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_flags_alu~12_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_alu~17_combout )) # (!\z80_|execute_|ctl_flags_alu~23_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~12_combout ), + .datab(\z80_|execute_|ctl_flags_alu~23_combout ), + .datac(\z80_|execute_|ctl_flags_alu~17_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~5_combout )))) # (!\z80_|pla_decode_|Equal48~0_combout & +// (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_alu_oe~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFD; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_ir_we~18_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_ir_we~13_combout & +// (((!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~16 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & +// (((!\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_oe~16_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & \z80_|execute_|ctl_alu_core_S~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~16_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (\z80_|execute_|ctl_flags_pf_we~1_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~16_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~23_combout & (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~23_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~50_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~50 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal1~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal1~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~17_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~5_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF200; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~19_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = ((!\z80_|execute_|ixy_d~5_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h2020; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~49_combout = ((\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~49 .lut_mask = 16'hD555; +defparam \z80_|execute_|ctl_alu_shift_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = ((\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~49_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~51_combout = (\z80_|execute_|ctl_ir_we~11_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~51_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~14_combout & (\z80_|execute_|ctl_alu_shift_oe~51_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~51_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0EAA; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~48_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~14_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~48 .lut_mask = 16'hBAAA; +defparam \z80_|execute_|ctl_alu_shift_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & !\z80_|execute_|ctl_reg_gp_sel~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = (((\z80_|execute_|ctl_alu_shift_oe~48_combout & !\z80_|execute_|ctl_alu_bs_oe~8_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~48_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_mRead~34_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (\z80_|execute_|ctl_alu_shift_oe~35_combout & (\z80_|execute_|ctl_alu_shift_oe~34_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ))) # (!\z80_|execute_|ixy_d~5_combout & +// (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'hCE0A; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = ((\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~24_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_ir_we~11_combout & +// (((\z80_|execute_|ctl_ir_we~14_combout & \z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # (((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~36_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~18_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'hF400; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~47_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout )))) # +// (!\z80_|execute_|ctl_ir_we~13_combout & (((\z80_|execute_|ctl_alu_shift_oe~26_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3F20; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (\z80_|execute_|ctl_mWrite~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~27_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) # +// (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout & \z80_|execute_|ctl_mWrite~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (\z80_|execute_|ctl_alu_shift_oe~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_alu_bs_oe~combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|alu_|db_high[3]~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~17_combout = (\z80_|execute_|ctl_alu_oe~9_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_oe~9_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_alu_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_oe~5_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_oe~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_alu_oe~8_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~12_combout ) # ((\z80_|execute_|ctl_66_oe~4_combout ) # (\z80_|execute_|ctl_alu_oe~13_combout ))) # (!\z80_|execute_|ctl_alu_oe~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~12_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # (((!\z80_|execute_|ctl_flags_alu~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_alu~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|nextM~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (((\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~17_combout ) # (\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|rsel3~combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~11_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0F07; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~10_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hDCFC; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = (\z80_|execute_|ctl_sw_2d~12_combout ) # (((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout )) # (!\z80_|execute_|ctl_reg_out_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_sw_2d~12_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_sw_2d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~15_combout ) # ((\z80_|execute_|ctl_reg_out_hi~5_combout ) # (\z80_|execute_|ctl_sw_2d~13_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~22_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|pla_decode_|Equal37~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal37~0_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|fMRead~10_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'h1F00; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|fMRead~11_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|fMRead~9_combout )) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~9_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~27_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~27 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_sel_wz~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal47~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~14_combout ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'hAA00; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_reg_in_hi~7_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~12_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h0011; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h2323; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & ((\z80_|execute_|ctl_reg_sel_wz~16_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'hAF03; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~22_combout = (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal5~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal5~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal2~3_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal2~3_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal5~2 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (((\z80_|execute_|setM1~43_combout & !\z80_|pla_decode_|Equal5~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h0233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_mRead~9_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_mRead~9_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~36_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~4_combout & (\z80_|execute_|ctl_inc_dec~2_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_sw_1d~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_sw_1d~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|execute_|ctl_sw_4d~5_combout & (\z80_|execute_|ctl_reg_sel_wz~22_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|ctl_ir_we~8_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h3F2A; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_al_we~7_combout ) # (((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (!\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout & (!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~3_combout = (!\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~3 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_al_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (!\z80_|execute_|ctl_mRead~4_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|ir_|opcode [1])))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'h4555; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )) # (!\z80_|execute_|ctl_al_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~3_combout ), + .datab(\z80_|execute_|ctl_apin_mux~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout ))) # (!\z80_|pla_decode_|Equal77~0_combout ) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & !\z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout )) # (!\z80_|execute_|ctl_alu_oe~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~7_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_ir_we~18_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (!\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0300; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & \z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~17_combout & (!\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~2_combout = (!\z80_|execute_|ctl_mRead~3_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~2 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # ((!\z80_|execute_|ctl_al_we~2_combout ) # (!\z80_|execute_|setM1~48_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = ((\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_al_we~4_combout ) # (\z80_|execute_|ctl_al_we~6_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_al_we~8_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout ))) # (!\z80_|execute_|setM1~55_combout ) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~9_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N25 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~0_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h0F0D; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & \z80_|pla_decode_|Equal52~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~8_combout ) # (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_reg_gp_sel~13_combout )) # (!\z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_state_alu~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~9 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|ir_|opcode [5]) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~9 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_pf_sel[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_flags_pf_we~2_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~50_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~50_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~7_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[2] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [2] = (\z80_|bus_control_|db[2]~14_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[2]~14_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h80FF; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal21~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~2_combout = ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # (\z80_|execute_|ctl_alu_op1_oe~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~2 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_alu_op1_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_ir_we~15_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h5400; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|execute_|ctl_alu_op_low~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|pla_decode_|Equal48~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~4_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~18_combout & ((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~13_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~13_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~15_combout )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # +// (!\z80_|execute_|ctl_ir_we~11_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~5_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~5_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~36_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[3]~5_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db_low[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFEE; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N17 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N25 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|execute_|ixy_d~3_combout & (((\z80_|execute_|ctl_eval_cond~0_combout & +// \z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFCA0; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~10_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # ((\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~7_combout & ((\z80_|execute_|ctl_alu_op_low~11_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (((\z80_|execute_|ctl_alu_op_low~17_combout ) # (!\z80_|execute_|ctl_state_alu~7_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'h5FDF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout ) # (((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h00C0; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ixy_d~3_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal21~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal21~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~16_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'h88C0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[3]~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|alu_|db_low[3]~5_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h5540; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N5 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~2 ( +// Equation(s): +// \z80_|alu_|db_low[3]~2_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [3])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~2 .lut_mask = 16'hF351; +defparam \z80_|alu_|db_low[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~3 ( +// Equation(s): +// \z80_|alu_|db_low[3]~3_combout = (\z80_|alu_|db_low[3]~2_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[3]~2_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~3 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|alu_|db_low[3]~3_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_low[3]~3_combout ), + .datad(\z80_|alu_|result_lo [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hF0A0; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_out_lo~9_combout & (\z80_|execute_|ctl_inc_cy~29_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~35_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~24_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~16_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~24 .lut_mask = 16'h0111; +defparam \z80_|execute_|ctl_reg_sel_wz~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout +// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout = (\z80_|execute_|ctl_mRead~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~18_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~25_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~24_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~24_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~25 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~3_combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_sw_4u~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ctl_inc_cy~80_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~80_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~14_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout & (\z80_|execute_|ctl_inc_cy~79_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout & \z80_|execute_|ctl_inc_cy~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~14 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal4~0_combout & \z80_|sequencer_|DFFE_T5_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ixy_d~3_combout ))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & +// !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_inc_cy~72_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_inc_cy~72_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|execute_|ctl_inc_cy~44_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~73_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|ctl_inc_cy~44_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_bus_inc_oe~36_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (!\z80_|execute_|ctl_sw_4u~2_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~17_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|execute_|ctl_sw_4u~1_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hFBBB; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~25_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~16_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_mRead~14_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'hF4F4; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (\z80_|execute_|ctl_reg_sel_pc~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ixy_d~16_combout & +// (((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_reg_sel_pc~5_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~22_combout = (((!\z80_|execute_|ixy_d~9_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~22 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_sel_pc~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~3_combout ) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_reg_sel_pc~8_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~22_combout & \z80_|execute_|ctl_reg_sel_pc~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (!\z80_|execute_|ctl_reg_sel_pc~11_combout & (\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & \z80_|execute_|ctl_inc_cy~35_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|ctl_inc_cy~77_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (!\z80_|pla_decode_|Equal52~0_combout & !\z80_|pla_decode_|Equal21~1_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h0303; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0011; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|ixy_d~8_combout & (!\z80_|pla_decode_|Equal33~2_combout & ((!\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0105; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|pc_inc_hold~16_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~20_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_reg_sel_pc~16_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~20 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_bus_inc_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~21_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|ctl_bus_inc_oe~20_combout & !\z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~21 .lut_mask = 16'h0A8A; +defparam \z80_|execute_|ctl_bus_inc_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hF0C0; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|pc_inc_hold~18_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hEC00; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~19_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal33~3_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~19 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_bus_inc_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~19_combout & \z80_|execute_|ixy_d~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~4_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~4_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~20_combout ) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) # (!\z80_|execute_|ctl_reg_in_hi~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~11_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (\z80_|execute_|ctl_reg_sel_pc~13_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_sw_4d~9_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (\z80_|execute_|setM1~55_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~16_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~6_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_reg_sys_hilo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|ctl_reg_sys_hilo~6_combout ) # ((!\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3310; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (!\z80_|pla_decode_|Equal24~0_combout & !\z80_|pla_decode_|Equal35~0_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'h0055; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~8_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_inc_dec~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # ((!\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_inc_dec~3_combout & +// (!\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ctl_reg_sys_hilo~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'h8ACF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h5100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~17_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h3B00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((\z80_|execute_|ctl_al_we~3_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h00A2; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|execute_|ctl_bus_db_oe~2_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_sel_wz~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_pc~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|execute_|ctl_reg_sel_wz~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~30_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~30 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_reg_sel_wz~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (!\z80_|execute_|ctl_reg_sel_wz~30_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (((!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~12_combout )) # (!\z80_|execute_|ctl_reg_out_hi~2_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hF777; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFAFF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~7_combout )) # (!\z80_|execute_|setM1~48_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_al_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~8_combout = ((\z80_|execute_|ctl_sw_4d~2_combout ) # ((\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_state_alu~3_combout ))) # (!\z80_|execute_|ctl_sw_4d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_4d~7_combout ), + .datab(\z80_|execute_|ctl_sw_4d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~8 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_sw_4d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~8_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hBF00; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = (\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datab(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'h8C8C; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = (!\z80_|execute_|ctl_mWrite~8_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'h3233; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~17_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~19_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~17 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_bus_inc_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~18_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_bus_inc_oe~38_combout & \z80_|execute_|ctl_bus_inc_oe~17_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~25_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~26_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~18_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~27_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~24_combout = ((\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~36_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~22_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~22 .lut_mask = 16'h151F; +defparam \z80_|execute_|ctl_bus_inc_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~23_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (\z80_|execute_|ctl_bus_inc_oe~22_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~23 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_bus_inc_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (\z80_|execute_|ctl_inc_cy~73_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (\z80_|execute_|ctl_inc_cy~44_combout & \z80_|execute_|ctl_inc_cy~74_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~74_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~24_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~24_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|ctl_bus_inc_oe~32_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~21_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~3_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # (\z80_|execute_|ctl_bus_inc_oe~33_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [11]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = ((\z80_|reg_file_|db_hi_as[3]~9_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~25_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~26_combout = (\z80_|execute_|ctl_alu_oe~17_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~17_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~25_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~2_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~1_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|pla_decode_|Equal25~0_combout ) # (!\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h00BF; +defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~17_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~51_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~51_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~17 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (!\z80_|pla_decode_|Equal49~0_combout & (!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|execute_|ctl_mRead~11_combout )) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_sw_1d~7_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal52~0_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & \z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~12_combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & \z80_|execute_|ctl_reg_gp_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mRead~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~14_combout = (\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (!\z80_|execute_|ctl_66_oe~4_combout & !\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_66_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~14 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_in_hi~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~15_combout = ((\z80_|execute_|ctl_reg_in_hi~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~15 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_reg_in_hi~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~11_combout )))) # (!\z80_|execute_|setM1~32_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ctl_al_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8FAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|ctl_sw_1d~2_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~7_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h3F2F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & ((\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|comb~1_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|comb~1_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8C00; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~28_combout = (\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~4_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|execute_|ixy_d~4_combout )) # +// (!\z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .lut_mask = 16'h115F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|execute_|fMRead~9_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~11_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ))) + + .dataa(\z80_|execute_|fMRead~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|fMRead~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|setM1~58_combout & \z80_|execute_|ctl_sw_2u~3_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|setM1~58_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = (!\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'h00BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~30_combout = (((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) # (!\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_sw_4d~9_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_4d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~3_combout = (\z80_|pla_decode_|Equal1~2_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal1~2_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N30 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|pla_decode_|Equal1~3_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N31 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~4_combout = (\z80_|pla_decode_|Equal2~3_combout & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|pla_decode_|Equal2~3_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~4 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & \z80_|execute_|ctl_sw_2u~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_sw_2u~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (!\z80_|execute_|ctl_reg_in_hi~17_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout & \z80_|execute_|ctl_reg_gp_sel[0]~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_reg_gp_sel[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout & \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~26_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~25_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .lut_mask = 16'h000E; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~43_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_reg_gp_sel[1]~25_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~27_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal12~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .lut_mask = 16'h8DCD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~28_combout = (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_reg_gp_sel[1]~27_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~27_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_sw_1d~5_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_mWrite~18_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_sw_1d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_reg_use_sp~2_combout & \z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .datad(\z80_|execute_|nextM~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|execute_|ctl_reg_use_sp~3_combout & \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~43_combout & ((\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~28_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~43_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (!\z80_|execute_|ctl_ir_we~16_combout & (\z80_|execute_|fMWrite~2_combout & \z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fMRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|ir_|opcode [2] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~19_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~41_combout = (\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) # +// (!\z80_|execute_|ctl_mRead~34_combout & (((!\z80_|execute_|nextM~4_combout & \z80_|execute_|ctl_reg_gp_sel[1]~41_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h8F88; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # (\z80_|pla_decode_|Equal5~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal5~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ))) # (!\z80_|execute_|ctl_alu_op_low~16_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|ir_|opcode [5]))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~38_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|execute_|ctl_mRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~39_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ) # ((\z80_|ir_|opcode [1] & !\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout )) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~37_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sys_hilo~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .lut_mask = 16'h08AA; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~40_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~37_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~39_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h5455; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hD800; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~6_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|reg_control_|bank_exx~q & \z80_|pla_decode_|Equal2~4_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y7_N11 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hE400; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h0A0A; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_reg_in_hi~6_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h0800; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~23_combout = (\z80_|execute_|ctl_66_oe~4_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~20_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~23 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~29_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~21_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~14_combout )))) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~29 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_reg_sel_wz~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~26_combout = (\z80_|execute_|ctl_reg_sel_wz~23_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~25_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~22_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~23_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~22_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~26 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (!\z80_|execute_|ctl_reg_use_sp~6_combout & !\z80_|reg_control_|bank_af~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_control_|bank_af~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0008; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFEFC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFFEE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~15_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|gdfx_temp1[3]~31_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[3]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hA0A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~33_combout & (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~37_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'hC040; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~10_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|reg_file_|gdfx_temp1[3]~39_combout & ((\z80_|alu_|db_low[3]~5_combout ) # ((!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|reg_file_|gdfx_temp1[3]~39_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_|db_low[3]~5_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~24_combout & (\z80_|execute_|ctl_bus_db_oe~6_combout & \z80_|execute_|ctl_flags_bus~12_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ixy_d~16_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = (\z80_|execute_|ctl_ir_we~16_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~16_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~18_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (!\z80_|execute_|fMRead~27_combout ))) # (!\z80_|execute_|ctl_flags_bus~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~13_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~7_combout ), + .datad(\z80_|execute_|fMRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout & +// (\z80_|alu_|db_low[3]~5_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|alu_control_|db[3]~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # +// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h3300; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N13 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~32 ( +// Equation(s): +// \z80_|alu_control_|db[3]~32_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (!\z80_|execute_|ctl_66_oe~combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~32 .lut_mask = 16'h1101; +defparam \z80_|alu_control_|db[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( +// Equation(s): +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|db[3]~32_combout & ((\z80_|bus_control_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|alu_control_|db[3]~32_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hD0D0; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_bus_db_oe~3_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~18_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|pc_inc_hold~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~33_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mWrite~10_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0800; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ixy_d~16_combout ) # (\z80_|pla_decode_|Equal52~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|execute_|ctl_mRead~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & +// ((\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hECA8; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~3_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|pc_inc_hold~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hEAFA; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~22_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # (\z80_|execute_|pc_inc_hold~20_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~21_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~37_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~14_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'h777F; +defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hABFF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (\z80_|execute_|pc_inc_hold~37_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|pc_inc_hold~37_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|execute_|pc_inc_hold~38_combout & (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~27_combout & \z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|execute_|pc_inc_hold~35_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout ))) # (!\z80_|execute_|ctl_inc_cy~78_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~35_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~3_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~64_combout & \z80_|execute_|ctl_inc_cy~65_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~65_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_mWrite~18_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~3_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = ((\z80_|execute_|ctl_inc_dec~6_combout ) # ((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~0_combout ))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'hDDFD; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_alu_oe~4_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F87; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout & \z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~68_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3~combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (!\z80_|execute_|pc_inc_hold~32_combout & \z80_|execute_|pc_inc_hold~28_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_inc_cy~69_combout & ((!\z80_|execute_|pc_inc_hold~29_combout ) # (!\z80_|execute_|pc_inc_hold~36_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~67_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFF2A; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (((!\z80_|execute_|ctl_inc_cy~33_combout ) # (!\z80_|execute_|ctl_inc_cy~36_combout )) # (!\z80_|execute_|ctl_inc_cy~28_combout )) # (!\z80_|execute_|ctl_inc_cy~29_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~29_combout ), + .datab(\z80_|execute_|ctl_inc_cy~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~36_combout ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((\z80_|execute_|ctl_inc_cy~71_combout ) # (!\z80_|execute_|ctl_inc_cy~74_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~32_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~70_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~75_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hEFCC; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (!\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~23_combout & (!\z80_|execute_|ctl_inc_cy~81_combout & \z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~23_combout ), + .datac(\z80_|execute_|ctl_inc_cy~81_combout ), + .datad(\z80_|execute_|pc_inc_hold~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|pc_inc_hold~38_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~38_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hAAFF; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|pc_inc_hold~30_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|pc_inc_hold~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0A08; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (\z80_|execute_|ctl_alu_oe~4_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~4_combout & +// (\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ctl_inc_cy~79_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~79_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_inc_cy~42_combout ) # ((\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~42_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|execute_|ctl_inc_cy~41_combout ) # ((\z80_|execute_|ctl_inc_cy~40_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # (!\z80_|execute_|ctl_inc_cy~44_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~41_combout ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|execute_|ctl_inc_cy~44_combout ), + .datad(\z80_|execute_|ctl_inc_cy~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~30 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~30_combout = ((!\z80_|execute_|ixy_d~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~8_combout ))) # (!\z80_|execute_|ctl_mWrite~18_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~18_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~30 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~31 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~31_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_inc_cy~30_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~31 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & (!\z80_|execute_|pc_inc_hold~29_combout +// & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~31_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~45_combout ), + .datad(\z80_|execute_|ctl_inc_cy~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hB0BB; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (!\z80_|execute_|ctl_inc_cy~34_combout & (((\z80_|execute_|pc_inc_hold~19_combout & !\z80_|execute_|pc_inc_hold~23_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), + .datab(\z80_|execute_|pc_inc_hold~19_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0545; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~48_combout ) # ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # (\z80_|execute_|ctl_inc_cy~47_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~48_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~46_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout & (!\z80_|execute_|pc_inc_hold~20_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h0013; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|execute_|ctl_mRead~7_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((\z80_|execute_|ctl_inc_cy~60_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~29_combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~20_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~16_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_mRead~34_combout & +// \z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ixy_d~3_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~19_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~9_combout ) + + .dataa(\z80_|execute_|ixy_d~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datab(\z80_|execute_|ctl_inc_cy~55_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (!\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|execute_|ctl_inc_cy~56_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_inc_cy~57_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datab(\z80_|execute_|ctl_inc_cy~57_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h0F08; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~21_combout ) # ((\z80_|execute_|pc_inc_hold~20_combout ) # ((\z80_|execute_|ctl_mRead~7_combout & \z80_|execute_|ixy_d~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|pc_inc_hold~21_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_mRead~11_combout & (!\z80_|interrupts_|DFFE_inst44~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~8_combout & !\z80_|execute_|pc_inc_hold~20_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h888C; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~18_combout & (!\z80_|execute_|pc_inc_hold~31_combout & \z80_|execute_|ctl_mRead~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~31_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|execute_|ctl_inc_cy~61_combout ) # ((\z80_|execute_|ctl_inc_cy~58_combout ) # (\z80_|execute_|ctl_inc_cy~53_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|ctl_inc_cy~61_combout ), + .datac(\z80_|execute_|ctl_inc_cy~58_combout ), + .datad(\z80_|execute_|ctl_inc_cy~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~29_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~77_combout & ((\z80_|execute_|pc_inc_hold~28_combout ) # ((!\z80_|execute_|pc_inc_hold~29_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~77_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hC4F5; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((!\z80_|execute_|pc_inc_hold~30_combout & (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout & !\z80_|execute_|pc_inc_hold~27_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~30_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~27_combout ), + .datad(\z80_|execute_|ctl_inc_cy~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout & (((\z80_|execute_|ctl_inc_cy~78_combout & \z80_|execute_|pc_inc_hold~28_combout )) # (!\z80_|execute_|pc_inc_hold~29_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3~combout ), + .datad(\z80_|execute_|pc_inc_hold~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((\z80_|execute_|ctl_inc_cy~39_combout ) # (\z80_|execute_|ctl_inc_cy~37_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|ctl_inc_cy~62_combout ), + .datac(\z80_|execute_|ctl_inc_cy~39_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_inc_cy~76_combout ) # +// (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~66_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datac(\z80_|execute_|ctl_inc_cy~76_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hCCC8; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|address_latch_|Q[3]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[3]~feeder_combout = \z80_|address_latch_|abusz [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = ((\z80_|execute_|ctl_inc_dec~7_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ctl_reg_gp_sel~13_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~37_combout = (\z80_|execute_|setM1~51_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & ((\z80_|execute_|rsel0~combout )))) # (!\z80_|execute_|setM1~51_combout & (((\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout +// & \z80_|execute_|rsel0~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|rsel0~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .lut_mask = 16'hCD05; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mWrite~18_combout ) # (\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~39_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .lut_mask = 16'hF4F5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (\z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h006A; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~4_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~42_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ctl_mRead~23_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~40_combout = (\z80_|execute_|ctl_ir_we~18_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~18_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~41_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|pla_decode_|Equal25~0_combout & (!\z80_|pla_decode_|Equal12~1_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~43_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ) # (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~44_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~39_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout = (((\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~29_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h00C8; +defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & !\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~36_combout = (\z80_|execute_|ctl_reg_sel_wz~28_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hDF5F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~36_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_mRead~3_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_in_hi~14_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~29_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~29_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~14_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~21_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|reg_control_|reg_sel_de2~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|reg_control_|reg_sel_de~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|reg_control_|reg_sel_de~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & \z80_|execute_|ctl_reg_gp_we~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'h8888; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~40_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[2]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~40_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~40_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & (\z80_|execute_|ctl_reg_sel_wz~26_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~40_combout & (\z80_|reg_file_|gdfx_temp0[2]~36_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~38_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (!\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout & (\z80_|execute_|ctl_reg_gp_we~7_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~45_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~41_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~43_combout = ((\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[2]~43_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~33_combout ) # ((\z80_|execute_|ctl_sw_4d~8_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|execute_|ctl_sw_4d~8_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[1]~22_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|gdfx_temp0[1]~27_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~33_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~26_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~31_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~33_combout = ((\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp0[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[1]~33_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datac(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ +// (\z80_|address_latch_|Q [1]))))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [1]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N13 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [2]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [2]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [1]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h6666; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~13_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[3]~63_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~14_combout = (\z80_|reg_file_|db_lo_as[3]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~13_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~14 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~15_combout = ((\z80_|reg_file_|db_lo_as[3]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~15 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~57_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~35_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~58_combout = (\z80_|reg_file_|gdfx_temp0[3]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[3]~57_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[3]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~59_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~61_combout = (\z80_|reg_file_|gdfx_temp0[3]~58_combout & (\z80_|reg_file_|gdfx_temp0[3]~60_combout & (\z80_|reg_file_|gdfx_temp0[3]~59_combout & \z80_|reg_file_|gdfx_temp0[3]~56_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~60_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~59_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~63_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~62_combout = (\z80_|reg_file_|gdfx_temp0[3]~55_combout & (\z80_|reg_file_|gdfx_temp0[3]~61_combout & \z80_|reg_file_|gdfx_temp0[3]~54_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~55_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~61_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~63_combout = ((\z80_|reg_file_|gdfx_temp0[3]~62_combout & ((\z80_|reg_file_|db_lo_as[3]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~15_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[3]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & ((\z80_|reg_file_|gdfx_temp0[3]~63_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[3]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~63_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8A8A; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hB3BB; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[3]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~16_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~16_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~8_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~4_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|alu_control_|db[1]~22_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = (\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N31 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout = \z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [3]) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~67_combout = (\z80_|reg_file_|gdfx_temp0[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~65_combout = (\z80_|reg_file_|gdfx_temp0[4]~64_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|gdfx_temp0[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~70_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp0[4]~73_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~71_combout = (\z80_|reg_file_|gdfx_temp0[4]~70_combout & (\z80_|reg_file_|gdfx_temp0[4]~69_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~70_combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .lut_mask = 16'h8A00; +defparam \z80_|reg_file_|gdfx_temp0[4]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~72_combout = (\z80_|reg_file_|gdfx_temp0[4]~68_combout & (\z80_|reg_file_|gdfx_temp0[4]~67_combout & (\z80_|reg_file_|gdfx_temp0[4]~65_combout & \z80_|reg_file_|gdfx_temp0[4]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~73_combout = ((\z80_|reg_file_|gdfx_temp0[4]~72_combout & ((\z80_|reg_file_|db_lo_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~16_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~17_combout = (\z80_|reg_file_|db_lo_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[4]~16_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~17 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~18_combout = ((\z80_|reg_file_|db_lo_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~18 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N15 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~49_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_high[2]~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N3 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3222; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( +// Equation(s): +// \z80_|alu_|db_low[1]~14_combout = ((!\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|db_low[1]~15_combout & (\z80_|alu_|db_low[1]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|alu_|db_low[1]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ))) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hB030; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N1 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|execute_|ctl_alu_core_S~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|ir_|opcode [4]) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = (\z80_|execute_|ctl_alu_op_low~33_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & \z80_|execute_|ctl_flags_pf_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hC080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|execute_|ctl_alu_core_R~2_combout ) # ((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~9_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|pla_decode_|Equal73~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (\z80_|execute_|ctl_state_alu~11_combout & !\z80_|ir_|opcode [5]) + + .dataa(\z80_|execute_|ctl_state_alu~11_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hA800; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'hCC40; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~25_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & !\z80_|pla_decode_|Equal72~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal73~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|pla_decode_|Equal72~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hA080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h153F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~20 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~20_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~20 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mWrite~19_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~20_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h0515; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|execute_|ctl_flags_cf_cpl~0_combout & ((\z80_|execute_|ctl_alu_op_low~22_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (!\z80_|execute_|ctl_alu_op_low~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & !\z80_|execute_|ctl_flags_cf_cpl~1_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0008; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[0]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h3336; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDD5D; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y9_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~25_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|gdfx_temp0[0]~17_combout & \z80_|reg_file_|gdfx_temp0[0]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~23_combout = ((\z80_|reg_file_|gdfx_temp0[0]~18_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[0]~4_combout = (\z80_|reg_file_|gdfx_temp0[0]~23_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~23_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[0]~4 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~23 ( +// Equation(s): +// \z80_|alu_control_|db[0]~23_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2u~8_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[0]~18_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~23 .lut_mask = 16'hF500; +defparam \z80_|alu_control_|db[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[0]~12_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~24 ( +// Equation(s): +// \z80_|alu_control_|db[0]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_cf~combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (((\z80_|sw1_|SYNTHESIZED_WIRE_2 [0])) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|sw1_|SYNTHESIZED_WIRE_2 [0]), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~24 .lut_mask = 16'hF531; +defparam \z80_|alu_control_|db[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~25 ( +// Equation(s): +// \z80_|alu_control_|db[0]~25_combout = ((\z80_|reg_file_|db_lo_ds[0]~4_combout & (\z80_|alu_control_|db[0]~23_combout & \z80_|alu_control_|db[0]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[0]~4_combout ), + .datab(\z80_|alu_control_|db[0]~23_combout ), + .datac(\z80_|alu_control_|db[0]~24_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~25 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_control_|db[0]~25_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # +// (!\z80_|alu_control_|db[0]~25_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[0]~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h8F88; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~15_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hEF00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~18_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (((\z80_|execute_|ctl_flags_cf_we~4_combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )) # (!\z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout = (\z80_|execute_|ixy_d~14_combout & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ixy_d~14_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~0_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|execute_|ctl_flags_cf2_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ) # ((\z80_|execute_|ctl_flags_cf2_we~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_flags_cf2_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~1_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~9_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~0_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~1_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|ir_|opcode [6] & (\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout & !\z80_|ir_|opcode [7]))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~0_combout ), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'hFFE0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [7] & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[7]~20_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|alu_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~81_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~82_combout = (\z80_|reg_file_|gdfx_temp1[7]~79_combout & (\z80_|reg_file_|gdfx_temp1[7]~80_combout & (\z80_|reg_file_|gdfx_temp1[7]~81_combout & \z80_|reg_file_|gdfx_temp1[7]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~83_combout = (\z80_|reg_file_|gdfx_temp1[7]~77_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout & (\z80_|reg_file_|gdfx_temp1[7]~82_combout & \z80_|reg_file_|gdfx_temp1[7]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~77_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[7]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~23_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~23 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~24_combout = (\z80_|reg_file_|db_hi_as[7]~23_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~24 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_hi_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~25_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~10_combout $ (\z80_|address_latch_|Q [14]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~25 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~25_combout = ((\z80_|reg_file_|db_hi_as[7]~24_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~24_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~25 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[7]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~84_combout = ((\z80_|reg_file_|gdfx_temp1[7]~83_combout & ((\z80_|reg_file_|db_hi_as[7]~25_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp1[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~84_combout & ((\z80_|alu_control_|db[7]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[7]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~84_combout ), + .datab(\z80_|alu_control_|db[7]~15_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'h8CAF; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~19_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~20_combout ))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_control_|out[6]~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # +// (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h5432; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout $ ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~1_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout & \z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hFE04; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8030; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal10~1_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|pla_decode_|Equal10~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_flags_alu~20_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_flags_alu~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hF2F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~16_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~16_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_core_S~12_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & \z80_|execute_|ctl_flags_sz_we~0_combout +// ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (((!\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # (((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBBB; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~41_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFAFF; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout & +// \z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_alu_core_hf~16_combout & !\z80_|pla_decode_|Equal71~2_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal71~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h0088; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal61~2_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'h2F3F; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|execute_|ctl_flags_nf_we~2_combout ) # ((!\z80_|execute_|ctl_flags_nf_we~1_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hEEEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_control_|db[1]~22_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datab(\z80_|alu_control_|db[1]~22_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~18_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h10F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'hD850; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h0E0E; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h7773; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((\z80_|pla_decode_|Equal68~2_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hCC08; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal71~2_combout ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal71~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~8_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal21~1_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & !\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout )))) # +// (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|execute_|ctl_alu_core_hf~15_combout ) # ((!\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFF04; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ixy_d~4_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~20_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (((\z80_|execute_|ctl_alu_op_low~30_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~19_combout )) # (!\z80_|execute_|ctl_alu_op_low~34_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout & (((\z80_|execute_|ctl_alu_core_hf~21_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~23_combout & (\z80_|execute_|ctl_alu_core_hf~21_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ixy_d~5_combout & ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_core_hf~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h0302; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mWrite~10_combout & !\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_mRead~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) # (!\z80_|execute_|ctl_mRead~5_combout & +// (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hCC0A; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (!\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout ))) # +// (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (!\z80_|execute_|ctl_alu_shift_oe~19_combout & (((!\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~30_combout & ((\z80_|execute_|ctl_alu_core_hf~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((!\z80_|execute_|ctl_alu_op_low~21_combout & \z80_|execute_|ctl_alu_core_hf~32_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFF22; +defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~39_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~39_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hAA08; +defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_alu_core_hf~24_combout ) # ((\z80_|execute_|ctl_alu_core_hf~33_combout ) # ((!\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_core_hf~40_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_core_hf~19_combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~35_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~35_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(gnd), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hF0CC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[0]~25_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N19 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[0]~23_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N7 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hC0A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0E0A; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(gnd), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF5A0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ) # (!\z80_|execute_|ctl_reg_out_hi~2_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hFB33; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~34_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~12_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ +// (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hB2E8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|pla_decode_|Equal71~2_combout ) # (\z80_|execute_|ctl_alu_core_S~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal71~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hAAAF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~17_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[1]~17_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N29 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|alu_|op2_high [1]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h3C5A; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[1]~1_combout & \z80_|alu_|alu_op1[1]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[1]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|alu_op2[1]~1_combout ), + .datab(\z80_|alu_|op1_low [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op1[1]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// \z80_|alu_|alu_op2[1]~1_combout )))) # (!\z80_|alu_|alu_op1[1]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[1]~1_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[1]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hCE8C; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'h0088; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|alu_|db[4]~10_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[4]~10_combout & (!\z80_|execute_|ctl_reg_in_hi~15_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~60_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & \z80_|reg_file_|gdfx_temp1[4]~61_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout & \z80_|reg_file_|gdfx_temp1[4]~58_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[4]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~19_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [4] & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[4]~66_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = (\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [12]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'h96AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~19_combout = ((\z80_|reg_file_|db_hi_as[4]~18_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~19 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~19_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[4]~19_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout = \z80_|address_latch_|Q [12] $ ((((\z80_|execute_|ctl_inc_dec~11_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~8_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .lut_mask = 16'h02FD; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~16_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N5 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout = \z80_|address_latch_|Q [11] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # ((\z80_|execute_|ctl_inc_dec~11_combout ) # (!\z80_|execute_|ctl_inc_dec~8_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|execute_|ctl_inc_dec~8_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .lut_mask = 16'h1E0F; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [5] & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[5]~57_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = (\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~16_combout = ((\z80_|reg_file_|db_hi_as[5]~15_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~16 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~52_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~53_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout ) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout & \z80_|reg_file_|gdfx_temp1[5]~50_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~16_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[5]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// (((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|alu_control_|db[5]~12_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[5]~23_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[1]~14_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[5]~24_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~16_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[1]~16_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[1]~17_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~19_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N5 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA280; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h5051; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|pla_decode_|Equal71~2_combout ) # ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) # +// (!\z80_|execute_|ctl_alu_core_S~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal71~2_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|execute_|ctl_alu_core_R~5_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'h45C7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .lut_mask = 16'hFF88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N27 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'hC088; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_low[2]~11_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[2]~11_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N11 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( +// Equation(s): +// \z80_|alu_|db_low[2]~6_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & (((\z80_|alu_|op2_low [2])) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~7 ( +// Equation(s): +// \z80_|alu_|db_low[2]~7_combout = (\z80_|alu_|db_low[2]~6_combout & (((!\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_low[2]~6_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~7 .lut_mask = 16'h4C0C; +defparam \z80_|alu_|db_low[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~8 ( +// Equation(s): +// \z80_|alu_|db_low[2]~8_combout = (\z80_|alu_|db_low[2]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(gnd), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~8 .lut_mask = 16'hFA00; +defparam \z80_|alu_|db_low[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~16_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hD8D8; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|gdfx_temp1[2]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = (\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~13_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N9 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (\z80_|address_latch_|Q [7] & !\z80_|execute_|ctl_inc_dec~10_combout +// )) # (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [7] & \z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1080; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~13_combout = ((\z80_|reg_file_|db_hi_as[2]~12_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~13 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_hi_as[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~43_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~44_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout & (\z80_|reg_file_|gdfx_temp1[2]~41_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & \z80_|reg_file_|gdfx_temp1[2]~46_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[2]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~13_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[2]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~28_combout & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~11_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[2]~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB3BB; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[2]~9_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|alu_|db_low[2]~9_combout ), + .datac(gnd), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hDD88; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = ((\z80_|alu_|db_low[2]~8_combout & ((\z80_|alu_|db_low[2]~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~8_combout ), + .datad(\z80_|alu_|db_low[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hF373; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[2]~13_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_low~combout & (((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & \z80_|alu_|db_low[2]~11_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|alu_|db_low[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y11_N27 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|alu_|op1_high [0]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEEE; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~12_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~18_combout )))) # (!\z80_|alu_control_|db[5]~12_combout +// & (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~18_combout )))) + + .dataa(\z80_|alu_control_|db[5]~12_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~8 ( +// Equation(s): +// \z80_|alu_control_|db[5]~8_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|flags_yf~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|flags_yf~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~8 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[5]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[5]~0_combout = (\z80_|reg_file_|gdfx_temp0[5]~53_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[5]~0 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~9 ( +// Equation(s): +// \z80_|alu_control_|db[5]~9_combout = (\z80_|alu_control_|db[5]~8_combout & (\z80_|reg_file_|db_lo_ds[5]~0_combout & ((\z80_|bus_control_|db[5]~16_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|alu_control_|db[5]~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[5]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~9 .lut_mask = 16'hD000; +defparam \z80_|alu_control_|db[5]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~12 ( +// Equation(s): +// \z80_|alu_control_|db[5]~12_combout = ((\z80_|alu_control_|db[5]~9_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[5]~9_combout ), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~12 .lut_mask = 16'hBB3B; +defparam \z80_|alu_control_|db[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~47_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~12_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~48_combout = (\z80_|reg_file_|gdfx_temp0[5]~47_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[5]~47_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[5]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~51_combout = (\z80_|reg_file_|gdfx_temp0[5]~49_combout & (\z80_|reg_file_|gdfx_temp0[5]~48_combout & (\z80_|reg_file_|gdfx_temp0[5]~50_combout & \z80_|reg_file_|gdfx_temp0[5]~46_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~48_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~50_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~52_combout = (\z80_|reg_file_|gdfx_temp0[5]~44_combout & (\z80_|reg_file_|gdfx_temp0[5]~51_combout & \z80_|reg_file_|gdfx_temp0[5]~45_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~51_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~45_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~53_combout = ((\z80_|reg_file_|gdfx_temp0[5]~52_combout & ((\z80_|reg_file_|db_lo_as[5]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~52_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|gdfx_temp0[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~10_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[5]~53_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~53_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~11_combout = (\z80_|reg_file_|db_lo_as[5]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|db_lo_as[5]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~11 .lut_mask = 16'hC0F0; +defparam \z80_|reg_file_|db_lo_as[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~12_combout = ((\z80_|reg_file_|db_lo_as[5]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~12 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~23_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h6555; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y8_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y9_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[6]~18_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y10_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~26_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N1 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[6]~82_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF050; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h3393; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h6AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N9 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & +// ((\z80_|address_latch_|Q [6] $ (\z80_|execute_|ctl_inc_dec~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0DD0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (((\z80_|reg_file_|b2v_latch_de_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[7]~15_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y9_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y8_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y8_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y8_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y9_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~89_combout & (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~8_combout & (\z80_|reg_file_|gdfx_temp0[7]~92_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~8_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [7]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [7]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h9A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~7_combout = ((\z80_|reg_file_|db_hi_as[0]~6_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~7 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout = (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de2_hi|db[0]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y7_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [0] & ((\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[0]~18_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datac(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'hD000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~7_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datac(\z80_|alu_control_|db[0]~25_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[0]~23_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( +// Equation(s): +// \z80_|alu_|db_low[1]~13_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[1]~12_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[1]~16_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[1]~12_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hBBF3; +defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = ((\z80_|alu_|db_low[1]~13_combout & \z80_|alu_|db_low[1]~16_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[1]~13_combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hAF0F; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[1]~15_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hC4FF; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [5] & ((\z80_|alu_|db[0]~18_combout ))))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout +// & (!\z80_|ir_|opcode [5]))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'h8E82; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'h08A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~3 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~3_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout & !\z80_|ir_|opcode [4])) + + .dataa(gnd), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .lut_mask = 16'hFF0C; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( +// Equation(s): +// \z80_|alu_|db_low[0]~18_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( +// Equation(s): +// \z80_|alu_|db_low[0]~19_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_low[0]~18_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[0]~18_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db_low[0]~18_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hAFCF; +defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h396C; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & !\z80_|execute_|ctl_alu_core_S~combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h555F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_|alu_op2[0]~3_combout )))) +// # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|alu_op2[0]~3_combout )))) + + .dataa(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datab(\z80_|alu_|alu_op1[0]~1_combout ), + .datac(\z80_|alu_|alu_op2[0]~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hFE80; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y13_N9 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( +// Equation(s): +// \z80_|alu_|db_low[0]~20_combout = ((!\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|alu_|op1_low [0] & (((\z80_|alu_|op2_low [0])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [0] & (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = (\z80_|alu_|db_low[0]~20_combout & (\z80_|alu_|db_low[0]~21_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|result_lo [0]), + .datac(\z80_|alu_|db_low[0]~20_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hE000; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((\z80_|alu_|db_low[0]~19_combout & \z80_|alu_|db_low[0]~22_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[0]~19_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_low[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hCF0F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|alu_|db_low[0]~23_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N27 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db_high[0]~20_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db[4]~10_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[0]~20_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hF7B3; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|bus_control_|db[5]~16_combout & (!\z80_|bus_control_|db[3]~20_combout & !\z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'h0022; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~22_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[0]~22_combout ), + .datab(\z80_|alu_|db_high[0]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hA8FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|alu_control_|db[4]~31_combout & ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~5_combout )))) # (!\z80_|alu_control_|db[4]~31_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[4]~66_combout ) # (!\z80_|execute_|ctl_reg_out_hi~5_combout )))) + + .dataa(\z80_|alu_control_|db[4]~31_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~15_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db[4]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~0 ( +// Equation(s): +// \z80_|alu_|db_low[3]~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~0 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_low[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~1 ( +// Equation(s): +// \z80_|alu_|db_low[3]~1_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_low[3]~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|alu_|db_low[3]~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~1 .lut_mask = 16'hF5DD; +defparam \z80_|alu_|db_low[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|alu_|db_low[3]~4_combout & \z80_|alu_|db_low[3]~1_combout )) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[3]~4_combout ), + .datad(\z80_|alu_|db_low[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hF333; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[3]~5_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|alu_|db_high[3]~7_combout & (\z80_|alu_|db_low[3]~5_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_low[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N25 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h27D8; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [3]))))) # +// (!\z80_|execute_|ctl_alu_op_low~16_combout & (\z80_|alu_|op1_low [3])) + + .dataa(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hCCE4; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFC0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0027; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF3F2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~31_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~31_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFCB8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N29 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~19 ( +// Equation(s): +// \z80_|alu_control_|db[2]~19_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~19 .lut_mask = 16'hFFEF; +defparam \z80_|alu_control_|db[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~26 ( +// Equation(s): +// \z80_|alu_control_|db[2]~26_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~26 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~5_combout = (\z80_|reg_file_|gdfx_temp0[2]~43_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~43_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~5 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_control_|db[2]~26_combout & (\z80_|reg_file_|db_lo_ds[2]~5_combout & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[2]~26_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = ((\z80_|alu_control_|db[2]~27_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [2]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[2]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~8_combout & (((\z80_|alu_control_|db[2]~28_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|execute_|ctl_flags_pf_we~8_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|db[2]~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hE444; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~8_combout & (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~9_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h0770; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~13_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & (!\z80_|pla_decode_|Equal62~3_combout & \z80_|execute_|ctl_pf_sel[0]~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h0CFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [7] & !\z80_|address_latch_|Q [6]))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [7]), + .datad(\z80_|address_latch_|Q [6]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (!\z80_|address_latch_|Q [2] & (\z80_|address_latch_|Q [0] & !\z80_|address_latch_|Q [3]))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0010; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [10] & !\z80_|address_latch_|Q [9]))) + + .dataa(\z80_|address_latch_|Q [8]), + .datab(\z80_|address_latch_|Q [11]), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|Q [9]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [14] & !\z80_|address_latch_|Q [12]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~7_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~7_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE4F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80A2; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h80B0; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|alu_control_|DFFE_latch_pf_tmp~q ) # (\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|alu_|alu_parity_out~0_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h555A; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~9_combout & (\z80_|execute_|ctl_pf_sel[0]~8_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~9_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datac(\z80_|alu_|alu_parity_out~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_pf_we~8_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hEAAA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h7F00; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hFCFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[1]~19_combout & !\z80_|alu_|db_high[2]~13_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|alu_|db_high[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~18_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hCC00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~5_combout & (!\z80_|alu_|db_low[2]~11_combout & (!\z80_|alu_|db_low[1]~17_combout & !\z80_|alu_|db_low[0]~23_combout ))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|alu_|db_low[2]~11_combout ), + .datac(\z80_|alu_|db_low[1]~17_combout ), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .lut_mask = 16'hF8F0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hDF00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~2_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & (((\z80_|alu_control_|sel[1]~0_combout ) # (\z80_|alu_flags_|flags_cf~combout )))) # (!\z80_|ir_|opcode [4] & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// (!\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hAEA4; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~28_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~27_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|pla_decode_|Equal5~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~27_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = (\z80_|execute_|ctl_reg_sel_wz~16_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_al_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~12_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h3FBF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~19_combout )) # (!\z80_|execute_|ctl_mWrite~10_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~20_combout = (((\z80_|execute_|ixy_d~3_combout & !\z80_|execute_|ctl_bus_inc_oe~19_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~19_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~19_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5DFF; +defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~23_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~3_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_al_we~3_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~23 .lut_mask = 16'h4404; +defparam \z80_|execute_|ctl_reg_sel_pc~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~6_combout & ((!\z80_|execute_|ctl_reg_sel_pc~16_combout ) # (!\z80_|execute_|setM1~39_combout )))) + + .dataa(\z80_|execute_|setM1~39_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hCCDF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~21_combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # (\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~15_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~21 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_sel_pc~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~28_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_reg_sel_pc~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~28_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~21_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [1] & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # ((!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~2_combout = (\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datad(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~2 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~4_combout = ((\z80_|reg_file_|db_hi_as[1]~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[1]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~4 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_hi_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~10_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~10_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~10_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~10_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ ((((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~23_combout ))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_bus_inc_oe~23_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [14]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = (\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'h8A8A; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = ((\z80_|reg_file_|db_hi_as[6]~21_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~3_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y9_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y7_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # (!\z80_|reg_file_|b2v_latch_de_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y10_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y7_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~15_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~15_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y7_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y7_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~71_combout & \z80_|reg_file_|gdfx_temp1[6]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|gdfx_temp1[6]~68_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[6]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~22_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hBF33; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~75_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~5_combout & +// (((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datac(\z80_|alu_control_|db[6]~18_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~15_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[6]~21_combout ), + .datad(\z80_|execute_|ctl_alu_oe~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hB3F3; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hACAC; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|alu_|op2_high [2] & (((\z80_|alu_|op1_high [2]) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) # (!\z80_|alu_|op2_high [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [2]) # +// (!\z80_|execute_|ctl_alu_op1_oe~2_combout )))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~11_combout & (((\z80_|bus_control_|db[5]~16_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|alu_|db_high[2]~11_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'h8C0C; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|execute_|ctl_alu_res_oe~2_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hFFF8; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~12_combout & \z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~12_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hD555; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~11_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[2]~11_combout ))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y12_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0415; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hF0FB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # +// (\z80_|alu_|alu_op1[3]~2_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op2[3]~2_combout & \z80_|alu_|alu_op1[3]~2_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFD40; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|execute_|ctl_alu_op1_oe~2_combout & (\z80_|alu_|op1_high [3] & ((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~2_combout & ((\z80_|alu_|op2_high [3]) +// # ((!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~2_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[5]~16_combout & (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout )) + + .dataa(\z80_|bus_control_|db[5]~16_combout ), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~45_combout ) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hEF2F; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[3]~5_combout ), + .datad(\z80_|alu_|db_high[3]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[3]~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFD55; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_control_|db[7]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|execute_|ctl_flags_alu~18_combout & \z80_|alu_|db_high[3]~7_combout )))) # (!\z80_|alu_control_|db[7]~15_combout & +// (\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_control_|db[7]~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y13_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~13 ( +// Equation(s): +// \z80_|alu_control_|db[7]~13_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~13 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[7]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[7]~1_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_out_lo~3_combout & !\z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[7]~1 .lut_mask = 16'hFF08; +defparam \z80_|reg_file_|db_lo_ds[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~14 ( +// Equation(s): +// \z80_|alu_control_|db[7]~14_combout = (\z80_|alu_control_|db[7]~13_combout & (\z80_|reg_file_|db_lo_ds[7]~1_combout & ((\z80_|alu_|db[7]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_control_|db[7]~13_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|reg_file_|db_lo_ds[7]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~14 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~15 ( +// Equation(s): +// \z80_|alu_control_|db[7]~15_combout = ((\z80_|alu_control_|db[7]~14_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [1]), + .datab(\z80_|alu_control_|db[6]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[7]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~15 .lut_mask = 16'hBF33; +defparam \z80_|alu_control_|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~4 ( +// Equation(s): +// \z80_|bus_control_|db[7]~4_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[7]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[7]~15_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~4 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~2_combout & \z80_|execute_|ctl_mRead~11_combout ))) # (!\z80_|execute_|fMRead~27_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~27_combout ), + .datac(\z80_|execute_|ixy_d~2_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( // Equation(s): -// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|fMRead~36_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~12_combout )))) - .dataa(\z80_|execute_|fMRead~35_combout ), - .datab(\z80_|execute_|fMRead~34_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'h0A08; defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N30 +// Location: LCCOMB_X36_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~16 ( +// Equation(s): +// \z80_|execute_|nextM~16_combout = (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|execute_|ctl_mRead~3_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|nextM~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|nextM~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ixy_d~4_combout & (((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ixy_d~4_combout & (\z80_|execute_|ixy_d~3_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|execute_|ixy_d~3_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~20_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~20 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_ir_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_ir_we~20_combout & (((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) # (!\z80_|execute_|ctl_ir_we~20_combout & (\z80_|execute_|ctl_ir_we~19_combout & ((\z80_|ir_|opcode [7])))) + + .dataa(\z80_|execute_|ctl_ir_we~19_combout ), + .datab(\z80_|execute_|ctl_ir_we~20_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~38 ( +// Equation(s): +// \z80_|execute_|fMRead~38_combout = (\z80_|execute_|fMRead~29_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|fMRead~30_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|fMRead~29_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~38 .lut_mask = 16'hECCC; +defparam \z80_|execute_|fMRead~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = ((\z80_|execute_|fMRead~37_combout ) # ((\z80_|execute_|fMRead~38_combout ) # (!\z80_|execute_|nextM~16_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~37_combout ), + .datac(\z80_|execute_|nextM~16_combout ), + .datad(\z80_|execute_|fMRead~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~36_combout ) # (\z80_|execute_|fMRead~31_combout ))) # (!\z80_|execute_|fMRead~8_combout ) + + .dataa(\z80_|execute_|fMRead~8_combout ), + .datab(\z80_|execute_|fMRead~28_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|fMRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~4_combout )) # (!\z80_|execute_|fMRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0FAF; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (!\z80_|execute_|fMWrite~0_combout & ((\z80_|execute_|ctl_ir_we~15_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|fMRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|ctl_bus_db_oe~3_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ixy_d~16_combout )) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|fMRead~12_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|fMRead~13_combout ))) + + .dataa(\z80_|execute_|fMRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|fMRead~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~16_combout ) # ((\z80_|execute_|fMRead~14_combout ) # ((\z80_|execute_|fMRead~17_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|fMRead~18_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~31_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) # (!\z80_|execute_|fMRead~22_combout ) + + .dataa(\z80_|execute_|fMRead~22_combout ), + .datab(\z80_|execute_|fMRead~18_combout ), + .datac(\z80_|execute_|ctl_sw_4d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_alu_oe~4_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (\z80_|execute_|ctl_mRead~15_combout & +// ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|execute_|ctl_alu_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|fMRead~25_combout ) # (((!\z80_|execute_|pc_inc_hold~17_combout & \z80_|execute_|ixy_d~3_combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|fMRead~25_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~26_combout ))) + + .dataa(\z80_|execute_|fMRead~32_combout ), + .datab(\z80_|execute_|fMRead~24_combout ), + .datac(\z80_|execute_|fMRead~23_combout ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|pla_decode_|Equal52~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & \z80_|execute_|setM1~39_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (((\z80_|execute_|ctl_ir_we~16_combout ) # (\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|fMWrite~2_combout ) + + .dataa(\z80_|execute_|fMWrite~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datac(\z80_|execute_|ctl_ir_we~16_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~23_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|ctl_reg_sys_hilo~6_combout ))) + + .dataa(\z80_|execute_|fMRead~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~23_combout ), + .datac(\z80_|execute_|fMRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~35_combout )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), .combout(\z80_|pin_control_|bus_db_pin_re~combout ), @@ -44338,1712 +39032,1971 @@ defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F33; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( +// Location: LCCOMB_X34_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ixy_d~3_combout ), + .datad(\z80_|execute_|fIOWrite~3_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo~6_combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( +// Location: LCCOMB_X34_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~2_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|execute_|ixy_d~2_combout ), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hF500; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) +// \z80_|execute_|ctl_iorw~12_combout = ((\z80_|ir_|opcode [7]) # ((!\z80_|ir_|opcode [6]) # (!\z80_|decode_state_|DFFE_instED~q ))) # (!\z80_|pla_decode_|Equal1~0_combout ) - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|pla_decode_|Equal1~0_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .combout(\z80_|execute_|ctl_iorw~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~2_combout ) # ((!\z80_|execute_|ctl_iorw~12_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (!\z80_|execute_|ctl_iorw~12_combout & ((\z80_|execute_|ctl_eval_cond~0_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .combout(\z80_|execute_|ctl_iorw~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y10_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( // Equation(s): -// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~16_combout ) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .dataa(\z80_|execute_|nextM~16_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|execute_|ctl_iorw~8_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .combout(\z80_|execute_|ctl_iorw~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; -defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; -defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[4][3] ( +// Location: FF_X30_Y18_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N12 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\ula_|zx_keyboard_|keys[5][3]~q ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[4][3]~q ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hA2F3; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & -// !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; -defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; -defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & -// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N23 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y7_N25 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N20 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[3][3]~q ), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'h8ACF; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; -defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & -// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[7][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; -defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; -defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & -// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N5 -dffeas \ula_|zx_keyboard_|keys[6][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N30 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hCF45; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; -defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & -// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N3 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N5 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N8 -cycloneive_lcell_comb \D[3]~72 ( -// Equation(s): -// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][3]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][3]~q ), - .cin(gnd), - .combout(\D[3]~72_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'hA2F3; -defparam \D[3]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N10 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) - - .dataa(\D[3]~74_combout ), - .datab(\D[3]~73_combout ), - .datac(\D[3]~75_combout ), - .datad(\D[3]~72_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'h8000; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N2 -cycloneive_lcell_comb \D[3]~122 ( -// Equation(s): -// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) - - .dataa(\D[3]~76_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[3]~122_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~122 .lut_mask = 16'hEF00; -defparam \D[3]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N28 -cycloneive_lcell_comb \D[3]~79 ( -// Equation(s): -// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\Equal2~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~79 .lut_mask = 16'h3332; -defparam \D[3]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N20 -cycloneive_lcell_comb \D[3]~77 ( -// Equation(s): -// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # -// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\D[3]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~77 .lut_mask = 16'hF5E4; -defparam \D[3]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N22 -cycloneive_lcell_comb \D[3]~80 ( -// Equation(s): -// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) - - .dataa(gnd), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~80 .lut_mask = 16'hCFC0; -defparam \D[3]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N4 -cycloneive_lcell_comb \D[3]~81 ( -// Equation(s): -// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout -// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datac(\D[3]~80_combout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~81 .lut_mask = 16'hF0DD; -defparam \D[3]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N30 -cycloneive_lcell_comb \D[3]~124 ( -// Equation(s): -// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~77_combout ), - .cin(gnd), - .combout(\D[3]~124_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~124 .lut_mask = 16'hF200; -defparam \D[3]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~109_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N0 -cycloneive_lcell_comb \D[3]~123 ( -// Equation(s): -// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & -// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~123_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~123 .lut_mask = 16'hF2D0; -defparam \D[3]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N10 -cycloneive_lcell_comb \D[3]~78 ( -// Equation(s): -// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - - .dataa(\Equal2~0_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[3]~124_combout ), - .datad(\D[3]~123_combout ), - .cin(gnd), - .combout(\D[3]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~78 .lut_mask = 16'h5410; -defparam \D[3]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N6 -cycloneive_lcell_comb \D[3]~82 ( -// Equation(s): -// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[3]~79_combout ), - .datac(\D[3]~81_combout ), - .datad(\D[3]~78_combout ), - .cin(gnd), - .combout(\D[3]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~82 .lut_mask = 16'hD580; -defparam \D[3]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N26 -cycloneive_lcell_comb \D[3]~108 ( -// Equation(s): -// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[3]~122_combout ), - .datac(gnd), - .datad(\D[3]~82_combout ), - .cin(gnd), - .combout(\D[3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hFFDD; -defparam \D[3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N8 -cycloneive_lcell_comb \D[3]~109 ( -// Equation(s): -// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(\D[3]~108_combout ), - .datad(\Equal2~1_combout ), - .cin(gnd), - .combout(\D[3]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~109 .lut_mask = 16'hD0D5; -defparam \D[3]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[3]~109_combout ), - .datac(\z80_|bus_control_|db[3]~21_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N5 -dffeas \z80_|data_pins_|dout[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( -// Equation(s): -// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( -// Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|alu_control_|db[3]~36_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[3]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|ir_|opcode[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|execute_|ctl_iorw~9_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y8_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|bus_control_|db[0]~4_combout ), - .datab(\z80_|alu_control_|db[7]~37_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X30_Y18_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y1_N0 +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N27 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y18_N15 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(\z80_|memory_ifc_|wait_iorq~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (!\z80_|execute_|ctl_mWrite~20_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~20_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_mWrite~13_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~13_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~18_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout & (\z80_|execute_|ctl_mWrite~14_combout & (\z80_|execute_|ctl_mWrite~12_combout & \z80_|execute_|ctl_bus_db_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = (!\z80_|execute_|ixy_d~8_combout & !\z80_|pla_decode_|Equal33~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h0303; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = ((\z80_|execute_|ctl_mWrite~16_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~15_combout ))) # (!\z80_|execute_|ctl_mWrite~15_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mWrite~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'hFF5D; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y15_N21 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N3 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(gnd), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|mwr_wr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hFFA0; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFF0; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # ((\z80_|sequencer_|M5~q )))) # (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # +// (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_mWrite~8_combout & !\z80_|execute_|ctl_mRead~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0055; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~0_combout ) # ((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|fMWrite~1_combout )))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h2322; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_bus_inc_oe~14_combout & (\z80_|pin_control_|bus_db_pin_oe~3_combout & ((\z80_|execute_|fMWrite~2_combout ) # (!\z80_|execute_|fMWrite~3_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~14_combout ), + .datab(\z80_|execute_|fMWrite~3_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hA200; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_reg_in_hi~6_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((\z80_|execute_|ixy_d~2_combout ) # ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ixy_d~2_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h8CCC; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_alu_oe~4_combout ) # ((\z80_|execute_|ctl_reg_in_hi~6_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|pla_decode_|Equal9~1_combout & +// ((\z80_|execute_|ctl_alu_oe~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (\z80_|execute_|ctl_mWrite~19_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|pla_decode_|Equal3~2_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~19_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ixy_d~4_combout )) # (!\z80_|execute_|fMWrite~4_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|execute_|ctl_inc_dec~2_combout ), + .datad(\z80_|execute_|fMWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h10F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout & +// (((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h070F; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout & \z80_|execute_|fMRead~6_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ctl_mRead~5_combout )) # +// (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|fMRead~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h1F13; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fIOWrite~0_combout ) # ((!\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|execute_|fMWrite~5_combout & (\z80_|execute_|fMWrite~6_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'hC8FA; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~9_combout & (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~11_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_bus_inc_oe~18_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~12_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~18_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~13_combout & ((!\z80_|execute_|ixy_d~4_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h40C0; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|execute_|ctl_inc_cy~31_combout & (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~31_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # +// (!\z80_|execute_|fIOWrite~5_combout & (((\z80_|pin_control_|bus_db_pin_oe~2_combout & !\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h88F8; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \D[0]~49 ( +// Equation(s): +// \D[0]~49_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~49 .lut_mask = 16'hFF40; +defparam \D[0]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N15 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|DFF_inst5~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N17 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y12_N17 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(\z80_|memory_ifc_|iorq~0_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \Equal5~0 ( +// Equation(s): +// \Equal5~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~0 .lut_mask = 16'h0080; +defparam \Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~18_combout )) # (!\z80_|execute_|ctl_inc_dec~8_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|address_latch_|abusz [1]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h00DD; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~35_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout ) # +// ((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h44F4; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N10 +cycloneive_lcell_comb \Equal3~0 ( +// Equation(s): +// \Equal3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((!\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|address_pins_|DFFE_apin_latch [1])) # (!\z80_|address_pins_|DFFE_apin_latch [0]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~0 .lut_mask = 16'h2AAA; +defparam \Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [6]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[6]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~26 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[7]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [5]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N16 +cycloneive_lcell_comb \Equal3~1 ( +// Equation(s): +// \Equal3~1_combout = (((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\z80_|address_pins_|DFFE_apin_latch [4])) # (!\z80_|address_pins_|DFFE_apin_latch [3]) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~1 .lut_mask = 16'hF7FF; +defparam \Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N0 +cycloneive_lcell_comb \Equal3~2 ( +// Equation(s): +// \Equal3~2_combout = (\Equal3~0_combout ) # ((\z80_|address_pins_|abus[6]~25_combout ) # ((\z80_|address_pins_|abus[7]~26_combout ) # (\Equal3~1_combout ))) + + .dataa(\Equal3~0_combout ), + .datab(\z80_|address_pins_|abus[6]~25_combout ), + .datac(\z80_|address_pins_|abus[7]~26_combout ), + .datad(\Equal3~1_combout ), + .cin(gnd), + .combout(\Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal3~2 .lut_mask = 16'hFFFE; +defparam \Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \D[5]~26 ( +// Equation(s): +// \D[5]~26_combout = (\Equal5~1_combout & ((!\Equal3~2_combout ) # (!\Equal5~0_combout ))) + + .dataa(\Equal5~1_combout ), + .datab(gnd), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\D[5]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~26 .lut_mask = 16'h0AAA; +defparam \D[5]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [15])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [15]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [15]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N3 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~23 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[15]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hF3F3; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h1000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~24 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~27 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~28 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~29 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[3]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N18 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [4]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~30 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[5]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~17 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[8]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~16 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|address_latch_|abusz [10]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[10]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [11]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~18 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -46059,10 +41012,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46100,7 +41053,170 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: FF_X21_Y15_N25 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N23 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0088; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h0C00; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -46116,10 +41232,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46157,7 +41273,96 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y16_N0 +// Location: LCCOMB_X29_Y12_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[13]~20_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[14]~22_combout & \z80_|address_pins_|abus[15]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0400; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [13]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -46173,10 +41378,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -46214,10 +41419,10 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # // (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) @@ -46226,52 +41431,776 @@ cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .lut_mask = 16'hBBC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N2 -cycloneive_lcell_comb \D[5]~97 ( +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X31_Y22_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( // Equation(s): -// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\D[5]~97_combout ), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[5]~97 .lut_mask = 16'h2000; -defparam \D[5]~97 .sum_lutc_input = "datac"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), +// Location: FF_X31_Y22_N13 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y15_N29 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (!\z80_|address_pins_|abus[15]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[13]~20_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0400; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N29 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y31_N11 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h00FF; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N27 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [7] $ (\ula_|video_|vga_hc [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N17 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [7]))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h9933; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N19 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] $ (VCC))) # (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [0] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0])) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N1 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y31_N5 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add4~10_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) + + .dataa(\ula_|video_|Add4~12_combout ), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hAAF0; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N0 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N19 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N14 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0060; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & ((\ula_|video_|Add4~4_combout )))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vram_address[10]~2_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|Add4~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hB830; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y31_N25 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|Add4~12_combout ), + .datad(\ula_|video_|vga_hc [2]), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFAA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N31 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -46279,16 +42208,181 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hD9C8; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[7]~48_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -46342,283 +42436,111 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~117_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N6 -cycloneive_lcell_comb \Mux0~0 ( +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \Selector0~1 ( // Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) +// \Selector0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector0~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # (!\Selector0~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector0~0_combout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\Selector0~0_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), .cin(gnd), - .combout(\Mux0~0_combout ), + .combout(\Selector0~1_combout ), .cout()); // synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hB9A8; -defparam \Mux0~0 .sum_lutc_input = "datac"; +defparam \Selector0~1 .lut_mask = 16'hF838; +defparam \Selector0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N4 -cycloneive_lcell_comb \Mux0~1 ( +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \D[7]~36 ( // Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) +// \D[7]~36_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector0~1_combout ))))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13_combout ), + .datad(\Selector0~1_combout ), .cin(gnd), - .combout(\Mux0~1_combout ), + .combout(\D[7]~36_combout ), .cout()); // synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hDDA0; -defparam \Mux0~1 .sum_lutc_input = "datac"; +defparam \D[7]~36 .lut_mask = 16'h5140; +defparam \D[7]~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N20 -cycloneive_lcell_comb \D[7]~116 ( +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \D[7]~37 ( // Equation(s): -// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) +// \D[7]~37_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~36_combout ) # (!\D[5]~26_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~36_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datab(\D[5]~97_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~116_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~116 .lut_mask = 16'hBFB3; -defparam \D[7]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N26 -cycloneive_lcell_comb \D[7]~117 ( -// Equation(s): -// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), + .dataa(\z80_|data_pins_|dout [7]), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [7]), - .datad(\D[7]~116_combout ), + .datac(\D[5]~26_combout ), + .datad(\D[7]~36_combout ), .cin(gnd), - .combout(\D[7]~117_combout ), + .combout(\D[7]~37_combout ), .cout()); // synopsys translate_off -defparam \D[7]~117 .lut_mask = 16'hF311; -defparam \D[7]~117 .sum_lutc_input = "datac"; +defparam \D[7]~37 .lut_mask = 16'hBB0B; +defparam \D[7]~37 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N0 +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \D[7]~48 ( +// Equation(s): +// \D[7]~48_combout = (\D[7]~37_combout ) # (!\D[0]~49_combout ) + + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), + .cin(gnd), + .combout(\D[7]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~48 .lut_mask = 16'hFF33; +defparam \D[7]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~6_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~48_combout )))) # (!\z80_|bus_control_|db[7]~6_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[7]~48_combout )))) - .dataa(\z80_|bus_control_|db[7]~7_combout ), + .dataa(\z80_|bus_control_|db[7]~6_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[7]~117_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[7]~48_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N1 +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFF8; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 dffeas \z80_|data_pins_|dout[7] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), @@ -46637,33 +42559,33 @@ defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~6 ( // Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[7]~6_combout = ((\z80_|bus_control_|db[7]~4_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[7]~5_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[7]~4_combout ), .datad(\z80_|data_pins_|dout [7]), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), + .combout(\z80_|bus_control_|db[7]~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[7]~6 .lut_mask = 16'hF575; +defparam \z80_|bus_control_|db[7]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N13 +// Location: FF_X29_Y17_N3 dffeas \z80_|ir_|opcode[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|bus_control_|db[7]~6_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [7]), @@ -46673,93 +42595,3266 @@ defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) +// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|decode_state_|DFFE_instED~q & \z80_|ir_|opcode [6])) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~9_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~0_combout & (\z80_|execute_|ctl_mWrite~7_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((!\z80_|execute_|fIOWrite~0_combout & \z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC800; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|fIORead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|ctl_mRead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~6_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~5_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal29~0_combout & (!\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0500; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~59 ( +// Equation(s): +// \z80_|execute_|setM1~59_combout = (!\z80_|execute_|ctl_mRead~11_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~59 .lut_mask = 16'h3233; +defparam \z80_|execute_|setM1~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & (\z80_|execute_|setM1~39_combout & (!\z80_|execute_|ctl_mRead~13_combout & \z80_|execute_|setM1~59_combout ))) + + .dataa(\z80_|execute_|setM1~40_combout ), + .datab(\z80_|execute_|setM1~39_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|setM1~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0800; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & ((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'h1030; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (!\z80_|execute_|ctl_reg_gp_sel~13_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~13_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal38~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|ctl_mRead~25_combout & (\z80_|execute_|ctl_mRead~22_combout & \z80_|execute_|ctl_mRead~26_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_mRead~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFFC0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~29_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (!\z80_|execute_|ctl_mRead~27_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~29_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|ctl_mRead~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y17_N21 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: FF_X32_Y15_N9 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N27 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \Equal5~1 ( +// Equation(s): +// \Equal5~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal5~1 .lut_mask = 16'h0808; +defparam \Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~13_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \Selector10~0 ( +// Equation(s): +// \Selector10~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~0 .lut_mask = 16'hD9C8; +defparam \Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \Selector10~1 ( +// Equation(s): +// \Selector10~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector10~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\Selector10~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector10~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\Selector10~0_combout ), + .cin(gnd), + .combout(\Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~1 .lut_mask = 16'hBBC0; +defparam \Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N29 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y29_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|clk_filter [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N17 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [6]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [1] & (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [1]), + .datab(\ula_|ps2_keyboard_|clk_filter [3]), + .datac(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0010; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h00FF; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N27 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y29_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y29_N1 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y21_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N29 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N30 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y20_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y21_N11 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y20_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y21_N8 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y21_N9 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|Equal0~1_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hC4C4; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y20_N25 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF850; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N21 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~52_combout = (\ula_|zx_keyboard_|keys[3][2]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~52 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~52_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~51_combout & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~54_combout = (\ula_|zx_keyboard_|keys[2][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~53_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~54 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N17 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~54_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~5 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~5_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~5 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~48_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~48 .lut_mask = 16'h0303; +defparam \ula_|zx_keyboard_|keys[0][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~50_combout = (\ula_|zx_keyboard_|keys[0][2]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[0][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[0][2]~48_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~48_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~46_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~46 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h0088; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[3][3]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N21 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~4_combout = (\ula_|zx_keyboard_|keys[0][2]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\ula_|zx_keyboard_|keys[0][2]~q & +// (((\z80_|address_pins_|abus[9]~16_combout )) # (!\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][2]~q ), + .datab(\ula_|zx_keyboard_|keys[1][2]~q ), + .datac(\z80_|address_pins_|abus[9]~16_combout ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~4 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~60_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h0A0A; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hC888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N23 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hCCFC; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~59_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~59 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[7][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[7][2]~63_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][2]~q ))))) # (!\ula_|zx_keyboard_|keys[7][2]~63_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N23 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~66 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[6][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~66_combout & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[6][2]~66_combout ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~65_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~65 .lut_mask = 16'hFF0C; +defparam \ula_|zx_keyboard_|keys[5][0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|zx_keyboard_|keys[6][2]~67_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|zx_keyboard_|keys[6][2]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N21 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~7 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~7_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~22_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~7 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h00CC; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][2]~30_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|zx_keyboard_|keys[5][2]~55_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~55_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~57_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~57 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~129_combout = (\ula_|zx_keyboard_|keys[4][2]~57_combout & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[4][2]~57_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~129 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[4][2]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~128_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~128 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|zx_keyboard_|keys[4][2]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[4][2]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N7 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2]~6 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[2]~6_combout = (\ula_|zx_keyboard_|keys[5][2]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2]~6 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[2] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [2] = (\ula_|zx_keyboard_|key_row[2]~5_combout & (\ula_|zx_keyboard_|key_row[2]~4_combout & (\ula_|zx_keyboard_|key_row[2]~7_combout & \ula_|zx_keyboard_|key_row[2]~6_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[2]~5_combout ), + .datab(\ula_|zx_keyboard_|key_row[2]~4_combout ), + .datac(\ula_|zx_keyboard_|key_row[2]~7_combout ), + .datad(\ula_|zx_keyboard_|key_row[2]~6_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [2]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[2] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \Selector14~17 ( +// Equation(s): +// \Selector14~17_combout = (\Equal5~0_combout & (((!\z80_|address_pins_|DFFE_apin_latch [0] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\Equal3~2_combout ))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~17_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~17 .lut_mask = 16'h40F0; +defparam \Selector14~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \Selector14~18 ( +// Equation(s): +// \Selector14~18_combout = (\Equal5~0_combout & (((!\Equal3~2_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|DFFE_apin_latch [15]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Equal5~0_combout ), + .datad(\Equal3~2_combout ), + .cin(gnd), + .combout(\Selector14~18_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~18 .lut_mask = 16'h0BFB; +defparam \Selector14~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N22 +cycloneive_io_ibuf \kempston[1]~input ( + .i(kempston[1]), + .ibar(gnd), + .o(\kempston[1]~input_o )); +// synopsys translate_off +defparam \kempston[1]~input .bus_hold = "false"; +defparam \kempston[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \Selector10~2 ( +// Equation(s): +// \Selector10~2_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[1]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [2])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [2]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[1]~input_o ), + .cin(gnd), + .combout(\Selector10~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~2 .lut_mask = 16'h0BCB; +defparam \Selector10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \Selector10~3 ( +// Equation(s): +// \Selector10~3_combout = (\Equal5~0_combout & (((\Selector10~2_combout )))) # (!\Equal5~0_combout & ((\Selector10~2_combout & ((\Selector10~1_combout ))) # (!\Selector10~2_combout & +// (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector10~1_combout ), + .datad(\Selector10~2_combout ), + .cin(gnd), + .combout(\Selector10~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector10~3 .lut_mask = 16'hFC22; +defparam \Selector10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \D[2]~13 ( +// Equation(s): +// \D[2]~13_combout = (\Equal5~1_combout & (\Selector10~3_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & (((\z80_|data_pins_|dout [2])) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout +// ))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Selector10~3_combout ), + .datad(\z80_|data_pins_|dout [2]), + .cin(gnd), + .combout(\D[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~13 .lut_mask = 16'hF531; +defparam \D[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\D[2]~13_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[2]~14_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[2]~13_combout & (\z80_|bus_control_|db[2]~14_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\D[2]~13_combout ), + .datab(\z80_|bus_control_|db[2]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N23 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[2]~28_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|alu_control_|db[2]~28_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF050; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~14 ( +// Equation(s): +// \z80_|bus_control_|db[2]~14_combout = ((\z80_|bus_control_|db[2]~13_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|data_pins_|dout [2]), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|bus_control_|db[0]~5_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~14 .lut_mask = 16'h8FCF; +defparam \z80_|bus_control_|db[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N1 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[2]~14_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hC800; defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N18 +// Location: LCCOMB_X29_Y14_N12 cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), .datad(\z80_|pla_decode_|Equal41~1_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal41~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N8 +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~17_combout = ((\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~17 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_ir_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N27 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[4]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~3_combout = (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~3 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~2_combout = (!\z80_|ir_|opcode [5] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|pla_decode_|Equal2~3_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal2~2_combout ), + .datad(\z80_|pla_decode_|Equal2~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_tbl_cb_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( // Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # -// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_state_tbl_cb_set~2_combout ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal41~2_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .dataa(\z80_|execute_|ctl_state_tbl_cb_set~2_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hBAAA; defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N9 +// Location: FF_X29_Y18_N15 dffeas \z80_|decode_state_|DFFE_instCB ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), @@ -46778,941 +45873,1095 @@ defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y6_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( // Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) - .dataa(\z80_|decode_state_|DFFE_instED~q ), + .dataa(gnd), .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), + .combout(\z80_|decode_state_|table_xx~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( // Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .combout(\z80_|pla_decode_|Equal47~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y12_N29 -dffeas \z80_|interrupts_|im1 ( +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_66_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_1[0] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_1 [0] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|bus_control_|db[6]~8_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .lut_mask = 16'hF0B0; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_1[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~16 ( +// Equation(s): +// \z80_|alu_control_|db[6]~16_combout = (\z80_|alu_control_|out[6]~2_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~16 .lut_mask = 16'hCF8A; +defparam \z80_|alu_control_|db[6]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~2_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~2 .lut_mask = 16'hBAAA; +defparam \z80_|reg_file_|db_lo_ds[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~17 ( +// Equation(s): +// \z80_|alu_control_|db[6]~17_combout = (\z80_|alu_control_|db[6]~16_combout & (\z80_|reg_file_|db_lo_ds[6]~2_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|db[6]~16_combout ), + .datac(\z80_|execute_|ctl_sw_2u~8_combout ), + .datad(\z80_|reg_file_|db_lo_ds[6]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~17 .lut_mask = 16'h8C00; +defparam \z80_|alu_control_|db[6]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~18 ( +// Equation(s): +// \z80_|alu_control_|db[6]~18_combout = ((\z80_|alu_control_|db[6]~17_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_1 [0]), + .datab(\z80_|alu_control_|db[6]~17_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~7 ( +// Equation(s): +// \z80_|bus_control_|db[6]~7_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[6]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(\z80_|alu_control_|db[6]~18_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~7 .lut_mask = 16'h8A8A; +defparam \z80_|bus_control_|db[6]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \D[6]~28 ( +// Equation(s): +// \D[6]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~28 .lut_mask = 16'hFFCF; +defparam \D[6]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \D[6]~43 ( +// Equation(s): +// \D[6]~43_combout = (\Equal5~0_combout & (\Equal3~2_combout & ((\D[6]~28_combout )))) # (!\Equal5~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\Equal5~0_combout ), + .datab(\Equal3~2_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\D[6]~28_combout ), + .cin(gnd), + .combout(\D[6]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~43 .lut_mask = 16'hD850; +defparam \D[6]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \D[6]~44 ( +// Equation(s): +// \D[6]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\Equal5~0_combout & ((\D[6]~43_combout ))) # (!\Equal5~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[6]~43_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\Equal5~0_combout ), + .datad(\D[6]~43_combout ), + .cin(gnd), + .combout(\D[6]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~44 .lut_mask = 16'hFB08; +defparam \D[6]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \D[6]~42 ( +// Equation(s): +// \D[6]~42_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(gnd), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[6]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~42 .lut_mask = 16'hAACC; +defparam \D[6]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \D[6]~45 ( +// Equation(s): +// \D[6]~45_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~44_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Equal5~0_combout & (\D[6]~44_combout )) # (!\Equal5~0_combout & +// ((\D[6]~42_combout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\D[6]~44_combout ), + .datad(\D[6]~42_combout ), + .cin(gnd), + .combout(\D[6]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~45 .lut_mask = 16'hF1E0; +defparam \D[6]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~47_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) # (!\z80_|address_pins_|abus[14]~22_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux1~0 .lut_mask = 16'hDC98; +defparam \Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \D[6]~41 ( +// Equation(s): +// \D[6]~41_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux1~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # (!\Mux1~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux1~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Mux1~0_combout ), + .cin(gnd), + .combout(\D[6]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~41 .lut_mask = 16'hF388; +defparam \D[6]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \D[6]~46 ( +// Equation(s): +// \D[6]~46_combout = (\Equal5~0_combout & (((\D[6]~45_combout )))) # (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\D[6]~45_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\D[6]~41_combout ))))) + + .dataa(\Equal5~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\D[6]~45_combout ), + .datad(\D[6]~41_combout ), + .cin(gnd), + .combout(\D[6]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~46 .lut_mask = 16'hF1E0; +defparam \D[6]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \D[6]~47 ( +// Equation(s): +// \D[6]~47_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~46_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~46_combout ), + .cin(gnd), + .combout(\D[6]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~47 .lut_mask = 16'hAF23; +defparam \D[6]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|bus_control_|db[6]~8_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~47_combout )))) # (!\z80_|bus_control_|db[6]~8_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~47_combout )))) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\D[6]~47_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = ((\z80_|bus_control_|db[6]~7_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[6]~7_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~8_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[6]~8_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N29 +dffeas \z80_|ir_|opcode[6] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .d(\z80_|ir_|opcode[6]~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_im_we~combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), + .q(\z80_|ir_|opcode [6]), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~18 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) +// \z80_|execute_|ctl_ir_we~18_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~9_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|DFFE_inst44~q ), - .datac(\z80_|interrupts_|im1~q ), - .datad(\z80_|interrupts_|im2~q ), + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .combout(\z80_|execute_|ctl_ir_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Location: LCCOMB_X34_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~18_combout & !\z80_|execute_|ctl_ir_we~13_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~18_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_ir_we~13_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hAFBF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~16 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_bus_inc_oe~16_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~35_combout & \z80_|execute_|ctl_bus_inc_oe~15_combout )) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datad(\z80_|decode_state_|in_halt~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X34_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_inc_oe~16_combout & (\z80_|execute_|ctl_mWrite~12_combout & ((!\z80_|execute_|ixy_d~3_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .dataa(\z80_|execute_|ctl_bus_inc_oe~16_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ctl_mWrite~12_combout ), + .datad(\z80_|execute_|ixy_d~3_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Location: LCCOMB_X34_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~10 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) +// \z80_|execute_|ctl_bus_db_we~10_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|execute_|ctl_mWrite~18_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~10 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_bus_db_we~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Location: LCCOMB_X34_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( // Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) +// \z80_|execute_|ctl_bus_db_we~7_combout = (((\z80_|execute_|ctl_bus_db_we~10_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_bus_db_we~6_combout ) - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~10_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_ir_we~8_combout ))) - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Location: LCCOMB_X34_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ctl_ir_we~8_combout & ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Location: LCCOMB_X34_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~9 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|execute_|ctl_bus_db_we~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~9 .lut_mask = 16'h4440; +defparam \z80_|execute_|ctl_bus_db_we~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Location: LCCOMB_X34_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|execute_|ctl_bus_db_we~5_combout ) # ((\z80_|execute_|ctl_bus_db_we~4_combout ) # (\z80_|execute_|ctl_bus_db_we~9_combout ))) - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~9_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout -// )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; -defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N1 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N28 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hD0DD; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; -defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; -defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y7_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N23 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & -// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; -defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & -// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N15 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N2 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[5][0]~q ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'h8ACF; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N23 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; -defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & -// \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; -defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), - .datac(\ula_|zx_keyboard_|keys~69_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; -defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; -defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # -// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|keys~71_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y8_N11 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N15 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N17 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N0 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[3][0]~q ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'h8CAF; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N12 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), - .datab(\z80_|address_pins_|abus[9]~17_combout ), - .datac(\ula_|zx_keyboard_|key_row~2_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hD000; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) - - .dataa(\D[0]~57_combout ), - .datab(\D[0]~56_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[0]~55_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hF8F0; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 +// Location: M9K_X22_Y17_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -47728,10 +46977,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47769,140 +47018,879 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N12 -cycloneive_lcell_comb \D[0]~62 ( +// Location: LCCOMB_X19_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( // Equation(s): -// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\D[0]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), .cout()); // synopsys translate_off -defparam \D[0]~62 .lut_mask = 16'hEC64; -defparam \D[0]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'hFF30; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'h1204; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][1]~34_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|keys[4][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~83_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~82_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|zx_keyboard_|keys[5][0]~79_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h2080; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & ((!\ula_|zx_keyboard_|keys[5][0]~65_combout ))) # (!\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|zx_keyboard_|keys[5][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~65_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N11 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~10_combout = (\ula_|zx_keyboard_|keys[4][0]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) # (!\ula_|zx_keyboard_|keys[4][0]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~10 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~130_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~76_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~130 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & ((\ula_|zx_keyboard_|keys[7][0]~85_combout ) # (\ula_|zx_keyboard_|keys[7][0]~130_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~130_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N17 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~11 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~11_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][0]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~11 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg +// [5] & \ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8180; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~74_combout = (!\ula_|zx_keyboard_|extended~q & ((\ula_|ps2_keyboard_|shiftreg [3]) # ((!\ula_|zx_keyboard_|keys[4][1]~29_combout ) # (!\ula_|zx_keyboard_|WideOr4~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h0B0F; +defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// ((\ula_|ps2_keyboard_|shiftreg [2]))))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0510; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~72_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~45_combout )) # (!\ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~72 .lut_mask = 16'h335F; +defparam \ula_|zx_keyboard_|keys~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~71_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~71 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~73_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~72_combout & \ula_|zx_keyboard_|keys[4][3]~71_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys~72_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~73 .lut_mask = 16'h4C0C; +defparam \ula_|zx_keyboard_|keys[0][0]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys~74_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~74_combout & ((\ula_|zx_keyboard_|keys[0][0]~73_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[0][0]~73_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys~74_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~73_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hCC00; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & (\ula_|zx_keyboard_|keys[7][1]~21_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~69_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~69 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][0]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~70_combout = (\ula_|zx_keyboard_|keys[1][0]~69_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~69_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~69_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~70 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~70_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~8 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~8_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & +// (((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\z80_|address_pins_|abus[9]~16_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~8 .lut_mask = 16'hDD0D; +defparam \ula_|zx_keyboard_|key_row[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h4400; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~78 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[2][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~78_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~77_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~76_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~77 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N29 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0]~9 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[0]~9_combout = (\ula_|zx_keyboard_|keys[2][0]~q & (\z80_|address_pins_|abus[10]~19_combout & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\ula_|zx_keyboard_|keys[2][0]~q & +// (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][0]~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0]~9 .lut_mask = 16'hF351; +defparam \ula_|zx_keyboard_|key_row[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[0] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [0] = (\ula_|zx_keyboard_|key_row[0]~10_combout & (\ula_|zx_keyboard_|key_row[0]~11_combout & (\ula_|zx_keyboard_|key_row[0]~8_combout & \ula_|zx_keyboard_|key_row[0]~9_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[0]~10_combout ), + .datab(\ula_|zx_keyboard_|key_row[0]~11_combout ), + .datac(\ula_|zx_keyboard_|key_row[0]~8_combout ), + .datad(\ula_|zx_keyboard_|key_row[0]~9_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [0]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[0] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y34_N22 +cycloneive_io_ibuf \kempston[3]~input ( + .i(kempston[3]), + .ibar(gnd), + .o(\kempston[3]~input_o )); +// synopsys translate_off +defparam \kempston[3]~input .bus_hold = "false"; +defparam \kempston[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \Selector14~8 ( +// Equation(s): +// \Selector14~8_combout = (\Selector14~18_combout & (((!\kempston[3]~input_o & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row [0]) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [0]), + .datab(\Selector14~18_combout ), + .datac(\kempston[3]~input_o ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~8 .lut_mask = 16'h2E33; +defparam \Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \Selector14~13 ( +// Equation(s): +// \Selector14~13_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\Selector14~8_combout ) # ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a +// [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~13 .lut_mask = 16'hFFEA; +defparam \Selector14~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -47918,10 +47906,10 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -47959,27 +47947,9 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N8 -cycloneive_lcell_comb \D[0]~63 ( -// Equation(s): -// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~62_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~63 .lut_mask = 16'hE3E0; -defparam \D[0]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 +// Location: M9K_X22_Y25_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -47987,16 +47957,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48050,7 +48020,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y4_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portawe(vcc), .portare(vcc), @@ -48060,16 +48030,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48108,27 +48078,176 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \Selector14~19 ( // Equation(s): -// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) +// \Selector14~19_combout = (\z80_|address_pins_|DFFE_apin_latch [14] & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [14]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\Selector14~19_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hE6A2; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \Selector14~19 .lut_mask = 16'hF4B0; +defparam \Selector14~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y29_N0 +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \Selector14~10 ( +// Equation(s): +// \Selector14~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~10 .lut_mask = 16'hFA0A; +defparam \Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \Selector14~11 ( +// Equation(s): +// \Selector14~11_combout = (\Selector14~8_combout & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((!\Selector14~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector14~10_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~11 .lut_mask = 16'hCC0A; +defparam \Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -48136,16 +48255,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[0]~65_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[0]~14_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -48198,7 +48317,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y11_N0 +// Location: M9K_X22_Y3_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -48208,16 +48327,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -48256,104 +48375,102 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N28 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \Selector14~20 ( // Equation(s): -// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) +// \Selector14~20_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'h30CA; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N10 -cycloneive_lcell_comb \D[0]~61 ( -// Equation(s): -// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) - - .dataa(\D[0]~59_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datad(\D[0]~60_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~61_combout ), + .combout(\Selector14~20_combout ), .cout()); // synopsys translate_off -defparam \D[0]~61 .lut_mask = 16'h99A8; -defparam \D[0]~61 .sum_lutc_input = "datac"; +defparam \Selector14~20 .lut_mask = 16'hF2D0; +defparam \Selector14~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N18 -cycloneive_lcell_comb \D[0]~120 ( +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \Selector14~9 ( // Equation(s): -// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~63_combout )))) +// \Selector14~9_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector14~20_combout )) # (!\Selector14~8_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~63_combout ), - .datad(\D[0]~61_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Equal5~0_combout ), + .datac(\Selector14~20_combout ), + .datad(\Selector14~8_combout ), .cin(gnd), - .combout(\D[0]~120_combout ), + .combout(\Selector14~9_combout ), .cout()); // synopsys translate_off -defparam \D[0]~120 .lut_mask = 16'hF4B0; -defparam \D[0]~120 .sum_lutc_input = "datac"; +defparam \Selector14~9 .lut_mask = 16'hDC33; +defparam \Selector14~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N26 -cycloneive_lcell_comb \D[0]~64 ( +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \Selector14~12 ( // Equation(s): -// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) +// \Selector14~12_combout = (\Selector14~11_combout & (\Selector14~8_combout & ((\Selector14~19_combout ) # (\Selector14~9_combout )))) # (!\Selector14~11_combout & (((\Selector14~9_combout )))) - .dataa(\D[0]~58_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[0]~120_combout ), + .dataa(\Selector14~19_combout ), + .datab(\Selector14~8_combout ), + .datac(\Selector14~11_combout ), + .datad(\Selector14~9_combout ), .cin(gnd), - .combout(\D[0]~64_combout ), + .combout(\Selector14~12_combout ), .cout()); // synopsys translate_off -defparam \D[0]~64 .lut_mask = 16'hBF8F; -defparam \D[0]~64 .sum_lutc_input = "datac"; +defparam \Selector14~12 .lut_mask = 16'hCF80; +defparam \Selector14~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N16 -cycloneive_lcell_comb \D[0]~65 ( +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \Selector14~14 ( // Equation(s): -// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) +// \Selector14~14_combout = (\Selector14~12_combout & ((\Selector14~13_combout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) + + .dataa(\Selector14~13_combout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\Selector14~12_combout ), + .cin(gnd), + .combout(\Selector14~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector14~14 .lut_mask = 16'hBA00; +defparam \Selector14~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \D[0]~14 ( +// Equation(s): +// \D[0]~14_combout = (\z80_|data_pins_|dout [0] & (((\Selector14~14_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [0]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[0]~64_combout ), - .datad(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), - .combout(\D[0]~65_combout ), + .combout(\D[0]~14_combout ), .cout()); // synopsys translate_off -defparam \D[0]~65 .lut_mask = 16'hB0B3; -defparam \D[0]~65 .sum_lutc_input = "datac"; +defparam \D[0]~14 .lut_mask = 16'hAF23; +defparam \D[0]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N26 +// Location: LCCOMB_X26_Y16_N8 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & -// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|bus_control_|db[0]~12_combout & ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[0]~12_combout & +// (((\D[0]~14_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\D[0]~65_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\D[0]~14_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), .cout()); @@ -48362,7 +48479,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N27 +// Location: FF_X26_Y16_N9 dffeas \z80_|data_pins_|dout[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), @@ -48381,50 +48498,51 @@ defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~11 ( // Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[0]~11_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|alu_control_|db[0]~25_combout ) # ((!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|execute_|ctl_bus_ff_oe~1_combout & +// (!\z80_|execute_|ctl_bus_zero_oe~3_combout & ((\z80_|alu_control_|db[0]~25_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|data_pins_|dout [0]), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|alu_control_|db[0]~25_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), + .combout(\z80_|bus_control_|db[0]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~11 .lut_mask = 16'h8ACF; +defparam \z80_|bus_control_|db[0]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~12 ( // Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[0]~12_combout = ((\z80_|bus_control_|db[0]~11_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|bus_control_|db[0]~16_combout ), - .datab(\z80_|alu_control_|db[0]~14_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\z80_|bus_control_|db[0]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), + .combout(\z80_|bus_control_|db[0]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~12 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N19 +// Location: FF_X26_Y15_N15 dffeas \z80_|ir_|opcode[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), + .d(\z80_|bus_control_|db[0]~12_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [0]), @@ -48434,2832 +48552,311 @@ defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y7_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( // Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|pla_decode_|Equal52~0_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y7_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( // Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ))) - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal3~2_combout ), + .dataa(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y7_N31 -dffeas \z80_|decode_state_|DFFE_instIY1 ( +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|alu_flags_|DFFE_inst_latch_nf~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((\z80_|alu_control_|db[4]~31_combout & \z80_|execute_|ctl_flags_bus~combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))) # +// (!\z80_|execute_|ctl_flags_alu~18_combout & (\z80_|alu_control_|db[4]~31_combout & ((\z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hCE0A; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECA8; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y14_N13 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( -// Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_inst4~q ), - .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|ixy_d~10_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # -// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~12_combout ), - .datac(\z80_|execute_|ixy_d~13_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|ixy_d~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~11_combout ), - .datac(\z80_|execute_|ctl_alu_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_oe~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( -// Equation(s): -// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|execute_|ctl_sw_2d~13_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; -defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N0 -cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( -// Equation(s): -// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & -// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( -// Equation(s): -// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) - - .dataa(\z80_|alu_|db[7]~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~20_combout ), - .datad(\z80_|alu_|db[1]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; -defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|alu_|db[1]~16_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|alu_control_|db[2]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N6 -cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( -// Equation(s): -// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datad(\z80_|execute_|ctl_sw_1d~7_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; -defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( -// Equation(s): -// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|sw1_|db_down[1]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; -defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(\z80_|alu_control_|db[1]~27_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; -defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N9 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y10_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y10_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [12]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[4][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; -defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; -defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y10_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y10_N25 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), - .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; -defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; -defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N28 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & -// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\z80_|address_pins_|abus[15]~21_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hCF45; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N12 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|key_row~0_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hB000; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; -defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; -defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; -defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; -defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & -// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N16 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & -// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), - .datab(\ula_|zx_keyboard_|keys[0][1]~q ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\z80_|address_pins_|abus[8]~18_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hF531; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; -defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N31 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y10_N21 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N8 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & -// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\z80_|address_pins_|abus[10]~20_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'h8ACF; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y9_N6 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~33_combout ), - .datab(\D[1]~30_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF8F0; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N22 -cycloneive_lcell_comb \D[1]~38 ( -// Equation(s): -// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .cin(gnd), - .combout(\D[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~38 .lut_mask = 16'hE6A2; -defparam \D[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N4 -cycloneive_lcell_comb \D[1]~39 ( -// Equation(s): -// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datac(\D[1]~38_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\D[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~39 .lut_mask = 16'hE5E0; -defparam \D[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~41_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N24 -cycloneive_lcell_comb \D[1]~35 ( -// Equation(s): -// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\D[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~35 .lut_mask = 16'hEA62; -defparam \D[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N14 -cycloneive_lcell_comb \D[1]~36 ( -// Equation(s): -// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~36 .lut_mask = 16'h44B8; -defparam \D[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N0 -cycloneive_lcell_comb \D[1]~37 ( -// Equation(s): -// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datac(\D[1]~36_combout ), - .datad(\D[1]~35_combout ), - .cin(gnd), - .combout(\D[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~37 .lut_mask = 16'hAE50; -defparam \D[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[1]~118 ( -// Equation(s): -// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[1]~39_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[1]~39_combout ), - .datad(\D[1]~37_combout ), - .cin(gnd), - .combout(\D[1]~118_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~118 .lut_mask = 16'hF4B0; -defparam \D[1]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N2 -cycloneive_lcell_comb \D[1]~40 ( -// Equation(s): -// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) - - .dataa(\D[1]~34_combout ), - .datab(\Equal2~0_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[1]~118_combout ), - .cin(gnd), - .combout(\D[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~40 .lut_mask = 16'hBF8F; -defparam \D[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N12 -cycloneive_lcell_comb \D[1]~41 ( -// Equation(s): -// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [1]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[1]~40_combout ), - .cin(gnd), - .combout(\D[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~41 .lut_mask = 16'hAF03; -defparam \D[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & -// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[1]~41_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[1]~11_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[1]~10_combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[1]~11_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y7_N29 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y6_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal9~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y7_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_apin_mux~0_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y9_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y9_N1 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y9_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~1_combout ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|flags_cf~combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .combout(\z80_|alu_flags_|flags_hf~combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h31CE; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y9_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N16 -cycloneive_lcell_comb \D[4]~88 ( +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~29 ( // Equation(s): -// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & -// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) +// \z80_|alu_control_|db[4]~29_combout = (\z80_|reg_file_|gdfx_temp0[4]~73_combout & (!\z80_|alu_|db[4]~10_combout & ((\z80_|execute_|ctl_sw_2u~8_combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~73_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # +// ((!\z80_|alu_|db[4]~10_combout & \z80_|execute_|ctl_sw_2u~8_combout )))) - .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), - .datab(\z80_|address_pins_|abus[14]~22_combout ), - .datac(\z80_|address_pins_|abus[15]~21_combout ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .dataa(\z80_|reg_file_|gdfx_temp0[4]~73_combout ), + .datab(\z80_|alu_|db[4]~10_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|execute_|ctl_sw_2u~8_combout ), .cin(gnd), - .combout(\D[4]~88_combout ), + .combout(\z80_|alu_control_|db[4]~29_combout ), .cout()); // synopsys translate_off -defparam \D[4]~88 .lut_mask = 16'hD0DD; -defparam \D[4]~88 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~29 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~29 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|alu_control_|db[4]~30_combout = (!\z80_|alu_control_|db[4]~29_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_control_|db[4]~29_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .combout(\z80_|alu_control_|db[4]~30_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h2300; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y9_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q -// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|alu_control_|db[4]~31_combout = ((\z80_|alu_control_|db[4]~30_combout & ((\z80_|bus_control_|db[4]~18_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|bus_control_|db[4]~18_combout ), + .datab(\z80_|alu_control_|db[4]~30_combout ), + .datac(\z80_|alu_control_|db[6]~11_combout ), + .datad(\z80_|execute_|ctl_sw_1d~6_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .combout(\z80_|alu_control_|db[4]~31_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h8FCF; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y9_N31 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y9_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y9_N9 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N28 -cycloneive_lcell_comb \D[4]~87 ( -// Equation(s): -// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & -// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\z80_|address_pins_|abus[12]~24_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\D[4]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~87 .lut_mask = 16'h8ACF; -defparam \D[4]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & -// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; -defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N25 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y10_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[2][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y8_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; -defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y9_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y9_N21 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y8_N21 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y8_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|Equal0~2_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y8_N15 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y8_N6 -cycloneive_lcell_comb \D[4]~85 ( -// Equation(s): -// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~q ), - .datac(\z80_|address_pins_|abus[8]~18_combout ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~85 .lut_mask = 16'hA2F3; -defparam \D[4]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y11_N20 -cycloneive_lcell_comb \D[4]~86 ( -// Equation(s): -// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|key_row~3_combout ), - .datab(\z80_|address_pins_|abus[11]~19_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\D[4]~85_combout ), - .cin(gnd), - .combout(\D[4]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~86 .lut_mask = 16'h8A00; -defparam \D[4]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y14_N24 -cycloneive_lcell_comb \D[4]~89 ( -// Equation(s): -// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) - - .dataa(\D[4]~88_combout ), - .datab(\D[4]~87_combout ), - .datac(\z80_|address_pins_|abus[0]~16_combout ), - .datad(\D[4]~86_combout ), - .cin(gnd), - .combout(\D[4]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~89 .lut_mask = 16'hF8F0; -defparam \D[4]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N18 -cycloneive_lcell_comb \D[4]~93 ( -// Equation(s): -// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .cin(gnd), - .combout(\D[4]~93_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~93 .lut_mask = 16'hF838; -defparam \D[4]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X25_Y19_N4 -cycloneive_lcell_comb \D[4]~94 ( -// Equation(s): -// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\D[4]~93_combout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .cin(gnd), - .combout(\D[4]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~94 .lut_mask = 16'hCEC2; -defparam \D[4]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: M9K_X22_Y21_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51267,16 +48864,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[4]~111_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51330,83 +48927,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N8 -cycloneive_lcell_comb \D[4]~90 ( -// Equation(s): -// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .cin(gnd), - .combout(\D[4]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~90 .lut_mask = 16'hE6A2; -defparam \D[4]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 +// Location: M9K_X33_Y22_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portawe(vcc), .portare(vcc), @@ -51416,16 +48937,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51464,104 +48985,2926 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N22 -cycloneive_lcell_comb \D[4]~91 ( +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \Selector6~0 ( // Equation(s): -// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ) # (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout & ((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hCCE2; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector6~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector6~0_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector6~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hF388; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout )))) .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), - .datac(\D[4]~90_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), .cin(gnd), - .combout(\D[4]~91_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), .cout()); // synopsys translate_off -defparam \D[4]~91 .lut_mask = 16'h4B48; -defparam \D[4]~91 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N28 -cycloneive_lcell_comb \D[4]~92 ( +// Location: LCCOMB_X19_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( // Equation(s): -// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [0]))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[4]~90_combout ), - .datad(\D[4]~91_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\D[4]~92_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~92 .lut_mask = 16'hC3E0; -defparam \D[4]~92 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N8 -cycloneive_lcell_comb \D[4]~125 ( +// Location: LCCOMB_X20_Y21_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~114 ( // Equation(s): -// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (((\D[4]~94_combout )))) +// \ula_|zx_keyboard_|keys[6][4]~114_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\D[4]~94_combout ), - .datad(\D[4]~92_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\D[4]~125_combout ), + .combout(\ula_|zx_keyboard_|keys[6][4]~114_combout ), .cout()); // synopsys translate_off -defparam \D[4]~125 .lut_mask = 16'hF2D0; -defparam \D[4]~125 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][4]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N30 -cycloneive_lcell_comb \D[4]~110 ( +// Location: LCCOMB_X20_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~115 ( // Equation(s): -// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) +// \ula_|zx_keyboard_|keys[6][4]~115_combout = (\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~115 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N31 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~113_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~1_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~113 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N5 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~16_combout = (\z80_|address_pins_|abus[15]~23_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][4]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~16 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[0]~21 ( +// Equation(s): +// \debounce_autofire|r_Count[0]~21_combout = \debounce_autofire|r_Count [0] $ (VCC) +// \debounce_autofire|r_Count[0]~22 = CARRY(\debounce_autofire|r_Count [0]) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\debounce_autofire|r_Count[0]~21_combout ), + .cout(\debounce_autofire|r_Count[0]~22 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0]~21 .lut_mask = 16'h55AA; +defparam \debounce_autofire|r_Count[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[1]~23 ( +// Equation(s): +// \debounce_autofire|r_Count[1]~23_combout = (\debounce_autofire|r_Count [1] & (!\debounce_autofire|r_Count[0]~22 )) # (!\debounce_autofire|r_Count [1] & ((\debounce_autofire|r_Count[0]~22 ) # (GND))) +// \debounce_autofire|r_Count[1]~24 = CARRY((!\debounce_autofire|r_Count[0]~22 ) # (!\debounce_autofire|r_Count [1])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [1]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[0]~22 ), + .combout(\debounce_autofire|r_Count[1]~23_combout ), + .cout(\debounce_autofire|r_Count[1]~24 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1]~23 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \debounce_autofire|r_Count[1] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[1]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[1] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[2]~25 ( +// Equation(s): +// \debounce_autofire|r_Count[2]~25_combout = (\debounce_autofire|r_Count [2] & (\debounce_autofire|r_Count[1]~24 $ (GND))) # (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count[1]~24 & VCC)) +// \debounce_autofire|r_Count[2]~26 = CARRY((\debounce_autofire|r_Count [2] & !\debounce_autofire|r_Count[1]~24 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [2]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[1]~24 ), + .combout(\debounce_autofire|r_Count[2]~25_combout ), + .cout(\debounce_autofire|r_Count[2]~26 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2]~25 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \debounce_autofire|r_Count[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[2]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[2] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[3]~27 ( +// Equation(s): +// \debounce_autofire|r_Count[3]~27_combout = (\debounce_autofire|r_Count [3] & (!\debounce_autofire|r_Count[2]~26 )) # (!\debounce_autofire|r_Count [3] & ((\debounce_autofire|r_Count[2]~26 ) # (GND))) +// \debounce_autofire|r_Count[3]~28 = CARRY((!\debounce_autofire|r_Count[2]~26 ) # (!\debounce_autofire|r_Count [3])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [3]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[2]~26 ), + .combout(\debounce_autofire|r_Count[3]~27_combout ), + .cout(\debounce_autofire|r_Count[3]~28 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3]~27 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \debounce_autofire|r_Count[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[3]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[3] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[4]~29 ( +// Equation(s): +// \debounce_autofire|r_Count[4]~29_combout = (\debounce_autofire|r_Count [4] & (\debounce_autofire|r_Count[3]~28 $ (GND))) # (!\debounce_autofire|r_Count [4] & (!\debounce_autofire|r_Count[3]~28 & VCC)) +// \debounce_autofire|r_Count[4]~30 = CARRY((\debounce_autofire|r_Count [4] & !\debounce_autofire|r_Count[3]~28 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [4]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[3]~28 ), + .combout(\debounce_autofire|r_Count[4]~29_combout ), + .cout(\debounce_autofire|r_Count[4]~30 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4]~29 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \debounce_autofire|r_Count[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[4]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [4]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[4] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \debounce_autofire|r_Count[5]~31 ( +// Equation(s): +// \debounce_autofire|r_Count[5]~31_combout = (\debounce_autofire|r_Count [5] & (!\debounce_autofire|r_Count[4]~30 )) # (!\debounce_autofire|r_Count [5] & ((\debounce_autofire|r_Count[4]~30 ) # (GND))) +// \debounce_autofire|r_Count[5]~32 = CARRY((!\debounce_autofire|r_Count[4]~30 ) # (!\debounce_autofire|r_Count [5])) + + .dataa(\debounce_autofire|r_Count [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[4]~30 ), + .combout(\debounce_autofire|r_Count[5]~31_combout ), + .cout(\debounce_autofire|r_Count[5]~32 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5]~31 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \debounce_autofire|r_Count[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[5]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [5]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[5] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \debounce_autofire|r_Count[6]~33 ( +// Equation(s): +// \debounce_autofire|r_Count[6]~33_combout = (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count[5]~32 $ (GND))) # (!\debounce_autofire|r_Count [6] & (!\debounce_autofire|r_Count[5]~32 & VCC)) +// \debounce_autofire|r_Count[6]~34 = CARRY((\debounce_autofire|r_Count [6] & !\debounce_autofire|r_Count[5]~32 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [6]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[5]~32 ), + .combout(\debounce_autofire|r_Count[6]~33_combout ), + .cout(\debounce_autofire|r_Count[6]~34 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6]~33 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \debounce_autofire|r_Count[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[6]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [6]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[6] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \debounce_autofire|r_Count[7]~35 ( +// Equation(s): +// \debounce_autofire|r_Count[7]~35_combout = (\debounce_autofire|r_Count [7] & (!\debounce_autofire|r_Count[6]~34 )) # (!\debounce_autofire|r_Count [7] & ((\debounce_autofire|r_Count[6]~34 ) # (GND))) +// \debounce_autofire|r_Count[7]~36 = CARRY((!\debounce_autofire|r_Count[6]~34 ) # (!\debounce_autofire|r_Count [7])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[6]~34 ), + .combout(\debounce_autofire|r_Count[7]~35_combout ), + .cout(\debounce_autofire|r_Count[7]~36 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7]~35 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N27 +dffeas \debounce_autofire|r_Count[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[7]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [7]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[7] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \debounce_autofire|r_Count[8]~37 ( +// Equation(s): +// \debounce_autofire|r_Count[8]~37_combout = (\debounce_autofire|r_Count [8] & (\debounce_autofire|r_Count[7]~36 $ (GND))) # (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_Count[7]~36 & VCC)) +// \debounce_autofire|r_Count[8]~38 = CARRY((\debounce_autofire|r_Count [8] & !\debounce_autofire|r_Count[7]~36 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [8]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[7]~36 ), + .combout(\debounce_autofire|r_Count[8]~37_combout ), + .cout(\debounce_autofire|r_Count[8]~38 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8]~37 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N29 +dffeas \debounce_autofire|r_Count[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[8]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [8]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[8] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \debounce_autofire|r_Count[9]~39 ( +// Equation(s): +// \debounce_autofire|r_Count[9]~39_combout = (\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count[8]~38 )) # (!\debounce_autofire|r_Count [9] & ((\debounce_autofire|r_Count[8]~38 ) # (GND))) +// \debounce_autofire|r_Count[9]~40 = CARRY((!\debounce_autofire|r_Count[8]~38 ) # (!\debounce_autofire|r_Count [9])) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[8]~38 ), + .combout(\debounce_autofire|r_Count[9]~39_combout ), + .cout(\debounce_autofire|r_Count[9]~40 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9]~39 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \debounce_autofire|r_Count[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[9]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [9]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[9] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_Count[10]~41 ( +// Equation(s): +// \debounce_autofire|r_Count[10]~41_combout = (\debounce_autofire|r_Count [10] & (\debounce_autofire|r_Count[9]~40 $ (GND))) # (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count[9]~40 & VCC)) +// \debounce_autofire|r_Count[10]~42 = CARRY((\debounce_autofire|r_Count [10] & !\debounce_autofire|r_Count[9]~40 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [10]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[9]~40 ), + .combout(\debounce_autofire|r_Count[10]~41_combout ), + .cout(\debounce_autofire|r_Count[10]~42 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10]~41 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \debounce_autofire|r_Count[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[10]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [10]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[10] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \debounce_autofire|r_Count[11]~43 ( +// Equation(s): +// \debounce_autofire|r_Count[11]~43_combout = (\debounce_autofire|r_Count [11] & (!\debounce_autofire|r_Count[10]~42 )) # (!\debounce_autofire|r_Count [11] & ((\debounce_autofire|r_Count[10]~42 ) # (GND))) +// \debounce_autofire|r_Count[11]~44 = CARRY((!\debounce_autofire|r_Count[10]~42 ) # (!\debounce_autofire|r_Count [11])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [11]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[10]~42 ), + .combout(\debounce_autofire|r_Count[11]~43_combout ), + .cout(\debounce_autofire|r_Count[11]~44 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11]~43 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \debounce_autofire|r_Count[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[11]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [11]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[11] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \debounce_autofire|r_Count[12]~45 ( +// Equation(s): +// \debounce_autofire|r_Count[12]~45_combout = (\debounce_autofire|r_Count [12] & (\debounce_autofire|r_Count[11]~44 $ (GND))) # (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count[11]~44 & VCC)) +// \debounce_autofire|r_Count[12]~46 = CARRY((\debounce_autofire|r_Count [12] & !\debounce_autofire|r_Count[11]~44 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [12]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[11]~44 ), + .combout(\debounce_autofire|r_Count[12]~45_combout ), + .cout(\debounce_autofire|r_Count[12]~46 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12]~45 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \debounce_autofire|r_Count[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[12]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [12]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[12] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \debounce_autofire|r_Count[13]~47 ( +// Equation(s): +// \debounce_autofire|r_Count[13]~47_combout = (\debounce_autofire|r_Count [13] & (!\debounce_autofire|r_Count[12]~46 )) # (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|r_Count[12]~46 ) # (GND))) +// \debounce_autofire|r_Count[13]~48 = CARRY((!\debounce_autofire|r_Count[12]~46 ) # (!\debounce_autofire|r_Count [13])) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[12]~46 ), + .combout(\debounce_autofire|r_Count[13]~47_combout ), + .cout(\debounce_autofire|r_Count[13]~48 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13]~47 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \debounce_autofire|r_Count[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[13]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [13]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[13] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \debounce_autofire|r_Count[14]~49 ( +// Equation(s): +// \debounce_autofire|r_Count[14]~49_combout = (\debounce_autofire|r_Count [14] & (\debounce_autofire|r_Count[13]~48 $ (GND))) # (!\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count[13]~48 & VCC)) +// \debounce_autofire|r_Count[14]~50 = CARRY((\debounce_autofire|r_Count [14] & !\debounce_autofire|r_Count[13]~48 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [14]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[13]~48 ), + .combout(\debounce_autofire|r_Count[14]~49_combout ), + .cout(\debounce_autofire|r_Count[14]~50 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14]~49 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \debounce_autofire|r_Count[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[14]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [14]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[14] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \debounce_autofire|r_Count[15]~51 ( +// Equation(s): +// \debounce_autofire|r_Count[15]~51_combout = (\debounce_autofire|r_Count [15] & (!\debounce_autofire|r_Count[14]~50 )) # (!\debounce_autofire|r_Count [15] & ((\debounce_autofire|r_Count[14]~50 ) # (GND))) +// \debounce_autofire|r_Count[15]~52 = CARRY((!\debounce_autofire|r_Count[14]~50 ) # (!\debounce_autofire|r_Count [15])) + + .dataa(\debounce_autofire|r_Count [15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[14]~50 ), + .combout(\debounce_autofire|r_Count[15]~51_combout ), + .cout(\debounce_autofire|r_Count[15]~52 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15]~51 .lut_mask = 16'h5A5F; +defparam \debounce_autofire|r_Count[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \debounce_autofire|r_Count[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[15]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [15]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[15] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \debounce_autofire|r_Count[16]~53 ( +// Equation(s): +// \debounce_autofire|r_Count[16]~53_combout = (\debounce_autofire|r_Count [16] & (\debounce_autofire|r_Count[15]~52 $ (GND))) # (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count[15]~52 & VCC)) +// \debounce_autofire|r_Count[16]~54 = CARRY((\debounce_autofire|r_Count [16] & !\debounce_autofire|r_Count[15]~52 )) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[15]~52 ), + .combout(\debounce_autofire|r_Count[16]~53_combout ), + .cout(\debounce_autofire|r_Count[16]~54 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16]~53 .lut_mask = 16'hA50A; +defparam \debounce_autofire|r_Count[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \debounce_autofire|r_Count[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[16]~53_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [16]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[16] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \debounce_autofire|r_Count[17]~55 ( +// Equation(s): +// \debounce_autofire|r_Count[17]~55_combout = (\debounce_autofire|r_Count [17] & (!\debounce_autofire|r_Count[16]~54 )) # (!\debounce_autofire|r_Count [17] & ((\debounce_autofire|r_Count[16]~54 ) # (GND))) +// \debounce_autofire|r_Count[17]~56 = CARRY((!\debounce_autofire|r_Count[16]~54 ) # (!\debounce_autofire|r_Count [17])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [17]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[16]~54 ), + .combout(\debounce_autofire|r_Count[17]~55_combout ), + .cout(\debounce_autofire|r_Count[17]~56 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17]~55 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \debounce_autofire|r_Count[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[17]~55_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [17]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[17] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \debounce_autofire|r_Count[18]~57 ( +// Equation(s): +// \debounce_autofire|r_Count[18]~57_combout = (\debounce_autofire|r_Count [18] & (\debounce_autofire|r_Count[17]~56 $ (GND))) # (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count[17]~56 & VCC)) +// \debounce_autofire|r_Count[18]~58 = CARRY((\debounce_autofire|r_Count [18] & !\debounce_autofire|r_Count[17]~56 )) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [18]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[17]~56 ), + .combout(\debounce_autofire|r_Count[18]~57_combout ), + .cout(\debounce_autofire|r_Count[18]~58 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18]~57 .lut_mask = 16'hC30C; +defparam \debounce_autofire|r_Count[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \debounce_autofire|r_Count[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[18]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [18]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[18] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_Count[19]~59 ( +// Equation(s): +// \debounce_autofire|r_Count[19]~59_combout = (\debounce_autofire|r_Count [19] & (!\debounce_autofire|r_Count[18]~58 )) # (!\debounce_autofire|r_Count [19] & ((\debounce_autofire|r_Count[18]~58 ) # (GND))) +// \debounce_autofire|r_Count[19]~60 = CARRY((!\debounce_autofire|r_Count[18]~58 ) # (!\debounce_autofire|r_Count [19])) + + .dataa(gnd), + .datab(\debounce_autofire|r_Count [19]), + .datac(gnd), + .datad(vcc), + .cin(\debounce_autofire|r_Count[18]~58 ), + .combout(\debounce_autofire|r_Count[19]~59_combout ), + .cout(\debounce_autofire|r_Count[19]~60 )); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19]~59 .lut_mask = 16'h3C3F; +defparam \debounce_autofire|r_Count[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \debounce_autofire|r_Count[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[19]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [19]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[19] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \debounce_autofire|r_Count[20]~61 ( +// Equation(s): +// \debounce_autofire|r_Count[20]~61_combout = \debounce_autofire|r_Count[19]~60 $ (!\debounce_autofire|r_Count [20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\debounce_autofire|r_Count [20]), + .cin(\debounce_autofire|r_Count[19]~60 ), + .combout(\debounce_autofire|r_Count[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20]~61 .lut_mask = 16'hF00F; +defparam \debounce_autofire|r_Count[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \debounce_autofire|r_Count[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[20]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [20]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[20] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y15_N8 +cycloneive_io_ibuf \kempston_autofire_button~input ( + .i(kempston_autofire_button), + .ibar(gnd), + .o(\kempston_autofire_button~input_o )); +// synopsys translate_off +defparam \kempston_autofire_button~input .bus_hold = "false"; +defparam \kempston_autofire_button~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~7 ( +// Equation(s): +// \debounce_autofire|r_State~7_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [6])) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(gnd), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [6]), + .cin(gnd), + .combout(\debounce_autofire|r_State~7_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~7 .lut_mask = 16'hA000; +defparam \debounce_autofire|r_State~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \debounce_autofire|LessThan0~0 ( +// Equation(s): +// \debounce_autofire|LessThan0~0_combout = (!\debounce_autofire|r_Count [9] & (!\debounce_autofire|r_Count [8] & (!\debounce_autofire|r_State~7_combout & !\debounce_autofire|r_Count [10]))) + + .dataa(\debounce_autofire|r_Count [9]), + .datab(\debounce_autofire|r_Count [8]), + .datac(\debounce_autofire|r_State~7_combout ), + .datad(\debounce_autofire|r_Count [10]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \debounce_autofire|LessThan0~1 ( +// Equation(s): +// \debounce_autofire|LessThan0~1_combout = (!\debounce_autofire|r_Count [12] & (!\debounce_autofire|r_Count [13] & ((\debounce_autofire|LessThan0~0_combout ) # (!\debounce_autofire|r_Count [11])))) + + .dataa(\debounce_autofire|LessThan0~0_combout ), + .datab(\debounce_autofire|r_Count [11]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [13]), + .cin(gnd), + .combout(\debounce_autofire|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|LessThan0~1 .lut_mask = 16'h000B; +defparam \debounce_autofire|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \debounce_autofire|always0~0 ( +// Equation(s): +// \debounce_autofire|always0~0_combout = (!\debounce_autofire|r_Count [16] & (!\debounce_autofire|r_Count [18] & (!\debounce_autofire|r_Count [17] & !\debounce_autofire|r_Count [19]))) + + .dataa(\debounce_autofire|r_Count [16]), + .datab(\debounce_autofire|r_Count [18]), + .datac(\debounce_autofire|r_Count [17]), + .datad(\debounce_autofire|r_Count [19]), + .cin(gnd), + .combout(\debounce_autofire|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~0 .lut_mask = 16'h0001; +defparam \debounce_autofire|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \debounce_autofire|always0~1 ( +// Equation(s): +// \debounce_autofire|always0~1_combout = (\debounce_autofire|always0~0_combout & ((\debounce_autofire|LessThan0~1_combout ) # ((!\debounce_autofire|r_Count [15]) # (!\debounce_autofire|r_Count [14])))) + + .dataa(\debounce_autofire|LessThan0~1_combout ), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|always0~0_combout ), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~1 .lut_mask = 16'hB0F0; +defparam \debounce_autofire|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \debounce_autofire|always0~2 ( +// Equation(s): +// \debounce_autofire|always0~2_combout = (\debounce_autofire|r_Count [20] & ((\debounce_autofire|r_State~q $ (!\kempston_autofire_button~input_o )) # (!\debounce_autofire|always0~1_combout ))) # (!\debounce_autofire|r_Count [20] & +// (\debounce_autofire|r_State~q $ ((!\kempston_autofire_button~input_o )))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_State~q ), + .datac(\kempston_autofire_button~input_o ), + .datad(\debounce_autofire|always0~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|always0~2 .lut_mask = 16'hC3EB; +defparam \debounce_autofire|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \debounce_autofire|r_Count[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\debounce_autofire|r_Count[0]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\debounce_autofire|always0~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_Count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_Count[0] .is_wysiwyg = "true"; +defparam \debounce_autofire|r_Count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \debounce_autofire|r_State~4 ( +// Equation(s): +// \debounce_autofire|r_State~4_combout = (!\debounce_autofire|r_Count [0] & (!\debounce_autofire|r_Count [2] & (!\debounce_autofire|r_Count [1] & !\debounce_autofire|r_Count [3]))) + + .dataa(\debounce_autofire|r_Count [0]), + .datab(\debounce_autofire|r_Count [2]), + .datac(\debounce_autofire|r_Count [1]), + .datad(\debounce_autofire|r_Count [3]), + .cin(gnd), + .combout(\debounce_autofire|r_State~4_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~4 .lut_mask = 16'h0001; +defparam \debounce_autofire|r_State~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \debounce_autofire|r_State~5 ( +// Equation(s): +// \debounce_autofire|r_State~5_combout = (\debounce_autofire|r_State~4_combout & !\debounce_autofire|r_Count [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\debounce_autofire|r_State~4_combout ), + .datad(\debounce_autofire|r_Count [4]), + .cin(gnd), + .combout(\debounce_autofire|r_State~5_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~5 .lut_mask = 16'h00F0; +defparam \debounce_autofire|r_State~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \debounce_autofire|r_State~2 ( +// Equation(s): +// \debounce_autofire|r_State~2_combout = (\debounce_autofire|r_Count [20] & (!\debounce_autofire|r_Count [10] & (!\debounce_autofire|r_Count [9] & !\debounce_autofire|r_Count [8]))) + + .dataa(\debounce_autofire|r_Count [20]), + .datab(\debounce_autofire|r_Count [10]), + .datac(\debounce_autofire|r_Count [9]), + .datad(\debounce_autofire|r_Count [8]), + .cin(gnd), + .combout(\debounce_autofire|r_State~2_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~2 .lut_mask = 16'h0002; +defparam \debounce_autofire|r_State~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \debounce_autofire|r_State~0 ( +// Equation(s): +// \debounce_autofire|r_State~0_combout = (!\debounce_autofire|r_Count [13] & (\debounce_autofire|r_Count [14] & (!\debounce_autofire|r_Count [12] & \debounce_autofire|r_Count [15]))) + + .dataa(\debounce_autofire|r_Count [13]), + .datab(\debounce_autofire|r_Count [14]), + .datac(\debounce_autofire|r_Count [12]), + .datad(\debounce_autofire|r_Count [15]), + .cin(gnd), + .combout(\debounce_autofire|r_State~0_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~0 .lut_mask = 16'h0400; +defparam \debounce_autofire|r_State~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \debounce_autofire|r_State~1 ( +// Equation(s): +// \debounce_autofire|r_State~1_combout = (\debounce_autofire|r_Count [7] & (\debounce_autofire|r_Count [6] & (\debounce_autofire|r_Count [5] & \debounce_autofire|r_Count [11]))) + + .dataa(\debounce_autofire|r_Count [7]), + .datab(\debounce_autofire|r_Count [6]), + .datac(\debounce_autofire|r_Count [5]), + .datad(\debounce_autofire|r_Count [11]), + .cin(gnd), + .combout(\debounce_autofire|r_State~1_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~1 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N0 +cycloneive_lcell_comb \debounce_autofire|r_State~3 ( +// Equation(s): +// \debounce_autofire|r_State~3_combout = (\debounce_autofire|always0~0_combout & (\debounce_autofire|r_State~2_combout & (\debounce_autofire|r_State~0_combout & \debounce_autofire|r_State~1_combout ))) + + .dataa(\debounce_autofire|always0~0_combout ), + .datab(\debounce_autofire|r_State~2_combout ), + .datac(\debounce_autofire|r_State~0_combout ), + .datad(\debounce_autofire|r_State~1_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~3_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~3 .lut_mask = 16'h8000; +defparam \debounce_autofire|r_State~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N18 +cycloneive_lcell_comb \debounce_autofire|r_State~6 ( +// Equation(s): +// \debounce_autofire|r_State~6_combout = (\debounce_autofire|r_State~5_combout & ((\debounce_autofire|r_State~3_combout & (\kempston_autofire_button~input_o )) # (!\debounce_autofire|r_State~3_combout & ((\debounce_autofire|r_State~q ))))) # +// (!\debounce_autofire|r_State~5_combout & (((\debounce_autofire|r_State~q )))) + + .dataa(\debounce_autofire|r_State~5_combout ), + .datab(\kempston_autofire_button~input_o ), + .datac(\debounce_autofire|r_State~q ), + .datad(\debounce_autofire|r_State~3_combout ), + .cin(gnd), + .combout(\debounce_autofire|r_State~6_combout ), + .cout()); +// synopsys translate_off +defparam \debounce_autofire|r_State~6 .lut_mask = 16'hD8F0; +defparam \debounce_autofire|r_State~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N19 +dffeas \debounce_autofire|r_State ( + .clk(\CLOCK_50~input_o ), + .d(\debounce_autofire|r_State~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\debounce_autofire|r_State~q ), + .prn(vcc)); +// synopsys translate_off +defparam \debounce_autofire|r_State .is_wysiwyg = "true"; +defparam \debounce_autofire|r_State .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N30 +cycloneive_lcell_comb \kempston_autofire_enabled~0 ( +// Equation(s): +// \kempston_autofire_enabled~0_combout = !\kempston_autofire_enabled~q + + .dataa(gnd), + .datab(gnd), + .datac(\kempston_autofire_enabled~q ), + .datad(gnd), + .cin(gnd), + .combout(\kempston_autofire_enabled~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_autofire_enabled~0 .lut_mask = 16'h0F0F; +defparam \kempston_autofire_enabled~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y14_N31 +dffeas kempston_autofire_enabled( + .clk(!\debounce_autofire|r_State~q ), + .d(\kempston_autofire_enabled~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_autofire_enabled~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_autofire_enabled.is_wysiwyg = "true"; +defparam kempston_autofire_enabled.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[0]~51 ( +// Equation(s): +// \kempston_auto_fire_counter[0]~51_combout = \kempston_autofire_enabled~q $ (kempston_auto_fire_counter[0]) + + .dataa(\kempston_autofire_enabled~q ), + .datab(gnd), + .datac(kempston_auto_fire_counter[0]), + .datad(gnd), + .cin(gnd), + .combout(\kempston_auto_fire_counter[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0]~51 .lut_mask = 16'h5A5A; +defparam \kempston_auto_fire_counter[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N13 +dffeas \kempston_auto_fire_counter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[0]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[0]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[0] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[1]~17 ( +// Equation(s): +// \kempston_auto_fire_counter[1]~17_combout = (kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] $ (VCC))) # (!kempston_auto_fire_counter[0] & (kempston_auto_fire_counter[1] & VCC)) +// \kempston_auto_fire_counter[1]~18 = CARRY((kempston_auto_fire_counter[0] & kempston_auto_fire_counter[1])) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\kempston_auto_fire_counter[1]~17_combout ), + .cout(\kempston_auto_fire_counter[1]~18 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1]~17 .lut_mask = 16'h6688; +defparam \kempston_auto_fire_counter[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y13_N17 +dffeas \kempston_auto_fire_counter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[1]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[1]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[1] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N18 +cycloneive_lcell_comb \kempston_auto_fire_counter[2]~19 ( +// Equation(s): +// \kempston_auto_fire_counter[2]~19_combout = (kempston_auto_fire_counter[2] & (!\kempston_auto_fire_counter[1]~18 )) # (!kempston_auto_fire_counter[2] & ((\kempston_auto_fire_counter[1]~18 ) # (GND))) +// \kempston_auto_fire_counter[2]~20 = CARRY((!\kempston_auto_fire_counter[1]~18 ) # (!kempston_auto_fire_counter[2])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[1]~18 ), + .combout(\kempston_auto_fire_counter[2]~19_combout ), + .cout(\kempston_auto_fire_counter[2]~20 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2]~19 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[2]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N19 +dffeas \kempston_auto_fire_counter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[2]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[2] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \kempston_auto_fire_counter[3]~21 ( +// Equation(s): +// \kempston_auto_fire_counter[3]~21_combout = (kempston_auto_fire_counter[3] & (\kempston_auto_fire_counter[2]~20 $ (GND))) # (!kempston_auto_fire_counter[3] & (!\kempston_auto_fire_counter[2]~20 & VCC)) +// \kempston_auto_fire_counter[3]~22 = CARRY((kempston_auto_fire_counter[3] & !\kempston_auto_fire_counter[2]~20 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[2]~20 ), + .combout(\kempston_auto_fire_counter[3]~21_combout ), + .cout(\kempston_auto_fire_counter[3]~22 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3]~21 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[3]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N21 +dffeas \kempston_auto_fire_counter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[3]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[3] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N22 +cycloneive_lcell_comb \kempston_auto_fire_counter[4]~23 ( +// Equation(s): +// \kempston_auto_fire_counter[4]~23_combout = (kempston_auto_fire_counter[4] & (!\kempston_auto_fire_counter[3]~22 )) # (!kempston_auto_fire_counter[4] & ((\kempston_auto_fire_counter[3]~22 ) # (GND))) +// \kempston_auto_fire_counter[4]~24 = CARRY((!\kempston_auto_fire_counter[3]~22 ) # (!kempston_auto_fire_counter[4])) + + .dataa(kempston_auto_fire_counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[3]~22 ), + .combout(\kempston_auto_fire_counter[4]~23_combout ), + .cout(\kempston_auto_fire_counter[4]~24 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4]~23 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[4]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N23 +dffeas \kempston_auto_fire_counter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[4]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[4] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N24 +cycloneive_lcell_comb \kempston_auto_fire_counter[5]~25 ( +// Equation(s): +// \kempston_auto_fire_counter[5]~25_combout = (kempston_auto_fire_counter[5] & (\kempston_auto_fire_counter[4]~24 $ (GND))) # (!kempston_auto_fire_counter[5] & (!\kempston_auto_fire_counter[4]~24 & VCC)) +// \kempston_auto_fire_counter[5]~26 = CARRY((kempston_auto_fire_counter[5] & !\kempston_auto_fire_counter[4]~24 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[4]~24 ), + .combout(\kempston_auto_fire_counter[5]~25_combout ), + .cout(\kempston_auto_fire_counter[5]~26 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5]~25 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[5]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N25 +dffeas \kempston_auto_fire_counter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[5]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[5] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N26 +cycloneive_lcell_comb \kempston_auto_fire_counter[6]~27 ( +// Equation(s): +// \kempston_auto_fire_counter[6]~27_combout = (kempston_auto_fire_counter[6] & (!\kempston_auto_fire_counter[5]~26 )) # (!kempston_auto_fire_counter[6] & ((\kempston_auto_fire_counter[5]~26 ) # (GND))) +// \kempston_auto_fire_counter[6]~28 = CARRY((!\kempston_auto_fire_counter[5]~26 ) # (!kempston_auto_fire_counter[6])) + + .dataa(kempston_auto_fire_counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[5]~26 ), + .combout(\kempston_auto_fire_counter[6]~27_combout ), + .cout(\kempston_auto_fire_counter[6]~28 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6]~27 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[6]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N27 +dffeas \kempston_auto_fire_counter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[6]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[6] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N28 +cycloneive_lcell_comb \kempston_auto_fire_counter[7]~29 ( +// Equation(s): +// \kempston_auto_fire_counter[7]~29_combout = (kempston_auto_fire_counter[7] & (\kempston_auto_fire_counter[6]~28 $ (GND))) # (!kempston_auto_fire_counter[7] & (!\kempston_auto_fire_counter[6]~28 & VCC)) +// \kempston_auto_fire_counter[7]~30 = CARRY((kempston_auto_fire_counter[7] & !\kempston_auto_fire_counter[6]~28 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[6]~28 ), + .combout(\kempston_auto_fire_counter[7]~29_combout ), + .cout(\kempston_auto_fire_counter[7]~30 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7]~29 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[7]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N29 +dffeas \kempston_auto_fire_counter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[7]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[7] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \kempston_auto_fire_counter[8]~31 ( +// Equation(s): +// \kempston_auto_fire_counter[8]~31_combout = (kempston_auto_fire_counter[8] & (!\kempston_auto_fire_counter[7]~30 )) # (!kempston_auto_fire_counter[8] & ((\kempston_auto_fire_counter[7]~30 ) # (GND))) +// \kempston_auto_fire_counter[8]~32 = CARRY((!\kempston_auto_fire_counter[7]~30 ) # (!kempston_auto_fire_counter[8])) + + .dataa(kempston_auto_fire_counter[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[7]~30 ), + .combout(\kempston_auto_fire_counter[8]~31_combout ), + .cout(\kempston_auto_fire_counter[8]~32 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8]~31 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[8]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y13_N31 +dffeas \kempston_auto_fire_counter[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[8]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[8] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \kempston_auto_fire_counter[9]~33 ( +// Equation(s): +// \kempston_auto_fire_counter[9]~33_combout = (kempston_auto_fire_counter[9] & (\kempston_auto_fire_counter[8]~32 $ (GND))) # (!kempston_auto_fire_counter[9] & (!\kempston_auto_fire_counter[8]~32 & VCC)) +// \kempston_auto_fire_counter[9]~34 = CARRY((kempston_auto_fire_counter[9] & !\kempston_auto_fire_counter[8]~32 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[9]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[8]~32 ), + .combout(\kempston_auto_fire_counter[9]~33_combout ), + .cout(\kempston_auto_fire_counter[9]~34 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9]~33 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[9]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N1 +dffeas \kempston_auto_fire_counter[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[9]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[9] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \kempston_auto_fire_counter[10]~35 ( +// Equation(s): +// \kempston_auto_fire_counter[10]~35_combout = (kempston_auto_fire_counter[10] & (!\kempston_auto_fire_counter[9]~34 )) # (!kempston_auto_fire_counter[10] & ((\kempston_auto_fire_counter[9]~34 ) # (GND))) +// \kempston_auto_fire_counter[10]~36 = CARRY((!\kempston_auto_fire_counter[9]~34 ) # (!kempston_auto_fire_counter[10])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[9]~34 ), + .combout(\kempston_auto_fire_counter[10]~35_combout ), + .cout(\kempston_auto_fire_counter[10]~36 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10]~35 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[10]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N3 +dffeas \kempston_auto_fire_counter[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[10]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[10] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N4 +cycloneive_lcell_comb \kempston_auto_fire_counter[11]~37 ( +// Equation(s): +// \kempston_auto_fire_counter[11]~37_combout = (kempston_auto_fire_counter[11] & (\kempston_auto_fire_counter[10]~36 $ (GND))) # (!kempston_auto_fire_counter[11] & (!\kempston_auto_fire_counter[10]~36 & VCC)) +// \kempston_auto_fire_counter[11]~38 = CARRY((kempston_auto_fire_counter[11] & !\kempston_auto_fire_counter[10]~36 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[10]~36 ), + .combout(\kempston_auto_fire_counter[11]~37_combout ), + .cout(\kempston_auto_fire_counter[11]~38 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11]~37 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[11]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N5 +dffeas \kempston_auto_fire_counter[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[11]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[11] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \kempston_auto_fire_counter[12]~39 ( +// Equation(s): +// \kempston_auto_fire_counter[12]~39_combout = (kempston_auto_fire_counter[12] & (!\kempston_auto_fire_counter[11]~38 )) # (!kempston_auto_fire_counter[12] & ((\kempston_auto_fire_counter[11]~38 ) # (GND))) +// \kempston_auto_fire_counter[12]~40 = CARRY((!\kempston_auto_fire_counter[11]~38 ) # (!kempston_auto_fire_counter[12])) + + .dataa(kempston_auto_fire_counter[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[11]~38 ), + .combout(\kempston_auto_fire_counter[12]~39_combout ), + .cout(\kempston_auto_fire_counter[12]~40 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12]~39 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[12]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N7 +dffeas \kempston_auto_fire_counter[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[12]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[12] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N8 +cycloneive_lcell_comb \kempston_auto_fire_counter[13]~41 ( +// Equation(s): +// \kempston_auto_fire_counter[13]~41_combout = (kempston_auto_fire_counter[13] & (\kempston_auto_fire_counter[12]~40 $ (GND))) # (!kempston_auto_fire_counter[13] & (!\kempston_auto_fire_counter[12]~40 & VCC)) +// \kempston_auto_fire_counter[13]~42 = CARRY((kempston_auto_fire_counter[13] & !\kempston_auto_fire_counter[12]~40 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[12]~40 ), + .combout(\kempston_auto_fire_counter[13]~41_combout ), + .cout(\kempston_auto_fire_counter[13]~42 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13]~41 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[13]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N9 +dffeas \kempston_auto_fire_counter[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[13]~41_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[13] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N10 +cycloneive_lcell_comb \kempston_auto_fire_counter[14]~43 ( +// Equation(s): +// \kempston_auto_fire_counter[14]~43_combout = (kempston_auto_fire_counter[14] & (!\kempston_auto_fire_counter[13]~42 )) # (!kempston_auto_fire_counter[14] & ((\kempston_auto_fire_counter[13]~42 ) # (GND))) +// \kempston_auto_fire_counter[14]~44 = CARRY((!\kempston_auto_fire_counter[13]~42 ) # (!kempston_auto_fire_counter[14])) + + .dataa(kempston_auto_fire_counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[13]~42 ), + .combout(\kempston_auto_fire_counter[14]~43_combout ), + .cout(\kempston_auto_fire_counter[14]~44 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14]~43 .lut_mask = 16'h5A5F; +defparam \kempston_auto_fire_counter[14]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N11 +dffeas \kempston_auto_fire_counter[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[14]~43_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[14] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \kempston_auto_fire_counter[15]~45 ( +// Equation(s): +// \kempston_auto_fire_counter[15]~45_combout = (kempston_auto_fire_counter[15] & (\kempston_auto_fire_counter[14]~44 $ (GND))) # (!kempston_auto_fire_counter[15] & (!\kempston_auto_fire_counter[14]~44 & VCC)) +// \kempston_auto_fire_counter[15]~46 = CARRY((kempston_auto_fire_counter[15] & !\kempston_auto_fire_counter[14]~44 )) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[14]~44 ), + .combout(\kempston_auto_fire_counter[15]~45_combout ), + .cout(\kempston_auto_fire_counter[15]~46 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15]~45 .lut_mask = 16'hC30C; +defparam \kempston_auto_fire_counter[15]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \kempston_auto_fire_counter[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[15]~45_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[15] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \Equal2~3 ( +// Equation(s): +// \Equal2~3_combout = (!kempston_auto_fire_counter[14] & (!kempston_auto_fire_counter[15] & (!kempston_auto_fire_counter[13] & !kempston_auto_fire_counter[12]))) + + .dataa(kempston_auto_fire_counter[14]), + .datab(kempston_auto_fire_counter[15]), + .datac(kempston_auto_fire_counter[13]), + .datad(kempston_auto_fire_counter[12]), + .cin(gnd), + .combout(\Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~3 .lut_mask = 16'h0001; +defparam \Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \Equal2~2 ( +// Equation(s): +// \Equal2~2_combout = (!kempston_auto_fire_counter[8] & (!kempston_auto_fire_counter[9] & (!kempston_auto_fire_counter[11] & !kempston_auto_fire_counter[10]))) + + .dataa(kempston_auto_fire_counter[8]), + .datab(kempston_auto_fire_counter[9]), + .datac(kempston_auto_fire_counter[11]), + .datad(kempston_auto_fire_counter[10]), + .cin(gnd), + .combout(\Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~2 .lut_mask = 16'h0001; +defparam \Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N10 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!kempston_auto_fire_counter[0] & (!kempston_auto_fire_counter[1] & (!kempston_auto_fire_counter[3] & !kempston_auto_fire_counter[2]))) + + .dataa(kempston_auto_fire_counter[0]), + .datab(kempston_auto_fire_counter[1]), + .datac(kempston_auto_fire_counter[3]), + .datad(kempston_auto_fire_counter[2]), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N0 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!kempston_auto_fire_counter[4] & (!kempston_auto_fire_counter[5] & (!kempston_auto_fire_counter[6] & !kempston_auto_fire_counter[7]))) + + .dataa(kempston_auto_fire_counter[4]), + .datab(kempston_auto_fire_counter[5]), + .datac(kempston_auto_fire_counter[6]), + .datad(kempston_auto_fire_counter[7]), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0001; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \Equal2~4 ( +// Equation(s): +// \Equal2~4_combout = (\Equal2~3_combout & (\Equal2~2_combout & (\Equal2~0_combout & \Equal2~1_combout ))) + + .dataa(\Equal2~3_combout ), + .datab(\Equal2~2_combout ), + .datac(\Equal2~0_combout ), .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[4]~110_combout ), + .combout(\Equal2~4_combout ), .cout()); // synopsys translate_off -defparam \D[4]~110 .lut_mask = 16'hB8FF; -defparam \D[4]~110 .sum_lutc_input = "datac"; +defparam \Equal2~4 .lut_mask = 16'h8000; +defparam \Equal2~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N4 -cycloneive_lcell_comb \D[4]~111 ( +// Location: LCCOMB_X18_Y12_N14 +cycloneive_lcell_comb \kempston_auto_fire_counter[16]~47 ( // Equation(s): -// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) +// \kempston_auto_fire_counter[16]~47_combout = (kempston_auto_fire_counter[16] & (!\kempston_auto_fire_counter[15]~46 )) # (!kempston_auto_fire_counter[16] & ((\kempston_auto_fire_counter[15]~46 ) # (GND))) +// \kempston_auto_fire_counter[16]~48 = CARRY((!\kempston_auto_fire_counter[15]~46 ) # (!kempston_auto_fire_counter[16])) + + .dataa(gnd), + .datab(kempston_auto_fire_counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\kempston_auto_fire_counter[15]~46 ), + .combout(\kempston_auto_fire_counter[16]~47_combout ), + .cout(\kempston_auto_fire_counter[16]~48 )); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16]~47 .lut_mask = 16'h3C3F; +defparam \kempston_auto_fire_counter[16]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N15 +dffeas \kempston_auto_fire_counter[16] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[16]~47_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[16] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N16 +cycloneive_lcell_comb \kempston_auto_fire_counter[17]~49 ( +// Equation(s): +// \kempston_auto_fire_counter[17]~49_combout = \kempston_auto_fire_counter[16]~48 $ (!kempston_auto_fire_counter[17]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(kempston_auto_fire_counter[17]), + .cin(\kempston_auto_fire_counter[16]~48 ), + .combout(\kempston_auto_fire_counter[17]~49_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17]~49 .lut_mask = 16'hF00F; +defparam \kempston_auto_fire_counter[17]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X18_Y12_N17 +dffeas \kempston_auto_fire_counter[17] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire_counter[17]~49_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\kempston_autofire_enabled~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(kempston_auto_fire_counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \kempston_auto_fire_counter[17] .is_wysiwyg = "true"; +defparam \kempston_auto_fire_counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N26 +cycloneive_lcell_comb \kempston_auto_fire~0 ( +// Equation(s): +// \kempston_auto_fire~0_combout = \kempston_auto_fire~q $ (((\Equal2~4_combout & (!kempston_auto_fire_counter[16] & !kempston_auto_fire_counter[17])))) + + .dataa(\Equal2~4_combout ), + .datab(kempston_auto_fire_counter[16]), + .datac(\kempston_auto_fire~q ), + .datad(kempston_auto_fire_counter[17]), + .cin(gnd), + .combout(\kempston_auto_fire~0_combout ), + .cout()); +// synopsys translate_off +defparam \kempston_auto_fire~0 .lut_mask = 16'hF0D2; +defparam \kempston_auto_fire~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N27 +dffeas kempston_auto_fire( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\kempston_auto_fire~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\kempston_autofire_enabled~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\kempston_auto_fire~q ), + .prn(vcc)); +// synopsys translate_off +defparam kempston_auto_fire.is_wysiwyg = "true"; +defparam kempston_auto_fire.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \Selector6~2 ( +// Equation(s): +// \Selector6~2_combout = (\Selector14~18_combout & (((\kempston_auto_fire~q & \Selector14~17_combout )))) # (!\Selector14~18_combout & ((\ula_|zx_keyboard_|key_row[4]~16_combout ) # ((!\Selector14~17_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row[4]~16_combout ), + .datab(\Selector14~18_combout ), + .datac(\kempston_auto_fire~q ), + .datad(\Selector14~17_combout ), + .cin(gnd), + .combout(\Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~2 .lut_mask = 16'hE233; +defparam \Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~116 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[5][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~117_combout = (\ula_|zx_keyboard_|keys[5][4]~116_combout & ((\ula_|zx_keyboard_|keys[6][4]~114_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~114_combout & ((\ula_|zx_keyboard_|keys[5][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][4]~116_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~116_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~114_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~117 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N11 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [6])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~118 .lut_mask = 16'h4242; +defparam \ula_|zx_keyboard_|keys[4][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~119_combout = (\ula_|zx_keyboard_|keys[4][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~118_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~119 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~120_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~119_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~119_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~119_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~120 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N13 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[4]~17_combout = (\ula_|zx_keyboard_|keys[5][4]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][4]~q )))) # (!\ula_|zx_keyboard_|keys[5][4]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[4]~17 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~121_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~121 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~133 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~133_combout = (\ula_|zx_keyboard_|keys[3][4]~121_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~121_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~133 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[3][4]~133 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~122_combout = (\ula_|zx_keyboard_|keys[3][4]~133_combout & ((\ula_|zx_keyboard_|keys[3][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][4]~128_combout & +// (\ula_|zx_keyboard_|keys[3][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~133_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~133_combout ), + .datab(\ula_|zx_keyboard_|keys[3][4]~128_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~122 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N1 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~122_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hBBAA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~123 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~124_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~123_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~124 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~125_combout = (\ula_|zx_keyboard_|keys[2][4]~124_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~124_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~124_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~125 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \Selector6~3 ( +// Equation(s): +// \Selector6~3_combout = (\ula_|zx_keyboard_|keys[3][4]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][4]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][4]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\z80_|address_pins_|abus[10]~19_combout ), + .cin(gnd), + .combout(\Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~3 .lut_mask = 16'hDD0D; +defparam \Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~126_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~126 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y23_N31 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~127_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~127 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N19 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y23_N8 +cycloneive_lcell_comb \Selector6~4 ( +// Equation(s): +// \Selector6~4_combout = (\ula_|zx_keyboard_|keys[1][4]~q & (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[1][4]~q & +// (((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~4 .lut_mask = 16'hDD0D; +defparam \Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \Selector6~5 ( +// Equation(s): +// \Selector6~5_combout = ((\ula_|zx_keyboard_|key_row[4]~17_combout & (\Selector6~3_combout & \Selector6~4_combout ))) # (!\Selector14~17_combout ) + + .dataa(\ula_|zx_keyboard_|key_row[4]~17_combout ), + .datab(\Selector14~17_combout ), + .datac(\Selector6~3_combout ), + .datad(\Selector6~4_combout ), + .cin(gnd), + .combout(\Selector6~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~5 .lut_mask = 16'hB333; +defparam \Selector6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y34_N15 +cycloneive_io_ibuf \kempston[4]~input ( + .i(kempston[4]), + .ibar(gnd), + .o(\kempston[4]~input_o )); +// synopsys translate_off +defparam \kempston[4]~input .bus_hold = "false"; +defparam \kempston[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \Selector6~6 ( +// Equation(s): +// \Selector6~6_combout = (\Selector6~2_combout & ((\Selector14~18_combout & ((!\kempston[4]~input_o ))) # (!\Selector14~18_combout & (\Selector6~5_combout )))) + + .dataa(\Selector6~2_combout ), + .datab(\Selector6~5_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[4]~input_o ), + .cin(gnd), + .combout(\Selector6~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~6 .lut_mask = 16'h08A8; +defparam \Selector6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \Selector6~7 ( +// Equation(s): +// \Selector6~7_combout = (\Equal5~0_combout & (((\Selector6~6_combout )))) # (!\Equal5~0_combout & ((\Selector6~6_combout & (\Selector6~1_combout )) # (!\Selector6~6_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout +// ))))) + + .dataa(\Selector6~1_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector6~6_combout ), + .cin(gnd), + .combout(\Selector6~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~7 .lut_mask = 16'hEE30; +defparam \Selector6~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[4]~39 ( +// Equation(s): +// \D[4]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector6~7_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[4]~110_combout ), - .datad(\z80_|data_pins_|dout [4]), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), - .combout(\D[4]~111_combout ), + .combout(\D[4]~39_combout ), .cout()); // synopsys translate_off -defparam \D[4]~111 .lut_mask = 16'hF151; -defparam \D[4]~111 .sum_lutc_input = "datac"; +defparam \D[4]~39 .lut_mask = 16'hDD0D; +defparam \D[4]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N10 +// Location: LCCOMB_X26_Y16_N24 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & -// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~39_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) # (!\D[4]~39_combout & +// (((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[4]~18_combout )))) - .dataa(\D[4]~111_combout ), + .dataa(\D[4]~39_combout ), .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\z80_|bus_control_|db[4]~19_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), .cout()); @@ -51570,7 +51913,7 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N11 +// Location: FF_X26_Y16_N25 dffeas \z80_|data_pins_|dout[4] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), @@ -51589,145 +51932,3743 @@ defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y12_N18 +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~17 ( +// Equation(s): +// \z80_|bus_control_|db[4]~17_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [4]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~17 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( // Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|bus_control_|db[4]~18_combout = ((\z80_|bus_control_|db[4]~17_combout & ((\z80_|alu_control_|db[4]~31_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[4]~17_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[4]~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hDF55; defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( // Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~20_combout & \z80_|bus_control_|db[4]~18_combout ) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[4]~18_combout ), - .datac(\z80_|alu_control_|db[4]~33_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[3]~20_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~18_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N23 -dffeas \z80_|ir_|opcode[4] ( +// Location: FF_X27_Y12_N15 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[4]~19_combout ), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [4]), + .q(\z80_|interrupts_|im2~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( // Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|DFFE_inst44~q & \z80_|interrupts_|im2~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|sw1_|SYNTHESIZED_WIRE_2[1] ( +// Equation(s): +// \z80_|sw1_|SYNTHESIZED_WIRE_2 [1] = (\z80_|bus_control_|db[1]~10_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~10_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~4_combout ), + .cin(gnd), + .combout(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .lut_mask = 16'hC8CC; +defparam \z80_|sw1_|SYNTHESIZED_WIRE_2[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~3_combout = (\z80_|reg_file_|gdfx_temp0[1]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (!\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_out_lo~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~33_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~3 .lut_mask = 16'hF2F0; +defparam \z80_|reg_file_|db_lo_ds[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~20 ( +// Equation(s): +// \z80_|alu_control_|db[1]~20_combout = (\z80_|alu_control_|db[2]~19_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|alu_control_|db[2]~19_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~20 .lut_mask = 16'h88CC; +defparam \z80_|alu_control_|db[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~21 ( +// Equation(s): +// \z80_|alu_control_|db[1]~21_combout = (\z80_|reg_file_|db_lo_ds[1]~3_combout & (\z80_|alu_control_|db[1]~20_combout & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_sw_2u~8_combout )))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~3_combout ), + .datab(\z80_|execute_|ctl_sw_2u~8_combout ), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|db[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~21 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~22 ( +// Equation(s): +// \z80_|alu_control_|db[1]~22_combout = ((\z80_|alu_control_|db[1]~21_combout & ((\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|sw1_|SYNTHESIZED_WIRE_2 [1]), + .datab(\z80_|alu_control_|db[1]~21_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~22 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~9 ( +// Equation(s): +// \z80_|bus_control_|db[1]~9_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|alu_control_|db[1]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout ))) + + .dataa(\z80_|alu_control_|db[1]~22_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[0]~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~9 .lut_mask = 16'hA0F0; +defparam \z80_|bus_control_|db[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0003; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[5][1]~33_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~2_combout = (\ula_|zx_keyboard_|keys[5][1]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # ((!\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~2 .lut_mask = 16'hC4F5; +defparam \ula_|zx_keyboard_|key_row[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N1 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & (\ula_|zx_keyboard_|keys[2][1]~q )))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N5 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~1_combout = (\z80_|address_pins_|abus[10]~19_combout & (((\z80_|address_pins_|abus[11]~18_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~q ))) # (!\z80_|address_pins_|abus[10]~19_combout & (!\ula_|zx_keyboard_|keys[2][1]~q +// & ((\z80_|address_pins_|abus[11]~18_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~1 .lut_mask = 16'hA2F3; +defparam \ula_|zx_keyboard_|key_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~38 .lut_mask = 16'h0004; +defparam \ula_|zx_keyboard_|keys[7][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg +// [1] & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0210; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr16~2_combout )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h8B88; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & ((\ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hE2C0; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~39_combout = (\ula_|zx_keyboard_|keys[7][1]~38_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|WideOr16~6_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) # +// (!\ula_|zx_keyboard_|keys[7][1]~38_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~38_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~39 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~39_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hFCCC; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~42_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~41_combout )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & (!\ula_|zx_keyboard_|keys[6][1]~40_combout )) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & ((\ula_|zx_keyboard_|keys[6][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N29 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~3_combout = (\z80_|address_pins_|abus[15]~23_combout & (((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\z80_|address_pins_|abus[15]~23_combout & (!\ula_|zx_keyboard_|keys[7][1]~q +// & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~q ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~3 .lut_mask = 16'hB0BB; +defparam \ula_|zx_keyboard_|key_row[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y20_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & (!\ula_|zx_keyboard_|keys[0][1]~12_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][4]~18_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y21_N25 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1]~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[1]~0_combout = (\z80_|address_pins_|abus[9]~16_combout & ((\z80_|address_pins_|abus[8]~17_combout ) # ((!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\z80_|address_pins_|abus[9]~16_combout & (!\ula_|zx_keyboard_|keys[1][1]~q & +// ((\z80_|address_pins_|abus[8]~17_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~16_combout ), + .datab(\z80_|address_pins_|abus[8]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1]~0 .lut_mask = 16'h8ACF; +defparam \ula_|zx_keyboard_|key_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[1] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [1] = (\ula_|zx_keyboard_|key_row[1]~2_combout & (\ula_|zx_keyboard_|key_row[1]~1_combout & (\ula_|zx_keyboard_|key_row[1]~3_combout & \ula_|zx_keyboard_|key_row[1]~0_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[1]~2_combout ), + .datab(\ula_|zx_keyboard_|key_row[1]~1_combout ), + .datac(\ula_|zx_keyboard_|key_row[1]~3_combout ), + .datad(\ula_|zx_keyboard_|key_row[1]~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [1]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[1] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y34_N1 +cycloneive_io_ibuf \kempston[2]~input ( + .i(kempston[2]), + .ibar(gnd), + .o(\kempston[2]~input_o )); +// synopsys translate_off +defparam \kempston[2]~input .bus_hold = "false"; +defparam \kempston[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \Selector12~4 ( +// Equation(s): +// \Selector12~4_combout = (\Selector14~17_combout & ((\Selector14~18_combout & ((!\kempston[2]~input_o ))) # (!\Selector14~18_combout & (\ula_|zx_keyboard_|key_row [1])))) # (!\Selector14~17_combout & (((!\Selector14~18_combout )))) + + .dataa(\ula_|zx_keyboard_|key_row [1]), + .datab(\Selector14~17_combout ), + .datac(\Selector14~18_combout ), + .datad(\kempston[2]~input_o ), + .cin(gnd), + .combout(\Selector12~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~4 .lut_mask = 16'h0BCB; +defparam \Selector12~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \Selector12~10 ( +// Equation(s): +// \Selector12~10_combout = (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector12~10_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~10 .lut_mask = 16'hFFCF; +defparam \Selector12~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \Selector12~7 ( +// Equation(s): +// \Selector12~7_combout = (\Selector12~4_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\Selector12~4_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\Selector12~4_combout ), + .cin(gnd), + .combout(\Selector12~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~7 .lut_mask = 16'hEEF0; +defparam \Selector12~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \Selector12~8 ( +// Equation(s): +// \Selector12~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\Selector12~7_combout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(gnd), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\Selector12~7_combout ), + .cin(gnd), + .combout(\Selector12~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~8 .lut_mask = 16'hAFA0; +defparam \Selector12~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \Selector12~9 ( +// Equation(s): +// \Selector12~9_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\Selector12~8_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a +// [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\Selector12~8_combout ), + .cin(gnd), + .combout(\Selector12~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~9 .lut_mask = 16'hFE0E; +defparam \Selector12~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \Selector12~15 ( +// Equation(s): +// \Selector12~15_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~15_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~15 .lut_mask = 16'hF2D0; +defparam \Selector12~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \Selector12~5 ( +// Equation(s): +// \Selector12~5_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \Selector12~15_combout )) # (!\Selector12~4_combout ))) + + .dataa(\Equal5~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\Selector12~4_combout ), + .datad(\Selector12~15_combout ), + .cin(gnd), + .combout(\Selector12~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~5 .lut_mask = 16'hB5A5; +defparam \Selector12~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~12_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \Selector12~14 ( +// Equation(s): +// \Selector12~14_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\Selector12~14_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~14 .lut_mask = 16'hF2D0; +defparam \Selector12~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \Selector12~6 ( +// Equation(s): +// \Selector12~6_combout = (\Selector12~5_combout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\Selector12~4_combout & \Selector12~14_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\Selector12~4_combout ), + .datac(\Selector12~5_combout ), + .datad(\Selector12~14_combout ), + .cin(gnd), + .combout(\Selector12~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~6 .lut_mask = 16'hF8F0; +defparam \Selector12~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \Selector12~11 ( +// Equation(s): +// \Selector12~11_combout = (\Selector12~6_combout & ((\Selector12~4_combout ) # ((\Selector12~10_combout & \Selector12~9_combout )))) + + .dataa(\Selector12~4_combout ), + .datab(\Selector12~10_combout ), + .datac(\Selector12~9_combout ), + .datad(\Selector12~6_combout ), + .cin(gnd), + .combout(\Selector12~11_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~11 .lut_mask = 16'hEA00; +defparam \Selector12~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[1]~12 ( +// Equation(s): +// \D[1]~12_combout = (\Equal5~1_combout & (\Selector12~11_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout +// )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\Selector12~11_combout ), + .cin(gnd), + .combout(\D[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~12 .lut_mask = 16'hCF45; +defparam \D[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~12_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[1]~10_combout )))) # (!\D[1]~12_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[1]~10_combout ))) + + .dataa(\D[1]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[1]~10_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N17 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = ((\z80_|bus_control_|db[1]~9_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[1]~9_combout ), + .datab(\z80_|bus_control_|db[0]~5_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [1]), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB3B; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[1]~10_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(\z80_|ir_|opcode [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h00AA; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal1~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal1~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|iff1~q ))))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal79~0_combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N12 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFCF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y7_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal1~7_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y7_N26 +// Location: LCCOMB_X29_Y17_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) +// \z80_|interrupts_|test1~2_combout = ((\z80_|ir_|opcode [5] & ((!\z80_|pla_decode_|Equal3~1_combout ))) # (!\z80_|ir_|opcode [5] & (!\z80_|pla_decode_|Equal2~2_combout ))) # (!\z80_|pla_decode_|Equal2~3_combout ) - .dataa(\z80_|pla_decode_|Equal36~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal43~0_combout ), + .dataa(\z80_|pla_decode_|Equal2~2_combout ), + .datab(\z80_|pla_decode_|Equal2~3_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|ir_|opcode [5]), .cin(gnd), .combout(\z80_|interrupts_|test1~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h3F77; defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N30 +// Location: LCCOMB_X29_Y14_N14 cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) +// \z80_|interrupts_|test1~3_combout = (\z80_|interrupts_|test1~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & ((!\z80_|pla_decode_|Equal3~2_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|interrupts_|test1~2_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~53_combout ), + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal3~2_combout ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|test1~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h002A; defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N7 +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|interrupts_|test1~4 ( +// Equation(s): +// \z80_|interrupts_|test1~4_combout = (!\z80_|execute_|setM1~55_combout & ((\z80_|interrupts_|test1~3_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~4 .lut_mask = 16'h3323; +defparam \z80_|interrupts_|test1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N1 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_inst44~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(gnd), + .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datac(\z80_|clk_delay_|DFF_inst5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0303; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N9 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|execute_|setM1~55_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h5000; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N11 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~2 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~3 ( +// Equation(s): +// \z80_|bus_control_|db[0]~3_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~2_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~2_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~3 .lut_mask = 16'hAEAF; +defparam \z80_|bus_control_|db[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \Selector8~5 ( +// Equation(s): +// \Selector8~5_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~5_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~5 .lut_mask = 16'hCBC8; +defparam \Selector8~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \Selector8~6 ( +// Equation(s): +// \Selector8~6_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~5_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~5_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~5_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~5_combout ), + .cin(gnd), + .combout(\Selector8~6_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~6 .lut_mask = 16'hF388; +defparam \Selector8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~38_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \Selector8~7 ( +// Equation(s): +// \Selector8~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # (\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\Selector8~7_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~7 .lut_mask = 16'hAEA4; +defparam \Selector8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \Selector8~8 ( +// Equation(s): +// \Selector8~8_combout = (\Selector8~7_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ) # ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\Selector8~7_combout & +// (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout & \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datac(\Selector8~7_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\Selector8~8_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~8 .lut_mask = 16'hACF0; +defparam \Selector8~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~134_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[0][0]~13_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [3]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~112_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~134 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~135_combout = (\ula_|zx_keyboard_|keys[6][3]~134_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~134_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~134_combout ), + .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hB1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N15 +dffeas \ula_|zx_keyboard_|keys[6][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][3]~135_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~59_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~59_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y20_N9 +dffeas \ula_|zx_keyboard_|keys[7][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~15_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\ula_|zx_keyboard_|keys[6][3]~q +// & ((\z80_|address_pins_|abus[15]~23_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\z80_|address_pins_|abus[15]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~15 .lut_mask = 16'hBB0B; +defparam \ula_|zx_keyboard_|key_row[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[0][3]~94_combout & ((!\ula_|zx_keyboard_|keys[2][4]~93_combout ))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & +// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N27 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~12_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~17_combout & ((\z80_|address_pins_|abus[9]~16_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// ((\z80_|address_pins_|abus[9]~16_combout ) # ((!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[9]~16_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[8]~17_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~12 .lut_mask = 16'hCF45; +defparam \ula_|zx_keyboard_|key_row[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y23_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h00A0; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~46_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~46_combout & (\ula_|zx_keyboard_|keys[3][3]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datab(\ula_|zx_keyboard_|keys[3][3]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y23_N23 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0180; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[2][3]~100_combout & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h00C0; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[2][3]~101_combout & ((\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|zx_keyboard_|keys[2][3]~99_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & +// ((\ula_|zx_keyboard_|keys[2][3]~q ))))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N15 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~13_combout = (\ula_|zx_keyboard_|keys[3][3]~q & (\z80_|address_pins_|abus[11]~18_combout & ((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[3][3]~q & +// (((\z80_|address_pins_|abus[10]~19_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\z80_|address_pins_|abus[10]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~13 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y20_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[3][0]~76_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~131_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|Selector5~1_combout ), + .datad(\ula_|zx_keyboard_|Selector5~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~131 .lut_mask = 16'hFF20; +defparam \ula_|zx_keyboard_|keys[4][3]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~105_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~131_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[4][3]~131_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hB888; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|shifted~q & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hCCDC; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y22_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[4][3]~106_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & ((!\ula_|zx_keyboard_|keys[4][3]~132_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~132_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y22_N9 +dffeas \ula_|zx_keyboard_|keys[4][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~103_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N21 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row[3]~14_combout = (\ula_|zx_keyboard_|keys[4][3]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~q & +// (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~q ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[5][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3]~14 .lut_mask = 16'hD0DD; +defparam \ula_|zx_keyboard_|key_row[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y23_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row[3] ( +// Equation(s): +// \ula_|zx_keyboard_|key_row [3] = (\ula_|zx_keyboard_|key_row[3]~15_combout & (\ula_|zx_keyboard_|key_row[3]~12_combout & (\ula_|zx_keyboard_|key_row[3]~13_combout & \ula_|zx_keyboard_|key_row[3]~14_combout ))) + + .dataa(\ula_|zx_keyboard_|key_row[3]~15_combout ), + .datab(\ula_|zx_keyboard_|key_row[3]~12_combout ), + .datac(\ula_|zx_keyboard_|key_row[3]~13_combout ), + .datad(\ula_|zx_keyboard_|key_row[3]~14_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row [3]), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row[3] .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|key_row[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y34_N1 +cycloneive_io_ibuf \kempston[0]~input ( + .i(kempston[0]), + .ibar(gnd), + .o(\kempston[0]~input_o )); +// synopsys translate_off +defparam \kempston[0]~input .bus_hold = "false"; +defparam \kempston[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \Selector8~4 ( +// Equation(s): +// \Selector8~4_combout = (\Selector14~18_combout & (\Selector14~17_combout & ((!\kempston[0]~input_o )))) # (!\Selector14~18_combout & (((\ula_|zx_keyboard_|key_row [3])) # (!\Selector14~17_combout ))) + + .dataa(\Selector14~18_combout ), + .datab(\Selector14~17_combout ), + .datac(\ula_|zx_keyboard_|key_row [3]), + .datad(\kempston[0]~input_o ), + .cin(gnd), + .combout(\Selector8~4_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~4 .lut_mask = 16'h51D9; +defparam \Selector8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \Selector8~9 ( +// Equation(s): +// \Selector8~9_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & (\Selector8~6_combout )) # (!\Selector8~4_combout & ((\Selector8~8_combout ))))) + + .dataa(\Selector8~6_combout ), + .datab(\Equal5~0_combout ), + .datac(\Selector8~8_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\Selector8~9_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~9 .lut_mask = 16'hEE30; +defparam \Selector8~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[3]~38 ( +// Equation(s): +// \D[3]~38_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\Selector8~9_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), + .cin(gnd), + .combout(\D[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~38 .lut_mask = 16'hDD0D; +defparam \D[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\D[3]~38_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout & \z80_|bus_control_|db[3]~20_combout )))) # (!\D[3]~38_combout & +// (\z80_|execute_|ctl_bus_db_we~8_combout & (\z80_|bus_control_|db[3]~20_combout ))) + + .dataa(\D[3]~38_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N31 +dffeas \z80_|data_pins_|dout[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~19 ( +// Equation(s): +// \z80_|bus_control_|db[3]~19_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~19 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( +// Equation(s): +// \z80_|bus_control_|db[3]~20_combout = ((\z80_|bus_control_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[3]~19_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|bus_control_|db[0]~5_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|ir_|opcode[3]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[3]~feeder_combout = \z80_|bus_control_|db[3]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N13 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|ir_|opcode[3]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~2_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = (!\z80_|execute_|ctl_alu_op_low~11_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|pla_decode_|Equal56~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|setM1~41_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~60 ( +// Equation(s): +// \z80_|execute_|setM1~60_combout = (\z80_|execute_|ctl_mRead~17_combout & (((\z80_|ir_|opcode [1]) # (\z80_|ir_|opcode [2])) # (!\z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|setM1~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~60 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|setM1~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~60_combout ) # (!\z80_|execute_|setM1~42_combout )) # (!\z80_|execute_|nextM~4_combout ))) + + .dataa(\z80_|execute_|nextM~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~60_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~17 ( +// Equation(s): +// \z80_|execute_|nextM~17_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~13_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|fMRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~17 .lut_mask = 16'hA020; +defparam \z80_|execute_|nextM~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = (((\z80_|pla_decode_|Equal49~0_combout & \z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|ixy_d~15_combout )) # (!\z80_|execute_|nextM~5_combout ) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|execute_|nextM~5_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = ((\z80_|execute_|nextM~7_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|nextM~16_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|nextM~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout +// ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'h44F4; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hA080; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = (\z80_|execute_|nextM~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|nextM~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|nextM~11_combout ) # (!\z80_|execute_|nextM~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|nextM~12_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~17_combout ) # ((\z80_|execute_|nextM~8_combout ) # (\z80_|execute_|nextM~13_combout )) + + .dataa(\z80_|execute_|nextM~17_combout ), + .datab(gnd), + .datac(\z80_|execute_|nextM~8_combout ), + .datad(\z80_|execute_|nextM~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|execute_|nextM~6_combout ) # (((\z80_|execute_|nextM~14_combout ) # (!\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ctl_mWrite~15_combout )) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mRead~27_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|execute_|nextM~15_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|setM1~55_combout )) + + .dataa(\z80_|execute_|nextM~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h1010; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y11_N23 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF0FC; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N17 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N14 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y11_N25 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|nmi_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -51736,7 +55677,7 @@ dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), + .ena(\z80_|interrupts_|test1~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), @@ -51746,115 +55687,363 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X26_Y11_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|interrupts_|im1~feeder ( // Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) +// \z80_|interrupts_|im1~feeder_combout = \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), + .combout(\z80_|interrupts_|im1~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|im1~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|im1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & -// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_flags_alu~19_combout ), - .datac(\z80_|alu_control_|db[5]~17_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y10_N3 -dffeas \z80_|alu_flags_|flags_yf ( +// Location: FF_X27_Y12_N9 +dffeas \z80_|interrupts_|im1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .d(\z80_|interrupts_|im1~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .ena(\z80_|execute_|ctl_im_we~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), + .q(\z80_|interrupts_|im1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( // Equation(s): -// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & -// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - .dataa(\z80_|alu_control_|out[6]~2_combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_flags_|flags_yf~q ), - .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .dataa(\z80_|interrupts_|im1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|interrupts_|im2~q ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'h8C88; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( // Equation(s): -// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~4_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|alu_control_|db[5]~15_combout ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~4_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~16_combout ), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; -defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~5 ( // Equation(s): -// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) +// \z80_|bus_control_|db[0]~5_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_zero_oe~3_combout ))) - .dataa(\z80_|alu_control_|db[5]~16_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_control_|db[6]~13_combout ), - .datad(\z80_|alu_|db[5]~24_combout ), + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_zero_oe~3_combout ), .cin(gnd), - .combout(\z80_|alu_control_|db[5]~17_combout ), + .combout(\z80_|bus_control_|db[0]~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; -defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +defparam \z80_|bus_control_|db[0]~5 .lut_mask = 16'hFFFE; +defparam \z80_|bus_control_|db[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y24_N0 +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hEE30; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51862,16 +56051,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -51925,7 +56114,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y33_N0 +// Location: M9K_X33_Y6_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -51935,16 +56124,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -51983,9 +56172,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -51993,16 +56182,16 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portadatain({\D[5]~40_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain({\~GND~combout }), .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], @@ -52055,7 +56244,7 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; // synopsys translate_on -// Location: M9K_X33_Y6_N0 +// Location: M9K_X33_Y33_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -52065,16 +56254,16 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~18_combout ,\z80_|address_pins_|abus[10]~19_combout ,\z80_|address_pins_|abus[9]~16_combout ,\z80_|address_pins_|abus[8]~17_combout ,\z80_|address_pins_|abus[7]~26_combout , +\z80_|address_pins_|abus[6]~25_combout ,\z80_|address_pins_|abus[5]~31_combout ,\z80_|address_pins_|abus[4]~30_combout ,\z80_|address_pins_|abus[3]~29_combout ,\z80_|address_pins_|abus[2]~28_combout ,\z80_|address_pins_|abus[1]~27_combout , +\z80_|address_pins_|abus[0]~24_combout }), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -52113,361 +56302,112 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N2 -cycloneive_lcell_comb \Mux2~0 ( +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \Selector4~0 ( // Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), .cin(gnd), - .combout(\Mux2~0_combout ), + .combout(\Selector4~0_combout ), .cout()); // synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hB9A8; -defparam \Mux2~0 .sum_lutc_input = "datac"; +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \Mux2~1 ( +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \Selector4~1 ( // Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) +// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Selector4~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), + .datad(\Selector4~0_combout ), .cin(gnd), - .combout(\Mux2~1_combout ), + .combout(\Selector4~1_combout ), .cout()); // synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; +defparam \Selector4~1 .lut_mask = 16'hDDA0; +defparam \Selector4~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \D[5]~25 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) +// \D[5]~25_combout = (!\Equal5~0_combout & ((\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|abus[15]~23_combout & ((\Selector4~1_combout ))))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\Equal5~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datad(\Selector4~1_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .combout(\D[5]~25_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +defparam \D[5]~25 .lut_mask = 16'h3120; +defparam \D[5]~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~113_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X24_Y18_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \D[5]~27 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) +// \D[5]~27_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~25_combout )) # (!\D[5]~26_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~25_combout ) # (!\D[5]~26_combout )))) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~26_combout ), + .datac(\D[5]~25_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .combout(\D[5]~27_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +defparam \D[5]~27 .lut_mask = 16'hA2F3; +defparam \D[5]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N30 -cycloneive_lcell_comb \D[5]~112 ( +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \D[5]~40 ( // Equation(s): -// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) +// \D[5]~40_combout = (\D[5]~27_combout ) # (!\D[0]~49_combout ) - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\D[5]~97_combout ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .dataa(gnd), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[5]~27_combout ), .cin(gnd), - .combout(\D[5]~112_combout ), + .combout(\D[5]~40_combout ), .cout()); // synopsys translate_off -defparam \D[5]~112 .lut_mask = 16'hFB73; -defparam \D[5]~112 .sum_lutc_input = "datac"; +defparam \D[5]~40 .lut_mask = 16'hFF33; +defparam \D[5]~40 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N8 -cycloneive_lcell_comb \D[5]~113 ( -// Equation(s): -// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[5]~112_combout ), - .datad(\z80_|data_pins_|dout [5]), - .cin(gnd), - .combout(\D[5]~113_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~113 .lut_mask = 16'hF151; -defparam \D[5]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 +// Location: LCCOMB_X26_Y16_N18 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~40_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[5]~16_combout & \z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\D[5]~40_combout & (\z80_|bus_control_|db[5]~16_combout +// & (\z80_|execute_|ctl_bus_db_we~8_combout ))) - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[5]~113_combout ), + .dataa(\D[5]~40_combout ), + .datab(\z80_|bus_control_|db[5]~16_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y12_N25 +// Location: FF_X26_Y16_N19 dffeas \z80_|data_pins_|dout[5] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), @@ -52486,50 +56426,50 @@ defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y12_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|data_pins_|dout [5]), - .datac(\z80_|bus_control_|db[0]~4_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N24 +// Location: LCCOMB_X26_Y15_N16 cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[5]~15_combout = (\z80_|bus_control_|db[0]~3_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|alu_control_|db[5]~17_combout ), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|bus_control_|db[5]~14_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .dataa(\z80_|bus_control_|db[0]~3_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [5]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[5]~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hA0AA; defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y12_N25 +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~16 ( +// Equation(s): +// \z80_|bus_control_|db[5]~16_combout = ((\z80_|bus_control_|db[5]~15_combout & ((\z80_|alu_control_|db[5]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~8_combout )))) # (!\z80_|bus_control_|db[0]~5_combout ) + + .dataa(\z80_|bus_control_|db[0]~5_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|alu_control_|db[5]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~16 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N21 dffeas \z80_|ir_|opcode[5] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[5]~15_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~16_combout ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~17_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|ir_|opcode [5]), @@ -52539,991 +56479,75 @@ defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) - - .dataa(gnd), .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) - - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|execute_|nextM~3_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|ixy_d~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~2_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~34_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), - .datab(\z80_|execute_|nextM~11_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|nextM~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) - - .dataa(\z80_|execute_|nextM~7_combout ), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) - - .dataa(\z80_|execute_|nextM~5_combout ), - .datab(\z80_|execute_|nextM~13_combout ), - .datac(\z80_|execute_|ctl_mRead~28_combout ), - .datad(\z80_|execute_|ctl_mWrite~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N23 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N27 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N31 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y13_N21 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # -// (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_iorw~11_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal1~1_combout & (\z80_|pla_decode_|Equal1~0_combout & \z80_|ir_|opcode [3]))) - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|execute_|setM1~22_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal1~1_combout ), + .datac(\z80_|pla_decode_|Equal1~0_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|pla_decode_|Equal4~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y9_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|fMWrite~0_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) - - .dataa(\z80_|execute_|setM1~55_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y8_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~34_combout ), - .datab(\z80_|execute_|setM1~11_combout ), - .datac(\z80_|execute_|ctl_mRead~3_combout ), - .datad(\z80_|execute_|ctl_mRead~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) - - .dataa(\z80_|execute_|setM1~56_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|setM1~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~31_combout ), - .datac(\z80_|execute_|setM1~32_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|execute_|setM1~20_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~28_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|execute_|setM1~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & -// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~2_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal77~1_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|interrupts_|test1~2_combout ), - .datab(\z80_|execute_|setM1~15_combout ), - .datac(\z80_|execute_|setM1~14_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|fMWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|nextM~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~17_combout ), - .datac(\z80_|execute_|setM1~11_combout ), - .datad(\z80_|execute_|setM1~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) - - .dataa(\z80_|execute_|setM1~8_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) - - .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~12_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y8_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N16 +// Location: LCCOMB_X31_Y15_N8 cycloneive_lcell_comb \z80_|execute_|setM1~43 ( // Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|setM1~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h1515; defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y8_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y8_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|setM1~42_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal2~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal1~4_combout ), - .datad(\z80_|execute_|setM1~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) - - .dataa(\z80_|execute_|setM1~45_combout ), - .datab(\z80_|execute_|setM1~47_combout ), - .datac(\z80_|execute_|setM1~50_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 +// Location: LCCOMB_X36_Y11_N28 cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (!\z80_|execute_|nextM~15_combout & (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~55_combout )) - .dataa(gnd), + .dataa(\z80_|execute_|nextM~15_combout ), .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~53_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h4040; defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N19 +// Location: FF_X36_Y11_N29 dffeas \z80_|sequencer_|T6 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), @@ -53542,59 +56566,625 @@ defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; defparam \z80_|sequencer_|T6 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( // Equation(s): -// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & -// (!\z80_|execute_|setM1~41_combout ))) +// \z80_|execute_|setM1~16_combout = (!\z80_|execute_|ctl_alu_oe~5_combout & (!\z80_|pla_decode_|Equal1~3_combout & (!\z80_|pla_decode_|Equal77~1_combout & !\z80_|pla_decode_|Equal2~4_combout ))) - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|sequencer_|T6~q ), - .datac(\z80_|execute_|setM1~41_combout ), - .datad(\z80_|execute_|setM1~40_combout ), + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|pla_decode_|Equal1~3_combout ), + .datac(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|pla_decode_|Equal2~4_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), + .combout(\z80_|execute_|setM1~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N16 +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|interrupts_|test1~3_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~17_combout )) + + .dataa(\z80_|interrupts_|test1~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal13~3_combout )))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal13~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h080C; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~13_combout & (\z80_|execute_|setM1~45_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~13_combout ), + .datac(\z80_|execute_|setM1~45_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h1000; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_sw_4d~9_combout & (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|pla_decode_|Equal5~2_combout & \z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|pla_decode_|Equal5~2_combout ), + .datad(\z80_|execute_|setM1~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N2 cycloneive_lcell_comb \z80_|execute_|setM1~53 ( // Equation(s): -// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & (\z80_|execute_|setM1~18_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|setM1~48_combout ))) - .dataa(\z80_|execute_|setM1~35_combout ), - .datab(\z80_|execute_|setM1~19_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~18_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~48_combout ), .cin(gnd), .combout(\z80_|execute_|setM1~53_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h8000; defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) +// \z80_|execute_|setM1~54_combout = (\z80_|execute_|setM1~43_combout & (((\z80_|execute_|setM1~42_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~43_combout & ((\z80_|sequencer_|T6~q ) # ((\z80_|execute_|setM1~42_combout & +// \z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'hCCCE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~24_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|setM1~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hE0A0; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|fMWrite~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|setM1~57_combout & (((\z80_|execute_|ctl_reg_in_hi~6_combout & !\z80_|execute_|setM1~25_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~57_combout & +// (\z80_|execute_|ctl_reg_in_hi~6_combout & (!\z80_|execute_|setM1~25_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'h0CAE; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (((\z80_|pla_decode_|Equal40~1_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~8_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|alu_control_|flags_cond_true~q & (!\z80_|execute_|ctl_mRead~10_combout & ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) # (!\z80_|alu_control_|flags_cond_true~q & +// ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|setM1~26_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~29_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|ctl_reg_in_hi~6_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ixy_d~4_combout & \z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~6_combout & +// (\z80_|execute_|ixy_d~4_combout & (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~6_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hCCDC; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~13_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (((\z80_|execute_|setM1~31_combout & \z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|setM1~32_combout )) # (!\z80_|execute_|setM1~58_combout ) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~32_combout ), + .datac(\z80_|execute_|setM1~31_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hF777; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (\z80_|execute_|setM1~34_combout ) # ((\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|setM1~35_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~34_combout ), + .datac(\z80_|execute_|setM1~35_combout ), + .datad(\z80_|execute_|setM1~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_iorw~11_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|execute_|ctl_mRead~9_combout & (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'h2A0A; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout ) # ((\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|setM1~36_combout ) # ((\z80_|execute_|setM1~56_combout ) # (\z80_|execute_|setM1~23_combout ))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|setM1~56_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = (\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mWrite~18_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMWrite~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~12_combout ) # (((\z80_|execute_|ctl_mWrite~19_combout & \z80_|execute_|setM1~13_combout )) # (!\z80_|execute_|nextM~4_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~19_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|setM1~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|sequencer_|M5~q ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|execute_|ctl_sw_4d~9_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|DFFE_M4_ff~q & +// (!\z80_|execute_|ctl_sw_4d~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_sw_4d~9_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hCF0F; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|execute_|setM1~11_combout ) # (((\z80_|execute_|setM1~14_combout & \z80_|execute_|ixy_d~4_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) + + .dataa(\z80_|execute_|setM1~14_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|setM1~19_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (\z80_|execute_|ctl_alu_op_low~32_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~15_combout ) # (((!\z80_|execute_|setM1~18_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~20_combout )) + + .dataa(\z80_|execute_|setM1~15_combout ), + .datab(\z80_|execute_|setM1~20_combout ), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hBFBB; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|setM1~37_combout & (!\z80_|execute_|setM1~21_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~54_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'h000B; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~15_combout ))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(gnd), .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .datad(\z80_|execute_|nextM~15_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N15 +// Location: FF_X36_Y11_N7 dffeas \z80_|sequencer_|DFFE_M1_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), @@ -53613,27 +57203,28 @@ defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|resets_|clrpc_int~q & ((!\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|resets_|clrpc_int~q & +// (!\z80_|resets_|x1~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|resets_|x1~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hC1F0; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N29 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), +// Location: FF_X27_Y15_N23 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53642,65 +57233,156 @@ dffeas \z80_|sequencer_|DFFE_M2_ff ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .q(\z80_|resets_|clrpc_int~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(gnd), .datac(gnd), - .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y16_N20 +// Location: FF_X26_Y9_N3 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N5 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y9_N1 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y16_N21 +// Location: FF_X29_Y9_N17 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53719,332 +57401,561 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N30 -cycloneive_lcell_comb \D[0]~66 ( +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 ( // Equation(s): -// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[0]~58_combout ), - .datad(\D[0]~120_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~66_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cout()); // synopsys translate_off -defparam \D[0]~66 .lut_mask = 16'hF3C0; -defparam \D[0]~66 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N18 -cycloneive_lcell_comb \D[0]~67 ( +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 ( // Equation(s): -// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\Equal2~1_combout ), - .datad(\D[0]~66_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2_combout ), .cin(gnd), - .combout(\D[0]~67_combout ), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), .cout()); // synopsys translate_off -defparam \D[0]~67 .lut_mask = 16'hDD0D; -defparam \D[0]~67 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .lut_mask = 16'hF388; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N24 -cycloneive_lcell_comb \D[0]~121 ( +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \Selector14~15 ( // Equation(s): -// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \Selector14~15_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) # +// (!\z80_|address_pins_|abus[14]~22_combout & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) - .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .cin(gnd), - .combout(\D[0]~121_combout ), + .combout(\Selector14~15_combout ), .cout()); // synopsys translate_off -defparam \D[0]~121 .lut_mask = 16'hFF20; -defparam \D[0]~121 .sum_lutc_input = "datac"; +defparam \Selector14~15 .lut_mask = 16'hBA98; +defparam \Selector14~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N16 -cycloneive_lcell_comb \D[1]~68 ( +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \Selector14~16 ( // Equation(s): -// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) +// \Selector14~16_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector14~15_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\Selector14~15_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector14~15_combout )))) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[1]~34_combout ), - .datad(\D[1]~118_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\Selector14~15_combout ), .cin(gnd), - .combout(\D[1]~68_combout ), + .combout(\Selector14~16_combout ), .cout()); // synopsys translate_off -defparam \D[1]~68 .lut_mask = 16'hF3C0; -defparam \D[1]~68 .sum_lutc_input = "datac"; +defparam \Selector14~16 .lut_mask = 16'hBBC0; +defparam \Selector14~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y15_N14 -cycloneive_lcell_comb \D[1]~69 ( +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \D[0]~15 ( // Equation(s): -// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) +// \D[0]~15_combout = (\Equal5~0_combout & (((\Selector14~8_combout )))) # (!\Equal5~0_combout & ((\Selector14~8_combout & ((\Selector14~16_combout ))) # (!\Selector14~8_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout +// )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3_combout ), + .datac(\Selector14~16_combout ), + .datad(\Selector14~8_combout ), + .cin(gnd), + .combout(\D[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~15 .lut_mask = 16'hFA44; +defparam \D[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \D[0]~16 ( +// Equation(s): +// \D[0]~16_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~15_combout ) # (!\Equal5~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[0]~15_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\Equal5~1_combout ), + .datad(\D[0]~15_combout ), + .cin(gnd), + .combout(\D[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~16 .lut_mask = 16'hBB0B; +defparam \D[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \Selector12~12 ( +// Equation(s): +// \Selector12~12_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~22_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\Selector12~12_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~12 .lut_mask = 16'hD9C8; +defparam \Selector12~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N2 +cycloneive_lcell_comb \Selector12~13 ( +// Equation(s): +// \Selector12~13_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector12~12_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector12~12_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector12~12_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\Selector12~12_combout ), + .cin(gnd), + .combout(\Selector12~13_combout ), + .cout()); +// synopsys translate_off +defparam \Selector12~13 .lut_mask = 16'hDDA0; +defparam \Selector12~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \D[1]~17 ( +// Equation(s): +// \D[1]~17_combout = (\Equal5~0_combout & (((\Selector12~4_combout )))) # (!\Equal5~0_combout & ((\Selector12~4_combout & ((\Selector12~13_combout ))) # (!\Selector12~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout +// )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5_combout ), + .datac(\Selector12~4_combout ), + .datad(\Selector12~13_combout ), + .cin(gnd), + .combout(\D[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~17 .lut_mask = 16'hF4A4; +defparam \D[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \D[1]~18 ( +// Equation(s): +// \D[1]~18_combout = (\Equal5~1_combout & (\D[1]~17_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), .datab(\z80_|data_pins_|dout [1]), - .datac(\Equal2~1_combout ), - .datad(\D[1]~68_combout ), - .cin(gnd), - .combout(\D[1]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~69 .lut_mask = 16'hDD0D; -defparam \D[1]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N16 -cycloneive_lcell_comb \D[2]~70 ( -// Equation(s): -// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) - - .dataa(gnd), - .datab(\D[2]~46_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[2]~119_combout ), - .cin(gnd), - .combout(\D[2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~70 .lut_mask = 16'hCFC0; -defparam \D[2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N14 -cycloneive_lcell_comb \D[2]~71 ( -// Equation(s): -// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [2]), - .datad(\D[2]~70_combout ), - .cin(gnd), - .combout(\D[2]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~71 .lut_mask = 16'hF531; -defparam \D[2]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y15_N24 -cycloneive_lcell_comb \D[3]~83 ( -// Equation(s): -// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datab(gnd), - .datac(\z80_|data_pins_|dout [3]), - .datad(gnd), - .cin(gnd), - .combout(\D[3]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~83 .lut_mask = 16'hF5F5; -defparam \D[3]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y15_N6 -cycloneive_lcell_comb \D[3]~84 ( -// Equation(s): -// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) - - .dataa(\D[3]~122_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[3]~82_combout ), - .datad(\D[3]~83_combout ), - .cin(gnd), - .combout(\D[3]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~84 .lut_mask = 16'hFB00; -defparam \D[3]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N20 -cycloneive_lcell_comb \D[4]~95 ( -// Equation(s): -// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) - - .dataa(\D[4]~89_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[4]~125_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~95 .lut_mask = 16'hB8B8; -defparam \D[4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N6 -cycloneive_lcell_comb \D[4]~96 ( -// Equation(s): -// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\Equal2~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[4]~95_combout ), + .datad(\D[1]~17_combout ), .cin(gnd), - .combout(\D[4]~96_combout ), + .combout(\D[1]~18_combout ), .cout()); // synopsys translate_off -defparam \D[4]~96 .lut_mask = 16'hAF23; -defparam \D[4]~96 .sum_lutc_input = "datac"; +defparam \D[1]~18 .lut_mask = 16'hCF45; +defparam \D[1]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N18 -cycloneive_lcell_comb \D[5]~126 ( +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \D[2]~19 ( // Equation(s): -// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) +// \D[2]~19_combout = (\Selector10~2_combout & (((\Selector10~1_combout ) # (\Equal5~0_combout )))) # (!\Selector10~2_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout & ((!\Equal5~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1_combout ), + .datab(\Selector10~2_combout ), + .datac(\Selector10~1_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~19 .lut_mask = 16'hCCE2; +defparam \D[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \D[2]~20 ( +// Equation(s): +// \D[2]~20_combout = (\Equal5~1_combout & (\D[2]~19_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) # (!\Equal5~1_combout & ((\z80_|data_pins_|dout [2]) # ((!\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal5~1_combout ), + .datab(\z80_|data_pins_|dout [2]), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[2]~19_combout ), + .cin(gnd), + .combout(\D[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~20 .lut_mask = 16'hCF45; +defparam \D[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hBA98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \Selector8~2 ( +// Equation(s): +// \Selector8~2_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\Selector8~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~2 .lut_mask = 16'hCBC8; +defparam \Selector8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \Selector8~3 ( +// Equation(s): +// \Selector8~3_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector8~2_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\Selector8~2_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector8~2_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector8~2_combout ), + .cin(gnd), + .combout(\Selector8~3_combout ), + .cout()); +// synopsys translate_off +defparam \Selector8~3 .lut_mask = 16'hF388; +defparam \Selector8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[3]~21 ( +// Equation(s): +// \D[3]~21_combout = (\Equal5~0_combout & (((\Selector8~4_combout )))) # (!\Equal5~0_combout & ((\Selector8~4_combout & ((\Selector8~3_combout ))) # (!\Selector8~4_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) + + .dataa(\Equal5~0_combout ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datac(\Selector8~3_combout ), + .datad(\Selector8~4_combout ), + .cin(gnd), + .combout(\D[3]~21_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~21 .lut_mask = 16'hFA44; +defparam \D[3]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[3]~22 ( +// Equation(s): +// \D[3]~22_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~21_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[3]~21_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\Equal5~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[3]~21_combout ), + .cin(gnd), + .combout(\D[3]~22_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~22 .lut_mask = 16'hAF23; +defparam \D[3]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[4]~23 ( +// Equation(s): +// \D[4]~23_combout = (\Selector6~6_combout & ((\Selector6~1_combout ) # ((\Equal5~0_combout )))) # (!\Selector6~6_combout & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout & !\Equal5~0_combout )))) + + .dataa(\Selector6~1_combout ), + .datab(\Selector6~6_combout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Equal5~0_combout ), + .cin(gnd), + .combout(\D[4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~23 .lut_mask = 16'hCCB8; +defparam \D[4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[4]~24 ( +// Equation(s): +// \D[4]~24_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~23_combout ) # (!\Equal5~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~23_combout ) # (!\Equal5~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\Equal5~1_combout ), + .datad(\D[4]~23_combout ), + .cin(gnd), + .combout(\D[4]~24_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~24 .lut_mask = 16'hDD0D; +defparam \D[4]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \D[6]~32 ( +// Equation(s): +// \D[6]~32_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~32 .lut_mask = 16'hE3E0; +defparam \D[6]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \D[6]~33 ( +// Equation(s): +// \D[6]~33_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~32_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~32_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~32_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~32_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~33 .lut_mask = 16'hF838; +defparam \D[6]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \D[6]~29 ( +// Equation(s): +// \D[6]~29_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~29 .lut_mask = 16'hE6A2; +defparam \D[6]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \D[6]~30 ( +// Equation(s): +// \D[6]~30_combout = (\z80_|address_pins_|abus[15]~23_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~29_combout ))))) # (!\z80_|address_pins_|abus[15]~23_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~29_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~29_combout ), + .cin(gnd), + .combout(\D[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~30 .lut_mask = 16'h44B8; +defparam \D[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \D[6]~31 ( +// Equation(s): +// \D[6]~31_combout = (\D[6]~29_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~30_combout )))) # (!\D[6]~29_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~30_combout )))) + + .dataa(\D[6]~29_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~30_combout ), + .cin(gnd), + .combout(\D[6]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~31 .lut_mask = 16'h99A8; +defparam \D[6]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \D[6]~50 ( +// Equation(s): +// \D[6]~50_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~33_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~31_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~33_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Mux2~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .datac(\D[6]~33_combout ), + .datad(\D[6]~31_combout ), .cin(gnd), - .combout(\D[5]~126_combout ), + .combout(\D[6]~50_combout ), .cout()); // synopsys translate_off -defparam \D[5]~126 .lut_mask = 16'hFB40; -defparam \D[5]~126 .sum_lutc_input = "datac"; +defparam \D[6]~50 .lut_mask = 16'hF4B0; +defparam \D[6]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y18_N0 -cycloneive_lcell_comb \D[5]~98 ( +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \D[6]~34 ( // Equation(s): -// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) +// \D[6]~34_combout = (\Equal5~0_combout & (\D[6]~28_combout & (\Equal3~2_combout ))) # (!\Equal5~0_combout & (((\D[6]~50_combout )))) - .dataa(\z80_|data_pins_|dout [5]), - .datab(\D[5]~97_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[5]~126_combout ), + .dataa(\D[6]~28_combout ), + .datab(\Equal3~2_combout ), + .datac(\Equal5~0_combout ), + .datad(\D[6]~50_combout ), .cin(gnd), - .combout(\D[5]~98_combout ), + .combout(\D[6]~34_combout ), .cout()); // synopsys translate_off -defparam \D[5]~98 .lut_mask = 16'hAF23; -defparam \D[5]~98 .sum_lutc_input = "datac"; +defparam \D[6]~34 .lut_mask = 16'h8F80; +defparam \D[6]~34 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N18 -cycloneive_lcell_comb \D[6]~105 ( +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \D[6]~35 ( // Equation(s): -// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) - - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~127_combout ), - .datad(\D[6]~99_combout ), - .cin(gnd), - .combout(\D[6]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~105 .lut_mask = 16'hFC30; -defparam \D[6]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y19_N0 -cycloneive_lcell_comb \D[6]~106 ( -// Equation(s): -// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) +// \D[6]~35_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~34_combout )) # (!\Equal5~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~34_combout ) # (!\Equal5~1_combout )))) .dataa(\z80_|data_pins_|dout [6]), - .datab(\Equal2~1_combout ), + .datab(\Equal5~1_combout ), .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~105_combout ), + .datad(\D[6]~34_combout ), .cin(gnd), - .combout(\D[6]~106_combout ), + .combout(\D[6]~35_combout ), .cout()); // synopsys translate_off -defparam \D[6]~106 .lut_mask = 16'hAF23; -defparam \D[6]~106 .sum_lutc_input = "datac"; +defparam \D[6]~35 .lut_mask = 16'hAF23; +defparam \D[6]~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y17_N10 -cycloneive_lcell_comb \D[7]~128 ( -// Equation(s): -// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~128_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~128 .lut_mask = 16'hF2D0; -defparam \D[7]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y17_N16 -cycloneive_lcell_comb \D[7]~107 ( -// Equation(s): -// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[5]~97_combout ), - .datad(\D[7]~128_combout ), - .cin(gnd), - .combout(\D[7]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~107 .lut_mask = 16'hBB0B; -defparam \D[7]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datac(\z80_|memory_ifc_|iorq~0_combout ), - .datad(\z80_|memory_ifc_|wait_iorqinta~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 +// Location: LCCOMB_X36_Y11_N2 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~55_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q ))) - .dataa(gnd), - .datab(\z80_|execute_|setM1~53_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~55_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; +defparam \z80_|nM1_int~3 .lut_mask = 16'hE0E0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N13 +// Location: FF_X36_Y11_N3 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -54063,7 +57974,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X26_Y12_N22 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -54080,7 +57991,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y11_N5 +// Location: FF_X26_Y12_N23 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -54099,7 +58010,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y11_N27 +// Location: FF_X26_Y12_N21 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -54118,32 +58029,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N26 +// Location: LCCOMB_X26_Y12_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|wait_mwr~q ), - .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), + .datab(\z80_|memory_ifc_|wait_mwr~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y11_N2 +// Location: LCCOMB_X26_Y12_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ))) - .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datab(\z80_|memory_ifc_|wait_mrd~q ), - .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -54165,7 +58076,24 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N18 +// Location: LCCOMB_X1_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -54182,7 +58110,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N19 +// Location: FF_X3_Y24_N1 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -54201,14 +58129,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X3_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) - .dataa(\ula_|i2c_loader_|divider [0]), - .datab(\ula_|i2c_loader_|divider [1]), + .dataa(\ula_|i2c_loader_|divider [1]), + .datab(\ula_|i2c_loader_|divider [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -54219,7 +58147,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N9 +// Location: FF_X3_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -54238,7 +58166,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X3_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -54256,7 +58184,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N11 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -54275,7 +58203,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 +// Location: LCCOMB_X3_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -54293,7 +58221,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N13 +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -54312,24 +58240,7 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) - - .dataa(\ula_|i2c_loader_|divider [3]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [1]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -54347,7 +58258,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N15 +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -54366,7 +58277,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X3_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -54383,7 +58294,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X1_Y24_N17 +// Location: FF_X3_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -54402,60 +58313,41 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N30 +// Location: LCCOMB_X3_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) +// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(\ula_|i2c_loader_|divider [5]), .datac(\ula_|i2c_loader_|divider [4]), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(\ula_|i2c_loader_|WideAnd0~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hFF3F; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 -dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|scl_out~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N23 +// Location: FF_X1_Y23_N19 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -54474,7 +58366,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N8 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -54491,7 +58383,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N9 +// Location: FF_X1_Y23_N29 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -54510,24 +58402,24 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [1] $ (\ula_|i2c_loader_|phase [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|phase~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h0CC0; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N31 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -54546,75 +58438,174 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: FF_X1_Y23_N5 +dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|scl_out~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N24 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hA0A0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~4_combout ), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; -defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [1] $ (!\ula_|i2c_loader_|nbyte [0])))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEAAE; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N31 +// Location: FF_X2_Y23_N15 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54633,67 +58624,135 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [1]) # (\ula_|i2c_loader_|nbyte [0]))) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hCCC0; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 +// Location: LCCOMB_X1_Y22_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|nbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|state.Pause~0_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|nbit[0]~1_combout )))) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~0_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datac(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N27 +// Location: LCCOMB_X1_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|Mux42~0_combout & !\ula_|i2c_loader_|WideAnd0~combout ))) + + .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0040; +defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~4_combout ), + .d(\ula_|i2c_loader_|nbit~5_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [0]), @@ -54703,43 +58762,7 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y25_N1 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y25_N28 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) @@ -54756,75 +58779,41 @@ defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 +// Location: LCCOMB_X2_Y22_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]) - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N4 +// Location: LCCOMB_X2_Y22_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~27_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~26_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|state~27_combout ), + .datab(\ula_|i2c_loader_|state~26_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), + .datad(\ula_|i2c_loader_|state~27_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X2_Y22_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54843,24 +58832,60 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N12 +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): // \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [1]), + .dataa(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|nbit [2]), .datad(\ula_|i2c_loader_|nbit [0]), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF3B7; defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y25_N13 +// Location: FF_X2_Y23_N13 dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~0_combout ), @@ -54869,7 +58894,7 @@ dffeas \ula_|i2c_loader_|nbit[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|nbit [2]), @@ -54879,32 +58904,32 @@ defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y25_N30 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [0] & \ula_|i2c_loader_|state.Data~q ))) .dataa(\ula_|i2c_loader_|nbit [2]), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [1]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0100; defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N2 +// Location: LCCOMB_X2_Y22_N16 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Pause~q & (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Ack~q ))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Idle~0_combout ), .cout()); @@ -54913,7 +58938,7 @@ defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N16 +// Location: LCCOMB_X2_Y22_N6 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( // Equation(s): // \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) @@ -54930,25 +58955,25 @@ defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 +// Location: LCCOMB_X2_Y22_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Ack~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Ack~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N25 +// Location: FF_X2_Y22_N3 dffeas \ula_|i2c_loader_|state.Ack ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Ack~1_combout ), @@ -54967,121 +58992,24 @@ defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(\ula_|i2c_loader_|state.Idle~q ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N21 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2c_loader_|nbyte~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( // Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) +// \ula_|i2c_loader_|state.Stop~0_combout = (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|nbyte [0])) .dataa(gnd), - .datab(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Ack~q ), .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Stop~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h000C; defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N6 +// Location: LCCOMB_X2_Y22_N4 cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( // Equation(s): // \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # @@ -55099,7 +59027,7 @@ defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N7 +// Location: FF_X2_Y22_N5 dffeas \ula_|i2c_loader_|state.Stop ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Stop~1_combout ), @@ -55118,24 +59046,24 @@ defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 +// Location: LCCOMB_X2_Y22_N22 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - .dataa(\ula_|i2c_loader_|state.Stop~q ), - .datab(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|state.Stop~q ), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h5FCC; defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) @@ -55153,41 +59081,41 @@ defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~5 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\I2C_SDAT~input_o ), + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\I2C_SDAT~input_o ), + .datad(\ula_|i2c_loader_|nbyte [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .combout(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbyte[0]~5 .lut_mask = 16'hFAD8; +defparam \ula_|i2c_loader_|nbyte[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|nbyte[0]~5_combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h2000; defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y23_N5 dffeas \ula_|i2c_loader_|thisbyte[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), @@ -55206,25 +59134,25 @@ defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N20 +// Location: LCCOMB_X3_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) // \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N21 +// Location: FF_X3_Y23_N7 dffeas \ula_|i2c_loader_|thisbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), @@ -55243,25 +59171,25 @@ defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) // \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: FF_X3_Y23_N9 dffeas \ula_|i2c_loader_|thisbyte[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), @@ -55280,25 +59208,25 @@ defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X3_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( // Equation(s): // \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) // \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N25 +// Location: FF_X3_Y23_N11 dffeas \ula_|i2c_loader_|thisbyte[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), @@ -55318,40 +59246,23 @@ defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte[3]~15 $ (!\ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X3_Y23_N27 +// Location: FF_X3_Y23_N13 dffeas \ula_|i2c_loader_|thisbyte[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), @@ -55370,94 +59281,111 @@ defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N22 +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0004; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y22_N12 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( // Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|Equal2~0_combout ) # (!\ula_|i2c_loader_|thisbyte [4]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Pause~2_combout ), - .datac(\ula_|i2c_loader_|Equal2~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), + .dataa(\ula_|i2c_loader_|state.Pause~2_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0AAA; defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X2_Y22_N10 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Stop~q & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|state.Stop~q ), + .dataa(gnd), .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(gnd), + .datac(\ula_|i2c_loader_|state.Stop~q ), .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N26 +// Location: LCCOMB_X2_Y22_N30 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) +// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Pause~1_combout )))) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h0ACE; defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y22_N20 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF373; defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N20 +// Location: LCCOMB_X2_Y22_N26 cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( // Equation(s): // \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # // (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .dataa(\ula_|i2c_loader_|state.Pause~3_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), .datac(\ula_|i2c_loader_|state.Pause~q ), .datad(\ula_|i2c_loader_|state.Pause~5_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Pause~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE2F0; defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N21 +// Location: FF_X2_Y22_N27 dffeas \ula_|i2c_loader_|state.Pause ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Pause~6_combout ), @@ -55476,25 +59404,25 @@ defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N30 +// Location: LCCOMB_X2_Y22_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( // Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|state.Start~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|state.Pause~q & \ula_|i2c_loader_|Mux42~0_combout ))) # // (!\ula_|i2c_loader_|state.Idle~q ) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Pause~q ), + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h3BF3; defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N31 +// Location: FF_X2_Y22_N29 dffeas \ula_|i2c_loader_|state.Start ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state~25_combout ), @@ -55513,38 +59441,38 @@ defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Start .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (!\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # // ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hC3EA; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~1_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|scl_out~1_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC0C3; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55586,186 +59514,152 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [2]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~4_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; -defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [4])) # (!\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4]))))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h0310; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|shiftreg~14_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|shiftreg~19_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~13_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hFF10; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X3_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte [4])))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|shiftreg~22_combout ), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h3530; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~14_combout & (\ula_|i2c_loader_|thisbyte [3]))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|shiftreg~14_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hF404; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) +// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h1010; +defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~27_combout = (\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; -defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - - .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datab(\ula_|i2c_loader_|state~24_combout ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state~24_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; -defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .lut_mask = 16'hEEE4; +defparam \ula_|i2c_loader_|shiftreg[0]~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~28 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) +// \ula_|i2c_loader_|shiftreg[0]~28_combout = (\ula_|i2c_loader_|shiftreg[0]~27_combout & (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Idle~q & !\ula_|i2c_loader_|WideAnd0~combout ))) - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~27_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|WideAnd0~combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .lut_mask = 16'h0080; +defparam \ula_|i2c_loader_|shiftreg[0]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N21 +// Location: FF_X2_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55775,85 +59669,136 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg~23_combout ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [0]), + .dataa(\ula_|i2c_loader_|thisbyte [3]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; -defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h8090; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y22_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~6 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~6_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~6 .lut_mask = 16'h0033; +defparam \ula_|i2c_loader_|shiftreg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~6_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((!\ula_|i2c_loader_|thisbyte [0] & \ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), + .datab(\ula_|i2c_loader_|shiftreg~6_combout ), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8C88; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [1]) # ((!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state~24_combout )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'h8CBF; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~9_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|state~24_combout ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h2E2F; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 +// Location: LCCOMB_X2_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & -// !\ula_|i2c_loader_|state.Data~q )))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (!\ula_|i2c_loader_|shiftreg[6]~10_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg[6]~10_combout ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h0300; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; -defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 +// Location: FF_X2_Y24_N17 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~24_combout ), + .d(\ula_|i2c_loader_|shiftreg~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55863,33 +59808,67 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) - .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h5030; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N11 +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~18_combout ))) # (!\ula_|i2c_loader_|shiftreg~6_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|shiftreg~6_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h2EFF; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hCF00; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~21_combout ), + .d(\ula_|i2c_loader_|shiftreg~20_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55899,84 +59878,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg~17_combout & (!\ula_|i2c_loader_|state.Start~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~17_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAE04; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), - .datab(\ula_|i2c_loader_|shiftreg~15_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [2]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~18_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; -defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N23 +// Location: FF_X2_Y24_N19 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~27_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55986,67 +59914,33 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Location: LCCOMB_X2_Y24_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|shiftreg [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE54; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|shiftreg~14_combout ), - .datac(\ula_|i2c_loader_|thisbyte [3]), - .datad(\ula_|i2c_loader_|shiftreg~15_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) - - .dataa(\ula_|i2c_loader_|shiftreg [3]), - .datab(\ula_|i2c_loader_|state.Start~q ), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~16_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N15 +// Location: FF_X2_Y24_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -56056,33 +59950,50 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) - .dataa(\ula_|i2c_loader_|Mux35~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(gnd), - .datad(\ula_|i2c_loader_|shiftreg [4]), + .dataa(\ula_|i2c_loader_|thisbyte [1]), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|thisbyte [0]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h40C0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N5 +// Location: LCCOMB_X1_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [4])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) + + .dataa(\ula_|i2c_loader_|shiftreg [4]), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hBB88; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~13_combout ), + .d(\ula_|i2c_loader_|shiftreg~12_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -56092,33 +60003,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), - .datab(\ula_|i2c_loader_|Mux35~0_combout ), + .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg [5]), + .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -56128,33 +60039,33 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) +// \ula_|i2c_loader_|shiftreg[7]~7_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|shiftreg [6]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .combout(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|shiftreg[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N29 +// Location: FF_X2_Y24_N1 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), + .d(\ula_|i2c_loader_|shiftreg[7]~7_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~28_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -56164,16 +60075,16 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N20 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) .dataa(\ula_|i2c_loader_|shiftreg [7]), - .datab(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); @@ -56182,14 +60093,14 @@ defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~6_combout & !\I2C_SDAT~input_o )))) .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~6_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), @@ -56199,38 +60110,38 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h0C0E; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) - .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), + .dataa(\ula_|i2c_loader_|phase [1]), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2F4; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56239,15 +60150,15 @@ cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56391,735 +60302,118 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux38~0 ( -// Equation(s): -// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) - - .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), - .datab(\Equal2~1_combout ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Mux39~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux38~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; -defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y12_N15 -dffeas \sdram_|r.rd_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux38~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rd_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rd_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N0 -cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( -// Equation(s): -// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) -// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\sdram_|r.rf_counter[0]~12_combout ), - .cout(\sdram_|r.rf_counter[0]~13 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; -defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N26 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.address[3]~6_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.rf_counter[3]~32_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; -defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N1 -dffeas \sdram_|r.rf_counter[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[0]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N2 -cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( -// Equation(s): -// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) -// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [1]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[0]~13 ), - .combout(\sdram_|r.rf_counter[1]~14_combout ), - .cout(\sdram_|r.rf_counter[1]~15 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N3 -dffeas \sdram_|r.rf_counter[1] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[1]~14_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N4 -cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( -// Equation(s): -// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) -// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [2]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[1]~15 ), - .combout(\sdram_|r.rf_counter[2]~16_combout ), - .cout(\sdram_|r.rf_counter[2]~17 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N5 -dffeas \sdram_|r.rf_counter[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[2]~16_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N6 -cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( -// Equation(s): -// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) -// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[2]~17 ), - .combout(\sdram_|r.rf_counter[3]~18_combout ), - .cout(\sdram_|r.rf_counter[3]~19 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N7 -dffeas \sdram_|r.rf_counter[3] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[3]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N8 -cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( -// Equation(s): -// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) -// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [4]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[3]~19 ), - .combout(\sdram_|r.rf_counter[4]~20_combout ), - .cout(\sdram_|r.rf_counter[4]~21 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N9 -dffeas \sdram_|r.rf_counter[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[4]~20_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N10 -cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( -// Equation(s): -// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) -// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[4]~21 ), - .combout(\sdram_|r.rf_counter[5]~22_combout ), - .cout(\sdram_|r.rf_counter[5]~23 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; -defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N11 -dffeas \sdram_|r.rf_counter[5] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[5]~22_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N12 -cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( -// Equation(s): -// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) -// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) - - .dataa(\sdram_|r.rf_counter [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[5]~23 ), - .combout(\sdram_|r.rf_counter[6]~24_combout ), - .cout(\sdram_|r.rf_counter[6]~25 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; -defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N13 -dffeas \sdram_|r.rf_counter[6] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N14 -cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( -// Equation(s): -// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) -// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [7]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[6]~25 ), - .combout(\sdram_|r.rf_counter[7]~26_combout ), - .cout(\sdram_|r.rf_counter[7]~27 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; -defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N15 -dffeas \sdram_|r.rf_counter[7] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[7]~26_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N24 -cycloneive_lcell_comb \sdram_|Equal0~1 ( -// Equation(s): -// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) - - .dataa(\sdram_|r.rf_counter [5]), - .datab(\sdram_|r.rf_counter [7]), - .datac(\sdram_|r.rf_counter [4]), - .datad(\sdram_|r.rf_counter [6]), - .cin(gnd), - .combout(\sdram_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; -defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N16 -cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( -// Equation(s): -// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) -// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) - - .dataa(gnd), - .datab(\sdram_|r.rf_counter [8]), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|r.rf_counter[7]~27 ), - .combout(\sdram_|r.rf_counter[8]~28_combout ), - .cout(\sdram_|r.rf_counter[8]~29 )); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; -defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N17 -dffeas \sdram_|r.rf_counter[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[8]~28_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal0~0 ( -// Equation(s): -// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) - - .dataa(\sdram_|r.rf_counter [3]), - .datab(\sdram_|r.rf_counter [0]), - .datac(\sdram_|r.rf_counter [2]), - .datad(\sdram_|r.rf_counter [1]), - .cin(gnd), - .combout(\sdram_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; -defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N18 -cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( -// Equation(s): -// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\sdram_|r.rf_counter [9]), - .cin(\sdram_|r.rf_counter[8]~29 ), - .combout(\sdram_|r.rf_counter[9]~30_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; -defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X20_Y13_N19 -dffeas \sdram_|r.rf_counter[9] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.rf_counter[9]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(\sdram_|r.rf_counter[3]~32_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_counter [9]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; -defparam \sdram_|r.rf_counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N22 -cycloneive_lcell_comb \sdram_|Equal0~2 ( -// Equation(s): -// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) - - .dataa(\sdram_|Equal0~1_combout ), - .datab(\sdram_|r.rf_counter [8]), - .datac(\sdram_|Equal0~0_combout ), - .datad(\sdram_|r.rf_counter [9]), - .cin(gnd), - .combout(\sdram_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; -defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N28 -cycloneive_lcell_comb \sdram_|Mux13~8 ( -// Equation(s): -// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|Mux13~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; -defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y13_N20 -cycloneive_lcell_comb \sdram_|Mux37~0 ( -// Equation(s): -// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) - - .dataa(\sdram_|Equal0~2_combout ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux13~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux37~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; -defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y13_N21 -dffeas \sdram_|r.rf_pending ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux37~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.rf_pending~q ), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; -defparam \sdram_|r.rf_pending .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N14 -cycloneive_lcell_comb \sdram_|Mux4~0 ( -// Equation(s): -// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; -defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux4~1 ( -// Equation(s): -// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; -defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N2 -cycloneive_lcell_comb \sdram_|Mux4~2 ( -// Equation(s): -// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux4~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux4~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; -defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N30 +// Location: LCCOMB_X21_Y19_N4 cycloneive_lcell_comb \sdram_|Mux4~3 ( // Equation(s): -// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) +// \sdram_|Mux4~3_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [6])) - .dataa(\sdram_|Mux4~1_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux4~2_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux4~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .lut_mask = 16'hAA50; defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N31 -dffeas \sdram_|r.state[8] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux4~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.state [8]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.state[8] .is_wysiwyg = "true"; -defparam \sdram_|r.state[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N6 -cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~0 ( // Equation(s): -// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) +// \sdram_|Mux4~0_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4]))) .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.act_row[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; -defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N18 -cycloneive_lcell_comb \sdram_|process_0~2 ( -// Equation(s): -// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) - - .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|process_0~2_combout ), + .combout(\sdram_|Mux4~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; -defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux4~0 .lut_mask = 16'hAF00; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N0 -cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( // Equation(s): -// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - .dataa(\sdram_|r.act_row[1]~0_combout ), - .datab(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.state [6]), + .datab(gnd), .datac(\sdram_|r.state [7]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.act_row[1]~1_combout ), + .combout(\sdram_|r.address[3]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; -defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N9 -dffeas \sdram_|r.act_row[4] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\z80_|address_pins_|abus[15]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [4]), - .prn(vcc)); +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); // synopsys translate_off -defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[4] .power_up = "low"; +defparam \sdram_|Mux7~2 .lut_mask = 16'h0B00; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N23 -dffeas \sdram_|r.act_row[3] ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [6] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hCC00; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h5500; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \sdram_|r.act_row[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .asdata(\z80_|address_pins_|abus[13]~20_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [3]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N20 -cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( -// Equation(s): -// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~23_combout ), - .cin(gnd), - .combout(\sdram_|r.act_row[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; -defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X21_Y13_N21 -dffeas \sdram_|r.act_row[2] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.act_row[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.act_row [2]), @@ -57129,115 +60423,80 @@ defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; defparam \sdram_|r.act_row[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N22 +// Location: FF_X21_Y14_N11 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 cycloneive_lcell_comb \sdram_|Equal7~1 ( // Equation(s): -// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & -// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~20_combout $ (!\sdram_|r.act_row [2])))) .dataa(\z80_|address_pins_|abus[14]~22_combout ), - .datab(\z80_|address_pins_|abus[13]~23_combout ), - .datac(\sdram_|r.act_row [3]), - .datad(\sdram_|r.act_row [2]), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\sdram_|r.act_row [2]), + .datad(\sdram_|r.act_row [3]), .cin(gnd), .combout(\sdram_|Equal7~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .lut_mask = 16'h8241; defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y13_N3 -dffeas \sdram_|r.act_row[1] ( +// Location: FF_X21_Y14_N1 +dffeas \sdram_|r.act_row[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .asdata(\z80_|address_pins_|abus[15]~23_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), + .ena(\sdram_|r.act_row[2]~1_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.act_row [1]), + .q(\sdram_|r.act_row [4]), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[1] .power_up = "low"; +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X21_Y13_N13 -dffeas \sdram_|r.act_row[0] ( - .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[11]~19_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\sdram_|r.act_row[1]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\sdram_|r.act_row [0]), - .prn(vcc)); -// synopsys translate_off -defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; -defparam \sdram_|r.act_row[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N2 -cycloneive_lcell_comb \sdram_|Equal7~0 ( -// Equation(s): -// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & -// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[12]~24_combout ), - .datac(\sdram_|r.act_row [1]), - .datad(\sdram_|r.act_row [0]), - .cin(gnd), - .combout(\sdram_|Equal7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; -defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N30 -cycloneive_lcell_comb \sdram_|Equal7~2 ( -// Equation(s): -// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) - - .dataa(\z80_|address_pins_|abus[15]~21_combout ), - .datab(\sdram_|r.act_row [4]), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|Equal7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; -defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N4 +// Location: LCCOMB_X20_Y15_N20 cycloneive_lcell_comb \sdram_|Mux39~0 ( // Equation(s): -// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) +// \sdram_|Mux39~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux39~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .lut_mask = 16'h8402; defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N12 +// Location: LCCOMB_X20_Y15_N14 cycloneive_lcell_comb \sdram_|Mux39~1 ( // Equation(s): // \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) @@ -57254,24 +60513,24 @@ defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N24 +// Location: LCCOMB_X21_Y15_N30 cycloneive_lcell_comb \sdram_|Mux39~2 ( // Equation(s): -// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.wr_pending~q & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~23_combout ))) - .dataa(\sdram_|Mux39~1_combout ), - .datab(\z80_|address_pins_|abus[15]~21_combout ), + .dataa(\ExtRamWE~0_combout ), + .datab(\z80_|address_pins_|abus[15]~23_combout ), .datac(\sdram_|r.wr_pending~q ), - .datad(\ExtRamWE~0_combout ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), .combout(\sdram_|Mux39~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .lut_mask = 16'hF808; defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y12_N25 +// Location: FF_X21_Y15_N31 dffeas \sdram_|r.wr_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux39~2_combout ), @@ -57290,180 +60549,44 @@ defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; defparam \sdram_|r.wr_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux38~3 ( // Equation(s): -// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) +// \sdram_|Mux38~3_combout = (!\sdram_|r.rd_pending~q & (((!\z80_|memory_ifc_|nIORQ_out~0_combout & \z80_|address_pins_|DFFE_apin_latch [15])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux9~8_combout ), + .combout(\sdram_|Mux38~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; -defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~3 .lut_mask = 16'h0073; +defparam \sdram_|Mux38~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux38~2 ( // Equation(s): -// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) +// \sdram_|Mux38~2_combout = (\Equal5~1_combout & ((\sdram_|Mux38~3_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) # (!\Equal5~1_combout & (((\sdram_|r.rd_pending~q & \sdram_|Mux39~1_combout )))) - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|Mux38~3_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), .cin(gnd), - .combout(\sdram_|Mux9~9_combout ), + .combout(\sdram_|Mux38~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; -defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +defparam \sdram_|Mux38~2 .lut_mask = 16'hF888; +defparam \sdram_|Mux38~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N26 -cycloneive_lcell_comb \sdram_|Mux6~3 ( -// Equation(s): -// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux9~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; -defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N0 -cycloneive_lcell_comb \sdram_|Mux6~4 ( -// Equation(s): -// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) - - .dataa(gnd), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux6~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; -defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N6 -cycloneive_lcell_comb \sdram_|Mux6~2 ( -// Equation(s): -// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; -defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N10 -cycloneive_lcell_comb \sdram_|Mux6~5 ( -// Equation(s): -// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) - - .dataa(\sdram_|Mux6~3_combout ), - .datab(\sdram_|Mux6~4_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|Mux6~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; -defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N8 -cycloneive_lcell_comb \sdram_|process_0~3 ( -// Equation(s): -// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) - - .dataa(\sdram_|r.wr_pending~q ), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|process_0~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; -defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux6~0 ( -// Equation(s): -// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|process_0~3_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; -defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N16 -cycloneive_lcell_comb \sdram_|Mux6~1 ( -// Equation(s): -// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux6~0_combout ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux6~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; -defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N24 -cycloneive_lcell_comb \sdram_|Mux6~6 ( -// Equation(s): -// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux6~5_combout ), - .datad(\sdram_|Mux6~1_combout ), - .cin(gnd), - .combout(\sdram_|Mux6~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; -defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y15_N25 -dffeas \sdram_|r.state[6] ( +// Location: FF_X21_Y15_N21 +dffeas \sdram_|r.rd_pending ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux6~6_combout ), + .d(\sdram_|Mux38~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57472,175 +60595,73 @@ dffeas \sdram_|r.state[6] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\sdram_|r.state [6]), + .q(\sdram_|r.rd_pending~q ), .prn(vcc)); // synopsys translate_off -defparam \sdram_|r.state[6] .is_wysiwyg = "true"; -defparam \sdram_|r.state[6] .power_up = "low"; +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N12 -cycloneive_lcell_comb \sdram_|r.address[3]~6 ( -// Equation(s): -// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) - - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; -defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux7~2 ( -// Equation(s): -// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) - - .dataa(\sdram_|r.address[3]~6_combout ), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; -defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N12 +// Location: LCCOMB_X21_Y14_N22 cycloneive_lcell_comb \sdram_|n~3 ( // Equation(s): -// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) +// \sdram_|n~3_combout = (\sdram_|r.wr_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ ((!\sdram_|r.act_row [4])))) # (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) - .dataa(gnd), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|Equal7~2_combout ), + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|n~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .lut_mask = 16'h9990; defparam \sdram_|n~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N6 -cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \sdram_|n~4 ( // Equation(s): -// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.state [6]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; -defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N28 -cycloneive_lcell_comb \sdram_|Mux7~4 ( -// Equation(s): -// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) - - .dataa(\sdram_|Mux7~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux7~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; -defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N10 -cycloneive_lcell_comb \sdram_|Mux7~5 ( -// Equation(s): -// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|Mux7~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux7~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; -defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux23~0 ( -// Equation(s): -// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) +// \sdram_|n~4_combout = (\sdram_|Equal7~1_combout & (\sdram_|n~3_combout & \sdram_|Equal7~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(gnd), + .datab(\sdram_|Equal7~1_combout ), + .datac(\sdram_|n~3_combout ), + .datad(\sdram_|Equal7~0_combout ), .cin(gnd), - .combout(\sdram_|Mux23~0_combout ), + .combout(\sdram_|n~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; -defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +defparam \sdram_|n~4 .lut_mask = 16'hC000; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \sdram_|Mux10~9 ( // Equation(s): -// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) +// \sdram_|Mux10~9_combout = (!\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|Mux13~7_combout ), + .combout(\sdram_|Mux10~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; -defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux10~9 .lut_mask = 16'h00EF; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux10~10 ( -// Equation(s): -// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) - - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.rf_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; -defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N18 +// Location: LCCOMB_X19_Y17_N20 cycloneive_lcell_comb \sdram_|Mux7~1 ( // Equation(s): -// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~9_combout ) # (!\sdram_|r.state [7])))) .dataa(\sdram_|Mux23~0_combout ), .datab(\sdram_|Mux13~7_combout ), .datac(\sdram_|r.state [7]), - .datad(\sdram_|Mux10~10_combout ), + .datad(\sdram_|Mux10~9_combout ), .cin(gnd), .combout(\sdram_|Mux7~1_combout ), .cout()); @@ -57649,24 +60670,75 @@ defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N22 +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h3F00; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.wr_pending~q & \sdram_|Mux7~3_combout ))) # (!\sdram_|r.state [6] & (\sdram_|r.state [7] $ (((\sdram_|Mux7~3_combout ))))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux7~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h250A; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.rf_pending~q & (\sdram_|r.state [6] $ (((!\sdram_|Mux7~4_combout ))))) # (!\sdram_|r.rf_pending~q & (!\sdram_|r.state [6] & (!\sdram_|n~4_combout & !\sdram_|Mux7~4_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'h8823; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \sdram_|Mux7~6 ( // Equation(s): -// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|r.state [8] & \sdram_|Mux7~5_combout ))) .dataa(\sdram_|Mux7~2_combout ), - .datab(\sdram_|Mux7~5_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|Mux7~1_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux7~1_combout ), + .datad(\sdram_|Mux7~5_combout ), .cin(gnd), .combout(\sdram_|Mux7~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .lut_mask = 16'hFEFA; defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N23 +// Location: FF_X23_Y19_N3 dffeas \sdram_|r.state[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux7~6_combout ), @@ -57685,14 +60757,938 @@ defparam \sdram_|r.state[5] .is_wysiwyg = "true"; defparam \sdram_|r.state[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N6 +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~32_combout = ((\sdram_|r.address[3]~6_combout & (!\sdram_|r.state [4] & !\sdram_|r.state [5]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[8]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~32 .lut_mask = 16'h555D; +defparam \sdram_|r.rf_counter[8]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(\sdram_|r.rf_counter [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [2]) # ((\sdram_|r.rf_counter [0]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [2]), + .datac(\sdram_|r.rf_counter [0]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter [9] $ (\sdram_|r.rf_counter[8]~29 ) + + .dataa(\sdram_|r.rf_counter [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h5A5A; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N23 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[8]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [4]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [5]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [4]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [5]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~0_combout ) # (((\sdram_|Equal0~1_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~0_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|r.rf_counter [9]), + .datad(\sdram_|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFFBF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|r.address[3]~6_combout )) # (!\sdram_|Mux13~8_combout ))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|Equal0~2_combout )))) + + .dataa(\sdram_|Mux13~8_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h707F; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N25 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (!\sdram_|r.rf_pending~q & (\sdram_|r.rd_pending~q & (\sdram_|Equal7~2_combout & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h0040; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux4~4 ( +// Equation(s): +// \sdram_|Mux4~4_combout = (\sdram_|r.state [8] & (((!\sdram_|Mux4~0_combout & \sdram_|Mux4~1_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|Mux4~1_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux4~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~4 .lut_mask = 16'h5F44; +defparam \sdram_|Mux4~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [5] & (((\sdram_|r.state [6] & !\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [6] $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'h39FE; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux4~5 ( +// Equation(s): +// \sdram_|Mux4~5_combout = (\sdram_|Mux4~2_combout & (((\sdram_|r.state [8])))) # (!\sdram_|Mux4~2_combout & (\sdram_|Mux4~4_combout & ((\sdram_|Mux4~3_combout ) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~3_combout ), + .datab(\sdram_|Mux4~4_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~5 .lut_mask = 16'hF0C8; +defparam \sdram_|Mux4~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = (\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~0 ( +// Equation(s): +// \sdram_|r.act_row[2]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [5] & (\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [6] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \sdram_|r.act_row[2]~1 ( +// Equation(s): +// \sdram_|r.act_row[2]~1_combout = (\sdram_|process_0~4_combout & (\sdram_|r.act_row[2]~0_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.act_row[2]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~1 .lut_mask = 16'h9000; +defparam \sdram_|r.act_row[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N3 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[2]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~18_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~18_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~21_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~18_combout ), + .datab(\z80_|address_pins_|abus[12]~21_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~0_combout & (\sdram_|Equal7~1_combout & (\z80_|address_pins_|abus[15]~23_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~23_combout ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|r.act_row [4]), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h8040; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF88; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (!\sdram_|r.rf_pending~q & (!\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'h0501; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (!\sdram_|r.state [4] & \sdram_|r.state [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'h0F00; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~4_combout )) # (!\sdram_|Mux9~5_combout ))) # (!\sdram_|r.state [6] & (((!\sdram_|r.rf_pending~q & \sdram_|Mux9~4_combout )))) + + .dataa(\sdram_|Mux9~5_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux9~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h47CC; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hAFF0; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~4_combout & (\sdram_|Mux6~3_combout ))) + + .dataa(\sdram_|Mux6~4_combout ), + .datab(\sdram_|Mux6~3_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(gnd), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hCC00; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [4] & (\sdram_|r.state [8] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~2_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8C10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|Mux6~0_combout ) # (\sdram_|r.state [6]))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h6628; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFA50; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (\sdram_|r.state [4] & (!\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h00E0; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N28 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rf_pending~q & \sdram_|Mux5~7_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux5~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h4544; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 cycloneive_lcell_comb \sdram_|Mux5~2 ( // Equation(s): -// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [8] & !\sdram_|Mux4~1_combout )))) - .dataa(\sdram_|Mux4~0_combout ), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [8]), + .datac(\sdram_|Mux4~1_combout ), .datad(\sdram_|Mux13~7_combout ), .cin(gnd), .combout(\sdram_|Mux5~2_combout ), @@ -57702,143 +61698,109 @@ defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N18 +// Location: LCCOMB_X18_Y17_N22 cycloneive_lcell_comb \sdram_|Mux5~10 ( // Equation(s): -// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) +// \sdram_|Mux5~10_combout = (\sdram_|r.state [8] & (\sdram_|r.state [6] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6])) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux5~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .lut_mask = 16'h9991; defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N16 +// Location: LCCOMB_X18_Y17_N2 cycloneive_lcell_comb \sdram_|Mux5~3 ( // Equation(s): -// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|Mux4~1_combout & !\sdram_|r.state [6]))) # (!\sdram_|r.state [5]) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux4~0_combout ), - .datad(\sdram_|Mux5~10_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux4~1_combout ), + .datac(\sdram_|Mux5~10_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .lut_mask = 16'hF5F7; defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N30 +// Location: LCCOMB_X18_Y17_N0 cycloneive_lcell_comb \sdram_|Mux5~4 ( // Equation(s): -// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|r.state [4] & \sdram_|Mux5~3_combout )))) - .dataa(\sdram_|Mux5~2_combout ), - .datab(\sdram_|Mux5~3_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux5~2_combout ), + .datad(\sdram_|Mux5~3_combout ), .cin(gnd), .combout(\sdram_|Mux5~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .lut_mask = 16'hC8C0; defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N18 -cycloneive_lcell_comb \sdram_|Mux5~7 ( -// Equation(s): -// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.wr_pending~q ), - .datad(\sdram_|r.rd_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux5~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; -defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N4 -cycloneive_lcell_comb \sdram_|Mux5~8 ( -// Equation(s): -// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) - - .dataa(\sdram_|Mux5~7_combout ), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.rf_pending~q ), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|Mux5~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; -defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y15_N26 +// Location: LCCOMB_X20_Y16_N26 cycloneive_lcell_comb \sdram_|Mux5~5 ( // Equation(s): // \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.state [7]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|Mux5~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .lut_mask = 16'h0D0F; defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N12 +// Location: LCCOMB_X20_Y16_N8 cycloneive_lcell_comb \sdram_|Mux5~6 ( // Equation(s): -// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~4_combout & ((\sdram_|Mux5~5_combout ) # ((\sdram_|process_0~2_combout & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~3_combout ), - .datac(\sdram_|Mux9~8_combout ), - .datad(\sdram_|Mux5~5_combout ), + .dataa(\sdram_|Mux5~5_combout ), + .datab(\sdram_|Mux9~4_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux5~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .lut_mask = 16'h88C8; defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N20 +// Location: LCCOMB_X23_Y19_N10 cycloneive_lcell_comb \sdram_|Mux5~9 ( // Equation(s): // \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) - .dataa(\sdram_|r.state [5]), - .datab(\sdram_|Mux5~4_combout ), - .datac(\sdram_|Mux5~8_combout ), + .dataa(\sdram_|Mux5~8_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux5~4_combout ), .datad(\sdram_|Mux5~6_combout ), .cin(gnd), .combout(\sdram_|Mux5~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .lut_mask = 16'hF3F2; defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y15_N21 +// Location: FF_X23_Y19_N11 dffeas \sdram_|r.state[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|Mux5~9_combout ), @@ -57857,7 +61819,7 @@ defparam \sdram_|r.state[7] .is_wysiwyg = "true"; defparam \sdram_|r.state[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N8 +// Location: LCCOMB_X18_Y17_N16 cycloneive_lcell_comb \sdram_|n~2 ( // Equation(s): // \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) @@ -57874,78 +61836,112 @@ defparam \sdram_|n~2 .lut_mask = 16'hFFFC; defparam \sdram_|n~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Location: LCCOMB_X19_Y19_N10 +cycloneive_lcell_comb \sdram_|Mux8~6 ( // Equation(s): -// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) +// \sdram_|Mux8~6_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), .datad(\sdram_|r.state [4]), .cin(gnd), + .combout(\sdram_|Mux8~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~6 .lut_mask = 16'hB03B; +defparam \sdram_|Mux8~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N16 +cycloneive_lcell_comb \sdram_|Mux8~7 ( +// Equation(s): +// \sdram_|Mux8~7_combout = (\sdram_|r.state [8] & (\sdram_|Mux8~6_combout $ ((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|Mux8~6_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|Mux8~6_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~7 .lut_mask = 16'h606E; +defparam \sdram_|Mux8~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N18 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|r.state [5] $ (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [5]) # (\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7336; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N28 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [6] & (\sdram_|Mux8~1_combout & (!\sdram_|r.state [8]))) # (!\sdram_|r.state [6] & (\sdram_|r.state [8] $ (((!\sdram_|n~2_combout ) # (!\sdram_|Mux8~1_combout ))))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'h490D; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N26 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [6] & ((\sdram_|Mux9~5_combout & ((\sdram_|Mux8~2_combout ))) # (!\sdram_|Mux9~5_combout & (\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|Mux8~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux8~2_combout ), + .cin(gnd), .combout(\sdram_|Mux8~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .lut_mask = 16'hFD08; defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Location: LCCOMB_X19_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~44 ( // Equation(s): -// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|Mux8~3_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux8~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; -defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux9~10 ( -// Equation(s): -// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) - - .dataa(gnd), - .datab(\sdram_|Mux9~9_combout ), - .datac(\sdram_|r.state [8]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux9~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; -defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N28 -cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( -// Equation(s): -// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] +// \sdram_|r.init_counter[0]~44_combout = !\sdram_|r.init_counter [0] .dataa(gnd), .datab(gnd), .datac(\sdram_|r.init_counter [0]), .datad(gnd), .cin(gnd), - .combout(\sdram_|r.init_counter[0]~0_combout ), + .combout(\sdram_|r.init_counter[0]~44_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[0]~44 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y7_N29 +// Location: FF_X19_Y16_N7 dffeas \sdram_|r.init_counter[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[0]~0_combout ), + .d(\sdram_|r.init_counter[0]~44_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57961,45 +61957,45 @@ defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N2 -cycloneive_lcell_comb \sdram_|Add1~1 ( +// Location: LCCOMB_X18_Y16_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~15 ( // Equation(s): -// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) +// \sdram_|r.init_counter[1]~15_cout = CARRY(\sdram_|r.init_counter [0]) - .dataa(gnd), - .datab(\sdram_|r.init_counter [0]), + .dataa(\sdram_|r.init_counter [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), - .cout(\sdram_|Add1~1_cout )); + .cout(\sdram_|r.init_counter[1]~15_cout )); // synopsys translate_off -defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; -defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[1]~15 .lut_mask = 16'h00AA; +defparam \sdram_|r.init_counter[1]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N4 -cycloneive_lcell_comb \sdram_|Add1~2 ( +// Location: LCCOMB_X18_Y16_N4 +cycloneive_lcell_comb \sdram_|r.init_counter[1]~16 ( // Equation(s): -// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) -// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) +// \sdram_|r.init_counter[1]~16_combout = (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter[1]~15_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter[1]~15_cout )) +// \sdram_|r.init_counter[1]~17 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|r.init_counter[1]~15_cout )) .dataa(gnd), .datab(\sdram_|r.init_counter [1]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~1_cout ), - .combout(\sdram_|Add1~2_combout ), - .cout(\sdram_|Add1~3 )); + .cin(\sdram_|r.init_counter[1]~15_cout ), + .combout(\sdram_|r.init_counter[1]~16_combout ), + .cout(\sdram_|r.init_counter[1]~17 )); // synopsys translate_off -defparam \sdram_|Add1~2 .lut_mask = 16'hC303; -defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[1]~16 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[1]~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N5 +// Location: FF_X18_Y16_N5 dffeas \sdram_|r.init_counter[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~2_combout ), + .d(\sdram_|r.init_counter[1]~16_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58015,28 +62011,28 @@ defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N6 -cycloneive_lcell_comb \sdram_|Add1~4 ( +// Location: LCCOMB_X18_Y16_N6 +cycloneive_lcell_comb \sdram_|r.init_counter[2]~18 ( // Equation(s): -// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) -// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) +// \sdram_|r.init_counter[2]~18_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|r.init_counter[1]~17 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter[1]~17 $ (GND))) +// \sdram_|r.init_counter[2]~19 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|r.init_counter[1]~17 )) .dataa(\sdram_|r.init_counter [2]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~3 ), - .combout(\sdram_|Add1~4_combout ), - .cout(\sdram_|Add1~5 )); + .cin(\sdram_|r.init_counter[1]~17 ), + .combout(\sdram_|r.init_counter[2]~18_combout ), + .cout(\sdram_|r.init_counter[2]~19 )); // synopsys translate_off -defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[2]~18 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[2]~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N7 +// Location: FF_X18_Y16_N7 dffeas \sdram_|r.init_counter[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~4_combout ), + .d(\sdram_|r.init_counter[2]~18_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58052,45 +62048,28 @@ defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N8 -cycloneive_lcell_comb \sdram_|Add1~6 ( +// Location: LCCOMB_X18_Y16_N8 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~20 ( // Equation(s): -// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) -// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) - - .dataa(\sdram_|r.init_counter [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\sdram_|Add1~5 ), - .combout(\sdram_|Add1~6_combout ), - .cout(\sdram_|Add1~7 )); -// synopsys translate_off -defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; -defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N2 -cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( -// Equation(s): -// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout +// \sdram_|r.init_counter[3]~20_combout = (\sdram_|r.init_counter [3] & (\sdram_|r.init_counter[2]~19 & VCC)) # (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter[2]~19 )) +// \sdram_|r.init_counter[3]~21 = CARRY((!\sdram_|r.init_counter [3] & !\sdram_|r.init_counter[2]~19 )) .dataa(gnd), - .datab(gnd), - .datac(\sdram_|Add1~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.init_counter[3]~1_combout ), - .cout()); + .datab(\sdram_|r.init_counter [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.init_counter[2]~19 ), + .combout(\sdram_|r.init_counter[3]~20_combout ), + .cout(\sdram_|r.init_counter[3]~21 )); // synopsys translate_off -defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; -defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +defparam \sdram_|r.init_counter[3]~20 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[3]~20 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X20_Y3_N3 +// Location: FF_X18_Y16_N9 dffeas \sdram_|r.init_counter[3] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.init_counter[3]~1_combout ), + .d(\sdram_|r.init_counter[3]~20_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58106,28 +62085,28 @@ defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N10 -cycloneive_lcell_comb \sdram_|Add1~8 ( +// Location: LCCOMB_X18_Y16_N10 +cycloneive_lcell_comb \sdram_|r.init_counter[4]~22 ( // Equation(s): -// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) -// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) +// \sdram_|r.init_counter[4]~22_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|r.init_counter[3]~21 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|r.init_counter[3]~21 $ (GND))) +// \sdram_|r.init_counter[4]~23 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|r.init_counter[3]~21 )) .dataa(\sdram_|r.init_counter [4]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~7 ), - .combout(\sdram_|Add1~8_combout ), - .cout(\sdram_|Add1~9 )); + .cin(\sdram_|r.init_counter[3]~21 ), + .combout(\sdram_|r.init_counter[4]~22_combout ), + .cout(\sdram_|r.init_counter[4]~23 )); // synopsys translate_off -defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[4]~22 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[4]~22 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N11 +// Location: FF_X18_Y16_N11 dffeas \sdram_|r.init_counter[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~8_combout ), + .d(\sdram_|r.init_counter[4]~22_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58143,28 +62122,28 @@ defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N12 -cycloneive_lcell_comb \sdram_|Add1~10 ( +// Location: LCCOMB_X18_Y16_N12 +cycloneive_lcell_comb \sdram_|r.init_counter[5]~24 ( // Equation(s): -// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) -// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) +// \sdram_|r.init_counter[5]~24_combout = (\sdram_|r.init_counter [5] & (\sdram_|r.init_counter[4]~23 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|r.init_counter[4]~23 )) +// \sdram_|r.init_counter[5]~25 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|r.init_counter[4]~23 )) .dataa(\sdram_|r.init_counter [5]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~9 ), - .combout(\sdram_|Add1~10_combout ), - .cout(\sdram_|Add1~11 )); + .cin(\sdram_|r.init_counter[4]~23 ), + .combout(\sdram_|r.init_counter[5]~24_combout ), + .cout(\sdram_|r.init_counter[5]~25 )); // synopsys translate_off -defparam \sdram_|Add1~10 .lut_mask = 16'hA505; -defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[5]~24 .lut_mask = 16'hA505; +defparam \sdram_|r.init_counter[5]~24 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N13 +// Location: FF_X18_Y16_N13 dffeas \sdram_|r.init_counter[5] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~10_combout ), + .d(\sdram_|r.init_counter[5]~24_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58180,28 +62159,28 @@ defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N14 -cycloneive_lcell_comb \sdram_|Add1~12 ( +// Location: LCCOMB_X18_Y16_N14 +cycloneive_lcell_comb \sdram_|r.init_counter[6]~26 ( // Equation(s): -// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) -// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) +// \sdram_|r.init_counter[6]~26_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|r.init_counter[5]~25 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|r.init_counter[5]~25 $ (GND))) +// \sdram_|r.init_counter[6]~27 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|r.init_counter[5]~25 )) .dataa(gnd), .datab(\sdram_|r.init_counter [6]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~11 ), - .combout(\sdram_|Add1~12_combout ), - .cout(\sdram_|Add1~13 )); + .cin(\sdram_|r.init_counter[5]~25 ), + .combout(\sdram_|r.init_counter[6]~26_combout ), + .cout(\sdram_|r.init_counter[6]~27 )); // synopsys translate_off -defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[6]~26 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[6]~26 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N15 +// Location: FF_X18_Y16_N15 dffeas \sdram_|r.init_counter[6] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~12_combout ), + .d(\sdram_|r.init_counter[6]~26_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58217,28 +62196,28 @@ defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N16 -cycloneive_lcell_comb \sdram_|Add1~14 ( +// Location: LCCOMB_X18_Y16_N16 +cycloneive_lcell_comb \sdram_|r.init_counter[7]~28 ( // Equation(s): -// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) -// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) +// \sdram_|r.init_counter[7]~28_combout = (\sdram_|r.init_counter [7] & (\sdram_|r.init_counter[6]~27 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|r.init_counter[6]~27 )) +// \sdram_|r.init_counter[7]~29 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|r.init_counter[6]~27 )) .dataa(gnd), .datab(\sdram_|r.init_counter [7]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~13 ), - .combout(\sdram_|Add1~14_combout ), - .cout(\sdram_|Add1~15 )); + .cin(\sdram_|r.init_counter[6]~27 ), + .combout(\sdram_|r.init_counter[7]~28_combout ), + .cout(\sdram_|r.init_counter[7]~29 )); // synopsys translate_off -defparam \sdram_|Add1~14 .lut_mask = 16'hC303; -defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[7]~28 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[7]~28 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N17 +// Location: FF_X18_Y16_N17 dffeas \sdram_|r.init_counter[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~14_combout ), + .d(\sdram_|r.init_counter[7]~28_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58254,28 +62233,28 @@ defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N18 -cycloneive_lcell_comb \sdram_|Add1~16 ( +// Location: LCCOMB_X18_Y16_N18 +cycloneive_lcell_comb \sdram_|r.init_counter[8]~30 ( // Equation(s): -// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) -// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) +// \sdram_|r.init_counter[8]~30_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|r.init_counter[7]~29 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|r.init_counter[7]~29 $ (GND))) +// \sdram_|r.init_counter[8]~31 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|r.init_counter[7]~29 )) .dataa(gnd), .datab(\sdram_|r.init_counter [8]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~15 ), - .combout(\sdram_|Add1~16_combout ), - .cout(\sdram_|Add1~17 )); + .cin(\sdram_|r.init_counter[7]~29 ), + .combout(\sdram_|r.init_counter[8]~30_combout ), + .cout(\sdram_|r.init_counter[8]~31 )); // synopsys translate_off -defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; -defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[8]~30 .lut_mask = 16'h3CCF; +defparam \sdram_|r.init_counter[8]~30 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N19 +// Location: FF_X18_Y16_N19 dffeas \sdram_|r.init_counter[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~16_combout ), + .d(\sdram_|r.init_counter[8]~30_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58291,28 +62270,28 @@ defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N20 -cycloneive_lcell_comb \sdram_|Add1~18 ( +// Location: LCCOMB_X18_Y16_N20 +cycloneive_lcell_comb \sdram_|r.init_counter[9]~32 ( // Equation(s): -// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) -// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) +// \sdram_|r.init_counter[9]~32_combout = (\sdram_|r.init_counter [9] & (\sdram_|r.init_counter[8]~31 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter[8]~31 )) +// \sdram_|r.init_counter[9]~33 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|r.init_counter[8]~31 )) .dataa(gnd), .datab(\sdram_|r.init_counter [9]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~17 ), - .combout(\sdram_|Add1~18_combout ), - .cout(\sdram_|Add1~19 )); + .cin(\sdram_|r.init_counter[8]~31 ), + .combout(\sdram_|r.init_counter[9]~32_combout ), + .cout(\sdram_|r.init_counter[9]~33 )); // synopsys translate_off -defparam \sdram_|Add1~18 .lut_mask = 16'hC303; -defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[9]~32 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[9]~32 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N21 +// Location: FF_X18_Y16_N21 dffeas \sdram_|r.init_counter[9] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~18_combout ), + .d(\sdram_|r.init_counter[9]~32_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58328,28 +62307,28 @@ defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N22 -cycloneive_lcell_comb \sdram_|Add1~20 ( +// Location: LCCOMB_X18_Y16_N22 +cycloneive_lcell_comb \sdram_|r.init_counter[10]~34 ( // Equation(s): -// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) -// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) +// \sdram_|r.init_counter[10]~34_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|r.init_counter[9]~33 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|r.init_counter[9]~33 $ (GND))) +// \sdram_|r.init_counter[10]~35 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|r.init_counter[9]~33 )) .dataa(\sdram_|r.init_counter [10]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~19 ), - .combout(\sdram_|Add1~20_combout ), - .cout(\sdram_|Add1~21 )); + .cin(\sdram_|r.init_counter[9]~33 ), + .combout(\sdram_|r.init_counter[10]~34_combout ), + .cout(\sdram_|r.init_counter[10]~35 )); // synopsys translate_off -defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[10]~34 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[10]~34 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N23 +// Location: FF_X18_Y16_N23 dffeas \sdram_|r.init_counter[10] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~20_combout ), + .d(\sdram_|r.init_counter[10]~34_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58365,62 +62344,28 @@ defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N22 -cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Location: LCCOMB_X18_Y16_N24 +cycloneive_lcell_comb \sdram_|r.init_counter[11]~36 ( // Equation(s): -// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|r.init_counter [4]), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; -defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N0 -cycloneive_lcell_comb \sdram_|Equal2~1 ( -// Equation(s): -// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [3]), - .cin(gnd), - .combout(\sdram_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; -defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y3_N24 -cycloneive_lcell_comb \sdram_|Add1~22 ( -// Equation(s): -// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) -// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) +// \sdram_|r.init_counter[11]~36_combout = (\sdram_|r.init_counter [11] & (\sdram_|r.init_counter[10]~35 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter[10]~35 )) +// \sdram_|r.init_counter[11]~37 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|r.init_counter[10]~35 )) .dataa(gnd), .datab(\sdram_|r.init_counter [11]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~21 ), - .combout(\sdram_|Add1~22_combout ), - .cout(\sdram_|Add1~23 )); + .cin(\sdram_|r.init_counter[10]~35 ), + .combout(\sdram_|r.init_counter[11]~36_combout ), + .cout(\sdram_|r.init_counter[11]~37 )); // synopsys translate_off -defparam \sdram_|Add1~22 .lut_mask = 16'hC303; -defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[11]~36 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[11]~36 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N25 +// Location: FF_X18_Y16_N25 dffeas \sdram_|r.init_counter[11] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~22_combout ), + .d(\sdram_|r.init_counter[11]~36_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58436,28 +62381,28 @@ defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N26 -cycloneive_lcell_comb \sdram_|Add1~24 ( +// Location: LCCOMB_X18_Y16_N26 +cycloneive_lcell_comb \sdram_|r.init_counter[12]~38 ( // Equation(s): -// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) -// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) +// \sdram_|r.init_counter[12]~38_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|r.init_counter[11]~37 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|r.init_counter[11]~37 $ (GND))) +// \sdram_|r.init_counter[12]~39 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|r.init_counter[11]~37 )) .dataa(\sdram_|r.init_counter [12]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~23 ), - .combout(\sdram_|Add1~24_combout ), - .cout(\sdram_|Add1~25 )); + .cin(\sdram_|r.init_counter[11]~37 ), + .combout(\sdram_|r.init_counter[12]~38_combout ), + .cout(\sdram_|r.init_counter[12]~39 )); // synopsys translate_off -defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; -defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[12]~38 .lut_mask = 16'h5AAF; +defparam \sdram_|r.init_counter[12]~38 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N27 +// Location: FF_X18_Y16_N27 dffeas \sdram_|r.init_counter[12] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~24_combout ), + .d(\sdram_|r.init_counter[12]~38_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58473,28 +62418,28 @@ defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N28 -cycloneive_lcell_comb \sdram_|Add1~26 ( +// Location: LCCOMB_X18_Y16_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[13]~40 ( // Equation(s): -// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) -// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) +// \sdram_|r.init_counter[13]~40_combout = (\sdram_|r.init_counter [13] & (\sdram_|r.init_counter[12]~39 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter[12]~39 )) +// \sdram_|r.init_counter[13]~41 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|r.init_counter[12]~39 )) .dataa(gnd), .datab(\sdram_|r.init_counter [13]), .datac(gnd), .datad(vcc), - .cin(\sdram_|Add1~25 ), - .combout(\sdram_|Add1~26_combout ), - .cout(\sdram_|Add1~27 )); + .cin(\sdram_|r.init_counter[12]~39 ), + .combout(\sdram_|r.init_counter[13]~40_combout ), + .cout(\sdram_|r.init_counter[13]~41 )); // synopsys translate_off -defparam \sdram_|Add1~26 .lut_mask = 16'hC303; -defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[13]~40 .lut_mask = 16'hC303; +defparam \sdram_|r.init_counter[13]~40 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N29 +// Location: FF_X18_Y16_N29 dffeas \sdram_|r.init_counter[13] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~26_combout ), + .d(\sdram_|r.init_counter[13]~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58510,27 +62455,27 @@ defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N30 -cycloneive_lcell_comb \sdram_|Add1~28 ( +// Location: LCCOMB_X18_Y16_N30 +cycloneive_lcell_comb \sdram_|r.init_counter[14]~42 ( // Equation(s): -// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) +// \sdram_|r.init_counter[14]~42_combout = \sdram_|r.init_counter [14] $ (\sdram_|r.init_counter[13]~41 ) .dataa(\sdram_|r.init_counter [14]), .datab(gnd), .datac(gnd), .datad(gnd), - .cin(\sdram_|Add1~27 ), - .combout(\sdram_|Add1~28_combout ), + .cin(\sdram_|r.init_counter[13]~41 ), + .combout(\sdram_|r.init_counter[14]~42_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; -defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +defparam \sdram_|r.init_counter[14]~42 .lut_mask = 16'h5A5A; +defparam \sdram_|r.init_counter[14]~42 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X21_Y3_N31 +// Location: FF_X18_Y16_N31 dffeas \sdram_|r.init_counter[14] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Add1~28_combout ), + .d(\sdram_|r.init_counter[14]~42_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58546,15 +62491,32 @@ defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; defparam \sdram_|r.init_counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y3_N0 +// Location: LCCOMB_X19_Y16_N2 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0003; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y16_N0 cycloneive_lcell_comb \sdram_|process_0~5 ( // Equation(s): -// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [10] & !\sdram_|r.init_counter [9]))) - .dataa(\sdram_|r.init_counter [14]), + .dataa(\sdram_|r.init_counter [8]), .datab(\sdram_|r.init_counter [11]), - .datac(\sdram_|r.init_counter [12]), - .datad(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [10]), + .datad(\sdram_|r.init_counter [9]), .cin(gnd), .combout(\sdram_|process_0~5_combout ), .cout()); @@ -58563,129 +62525,95 @@ defparam \sdram_|process_0~5 .lut_mask = 16'h0001; defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y3_N6 +// Location: LCCOMB_X19_Y16_N10 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [3] & (!\sdram_|r.init_counter [4] & (!\sdram_|r.init_counter [2] & !\sdram_|r.init_counter [5]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|r.init_counter [4]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [5]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N0 cycloneive_lcell_comb \sdram_|Equal2~2 ( // Equation(s): -// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) +// \sdram_|Equal2~2_combout = (!\sdram_|r.init_counter [6] & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & \sdram_|Equal2~0_combout ))) - .dataa(\sdram_|Equal2~0_combout ), + .dataa(\sdram_|r.init_counter [6]), .datab(\sdram_|Equal2~1_combout ), .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [2]), + .datad(\sdram_|Equal2~0_combout ), .cin(gnd), .combout(\sdram_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .lut_mask = 16'h4000; defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~11 ( -// Equation(s): -// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(gnd), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Mux9~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; -defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux9~12 ( -// Equation(s): -// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) - - .dataa(\sdram_|n~2_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux9~11_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; -defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N0 -cycloneive_lcell_comb \sdram_|Mux9~13 ( -// Equation(s): -// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|n~2_combout ), - .datad(\sdram_|Mux9~12_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; -defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N2 +// Location: LCCOMB_X19_Y16_N4 cycloneive_lcell_comb \sdram_|Mux8~0 ( // Equation(s): -// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) +// \sdram_|Mux8~0_combout = (\sdram_|r.init_counter [0] & (!\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|Mux9~10_combout ), - .datad(\sdram_|Mux9~13_combout ), + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), .cin(gnd), .combout(\sdram_|Mux8~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .lut_mask = 16'h0200; defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y12_N16 -cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Location: LCCOMB_X19_Y19_N24 +cycloneive_lcell_comb \sdram_|Mux8~4 ( // Equation(s): -// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) +// \sdram_|Mux8~4_combout = (\sdram_|r.state [5] & (((\sdram_|Mux8~1_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux8~3_combout & ((\sdram_|Mux8~1_combout ) # (\sdram_|Mux8~0_combout )))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), + .dataa(\sdram_|Mux8~3_combout ), + .datab(\sdram_|Mux8~1_combout ), .datac(\sdram_|r.state [5]), .datad(\sdram_|Mux8~0_combout ), .cin(gnd), - .combout(\sdram_|Mux8~1_combout ), + .combout(\sdram_|Mux8~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; -defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~4 .lut_mask = 16'hCAC8; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux8~5 ( // Equation(s): -// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) +// \sdram_|Mux8~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~7_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~4_combout ))) .dataa(\sdram_|r.state [7]), .datab(gnd), - .datac(\sdram_|Mux8~4_combout ), - .datad(\sdram_|Mux8~1_combout ), + .datac(\sdram_|Mux8~7_combout ), + .datad(\sdram_|Mux8~4_combout ), .cin(gnd), - .combout(\sdram_|Mux8~2_combout ), + .combout(\sdram_|Mux8~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; -defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux8~5 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y15_N21 +// Location: FF_X23_Y19_N5 dffeas \sdram_|r.state[4] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux8~2_combout ), + .d(\sdram_|Mux8~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58701,49 +62629,49 @@ defparam \sdram_|r.state[4] .is_wysiwyg = "true"; defparam \sdram_|r.state[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 +// Location: LCCOMB_X23_Y19_N18 cycloneive_lcell_comb \sdram_|Mux72~0 ( // Equation(s): -// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux72~0_combout = (\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [0]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux72~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 +// Location: LCCOMB_X23_Y19_N20 cycloneive_lcell_comb \sdram_|Mux72~1 ( // Equation(s): -// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux72~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux72~0_combout & ((\Selector14~14_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .dataa(\Equal5~1_combout ), + .datab(\sdram_|r.state [4]), .datac(\sdram_|Mux72~0_combout ), - .datad(\D[0]~64_combout ), + .datad(\Selector14~14_combout ), .cin(gnd), .combout(\sdram_|Mux72~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .lut_mask = 16'hC040; defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N0 +// Location: LCCOMB_X23_Y19_N6 cycloneive_lcell_comb \sdram_|Mux84~0 ( // Equation(s): -// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) +// \sdram_|Mux84~0_combout = (\sdram_|r.state [4]) # (\sdram_|r.state [5]) .dataa(gnd), .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux84~0_combout ), .cout()); @@ -58752,245 +62680,245 @@ defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y15_N2 +// Location: LCCOMB_X23_Y19_N28 cycloneive_lcell_comb \sdram_|Mux84~1 ( // Equation(s): -// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) +// \sdram_|Mux84~1_combout = (\sdram_|r.state [7] & (!\sdram_|r.state [8] & (\sdram_|r.state [6] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.state [8] & (!\sdram_|r.state [6] & !\sdram_|Mux84~0_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [8]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|Mux84~0_combout ), .cin(gnd), .combout(\sdram_|Mux84~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .lut_mask = 16'h2004; defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 +// Location: LCCOMB_X23_Y19_N26 cycloneive_lcell_comb \sdram_|Mux3~0 ( // Equation(s): -// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux3~0_combout = (\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) - .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\sdram_|r.state [4]), + .dataa(\z80_|data_pins_|dout [1]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .cin(gnd), .combout(\sdram_|Mux3~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .lut_mask = 16'hAAFF; defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 +// Location: LCCOMB_X23_Y19_N8 cycloneive_lcell_comb \sdram_|Mux3~1 ( // Equation(s): -// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & (\sdram_|r.state [4] & ((\Selector12~11_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux3~0_combout ), - .datad(\D[1]~40_combout ), + .dataa(\sdram_|Mux3~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector12~11_combout ), .cin(gnd), .combout(\sdram_|Mux3~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .lut_mask = 16'h8808; defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N0 +// Location: LCCOMB_X27_Y19_N8 cycloneive_lcell_comb \sdram_|Mux2~0 ( // Equation(s): -// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux2~0_combout = (\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datac(\z80_|data_pins_|dout [2]), - .datad(\sdram_|r.state [4]), + .datad(gnd), .cin(gnd), .combout(\sdram_|Mux2~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .lut_mask = 16'hF3F3; defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 +// Location: LCCOMB_X23_Y19_N30 cycloneive_lcell_comb \sdram_|Mux2~1 ( // Equation(s): -// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & (\sdram_|r.state [4] & ((\Selector10~3_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux2~0_combout ), - .datad(\D[2]~52_combout ), + .dataa(\sdram_|Mux2~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Selector10~3_combout ), + .datad(\Equal5~1_combout ), .cin(gnd), .combout(\sdram_|Mux2~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .lut_mask = 16'h8088; defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y16_N6 cycloneive_lcell_comb \sdram_|Mux1~0 ( // Equation(s): -// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux1~0_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\sdram_|Mux1~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N10 +// Location: LCCOMB_X24_Y15_N4 cycloneive_lcell_comb \sdram_|Mux1~1 ( // Equation(s): -// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux1~1_combout = (\sdram_|r.state [4] & (\sdram_|Mux1~0_combout & ((\Selector8~9_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\D[3]~108_combout ), - .datad(\sdram_|Mux1~0_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|Mux1~0_combout ), + .datac(\Equal5~1_combout ), + .datad(\Selector8~9_combout ), .cin(gnd), .combout(\sdram_|Mux1~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .lut_mask = 16'h8808; defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N12 +// Location: LCCOMB_X25_Y16_N8 cycloneive_lcell_comb \sdram_|Mux0~0 ( // Equation(s): -// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux0~0_combout = (\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [4]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [4]), .cin(gnd), .combout(\sdram_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 +// Location: LCCOMB_X23_Y19_N12 cycloneive_lcell_comb \sdram_|Mux0~1 ( // Equation(s): -// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & (\sdram_|r.state [4] & ((\Selector6~7_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux0~0_combout ), - .datad(\D[4]~110_combout ), + .dataa(\sdram_|Mux0~0_combout ), + .datab(\sdram_|r.state [4]), + .datac(\Equal5~1_combout ), + .datad(\Selector6~7_combout ), .cin(gnd), .combout(\sdram_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .lut_mask = 16'h8808; defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 +// Location: LCCOMB_X29_Y19_N4 cycloneive_lcell_comb \sdram_|Mux73~0 ( // Equation(s): -// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\D[5]~27_combout ) # (!\D[0]~49_combout ))) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[5]~27_combout ), .cin(gnd), .combout(\sdram_|Mux73~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .lut_mask = 16'hF030; defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \sdram_|Mux73~1 ( -// Equation(s): -// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\sdram_|Mux73~0_combout ), - .datad(\D[5]~112_combout ), - .cin(gnd), - .combout(\sdram_|Mux73~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; -defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N24 +// Location: LCCOMB_X26_Y16_N10 cycloneive_lcell_comb \sdram_|Mux74~0 ( // Equation(s): -// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) +// \sdram_|Mux74~0_combout = (\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) .dataa(gnd), - .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datac(\z80_|data_pins_|dout [6]), - .datad(\sdram_|r.state [4]), + .datab(gnd), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\z80_|data_pins_|dout [6]), .cin(gnd), .combout(\sdram_|Mux74~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .lut_mask = 16'hFF0F; defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N6 +// Location: LCCOMB_X23_Y19_N14 cycloneive_lcell_comb \sdram_|Mux74~1 ( // Equation(s): -// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & (\sdram_|r.state [4] & ((\D[6]~46_combout ) # (!\Equal5~1_combout )))) - .dataa(\Equal2~1_combout ), + .dataa(\Equal5~1_combout ), .datab(\sdram_|Mux74~0_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), - .datad(\D[6]~114_combout ), + .datac(\sdram_|r.state [4]), + .datad(\D[6]~46_combout ), .cin(gnd), .combout(\sdram_|Mux74~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .lut_mask = 16'hC040; defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X17_Y4_N28 +// Location: LCCOMB_X24_Y16_N8 cycloneive_lcell_comb \sdram_|Mux75~0 ( // Equation(s): -// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & ((\D[7]~37_combout ) # (!\D[0]~49_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [4]), - .datad(\D[7]~117_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\D[0]~49_combout ), + .datac(gnd), + .datad(\D[7]~37_combout ), .cin(gnd), .combout(\sdram_|Mux75~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .lut_mask = 16'hAA22; defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N8 +// Location: LCCOMB_X1_Y10_N16 +cycloneive_lcell_comb \LED~0 ( +// Equation(s): +// \LED~0_combout = (!\kempston[4]~input_o & \kempston_auto_fire~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\kempston[4]~input_o ), + .datad(\kempston_auto_fire~q ), + .cin(gnd), + .combout(\LED~0_combout ), + .cout()); +// synopsys translate_off +defparam \LED~0 .lut_mask = 16'h0F00; +defparam \LED~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -59007,7 +62935,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N9 +// Location: FF_X21_Y33_N13 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -59045,24 +62973,43 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N12 +// Location: FF_X24_Y19_N13 +dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N14 +// Location: LCCOMB_X25_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -59080,24 +63027,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N0 +// Location: LCCOMB_X25_Y30_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N1 +// Location: FF_X25_Y30_N29 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -59116,42 +63063,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N16 +// Location: LCCOMB_X25_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N6 +// Location: LCCOMB_X26_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~4_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~4_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N7 +// Location: FF_X26_Y30_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -59170,25 +63117,25 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N18 +// Location: LCCOMB_X25_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(\ula_|i2s_intf_|lrdivider [3]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [3]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y32_N30 +// Location: LCCOMB_X26_Y30_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout @@ -59205,7 +63152,7 @@ defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y32_N31 +// Location: FF_X26_Y30_N9 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -59224,7 +63171,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N20 +// Location: LCCOMB_X25_Y30_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -59242,24 +63189,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N4 +// Location: LCCOMB_X25_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~8_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~8_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N5 +// Location: FF_X25_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -59278,7 +63225,7 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N22 +// Location: LCCOMB_X25_Y30_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) @@ -59296,24 +63243,24 @@ defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N4 +// Location: LCCOMB_X26_Y30_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~10_combout ), + .datac(\ula_|i2s_intf_|Add0~10_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N5 +// Location: FF_X26_Y30_N7 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -59332,24 +63279,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N10 +// Location: LCCOMB_X25_Y30_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|lrdivider [4] & \ula_|i2s_intf_|lrdivider [2]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), - .datac(\ula_|i2s_intf_|lrdivider [3]), - .datad(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(\ula_|i2s_intf_|lrdivider [3]), + .datac(\ula_|i2s_intf_|lrdivider [4]), + .datad(\ula_|i2s_intf_|lrdivider [2]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N24 +// Location: LCCOMB_X25_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -59367,7 +63314,7 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N22 +// Location: LCCOMB_X26_Y30_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -59384,7 +63331,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N23 +// Location: FF_X26_Y30_N13 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -59403,42 +63350,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N26 +// Location: LCCOMB_X25_Y30_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X21_Y31_N20 +// Location: LCCOMB_X26_Y30_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~14_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~14_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y31_N21 +// Location: FF_X26_Y30_N11 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -59457,7 +63404,7 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N28 +// Location: LCCOMB_X25_Y30_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) @@ -59475,24 +63422,24 @@ defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N8 +// Location: LCCOMB_X25_Y30_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|lrdivider~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~16_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Add0~16_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y31_N9 +// Location: FF_X25_Y30_N1 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -59511,7 +63458,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N30 +// Location: LCCOMB_X25_Y30_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -59528,24 +63475,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X19_Y31_N24 +// Location: LCCOMB_X26_Y30_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~18_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~18_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X19_Y31_N25 +// Location: FF_X26_Y30_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -59564,73 +63511,54 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N6 +// Location: LCCOMB_X25_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [6] & !\ula_|i2s_intf_|lrdivider [8]))) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [8]), - .datad(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [9]), + .datab(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [6]), + .datad(\ula_|i2s_intf_|lrdivider [8]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y31_N2 +// Location: LCCOMB_X25_Y30_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|Equal0~0_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & !\ula_|i2s_intf_|lrdivider [1]))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|Equal0~0_combout ), - .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|lrdivider [1]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h0080; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N29 -dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N30 +// Location: LCCOMB_X24_Y19_N12 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): -// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) +// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q $ (\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(gnd), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59672,43 +63600,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; -defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y32_N9 -dffeas \ula_|i2s_intf_|bdivider[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N14 +// Location: LCCOMB_X24_Y23_N14 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -59726,303 +63618,50 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|bclk_r~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N25 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y32_N15 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N17 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N19 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N21 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(\ula_|i2s_intf_|bitcount [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X24_Y32_N23 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(\ula_|i2s_intf_|bitcount [0]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; -defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N18 +// Location: LCCOMB_X24_Y19_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): // \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [0]), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add2~7_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N20 +// Location: LCCOMB_X24_Y19_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( // Equation(s): // \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) // \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [1]), + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~7_cout ), .combout(\ula_|i2s_intf_|Add2~8_combout ), .cout(\ula_|i2s_intf_|Add2~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N4 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( // Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|bdivider [0]) # (!\ula_|i2s_intf_|Equal1~0_combout )))) - .dataa(\ula_|i2s_intf_|bdivider [0]), + .dataa(\ula_|i2s_intf_|Equal1~0_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|Add2~8_combout ), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~20_combout ), .cout()); @@ -60031,7 +63670,7 @@ defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N5 +// Location: FF_X24_Y19_N31 dffeas \ula_|i2s_intf_|bdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~20_combout ), @@ -60050,7 +63689,7 @@ defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N22 +// Location: LCCOMB_X24_Y19_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( // Equation(s): // \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) @@ -60068,24 +63707,24 @@ defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N16 +// Location: LCCOMB_X24_Y23_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( // Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~10_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~10_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~10_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N17 +// Location: FF_X24_Y23_N31 dffeas \ula_|i2s_intf_|bdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~17_combout ), @@ -60104,42 +63743,42 @@ defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N24 +// Location: LCCOMB_X24_Y19_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( // Equation(s): // \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) // \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add2~11 ), .combout(\ula_|i2s_intf_|Add2~12_combout ), .cout(\ula_|i2s_intf_|Add2~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N14 +// Location: LCCOMB_X24_Y23_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( // Equation(s): // \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Add2~12_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Add2~12_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h0222; defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N15 +// Location: FF_X24_Y23_N1 dffeas \ula_|i2s_intf_|bdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~19_combout ), @@ -60158,7 +63797,7 @@ defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N26 +// Location: LCCOMB_X24_Y19_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( // Equation(s): // \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) @@ -60175,24 +63814,24 @@ defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N6 +// Location: LCCOMB_X24_Y23_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( // Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((!\ula_|i2s_intf_|LessThan0~1_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|Add2~14_combout )))) - .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .dataa(\ula_|i2s_intf_|Add2~14_combout ), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Add2~14_combout ), - .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|LessThan0~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Add2~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0131; defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N7 +// Location: FF_X24_Y23_N25 dffeas \ula_|i2s_intf_|bdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~16_combout ), @@ -60211,78 +63850,333 @@ defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N2 +// Location: LCCOMB_X24_Y19_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & (!\ula_|i2s_intf_|bdivider [1] & \ula_|i2s_intf_|bdivider [4]))) - .dataa(\ula_|i2s_intf_|bdivider [4]), - .datab(\ula_|i2s_intf_|bdivider [1]), - .datac(\ula_|i2s_intf_|bdivider [3]), - .datad(\ula_|i2s_intf_|bdivider [2]), + .dataa(\ula_|i2s_intf_|bdivider [3]), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(\ula_|i2s_intf_|bdivider [1]), + .datad(\ula_|i2s_intf_|bdivider [4]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0400; defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N28 +// Location: LCCOMB_X24_Y23_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (((!\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~0_combout )) # (!\ula_|i2s_intf_|bdivider [0]))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1303; +defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N27 +dffeas \ula_|i2s_intf_|bdivider[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N4 cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [0]), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hAA00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) +// Location: FF_X24_Y23_N29 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), +// Location: LCCOMB_X24_Y23_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~9_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~9 .lut_mask = 16'hCCEC; +defparam \ula_|i2s_intf_|bitcount[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y23_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~10 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~10_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~11 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~10 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~12 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~12_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~11 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~11 )) +// \ula_|i2s_intf_|bitcount[3]~13 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~11 ), + .combout(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~12_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~14 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~14_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~13 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~13 ), + .combout(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~14 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y23_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [2]), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~1 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~1_combout = (\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]) + + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~1 .lut_mask = 16'hFF0F; +defparam \ula_|i2s_intf_|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~1_combout & \ula_|i2s_intf_|Equal1~1_combout ))))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h0078; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( -// Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bclk_r~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; -defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X14_Y34_N18 dffeas \ula_|i2s_intf_|bclk_r ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -60298,15 +64192,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N16 +// Location: LCCOMB_X23_Y18_N26 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~38_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~109_combout ), + .datad(\D[3]~38_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -60315,41 +64209,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N30 +// Location: LCCOMB_X23_Y17_N0 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) +// \ula_|always0~2_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(gnd), - .datab(\z80_|memory_ifc_|nWR_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .datac(\z80_|memory_ifc_|nWR_out~0_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h00C0; +defparam \ula_|always0~2 .lut_mask = 16'h2020; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N2 +// Location: LCCOMB_X23_Y17_N24 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [0]), - .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h0200; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N17 +// Location: FF_X23_Y18_N27 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -60368,538 +64262,25 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y32_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; -defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X23_Y34_N22 -cycloneive_io_ibuf \AUD_ADCDAT~input ( - .i(AUD_ADCDAT), - .ibar(gnd), - .o(\AUD_ADCDAT~input_o )); -// synopsys translate_off -defparam \AUD_ADCDAT~input .bus_hold = "false"; -defparam \AUD_ADCDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datac(\ula_|i2s_intf_|shiftreg [0]), - .datad(\AUD_ADCDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; -defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N7 -dffeas \ula_|i2s_intf_|shiftreg[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y32_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; -defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N29 -dffeas \ula_|i2s_intf_|shiftreg[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N15 -dffeas \ula_|i2s_intf_|shiftreg[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N17 -dffeas \ula_|i2s_intf_|shiftreg[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N23 -dffeas \ula_|i2s_intf_|shiftreg[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~15_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(\ula_|i2s_intf_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; -defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N13 -dffeas \ula_|i2s_intf_|shiftreg[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~14_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N19 -dffeas \ula_|i2s_intf_|shiftreg[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~13_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N9 -dffeas \ula_|i2s_intf_|shiftreg[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [7]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N3 -dffeas \ula_|i2s_intf_|shiftreg[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~11_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [8]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N5 -dffeas \ula_|i2s_intf_|shiftreg[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~10_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N10 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [9]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; -defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N11 -dffeas \ula_|i2s_intf_|shiftreg[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~9_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [10]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N1 -dffeas \ula_|i2s_intf_|shiftreg[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~8_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y33_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|shiftreg [11]), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; -defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y33_N27 -dffeas \ula_|i2s_intf_|shiftreg[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~7_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|shiftreg [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y32_N10 +// Location: LCCOMB_X24_Y19_N26 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INR [14]))))) # +// (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INR [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hD8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N11 +// Location: FF_X24_Y19_N27 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -60918,25 +64299,25 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N12 +// Location: LCCOMB_X24_Y19_N20 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (((\ula_|i2s_intf_|PCM_INL [14])))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) # +// (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|PCM_INL [14]))))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datab(\ula_|i2s_intf_|shiftreg [14]), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hE4F0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N13 +// Location: FF_X24_Y19_N21 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -60955,24 +64336,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y32_N0 +// Location: LCCOMB_X24_Y19_N14 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(\ula_|i2s_intf_|PCM_INR [14]), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\ula_|i2s_intf_|PCM_INR [14]), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y32_N1 +// Location: FF_X24_Y19_N15 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -60991,25 +64372,502 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N20 +// Location: LCCOMB_X24_Y23_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~18 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~18_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~18 .lut_mask = 16'h008C; +defparam \ula_|i2s_intf_|shiftreg[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y34_N22 +cycloneive_io_ibuf \AUD_ADCDAT~input ( + .i(AUD_ADCDAT), + .ibar(gnd), + .o(\AUD_ADCDAT~input_o )); +// synopsys translate_off +defparam \AUD_ADCDAT~input .bus_hold = "false"; +defparam \AUD_ADCDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|shiftreg[0]~18_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # +// (!\ula_|i2s_intf_|shiftreg[0]~18_combout & (((\ula_|i2s_intf_|shiftreg [0])))) + + .dataa(\ula_|i2s_intf_|shiftreg[0]~18_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\AUD_ADCDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N27 +dffeas \ula_|i2s_intf_|shiftreg[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg[0]~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [0]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y23_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[7]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[7]~1_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|LessThan0~1_combout & (\ula_|i2s_intf_|Equal1~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))) + + .dataa(\ula_|i2s_intf_|LessThan0~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal1~1_combout ), + .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7]~1 .lut_mask = 16'hECCC; +defparam \ula_|i2s_intf_|shiftreg[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N21 +dffeas \ula_|i2s_intf_|shiftreg[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N11 +dffeas \ula_|i2s_intf_|shiftreg[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N25 +dffeas \ula_|i2s_intf_|shiftreg[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~15_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N7 +dffeas \ula_|i2s_intf_|shiftreg[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N13 +dffeas \ula_|i2s_intf_|shiftreg[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~13_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N30 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N31 +dffeas \ula_|i2s_intf_|shiftreg[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [6]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N29 +dffeas \ula_|i2s_intf_|shiftreg[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~11_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N23 +dffeas \ula_|i2s_intf_|shiftreg[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~10_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [8]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N1 +dffeas \ula_|i2s_intf_|shiftreg[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~9_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [9]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [9]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N15 +dffeas \ula_|i2s_intf_|shiftreg[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~8_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2s_intf_|shiftreg [10]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N9 +dffeas \ula_|i2s_intf_|shiftreg[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~7_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) +// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|shiftreg [12]), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|pcm_outl [12]), + .datac(\ula_|i2s_intf_|shiftreg [11]), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N21 -dffeas \ula_|i2s_intf_|shiftreg[13] ( +// Location: FF_X24_Y30_N19 +dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), .asdata(vcc), @@ -61017,7 +64875,43 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|shiftreg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y30_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [12])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [12]))) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|pcm_outl [12]), + .datad(\ula_|i2s_intf_|shiftreg [12]), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hF3C0; +defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y30_N5 +dffeas \ula_|i2s_intf_|shiftreg[13] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -61027,33 +64921,33 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|pcm_outl [13]), .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~5_combout ), + .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; -defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF5A0; +defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N31 +// Location: FF_X24_Y21_N13 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~5_combout ), + .d(\ula_|i2s_intf_|shiftreg~4_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -61063,32 +64957,15 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N22 -cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( -// Equation(s): -// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[4]~111_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X23_Y19_N23 +// Location: FF_X25_Y19_N13 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[14]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[4]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -61099,33 +64976,33 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y33_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( +// Location: LCCOMB_X24_Y22_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [14]), .datad(\ula_|pcm_outl [14]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~4_combout ), + .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; -defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y33_N25 +// Location: FF_X24_Y22_N21 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~4_combout ), + .d(\ula_|i2s_intf_|shiftreg~3_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -61135,33 +65012,33 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( +// Location: LCCOMB_X24_Y30_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) +// \ula_|i2s_intf_|shiftreg~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg~3_combout ), + .combout(\ula_|i2s_intf_|shiftreg~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; -defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg~2 .lut_mask = 16'h3300; +defparam \ula_|i2s_intf_|shiftreg~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y33_N1 +// Location: FF_X24_Y30_N17 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|shiftreg~3_combout ), + .d(\ula_|i2s_intf_|shiftreg~2_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -61171,7 +65048,7 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y33_N14 +// Location: LCCOMB_X24_Y30_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) @@ -61197,7 +65074,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[7]~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -61207,1083 +65084,41 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y18_N12 -cycloneive_lcell_comb \ula_|border[1]~feeder ( -// Equation(s): -// \ula_|border[1]~feeder_combout = \D[1]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[1]~41_combout ), - .cin(gnd), - .combout(\ula_|border[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y18_N13 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N28 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y30_N14 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y30_N6 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [6]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_hc [9]), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|LessThan4~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N24 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N0 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N20 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N1 -dffeas \ula_|video_|attr_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N7 -dffeas \ula_|video_|attr[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N4 -cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( -// Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - - .dataa(gnd), - .datab(\ula_|video_|Equal3~1_combout ), - .datac(gnd), - .datad(\ula_|video_|frame [0]), - .cin(gnd), - .combout(\ula_|video_|frame[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; -defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N21 -dffeas \ula_|video_|frame[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[0]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N14 -cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( -// Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - - .dataa(\ula_|video_|frame [1]), - .datab(\ula_|video_|frame [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|frame[1]~4_combout ), - .cout(\ula_|video_|frame[1]~5 )); -// synopsys translate_off -defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; -defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y30_N15 -dffeas \ula_|video_|frame[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[1]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N16 -cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( -// Equation(s): -// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) -// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - - .dataa(gnd), - .datab(\ula_|video_|frame [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[1]~5 ), - .combout(\ula_|video_|frame[2]~6_combout ), - .cout(\ula_|video_|frame[2]~7 )); -// synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N17 -dffeas \ula_|video_|frame[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[2]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N18 -cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( -// Equation(s): -// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) -// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) - - .dataa(gnd), - .datab(\ula_|video_|frame [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|frame[2]~7 ), - .combout(\ula_|video_|frame[3]~8_combout ), - .cout(\ula_|video_|frame[3]~9 )); -// synopsys translate_off -defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N19 -dffeas \ula_|video_|frame[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[3]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y30_N20 -cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( -// Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|frame [4]), - .cin(\ula_|video_|frame[3]~9 ), - .combout(\ula_|video_|frame[4]~10_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; -defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y30_N5 -dffeas \ula_|video_|frame[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|frame[4]~10_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Equal3~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|frame [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; -defparam \ula_|video_|frame[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N6 -cycloneive_lcell_comb \ula_|video_|inverted ( -// Equation(s): -// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|attr [7]), - .datad(\ula_|video_|frame [4]), - .cin(gnd), - .combout(\ula_|video_|inverted~combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|inverted .lut_mask = 16'hF000; -defparam \ula_|video_|inverted .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N28 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y29_N14 -cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( -// Equation(s): -// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - - .dataa(\ula_|video_|vga_hc [0]), - .datab(\ula_|video_|vga_hc [2]), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|vga_hc [1]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; -defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N29 -dffeas \ula_|video_|bits_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N5 -dffeas \ula_|video_|bits[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N26 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N27 -dffeas \ula_|video_|bits_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N29 -dffeas \ula_|video_|bits[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N14 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N15 -dffeas \ula_|video_|bits_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N24 -cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( -// Equation(s): -// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [5]), - .cin(gnd), - .combout(\ula_|video_|bits[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N25 -dffeas \ula_|video_|bits[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N12 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N13 -dffeas \ula_|video_|bits_prefetch[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N19 -dffeas \ula_|video_|bits[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N18 -cycloneive_lcell_comb \ula_|video_|Mux0~0 ( -// Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [5]), - .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N28 -cycloneive_lcell_comb \ula_|video_|Mux0~1 ( -// Equation(s): -// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [6]), - .datac(\ula_|video_|bits [4]), - .datad(\ula_|video_|Mux0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N20 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N21 -dffeas \ula_|video_|bits_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N14 -cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( -// Equation(s): -// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [2]), - .cin(gnd), - .combout(\ula_|video_|bits[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N15 -dffeas \ula_|video_|bits[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N18 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N19 -dffeas \ula_|video_|bits_prefetch[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N1 -dffeas \ula_|video_|bits[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N6 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N7 -dffeas \ula_|video_|bits_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N20 -cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( -// Equation(s): -// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [1]), - .cin(gnd), - .combout(\ula_|video_|bits[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y30_N21 -dffeas \ula_|video_|bits[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N24 -cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( -// Equation(s): -// \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N25 -dffeas \ula_|video_|bits_prefetch[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits_prefetch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N3 -dffeas \ula_|video_|bits[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|bits_prefetch [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|bits [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; -defparam \ula_|video_|bits[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N2 -cycloneive_lcell_comb \ula_|video_|Mux0~2 ( -// Equation(s): -// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [1]), - .datac(\ula_|video_|bits [3]), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Mux0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; -defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N0 -cycloneive_lcell_comb \ula_|video_|Mux0~3 ( -// Equation(s): -// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - - .dataa(\ula_|video_|vga_hc [1]), - .datab(\ula_|video_|bits [2]), - .datac(\ula_|video_|bits [0]), - .datad(\ula_|video_|Mux0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|Mux0~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; -defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y30_N10 -cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( -// Equation(s): -// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - - .dataa(\ula_|video_|inverted~combout ), - .datab(\ula_|video_|Mux0~1_combout ), - .datac(\ula_|video_|vga_hc [3]), - .datad(\ula_|video_|Mux0~3_combout ), - .cin(gnd), - .combout(\ula_|video_|cindex[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; -defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N17 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N4 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N5 +// Location: LCCOMB_X30_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N29 dffeas \ula_|video_|attr_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), @@ -62302,7 +65137,24 @@ defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N19 +// Location: LCCOMB_X29_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N11 dffeas \ula_|video_|attr[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62321,82 +65173,832 @@ defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; defparam \ula_|video_|attr[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N16 +// Location: LCCOMB_X25_Y31_N6 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N7 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N27 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N21 +dffeas \ula_|video_|attr_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N7 +dffeas \ula_|video_|attr[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y31_N2 +cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( +// Equation(s): +// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) + + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|frame [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|frame[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h3C3C; +defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y31_N3 +dffeas \ula_|video_|frame[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N14 +cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( +// Equation(s): +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) + + .dataa(\ula_|video_|frame [0]), + .datab(\ula_|video_|frame [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|frame[1]~4_combout ), + .cout(\ula_|video_|frame[1]~5 )); +// synopsys translate_off +defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; +defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N15 +dffeas \ula_|video_|frame[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[1]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N16 +cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( +// Equation(s): +// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) +// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) + + .dataa(gnd), + .datab(\ula_|video_|frame [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[1]~5 ), + .combout(\ula_|video_|frame[2]~6_combout ), + .cout(\ula_|video_|frame[2]~7 )); +// synopsys translate_off +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N17 +dffeas \ula_|video_|frame[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[2]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N18 +cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( +// Equation(s): +// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) +// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 )) + + .dataa(gnd), + .datab(\ula_|video_|frame [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|frame[2]~7 ), + .combout(\ula_|video_|frame[3]~8_combout ), + .cout(\ula_|video_|frame[3]~9 )); +// synopsys translate_off +defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; +defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y31_N19 +dffeas \ula_|video_|frame[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N20 +cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( +// Equation(s): +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame [4]), + .cin(\ula_|video_|frame[3]~9 ), + .combout(\ula_|video_|frame[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; +defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N1 +dffeas \ula_|video_|frame[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|frame[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Equal3~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|frame [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; +defparam \ula_|video_|frame[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N6 +cycloneive_lcell_comb \ula_|video_|inverted ( +// Equation(s): +// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|attr [7]), + .datad(\ula_|video_|frame [4]), + .cin(gnd), + .combout(\ula_|video_|inverted~combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|inverted .lut_mask = 16'hF000; +defparam \ula_|video_|inverted .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N22 +cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( +// Equation(s): +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; +defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N13 +dffeas \ula_|video_|bits_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N1 +dffeas \ula_|video_|bits[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N19 +dffeas \ula_|video_|bits_prefetch[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N31 +dffeas \ula_|video_|bits[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N15 +dffeas \ula_|video_|bits_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N22 +cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( +// Equation(s): +// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|bits_prefetch [1]), + .cin(gnd), + .combout(\ula_|video_|bits[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y31_N23 +dffeas \ula_|video_|bits[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N17 +dffeas \ula_|video_|bits_prefetch[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N21 +dffeas \ula_|video_|bits[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Mux0~2 ( +// Equation(s): +// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [1]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [3] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [1]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N30 +cycloneive_lcell_comb \ula_|video_|Mux0~3 ( +// Equation(s): +// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), + .datac(\ula_|video_|bits [0]), + .datad(\ula_|video_|Mux0~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N4 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N5 +dffeas \ula_|video_|bits_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y31_N29 +dffeas \ula_|video_|bits[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N11 +dffeas \ula_|video_|bits_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N19 +dffeas \ula_|video_|bits[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N30 +cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N31 +dffeas \ula_|video_|bits_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N25 +dffeas \ula_|video_|bits[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y31_N9 +dffeas \ula_|video_|bits_prefetch[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits_prefetch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N29 +dffeas \ula_|video_|bits[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|bits [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; +defparam \ula_|video_|bits[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N28 +cycloneive_lcell_comb \ula_|video_|Mux0~0 ( +// Equation(s): +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|bits [5]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|bits [7]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; +defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Mux0~1 ( +// Equation(s): +// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), + .datac(\ula_|video_|bits [4]), + .datad(\ula_|video_|Mux0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; +defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N16 +cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Equation(s): +// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~3_combout )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~1_combout ))))) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(\ula_|video_|inverted~combout ), + .datac(\ula_|video_|Mux0~3_combout ), + .datad(\ula_|video_|Mux0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|cindex[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h396C; +defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N26 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), + .dataa(\ula_|video_|attr [1]), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|attr [1]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N4 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y31_N20 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [6]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|video_|LessThan6~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N2 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [4]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y30_N14 +// Location: LCCOMB_X27_Y31_N10 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): // \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|Equal2~0_combout ), + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|Equal2~0_combout ), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N0 +// Location: LCCOMB_X26_Y31_N24 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(\ula_|video_|vga_hc [5]), .datab(gnd), - .datac(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), @@ -62406,84 +66008,189 @@ defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y30_N4 +// Location: LCCOMB_X26_Y31_N30 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): // \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & // !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_hc [7]), .datac(\ula_|video_|vga_hc [9]), .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7A5E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N12 +// Location: LCCOMB_X27_Y31_N16 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [6]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [7]), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|vga_vc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|LessThan6~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h4F00; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N24 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) +// \ula_|video_|disp_enable~1_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & !\ula_|video_|LessThan2~1_combout )) - .dataa(gnd), - .datab(\ula_|video_|LessThan2~1_combout ), - .datac(\ula_|video_|LessThan3~0_combout ), - .datad(\ula_|video_|disp_enable~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), + .datac(gnd), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h0088; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N26 -cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( -// Equation(s): -// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - - .dataa(\ula_|border [1]), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(\ula_|video_|disp_enable~1_combout ), - .cin(gnd), - .combout(\ula_|video_|VGA_R[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; -defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N22 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N23 -dffeas \ula_|video_|attr_prefetch[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), +// Location: FF_X24_Y19_N17 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[1]~12_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y31_N0 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y31_N26 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [6])) # (!\ula_|video_|vga_hc [7]) + + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N24 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1203; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y31_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|LessThan6~1_combout ), + .datad(\ula_|video_|screen_en~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N10 +cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( +// Equation(s): +// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & (\ula_|video_|cindex[1]~1_combout )) # (!\ula_|video_|screen_en~1_combout & ((\ula_|border [1]))))) + + .dataa(\ula_|video_|cindex[1]~1_combout ), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [1]), + .datad(\ula_|video_|screen_en~1_combout ), + .cin(gnd), + .combout(\ula_|video_|VGA_R[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'h88C0; +defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N23 +dffeas \ula_|video_|attr_prefetch[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62494,7 +66201,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X31_Y30_N29 +// Location: FF_X27_Y31_N27 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62513,66 +66220,49 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N28 +// Location: LCCOMB_X27_Y31_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & \ula_|video_|LessThan3~0_combout ))) - .dataa(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan2~1_combout ), .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|LessThan2~1_combout ), + .datad(\ula_|video_|LessThan3~0_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N6 +// Location: LCCOMB_X28_Y31_N4 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|cindex[1]~1_combout ), - .datad(gnd), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y27_N20 -cycloneive_lcell_comb \ula_|border[2]~feeder ( -// Equation(s): -// \ula_|border[2]~feeder_combout = \D[2]~53_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[2]~53_combout ), - .cin(gnd), - .combout(\ula_|border[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y27_N21 +// Location: FF_X24_Y19_N5 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[2]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[2]~13_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62583,79 +66273,24 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N30 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y28_N31 -dffeas \ula_|video_|attr_prefetch[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y30_N31 -dffeas \ula_|video_|attr[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y28_N16 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N17 +// Location: FF_X25_Y31_N25 dffeas \ula_|video_|attr_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), @@ -62674,15 +66309,32 @@ defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N13 +// Location: LCCOMB_X28_Y31_N30 +cycloneive_lcell_comb \ula_|video_|attr[2]~feeder ( +// Equation(s): +// \ula_|video_|attr[2]~feeder_combout = \ula_|video_|attr_prefetch [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [2]), + .cin(gnd), + .combout(\ula_|video_|attr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N31 dffeas \ula_|video_|attr[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), + .d(\ula_|video_|attr[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62693,48 +66345,103 @@ defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; defparam \ula_|video_|attr[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N30 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 +dffeas \ula_|video_|attr_prefetch[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y31_N5 +dffeas \ula_|video_|attr[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y31_N4 cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) - .dataa(\ula_|video_|cindex[2]~0_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|attr [2]), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|attr [2]), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N0 +// Location: LCCOMB_X29_Y31_N2 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|border [2]), - .datad(\ula_|video_|cindex[2]~2_combout ), + .dataa(\ula_|border [2]), + .datab(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|video_|cindex[2]~2_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hC088; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y30_N18 +// Location: LCCOMB_X28_Y31_N12 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[2]~2_combout )) - .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(gnd), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|VGA_B[1]~0_combout ), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), @@ -62744,32 +66451,15 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X26_Y15_N4 -cycloneive_lcell_comb \ula_|border[0]~feeder ( -// Equation(s): -// \ula_|border[0]~feeder_combout = \D[0]~65_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[0]~65_combout ), - .cin(gnd), - .combout(\ula_|border[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y15_N5 +// Location: FF_X23_Y20_N25 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|border[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\D[0]~14_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62780,24 +66470,24 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N8 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[0]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N9 +// Location: FF_X25_Y31_N1 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -62816,15 +66506,32 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y30_N23 +// Location: LCCOMB_X28_Y31_N2 +cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( +// Equation(s): +// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|attr_prefetch [0]), + .cin(gnd), + .combout(\ula_|video_|attr[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y31_N3 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [0]), + .d(\ula_|video_|attr[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -62835,24 +66542,24 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y28_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y28_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -62871,7 +66578,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X30_Y30_N9 +// Location: FF_X29_Y31_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -62890,47 +66597,47 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N8 +// Location: LCCOMB_X29_Y31_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[2]~0_combout ), + .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N26 +// Location: LCCOMB_X29_Y31_N6 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) .dataa(\ula_|border [0]), - .datab(\ula_|video_|cindex[0]~3_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[0]~3_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y30_N12 +// Location: LCCOMB_X29_Y31_N0 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[0]~3_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|cindex[0]~3_combout ), - .datab(\ula_|video_|VGA_B[1]~0_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|cindex[0]~3_combout ), .datac(gnd), .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), @@ -62941,24 +66648,7 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N12 -cycloneive_lcell_comb \ula_|video_|Equal0~2 ( -// Equation(s): -// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [6]), - .cin(gnd), - .combout(\ula_|video_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; -defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y29_N1 +// Location: FF_X30_Y31_N13 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -62977,16 +66667,33 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y29_N0 +// Location: LCCOMB_X30_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Equal0~2 ( +// Equation(s): +// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [8] & !\ula_|video_|vga_hc [9])) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h000A; +defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y31_N12 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~1_combout & ((\ula_|video_|Equal0~2_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~1_combout & (\ula_|video_|Equal1~0_combout & // (\ula_|video_|VGA_HS~_Duplicate_1_q ))) - .dataa(\ula_|video_|Equal0~2_combout ), + .dataa(\ula_|video_|Equal0~1_combout ), .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); @@ -63014,7 +66721,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y30_N1 +// Location: FF_X31_Y31_N29 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -63033,21 +66740,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y30_N0 +// Location: LCCOMB_X31_Y31_N28 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & -// !\ula_|video_|Equal3~1_combout )))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((!\ula_|video_|Equal3~1_combout & \ula_|video_|VGA_VS~_Duplicate_1_q )))) # (!\ula_|video_|Equal2~2_combout & (!\ula_|video_|Equal3~1_combout & +// (\ula_|video_|VGA_VS~_Duplicate_1_q ))) - .dataa(\ula_|video_|vga_vc [1]), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'hBA30; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63070,7 +66777,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N4 +// Location: LCCOMB_X36_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -63087,7 +66794,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X40_Y13_N5 +// Location: FF_X36_Y11_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -63106,7 +66813,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X40_Y13_N3 +// Location: FF_X36_Y11_N1 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -63125,7 +66832,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 +// Location: LCCOMB_X36_Y11_N0 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -63142,41 +66849,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N24 +// Location: LCCOMB_X52_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF33; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y19_N24 +// Location: LCCOMB_X23_Y18_N4 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~38_combout $ (\D[4]~39_combout )) - .dataa(\D[3]~109_combout ), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\D[4]~111_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~38_combout ), + .datac(gnd), + .datad(\D[4]~39_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hA55A; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y19_N25 +// Location: FF_X23_Y18_N5 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -63195,160 +66902,194 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N4 +// Location: LCCOMB_X29_Y8_N18 cycloneive_lcell_comb \sdram_|Mux26~4 ( // Equation(s): // \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\sdram_|r.address[3]~6_combout ), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.address[3]~6_combout ), .datad(\z80_|address_pins_|DFFE_apin_latch [9]), .cin(gnd), .combout(\sdram_|Mux26~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .lut_mask = 16'h0F05; defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N10 -cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( -// Equation(s): -// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|r.bank[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; -defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N8 -cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( -// Equation(s): -// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.bank[0]~7_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; -defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( -// Equation(s): -// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; -defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( -// Equation(s): -// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|r.bank[0]~4_combout ), - .cin(gnd), - .combout(\sdram_|r.bank[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; -defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N4 +// Location: LCCOMB_X19_Y13_N28 cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( // Equation(s): -// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # -// (\sdram_|r.bank[0]~5_combout ))))) +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.bank[0]~5_combout ), + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.bank[0]~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hA005; defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N28 -cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( // Equation(s): -// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) +// \sdram_|r.bank[0]~4_combout = (\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.bank[0]~8_combout ), + .combout(\sdram_|r.bank[0]~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; -defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hFC00; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N18 +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [6] & ((\sdram_|r.bank[0]~4_combout ) # ((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) # (!\sdram_|r.state [6] & (((\sdram_|r.rd_pending~q & \sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'hF888; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( // Equation(s): -// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) +// \sdram_|r.bank[0]~12_combout = ((!\sdram_|r.bank[0]~5_combout & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|r.bank[0]~6_combout ) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.bank[0]~11_combout ), - .datad(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.bank[0]~6_combout ), + .datac(\sdram_|r.bank[0]~5_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'h373F; defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N2 +// Location: LCCOMB_X19_Y13_N22 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [5]) # ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [5]), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hAFFF; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [7] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'h5A7A; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( // Equation(s): -// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [4]) # ((\sdram_|r.bank[0]~8_combout ) # ((\sdram_|r.state [5] & !\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.bank[0]~11_combout ), - .datac(\sdram_|r.bank[0]~6_combout ), - .datad(\sdram_|r.bank[0]~12_combout ), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~8_combout ), .cin(gnd), .combout(\sdram_|r.bank[0]~9_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'hFFF2; defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~9_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~7_combout ), + .datad(\sdram_|r.bank[0]~9_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'hB9A8; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~13 ( +// Equation(s): +// \sdram_|r.bank[0]~13_combout = ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [4]) # (\sdram_|r.state [7])))) # (!\sdram_|r.bank[0]~5_combout ) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.bank[0]~5_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~13 .lut_mask = 16'h7FFB; +defparam \sdram_|r.bank[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N26 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.state [8] & ((\sdram_|r.bank[0]~10_combout & ((!\sdram_|r.bank[0]~13_combout ))) # (!\sdram_|r.bank[0]~10_combout & (!\sdram_|r.bank[0]~12_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~10_combout +// )))) + + .dataa(\sdram_|r.bank[0]~12_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.bank[0]~10_combout ), + .datad(\sdram_|r.bank[0]~13_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'h07C7; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X11_Y0_N18 dffeas \sdram_|r.bank[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -63358,7 +67099,7 @@ dffeas \sdram_|r.bank[0] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [0]), @@ -63368,20 +67109,20 @@ defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; defparam \sdram_|r.bank[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y10_N2 +// Location: LCCOMB_X29_Y8_N26 cycloneive_lcell_comb \sdram_|Mux25~4 ( // Equation(s): // \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .dataa(\z80_|address_pins_|DFFE_apin_latch [10]), + .datab(\sdram_|r.address[3]~6_combout ), .datac(gnd), - .datad(\sdram_|r.address[3]~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\sdram_|Mux25~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .lut_mask = 16'h2233; defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -63394,7 +67135,7 @@ dffeas \sdram_|r.bank[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.bank[0]~9_combout ), + .ena(\sdram_|r.bank[0]~11_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.bank [1]), @@ -63404,146 +67145,146 @@ defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; defparam \sdram_|r.bank[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux71~6 ( // Equation(s): -// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) +// \sdram_|Mux71~6_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & ((\sdram_|r.state [6]) # (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [4] & \sdram_|r.state [6])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux24~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; -defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N24 -cycloneive_lcell_comb \sdram_|Mux71~0 ( -// Equation(s): -// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - - .dataa(gnd), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [5]), - .datad(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [7]), .cin(gnd), - .combout(\sdram_|Mux71~0_combout ), + .combout(\sdram_|Mux71~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; -defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux71~6 .lut_mask = 16'hF710; +defparam \sdram_|Mux71~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N4 -cycloneive_lcell_comb \sdram_|process_0~7 ( -// Equation(s): -// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\sdram_|r.act_row [4]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\sdram_|process_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; -defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y13_N28 -cycloneive_lcell_comb \sdram_|process_0~4 ( -// Equation(s): -// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|process_0~7_combout ), - .datac(\sdram_|Equal7~1_combout ), - .datad(\sdram_|Equal7~0_combout ), - .cin(gnd), - .combout(\sdram_|process_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; -defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux71~1 ( -// Equation(s): -// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [6]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux71~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; -defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N28 +// Location: LCCOMB_X20_Y15_N0 cycloneive_lcell_comb \sdram_|Mux71~2 ( // Equation(s): -// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) +// \sdram_|Mux71~2_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux71~1_combout ), - .datad(\sdram_|Mux71~0_combout ), + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), .cin(gnd), .combout(\sdram_|Mux71~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .lut_mask = 16'h000F; defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N14 +// Location: LCCOMB_X20_Y15_N16 cycloneive_lcell_comb \sdram_|Mux71~3 ( // Equation(s): -// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) +// \sdram_|Mux71~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [7])) # (!\sdram_|Mux71~2_combout ))) # (!\sdram_|r.state [8] & ((\sdram_|Mux71~2_combout ) # ((!\sdram_|Mux4~0_combout )))) - .dataa(\sdram_|process_0~4_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux71~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux71~2_combout ), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux71~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .lut_mask = 16'hEF67; defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N4 +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \sdram_|process_0~8 ( +// Equation(s): +// \sdram_|process_0~8_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\sdram_|process_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~8 .lut_mask = 16'h0FA5; +defparam \sdram_|process_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (((\sdram_|process_0~8_combout ) # (!\sdram_|Equal7~1_combout )) # (!\sdram_|Equal7~0_combout )) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~0_combout ), + .datac(\sdram_|process_0~8_combout ), + .datad(\sdram_|Equal7~1_combout ), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hF7FF; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 cycloneive_lcell_comb \sdram_|Mux71~4 ( // Equation(s): -// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) +// \sdram_|Mux71~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux71~6_combout & ((\sdram_|Mux71~3_combout ) # (\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux71~3_combout )))) - .dataa(\sdram_|Mux24~5_combout ), - .datab(\sdram_|Mux71~0_combout ), - .datac(\sdram_|Mux71~3_combout ), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|Mux71~6_combout ), + .datab(\sdram_|Mux71~3_combout ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux71~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .lut_mask = 16'hA8CC; defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux24~8 ( +// Equation(s): +// \sdram_|Mux24~8_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~8 .lut_mask = 16'h0307; +defparam \sdram_|Mux24~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux71~5 ( +// Equation(s): +// \sdram_|Mux71~5_combout = (\sdram_|Mux71~4_combout ) # ((\sdram_|Mux24~8_combout & ((\sdram_|r.state [7]) # (\sdram_|Mux71~2_combout )))) + + .dataa(\sdram_|Mux71~4_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~8_combout ), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~5 .lut_mask = 16'hFAEA; +defparam \sdram_|Mux71~5 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X14_Y0_N11 dffeas \sdram_|r.dq_masks[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63562,7 +67303,7 @@ defparam \sdram_|r.dq_masks[0] .power_up = "low"; // Location: DDIOOUTCELL_X14_Y0_N18 dffeas \sdram_|r.dq_masks[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux71~4_combout ), + .d(\sdram_|Mux71~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63578,248 +67319,248 @@ defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; defparam \sdram_|r.dq_masks[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N2 -cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \sdram_|n~6 ( // Equation(s): -// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) +// \sdram_|n~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - .dataa(gnd), - .datab(gnd), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.bank[0]~10_combout ), + .combout(\sdram_|n~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; -defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +defparam \sdram_|n~6 .lut_mask = 16'h5051; +defparam \sdram_|n~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N18 -cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Location: LCCOMB_X19_Y19_N12 +cycloneive_lcell_comb \sdram_|Mux9~0 ( // Equation(s): -// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) +// \sdram_|Mux9~0_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [7] & ((!\sdram_|r.state [4]))) # (!\sdram_|r.state [7] & ((\sdram_|n~6_combout ) # (\sdram_|r.state [4]))))) + + .dataa(\sdram_|n~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~0 .lut_mask = 16'h3E00; +defparam \sdram_|Mux9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N14 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|r.state [6] & (!\sdram_|n~2_combout & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (((\sdram_|n~6_combout )))) .dataa(\sdram_|n~2_combout ), .datab(\sdram_|r.state [6]), .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.bank[0]~10_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; -defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y12_N30 -cycloneive_lcell_comb \sdram_|n~5 ( -// Equation(s): -// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) - - .dataa(\sdram_|r.rd_pending~q ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|n~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|n~5 .lut_mask = 16'h3031; -defparam \sdram_|n~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N12 -cycloneive_lcell_comb \sdram_|Mux9~4 ( -// Equation(s): -// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) - - .dataa(\sdram_|Mux9~3_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux9~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N4 -cycloneive_lcell_comb \sdram_|Mux9~2 ( -// Equation(s): -// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux9~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; -defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N30 -cycloneive_lcell_comb \sdram_|Equal2~3 ( -// Equation(s): -// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [0]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [7]), - .cin(gnd), - .combout(\sdram_|Equal2~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; -defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N8 -cycloneive_lcell_comb \sdram_|Mux10~2 ( -// Equation(s): -// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) - - .dataa(gnd), - .datab(\sdram_|r.init_counter [6]), - .datac(\sdram_|r.init_counter [5]), - .datad(\sdram_|r.init_counter [4]), - .cin(gnd), - .combout(\sdram_|Mux10~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; -defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N26 -cycloneive_lcell_comb \sdram_|Mux10~3 ( -// Equation(s): -// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) - - .dataa(\sdram_|r.init_counter [2]), - .datab(\sdram_|r.init_counter [3]), - .datac(\sdram_|Mux10~2_combout ), - .datad(\sdram_|r.init_counter [1]), - .cin(gnd), - .combout(\sdram_|Mux10~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; -defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N4 -cycloneive_lcell_comb \sdram_|process_0~6 ( -// Equation(s): -// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) - - .dataa(\sdram_|r.init_counter [9]), - .datab(\sdram_|r.init_counter [8]), - .datac(\sdram_|process_0~5_combout ), - .datad(\sdram_|r.init_counter [10]), - .cin(gnd), - .combout(\sdram_|process_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|process_0~6 .lut_mask = 16'h0010; -defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y3_N24 -cycloneive_lcell_comb \sdram_|Mux10~4 ( -// Equation(s): -// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) - - .dataa(\sdram_|Mux10~3_combout ), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|process_0~6_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux10~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; -defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux9~5 ( -// Equation(s): -// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [7]), - .datad(\sdram_|n~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux9~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; -defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N20 -cycloneive_lcell_comb \sdram_|Mux7~0 ( -// Equation(s): -// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) - - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(gnd), - .datad(\sdram_|r.state [4]), - .cin(gnd), - .combout(\sdram_|Mux7~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; -defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N10 -cycloneive_lcell_comb \sdram_|Mux9~6 ( -// Equation(s): -// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|Mux10~4_combout ), - .datac(\sdram_|Mux9~5_combout ), - .datad(\sdram_|Mux7~0_combout ), + .datad(\sdram_|n~6_combout ), .cin(gnd), .combout(\sdram_|Mux9~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .lut_mask = 16'h7340; defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N24 +// Location: LCCOMB_X19_Y19_N0 cycloneive_lcell_comb \sdram_|Mux9~7 ( // Equation(s): -// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~6_combout & ((\sdram_|r.state [6]) # ((\sdram_|r.state [5]) # (\sdram_|r.state [7])))) # (!\sdram_|Mux9~6_combout & ((\sdram_|r.state [5] $ (\sdram_|r.state [7])))) - .dataa(\sdram_|Mux9~4_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|Mux9~2_combout ), - .datad(\sdram_|Mux9~6_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux9~6_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|Mux9~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .lut_mask = 16'hCFF8; defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y19_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h000F; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (!\sdram_|r.init_counter [0] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [7] & \sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|r.init_counter [0]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|Equal2~2_combout ), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h4000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (\sdram_|process_0~5_combout & (!\sdram_|r.init_counter [13] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [14]))) + + .dataa(\sdram_|process_0~5_combout ), + .datab(\sdram_|r.init_counter [13]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [14]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0002; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [6]), + .datab(gnd), + .datac(\sdram_|r.init_counter [7]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h0500; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \sdram_|Equal5~1 ( +// Equation(s): +// \sdram_|Equal5~1_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal5~0_combout & (\sdram_|r.init_counter [1] & \sdram_|process_0~6_combout ))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal5~0_combout ), + .datac(\sdram_|r.init_counter [1]), + .datad(\sdram_|process_0~6_combout ), + .cin(gnd), + .combout(\sdram_|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~1 .lut_mask = 16'h8000; +defparam \sdram_|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = (!\sdram_|r.init_counter [7] & (\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [2] & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [7]), + .datab(\sdram_|r.init_counter [1]), + .datac(\sdram_|r.init_counter [2]), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h4000; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (!\sdram_|Equal5~1_combout & (((!\sdram_|process_0~7_combout ) # (!\sdram_|process_0~6_combout )) # (!\sdram_|r.init_counter [3]))) + + .dataa(\sdram_|r.init_counter [3]), + .datab(\sdram_|process_0~6_combout ), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|process_0~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'h070F; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N6 +cycloneive_lcell_comb \sdram_|Mux9~1 ( +// Equation(s): +// \sdram_|Mux9~1_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~1 .lut_mask = 16'hFFD0; +defparam \sdram_|Mux9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N2 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|Mux9~1_combout ) # ((\sdram_|Mux7~0_combout & (!\sdram_|Equal2~3_combout & \sdram_|Mux10~2_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|Equal2~3_combout ), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux9~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'hFF20; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y19_N4 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|Mux9~0_combout ) # ((\sdram_|Mux9~7_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~2_combout ))) + + .dataa(\sdram_|Mux9~0_combout ), + .datab(\sdram_|Mux9~7_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux9~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hEFEE; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X0_Y11_N4 dffeas \sdram_|r.state[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux9~7_combout ), + .d(\sdram_|Mux9~3_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63835,112 +67576,163 @@ defparam \sdram_|r.state[2] .is_wysiwyg = "true"; defparam \sdram_|r.state[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux10~11 ( -// Equation(s): -// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) - - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|Mux10~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; -defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y7_N12 +// Location: LCCOMB_X19_Y17_N12 cycloneive_lcell_comb \sdram_|Mux10~6 ( // Equation(s): -// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) +// \sdram_|Mux10~6_combout = (\sdram_|r.state [4] & (((\sdram_|r.rd_pending~q & \sdram_|r.state [6])) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & (((\sdram_|r.state [6]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Mux10~11_combout ), - .datac(\sdram_|process_0~4_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .lut_mask = 16'hD5FA; defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N26 +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7]) # ((\sdram_|Mux10~2_combout & !\sdram_|Mux10~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h6676; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.state [8]) # ((\sdram_|r.state [4] & \sdram_|r.state [7])))) # (!\sdram_|r.rf_pending~q & (\sdram_|r.state [4])) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'hEEA2; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [4] & (\sdram_|r.state [7] & !\sdram_|r.state [8])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [8]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'h1120; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 cycloneive_lcell_comb \sdram_|Mux10~5 ( // Equation(s): -// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) +// \sdram_|Mux10~5_combout = (\sdram_|r.state [6] & ((\sdram_|Mux10~3_combout ) # ((!\sdram_|Mux10~4_combout )))) # (!\sdram_|r.state [6] & ((\sdram_|Mux10~4_combout & ((!\sdram_|n~4_combout ))) # (!\sdram_|Mux10~4_combout & (\sdram_|Mux10~3_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~3_combout ), + .datac(\sdram_|n~4_combout ), .datad(\sdram_|Mux10~4_combout ), .cin(gnd), .combout(\sdram_|Mux10~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .lut_mask = 16'h8DEE; defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N10 +// Location: LCCOMB_X19_Y17_N22 cycloneive_lcell_comb \sdram_|Mux10~7 ( // Equation(s): -// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & ((\sdram_|r.wr_pending~q ) # ((!\sdram_|r.rf_pending~q & \sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|r.rf_pending~q )) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.rf_pending~q ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux10~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .lut_mask = 16'hDACA; defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N20 +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~6_combout ) # ((!\sdram_|r.state [6] & !\sdram_|n~4_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|n~4_combout ), + .datac(\sdram_|Mux10~7_combout ), + .datad(\sdram_|Mux10~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hFFF1; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux10~12 ( +// Equation(s): +// \sdram_|Mux10~12_combout = (\sdram_|r.state [7] & (((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (\sdram_|r.state [6] & (\sdram_|process_0~3_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~12 .lut_mask = 16'hEC20; +defparam \sdram_|Mux10~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 cycloneive_lcell_comb \sdram_|Mux10~8 ( // Equation(s): -// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) +// \sdram_|Mux10~8_combout = (\sdram_|Mux10~10_combout ) # ((\sdram_|Mux10~12_combout ) # ((!\sdram_|r.state [7] & \sdram_|Mux10~5_combout ))) - .dataa(\sdram_|Mux10~7_combout ), + .dataa(\sdram_|Mux10~10_combout ), .datab(\sdram_|r.state [7]), .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~11_combout ), + .datad(\sdram_|Mux10~12_combout ), .cin(gnd), .combout(\sdram_|Mux10~8_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .lut_mask = 16'hFFBA; defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N22 -cycloneive_lcell_comb \sdram_|Mux10~9 ( -// Equation(s): -// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) - - .dataa(\sdram_|Mux10~6_combout ), - .datab(\sdram_|r.bank[0]~10_combout ), - .datac(\sdram_|Mux10~5_combout ), - .datad(\sdram_|Mux10~8_combout ), - .cin(gnd), - .combout(\sdram_|Mux10~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; -defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y11_N11 dffeas \sdram_|r.state[1] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux10~9_combout ), + .d(\sdram_|Mux10~8_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -63969,146 +67761,129 @@ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~ defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N8 -cycloneive_lcell_comb \sdram_|Mux11~2 ( -// Equation(s): -// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux11~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; -defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N6 -cycloneive_lcell_comb \sdram_|Mux11~3 ( -// Equation(s): -// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|Mux11~2_combout ), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux11~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; -defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N26 +// Location: LCCOMB_X18_Y17_N26 cycloneive_lcell_comb \sdram_|Mux11~4 ( // Equation(s): -// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) +// \sdram_|Mux11~4_combout = (\sdram_|r.state [5] & ((\sdram_|r.state [8] $ (\sdram_|r.state [4])) # (!\sdram_|r.state [7]))) # (!\sdram_|r.state [5] & (\sdram_|r.state [7])) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [5]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|Mux11~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux11~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .lut_mask = 16'h6EE6; defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N28 +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|r.state [6] & (((\sdram_|n~6_combout ) # (!\sdram_|r.state [8])) # (!\sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Mux7~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|n~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hCC4C; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (!\sdram_|Equal2~3_combout & (!\sdram_|r.state [8] & (!\sdram_|Equal5~1_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'h0001; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~2_combout ) # ((!\sdram_|Mux23~0_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|Mux11~2_combout ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 cycloneive_lcell_comb \sdram_|Mux11~5 ( // Equation(s): -// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) +// \sdram_|Mux11~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((\sdram_|r.state [8] & !\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [8]), .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [8]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux11~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .lut_mask = 16'h0C0E; defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y7_N0 +// Location: LCCOMB_X18_Y17_N10 cycloneive_lcell_comb \sdram_|Mux11~6 ( // Equation(s): -// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) +// \sdram_|Mux11~6_combout = (\sdram_|Mux11~5_combout & (!\sdram_|r.wr_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) - .dataa(\sdram_|r.rf_pending~q ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .dataa(\sdram_|Mux11~5_combout ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), .cin(gnd), .combout(\sdram_|Mux11~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .lut_mask = 16'h008A; defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N30 +// Location: LCCOMB_X18_Y17_N24 cycloneive_lcell_comb \sdram_|Mux11~7 ( // Equation(s): -// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) +// \sdram_|Mux11~7_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~8_combout ) # ((\sdram_|Mux11~3_combout ) # (\sdram_|Mux11~6_combout ))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.wr_pending~q ), - .datac(\sdram_|r.rd_pending~q ), + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~8_combout ), + .datac(\sdram_|Mux11~3_combout ), .datad(\sdram_|Mux11~6_combout ), .cin(gnd), .combout(\sdram_|Mux11~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .lut_mask = 16'hFFFE; defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N16 -cycloneive_lcell_comb \sdram_|Mux11~9 ( -// Equation(s): -// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|n~5_combout ), - .datad(\sdram_|Mux7~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; -defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N14 -cycloneive_lcell_comb \sdram_|Mux11~8 ( -// Equation(s): -// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) - - .dataa(\sdram_|Mux11~4_combout ), - .datab(\sdram_|Mux11~5_combout ), - .datac(\sdram_|Mux11~7_combout ), - .datad(\sdram_|Mux11~9_combout ), - .cin(gnd), - .combout(\sdram_|Mux11~8_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; -defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: DDIOOUTCELL_X0_Y27_N4 dffeas \sdram_|r.state[0] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux11~8_combout ), + .d(\sdram_|Mux11~7_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -64124,75 +67899,41 @@ defparam \sdram_|r.state[0] .is_wysiwyg = "true"; defparam \sdram_|r.state[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N20 -cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \sdram_|Mux24~5 ( // Equation(s): -// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) +// \sdram_|Mux24~5_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[11]~18_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q )))) - .dataa(\sdram_|r.wr_pending~q ), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Equal7~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux24~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; -defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N2 -cycloneive_lcell_comb \sdram_|r.address[0]~7 ( -// Equation(s): -// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .dataa(\sdram_|process_0~4_combout ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), + .datac(\z80_|address_pins_|abus[11]~18_combout ), + .datad(\sdram_|Mux23~0_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~7_combout ), + .combout(\sdram_|Mux24~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; -defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~5 .lut_mask = 16'hE400; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N12 -cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \sdram_|Mux24~6 ( // Equation(s): -// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) +// \sdram_|Mux24~6_combout = (\sdram_|Mux24~5_combout ) # ((!\sdram_|n~4_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.address[0]~_Duplicate_1_q ), - .datad(\sdram_|r.address[0]~7_combout ), + .dataa(\sdram_|n~4_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux24~5_combout ), .cin(gnd), - .combout(\sdram_|r.address[0]~0_combout ), + .combout(\sdram_|Mux24~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; -defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux24~6 .lut_mask = 16'hFF04; +defparam \sdram_|Mux24~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N30 -cycloneive_lcell_comb \sdram_|Mux13~9 ( -// Equation(s): -// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [8]), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [6]), - .cin(gnd), - .combout(\sdram_|Mux13~9_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; -defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y7_N0 +// Location: LCCOMB_X21_Y16_N6 cycloneive_lcell_comb \sdram_|Mux13~4 ( // Equation(s): // \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) @@ -64209,28 +67950,45 @@ defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y7_N2 +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 cycloneive_lcell_comb \sdram_|Mux13~5 ( // Equation(s): -// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux13~9_combout ))) - .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux13~9_combout ), - .datad(\sdram_|Mux13~4_combout ), + .dataa(\sdram_|Mux13~4_combout ), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux13~9_combout ), .cin(gnd), .combout(\sdram_|Mux13~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .lut_mask = 16'hAFA0; defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N13 +// Location: FF_X20_Y14_N21 dffeas \sdram_|r.address[0]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[0]~0_combout ), - .asdata(\sdram_|Mux24~4_combout ), + .asdata(\sdram_|Mux24~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64245,54 +68003,88 @@ defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N4 +// Location: LCCOMB_X19_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & (\z80_|address_pins_|abus[11]~18_combout )) # (!\sdram_|process_0~4_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\z80_|address_pins_|abus[11]~18_combout ), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hD800; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 cycloneive_lcell_comb \sdram_|Mux24~3 ( // Equation(s): -// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) +// \sdram_|Mux24~3_combout = (\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q ) - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux24~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .lut_mask = 16'hFF55; defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N14 +// Location: LCCOMB_X21_Y14_N6 cycloneive_lcell_comb \sdram_|Mux24~4 ( // Equation(s): -// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) +// \sdram_|Mux24~4_combout = (\sdram_|r.address[0]~_Duplicate_1_q & (((!\sdram_|r.rd_pending~q & \sdram_|Mux24~3_combout )) # (!\sdram_|Equal7~2_combout ))) - .dataa(\sdram_|n~3_combout ), + .dataa(\sdram_|r.rd_pending~q ), .datab(\sdram_|r.address[0]~_Duplicate_1_q ), - .datac(\sdram_|Mux24~3_combout ), - .datad(\sdram_|r.state [6]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux24~3_combout ), .cin(gnd), .combout(\sdram_|Mux24~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .lut_mask = 16'h4C0C; defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N24 +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & ((\sdram_|Mux24~4_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux24~2_combout )) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux24~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'hEE22; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux24~6_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[0]~0_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux24~4_combout ), - .datad(\sdram_|r.address[0]~0_combout ), + .datab(\sdram_|r.address[0]~0_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux24~6_combout ), .cin(gnd), .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64315,114 +68107,148 @@ defparam \sdram_|r.address[0] .is_wysiwyg = "true"; defparam \sdram_|r.address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N16 +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [4] & (\sdram_|process_0~4_combout & ((\sdram_|Equal7~2_combout ) # (\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'h8880; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~8 ( +// Equation(s): +// \sdram_|r.address[1]~8_combout = (\sdram_|r.state [4]) # ((\sdram_|r.state [6]) # (!\sdram_|n~4_combout )) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~8 .lut_mask = 16'hEEFF; +defparam \sdram_|r.address[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[1]~9 ( +// Equation(s): +// \sdram_|r.address[1]~9_combout = (\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~9 .lut_mask = 16'hDD00; +defparam \sdram_|r.address[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \sdram_|r.address[1]~7 ( +// Equation(s): +// \sdram_|r.address[1]~7_combout = (\sdram_|r.address[1]~_Duplicate_1_q & (((\sdram_|r.state [8]) # (!\sdram_|r.state [6])) # (!\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~7 .lut_mask = 16'hF070; +defparam \sdram_|r.address[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|r.address[1]~10 ( +// Equation(s): +// \sdram_|r.address[1]~10_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~9_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[1]~7_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[1]~9_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~10 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~8_combout & (\sdram_|r.address[1]~10_combout ))) # (!\sdram_|Mux23~1_combout & (\sdram_|r.address[1]~7_combout & ((\sdram_|r.address[1]~8_combout ) # +// (!\sdram_|r.address[1]~10_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|r.address[1]~8_combout ), + .datac(\sdram_|r.address[1]~10_combout ), + .datad(\sdram_|r.address[1]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hC580; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( // Equation(s): // \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout - .dataa(\sdram_|r.address[1]~1_combout ), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hFF00; defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N20 -cycloneive_lcell_comb \sdram_|Mux23~4 ( -// Equation(s): -// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & -// (\sdram_|r.address[1]~_Duplicate_1_q )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\z80_|address_pins_|abus[12]~24_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~4_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; -defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N16 -cycloneive_lcell_comb \sdram_|Equal5~0 ( -// Equation(s): -// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Equal5~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; -defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N14 -cycloneive_lcell_comb \sdram_|Mux23~5 ( -// Equation(s): -// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux23~4_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Equal5~0_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; -defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N8 -cycloneive_lcell_comb \sdram_|Mux23~6 ( -// Equation(s): -// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|Mux23~5_combout ), - .datad(\sdram_|Mux24~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~6_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; -defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N2 +// Location: LCCOMB_X21_Y16_N30 cycloneive_lcell_comb \sdram_|Mux19~0 ( // Equation(s): // \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [5]), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .lut_mask = 16'h9299; defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y12_N17 +// Location: FF_X25_Y16_N25 dffeas \sdram_|r.address[1]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), - .asdata(\sdram_|Mux23~6_combout ), + .asdata(\sdram_|Mux23~5_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64437,88 +68263,89 @@ defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N28 -cycloneive_lcell_comb \sdram_|Mux23~2 ( -// Equation(s): -// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|Mux23~2_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; -defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y12_N30 +// Location: LCCOMB_X20_Y17_N2 cycloneive_lcell_comb \sdram_|Mux23~3 ( // Equation(s): -// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) +// \sdram_|Mux23~3_combout = (\sdram_|r.state [8] & (((\sdram_|r.address[1]~_Duplicate_1_q )))) # (!\sdram_|r.state [8] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[12]~21_combout ))) # (!\sdram_|process_0~4_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) - .dataa(\sdram_|r.state [6]), - .datab(gnd), - .datac(\sdram_|Equal7~2_combout ), - .datad(\sdram_|Mux23~2_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[1]~_Duplicate_1_q ), + .datad(\z80_|address_pins_|abus[12]~21_combout ), .cin(gnd), .combout(\sdram_|Mux23~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .lut_mask = 16'hF4B0; defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N18 -cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Location: LCCOMB_X20_Y17_N8 +cycloneive_lcell_comb \sdram_|Mux23~4 ( // Equation(s): -// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (((\sdram_|Mux23~3_combout )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((\sdram_|Mux23~3_combout ))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )))) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|Mux23~3_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hCCCA; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = ((!\sdram_|r.rd_pending~q & ((\sdram_|r.state [6]) # (!\sdram_|r.wr_pending~q )))) # (!\sdram_|Equal7~2_combout ) .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), - .combout(\sdram_|Mux23~1_combout ), + .combout(\sdram_|Mux23~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; -defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~2 .lut_mask = 16'h33BF; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N22 -cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( // Equation(s): -// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) +// \sdram_|Mux23~5_combout = (\sdram_|Mux23~4_combout & (((\sdram_|Mux23~2_combout ) # (\sdram_|r.state [4])) # (!\sdram_|r.state [8]))) - .dataa(gnd), - .datab(\sdram_|r.address[1]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~3_combout ), - .datad(\sdram_|Mux23~1_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|Mux23~2_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), - .combout(\sdram_|r.address[1]~1_combout ), + .combout(\sdram_|Mux23~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; -defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +defparam \sdram_|Mux23~5 .lut_mask = 16'hCCC4; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N2 +// Location: LCCOMB_X21_Y16_N4 cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( // Equation(s): -// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|r.address[1]~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux23~5_combout )) - .dataa(\sdram_|r.address[1]~1_combout ), - .datab(\sdram_|Mux23~6_combout ), + .dataa(gnd), + .datab(\sdram_|Mux23~5_combout ), .datac(\sdram_|r.state [7]), - .datad(gnd), + .datad(\sdram_|r.address[1]~1_combout ), .cin(gnd), .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hFC0C; defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -64541,211 +68368,211 @@ defparam \sdram_|r.address[1] .is_wysiwyg = "true"; defparam \sdram_|r.address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N10 -cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( // Equation(s): -// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|r.state [5]), - .datac(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[3]~8_combout ), + .combout(\sdram_|r.address[3]~11_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; -defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h5F5C; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N24 -cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( // Equation(s): -// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) +// \sdram_|r.address[3]~12_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) .dataa(gnd), - .datab(\sdram_|r.state [5]), - .datac(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|r.address[3]~9_combout ), + .combout(\sdram_|r.address[3]~12_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; -defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hF000; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y12_N26 +// Location: LCCOMB_X23_Y14_N28 cycloneive_lcell_comb \sdram_|Mux21~0 ( // Equation(s): -// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~11_combout & ((\sdram_|r.address[3]~12_combout ) # ((\sdram_|r.state [4] & \sdram_|r.address[3]~6_combout )))) - .dataa(\sdram_|r.address[3]~6_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.address[3]~9_combout ), - .datad(\sdram_|r.address[3]~8_combout ), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.address[3]~12_combout ), .cin(gnd), .combout(\sdram_|Mux21~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .lut_mask = 16'h5540; defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N18 +// Location: LCCOMB_X24_Y8_N12 cycloneive_lcell_comb \sdram_|Mux22~0 ( // Equation(s): -// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[1]~27_combout ) # ((\z80_|address_pins_|abus[13]~20_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[13]~20_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[1]~25_combout ), - .datac(\z80_|address_pins_|abus[13]~23_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[1]~27_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux22~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .lut_mask = 16'hECA0; defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N20 -cycloneive_lcell_comb \sdram_|r.address[3]~10 ( -// Equation(s): -// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) - - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), - .cin(gnd), - .combout(\sdram_|r.address[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; -defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N14 -cycloneive_lcell_comb \sdram_|r.address[3]~11 ( -// Equation(s): -// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [7]), - .cin(gnd), - .combout(\sdram_|r.address[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; -defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N0 -cycloneive_lcell_comb \sdram_|r.address[3]~12 ( -// Equation(s): -// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~11_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.state [8]), - .cin(gnd), - .combout(\sdram_|r.address[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; -defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N6 -cycloneive_lcell_comb \sdram_|r.address[3]~13 ( -// Equation(s): -// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.address[3]~10_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.address[3]~12_combout ), - .cin(gnd), - .combout(\sdram_|r.address[3]~13_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; -defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y8_N16 +// Location: LCCOMB_X18_Y17_N12 cycloneive_lcell_comb \sdram_|r.address[3]~14 ( // Equation(s): -// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|r.state [4]), - .datab(\sdram_|r.state [7]), + .dataa(gnd), + .datab(\sdram_|r.state [4]), .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), .cin(gnd), .combout(\sdram_|r.address[3]~14_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h33CF; defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N22 +// Location: LCCOMB_X18_Y17_N30 cycloneive_lcell_comb \sdram_|r.address[3]~15 ( // Equation(s): -// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [8] & ((\sdram_|r.state [4]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4]))) - .dataa(\sdram_|Equal7~2_combout ), - .datab(\sdram_|r.address[3]~14_combout ), - .datac(\sdram_|r.state [5]), - .datad(\sdram_|r.state [7]), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.address[3]~14_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~15_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hFF9B; defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N24 +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (((!\sdram_|r.wr_pending~q & !\sdram_|r.rd_pending~q )) # (!\sdram_|r.state [4])) # (!\sdram_|r.state [7]) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'h37FF; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 cycloneive_lcell_comb \sdram_|r.address[3]~16 ( // Equation(s): -// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~15_combout )))) - .dataa(\sdram_|n~3_combout ), - .datab(\sdram_|r.bank[0]~8_combout ), + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [5]), .datac(\sdram_|r.address[3]~15_combout ), - .datad(\sdram_|r.state [8]), + .datad(\sdram_|r.address[3]~13_combout ), .cin(gnd), .combout(\sdram_|r.address[3]~16_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .lut_mask = 16'hFC74; defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y8_N26 +// Location: LCCOMB_X19_Y13_N24 cycloneive_lcell_comb \sdram_|r.address[3]~17 ( // Equation(s): -// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & (!\sdram_|r.wr_pending~q & \sdram_|r.state [4]))) - .dataa(\sdram_|r.address[3]~13_combout ), - .datab(gnd), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.address[3]~16_combout ), + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|r.address[3]~17_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .lut_mask = 16'hAB02; defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; // synopsys translate_on +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~18 ( +// Equation(s): +// \sdram_|r.address[3]~18_combout = (\sdram_|r.address[3]~17_combout ) # ((\sdram_|r.state [7] & ((!\sdram_|Equal7~2_combout ) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (\sdram_|r.state [5]))) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[3]~17_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~18 .lut_mask = 16'hDEFE; +defparam \sdram_|r.address[3]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~19 ( +// Equation(s): +// \sdram_|r.address[3]~19_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout ) # (!\sdram_|n~4_combout )))) # (!\sdram_|r.state [8] & (\sdram_|r.address[3]~18_combout )) + + .dataa(\sdram_|r.address[3]~18_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~4_combout ), + .datad(\sdram_|r.bank[0]~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~19 .lut_mask = 16'h2EEE; +defparam \sdram_|r.address[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \sdram_|r.address[3]~20 ( +// Equation(s): +// \sdram_|r.address[3]~20_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~16_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~19_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[3]~16_combout ), + .datad(\sdram_|r.address[3]~19_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~20 .lut_mask = 16'h0A5F; +defparam \sdram_|r.address[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: DDIOOUTCELL_X5_Y0_N4 dffeas \sdram_|r.address[2] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), @@ -64755,7 +68582,7 @@ dffeas \sdram_|r.address[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [2]), @@ -64765,21 +68592,21 @@ defparam \sdram_|r.address[2] .is_wysiwyg = "true"; defparam \sdram_|r.address[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N2 +// Location: LCCOMB_X24_Y8_N4 cycloneive_lcell_comb \sdram_|Mux21~1 ( // Equation(s): -// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & -// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|abus[2]~28_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~11_combout & +// (\z80_|address_pins_|abus[14]~22_combout & ((\sdram_|Mux21~0_combout )))) - .dataa(\sdram_|r.address[3]~8_combout ), - .datab(\z80_|address_pins_|abus[2]~26_combout ), - .datac(\z80_|address_pins_|abus[14]~22_combout ), + .dataa(\sdram_|r.address[3]~11_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[2]~28_combout ), .datad(\sdram_|Mux21~0_combout ), .cin(gnd), .combout(\sdram_|Mux21~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .lut_mask = 16'hECA0; defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -64792,7 +68619,7 @@ dffeas \sdram_|r.address[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [3]), @@ -64802,130 +68629,114 @@ defparam \sdram_|r.address[3] .is_wysiwyg = "true"; defparam \sdram_|r.address[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N22 +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \sdram_|Mux24~7 ( +// Equation(s): +// \sdram_|Mux24~7_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~7 .lut_mask = 16'hA0A8; +defparam \sdram_|Mux24~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 cycloneive_lcell_comb \sdram_|Mux20~4 ( // Equation(s): -// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) +// \sdram_|Mux20~4_combout = (\sdram_|Mux24~7_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~29_combout )))) # (!\sdram_|Mux24~7_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(gnd), - .datad(\sdram_|r.init_counter [0]), + .dataa(\z80_|address_pins_|abus[3]~29_combout ), + .datab(\sdram_|Mux24~7_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), .cin(gnd), .combout(\sdram_|Mux20~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .lut_mask = 16'hFB08; defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y13_N26 -cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \sdram_|Mux20~2 ( // Equation(s): -// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) - - .dataa(\sdram_|r.state [6]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\sdram_|Mux20~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; -defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X19_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux23~7 ( -// Equation(s): -// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) - - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux23~7_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; -defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N10 -cycloneive_lcell_comb \sdram_|Mux20~8 ( -// Equation(s): -// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) +// \sdram_|Mux20~2_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~4_combout & ((\z80_|address_pins_|abus[15]~23_combout ))) # (!\sdram_|process_0~4_combout & (\sdram_|r.address[4]~_Duplicate_1_q )))) .dataa(\sdram_|r.state [4]), - .datab(\sdram_|n~3_combout ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|r.state [8]), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[15]~23_combout ), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|Mux20~8_combout ), + .combout(\sdram_|Mux20~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; -defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~2 .lut_mask = 16'hA088; +defparam \sdram_|Mux20~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N18 -cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \sdram_|Mux20~3 ( // Equation(s): -// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|Mux20~3_combout = (\sdram_|Mux20~2_combout ) # ((!\sdram_|r.state [4] & \sdram_|Equal5~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(\sdram_|r.state [4]), + .datab(gnd), + .datac(\sdram_|Equal5~1_combout ), + .datad(\sdram_|Mux20~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~10_combout ), + .combout(\sdram_|Mux20~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; -defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~3 .lut_mask = 16'hFF50; +defparam \sdram_|Mux20~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N0 -cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( // Equation(s): -// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux20~3_combout ))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~7_combout ), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|Mux20~8_combout ), + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux20~4_combout ), + .datad(\sdram_|Mux20~3_combout ), .cin(gnd), - .combout(\sdram_|Mux20~9_combout ), + .combout(\sdram_|r.address[4]~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; -defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N24 -cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \sdram_|r.address[4]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) +// \sdram_|r.address[4]~_Duplicate_1feeder_combout = \sdram_|r.address[4]~2_combout - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|Mux20~10_combout ), - .datad(\sdram_|Mux20~9_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), - .combout(\sdram_|Mux20~11_combout ), + .combout(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; -defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[4]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N5 +// Location: FF_X21_Y13_N17 dffeas \sdram_|r.address[4]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[4]~2_combout ), - .asdata(\sdram_|Mux20~11_combout ), + .d(\sdram_|r.address[4]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux20~9_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -64940,89 +68751,122 @@ defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N2 -cycloneive_lcell_comb \sdram_|Mux20~12 ( -// Equation(s): -// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) - - .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux20~12_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; -defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y7_N4 +// Location: LCCOMB_X21_Y13_N20 cycloneive_lcell_comb \sdram_|Mux20~5 ( // Equation(s): -// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) +// \sdram_|Mux20~5_combout = ((\sdram_|r.state [6] & ((\z80_|address_pins_|DFFE_apin_latch [15]))) # (!\sdram_|r.state [6] & (\z80_|address_pins_|DFFE_apin_latch [3]))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\sdram_|Mux20~4_combout ), - .datab(\sdram_|Equal2~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|Mux20~12_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux20~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .lut_mask = 16'hCFAF; defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N16 +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (((\sdram_|Mux20~5_combout )))) # (!\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [3]) # ((!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(\sdram_|r.state [8]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|Mux20~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'hEF23; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 cycloneive_lcell_comb \sdram_|Mux20~6 ( // Equation(s): -// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[4]~_Duplicate_1_q )))) +// \sdram_|Mux20~6_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\z80_|address_pins_|abus[3]~27_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .dataa(gnd), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), .cin(gnd), .combout(\sdram_|Mux20~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .lut_mask = 16'hCCC0; defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Mux20~7 ( // Equation(s): -// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) +// \sdram_|Mux20~7_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|Mux20~6_combout & !\sdram_|r.state [8]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux20~5_combout ), - .datac(gnd), - .datad(\sdram_|Mux20~6_combout ), + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux20~6_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), - .combout(\sdram_|r.address[4]~2_combout ), + .combout(\sdram_|Mux20~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; -defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux20~7 .lut_mask = 16'h4498; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N8 -cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \sdram_|Mux20~8 ( // Equation(s): -// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) +// \sdram_|Mux20~8_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~1_combout & ((\sdram_|Mux20~10_combout ) # (!\sdram_|Mux20~7_combout )))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~7_combout )))) + + .dataa(\sdram_|Mux23~1_combout ), + .datab(\sdram_|Mux20~10_combout ), + .datac(\sdram_|Mux20~7_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h8AF0; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|Mux20~8_combout & ((\sdram_|Mux20~10_combout ))) # (!\sdram_|Mux20~8_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) .dataa(gnd), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[4]~2_combout ), - .datad(\sdram_|Mux20~11_combout ), + .datab(\sdram_|r.address[4]~_Duplicate_1_q ), + .datac(\sdram_|Mux20~8_combout ), + .datad(\sdram_|Mux20~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'hFC0C; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux20~9_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[4]~2_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux20~9_combout ), + .datad(\sdram_|r.address[4]~2_combout ), .cin(gnd), .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hF5A0; defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65045,66 +68889,32 @@ defparam \sdram_|r.address[4] .is_wysiwyg = "true"; defparam \sdram_|r.address[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N26 -cycloneive_lcell_comb \sdram_|Mux19~1 ( -// Equation(s): -// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) - - .dataa(\sdram_|r.init_counter [1]), - .datab(\sdram_|r.init_counter [7]), - .datac(\sdram_|Equal2~2_combout ), - .datad(\sdram_|r.init_counter [0]), - .cin(gnd), - .combout(\sdram_|Mux19~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; -defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N12 +// Location: LCCOMB_X21_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~4 ( // Equation(s): -// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~6_combout )) - .dataa(\sdram_|r.state [8]), + .dataa(\sdram_|Mux20~6_combout ), .datab(gnd), - .datac(\sdram_|Mux23~7_combout ), - .datad(\sdram_|r.bank[0]~4_combout ), + .datac(\sdram_|Mux23~1_combout ), + .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux19~4_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .lut_mask = 16'hF0AA; defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux19~5 ( -// Equation(s): -// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) - - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux19~5_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; -defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X21_Y11_N20 +// Location: LCCOMB_X20_Y14_N12 cycloneive_lcell_comb \sdram_|Mux19~6 ( // Equation(s): -// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) +// \sdram_|Mux19~6_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & (\sdram_|Mux19~4_combout & \sdram_|r.state [4]))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|r.state [4]), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|Mux19~4_combout ), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), .cin(gnd), .combout(\sdram_|Mux19~6_combout ), .cout()); @@ -65113,25 +68923,42 @@ defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N14 +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux19~4_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h6250; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 cycloneive_lcell_comb \sdram_|Mux19~7 ( // Equation(s): -// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~6_combout & (\sdram_|r.address[5]~_Duplicate_1_q & (\sdram_|Mux19~5_combout ))) # (!\sdram_|Mux19~6_combout & ((\sdram_|Mux19~5_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # +// (!\sdram_|Mux19~5_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) - .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .dataa(\sdram_|Mux19~6_combout ), .datab(\sdram_|r.address[5]~_Duplicate_1_q ), .datac(\sdram_|Mux19~5_combout ), - .datad(\sdram_|Mux19~6_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~7_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .lut_mask = 16'hD484; defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X21_Y11_N31 +// Location: FF_X20_Y14_N11 dffeas \sdram_|r.address[5]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\sdram_|r.address[5]~3_combout ), @@ -65150,72 +68977,89 @@ defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X21_Y7_N20 +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~4_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Equal5~1_combout )) + + .dataa(\sdram_|Equal5~1_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.address[5]~_Duplicate_1_q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h30AA; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 cycloneive_lcell_comb \sdram_|Mux19~2 ( // Equation(s): -// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) +// \sdram_|Mux19~2_combout = (!\sdram_|r.state [4] & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) - .dataa(\sdram_|Mux19~1_combout ), - .datab(\sdram_|process_0~2_combout ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [6]), .cin(gnd), .combout(\sdram_|Mux19~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .lut_mask = 16'h2232; defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N6 +// Location: LCCOMB_X20_Y14_N16 cycloneive_lcell_comb \sdram_|Mux19~3 ( // Equation(s): -// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & -// (((\sdram_|r.address[5]~_Duplicate_1_q )))) +// \sdram_|Mux19~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|Mux19~2_combout & ((\z80_|address_pins_|abus[4]~30_combout ))) # (!\sdram_|Mux19~2_combout & (\sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|Equal7~2_combout & +// (\sdram_|r.address[5]~_Duplicate_1_q )) - .dataa(\sdram_|Mux24~2_combout ), - .datab(\sdram_|r.state [4]), - .datac(\z80_|address_pins_|abus[4]~28_combout ), - .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~2_combout ), + .datad(\z80_|address_pins_|abus[4]~30_combout ), .cin(gnd), .combout(\sdram_|Mux19~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .lut_mask = 16'hEC4C; defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N30 +// Location: LCCOMB_X20_Y14_N10 cycloneive_lcell_comb \sdram_|r.address[5]~3 ( // Equation(s): -// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~1_combout )) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux19~2_combout ), + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|r.state [8]), .datac(gnd), .datad(\sdram_|Mux19~3_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~3_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X21_Y11_N26 +// Location: LCCOMB_X20_Y14_N6 cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) .dataa(\sdram_|r.address[5]~3_combout ), .datab(\sdram_|r.state [7]), - .datac(\sdram_|Mux19~7_combout ), - .datad(gnd), + .datac(gnd), + .datad(\sdram_|Mux19~7_combout ), .cin(gnd), .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hEE22; defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65238,15 +69082,15 @@ defparam \sdram_|r.address[5] .is_wysiwyg = "true"; defparam \sdram_|r.address[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N6 +// Location: LCCOMB_X24_Y8_N20 cycloneive_lcell_comb \sdram_|Mux18~0 ( // Equation(s): -// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux18~0_combout ), .cout()); @@ -65264,7 +69108,7 @@ dffeas \sdram_|r.address[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [6]), @@ -65274,33 +69118,33 @@ defparam \sdram_|r.address[6] .is_wysiwyg = "true"; defparam \sdram_|r.address[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N4 -cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Location: LCCOMB_X24_Y8_N24 +cycloneive_lcell_comb \sdram_|Mux17~2 ( // Equation(s): -// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux17~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [6]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux17~0_combout ), + .combout(\sdram_|Mux17~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux17~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X14_Y0_N4 dffeas \sdram_|r.address[7] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux17~0_combout ), + .d(\sdram_|Mux17~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [7]), @@ -65310,33 +69154,33 @@ defparam \sdram_|r.address[7] .is_wysiwyg = "true"; defparam \sdram_|r.address[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N22 -cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Location: LCCOMB_X24_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux16~2 ( // Equation(s): -// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux16~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), .datac(\z80_|address_pins_|DFFE_apin_latch [7]), - .datad(\sdram_|r.address[3]~8_combout ), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), - .combout(\sdram_|Mux16~0_combout ), + .combout(\sdram_|Mux16~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; -defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +defparam \sdram_|Mux16~2 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~2 .sum_lutc_input = "datac"; // synopsys translate_on // Location: DDIOOUTCELL_X0_Y5_N25 dffeas \sdram_|r.address[8] ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|Mux16~0_combout ), + .d(\sdram_|Mux16~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [8]), @@ -65346,20 +69190,20 @@ defparam \sdram_|r.address[8] .is_wysiwyg = "true"; defparam \sdram_|r.address[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X25_Y12_N30 +// Location: LCCOMB_X24_Y8_N8 cycloneive_lcell_comb \sdram_|Mux15~2 ( // Equation(s): -// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~11_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\sdram_|r.address[3]~8_combout ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [8]), + .datad(\sdram_|r.address[3]~11_combout ), .cin(gnd), .combout(\sdram_|Mux15~2_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .lut_mask = 16'hF500; defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -65372,7 +69216,7 @@ dffeas \sdram_|r.address[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\sdram_|r.address[3]~17_combout ), + .ena(\sdram_|r.address[3]~20_combout ), .devclrn(devclrn), .devpor(devpor), .q(\sdram_|r.address [9]), @@ -65382,61 +69226,78 @@ defparam \sdram_|r.address[9] .is_wysiwyg = "true"; defparam \sdram_|r.address[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N22 -cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \sdram_|r.address[10]~_Duplicate_1feeder ( // Equation(s): -// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) +// \sdram_|r.address[10]~_Duplicate_1feeder_combout = \sdram_|r.address[10]~4_combout - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~0_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; -defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N28 -cycloneive_lcell_comb \sdram_|Mux14~1 ( -// Equation(s): -// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - - .dataa(\sdram_|Equal2~3_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.state [4]), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~1_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; -defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N10 -cycloneive_lcell_comb \sdram_|r.address[10]~4 ( -// Equation(s): -// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) - - .dataa(\sdram_|Mux14~0_combout ), - .datab(\sdram_|r.state [8]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\sdram_|Mux14~1_combout ), + .datad(\sdram_|r.address[10]~4_combout ), .cin(gnd), - .combout(\sdram_|r.address[10]~4_combout ), + .combout(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; -defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.address[10]~_Duplicate_1feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X20_Y11_N11 +// Location: LCCOMB_X20_Y16_N2 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q ) # (\sdram_|r.address[10]~_Duplicate_1_q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.address[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h5F5C; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & !\sdram_|process_0~2_combout )))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h00AE; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((!\sdram_|process_0~4_combout & (\sdram_|r.address[10]~_Duplicate_1_q & \sdram_|Mux23~0_combout ))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux14~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y16_N25 dffeas \sdram_|r.address[10]~_Duplicate_1 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[10]~4_combout ), + .d(\sdram_|r.address[10]~_Duplicate_1feeder_combout ), .asdata(\sdram_|Mux14~3_combout ), .clrn(vcc), .aload(gnd), @@ -65452,71 +69313,71 @@ defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N16 -cycloneive_lcell_comb \sdram_|n~4 ( +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \sdram_|Mux14~1 ( // Equation(s): -// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~4_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) - .dataa(\sdram_|Equal7~2_combout ), + .dataa(\sdram_|Equal2~3_combout ), .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|r.rd_pending~q ), - .datad(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~4_combout ), .cin(gnd), - .combout(\sdram_|n~4_combout ), + .combout(\sdram_|Mux14~1_combout ), .cout()); // synopsys translate_off -defparam \sdram_|n~4 .lut_mask = 16'h5F5C; -defparam \sdram_|n~4 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N30 -cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \sdram_|Mux14~0 ( // Equation(s): -// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~5_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~2_combout )))) - .dataa(\sdram_|process_0~3_combout ), - .datab(\sdram_|r.rf_pending~q ), - .datac(\sdram_|r.state [6]), - .datad(\sdram_|n~4_combout ), + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|n~5_combout ), + .datac(\sdram_|process_0~2_combout ), + .datad(\sdram_|r.state [6]), .cin(gnd), - .combout(\sdram_|Mux14~2_combout ), + .combout(\sdram_|Mux14~0_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; -defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +defparam \sdram_|Mux14~0 .lut_mask = 16'hEEAE; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X20_Y11_N8 -cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( // Equation(s): -// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) - - .dataa(\sdram_|Mux14~2_combout ), - .datab(\sdram_|r.address[10]~_Duplicate_1_q ), - .datac(\sdram_|Mux23~0_combout ), - .datad(\sdram_|process_0~2_combout ), - .cin(gnd), - .combout(\sdram_|Mux14~3_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; -defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y11_N26 -cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( -// Equation(s): -// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & ((\sdram_|Mux14~0_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux14~1_combout )) .dataa(gnd), - .datab(\sdram_|r.state [7]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux14~1_combout ), + .datad(\sdram_|Mux14~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hFC30; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux14~3_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[10]~4_combout )) + + .dataa(\sdram_|r.state [7]), + .datab(\sdram_|r.address[10]~4_combout ), .datac(\sdram_|Mux14~3_combout ), - .datad(\sdram_|r.address[10]~4_combout ), + .datad(gnd), .cin(gnd), .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hE4E4; defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65539,61 +69400,61 @@ defparam \sdram_|r.address[10] .is_wysiwyg = "true"; defparam \sdram_|r.address[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N28 -cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~21 ( // Equation(s): -// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) +// \sdram_|r.address[11]~21_combout = (!\sdram_|r.rd_pending~q & (((\sdram_|r.state [6] & \sdram_|r.state [8])) # (!\sdram_|r.wr_pending~q ))) - .dataa(gnd), - .datab(\sdram_|r.rd_pending~q ), - .datac(\sdram_|r.state [4]), + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.rd_pending~q ), .datad(\sdram_|r.wr_pending~q ), .cin(gnd), - .combout(\sdram_|r.address[11]~18_combout ), + .combout(\sdram_|r.address[11]~21_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; -defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +defparam \sdram_|r.address[11]~21 .lut_mask = 16'h080F; +defparam \sdram_|r.address[11]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N26 +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \sdram_|r.address[11]~22 ( +// Equation(s): +// \sdram_|r.address[11]~22_combout = (\sdram_|r.address[11]~21_combout & ((\sdram_|r.state [8]) # (\sdram_|r.state [4]))) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[11]~21_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~22 .lut_mask = 16'hFC00; +defparam \sdram_|r.address[11]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 cycloneive_lcell_comb \sdram_|r.address[11]~5 ( // Equation(s): -// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.address[11]~22_combout ) # ((\sdram_|r.state [8] & !\sdram_|Equal7~2_combout )))) - .dataa(\sdram_|r.state [8]), - .datab(\sdram_|Mux24~2_combout ), + .dataa(\sdram_|r.address[11]~22_combout ), + .datab(\sdram_|r.state [8]), .datac(\sdram_|r.address[11]~_Duplicate_2_q ), - .datad(\sdram_|r.address[11]~18_combout ), + .datad(\sdram_|Equal7~2_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~5_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .lut_mask = 16'hA0E0; defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N4 -cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( -// Equation(s): -// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout - - .dataa(\sdram_|r.address[11]~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; -defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X19_Y11_N5 +// Location: FF_X20_Y14_N9 dffeas \sdram_|r.address[11]~_Duplicate_2 ( .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .d(\sdram_|r.address[11]~5_combout ), .asdata(\sdram_|Mux13~6_combout ), .clrn(vcc), .aload(gnd), @@ -65609,54 +69470,54 @@ defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N8 +// Location: LCCOMB_X20_Y14_N14 cycloneive_lcell_comb \sdram_|Mux13~10 ( // Equation(s): // \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) - .dataa(gnd), - .datab(\sdram_|r.address[11]~_Duplicate_2_q ), - .datac(\sdram_|r.state [6]), + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), .datad(\sdram_|r.state [8]), .cin(gnd), .combout(\sdram_|Mux13~10_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .lut_mask = 16'hF050; defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N22 +// Location: LCCOMB_X20_Y14_N0 cycloneive_lcell_comb \sdram_|Mux13~6 ( // Equation(s): -// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|Equal7~2_combout & !\sdram_|r.state [6])) # (!\sdram_|process_0~4_combout ))) - .dataa(\sdram_|r.state [6]), - .datab(\sdram_|Equal7~2_combout ), - .datac(\sdram_|Mux13~10_combout ), - .datad(\sdram_|process_0~2_combout ), + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|process_0~4_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux13~10_combout ), .cin(gnd), .combout(\sdram_|Mux13~6_combout ), .cout()); // synopsys translate_off -defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .lut_mask = 16'h3700; defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N12 +// Location: LCCOMB_X20_Y14_N4 cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65679,20 +69540,20 @@ defparam \sdram_|r.address[11] .is_wysiwyg = "true"; defparam \sdram_|r.address[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X19_Y11_N6 +// Location: LCCOMB_X20_Y14_N2 cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( // Equation(s): // \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) - .dataa(\sdram_|Mux13~6_combout ), - .datab(\sdram_|r.state [7]), - .datac(\sdram_|r.address[11]~5_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\sdram_|Mux13~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.address[11]~5_combout ), .cin(gnd), .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), .cout()); // synopsys translate_off -defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hCFC0; defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; // synopsys translate_on @@ -65725,6 +69586,16 @@ defparam \SW[0]~input .bus_hold = "false"; defparam \SW[0]~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X25_Y34_N8 +cycloneive_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + // Location: IOIBUF_X53_Y17_N15 cycloneive_io_ibuf \SW[3]~input ( .i(SW[3]), diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index bf15cbf..5605746 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/02/2022 14:51:22") + (DATE "04/06/2022 13:58:29") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (851:851:851) (986:986:986)) - (PORT oe (952:952:952) (1082:1082:1082)) + (PORT i (1343:1343:1343) (1508:1508:1508)) + (PORT oe (2775:2775:2775) (3149:3149:3149)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1146:1146:1146) (1288:1288:1288)) - (PORT oe (925:925:925) (1058:1058:1058)) + (PORT i (969:969:969) (1111:1111:1111)) + (PORT oe (2023:2023:2023) (2309:2309:2309)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1254:1254:1254) (1396:1396:1396)) - (PORT oe (925:925:925) (1058:1058:1058)) + (PORT i (728:728:728) (833:833:833)) + (PORT oe (2023:2023:2023) (2309:2309:2309)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1003:1003:1003) (1126:1126:1126)) - (PORT oe (1151:1151:1151) (1314:1314:1314)) + (PORT i (880:880:880) (988:988:988)) + (PORT oe (1920:1920:1920) (2197:2197:2197)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1052:1052:1052) (1196:1196:1196)) - (PORT oe (1151:1151:1151) (1314:1314:1314)) + (PORT i (907:907:907) (1033:1033:1033)) + (PORT oe (1920:1920:1920) (2197:2197:2197)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (867:867:867) (1013:1013:1013)) - (PORT oe (1288:1288:1288) (1473:1473:1473)) + (PORT i (741:741:741) (843:843:843)) + (PORT oe (1776:1776:1776) (2040:2040:2040)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (903:903:903) (1032:1032:1032)) - (PORT oe (1288:1288:1288) (1473:1473:1473)) + (PORT i (778:778:778) (904:904:904)) + (PORT oe (1776:1776:1776) (2040:2040:2040)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (915:915:915) (1053:1053:1053)) - (PORT oe (1288:1288:1288) (1473:1473:1473)) + (PORT i (796:796:796) (903:903:903)) + (PORT oe (1776:1776:1776) (2040:2040:2040)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (806:806:806) (927:927:927)) - (PORT oe (1431:1431:1431) (1637:1637:1637)) + (PORT i (639:639:639) (727:727:727)) + (PORT oe (1663:1663:1663) (1915:1915:1915)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (888:888:888) (1012:1012:1012)) - (PORT oe (1431:1431:1431) (1637:1637:1637)) + (PORT i (764:764:764) (862:862:862)) + (PORT oe (1663:1663:1663) (1915:1915:1915)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (969:969:969) (1122:1122:1122)) - (PORT oe (1283:1283:1283) (1469:1469:1469)) + (PORT i (801:801:801) (898:898:898)) + (PORT oe (1821:1821:1821) (2092:2092:2092)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) (IOPATH oe o (3164:3164:3164) (2848:2848:2848)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (845:845:845) (958:958:958)) - (PORT oe (1431:1431:1431) (1637:1637:1637)) + (PORT i (791:791:791) (885:885:885)) + (PORT oe (1663:1663:1663) (1915:1915:1915)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (907:907:907) (1029:1029:1029)) - (PORT oe (934:934:934) (1068:1068:1068)) + (PORT i (1233:1233:1233) (1392:1392:1392)) + (PORT oe (2043:2043:2043) (2334:2334:2334)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (913:913:913) (1049:1049:1049)) - (PORT oe (1283:1283:1283) (1469:1469:1469)) + (PORT i (877:877:877) (988:988:988)) + (PORT oe (1822:1822:1822) (2093:2093:2093)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (834:834:834) (953:953:953)) - (PORT oe (1202:1202:1202) (1384:1384:1384)) + (PORT i (612:612:612) (694:694:694)) + (PORT oe (1497:1497:1497) (1729:1729:1729)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (996:996:996) (1130:1130:1130)) - (PORT oe (1037:1037:1037) (1186:1186:1186)) + (PORT i (852:852:852) (956:956:956)) + (PORT oe (2017:2017:2017) (2303:2303:2303)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (665:665:665) (771:771:771)) - (PORT oe (779:779:779) (899:899:899)) + (PORT i (919:919:919) (1035:1035:1035)) + (PORT oe (1030:1030:1030) (1159:1159:1159)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (699:699:699) (800:800:800)) - (PORT oe (952:952:952) (1085:1085:1085)) + (PORT i (827:827:827) (944:944:944)) + (PORT oe (1507:1507:1507) (1696:1696:1696)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (821:821:821) (941:941:941)) - (PORT oe (924:924:924) (1056:1056:1056)) + (PORT i (777:777:777) (888:888:888)) + (PORT oe (1304:1304:1304) (1474:1474:1474)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (780:780:780) (878:878:878)) - (PORT oe (779:779:779) (899:899:899)) + (PORT i (666:666:666) (772:772:772)) + (PORT oe (1030:1030:1030) (1159:1159:1159)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (910:910:910) (1026:1026:1026)) - (PORT oe (793:793:793) (914:914:914)) + (PORT i (807:807:807) (921:921:921)) + (PORT oe (1141:1141:1141) (1283:1283:1283)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (817:817:817) (938:938:938)) - (PORT oe (955:955:955) (1093:1093:1093)) + (PORT i (873:873:873) (987:987:987)) + (PORT oe (1298:1298:1298) (1458:1458:1458)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (943:943:943) (1090:1090:1090)) - (PORT oe (908:908:908) (1044:1044:1044)) + (PORT i (788:788:788) (896:896:896)) + (PORT oe (1151:1151:1151) (1298:1298:1298)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (776:776:776) (890:890:890)) - (PORT oe (782:782:782) (897:897:897)) + (PORT i (929:929:929) (1048:1048:1048)) + (PORT oe (1326:1326:1326) (1494:1494:1494)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (887:887:887) (799:799:799)) - (PORT oe (839:839:839) (969:969:969)) + (PORT i (1211:1211:1211) (1071:1071:1071)) + (PORT oe (2084:2084:2084) (2371:2371:2371)) (IOPATH i o (1541:1541:1541) (1586:1586:1586)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (773:773:773) (700:700:700)) - (PORT oe (1037:1037:1037) (1186:1186:1186)) + (PORT i (983:983:983) (859:859:859)) + (PORT oe (2017:2017:2017) (2303:2303:2303)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (646:646:646) (707:707:707)) - (PORT oe (1025:1025:1025) (1173:1173:1173)) - (IOPATH i o (1666:1666:1666) (1600:1600:1600)) + (PORT i (1229:1229:1229) (1088:1088:1088)) + (PORT oe (2249:2249:2249) (2554:2554:2554)) + (IOPATH i o (1600:1600:1600) (1666:1666:1666)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (637:637:637) (702:702:702)) - (PORT oe (544:544:544) (628:628:628)) + (PORT i (1070:1070:1070) (1183:1183:1183)) + (PORT oe (2426:2426:2426) (2754:2754:2754)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -377,7 +377,17 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1023:1023:1023) (889:889:889)) + (PORT i (1083:1083:1083) (956:956:956)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1291:1291:1291) (1483:1483:1483)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -387,7 +397,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (642:642:642) (575:575:575)) + (PORT i (869:869:869) (1016:1016:1016)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -397,8 +407,48 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (860:860:860) (990:990:990)) - (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + (PORT i (931:931:931) (834:834:834)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (774:774:774) (700:700:700)) + (IOPATH i o (1600:1600:1600) (1666:1666:1666)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (776:776:776) (702:702:702)) + (IOPATH i o (2841:2841:2841) (3106:3106:3106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (778:778:778) (700:700:700)) + (IOPATH i o (1541:1541:1541) (1586:1586:1586)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (160:160:160) (180:180:180)) + (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) ) @@ -452,7 +502,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (623:623:623) (717:717:717)) + (PORT i (568:568:568) (629:629:629)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -462,7 +512,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (632:632:632) (726:726:726)) + (PORT i (546:546:546) (610:610:610)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -472,7 +522,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (480:480:480) (539:539:539)) + (PORT i (548:548:548) (600:600:600)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -482,7 +532,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (445:445:445) (499:499:499)) + (PORT i (291:291:291) (321:321:321)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -492,7 +542,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (313:313:313) (353:353:353)) + (PORT i (381:381:381) (421:421:421)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -502,7 +552,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (307:307:307) (345:345:345)) + (PORT i (382:382:382) (421:421:421)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -512,7 +562,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (706:706:706) (787:787:787)) + (PORT i (719:719:719) (804:804:804)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -522,7 +572,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (706:706:706) (787:787:787)) + (PORT i (719:719:719) (804:804:804)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -532,7 +582,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (618:618:618) (708:708:708)) + (PORT i (590:590:590) (668:668:668)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) ) ) @@ -542,7 +592,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (694:694:694) (759:759:759)) + (PORT i (561:561:561) (633:633:633)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -552,7 +602,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (638:638:638) (732:732:732)) + (PORT i (589:589:589) (664:664:664)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -562,7 +612,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (639:639:639) (733:733:733)) + (PORT i (595:595:595) (671:671:671)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -590,7 +640,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1044:1044:1044) (916:916:916)) + (PORT i (1131:1131:1131) (993:993:993)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -600,7 +650,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (696:696:696) (629:629:629)) + (PORT i (831:831:831) (755:755:755)) (IOPATH i o (2841:2841:2841) (3106:3106:3106)) ) ) @@ -610,7 +660,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (472:472:472) (516:516:516)) + (PORT i (154:154:154) (173:173:173)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -620,7 +670,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (917:917:917) (1047:1047:1047)) + (PORT i (865:865:865) (996:996:996)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -838,8 +888,8 @@ (INSTANCE DRAM_DQ\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (701:701:701) (808:808:808)) - (PORT oe (956:956:956) (1100:1100:1100)) + (PORT i (648:648:648) (738:738:738)) + (PORT oe (800:800:800) (908:908:908)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -850,8 +900,8 @@ (INSTANCE DRAM_DQ\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (766:766:766) (870:870:870)) - (PORT oe (956:956:956) (1100:1100:1100)) + (PORT i (814:814:814) (937:937:937)) + (PORT oe (800:800:800) (908:908:908)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -862,8 +912,8 @@ (INSTANCE DRAM_DQ\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (613:613:613) (699:699:699)) - (PORT oe (793:793:793) (885:885:885)) + (PORT i (748:748:748) (845:845:845)) + (PORT oe (784:784:784) (892:892:892)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -874,8 +924,8 @@ (INSTANCE DRAM_DQ\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (673:673:673) (774:774:774)) - (PORT oe (845:845:845) (968:968:968)) + (PORT i (829:829:829) (961:961:961)) + (PORT oe (938:938:938) (1093:1093:1093)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -886,8 +936,8 @@ (INSTANCE DRAM_DQ\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (662:662:662) (753:753:753)) - (PORT oe (669:669:669) (766:766:766)) + (PORT i (864:864:864) (987:987:987)) + (PORT oe (869:869:869) (994:994:994)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -898,8 +948,8 @@ (INSTANCE DRAM_DQ\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (811:811:811) (939:939:939)) - (PORT oe (732:732:732) (811:811:811)) + (PORT i (813:813:813) (944:944:944)) + (PORT oe (709:709:709) (814:814:814)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -910,8 +960,8 @@ (INSTANCE DRAM_DQ\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (646:646:646) (745:745:745)) - (PORT oe (732:732:732) (811:811:811)) + (PORT i (566:566:566) (659:659:659)) + (PORT oe (709:709:709) (814:814:814)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -922,8 +972,8 @@ (INSTANCE DRAM_DQ\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (303:303:303) (338:338:338)) - (PORT oe (759:759:759) (864:864:864)) + (PORT i (782:782:782) (896:896:896)) + (PORT oe (904:904:904) (1046:1046:1046)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -934,7 +984,7 @@ (INSTANCE DRAM_DQ\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1031:1031:1031) (902:902:902)) + (PORT i (1006:1006:1006) (874:874:874)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -944,7 +994,7 @@ (INSTANCE DRAM_DQ\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (900:900:900) (791:791:791)) + (PORT i (990:990:990) (860:860:860)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -954,7 +1004,7 @@ (INSTANCE DRAM_DQ\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (890:890:890) (782:782:782)) + (PORT i (998:998:998) (866:866:866)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -964,7 +1014,7 @@ (INSTANCE DRAM_DQ\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (890:890:890) (782:782:782)) + (PORT i (998:998:998) (866:866:866)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -974,7 +1024,7 @@ (INSTANCE DRAM_DQ\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1021:1021:1021) (899:899:899)) + (PORT i (987:987:987) (856:856:856)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -984,7 +1034,7 @@ (INSTANCE DRAM_DQ\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1022:1022:1022) (894:894:894)) + (PORT i (1010:1010:1010) (877:877:877)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -994,7 +1044,7 @@ (INSTANCE DRAM_DQ\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1022:1022:1022) (894:894:894)) + (PORT i (1010:1010:1010) (877:877:877)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -1004,7 +1054,7 @@ (INSTANCE DRAM_DQ\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (766:766:766) (669:669:669)) + (PORT i (994:994:994) (869:869:869)) (IOPATH i o (1600:1600:1600) (1666:1666:1666)) ) ) @@ -1036,6 +1086,887 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE turbo_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (705:705:705)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (91:91:91) (78:78:78)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (199:199:199)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (194:194:194)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (200:200:200)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (188:188:188)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (194:194:194)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (196:196:196)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (284:284:284)) + (PORT datac (314:314:314) (371:371:371)) + (PORT datad (210:210:210) (259:259:259)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (222:222:222) (279:279:279)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (129:129:129) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (202:202:202)) + (PORT datab (144:144:144) (197:197:197)) + (PORT datac (329:329:329) (388:388:388)) + (PORT datad (137:137:137) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (102:102:102) (122:122:122)) + (PORT datad (128:128:128) (169:169:169)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (410:410:410)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (2155:2155:2155) (2438:2438:2438)) + (PORT datad (365:365:365) (439:439:439)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (551:551:551) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (443:443:443)) + (PORT datab (221:221:221) (278:278:278)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (201:201:201)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (129:129:129) (175:175:175)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (369:369:369) (443:443:443)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (136:136:136) (175:175:175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (338:338:338) (394:394:394)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (337:337:337) (393:393:393)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2178:2178:2178) (2462:2462:2462)) + (PORT datad (321:321:321) (372:372:372)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1125:1125:1125) (1004:1004:1004)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE turbo\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE turbo) + (DELAY + (ABSOLUTE + (PORT clk (481:481:481) (433:433:433)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|counter\[0\]\~0) @@ -1050,7 +1981,7 @@ (INSTANCE ula_\|clocks_\|counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1126:1126:1126) (1157:1157:1157)) + (PORT clk (914:914:914) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1059,23 +1990,14 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE SW\[2\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (341:341:341) (316:316:316)) - (IOPATH datab combout (188:188:188) (193:193:193)) + (PORT datab (490:490:490) (585:585:585)) + (PORT datad (355:355:355) (426:426:426)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1086,7 +2008,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu) (DELAY (ABSOLUTE - (PORT clk (1126:1126:1126) (1157:1157:1157)) + (PORT clk (919:919:919) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1100,16 +2022,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (391:391:391) (423:423:423)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[1\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (705:705:705)) + (PORT inclk[0] (392:392:392) (424:424:424)) ) ) ) @@ -1127,8 +2040,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (979:979:979) (855:855:855)) - (PORT datad (283:283:283) (305:305:305)) + (PORT datac (981:981:981) (856:856:856)) + (PORT datad (284:284:284) (306:306:306)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1139,7 +2052,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (104:104:104) (121:121:121)) + (PORT datad (1006:1006:1006) (1161:1161:1161)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -1149,7 +2062,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (918:918:918) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1163,7 +2076,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (411:411:411) (447:447:447)) + (PORT inclk[0] (386:386:386) (418:418:418)) ) ) ) @@ -1172,9 +2085,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (924:924:924) (908:908:908)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (896:896:896)) + (PORT clrn (907:907:907) (894:894:894)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -1184,69 +2097,11 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[1\]\~input) (DELAY (ABSOLUTE - (PORT dataa (1093:1093:1093) (1296:1296:1296)) - (PORT datac (797:797:797) (942:942:942)) - (PORT datad (636:636:636) (763:763:763)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (915:915:915) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT datac (410:410:410) (494:494:494)) - (PORT datad (178:178:178) (236:236:236)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1233:1233:1233) (1373:1373:1373)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (780:780:780) (846:846:846)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1264:1264:1264) (1415:1415:1415)) + (IOPATH i o (153:153:153) (705:705:705)) ) ) ) @@ -1255,13 +2110,66 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (808:808:808) (953:953:953)) - (PORT datad (951:951:951) (1131:1131:1131)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (1063:1063:1063) (1276:1276:1276)) + (PORT datad (896:896:896) (1064:1064:1064)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (823:823:823)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (548:548:548) (644:644:644)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2741:2741:2741) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (665:665:665) (787:787:787)) + (PORT datad (550:550:550) (647:647:647)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -1276,7 +2184,7 @@ (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (445:445:445)) + (PORT dataa (362:362:362) (432:432:432)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1288,10 +2196,10 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (191:191:191) (233:233:233)) - (PORT datad (332:332:332) (389:389:389)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datac (402:402:402) (453:453:453)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -1300,7 +2208,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1314,7 +2222,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (295:295:295)) + (PORT datab (356:356:356) (428:428:428)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1328,7 +2236,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (168:168:168) (197:197:197)) + (PORT datad (441:441:441) (505:505:505)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -1338,7 +2246,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1352,7 +2260,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (217:217:217) (275:275:275)) + (PORT datab (369:369:369) (443:443:443)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1366,8 +2274,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (445:445:445) (482:482:482)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (901:901:901) (997:997:997)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1380,9 +2288,9 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (330:330:330) (400:400:400)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (350:350:350) (431:431:431)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -1394,13 +2302,29 @@ (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (450:450:450) (489:489:489)) + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (335:335:335)) + (PORT datab (804:804:804) (978:978:978)) + (PORT datac (897:897:897) (1042:1042:1042)) + (PORT datad (149:149:149) (191:191:191)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) ) ) (CELL @@ -1408,7 +2332,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (330:330:330) (404:404:404)) + (PORT dataa (219:219:219) (276:276:276)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1422,8 +2346,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (449:449:449) (486:486:486)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (268:268:268) (289:289:289)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1433,10 +2357,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT datab (431:431:431) (504:504:504)) + (PORT dataa (854:854:854) (977:977:977)) + (PORT datab (793:793:793) (936:936:936)) + (PORT datac (92:92:92) (113:113:113)) + (PORT datad (363:363:363) (433:433:433)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (457:457:457)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1445,126 +2385,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (132:132:132)) - (PORT datad (336:336:336) (394:394:394)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (270:270:270) (291:291:291)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT datab (746:746:746) (859:859:859)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (338:338:338) (363:363:363)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (416:416:416)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (781:781:781) (871:871:871)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (309:309:309)) - (PORT datab (521:521:521) (622:622:622)) - (PORT datac (381:381:381) (463:463:463)) - (PORT datad (397:397:397) (476:476:476)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (799:799:799)) - (PORT datab (486:486:486) (567:567:567)) - (PORT datac (353:353:353) (419:419:419)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (565:565:565) (661:661:661)) + (PORT dataa (219:219:219) (275:275:275)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1578,8 +2404,8 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datab (103:103:103) (131:131:131)) - (PORT datad (336:336:336) (394:394:394)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1590,8 +2416,8 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (444:444:444) (481:481:481)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (860:860:860) (980:980:980)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1604,8 +2430,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (144:144:144) (193:193:193)) - (IOPATH datab combout (196:196:196) (205:205:205)) + (PORT datad (360:360:360) (437:437:437)) + (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -1615,8 +2441,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (177:177:177) (218:218:218)) - (PORT datad (337:337:337) (395:395:395)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1627,8 +2453,8 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (764:764:764) (846:846:846)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (340:340:340) (366:366:366)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1641,35 +2467,23 @@ (INSTANCE ula_\|video_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (119:119:119) (151:151:151)) - (PORT datab (683:683:683) (799:799:799)) - (PORT datac (480:480:480) (572:572:572)) - (PORT datad (470:470:470) (548:548:548)) + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (869:869:869) (1011:1011:1011)) + (PORT datac (387:387:387) (467:467:467)) + (PORT datad (396:396:396) (464:464:464)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (688:688:688) (802:802:802)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (379:379:379) (456:456:456)) + (PORT datab (733:733:733) (842:842:842)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1680,39 +2494,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (415:415:415)) - (PORT datab (832:832:832) (954:954:954)) - (PORT datad (317:317:317) (366:366:366)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datab (342:342:342) (399:399:399)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (849:849:849) (953:953:953)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~4) + (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (365:365:365) (439:439:439)) + (PORT datab (382:382:382) (459:459:459)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1721,172 +2532,84 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (417:417:417)) - (PORT datab (339:339:339) (404:404:404)) - (PORT datad (813:813:813) (929:929:929)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[2\]) + (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (366:366:366) (402:402:402)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datab (376:376:376) (452:452:452)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (416:416:416)) - (PORT datab (832:832:832) (954:954:954)) - (PORT datad (318:318:318) (369:369:369)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[3\]) + (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (268:268:268) (288:288:288)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~8) + (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (506:506:506) (598:598:598)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (420:420:420) (506:506:506)) + (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (417:417:417)) - (PORT datab (351:351:351) (415:415:415)) - (PORT datad (813:813:813) (928:928:928)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (934:934:934) (1084:1084:1084)) + (PORT datab (337:337:337) (406:406:406)) + (PORT datac (397:397:397) (481:481:481)) + (PORT datad (394:394:394) (469:469:469)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (396:396:396) (481:481:481)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (324:324:324) (389:389:389)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (421:421:421)) - (PORT datab (836:836:836) (958:958:958)) - (PORT datad (314:314:314) (362:362:362)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (596:596:596)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (331:331:331) (396:396:396)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -1898,11 +2621,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (424:424:424)) - (PORT datab (303:303:303) (357:357:357)) - (PORT datad (415:415:415) (470:470:470)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (366:366:366) (450:450:450)) + (PORT datab (292:292:292) (339:339:339)) + (PORT datad (910:910:910) (1045:1045:1045)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1913,7 +2636,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1927,7 +2650,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (530:530:530) (630:630:630)) + (PORT datab (514:514:514) (598:598:598)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1941,9 +2664,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (423:423:423)) - (PORT datab (570:570:570) (653:653:653)) - (PORT datad (289:289:289) (333:333:333)) + (PORT dataa (358:358:358) (438:438:438)) + (PORT datab (411:411:411) (472:472:472)) + (PORT datad (903:903:903) (1037:1037:1037)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -1956,7 +2679,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -1970,9 +2693,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (505:505:505) (596:596:596)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (354:354:354) (422:422:422)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -1984,9 +2707,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (423:423:423)) - (PORT datab (603:603:603) (696:696:696)) - (PORT datad (289:289:289) (333:333:333)) + (PORT dataa (357:357:357) (437:437:437)) + (PORT datab (391:391:391) (452:452:452)) + (PORT datad (903:903:903) (1037:1037:1037)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -1999,7 +2722,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -2013,8 +2736,8 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (347:347:347) (419:419:419)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (420:420:420) (500:500:500)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -2024,11 +2747,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (426:426:426)) - (PORT datab (304:304:304) (358:358:358)) - (PORT datad (418:418:418) (477:477:477)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (357:357:357) (437:437:437)) + (PORT datab (276:276:276) (322:322:322)) + (PORT datad (902:902:902) (1036:1036:1036)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2039,7 +2762,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -2048,31 +2771,15 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (156:156:156) (213:213:213)) - (PORT datab (365:365:365) (440:440:440)) - (PORT datac (337:337:337) (404:404:404)) - (PORT datad (641:641:641) (743:743:743)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (277:277:277)) - (PORT datab (158:158:158) (207:207:207)) - (PORT datac (136:136:136) (182:182:182)) - (PORT datad (222:222:222) (270:270:270)) + (PORT dataa (149:149:149) (202:202:202)) + (PORT datab (160:160:160) (209:209:209)) + (PORT datac (148:148:148) (192:192:192)) + (PORT datad (135:135:135) (177:177:177)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -2085,10 +2792,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (275:275:275)) - (PORT datab (479:479:479) (550:550:550)) - (PORT datac (326:326:326) (387:387:387)) - (PORT datad (308:308:308) (347:347:347)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (516:516:516) (597:597:597)) + (PORT datac (311:311:311) (368:368:368)) + (PORT datad (297:297:297) (335:335:335)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -2101,11 +2808,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (417:417:417)) - (PORT datab (833:833:833) (955:955:955)) - (PORT datad (161:161:161) (188:188:188)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (359:359:359) (440:440:440)) + (PORT datab (280:280:280) (332:332:332)) + (PORT datad (904:904:904) (1039:1039:1039)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2116,7 +2823,209 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (416:416:416) (497:497:497)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (445:445:445)) + (PORT datab (279:279:279) (323:323:323)) + (PORT datad (907:907:907) (1042:1042:1042)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (410:410:410)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (732:732:732)) + (PORT datab (291:291:291) (340:340:340)) + (PORT datac (611:611:611) (698:698:698)) + (PORT datad (573:573:573) (648:648:648)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (443:443:443) (485:485:485)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1081:1081:1081)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (435:435:435)) + (PORT datab (296:296:296) (346:346:346)) + (PORT datad (902:902:902) (1035:1035:1035)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (512:512:512) (598:598:598)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (447:447:447)) + (PORT datab (280:280:280) (325:325:325)) + (PORT datad (908:908:908) (1043:1043:1043)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (450:450:450)) + (PORT datab (292:292:292) (341:341:341)) + (PORT datad (910:910:910) (1045:1045:1045)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -2130,10 +3039,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (274:274:274)) - (PORT datab (365:365:365) (441:441:441)) - (PORT datac (335:335:335) (402:402:402)) - (PORT datad (198:198:198) (250:250:250)) + (PORT dataa (420:420:420) (507:507:507)) + (PORT datab (342:342:342) (412:412:412)) + (PORT datac (393:393:393) (471:471:471)) + (PORT datad (916:916:916) (1054:1054:1054)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -2146,11 +3055,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (177:177:177) (220:220:220)) - (PORT datac (325:325:325) (386:386:386)) - (PORT datad (309:309:309) (349:349:349)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (322:322:322) (387:387:387)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datad (293:293:293) (330:330:330)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -2169,10 +3078,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (588:588:588)) - (PORT datab (508:508:508) (603:603:603)) - (PORT datac (495:495:495) (577:577:577)) - (PORT datad (816:816:816) (701:701:701)) + (PORT dataa (364:364:364) (439:439:439)) + (PORT datab (386:386:386) (468:468:468)) + (PORT datac (363:363:363) (428:428:428)) + (PORT datad (902:902:902) (785:785:785)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -2182,54 +3091,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (INSTANCE z80_\|ir_\|opcode\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (781:781:781) (898:898:898)) - (PORT datad (1070:1070:1070) (1244:1244:1244)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (131:131:131) (160:160:160)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (408:408:408) (505:505:505)) - (PORT datab (804:804:804) (961:961:961)) - (PORT datac (1061:1061:1061) (1240:1240:1240)) - (PORT datad (939:939:939) (1085:1085:1085)) + (PORT dataa (694:694:694) (821:821:821)) + (PORT datab (220:220:220) (275:275:275)) + (PORT datad (548:548:548) (645:645:645)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (990:990:990) (1153:1153:1153)) - (PORT datad (172:172:172) (204:204:204)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (213:213:213) (275:275:275)) - (PORT datab (388:388:388) (467:467:467)) - (PORT datad (492:492:492) (569:569:569)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (688:688:688) (813:813:813)) + (PORT datab (214:214:214) (272:272:272)) + (PORT datad (550:550:550) (647:647:647)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2240,9 +3150,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (900:900:900) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) + (PORT clrn (898:898:898) (885:885:885)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -2251,284 +3161,16 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (974:974:974)) - (PORT datad (520:520:520) (619:619:619)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1225:1225:1225)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (350:350:350) (408:408:408)) - (PORT datad (922:922:922) (1096:1096:1096)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1152:1152:1152)) - (PORT datab (940:940:940) (1122:1122:1122)) - (PORT datad (1048:1048:1048) (1199:1199:1199)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (1044:1044:1044)) - (PORT datab (143:143:143) (176:176:176)) - (PORT datac (806:806:806) (925:925:925)) - (PORT datad (662:662:662) (766:766:766)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (510:510:510)) - (PORT datab (411:411:411) (504:504:504)) - (PORT datac (1058:1058:1058) (1236:1236:1236)) - (PORT datad (935:935:935) (1080:1080:1080)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (774:774:774)) - (PORT datac (519:519:519) (602:602:602)) - (PORT datad (662:662:662) (767:767:767)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (410:410:410)) - (PORT datac (373:373:373) (445:445:445)) - (PORT datad (488:488:488) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (924:924:924)) - (PORT datab (1245:1245:1245) (1493:1493:1493)) - (PORT datac (203:203:203) (251:251:251)) - (PORT datad (175:175:175) (233:233:233)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (925:925:925) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (663:663:663) (764:764:764)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (901:901:901)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT dataa (139:139:139) (194:194:194)) - (PORT datad (661:661:661) (762:762:762)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (843:843:843) (990:990:990)) - (PORT datac (655:655:655) (765:765:765)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (764:764:764)) - (PORT datab (663:663:663) (753:753:753)) - (PORT datac (1275:1275:1275) (1482:1482:1482)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1486:1486:1486)) - (PORT datab (1233:1233:1233) (1453:1453:1453)) - (PORT datac (686:686:686) (799:799:799)) - (PORT datad (499:499:499) (573:573:573)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (906:906:906)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (890:890:890)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (120:120:120) (154:154:154)) - (PORT datac (556:556:556) (656:656:656)) - (PORT datad (837:837:837) (971:971:971)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (283:283:283)) - (PORT datab (386:386:386) (465:465:465)) - (PORT datad (494:494:494) (572:572:572)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (683:683:683) (806:806:806)) + (PORT datab (143:143:143) (191:191:191)) + (PORT datad (552:552:552) (649:649:649)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2539,9 +3181,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (900:900:900) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) + (PORT clrn (898:898:898) (885:885:885)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -2550,2264 +3192,14 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1642:1642:1642)) - (PORT datab (866:866:866) (1015:1015:1015)) - (PORT datac (659:659:659) (783:783:783)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1652:1652:1652)) - (PORT datac (1408:1408:1408) (1660:1660:1660)) - (PORT datad (1036:1036:1036) (1194:1194:1194)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1258:1258:1258)) - (PORT datab (1172:1172:1172) (1380:1380:1380)) - (PORT datac (836:836:836) (990:990:990)) - (PORT datad (111:111:111) (136:136:136)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datab (1400:1400:1400) (1645:1645:1645)) - (PORT datac (1217:1217:1217) (1400:1400:1400)) - (PORT datad (823:823:823) (960:960:960)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (421:421:421)) - (PORT datac (834:834:834) (966:966:966)) - (PORT datad (352:352:352) (425:425:425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT datac (312:312:312) (377:377:377)) - (PORT datad (355:355:355) (428:428:428)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT datab (647:647:647) (759:759:759)) - (PORT datac (832:832:832) (977:977:977)) - (PORT datad (661:661:661) (784:784:784)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT datab (935:935:935) (1113:1113:1113)) - (PORT datad (926:926:926) (1075:1075:1075)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1651:1651:1651)) - (PORT datab (1434:1434:1434) (1688:1688:1688)) - (PORT datac (840:840:840) (995:995:995)) - (PORT datad (1038:1038:1038) (1195:1195:1195)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (173:173:173)) - (PORT datab (483:483:483) (557:557:557)) - (PORT datac (722:722:722) (838:838:838)) - (PORT datad (450:450:450) (533:533:533)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datab (955:955:955) (1140:1140:1140)) - (PORT datad (1016:1016:1016) (1186:1186:1186)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (285:285:285)) - (PORT datad (136:136:136) (176:176:176)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1108:1108:1108)) - (PORT datab (626:626:626) (727:727:727)) - (PORT datac (501:501:501) (587:587:587)) - (PORT datad (1095:1095:1095) (1255:1255:1255)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (588:588:588) (701:701:701)) - (PORT datad (694:694:694) (826:826:826)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (651:651:651)) - (PORT datab (822:822:822) (952:952:952)) - (PORT datac (584:584:584) (674:674:674)) - (PORT datad (106:106:106) (125:125:125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (648:648:648)) - (PORT datab (413:413:413) (503:503:503)) - (PORT datac (498:498:498) (589:589:589)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (393:393:393) (480:480:480)) - (PORT datad (392:392:392) (472:472:472)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (407:407:407)) - (PORT datab (345:345:345) (406:406:406)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (329:329:329) (374:374:374)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (910:910:910) (1031:1031:1031)) - (PORT datad (335:335:335) (392:392:392)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (585:585:585)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (583:583:583) (685:685:685)) - (PORT datad (724:724:724) (856:856:856)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (409:409:409) (506:506:506)) - (PORT datac (525:525:525) (621:621:621)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT datab (927:927:927) (1099:1099:1099)) - (PORT datad (1056:1056:1056) (1230:1230:1230)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (159:159:159)) - (PORT datab (747:747:747) (857:857:857)) - (PORT datac (929:929:929) (1075:1075:1075)) - (PORT datad (956:956:956) (1092:1092:1092)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datac (348:348:348) (431:431:431)) - (PORT datad (366:366:366) (441:441:441)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (589:589:589) (701:701:701)) - (PORT datad (696:696:696) (828:828:828)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1419:1419:1419)) - (PORT datab (801:801:801) (908:908:908)) - (PORT datac (615:615:615) (693:693:693)) - (PORT datad (338:338:338) (395:395:395)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (741:741:741)) - (PORT datab (498:498:498) (585:585:585)) - (PORT datac (769:769:769) (885:885:885)) - (PORT datad (344:344:344) (410:410:410)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1218:1218:1218)) - (PORT datab (952:952:952) (1136:1136:1136)) - (PORT datac (962:962:962) (1114:1114:1114)) - (PORT datad (471:471:471) (545:545:545)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT datab (893:893:893) (1057:1057:1057)) - (PORT datac (982:982:982) (1155:1155:1155)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (918:918:918)) - (PORT datab (847:847:847) (969:969:969)) - (PORT datac (687:687:687) (795:795:795)) - (PORT datad (682:682:682) (781:781:781)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (596:596:596) (688:688:688)) - (PORT datac (936:936:936) (1068:1068:1068)) - (PORT datad (549:549:549) (637:637:637)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (575:575:575)) - (PORT datab (355:355:355) (417:417:417)) - (PORT datac (1159:1159:1159) (1382:1382:1382)) - (PORT datad (497:497:497) (574:574:574)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1107:1107:1107)) - (PORT datab (134:134:134) (169:169:169)) - (PORT datac (500:500:500) (586:586:586)) - (PORT datad (517:517:517) (599:599:599)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (956:956:956) (1142:1142:1142)) - (PORT datad (1016:1016:1016) (1186:1186:1186)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (1109:1109:1109)) - (PORT datab (134:134:134) (168:168:168)) - (PORT datac (501:501:501) (587:587:587)) - (PORT datad (643:643:643) (744:744:744)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1071:1071:1071)) - (PORT datab (748:748:748) (856:856:856)) - (PORT datac (1414:1414:1414) (1606:1606:1606)) - (PORT datad (618:618:618) (710:710:710)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (570:570:570)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (614:614:614) (723:723:723)) - (PORT datad (521:521:521) (622:622:622)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (287:287:287)) - (PORT datab (389:389:389) (468:468:468)) - (PORT datad (491:491:491) (569:569:569)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (647:647:647)) - (PORT datac (378:378:378) (464:464:464)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1312:1312:1312) (1557:1557:1557)) - (PORT datad (685:685:685) (808:808:808)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (407:407:407)) - (PORT datab (746:746:746) (854:854:854)) - (PORT datac (916:916:916) (1049:1049:1049)) - (PORT datad (493:493:493) (572:572:572)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (570:570:570)) - (PORT datab (177:177:177) (215:215:215)) - (PORT datac (332:332:332) (384:384:384)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (868:868:868)) - (PORT datab (523:523:523) (603:603:603)) - (PORT datac (829:829:829) (980:980:980)) - (PORT datad (662:662:662) (767:767:767)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (140:140:140) (187:187:187)) - (PORT datac (127:127:127) (168:168:168)) - (PORT datad (208:208:208) (261:261:261)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (290:290:290)) - (PORT datab (938:938:938) (1087:1087:1087)) - (PORT datac (1058:1058:1058) (1236:1236:1236)) - (PORT datad (443:443:443) (531:531:531)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (290:290:290)) - (PORT datab (938:938:938) (1087:1087:1087)) - (PORT datac (1057:1057:1057) (1235:1235:1235)) - (PORT datad (443:443:443) (530:530:530)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (293:293:293)) - (PORT datab (942:942:942) (1092:1092:1092)) - (PORT datac (1063:1063:1063) (1242:1242:1242)) - (PORT datad (449:449:449) (537:537:537)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (925:925:925)) - (PORT datab (345:345:345) (410:410:410)) - (PORT datac (354:354:354) (419:419:419)) - (PORT datad (347:347:347) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (451:451:451)) - (PORT datab (798:798:798) (958:958:958)) - (PORT datac (781:781:781) (935:935:935)) - (PORT datad (378:378:378) (457:457:457)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (771:771:771)) - (PORT datab (524:524:524) (612:612:612)) - (PORT datac (378:378:378) (464:464:464)) - (PORT datad (388:388:388) (468:468:468)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (874:874:874)) - (PORT datab (645:645:645) (762:762:762)) - (PORT datac (378:378:378) (464:464:464)) - (PORT datad (388:388:388) (468:468:468)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1420:1420:1420) (1646:1646:1646)) - (PORT datab (127:127:127) (154:154:154)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (913:913:913) (1027:1027:1027)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (593:593:593)) - (PORT datab (177:177:177) (217:217:217)) - (PORT datad (175:175:175) (207:207:207)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (1107:1107:1107)) - (PORT datab (861:861:861) (1009:1009:1009)) - (PORT datac (927:927:927) (1072:1072:1072)) - (PORT datad (993:993:993) (1182:1182:1182)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (728:728:728)) - (PORT datab (835:835:835) (959:959:959)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (443:443:443) (528:528:528)) - (PORT datac (549:549:549) (647:647:647)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1168:1168:1168)) - (PORT datab (608:608:608) (719:719:719)) - (PORT datac (965:965:965) (1116:1116:1116)) - (PORT datad (116:116:116) (141:141:141)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (918:918:918)) - (PORT datad (1121:1121:1121) (1297:1297:1297)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (890:890:890)) - (PORT datab (460:460:460) (537:537:537)) - (PORT datac (507:507:507) (599:599:599)) - (PORT datad (328:328:328) (382:382:382)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (774:774:774)) - (PORT datab (142:142:142) (174:174:174)) - (PORT datac (523:523:523) (606:606:606)) - (PORT datad (664:664:664) (769:769:769)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (344:344:344)) - (PORT datab (771:771:771) (925:925:925)) - (PORT datac (432:432:432) (495:495:495)) - (PORT datad (486:486:486) (585:585:585)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1217:1217:1217)) - (PORT datab (955:955:955) (1139:1139:1139)) - (PORT datac (966:966:966) (1118:1118:1118)) - (PORT datad (473:473:473) (548:548:548)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT datab (902:902:902) (1067:1067:1067)) - (PORT datac (778:778:778) (895:895:895)) - (PORT datad (749:749:749) (871:871:871)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (1197:1197:1197) (1407:1407:1407)) - (PORT datad (519:519:519) (618:618:618)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (602:602:602)) - (PORT datab (746:746:746) (854:854:854)) - (PORT datac (916:916:916) (1049:1049:1049)) - (PORT datad (656:656:656) (754:754:754)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (572:572:572)) - (PORT datab (384:384:384) (460:460:460)) - (PORT datac (510:510:510) (587:587:587)) - (PORT datad (367:367:367) (443:443:443)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (735:735:735)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (483:483:483) (565:565:565)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (654:654:654)) - (PORT datab (1122:1122:1122) (1279:1279:1279)) - (PORT datac (553:553:553) (639:639:639)) - (PORT datad (617:617:617) (711:711:711)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1614:1614:1614)) - (PORT datab (676:676:676) (799:799:799)) - (PORT datac (800:800:800) (961:961:961)) - (PORT datad (295:295:295) (336:336:336)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (292:292:292)) - (PORT datab (409:409:409) (501:501:501)) - (PORT datac (574:574:574) (652:652:652)) - (PORT datad (448:448:448) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1482:1482:1482)) - (PORT datab (362:362:362) (428:428:428)) - (PORT datac (461:461:461) (534:534:534)) - (PORT datad (1073:1073:1073) (1267:1267:1267)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1151:1151:1151)) - (PORT datab (390:390:390) (479:479:479)) - (PORT datac (1026:1026:1026) (1170:1170:1170)) - (PORT datad (923:923:923) (1097:1097:1097)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (561:561:561)) - (PORT datab (1080:1080:1080) (1265:1265:1265)) - (PORT datac (168:168:168) (199:199:199)) - (PORT datad (940:940:940) (1086:1086:1086)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (620:620:620)) - (PORT datab (1084:1084:1084) (1288:1288:1288)) - (PORT datac (1236:1236:1236) (1458:1458:1458)) - (PORT datad (515:515:515) (608:608:608)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (938:938:938) (1079:1079:1079)) - (PORT datad (1215:1215:1215) (1390:1390:1390)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_ir_we\~8) (DELAY (ABSOLUTE - (PORT dataa (732:732:732) (864:864:864)) - (PORT datab (340:340:340) (412:412:412)) - (PORT datac (460:460:460) (528:528:528)) - (PORT datad (461:461:461) (526:526:526)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (927:927:927)) - (PORT datab (851:851:851) (977:977:977)) - (PORT datac (688:688:688) (796:796:796)) - (PORT datad (518:518:518) (603:603:603)) + (PORT dataa (534:534:534) (637:637:637)) + (PORT datac (542:542:542) (654:654:654)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (509:509:509) (585:585:585)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1147:1147:1147)) - (PORT datab (956:956:956) (1140:1140:1140)) - (PORT datad (1016:1016:1016) (1186:1186:1186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (652:652:652)) - (PORT datac (765:765:765) (898:898:898)) - (PORT datad (508:508:508) (587:587:587)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1731:1731:1731)) - (PORT datab (404:404:404) (477:477:477)) - (PORT datac (554:554:554) (652:652:652)) - (PORT datad (488:488:488) (561:561:561)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (661:661:661)) - (PORT datac (597:597:597) (676:676:676)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datab (858:858:858) (1006:1006:1006)) - (PORT datac (663:663:663) (787:787:787)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (654:654:654)) - (PORT datab (810:810:810) (934:934:934)) - (PORT datac (766:766:766) (899:899:899)) - (PORT datad (509:509:509) (587:587:587)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (788:788:788)) - (PORT datab (346:346:346) (406:406:406)) - (PORT datac (651:651:651) (742:742:742)) - (PORT datad (1096:1096:1096) (1266:1266:1266)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (800:800:800)) - (PORT datab (795:795:795) (949:949:949)) - (PORT datac (1257:1257:1257) (1462:1462:1462)) - (PORT datad (1356:1356:1356) (1586:1586:1586)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (555:555:555)) - (PORT datab (1075:1075:1075) (1260:1260:1260)) - (PORT datac (165:165:165) (196:196:196)) - (PORT datad (933:933:933) (1078:1078:1078)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (883:883:883)) - (PORT datab (352:352:352) (420:420:420)) - (PORT datac (1251:1251:1251) (1430:1430:1430)) - (PORT datad (1107:1107:1107) (1296:1296:1296)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (799:799:799)) - (PORT datab (818:818:818) (980:980:980)) - (PORT datac (1255:1255:1255) (1459:1459:1459)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (442:442:442) (505:505:505)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1077:1077:1077)) - (PORT datac (497:497:497) (569:569:569)) - (PORT datad (788:788:788) (929:929:929)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (1027:1027:1027)) - (PORT datab (1123:1123:1123) (1280:1280:1280)) - (PORT datac (633:633:633) (721:721:721)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1510:1510:1510) (1732:1732:1732)) - (PORT datab (569:569:569) (661:661:661)) - (PORT datac (471:471:471) (565:565:565)) - (PORT datad (386:386:386) (452:452:452)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (365:365:365)) - (PORT datab (442:442:442) (524:524:524)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (618:618:618)) - (PORT datab (661:661:661) (772:772:772)) - (PORT datac (1052:1052:1052) (1208:1208:1208)) - (PORT datad (342:342:342) (394:394:394)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (1084:1084:1084)) - (PORT datab (297:297:297) (338:338:338)) - (PORT datac (102:102:102) (124:124:124)) - (PORT datad (182:182:182) (216:216:216)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (239:239:239)) - (PORT datab (506:506:506) (599:599:599)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (598:598:598) (680:680:680)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datab (778:778:778) (933:933:933)) - (PORT datad (527:527:527) (633:633:633)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (400:400:400)) - (PORT datab (460:460:460) (558:558:558)) - (PORT datac (980:980:980) (1134:1134:1134)) - (PORT datad (109:109:109) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (783:783:783)) - (PORT datab (474:474:474) (571:571:571)) - (PORT datac (472:472:472) (566:566:566)) - (PORT datad (486:486:486) (560:560:560)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (679:679:679) (788:788:788)) - (PORT datac (549:549:549) (630:630:630)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (560:560:560)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (104:104:104) (126:126:126)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (401:401:401)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (189:189:189) (223:223:223)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT datab (860:860:860) (1008:1008:1008)) - (PORT datac (927:927:927) (1072:1072:1072)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (919:919:919)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (721:721:721) (852:852:852)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1300:1300:1300)) - (PORT datac (644:644:644) (752:752:752)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (167:167:167)) - (PORT datab (855:855:855) (1020:1020:1020)) - (PORT datac (963:963:963) (1115:1115:1115)) - (PORT datad (719:719:719) (817:817:817)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (949:949:949)) - (PORT datab (667:667:667) (775:775:775)) - (PORT datac (347:347:347) (412:412:412)) - (PORT datad (353:353:353) (414:414:414)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (590:590:590) (701:701:701)) - (PORT datad (697:697:697) (829:829:829)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1277:1277:1277) (1502:1502:1502)) - (PORT datac (784:784:784) (944:944:944)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1255:1255:1255)) - (PORT datab (929:929:929) (1102:1102:1102)) - (PORT datac (822:822:822) (943:943:943)) - (PORT datad (584:584:584) (694:694:694)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (391:391:391)) - (PORT datab (747:747:747) (848:848:848)) - (PORT datac (342:342:342) (389:389:389)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (750:750:750)) - (PORT datab (364:364:364) (430:430:430)) - (PORT datac (102:102:102) (122:122:122)) - (PORT datad (326:326:326) (377:377:377)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (916:916:916) (897:897:897)) - (PORT ena (658:658:658) (719:719:719)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (909:909:909)) - (PORT asdata (365:365:365) (415:415:415)) - (PORT clrn (915:915:915) (897:897:897)) - (PORT ena (764:764:764) (833:833:833)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (361:361:361) (429:429:429)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT asdata (299:299:299) (340:340:340)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (184:184:184)) - (PORT datad (360:360:360) (427:427:427)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (1044:1044:1044)) - (PORT datac (806:806:806) (925:925:925)) - (PORT datad (662:662:662) (766:766:766)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (115:115:115) (149:149:149)) - (PORT datac (553:553:553) (651:651:651)) - (PORT datad (831:831:831) (963:963:963)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (779:779:779)) - (PORT datab (1054:1054:1054) (1212:1212:1212)) - (PORT datac (584:584:584) (688:688:688)) - (PORT datad (580:580:580) (682:682:682)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~18) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1154:1154:1154)) - (PORT datab (348:348:348) (408:408:408)) - (PORT datad (921:921:921) (1090:1090:1090)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (578:578:578)) - (PORT datab (687:687:687) (795:795:795)) - (PORT datac (446:446:446) (516:516:516)) - (PORT datad (98:98:98) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) - (DELAY - (ABSOLUTE - (PORT dataa (525:525:525) (622:622:622)) - (PORT datab (536:536:536) (635:635:635)) - (PORT datac (1128:1128:1128) (1307:1307:1307)) - (PORT datad (843:843:843) (988:988:988)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (420:420:420)) - (PORT datab (840:840:840) (984:984:984)) - (PORT datac (967:967:967) (1130:1130:1130)) - (PORT datad (342:342:342) (399:399:399)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (400:400:400)) - (PORT datab (998:998:998) (1153:1153:1153)) - (PORT datac (492:492:492) (573:573:573)) - (PORT datad (311:311:311) (345:345:345)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (371:371:371)) - (PORT datab (350:350:350) (417:417:417)) - (PORT datac (786:786:786) (916:916:916)) - (PORT datad (996:996:996) (1163:1163:1163)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (395:395:395)) - (PORT datab (642:642:642) (742:742:742)) - (PORT datac (502:502:502) (584:584:584)) - (PORT datad (100:100:100) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (389:389:389)) - (PORT datab (1000:1000:1000) (1149:1149:1149)) - (PORT datac (463:463:463) (538:538:538)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datab (1489:1489:1489) (1764:1764:1764)) - (PORT datac (1107:1107:1107) (1306:1306:1306)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (1075:1075:1075)) - (PORT datab (940:940:940) (1062:1062:1062)) - (PORT datac (726:726:726) (832:832:832)) - (PORT datad (618:618:618) (716:716:716)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (590:590:590)) - (PORT datab (672:672:672) (794:794:794)) - (PORT datac (363:363:363) (442:442:442)) - (PORT datad (370:370:370) (436:436:436)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (469:469:469)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (651:651:651) (737:737:737)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (819:819:819)) - (PORT datab (603:603:603) (694:694:694)) - (PORT datac (779:779:779) (896:896:896)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (951:951:951)) - (PORT datab (839:839:839) (992:992:992)) - (PORT datac (796:796:796) (927:927:927)) - (PORT datad (777:777:777) (894:894:894)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (344:344:344) (409:409:409)) - (PORT datac (1005:1005:1005) (1145:1145:1145)) - (PORT datad (348:348:348) (409:409:409)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT datac (664:664:664) (784:784:784)) - (PORT datad (658:658:658) (754:754:754)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (956:956:956)) - (PORT datab (620:620:620) (711:711:711)) - (PORT datac (356:356:356) (421:421:421)) - (PORT datad (824:824:824) (967:967:967)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT datac (669:669:669) (789:789:789)) - (PORT datad (663:663:663) (760:760:760)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (418:418:418)) - (PORT datab (132:132:132) (161:161:161)) - (PORT datac (513:513:513) (594:594:594)) - (PORT datad (449:449:449) (515:515:515)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (592:592:592)) - (PORT datab (501:501:501) (582:582:582)) - (PORT datac (491:491:491) (567:567:567)) - (PORT datad (316:316:316) (367:367:367)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (971:971:971)) - (PORT datad (675:675:675) (789:789:789)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (400:400:400)) - (PORT datab (445:445:445) (519:519:519)) - (PORT datac (604:604:604) (685:685:685)) - (PORT datad (1336:1336:1336) (1531:1531:1531)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (903:903:903)) - (PORT ena (623:623:623) (673:673:673)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (118:118:118) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (903:903:903)) - (PORT ena (609:609:609) (652:652:652)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (493:493:493) (578:578:578)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (133:133:133) (182:182:182)) - (PORT datac (582:582:582) (688:688:688)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) ) ) @@ -4817,16 +3209,16 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) + (PORT clk (915:915:915) (903:903:903)) + (PORT asdata (607:607:607) (667:667:667)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (643:643:643) (700:700:700)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -4835,8 +3227,8 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (117:117:117) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -4845,10 +3237,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) + (PORT clk (915:915:915) (903:903:903)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (643:643:643) (700:700:700)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -4863,10 +3255,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (904:904:904) (911:911:911)) - (PORT asdata (298:298:298) (339:339:339)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (681:681:681) (744:744:744)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (299:299:299) (341:341:341)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (660:660:660) (730:730:730)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -4881,9 +3273,9 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (707:707:707)) - (PORT datab (134:134:134) (183:183:183)) - (PORT datad (754:754:754) (862:862:862)) + (PORT dataa (629:629:629) (738:738:738)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datad (229:229:229) (280:280:280)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -4891,151 +3283,83 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (1071:1071:1071)) + (PORT datab (687:687:687) (810:810:810)) + (PORT datac (1369:1369:1369) (1599:1599:1599)) + (PORT datad (706:706:706) (839:839:839)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (828:828:828)) + (PORT datac (939:939:939) (1116:1116:1116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (850:850:850) (1002:1002:1002)) + (PORT datad (1005:1005:1005) (1168:1168:1168)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (498:498:498) (591:591:591)) + (PORT datad (1053:1053:1053) (1253:1253:1253)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (792:792:792)) + (PORT datab (665:665:665) (785:785:785)) + (PORT datac (387:387:387) (473:473:473)) + (PORT datad (130:130:130) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (540:540:540) (650:650:650)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (585:585:585) (674:674:674)) - (PORT datad (806:806:806) (929:929:929)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (860:860:860)) - (PORT datab (531:531:531) (627:627:627)) - (PORT datac (659:659:659) (757:757:757)) - (PORT datad (810:810:810) (914:914:914)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1143:1143:1143)) - (PORT datab (952:952:952) (1137:1137:1137)) - (PORT datac (592:592:592) (699:699:699)) - (PORT datad (1016:1016:1016) (1187:1187:1187)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datab (926:926:926) (1099:1099:1099)) - (PORT datad (1056:1056:1056) (1230:1230:1230)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (141:141:141) (176:176:176)) - (PORT datab (1011:1011:1011) (1204:1204:1204)) - (PORT datac (769:769:769) (909:909:909)) - (PORT datad (1617:1617:1617) (1861:1861:1861)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (175:175:175)) - (PORT datab (531:531:531) (627:627:627)) - (PORT datac (659:659:659) (757:757:757)) - (PORT datad (974:974:974) (1127:1127:1127)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (720:720:720)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (771:771:771) (873:873:873)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (1019:1019:1019)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (304:304:304)) - (PORT datad (315:315:315) (372:372:372)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (947:947:947)) - (PORT datab (801:801:801) (917:917:917)) - (PORT datac (784:784:784) (945:945:945)) - (PORT datad (1424:1424:1424) (1645:1645:1645)) + (PORT dataa (120:120:120) (151:151:151)) + (PORT datab (402:402:402) (478:478:478)) + (PORT datac (1645:1645:1645) (1904:1904:1904)) + (PORT datad (629:629:629) (716:716:716)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -5043,337 +3367,173 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datab (881:881:881) (1038:1038:1038)) + (PORT datac (721:721:721) (848:848:848)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datac (597:597:597) (723:723:723)) + (PORT datad (1178:1178:1178) (1370:1370:1370)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (837:837:837) (967:967:967)) + (PORT datad (675:675:675) (797:797:797)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (966:966:966)) + (PORT datab (399:399:399) (475:475:475)) + (PORT datac (1648:1648:1648) (1908:1908:1908)) + (PORT datad (629:629:629) (715:715:715)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (720:720:720)) + (PORT datab (373:373:373) (432:432:432)) + (PORT datac (818:818:818) (939:939:939)) + (PORT datad (612:612:612) (697:697:697)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (850:850:850)) + (PORT datab (1007:1007:1007) (1211:1211:1211)) + (PORT datac (691:691:691) (813:813:813)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (777:777:777)) + (PORT datac (809:809:809) (953:953:953)) + (PORT datad (1445:1445:1445) (1668:1668:1668)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (858:858:858) (1032:1032:1032)) + (PORT datad (703:703:703) (841:841:841)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (961:961:961)) + (PORT datab (720:720:720) (848:848:848)) + (PORT datac (328:328:328) (377:377:377)) + (PORT datad (695:695:695) (832:832:832)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1491:1491:1491)) + (PORT datab (895:895:895) (1061:1061:1061)) + (PORT datac (488:488:488) (571:571:571)) + (PORT datad (1117:1117:1117) (1296:1296:1296)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|decode_state_\|DFFE_instED) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (524:524:524) (568:568:568)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (498:498:498) (538:538:538)) + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (INSTANCE z80_\|pla_decode_\|Equal6\~0) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (253:253:253)) - (PORT datab (459:459:459) (544:544:544)) - (PORT datad (148:148:148) (192:192:192)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (1041:1041:1041)) - (PORT datab (142:142:142) (175:175:175)) - (PORT datac (803:803:803) (922:922:922)) - (PORT datad (665:665:665) (769:769:769)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (946:946:946) (1099:1099:1099)) - (PORT datab (125:125:125) (159:159:159)) - (PORT datac (989:989:989) (1138:1138:1138)) - (PORT datad (457:457:457) (549:549:549)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (285:285:285)) - (PORT datab (712:712:712) (831:831:831)) - (PORT datac (747:747:747) (859:859:859)) - (PORT datad (349:349:349) (408:408:408)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT datab (351:351:351) (401:401:401)) - (PORT datac (456:456:456) (532:532:532)) - (PORT datad (458:458:458) (519:519:519)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (293:293:293)) - (PORT datab (943:943:943) (1093:1093:1093)) - (PORT datac (1064:1064:1064) (1243:1243:1243)) - (PORT datad (450:450:450) (538:538:538)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT datab (804:804:804) (934:934:934)) - (PORT datac (654:654:654) (752:752:752)) - (PORT datad (799:799:799) (923:923:923)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (507:507:507)) - (PORT datab (410:410:410) (503:503:503)) - (PORT datac (1060:1060:1060) (1238:1238:1238)) - (PORT datad (938:938:938) (1083:1083:1083)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (575:575:575)) - (PORT datab (572:572:572) (675:675:675)) - (PORT datac (803:803:803) (922:922:922)) - (PORT datad (835:835:835) (969:969:969)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (576:576:576)) - (PORT datab (510:510:510) (622:622:622)) - (PORT datac (585:585:585) (687:687:687)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT datab (355:355:355) (421:421:421)) - (PORT datac (442:442:442) (500:500:500)) - (PORT datad (455:455:455) (517:517:517)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (1042:1042:1042)) - (PORT datac (804:804:804) (923:923:923)) - (PORT datad (664:664:664) (768:768:768)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (946:946:946)) - (PORT datab (539:539:539) (629:629:629)) - (PORT datac (656:656:656) (749:749:749)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (758:758:758)) - (PORT datab (357:357:357) (421:421:421)) - (PORT datac (912:912:912) (1043:1043:1043)) - (PORT datad (492:492:492) (577:577:577)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1168:1168:1168)) - (PORT datab (608:608:608) (720:720:720)) - (PORT datac (964:964:964) (1116:1116:1116)) - (PORT datad (117:117:117) (141:141:141)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1417:1417:1417)) - (PORT datab (1476:1476:1476) (1702:1702:1702)) - (PORT datac (782:782:782) (932:932:932)) - (PORT datad (473:473:473) (552:552:552)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1460:1460:1460)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (338:338:338) (398:398:398)) - (PORT datad (568:568:568) (663:663:663)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT datab (897:897:897) (1044:1044:1044)) - (PORT datac (686:686:686) (796:796:796)) - (PORT datad (617:617:617) (704:704:704)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (859:859:859)) - (PORT datab (526:526:526) (606:606:606)) - (PORT datac (819:819:819) (969:969:969)) - (PORT datad (667:667:667) (773:773:773)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (574:574:574)) - (PORT datab (568:568:568) (671:671:671)) - (PORT datac (807:807:807) (926:926:926)) - (PORT datad (828:828:828) (960:960:960)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (499:499:499)) - (PORT datab (319:319:319) (371:371:371)) - (PORT datac (911:911:911) (1033:1033:1033)) - (PORT datad (881:881:881) (996:996:996)) + (PORT dataa (976:976:976) (1146:1146:1146)) + (PORT datab (530:530:530) (632:632:632)) + (PORT datac (369:369:369) (450:450:450)) + (PORT datad (467:467:467) (546:546:546)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -5383,12 +3543,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (423:423:423)) - (PORT datac (612:612:612) (704:704:704)) - (PORT datad (462:462:462) (553:553:553)) + (PORT dataa (634:634:634) (734:734:734)) + (PORT datac (688:688:688) (794:794:794)) + (PORT datad (435:435:435) (489:489:489)) (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -5397,105 +3557,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (1193:1193:1193) (1420:1420:1420)) - (PORT datab (358:358:358) (420:420:420)) - (PORT datac (601:601:601) (709:709:709)) - (PORT datad (478:478:478) (548:548:548)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (202:202:202) (239:239:239)) - (PORT datac (352:352:352) (430:430:430)) + (PORT dataa (970:970:970) (1138:1138:1138)) + (PORT datab (526:526:526) (627:627:627)) + (PORT datac (362:362:362) (442:442:442)) + (PORT datad (462:462:462) (541:541:541)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (764:764:764) (868:868:868)) - (PORT datab (1070:1070:1070) (1233:1233:1233)) - (PORT datac (501:501:501) (587:587:587)) - (PORT datad (120:120:120) (145:145:145)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1742:1742:1742) (2009:2009:2009)) - (PORT datab (462:462:462) (540:540:540)) - (PORT datac (842:842:842) (990:990:990)) - (PORT datad (1111:1111:1111) (1269:1269:1269)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datab (991:991:991) (1168:1168:1168)) - (PORT datad (1314:1314:1314) (1503:1503:1503)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (574:574:574)) - (PORT datab (200:200:200) (244:244:244)) - (PORT datac (991:991:991) (1140:1140:1140)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (763:763:763)) - (PORT datab (999:999:999) (1153:1153:1153)) - (PORT datac (319:319:319) (370:370:370)) - (PORT datad (336:336:336) (388:388:388)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -5503,2472 +3573,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT datab (486:486:486) (566:566:566)) - (PORT datac (505:505:505) (592:592:592)) - (PORT datad (311:311:311) (360:360:360)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1060:1060:1060) (1223:1223:1223)) - (PORT datab (944:944:944) (1126:1126:1126)) - (PORT datac (332:332:332) (390:390:390)) - (PORT datad (974:974:974) (1126:1126:1126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (554:554:554)) - (PORT datab (179:179:179) (218:218:218)) - (PORT datac (1105:1105:1105) (1295:1295:1295)) - (PORT datad (600:600:600) (673:673:673)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~14) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (142:142:142) (176:176:176)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (102:102:102) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (740:740:740)) - (PORT datab (346:346:346) (409:409:409)) - (PORT datac (520:520:520) (609:609:609)) - (PORT datad (643:643:643) (736:736:736)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1101:1101:1101)) - (PORT datab (744:744:744) (855:855:855)) - (PORT datac (991:991:991) (1140:1140:1140)) - (PORT datad (117:117:117) (142:142:142)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (342:342:342) (393:393:393)) - (PORT datad (460:460:460) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (777:777:777)) - (PORT datab (190:190:190) (230:230:230)) - (PORT datac (1034:1034:1034) (1191:1191:1191)) - (PORT datad (318:318:318) (372:372:372)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1652:1652:1652)) - (PORT datab (1432:1432:1432) (1685:1685:1685)) - (PORT datad (1037:1037:1037) (1195:1195:1195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1225:1225:1225)) - (PORT datab (487:487:487) (565:565:565)) - (PORT datac (931:931:931) (1095:1095:1095)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1109:1109:1109)) - (PORT datab (622:622:622) (733:733:733)) - (PORT datac (501:501:501) (587:587:587)) - (PORT datad (120:120:120) (145:145:145)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (597:597:597)) - (PORT datab (774:774:774) (869:869:869)) - (PORT datac (325:325:325) (388:388:388)) - (PORT datad (441:441:441) (506:506:506)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1060:1060:1060) (1223:1223:1223)) - (PORT datab (944:944:944) (1125:1125:1125)) - (PORT datac (332:332:332) (390:390:390)) - (PORT datad (974:974:974) (1126:1126:1126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1450:1450:1450)) - (PORT datab (484:484:484) (560:560:560)) - (PORT datac (885:885:885) (1057:1057:1057)) - (PORT datad (949:949:949) (1083:1083:1083)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (585:585:585)) - (PORT datab (886:886:886) (1031:1031:1031)) - (PORT datac (662:662:662) (769:769:769)) - (PORT datad (940:940:940) (1066:1066:1066)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (492:492:492)) - (PORT datab (897:897:897) (1044:1044:1044)) - (PORT datac (687:687:687) (797:797:797)) - (PORT datad (617:617:617) (705:705:705)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1413:1413:1413)) - (PORT datab (801:801:801) (907:907:907)) - (PORT datac (614:614:614) (693:693:693)) - (PORT datad (337:337:337) (393:393:393)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (599:599:599)) - (PORT datab (292:292:292) (343:343:343)) - (PORT datac (296:296:296) (337:337:337)) - (PORT datad (298:298:298) (342:342:342)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (114:114:114) (143:143:143)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (119:119:119) (138:138:138)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (574:574:574)) - (PORT datab (384:384:384) (458:458:458)) - (PORT datac (720:720:720) (818:818:818)) - (PORT datad (654:654:654) (750:750:750)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (592:592:592)) - (PORT datab (821:821:821) (954:954:954)) - (PORT datac (485:485:485) (558:558:558)) - (PORT datad (114:114:114) (135:135:135)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (563:563:563)) - (PORT datab (381:381:381) (463:463:463)) - (PORT datac (164:164:164) (194:194:194)) - (PORT datad (456:456:456) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (420:420:420)) - (PORT datab (495:495:495) (576:576:576)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (470:470:470) (541:541:541)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (291:291:291)) - (PORT datab (590:590:590) (670:670:670)) - (PORT datac (387:387:387) (484:484:484)) - (PORT datad (391:391:391) (478:478:478)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (389:389:389)) - (PORT datab (349:349:349) (410:410:410)) - (PORT datac (310:310:310) (359:359:359)) - (PORT datad (361:361:361) (421:421:421)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (537:537:537)) - (PORT datab (324:324:324) (384:384:384)) - (PORT datac (842:842:842) (968:968:968)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (494:494:494) (571:571:571)) - (PORT datac (314:314:314) (368:368:368)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (405:405:405)) - (PORT datab (674:674:674) (788:788:788)) - (PORT datad (486:486:486) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (758:758:758)) - (PORT datab (347:347:347) (411:411:411)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (1337:1337:1337) (1531:1531:1531)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (496:496:496)) - (PORT datab (313:313:313) (363:363:363)) - (PORT datac (464:464:464) (536:536:536)) - (PORT datad (572:572:572) (673:673:673)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (681:681:681) (744:744:744)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (128:128:128) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datad (129:129:129) (172:172:172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (443:443:443) (512:512:512)) - (PORT datac (107:107:107) (131:131:131)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (1080:1080:1080) (1284:1284:1284)) - (PORT datac (1739:1739:1739) (2035:2035:2035)) - (PORT datad (1448:1448:1448) (1664:1664:1664)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (478:478:478) (503:503:503)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (204:204:204)) - (PORT datab (158:158:158) (213:213:213)) - (PORT datad (137:137:137) (182:182:182)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1926:1926:1926) (2185:2185:2185)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (123:123:123) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (130:130:130) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (PORT datab (134:134:134) (184:184:184)) - (PORT datac (198:198:198) (247:247:247)) - (PORT datad (124:124:124) (163:163:163)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (137:137:137) (190:190:190)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (122:122:122) (164:164:164)) - (PORT datad (125:125:125) (165:165:165)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (122:122:122) (164:164:164)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (109:109:109) (140:140:140)) - (PORT datac (122:122:122) (166:166:166)) - (PORT datad (118:118:118) (156:156:156)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (893:893:893) (896:896:896)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (893:893:893)) - (PORT ena (1192:1192:1192) (1344:1344:1344)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (203:203:203)) - (PORT datab (148:148:148) (203:203:203)) - (PORT datad (138:138:138) (183:183:183)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (893:893:893)) - (PORT ena (1192:1192:1192) (1344:1344:1344)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (207:207:207)) - (PORT datab (160:160:160) (216:216:216)) - (PORT datad (135:135:135) (181:181:181)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (893:893:893)) - (PORT ena (1192:1192:1192) (1344:1344:1344)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (152:152:152) (211:211:211)) - (PORT datab (156:156:156) (211:211:211)) - (PORT datad (134:134:134) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (893:893:893)) - (PORT ena (1192:1192:1192) (1344:1344:1344)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (150:150:150) (208:208:208)) - (PORT datab (161:161:161) (217:217:217)) - (PORT datad (137:137:137) (182:182:182)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (150:150:150) (208:208:208)) - (PORT datab (150:150:150) (205:205:205)) - (PORT datac (202:202:202) (249:249:249)) - (PORT datad (1930:1930:1930) (2186:2186:2186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (208:208:208)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (858:858:858) (1002:1002:1002)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (894:894:894) (899:899:899)) - (PORT asdata (2099:2099:2099) (2358:2358:2358)) - (PORT clrn (887:887:887) (891:891:891)) - (PORT ena (865:865:865) (948:948:948)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (894:894:894) (899:899:899)) - (PORT asdata (366:366:366) (414:414:414)) - (PORT clrn (887:887:887) (891:891:891)) - (PORT ena (865:865:865) (948:948:948)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (894:894:894) (899:899:899)) - (PORT asdata (331:331:331) (390:390:390)) - (PORT clrn (887:887:887) (891:891:891)) - (PORT ena (865:865:865) (948:948:948)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) - (PORT asdata (708:708:708) (799:799:799)) - (PORT clrn (883:883:883) (888:888:888)) - (PORT ena (907:907:907) (992:992:992)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (894:894:894) (899:899:899)) - (PORT asdata (673:673:673) (771:771:771)) - (PORT clrn (887:887:887) (891:891:891)) - (PORT ena (865:865:865) (948:948:948)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT asdata (714:714:714) (822:822:822)) - (PORT clrn (883:883:883) (887:887:887)) - (PORT ena (763:763:763) (839:839:839)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT asdata (620:620:620) (688:688:688)) - (PORT clrn (883:883:883) (887:887:887)) - (PORT ena (763:763:763) (839:839:839)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT asdata (324:324:324) (372:372:372)) - (PORT clrn (883:883:883) (887:887:887)) - (PORT ena (763:763:763) (839:839:839)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (894:894:894) (899:899:899)) - (PORT asdata (683:683:683) (774:774:774)) - (PORT clrn (887:887:887) (891:891:891)) - (PORT ena (865:865:865) (948:948:948)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (166:166:166) (231:231:231)) - (PORT datab (511:511:511) (614:614:614)) - (PORT datac (137:137:137) (181:181:181)) - (PORT datad (518:518:518) (618:618:618)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (534:534:534)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (502:502:502) (594:594:594)) - (PORT datad (145:145:145) (188:188:188)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (240:240:240)) - (PORT datab (539:539:539) (645:645:645)) - (PORT datad (145:145:145) (189:189:189)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (598:598:598)) - (PORT datab (521:521:521) (620:620:620)) - (PORT datad (419:419:419) (512:512:512)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (128:128:128) (170:170:170)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (421:421:421)) - (PORT datab (1945:1945:1945) (2207:2207:2207)) - (PORT datac (858:858:858) (1002:1002:1002)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (893:893:893)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (430:430:430)) - (PORT datab (478:478:478) (562:562:562)) - (PORT datad (381:381:381) (454:454:454)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (460:460:460)) - (PORT datab (440:440:440) (536:536:536)) - (PORT datac (395:395:395) (484:484:484)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (473:473:473)) - (PORT datad (406:406:406) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (432:432:432)) - (PORT datad (373:373:373) (445:445:445)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (PORT ena (794:794:794) (881:881:881)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (163:163:163) (229:229:229)) - (PORT datab (353:353:353) (426:426:426)) - (PORT datac (485:485:485) (576:576:576)) - (PORT datad (146:146:146) (191:191:191)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (417:417:417)) - (PORT datab (421:421:421) (513:513:513)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (618:618:618) (700:700:700)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (243:243:243)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1296:1296:1296)) - (PORT datab (814:814:814) (961:961:961)) - (PORT datad (635:635:635) (762:762:762)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (1129:1129:1129) (1094:1094:1094)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (516:516:516) (604:604:604)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (162:162:162)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (902:902:902)) - (PORT asdata (300:300:300) (341:341:341)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (443:443:443)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datad (124:124:124) (163:163:163)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (846:846:846)) - (PORT datab (535:535:535) (643:643:643)) - (PORT datac (347:347:347) (410:410:410)) - (PORT datad (481:481:481) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1225:1225:1225)) - (PORT datab (638:638:638) (731:731:731)) - (PORT datac (933:933:933) (1097:1097:1097)) - (PORT datad (467:467:467) (541:541:541)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1225:1225:1225)) - (PORT datab (486:486:486) (564:564:564)) - (PORT datac (933:933:933) (1097:1097:1097)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1225:1225:1225)) - (PORT datab (966:966:966) (1102:1102:1102)) - (PORT datac (929:929:929) (1093:1093:1093)) - (PORT datad (468:468:468) (542:542:542)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT datab (136:136:136) (171:171:171)) - (PORT datac (140:140:140) (180:180:180)) - (PORT datad (135:135:135) (166:166:166)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (391:391:391)) - (PORT datac (918:918:918) (1055:1055:1055)) - (PORT datad (627:627:627) (728:728:728)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (418:418:418)) - (PORT datac (332:332:332) (385:385:385)) - (PORT datad (683:683:683) (791:791:791)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (423:423:423)) - (PORT datab (787:787:787) (906:906:906)) - (PORT datac (313:313:313) (355:355:355)) - (PORT datad (626:626:626) (717:717:717)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (413:413:413)) - (PORT datab (508:508:508) (593:593:593)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (484:484:484) (549:549:549)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT datab (849:849:849) (975:975:975)) - (PORT datac (686:686:686) (793:793:793)) - (PORT datad (804:804:804) (917:917:917)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (884:884:884)) - (PORT datab (899:899:899) (1072:1072:1072)) - (PORT datac (338:338:338) (399:399:399)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1326:1326:1326)) - (PORT datab (1482:1482:1482) (1751:1751:1751)) - (PORT datad (961:961:961) (1121:1121:1121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (930:930:930)) - (PORT datab (522:522:522) (605:605:605)) - (PORT datac (492:492:492) (559:559:559)) - (PORT datad (511:511:511) (592:592:592)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (1330:1330:1330) (1548:1548:1548)) - (PORT datac (1025:1025:1025) (1163:1163:1163)) - (PORT datad (988:988:988) (1156:1156:1156)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (526:526:526) (621:621:621)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (753:753:753)) - (PORT datab (326:326:326) (381:381:381)) - (PORT datac (504:504:504) (578:578:578)) - (PORT datad (466:466:466) (544:544:544)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (492:492:492) (570:570:570)) - (PORT datac (343:343:343) (397:397:397)) - (PORT datad (345:345:345) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (541:541:541)) - (PORT datab (877:877:877) (1025:1025:1025)) - (PORT datac (346:346:346) (409:409:409)) - (PORT datad (682:682:682) (790:790:790)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (97:97:97) (122:122:122)) - (PORT datad (690:690:690) (802:802:802)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (1578:1578:1578) (1849:1849:1849)) - (PORT datac (959:959:959) (1116:1116:1116)) - (PORT datad (450:450:450) (517:517:517)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (1051:1051:1051)) - (PORT datab (1134:1134:1134) (1320:1320:1320)) - (PORT datac (1242:1242:1242) (1423:1423:1423)) - (PORT datad (985:985:985) (1151:1151:1151)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1152:1152:1152)) - (PORT datab (184:184:184) (226:226:226)) - (PORT datac (1029:1029:1029) (1174:1174:1174)) - (PORT datad (914:914:914) (1087:1087:1087)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1571:1571:1571)) - (PORT datab (627:627:627) (720:720:720)) - (PORT datac (873:873:873) (1030:1030:1030)) - (PORT datad (1124:1124:1124) (1302:1302:1302)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (557:557:557)) - (PORT datab (433:433:433) (504:504:504)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (919:919:919) (1054:1054:1054)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (125:125:125) (159:159:159)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (367:367:367) (425:425:425)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (754:754:754)) - (PORT datab (461:461:461) (539:539:539)) - (PORT datac (661:661:661) (763:763:763)) - (PORT datad (497:497:497) (576:576:576)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (996:996:996)) - (PORT datab (607:607:607) (697:697:697)) - (PORT datac (966:966:966) (1116:1116:1116)) - (PORT datad (651:651:651) (752:752:752)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (991:991:991)) - (PORT datab (115:115:115) (147:147:147)) - (PORT datac (692:692:692) (818:818:818)) - (PORT datad (656:656:656) (756:756:756)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (198:198:198)) - (PORT datab (132:132:132) (167:167:167)) - (PORT datac (135:135:135) (174:174:174)) - (PORT datad (788:788:788) (901:901:901)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (369:369:369)) - (PORT datab (436:436:436) (506:506:506)) - (PORT datac (192:192:192) (222:222:222)) - (PORT datad (492:492:492) (576:576:576)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (360:360:360)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datac (613:613:613) (697:697:697)) - (PORT datad (483:483:483) (564:564:564)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (701:701:701)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (738:738:738)) - (PORT datab (1131:1131:1131) (1301:1301:1301)) - (PORT datac (789:789:789) (941:941:941)) - (PORT datad (1048:1048:1048) (1201:1201:1201)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (1100:1100:1100)) - (PORT datab (336:336:336) (393:393:393)) - (PORT datac (990:990:990) (1139:1139:1139)) - (PORT datad (587:587:587) (696:696:696)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1101:1101:1101)) - (PORT datab (335:335:335) (392:392:392)) - (PORT datac (991:991:991) (1140:1140:1140)) - (PORT datad (585:585:585) (695:695:695)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (769:769:769)) - (PORT datab (478:478:478) (561:561:561)) - (PORT datac (524:524:524) (610:610:610)) - (PORT datad (518:518:518) (607:607:607)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (251:251:251)) - (PORT datab (516:516:516) (600:600:600)) - (PORT datac (326:326:326) (377:377:377)) - (PORT datad (120:120:120) (139:139:139)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (593:593:593)) - (PORT datab (517:517:517) (598:598:598)) - (PORT datac (353:353:353) (410:410:410)) - (PORT datad (663:663:663) (765:765:765)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (641:641:641)) - (PORT datab (539:539:539) (633:633:633)) - (PORT datac (659:659:659) (754:754:754)) - (PORT datad (551:551:551) (642:642:642)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (407:407:407)) - (PORT datab (818:818:818) (946:946:946)) - (PORT datac (481:481:481) (582:582:582)) - (PORT datad (1089:1089:1089) (1263:1263:1263)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datac (745:745:745) (897:897:897)) - (PORT datad (1230:1230:1230) (1468:1468:1468)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (525:525:525)) - (PORT datab (114:114:114) (149:149:149)) - (PORT datac (635:635:635) (724:724:724)) - (PORT datad (343:343:343) (405:405:405)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (592:592:592)) - (PORT datab (829:829:829) (949:949:949)) - (PORT datac (798:798:798) (946:946:946)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (385:385:385)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (440:440:440) (506:506:506)) - (PORT datad (447:447:447) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1332:1332:1332)) - (PORT datab (326:326:326) (381:381:381)) - (PORT datac (462:462:462) (526:526:526)) - (PORT datad (381:381:381) (447:447:447)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (1098:1098:1098)) - (PORT datab (999:999:999) (1154:1154:1154)) - (PORT datac (486:486:486) (567:567:567)) - (PORT datad (380:380:380) (446:446:446)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (572:572:572)) - (PORT datab (1141:1141:1141) (1317:1317:1317)) - (PORT datac (993:993:993) (1128:1128:1128)) - (PORT datad (783:783:783) (882:882:882)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (388:388:388)) - (PORT datab (399:399:399) (470:470:470)) - (PORT datac (636:636:636) (740:740:740)) - (PORT datad (432:432:432) (496:496:496)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (397:397:397)) - (PORT datab (400:400:400) (471:471:471)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (329:329:329) (375:375:375)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (215:215:215)) - (PORT datab (103:103:103) (133:133:133)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (1046:1046:1046)) - (PORT datab (446:446:446) (520:520:520)) - (PORT datac (471:471:471) (549:549:549)) - (PORT datad (317:317:317) (359:359:359)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1093:1093:1093)) - (PORT datab (325:325:325) (379:379:379)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (1122:1122:1122) (1303:1303:1303)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (555:555:555)) - (PORT datab (611:611:611) (725:725:725)) - (PORT datac (448:448:448) (519:519:519)) - (PORT datad (346:346:346) (405:405:405)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (482:482:482)) - (PORT datab (1347:1347:1347) (1571:1571:1571)) - (PORT datac (421:421:421) (511:511:511)) - (PORT datad (1038:1038:1038) (1202:1202:1202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (338:338:338) (401:401:401)) - (PORT datac (188:188:188) (222:222:222)) - (PORT datad (449:449:449) (516:516:516)) + (PORT dataa (486:486:486) (552:552:552)) + (PORT datab (1398:1398:1398) (1615:1615:1615)) + (PORT datac (833:833:833) (968:968:968)) + (PORT datad (647:647:647) (733:733:733)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -7981,40 +3592,67 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) (DELAY (ABSOLUTE - (PORT datac (1186:1186:1186) (1389:1389:1389)) - (PORT datad (952:952:952) (1132:1132:1132)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (684:684:684) (811:811:811)) + (PORT datad (1367:1367:1367) (1598:1598:1598)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (INSTANCE z80_\|decode_state_\|in_halt\~0) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (487:487:487) (554:554:554)) - (PORT datad (188:188:188) (219:219:219)) + (PORT dataa (630:630:630) (740:740:740)) + (PORT datab (225:225:225) (286:286:286)) + (PORT datad (232:232:232) (284:284:284)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (716:716:716)) + (PORT datab (695:695:695) (804:804:804)) + (PORT datad (162:162:162) (185:185:185)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (223:223:223)) - (PORT datab (315:315:315) (367:367:367)) - (PORT datac (314:314:314) (357:357:357)) - (PORT datad (428:428:428) (489:489:489)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (892:892:892)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (740:740:740) (868:868:868)) + (PORT datac (833:833:833) (968:968:968)) + (PORT datad (647:647:647) (733:733:733)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8022,31 +3660,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (INSTANCE z80_\|nM1_int\~2) (DELAY (ABSOLUTE - (PORT dataa (151:151:151) (195:195:195)) - (PORT datab (990:990:990) (1129:1129:1129)) - (PORT datac (137:137:137) (174:174:174)) - (PORT datad (121:121:121) (146:146:146)) + (PORT dataa (858:858:858) (1017:1017:1017)) + (PORT datac (983:983:983) (1155:1155:1155)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (824:824:824)) + (PORT datab (184:184:184) (224:224:224)) + (PORT datac (937:937:937) (1115:1115:1115)) + (PORT datad (783:783:783) (913:913:913)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) (DELAY (ABSOLUTE - (PORT dataa (526:526:526) (618:618:618)) - (PORT datab (535:535:535) (622:622:622)) - (PORT datac (1052:1052:1052) (1208:1208:1208)) - (PORT datad (342:342:342) (395:395:395)) + (PORT dataa (1001:1001:1001) (1176:1176:1176)) + (PORT datab (1093:1093:1093) (1266:1266:1266)) + (PORT datac (788:788:788) (921:921:921)) + (PORT datad (365:365:365) (425:425:425)) (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8054,30 +3704,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~3) (DELAY (ABSOLUTE - (PORT dataa (526:526:526) (635:635:635)) - (PORT datab (799:799:799) (966:966:966)) - (PORT datac (518:518:518) (621:621:621)) - (PORT datad (420:420:420) (484:484:484)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (426:426:426)) - (PORT datab (891:891:891) (1037:1037:1037)) - (PORT datac (725:725:725) (841:841:841)) - (PORT datad (629:629:629) (720:720:720)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (796:796:796) (919:919:919)) + (PORT datab (667:667:667) (773:773:773)) + (PORT datac (633:633:633) (737:737:737)) + (PORT datad (448:448:448) (517:517:517)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8086,11 +3720,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (INSTANCE z80_\|execute_\|ctl_im_we) (DELAY (ABSOLUTE - (PORT datac (1065:1065:1065) (1230:1230:1230)) - (PORT datad (1150:1150:1150) (1352:1352:1352)) + (PORT dataa (536:536:536) (630:630:630)) + (PORT datab (791:791:791) (934:934:934)) + (PORT datac (825:825:825) (938:938:938)) + (PORT datad (576:576:576) (679:679:679)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -8098,30 +3736,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (INSTANCE z80_\|pla_decode_\|Equal13\~1) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (153:153:153)) - (PORT datab (851:851:851) (1010:1010:1010)) - (PORT datac (1107:1107:1107) (1253:1253:1253)) - (PORT datad (109:109:109) (133:133:133)) + (PORT dataa (890:890:890) (1057:1057:1057)) + (PORT datab (871:871:871) (1050:1050:1050)) + (PORT datad (707:707:707) (844:844:844)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~2) (DELAY (ABSOLUTE - (PORT dataa (1089:1089:1089) (1254:1254:1254)) - (PORT datab (1170:1170:1170) (1377:1377:1377)) - (PORT datac (839:839:839) (994:994:994)) - (PORT datad (114:114:114) (138:138:138)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (1426:1426:1426) (1663:1663:1663)) + (PORT datab (810:810:810) (955:955:955)) + (PORT datac (715:715:715) (829:829:829)) + (PORT datad (760:760:760) (889:889:889)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8130,106 +3766,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (INSTANCE z80_\|pla_decode_\|Equal40\~0) (DELAY (ABSOLUTE - (PORT dataa (1101:1101:1101) (1285:1285:1285)) - (PORT datab (659:659:659) (763:763:763)) - (PORT datac (962:962:962) (1102:1102:1102)) - (PORT datad (522:522:522) (611:611:611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (939:939:939)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (750:750:750) (869:869:869)) - (PORT datad (334:334:334) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (728:728:728)) - (PORT datab (892:892:892) (1038:1038:1038)) - (PORT datac (489:489:489) (571:571:571)) - (PORT datad (498:498:498) (569:569:569)) + (PORT dataa (375:375:375) (456:456:456)) + (PORT datab (641:641:641) (773:773:773)) + (PORT datac (612:612:612) (737:737:737)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (INSTANCE z80_\|pla_decode_\|Equal21\~1) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (112:112:112) (134:134:134)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT datab (1173:1173:1173) (1380:1380:1380)) - (PORT datac (835:835:835) (989:989:989)) - (PORT datad (109:109:109) (134:134:134)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (811:811:811) (956:956:956)) - (PORT datac (1189:1189:1189) (1392:1392:1392)) - (PORT datad (954:954:954) (1134:1134:1134)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (611:611:611)) - (PORT datab (599:599:599) (689:689:689)) - (PORT datac (348:348:348) (410:410:410)) - (PORT datad (330:330:330) (388:388:388)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (503:503:503) (579:579:579)) + (PORT datab (621:621:621) (752:752:752)) + (PORT datac (952:952:952) (1101:1101:1101)) + (PORT datad (490:490:490) (566:566:566)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8238,264 +3796,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) + (INSTANCE z80_\|pla_decode_\|Equal40\~1) (DELAY (ABSOLUTE - (PORT dataa (311:311:311) (365:365:365)) - (PORT datab (489:489:489) (566:566:566)) - (PORT datac (306:306:306) (350:350:350)) - (PORT datad (901:901:901) (1007:1007:1007)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1446:1446:1446)) - (PORT datab (908:908:908) (1082:1082:1082)) - (PORT datac (467:467:467) (543:543:543)) - (PORT datad (481:481:481) (546:546:546)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (419:419:419)) - (PORT datab (475:475:475) (557:557:557)) - (PORT datac (952:952:952) (1085:1085:1085)) - (PORT datad (836:836:836) (967:967:967)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (755:755:755)) - (PORT datab (336:336:336) (391:391:391)) - (PORT datac (355:355:355) (421:421:421)) - (PORT datad (650:650:650) (741:741:741)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (808:808:808)) - (PORT datab (538:538:538) (632:632:632)) - (PORT datac (934:934:934) (1079:1079:1079)) - (PORT datad (777:777:777) (885:885:885)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (563:563:563) (663:663:663)) - (PORT datac (993:993:993) (1149:1149:1149)) - (PORT datad (776:776:776) (884:884:884)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (585:585:585)) - (PORT datab (522:522:522) (612:612:612)) - (PORT datad (483:483:483) (569:569:569)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (153:153:153)) - (PORT datab (543:543:543) (638:638:638)) - (PORT datac (435:435:435) (498:498:498)) - (PORT datad (763:763:763) (865:865:865)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1152:1152:1152)) - (PORT datab (935:935:935) (1116:1116:1116)) - (PORT datad (1050:1050:1050) (1202:1202:1202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (725:725:725)) - (PORT datac (974:974:974) (1145:1145:1145)) - (PORT datad (352:352:352) (415:415:415)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (735:735:735)) - (PORT datab (513:513:513) (603:603:603)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (301:301:301) (348:348:348)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1227:1227:1227)) - (PORT datab (854:854:854) (980:980:980)) - (PORT datac (931:931:931) (1095:1095:1095)) - (PORT datad (469:469:469) (543:543:543)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (911:911:911)) - (PORT datab (683:683:683) (792:792:792)) - (PORT datac (529:529:529) (624:624:624)) - (PORT datad (453:453:453) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (165:165:165)) - (PORT datab (1089:1089:1089) (1273:1273:1273)) - (PORT datac (760:760:760) (887:887:887)) - (PORT datad (850:850:850) (1006:1006:1006)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (917:917:917)) - (PORT datab (865:865:865) (1013:1013:1013)) - (PORT datac (1380:1380:1380) (1618:1618:1618)) - (PORT datad (697:697:697) (833:833:833)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (1074:1074:1074)) - (PORT datab (512:512:512) (591:591:591)) - (PORT datac (1420:1420:1420) (1615:1615:1615)) - (PORT datad (436:436:436) (520:520:520)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (920:920:920)) - (PORT datab (310:310:310) (359:359:359)) - (PORT datac (614:614:614) (711:711:711)) - (PORT datad (309:309:309) (354:354:354)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (790:790:790) (916:916:916)) + (PORT datac (114:114:114) (142:142:142)) + (PORT datad (552:552:552) (657:657:657)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -8504,693 +3810,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (INSTANCE z80_\|pla_decode_\|Equal39\~0) (DELAY (ABSOLUTE - (PORT dataa (785:785:785) (914:914:914)) - (PORT datab (798:798:798) (902:902:902)) - (PORT datac (528:528:528) (622:622:622)) - (PORT datad (777:777:777) (891:891:891)) + (PORT dataa (737:737:737) (869:869:869)) + (PORT datab (128:128:128) (162:162:162)) + (PORT datac (774:774:774) (894:894:894)) + (PORT datad (552:552:552) (657:657:657)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1167:1167:1167)) - (PORT datab (113:113:113) (141:141:141)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (490:490:490)) - (PORT datab (662:662:662) (757:757:757)) - (PORT datac (669:669:669) (769:769:769)) - (PORT datad (479:479:479) (562:562:562)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (563:563:563)) - (PORT datab (1082:1082:1082) (1267:1267:1267)) - (PORT datac (169:169:169) (200:200:200)) - (PORT datad (943:943:943) (1089:1089:1089)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1479:1479:1479)) - (PORT datab (780:780:780) (895:895:895)) - (PORT datac (779:779:779) (897:897:897)) - (PORT datad (1272:1272:1272) (1474:1474:1474)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (840:840:840)) - (PORT datab (665:665:665) (772:772:772)) - (PORT datac (367:367:367) (433:433:433)) - (PORT datad (644:644:644) (737:737:737)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (798:798:798) (928:928:928)) - (PORT datab (667:667:667) (774:774:774)) - (PORT datac (369:369:369) (436:436:436)) - (PORT datad (100:100:100) (122:122:122)) + (PORT dataa (1061:1061:1061) (1220:1220:1220)) + (PORT datab (688:688:688) (823:823:823)) + (PORT datad (509:509:509) (597:597:597)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (INSTANCE z80_\|pla_decode_\|Equal41\~0) (DELAY (ABSOLUTE - (PORT dataa (1204:1204:1204) (1413:1413:1413)) - (PORT datab (972:972:972) (1159:1159:1159)) - (PORT datac (655:655:655) (755:755:755)) - (PORT datad (1072:1072:1072) (1229:1229:1229)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (562:562:562)) - (PORT datab (511:511:511) (590:590:590)) - (PORT datac (296:296:296) (339:339:339)) - (PORT datad (598:598:598) (681:681:681)) + (PORT dataa (664:664:664) (794:794:794)) + (PORT datac (651:651:651) (771:771:771)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (INSTANCE z80_\|pla_decode_\|Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (486:486:486) (552:552:552)) - (PORT datab (581:581:581) (682:682:682)) - (PORT datac (640:640:640) (727:727:727)) - (PORT datad (347:347:347) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (414:414:414)) - (PORT datab (363:363:363) (428:428:428)) - (PORT datac (347:347:347) (412:412:412)) - (PORT datad (635:635:635) (715:715:715)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (408:408:408)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (639:639:639) (726:726:726)) - (PORT datad (296:296:296) (342:342:342)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (868:868:868)) - (PORT datab (847:847:847) (970:970:970)) - (PORT datac (829:829:829) (981:981:981)) - (PORT datad (1417:1417:1417) (1647:1647:1647)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (952:952:952)) - (PORT datab (840:840:840) (984:984:984)) - (PORT datac (901:901:901) (1032:1032:1032)) - (PORT datad (833:833:833) (985:985:985)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (796:796:796)) - (PORT datab (359:359:359) (427:427:427)) - (PORT datac (90:90:90) (113:113:113)) - (PORT datad (366:366:366) (428:428:428)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1306:1306:1306) (1526:1526:1526)) - (PORT datab (1252:1252:1252) (1442:1442:1442)) - (PORT datac (828:828:828) (979:979:979)) - (PORT datad (651:651:651) (751:751:751)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (1148:1148:1148)) - (PORT datab (957:957:957) (1143:1143:1143)) - (PORT datac (586:586:586) (693:693:693)) - (PORT datad (1016:1016:1016) (1186:1186:1186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (931:931:931)) - (PORT datab (628:628:628) (733:733:733)) - (PORT datac (438:438:438) (502:502:502)) - (PORT datad (839:839:839) (991:991:991)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (712:712:712)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (962:962:962) (1113:1113:1113)) - (PORT datad (842:842:842) (997:997:997)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~2) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (423:423:423)) - (PORT datac (1249:1249:1249) (1427:1427:1427)) - (PORT datad (947:947:947) (1081:1081:1081)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (405:405:405)) - (PORT datab (832:832:832) (956:956:956)) - (PORT datac (669:669:669) (773:773:773)) - (PORT datad (296:296:296) (340:340:340)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1218:1218:1218)) - (PORT datab (486:486:486) (551:551:551)) - (PORT datac (470:470:470) (547:547:547)) - (PORT datad (848:848:848) (957:957:957)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (702:702:702)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (670:670:670) (774:774:774)) - (PORT datad (508:508:508) (586:586:586)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (421:421:421)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (627:627:627) (724:724:724)) - (PORT datad (517:517:517) (603:603:603)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (805:805:805)) - (PORT datab (531:531:531) (633:633:633)) - (PORT datac (450:450:450) (523:523:523)) - (PORT datad (765:765:765) (915:915:915)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (562:562:562)) - (PORT datab (670:670:670) (781:781:781)) - (PORT datac (668:668:668) (780:780:780)) - (PORT datad (380:380:380) (446:446:446)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1382:1382:1382)) - (PORT datab (858:858:858) (995:995:995)) - (PORT datac (324:324:324) (381:381:381)) - (PORT datad (1179:1179:1179) (1377:1377:1377)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) - (DELAY - (ABSOLUTE - (PORT dataa (524:524:524) (611:611:611)) - (PORT datab (134:134:134) (169:169:169)) - (PORT datac (659:659:659) (763:763:763)) - (PORT datad (983:983:983) (1125:1125:1125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (166:166:166)) - (PORT datab (342:342:342) (401:401:401)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (650:650:650)) - (PORT datab (478:478:478) (553:553:553)) - (PORT datac (589:589:589) (702:702:702)) - (PORT datad (694:694:694) (826:826:826)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (555:555:555)) - (PORT datab (345:345:345) (406:406:406)) - (PORT datac (949:949:949) (1115:1115:1115)) - (PORT datad (628:628:628) (717:717:717)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (489:489:489)) - (PORT datab (682:682:682) (788:788:788)) - (PORT datac (738:738:738) (877:877:877)) - (PORT datad (481:481:481) (564:564:564)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (243:243:243)) - (PORT datab (677:677:677) (782:782:782)) - (PORT datac (519:519:519) (630:630:630)) - (PORT datad (1108:1108:1108) (1303:1303:1303)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (860:860:860)) - (PORT datab (912:912:912) (1075:1075:1075)) - (PORT datac (1238:1238:1238) (1424:1424:1424)) - (PORT datad (514:514:514) (595:595:595)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1471:1471:1471) (1746:1746:1746)) - (PORT datab (686:686:686) (803:803:803)) - (PORT datac (480:480:480) (561:561:561)) - (PORT datad (1222:1222:1222) (1442:1442:1442)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (818:818:818)) - (PORT datac (776:776:776) (885:885:885)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (404:404:404)) - (PORT datab (694:694:694) (803:803:803)) - (PORT datac (1062:1062:1062) (1260:1260:1260)) - (PORT datad (954:954:954) (1134:1134:1134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (775:775:775)) - (PORT datab (292:292:292) (340:340:340)) - (PORT datac (1165:1165:1165) (1358:1358:1358)) - (PORT datad (729:729:729) (880:880:880)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (363:363:363) (422:422:422)) - (PORT datac (494:494:494) (570:570:570)) - (PORT datad (159:159:159) (186:186:186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (1031:1031:1031)) - (PORT datab (858:858:858) (996:996:996)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (390:390:390) (463:463:463)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~1) - (DELAY - (ABSOLUTE - (PORT datac (1191:1191:1191) (1360:1360:1360)) - (PORT datad (784:784:784) (907:907:907)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (773:773:773)) - (PORT datab (781:781:781) (901:901:901)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (799:799:799) (923:923:923)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1255:1255:1255)) - (PORT datab (1170:1170:1170) (1378:1378:1378)) - (PORT datac (839:839:839) (993:993:993)) - (PORT datad (113:113:113) (138:138:138)) + (PORT dataa (920:920:920) (1065:1065:1065)) + (PORT datab (145:145:145) (188:188:188)) + (PORT datac (386:386:386) (472:472:472)) + (PORT datad (136:136:136) (167:167:167)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -9200,2860 +3868,378 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~0) (DELAY (ABSOLUTE - (PORT dataa (1020:1020:1020) (1170:1170:1170)) - (PORT datab (747:747:747) (904:904:904)) - (PORT datac (1165:1165:1165) (1358:1358:1358)) - (PORT datad (1180:1180:1180) (1379:1379:1379)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (301:301:301) (349:349:349)) + (PORT datab (377:377:377) (443:443:443)) + (PORT datac (1453:1453:1453) (1685:1685:1685)) + (PORT datad (743:743:743) (851:851:851)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT dataa (971:971:971) (1130:1130:1130)) - (PORT datab (508:508:508) (586:586:586)) + (PORT dataa (157:157:157) (208:208:208)) + (PORT datac (661:661:661) (783:783:783)) + (PORT datad (551:551:551) (648:648:648)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (156:156:156)) + (PORT datab (1670:1670:1670) (1933:1933:1933)) + (PORT datac (650:650:650) (754:754:754)) + (PORT datad (380:380:380) (447:447:447)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (759:759:759)) + (PORT datab (748:748:748) (885:885:885)) + (PORT datac (285:285:285) (322:322:322)) + (PORT datad (351:351:351) (412:412:412)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datac (941:941:941) (1121:1121:1121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~3) + (DELAY + (ABSOLUTE + (PORT datac (660:660:660) (776:776:776)) + (PORT datad (692:692:692) (813:813:813)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (792:792:792) (924:924:924)) + (PORT datad (670:670:670) (790:790:790)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (818:818:818) (955:955:955)) + (PORT datad (918:918:918) (1071:1071:1071)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (881:881:881) (1038:1038:1038)) + (PORT datac (771:771:771) (907:907:907)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (669:669:669)) + (PORT datab (656:656:656) (748:748:748)) + (PORT datac (788:788:788) (890:890:890)) + (PORT datad (1040:1040:1040) (1192:1192:1192)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (757:757:757)) + (PORT datab (470:470:470) (548:548:548)) + (PORT datac (1018:1018:1018) (1179:1179:1179)) + (PORT datad (723:723:723) (847:847:847)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (867:867:867)) + (PORT datab (375:375:375) (460:460:460)) + (PORT datad (361:361:361) (441:441:441)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datab (708:708:708) (820:820:820)) + (PORT datac (940:940:940) (1121:1121:1121)) + (PORT datad (1118:1118:1118) (1274:1274:1274)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (991:991:991)) + (PORT datab (478:478:478) (557:557:557)) + (PORT datac (842:842:842) (963:963:963)) + (PORT datad (990:990:990) (1128:1128:1128)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (612:612:612)) + (PORT datab (378:378:378) (445:445:445)) + (PORT datac (936:936:936) (1084:1084:1084)) + (PORT datad (285:285:285) (331:331:331)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (405:405:405)) + (PORT datab (310:310:310) (363:363:363)) + (PORT datac (333:333:333) (381:381:381)) + (PORT datad (121:121:121) (147:147:147)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (352:352:352)) + (PORT datab (341:341:341) (402:402:402)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (458:458:458) (522:522:522)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (671:671:671)) + (PORT datac (1138:1138:1138) (1318:1318:1318)) + (PORT datad (514:514:514) (603:603:603)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (513:513:513)) + (PORT datab (722:722:722) (862:862:862)) + (PORT datac (363:363:363) (430:430:430)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (676:676:676)) + (PORT datab (294:294:294) (349:349:349)) (PORT datac (90:90:90) (112:112:112)) - (PORT datad (337:337:337) (397:397:397)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (349:349:349) (408:408:408)) - (PORT datac (319:319:319) (376:376:376)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (648:648:648)) - (PORT datab (477:477:477) (552:552:552)) - (PORT datac (935:935:935) (1125:1125:1125)) - (PORT datad (1197:1197:1197) (1425:1425:1425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (704:704:704)) - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (473:473:473) (546:546:546)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (198:198:198)) - (PORT datab (134:134:134) (168:168:168)) - (PORT datac (648:648:648) (745:745:745)) - (PORT datad (137:137:137) (171:171:171)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (1038:1038:1038)) - (PORT datab (1113:1113:1113) (1275:1275:1275)) - (PORT datac (474:474:474) (557:557:557)) - (PORT datad (961:961:961) (1121:1121:1121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (809:809:809)) - (PORT datab (336:336:336) (392:392:392)) - (PORT datac (340:340:340) (402:402:402)) - (PORT datad (479:479:479) (552:552:552)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1212:1212:1212)) - (PORT datab (500:500:500) (593:593:593)) - (PORT datad (348:348:348) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (144:144:144)) - (PORT datab (610:610:610) (705:705:705)) - (PORT datac (164:164:164) (194:194:194)) - (PORT datad (369:369:369) (440:440:440)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (333:333:333) (391:391:391)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1211:1211:1211)) - (PORT datab (366:366:366) (418:418:418)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (488:488:488) (571:571:571)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (650:650:650)) - (PORT datab (1030:1030:1030) (1209:1209:1209)) - (PORT datac (541:541:541) (643:643:643)) - (PORT datad (694:694:694) (800:800:800)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1548:1548:1548)) - (PORT datab (1031:1031:1031) (1210:1210:1210)) - (PORT datac (476:476:476) (555:555:555)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (537:537:537)) - (PORT datab (798:798:798) (954:954:954)) - (PORT datac (364:364:364) (427:427:427)) - (PORT datad (368:368:368) (443:443:443)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (198:198:198)) - (PORT datab (133:133:133) (167:167:167)) - (PORT datac (136:136:136) (174:174:174)) - (PORT datad (667:667:667) (766:766:766)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (544:544:544)) - (PORT datab (338:338:338) (410:410:410)) - (PORT datac (474:474:474) (561:561:561)) - (PORT datad (356:356:356) (427:427:427)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (870:870:870) (1013:1013:1013)) - (PORT datac (1557:1557:1557) (1772:1772:1772)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (429:429:429)) - (PORT datab (190:190:190) (229:229:229)) - (PORT datac (94:94:94) (119:119:119)) - (PORT datad (489:489:489) (566:566:566)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (853:853:853)) - (PORT datab (555:555:555) (654:654:654)) - (PORT datac (531:531:531) (631:631:631)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (640:640:640) (702:702:702)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (852:852:852)) - (PORT datab (556:556:556) (655:655:655)) - (PORT datac (531:531:531) (630:630:630)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (948:948:948)) - (PORT datab (607:607:607) (718:718:718)) - (PORT datac (653:653:653) (752:752:752)) - (PORT datad (786:786:786) (910:910:910)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (400:400:400)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (755:755:755) (854:854:854)) - (PORT datad (695:695:695) (808:808:808)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (978:978:978)) - (PORT datab (987:987:987) (1134:1134:1134)) - (PORT datac (316:316:316) (360:360:360)) - (PORT datad (326:326:326) (381:381:381)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT datab (375:375:375) (440:440:440)) - (PORT datac (196:196:196) (235:235:235)) - (PORT datad (468:468:468) (542:542:542)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (581:581:581)) - (PORT datab (667:667:667) (769:769:769)) - (PORT datac (97:97:97) (123:123:123)) - (PORT datad (788:788:788) (915:915:915)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (550:550:550)) - (PORT datab (366:366:366) (449:449:449)) - (PORT datac (475:475:475) (557:557:557)) - (PORT datad (815:815:815) (934:934:934)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (392:392:392)) - (PORT datab (366:366:366) (450:450:450)) - (PORT datac (919:919:919) (1060:1060:1060)) - (PORT datad (192:192:192) (219:219:219)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (393:393:393)) - (PORT datab (935:935:935) (1083:1083:1083)) - (PORT datac (445:445:445) (510:510:510)) - (PORT datad (460:460:460) (522:522:522)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (391:391:391)) - (PORT datab (493:493:493) (578:578:578)) - (PORT datac (918:918:918) (1059:1059:1059)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (336:336:336) (396:396:396)) - (PORT datac (93:93:93) (115:115:115)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (905:905:905)) - (PORT datac (1123:1123:1123) (1343:1343:1343)) - (PORT datad (643:643:643) (740:740:740)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1164:1164:1164)) - (PORT datab (133:133:133) (167:167:167)) - (PORT datac (489:489:489) (565:565:565)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (516:516:516) (605:605:605)) - (PORT datac (602:602:602) (704:704:704)) - (PORT datad (333:333:333) (383:383:383)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (1100:1100:1100)) - (PORT datab (991:991:991) (1168:1168:1168)) - (PORT datac (730:730:730) (835:835:835)) - (PORT datad (354:354:354) (415:415:415)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (586:586:586)) - (PORT datab (572:572:572) (667:667:667)) - (PORT datac (847:847:847) (975:975:975)) - (PORT datad (674:674:674) (780:780:780)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (863:863:863) (992:992:992)) - (PORT datac (595:595:595) (683:683:683)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (582:582:582)) - (PORT datab (928:928:928) (1051:1051:1051)) - (PORT datac (722:722:722) (837:837:837)) - (PORT datad (877:877:877) (991:991:991)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (395:395:395)) - (PORT datac (676:676:676) (779:779:779)) - (PORT datad (490:490:490) (569:569:569)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (924:924:924)) - (PORT datab (346:346:346) (405:405:405)) - (PORT datac (91:91:91) (115:115:115)) - (PORT datad (512:512:512) (595:595:595)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT datac (315:315:315) (359:359:359)) - (PORT datad (473:473:473) (540:540:540)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (444:444:444) (505:505:505)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (184:184:184) (220:220:220)) - (PORT datac (314:314:314) (367:367:367)) - (PORT datad (333:333:333) (387:387:387)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (865:865:865)) - (PORT datab (885:885:885) (1031:1031:1031)) - (PORT datac (533:533:533) (631:631:631)) - (PORT datad (1192:1192:1192) (1344:1344:1344)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (541:541:541)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (530:530:530) (625:625:625)) - (PORT datad (625:625:625) (715:715:715)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (728:728:728)) - (PORT datab (482:482:482) (561:561:561)) - (PORT datac (526:526:526) (619:619:619)) - (PORT datad (103:103:103) (127:127:127)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (846:846:846)) - (PORT datab (329:329:329) (380:380:380)) - (PORT datac (99:99:99) (125:125:125)) - (PORT datad (519:519:519) (624:624:624)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT datab (671:671:671) (781:781:781)) - (PORT datac (520:520:520) (594:594:594)) - (PORT datad (513:513:513) (592:592:592)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (754:754:754)) - (PORT datab (486:486:486) (563:563:563)) - (PORT datac (619:619:619) (708:708:708)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (733:733:733) (832:832:832)) - (PORT datad (629:629:629) (721:721:721)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (410:410:410)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (441:441:441) (498:498:498)) - (PORT datad (453:453:453) (521:521:521)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (408:408:408)) - (PORT datab (540:540:540) (652:652:652)) - (PORT datac (584:584:584) (660:660:660)) - (PORT datad (1008:1008:1008) (1185:1185:1185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (404:404:404)) - (PORT datab (515:515:515) (599:599:599)) - (PORT datac (192:192:192) (232:232:232)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (320:320:320) (373:373:373)) - (PORT datac (482:482:482) (545:545:545)) - (PORT datad (298:298:298) (343:343:343)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (854:854:854)) - (PORT datab (538:538:538) (627:627:627)) - (PORT datac (534:534:534) (632:632:632)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (842:842:842)) - (PORT datab (535:535:535) (624:624:624)) - (PORT datac (541:541:541) (639:639:639)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (278:278:278) (297:297:297)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (618:618:618)) - (PORT datab (1462:1462:1462) (1681:1681:1681)) - (PORT datac (102:102:102) (130:130:130)) - (PORT datad (769:769:769) (880:880:880)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1299:1299:1299)) - (PORT datab (816:816:816) (963:963:963)) - (PORT datad (633:633:633) (732:732:732)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (1129:1129:1129) (1094:1094:1094)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (1027:1027:1027)) - (PORT datab (956:956:956) (1091:1091:1091)) - (PORT datac (660:660:660) (762:762:762)) - (PORT datad (684:684:684) (790:790:790)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (768:768:768)) - (PORT datab (680:680:680) (785:785:785)) - (PORT datac (924:924:924) (1056:1056:1056)) - (PORT datad (309:309:309) (353:353:353)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (947:947:947)) - (PORT datab (538:538:538) (628:628:628)) - (PORT datac (656:656:656) (749:749:749)) - (PORT datad (664:664:664) (769:769:769)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (394:394:394)) - (PORT datab (1052:1052:1052) (1211:1211:1211)) - (PORT datac (583:583:583) (687:687:687)) - (PORT datad (1479:1479:1479) (1682:1682:1682)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (786:786:786)) - (PORT datab (702:702:702) (815:815:815)) - (PORT datac (464:464:464) (552:552:552)) - (PORT datad (469:469:469) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (575:575:575)) - (PORT datac (338:338:338) (400:400:400)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (121:121:121) (156:156:156)) - (PORT datac (1563:1563:1563) (1836:1836:1836)) - (PORT datad (115:115:115) (138:138:138)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (1002:1002:1002)) - (PORT datab (833:833:833) (963:963:963)) - (PORT datac (832:832:832) (947:947:947)) - (PORT datad (612:612:612) (699:699:699)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (804:804:804)) - (PORT datab (530:530:530) (632:632:632)) - (PORT datac (1107:1107:1107) (1253:1253:1253)) - (PORT datad (767:767:767) (917:917:917)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (917:917:917)) - (PORT datab (730:730:730) (864:864:864)) - (PORT datac (526:526:526) (621:621:621)) - (PORT datad (847:847:847) (1002:1002:1002)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (617:617:617)) - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (326:326:326) (383:383:383)) - (PORT datad (686:686:686) (801:801:801)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (991:991:991)) - (PORT datab (478:478:478) (551:551:551)) - (PORT datac (792:792:792) (917:917:917)) - (PORT datad (378:378:378) (444:444:444)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (524:524:524) (608:608:608)) - (PORT datac (334:334:334) (390:390:390)) - (PORT datad (315:315:315) (356:356:356)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (439:439:439)) - (PORT datab (597:597:597) (690:690:690)) - (PORT datac (1111:1111:1111) (1284:1284:1284)) - (PORT datad (452:452:452) (516:516:516)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (600:600:600)) - (PORT datab (291:291:291) (342:342:342)) - (PORT datac (521:521:521) (610:610:610)) - (PORT datad (513:513:513) (589:589:589)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (216:216:216)) - (PORT datab (134:134:134) (164:164:164)) - (PORT datac (521:521:521) (610:610:610)) - (PORT datad (512:512:512) (589:589:589)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (652:652:652)) - (PORT datab (431:431:431) (534:534:534)) - (PORT datac (409:409:409) (501:501:501)) - (PORT datad (347:347:347) (410:410:410)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (777:777:777)) - (PORT datab (177:177:177) (215:215:215)) - (PORT datac (1069:1069:1069) (1278:1278:1278)) - (PORT datad (333:333:333) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (211:211:211) (254:254:254)) - (PORT datac (534:534:534) (624:624:624)) - (PORT datad (440:440:440) (504:504:504)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (676:676:676) (779:779:779)) - (PORT datad (167:167:167) (197:197:197)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (1029:1029:1029)) - (PORT datab (656:656:656) (763:763:763)) - (PORT datac (739:739:739) (878:878:878)) - (PORT datad (389:389:389) (462:462:462)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (152:152:152)) - (PORT datab (328:328:328) (383:383:383)) - (PORT datac (623:623:623) (714:714:714)) - (PORT datad (389:389:389) (462:462:462)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (489:489:489)) - (PORT datab (365:365:365) (435:435:435)) - (PORT datac (351:351:351) (409:409:409)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (632:632:632) (722:722:722)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (378:378:378)) - (PORT datab (635:635:635) (734:734:734)) - (PORT datac (780:780:780) (901:901:901)) - (PORT datad (462:462:462) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (128:128:128) (164:164:164)) - (PORT datab (539:539:539) (632:632:632)) - (PORT datac (362:362:362) (420:420:420)) - (PORT datad (162:162:162) (187:187:187)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT datab (2033:2033:2033) (2335:2335:2335)) - (PORT datad (842:842:842) (984:984:984)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (379:379:379)) - (PORT datab (638:638:638) (734:734:734)) - (PORT datac (335:335:335) (389:389:389)) - (PORT datad (449:449:449) (517:517:517)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1217:1217:1217)) - (PORT datab (505:505:505) (592:592:592)) - (PORT datac (492:492:492) (551:551:551)) - (PORT datad (471:471:471) (544:544:544)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datab (354:354:354) (423:423:423)) - (PORT datad (609:609:609) (704:704:704)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT datab (473:473:473) (553:553:553)) - (PORT datac (599:599:599) (710:710:710)) - (PORT datad (824:824:824) (965:965:965)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (223:223:223)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (284:284:284) (327:327:327)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1125:1125:1125)) - (PORT datab (681:681:681) (810:810:810)) - (PORT datac (743:743:743) (849:849:849)) - (PORT datad (315:315:315) (366:366:366)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1447:1447:1447)) - (PORT datab (485:485:485) (562:562:562)) - (PORT datac (888:888:888) (1060:1060:1060)) - (PORT datad (951:951:951) (1086:1086:1086)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (586:586:586)) - (PORT datab (733:733:733) (840:840:840)) - (PORT datac (486:486:486) (566:566:566)) - (PORT datad (780:780:780) (900:900:900)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (436:436:436)) - (PORT datab (812:812:812) (932:932:932)) - (PORT datac (465:465:465) (530:530:530)) - (PORT datad (372:372:372) (437:437:437)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (828:828:828)) - (PORT datab (505:505:505) (589:589:589)) - (PORT datac (770:770:770) (887:887:887)) - (PORT datad (997:997:997) (1134:1134:1134)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (472:472:472) (537:537:537)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (351:351:351) (406:406:406)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (600:600:600)) - (PORT datab (553:553:553) (640:640:640)) - (PORT datac (500:500:500) (572:572:572)) - (PORT datad (489:489:489) (563:563:563)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1151:1151:1151)) - (PORT datab (838:838:838) (984:984:984)) - (PORT datac (598:598:598) (710:710:710)) - (PORT datad (459:459:459) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (750:750:750)) - (PORT datab (472:472:472) (551:551:551)) - (PORT datac (598:598:598) (710:710:710)) - (PORT datad (819:819:819) (959:959:959)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1126:1126:1126)) - (PORT datab (1067:1067:1067) (1220:1220:1220)) - (PORT datac (845:845:845) (962:962:962)) - (PORT datad (596:596:596) (698:698:698)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (127:127:127) (163:163:163)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datac (571:571:571) (667:667:667)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (1127:1127:1127)) - (PORT datac (695:695:695) (833:833:833)) - (PORT datad (615:615:615) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (891:891:891)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (436:436:436) (495:495:495)) - (PORT datad (464:464:464) (540:540:540)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (760:760:760)) - (PORT datac (497:497:497) (580:580:580)) - (PORT datad (474:474:474) (546:546:546)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (865:865:865)) - (PORT datab (509:509:509) (586:586:586)) - (PORT datac (826:826:826) (977:977:977)) - (PORT datad (663:663:663) (769:769:769)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (592:592:592)) - (PORT datab (913:913:913) (1076:1076:1076)) - (PORT datac (1237:1237:1237) (1423:1423:1423)) - (PORT datad (904:904:904) (1057:1057:1057)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (665:665:665) (771:771:771)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1123:1123:1123)) - (PORT datab (184:184:184) (223:223:223)) - (PORT datac (690:690:690) (828:828:828)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (381:381:381)) - (PORT datab (526:526:526) (621:621:621)) - (PORT datac (361:361:361) (426:426:426)) - (PORT datad (309:309:309) (362:362:362)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (556:556:556)) - (PORT datab (109:109:109) (141:141:141)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (895:895:895) (1043:1043:1043)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (382:382:382)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (345:345:345) (404:404:404)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (345:345:345) (413:413:413)) - (PORT datac (450:450:450) (514:514:514)) - (PORT datad (950:950:950) (1084:1084:1084)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (225:225:225)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (676:676:676) (780:780:780)) - (PORT datad (583:583:583) (664:664:664)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (911:911:911)) - (PORT datab (631:631:631) (732:732:732)) - (PORT datad (914:914:914) (1081:1081:1081)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (1003:1003:1003)) - (PORT datab (903:903:903) (1068:1068:1068)) - (PORT datac (482:482:482) (564:564:564)) - (PORT datad (750:750:750) (871:871:871)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (131:131:131) (166:166:166)) - (PORT datac (820:820:820) (941:941:941)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (891:891:891)) - (PORT datab (579:579:579) (661:661:661)) - (PORT datac (838:838:838) (963:963:963)) - (PORT datad (336:336:336) (388:388:388)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (383:383:383)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (326:326:326) (388:388:388)) - (PORT datad (329:329:329) (380:380:380)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (804:804:804)) - (PORT datab (1376:1376:1376) (1582:1582:1582)) - (PORT datac (933:933:933) (1078:1078:1078)) - (PORT datad (551:551:551) (642:642:642)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (655:655:655)) - (PORT datab (425:425:425) (519:519:519)) - (PORT datac (328:328:328) (388:388:388)) - (PORT datad (491:491:491) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (732:732:732)) - (PORT datab (188:188:188) (225:225:225)) - (PORT datac (517:517:517) (601:601:601)) - (PORT datad (460:460:460) (526:526:526)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (127:127:127) (159:159:159)) - (PORT datac (106:106:106) (137:137:137)) - (PORT datad (471:471:471) (548:548:548)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (992:992:992)) - (PORT datab (570:570:570) (673:673:673)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (103:103:103) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (890:890:890)) - (PORT datab (597:597:597) (681:681:681)) - (PORT datac (755:755:755) (873:873:873)) - (PORT datad (175:175:175) (206:206:206)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (583:583:583)) - (PORT datab (378:378:378) (461:461:461)) - (PORT datac (362:362:362) (441:441:441)) - (PORT datad (314:314:314) (362:362:362)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (285:285:285)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datac (798:798:798) (958:958:958)) - (PORT datad (661:661:661) (777:777:777)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (1081:1081:1081)) - (PORT datab (1092:1092:1092) (1283:1283:1283)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (1458:1458:1458) (1677:1677:1677)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1415:1415:1415)) - (PORT datab (1414:1414:1414) (1657:1657:1657)) - (PORT datac (1250:1250:1250) (1429:1429:1429)) - (PORT datad (921:921:921) (1056:1056:1056)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (788:788:788)) - (PORT datab (482:482:482) (558:558:558)) - (PORT datac (1253:1253:1253) (1431:1431:1431)) - (PORT datad (1397:1397:1397) (1634:1634:1634)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (1151:1151:1151) (1305:1305:1305)) - (PORT datad (106:106:106) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (528:528:528)) - (PORT datab (454:454:454) (525:525:525)) - (PORT datac (875:875:875) (1046:1046:1046)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (229:229:229)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (671:671:671) (775:775:775)) - (PORT datad (478:478:478) (552:552:552)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) - (DELAY - (ABSOLUTE - (PORT datac (455:455:455) (532:532:532)) - (PORT datad (753:753:753) (862:862:862)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (936:936:936)) - (PORT datab (657:657:657) (768:768:768)) - (PORT datac (985:985:985) (1153:1153:1153)) - (PORT datad (811:811:811) (940:940:940)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (575:575:575)) - (PORT datab (355:355:355) (416:416:416)) - (PORT datac (1157:1157:1157) (1380:1380:1380)) - (PORT datad (781:781:781) (882:882:882)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (507:507:507)) - (PORT datab (484:484:484) (559:559:559)) - (PORT datad (654:654:654) (755:755:755)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (926:926:926) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (509:509:509)) - (PORT datab (120:120:120) (155:155:155)) - (PORT datac (419:419:419) (479:479:479)) - (PORT datad (122:122:122) (160:160:160)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (726:726:726)) - (PORT datab (511:511:511) (600:600:600)) - (PORT datac (1068:1068:1068) (1277:1277:1277)) - (PORT datad (661:661:661) (773:773:773)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (578:578:578)) - (PORT datab (238:238:238) (299:299:299)) - (PORT datac (220:220:220) (277:277:277)) - (PORT datad (550:550:550) (641:641:641)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1189:1189:1189)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (380:380:380) (441:441:441)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (712:712:712)) - (PORT datab (690:690:690) (785:785:785)) - (PORT datac (678:678:678) (782:782:782)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (463:463:463)) - (PORT datab (833:833:833) (958:958:958)) - (PORT datac (1099:1099:1099) (1263:1263:1263)) - (PORT datad (817:817:817) (923:923:923)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (564:564:564)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (161:161:161) (189:189:189)) - (PORT datad (325:325:325) (370:370:370)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1628:1628:1628) (1913:1913:1913)) - (PORT datab (576:576:576) (658:658:658)) - (PORT datac (841:841:841) (966:966:966)) - (PORT datad (715:715:715) (841:841:841)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (551:551:551)) - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (892:892:892) (1040:1040:1040)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (792:792:792)) - (PORT datab (772:772:772) (887:887:887)) - (PORT datac (674:674:674) (768:768:768)) - (PORT datad (802:802:802) (912:912:912)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (806:806:806)) - (PORT datab (486:486:486) (585:585:585)) - (PORT datac (966:966:966) (1120:1120:1120)) - (PORT datad (466:466:466) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (484:484:484)) - (PORT datac (781:781:781) (935:935:935)) - (PORT datad (368:368:368) (444:444:444)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (711:711:711)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (770:770:770) (887:887:887)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (450:450:450)) - (PORT datab (354:354:354) (425:425:425)) - (PORT datac (682:682:682) (791:791:791)) - (PORT datad (613:613:613) (700:700:700)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (721:721:721)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (95:95:95) (118:118:118)) (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1452:1452:1452)) - (PORT datac (883:883:883) (1055:1055:1055)) - (PORT datad (948:948:948) (1082:1082:1082)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (922:922:922)) - (PORT datab (593:593:593) (683:683:683)) - (PORT datac (164:164:164) (197:197:197)) - (PORT datad (332:332:332) (386:386:386)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (703:703:703) (847:847:847)) - (PORT datab (536:536:536) (645:645:645)) - (PORT datac (476:476:476) (554:554:554)) - (PORT datad (341:341:341) (387:387:387)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (401:401:401)) - (PORT datab (818:818:818) (954:954:954)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (696:696:696) (810:810:810)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (669:669:669)) - (PORT datab (478:478:478) (556:556:556)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (495:495:495) (569:569:569)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (123:123:123) (159:159:159)) - (PORT datac (463:463:463) (529:529:529)) - (PORT datad (114:114:114) (136:136:136)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1503:1503:1503)) - (PORT datab (1579:1579:1579) (1859:1859:1859)) - (PORT datad (473:473:473) (551:551:551)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (407:407:407)) - (PORT datab (344:344:344) (405:405:405)) - (PORT datac (340:340:340) (383:383:383)) - (PORT datad (626:626:626) (725:725:725)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (403:403:403)) - (PORT datab (338:338:338) (397:397:397)) - (PORT datac (348:348:348) (412:412:412)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (1002:1002:1002)) - (PORT datab (527:527:527) (613:613:613)) - (PORT datac (724:724:724) (841:841:841)) - (PORT datad (663:663:663) (769:769:769)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (585:585:585)) - (PORT datab (733:733:733) (841:841:841)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (781:781:781) (900:900:900)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (509:509:509) (586:586:586)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (562:562:562)) - (PORT datab (800:800:800) (967:967:967)) - (PORT datac (290:290:290) (332:332:332)) - (PORT datad (521:521:521) (621:621:621)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (735:735:735) (847:847:847)) - (PORT datab (1053:1053:1053) (1256:1256:1256)) - (PORT datac (1069:1069:1069) (1269:1269:1269)) - (PORT datad (582:582:582) (662:662:662)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) (DELAY (ABSOLUTE - (PORT dataa (128:128:128) (163:163:163)) - (PORT datab (487:487:487) (572:572:572)) - (PORT datac (967:967:967) (1120:1120:1120)) - (PORT datad (346:346:346) (398:398:398)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (611:611:611)) - (PORT datab (793:793:793) (916:916:916)) - (PORT datac (1014:1014:1014) (1146:1146:1146)) - (PORT datad (482:482:482) (562:562:562)) + (PORT dataa (1286:1286:1286) (1491:1491:1491)) + (PORT datab (746:746:746) (883:883:883)) + (PORT datac (639:639:639) (741:741:741)) + (PORT datad (1067:1067:1067) (1280:1280:1280)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (513:513:513) (592:592:592)) - (PORT datac (737:737:737) (857:857:857)) - (PORT datad (441:441:441) (496:496:496)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (623:623:623)) - (PORT datab (912:912:912) (1075:1075:1075)) - (PORT datac (1238:1238:1238) (1424:1424:1424)) - (PORT datad (902:902:902) (1055:1055:1055)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (630:630:630)) - (PORT datab (673:673:673) (787:787:787)) - (PORT datac (438:438:438) (504:504:504)) - (PORT datad (319:319:319) (361:361:361)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (661:661:661) (758:758:758)) - (PORT datac (293:293:293) (338:338:338)) - (PORT datad (343:343:343) (401:401:401)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (705:705:705)) - (PORT datab (831:831:831) (943:943:943)) - (PORT datac (560:560:560) (645:645:645)) - (PORT datad (803:803:803) (920:920:920)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (180:180:180) (220:220:220)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (466:466:466) (535:535:535)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (122:122:122) (157:157:157)) - (PORT datac (665:665:665) (759:759:759)) - (PORT datad (345:345:345) (408:408:408)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (541:541:541)) - (PORT datab (964:964:964) (1116:1116:1116)) - (PORT datad (1036:1036:1036) (1215:1215:1215)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (509:509:509)) - (PORT datab (483:483:483) (558:558:558)) - (PORT datad (653:653:653) (754:754:754)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (922:922:922)) + (PORT clk (915:915:915) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (926:926:926) (909:909:909)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (507:507:507)) - (PORT datab (134:134:134) (183:183:183)) - (PORT datac (417:417:417) (477:477:477)) - (PORT datad (106:106:106) (129:129:129)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT dataa (128:128:128) (163:163:163)) - (PORT datac (760:760:760) (874:874:874)) - (PORT datad (1044:1044:1044) (1189:1189:1189)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT dataa (582:582:582) (699:699:699)) + (PORT datac (946:946:946) (1128:1128:1128)) + (PORT datad (567:567:567) (669:669:669)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12061,88 +4247,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) (DELAY (ABSOLUTE - (PORT dataa (125:125:125) (158:158:158)) - (PORT datac (756:756:756) (870:870:870)) - (PORT datad (1046:1046:1046) (1191:1191:1191)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (724:724:724) (876:876:876)) + (PORT datab (486:486:486) (566:566:566)) + (PORT datac (235:235:235) (296:296:296)) + (PORT datad (650:650:650) (745:745:745)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1145:1145:1145)) + (PORT datab (385:385:385) (471:471:471)) + (PORT datac (513:513:513) (610:610:610)) + (PORT datad (1478:1478:1478) (1703:1703:1703)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (528:528:528) (590:590:590)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (INSTANCE z80_\|execute_\|ctl_mWrite\~19) (DELAY (ABSOLUTE - (PORT datab (965:965:965) (1118:1118:1118)) - (PORT datac (454:454:454) (522:522:522)) - (PORT datad (1033:1033:1033) (1212:1212:1212)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (533:533:533) (595:595:595)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (139:139:139) (184:184:184)) - (PORT datab (589:589:589) (679:679:679)) - (PORT datad (189:189:189) (236:236:236)) + (PORT dataa (709:709:709) (848:848:848)) + (PORT datab (720:720:720) (851:851:851)) + (PORT datac (998:998:998) (1197:1197:1197)) + (PORT datad (206:206:206) (244:244:244)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (922:922:922)) - (PORT datab (607:607:607) (700:700:700)) - (PORT datac (524:524:524) (617:617:617)) - (PORT datad (310:310:310) (354:354:354)) + (PORT dataa (867:867:867) (1026:1026:1026)) + (PORT datab (881:881:881) (1045:1045:1045)) + (PORT datac (444:444:444) (509:509:509)) + (PORT datad (573:573:573) (660:660:660)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -12152,13 +4311,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~8) (DELAY (ABSOLUTE - (PORT dataa (205:205:205) (251:251:251)) - (PORT datab (118:118:118) (147:147:147)) - (PORT datac (109:109:109) (138:138:138)) - (PORT datad (714:714:714) (802:802:802)) + (PORT dataa (784:784:784) (883:883:883)) + (PORT datab (465:465:465) (531:531:531)) + (PORT datac (403:403:403) (488:488:488)) + (PORT datad (691:691:691) (812:812:812)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (423:423:423)) + (PORT datab (465:465:465) (531:531:531)) + (PORT datac (786:786:786) (902:902:902)) + (PORT datad (102:102:102) (118:118:118)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12168,15 +4343,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (INSTANCE z80_\|pla_decode_\|Equal6\~1) (DELAY (ABSOLUTE - (PORT dataa (1158:1158:1158) (1388:1388:1388)) - (PORT datab (764:764:764) (927:927:927)) - (PORT datac (613:613:613) (706:706:706)) - (PORT datad (475:475:475) (540:540:540)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (975:975:975) (1160:1160:1160)) + (PORT datab (968:968:968) (1123:1123:1123)) + (PORT datac (559:559:559) (670:670:670)) + (PORT datad (450:450:450) (523:523:523)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12184,64 +4359,40 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (INSTANCE z80_\|pla_decode_\|Equal9\~0) (DELAY (ABSOLUTE - (PORT dataa (528:528:528) (614:614:614)) - (PORT datab (599:599:599) (688:688:688)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (477:477:477) (545:545:545)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datac (497:497:497) (590:590:590)) + (PORT datad (1051:1051:1051) (1251:1251:1251)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (INSTANCE z80_\|pla_decode_\|Equal9\~1) (DELAY (ABSOLUTE - (PORT dataa (630:630:630) (732:732:732)) - (PORT datab (536:536:536) (635:635:635)) - (PORT datac (668:668:668) (789:789:789)) - (PORT datad (1614:1614:1614) (1855:1855:1855)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (756:756:756) (870:870:870)) - (PORT datad (347:347:347) (399:399:399)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (309:309:309) (359:359:359)) + (PORT datab (1664:1664:1664) (1925:1925:1925)) + (PORT datac (759:759:759) (861:861:861)) + (PORT datad (383:383:383) (450:450:450)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (INSTANCE z80_\|execute_\|ctl_mRead\~9) (DELAY (ABSOLUTE - (PORT dataa (1312:1312:1312) (1556:1556:1556)) - (PORT datab (969:969:969) (1134:1134:1134)) - (PORT datac (799:799:799) (924:924:924)) - (PORT datad (605:605:605) (689:689:689)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (985:985:985) (1151:1151:1151)) + (PORT datad (897:897:897) (1065:1065:1065)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12251,10 +4402,10 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) (DELAY (ABSOLUTE - (PORT dataa (607:607:607) (702:702:702)) - (PORT datab (671:671:671) (774:774:774)) - (PORT datac (663:663:663) (757:757:757)) - (PORT datad (1231:1231:1231) (1401:1401:1401)) + (PORT dataa (368:368:368) (436:436:436)) + (PORT datab (307:307:307) (354:354:354)) + (PORT datac (474:474:474) (549:549:549)) + (PORT datad (791:791:791) (900:900:900)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -12267,12 +4418,136 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) (DELAY (ABSOLUTE - (PORT dataa (630:630:630) (731:731:731)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (461:461:461) (537:537:537)) - (PORT datad (1107:1107:1107) (1244:1244:1244)) + (PORT dataa (715:715:715) (829:829:829)) + (PORT datab (504:504:504) (582:582:582)) + (PORT datac (460:460:460) (532:532:532)) + (PORT datad (89:89:89) (106:106:106)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (880:880:880)) + (PORT datab (485:485:485) (565:565:565)) + (PORT datac (238:238:238) (299:299:299)) + (PORT datad (651:651:651) (747:747:747)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (673:673:673)) + (PORT datac (399:399:399) (477:477:477)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1426:1426:1426)) + (PORT datab (877:877:877) (1040:1040:1040)) + (PORT datac (1253:1253:1253) (1463:1463:1463)) + (PORT datad (568:568:568) (670:670:670)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (873:873:873)) + (PORT datab (156:156:156) (210:210:210)) + (PORT datac (638:638:638) (736:736:736)) + (PORT datad (649:649:649) (744:744:744)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (731:731:731)) + (PORT datab (797:797:797) (940:940:940)) + (PORT datac (929:929:929) (1074:1074:1074)) + (PORT datad (201:201:201) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (629:629:629)) + (PORT datab (884:884:884) (1022:1022:1022)) + (PORT datac (477:477:477) (553:553:553)) + (PORT datad (509:509:509) (600:600:600)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (847:847:847)) + (PORT datab (723:723:723) (855:855:855)) + (PORT datac (1001:1001:1001) (1200:1200:1200)) + (PORT datad (204:204:204) (242:242:242)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (862:862:862)) + (PORT datab (903:903:903) (1077:1077:1077)) + (PORT datac (801:801:801) (920:920:920)) + (PORT datad (104:104:104) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12283,12 +4558,52 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (801:801:801)) - (PORT datab (749:749:749) (853:853:853)) - (PORT datac (496:496:496) (569:569:569)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (195:195:195) (235:235:235)) + (PORT datab (323:323:323) (367:367:367)) + (PORT datac (358:358:358) (424:424:424)) + (PORT datad (485:485:485) (558:558:558)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT datab (408:408:408) (496:496:496)) + (PORT datad (202:202:202) (239:239:239)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (818:818:818)) + (PORT datab (704:704:704) (817:817:817)) + (PORT datad (684:684:684) (798:798:798)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (772:772:772)) + (PORT datac (1221:1221:1221) (1439:1439:1439)) + (PORT datad (970:970:970) (1118:1118:1118)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12296,73 +4611,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (INSTANCE z80_\|pla_decode_\|Equal12\~1) (DELAY (ABSOLUTE - (PORT dataa (698:698:698) (821:821:821)) - (PORT datad (483:483:483) (561:561:561)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (597:597:597)) - (PORT datab (350:350:350) (410:410:410)) - (PORT datac (1078:1078:1078) (1250:1250:1250)) - (PORT datad (923:923:923) (1093:1093:1093)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (993:993:993) (1139:1139:1139)) + (PORT datab (695:695:695) (820:820:820)) + (PORT datad (966:966:966) (1107:1107:1107)) + (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (INSTANCE z80_\|pla_decode_\|Equal25\~0) (DELAY (ABSOLUTE - (PORT dataa (500:500:500) (580:580:580)) - (PORT datab (527:527:527) (618:618:618)) - (PORT datac (759:759:759) (862:862:862)) - (PORT datad (319:319:319) (369:369:369)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (994:994:994) (1140:1140:1140)) + (PORT datab (684:684:684) (801:801:801)) + (PORT datac (1149:1149:1149) (1345:1345:1345)) + (PORT datad (968:968:968) (1109:1109:1109)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) + (INSTANCE z80_\|execute_\|ctl_mRead\~20) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (760:760:760)) - (PORT datab (351:351:351) (418:418:418)) - (PORT datac (483:483:483) (561:561:561)) - (PORT datad (471:471:471) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (169:169:169)) - (PORT datab (512:512:512) (602:602:602)) - (PORT datac (821:821:821) (939:939:939)) - (PORT datad (454:454:454) (514:514:514)) + (PORT dataa (966:966:966) (1113:1113:1113)) + (PORT datab (133:133:133) (163:163:163)) + (PORT datac (105:105:105) (129:129:129)) + (PORT datad (108:108:108) (127:127:127)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -12372,13 +4657,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) + (INSTANCE z80_\|execute_\|ctl_mRead\~12) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (311:311:311) (357:357:357)) + (PORT dataa (181:181:181) (219:219:219)) + (PORT datab (987:987:987) (1133:1133:1133)) + (PORT datac (977:977:977) (1116:1116:1116)) + (PORT datad (686:686:686) (800:800:800)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12388,13 +4673,277 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (INSTANCE z80_\|execute_\|ctl_mRead\~8) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (431:431:431)) - (PORT datab (886:886:886) (1032:1032:1032)) - (PORT datac (725:725:725) (841:841:841)) - (PORT datad (497:497:497) (568:568:568)) + (PORT dataa (993:993:993) (1138:1138:1138)) + (PORT datab (351:351:351) (406:406:406)) + (PORT datac (1143:1143:1143) (1338:1338:1338)) + (PORT datad (965:965:965) (1106:1106:1106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (819:819:819)) + (PORT datab (703:703:703) (816:816:816)) + (PORT datad (685:685:685) (799:799:799)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (514:514:514) (590:590:590)) + (PORT datac (431:431:431) (484:484:484)) + (PORT datad (697:697:697) (806:806:806)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (252:252:252)) + (PORT datab (194:194:194) (229:229:229)) + (PORT datac (296:296:296) (342:342:342)) + (PORT datad (533:533:533) (624:624:624)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (380:380:380)) + (PORT datab (1666:1666:1666) (1927:1927:1927)) + (PORT datac (516:516:516) (606:606:606)) + (PORT datad (381:381:381) (449:449:449)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (769:769:769)) + (PORT datab (1663:1663:1663) (1924:1924:1924)) + (PORT datac (295:295:295) (354:354:354)) + (PORT datad (384:384:384) (451:451:451)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (848:848:848)) + (PORT datab (722:722:722) (854:854:854)) + (PORT datac (1000:1000:1000) (1199:1199:1199)) + (PORT datad (177:177:177) (208:208:208)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (557:557:557)) + (PORT datab (144:144:144) (188:188:188)) + (PORT datac (386:386:386) (473:473:473)) + (PORT datad (141:141:141) (174:174:174)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1064:1064:1064)) + (PORT datab (145:145:145) (189:189:189)) + (PORT datac (387:387:387) (473:473:473)) + (PORT datad (141:141:141) (175:175:175)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (460:460:460)) + (PORT datab (146:146:146) (190:190:190)) + (PORT datac (387:387:387) (473:473:473)) + (PORT datad (143:143:143) (176:176:176)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (551:551:551)) + (PORT datab (465:465:465) (547:547:547)) + (PORT datac (342:342:342) (398:398:398)) + (PORT datad (362:362:362) (421:421:421)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (357:357:357)) + (PORT datab (1667:1667:1667) (1928:1928:1928)) + (PORT datac (760:760:760) (862:862:862)) + (PORT datad (381:381:381) (448:448:448)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (1029:1029:1029)) + (PORT datab (773:773:773) (888:888:888)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (737:737:737) (827:827:827)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1409:1409:1409)) + (PORT datad (541:541:541) (645:645:645)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1171:1171:1171)) + (PORT datab (693:693:693) (804:804:804)) + (PORT datac (893:893:893) (1015:1015:1015)) + (PORT datad (623:623:623) (708:708:708)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (229:229:229)) + (PORT datab (696:696:696) (807:807:807)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1415:1415:1415)) + (PORT datab (1484:1484:1484) (1719:1719:1719)) + (PORT datac (1060:1060:1060) (1225:1225:1225)) + (PORT datad (105:105:105) (124:124:124)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (255:255:255)) + (PORT datab (513:513:513) (585:585:585)) + (PORT datac (801:801:801) (922:922:922)) + (PORT datad (187:187:187) (213:213:213)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -12404,13 +4953,406 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) + (INSTANCE z80_\|execute_\|ctl_mRead\~22) (DELAY (ABSOLUTE - (PORT dataa (329:329:329) (393:393:393)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (327:327:327) (385:385:385)) - (PORT datad (512:512:512) (588:588:588)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (642:642:642) (733:733:733)) + (PORT datac (803:803:803) (923:923:923)) + (PORT datad (115:115:115) (132:132:132)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (819:819:819)) + (PORT datab (211:211:211) (271:271:271)) + (PORT datad (549:549:549) (645:645:645)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT datab (677:677:677) (809:809:809)) + (PORT datad (1155:1155:1155) (1337:1337:1337)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (416:416:416)) + (PORT datab (145:145:145) (179:179:179)) + (PORT datac (1072:1072:1072) (1228:1228:1228)) + (PORT datad (495:495:495) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M5T3_9) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (449:449:449)) + (PORT datab (1121:1121:1121) (1309:1309:1309)) + (PORT datad (876:876:876) (1042:1042:1042)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (1026:1026:1026)) + (PORT datab (821:821:821) (950:950:950)) + (PORT datac (449:449:449) (531:531:531)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (852:852:852)) + (PORT datab (821:821:821) (949:949:949)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (359:359:359) (417:417:417)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (877:877:877)) + (PORT datab (486:486:486) (566:566:566)) + (PORT datac (235:235:235) (296:296:296)) + (PORT datad (650:650:650) (745:745:745)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datab (709:709:709) (821:821:821)) + (PORT datac (937:937:937) (1116:1116:1116)) + (PORT datad (1120:1120:1120) (1277:1277:1277)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (580:580:580)) + (PORT datab (417:417:417) (513:513:513)) + (PORT datac (384:384:384) (473:473:473)) + (PORT datad (142:142:142) (175:175:175)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1107:1107:1107)) + (PORT datab (669:669:669) (767:767:767)) + (PORT datac (608:608:608) (697:697:697)) + (PORT datad (133:133:133) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (687:687:687)) + (PORT datab (1169:1169:1169) (1325:1325:1325)) + (PORT datac (291:291:291) (340:340:340)) + (PORT datad (133:133:133) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (850:850:850)) + (PORT datab (712:712:712) (842:842:842)) + (PORT datac (991:991:991) (1189:1189:1189)) + (PORT datad (209:209:209) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (848:848:848)) + (PORT datab (718:718:718) (849:849:849)) + (PORT datac (996:996:996) (1195:1195:1195)) + (PORT datad (207:207:207) (245:245:245)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (604:604:604)) + (PORT datab (644:644:644) (740:740:740)) + (PORT datac (597:597:597) (723:723:723)) + (PORT datad (1178:1178:1178) (1371:1371:1371)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (570:570:570)) + (PORT datab (477:477:477) (556:556:556)) + (PORT datac (842:842:842) (961:961:961)) + (PORT datad (990:990:990) (1128:1128:1128)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (720:720:720)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (722:722:722) (843:843:843)) + (PORT datad (133:133:133) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (870:870:870)) + (PORT datab (154:154:154) (208:208:208)) + (PORT datac (638:638:638) (736:736:736)) + (PORT datad (648:648:648) (742:742:742)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (1044:1044:1044)) + (PORT datab (1238:1238:1238) (1466:1466:1466)) + (PORT datac (619:619:619) (714:714:714)) + (PORT datad (621:621:621) (706:706:706)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (753:753:753)) + (PORT datab (488:488:488) (566:566:566)) + (PORT datac (509:509:509) (600:600:600)) + (PORT datad (629:629:629) (718:718:718)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (581:581:581)) + (PORT datab (153:153:153) (194:194:194)) + (PORT datac (385:385:385) (475:475:475)) + (PORT datad (780:780:780) (885:885:885)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1462:1462:1462)) + (PORT datab (776:776:776) (894:894:894)) + (PORT datac (847:847:847) (993:993:993)) + (PORT datad (488:488:488) (560:560:560)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (881:881:881)) + (PORT datab (159:159:159) (213:213:213)) + (PORT datac (636:636:636) (734:734:734)) + (PORT datad (652:652:652) (747:747:747)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1246:1246:1246)) + (PORT datab (515:515:515) (601:601:601)) + (PORT datac (848:848:848) (994:994:994)) + (PORT datad (1221:1221:1221) (1435:1435:1435)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (411:411:411)) + (PORT datab (498:498:498) (576:576:576)) + (PORT datac (510:510:510) (593:593:593)) + (PORT datad (489:489:489) (554:554:554)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12420,15 +5362,139 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (INSTANCE z80_\|execute_\|fMRead\~21) (DELAY (ABSOLUTE - (PORT dataa (178:178:178) (223:223:223)) - (PORT datab (673:673:673) (780:780:780)) - (PORT datac (871:871:871) (993:993:993)) - (PORT datad (532:532:532) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (102:102:102) (134:134:134)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (477:477:477)) + (PORT datac (1101:1101:1101) (1305:1305:1305)) + (PORT datad (969:969:969) (1145:1145:1145)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (238:238:238)) + (PORT datab (145:145:145) (188:188:188)) + (PORT datac (386:386:386) (472:472:472)) + (PORT datad (136:136:136) (167:167:167)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (827:827:827)) + (PORT datab (681:681:681) (789:789:789)) + (PORT datac (1129:1129:1129) (1302:1302:1302)) + (PORT datad (779:779:779) (885:885:885)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (625:625:625)) + (PORT datab (792:792:792) (909:909:909)) + (PORT datac (796:796:796) (911:911:911)) + (PORT datad (693:693:693) (798:798:798)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (389:389:389)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (406:406:406) (481:481:481)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (902:902:902)) + (PORT datac (401:401:401) (494:494:494)) + (PORT datad (1002:1002:1002) (1167:1167:1167)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1241:1241:1241)) + (PORT datab (509:509:509) (586:586:586)) + (PORT datac (973:973:973) (1117:1117:1117)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (361:361:361) (432:432:432)) + (PORT datac (604:604:604) (691:691:691)) + (PORT datad (167:167:167) (197:197:197)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12439,294 +5505,26 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (539:539:539) (628:628:628)) + (PORT datac (162:162:162) (194:194:194)) + (PORT datad (313:313:313) (363:363:363)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (734:734:734)) (PORT datab (101:101:101) (129:129:129)) - (PORT datac (340:340:340) (400:400:400)) - (PORT datad (468:468:468) (538:538:538)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (802:802:802)) - (PORT datab (805:805:805) (933:933:933)) - (PORT datac (617:617:617) (718:718:718)) - (PORT datad (672:672:672) (774:774:774)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (179:179:179) (218:218:218)) - (PORT datab (750:750:750) (862:862:862)) - (PORT datac (599:599:599) (680:680:680)) - (PORT datad (735:735:735) (843:843:843)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (431:431:431)) - (PORT datab (494:494:494) (575:575:575)) - (PORT datad (652:652:652) (757:757:757)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1468:1468:1468)) - (PORT datab (895:895:895) (1059:1059:1059)) - (PORT datac (823:823:823) (976:976:976)) - (PORT datad (465:465:465) (538:538:538)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1151:1151:1151)) - (PORT datab (661:661:661) (772:772:772)) - (PORT datac (1052:1052:1052) (1208:1208:1208)) - (PORT datad (606:606:606) (693:693:693)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (228:228:228)) - (PORT datab (340:340:340) (407:407:407)) - (PORT datac (331:331:331) (393:393:393)) - (PORT datad (318:318:318) (370:370:370)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (733:733:733)) - (PORT datab (472:472:472) (551:551:551)) - (PORT datac (988:988:988) (1127:1127:1127)) - (PORT datad (623:623:623) (721:721:721)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (626:626:626)) - (PORT datab (474:474:474) (547:547:547)) - (PORT datac (510:510:510) (593:593:593)) - (PORT datad (777:777:777) (893:893:893)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (151:151:151)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (647:647:647) (744:744:744)) - (PORT datad (337:337:337) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (774:774:774)) - (PORT datab (538:538:538) (631:631:631)) - (PORT datac (477:477:477) (558:558:558)) - (PORT datad (670:670:670) (782:782:782)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (327:327:327) (382:382:382)) - (PORT datad (117:117:117) (134:134:134)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (804:804:804)) - (PORT datab (528:528:528) (630:630:630)) - (PORT datac (348:348:348) (410:410:410)) - (PORT datad (770:770:770) (920:920:920)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (579:579:579)) - (PORT datab (791:791:791) (948:948:948)) - (PORT datac (350:350:350) (412:412:412)) - (PORT datad (187:187:187) (223:223:223)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1225:1225:1225)) - (PORT datab (938:938:938) (1119:1119:1119)) - (PORT datac (329:329:329) (387:387:387)) - (PORT datad (975:975:975) (1127:1127:1127)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (697:697:697)) - (PORT datab (488:488:488) (574:574:574)) - (PORT datac (1249:1249:1249) (1432:1432:1432)) - (PORT datad (925:925:925) (1095:1095:1095)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (864:864:864)) - (PORT datab (508:508:508) (586:586:586)) - (PORT datac (1236:1236:1236) (1422:1422:1422)) - (PORT datad (896:896:896) (1053:1053:1053)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (647:647:647)) - (PORT datab (477:477:477) (551:551:551)) - (PORT datac (113:113:113) (138:138:138)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (419:419:419)) - (PORT datab (684:684:684) (797:797:797)) - (PORT datac (696:696:696) (813:813:813)) - (PORT datad (304:304:304) (351:351:351)) + (PORT datac (433:433:433) (500:500:500)) + (PORT datad (593:593:593) (686:686:686)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -12736,13 +5534,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (556:556:556) (641:641:641)) - (PORT datab (630:630:630) (728:728:728)) - (PORT datac (746:746:746) (861:861:861)) - (PORT datad (489:489:489) (572:572:572)) + (PORT dataa (979:979:979) (1150:1150:1150)) + (PORT datab (507:507:507) (587:587:587)) + (PORT datac (993:993:993) (1167:1167:1167)) + (PORT datad (1127:1127:1127) (1313:1313:1313)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (756:756:756) (869:869:869)) + (PORT datac (462:462:462) (530:530:530)) + (PORT datad (850:850:850) (976:976:976)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (876:876:876)) + (PORT datab (811:811:811) (923:923:923)) + (PORT datac (101:101:101) (127:127:127)) + (PORT datad (846:846:846) (971:971:971)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1152:1152:1152)) + (PORT datab (757:757:757) (870:870:870)) + (PORT datac (489:489:489) (563:563:563)) + (PORT datad (550:550:550) (663:663:663)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -12752,29 +5598,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (508:508:508) (597:597:597)) - (PORT datac (838:838:838) (963:963:963)) - (PORT datad (637:637:637) (731:731:731)) + (PORT dataa (766:766:766) (873:873:873)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (555:555:555) (669:669:669)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) (DELAY (ABSOLUTE - (PORT dataa (493:493:493) (572:572:572)) - (PORT datab (619:619:619) (720:720:720)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (95:95:95) (114:114:114)) + (PORT dataa (803:803:803) (916:916:916)) + (PORT datab (514:514:514) (600:600:600)) + (PORT datac (461:461:461) (527:527:527)) + (PORT datad (1014:1014:1014) (1176:1176:1176)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12784,13 +5630,283 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (786:786:786)) - (PORT datab (110:110:110) (140:140:140)) - (PORT datac (97:97:97) (123:123:123)) - (PORT datad (1150:1150:1150) (1334:1334:1334)) + (PORT dataa (336:336:336) (399:399:399)) + (PORT datab (378:378:378) (452:452:452)) + (PORT datac (684:684:684) (795:795:795)) + (PORT datad (944:944:944) (1078:1078:1078)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT datab (466:466:466) (543:543:543)) + (PORT datac (436:436:436) (496:496:496)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1397:1397:1397)) + (PORT datab (1210:1210:1210) (1425:1425:1425)) + (PORT datac (539:539:539) (631:631:631)) + (PORT datad (755:755:755) (914:914:914)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (534:534:534)) + (PORT datab (561:561:561) (648:648:648)) + (PORT datac (482:482:482) (555:555:555)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (523:523:523)) + (PORT datab (507:507:507) (585:585:585)) + (PORT datac (324:324:324) (389:389:389)) + (PORT datad (294:294:294) (336:336:336)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (628:628:628)) + (PORT datab (592:592:592) (673:673:673)) + (PORT datac (780:780:780) (902:902:902)) + (PORT datad (1117:1117:1117) (1273:1273:1273)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (727:727:727)) + (PORT datab (497:497:497) (586:586:586)) + (PORT datac (340:340:340) (395:395:395)) + (PORT datad (358:358:358) (417:417:417)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (709:709:709)) + (PORT datab (470:470:470) (553:553:553)) + (PORT datac (365:365:365) (436:436:436)) + (PORT datad (792:792:792) (902:902:902)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (848:848:848)) + (PORT datab (721:721:721) (853:853:853)) + (PORT datac (999:999:999) (1198:1198:1198)) + (PORT datad (177:177:177) (208:208:208)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (714:714:714)) + (PORT datab (593:593:593) (689:689:689)) + (PORT datac (368:368:368) (440:440:440)) + (PORT datad (322:322:322) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (210:210:210)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (369:369:369) (441:441:441)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (868:868:868)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (618:618:618) (717:717:717)) + (PORT datad (771:771:771) (876:876:876)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (592:592:592)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (852:852:852) (998:998:998)) + (PORT datad (608:608:608) (712:712:712)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1166:1166:1166)) + (PORT datab (963:963:963) (1118:1118:1118)) + (PORT datac (561:561:561) (671:671:671)) + (PORT datad (448:448:448) (521:521:521)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (239:239:239)) + (PORT datab (294:294:294) (342:342:342)) + (PORT datac (1092:1092:1092) (1299:1299:1299)) + (PORT datad (1005:1005:1005) (1183:1183:1183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (1002:1002:1002)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (611:611:611) (715:715:715)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1218:1218:1218)) + (PORT datab (616:616:616) (746:746:746)) + (PORT datac (818:818:818) (944:944:944)) + (PORT datad (491:491:491) (567:567:567)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1158:1158:1158)) + (PORT datab (127:127:127) (159:159:159)) + (PORT datac (449:449:449) (529:529:529)) + (PORT datad (535:535:535) (638:638:638)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12800,11 +5916,1791 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) (DELAY (ABSOLUTE - (PORT datab (127:127:127) (161:161:161)) - (PORT datac (113:113:113) (139:139:139)) + (PORT dataa (592:592:592) (700:700:700)) + (PORT datab (990:990:990) (1166:1166:1166)) + (PORT datac (1050:1050:1050) (1241:1241:1241)) + (PORT datad (344:344:344) (402:402:402)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (493:493:493)) + (PORT datab (847:847:847) (974:974:974)) + (PORT datac (490:490:490) (574:574:574)) + (PORT datad (1016:1016:1016) (1177:1177:1177)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (1164:1164:1164)) + (PORT datab (1098:1098:1098) (1304:1304:1304)) + (PORT datac (482:482:482) (574:574:574)) + (PORT datad (1290:1290:1290) (1500:1500:1500)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1014:1014:1014) (1219:1219:1219)) + (PORT datac (699:699:699) (822:822:822)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (696:696:696)) + (PORT datab (613:613:613) (743:743:743)) + (PORT datac (946:946:946) (1094:1094:1094)) + (PORT datad (437:437:437) (507:507:507)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1320:1320:1320)) + (PORT datab (499:499:499) (580:580:580)) + (PORT datac (190:190:190) (226:226:226)) + (PORT datad (1004:1004:1004) (1182:1182:1182)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (439:439:439) (510:510:510)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (598:598:598)) + (PORT datab (460:460:460) (532:532:532)) + (PORT datac (495:495:495) (562:562:562)) + (PORT datad (631:631:631) (717:717:717)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (783:783:783)) + (PORT datab (852:852:852) (989:989:989)) + (PORT datac (506:506:506) (596:596:596)) + (PORT datad (676:676:676) (797:797:797)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (937:937:937)) + (PORT datab (548:548:548) (646:646:646)) + (PORT datac (1304:1304:1304) (1517:1517:1517)) + (PORT datad (984:984:984) (1127:1127:1127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (680:680:680)) + (PORT datad (558:558:558) (667:667:667)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (614:614:614)) + (PORT datab (112:112:112) (143:143:143)) + (PORT datac (290:290:290) (336:336:336)) + (PORT datad (652:652:652) (758:758:758)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1666:1666:1666)) + (PORT datab (810:810:810) (955:955:955)) + (PORT datac (717:717:717) (832:832:832)) + (PORT datad (759:759:759) (888:888:888)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1432:1432:1432) (1671:1671:1671)) + (PORT datab (810:810:810) (955:955:955)) + (PORT datac (720:720:720) (835:835:835)) + (PORT datad (757:757:757) (885:885:885)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (219:219:219)) + (PORT datab (490:490:490) (569:569:569)) + (PORT datac (914:914:914) (1077:1077:1077)) + (PORT datad (345:345:345) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (620:620:620) (709:709:709)) + (PORT datad (909:909:909) (1044:1044:1044)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1182:1182:1182)) + (PORT datab (790:790:790) (898:898:898)) + (PORT datac (975:975:975) (1124:1124:1124)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (472:472:472)) + (PORT datab (617:617:617) (732:732:732)) + (PORT datac (338:338:338) (401:401:401)) + (PORT datad (378:378:378) (452:452:452)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (404:404:404) (489:489:489)) + (PORT datad (199:199:199) (235:235:235)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datac (702:702:702) (832:832:832)) + (PORT datad (702:702:702) (827:827:827)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (779:779:779)) + (PORT datab (125:125:125) (158:158:158)) + (PORT datac (560:560:560) (670:670:670)) + (PORT datad (699:699:699) (818:818:818)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (531:531:531)) + (PORT datab (385:385:385) (465:465:465)) + (PORT datac (615:615:615) (711:711:711)) + (PORT datad (747:747:747) (860:860:860)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (217:217:217)) + (PORT datab (509:509:509) (592:592:592)) + (PORT datac (642:642:642) (726:726:726)) + (PORT datad (278:278:278) (314:314:314)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (1039:1039:1039)) + (PORT datac (536:536:536) (630:630:630)) + (PORT datad (664:664:664) (786:786:786)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1447:1447:1447)) + (PORT datab (516:516:516) (603:603:603)) + (PORT datac (519:519:519) (599:599:599)) + (PORT datad (494:494:494) (567:567:567)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (871:871:871) (1019:1019:1019)) + (PORT datad (665:665:665) (787:787:787)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~28) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (735:735:735)) + (PORT datab (382:382:382) (452:452:452)) + (PORT datac (597:597:597) (680:680:680)) + (PORT datad (663:663:663) (760:760:760)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (589:589:589)) + (PORT datab (550:550:550) (656:656:656)) + (PORT datac (671:671:671) (795:795:795)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (943:943:943)) + (PORT datab (1145:1145:1145) (1339:1339:1339)) + (PORT datac (728:728:728) (861:861:861)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (778:778:778)) + (PORT datac (806:806:806) (950:950:950)) + (PORT datad (1446:1446:1446) (1669:1669:1669)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (804:804:804)) + (PORT datab (396:396:396) (479:479:479)) + (PORT datac (953:953:953) (1106:1106:1106)) + (PORT datad (744:744:744) (842:842:842)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (850:850:850)) + (PORT datab (710:710:710) (840:840:840)) + (PORT datac (989:989:989) (1187:1187:1187)) + (PORT datad (177:177:177) (209:209:209)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (800:800:800)) + (PORT datab (772:772:772) (881:881:881)) + (PORT datac (1013:1013:1013) (1168:1168:1168)) + (PORT datad (622:622:622) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (561:561:561)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (92:92:92) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (769:769:769)) + (PORT datab (402:402:402) (478:478:478)) + (PORT datac (677:677:677) (778:778:778)) + (PORT datad (1054:1054:1054) (1253:1253:1253)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (520:520:520)) + (PORT datab (1092:1092:1092) (1239:1239:1239)) + (PORT datac (819:819:819) (943:943:943)) + (PORT datad (920:920:920) (1063:1063:1063)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (315:315:315) (369:369:369)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datac (663:663:663) (779:779:779)) + (PORT datad (203:203:203) (240:240:240)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (1070:1070:1070)) + (PORT datad (679:679:679) (794:794:794)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (474:474:474)) + (PORT datab (619:619:619) (733:733:733)) + (PORT datac (915:915:915) (1077:1077:1077)) + (PORT datad (378:378:378) (453:453:453)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (954:954:954)) + (PORT datab (571:571:571) (675:675:675)) + (PORT datac (836:836:836) (960:960:960)) + (PORT datad (677:677:677) (775:775:775)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (1055:1055:1055)) + (PORT datab (874:874:874) (1054:1054:1054)) + (PORT datad (705:705:705) (842:842:842)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1220:1220:1220)) + (PORT datab (530:530:530) (625:625:625)) + (PORT datac (1069:1069:1069) (1231:1231:1231)) + (PORT datad (669:669:669) (797:797:797)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (929:929:929)) + (PORT datab (777:777:777) (931:931:931)) + (PORT datac (766:766:766) (863:863:863)) + (PORT datad (768:768:768) (913:913:913)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (759:759:759)) + (PORT datab (475:475:475) (553:553:553)) + (PORT datac (1019:1019:1019) (1181:1181:1181)) + (PORT datad (719:719:719) (841:841:841)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (762:762:762)) + (PORT datab (1039:1039:1039) (1202:1202:1202)) + (PORT datac (831:831:831) (966:966:966)) + (PORT datad (715:715:715) (837:837:837)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (600:600:600)) + (PORT datab (854:854:854) (989:989:989)) + (PORT datac (925:925:925) (1053:1053:1053)) + (PORT datad (1116:1116:1116) (1268:1268:1268)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (579:579:579)) + (PORT datab (663:663:663) (783:783:783)) + (PORT datac (331:331:331) (395:395:395)) + (PORT datad (131:131:131) (166:166:166)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (524:524:524)) + (PORT datab (354:354:354) (414:414:414)) + (PORT datac (788:788:788) (893:893:893)) + (PORT datad (1013:1013:1013) (1175:1175:1175)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~13) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (580:580:580)) + (PORT datab (143:143:143) (188:188:188)) + (PORT datac (575:575:575) (664:664:664)) + (PORT datad (140:140:140) (173:173:173)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datab (580:580:580) (692:692:692)) + (PORT datac (945:945:945) (1126:1126:1126)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~58) + (DELAY + (ABSOLUTE + (PORT dataa (312:312:312) (366:366:366)) + (PORT datab (411:411:411) (495:495:495)) + (PORT datac (640:640:640) (749:749:749)) + (PORT datad (891:891:891) (1039:1039:1039)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (591:591:591)) + (PORT datab (351:351:351) (418:418:418)) + (PORT datac (474:474:474) (552:552:552)) + (PORT datad (646:646:646) (744:744:744)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (476:476:476) (541:541:541)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (576:576:576)) + (PORT datac (461:461:461) (535:535:535)) + (PORT datad (615:615:615) (709:709:709)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (738:738:738)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (351:351:351) (411:411:411)) + (PORT datad (667:667:667) (765:765:765)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~29) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (646:646:646)) + (PORT datab (608:608:608) (696:696:696)) + (PORT datac (621:621:621) (713:713:713)) + (PORT datad (1246:1246:1246) (1417:1417:1417)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (666:666:666)) + (PORT datab (550:550:550) (656:656:656)) + (PORT datac (489:489:489) (566:566:566)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (481:481:481)) + (PORT datab (211:211:211) (253:253:253)) + (PORT datac (896:896:896) (1020:1020:1020)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~9) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (1055:1055:1055)) + (PORT datab (717:717:717) (865:865:865)) + (PORT datac (858:858:858) (1032:1032:1032)) + (PORT datad (476:476:476) (540:540:540)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (615:615:615)) + (PORT datab (1053:1053:1053) (1237:1237:1237)) + (PORT datac (1246:1246:1246) (1435:1435:1435)) + (PORT datad (661:661:661) (754:754:754)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (560:560:560)) + (PORT datab (417:417:417) (506:506:506)) + (PORT datac (972:972:972) (1121:1121:1121)) + (PORT datad (466:466:466) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1633:1633:1633)) + (PORT datab (398:398:398) (474:474:474)) + (PORT datac (742:742:742) (872:872:872)) + (PORT datad (1049:1049:1049) (1248:1248:1248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (789:789:789)) + (PORT datab (704:704:704) (807:807:807)) + (PORT datac (385:385:385) (457:457:457)) + (PORT datad (510:510:510) (602:602:602)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (665:665:665)) + (PORT datab (499:499:499) (581:581:581)) + (PORT datac (349:349:349) (412:412:412)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1079:1079:1079) (1260:1260:1260)) + (PORT datab (719:719:719) (853:853:853)) + (PORT datac (526:526:526) (599:599:599)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (327:327:327)) + (PORT datab (462:462:462) (535:535:535)) + (PORT datac (577:577:577) (663:663:663)) + (PORT datad (781:781:781) (900:900:900)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (476:476:476)) + (PORT datab (394:394:394) (477:477:477)) + (PORT datac (590:590:590) (670:670:670)) + (PORT datad (633:633:633) (734:734:734)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (977:977:977)) + (PORT datab (511:511:511) (587:587:587)) + (PORT datac (528:528:528) (615:615:615)) + (PORT datad (497:497:497) (570:570:570)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1080:1080:1080)) + (PORT datab (930:930:930) (1073:1073:1073)) + (PORT datac (457:457:457) (533:533:533)) + (PORT datad (898:898:898) (1049:1049:1049)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (1063:1063:1063)) + (PORT datab (1019:1019:1019) (1180:1180:1180)) + (PORT datac (745:745:745) (854:854:854)) + (PORT datad (289:289:289) (338:338:338)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (556:556:556)) + (PORT datab (571:571:571) (684:684:684)) + (PORT datac (560:560:560) (671:671:671)) + (PORT datad (438:438:438) (508:508:508)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (858:858:858)) + (PORT datab (893:893:893) (1058:1058:1058)) + (PORT datac (1020:1020:1020) (1190:1190:1190)) + (PORT datad (178:178:178) (210:210:210)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (568:568:568)) + (PORT datab (122:122:122) (158:158:158)) + (PORT datac (748:748:748) (854:854:854)) + (PORT datad (579:579:579) (661:661:661)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (984:984:984)) + (PORT datab (526:526:526) (621:621:621)) + (PORT datac (1045:1045:1045) (1193:1193:1193)) + (PORT datad (667:667:667) (795:795:795)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1135:1135:1135)) + (PORT datab (848:848:848) (1000:1000:1000)) + (PORT datac (873:873:873) (1042:1042:1042)) + (PORT datad (1262:1262:1262) (1461:1461:1461)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (390:390:390)) + (PORT datab (440:440:440) (508:508:508)) + (PORT datac (348:348:348) (414:414:414)) + (PORT datad (684:684:684) (790:790:790)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT datab (392:392:392) (477:477:477)) + (PORT datac (610:610:610) (686:686:686)) + (PORT datad (338:338:338) (392:392:392)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (708:708:708)) + (PORT datab (177:177:177) (216:216:216)) + (PORT datac (451:451:451) (511:511:511)) + (PORT datad (311:311:311) (362:362:362)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (453:453:453)) + (PORT datab (678:678:678) (798:798:798)) + (PORT datac (349:349:349) (416:416:416)) + (PORT datad (1257:1257:1257) (1428:1428:1428)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (536:536:536)) + (PORT datab (333:333:333) (390:390:390)) + (PORT datac (316:316:316) (364:364:364)) + (PORT datad (510:510:510) (585:585:585)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~8) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (618:618:618) (710:710:710)) + (PORT datac (495:495:495) (579:579:579)) + (PORT datad (440:440:440) (504:504:504)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (427:427:427)) + (PORT datac (387:387:387) (475:475:475)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (699:699:699)) + (PORT datab (304:304:304) (359:359:359)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (107:107:107) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (227:227:227)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (506:506:506) (596:596:596)) + (PORT datad (797:797:797) (907:907:907)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT datab (468:468:468) (540:540:540)) + (PORT datac (1122:1122:1122) (1283:1283:1283)) + (PORT datad (1014:1014:1014) (1176:1176:1176)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT datab (612:612:612) (701:701:701)) + (PORT datac (436:436:436) (501:501:501)) + (PORT datad (618:618:618) (712:712:712)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (388:388:388)) + (PORT datab (525:525:525) (615:615:615)) + (PORT datac (461:461:461) (539:539:539)) + (PORT datad (368:368:368) (437:437:437)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~9) + (DELAY + (ABSOLUTE + (PORT datab (713:713:713) (843:843:843)) + (PORT datac (992:992:992) (1190:1190:1190)) + (PORT datad (209:209:209) (247:247:247)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT datab (719:719:719) (850:850:850)) + (PORT datac (997:997:997) (1196:1196:1196)) + (PORT datad (206:206:206) (244:244:244)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (839:839:839)) + (PORT datab (766:766:766) (879:879:879)) + (PORT datac (629:629:629) (742:742:742)) + (PORT datad (353:353:353) (411:411:411)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (755:755:755)) + (PORT datab (895:895:895) (1025:1025:1025)) + (PORT datac (647:647:647) (747:747:747)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (651:651:651) (761:761:761)) + (PORT datac (965:965:965) (1120:1120:1120)) + (PORT datad (646:646:646) (743:743:743)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (653:653:653)) + (PORT datab (624:624:624) (726:726:726)) + (PORT datac (1153:1153:1153) (1357:1357:1357)) + (PORT datad (506:506:506) (596:596:596)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (908:908:908)) + (PORT datab (379:379:379) (455:455:455)) + (PORT datac (316:316:316) (381:381:381)) + (PORT datad (579:579:579) (652:652:652)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (440:440:440)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (253:253:253)) + (PORT datab (313:313:313) (368:368:368)) + (PORT datac (358:358:358) (432:432:432)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (412:412:412)) + (PORT datac (511:511:511) (594:594:594)) + (PORT datad (488:488:488) (553:553:553)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (1117:1117:1117)) + (PORT datac (871:871:871) (1035:1035:1035)) + (PORT datad (376:376:376) (450:450:450)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (1024:1024:1024)) + (PORT datab (743:743:743) (883:883:883)) + (PORT datad (569:569:569) (673:673:673)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (1664:1664:1664) (1925:1925:1925)) + (PORT datac (499:499:499) (592:592:592)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1623:1623:1623)) + (PORT datab (363:363:363) (423:423:423)) + (PORT datac (715:715:715) (830:830:830)) + (PORT datad (760:760:760) (888:888:888)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (793:793:793)) + (PORT datab (688:688:688) (818:818:818)) + (PORT datac (431:431:431) (486:486:486)) + (PORT datad (340:340:340) (396:396:396)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (391:391:391) (475:475:475)) + (PORT datac (612:612:612) (712:712:712)) + (PORT datad (631:631:631) (733:733:733)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (225:225:225)) + (PORT datab (607:607:607) (698:698:698)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (848:848:848)) + (PORT datab (925:925:925) (1100:1100:1100)) + (PORT datac (493:493:493) (589:589:589)) + (PORT datad (363:363:363) (424:424:424)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (DELAY + (ABSOLUTE + (PORT datac (868:868:868) (1033:1033:1033)) + (PORT datad (706:706:706) (843:843:843)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1120:1120:1120)) + (PORT datab (874:874:874) (1054:1054:1054)) + (PORT datac (765:765:765) (877:877:877)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (532:532:532)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (809:809:809) (943:943:943)) + (PORT datad (598:598:598) (675:675:675)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (394:394:394)) + (PORT datab (471:471:471) (551:551:551)) + (PORT datac (920:920:920) (1063:1063:1063)) + (PORT datad (820:820:820) (952:952:952)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1203:1203:1203)) + (PORT datab (916:916:916) (1045:1045:1045)) + (PORT datac (383:383:383) (457:457:457)) + (PORT datad (355:355:355) (417:417:417)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (1024:1024:1024)) + (PORT datac (727:727:727) (866:866:866)) + (PORT datad (776:776:776) (901:901:901)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (548:548:548)) + (PORT datab (532:532:532) (627:627:627)) + (PORT datac (1046:1046:1046) (1196:1196:1196)) + (PORT datad (669:669:669) (798:798:798)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (512:512:512)) + (PORT datab (462:462:462) (539:539:539)) + (PORT datac (315:315:315) (364:364:364)) + (PORT datad (451:451:451) (517:517:517)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (153:153:153)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (446:446:446) (512:512:512)) + (PORT datad (782:782:782) (915:915:915)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1219:1219:1219)) + (PORT datab (686:686:686) (821:821:821)) + (PORT datac (474:474:474) (553:553:553)) + (PORT datad (462:462:462) (530:530:530)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (414:414:414)) + (PORT datac (546:546:546) (623:623:623)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) ) @@ -12815,10 +7711,68 @@ (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) (DELAY (ABSOLUTE - (PORT dataa (2065:2065:2065) (2371:2371:2371)) - (PORT datab (526:526:526) (637:637:637)) - (PORT datac (690:690:690) (812:812:812)) - (PORT datad (373:373:373) (438:438:438)) + (PORT dataa (552:552:552) (670:670:670)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (402:402:402) (486:486:486)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (581:581:581) (667:667:667)) + (PORT datad (556:556:556) (630:630:630)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1675:1675:1675)) + (PORT datab (376:376:376) (445:445:445)) + (PORT datac (813:813:813) (945:945:945)) + (PORT datad (756:756:756) (884:884:884)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1357:1357:1357)) + (PORT datab (383:383:383) (463:463:463)) + (PORT datac (614:614:614) (710:710:710)) + (PORT datad (745:745:745) (857:857:857)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (729:729:729)) + (PORT datab (510:510:510) (581:581:581)) + (PORT datac (645:645:645) (744:744:744)) + (PORT datad (1317:1317:1317) (1488:1488:1488)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -12826,16 +7780,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (619:619:619)) + (PORT datab (1064:1064:1064) (1263:1263:1263)) + (PORT datac (516:516:516) (601:601:601)) + (PORT datad (388:388:388) (481:481:481)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) (DELAY (ABSOLUTE - (PORT dataa (1109:1109:1109) (1309:1309:1309)) - (PORT datab (813:813:813) (933:933:933)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (752:752:752) (914:914:914)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (901:901:901) (1070:1070:1070)) + (PORT datab (870:870:870) (1021:1021:1021)) + (PORT datac (583:583:583) (669:669:669)) + (PORT datad (351:351:351) (406:406:406)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -12847,61 +7817,13 @@ (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) (DELAY (ABSOLUTE - (PORT dataa (405:405:405) (491:491:491)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (886:886:886) (1008:1008:1008)) - (PORT datad (847:847:847) (975:975:975)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (660:660:660)) - (PORT datab (436:436:436) (540:540:540)) - (PORT datac (839:839:839) (964:964:964)) - (PORT datad (352:352:352) (415:415:415)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1327:1327:1327)) - (PORT datab (608:608:608) (694:694:694)) - (PORT datac (463:463:463) (540:540:540)) - (PORT datad (369:369:369) (434:434:434)) + (PORT dataa (224:224:224) (262:262:262)) + (PORT datab (797:797:797) (940:940:940)) + (PORT datac (355:355:355) (419:419:419)) + (PORT datad (112:112:112) (134:134:134)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (654:654:654)) - (PORT datab (426:426:426) (519:519:519)) - (PORT datac (838:838:838) (963:963:963)) - (PORT datad (495:495:495) (575:575:575)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12911,13 +7833,13 @@ (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (814:814:814) (934:934:934)) - (PORT datac (553:553:553) (627:627:627)) - (PORT datad (337:337:337) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (351:351:351) (408:408:408)) + (PORT datab (509:509:509) (588:588:588)) + (PORT datac (285:285:285) (324:324:324)) + (PORT datad (331:331:331) (379:379:379)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12927,10 +7849,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) (DELAY (ABSOLUTE - (PORT dataa (530:530:530) (604:604:604)) - (PORT datab (699:699:699) (798:798:798)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (487:487:487) (554:554:554)) + (PORT dataa (468:468:468) (545:545:545)) + (PORT datab (763:763:763) (876:876:876)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -12940,13 +7862,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) (DELAY (ABSOLUTE - (PORT dataa (942:942:942) (1114:1114:1114)) - (PORT datac (769:769:769) (879:879:879)) - (PORT datad (960:960:960) (1116:1116:1116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (1150:1150:1150) (1350:1350:1350)) + (PORT datab (864:864:864) (1021:1021:1021)) + (PORT datac (634:634:634) (736:736:736)) + (PORT datad (873:873:873) (989:989:989)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12954,45 +7878,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (395:395:395)) - (PORT datab (104:104:104) (134:134:134)) - (PORT datac (582:582:582) (657:657:657)) - (PORT datad (465:465:465) (541:541:541)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (395:395:395)) - (PORT datab (642:642:642) (742:742:742)) - (PORT datac (262:262:262) (298:298:298)) - (PORT datad (101:101:101) (123:123:123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (637:637:637)) - (PORT datab (850:850:850) (1008:1008:1008)) - (PORT datac (102:102:102) (131:131:131)) - (PORT datad (106:106:106) (130:130:130)) + (PORT dataa (576:576:576) (694:694:694)) + (PORT datab (836:836:836) (965:965:965)) + (PORT datac (450:450:450) (530:530:530)) + (PORT datad (612:612:612) (701:701:701)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13002,121 +7894,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (955:955:955)) - (PORT datac (671:671:671) (784:784:784)) - (PORT datad (750:750:750) (911:911:911)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (955:955:955)) - (PORT datab (944:944:944) (1105:1105:1105)) - (PORT datac (964:964:964) (1133:1133:1133)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (952:952:952)) - (PORT datab (1483:1483:1483) (1754:1754:1754)) - (PORT datac (679:679:679) (784:784:784)) - (PORT datad (478:478:478) (551:551:551)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (790:790:790)) - (PORT datab (338:338:338) (395:395:395)) - (PORT datac (113:113:113) (140:140:140)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (1099:1099:1099)) - (PORT datab (1487:1487:1487) (1762:1762:1762)) - (PORT datac (930:930:930) (1124:1124:1124)) - (PORT datad (861:861:861) (977:977:977)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (819:819:819)) - (PORT datab (603:603:603) (694:694:694)) - (PORT datac (885:885:885) (1044:1044:1044)) - (PORT datad (814:814:814) (943:943:943)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (602:602:602) (688:688:688)) - (PORT datad (118:118:118) (143:143:143)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (951:951:951)) - (PORT datab (854:854:854) (990:990:990)) - (PORT datac (844:844:844) (971:971:971)) - (PORT datad (1114:1114:1114) (1266:1266:1266)) + (PORT dataa (720:720:720) (851:851:851)) + (PORT datab (1383:1383:1383) (1621:1621:1621)) + (PORT datac (635:635:635) (727:727:727)) + (PORT datad (101:101:101) (125:125:125)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -13124,17 +7908,217 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (436:436:436)) + (PORT datac (340:340:340) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (569:569:569)) + (PORT datab (1040:1040:1040) (1202:1202:1202)) + (PORT datac (842:842:842) (963:963:963)) + (PORT datad (946:946:946) (1079:1079:1079)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT datab (620:620:620) (716:716:716)) + (PORT datac (263:263:263) (303:303:303)) + (PORT datad (594:594:594) (676:676:676)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) (DELAY (ABSOLUTE - (PORT dataa (510:510:510) (588:588:588)) - (PORT datab (361:361:361) (428:428:428)) - (PORT datac (333:333:333) (391:391:391)) - (PORT datad (103:103:103) (120:120:120)) + (PORT dataa (456:456:456) (525:525:525)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (98:98:98) (123:123:123)) + (PORT datad (501:501:501) (583:583:583)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (608:608:608)) + (PORT datab (997:997:997) (1150:1150:1150)) + (PORT datac (525:525:525) (621:621:621)) + (PORT datad (914:914:914) (1045:1045:1045)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (856:856:856)) + (PORT datab (997:997:997) (1149:1149:1149)) + (PORT datac (837:837:837) (991:991:991)) + (PORT datad (664:664:664) (784:784:784)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (825:825:825)) + (PORT datab (413:413:413) (497:497:497)) + (PORT datac (541:541:541) (653:653:653)) + (PORT datad (545:545:545) (633:633:633)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (177:177:177)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datad (589:589:589) (669:669:669)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (1072:1072:1072)) + (PORT datab (874:874:874) (1036:1036:1036)) + (PORT datac (340:340:340) (400:400:400)) + (PORT datad (348:348:348) (412:412:412)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (607:607:607)) + (PORT datab (1065:1065:1065) (1265:1265:1265)) + (PORT datac (514:514:514) (599:599:599)) + (PORT datad (389:389:389) (482:482:482)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (984:984:984)) + (PORT datab (500:500:500) (580:580:580)) + (PORT datac (494:494:494) (578:578:578)) + (PORT datad (1014:1014:1014) (1177:1177:1177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (701:701:701)) + (PORT datab (1033:1033:1033) (1200:1200:1200)) + (PORT datac (661:661:661) (758:758:758)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (431:431:431)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (277:277:277) (318:318:318)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (717:717:717)) + (PORT datab (755:755:755) (857:857:857)) + (PORT datac (843:843:843) (982:982:982)) + (PORT datad (573:573:573) (664:664:664)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13145,10 +8129,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) (DELAY (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (346:346:346) (407:407:407)) - (PORT datac (497:497:497) (580:580:580)) - (PORT datad (518:518:518) (601:601:601)) + (PORT dataa (708:708:708) (809:809:809)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (341:341:341) (399:399:399)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13161,339 +8145,25 @@ (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) (DELAY (ABSOLUTE - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (721:721:721) (830:830:830)) - (PORT datad (448:448:448) (517:517:517)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (116:116:116) (148:148:148)) + (PORT datab (196:196:196) (236:236:236)) + (PORT datac (471:471:471) (546:546:546)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) (DELAY (ABSOLUTE - (PORT dataa (468:468:468) (542:542:542)) - (PORT datab (600:600:600) (690:690:690)) - (PORT datac (267:267:267) (307:307:307)) - (PORT datad (273:273:273) (314:314:314)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (862:862:862)) - (PORT datab (1254:1254:1254) (1445:1445:1445)) - (PORT datac (822:822:822) (972:972:972)) - (PORT datad (494:494:494) (562:562:562)) + (PORT dataa (491:491:491) (597:597:597)) + (PORT datab (467:467:467) (546:546:546)) + (PORT datac (584:584:584) (665:665:665)) + (PORT datad (597:597:597) (686:686:686)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (749:749:749)) - (PORT datab (668:668:668) (777:777:777)) - (PORT datac (482:482:482) (564:564:564)) - (PORT datad (667:667:667) (778:778:778)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (597:597:597)) - (PORT datab (491:491:491) (577:577:577)) - (PORT datac (681:681:681) (780:780:780)) - (PORT datad (317:317:317) (358:358:358)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (860:860:860)) - (PORT datab (996:996:996) (1143:1143:1143)) - (PORT datac (446:446:446) (527:527:527)) - (PORT datad (1180:1180:1180) (1322:1322:1322)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (719:719:719)) - (PORT datab (672:672:672) (783:783:783)) - (PORT datad (514:514:514) (593:593:593)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (518:518:518) (614:614:614)) - (PORT datab (360:360:360) (415:415:415)) - (PORT datac (452:452:452) (525:525:525)) - (PORT datad (474:474:474) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (631:631:631) (729:729:729)) - (PORT datac (109:109:109) (132:132:132)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (423:423:423)) - (PORT datab (176:176:176) (214:214:214)) - (PORT datac (629:629:629) (726:726:726)) - (PORT datad (518:518:518) (604:604:604)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (708:708:708)) - (PORT datab (361:361:361) (433:433:433)) - (PORT datac (494:494:494) (574:574:574)) - (PORT datad (445:445:445) (514:514:514)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (129:129:129) (163:163:163)) - (PORT datac (114:114:114) (141:141:141)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (825:825:825)) - (PORT datab (1104:1104:1104) (1305:1305:1305)) - (PORT datac (1091:1091:1091) (1266:1266:1266)) - (PORT datad (750:750:750) (873:873:873)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (784:784:784)) - (PORT datab (670:670:670) (777:777:777)) - (PORT datac (557:557:557) (633:633:633)) - (PORT datad (161:161:161) (188:188:188)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1413:1413:1413)) - (PORT datab (972:972:972) (1160:1160:1160)) - (PORT datac (309:309:309) (359:359:359)) - (PORT datad (1129:1129:1129) (1295:1295:1295)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1350:1350:1350)) - (PORT datab (662:662:662) (768:768:768)) - (PORT datac (799:799:799) (924:924:924)) - (PORT datad (761:761:761) (873:873:873)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (555:555:555)) - (PORT datab (368:368:368) (433:433:433)) - (PORT datac (1005:1005:1005) (1146:1146:1146)) - (PORT datad (986:986:986) (1124:1124:1124)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (911:911:911)) - (PORT datab (492:492:492) (579:579:579)) - (PORT datac (818:818:818) (936:936:936)) - (PORT datad (468:468:468) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (593:593:593)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (344:344:344) (405:405:405)) - (PORT datad (337:337:337) (391:391:391)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (559:559:559)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (95:95:95) (118:118:118)) - (PORT datad (444:444:444) (507:507:507)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (414:414:414)) - (PORT datab (358:358:358) (424:424:424)) - (PORT datac (356:356:356) (408:408:408)) - (PORT datad (178:178:178) (211:211:211)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (810:810:810)) - (PORT datab (673:673:673) (781:781:781)) - (PORT datac (342:342:342) (402:402:402)) - (PORT datad (660:660:660) (757:757:757)) - (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13502,325 +8172,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (501:501:501) (574:574:574)) - (PORT datad (331:331:331) (390:390:390)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1546:1546:1546)) - (PORT datab (533:533:533) (621:621:621)) - (PORT datac (581:581:581) (656:656:656)) - (PORT datad (990:990:990) (1157:1157:1157)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (477:477:477) (544:544:544)) - (PORT datac (664:664:664) (767:767:767)) - (PORT datad (797:797:797) (917:917:917)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datac (939:939:939) (1073:1073:1073)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (391:391:391)) - (PORT datab (298:298:298) (348:348:348)) - (PORT datac (846:846:846) (972:972:972)) - (PORT datad (913:913:913) (1042:1042:1042)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (821:821:821)) - (PORT datab (632:632:632) (734:734:734)) - (PORT datac (504:504:504) (599:599:599)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (555:555:555) (635:635:635)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1154:1154:1154)) - (PORT datab (508:508:508) (595:595:595)) - (PORT datac (666:666:666) (769:769:769)) - (PORT datad (1383:1383:1383) (1621:1621:1621)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (356:356:356) (418:418:418)) - (PORT datac (95:95:95) (121:121:121)) - (PORT datad (101:101:101) (123:123:123)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (794:794:794)) - (PORT datab (903:903:903) (1078:1078:1078)) - (PORT datac (854:854:854) (1008:1008:1008)) - (PORT datad (995:995:995) (1153:1153:1153)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1349:1349:1349)) - (PORT datab (699:699:699) (819:819:819)) - (PORT datac (839:839:839) (965:965:965)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (241:241:241)) - (PORT datab (700:700:700) (820:820:820)) - (PORT datac (637:637:637) (728:728:728)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (149:149:149)) - (PORT datab (325:325:325) (377:377:377)) - (PORT datac (748:748:748) (855:855:855)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (436:436:436)) - (PORT datab (528:528:528) (616:616:616)) - (PORT datac (840:840:840) (967:967:967)) - (PORT datad (664:664:664) (770:770:770)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (799:799:799) (921:921:921)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (844:844:844)) - (PORT datab (667:667:667) (775:775:775)) - (PORT datac (845:845:845) (971:971:971)) - (PORT datad (358:358:358) (415:415:415)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (681:681:681) (788:788:788)) - (PORT datac (845:845:845) (972:972:972)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (903:903:903)) - (PORT datab (958:958:958) (1152:1152:1152)) - (PORT datac (519:519:519) (589:589:589)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (729:729:729)) - (PORT datab (365:365:365) (432:432:432)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (349:349:349) (400:400:400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (1058:1058:1058)) - (PORT datab (744:744:744) (851:851:851)) - (PORT datac (629:629:629) (723:723:723)) - (PORT datad (332:332:332) (389:389:389)) + (PORT dataa (511:511:511) (588:588:588)) + (PORT datab (787:787:787) (903:903:903)) + (PORT datac (925:925:925) (1053:1053:1053)) + (PORT datad (836:836:836) (965:965:965)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (750:750:750)) - (PORT datab (750:750:750) (858:858:858)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13828,47 +8188,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (357:357:357) (418:418:418)) - (PORT datac (99:99:99) (126:126:126)) - (PORT datad (97:97:97) (118:118:118)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (686:686:686) (803:803:803)) + (PORT datab (505:505:505) (590:590:590)) + (PORT datac (611:611:611) (691:691:691)) + (PORT datad (1113:1113:1113) (1265:1265:1265)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (177:177:177) (220:220:220)) - (PORT datab (431:431:431) (491:491:491)) - (PORT datac (781:781:781) (909:909:909)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (615:615:615) (724:724:724)) + (PORT datab (521:521:521) (607:607:607)) + (PORT datac (610:610:610) (691:691:691)) + (PORT datad (1258:1258:1258) (1429:1429:1429)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (1039:1039:1039)) - (PORT datab (705:705:705) (829:829:829)) - (PORT datac (838:838:838) (965:965:965)) - (PORT datad (1161:1161:1161) (1324:1324:1324)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13876,143 +8220,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1008:1008:1008) (1178:1178:1178)) - (PORT datab (901:901:901) (1076:1076:1076)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (894:894:894) (1013:1013:1013)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (993:993:993)) - (PORT datab (985:985:985) (1137:1137:1137)) - (PORT datac (847:847:847) (980:980:980)) - (PORT datad (170:170:170) (201:201:201)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (459:459:459)) - (PORT datab (513:513:513) (593:593:593)) - (PORT datac (968:968:968) (1117:1117:1117)) - (PORT datad (89:89:89) (107:107:107)) + (PORT dataa (125:125:125) (159:159:159)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (281:281:281) (321:321:321)) + (PORT datad (93:93:93) (113:113:113)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (991:991:991)) - (PORT datab (609:609:609) (699:699:699)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (1057:1057:1057) (1212:1212:1212)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (458:458:458)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (594:594:594) (678:678:678)) - (PORT datad (939:939:939) (1073:1073:1073)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (928:928:928)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (339:339:339) (399:399:399)) - (PORT datad (1062:1062:1062) (1217:1217:1217)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (412:412:412)) - (PORT datab (328:328:328) (385:385:385)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (912:912:912)) - (PORT datab (529:529:529) (622:622:622)) - (PORT datac (673:673:673) (777:777:777)) - (PORT datad (642:642:642) (744:744:744)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (724:724:724)) - (PORT datab (629:629:629) (721:721:721)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14023,10 +8239,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) (DELAY (ABSOLUTE - (PORT dataa (981:981:981) (1132:1132:1132)) - (PORT datab (771:771:771) (887:887:887)) - (PORT datac (666:666:666) (777:777:777)) - (PORT datad (854:854:854) (976:976:976)) + (PORT dataa (499:499:499) (584:584:584)) + (PORT datab (480:480:480) (561:561:561)) + (PORT datac (657:657:657) (753:753:753)) + (PORT datad (760:760:760) (873:873:873)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -14039,26 +8255,74 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) (DELAY (ABSOLUTE - (PORT dataa (980:980:980) (1130:1130:1130)) - (PORT datab (774:774:774) (891:891:891)) - (PORT datac (818:818:818) (940:940:940)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (843:843:843) (982:982:982)) + (PORT datab (779:779:779) (897:897:897)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (486:486:486) (557:557:557)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (1016:1016:1016)) + (PORT datab (684:684:684) (786:786:786)) + (PORT datac (981:981:981) (1153:1153:1153)) + (PORT datad (358:358:358) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (1088:1088:1088)) + (PORT datab (950:950:950) (1101:1101:1101)) + (PORT datac (591:591:591) (691:691:691)) + (PORT datad (961:961:961) (1121:1121:1121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (701:701:701)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (629:629:629) (734:734:734)) + (PORT datad (438:438:438) (500:500:500)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) (DELAY (ABSOLUTE - (PORT dataa (691:691:691) (815:815:815)) - (PORT datab (878:878:878) (1008:1008:1008)) - (PORT datac (515:515:515) (605:605:605)) - (PORT datad (521:521:521) (615:615:615)) + (PORT dataa (623:623:623) (730:730:730)) + (PORT datab (366:366:366) (437:437:437)) + (PORT datac (623:623:623) (719:719:719)) + (PORT datad (622:622:622) (707:707:707)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -14071,10 +8335,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) (DELAY (ABSOLUTE - (PORT dataa (660:660:660) (759:759:759)) - (PORT datab (537:537:537) (636:636:636)) - (PORT datac (510:510:510) (599:599:599)) - (PORT datad (95:95:95) (115:115:115)) + (PORT dataa (635:635:635) (731:731:731)) + (PORT datab (605:605:605) (694:694:694)) + (PORT datac (623:623:623) (718:718:718)) + (PORT datad (93:93:93) (112:112:112)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -14082,49 +8346,81 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (585:585:585)) - (PORT datab (1087:1087:1087) (1289:1289:1289)) - (PORT datac (1068:1068:1068) (1268:1268:1268)) - (PORT datad (583:583:583) (662:662:662)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (802:802:802)) - (PORT datab (662:662:662) (772:772:772)) - (PORT datac (455:455:455) (521:521:521)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (329:329:329) (391:391:391)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT dataa (189:189:189) (235:235:235)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (416:416:416) (471:471:471)) + (PORT datad (331:331:331) (381:381:381)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (954:954:954)) + (PORT datab (483:483:483) (565:565:565)) + (PORT datac (940:940:940) (1084:1084:1084)) + (PORT datad (531:531:531) (634:634:634)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (575:575:575)) + (PORT datab (913:913:913) (1070:1070:1070)) + (PORT datac (351:351:351) (417:417:417)) + (PORT datad (499:499:499) (573:573:573)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (442:442:442)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (101:101:101) (123:123:123)) + (PORT datad (468:468:468) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (173:173:173)) + (PORT datab (928:928:928) (1062:1062:1062)) + (PORT datac (1059:1059:1059) (1226:1226:1226)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14135,949 +8431,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (500:500:500) (577:577:577)) - (PORT datab (491:491:491) (570:570:570)) - (PORT datac (349:349:349) (405:405:405)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1636:1636:1636) (1867:1867:1867)) - (PORT datab (580:580:580) (692:692:692)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (1443:1443:1443) (1656:1656:1656)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (790:790:790)) - (PORT datab (599:599:599) (687:687:687)) - (PORT datac (755:755:755) (868:868:868)) - (PORT datad (657:657:657) (753:753:753)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (904:904:904)) - (PORT datab (341:341:341) (405:405:405)) - (PORT datac (332:332:332) (384:384:384)) - (PORT datad (390:390:390) (463:463:463)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (549:549:549)) - (PORT datab (483:483:483) (563:563:563)) - (PORT datac (1127:1127:1127) (1311:1311:1311)) - (PORT datad (453:453:453) (518:518:518)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1544:1544:1544)) - (PORT datab (534:534:534) (622:622:622)) - (PORT datac (1025:1025:1025) (1163:1163:1163)) - (PORT datad (990:990:990) (1158:1158:1158)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (653:653:653) (763:763:763)) - (PORT datad (952:952:952) (1106:1106:1106)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1326:1326:1326)) - (PORT datab (351:351:351) (408:408:408)) - (PORT datac (465:465:465) (542:542:542)) - (PORT datad (372:372:372) (437:437:437)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (148:148:148)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (470:470:470) (537:537:537)) - (PORT datad (174:174:174) (206:206:206)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1286:1286:1286)) - (PORT datab (854:854:854) (981:981:981)) - (PORT datac (655:655:655) (772:772:772)) - (PORT datad (337:337:337) (392:392:392)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (316:316:316) (359:359:359)) - (PORT datad (466:466:466) (537:537:537)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (1048:1048:1048)) - (PORT datab (561:561:561) (675:675:675)) - (PORT datac (1281:1281:1281) (1512:1512:1512)) - (PORT datad (337:337:337) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (475:475:475) (556:556:556)) - (PORT datac (1234:1234:1234) (1420:1420:1420)) - (PORT datad (650:650:650) (751:751:751)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (391:391:391)) - (PORT datab (327:327:327) (387:387:387)) - (PORT datac (582:582:582) (656:656:656)) - (PORT datad (794:794:794) (914:914:914)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (630:630:630)) - (PORT datab (727:727:727) (824:824:824)) - (PORT datac (783:783:783) (897:897:897)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (740:740:740)) - (PORT datab (494:494:494) (577:577:577)) - (PORT datac (329:329:329) (385:385:385)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (954:954:954)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (163:163:163) (190:190:190)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (569:569:569)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (321:321:321) (379:379:379)) - (PORT datad (788:788:788) (914:914:914)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (576:576:576)) - (PORT datab (520:520:520) (613:613:613)) - (PORT datac (393:393:393) (448:448:448)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (400:400:400)) - (PORT datab (1032:1032:1032) (1177:1177:1177)) - (PORT datac (522:522:522) (608:608:608)) - (PORT datad (694:694:694) (807:807:807)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (317:317:317) (370:370:370)) - (PORT datad (574:574:574) (658:658:658)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (229:229:229)) - (PORT datab (346:346:346) (407:407:407)) - (PORT datac (327:327:327) (378:378:378)) - (PORT datad (333:333:333) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (580:580:580)) + (PORT dataa (601:601:601) (696:696:696)) (PORT datab (102:102:102) (129:129:129)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (631:631:631) (716:716:716)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (554:554:554)) - (PORT datab (1259:1259:1259) (1482:1482:1482)) - (PORT datac (704:704:704) (843:843:843)) - (PORT datad (1613:1613:1613) (1886:1886:1886)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (382:382:382)) - (PORT datab (373:373:373) (443:443:443)) - (PORT datac (509:509:509) (602:602:602)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (382:382:382)) - (PORT datac (474:474:474) (539:539:539)) - (PORT datad (446:446:446) (511:511:511)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1277:1277:1277)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datad (476:476:476) (557:557:557)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (907:907:907)) - (PORT datab (656:656:656) (766:766:766)) - (PORT datac (461:461:461) (543:543:543)) - (PORT datad (737:737:737) (855:855:855)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1166:1166:1166)) - (PORT datac (343:343:343) (400:400:400)) - (PORT datad (783:783:783) (926:926:926)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (664:664:664) (764:764:764)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (955:955:955)) - (PORT datab (352:352:352) (413:413:413)) - (PORT datad (949:949:949) (1123:1123:1123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (839:839:839)) - (PORT datab (492:492:492) (570:570:570)) - (PORT datac (811:811:811) (941:941:941)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (832:832:832) (963:963:963)) - (PORT datac (487:487:487) (568:568:568)) - (PORT datad (677:677:677) (811:811:811)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (537:537:537) (608:608:608)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (853:853:853)) - (PORT datab (488:488:488) (566:566:566)) - (PORT datac (813:813:813) (942:942:942)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (540:540:540) (612:612:612)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (831:831:831) (962:962:962)) - (PORT datac (489:489:489) (571:571:571)) - (PORT datad (672:672:672) (805:805:805)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (599:599:599)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datad (490:490:490) (569:569:569)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (508:508:508)) - (PORT datab (134:134:134) (183:183:183)) - (PORT datac (419:419:419) (478:478:478)) - (PORT datad (107:107:107) (130:130:130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (831:831:831) (962:962:962)) - (PORT datac (470:470:470) (546:546:546)) - (PORT datad (676:676:676) (810:810:810)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (506:506:506)) - (PORT datab (118:118:118) (153:153:153)) - (PORT datac (416:416:416) (476:476:476)) - (PORT datad (120:120:120) (159:159:159)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (831:831:831) (962:962:962)) - (PORT datac (463:463:463) (537:537:537)) - (PORT datad (673:673:673) (807:807:807)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (832:832:832) (963:963:963)) - (PORT datac (467:467:467) (543:543:543)) - (PORT datad (681:681:681) (818:818:818)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (793:793:793) (902:902:902)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (832:832:832) (963:963:963)) - (PORT datac (463:463:463) (537:537:537)) - (PORT datad (675:675:675) (809:809:809)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (790:790:790) (899:899:899)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (644:644:644)) - (PORT datab (539:539:539) (625:625:625)) - (PORT datad (186:186:186) (232:232:232)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (486:486:486) (585:585:585)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (947:947:947)) - (PORT datab (661:661:661) (772:772:772)) - (PORT datac (979:979:979) (1147:1147:1147)) - (PORT datad (813:813:813) (942:942:942)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (939:939:939) (1108:1108:1108)) - (PORT datac (611:611:611) (705:705:705)) - (PORT datad (179:179:179) (214:214:214)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (936:936:936) (1104:1104:1104)) - (PORT datac (609:609:609) (704:704:704)) - (PORT datad (177:177:177) (212:212:212)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datab (935:935:935) (1103:1103:1103)) - (PORT datad (967:967:967) (1123:1123:1123)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (951:951:951)) - (PORT datab (998:998:998) (1166:1166:1166)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (642:642:642) (746:746:746)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (783:783:783) (891:891:891)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datab (934:934:934) (1102:1102:1102)) - (PORT datac (609:609:609) (703:703:703)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (934:934:934)) - (PORT datab (196:196:196) (237:237:237)) - (PORT datac (987:987:987) (1155:1155:1155)) - (PORT datad (636:636:636) (739:739:739)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (318:318:318)) - (PORT datab (269:269:269) (326:326:326)) - (PORT datad (339:339:339) (394:394:394)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (330:330:330) (385:385:385)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (908:908:908)) - (PORT datab (657:657:657) (768:768:768)) - (PORT datac (176:176:176) (210:210:210)) - (PORT datad (738:738:738) (855:855:855)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (949:949:949)) - (PORT datab (191:191:191) (230:230:230)) - (PORT datac (769:769:769) (886:886:886)) - (PORT datad (642:642:642) (745:745:745)) + (PORT datac (519:519:519) (588:588:588)) + (PORT datad (104:104:104) (121:121:121)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15087,45 +8444,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~50) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (110:110:110) (131:131:131)) + (PORT dataa (584:584:584) (701:701:701)) + (PORT datab (808:808:808) (950:950:950)) + (PORT datac (289:289:289) (334:334:334)) + (PORT datad (473:473:473) (545:545:545)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) (DELAY (ABSOLUTE - (PORT dataa (1144:1144:1144) (1304:1304:1304)) - (PORT datab (802:802:802) (954:954:954)) - (PORT datac (1164:1164:1164) (1388:1388:1388)) - (PORT datad (474:474:474) (553:553:553)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (677:677:677)) - (PORT datab (710:710:710) (829:829:829)) - (PORT datac (1069:1069:1069) (1218:1218:1218)) - (PORT datad (187:187:187) (218:218:218)) + (PORT dataa (703:703:703) (845:845:845)) + (PORT datab (479:479:479) (555:555:555)) + (PORT datac (648:648:648) (749:749:749)) + (PORT datad (635:635:635) (727:727:727)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -15135,27 +8476,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datac (326:326:326) (382:382:382)) - (PORT datad (451:451:451) (517:517:517)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (431:431:431)) - (PORT datab (116:116:116) (150:150:150)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (781:781:781) (916:916:916)) + (PORT datab (350:350:350) (422:422:422)) + (PORT datac (720:720:720) (835:835:835)) + (PORT datad (346:346:346) (400:400:400)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15165,609 +8492,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) (DELAY (ABSOLUTE - (PORT dataa (114:114:114) (145:145:145)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (462:462:462) (538:538:538)) - (PORT datad (346:346:346) (402:402:402)) + (PORT dataa (815:815:815) (947:947:947)) + (PORT datab (684:684:684) (795:795:795)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (621:621:621) (712:712:712)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (635:635:635)) - (PORT datac (507:507:507) (593:593:593)) - (PORT datad (686:686:686) (796:796:796)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (508:508:508) (563:563:563)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (633:633:633)) - (PORT datac (508:508:508) (593:593:593)) - (PORT datad (685:685:685) (795:795:795)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (180:180:180)) - (PORT datab (523:523:523) (617:617:617)) - (PORT datad (468:468:468) (549:549:549)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (945:945:945)) - (PORT datab (660:660:660) (771:771:771)) - (PORT datac (176:176:176) (209:209:209)) - (PORT datad (310:310:310) (374:374:374)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (945:945:945)) - (PORT datab (325:325:325) (400:400:400)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (640:640:640) (743:743:743)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (795:795:795) (910:910:910)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (940:940:940)) - (PORT datab (324:324:324) (398:398:398)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (639:639:639) (741:741:741)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (800:800:800) (915:915:915)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (946:946:946)) - (PORT datab (660:660:660) (772:772:772)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (310:310:310) (375:375:375)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (420:420:420)) - (PORT datab (132:132:132) (181:181:181)) - (PORT datad (339:339:339) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (910:910:910)) - (PORT datab (661:661:661) (772:772:772)) - (PORT datac (464:464:464) (546:546:546)) - (PORT datad (741:741:741) (859:859:859)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (958:958:958)) - (PORT datab (475:475:475) (556:556:556)) - (PORT datad (956:956:956) (1130:1130:1130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (890:890:890) (1036:1036:1036)) - (PORT datac (490:490:490) (573:573:573)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1081:1081:1081)) - (PORT datab (200:200:200) (238:238:238)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (485:485:485) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (955:955:955)) - (PORT datab (480:480:480) (562:562:562)) - (PORT datad (948:948:948) (1122:1122:1122)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (787:787:787) (896:896:896)) - (PORT ena (655:655:655) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (637:637:637)) - (PORT datab (718:718:718) (840:840:840)) - (PORT datad (471:471:471) (544:544:544)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (699:699:699) (804:804:804)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (290:290:290) (336:336:336)) - (PORT datac (434:434:434) (503:503:503)) - (PORT datad (580:580:580) (687:687:687)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (749:749:749) (858:858:858)) - (PORT datac (635:635:635) (729:729:729)) - (PORT datad (330:330:330) (387:387:387)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (440:440:440)) - (PORT datab (486:486:486) (570:570:570)) - (PORT datac (670:670:670) (789:789:789)) - (PORT datad (295:295:295) (342:342:342)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (469:469:469) (545:545:545)) - (PORT datac (178:178:178) (212:212:212)) - (PORT datad (625:625:625) (706:706:706)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (337:337:337) (382:382:382)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (343:343:343)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (118:118:118) (147:147:147)) - (PORT datac (104:104:104) (125:125:125)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (585:585:585)) - (PORT datab (757:757:757) (870:870:870)) - (PORT datac (754:754:754) (864:864:864)) - (PORT datad (458:458:458) (542:542:542)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (393:393:393)) - (PORT datab (759:759:759) (873:873:873)) - (PORT datac (219:219:219) (261:261:261)) - (PORT datad (113:113:113) (135:135:135)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (991:991:991)) - (PORT datab (437:437:437) (509:509:509)) - (PORT datac (478:478:478) (573:573:573)) - (PORT datad (465:465:465) (540:540:540)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (534:534:534) (612:612:612)) - (PORT datab (767:767:767) (880:880:880)) - (PORT datac (613:613:613) (718:718:718)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (691:691:691)) - (PORT datab (1053:1053:1053) (1212:1212:1212)) - (PORT datac (469:469:469) (545:545:545)) - (PORT datad (341:341:341) (399:399:399)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (739:739:739)) - (PORT datab (806:806:806) (934:934:934)) - (PORT datac (588:588:588) (673:673:673)) - (PORT datad (663:663:663) (767:767:767)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (802:802:802)) - (PORT datab (632:632:632) (735:735:735)) - (PORT datac (508:508:508) (590:590:590)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (537:537:537)) - (PORT datab (434:434:434) (500:500:500)) - (PORT datac (876:876:876) (1003:1003:1003)) - (PORT datad (595:595:595) (681:681:681)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (641:641:641)) - (PORT datab (349:349:349) (410:410:410)) - (PORT datac (490:490:490) (565:565:565)) - (PORT datad (105:105:105) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (952:952:952)) - (PORT datab (350:350:350) (407:407:407)) - (PORT datac (507:507:507) (592:592:592)) - (PORT datad (657:657:657) (754:754:754)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (145:145:145)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (757:757:757) (870:870:870)) - (PORT datad (328:328:328) (381:381:381)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (905:905:905)) - (PORT datab (192:192:192) (231:231:231)) - (PORT datac (347:347:347) (401:401:401)) - (PORT datad (390:390:390) (463:463:463)) - (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -15776,15 +8508,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (541:541:541) (626:626:626)) - (PORT datab (458:458:458) (537:537:537)) - (PORT datac (281:281:281) (325:325:325)) - (PORT datad (601:601:601) (692:692:692)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (435:435:435) (493:493:493)) + (PORT datad (170:170:170) (200:200:200)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15792,1208 +8520,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) (DELAY (ABSOLUTE - (PORT dataa (623:623:623) (721:721:721)) - (PORT datab (497:497:497) (576:576:576)) - (PORT datac (681:681:681) (786:786:786)) - (PORT datad (681:681:681) (793:793:793)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (691:691:691)) - (PORT datab (337:337:337) (392:392:392)) - (PORT datac (100:100:100) (126:126:126)) - (PORT datad (449:449:449) (507:507:507)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (1105:1105:1105) (1307:1307:1307)) - (PORT datac (1092:1092:1092) (1268:1268:1268)) - (PORT datad (926:926:926) (1105:1105:1105)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (903:903:903)) - (PORT datab (676:676:676) (789:789:789)) - (PORT datac (645:645:645) (750:750:750)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datac (451:451:451) (525:525:525)) - (PORT datad (338:338:338) (391:391:391)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (346:346:346)) - (PORT datab (196:196:196) (237:237:237)) - (PORT datac (600:600:600) (690:690:690)) - (PORT datad (448:448:448) (506:506:506)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (1043:1043:1043)) - (PORT datab (910:910:910) (1035:1035:1035)) - (PORT datac (917:917:917) (1055:1055:1055)) - (PORT datad (625:625:625) (724:724:724)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (434:434:434)) - (PORT datab (800:800:800) (904:904:904)) - (PORT datac (524:524:524) (618:618:618)) - (PORT datad (165:165:165) (193:193:193)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (260:260:260)) - (PORT datab (199:199:199) (236:236:236)) - (PORT datac (520:520:520) (610:610:610)) - (PORT datad (476:476:476) (554:554:554)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (543:543:543)) - (PORT datab (644:644:644) (744:744:744)) - (PORT datad (310:310:310) (362:362:362)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (389:389:389)) - (PORT datab (215:215:215) (269:269:269)) - (PORT datac (483:483:483) (571:571:571)) - (PORT datad (645:645:645) (743:743:743)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (717:717:717)) - (PORT datad (1041:1041:1041) (1186:1186:1186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (747:747:747)) - (PORT datab (632:632:632) (732:732:732)) - (PORT datac (763:763:763) (872:872:872)) - (PORT datad (606:606:606) (693:693:693)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (237:237:237)) - (PORT datab (966:966:966) (1114:1114:1114)) - (PORT datac (919:919:919) (1083:1083:1083)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (761:761:761) (875:875:875)) - (PORT datad (1044:1044:1044) (1189:1189:1189)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (748:748:748)) - (PORT datab (633:633:633) (733:733:733)) - (PORT datac (763:763:763) (873:873:873)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (352:352:352) (384:384:384)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (236:236:236)) - (PORT datab (966:966:966) (1113:1113:1113)) - (PORT datac (917:917:917) (1081:1081:1081)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (931:931:931) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (184:184:184)) - (PORT datab (819:819:819) (974:974:974)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (703:703:703) (848:848:848)) - (PORT datac (571:571:571) (660:660:660)) - (PORT datad (770:770:770) (876:876:876)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (718:718:718)) - (PORT datab (193:193:193) (230:230:230)) - (PORT datad (1042:1042:1042) (1188:1188:1188)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (841:841:841)) - (PORT datac (569:569:569) (659:659:659)) - (PORT datad (768:768:768) (873:873:873)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (896:896:896) (995:995:995)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (491:491:491) (569:569:569)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (718:718:718)) - (PORT datab (192:192:192) (229:229:229)) - (PORT datad (1043:1043:1043) (1189:1189:1189)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (393:393:393)) - (PORT datab (517:517:517) (607:607:607)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (846:846:846)) - (PORT datab (558:558:558) (657:657:657)) - (PORT datac (507:507:507) (593:593:593)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (860:860:860)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (603:603:603) (699:699:699)) - (PORT datad (312:312:312) (377:377:377)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (504:504:504)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (455:455:455) (531:531:531)) - (PORT datad (752:752:752) (862:862:862)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (515:515:515) (574:574:574)) - (PORT ena (666:666:666) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (782:782:782)) - (PORT datab (372:372:372) (441:441:441)) - (PORT datad (532:532:532) (613:613:613)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (715:715:715) (843:843:843)) - (PORT datab (560:560:560) (660:660:660)) - (PORT datac (509:509:509) (596:596:596)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (516:516:516) (575:575:575)) - (PORT ena (603:603:603) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (267:267:267)) - (PORT datab (102:102:102) (131:131:131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (944:944:944)) - (PORT datab (660:660:660) (771:771:771)) - (PORT datac (983:983:983) (1151:1151:1151)) - (PORT datad (286:286:286) (326:326:326)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (602:602:602) (664:664:664)) - (PORT ena (495:495:495) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1134:1134:1134)) - (PORT datab (739:739:739) (856:856:856)) - (PORT datac (603:603:603) (700:700:700)) - (PORT datad (602:602:602) (693:693:693)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (721:721:721)) - (PORT datab (325:325:325) (400:400:400)) - (PORT datac (721:721:721) (833:833:833)) - (PORT datad (434:434:434) (496:496:496)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (600:600:600) (661:661:661)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (863:863:863)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datac (604:604:604) (700:700:700)) - (PORT datad (313:313:313) (378:378:378)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (181:181:181)) - (PORT datab (133:133:133) (167:167:167)) - (PORT datad (113:113:113) (135:135:135)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (421:421:421)) - (PORT datab (344:344:344) (407:407:407)) - (PORT datac (411:411:411) (468:468:468)) - (PORT datad (337:337:337) (393:393:393)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (845:845:845)) - (PORT datac (462:462:462) (536:536:536)) - (PORT datad (769:769:769) (875:875:875)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (854:854:854)) - (PORT datac (466:466:466) (542:542:542)) - (PORT datad (773:773:773) (879:879:879)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (852:852:852)) - (PORT datac (467:467:467) (543:543:543)) - (PORT datad (772:772:772) (878:878:878)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (641:641:641) (717:717:717)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (372:372:372) (442:442:442)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (849:849:849)) - (PORT datac (461:461:461) (535:535:535)) - (PORT datad (771:771:771) (877:877:877)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (269:269:269)) - (PORT datab (234:234:234) (280:280:280)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (579:579:579) (634:634:634)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (578:578:578) (632:632:632)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (180:180:180)) - (PORT datab (590:590:590) (680:680:680)) - (PORT datad (188:188:188) (231:231:231)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (417:417:417)) - (PORT datab (350:350:350) (420:420:420)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1215:1215:1215)) - (PORT datab (1046:1046:1046) (1222:1222:1222)) - (PORT datac (112:112:112) (139:139:139)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (470:470:470) (547:547:547)) - (PORT datab (478:478:478) (555:555:555)) - (PORT datac (278:278:278) (314:314:314)) - (PORT datad (337:337:337) (389:389:389)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (759:759:759)) - (PORT datab (567:567:567) (657:657:657)) - (PORT datac (381:381:381) (454:454:454)) - (PORT datad (616:616:616) (712:712:712)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (806:806:806)) - (PORT datab (380:380:380) (446:446:446)) - (PORT datac (282:282:282) (328:328:328)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (318:318:318)) - (PORT datab (352:352:352) (421:421:421)) - (PORT datac (345:345:345) (397:397:397)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (640:640:640) (702:702:702)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (280:280:280) (300:300:300)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (944:944:944)) - (PORT datab (301:301:301) (351:351:351)) - (PORT datad (349:349:349) (404:404:404)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (260:260:260)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (328:328:328) (383:383:383)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (640:640:640)) - (PORT datab (228:228:228) (290:290:290)) - (PORT datac (660:660:660) (754:754:754)) - (PORT datad (223:223:223) (278:278:278)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1166:1166:1166)) - (PORT datab (689:689:689) (783:783:783)) - (PORT datac (675:675:675) (779:779:779)) - (PORT datad (551:551:551) (642:642:642)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (501:501:501) (583:583:583)) - (PORT datad (97:97:97) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1064:1064:1064)) - (PORT datab (661:661:661) (772:772:772)) - (PORT datac (339:339:339) (396:396:396)) - (PORT datad (466:466:466) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (407:407:407)) - (PORT datab (336:336:336) (395:395:395)) - (PORT datad (486:486:486) (558:558:558)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (584:584:584)) - (PORT datab (621:621:621) (716:716:716)) - (PORT datac (911:911:911) (1032:1032:1032)) - (PORT datad (488:488:488) (556:556:556)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (505:505:505) (579:579:579)) - (PORT datac (586:586:586) (667:667:667)) - (PORT datad (604:604:604) (688:688:688)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (744:744:744)) - (PORT datab (485:485:485) (584:584:584)) - (PORT datac (629:629:629) (725:725:725)) - (PORT datad (465:465:465) (533:533:533)) + (PORT dataa (807:807:807) (913:913:913)) + (PORT datab (517:517:517) (602:602:602)) + (PORT datac (925:925:925) (1053:1053:1053)) + (PORT datad (836:836:836) (965:965:965)) (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (715:715:715)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (549:549:549) (634:634:634)) - (PORT datad (497:497:497) (576:576:576)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (655:655:655)) - (PORT datab (522:522:522) (625:625:625)) - (PORT datac (582:582:582) (666:666:666)) - (PORT datad (102:102:102) (126:126:126)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (579:579:579)) - (PORT datab (450:450:450) (515:515:515)) - (PORT datac (216:216:216) (277:277:277)) - (PORT datad (345:345:345) (416:416:416)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (717:717:717)) - (PORT datab (205:205:205) (266:266:266)) - (PORT datac (597:597:597) (683:683:683)) - (PORT datad (347:347:347) (418:418:418)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17002,249 +8536,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) (DELAY (ABSOLUTE - (PORT dataa (316:316:316) (365:365:365)) - (PORT datab (872:872:872) (1007:1007:1007)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (469:469:469) (546:546:546)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (488:488:488)) - (PORT datab (119:119:119) (147:147:147)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (543:543:543) (640:640:640)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (945:945:945)) - (PORT datab (342:342:342) (406:406:406)) - (PORT datac (667:667:667) (776:776:776)) - (PORT datad (355:355:355) (411:411:411)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (256:256:256)) - (PORT datab (160:160:160) (215:215:215)) - (PORT datad (135:135:135) (176:176:176)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (422:422:422)) - (PORT datab (556:556:556) (634:634:634)) - (PORT datac (691:691:691) (805:805:805)) - (PORT datad (1118:1118:1118) (1256:1256:1256)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (655:655:655)) - (PORT datab (433:433:433) (536:536:536)) - (PORT datac (838:838:838) (963:963:963)) - (PORT datad (496:496:496) (576:576:576)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (495:495:495)) - (PORT datab (1406:1406:1406) (1621:1621:1621)) - (PORT datac (741:741:741) (851:851:851)) - (PORT datad (396:396:396) (481:481:481)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (527:527:527)) - (PORT datab (351:351:351) (413:413:413)) - (PORT datac (463:463:463) (529:529:529)) - (PORT datad (459:459:459) (528:528:528)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (656:656:656)) - (PORT datab (487:487:487) (564:564:564)) - (PORT datac (505:505:505) (602:602:602)) - (PORT datad (102:102:102) (124:124:124)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (709:709:709)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (783:783:783)) - (PORT datab (1123:1123:1123) (1302:1302:1302)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (312:312:312) (354:354:354)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (924:924:924)) - (PORT datab (833:833:833) (963:963:963)) - (PORT datac (474:474:474) (555:555:555)) - (PORT datad (654:654:654) (740:740:740)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (744:744:744)) - (PORT datab (472:472:472) (541:541:541)) - (PORT datac (368:368:368) (447:447:447)) - (PORT datad (595:595:595) (681:681:681)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (950:950:950) (1091:1091:1091)) - (PORT datab (1125:1125:1125) (1305:1305:1305)) - (PORT datac (342:342:342) (397:397:397)) - (PORT datad (447:447:447) (513:513:513)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (755:755:755)) - (PORT datab (387:387:387) (456:456:456)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (379:379:379) (458:458:458)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (157:157:157)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (333:333:333) (385:385:385)) - (PORT datad (103:103:103) (120:120:120)) + (PORT dataa (504:504:504) (585:585:585)) + (PORT datab (665:665:665) (781:781:781)) + (PORT datac (510:510:510) (592:592:592)) + (PORT datad (507:507:507) (587:587:587)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17254,189 +8552,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1454:1454:1454)) - (PORT datab (820:820:820) (953:953:953)) - (PORT datac (403:403:403) (472:472:472)) - (PORT datad (114:114:114) (136:136:136)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (654:654:654)) - (PORT datab (524:524:524) (627:627:627)) - (PORT datac (326:326:326) (374:374:374)) - (PORT datad (652:652:652) (743:743:743)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~17) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (376:376:376)) - (PORT datab (305:305:305) (357:357:357)) - (PORT datac (1235:1235:1235) (1429:1429:1429)) - (PORT datad (285:285:285) (325:325:325)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (886:886:886)) - (PORT datab (417:417:417) (491:491:491)) - (PORT datac (1236:1236:1236) (1430:1430:1430)) - (PORT datad (712:712:712) (831:831:831)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (646:646:646)) - (PORT datab (780:780:780) (914:914:914)) - (PORT datac (401:401:401) (469:469:469)) - (PORT datad (507:507:507) (586:586:586)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (123:123:123) (155:155:155)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (531:531:531)) - (PORT datab (428:428:428) (530:530:530)) - (PORT datac (344:344:344) (401:401:401)) - (PORT datad (396:396:396) (481:481:481)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~15) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (384:384:384)) - (PORT datab (402:402:402) (473:473:473)) - (PORT datac (1124:1124:1124) (1294:1294:1294)) - (PORT datad (435:435:435) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~16) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (507:507:507)) - (PORT datab (431:431:431) (533:533:533)) - (PORT datac (424:424:424) (514:514:514)) - (PORT datad (1037:1037:1037) (1201:1201:1201)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (430:430:430)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (273:273:273) (311:311:311)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (713:713:713)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (440:440:440) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (1045:1045:1045)) - (PORT datab (1139:1139:1139) (1315:1315:1315)) - (PORT datac (472:472:472) (550:550:550)) - (PORT datad (789:789:789) (889:889:889)) + (PORT dataa (324:324:324) (381:381:381)) + (PORT datab (480:480:480) (561:561:561)) + (PORT datac (492:492:492) (576:576:576)) + (PORT datad (1015:1015:1015) (1176:1176:1176)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -17446,90 +8568,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT datab (427:427:427) (528:528:528)) - (PORT datac (415:415:415) (504:504:504)) - (PORT datad (563:563:563) (631:631:631)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (494:494:494)) - (PORT datab (1344:1344:1344) (1567:1567:1567)) - (PORT datac (417:417:417) (506:506:506)) - (PORT datad (354:354:354) (415:415:415)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) - (DELAY - (ABSOLUTE - (PORT datab (643:643:643) (760:760:760)) - (PORT datac (497:497:497) (588:588:588)) - (PORT datad (390:390:390) (470:470:470)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1419:1419:1419) (1644:1644:1644)) - (PORT datab (511:511:511) (599:599:599)) - (PORT datac (612:612:612) (696:696:696)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (575:575:575)) - (PORT datab (428:428:428) (529:529:529)) - (PORT datac (417:417:417) (506:506:506)) - (PORT datad (302:302:302) (347:347:347)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) (DELAY (ABSOLUTE (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (108:108:108) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (470:470:470) (542:542:542)) + (PORT datac (334:334:334) (393:393:393)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17538,27 +8584,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) (DELAY (ABSOLUTE - (PORT datab (207:207:207) (251:251:251)) - (PORT datad (467:467:467) (546:546:546)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (698:698:698)) - (PORT datab (235:235:235) (281:281:281)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (1100:1100:1100) (1235:1235:1235)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (428:428:428) (508:508:508)) + (PORT datab (833:833:833) (965:965:965)) + (PORT datac (723:723:723) (870:870:870)) + (PORT datad (503:503:503) (579:579:579)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17566,143 +8600,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) (DELAY (ABSOLUTE - (PORT dataa (549:549:549) (651:651:651)) - (PORT datab (783:783:783) (917:917:917)) - (PORT datac (1235:1235:1235) (1429:1429:1429)) - (PORT datad (508:508:508) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (422:422:422) (489:489:489)) + (PORT datab (511:511:511) (601:601:601)) + (PORT datac (439:439:439) (504:504:504)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (597:597:597)) + (PORT datab (790:790:790) (925:925:925)) + (PORT datac (684:684:684) (799:799:799)) + (PORT datad (563:563:563) (643:643:643)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (220:220:220)) + (PORT dataa (107:107:107) (139:139:139)) (PORT datab (102:102:102) (130:130:130)) - (PORT datac (886:886:886) (1003:1003:1003)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (433:433:433)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (490:490:490) (563:563:563)) - (PORT datad (796:796:796) (916:916:916)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (811:811:811) (935:935:935)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (114:114:114) (135:135:135)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) - (DELAY - (ABSOLUTE - (PORT dataa (438:438:438) (534:534:534)) - (PORT datab (1347:1347:1347) (1571:1571:1571)) - (PORT datac (343:343:343) (400:400:400)) - (PORT datad (374:374:374) (455:455:455)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (430:430:430)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (271:271:271) (309:309:309)) + (PORT datac (878:878:878) (997:997:997)) (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (145:145:145)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (402:402:402) (470:470:470)) - (PORT datad (115:115:115) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (250:250:250)) - (PORT datab (163:163:163) (218:218:218)) - (PORT datac (617:617:617) (718:718:718)) - (PORT datad (136:136:136) (176:176:176)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1454:1454:1454)) - (PORT datab (124:124:124) (155:155:155)) - (PORT datac (340:340:340) (395:395:395)) - (PORT datad (564:564:564) (630:630:630)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17710,203 +8646,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~51) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (814:814:814) (938:938:938)) - (PORT datac (807:807:807) (935:935:935)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (299:299:299) (347:347:347)) - (PORT datab (282:282:282) (326:326:326)) - (PORT datac (747:747:747) (846:846:846)) - (PORT datad (354:354:354) (404:404:404)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (286:286:286) (336:336:336)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (113:113:113) (134:134:134)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (343:343:343) (408:408:408)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (331:331:331) (385:385:385)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (573:573:573)) - (PORT datab (1113:1113:1113) (1259:1259:1259)) - (PORT datac (427:427:427) (495:495:495)) - (PORT datad (468:468:468) (547:547:547)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT datab (115:115:115) (148:148:148)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (114:114:114) (135:135:135)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (1128:1128:1128) (1300:1300:1300)) - (PORT datac (471:471:471) (569:569:569)) - (PORT datad (283:283:283) (324:324:324)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (327:327:327) (384:384:384)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (152:152:152)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (396:396:396)) - (PORT datab (114:114:114) (141:141:141)) - (PORT datad (174:174:174) (206:206:206)) + (PORT dataa (188:188:188) (230:230:230)) + (PORT datab (1239:1239:1239) (1461:1461:1461)) + (PORT datac (874:874:874) (1031:1031:1031)) + (PORT datad (989:989:989) (1153:1153:1153)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (756:756:756)) - (PORT datab (235:235:235) (281:281:281)) - (PORT datac (423:423:423) (502:502:502)) - (PORT datad (1107:1107:1107) (1276:1276:1276)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) (DELAY (ABSOLUTE (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (675:675:675) (771:771:771)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (1099:1099:1099) (1234:1234:1234)) + (PORT datab (655:655:655) (765:765:765)) + (PORT datac (627:627:627) (722:722:722)) + (PORT datad (104:104:104) (121:121:121)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~48) (DELAY (ABSOLUTE - (PORT dataa (493:493:493) (570:570:570)) - (PORT datab (522:522:522) (603:603:603)) - (PORT datac (524:524:524) (634:634:634)) - (PORT datad (682:682:682) (804:804:804)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (889:889:889) (1052:1052:1052)) + (PORT datac (182:182:182) (213:213:213)) + (PORT datad (1001:1001:1001) (1158:1158:1158)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17914,30 +8694,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (480:480:480) (555:555:555)) - (PORT datab (298:298:298) (345:345:345)) - (PORT datac (1504:1504:1504) (1707:1707:1707)) - (PORT datad (166:166:166) (196:196:196)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (662:662:662)) - (PORT datab (438:438:438) (541:541:541)) - (PORT datac (403:403:403) (495:495:495)) - (PORT datad (895:895:895) (1024:1024:1024)) + (PORT dataa (857:857:857) (1016:1016:1016)) + (PORT datab (927:927:927) (1061:1061:1061)) + (PORT datac (332:332:332) (398:398:398)) + (PORT datad (866:866:866) (1020:1020:1020)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (303:303:303) (347:347:347)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1210:1210:1210)) + (PORT datab (476:476:476) (557:557:557)) + (PORT datac (1337:1337:1337) (1570:1570:1570)) + (PORT datad (168:168:168) (198:198:198)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17946,63 +8740,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (1009:1009:1009)) + (PORT datab (658:658:658) (755:755:755)) + (PORT datac (437:437:437) (508:508:508)) + (PORT datad (160:160:160) (187:187:187)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (139:139:139)) + (PORT datab (366:366:366) (435:435:435)) + (PORT datac (302:302:302) (343:343:343)) + (PORT datad (487:487:487) (558:558:558)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (647:647:647)) + (PORT datab (380:380:380) (447:447:447)) + (PORT datac (341:341:341) (405:405:405)) + (PORT datad (631:631:631) (717:717:717)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (449:449:449)) + (PORT datab (766:766:766) (880:880:880)) + (PORT datac (703:703:703) (790:790:790)) + (PORT datad (658:658:658) (760:760:760)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (715:715:715)) + (PORT datab (593:593:593) (689:689:689)) + (PORT datac (841:841:841) (980:980:980)) + (PORT datad (621:621:621) (718:718:718)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) (DELAY (ABSOLUTE (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (280:280:280) (320:320:320)) - (PORT datad (1099:1099:1099) (1234:1234:1234)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (858:858:858)) - (PORT datab (841:841:841) (967:967:967)) - (PORT datac (343:343:343) (408:408:408)) - (PORT datad (468:468:468) (562:562:562)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (553:553:553)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (593:593:593) (677:677:677)) - (PORT datad (195:195:195) (229:229:229)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT datab (753:753:753) (855:855:855)) + (PORT datac (358:358:358) (424:424:424)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1418:1418:1418) (1643:1643:1643)) - (PORT datab (522:522:522) (610:610:610)) - (PORT datac (723:723:723) (813:813:813)) - (PORT datad (474:474:474) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18010,13 +8836,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (276:276:276)) - (PORT datab (523:523:523) (611:611:611)) - (PORT datac (744:744:744) (850:850:850)) - (PORT datad (93:93:93) (112:112:112)) + (PORT dataa (681:681:681) (792:792:792)) + (PORT datab (681:681:681) (792:792:792)) + (PORT datac (441:441:441) (510:510:510)) + (PORT datad (592:592:592) (671:671:671)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (504:504:504) (585:585:585)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (868:868:868)) + (PORT datab (869:869:869) (999:999:999)) + (PORT datac (462:462:462) (529:529:529)) + (PORT datad (551:551:551) (664:664:664)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18026,13 +8882,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (274:274:274)) - (PORT datab (490:490:490) (570:570:570)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (576:576:576) (695:695:695)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (782:782:782) (889:889:889)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (587:587:587)) + (PORT datab (363:363:363) (429:429:429)) + (PORT datac (315:315:315) (363:363:363)) + (PORT datad (341:341:341) (399:399:399)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18042,13 +8914,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (223:223:223)) - (PORT datab (208:208:208) (252:252:252)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (467:467:467) (546:546:546)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (304:304:304) (347:347:347)) + (PORT datad (95:95:95) (117:117:117)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18058,839 +8930,143 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (341:341:341)) + (PORT datab (105:105:105) (133:133:133)) + (PORT datac (427:427:427) (489:489:489)) + (PORT datad (457:457:457) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (698:698:698)) + (PORT datab (402:402:402) (472:472:472)) + (PORT datac (953:953:953) (1099:1099:1099)) + (PORT datad (741:741:741) (843:843:843)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1338:1338:1338)) + (PORT datab (755:755:755) (868:868:868)) + (PORT datac (993:993:993) (1167:1167:1167)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (698:698:698)) + (PORT datab (509:509:509) (589:589:589)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (384:384:384) (448:448:448)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (395:395:395)) + (PORT datab (865:865:865) (995:995:995)) + (PORT datac (496:496:496) (570:570:570)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1150:1150:1150)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (521:521:521) (605:605:605)) + (PORT datad (552:552:552) (665:665:665)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (866:866:866) (996:996:996)) + (PORT datac (961:961:961) (1124:1124:1124)) + (PORT datad (454:454:454) (524:524:524)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (370:370:370)) + (PORT datab (811:811:811) (923:923:923)) + (PORT datac (524:524:524) (607:607:607)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) (DELAY (ABSOLUTE (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (1100:1100:1100) (1235:1235:1235)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (503:503:503) (584:584:584)) + (PORT datad (322:322:322) (371:371:371)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (779:779:779) (897:897:897)) - (PORT datac (763:763:763) (873:873:873)) - (PORT datad (575:575:575) (662:662:662)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (532:532:532) (591:591:591)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (533:533:533) (591:591:591)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (391:391:391)) - (PORT datab (516:516:516) (605:605:605)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (350:350:350) (375:375:375)) - (PORT ena (666:666:666) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (253:253:253)) - (PORT datab (497:497:497) (582:582:582)) - (PORT datac (525:525:525) (616:616:616)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (554:554:554)) - (PORT datab (476:476:476) (557:557:557)) - (PORT datac (430:430:430) (494:494:494)) - (PORT datad (298:298:298) (337:337:337)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (696:696:696) (773:773:773)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (699:699:699) (777:777:777)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (642:642:642)) - (PORT datab (536:536:536) (622:622:622)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (532:532:532) (588:588:588)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (354:354:354) (412:412:412)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (600:600:600)) - (PORT datab (513:513:513) (599:599:599)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (645:645:645) (735:735:735)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (960:960:960)) - (PORT datab (361:361:361) (424:424:424)) - (PORT datad (958:958:958) (1134:1134:1134)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (350:350:350) (407:407:407)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (540:540:540) (606:606:606)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (180:180:180)) - (PORT datab (519:519:519) (612:612:612)) - (PORT datad (472:472:472) (553:553:553)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (638:638:638) (719:719:719)) - (PORT ena (629:629:629) (679:679:679)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (828:828:828) (921:921:921)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (444:444:444)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datad (302:302:302) (347:347:347)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (691:691:691) (768:768:768)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (691:691:691) (768:768:768)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (420:420:420)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (337:337:337) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (906:906:906)) - (PORT asdata (894:894:894) (1025:1025:1025)) - (PORT ena (656:656:656) (724:724:724)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (574:574:574)) - (PORT datab (693:693:693) (815:815:815)) - (PORT datad (335:335:335) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (413:413:413)) - (PORT datab (459:459:459) (549:549:549)) - (PORT datac (323:323:323) (372:372:372)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (523:523:523)) - (PORT datab (580:580:580) (678:678:678)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (740:740:740)) - (PORT datab (761:761:761) (868:868:868)) - (PORT datac (522:522:522) (614:614:614)) - (PORT datad (767:767:767) (863:863:863)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1457:1457:1457) (1668:1668:1668)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (608:608:608) (706:706:706)) - (PORT datad (797:797:797) (918:918:918)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (409:409:409)) - (PORT datab (508:508:508) (590:590:590)) - (PORT datac (617:617:617) (715:715:715)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (739:739:739)) - (PORT datac (494:494:494) (570:570:570)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (736:736:736)) - (PORT datab (512:512:512) (595:595:595)) - (PORT datac (602:602:602) (699:699:699)) - (PORT datad (792:792:792) (912:912:912)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (281:281:281)) - (PORT datac (303:303:303) (353:353:353)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (360:360:360) (391:391:391)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (360:360:360) (391:391:391)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (394:394:394)) - (PORT datab (517:517:517) (607:607:607)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (681:681:681) (761:761:761)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (682:682:682) (761:761:761)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (177:177:177)) - (PORT datab (591:591:591) (681:681:681)) - (PORT datad (187:187:187) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (480:480:480) (524:524:524)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (480:480:480) (524:524:524)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (221:221:221) (260:260:260)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (751:751:751) (832:832:832)) - (PORT ena (434:434:434) (462:462:462)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (856:856:856)) - (PORT datab (553:553:553) (652:652:652)) - (PORT datad (495:495:495) (575:575:575)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (785:785:785) (874:874:874)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (973:973:973)) - (PORT datab (851:851:851) (1009:1009:1009)) - (PORT datac (1145:1145:1145) (1307:1307:1307)) - (PORT datad (341:341:341) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (159:159:159)) - (PORT datab (389:389:389) (477:477:477)) - (PORT datac (485:485:485) (561:561:561)) - (PORT datad (657:657:657) (748:748:748)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (582:582:582)) - (PORT datab (346:346:346) (406:406:406)) - (PORT datac (722:722:722) (847:847:847)) - (PORT datad (170:170:170) (201:201:201)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (474:474:474) (565:565:565)) - (PORT datac (388:388:388) (477:477:477)) - (PORT datad (349:349:349) (407:407:407)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (564:564:564)) - (PORT datab (775:775:775) (889:889:889)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18901,8 +9077,12 @@ (INSTANCE z80_\|alu_\|db_high\[3\]\~1) (DELAY (ABSOLUTE - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (704:704:704) (806:806:806)) + (PORT dataa (471:471:471) (547:547:547)) + (PORT datab (653:653:653) (760:760:760)) + (PORT datac (741:741:741) (852:852:852)) + (PORT datad (742:742:742) (849:849:849)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18910,13 +9090,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (666:666:666) (777:777:777)) - (PORT datac (1159:1159:1159) (1351:1351:1351)) - (PORT datad (724:724:724) (874:874:874)) + (PORT dataa (519:519:519) (612:612:612)) + (PORT datab (121:121:121) (150:150:150)) + (PORT datac (527:527:527) (610:610:610)) + (PORT datad (124:124:124) (150:150:150)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (540:540:540)) + (PORT datab (855:855:855) (1013:1013:1013)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (700:700:700) (824:824:824)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18924,197 +9122,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (419:419:419)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (282:282:282) (325:325:325)) + (PORT dataa (1153:1153:1153) (1316:1316:1316)) + (PORT datab (387:387:387) (461:461:461)) + (PORT datac (1070:1070:1070) (1225:1225:1225)) + (PORT datad (735:735:735) (833:833:833)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1312:1312:1312)) - (PORT datab (818:818:818) (946:946:946)) - (PORT datac (598:598:598) (684:684:684)) - (PORT datad (892:892:892) (1058:1058:1058)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (987:987:987) (1162:1162:1162)) - (PORT datab (904:904:904) (1080:1080:1080)) - (PORT datac (1763:1763:1763) (2032:2032:2032)) - (PORT datad (1082:1082:1082) (1285:1285:1285)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (950:950:950)) - (PORT datab (1113:1113:1113) (1288:1288:1288)) - (PORT datac (837:837:837) (972:972:972)) - (PORT datad (994:994:994) (1152:1152:1152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (871:871:871) (1019:1019:1019)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (377:377:377)) - (PORT datab (330:330:330) (392:392:392)) - (PORT datac (333:333:333) (390:390:390)) - (PORT datad (174:174:174) (207:207:207)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (162:162:162)) - (PORT datab (363:363:363) (422:422:422)) - (PORT datac (549:549:549) (617:617:617)) - (PORT datad (325:325:325) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (581:581:581)) - (PORT datab (354:354:354) (421:421:421)) - (PORT datac (986:986:986) (1128:1128:1128)) - (PORT datad (293:293:293) (336:336:336)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (369:369:369)) - (PORT datab (353:353:353) (421:421:421)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (511:511:511) (595:595:595)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT datac (296:296:296) (348:348:348)) - (PORT datad (594:594:594) (683:683:683)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1309:1309:1309)) - (PORT datab (793:793:793) (912:912:912)) - (PORT datad (755:755:755) (916:916:916)) + (PORT dataa (137:137:137) (176:176:176)) + (PORT datab (347:347:347) (408:408:408)) + (PORT datac (1055:1055:1055) (1222:1222:1222)) + (PORT datad (914:914:914) (1038:1038:1038)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (626:626:626)) - (PORT datab (539:539:539) (638:638:638)) - (PORT datac (822:822:822) (942:942:942)) - (PORT datad (702:702:702) (816:816:816)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (544:544:544) (630:630:630)) - (PORT datac (513:513:513) (603:603:603)) - (PORT datad (520:520:520) (614:614:614)) + (PORT dataa (925:925:925) (1057:1057:1057)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (102:102:102) (124:124:124)) + (PORT datad (495:495:495) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (404:404:404)) + (PORT datab (113:113:113) (141:141:141)) + (PORT datac (103:103:103) (131:131:131)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (697:697:697)) + (PORT datab (658:658:658) (769:769:769)) + (PORT datac (498:498:498) (576:576:576)) + (PORT datad (819:819:819) (948:948:948)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -19124,14 +9202,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) (DELAY (ABSOLUTE - (PORT dataa (1030:1030:1030) (1169:1169:1169)) - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (326:326:326) (382:382:382)) - (PORT datad (857:857:857) (975:975:975)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (671:671:671) (807:807:807)) + (PORT datab (470:470:470) (541:541:541)) + (PORT datac (1215:1215:1215) (1401:1401:1401)) + (PORT datad (810:810:810) (951:951:951)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19140,15 +9218,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) (DELAY (ABSOLUTE - (PORT dataa (775:775:775) (899:899:899)) - (PORT datab (765:765:765) (935:935:935)) - (PORT datac (608:608:608) (695:695:695)) - (PORT datad (755:755:755) (921:921:921)) + (PORT dataa (344:344:344) (397:397:397)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (546:546:546) (623:623:623)) + (PORT datad (89:89:89) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19156,199 +9234,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (150:150:150)) - (PORT datab (348:348:348) (416:416:416)) - (PORT datad (172:172:172) (204:204:204)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (688:688:688)) - (PORT datab (441:441:441) (509:509:509)) - (PORT datac (298:298:298) (350:350:350)) - (PORT datad (280:280:280) (323:323:323)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (652:652:652)) - (PORT datab (479:479:479) (554:554:554)) - (PORT datac (590:590:590) (701:701:701)) - (PORT datad (698:698:698) (830:830:830)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (440:440:440)) - (PORT datab (514:514:514) (604:604:604)) - (PORT datac (839:839:839) (964:964:964)) - (PORT datad (639:639:639) (733:733:733)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (707:707:707)) - (PORT datab (185:185:185) (226:226:226)) - (PORT datac (295:295:295) (347:347:347)) - (PORT datad (571:571:571) (653:653:653)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT datab (118:118:118) (148:148:148)) - (PORT datac (323:323:323) (377:377:377)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (464:464:464) (541:541:541)) - (PORT datad (318:318:318) (364:364:364)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (858:858:858) (984:984:984)) - (PORT datac (530:530:530) (602:602:602)) - (PORT datad (755:755:755) (865:865:865)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (541:541:541)) - (PORT datab (290:290:290) (336:336:336)) - (PORT datac (434:434:434) (499:499:499)) - (PORT datad (451:451:451) (520:520:520)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (192:192:192)) - (PORT datab (994:994:994) (1134:1134:1134)) - (PORT datac (141:141:141) (181:181:181)) - (PORT datad (664:664:664) (763:763:763)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1114:1114:1114)) - (PORT datab (469:469:469) (546:546:546)) - (PORT datac (471:471:471) (550:550:550)) - (PORT datad (1037:1037:1037) (1237:1237:1237)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1113:1113:1113)) - (PORT datab (972:972:972) (1138:1138:1138)) - (PORT datac (471:471:471) (550:550:550)) - (PORT datad (1216:1216:1216) (1455:1455:1455)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (119:119:119) (154:154:154)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (107:107:107) (126:126:126)) + (PORT dataa (812:812:812) (943:943:943)) + (PORT datab (499:499:499) (576:576:576)) + (PORT datac (731:731:731) (835:835:835)) + (PORT datad (192:192:192) (231:231:231)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -19356,314 +9248,17 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (372:372:372) (408:408:408)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (372:372:372) (408:408:408)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (600:600:600)) - (PORT datab (518:518:518) (605:605:605)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (676:676:676) (752:752:752)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (677:677:677) (753:753:753)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (644:644:644)) - (PORT datab (540:540:540) (626:626:626)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (544:544:544) (600:600:600)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (956:956:956)) - (PORT datab (353:353:353) (415:415:415)) - (PORT datad (951:951:951) (1124:1124:1124)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (989:989:989) (1104:1104:1104)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (1072:1072:1072) (1210:1210:1210)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (411:411:411)) - (PORT datab (268:268:268) (325:325:325)) - (PORT datad (340:340:340) (394:394:394)) + (PORT dataa (687:687:687) (802:802:802)) + (PORT datab (755:755:755) (863:863:863)) + (PORT datac (1012:1012:1012) (1167:1167:1167)) + (PORT datad (191:191:191) (229:229:229)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (906:906:906)) - (PORT asdata (808:808:808) (899:899:899)) - (PORT ena (656:656:656) (724:724:724)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (581:581:581)) - (PORT datab (353:353:353) (417:417:417)) - (PORT datad (675:675:675) (791:791:791)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (472:472:472) (509:509:509)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (583:583:583)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (500:500:500) (586:586:586)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (541:541:541) (608:608:608)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (540:540:540) (606:606:606)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (420:420:420)) - (PORT datab (130:130:130) (177:177:177)) - (PORT datad (338:338:338) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (399:399:399)) - (PORT datab (483:483:483) (574:574:574)) - (PORT datac (308:308:308) (356:356:356)) - (PORT datad (313:313:313) (364:364:364)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19671,119 +9266,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) (DELAY (ABSOLUTE - (PORT dataa (437:437:437) (504:504:504)) - (PORT datab (567:567:567) (664:664:664)) - (PORT datac (465:465:465) (554:554:554)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (637:637:637)) - (PORT datac (531:531:531) (630:630:630)) - (PORT datad (688:688:688) (798:798:798)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (613:613:613) (681:681:681)) - (PORT ena (599:599:599) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (635:635:635)) - (PORT datab (549:549:549) (649:649:649)) - (PORT datac (700:700:700) (828:828:828)) - (PORT datad (608:608:608) (701:701:701)) + (PORT dataa (684:684:684) (791:791:791)) + (PORT datab (541:541:541) (635:635:635)) + (PORT datac (1101:1101:1101) (1257:1257:1257)) + (PORT datad (344:344:344) (408:408:408)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) (DELAY (ABSOLUTE - (PORT dataa (844:844:844) (977:977:977)) - (PORT datab (311:311:311) (365:365:365)) - (PORT datad (300:300:300) (350:350:350)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT datab (539:539:539) (628:628:628)) - (PORT datac (523:523:523) (613:613:613)) - (PORT datad (688:688:688) (798:798:798)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT datab (535:535:535) (624:624:624)) - (PORT datac (521:521:521) (610:610:610)) - (PORT datad (685:685:685) (795:795:795)) + (PORT dataa (368:368:368) (433:433:433)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (948:948:948) (1080:1080:1080)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19792,372 +9298,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (130:130:130) (177:177:177)) - (PORT datad (297:297:297) (342:342:342)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (545:545:545) (615:615:615)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (545:545:545) (615:615:615)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (641:641:641)) - (PORT datab (535:535:535) (621:621:621)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (469:469:469) (514:514:514)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (469:469:469) (514:514:514)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (600:600:600)) - (PORT datab (512:512:512) (598:598:598)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (653:653:653) (724:724:724)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (955:955:955)) - (PORT datab (350:350:350) (412:412:412)) - (PORT datad (948:948:948) (1121:1121:1121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (652:652:652) (723:723:723)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (649:649:649) (720:720:720)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (421:421:421)) - (PORT datab (131:131:131) (180:180:180)) - (PORT datad (335:335:335) (392:392:392)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (358:358:358) (392:392:392)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (581:581:581)) - (PORT datab (522:522:522) (616:616:616)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (663:663:663) (734:734:734)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (655:655:655) (727:727:727)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (300:300:300)) - (PORT datab (269:269:269) (326:326:326)) - (PORT datad (339:339:339) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (657:657:657) (729:729:729)) - (PORT ena (655:655:655) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (637:637:637)) - (PORT datab (716:716:716) (838:838:838)) - (PORT datad (852:852:852) (996:996:996)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (210:210:210)) - (PORT datab (347:347:347) (409:409:409)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (217:217:217)) - (PORT datab (334:334:334) (395:395:395)) - (PORT datac (336:336:336) (395:395:395)) - (PORT datad (329:329:329) (384:384:384)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (518:518:518)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (748:748:748) (857:857:857)) - (PORT datad (309:309:309) (363:363:363)) + (PORT dataa (308:308:308) (360:360:360)) + (PORT datab (630:630:630) (734:734:734)) + (PORT datac (855:855:855) (965:965:965)) + (PORT datad (270:270:270) (310:310:310)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -20165,46 +9312,217 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (458:458:458) (505:505:505)) - (PORT ena (599:599:599) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (INSTANCE z80_\|alu_\|db\[7\]\~9) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (377:377:377)) - (PORT datab (700:700:700) (817:817:817)) - (PORT datad (298:298:298) (343:343:343)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (508:508:508) (604:604:604)) + (PORT datac (501:501:501) (589:589:589)) + (PORT datad (351:351:351) (414:414:414)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (INSTANCE z80_\|address_latch_\|abusz\[14\]) (DELAY (ABSOLUTE - (PORT dataa (129:129:129) (179:179:179)) - (PORT datab (309:309:309) (364:364:364)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (351:351:351) (429:429:429)) + (PORT datac (334:334:334) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (621:621:621)) + (PORT datab (833:833:833) (965:965:965)) + (PORT datac (422:422:422) (483:483:483)) + (PORT datad (520:520:520) (605:605:605)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (368:368:368)) + (PORT datab (547:547:547) (637:637:637)) + (PORT datac (382:382:382) (456:456:456)) + (PORT datad (283:283:283) (324:324:324)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (478:478:478)) + (PORT datab (546:546:546) (636:636:636)) + (PORT datac (353:353:353) (411:411:411)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (800:800:800)) + (PORT datab (547:547:547) (637:637:637)) + (PORT datac (578:578:578) (666:666:666)) + (PORT datad (587:587:587) (666:666:666)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (546:546:546) (638:638:638)) + (PORT datac (94:94:94) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~27) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (902:902:902)) + (PORT datab (506:506:506) (582:582:582)) + (PORT datac (362:362:362) (446:446:446)) + (PORT datad (1001:1001:1001) (1167:1167:1167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT datab (883:883:883) (1040:1040:1040)) + (PORT datac (776:776:776) (912:912:912)) + (PORT datad (600:600:600) (685:685:685)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (753:753:753)) + (PORT datab (336:336:336) (386:386:386)) + (PORT datac (478:478:478) (550:550:550)) + (PORT datad (624:624:624) (706:706:706)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (574:574:574)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (822:822:822) (962:962:962)) + (PORT datac (445:445:445) (510:510:510)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (535:535:535)) + (PORT datad (451:451:451) (518:518:518)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (535:535:535)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (640:640:640) (731:731:731)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (764:764:764)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datad (606:606:606) (688:688:688)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20212,59 +9530,203 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) (DELAY (ABSOLUTE - (PORT dataa (194:194:194) (233:233:233)) - (PORT datac (487:487:487) (571:571:571)) + (PORT dataa (731:731:731) (856:856:856)) + (PORT datab (697:697:697) (805:805:805)) + (PORT datac (557:557:557) (651:651:651)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (400:400:400)) - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (313:313:313) (358:358:358)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (160:160:160)) - (PORT datab (383:383:383) (447:447:447)) - (PORT datac (658:658:658) (761:761:761)) - (PORT datad (1002:1002:1002) (1140:1140:1140)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (516:516:516)) - (PORT datab (614:614:614) (723:723:723)) - (PORT datac (565:565:565) (664:664:664)) - (PORT datad (462:462:462) (517:517:517)) + (PORT dataa (492:492:492) (567:567:567)) + (PORT datab (126:126:126) (159:159:159)) + (PORT datac (487:487:487) (574:574:574)) + (PORT datad (632:632:632) (728:728:728)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~22) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (354:354:354) (416:416:416)) + (PORT datac (892:892:892) (1035:1035:1035)) + (PORT datad (290:290:290) (335:335:335)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1175:1175:1175)) + (PORT datab (1238:1238:1238) (1452:1452:1452)) + (PORT datac (308:308:308) (358:358:358)) + (PORT datad (817:817:817) (949:949:949)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (233:233:233)) + (PORT datab (340:340:340) (402:402:402)) + (PORT datac (107:107:107) (131:131:131)) + (PORT datad (496:496:496) (579:579:579)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1225:1225:1225)) + (PORT datab (613:613:613) (702:702:702)) + (PORT datac (619:619:619) (711:711:711)) + (PORT datad (1078:1078:1078) (1215:1215:1215)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (674:674:674)) + (PORT datab (344:344:344) (397:397:397)) + (PORT datac (863:863:863) (1019:1019:1019)) + (PORT datad (588:588:588) (668:668:668)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (738:738:738)) + (PORT datab (806:806:806) (916:916:916)) + (PORT datac (592:592:592) (674:674:674)) + (PORT datad (859:859:859) (981:981:981)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1155:1155:1155)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (489:489:489) (567:567:567)) + (PORT datad (787:787:787) (890:890:890)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (162:162:162)) + (PORT datab (360:360:360) (425:425:425)) + (PORT datac (505:505:505) (587:587:587)) + (PORT datad (513:513:513) (595:595:595)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (583:583:583)) + (PORT datab (556:556:556) (650:650:650)) + (PORT datac (902:902:902) (1024:1024:1024)) + (PORT datad (351:351:351) (415:415:415)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (583:583:583) (670:670:670)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (572:572:572)) + (PORT datab (341:341:341) (393:393:393)) + (PORT datac (452:452:452) (523:523:523)) + (PORT datad (306:306:306) (345:345:345)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20275,13 +9737,13 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (499:499:499) (582:582:582)) - (PORT datab (487:487:487) (569:569:569)) - (PORT datac (174:174:174) (201:201:201)) - (PORT datad (469:469:469) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (533:533:533) (631:631:631)) + (PORT datab (893:893:893) (1023:1023:1023)) + (PORT datac (635:635:635) (733:733:733)) + (PORT datad (515:515:515) (595:595:595)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -20291,10 +9753,42 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (262:262:262)) - (PORT datab (808:808:808) (941:941:941)) - (PORT datac (573:573:573) (682:682:682)) - (PORT datad (92:92:92) (109:109:109)) + (PORT dataa (355:355:355) (416:416:416)) + (PORT datab (1139:1139:1139) (1318:1318:1318)) + (PORT datac (817:817:817) (943:943:943)) + (PORT datad (503:503:503) (575:575:575)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (638:638:638)) + (PORT datab (672:672:672) (780:780:780)) + (PORT datac (649:649:649) (753:753:753)) + (PORT datad (636:636:636) (726:726:726)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (929:929:929)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datac (804:804:804) (908:908:908)) + (PORT datad (628:628:628) (722:722:722)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -20302,269 +9796,61 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (468:468:468)) + (PORT datab (353:353:353) (427:427:427)) + (PORT datac (941:941:941) (1080:1080:1080)) + (PORT datad (633:633:633) (730:730:730)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (521:521:521)) + (PORT datac (392:392:392) (479:479:479)) + (PORT datad (530:530:530) (636:636:636)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (990:990:990)) + (PORT datab (480:480:480) (559:559:559)) + (PORT datac (842:842:842) (963:963:963)) + (PORT datad (991:991:991) (1128:1128:1128)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (176:176:176) (214:214:214)) - (PORT datab (346:346:346) (409:409:409)) - (PORT datac (281:281:281) (327:327:327)) - (PORT datad (336:336:336) (390:390:390)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (756:756:756)) - (PORT datab (675:675:675) (783:783:783)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (451:451:451) (519:519:519)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (953:953:953) (1066:1066:1066)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (640:640:640) (702:702:702)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (470:470:470) (511:511:511)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (471:471:471) (512:512:512)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (186:186:186)) - (PORT datab (588:588:588) (678:678:678)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (653:653:653) (730:730:730)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (653:653:653) (731:731:731)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (236:236:236) (282:282:282)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (324:324:324) (382:382:382)) - (PORT datac (712:712:712) (815:815:815)) - (PORT datad (625:625:625) (714:714:714)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (345:345:345)) - (PORT datab (619:619:619) (718:718:718)) - (PORT datac (578:578:578) (658:658:658)) - (PORT datad (445:445:445) (514:514:514)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (508:508:508)) - (PORT datab (199:199:199) (240:240:240)) - (PORT datac (570:570:570) (651:651:651)) - (PORT datad (593:593:593) (675:675:675)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (411:411:411)) - (PORT datab (723:723:723) (830:830:830)) - (PORT datac (351:351:351) (427:427:427)) - (PORT datad (630:630:630) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (576:576:576)) - (PORT datab (469:469:469) (549:549:549)) - (PORT datac (607:607:607) (719:719:719)) - (PORT datad (450:450:450) (522:522:522)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (551:551:551)) - (PORT datab (315:315:315) (373:373:373)) - (PORT datac (427:427:427) (490:490:490)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (659:659:659) (771:771:771)) + (PORT datab (706:706:706) (836:836:836)) + (PORT datac (986:986:986) (1183:1183:1183)) + (PORT datad (212:212:212) (251:251:251)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -20574,392 +9860,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~37) + (INSTANCE z80_\|execute_\|ctl_al_we\~4) (DELAY (ABSOLUTE - (PORT dataa (497:497:497) (576:576:576)) - (PORT datab (483:483:483) (564:564:564)) - (PORT datac (432:432:432) (496:496:496)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (574:574:574)) - (PORT datab (477:477:477) (548:548:548)) - (PORT datac (476:476:476) (559:559:559)) - (PORT datad (572:572:572) (659:659:659)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (926:926:926) (1039:1039:1039)) - (PORT ena (495:495:495) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (564:564:564) (658:658:658)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (462:462:462)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datad (288:288:288) (341:341:341)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (915:915:915) (1026:1026:1026)) - (PORT ena (603:603:603) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (927:927:927) (1039:1039:1039)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (911:911:911) (1021:1021:1021)) - (PORT ena (666:666:666) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (457:457:457)) - (PORT datab (372:372:372) (441:441:441)) - (PORT datad (348:348:348) (405:405:405)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (265:265:265)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (769:769:769) (855:855:855)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (770:770:770) (856:856:856)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (390:390:390)) - (PORT datab (515:515:515) (605:605:605)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (367:367:367)) - (PORT datab (427:427:427) (491:491:491)) - (PORT datac (350:350:350) (414:414:414)) - (PORT datad (453:453:453) (526:526:526)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (431:431:431)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (343:343:343) (401:401:401)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (540:540:540)) - (PORT datab (182:182:182) (226:226:226)) - (PORT datac (625:625:625) (730:730:730)) - (PORT datad (375:375:375) (439:439:439)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (346:346:346) (376:376:376)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (945:945:945)) - (PORT datab (424:424:424) (489:489:489)) - (PORT datad (356:356:356) (411:411:411)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (327:327:327) (383:383:383)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (379:379:379) (464:464:464)) - (PORT datad (424:424:424) (487:487:487)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) + (PORT dataa (210:210:210) (251:251:251)) (PORT datab (115:115:115) (143:143:143)) - (PORT datac (669:669:669) (777:777:777)) - (PORT datad (115:115:115) (138:138:138)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (681:681:681)) - (PORT datad (335:335:335) (394:394:394)) + (PORT datac (670:670:670) (771:771:771)) + (PORT datad (200:200:200) (236:236:236)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (761:761:761)) - (PORT datab (492:492:492) (579:579:579)) - (PORT datac (199:199:199) (252:252:252)) - (PORT datad (499:499:499) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20967,427 +9876,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) (DELAY (ABSOLUTE - (PORT datac (206:206:206) (264:264:264)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (1002:1002:1002)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (233:233:233) (288:288:288)) - (PORT datad (164:164:164) (194:194:194)) + (PORT dataa (661:661:661) (759:759:759)) + (PORT datab (1037:1037:1037) (1200:1200:1200)) + (PORT datac (834:834:834) (969:969:969)) + (PORT datad (722:722:722) (846:846:846)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datac (482:482:482) (565:565:565)) - (PORT datad (162:162:162) (189:189:189)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (953:953:953) (1066:1066:1066)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (472:472:472) (512:512:512)) - (PORT ena (619:619:619) (673:673:673)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (736:736:736) (809:809:809)) - (PORT ena (655:655:655) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (638:638:638)) - (PORT datab (713:713:713) (834:834:834)) - (PORT datad (489:489:489) (576:576:576)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (634:634:634) (701:701:701)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (520:520:520) (614:614:614)) - (PORT datad (470:470:470) (552:552:552)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (658:658:658) (736:736:736)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (658:658:658) (736:736:736)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (421:421:421)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (332:332:332) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (649:649:649) (717:717:717)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (736:736:736) (808:808:808)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (295:295:295)) - (PORT datab (269:269:269) (326:326:326)) - (PORT datad (338:338:338) (391:391:391)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (407:407:407)) - (PORT datab (458:458:458) (530:530:530)) - (PORT datac (298:298:298) (341:341:341)) - (PORT datad (298:298:298) (343:343:343)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (756:756:756) (831:831:831)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (575:575:575) (652:652:652)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (643:643:643)) - (PORT datab (537:537:537) (623:623:623)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (649:649:649) (713:713:713)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (956:956:956)) - (PORT datab (352:352:352) (414:414:414)) - (PORT datad (950:950:950) (1123:1123:1123)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (367:367:367) (407:407:407)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (367:367:367) (406:406:406)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (601:601:601)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (497:497:497) (577:577:577)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (411:411:411)) - (PORT datab (358:358:358) (425:425:425)) - (PORT datac (487:487:487) (558:558:558)) - (PORT datad (164:164:164) (193:193:193)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (293:293:293) (336:336:336)) - (PORT datab (206:206:206) (249:249:249)) - (PORT datac (745:745:745) (856:856:856)) - (PORT datad (303:303:303) (349:349:349)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -21396,44 +9892,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (409:409:409)) - (PORT datab (332:332:332) (390:390:390)) - (PORT datad (296:296:296) (340:340:340)) + (PORT dataa (673:673:673) (775:775:775)) + (PORT datac (991:991:991) (1145:1145:1145)) + (PORT datad (624:624:624) (708:708:708)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (218:218:218) (276:276:276)) - (PORT datad (313:313:313) (358:358:358)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21441,545 +9906,137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (INSTANCE z80_\|execute_\|ctl_al_we\~5) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (292:292:292)) - (PORT datab (491:491:491) (578:578:578)) - (PORT datac (217:217:217) (279:279:279)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (998:998:998)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (235:235:235) (289:289:289)) - (PORT datad (184:184:184) (214:214:214)) + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (501:501:501) (580:580:580)) + (PORT datac (323:323:323) (380:380:380)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (867:867:867)) + (PORT datab (1087:1087:1087) (1246:1246:1246)) + (PORT datac (429:429:429) (486:486:486)) + (PORT datad (1156:1156:1156) (1303:1303:1303)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~16) (DELAY (ABSOLUTE - (PORT datac (489:489:489) (573:573:573)) - (PORT datad (170:170:170) (199:199:199)) + (PORT dataa (992:992:992) (1138:1138:1138)) + (PORT datab (984:984:984) (1130:1130:1130)) + (PORT datac (1143:1143:1143) (1336:1336:1336)) + (PORT datad (678:678:678) (791:791:791)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (953:953:953) (1066:1066:1066)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + (PORT datab (964:964:964) (1101:1101:1101)) + (PORT datac (636:636:636) (723:723:723)) + (PORT datad (726:726:726) (833:833:833)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~17) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (289:289:289)) - (PORT datab (490:490:490) (576:576:576)) - (PORT datac (217:217:217) (278:278:278)) - (PORT datad (100:100:100) (121:121:121)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (643:643:643) (762:762:762)) + (PORT datab (301:301:301) (351:351:351)) + (PORT datac (365:365:365) (428:428:428)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (1201:1201:1201) (1360:1360:1360)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (1202:1202:1202) (1362:1362:1362)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (INSTANCE z80_\|execute_\|setM1\~48) (DELAY (ABSOLUTE - (PORT dataa (513:513:513) (600:600:600)) - (PORT datab (516:516:516) (603:603:603)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (1068:1068:1068) (1190:1190:1190)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (958:958:958)) - (PORT datab (357:357:357) (420:420:420)) - (PORT datad (955:955:955) (1130:1130:1130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (511:511:511) (570:570:570)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (513:513:513) (571:571:571)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (642:642:642)) - (PORT datab (537:537:537) (622:622:622)) - (PORT datad (184:184:184) (231:231:231)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (970:970:970) (1085:1085:1085)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (972:972:972) (1087:1087:1087)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (421:421:421)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (333:333:333) (390:390:390)) + (PORT dataa (1028:1028:1028) (1191:1191:1191)) + (PORT datab (626:626:626) (722:722:722)) + (PORT datac (612:612:612) (707:707:707)) + (PORT datad (919:919:919) (1053:1053:1053)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~2) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (1050:1050:1050) (1181:1181:1181)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (622:622:622) (718:718:718)) + (PORT datab (312:312:312) (365:365:365)) + (PORT datac (618:618:618) (700:700:700)) + (PORT datad (120:120:120) (145:145:145)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (1083:1083:1083) (1207:1207:1207)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) + (INSTANCE z80_\|execute_\|ctl_al_we\~6) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (297:297:297)) - (PORT datab (269:269:269) (326:326:326)) - (PORT datad (331:331:331) (384:384:384)) + (PORT dataa (380:380:380) (447:447:447)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (608:608:608) (687:687:687)) + (PORT datad (346:346:346) (411:411:411)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (1084:1084:1084) (1208:1208:1208)) - (PORT ena (655:655:655) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (683:683:683)) - (PORT datab (478:478:478) (554:554:554)) - (PORT datac (435:435:435) (499:499:499)) - (PORT datad (632:632:632) (721:721:721)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (439:439:439)) - (PORT datab (579:579:579) (667:667:667)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (528:528:528) (611:611:611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (637:637:637)) - (PORT datab (714:714:714) (835:835:835)) - (PORT datad (493:493:493) (577:577:577)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (1189:1189:1189) (1340:1340:1340)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (178:178:178)) - (PORT datab (519:519:519) (612:612:612)) - (PORT datad (471:471:471) (553:553:553)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (424:424:424)) - (PORT datab (357:357:357) (426:426:426)) - (PORT datac (337:337:337) (397:397:397)) - (PORT datad (335:335:335) (395:395:395)) - (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (387:387:387)) - (PORT datab (364:364:364) (428:428:428)) - (PORT datac (458:458:458) (533:533:533)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (881:881:881)) - (PORT datab (347:347:347) (417:417:417)) - (PORT datac (289:289:289) (330:330:330)) - (PORT datad (194:194:194) (226:226:226)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (602:602:602) (658:658:658)) - (PORT ena (599:599:599) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (1058:1058:1058)) - (PORT datab (311:311:311) (365:365:365)) - (PORT datad (299:299:299) (350:350:350)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) + (INSTANCE z80_\|execute_\|ctl_al_we\~9) (DELAY (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) (PORT datab (103:103:103) (132:132:132)) - (PORT datac (116:116:116) (158:158:158)) - (PORT datad (297:297:297) (342:342:342)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (297:297:297) (345:345:345)) - (PORT datab (387:387:387) (461:461:461)) - (PORT datac (202:202:202) (259:259:259)) - (PORT datad (333:333:333) (395:395:395)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (313:313:313)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (277:277:277) (318:318:318)) - (PORT datad (832:832:832) (975:975:975)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -21989,25 +10046,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (INSTANCE z80_\|execute_\|ctl_al_we\~10) (DELAY (ABSOLUTE - (PORT datab (492:492:492) (571:571:571)) - (PORT datac (433:433:433) (495:495:495)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (690:690:690) (816:816:816)) + (PORT datab (556:556:556) (644:644:644)) + (PORT datac (326:326:326) (380:380:380)) + (PORT datad (817:817:817) (943:943:943)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) + (INSTANCE z80_\|address_latch_\|Q\[14\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (937:937:937) (1043:1043:1043)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -22019,15 +10080,107 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) (DELAY (ABSOLUTE - (PORT dataa (299:299:299) (347:347:347)) - (PORT datab (388:388:388) (462:462:462)) - (PORT datac (199:199:199) (256:256:256)) - (PORT datad (333:333:333) (395:395:395)) + (PORT dataa (843:843:843) (974:974:974)) + (PORT datab (1442:1442:1442) (1652:1652:1652)) + (PORT datac (529:529:529) (617:617:617)) + (PORT datad (498:498:498) (571:571:571)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (1016:1016:1016)) + (PORT datab (1060:1060:1060) (1278:1278:1278)) + (PORT datac (982:982:982) (1154:1154:1154)) + (PORT datad (846:846:846) (992:992:992)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (559:559:559)) + (PORT datab (529:529:529) (623:623:623)) + (PORT datac (491:491:491) (566:566:566)) + (PORT datad (820:820:820) (946:946:946)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (365:365:365) (434:434:434)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (487:487:487) (559:559:559)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT datac (630:630:630) (727:727:727)) + (PORT datad (583:583:583) (703:703:703)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (280:280:280)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datac (491:491:491) (573:573:573)) + (PORT datad (214:214:214) (277:277:277)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (824:824:824)) + (PORT datab (955:955:955) (1108:1108:1108)) + (PORT datac (632:632:632) (730:730:730)) + (PORT datad (580:580:580) (699:699:699)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22035,209 +10188,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (291:291:291)) - (PORT datad (98:98:98) (120:120:120)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (522:522:522) (585:585:585)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (522:522:522) (585:585:585)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (645:645:645)) - (PORT datab (540:540:540) (627:627:627)) - (PORT datad (116:116:116) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (351:351:351) (388:388:388)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (351:351:351) (388:388:388)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (600:600:600)) - (PORT datab (515:515:515) (601:601:601)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (493:493:493) (573:573:573)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (930:930:930) (1043:1043:1043)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (409:409:409)) - (PORT datab (269:269:269) (326:326:326)) - (PORT datad (332:332:332) (384:384:384)) + (PORT dataa (517:517:517) (623:623:623)) + (PORT datab (389:389:389) (464:464:464)) + (PORT datac (821:821:821) (963:963:963)) + (PORT datad (832:832:832) (970:970:970)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) (DELAY (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (929:929:929) (1041:1041:1041)) - (PORT ena (655:655:655) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (835:835:835) (957:957:957)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (764:764:764) (876:876:876)) + (PORT datad (588:588:588) (670:670:670)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (INSTANCE z80_\|pla_decode_\|Equal62\~3) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (704:704:704)) - (PORT datab (389:389:389) (460:460:460)) - (PORT datac (601:601:601) (681:681:681)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (238:238:238) (306:306:306)) + (PORT datab (1156:1156:1156) (1354:1354:1354)) + (PORT datac (632:632:632) (730:730:730)) + (PORT datad (581:581:581) (700:700:700)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -22246,16 +10236,236 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) (DELAY (ABSOLUTE - (PORT dataa (671:671:671) (799:799:799)) - (PORT datab (441:441:441) (511:511:511)) - (PORT datac (451:451:451) (523:523:523)) - (PORT datad (426:426:426) (487:487:487)) + (PORT dataa (138:138:138) (178:178:178)) + (PORT datab (462:462:462) (532:532:532)) + (PORT datac (838:838:838) (966:966:966)) + (PORT datad (601:601:601) (697:697:697)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (491:491:491) (577:577:577)) + (PORT datac (351:351:351) (401:401:401)) + (PORT datad (329:329:329) (381:381:381)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (356:356:356)) + (PORT datab (550:550:550) (623:623:623)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (99:99:99) (120:120:120)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (741:741:741)) + (PORT datab (382:382:382) (458:458:458)) + (PORT datac (868:868:868) (983:983:983)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (916:916:916)) + (PORT datab (645:645:645) (768:768:768)) + (PORT datac (655:655:655) (767:767:767)) + (PORT datad (1007:1007:1007) (1134:1134:1134)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT datab (873:873:873) (1024:1024:1024)) + (PORT datac (876:876:876) (1042:1042:1042)) + (PORT datad (357:357:357) (418:418:418)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (422:422:422)) + (PORT datab (747:747:747) (852:852:852)) + (PORT datac (543:543:543) (619:619:619)) + (PORT datad (163:163:163) (190:190:190)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (109:109:109) (139:139:139)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (1074:1074:1074)) + (PORT datab (747:747:747) (850:850:850)) + (PORT datac (752:752:752) (856:856:856)) + (PORT datad (699:699:699) (825:825:825)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (404:404:404)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (334:334:334) (383:383:383)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (595:595:595)) + (PORT datab (695:695:695) (803:803:803)) + (PORT datac (482:482:482) (559:559:559)) + (PORT datad (332:332:332) (387:387:387)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (927:927:927)) + (PORT datab (361:361:361) (424:424:424)) + (PORT datac (660:660:660) (773:773:773)) + (PORT datad (740:740:740) (838:838:838)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1556:1556:1556)) + (PORT datab (556:556:556) (656:656:656)) + (PORT datac (841:841:841) (961:961:961)) + (PORT datad (638:638:638) (752:752:752)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (805:805:805)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (783:783:783) (896:896:896)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (518:518:518) (601:601:601)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (774:774:774) (874:874:874)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -22265,12 +10475,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (805:805:805)) - (PORT datab (529:529:529) (631:631:631)) - (PORT datac (350:350:350) (413:413:413)) - (PORT datad (771:771:771) (922:922:922)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (525:525:525) (620:620:620)) + (PORT datab (1062:1062:1062) (1261:1261:1261)) + (PORT datac (521:521:521) (606:606:606)) + (PORT datad (387:387:387) (481:481:481)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22281,10 +10491,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (222:222:222)) - (PORT datab (498:498:498) (583:583:583)) - (PORT datac (341:341:341) (395:395:395)) - (PORT datad (521:521:521) (607:607:607)) + (PORT dataa (501:501:501) (585:585:585)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (516:516:516) (610:610:610)) + (PORT datad (759:759:759) (865:865:865)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -22292,206 +10502,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (605:605:605)) - (PORT datab (155:155:155) (200:200:200)) - (PORT datad (459:459:459) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datab (156:156:156) (200:200:200)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1311:1311:1311)) - (PORT datac (590:590:590) (673:673:673)) - (PORT datad (754:754:754) (917:917:917)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (572:572:572)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (491:491:491) (574:574:574)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datac (375:375:375) (459:459:459)) - (PORT datad (486:486:486) (579:579:579)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (753:753:753) (857:857:857)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (1015:1015:1015)) - (PORT datab (893:893:893) (1054:1054:1054)) - (PORT datac (473:473:473) (551:551:551)) - (PORT datad (217:217:217) (270:270:270)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (301:301:301)) - (PORT datab (309:309:309) (361:361:361)) - (PORT datac (476:476:476) (562:562:562)) - (PORT datad (128:128:128) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (341:341:341) (368:368:368)) - (PORT ena (779:779:779) (853:853:853)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (395:395:395)) - (PORT datab (614:614:614) (705:705:705)) - (PORT datad (450:450:450) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (396:396:396)) - (PORT datab (724:724:724) (832:832:832)) - (PORT datac (111:111:111) (136:136:136)) - (PORT datad (446:446:446) (519:519:519)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (136:136:136) (173:173:173)) - (PORT datad (179:179:179) (211:211:211)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (239:239:239)) - (PORT datab (552:552:552) (652:652:652)) - (PORT datac (924:924:924) (1078:1078:1078)) - (PORT datad (662:662:662) (759:759:759)) + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (630:630:630) (722:722:722)) + (PORT datac (722:722:722) (870:870:870)) + (PORT datad (502:502:502) (578:578:578)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -22501,42 +10520,180 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (308:308:308) (361:361:361)) - (PORT datac (499:499:499) (582:582:582)) - (PORT datad (459:459:459) (528:528:528)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (972:972:972) (1130:1130:1130)) + (PORT datab (780:780:780) (898:898:898)) + (PORT datac (333:333:333) (391:391:391)) + (PORT datad (485:485:485) (556:556:556)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (584:584:584)) + (PORT datab (779:779:779) (897:897:897)) + (PORT datac (474:474:474) (546:546:546)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (1185:1185:1185)) + (PORT datab (891:891:891) (1054:1054:1054)) + (PORT datad (115:115:115) (132:132:132)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (731:731:731)) + (PORT datab (1235:1235:1235) (1413:1413:1413)) + (PORT datac (621:621:621) (716:716:716)) + (PORT datad (1134:1134:1134) (1334:1334:1334)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (731:731:731)) + (PORT datab (671:671:671) (780:780:780)) + (PORT datac (622:622:622) (717:717:717)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (537:537:537)) + (PORT datab (192:192:192) (230:230:230)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (113:113:113) (134:134:134)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (253:253:253)) + (PORT datab (1206:1206:1206) (1370:1370:1370)) + (PORT datac (672:672:672) (783:783:783)) + (PORT datad (764:764:764) (872:872:872)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (224:224:224)) + (PORT datab (742:742:742) (852:852:852)) + (PORT datac (185:185:185) (216:216:216)) + (PORT datad (501:501:501) (575:575:575)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (933:933:933)) + (PORT datab (441:441:441) (517:517:517)) + (PORT datac (296:296:296) (340:340:340)) + (PORT datad (498:498:498) (573:573:573)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (622:622:622)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) (DELAY (ABSOLUTE - (PORT datab (315:315:315) (370:370:370)) - (PORT datac (137:137:137) (176:176:176)) - (PORT datad (461:461:461) (530:530:530)) + (PORT dataa (804:804:804) (927:927:927)) + (PORT datab (447:447:447) (524:524:524)) + (PORT datad (499:499:499) (590:590:590)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) + (PORT clk (908:908:908) (896:896:896)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (407:407:407) (424:424:424)) + (PORT ena (409:409:409) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22550,324 +10707,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT dataa (481:481:481) (557:557:557)) - (PORT datab (547:547:547) (646:646:646)) - (PORT datac (928:928:928) (1083:1083:1083)) - (PORT datad (654:654:654) (751:751:751)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (614:614:614)) - (PORT datab (610:610:610) (732:732:732)) - (PORT datac (474:474:474) (556:556:556)) - (PORT datad (346:346:346) (402:402:402)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (431:431:431)) - (PORT datab (355:355:355) (421:421:421)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (507:507:507) (592:592:592)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (427:427:427)) - (PORT datab (354:354:354) (418:418:418)) - (PORT datac (337:337:337) (402:402:402)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (964:964:964)) - (PORT datab (511:511:511) (591:591:591)) - (PORT datac (303:303:303) (350:350:350)) - (PORT datad (876:876:876) (1035:1035:1035)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (564:564:564)) - (PORT datab (548:548:548) (636:636:636)) - (PORT datac (765:765:765) (869:869:869)) - (PORT datad (353:353:353) (410:410:410)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (815:815:815)) - (PORT datab (337:337:337) (396:396:396)) - (PORT datac (822:822:822) (942:942:942)) - (PORT datad (335:335:335) (384:384:384)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (777:777:777)) - (PORT datab (682:682:682) (798:798:798)) - (PORT datac (484:484:484) (566:566:566)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (815:815:815)) - (PORT datab (720:720:720) (841:841:841)) - (PORT datac (1206:1206:1206) (1403:1403:1403)) - (PORT datad (815:815:815) (940:940:940)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (231:231:231)) - (PORT datab (348:348:348) (404:404:404)) - (PORT datac (183:183:183) (213:213:213)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (114:114:114) (141:141:141)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (224:224:224)) - (PORT datab (172:172:172) (210:210:210)) - (PORT datac (461:461:461) (531:531:531)) - (PORT datad (322:322:322) (378:378:378)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (163:163:163)) - (PORT datab (464:464:464) (531:531:531)) - (PORT datac (186:186:186) (225:225:225)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (599:599:599)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (330:330:330) (386:386:386)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (843:843:843)) - (PORT datab (360:360:360) (425:425:425)) - (PORT datac (344:344:344) (406:406:406)) - (PORT datad (507:507:507) (592:592:592)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (336:336:336) (400:400:400)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (420:420:420)) - (PORT datab (131:131:131) (160:160:160)) - (PORT datac (443:443:443) (514:514:514)) - (PORT datad (447:447:447) (513:513:513)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (293:293:293)) - (PORT datab (468:468:468) (544:544:544)) - (PORT datac (326:326:326) (379:379:379)) - (PORT datad (291:291:291) (339:339:339)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (758:758:758)) - (PORT datab (296:296:296) (343:343:343)) - (PORT datac (463:463:463) (537:537:537)) - (PORT datad (1005:1005:1005) (1179:1179:1179)) + (PORT dataa (943:943:943) (1084:1084:1084)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (1153:1153:1153) (1353:1353:1353)) + (PORT datad (115:115:115) (131:131:131)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -22875,1359 +10718,27 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (760:760:760)) - (PORT datab (295:295:295) (341:341:341)) - (PORT datac (461:461:461) (534:534:534)) - (PORT datad (1006:1006:1006) (1180:1180:1180)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (168:168:168)) - (PORT datab (288:288:288) (331:331:331)) - (PORT datac (123:123:123) (148:148:148)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (147:147:147)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (113:113:113) (142:142:142)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (437:437:437) (506:506:506)) - (PORT datac (290:290:290) (336:336:336)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) - (PORT asdata (353:353:353) (386:386:386)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (671:671:671)) - (PORT datab (352:352:352) (416:416:416)) - (PORT datac (339:339:339) (401:401:401)) - (PORT datad (311:311:311) (356:356:356)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datac (335:335:335) (399:399:399)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (668:668:668)) - (PORT datab (894:894:894) (1055:1055:1055)) - (PORT datac (472:472:472) (550:550:550)) - (PORT datad (225:225:225) (283:283:283)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (141:141:141)) - (PORT datac (389:389:389) (477:477:477)) - (PORT datad (483:483:483) (569:569:569)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (565:565:565)) - (PORT datab (777:777:777) (891:891:891)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (306:306:306)) - (PORT datab (145:145:145) (184:184:184)) - (PORT datad (317:317:317) (375:375:375)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (553:553:553)) - (PORT datab (459:459:459) (554:554:554)) - (PORT datac (324:324:324) (380:380:380)) - (PORT datad (332:332:332) (388:388:388)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (465:465:465) (545:545:545)) - (PORT datad (348:348:348) (402:402:402)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (989:989:989) (1119:1119:1119)) - (PORT ena (782:782:782) (860:860:860)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (989:989:989) (1119:1119:1119)) - (PORT ena (797:797:797) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (599:599:599)) - (PORT datab (510:510:510) (596:596:596)) - (PORT datad (115:115:115) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT asdata (957:957:957) (1082:1082:1082)) - (PORT ena (820:820:820) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (627:627:627) (733:733:733)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (778:778:778) (844:844:844)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (644:644:644)) - (PORT datab (539:539:539) (625:625:625)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (803:803:803) (907:907:907)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (958:958:958)) - (PORT datab (359:359:359) (421:421:421)) - (PORT datad (956:956:956) (1131:1131:1131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (513:513:513) (563:563:563)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (511:511:511) (561:561:561)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (581:581:581)) - (PORT datab (521:521:521) (614:614:614)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (670:670:670) (762:762:762)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (806:806:806) (913:913:913)) - (PORT ena (619:619:619) (665:665:665)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (409:409:409)) - (PORT datab (242:242:242) (306:306:306)) - (PORT datad (341:341:341) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (808:808:808) (916:916:916)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (808:808:808) (915:915:915)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (419:419:419)) - (PORT datab (128:128:128) (175:175:175)) - (PORT datad (340:340:340) (398:398:398)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (803:803:803) (910:910:910)) - (PORT ena (655:655:655) (718:718:718)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (637:637:637)) - (PORT datab (715:715:715) (837:837:837)) - (PORT datad (477:477:477) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (231:231:231)) - (PORT datab (486:486:486) (585:585:585)) - (PORT datac (318:318:318) (373:373:373)) - (PORT datad (436:436:436) (502:502:502)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (355:355:355)) - (PORT datab (459:459:459) (526:526:526)) - (PORT datac (343:343:343) (395:395:395)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT datab (488:488:488) (566:566:566)) - (PORT datad (477:477:477) (534:534:534)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (937:937:937) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (288:288:288)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datac (305:305:305) (364:364:364)) - (PORT datad (369:369:369) (437:437:437)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (401:401:401) (443:443:443)) - (PORT ena (619:619:619) (673:673:673)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (330:330:330) (388:388:388)) - (PORT datad (302:302:302) (346:346:346)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (281:281:281) (300:300:300)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (323:323:323) (379:379:379)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (213:213:213) (266:266:266)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (997:997:997)) - (PORT datab (280:280:280) (327:327:327)) - (PORT datac (234:234:234) (289:289:289)) - (PORT datad (184:184:184) (215:215:215)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (758:758:758) (871:871:871)) - (PORT datac (225:225:225) (269:269:269)) - (PORT datad (110:110:110) (131:131:131)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (664:664:664)) - (PORT datab (476:476:476) (552:552:552)) - (PORT datac (762:762:762) (883:883:883)) - (PORT datad (569:569:569) (656:656:656)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (445:445:445)) - (PORT datab (575:575:575) (663:663:663)) - (PORT datac (545:545:545) (642:642:642)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (407:407:407) (496:496:496)) - (PORT datac (104:104:104) (127:127:127)) - (PORT datad (123:123:123) (142:142:142)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (593:593:593)) - (PORT datac (764:764:764) (877:877:877)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (404:404:404)) - (PORT datab (222:222:222) (276:276:276)) - (PORT datac (477:477:477) (564:564:564)) - (PORT datad (133:133:133) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (422:422:422)) - (PORT datab (471:471:471) (543:543:543)) - (PORT datac (1125:1125:1125) (1310:1310:1310)) - (PORT datad (476:476:476) (574:574:574)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (257:257:257)) - (PORT datab (725:725:725) (832:832:832)) - (PORT datac (328:328:328) (384:384:384)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (556:556:556)) - (PORT datab (182:182:182) (224:224:224)) - (PORT datac (319:319:319) (376:376:376)) - (PORT datad (338:338:338) (393:393:393)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (591:591:591)) - (PORT datab (316:316:316) (370:370:370)) - (PORT datac (104:104:104) (126:126:126)) - (PORT datad (425:425:425) (492:492:492)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (449:449:449)) - (PORT datab (486:486:486) (567:567:567)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (115:115:115) (139:139:139)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (638:638:638)) - (PORT datab (709:709:709) (830:830:830)) - (PORT datad (772:772:772) (906:906:906)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (787:787:787) (866:866:866)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (470:470:470) (517:517:517)) - (PORT ena (619:619:619) (666:666:666)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (179:179:179)) - (PORT datab (522:522:522) (616:616:616)) - (PORT datad (468:468:468) (549:549:549)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (522:522:522) (582:582:582)) - (PORT ena (606:606:606) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (523:523:523) (583:583:583)) - (PORT ena (631:631:631) (686:686:686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (421:421:421)) - (PORT datab (197:197:197) (255:255:255)) - (PORT datad (331:331:331) (388:388:388)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (583:583:583) (662:662:662)) - (PORT datad (168:168:168) (197:197:197)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (655:655:655) (727:727:727)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (957:957:957)) - (PORT datab (357:357:357) (419:419:419)) - (PORT datad (954:954:954) (1129:1129:1129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (498:498:498)) - (PORT datab (488:488:488) (569:569:569)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (375:375:375)) - (PORT datab (351:351:351) (420:420:420)) - (PORT datac (747:747:747) (856:856:856)) - (PORT datad (198:198:198) (230:230:230)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (444:444:444) (486:486:486)) - (PORT ena (599:599:599) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (352:352:352)) - (PORT datab (330:330:330) (387:387:387)) - (PORT datac (227:227:227) (287:287:287)) - (PORT datad (303:303:303) (347:347:347)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (300:300:300)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (312:312:312) (357:357:357)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (995:995:995)) - (PORT datab (304:304:304) (350:350:350)) - (PORT datac (235:235:235) (290:290:290)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (490:490:490) (568:568:568)) - (PORT datac (401:401:401) (453:453:453)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (937:937:937) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datab (384:384:384) (458:458:458)) - (PORT datac (206:206:206) (261:261:261)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (534:534:534)) - (PORT datad (474:474:474) (548:548:548)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) - (PORT ena (937:937:937) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (738:738:738)) - (PORT datab (208:208:208) (269:269:269)) - (PORT datac (360:360:360) (424:424:424)) - (PORT datad (637:637:637) (734:734:734)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (138:138:138)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datac (288:288:288) (347:347:347)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (1001:1001:1001)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (234:234:234) (289:289:289)) - (PORT datad (276:276:276) (314:314:314)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (383:383:383)) - (PORT datab (211:211:211) (253:253:253)) - (PORT datac (747:747:747) (856:856:856)) - (PORT datad (295:295:295) (332:332:332)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (779:779:779)) - (PORT datab (478:478:478) (554:554:554)) - (PORT datac (305:305:305) (346:346:346)) - (PORT datad (569:569:569) (654:654:654)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (443:443:443)) - (PORT datab (577:577:577) (664:664:664)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (463:463:463) (544:544:544)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (284:284:284)) - (PORT datab (1036:1036:1036) (1196:1196:1196)) - (PORT datac (593:593:593) (688:688:688)) - (PORT datad (134:134:134) (174:174:174)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (515:515:515)) - (PORT datab (196:196:196) (231:231:231)) - (PORT datac (139:139:139) (178:178:178)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (248:248:248)) - (PORT datab (314:314:314) (369:369:369)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (461:461:461) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (248:248:248)) - (PORT datab (153:153:153) (196:196:196)) - (PORT datad (460:460:460) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (445:445:445) (522:522:522)) + (PORT datac (296:296:296) (340:340:340)) + (PORT datad (501:501:501) (592:592:592)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (444:444:444) (521:521:521)) + (PORT datad (503:503:503) (593:593:593)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24238,9 +10749,9 @@ (INSTANCE z80_\|alu_\|op1_high\[3\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) + (PORT clk (908:908:908) (896:896:896)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24251,29 +10762,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) (DELAY (ABSOLUTE - (PORT dataa (459:459:459) (549:549:549)) - (PORT datab (378:378:378) (464:464:464)) - (PORT datad (471:471:471) (548:548:548)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (425:425:425)) - (PORT datab (308:308:308) (360:360:360)) - (PORT datac (137:137:137) (175:175:175)) - (PORT datad (295:295:295) (344:344:344)) + (PORT dataa (499:499:499) (581:581:581)) + (PORT datab (686:686:686) (808:808:808)) + (PORT datac (1067:1067:1067) (1229:1229:1229)) + (PORT datad (501:501:501) (592:592:592)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24281,274 +10778,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) (DELAY (ABSOLUTE - (PORT datab (475:475:475) (553:553:553)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (356:356:356)) - (PORT datab (385:385:385) (472:472:472)) - (PORT datac (540:540:540) (649:649:649)) - (PORT datad (569:569:569) (671:671:671)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (425:425:425)) - (PORT datab (328:328:328) (380:380:380)) - (PORT datac (338:338:338) (403:403:403)) - (PORT datad (191:191:191) (226:226:226)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (304:304:304)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (270:270:270) (309:309:309)) - (PORT datad (217:217:217) (269:269:269)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (281:281:281)) - (PORT datab (591:591:591) (689:689:689)) - (PORT datac (420:420:420) (500:500:500)) - (PORT datad (329:329:329) (386:386:386)) + (PORT dataa (604:604:604) (692:692:692)) + (PORT datab (372:372:372) (439:439:439)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (435:435:435) (497:497:497)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (227:227:227)) - (PORT datab (670:670:670) (793:793:793)) - (PORT datac (370:370:370) (448:448:448)) - (PORT datad (473:473:473) (550:550:550)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (194:194:194) (235:235:235)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (384:384:384)) - (PORT datab (112:112:112) (145:145:145)) - (PORT datac (311:311:311) (362:362:362)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (260:260:260)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (171:171:171) (198:198:198)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT datab (356:356:356) (415:415:415)) - (PORT datac (436:436:436) (502:502:502)) - (PORT datad (355:355:355) (411:411:411)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (518:518:518)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (363:363:363) (418:418:418)) - (PORT datac (451:451:451) (524:524:524)) - (PORT datad (506:506:506) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (618:618:618)) - (PORT datab (115:115:115) (148:148:148)) - (PORT datac (284:284:284) (326:326:326)) - (PORT datad (687:687:687) (802:802:802)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (826:826:826)) - (PORT datab (1281:1281:1281) (1480:1480:1480)) - (PORT datac (672:672:672) (779:779:779)) - (PORT datad (738:738:738) (836:836:836)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (361:361:361)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (698:698:698) (816:816:816)) - (PORT datad (528:528:528) (611:611:611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (321:321:321)) - (PORT datab (460:460:460) (531:531:531)) - (PORT datac (282:282:282) (331:331:331)) - (PORT datad (334:334:334) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -24557,27 +10794,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) (DELAY (ABSOLUTE - (PORT datab (455:455:455) (532:532:532)) - (PORT datac (437:437:437) (490:490:490)) - (PORT datad (659:659:659) (761:761:761)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1179:1179:1179)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (1055:1055:1055) (1237:1237:1237)) - (PORT datad (916:916:916) (1089:1089:1089)) + (PORT dataa (935:935:935) (1099:1099:1099)) + (PORT datab (616:616:616) (730:730:730)) + (PORT datac (339:339:339) (401:401:401)) + (PORT datad (376:376:376) (450:450:450)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -24587,352 +10810,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (946:946:946) (1091:1091:1091)) - (PORT datac (777:777:777) (894:894:894)) - (PORT datad (1279:1279:1279) (1482:1482:1482)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (201:201:201)) - (PORT datab (1036:1036:1036) (1196:1196:1196)) - (PORT datac (580:580:580) (677:677:677)) - (PORT datad (135:135:135) (175:175:175)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (198:198:198)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (507:507:507) (603:603:603)) - (PORT datac (613:613:613) (710:710:710)) - (PORT datad (339:339:339) (392:392:392)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (1014:1014:1014)) - (PORT datab (523:523:523) (610:610:610)) - (PORT datac (555:555:555) (636:636:636)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (415:415:415)) - (PORT datab (154:154:154) (199:199:199)) - (PORT datac (106:106:106) (130:130:130)) - (PORT datad (289:289:289) (338:338:338)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (473:473:473) (551:551:551)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (306:306:306)) - (PORT datab (893:893:893) (1054:1054:1054)) - (PORT datac (474:474:474) (552:552:552)) - (PORT datad (314:314:314) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (346:346:346) (377:377:377)) - (PORT ena (805:805:805) (893:893:893)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (303:303:303)) - (PORT datab (308:308:308) (360:360:360)) - (PORT datac (475:475:475) (562:562:562)) - (PORT datad (130:130:130) (159:159:159)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (555:555:555)) - (PORT datab (185:185:185) (221:221:221)) - (PORT datad (328:328:328) (378:378:378)) + (PORT dataa (500:500:500) (584:584:584)) + (PORT datab (318:318:318) (366:366:366)) + (PORT datac (1096:1096:1096) (1250:1250:1250)) + (PORT datad (347:347:347) (410:410:410)) (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (514:514:514)) - (PORT datab (350:350:350) (415:415:415)) - (PORT datac (306:306:306) (352:352:352)) - (PORT datad (178:178:178) (201:201:201)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (595:595:595)) - (PORT datab (607:607:607) (728:728:728)) - (PORT datac (311:311:311) (375:375:375)) - (PORT datad (340:340:340) (396:396:396)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (429:429:429)) - (PORT datab (555:555:555) (653:653:653)) - (PORT datac (336:336:336) (401:401:401)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (425:425:425)) - (PORT datab (352:352:352) (415:415:415)) - (PORT datac (310:310:310) (351:351:351)) - (PORT datad (540:540:540) (628:628:628)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (337:337:337) (401:401:401)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (305:305:305)) - (PORT datab (306:306:306) (363:363:363)) - (PORT datac (233:233:233) (296:296:296)) - (PORT datad (451:451:451) (522:522:522)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (174:174:174)) - (PORT datab (286:286:286) (329:329:329)) - (PORT datac (293:293:293) (345:345:345)) - (PORT datad (590:590:590) (679:679:679)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -24942,72 +10829,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) (DELAY (ABSOLUTE - (PORT dataa (464:464:464) (541:541:541)) - (PORT datab (586:586:586) (668:668:668)) - (PORT datac (434:434:434) (500:500:500)) - (PORT datad (419:419:419) (477:477:477)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT datab (118:118:118) (153:153:153)) - (PORT datac (114:114:114) (141:141:141)) - (PORT datad (451:451:451) (520:520:520)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (146:146:146)) - (PORT datab (120:120:120) (155:155:155)) - (PORT datac (116:116:116) (143:143:143)) - (PORT datad (451:451:451) (520:520:520)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (955:955:955)) - (PORT datab (795:795:795) (918:918:918)) - (PORT datac (1012:1012:1012) (1144:1144:1144)) - (PORT datad (735:735:735) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (697:697:697)) - (PORT datab (756:756:756) (881:881:881)) - (PORT datac (430:430:430) (491:491:491)) - (PORT datad (727:727:727) (829:829:829)) + (PORT dataa (391:391:391) (476:476:476)) + (PORT datab (880:880:880) (1044:1044:1044)) + (PORT datac (864:864:864) (1027:1027:1027)) + (PORT datad (855:855:855) (1001:1001:1001)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -25017,235 +10842,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) (DELAY (ABSOLUTE - (PORT dataa (1083:1083:1083) (1265:1265:1265)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (1090:1090:1090) (1265:1265:1265)) - (PORT datad (914:914:914) (1045:1045:1045)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (704:704:704)) - (PORT datab (187:187:187) (226:226:226)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (456:456:456) (522:522:522)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datac (269:269:269) (308:308:308)) - (PORT datad (310:310:310) (358:358:358)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (993:993:993) (1133:1133:1133)) - (PORT datac (651:651:651) (747:747:747)) - (PORT datad (791:791:791) (905:905:905)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (192:192:192)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (141:141:141) (181:181:181)) - (PORT datad (664:664:664) (763:763:763)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1240:1240:1240) (1467:1467:1467)) - (PORT datab (893:893:893) (1057:1057:1057)) - (PORT datac (981:981:981) (1155:1155:1155)) - (PORT datad (462:462:462) (535:535:535)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (1060:1060:1060) (1233:1233:1233)) - (PORT datac (328:328:328) (384:384:384)) - (PORT datad (517:517:517) (606:606:606)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1180:1180:1180)) - (PORT datab (785:785:785) (892:892:892)) - (PORT datac (782:782:782) (903:903:903)) - (PORT datad (1334:1334:1334) (1550:1550:1550)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (1007:1007:1007)) - (PORT datab (672:672:672) (775:775:775)) - (PORT datac (780:780:780) (900:900:900)) - (PORT datad (918:918:918) (1053:1053:1053)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (922:922:922)) - (PORT datab (374:374:374) (448:448:448)) - (PORT datac (653:653:653) (755:755:755)) - (PORT datad (932:932:932) (1070:1070:1070)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (404:404:404)) - (PORT datab (1134:1134:1134) (1320:1320:1320)) - (PORT datac (871:871:871) (1027:1027:1027)) - (PORT datad (1334:1334:1334) (1550:1550:1550)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (1010:1010:1010)) - (PORT datab (368:368:368) (442:442:442)) - (PORT datac (879:879:879) (1020:1020:1020)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (373:373:373) (447:447:447)) - (PORT datac (1129:1129:1129) (1286:1286:1286)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (215:215:215)) - (PORT datab (189:189:189) (228:228:228)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (491:491:491) (564:564:564)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (419:419:419)) - (PORT datab (341:341:341) (408:408:408)) - (PORT datac (646:646:646) (743:743:743)) - (PORT datad (189:189:189) (221:221:221)) + (PORT dataa (487:487:487) (584:584:584)) + (PORT datab (580:580:580) (664:664:664)) + (PORT datac (405:405:405) (471:471:471)) + (PORT datad (472:472:472) (568:568:568)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25255,29 +10858,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (597:597:597)) - (PORT datab (114:114:114) (143:143:143)) - (PORT datac (746:746:746) (862:862:862)) - (PORT datad (332:332:332) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (421:421:421)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (642:642:642) (738:738:738)) + (PORT dataa (174:174:174) (217:217:217)) + (PORT datab (314:314:314) (368:368:368)) + (PORT datac (285:285:285) (328:328:328)) + (PORT datad (765:765:765) (895:895:895)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25287,109 +10874,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (397:397:397)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (314:314:314) (361:361:361)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (955:955:955)) - (PORT datab (795:795:795) (918:918:918)) - (PORT datac (564:564:564) (650:650:650)) - (PORT datad (734:734:734) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (500:500:500) (586:586:586)) - (PORT datac (514:514:514) (596:596:596)) - (PORT datad (1268:1268:1268) (1457:1457:1457)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (875:875:875)) - (PORT datab (713:713:713) (832:832:832)) - (PORT datac (515:515:515) (598:598:598)) - (PORT datad (644:644:644) (745:745:745)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (895:895:895)) - (PORT datab (551:551:551) (639:639:639)) - (PORT datac (196:196:196) (229:229:229)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (228:228:228)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (271:271:271) (304:304:304)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (540:540:540)) - (PORT datab (347:347:347) (406:406:406)) - (PORT datac (173:173:173) (208:208:208)) - (PORT datad (95:95:95) (115:115:115)) + (PORT dataa (1089:1089:1089) (1307:1307:1307)) + (PORT datab (863:863:863) (1020:1020:1020)) + (PORT datac (440:440:440) (502:502:502)) + (PORT datad (1027:1027:1027) (1186:1186:1186)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25399,13 +10890,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (INSTANCE z80_\|pla_decode_\|Equal21\~2) (DELAY (ABSOLUTE - (PORT dataa (458:458:458) (528:528:528)) - (PORT datab (348:348:348) (408:408:408)) - (PORT datac (441:441:441) (496:496:496)) - (PORT datad (704:704:704) (823:823:823)) + (PORT datab (794:794:794) (920:920:920)) + (PORT datac (117:117:117) (145:145:145)) + (PORT datad (552:552:552) (658:658:658)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (547:547:547)) + (PORT datab (527:527:527) (622:622:622)) + (PORT datac (1070:1070:1070) (1232:1232:1232)) + (PORT datad (667:667:667) (795:795:795)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25415,27 +10920,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (421:421:421)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (288:288:288) (334:334:334)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (316:316:316) (366:366:366)) + (PORT dataa (603:603:603) (693:693:693)) + (PORT datab (503:503:503) (600:600:600)) + (PORT datac (201:201:201) (241:241:241)) + (PORT datad (331:331:331) (386:386:386)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25445,3191 +10936,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (INSTANCE z80_\|execute_\|ctl_alu_op_low) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (318:318:318)) - (PORT datab (894:894:894) (1054:1054:1054)) - (PORT datac (556:556:556) (666:666:666)) - (PORT datad (463:463:463) (540:540:540)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (480:480:480)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (106:106:106) (125:125:125)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (435:435:435)) - (PORT datab (768:768:768) (882:882:882)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (404:404:404)) - (PORT datab (222:222:222) (276:276:276)) - (PORT datac (477:477:477) (564:564:564)) - (PORT datad (132:132:132) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (553:553:553)) - (PORT datab (722:722:722) (829:829:829)) - (PORT datac (453:453:453) (538:538:538)) - (PORT datad (430:430:430) (496:496:496)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (554:554:554)) - (PORT datab (183:183:183) (221:221:221)) - (PORT datac (305:305:305) (350:350:350)) - (PORT datad (340:340:340) (394:394:394)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (415:415:415)) - (PORT datab (155:155:155) (199:199:199)) - (PORT datad (459:459:459) (527:527:527)) + (PORT dataa (366:366:366) (436:436:436)) + (PORT datab (490:490:490) (573:573:573)) + (PORT datac (855:855:855) (969:969:969)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (583:583:583) (691:691:691)) - (PORT datac (556:556:556) (666:666:666)) - (PORT datad (314:314:314) (381:381:381)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (304:304:304)) - (PORT datab (306:306:306) (364:364:364)) - (PORT datac (233:233:233) (296:296:296)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (468:468:468) (543:543:543)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (319:319:319) (368:368:368)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (172:172:172)) - (PORT datab (136:136:136) (167:167:167)) - (PORT datac (272:272:272) (309:309:309)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (263:263:263)) - (PORT datab (201:201:201) (238:238:238)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (173:173:173) (201:201:201)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (314:314:314) (365:365:365)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (324:324:324) (381:381:381)) - (PORT datac (96:96:96) (122:122:122)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (293:293:293) (312:312:312)) - (PORT ena (805:805:805) (893:893:893)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (255:255:255)) - (PORT datad (447:447:447) (518:518:518)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (580:580:580)) - (PORT datab (383:383:383) (469:469:469)) - (PORT datac (872:872:872) (1028:1028:1028)) - (PORT datad (217:217:217) (269:269:269)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (298:298:298)) - (PORT datad (317:317:317) (374:374:374)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (514:514:514)) - (PORT datab (613:613:613) (714:714:714)) - (PORT datac (201:201:201) (240:240:240)) - (PORT datad (497:497:497) (568:568:568)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (488:488:488)) - (PORT datab (357:357:357) (417:417:417)) - (PORT datac (175:175:175) (211:211:211)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (687:687:687)) - (PORT datab (477:477:477) (554:554:554)) - (PORT datac (583:583:583) (682:682:682)) - (PORT datad (549:549:549) (643:643:643)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (420:420:420)) - (PORT datab (576:576:576) (664:664:664)) - (PORT datac (269:269:269) (308:308:308)) - (PORT datad (358:358:358) (416:416:416)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (398:398:398)) - (PORT datab (357:357:357) (435:435:435)) - (PORT datac (706:706:706) (808:808:808)) - (PORT datad (631:631:631) (721:721:721)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (618:618:618)) - (PORT datab (616:616:616) (708:708:708)) - (PORT datad (576:576:576) (651:651:651)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (201:201:201) (259:259:259)) - (PORT datac (199:199:199) (244:244:244)) - (PORT datad (201:201:201) (251:251:251)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (639:639:639)) - (PORT datab (1280:1280:1280) (1486:1486:1486)) - (PORT datad (1231:1231:1231) (1469:1469:1469)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (333:333:333) (394:394:394)) - (PORT datac (430:430:430) (492:492:492)) - (PORT datad (784:784:784) (883:883:883)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (781:781:781) (895:895:895)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (764:764:764)) - (PORT datab (513:513:513) (599:599:599)) - (PORT datac (668:668:668) (771:771:771)) - (PORT datad (655:655:655) (753:753:753)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (197:197:197)) - (PORT datab (988:988:988) (1126:1126:1126)) - (PORT datac (136:136:136) (174:174:174)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (395:395:395)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (597:597:597) (676:676:676)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (539:539:539)) - (PORT datab (501:501:501) (581:581:581)) - (PORT datac (444:444:444) (515:515:515)) - (PORT datad (445:445:445) (505:505:505)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (558:558:558)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (345:345:345) (408:408:408)) - (PORT datad (332:332:332) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (521:521:521)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (480:480:480) (562:562:562)) - (PORT datad (93:93:93) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (188:188:188)) - (PORT datab (633:633:633) (738:738:738)) - (PORT datad (687:687:687) (797:797:797)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (287:287:287) (310:310:310)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (505:505:505) (591:591:591)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (462:462:462)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (809:809:809)) - (PORT datab (385:385:385) (452:452:452)) - (PORT datad (477:477:477) (564:564:564)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (355:355:355) (410:410:410)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (287:287:287) (309:309:309)) - (PORT ena (684:684:684) (755:755:755)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (469:469:469)) - (PORT datab (402:402:402) (476:476:476)) - (PORT datad (553:553:553) (633:633:633)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (412:412:412)) - (PORT datab (336:336:336) (393:393:393)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (233:233:233)) - (PORT datab (337:337:337) (395:395:395)) - (PORT datac (157:157:157) (184:184:184)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (441:441:441) (511:511:511)) - (PORT datad (618:618:618) (714:714:714)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (642:642:642) (715:715:715)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (678:678:678)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (608:608:608) (701:701:701)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (652:652:652) (711:711:711)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (331:331:331) (386:386:386)) - (PORT datac (352:352:352) (425:425:425)) - (PORT datad (118:118:118) (156:156:156)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (259:259:259)) - (PORT datab (337:337:337) (397:397:397)) - (PORT datac (664:664:664) (774:774:774)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (689:689:689)) - (PORT datad (482:482:482) (555:555:555)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (837:837:837)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (922:922:922)) - (PORT asdata (500:500:500) (549:549:549)) - (PORT clrn (926:926:926) (909:909:909)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (315:315:315) (370:370:370)) - (PORT datac (313:313:313) (380:380:380)) - (PORT datad (358:358:358) (433:433:433)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (293:293:293)) - (PORT datab (317:317:317) (372:372:372)) - (PORT datac (316:316:316) (375:375:375)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (640:640:640) (702:702:702)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (279:279:279) (298:298:298)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (490:490:490) (547:547:547)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (491:491:491) (547:547:547)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (137:137:137) (181:181:181)) - (PORT datab (590:590:590) (680:680:680)) - (PORT datad (186:186:186) (231:231:231)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (999:999:999) (1123:1123:1123)) - (PORT ena (495:495:495) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (999:999:999) (1122:1122:1122)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (132:132:132) (167:167:167)) - (PORT datad (113:113:113) (134:134:134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (990:990:990) (1113:1113:1113)) - (PORT ena (666:666:666) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (776:776:776)) - (PORT datab (373:373:373) (442:442:442)) - (PORT datad (454:454:454) (512:512:512)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (990:990:990) (1112:1112:1112)) - (PORT ena (603:603:603) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (265:265:265)) - (PORT datab (101:101:101) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (931:931:931) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (575:575:575) (635:635:635)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (142:142:142) (182:182:182)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (805:805:805) (949:949:949)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (520:520:520) (576:576:576)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (520:520:520) (575:575:575)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (389:389:389)) - (PORT datab (514:514:514) (604:604:604)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (509:509:509)) - (PORT datab (351:351:351) (411:411:411)) - (PORT datac (334:334:334) (388:388:388)) - (PORT datad (326:326:326) (382:382:382)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (654:654:654) (728:728:728)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (653:653:653) (728:728:728)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (222:222:222) (262:262:262)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (429:429:429)) - (PORT datab (454:454:454) (530:530:530)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (540:540:540)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (627:627:627) (732:732:732)) - (PORT datad (372:372:372) (436:436:436)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (944:944:944)) - (PORT datab (363:363:363) (428:428:428)) - (PORT datad (169:169:169) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (364:364:364)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (327:327:327) (382:382:382)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (528:528:528)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (669:669:669) (778:778:778)) - (PORT datad (116:116:116) (139:139:139)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (691:691:691)) - (PORT datad (335:335:335) (387:387:387)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (728:728:728)) - (PORT datab (815:815:815) (941:941:941)) - (PORT datac (638:638:638) (747:747:747)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (363:363:363)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (328:328:328) (385:385:385)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (780:780:780) (877:877:877)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (776:776:776) (873:873:873)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (174:174:174)) - (PORT datab (591:591:591) (682:682:682)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (661:661:661) (744:744:744)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (658:658:658) (741:741:741)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (270:270:270)) - (PORT datab (232:232:232) (277:277:277)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (631:631:631) (696:696:696)) - (PORT ena (434:434:434) (462:462:462)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (715:715:715) (844:844:844)) - (PORT datab (559:559:559) (659:659:659)) - (PORT datad (498:498:498) (578:578:578)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1051:1051:1051) (1201:1201:1201)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (141:141:141) (182:182:182)) - (PORT datab (635:635:635) (741:741:741)) - (PORT datad (459:459:459) (530:530:530)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (513:513:513) (574:574:574)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (521:521:521) (583:583:583)) - (PORT ena (684:684:684) (755:755:755)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (746:746:746)) - (PORT datab (396:396:396) (469:469:469)) - (PORT datad (554:554:554) (635:635:635)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (521:521:521) (584:584:584)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (931:931:931) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (806:806:806)) - (PORT datab (378:378:378) (444:444:444)) - (PORT datad (361:361:361) (434:434:434)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (431:431:431)) - (PORT datab (356:356:356) (417:417:417)) - (PORT datac (304:304:304) (350:350:350)) - (PORT datad (159:159:159) (186:186:186)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (667:667:667) (749:749:749)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (357:357:357) (422:422:422)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (390:390:390)) - (PORT datab (515:515:515) (604:604:604)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (402:402:402)) - (PORT datab (166:166:166) (202:202:202)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (170:170:170) (201:201:201)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (422:422:422)) - (PORT datab (387:387:387) (456:456:456)) - (PORT datac (628:628:628) (734:734:734)) - (PORT datad (276:276:276) (318:318:318)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (440:440:440) (477:477:477)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (944:944:944)) - (PORT datab (197:197:197) (239:239:239)) - (PORT datad (346:346:346) (401:401:401)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (652:652:652) (711:711:711)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (448:448:448)) - (PORT datab (171:171:171) (208:208:208)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (528:528:528)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (663:663:663) (772:772:772)) - (PORT datad (192:192:192) (230:230:230)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datab (431:431:431) (498:498:498)) - (PORT datad (566:566:566) (657:657:657)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (474:474:474) (544:544:544)) - (PORT datac (327:327:327) (384:384:384)) - (PORT datad (97:97:97) (116:116:116)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (138:138:138)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (302:302:302) (341:341:341)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (761:761:761)) - (PORT datab (494:494:494) (581:581:581)) - (PORT datac (199:199:199) (252:252:252)) - (PORT datad (501:501:501) (593:593:593)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (470:470:470) (515:515:515)) - (PORT ena (619:619:619) (673:673:673)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (410:410:410)) - (PORT datab (331:331:331) (389:389:389)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (324:324:324) (380:380:380)) - (PORT datad (224:224:224) (280:280:280)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (211:211:211) (253:253:253)) - (PORT datac (233:233:233) (288:288:288)) - (PORT datad (831:831:831) (974:974:974)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (393:393:393)) - (PORT datab (123:123:123) (155:155:155)) - (PORT datac (291:291:291) (336:336:336)) - (PORT datad (740:740:740) (848:848:848)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (580:580:580)) - (PORT datab (485:485:485) (565:565:565)) - (PORT datac (345:345:345) (404:404:404)) - (PORT datad (420:420:420) (486:486:486)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1160:1160:1160)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (303:303:303) (350:350:350)) - (PORT datad (120:120:120) (144:144:144)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (573:573:573)) - (PORT datad (434:434:434) (501:501:501)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (671:671:671) (778:778:778)) - (PORT datac (484:484:484) (555:555:555)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datab (640:640:640) (738:738:738)) - (PORT datac (633:633:633) (732:732:732)) - (PORT datad (340:340:340) (396:396:396)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (783:783:783)) - (PORT datab (372:372:372) (441:441:441)) - (PORT datad (600:600:600) (678:678:678)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (749:749:749) (846:846:846)) - (PORT ena (667:667:667) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (850:850:850)) - (PORT datab (496:496:496) (576:576:576)) - (PORT datad (771:771:771) (877:877:877)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (632:632:632) (701:701:701)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (636:636:636) (701:701:701)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (637:637:637) (702:702:702)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datab (239:239:239) (286:286:286)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (511:511:511)) - (PORT datab (345:345:345) (412:412:412)) - (PORT datad (340:340:340) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (603:603:603) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (537:537:537) (597:597:597)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (536:536:536) (597:597:597)) - (PORT ena (495:495:495) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (258:258:258)) - (PORT datab (129:129:129) (163:163:163)) - (PORT datad (110:110:110) (131:131:131)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (625:625:625) (690:690:690)) - (PORT ena (931:931:931) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (622:622:622) (686:686:686)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (190:190:190)) - (PORT datab (825:825:825) (980:980:980)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (334:334:334) (396:396:396)) - (PORT datac (201:201:201) (242:242:242)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (407:407:407)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (270:270:270) (309:309:309)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (647:647:647)) - (PORT datab (645:645:645) (752:752:752)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (357:357:357) (418:418:418)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (595:595:595) (649:649:649)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (945:945:945)) - (PORT datab (652:652:652) (753:753:753)) - (PORT datad (353:353:353) (409:409:409)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (652:652:652) (711:711:711)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (212:212:212)) - (PORT datac (351:351:351) (423:423:423)) - (PORT datad (118:118:118) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (253:253:253)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (660:660:660) (768:768:768)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (483:483:483) (566:566:566)) - (PORT datad (426:426:426) (481:481:481)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (953:953:953) (1066:1066:1066)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (921:921:921)) - (PORT datab (586:586:586) (683:683:683)) - (PORT datac (353:353:353) (418:418:418)) - (PORT datad (613:613:613) (706:706:706)) - (IOPATH dataa combout (188:188:188) (196:196:196)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (442:442:442)) - (PORT datab (782:782:782) (900:900:900)) - (PORT datac (92:92:92) (117:117:117)) - (PORT datad (756:756:756) (862:862:862)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (652:652:652) (711:711:711)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (797:797:797) (892:892:892)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (798:798:798) (894:894:894)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (269:269:269)) - (PORT datab (233:233:233) (279:279:279)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (537:537:537) (605:605:605)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (754:754:754) (861:861:861)) - (PORT ena (435:435:435) (462:462:462)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (807:807:807)) - (PORT datab (381:381:381) (448:448:448)) - (PORT datad (477:477:477) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (796:796:796) (889:889:889)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (775:775:775) (865:865:865)) - (PORT ena (666:666:666) (729:729:729)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (467:467:467)) - (PORT datab (372:372:372) (441:441:441)) - (PORT datad (349:349:349) (406:406:406)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (775:775:775) (865:865:865)) - (PORT ena (603:603:603) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (268:268:268)) - (PORT datab (101:101:101) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (470:470:470) (514:514:514)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (583:583:583)) - (PORT datab (740:740:740) (859:859:859)) - (PORT datac (457:457:457) (525:525:525)) - (PORT datad (461:461:461) (541:541:541)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (215:215:215)) - (PORT datab (333:333:333) (397:397:397)) - (PORT datad (163:163:163) (192:192:192)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (488:488:488) (540:540:540)) - (PORT ena (754:754:754) (814:814:814)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (309:309:309) (364:364:364)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (185:185:185)) - (PORT datab (589:589:589) (679:679:679)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (652:652:652) (729:729:729)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (354:354:354) (423:423:423)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (392:392:392)) - (PORT datab (516:516:516) (606:606:606)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (317:317:317)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (450:450:450) (511:511:511)) - (PORT datad (160:160:160) (183:183:183)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (519:519:519)) - (PORT datab (298:298:298) (346:346:346)) - (PORT datac (629:629:629) (735:735:735)) - (PORT datad (368:368:368) (431:431:431)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (440:440:440) (475:475:475)) - (PORT ena (650:650:650) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (944:944:944)) - (PORT datab (196:196:196) (237:237:237)) - (PORT datad (347:347:347) (402:402:402)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (449:449:449)) - (PORT datac (119:119:119) (160:160:160)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (259:259:259)) - (PORT datab (680:680:680) (795:795:795)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (835:835:835)) - (PORT datad (279:279:279) (320:320:320)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (304:304:304) (349:349:349)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (443:443:443)) - (PORT datab (631:631:631) (730:730:730)) - (PORT datac (352:352:352) (416:416:416)) - (PORT datad (777:777:777) (892:892:892)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (780:780:780) (897:897:897)) - (PORT datac (762:762:762) (871:871:871)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (408:408:408)) - (PORT datab (315:315:315) (370:370:370)) - (PORT datac (313:313:313) (381:381:381)) - (PORT datad (358:358:358) (434:434:434)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (684:684:684) (799:799:799)) - (PORT datac (492:492:492) (565:565:565)) - (PORT datad (113:113:113) (136:136:136)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (211:211:211)) - (PORT datab (394:394:394) (462:462:462)) - (PORT datac (625:625:625) (730:730:730)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (386:386:386)) - (PORT datab (213:213:213) (254:254:254)) - (PORT datac (290:290:290) (329:329:329)) - (PORT datad (335:335:335) (391:391:391)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (151:151:151)) - (PORT datab (605:605:605) (698:698:698)) - (PORT datac (461:461:461) (530:530:530)) - (PORT datad (173:173:173) (206:206:206)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (169:169:169)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (303:303:303) (350:350:350)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (405:405:405) (494:494:494)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (117:117:117) (135:135:135)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (565:565:565)) - (PORT datab (364:364:364) (434:434:434)) - (PORT datac (758:758:758) (871:871:871)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT asdata (463:463:463) (500:500:500)) - (PORT ena (894:894:894) (985:985:985)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (582:582:582)) - (PORT datab (891:891:891) (1052:1052:1052)) - (PORT datac (475:475:475) (553:553:553)) - (PORT datad (224:224:224) (281:281:281)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (553:553:553)) - (PORT datab (141:141:141) (177:177:177)) - (PORT datac (476:476:476) (562:562:562)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (551:551:551)) - (PORT datab (485:485:485) (566:566:566)) - (PORT datad (422:422:422) (496:496:496)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (719:719:719) (826:826:826)) - (PORT datac (110:110:110) (136:136:136)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28640,12 +10955,12 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) (DELAY (ABSOLUTE - (PORT dataa (502:502:502) (599:599:599)) - (PORT datab (611:611:611) (733:733:733)) - (PORT datac (484:484:484) (579:579:579)) - (PORT datad (347:347:347) (403:403:403)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (510:510:510) (603:603:603)) + (PORT datab (655:655:655) (773:773:773)) + (PORT datac (474:474:474) (560:560:560)) + (PORT datad (603:603:603) (715:715:715)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28656,13 +10971,27 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (430:430:430)) - (PORT datab (456:456:456) (527:527:527)) - (PORT datac (336:336:336) (400:400:400)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (582:582:582) (679:679:679)) + (PORT datab (460:460:460) (534:534:534)) + (PORT datac (335:335:335) (385:385:385)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT datab (659:659:659) (778:778:778)) + (PORT datac (620:620:620) (724:724:724)) + (PORT datad (442:442:442) (506:506:506)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -28672,9 +11001,9 @@ (INSTANCE z80_\|alu_\|op2_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) + (PORT clk (909:909:909) (897:897:897)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) + (PORT ena (420:420:420) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -28685,15 +11014,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (INSTANCE z80_\|alu_\|db_low\[3\]\~2) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (426:426:426)) - (PORT datab (481:481:481) (568:568:568)) - (PORT datac (444:444:444) (509:509:509)) - (PORT datad (338:338:338) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (775:775:775) (924:924:924)) + (PORT datab (950:950:950) (1101:1101:1101)) + (PORT datac (190:190:190) (241:241:241)) + (PORT datad (363:363:363) (437:437:437)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28701,24 +11030,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (INSTANCE z80_\|alu_\|db_low\[3\]\~3) (DELAY (ABSOLUTE - (PORT datac (337:337:337) (402:402:402)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (506:506:506) (582:582:582)) + (PORT datab (339:339:339) (398:398:398)) + (PORT datac (732:732:732) (838:838:838)) + (PORT datad (480:480:480) (554:554:554)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) + (INSTANCE z80_\|alu_\|result_lo\[3\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (893:893:893)) + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (454:454:454)) + (PORT ena (917:917:917) (1035:1035:1035)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -28729,75 +11062,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (308:308:308)) - (PORT datab (306:306:306) (363:363:363)) - (PORT datac (350:350:350) (419:419:419)) - (PORT datad (450:450:450) (521:521:521)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (223:223:223)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (224:224:224)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datac (179:179:179) (212:212:212)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (415:415:415)) - (PORT datab (469:469:469) (540:540:540)) - (PORT datac (1130:1130:1130) (1315:1315:1315)) - (PORT datad (471:471:471) (574:574:574)) + (PORT dataa (498:498:498) (584:584:584)) + (PORT datac (438:438:438) (504:504:504)) + (PORT datad (194:194:194) (242:242:242)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (508:508:508) (604:604:604)) - (PORT datac (356:356:356) (412:412:412)) - (PORT datad (339:339:339) (391:391:391)) - (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28805,109 +11076,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) (DELAY (ABSOLUTE - (PORT dataa (883:883:883) (1013:1013:1013)) - (PORT datab (393:393:393) (458:458:458)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (531:531:531) (600:600:600)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (304:304:304)) - (PORT datab (144:144:144) (181:181:181)) - (PORT datad (318:318:318) (376:376:376)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (398:398:398)) - (PORT datab (305:305:305) (354:354:354)) - (PORT datac (475:475:475) (561:561:561)) - (PORT datad (93:93:93) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (350:350:350)) + (PORT dataa (1259:1259:1259) (1442:1442:1442)) (PORT datab (120:120:120) (150:150:150)) - (PORT datac (464:464:464) (544:544:544)) - (PORT datad (446:446:446) (526:526:526)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (436:436:436)) - (PORT datab (620:620:620) (719:719:719)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (283:283:283) (319:319:319)) + (PORT datac (490:490:490) (567:567:567)) + (PORT datad (98:98:98) (120:120:120)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1169:1169:1169)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (488:488:488) (570:570:570)) - (PORT datad (168:168:168) (200:200:200)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (695:695:695)) - (PORT datab (761:761:761) (887:887:887)) - (PORT datac (428:428:428) (489:489:489)) - (PORT datad (300:300:300) (348:348:348)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28915,15 +11092,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT dataa (432:432:432) (500:500:500)) - (PORT datab (188:188:188) (229:229:229)) - (PORT datac (584:584:584) (664:664:664)) - (PORT datad (570:570:570) (651:651:651)) + (PORT datac (666:666:666) (785:785:785)) + (PORT datad (1286:1286:1286) (1532:1532:1532)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (865:865:865)) + (PORT datab (546:546:546) (638:638:638)) + (PORT datac (551:551:551) (644:644:644)) + (PORT datad (683:683:683) (797:797:797)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (831:831:831)) + (PORT datab (589:589:589) (669:669:669)) + (PORT datad (556:556:556) (664:664:664)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (891:891:891)) + (PORT datab (500:500:500) (575:575:575)) + (PORT datac (537:537:537) (636:636:636)) + (PORT datad (805:805:805) (962:962:962)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28931,13 +11150,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (152:152:152)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (320:320:320) (375:375:375)) - (PORT datad (315:315:315) (361:361:361)) + (PORT dataa (458:458:458) (529:529:529)) + (PORT datac (514:514:514) (602:602:602)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1138:1138:1138)) + (PORT datab (984:984:984) (1129:1129:1129)) + (PORT datac (1142:1142:1142) (1336:1336:1336)) + (PORT datad (543:543:543) (627:627:627)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (964:964:964)) + (PORT datab (514:514:514) (590:590:590)) + (PORT datac (432:432:432) (485:485:485)) + (PORT datad (696:696:696) (805:805:805)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -28947,45 +11196,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~24) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (599:599:599)) - (PORT datab (487:487:487) (573:573:573)) - (PORT datac (679:679:679) (778:778:778)) - (PORT datad (331:331:331) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (120:120:120) (149:149:149)) - (PORT datac (466:466:466) (538:538:538)) - (PORT datad (341:341:341) (396:396:396)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (128:128:128) (165:165:165)) - (PORT datab (835:835:835) (969:969:969)) - (PORT datac (681:681:681) (786:786:786)) - (PORT datad (381:381:381) (448:448:448)) + (PORT dataa (461:461:461) (527:527:527)) + (PORT datab (470:470:470) (544:544:544)) + (PORT datac (963:963:963) (1124:1124:1124)) + (PORT datad (983:983:983) (1158:1158:1158)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -28995,72 +11212,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) + (INSTANCE z80_\|execute_\|fMRead\~8) (DELAY (ABSOLUTE - (PORT datac (97:97:97) (124:124:124)) - (PORT datad (102:102:102) (124:124:124)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (500:500:500)) - (PORT datab (187:187:187) (229:229:229)) - (PORT datac (269:269:269) (311:311:311)) - (PORT datad (431:431:431) (491:491:491)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (434:434:434) (505:505:505)) + (PORT datab (389:389:389) (465:465:465)) + (PORT datac (792:792:792) (900:900:900)) + (PORT datad (452:452:452) (538:538:538)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~7) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (400:400:400)) - (PORT datab (348:348:348) (412:412:412)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (651:651:651) (753:753:753)) + (PORT datab (489:489:489) (567:567:567)) + (PORT datac (501:501:501) (586:586:586)) + (PORT datad (634:634:634) (725:725:725)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~25) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (791:791:791)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (459:459:459) (550:550:550)) + (PORT datad (99:99:99) (120:120:120)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (381:381:381)) - (PORT datab (799:799:799) (903:903:903)) - (PORT datac (800:800:800) (932:932:932)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29068,29 +11260,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (767:767:767)) - (PORT datab (797:797:797) (901:901:901)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (451:451:451) (518:518:518)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (623:623:623)) - (PORT datab (668:668:668) (766:766:766)) - (PORT datac (330:330:330) (390:390:390)) - (PORT datad (753:753:753) (862:862:862)) + (PORT dataa (385:385:385) (469:469:469)) + (PORT datab (390:390:390) (473:473:473)) + (PORT datac (1056:1056:1056) (1213:1213:1213)) + (PORT datad (596:596:596) (705:705:705)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29100,15 +11276,125 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M4T2_3) (DELAY (ABSOLUTE - (PORT dataa (443:443:443) (513:513:513)) - (PORT datab (760:760:760) (886:886:886)) - (PORT datac (587:587:587) (672:672:672)) - (PORT datad (948:948:948) (1073:1073:1073)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (596:596:596) (681:681:681)) + (PORT datab (848:848:848) (989:989:989)) + (PORT datac (846:846:846) (987:987:987)) + (PORT datad (303:303:303) (344:344:344)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (965:965:965)) + (PORT datab (422:422:422) (524:524:524)) + (PORT datac (379:379:379) (468:468:468)) + (PORT datad (503:503:503) (594:594:594)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M5T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (684:684:684)) + (PORT datab (317:317:317) (368:368:368)) + (PORT datac (844:844:844) (984:984:984)) + (PORT datad (332:332:332) (381:381:381)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (625:625:625)) + (PORT datab (780:780:780) (896:896:896)) + (PORT datac (380:380:380) (470:470:470)) + (PORT datad (401:401:401) (498:498:498)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (426:426:426)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (827:827:827) (949:949:949)) + (PORT datad (889:889:889) (1005:1005:1005)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (92:92:92) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (799:799:799)) + (PORT datab (590:590:590) (694:694:694)) + (PORT datac (539:539:539) (637:637:637)) + (PORT datad (283:283:283) (323:323:323)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla5M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1718:1718:1718)) + (PORT datac (336:336:336) (394:394:394)) + (PORT datad (649:649:649) (759:759:759)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29116,13 +11402,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) (DELAY (ABSOLUTE - (PORT dataa (1008:1008:1008) (1169:1169:1169)) - (PORT datab (363:363:363) (431:431:431)) - (PORT datac (594:594:594) (701:701:701)) - (PORT datad (174:174:174) (205:205:205)) + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (797:797:797) (914:914:914)) + (PORT datac (535:535:535) (633:633:633)) + (PORT datad (578:578:578) (671:671:671)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (439:439:439)) + (PORT datab (593:593:593) (696:696:696)) + (PORT datac (533:533:533) (631:631:631)) + (PORT datad (300:300:300) (340:340:340)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (684:684:684)) + (PORT datab (593:593:593) (697:697:697)) + (PORT datac (532:532:532) (629:629:629)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (632:632:632)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (1022:1022:1022)) + (PORT datab (1011:1011:1011) (1166:1166:1166)) + (PORT datac (803:803:803) (918:918:918)) + (PORT datad (377:377:377) (443:443:443)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1092:1092:1092)) + (PORT datab (949:949:949) (1099:1099:1099)) + (PORT datac (591:591:591) (691:691:691)) + (PORT datad (962:962:962) (1123:1123:1123)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29132,449 +11498,327 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1213:1213:1213)) + (PORT datab (712:712:712) (845:845:845)) + (PORT datac (924:924:924) (1063:1063:1063)) + (PORT datad (406:406:406) (500:500:500)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (585:585:585)) + (PORT datab (750:750:750) (875:875:875)) + (PORT datac (557:557:557) (649:649:649)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (494:494:494)) + (PORT datab (1089:1089:1089) (1250:1250:1250)) + (PORT datad (360:360:360) (436:436:436)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (218:218:218)) + (PORT datab (814:814:814) (935:935:935)) + (PORT datac (744:744:744) (862:862:862)) + (PORT datad (96:96:96) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T4_3\~0) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (513:513:513)) + (PORT datac (381:381:381) (457:457:457)) + (PORT datad (799:799:799) (917:917:917)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (661:661:661)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (428:428:428) (484:484:484)) + (PORT datad (338:338:338) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (949:949:949)) + (PORT datab (450:450:450) (513:513:513)) + (PORT datac (616:616:616) (707:707:707)) + (PORT datad (659:659:659) (764:764:764)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (656:656:656)) + (PORT datab (950:950:950) (1100:1100:1100)) + (PORT datac (618:618:618) (709:709:709)) + (PORT datad (439:439:439) (502:502:502)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~16) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (535:535:535)) + (PORT datab (470:470:470) (542:542:542)) + (PORT datac (444:444:444) (513:513:513)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (775:775:775)) + (PORT datab (324:324:324) (380:380:380)) + (PORT datac (359:359:359) (419:419:419)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (857:857:857)) + (PORT datab (675:675:675) (778:778:778)) + (PORT datac (778:778:778) (886:886:886)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (417:417:417)) + (PORT datab (557:557:557) (651:651:651)) + (PORT datac (357:357:357) (426:426:426)) + (PORT datad (639:639:639) (736:736:736)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (579:579:579)) + (PORT datab (121:121:121) (152:152:152)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (157:157:157)) + (PORT datab (377:377:377) (449:449:449)) + (PORT datac (474:474:474) (538:538:538)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~22) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (173:173:173)) + (PORT datab (696:696:696) (823:823:823)) + (PORT datac (535:535:535) (647:647:647)) + (PORT datad (615:615:615) (700:700:700)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (228:228:228)) + (PORT datab (132:132:132) (161:161:161)) + (PORT datac (358:358:358) (428:428:428)) + (PORT datad (521:521:521) (607:607:607)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (288:288:288) (334:334:334)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (392:392:392)) + (PORT datab (670:670:670) (786:786:786)) + (PORT datac (901:901:901) (1030:1030:1030)) + (PORT datad (349:349:349) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) (DELAY (ABSOLUTE (PORT dataa (461:461:461) (533:533:533)) - (PORT datab (339:339:339) (400:400:400)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (344:344:344) (401:401:401)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (330:330:330)) - (PORT datab (342:342:342) (398:398:398)) - (PORT datac (305:305:305) (354:354:354)) - (PORT datad (165:165:165) (194:194:194)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (562:562:562)) - (PORT datab (582:582:582) (677:677:677)) - (PORT datac (439:439:439) (520:520:520)) - (PORT datad (313:313:313) (363:363:363)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (556:556:556)) - (PORT datab (228:228:228) (283:283:283)) - (PORT datac (165:165:165) (195:195:195)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT datab (509:509:509) (605:605:605)) - (PORT datac (373:373:373) (436:436:436)) - (PORT datad (510:510:510) (586:586:586)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (434:434:434)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (339:339:339) (391:391:391)) - (PORT datad (863:863:863) (988:988:988)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (514:514:514)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (120:120:120) (164:164:164)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (514:514:514)) - (PORT datab (181:181:181) (221:221:221)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (866:866:866) (992:992:992)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (954:954:954)) - (PORT datab (1484:1484:1484) (1755:1755:1755)) - (PORT datac (671:671:671) (783:783:783)) - (PORT datad (750:750:750) (911:911:911)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datac (959:959:959) (1109:1109:1109)) - (PORT datad (469:469:469) (526:526:526)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (419:419:419)) - (PORT datab (358:358:358) (426:426:426)) - (PORT datad (613:613:613) (707:707:707)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1218:1218:1218)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (442:442:442) (493:493:493)) - (PORT datad (643:643:643) (732:732:732)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (711:711:711)) - (PORT datab (460:460:460) (542:542:542)) - (PORT datac (647:647:647) (740:740:740)) - (PORT datad (606:606:606) (697:697:697)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (187:187:187)) - (PORT datab (140:140:140) (187:187:187)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (453:453:453) (518:518:518)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (650:650:650)) - (PORT datab (478:478:478) (553:553:553)) - (PORT datac (589:589:589) (701:701:701)) - (PORT datad (695:695:695) (827:827:827)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (128:128:128) (158:158:158)) - (PORT datab (791:791:791) (949:949:949)) - (PORT datac (1108:1108:1108) (1254:1254:1254)) - (PORT datad (489:489:489) (556:556:556)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (143:143:143)) - (PORT datab (550:550:550) (653:653:653)) - (PORT datac (653:653:653) (751:751:751)) - (PORT datad (799:799:799) (923:923:923)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (340:340:340) (397:397:397)) - (PORT datad (487:487:487) (561:561:561)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (416:416:416)) - (PORT datab (691:691:691) (802:802:802)) - (PORT datac (96:96:96) (122:122:122)) - (PORT datad (341:341:341) (400:400:400)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (398:398:398)) - (PORT datab (316:316:316) (365:365:365)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (165:165:165) (193:193:193)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT datac (519:519:519) (622:622:622)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (318:318:318) (367:367:367)) - (PORT datac (109:109:109) (135:135:135)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (573:573:573)) - (PORT datab (1102:1102:1102) (1281:1281:1281)) - (PORT datac (744:744:744) (851:851:851)) - (PORT datad (1216:1216:1216) (1455:1455:1455)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (549:549:549)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (116:116:116) (143:143:143)) - (PORT datad (101:101:101) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (537:537:537)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datac (679:679:679) (777:777:777)) - (PORT datad (473:473:473) (548:548:548)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (656:656:656) (759:759:759)) - (PORT datad (95:95:95) (116:116:116)) + (PORT datab (532:532:532) (627:627:627)) + (PORT datac (618:618:618) (705:705:705)) + (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (805:805:805)) - (PORT datab (374:374:374) (448:448:448)) - (PORT datac (420:420:420) (484:484:484)) - (PORT datad (932:932:932) (1070:1070:1070)) + (PORT dataa (871:871:871) (1023:1023:1023)) + (PORT datab (618:618:618) (720:720:720)) + (PORT datac (837:837:837) (965:965:965)) + (PORT datad (867:867:867) (1022:1022:1022)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (309:309:309) (357:357:357)) - (PORT datab (444:444:444) (512:512:512)) - (PORT datac (318:318:318) (367:367:367)) - (PORT datad (352:352:352) (408:408:408)) + (PORT dataa (463:463:463) (528:528:528)) + (PORT datab (1045:1045:1045) (1206:1206:1206)) + (PORT datac (459:459:459) (550:550:550)) + (PORT datad (99:99:99) (121:121:121)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29584,15 +11828,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (352:352:352) (417:417:417)) - (PORT datac (175:175:175) (212:212:212)) - (PORT datad (331:331:331) (378:378:378)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (354:354:354) (419:419:419)) + (PORT datab (608:608:608) (696:696:696)) + (PORT datac (462:462:462) (557:557:557)) + (PORT datad (460:460:460) (528:528:528)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29600,31 +11844,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) (DELAY (ABSOLUTE - (PORT dataa (750:750:750) (860:860:860)) - (PORT datab (499:499:499) (585:585:585)) - (PORT datac (566:566:566) (652:652:652)) - (PORT datad (776:776:776) (893:893:893)) + (PORT datab (671:671:671) (772:772:772)) + (PORT datac (613:613:613) (703:703:703)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (543:543:543)) + (PORT datab (689:689:689) (825:825:825)) + (PORT datad (511:511:511) (599:599:599)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (990:990:990)) + (PORT datab (1040:1040:1040) (1203:1203:1203)) + (PORT datac (841:841:841) (962:962:962)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (334:334:334) (394:394:394)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (349:349:349) (408:408:408)) + (PORT datab (299:299:299) (354:354:354)) + (PORT datac (177:177:177) (211:211:211)) + (PORT datad (569:569:569) (649:649:649)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29632,75 +11900,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (INSTANCE z80_\|execute_\|setM1\~39) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (451:451:451)) - (PORT datab (543:543:543) (622:622:622)) - (PORT datac (1106:1106:1106) (1296:1296:1296)) - (PORT datad (168:168:168) (197:197:197)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT datab (431:431:431) (498:498:498)) - (PORT datac (115:115:115) (141:141:141)) - (PORT datad (451:451:451) (520:520:520)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (177:177:177) (217:217:217)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (330:330:330) (386:386:386)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (392:392:392)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (306:306:306) (348:348:348)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (711:711:711)) - (PORT datab (650:650:650) (753:753:753)) - (PORT datac (643:643:643) (748:748:748)) - (PORT datad (750:750:750) (859:859:859)) + (PORT dataa (430:430:430) (493:493:493)) + (PORT datab (358:358:358) (433:433:433)) + (PORT datac (358:358:358) (430:430:430)) + (PORT datad (375:375:375) (441:441:441)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29710,136 +11916,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~20) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (701:701:701)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (274:274:274) (316:316:316)) + (PORT dataa (382:382:382) (454:454:454)) + (PORT datab (504:504:504) (591:591:591)) + (PORT datac (92:92:92) (116:116:116)) + (PORT datad (337:337:337) (391:391:391)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT datab (449:449:449) (517:517:517)) - (PORT datac (604:604:604) (690:690:690)) - (PORT datad (435:435:435) (506:506:506)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (512:512:512)) - (PORT datab (494:494:494) (570:570:570)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (595:595:595)) - (PORT datab (496:496:496) (568:568:568)) - (PORT datac (798:798:798) (907:907:907)) - (PORT datad (481:481:481) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (780:780:780)) - (PORT datab (485:485:485) (562:562:562)) - (PORT datac (633:633:633) (720:720:720)) - (PORT datad (534:534:534) (619:619:619)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (767:767:767)) - (PORT datab (798:798:798) (902:902:902)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (282:282:282) (324:324:324)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~21) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (418:418:418)) - (PORT datab (361:361:361) (443:443:443)) - (PORT datac (590:590:590) (672:672:672)) - (PORT datad (280:280:280) (325:325:325)) - (IOPATH dataa combout (158:158:158) (165:165:165)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (456:456:456)) - (PORT datab (725:725:725) (832:832:832)) - (PORT datac (537:537:537) (625:625:625)) - (PORT datad (194:194:194) (222:222:222)) + (PORT dataa (563:563:563) (664:664:664)) + (PORT datab (504:504:504) (583:583:583)) + (PORT datac (721:721:721) (833:833:833)) + (PORT datad (662:662:662) (757:757:757)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -29849,625 +11948,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) (DELAY (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (647:647:647) (746:746:746)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (312:312:312) (364:364:364)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (309:309:309) (359:359:359)) - (PORT datab (450:450:450) (514:514:514)) - (PORT datac (297:297:297) (343:343:343)) - (PORT datad (288:288:288) (332:332:332)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (542:542:542) (608:608:608)) - (PORT ena (503:503:503) (543:543:543)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (542:542:542) (609:609:609)) - (PORT ena (473:473:473) (498:498:498)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (779:779:779)) - (PORT datab (463:463:463) (539:539:539)) - (PORT datad (322:322:322) (375:375:375)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (634:634:634) (701:701:701)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (535:535:535) (600:600:600)) - (PORT ena (931:931:931) (1043:1043:1043)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (537:537:537) (601:601:601)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (190:190:190)) - (PORT datab (824:824:824) (979:979:979)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT datab (383:383:383) (450:450:450)) - (PORT datad (335:335:335) (391:391:391)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (526:526:526) (580:580:580)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (633:633:633) (700:700:700)) - (PORT ena (684:684:684) (755:755:755)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (470:470:470)) - (PORT datab (396:396:396) (470:470:470)) - (PORT datad (554:554:554) (635:635:635)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (638:638:638) (707:707:707)) - (PORT ena (594:594:594) (642:642:642)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (638:638:638) (707:707:707)) - (PORT ena (665:665:665) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (395:395:395)) - (PORT datab (518:518:518) (608:608:608)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (603:603:603) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (419:419:419)) - (PORT datab (341:341:341) (403:403:403)) - (PORT datac (201:201:201) (242:242:242)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (498:498:498)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (342:342:342) (407:407:407)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (644:644:644) (750:750:750)) - (PORT datac (575:575:575) (649:649:649)) - (PORT datad (355:355:355) (417:417:417)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (944:944:944)) - (PORT datab (362:362:362) (426:426:426)) - (PORT datad (442:442:442) (496:496:496)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (272:272:272)) - (PORT datac (352:352:352) (425:425:425)) - (PORT datad (168:168:168) (198:198:198)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (294:294:294)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (345:345:345)) - (PORT datab (131:131:131) (164:164:164)) - (PORT datac (672:672:672) (781:781:781)) - (PORT datad (333:333:333) (383:383:383)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (682:682:682)) - (PORT datad (455:455:455) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (1097:1097:1097) (1218:1218:1218)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (290:290:290)) - (PORT datab (207:207:207) (265:265:265)) - (PORT datac (133:133:133) (175:175:175)) - (PORT datad (129:129:129) (166:166:166)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (305:305:305)) - (PORT datab (220:220:220) (280:280:280)) - (PORT datac (207:207:207) (265:265:265)) - (PORT datad (131:131:131) (168:168:168)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (816:816:816)) - (PORT datab (378:378:378) (460:460:460)) - (PORT datac (315:315:315) (383:383:383)) - (PORT datad (131:131:131) (169:169:169)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (289:289:289)) - (PORT datab (218:218:218) (282:282:282)) - (PORT datac (290:290:290) (350:350:350)) - (PORT datad (198:198:198) (248:248:248)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (532:532:532)) - (PORT datab (446:446:446) (513:513:513)) - (PORT datac (330:330:330) (387:387:387)) - (PORT datad (339:339:339) (397:397:397)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (650:650:650)) - (PORT datab (367:367:367) (428:428:428)) - (PORT datad (334:334:334) (389:389:389)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (627:627:627)) - (PORT datab (347:347:347) (409:409:409)) - (PORT datac (453:453:453) (521:521:521)) - (PORT datad (346:346:346) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (370:370:370)) - (PORT datab (1477:1477:1477) (1703:1703:1703)) - (PORT datac (1166:1166:1166) (1392:1392:1392)) - (PORT datad (783:783:783) (884:884:884)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (358:358:358)) - (PORT datab (322:322:322) (390:390:390)) - (PORT datad (623:623:623) (719:719:719)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (253:253:253)) - (PORT datac (402:402:402) (485:485:485)) - (PORT datad (150:150:150) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (697:697:697) (760:760:760)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (895:895:895) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (744:744:744) (861:861:861)) - (PORT datac (459:459:459) (543:543:543)) - (PORT datad (127:127:127) (168:168:168)) - (IOPATH dataa combout (159:159:159) (173:173:173)) + (PORT datab (413:413:413) (498:498:498)) + (PORT datac (540:540:540) (652:652:652)) + (PORT datad (557:557:557) (665:665:665)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -30476,170 +11962,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (191:191:191)) - (PORT datab (104:104:104) (134:134:134)) - (PORT datac (532:532:532) (627:627:627)) - (PORT datad (451:451:451) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (649:649:649)) - (PORT datab (740:740:740) (857:857:857)) - (PORT datac (330:330:330) (385:385:385)) - (PORT datad (512:512:512) (596:596:596)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (557:557:557)) - (PORT datab (349:349:349) (425:425:425)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (346:346:346) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (645:645:645)) - (PORT datab (1225:1225:1225) (1465:1465:1465)) - (PORT datac (727:727:727) (838:838:838)) - (PORT datad (754:754:754) (914:914:914)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (653:653:653)) - (PORT datab (517:517:517) (608:608:608)) - (PORT datac (329:329:329) (384:384:384)) - (PORT datad (450:450:450) (528:528:528)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (545:545:545)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (346:346:346) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (222:222:222)) - (PORT datab (138:138:138) (169:169:169)) - (PORT datac (188:188:188) (223:223:223)) - (PORT datad (309:309:309) (356:356:356)) + (PORT dataa (983:983:983) (1124:1124:1124)) + (PORT datab (1135:1135:1135) (1316:1316:1316)) + (PORT datac (697:697:697) (806:806:806)) + (PORT datad (452:452:452) (517:517:517)) (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1037:1037:1037) (1155:1155:1155)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (236:236:236)) - (PORT datab (183:183:183) (225:225:225)) - (PORT datac (164:164:164) (196:196:196)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) (DELAY (ABSOLUTE - (PORT datab (719:719:719) (838:838:838)) - (PORT datad (419:419:419) (477:477:477)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (851:851:851) (992:992:992)) + (PORT datac (988:988:988) (1140:1140:1140)) + (PORT datad (674:674:674) (767:767:767)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~19) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (262:262:262) (296:296:296)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (644:644:644) (750:750:750)) + (PORT datab (402:402:402) (481:481:481)) + (PORT datac (482:482:482) (552:552:552)) + (PORT datad (796:796:796) (903:903:903)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (543:543:543)) + (PORT datab (640:640:640) (740:740:740)) + (PORT datac (810:810:810) (948:948:948)) + (PORT datad (657:657:657) (763:763:763)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (967:967:967)) + (PORT datab (1126:1126:1126) (1313:1313:1313)) + (PORT datad (671:671:671) (767:767:767)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (986:986:986)) + (PORT datab (703:703:703) (815:815:815)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (1019:1019:1019) (1163:1163:1163)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30649,214 +12056,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (268:268:268)) - (PORT datab (540:540:540) (641:641:641)) - (PORT datac (539:539:539) (633:633:633)) - (PORT datad (523:523:523) (610:610:610)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (640:640:640)) - (PORT datab (424:424:424) (493:493:493)) - (PORT datac (454:454:454) (526:526:526)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (782:782:782)) - (PORT datab (550:550:550) (650:650:650)) - (PORT datac (623:623:623) (722:722:722)) - (PORT datad (631:631:631) (726:726:726)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (277:277:277) (321:321:321)) - (PORT datad (180:180:180) (213:213:213)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (522:522:522)) - (PORT datab (336:336:336) (389:389:389)) - (PORT datac (289:289:289) (335:335:335)) - (PORT datad (285:285:285) (322:322:322)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (613:613:613) (711:711:711)) - (PORT datac (159:159:159) (187:187:187)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (402:402:402)) - (PORT datab (729:729:729) (856:856:856)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (444:444:444) (512:512:512)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (416:416:416)) - (PORT datab (496:496:496) (600:600:600)) - (PORT datac (639:639:639) (740:740:740)) - (PORT datad (407:407:407) (466:466:466)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (495:495:495)) - (PORT datab (356:356:356) (434:434:434)) - (PORT datac (353:353:353) (431:431:431)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (436:436:436)) - (PORT datab (531:531:531) (633:633:633)) - (PORT datad (262:262:262) (293:293:293)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (161:161:161) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (865:865:865)) - (PORT datab (547:547:547) (651:651:651)) - (PORT datac (598:598:598) (689:689:689)) - (PORT datad (868:868:868) (1007:1007:1007)) + (PORT dataa (1274:1274:1274) (1484:1484:1484)) + (PORT datab (940:940:940) (1079:1079:1079)) + (PORT datac (973:973:973) (1117:1117:1117)) + (PORT datad (1060:1060:1060) (1217:1217:1217)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -30869,10 +12075,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) (DELAY (ABSOLUTE - (PORT dataa (815:815:815) (939:939:939)) - (PORT datab (611:611:611) (706:706:706)) - (PORT datac (585:585:585) (660:660:660)) - (PORT datad (328:328:328) (376:376:376)) + (PORT dataa (1072:1072:1072) (1240:1240:1240)) + (PORT datab (197:197:197) (232:232:232)) + (PORT datac (492:492:492) (563:563:563)) + (PORT datad (94:94:94) (114:114:114)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30885,10 +12091,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (393:393:393)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datac (332:332:332) (390:390:390)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (500:500:500) (575:575:575)) + (PORT datab (352:352:352) (414:414:414)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (453:453:453) (518:518:518)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30898,13 +12104,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) (DELAY (ABSOLUTE - (PORT dataa (538:538:538) (634:634:634)) - (PORT datac (531:531:531) (630:630:630)) - (PORT datad (686:686:686) (795:795:795)) + (PORT dataa (540:540:540) (643:643:643)) + (PORT datab (553:553:553) (672:672:672)) + (PORT datac (777:777:777) (925:925:925)) + (PORT datad (518:518:518) (587:587:587)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (421:421:421)) + (PORT datab (1006:1006:1006) (1161:1161:1161)) + (PORT datac (808:808:808) (923:923:923)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (1043:1043:1043)) + (PORT datab (1002:1002:1002) (1177:1177:1177)) + (PORT datac (972:972:972) (1140:1140:1140)) + (PORT datad (993:993:993) (1161:1161:1161)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -30912,13 +12152,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (409:409:409)) - (PORT datab (809:809:809) (930:930:930)) - (PORT datac (315:315:315) (368:368:368)) - (PORT datad (311:311:311) (356:356:356)) + (PORT dataa (856:856:856) (1003:1003:1003)) + (PORT datab (894:894:894) (1024:1024:1024)) + (PORT datac (634:634:634) (732:732:732)) + (PORT datad (498:498:498) (576:576:576)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (698:698:698)) + (PORT datab (553:553:553) (640:640:640)) + (PORT datac (673:673:673) (798:798:798)) + (PORT datad (818:818:818) (944:944:944)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datac (487:487:487) (574:574:574)) + (PORT datad (632:632:632) (728:728:728)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30927,32 +12199,323 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~6) (DELAY (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (396:396:396) (436:436:436)) - (PORT ena (619:619:619) (673:673:673)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (698:698:698) (830:830:830)) + (PORT datab (575:575:575) (689:689:689)) + (PORT datad (523:523:523) (614:614:614)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (408:408:408)) - (PORT datab (333:333:333) (391:391:391)) - (PORT datad (326:326:326) (381:381:381)) + (PORT dataa (389:389:389) (468:468:468)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (359:359:359) (431:431:431)) + (PORT datad (510:510:510) (600:600:600)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (596:596:596)) + (PORT datac (323:323:323) (379:379:379)) + (PORT datad (345:345:345) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (930:930:930)) + (PORT datad (629:629:629) (723:723:723)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (715:715:715)) + (PORT datab (882:882:882) (1039:1039:1039)) + (PORT datac (722:722:722) (849:849:849)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~8) + (DELAY + (ABSOLUTE + (PORT datab (617:617:617) (748:748:748)) + (PORT datac (433:433:433) (502:502:502)) + (PORT datad (1044:1044:1044) (1194:1194:1194)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (598:598:598)) + (PORT datab (459:459:459) (527:527:527)) + (PORT datac (513:513:513) (595:595:595)) + (PORT datad (374:374:374) (438:438:438)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (733:733:733)) + (PORT datab (371:371:371) (445:445:445)) + (PORT datac (636:636:636) (727:727:727)) + (PORT datad (167:167:167) (196:196:196)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (153:153:153)) + (PORT datab (805:805:805) (936:936:936)) + (PORT datac (480:480:480) (549:549:549)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (384:384:384)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (347:347:347) (409:409:409)) + (PORT datad (1126:1126:1126) (1295:1295:1295)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (519:519:519)) + (PORT datab (478:478:478) (557:557:557)) + (PORT datac (392:392:392) (478:478:478)) + (PORT datad (345:345:345) (409:409:409)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (101:101:101) (133:133:133)) + (PORT datab (549:549:549) (631:631:631)) + (PORT datac (189:189:189) (229:229:229)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (571:571:571)) + (PORT datab (353:353:353) (415:415:415)) + (PORT datac (893:893:893) (1036:1036:1036)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (428:428:428)) + (PORT datab (556:556:556) (653:653:653)) + (PORT datac (321:321:321) (370:370:370)) + (PORT datad (335:335:335) (392:392:392)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (555:555:555)) + (PORT datab (118:118:118) (148:148:148)) + (PORT datac (974:974:974) (1117:1117:1117)) + (PORT datad (1058:1058:1058) (1215:1215:1215)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1460:1460:1460)) + (PORT datab (422:422:422) (518:518:518)) + (PORT datac (366:366:366) (450:450:450)) + (PORT datad (1010:1010:1010) (1176:1176:1176)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1239:1239:1239)) + (PORT datab (211:211:211) (247:247:247)) + (PORT datac (491:491:491) (562:562:562)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (537:537:537)) + (PORT datab (385:385:385) (465:465:465)) + (PORT datac (559:559:559) (668:668:668)) + (PORT datad (748:748:748) (857:857:857)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (519:519:519)) + (PORT datab (804:804:804) (948:948:948)) + (PORT datac (548:548:548) (624:624:624)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (417:417:417) (468:468:468)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (528:528:528) (607:607:607)) + (PORT datac (185:185:185) (224:224:224)) + (PORT datad (357:357:357) (420:420:420)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -30962,9 +12525,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (906:906:906) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (611:611:611) (658:658:658)) + (PORT ena (886:886:886) (964:964:964)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -30973,16 +12536,199 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (239:239:239)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (172:172:172) (198:198:198)) + (PORT datad (675:675:675) (780:780:780)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (397:397:397)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (335:335:335) (391:391:391)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1669:1669:1669)) + (PORT datac (719:719:719) (834:834:834)) + (PORT datad (758:758:758) (886:886:886)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (432:432:432)) + (PORT datac (330:330:330) (396:396:396)) + (PORT datad (708:708:708) (835:835:835)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (165:165:165)) + (PORT datab (509:509:509) (593:593:593)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (836:836:836) (965:965:965)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (604:604:604)) + (PORT datab (565:565:565) (645:645:645)) + (PORT datac (608:608:608) (687:687:687)) + (PORT datad (177:177:177) (213:213:213)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1053:1053:1053) (1229:1229:1229)) + (PORT datab (547:547:547) (629:629:629)) + (PORT datac (672:672:672) (773:773:773)) + (PORT datad (453:453:453) (514:514:514)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (357:357:357) (423:423:423)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (260:260:260)) + (PORT datab (376:376:376) (445:445:445)) + (PORT datac (277:277:277) (312:312:312)) + (PORT datad (486:486:486) (558:558:558)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (446:446:446)) + (PORT datac (184:184:184) (224:224:224)) + (PORT datad (291:291:291) (332:332:332)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (464:464:464) (502:502:502)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (447:447:447)) + (PORT datac (185:185:185) (225:225:225)) + (PORT datad (288:288:288) (328:328:328)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (295:295:295) (343:343:343)) - (PORT datab (311:311:311) (366:366:366)) - (PORT datad (117:117:117) (154:154:154)) + (PORT dataa (887:887:887) (1047:1047:1047)) + (PORT datab (726:726:726) (873:873:873)) + (PORT datad (628:628:628) (735:735:735)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -30992,12 +12738,320 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (315:315:315)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (826:826:826) (968:968:968)) + (PORT dataa (219:219:219) (278:278:278)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (618:618:618) (721:721:721)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datab (491:491:491) (567:567:567)) + (PORT datac (946:946:946) (1127:1127:1127)) + (PORT datad (468:468:468) (542:542:542)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (418:418:418)) + (PORT datab (944:944:944) (1071:1071:1071)) + (PORT datac (940:940:940) (1105:1105:1105)) + (PORT datad (933:933:933) (1063:1063:1063)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (799:799:799)) + (PORT datab (516:516:516) (607:607:607)) + (PORT datac (503:503:503) (573:573:573)) + (PORT datad (664:664:664) (762:762:762)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (841:841:841)) + (PORT datab (477:477:477) (560:560:560)) + (PORT datac (661:661:661) (777:777:777)) + (PORT datad (621:621:621) (708:708:708)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (924:924:924)) + (PORT datab (491:491:491) (571:571:571)) + (PORT datac (538:538:538) (637:637:637)) + (PORT datad (804:804:804) (959:959:959)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (558:558:558)) + (PORT datab (412:412:412) (500:500:500)) + (PORT datac (513:513:513) (596:596:596)) + (PORT datad (795:795:795) (928:928:928)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (575:575:575) (682:682:682)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (582:582:582)) + (PORT datac (651:651:651) (770:770:770)) + (PORT datad (780:780:780) (885:885:885)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (400:400:400)) + (PORT datab (654:654:654) (746:746:746)) + (PORT datac (666:666:666) (767:767:767)) + (PORT datad (427:427:427) (479:479:479)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (357:357:357)) + (PORT datab (115:115:115) (147:147:147)) + (PORT datac (454:454:454) (506:506:506)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (390:390:390)) + (PORT datab (357:357:357) (421:421:421)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (326:326:326) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (564:564:564)) + (PORT datab (641:641:641) (741:741:741)) + (PORT datac (321:321:321) (376:376:376)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1080:1080:1080)) + (PORT datab (850:850:850) (991:991:991)) + (PORT datac (989:989:989) (1141:1141:1141)) + (PORT datad (1123:1123:1123) (1294:1294:1294)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1121:1121:1121)) + (PORT datab (699:699:699) (803:803:803)) + (PORT datac (382:382:382) (472:472:472)) + (PORT datad (400:400:400) (496:496:496)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (634:634:634)) + (PORT datab (652:652:652) (749:749:749)) + (PORT datac (502:502:502) (587:587:587)) + (PORT datad (1038:1038:1038) (1171:1171:1171)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (572:572:572)) + (PORT datac (479:479:479) (542:542:542)) + (PORT datad (460:460:460) (529:529:529)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (481:481:481) (554:554:554)) + (PORT datac (341:341:341) (397:397:397)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (416:416:416)) + (PORT datad (333:333:333) (389:389:389)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (767:767:767)) + (PORT datab (725:725:725) (872:872:872)) + (PORT datac (622:622:622) (726:726:726)) + (PORT datad (613:613:613) (702:702:702)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31008,8 +13062,8 @@ (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT datac (485:485:485) (569:569:569)) - (PORT datad (180:180:180) (207:207:207)) + (PORT datac (659:659:659) (762:762:762)) + (PORT datad (327:327:327) (373:373:373)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31020,10 +13074,10 @@ (INSTANCE z80_\|address_latch_\|Q\[11\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (953:953:953) (1066:1066:1066)) + (PORT clrn (902:902:902) (889:889:889)) + (PORT ena (917:917:917) (1011:1011:1011)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -31038,8 +13092,150 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT datac (217:217:217) (272:272:272)) - (PORT datad (174:174:174) (206:206:206)) + (PORT datab (390:390:390) (477:477:477)) + (PORT datad (334:334:334) (387:387:387)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (315:315:315)) + (PORT datab (209:209:209) (253:253:253)) + (PORT datac (635:635:635) (734:734:734)) + (PORT datad (347:347:347) (399:399:399)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (684:684:684)) + (PORT datab (528:528:528) (614:614:614)) + (PORT datac (495:495:495) (579:579:579)) + (PORT datad (417:417:417) (477:477:477)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (243:243:243)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (777:777:777)) + (PORT datab (841:841:841) (974:974:974)) + (PORT datac (662:662:662) (758:758:758)) + (PORT datad (266:266:266) (304:304:304)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (862:862:862)) + (PORT datab (533:533:533) (620:620:620)) + (PORT datac (553:553:553) (646:646:646)) + (PORT datad (456:456:456) (520:520:520)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (159:159:159)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (938:938:938) (1077:1077:1077)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (438:438:438) (511:511:511)) + (PORT datac (505:505:505) (578:578:578)) + (PORT datad (721:721:721) (820:820:820)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (658:658:658)) + (PORT datab (778:778:778) (898:898:898)) + (PORT datac (505:505:505) (577:577:577)) + (PORT datad (647:647:647) (750:750:750)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1379:1379:1379) (1622:1622:1622)) + (PORT datab (769:769:769) (924:924:924)) + (PORT datac (463:463:463) (541:541:541)) + (PORT datad (524:524:524) (601:601:601)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31047,28 +13243,18388 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) (DELAY (ABSOLUTE - (PORT dataa (656:656:656) (771:771:771)) - (PORT datab (199:199:199) (235:235:235)) - (PORT datad (279:279:279) (320:320:320)) + (PORT dataa (497:497:497) (587:587:587)) + (PORT datac (925:925:925) (1053:1053:1053)) + (PORT datad (671:671:671) (772:772:772)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (735:735:735)) + (PORT datab (328:328:328) (383:383:383)) + (PORT datac (945:945:945) (1077:1077:1077)) + (PORT datad (346:346:346) (406:406:406)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (365:365:365)) + (PORT datab (990:990:990) (1167:1167:1167)) + (PORT datac (633:633:633) (742:742:742)) + (PORT datad (758:758:758) (919:919:919)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (542:542:542)) + (PORT datab (324:324:324) (369:369:369)) + (PORT datac (339:339:339) (397:397:397)) + (PORT datad (607:607:607) (685:685:685)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (700:700:700)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (337:337:337) (391:391:391)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (1020:1020:1020)) + (PORT datac (699:699:699) (804:804:804)) + (PORT datad (1134:1134:1134) (1321:1321:1321)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~14) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (702:702:702)) + (PORT datab (335:335:335) (388:388:388)) + (PORT datac (630:630:630) (709:709:709)) + (PORT datad (510:510:510) (584:584:584)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (985:985:985)) + (PORT datab (512:512:512) (585:585:585)) + (PORT datac (183:183:183) (207:207:207)) + (PORT datad (166:166:166) (196:196:196)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~15) + (DELAY + (ABSOLUTE + (PORT datab (502:502:502) (572:572:572)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (479:479:479)) + (PORT datab (910:910:910) (1040:1040:1040)) + (PORT datac (641:641:641) (734:734:734)) + (PORT datad (510:510:510) (588:588:588)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (739:739:739)) + (PORT datab (524:524:524) (608:608:608)) + (PORT datac (942:942:942) (1074:1074:1074)) + (PORT datad (347:347:347) (407:407:407)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (967:967:967)) + (PORT datab (756:756:756) (864:864:864)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (496:496:496) (574:574:574)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (741:741:741)) + (PORT datab (123:123:123) (159:159:159)) + (PORT datac (457:457:457) (533:533:533)) + (PORT datad (466:466:466) (537:537:537)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (777:777:777)) + (PORT datab (668:668:668) (774:774:774)) + (PORT datac (497:497:497) (577:577:577)) + (PORT datad (976:976:976) (1112:1112:1112)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1098:1098:1098)) + (PORT datab (329:329:329) (384:384:384)) + (PORT datac (416:416:416) (475:475:475)) + (PORT datad (160:160:160) (183:183:183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (212:212:212) (255:255:255)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (1023:1023:1023)) + (PORT datab (1009:1009:1009) (1164:1164:1164)) + (PORT datac (786:786:786) (887:887:887)) + (PORT datad (1041:1041:1041) (1193:1193:1193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (92:92:92) (117:117:117)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (412:412:412)) + (PORT datab (355:355:355) (418:418:418)) + (PORT datac (341:341:341) (403:403:403)) + (PORT datad (616:616:616) (700:700:700)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (590:590:590)) + (PORT datab (656:656:656) (765:765:765)) + (PORT datac (637:637:637) (732:732:732)) + (PORT datad (341:341:341) (399:399:399)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (576:576:576)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datad (643:643:643) (736:736:736)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (944:944:944) (1078:1078:1078)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (711:711:711)) + (PORT datab (829:829:829) (955:955:955)) + (PORT datac (358:358:358) (424:424:424)) + (PORT datad (508:508:508) (579:579:579)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (527:527:527)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (294:294:294) (342:342:342)) + (PORT datad (590:590:590) (679:679:679)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (399:399:399) (476:476:476)) + (PORT datac (518:518:518) (608:608:608)) + (PORT datad (1051:1051:1051) (1250:1250:1250)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1560:1560:1560)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datad (833:833:833) (972:972:972)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (835:835:835)) + (PORT datab (1484:1484:1484) (1720:1720:1720)) + (PORT datac (674:674:674) (800:800:800)) + (PORT datad (944:944:944) (1124:1124:1124)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (798:798:798)) + (PORT datab (418:418:418) (513:513:513)) + (PORT datad (688:688:688) (793:793:793)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datac (474:474:474) (552:552:552)) + (PORT datad (495:495:495) (578:578:578)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (546:546:546)) + (PORT datab (359:359:359) (418:418:418)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (494:494:494) (570:570:570)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (625:625:625) (710:710:710)) + (PORT datac (307:307:307) (350:350:350)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (505:505:505)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (345:345:345) (407:407:407)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1223:1223:1223)) + (PORT datab (735:735:735) (882:882:882)) + (PORT datac (360:360:360) (440:440:440)) + (PORT datad (461:461:461) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (825:825:825)) + (PORT datab (953:953:953) (1137:1137:1137)) + (PORT datac (1061:1061:1061) (1227:1227:1227)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1419:1419:1419)) + (PORT datab (365:365:365) (426:426:426)) + (PORT datac (1005:1005:1005) (1174:1174:1174)) + (PORT datad (781:781:781) (910:910:910)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1419:1419:1419)) + (PORT datab (1549:1549:1549) (1816:1816:1816)) + (PORT datac (1005:1005:1005) (1173:1173:1173)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1142:1142:1142)) + (PORT datab (528:528:528) (629:629:629)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (782:782:782) (912:912:912)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (944:944:944)) + (PORT datab (666:666:666) (766:766:766)) + (PORT datac (537:537:537) (625:625:625)) + (PORT datad (454:454:454) (517:517:517)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (714:714:714)) + (PORT datab (129:129:129) (164:164:164)) + (PORT datac (934:934:934) (1077:1077:1077)) + (PORT datad (692:692:692) (813:813:813)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (594:594:594)) + (PORT datab (573:573:573) (657:657:657)) + (PORT datac (384:384:384) (427:427:427)) + (PORT datad (570:570:570) (646:646:646)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (551:551:551) (645:645:645)) + (PORT datac (276:276:276) (309:309:309)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (209:209:209)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (161:161:161) (190:190:190)) + (PORT datad (284:284:284) (322:322:322)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (764:764:764)) + (PORT datac (316:316:316) (374:374:374)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (553:553:553)) + (PORT datab (555:555:555) (646:646:646)) + (PORT datac (513:513:513) (609:609:609)) + (PORT datad (973:973:973) (1105:1105:1105)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (1073:1073:1073) (1229:1229:1229)) + (PORT datad (543:543:543) (626:626:626)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (581:581:581)) + (PORT datab (751:751:751) (876:876:876)) + (PORT datac (549:549:549) (658:658:658)) + (PORT datad (697:697:697) (824:824:824)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (363:363:363)) + (PORT datab (651:651:651) (742:742:742)) + (PORT datac (668:668:668) (768:768:768)) + (PORT datad (732:732:732) (851:851:851)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (787:787:787)) + (PORT datab (615:615:615) (742:742:742)) + (PORT datac (605:605:605) (702:702:702)) + (PORT datad (1178:1178:1178) (1371:1371:1371)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (760:760:760)) + (PORT datab (146:146:146) (180:180:180)) + (PORT datac (783:783:783) (889:889:889)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (419:419:419)) + (PORT datab (118:118:118) (148:148:148)) + (PORT datac (507:507:507) (593:593:593)) + (PORT datad (500:500:500) (583:583:583)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (231:231:231)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (447:447:447) (504:504:504)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1087:1087:1087)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (501:501:501) (580:580:580)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (618:618:618)) + (PORT datab (446:446:446) (510:510:510)) + (PORT datac (1151:1151:1151) (1341:1341:1341)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (816:816:816)) + (PORT datab (824:824:824) (957:957:957)) + (PORT datac (667:667:667) (767:767:767)) + (PORT datad (635:635:635) (720:720:720)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1263:1263:1263)) + (PORT datab (561:561:561) (651:651:651)) + (PORT datad (495:495:495) (566:566:566)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1120:1120:1120)) + (PORT datab (556:556:556) (647:647:647)) + (PORT datac (279:279:279) (322:322:322)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (618:618:618)) + (PORT datab (114:114:114) (143:143:143)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1157:1157:1157)) + (PORT datab (518:518:518) (594:594:594)) + (PORT datac (508:508:508) (586:586:586)) + (PORT datad (528:528:528) (623:623:623)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (507:507:507) (590:590:590)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (PORT datab (672:672:672) (780:780:780)) + (PORT datac (794:794:794) (909:909:909)) + (PORT datad (398:398:398) (487:487:487)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (878:878:878)) + (PORT datab (123:123:123) (158:158:158)) + (PORT datac (459:459:459) (536:536:536)) + (PORT datad (625:625:625) (723:723:723)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (770:770:770)) + (PORT datab (307:307:307) (358:358:358)) + (PORT datad (617:617:617) (720:720:720)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (800:800:800)) + (PORT datab (422:422:422) (518:518:518)) + (PORT datad (686:686:686) (790:790:790)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datab (669:669:669) (777:777:777)) + (PORT datac (792:792:792) (907:907:907)) + (PORT datad (402:402:402) (491:491:491)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (580:580:580)) + (PORT datab (697:697:697) (816:816:816)) + (PORT datad (353:353:353) (408:408:408)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datab (671:671:671) (779:779:779)) + (PORT datac (793:793:793) (908:908:908)) + (PORT datad (400:400:400) (489:489:489)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (766:766:766)) + (PORT datab (309:309:309) (356:356:356)) + (PORT datad (618:618:618) (722:722:722)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (PORT datab (672:672:672) (780:780:780)) + (PORT datac (794:794:794) (910:910:910)) + (PORT datad (397:397:397) (486:486:486)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (580:580:580)) + (PORT datab (697:697:697) (816:816:816)) + (PORT datad (345:345:345) (405:405:405)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (689:689:689)) + (PORT datab (281:281:281) (325:325:325)) + (PORT datac (484:484:484) (589:589:589)) + (PORT datad (270:270:270) (311:311:311)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (609:609:609)) + (PORT datac (593:593:593) (686:686:686)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1283:1283:1283) (1487:1487:1487)) + (PORT datab (863:863:863) (1019:1019:1019)) + (PORT datac (465:465:465) (537:537:537)) + (PORT datad (1137:1137:1137) (1324:1324:1324)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (601:601:601)) + (PORT datab (662:662:662) (774:774:774)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (623:623:623) (711:711:711)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (213:213:213)) + (PORT datac (366:366:366) (436:436:436)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (805:805:805)) + (PORT datab (605:605:605) (715:715:715)) + (PORT datad (347:347:347) (408:408:408)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (979:979:979)) + (PORT datab (846:846:846) (979:979:979)) + (PORT datac (784:784:784) (897:897:897)) + (PORT datad (344:344:344) (414:414:414)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (415:415:415)) + (PORT datac (599:599:599) (702:702:702)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~23) + (DELAY + (ABSOLUTE + (PORT datab (647:647:647) (735:735:735)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~29) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (421:421:421)) + (PORT datab (392:392:392) (478:478:478)) + (PORT datac (610:610:610) (685:685:685)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~26) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (134:134:134)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (341:341:341) (401:401:401)) + (PORT datad (338:338:338) (395:395:395)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (246:246:246)) + (PORT datab (385:385:385) (460:460:460)) + (PORT datad (355:355:355) (418:418:418)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (979:979:979)) + (PORT datab (849:849:849) (982:982:982)) + (PORT datac (779:779:779) (892:892:892)) + (PORT datad (347:347:347) (417:417:417)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (245:245:245)) + (PORT datab (448:448:448) (516:516:516)) + (PORT datac (580:580:580) (663:663:663)) + (PORT datad (446:446:446) (505:505:505)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (906:906:906)) + (PORT datab (873:873:873) (1019:1019:1019)) + (PORT datac (180:180:180) (220:220:220)) + (PORT datad (862:862:862) (1005:1005:1005)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (1034:1034:1034)) + (PORT datab (875:875:875) (1021:1021:1021)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (389:389:389) (477:477:477)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1156:1156:1156)) + (PORT datab (518:518:518) (594:594:594)) + (PORT datac (509:509:509) (586:586:586)) + (PORT datad (528:528:528) (623:623:623)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (583:583:583)) + (PORT datab (694:694:694) (813:813:813)) + (PORT datad (662:662:662) (764:764:764)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (1024:1024:1024)) + (PORT datab (868:868:868) (1013:1013:1013)) + (PORT datac (182:182:182) (223:223:223)) + (PORT datad (394:394:394) (482:482:482)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (469:469:469) (547:547:547)) + (PORT datad (109:109:109) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (1033:1033:1033)) + (PORT datab (875:875:875) (1021:1021:1021)) + (PORT datac (179:179:179) (220:220:220)) + (PORT datad (692:692:692) (829:829:829)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (704:704:704)) + (PORT datab (679:679:679) (789:789:789)) + (PORT datac (254:254:254) (294:294:294)) + (PORT datad (317:317:317) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (763:763:763)) + (PORT datab (580:580:580) (671:671:671)) + (PORT datad (620:620:620) (724:724:724)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (586:586:586)) + (PORT datab (693:693:693) (812:812:812)) + (PORT datad (358:358:358) (414:414:414)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (659:659:659) (735:735:735)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (586:586:586)) + (PORT datab (694:694:694) (812:812:812)) + (PORT datad (343:343:343) (404:404:404)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (659:659:659) (735:735:735)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (537:537:537)) + (PORT datab (128:128:128) (176:176:176)) + (PORT datad (436:436:436) (505:505:505)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (341:341:341)) + (PORT datac (640:640:640) (739:739:739)) + (PORT datad (620:620:620) (724:724:724)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1035:1035:1035) (1176:1176:1176)) + (PORT ena (521:521:521) (565:565:565)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (307:307:307) (359:359:359)) + (PORT datac (646:646:646) (745:745:745)) + (PORT datad (617:617:617) (721:721:721)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1035:1035:1035) (1176:1176:1176)) + (PORT ena (418:418:418) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (765:765:765)) + (PORT datab (306:306:306) (358:358:358)) + (PORT datad (619:619:619) (723:723:723)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (560:560:560)) + (PORT datab (129:129:129) (163:163:163)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (609:609:609)) + (PORT datac (594:594:594) (687:687:687)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (1033:1033:1033)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (854:854:854) (999:999:999)) + (PORT datad (391:391:391) (480:480:480)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (1055:1055:1055) (1220:1220:1220)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (1036:1036:1036)) + (PORT datab (202:202:202) (244:244:244)) + (PORT datac (857:857:857) (1001:1001:1001)) + (PORT datad (389:389:389) (478:478:478)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (1056:1056:1056) (1222:1222:1222)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (441:441:441)) + (PORT datab (354:354:354) (416:416:416)) + (PORT datad (187:187:187) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (583:583:583)) + (PORT datab (696:696:696) (814:814:814)) + (PORT datad (663:663:663) (765:765:765)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (736:736:736) (833:833:833)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (869:869:869) (1022:1022:1022)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (1028:1028:1028)) + (PORT datab (713:713:713) (857:857:857)) + (PORT datac (851:851:851) (995:995:995)) + (PORT datad (188:188:188) (225:225:225)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (605:605:605)) + (PORT datab (486:486:486) (568:568:568)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (1028:1028:1028)) + (PORT datab (871:871:871) (1016:1016:1016)) + (PORT datac (779:779:779) (885:885:885)) + (PORT datad (188:188:188) (225:225:225)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (505:505:505) (561:561:561)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (385:385:385) (460:460:460)) + (PORT datad (357:357:357) (420:420:420)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (511:511:511) (567:567:567)) + (PORT ena (934:934:934) (1032:1032:1032)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (243:243:243) (294:294:294)) + (PORT datad (641:641:641) (745:745:745)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (417:417:417)) + (PORT datac (596:596:596) (698:698:698)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (635:635:635) (706:706:706)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (572:572:572)) + (PORT datab (673:673:673) (782:782:782)) + (PORT datad (467:467:467) (537:537:537)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (343:343:343) (403:403:403)) + (PORT datac (173:173:173) (209:209:209)) + (PORT datad (330:330:330) (383:383:383)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (724:724:724)) + (PORT datab (126:126:126) (159:159:159)) + (PORT datac (339:339:339) (396:396:396)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (771:771:771) (848:848:848)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (451:451:451) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (113:113:113) (141:141:141)) + (PORT datac (326:326:326) (378:378:378)) + (PORT datad (307:307:307) (354:354:354)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (583:583:583)) + (PORT datab (609:609:609) (697:697:697)) + (PORT datac (500:500:500) (588:588:588)) + (PORT datad (486:486:486) (574:574:574)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (937:937:937)) + (PORT datab (503:503:503) (604:604:604)) + (PORT datac (312:312:312) (376:376:376)) + (PORT datad (345:345:345) (405:405:405)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (587:587:587)) + (PORT datab (462:462:462) (534:534:534)) + (PORT datad (631:631:631) (718:718:718)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (976:976:976)) + (PORT datab (510:510:510) (587:587:587)) + (PORT datac (530:530:530) (617:617:617)) + (PORT datad (511:511:511) (590:590:590)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (863:863:863)) + (PORT datab (481:481:481) (559:559:559)) + (PORT datac (513:513:513) (602:602:602)) + (PORT datad (655:655:655) (774:774:774)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (958:958:958)) + (PORT datab (806:806:806) (921:921:921)) + (PORT datac (940:940:940) (1098:1098:1098)) + (PORT datad (453:453:453) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (338:338:338)) + (PORT datab (548:548:548) (646:646:646)) + (PORT datac (259:259:259) (297:297:297)) + (PORT datad (575:575:575) (653:653:653)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (430:430:430)) + (PORT datab (622:622:622) (709:709:709)) + (PORT datac (397:397:397) (446:446:446)) + (PORT datad (445:445:445) (534:534:534)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (744:744:744)) + (PORT datab (178:178:178) (217:217:217)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (293:293:293) (328:328:328)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (155:155:155)) + (PORT datab (510:510:510) (592:592:592)) + (PORT datac (466:466:466) (538:538:538)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (690:690:690) (821:821:821)) + (PORT datac (659:659:659) (772:772:772)) + (PORT datad (769:769:769) (899:899:899)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (358:358:358) (421:421:421)) + (PORT datac (481:481:481) (558:558:558)) + (PORT datad (678:678:678) (780:780:780)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (121:121:121) (151:151:151)) + (PORT datad (333:333:333) (388:388:388)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (668:668:668)) + (PORT datab (461:461:461) (535:535:535)) + (PORT datac (999:999:999) (1130:1130:1130)) + (PORT datad (604:604:604) (697:697:697)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (685:685:685)) + (PORT datab (298:298:298) (352:352:352)) + (PORT datac (374:374:374) (451:451:451)) + (PORT datad (117:117:117) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (353:353:353)) + (PORT datab (470:470:470) (541:541:541)) + (PORT datac (91:91:91) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (491:491:491)) + (PORT datab (385:385:385) (470:470:470)) + (PORT datac (777:777:777) (873:873:873)) + (PORT datad (599:599:599) (684:684:684)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (154:154:154)) + (PORT datab (506:506:506) (581:581:581)) + (PORT datac (620:620:620) (706:706:706)) + (PORT datad (797:797:797) (898:898:898)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (929:929:929)) + (PORT datab (631:631:631) (731:731:731)) + (PORT datac (791:791:791) (921:921:921)) + (PORT datad (344:344:344) (404:404:404)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (788:788:788) (918:918:918)) + (PORT datad (104:104:104) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (812:812:812)) + (PORT datab (1029:1029:1029) (1182:1182:1182)) + (PORT datac (340:340:340) (398:398:398)) + (PORT datad (597:597:597) (706:706:706)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (806:806:806)) + (PORT datab (419:419:419) (506:506:506)) + (PORT datac (393:393:393) (482:482:482)) + (PORT datad (688:688:688) (791:791:791)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (673:673:673)) + (PORT datac (674:674:674) (798:798:798)) + (PORT datad (120:120:120) (145:145:145)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (144:144:144)) + (PORT datab (987:987:987) (1128:1128:1128)) + (PORT datac (855:855:855) (1029:1029:1029)) + (PORT datad (435:435:435) (500:500:500)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (531:531:531)) + (PORT datab (848:848:848) (976:976:976)) + (PORT datac (592:592:592) (664:664:664)) + (PORT datad (163:163:163) (193:193:193)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (890:890:890)) + (PORT datab (492:492:492) (572:572:572)) + (PORT datac (702:702:702) (832:832:832)) + (PORT datad (586:586:586) (703:703:703)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (639:639:639)) + (PORT datab (532:532:532) (615:615:615)) + (PORT datac (891:891:891) (1019:1019:1019)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (716:716:716)) + (PORT datab (497:497:497) (573:573:573)) + (PORT datac (789:789:789) (920:920:920)) + (PORT datad (653:653:653) (744:744:744)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (1043:1043:1043)) + (PORT datab (514:514:514) (591:591:591)) + (PORT datac (434:434:434) (488:488:488)) + (PORT datad (695:695:695) (804:804:804)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (673:673:673)) + (PORT datab (723:723:723) (862:862:862)) + (PORT datac (176:176:176) (210:210:210)) + (PORT datad (287:287:287) (332:332:332)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (410:410:410)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (494:494:494) (563:563:563)) + (PORT datad (341:341:341) (396:396:396)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (225:225:225)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (311:311:311) (359:359:359)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (893:893:893)) + (PORT datab (500:500:500) (575:575:575)) + (PORT datac (700:700:700) (830:830:830)) + (PORT datad (588:588:588) (705:705:705)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (432:432:432)) + (PORT datab (506:506:506) (587:587:587)) + (PORT datac (292:292:292) (338:338:338)) + (PORT datad (302:302:302) (348:348:348)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (146:146:146)) + (PORT datab (348:348:348) (412:412:412)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (457:457:457) (524:524:524)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (391:391:391)) + (PORT datab (334:334:334) (392:392:392)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (487:487:487) (564:564:564)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (148:148:148)) + (PORT datab (502:502:502) (584:584:584)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (103:103:103) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (857:857:857)) + (PORT datab (308:308:308) (360:360:360)) + (PORT datac (663:663:663) (760:760:760)) + (PORT datad (967:967:967) (1117:1117:1117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (738:738:738)) + (PORT datab (225:225:225) (285:285:285)) + (PORT datad (234:234:234) (286:286:286)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (582:582:582)) + (PORT datab (968:968:968) (1117:1117:1117)) + (PORT datac (721:721:721) (833:833:833)) + (PORT datad (542:542:542) (625:625:625)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (518:518:518) (609:609:609)) + (PORT datac (354:354:354) (414:414:414)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (552:552:552)) + (PORT datab (638:638:638) (734:734:734)) + (PORT datac (743:743:743) (843:843:843)) + (PORT datad (483:483:483) (557:557:557)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (698:698:698)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (802:802:802) (924:924:924)) + (PORT datad (176:176:176) (208:208:208)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (651:651:651)) + (PORT datab (608:608:608) (695:695:695)) + (PORT datac (486:486:486) (573:573:573)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT datab (772:772:772) (879:879:879)) + (PORT datad (755:755:755) (858:858:858)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (905:905:905)) + (PORT datab (186:186:186) (225:225:225)) + (PORT datac (635:635:635) (728:728:728)) + (PORT datad (585:585:585) (661:661:661)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (449:449:449)) + (PORT datab (812:812:812) (934:934:934)) + (PORT datac (462:462:462) (540:540:540)) + (PORT datad (671:671:671) (769:769:769)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (544:544:544)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (631:631:631) (707:707:707)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (486:486:486)) + (PORT datab (1029:1029:1029) (1183:1183:1183)) + (PORT datac (373:373:373) (451:451:451)) + (PORT datad (698:698:698) (811:811:811)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (217:217:217)) + (PORT datab (305:305:305) (357:357:357)) + (PORT datac (349:349:349) (409:409:409)) + (PORT datad (284:284:284) (324:324:324)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT datab (109:109:109) (139:139:139)) + (PORT datac (480:480:480) (559:559:559)) + (PORT datad (317:317:317) (362:362:362)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (353:353:353) (413:413:413)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (891:891:891)) + (PORT datab (490:490:490) (570:570:570)) + (PORT datac (537:537:537) (637:637:637)) + (PORT datad (805:805:805) (961:961:961)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (145:145:145)) + (PORT datab (347:347:347) (410:410:410)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (455:455:455) (523:523:523)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (391:391:391)) + (PORT datad (488:488:488) (565:565:565)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (745:745:745)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (606:606:606) (684:684:684)) + (PORT datad (634:634:634) (719:719:719)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (719:719:719)) + (PORT datab (1006:1006:1006) (1160:1160:1160)) + (PORT datac (826:826:826) (948:948:948)) + (PORT datad (819:819:819) (945:945:945)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (560:560:560)) + (PORT datab (110:110:110) (140:140:140)) + (PORT datac (931:931:931) (1055:1055:1055)) + (PORT datad (820:820:820) (947:947:947)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (480:480:480)) + (PORT datab (798:798:798) (916:916:916)) + (PORT datac (901:901:901) (1024:1024:1024)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (426:426:426)) + (PORT datab (547:547:547) (639:639:639)) + (PORT datac (685:685:685) (786:786:786)) + (PORT datad (682:682:682) (796:796:796)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (759:759:759) (854:854:854)) + (PORT datad (654:654:654) (744:744:744)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (585:585:585)) + (PORT datab (553:553:553) (651:651:651)) + (PORT datac (541:541:541) (627:627:627)) + (PORT datad (579:579:579) (672:672:672)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (608:608:608)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (508:508:508) (590:590:590)) + (PORT datad (501:501:501) (572:572:572)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (239:239:239)) + (PORT datab (1016:1016:1016) (1176:1176:1176)) + (PORT datac (620:620:620) (707:707:707)) + (PORT datad (287:287:287) (323:323:323)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (530:530:530)) + (PORT datab (472:472:472) (546:546:546)) + (PORT datac (999:999:999) (1157:1157:1157)) + (PORT datad (327:327:327) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (754:754:754)) + (PORT datab (651:651:651) (748:748:748)) + (PORT datac (502:502:502) (587:587:587)) + (PORT datad (328:328:328) (382:382:382)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (274:274:274)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (517:517:517) (599:599:599)) + (PORT datad (307:307:307) (350:350:350)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (273:273:273)) + (PORT datab (1125:1125:1125) (1294:1294:1294)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (822:822:822) (942:942:942)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (786:786:786)) + (PORT datab (677:677:677) (780:780:780)) + (PORT datac (777:777:777) (886:886:886)) + (PORT datad (486:486:486) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (911:911:911)) + (PORT datab (1008:1008:1008) (1163:1163:1163)) + (PORT datac (806:806:806) (921:921:921)) + (PORT datad (376:376:376) (442:442:442)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (781:781:781)) + (PORT datab (369:369:369) (434:434:434)) + (PORT datac (901:901:901) (1030:1030:1030)) + (PORT datad (629:629:629) (719:719:719)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (754:754:754)) + (PORT datab (467:467:467) (536:536:536)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (325:325:325) (379:379:379)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (857:857:857)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (353:353:353) (413:413:413)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (273:273:273)) + (PORT datab (114:114:114) (143:143:143)) + (PORT datac (892:892:892) (1020:1020:1020)) + (PORT datad (308:308:308) (350:350:350)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (922:922:922)) + (PORT datab (242:242:242) (302:302:302)) + (PORT datac (611:611:611) (713:713:713)) + (PORT datad (208:208:208) (258:258:258)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (904:904:904)) + (PORT datab (531:531:531) (614:614:614)) + (PORT datac (442:442:442) (508:508:508)) + (PORT datad (309:309:309) (352:352:352)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (966:966:966)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (528:528:528) (616:616:616)) + (PORT datad (159:159:159) (186:186:186)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (597:597:597)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (521:521:521) (601:601:601)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (886:886:886)) + (PORT datab (848:848:848) (976:976:976)) + (PORT datac (446:446:446) (514:514:514)) + (PORT datad (690:690:690) (794:794:794)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (418:418:418)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (774:774:774) (880:880:880)) + (PORT datad (447:447:447) (505:505:505)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (493:493:493)) + (PORT datab (1033:1033:1033) (1186:1186:1186)) + (PORT datac (676:676:676) (783:783:783)) + (PORT datad (616:616:616) (721:721:721)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (117:117:117) (150:150:150)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (444:444:444) (502:502:502)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (580:580:580)) + (PORT datab (514:514:514) (601:601:601)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (302:302:302) (349:349:349)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (431:431:431)) + (PORT datad (430:430:430) (494:494:494)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (882:882:882)) + (PORT datab (773:773:773) (880:880:880)) + (PORT datac (618:618:618) (714:714:714)) + (PORT datad (768:768:768) (881:881:881)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datac (474:474:474) (552:552:552)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (748:748:748)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (1259:1259:1259) (1436:1436:1436)) + (PORT datad (644:644:644) (736:736:736)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (755:755:755)) + (PORT datab (701:701:701) (803:803:803)) + (PORT datac (557:557:557) (636:636:636)) + (PORT datad (483:483:483) (559:559:559)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (148:148:148)) + (PORT datab (402:402:402) (477:477:477)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (1407:1407:1407) (1602:1602:1602)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (777:777:777)) + (PORT datab (1559:1559:1559) (1803:1803:1803)) + (PORT datac (813:813:813) (958:958:958)) + (PORT datad (285:285:285) (324:324:324)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (839:839:839)) + (PORT datab (963:963:963) (1108:1108:1108)) + (PORT datac (663:663:663) (779:779:779)) + (PORT datad (618:618:618) (705:705:705)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (575:575:575)) + (PORT datab (385:385:385) (455:455:455)) + (PORT datac (866:866:866) (1007:1007:1007)) + (PORT datad (513:513:513) (586:586:586)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (714:714:714)) + (PORT datab (635:635:635) (727:727:727)) + (PORT datac (443:443:443) (510:510:510)) + (PORT datad (688:688:688) (797:797:797)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (421:421:421)) + (PORT datab (524:524:524) (610:610:610)) + (PORT datac (837:837:837) (965:965:965)) + (PORT datad (501:501:501) (576:576:576)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (630:630:630)) + (PORT datab (507:507:507) (594:594:594)) + (PORT datac (962:962:962) (1126:1126:1126)) + (PORT datad (530:530:530) (638:638:638)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (347:347:347) (410:410:410)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (805:805:805)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (478:478:478) (551:551:551)) + (PORT datad (329:329:329) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (334:334:334) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (221:221:221)) + (PORT datab (656:656:656) (765:765:765)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (587:587:587) (680:680:680)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (153:153:153)) + (PORT datab (653:653:653) (760:760:760)) + (PORT datac (590:590:590) (683:683:683)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (600:600:600)) + (PORT datab (693:693:693) (811:811:811)) + (PORT datad (661:661:661) (763:763:763)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (722:722:722)) + (PORT datad (637:637:637) (737:737:737)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (975:975:975)) + (PORT datab (122:122:122) (155:155:155)) + (PORT datac (828:828:828) (955:955:955)) + (PORT datad (689:689:689) (826:826:826)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (978:978:978)) + (PORT datab (845:845:845) (978:978:978)) + (PORT datac (787:787:787) (900:900:900)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (752:752:752)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (601:601:601) (704:704:704)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1204:1204:1204)) + (PORT datab (381:381:381) (472:472:472)) + (PORT datac (1250:1250:1250) (1437:1437:1437)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (515:515:515)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (344:344:344) (395:395:395)) + (PORT datad (790:790:790) (924:924:924)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (432:432:432) (489:489:489)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT datab (370:370:370) (439:439:439)) + (PORT datac (366:366:366) (440:440:440)) + (PORT datad (196:196:196) (233:233:233)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (752:752:752)) + (PORT datac (602:602:602) (705:705:705)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (356:356:356)) + (PORT datab (327:327:327) (381:381:381)) + (PORT datac (486:486:486) (571:571:571)) + (PORT datad (305:305:305) (348:348:348)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (478:478:478)) + (PORT datac (403:403:403) (495:495:495)) + (PORT datad (350:350:350) (406:406:406)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (539:539:539)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (97:97:97) (121:121:121)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (978:978:978)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datac (826:826:826) (953:953:953)) + (PORT datad (377:377:377) (457:457:457)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (977:977:977)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datac (827:827:827) (953:953:953)) + (PORT datad (377:377:377) (458:458:458)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1077:1077:1077)) + (PORT datab (224:224:224) (269:269:269)) + (PORT datac (307:307:307) (349:349:349)) + (PORT datad (205:205:205) (243:243:243)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (427:427:427)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (270:270:270) (312:312:312)) + (PORT datad (168:168:168) (199:199:199)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (606:606:606) (706:706:706)) + (PORT datac (636:636:636) (737:737:737)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (641:641:641) (743:743:743)) + (PORT datad (588:588:588) (681:681:681)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (683:683:683) (755:755:755)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (657:657:657) (765:765:765)) + (PORT datac (594:594:594) (687:687:687)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (679:679:679) (751:751:751)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (634:634:634)) + (PORT datab (397:397:397) (463:463:463)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (748:748:748)) + (PORT datab (643:643:643) (749:749:749)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (920:920:920)) + (PORT datab (814:814:814) (942:942:942)) + (PORT datac (103:103:103) (132:132:132)) + (PORT datad (827:827:827) (954:954:954)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (280:280:280) (300:300:300)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (947:947:947)) + (PORT datab (544:544:544) (623:623:623)) + (PORT datad (426:426:426) (485:485:485)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (753:753:753)) + (PORT datac (604:604:604) (707:707:707)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (535:535:535) (591:591:591)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (349:349:349) (399:399:399)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (751:751:751)) + (PORT datab (125:125:125) (157:157:157)) + (PORT datac (601:601:601) (703:703:703)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (437:437:437)) + (PORT datab (391:391:391) (458:458:458)) + (PORT datad (190:190:190) (238:238:238)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (345:345:345) (394:394:394)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (597:597:597)) + (PORT datab (698:698:698) (817:817:817)) + (PORT datad (664:664:664) (766:766:766)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (810:810:810) (883:883:883)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (159:159:159)) + (PORT datab (849:849:849) (982:982:982)) + (PORT datac (820:820:820) (957:957:957)) + (PORT datad (842:842:842) (992:992:992)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (534:534:534) (590:590:590)) + (PORT ena (660:660:660) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (396:396:396)) + (PORT datab (369:369:369) (433:433:433)) + (PORT datad (493:493:493) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (437:437:437) (500:500:500)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (486:486:486)) + (PORT datab (850:850:850) (983:983:983)) + (PORT datac (107:107:107) (136:136:136)) + (PORT datad (801:801:801) (920:920:920)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (481:481:481)) + (PORT datab (845:845:845) (978:978:978)) + (PORT datac (100:100:100) (128:128:128)) + (PORT datad (800:800:800) (919:919:919)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (617:617:617) (679:679:679)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (414:414:414)) + (PORT datab (220:220:220) (265:265:265)) + (PORT datad (203:203:203) (240:240:240)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT datab (364:364:364) (433:433:433)) + (PORT datac (367:367:367) (441:441:441)) + (PORT datad (197:197:197) (234:234:234)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (617:617:617) (679:679:679)) + (PORT ena (818:818:818) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (511:511:511) (598:598:598)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (379:379:379)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (462:462:462) (524:524:524)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (599:599:599)) + (PORT datab (694:694:694) (813:813:813)) + (PORT datad (344:344:344) (404:404:404)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (599:599:599)) + (PORT datab (694:694:694) (812:812:812)) + (PORT datad (357:357:357) (413:413:413)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (597:597:597)) + (PORT datab (699:699:699) (818:818:818)) + (PORT datad (345:345:345) (405:405:405)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (672:672:672) (741:741:741)) + (PORT ena (810:810:810) (884:884:884)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (598:598:598)) + (PORT datab (697:697:697) (815:815:815)) + (PORT datad (354:354:354) (410:410:410)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (671:671:671) (741:741:741)) + (PORT ena (792:792:792) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (611:611:611)) + (PORT datab (534:534:534) (618:618:618)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (311:311:311) (369:369:369)) + (PORT datad (172:172:172) (204:204:204)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (565:565:565)) + (PORT datab (461:461:461) (539:539:539)) + (PORT datac (496:496:496) (581:581:581)) + (PORT datad (311:311:311) (356:356:356)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (260:260:260)) + (PORT datab (526:526:526) (605:605:605)) + (PORT datad (348:348:348) (407:407:407)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT asdata (458:458:458) (500:500:500)) + (PORT ena (640:640:640) (692:692:692)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (259:259:259)) + (PORT datab (528:528:528) (607:607:607)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (807:807:807)) + (PORT datab (351:351:351) (418:418:418)) + (PORT datad (349:349:349) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (259:259:259)) + (PORT datab (369:369:369) (439:439:439)) + (PORT datad (289:289:289) (329:329:329)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (658:658:658) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (363:363:363) (432:432:432)) + (PORT datad (292:292:292) (333:333:333)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (356:356:356) (415:415:415)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (439:439:439)) + (PORT datab (358:358:358) (416:416:416)) + (PORT datac (673:673:673) (788:788:788)) + (PORT datad (345:345:345) (403:403:403)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (321:321:321) (387:387:387)) + (PORT datad (602:602:602) (684:684:684)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (658:658:658) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (628:628:628) (688:688:688)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (627:627:627) (688:688:688)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (629:629:629)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (382:382:382) (442:442:442)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (635:635:635) (699:699:699)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (948:948:948)) + (PORT datab (451:451:451) (518:518:518)) + (PORT datad (426:426:426) (485:485:485)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (773:773:773) (844:844:844)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (501:501:501) (570:570:570)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (440:440:440)) + (PORT datab (394:394:394) (461:461:461)) + (PORT datad (187:187:187) (235:235:235)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (497:497:497) (544:544:544)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (272:272:272)) + (PORT datab (219:219:219) (263:263:263)) + (PORT datad (202:202:202) (239:239:239)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (496:496:496) (544:544:544)) + (PORT ena (818:818:818) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (512:512:512) (599:599:599)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (502:502:502) (571:571:571)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (810:810:810) (883:883:883)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (773:773:773) (845:845:845)) + (PORT ena (660:660:660) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (410:410:410)) + (PORT datab (366:366:366) (429:429:429)) + (PORT datad (492:492:492) (554:554:554)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (409:409:409)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (479:479:479) (557:557:557)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (631:631:631) (691:691:691)) + (PORT ena (810:810:810) (884:884:884)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (631:631:631) (691:691:691)) + (PORT ena (792:792:792) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (610:610:610)) + (PORT datab (530:530:530) (613:613:613)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (319:319:319) (378:378:378)) + (PORT datad (161:161:161) (190:190:190)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (520:520:520)) + (PORT datab (454:454:454) (527:527:527)) + (PORT datac (296:296:296) (336:336:336)) + (PORT datad (320:320:320) (369:369:369)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT asdata (449:449:449) (488:488:488)) + (PORT ena (640:640:640) (692:692:692)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (805:805:805)) + (PORT datab (599:599:599) (676:676:676)) + (PORT datad (351:351:351) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (132:132:132) (180:180:180)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (356:356:356) (414:414:414)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (433:433:433)) + (PORT datab (294:294:294) (341:341:341)) + (PORT datac (122:122:122) (151:151:151)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (423:423:423)) + (PORT datad (415:415:415) (474:474:474)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (198:198:198)) + (PORT datab (303:303:303) (351:351:351)) + (PORT datac (322:322:322) (388:388:388)) + (PORT datad (602:602:602) (684:684:684)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (435:435:435)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (120:120:120) (149:149:149)) + (PORT datad (549:549:549) (617:617:617)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (424:424:424)) + (PORT datad (451:451:451) (521:521:521)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (387:387:387)) + (PORT datad (133:133:133) (173:173:173)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (387:387:387)) + (PORT datab (339:339:339) (411:411:411)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (709:709:709)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (658:658:658) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT asdata (443:443:443) (479:479:479)) + (PORT ena (640:640:640) (692:692:692)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (811:811:811)) + (PORT datab (450:450:450) (526:526:526)) + (PORT datad (346:346:346) (404:404:404)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (355:355:355) (414:414:414)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (435:435:435)) + (PORT datab (444:444:444) (510:510:510)) + (PORT datac (119:119:119) (147:147:147)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (439:439:439) (505:505:505)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (419:419:419) (439:439:439)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (614:614:614) (675:675:675)) + (PORT ena (434:434:434) (461:461:461)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (156:156:156)) + (PORT datab (128:128:128) (176:176:176)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (472:472:472) (525:525:525)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (1080:1080:1080)) + (PORT datab (462:462:462) (536:536:536)) + (PORT datad (206:206:206) (241:241:241)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (474:474:474) (527:527:527)) + (PORT ena (818:818:818) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~58) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (515:515:515) (602:602:602)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (633:633:633) (699:699:699)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (452:452:452) (521:521:521)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (743:743:743) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (262:262:262)) + (PORT datab (439:439:439) (507:507:507)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (486:486:486) (542:542:542)) + (PORT ena (644:644:644) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (483:483:483) (539:539:539)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (487:487:487) (560:560:560)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (687:687:687) (773:773:773)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (436:436:436)) + (PORT datab (214:214:214) (272:272:272)) + (PORT datad (370:370:370) (430:430:430)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (213:213:213)) + (PORT datab (331:331:331) (386:386:386)) + (PORT datac (292:292:292) (331:331:331)) + (PORT datad (457:457:457) (528:528:528)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (368:368:368)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (512:512:512) (565:565:565)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (630:630:630)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (381:381:381) (441:441:441)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (388:388:388)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (315:315:315) (362:362:362)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (507:507:507)) + (PORT datab (356:356:356) (417:417:417)) + (PORT datac (466:466:466) (538:538:538)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (618:618:618) (722:722:722)) + (PORT datac (198:198:198) (237:237:237)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (708:708:708) (799:799:799)) + (PORT datad (327:327:327) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (446:446:446)) + (PORT datab (144:144:144) (181:181:181)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (408:408:408) (459:459:459)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (828:828:828) (948:948:948)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (529:529:529)) + (PORT datab (674:674:674) (784:784:784)) + (PORT datad (456:456:456) (539:539:539)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (1091:1091:1091) (1263:1263:1263)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (1091:1091:1091) (1263:1263:1263)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (439:439:439)) + (PORT datab (356:356:356) (419:419:419)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (279:279:279) (298:298:298)) + (PORT ena (1146:1146:1146) (1308:1308:1308)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (999:999:999) (1143:1143:1143)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (437:437:437)) + (PORT datab (240:240:240) (291:291:291)) + (PORT datad (634:634:634) (738:738:738)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (895:895:895) (1015:1015:1015)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (892:892:892) (1012:1012:1012)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (601:601:601)) + (PORT datab (479:479:479) (561:561:561)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (548:548:548)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (290:290:290) (332:332:332)) + (PORT datad (458:458:458) (541:541:541)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (828:828:828) (949:949:949)) + (PORT ena (784:784:784) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (874:874:874)) + (PORT datab (761:761:761) (907:907:907)) + (PORT datad (471:471:471) (545:545:545)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT asdata (663:663:663) (752:752:752)) + (PORT ena (808:808:808) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (828:828:828) (949:949:949)) + (PORT ena (821:821:821) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (615:615:615)) + (PORT datab (496:496:496) (608:608:608)) + (PORT datad (562:562:562) (658:658:658)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (681:681:681) (774:774:774)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (680:680:680) (773:773:773)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (541:541:541)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (437:437:437) (507:507:507)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (560:560:560)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (436:436:436)) + (PORT datab (126:126:126) (159:159:159)) + (PORT datac (192:192:192) (229:229:229)) + (PORT datad (325:325:325) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (624:624:624)) + (PORT datab (530:530:530) (628:628:628)) + (PORT datac (297:297:297) (344:344:344)) + (PORT datad (351:351:351) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (372:372:372) (408:408:408)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (768:768:768)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datad (704:704:704) (843:843:843)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (376:376:376)) + (PORT datac (602:602:602) (695:695:695)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (475:475:475) (559:559:559)) + (PORT datad (182:182:182) (209:209:209)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (884:884:884)) + (PORT ena (1063:1063:1063) (1174:1174:1174)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (387:387:387)) + (PORT datad (134:134:134) (174:174:174)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (602:602:602) (683:683:683)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (401:401:401)) + (PORT datac (336:336:336) (393:393:393)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (658:658:658) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (828:828:828) (921:921:921)) + (PORT ena (810:810:810) (884:884:884)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (510:510:510) (578:578:578)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (792:792:792) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (611:611:611)) + (PORT datab (532:532:532) (616:616:616)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (358:358:358) (390:390:390)) + (PORT ena (608:608:608) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (461:461:461) (501:501:501)) + (PORT ena (743:743:743) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (463:463:463) (503:503:503)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (437:437:437) (505:505:505)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (527:527:527)) + (PORT datad (168:168:168) (197:197:197)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (812:812:812) (895:895:895)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (811:811:811) (893:893:893)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (632:632:632)) + (PORT datab (399:399:399) (465:465:465)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (725:725:725)) + (PORT datab (619:619:619) (712:712:712)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (592:592:592) (671:671:671)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (751:751:751) (819:819:819)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (259:259:259)) + (PORT datab (225:225:225) (270:270:270)) + (PORT datad (206:206:206) (244:244:244)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (826:826:826) (912:912:912)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (353:353:353) (402:402:402)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (530:530:530) (576:576:576)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (439:439:439)) + (PORT datab (216:216:216) (273:273:273)) + (PORT datad (372:372:372) (433:433:433)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (389:389:389)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (487:487:487) (572:572:572)) + (PORT datad (333:333:333) (387:387:387)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (548:548:548)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (564:564:564) (636:636:636)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (494:494:494) (569:569:569)) + (PORT datac (337:337:337) (386:386:386)) + (PORT datad (786:786:786) (894:894:894)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT asdata (354:354:354) (384:384:384)) + (PORT ena (640:640:640) (692:692:692)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (802:802:802)) + (PORT datab (347:347:347) (403:403:403)) + (PORT datad (353:353:353) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (356:356:356) (414:414:414)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (435:435:435)) + (PORT datab (419:419:419) (482:482:482)) + (PORT datac (120:120:120) (148:148:148)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datac (656:656:656) (759:759:759)) + (PORT datad (290:290:290) (331:331:331)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (902:902:902) (889:889:889)) + (PORT ena (917:917:917) (1011:1011:1011)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (418:418:418)) + (PORT datab (330:330:330) (401:401:401)) + (PORT datac (131:131:131) (178:178:178)) + (PORT datad (330:330:330) (387:387:387)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (658:658:658) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (702:702:702) (784:784:784)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (707:707:707) (789:789:789)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (628:628:628)) + (PORT datab (403:403:403) (470:470:470)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (623:623:623) (682:682:682)) + (PORT ena (644:644:644) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (619:619:619) (678:678:678)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (615:615:615) (673:673:673)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (530:530:530) (629:629:629)) + (PORT datac (421:421:421) (491:491:491)) + (PORT datad (332:332:332) (388:388:388)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (487:487:487)) + (PORT datab (749:749:749) (872:872:872)) + (PORT datac (595:595:595) (707:707:707)) + (PORT datad (386:386:386) (468:468:468)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (409:409:409)) + (PORT datab (634:634:634) (742:742:742)) + (PORT datac (626:626:626) (713:713:713)) + (PORT datad (445:445:445) (509:509:509)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (512:512:512)) + (PORT datab (947:947:947) (1097:1097:1097)) + (PORT datac (758:758:758) (901:901:901)) + (PORT datad (365:365:365) (441:441:441)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (279:279:279) (299:299:299)) + (PORT ena (914:914:914) (1024:1024:1024)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (199:199:199)) + (PORT datab (153:153:153) (197:197:197)) + (PORT datac (699:699:699) (790:790:790)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (586:586:586)) + (PORT datab (449:449:449) (522:522:522)) + (PORT datac (312:312:312) (370:370:370)) + (PORT datad (444:444:444) (526:526:526)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (395:395:395)) + (PORT datab (372:372:372) (439:439:439)) + (PORT datac (564:564:564) (648:648:648)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (937:937:937)) + (PORT datab (451:451:451) (518:518:518)) + (PORT datac (325:325:325) (384:384:384)) + (PORT datad (510:510:510) (602:602:602)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (482:482:482)) + (PORT datac (595:595:595) (707:707:707)) + (PORT datad (385:385:385) (466:466:466)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (243:243:243)) + (PORT datab (481:481:481) (565:565:565)) + (PORT datac (831:831:831) (967:967:967)) + (PORT datad (122:122:122) (146:146:146)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (485:485:485) (568:568:568)) + (PORT datad (174:174:174) (207:207:207)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1622:1622:1622)) + (PORT datab (524:524:524) (614:614:614)) + (PORT datac (654:654:654) (767:767:767)) + (PORT datad (675:675:675) (796:796:796)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (457:457:457)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (505:505:505) (594:594:594)) + (PORT datad (358:358:358) (421:421:421)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (347:347:347) (412:412:412)) + (PORT datad (101:101:101) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (488:488:488)) + (PORT datab (338:338:338) (399:399:399)) + (PORT datac (340:340:340) (401:401:401)) + (PORT datad (278:278:278) (319:319:319)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~0) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (305:305:305)) + (PORT datab (1155:1155:1155) (1353:1353:1353)) + (PORT datac (633:633:633) (731:731:731)) + (PORT datad (579:579:579) (698:698:698)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (545:545:545)) + (PORT datab (606:606:606) (691:691:691)) + (PORT datac (342:342:342) (405:405:405)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (804:804:804)) + (PORT datab (1033:1033:1033) (1187:1187:1187)) + (PORT datac (744:744:744) (855:855:855)) + (PORT datad (701:701:701) (813:813:813)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (699:699:699)) + (PORT datab (607:607:607) (692:692:692)) + (PORT datac (343:343:343) (406:406:406)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (305:305:305)) + (PORT datab (1154:1154:1154) (1352:1352:1352)) + (PORT datac (631:631:631) (729:729:729)) + (PORT datad (581:581:581) (700:700:700)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (542:542:542)) + (PORT datab (455:455:455) (525:525:525)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (583:583:583)) + (PORT datad (533:533:533) (641:641:641)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (549:549:549)) + (PORT datab (490:490:490) (574:574:574)) + (PORT datac (351:351:351) (413:413:413)) + (PORT datad (330:330:330) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (469:469:469) (556:556:556)) + (PORT datac (462:462:462) (538:538:538)) + (PORT datad (114:114:114) (137:137:137)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1488:1488:1488)) + (PORT datab (452:452:452) (520:520:520)) + (PORT datac (727:727:727) (861:861:861)) + (PORT datad (791:791:791) (900:900:900)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (551:551:551)) + (PORT datab (696:696:696) (800:800:800)) + (PORT datac (348:348:348) (409:409:409)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (821:821:821)) + (PORT datab (187:187:187) (227:227:227)) + (PORT datac (936:936:936) (1113:1113:1113)) + (PORT datad (785:785:785) (915:915:915)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (593:593:593)) + (PORT datab (685:685:685) (808:808:808)) + (PORT datac (1071:1071:1071) (1234:1234:1234)) + (PORT datad (499:499:499) (589:589:589)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (357:357:357) (425:425:425)) + (PORT datac (325:325:325) (373:373:373)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (986:986:986)) + (PORT datab (685:685:685) (821:821:821)) + (PORT datac (185:185:185) (218:218:218)) + (PORT datad (504:504:504) (592:592:592)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (846:846:846)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (836:836:836) (982:982:982)) + (PORT datad (865:865:865) (1019:1019:1019)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (232:232:232)) + (PORT datab (502:502:502) (587:587:587)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (995:995:995) (1126:1126:1126)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (547:547:547)) + (PORT datab (516:516:516) (612:612:612)) + (PORT datac (314:314:314) (370:370:370)) + (PORT datad (1040:1040:1040) (1211:1211:1211)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~20) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (660:660:660)) + (PORT datab (566:566:566) (678:678:678)) + (PORT datad (1184:1184:1184) (1384:1384:1384)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (531:531:531)) + (PORT datab (476:476:476) (566:566:566)) + (PORT datac (314:314:314) (370:370:370)) + (PORT datad (479:479:479) (562:562:562)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (285:285:285) (336:336:336)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (615:615:615)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datac (114:114:114) (141:141:141)) + (PORT datad (792:792:792) (901:901:901)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (264:264:264)) + (PORT datab (475:475:475) (559:559:559)) + (PORT datac (173:173:173) (209:209:209)) + (PORT datad (563:563:563) (665:665:665)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (632:632:632)) + (PORT datab (353:353:353) (420:420:420)) + (PORT datac (712:712:712) (813:813:813)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (345:345:345) (411:411:411)) + (PORT datac (324:324:324) (379:379:379)) + (PORT datad (342:342:342) (400:400:400)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT asdata (282:282:282) (302:302:302)) + (PORT ena (610:610:610) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (768:768:768)) + (PORT datab (632:632:632) (733:733:733)) + (PORT datad (293:293:293) (339:339:339)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (616:616:616) (664:664:664)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (286:286:286) (340:340:340)) + (PORT datad (308:308:308) (359:359:359)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (650:650:650) (753:753:753)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (304:304:304) (351:351:351)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (434:434:434)) + (PORT datab (177:177:177) (215:215:215)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (332:332:332) (386:386:386)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (829:829:829) (920:920:920)) + (PORT ena (434:434:434) (461:461:461)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (657:657:657) (753:753:753)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (419:419:419) (439:439:439)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (973:973:973) (1082:1082:1082)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (973:973:973) (1083:1083:1083)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (633:633:633)) + (PORT datab (398:398:398) (464:464:464)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (1276:1276:1276) (1428:1428:1428)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (1261:1261:1261) (1410:1410:1410)) + (PORT ena (436:436:436) (467:467:467)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (124:124:124) (155:155:155)) + (PORT datad (350:350:350) (425:425:425)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (1526:1526:1526) (1705:1705:1705)) + (PORT ena (818:818:818) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datad (516:516:516) (604:604:604)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (161:161:161) (190:190:190)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (608:608:608) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (1390:1390:1390) (1558:1558:1558)) + (PORT ena (743:743:743) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (259:259:259)) + (PORT datab (200:200:200) (259:259:259)) + (PORT datad (339:339:339) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (947:947:947)) + (PORT datab (441:441:441) (510:510:510)) + (PORT datac (119:119:119) (161:161:161)) + (PORT datad (465:465:465) (525:525:525)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (174:174:174) (212:212:212)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (1438:1438:1438) (1616:1616:1616)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT asdata (512:512:512) (559:559:559)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (440:440:440)) + (PORT datab (393:393:393) (461:461:461)) + (PORT datad (197:197:197) (247:247:247)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (396:396:396)) + (PORT datab (473:473:473) (546:546:546)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (318:318:318) (368:368:368)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (566:566:566)) + (PORT datab (512:512:512) (603:603:603)) + (PORT datac (324:324:324) (373:373:373)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (1088:1088:1088)) + (PORT datab (475:475:475) (553:553:553)) + (PORT datac (473:473:473) (564:564:564)) + (PORT datad (617:617:617) (712:712:712)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (409:409:409)) + (PORT datac (304:304:304) (351:351:351)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (737:737:737)) + (PORT datab (377:377:377) (452:452:452)) + (PORT datac (510:510:510) (586:586:586)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (440:440:440)) + (PORT datab (312:312:312) (367:367:367)) + (PORT datac (502:502:502) (583:583:583)) + (PORT datad (438:438:438) (506:506:506)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (270:270:270) (314:314:314)) + (PORT datad (185:185:185) (213:213:213)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (744:744:744)) + (PORT datab (129:129:129) (163:163:163)) + (PORT datac (317:317:317) (367:367:367)) + (PORT datad (218:218:218) (266:266:266)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (705:705:705)) + (PORT datab (746:746:746) (887:887:887)) + (PORT datac (814:814:814) (937:937:937)) + (PORT datad (574:574:574) (646:646:646)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (616:616:616)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (652:652:652) (760:760:760)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (985:985:985)) + (PORT datab (538:538:538) (634:634:634)) + (PORT datac (951:951:951) (1079:1079:1079)) + (PORT datad (115:115:115) (131:131:131)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (174:174:174)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (105:105:105) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (801:801:801)) + (PORT datab (671:671:671) (778:778:778)) + (PORT datac (511:511:511) (600:600:600)) + (PORT datad (730:730:730) (833:833:833)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (508:508:508)) + (PORT datab (336:336:336) (402:402:402)) + (PORT datac (439:439:439) (511:511:511)) + (PORT datad (281:281:281) (323:323:323)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT3_3) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (757:757:757)) + (PORT datac (1367:1367:1367) (1604:1604:1604)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (841:841:841)) + (PORT datab (512:512:512) (603:603:603)) + (PORT datad (409:409:409) (464:464:464)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (861:861:861)) + (PORT datab (359:359:359) (430:430:430)) + (PORT datac (337:337:337) (390:390:390)) + (PORT datad (993:993:993) (1133:1133:1133)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (395:395:395)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (271:271:271) (312:312:312)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (432:432:432)) + (PORT datab (1102:1102:1102) (1260:1260:1260)) + (PORT datac (434:434:434) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (699:699:699)) + (PORT datab (460:460:460) (532:532:532)) + (PORT datac (334:334:334) (395:395:395)) + (PORT datad (399:399:399) (478:478:478)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (1087:1087:1087)) + (PORT datab (642:642:642) (754:754:754)) + (PORT datac (1017:1017:1017) (1193:1193:1193)) + (PORT datad (924:924:924) (1073:1073:1073)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (577:577:577)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (107:107:107) (136:136:136)) + (PORT datad (465:465:465) (544:544:544)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (629:629:629) (724:724:724)) + (PORT datac (559:559:559) (639:639:639)) + (PORT datad (313:313:313) (363:363:363)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (684:684:684)) + (PORT datab (581:581:581) (693:693:693)) + (PORT datac (688:688:688) (799:799:799)) + (PORT datad (480:480:480) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~1) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (766:766:766) (888:888:888)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (1018:1018:1018) (1183:1183:1183)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (433:433:433)) + (PORT datab (1102:1102:1102) (1260:1260:1260)) + (PORT datac (173:173:173) (210:210:210)) + (PORT datad (496:496:496) (570:570:570)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (648:648:648) (752:752:752)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (931:931:931) (1077:1077:1077)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (548:548:548)) + (PORT datab (128:128:128) (175:175:175)) + (PORT datad (441:441:441) (510:510:510)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (536:536:536) (606:606:606)) + (PORT ena (784:784:784) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (873:873:873)) + (PORT datab (762:762:762) (908:908:908)) + (PORT datad (470:470:470) (544:544:544)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (541:541:541) (613:613:613)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (541:541:541) (613:613:613)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (604:604:604)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (465:465:465) (540:540:540)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (533:533:533) (592:592:592)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (568:568:568)) + (PORT datab (674:674:674) (784:784:784)) + (PORT datad (501:501:501) (569:569:569)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (934:934:934) (1032:1032:1032)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (342:342:342) (370:370:370)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (179:179:179)) + (PORT datab (242:242:242) (292:292:292)) + (PORT datad (638:638:638) (742:742:742)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (948:948:948) (1089:1089:1089)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (947:947:947) (1088:1088:1088)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (437:437:437)) + (PORT datab (358:358:358) (420:420:420)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (547:547:547)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datac (336:336:336) (395:395:395)) + (PORT datad (459:459:459) (547:547:547)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT asdata (846:846:846) (960:960:960)) + (PORT ena (808:808:808) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (535:535:535) (605:605:605)) + (PORT ena (821:821:821) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (615:615:615)) + (PORT datab (483:483:483) (597:597:597)) + (PORT datad (561:561:561) (657:657:657)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (256:256:256)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (466:466:466) (509:509:509)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1235:1235:1235)) + (PORT datab (728:728:728) (875:875:875)) + (PORT datad (626:626:626) (734:734:734)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (216:216:216) (274:274:274)) + (PORT datac (620:620:620) (724:724:724)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (428:428:428)) + (PORT datac (338:338:338) (402:402:402)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (403:403:403)) + (PORT datab (478:478:478) (554:554:554)) + (PORT datac (470:470:470) (552:552:552)) + (PORT datad (368:368:368) (449:449:449)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (224:224:224)) + (PORT datab (206:206:206) (251:251:251)) + (PORT datac (638:638:638) (736:736:736)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (458:458:458)) + (PORT datab (333:333:333) (393:393:393)) + (PORT datac (343:343:343) (401:401:401)) + (PORT datad (438:438:438) (509:509:509)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (626:626:626)) + (PORT datab (335:335:335) (394:394:394)) + (PORT datac (503:503:503) (592:592:592)) + (PORT datad (350:350:350) (413:413:413)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (144:144:144) (183:183:183)) + (PORT datac (416:416:416) (480:480:480)) + (PORT datad (480:480:480) (567:567:567)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (524:524:524)) + (PORT datac (483:483:483) (551:551:551)) + (PORT datad (650:650:650) (754:754:754)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (740:740:740)) + (PORT datac (339:339:339) (387:387:387)) + (PORT datad (440:440:440) (505:505:505)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (736:736:736)) + (PORT datab (332:332:332) (392:392:392)) + (PORT datac (455:455:455) (512:512:512)) + (PORT datad (91:91:91) (110:110:110)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (330:330:330) (390:390:390)) + (PORT datad (271:271:271) (312:312:312)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (703:703:703)) + (PORT datab (141:141:141) (189:189:189)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1120:1120:1120)) + (PORT datab (570:570:570) (686:686:686)) + (PORT datac (765:765:765) (876:876:876)) + (PORT datad (792:792:792) (926:926:926)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (799:799:799)) + (PORT datab (983:983:983) (1124:1124:1124)) + (PORT datac (857:857:857) (1032:1032:1032)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (1065:1065:1065)) + (PORT datab (1139:1139:1139) (1329:1329:1329)) + (PORT datac (620:620:620) (715:715:715)) + (PORT datad (621:621:621) (706:706:706)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (526:526:526)) + (PORT datab (418:418:418) (504:504:504)) + (PORT datac (318:318:318) (366:366:366)) + (PORT datad (589:589:589) (673:673:673)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (839:839:839)) + (PORT datab (964:964:964) (1120:1120:1120)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (355:355:355) (421:421:421)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (948:948:948)) + (PORT datab (1139:1139:1139) (1328:1328:1328)) + (PORT datac (1336:1336:1336) (1569:1569:1569)) + (PORT datad (200:200:200) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (193:193:193) (230:230:230)) + (PORT datac (463:463:463) (537:537:537)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (666:666:666)) + (PORT datab (478:478:478) (556:556:556)) + (PORT datac (476:476:476) (558:558:558)) + (PORT datad (566:566:566) (645:645:645)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (348:348:348)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (339:339:339) (397:397:397)) + (PORT datad (368:368:368) (426:426:426)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (218:218:218)) + (PORT datab (123:123:123) (155:155:155)) + (PORT datac (279:279:279) (318:318:318)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (523:523:523)) + (PORT datab (549:549:549) (651:651:651)) + (PORT datac (1319:1319:1319) (1526:1526:1526)) + (PORT datad (996:996:996) (1164:1164:1164)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (525:525:525)) + (PORT datab (641:641:641) (745:745:745)) + (PORT datac (1319:1319:1319) (1525:1525:1525)) + (PORT datad (995:995:995) (1164:1164:1164)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (527:527:527)) + (PORT datab (636:636:636) (734:734:734)) + (PORT datac (1317:1317:1317) (1523:1523:1523)) + (PORT datad (995:995:995) (1163:1163:1163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (583:583:583)) + (PORT datac (407:407:407) (473:473:473)) + (PORT datad (564:564:564) (642:642:642)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (536:536:536) (619:619:619)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (306:306:306)) + (PORT datab (1153:1153:1153) (1350:1350:1350)) + (PORT datac (628:628:628) (726:726:726)) + (PORT datad (585:585:585) (705:705:705)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (384:384:384)) + (PORT datab (1669:1669:1669) (1931:1931:1931)) + (PORT datac (290:290:290) (331:331:331)) + (PORT datad (752:752:752) (855:855:855)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (627:627:627)) + (PORT datab (328:328:328) (391:391:391)) + (PORT datad (265:265:265) (302:302:302)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (606:606:606)) + (PORT datab (863:863:863) (1012:1012:1012)) + (PORT datac (1304:1304:1304) (1516:1516:1516)) + (PORT datad (985:985:985) (1128:1128:1128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (666:666:666)) + (PORT datab (469:469:469) (555:555:555)) + (PORT datac (475:475:475) (557:557:557)) + (PORT datad (582:582:582) (667:667:667)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (175:175:175)) + (PORT datab (534:534:534) (630:630:630)) + (PORT datac (327:327:327) (378:378:378)) + (PORT datad (456:456:456) (520:520:520)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1121:1121:1121)) + (PORT datab (848:848:848) (1003:1003:1003)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (1393:1393:1393) (1624:1624:1624)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (513:513:513) (602:602:602)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (121:121:121) (152:152:152)) + (PORT datac (428:428:428) (484:484:484)) + (PORT datad (333:333:333) (389:389:389)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (525:525:525)) + (PORT datab (478:478:478) (569:569:569)) + (PORT datac (1319:1319:1319) (1526:1526:1526)) + (PORT datad (996:996:996) (1165:1165:1165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (606:606:606)) + (PORT datab (509:509:509) (590:590:590)) + (PORT datac (1303:1303:1303) (1516:1516:1516)) + (PORT datad (844:844:844) (987:987:987)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (1077:1077:1077)) + (PORT datab (524:524:524) (624:624:624)) + (PORT datac (526:526:526) (621:621:621)) + (PORT datad (913:913:913) (1045:1045:1045)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (469:469:469) (545:545:545)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (112:112:112) (135:135:135)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (825:825:825)) + (PORT datab (231:231:231) (289:289:289)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (701:701:701)) + (PORT datab (433:433:433) (504:504:504)) + (PORT datac (342:342:342) (405:405:405)) + (PORT datad (98:98:98) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (146:146:146)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (650:650:650) (746:746:746)) + (PORT datad (269:269:269) (305:305:305)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (434:434:434) (500:500:500)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (528:528:528)) + (PORT datab (328:328:328) (387:387:387)) + (PORT datac (713:713:713) (832:832:832)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1149:1149:1149)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (292:292:292) (341:341:341)) + (PORT datad (343:343:343) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (470:470:470) (558:558:558)) + (PORT datac (968:968:968) (1123:1123:1123)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1140:1140:1140)) + (PORT datab (793:793:793) (918:918:918)) + (PORT datac (324:324:324) (381:381:381)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (150:150:150)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (467:467:467) (558:558:558)) + (PORT datad (118:118:118) (137:137:137)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (555:555:555) (654:654:654)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (919:919:919)) + (PORT datab (958:958:958) (1104:1104:1104)) + (PORT datac (187:187:187) (220:220:220)) + (PORT datad (650:650:650) (750:750:750)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (153:153:153)) + (PORT datab (360:360:360) (431:431:431)) + (PORT datac (782:782:782) (896:896:896)) + (PORT datad (612:612:612) (697:697:697)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (361:361:361)) + (PORT datab (128:128:128) (160:160:160)) + (PORT datac (675:675:675) (774:774:774)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (353:353:353) (422:422:422)) + (PORT datac (348:348:348) (409:409:409)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (614:614:614)) + (PORT datab (805:805:805) (924:924:924)) + (PORT datac (189:189:189) (222:222:222)) + (PORT datad (651:651:651) (751:751:751)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (166:166:166)) + (PORT datab (706:706:706) (837:837:837)) + (PORT datac (492:492:492) (591:591:591)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (173:173:173)) + (PORT datab (531:531:531) (621:621:621)) + (PORT datac (277:277:277) (322:322:322)) + (PORT datad (512:512:512) (601:601:601)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (639:639:639) (738:738:738)) + (PORT datac (461:461:461) (533:533:533)) + (PORT datad (367:367:367) (430:430:430)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (596:596:596)) + (PORT datab (475:475:475) (559:559:559)) + (PORT datac (222:222:222) (263:263:263)) + (PORT datad (563:563:563) (664:664:664)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (231:231:231)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (120:120:120) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (418:418:418)) + (PORT datab (371:371:371) (445:445:445)) + (PORT datac (543:543:543) (637:637:637)) + (PORT datad (796:796:796) (898:898:898)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1408:1408:1408)) + (PORT datab (806:806:806) (935:935:935)) + (PORT datac (550:550:550) (656:656:656)) + (PORT datad (798:798:798) (901:901:901)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (235:235:235)) + (PORT datab (206:206:206) (244:244:244)) + (PORT datac (645:645:645) (737:737:737)) + (PORT datad (171:171:171) (203:203:203)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (845:845:845)) + (PORT datab (603:603:603) (698:698:698)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (634:634:634) (727:727:727)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (844:844:844)) + (PORT datab (871:871:871) (1031:1031:1031)) + (PORT datac (845:845:845) (996:996:996)) + (PORT datad (631:631:631) (722:722:722)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (577:577:577)) + (PORT datab (735:735:735) (868:868:868)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (684:684:684) (791:791:791)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (702:702:702) (814:814:814)) + (PORT datac (348:348:348) (414:414:414)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (808:808:808)) + (PORT datab (482:482:482) (559:559:559)) + (PORT datac (846:846:846) (998:998:998)) + (PORT datad (690:690:690) (820:820:820)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (108:108:108) (138:138:138)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (PORT datab (879:879:879) (1043:1043:1043)) + (PORT datac (868:868:868) (1031:1031:1031)) + (PORT datad (896:896:896) (1086:1086:1086)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (622:622:622) (737:737:737)) + (PORT datac (476:476:476) (550:550:550)) + (PORT datad (634:634:634) (736:736:736)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (504:504:504)) + (PORT datab (660:660:660) (763:763:763)) + (PORT datac (277:277:277) (316:316:316)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (553:553:553)) + (PORT datab (474:474:474) (552:552:552)) + (PORT datad (825:825:825) (959:959:959)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (213:213:213)) + (PORT datab (687:687:687) (822:822:822)) + (PORT datac (1071:1071:1071) (1233:1233:1233)) + (PORT datad (507:507:507) (594:594:594)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (271:271:271)) + (PORT datab (342:342:342) (411:411:411)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (173:173:173) (204:204:204)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (134:134:134)) + (PORT datab (438:438:438) (524:524:524)) + (PORT datac (194:194:194) (231:231:231)) + (PORT datad (412:412:412) (467:467:467)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (421:421:421)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (166:166:166) (196:196:196)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (444:444:444) (520:520:520)) + (PORT datac (330:330:330) (388:388:388)) + (PORT datad (503:503:503) (594:594:594)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (412:412:412)) + (PORT datab (440:440:440) (516:516:516)) + (PORT datac (793:793:793) (911:911:911)) + (PORT datad (613:613:613) (698:698:698)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (528:528:528) (627:627:627)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (458:458:458)) + (PORT datab (666:666:666) (778:778:778)) + (PORT datac (636:636:636) (753:753:753)) + (PORT datad (603:603:603) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (459:459:459) (532:532:532)) + (PORT datac (618:618:618) (721:721:721)) + (PORT datad (483:483:483) (553:553:553)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (524:524:524)) + (PORT datac (206:206:206) (264:264:264)) + (PORT datad (193:193:193) (241:241:241)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (387:387:387) (468:468:468)) + (PORT datac (361:361:361) (429:429:429)) + (PORT datad (600:600:600) (712:712:712)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (676:676:676)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datac (429:429:429) (491:491:491)) + (PORT datad (449:449:449) (516:516:516)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (239:239:239)) + (PORT datab (304:304:304) (351:351:351)) + (PORT datac (748:748:748) (856:856:856)) + (PORT datad (626:626:626) (738:738:738)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (477:477:477) (563:563:563)) + (PORT datac (1011:1011:1011) (1188:1188:1188)) + (PORT datad (719:719:719) (819:819:819)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1418:1418:1418)) + (PORT datab (1608:1608:1608) (1890:1890:1890)) + (PORT datac (537:537:537) (638:638:638)) + (PORT datad (715:715:715) (814:814:814)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (595:595:595)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (843:843:843)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (478:478:478) (568:568:568)) + (PORT datad (343:343:343) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (669:669:669)) + (PORT datab (140:140:140) (188:188:188)) + (PORT datac (91:91:91) (115:115:115)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (562:562:562)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (473:473:473) (550:550:550)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (543:543:543)) + (PORT datac (466:466:466) (539:539:539)) + (PORT datad (486:486:486) (561:561:561)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (578:578:578)) + (PORT datac (327:327:327) (378:378:378)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (553:553:553)) + (PORT datab (660:660:660) (778:778:778)) + (PORT datac (627:627:627) (714:714:714)) + (PORT datad (442:442:442) (506:506:506)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (623:623:623) (727:727:727)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (428:428:428)) + (PORT datab (372:372:372) (453:453:453)) + (PORT datac (305:305:305) (361:361:361)) + (PORT datad (566:566:566) (645:645:645)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (149:149:149)) + (PORT datac (304:304:304) (352:352:352)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (146:146:146)) + (PORT datab (403:403:403) (491:491:491)) + (PORT datac (595:595:595) (707:707:707)) + (PORT datad (374:374:374) (453:453:453)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (554:554:554)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (175:175:175) (202:202:202)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (487:487:487)) + (PORT datab (746:746:746) (859:859:859)) + (PORT datac (694:694:694) (831:831:831)) + (PORT datad (353:353:353) (427:427:427)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (204:204:204)) + (PORT datab (157:157:157) (202:202:202)) + (PORT datad (133:133:133) (162:162:162)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (252:252:252)) + (PORT datab (199:199:199) (241:241:241)) + (PORT datac (764:764:764) (891:891:891)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (909:909:909)) + (PORT datac (619:619:619) (716:716:716)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (465:465:465) (508:508:508)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (1020:1020:1020) (1168:1168:1168)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (1020:1020:1020) (1168:1168:1168)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (543:543:543)) + (PORT datab (225:225:225) (289:289:289)) + (PORT datad (438:438:438) (507:507:507)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (1146:1146:1146) (1309:1309:1309)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (465:465:465) (547:547:547)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (435:435:435)) + (PORT datab (361:361:361) (424:424:424)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (922:922:922) (1044:1044:1044)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (750:750:750)) + (PORT datab (673:673:673) (782:782:782)) + (PORT datad (459:459:459) (542:542:542)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1146:1146:1146) (1308:1308:1308)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (966:966:966) (1094:1094:1094)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (419:419:419)) + (PORT datab (242:242:242) (292:292:292)) + (PORT datad (636:636:636) (741:741:741)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (803:803:803) (906:906:906)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (803:803:803) (906:906:906)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (606:606:606)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (467:467:467) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (551:551:551)) + (PORT datab (294:294:294) (347:347:347)) + (PORT datac (547:547:547) (642:642:642)) + (PORT datad (190:190:190) (225:225:225)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (663:663:663) (740:740:740)) + (PORT ena (784:784:784) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (870:870:870)) + (PORT datab (765:765:765) (911:911:911)) + (PORT datad (467:467:467) (542:542:542)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1025:1025:1025) (1172:1172:1172)) + (PORT ena (521:521:521) (565:565:565)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (659:659:659) (736:736:736)) + (PORT ena (821:821:821) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (616:616:616)) + (PORT datab (361:361:361) (442:442:442)) + (PORT datad (561:561:561) (658:658:658)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (452:452:452) (529:529:529)) + (PORT datac (87:87:87) (109:109:109)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (355:355:355)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (345:345:345) (413:413:413)) + (PORT datad (463:463:463) (551:551:551)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (765:765:765)) + (PORT datab (728:728:728) (875:875:875)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (170:170:170) (206:206:206)) + (PORT datac (601:601:601) (694:694:694)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (449:449:449)) + (PORT datab (391:391:391) (478:478:478)) + (PORT datac (441:441:441) (503:503:503)) + (PORT datad (331:331:331) (384:384:384)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (655:655:655) (758:758:758)) + (PORT datac (359:359:359) (422:422:422)) + (PORT datad (191:191:191) (227:227:227)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datac (653:653:653) (756:756:756)) + (PORT datad (327:327:327) (379:379:379)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (902:902:902) (889:889:889)) + (PORT ena (917:917:917) (1011:1011:1011)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1076:1076:1076)) + (PORT datab (358:358:358) (422:422:422)) + (PORT datac (600:600:600) (682:682:682)) + (PORT datad (351:351:351) (422:422:422)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (421:421:421)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (703:703:703)) + (PORT datab (354:354:354) (417:417:417)) + (PORT datac (468:468:468) (556:556:556)) + (PORT datad (919:919:919) (1050:1050:1050)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (414:414:414)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (487:487:487) (583:583:583)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (362:362:362) (401:401:401)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (768:768:768)) + (PORT datab (724:724:724) (871:871:871)) + (PORT datad (596:596:596) (679:679:679)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (224:224:224)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datac (606:606:606) (700:700:700)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (411:411:411)) + (PORT datab (652:652:652) (755:755:755)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (194:194:194) (230:230:230)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (493:493:493) (549:549:549)) + (PORT ena (521:521:521) (565:565:565)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (492:492:492) (548:548:548)) + (PORT ena (418:418:418) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (130:130:130) (164:164:164)) + (PORT datad (283:283:283) (325:325:325)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (801:801:801) (896:896:896)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (801:801:801) (896:896:896)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (603:603:603)) + (PORT datab (482:482:482) (564:564:564)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (934:934:934) (1032:1032:1032)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (464:464:464) (507:507:507)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (180:180:180)) + (PORT datab (239:239:239) (289:289:289)) + (PORT datad (631:631:631) (735:735:735)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (506:506:506) (565:565:565)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (504:504:504) (563:563:563)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (440:440:440)) + (PORT datab (356:356:356) (418:418:418)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (523:523:523) (584:584:584)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (571:571:571)) + (PORT datab (673:673:673) (783:783:783)) + (PORT datad (466:466:466) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (391:391:391)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (292:292:292) (336:336:336)) + (PORT datad (317:317:317) (368:368:368)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (527:527:527) (589:589:589)) + (PORT ena (773:773:773) (840:840:840)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (520:520:520)) + (PORT datab (634:634:634) (746:746:746)) + (PORT datad (723:723:723) (824:824:824)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (767:767:767) (872:872:872)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (767:767:767) (871:871:871)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (547:547:547)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (440:440:440) (510:510:510)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (711:711:711)) + (PORT datab (346:346:346) (414:414:414)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (317:317:317) (359:359:359)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (453:453:453)) + (PORT datab (349:349:349) (413:413:413)) + (PORT datac (345:345:345) (404:404:404)) + (PORT datad (340:340:340) (398:398:398)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (445:445:445)) + (PORT datab (416:416:416) (478:478:478)) + (PORT datac (509:509:509) (599:599:599)) + (PORT datad (846:846:846) (980:980:980)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (600:600:600)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (198:198:198) (235:235:235)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (216:216:216)) + (PORT datab (193:193:193) (239:239:239)) + (PORT datac (744:744:744) (855:855:855)) + (PORT datad (840:840:840) (974:974:974)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (399:399:399)) + (PORT datab (755:755:755) (867:867:867)) + (PORT datac (300:300:300) (351:351:351)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (413:413:413)) + (PORT datab (653:653:653) (760:760:760)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (169:169:169) (201:201:201)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (439:439:439) (515:515:515)) + (PORT datac (326:326:326) (385:385:385)) + (PORT datad (509:509:509) (601:601:601)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (613:613:613) (735:735:735)) + (PORT datac (470:470:470) (548:548:548)) + (PORT datad (614:614:614) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (577:577:577)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (560:560:560)) + (PORT datab (502:502:502) (583:583:583)) + (PORT datac (451:451:451) (518:518:518)) + (PORT datad (456:456:456) (526:526:526)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (536:536:536)) + (PORT datab (202:202:202) (241:241:241)) + (PORT datac (316:316:316) (372:372:372)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (557:557:557)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (917:917:917) (1035:1035:1035)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (765:765:765)) + (PORT datab (659:659:659) (777:777:777)) + (PORT datac (363:363:363) (437:437:437)) + (PORT datad (601:601:601) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (554:554:554)) + (PORT datab (459:459:459) (533:533:533)) + (PORT datac (617:617:617) (720:720:720)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (925:925:925)) + (PORT datab (947:947:947) (1098:1098:1098)) + (PORT datac (471:471:471) (549:549:549)) + (PORT datad (199:199:199) (249:249:249)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (195:195:195)) + (PORT datad (130:130:130) (158:158:158)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (194:194:194)) + (PORT datab (308:308:308) (357:357:357)) + (PORT datac (694:694:694) (785:785:785)) + (PORT datad (107:107:107) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (584:584:584)) + (PORT datac (197:197:197) (248:248:248)) + (PORT datad (446:446:446) (528:528:528)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (768:768:768)) + (PORT datab (487:487:487) (563:563:563)) + (PORT datac (446:446:446) (506:506:506)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (360:360:360) (398:398:398)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (1007:1007:1007)) + (PORT datab (728:728:728) (875:875:875)) + (PORT datad (627:627:627) (734:734:734)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (749:749:749)) + (PORT datab (318:318:318) (388:388:388)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (480:480:480) (564:564:564)) + (PORT datad (282:282:282) (320:320:320)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (884:884:884)) + (PORT ena (1063:1063:1063) (1174:1174:1174)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (395:395:395)) + (PORT datab (490:490:490) (582:582:582)) + (PORT datac (337:337:337) (396:396:396)) + (PORT datad (559:559:559) (633:633:633)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (522:522:522)) + (PORT datab (571:571:571) (655:655:655)) + (PORT datac (132:132:132) (180:180:180)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (211:211:211)) + (PORT datab (207:207:207) (252:252:252)) + (PORT datac (637:637:637) (735:735:735)) + (PORT datad (297:297:297) (339:339:339)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (939:939:939) (1047:1047:1047)) + (PORT ena (784:784:784) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (875:875:875)) + (PORT datab (761:761:761) (906:906:906)) + (PORT datad (471:471:471) (546:546:546)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (662:662:662) (733:733:733)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (666:666:666) (737:737:737)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (551:551:551)) + (PORT datab (133:133:133) (182:182:182)) + (PORT datad (442:442:442) (511:511:511)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (481:481:481) (523:523:523)) + (PORT ena (521:521:521) (565:565:565)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (940:940:940) (1048:1048:1048)) + (PORT ena (821:821:821) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (614:614:614)) + (PORT datab (361:361:361) (442:442:442)) + (PORT datad (562:562:562) (659:659:659)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1024:1024:1024) (1150:1150:1150)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1023:1023:1023) (1149:1149:1149)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (603:603:603)) + (PORT datab (483:483:483) (565:565:565)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (102:102:102) (120:120:120)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (934:934:934) (1032:1032:1032)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (471:471:471) (513:513:513)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (241:241:241) (291:291:291)) + (PORT datad (634:634:634) (738:738:738)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (483:483:483) (528:528:528)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (836:836:836) (963:963:963)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (436:436:436)) + (PORT datab (359:359:359) (422:422:422)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (800:800:800) (890:890:890)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (557:557:557)) + (PORT datab (680:680:680) (791:791:791)) + (PORT datad (487:487:487) (561:561:561)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (495:495:495)) + (PORT datab (346:346:346) (406:406:406)) + (PORT datac (460:460:460) (534:534:534)) + (PORT datad (164:164:164) (193:193:193)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (195:195:195) (236:236:236)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (417:417:417)) + (PORT datab (357:357:357) (422:422:422)) + (PORT datac (366:366:366) (437:437:437)) + (PORT datad (323:323:323) (374:374:374)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (449:449:449)) + (PORT datab (507:507:507) (595:595:595)) + (PORT datac (500:500:500) (589:589:589)) + (PORT datad (313:313:313) (364:364:364)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (143:143:143) (180:180:180)) + (PORT datac (600:600:600) (690:690:690)) + (PORT datad (485:485:485) (574:574:574)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1075:1075:1075)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (489:489:489) (563:563:563)) (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (363:363:363)) + (PORT datab (365:365:365) (430:430:430)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (461:461:461) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (928:928:928)) + (PORT datab (339:339:339) (405:405:405)) + (PORT datac (429:429:429) (500:500:500)) + (PORT datad (457:457:457) (519:519:519)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (521:521:521) (618:618:618)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (PORT datac (129:129:129) (170:170:170)) + (PORT datad (128:128:128) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (280:280:280)) + (PORT datab (141:141:141) (189:189:189)) + (PORT datac (101:101:101) (123:123:123)) + (PORT datad (128:128:128) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (368:368:368)) + (PORT datab (392:392:392) (472:472:472)) + (PORT datac (633:633:633) (731:731:731)) + (PORT datad (283:283:283) (327:327:327)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (489:489:489)) + (PORT datab (444:444:444) (517:517:517)) + (PORT datac (346:346:346) (407:407:407)) + (PORT datad (445:445:445) (534:534:534)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (372:372:372) (448:448:448)) + (PORT datad (625:625:625) (720:720:720)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (589:589:589)) + (PORT datab (477:477:477) (556:556:556)) + (PORT datac (603:603:603) (689:689:689)) + (PORT datad (618:618:618) (714:714:714)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (353:353:353)) + (PORT datab (624:624:624) (731:731:731)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (298:298:298) (337:337:337)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (227:227:227)) + (PORT datab (129:129:129) (162:162:162)) + (PORT datac (358:358:358) (431:431:431)) + (PORT datad (304:304:304) (344:344:344)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1077:1077:1077)) + (PORT datab (225:225:225) (269:269:269)) + (PORT datad (423:423:423) (479:479:479)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (617:617:617) (674:674:674)) + (PORT ena (818:818:818) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (514:514:514) (601:601:601)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (363:363:363) (386:386:386)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (115:115:115) (132:132:132)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (743:743:743) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (262:262:262)) + (PORT datab (440:440:440) (508:508:508)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (345:345:345) (388:388:388)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (837:837:837) (927:927:927)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (436:436:436)) + (PORT datab (202:202:202) (261:261:261)) + (PORT datad (370:370:370) (430:430:430)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (210:210:210)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (302:302:302) (352:352:352)) + (PORT datad (421:421:421) (477:477:477)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (698:698:698) (777:777:777)) + (PORT ena (810:810:810) (884:884:884)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (702:702:702) (781:781:781)) + (PORT ena (792:792:792) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (610:610:610)) + (PORT datab (531:531:531) (615:615:615)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (354:354:354) (409:409:409)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (566:566:566)) + (PORT datab (512:512:512) (602:602:602)) + (PORT datac (454:454:454) (518:518:518)) + (PORT datad (316:316:316) (365:365:365)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT asdata (346:346:346) (374:374:374)) + (PORT ena (640:640:640) (692:692:692)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (804:804:804)) + (PORT datab (506:506:506) (582:582:582)) + (PORT datad (352:352:352) (412:412:412)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (132:132:132) (181:181:181)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (356:356:356) (414:414:414)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (432:432:432)) + (PORT datab (332:332:332) (381:381:381)) + (PORT datac (123:123:123) (152:152:152)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datac (658:658:658) (762:762:762)) + (PORT datad (277:277:277) (319:319:319)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (902:902:902) (889:889:889)) + (PORT ena (917:917:917) (1011:1011:1011)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (206:206:206)) + (PORT datab (451:451:451) (527:527:527)) + (PORT datac (617:617:617) (717:717:717)) + (PORT datad (759:759:759) (862:862:862)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (670:670:670) (747:747:747)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (672:672:672) (749:749:749)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (631:631:631)) + (PORT datab (400:400:400) (467:467:467)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (430:430:430) (489:489:489)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (743:743:743) (822:822:822)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (261:261:261)) + (PORT datab (221:221:221) (266:266:266)) + (PORT datad (204:204:204) (241:241:241)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (822:822:822) (918:918:918)) + (PORT ena (660:660:660) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT asdata (527:527:527) (589:589:589)) + (PORT ena (810:810:810) (883:883:883)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (582:582:582)) + (PORT datab (368:368:368) (431:431:431)) + (PORT datad (311:311:311) (373:373:373)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (497:497:497) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (1078:1078:1078)) + (PORT datab (334:334:334) (398:398:398)) + (PORT datac (461:461:461) (543:543:543)) + (PORT datad (567:567:567) (649:649:649)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT asdata (653:653:653) (720:720:720)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (259:259:259)) + (PORT datab (385:385:385) (460:460:460)) + (PORT datad (352:352:352) (412:412:412)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (409:409:409)) + (PORT datab (317:317:317) (370:370:370)) + (PORT datac (310:310:310) (350:350:350)) + (PORT datad (326:326:326) (381:381:381)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (671:671:671) (753:753:753)) + (PORT ena (810:810:810) (884:884:884)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (672:672:672) (754:754:754)) + (PORT ena (792:792:792) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (612:612:612)) + (PORT datab (536:536:536) (620:620:620)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT asdata (525:525:525) (586:586:586)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (820:820:820) (915:915:915)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (439:439:439)) + (PORT datab (216:216:216) (273:273:273)) + (PORT datad (373:373:373) (434:434:434)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (210:210:210)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (302:302:302) (346:346:346)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (563:563:563)) + (PORT datab (500:500:500) (581:581:581)) + (PORT datac (492:492:492) (577:577:577)) + (PORT datad (478:478:478) (555:555:555)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT asdata (279:279:279) (297:297:297)) + (PORT ena (610:610:610) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (765:765:765)) + (PORT datab (510:510:510) (596:596:596)) + (PORT datad (295:295:295) (341:341:341)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (616:616:616) (664:664:664)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (385:385:385)) + (PORT datac (160:160:160) (189:189:189)) + (PORT datad (186:186:186) (234:234:234)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (888:888:888)) + (PORT datab (331:331:331) (402:402:402)) + (PORT datac (615:615:615) (715:715:715)) + (PORT datad (437:437:437) (503:503:503)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (272:272:272)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (338:338:338) (396:396:396)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (163:163:163)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (348:348:348) (404:404:404)) + (PORT datad (332:332:332) (373:373:373)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (670:670:670) (781:781:781)) + (PORT datad (344:344:344) (397:397:397)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (902:902:902) (889:889:889)) + (PORT ena (917:917:917) (1011:1011:1011)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (783:783:783)) + (PORT datab (670:670:670) (784:784:784)) + (PORT datac (306:306:306) (367:367:367)) + (PORT datad (332:332:332) (389:389:389)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (422:422:422)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (357:357:357) (430:430:430)) + (PORT datad (275:275:275) (318:318:318)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (616:616:616) (664:664:664)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (659:659:659) (730:730:730)) + (PORT ena (808:808:808) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (658:658:658) (728:728:728)) + (PORT ena (794:794:794) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (634:634:634)) + (PORT datab (396:396:396) (462:462:462)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (667:667:667) (735:735:735)) + (PORT ena (810:810:810) (884:884:884)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (667:667:667) (735:735:735)) + (PORT ena (792:792:792) (851:851:851)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (612:612:612)) + (PORT datab (537:537:537) (621:621:621)) + (PORT datad (115:115:115) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (883:883:883)) + (PORT datab (347:347:347) (407:407:407)) + (PORT datac (115:115:115) (156:156:156)) + (PORT datad (424:424:424) (478:478:478)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (677:677:677) (753:753:753)) + (PORT ena (660:660:660) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT asdata (657:657:657) (721:721:721)) + (PORT ena (810:810:810) (883:883:883)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (583:583:583)) + (PORT datab (369:369:369) (432:432:432)) + (PORT datad (197:197:197) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (608:608:608) (676:676:676)) + (PORT ena (613:613:613) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (730:730:730) (808:808:808)) + (PORT ena (776:776:776) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (PORT datab (223:223:223) (267:267:267)) + (PORT datad (205:205:205) (242:242:242)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (732:732:732) (810:810:810)) + (PORT ena (818:818:818) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datad (510:510:510) (597:597:597)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (903:903:903)) + (PORT asdata (658:658:658) (722:722:722)) + (PORT ena (649:649:649) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (904:904:904)) + (PORT asdata (677:677:677) (753:753:753)) + (PORT ena (631:631:631) (670:670:670)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (436:436:436)) + (PORT datab (204:204:204) (264:264:264)) + (PORT datad (371:371:371) (431:431:431)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (491:491:491) (576:576:576)) + (PORT datac (317:317:317) (372:372:372)) + (PORT datad (475:475:475) (547:547:547)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (374:374:374)) + (PORT datac (320:320:320) (374:374:374)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (357:357:357)) + (PORT datab (454:454:454) (527:527:527)) + (PORT datac (586:586:586) (673:673:673)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT asdata (450:450:450) (491:491:491)) + (PORT ena (610:610:610) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (759:759:759)) + (PORT datab (512:512:512) (598:598:598)) + (PORT datad (298:298:298) (345:345:345)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (309:309:309) (360:360:360)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (163:163:163)) + (PORT datab (577:577:577) (656:656:656)) + (PORT datac (348:348:348) (404:404:404)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT datac (728:728:728) (830:830:830)) + (PORT datad (1021:1021:1021) (1158:1158:1158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (369:369:369) (402:402:402)) + (PORT clrn (900:900:900) (887:887:887)) + (PORT ena (913:913:913) (998:998:998)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (395:395:395)) + (PORT datab (490:490:490) (582:582:582)) + (PORT datac (337:337:337) (396:396:396)) + (PORT datad (559:559:559) (633:633:633)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (654:654:654) (757:757:757)) + (PORT datac (185:185:185) (220:220:220)) + (PORT datad (193:193:193) (228:228:228)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (647:647:647) (716:716:716)) + (PORT ena (773:773:773) (840:840:840)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (662:662:662) (734:734:734)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (660:660:660) (732:732:732)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (545:545:545)) + (PORT datab (130:130:130) (177:177:177)) + (PORT datad (440:440:440) (509:509:509)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (629:629:629) (702:702:702)) + (PORT ena (521:521:521) (565:565:565)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (630:630:630) (702:702:702)) + (PORT ena (418:418:418) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (764:764:764)) + (PORT datab (306:306:306) (357:357:357)) + (PORT datad (620:620:620) (723:723:723)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (531:531:531)) + (PORT datab (130:130:130) (163:163:163)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (515:515:515) (564:564:564)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (518:518:518) (567:567:567)) + (PORT ena (934:934:934) (1032:1032:1032)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (184:184:184)) + (PORT datab (243:243:243) (293:293:293)) + (PORT datad (639:639:639) (744:744:744)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (530:530:530) (591:591:591)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (528:528:528) (589:589:589)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (602:602:602)) + (PORT datab (480:480:480) (562:562:562)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (930:930:930) (1034:1034:1034)) + (PORT ena (648:648:648) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (659:659:659) (760:760:760)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (443:443:443)) + (PORT datab (353:353:353) (415:415:415)) + (PORT datad (216:216:216) (271:271:271)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (648:648:648) (718:718:718)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (568:568:568)) + (PORT datab (675:675:675) (785:785:785)) + (PORT datad (466:466:466) (535:535:535)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (234:234:234)) + (PORT datab (342:342:342) (410:410:410)) + (PORT datac (182:182:182) (216:216:216)) + (PORT datad (331:331:331) (383:383:383)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (364:364:364) (446:446:446)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (436:436:436)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datac (193:193:193) (231:231:231)) + (PORT datad (328:328:328) (385:385:385)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (560:560:560)) + (PORT datab (340:340:340) (403:403:403)) + (PORT datac (116:116:116) (137:137:137)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (767:767:767)) + (PORT datab (143:143:143) (181:181:181)) + (PORT datac (297:297:297) (348:348:348)) + (PORT datad (482:482:482) (570:570:570)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (240:240:240)) + (PORT datac (766:766:766) (893:893:893)) + (PORT datad (322:322:322) (369:369:369)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (759:759:759) (874:874:874)) + (PORT datac (185:185:185) (225:225:225)) + (PORT datad (842:842:842) (976:976:976)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (394:394:394)) + (PORT datac (355:355:355) (415:415:415)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (599:599:599)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (362:362:362) (420:420:420)) + (PORT datad (130:130:130) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (453:453:453)) + (PORT datab (638:638:638) (745:745:745)) + (PORT datac (1546:1546:1546) (1783:1783:1783)) + (PORT datad (437:437:437) (501:501:501)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (982:982:982)) + (PORT datab (521:521:521) (619:619:619)) + (PORT datac (1544:1544:1544) (1780:1780:1780)) + (PORT datad (648:648:648) (752:752:752)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~3) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (812:812:812) (956:956:956)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (201:201:201) (244:244:244)) + (PORT datac (764:764:764) (891:891:891)) + (PORT datad (398:398:398) (455:455:455)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (198:198:198) (240:240:240)) + (PORT datac (743:743:743) (854:854:854)) + (PORT datad (842:842:842) (976:976:976)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (526:526:526)) + (PORT datab (486:486:486) (572:572:572)) + (PORT datac (207:207:207) (265:265:265)) + (PORT datad (193:193:193) (241:241:241)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (554:554:554)) + (PORT datac (322:322:322) (373:373:373)) + (PORT datad (185:185:185) (217:217:217)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (561:561:561)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (310:310:310) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (498:498:498) (548:548:548)) + (PORT ena (917:917:917) (1035:1035:1035)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (198:198:198)) + (PORT datab (152:152:152) (195:195:195)) + (PORT datac (698:698:698) (789:789:789)) + (PORT datad (130:130:130) (158:158:158)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (582:582:582)) + (PORT datab (951:951:951) (1102:1102:1102)) + (PORT datac (758:758:758) (901:901:901)) + (PORT datad (194:194:194) (242:242:242)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (585:585:585)) + (PORT datab (319:319:319) (383:383:383)) + (PORT datac (451:451:451) (541:541:541)) + (PORT datad (428:428:428) (488:488:488)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (399:399:399)) + (PORT datac (350:350:350) (409:409:409)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (666:666:666)) + (PORT datab (496:496:496) (575:575:575)) + (PORT datac (642:642:642) (759:759:759)) + (PORT datad (440:440:440) (503:503:503)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datac (623:623:623) (727:727:727)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (287:287:287)) + (PORT datab (942:942:942) (1092:1092:1092)) + (PORT datac (361:361:361) (429:429:429)) + (PORT datad (855:855:855) (1016:1016:1016)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (191:191:191) (236:236:236)) + (PORT datac (763:763:763) (890:890:890)) + (PORT datad (165:165:165) (194:194:194)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (782:782:782)) + (PORT datab (612:612:612) (711:711:711)) + (PORT datac (175:175:175) (208:208:208)) + (PORT datad (324:324:324) (376:376:376)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (203:203:203)) + (PORT datab (157:157:157) (201:201:201)) + (PORT datad (133:133:133) (162:162:162)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (389:389:389)) + (PORT datab (173:173:173) (212:212:212)) + (PORT datac (729:729:729) (834:834:834)) + (PORT datad (449:449:449) (515:515:515)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (408:408:408)) + (PORT datab (512:512:512) (600:600:600)) + (PORT datac (319:319:319) (369:369:369)) + (PORT datad (339:339:339) (399:399:399)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (265:265:265)) + (PORT datab (515:515:515) (622:622:622)) + (PORT datac (503:503:503) (593:593:593)) + (PORT datad (353:353:353) (416:416:416)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (606:606:606)) + (PORT datab (144:144:144) (180:180:180)) + (PORT datac (438:438:438) (498:498:498)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (753:753:753)) + (PORT datac (634:634:634) (745:745:745)) + (PORT datad (487:487:487) (561:561:561)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (549:549:549)) + (PORT datab (487:487:487) (563:563:563)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (916:916:916) (1050:1050:1050)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (373:373:373) (440:440:440)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (460:460:460) (527:527:527)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (561:561:561)) + (PORT datab (350:350:350) (407:407:407)) + (PORT datac (638:638:638) (754:754:754)) + (PORT datad (444:444:444) (508:508:508)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (622:622:622) (726:726:726)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (516:516:516)) + (PORT datab (216:216:216) (272:272:272)) + (PORT datac (191:191:191) (242:242:242)) + (PORT datad (468:468:468) (544:544:544)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (856:856:856)) + (PORT datab (393:393:393) (471:471:471)) + (PORT datac (353:353:353) (424:424:424)) + (PORT datad (460:460:460) (529:529:529)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (414:414:414)) + (PORT datac (93:93:93) (118:118:118)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (716:716:716)) + (PORT datab (389:389:389) (467:467:467)) + (PORT datac (355:355:355) (427:427:427)) + (PORT datad (334:334:334) (393:393:393)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (450:450:450) (526:526:526)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT datac (316:316:316) (366:366:366)) + (PORT datad (218:218:218) (267:267:267)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (215:215:215)) + (PORT datab (552:552:552) (651:651:651)) + (PORT datad (354:354:354) (410:410:410)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (619:619:619)) + (PORT datab (323:323:323) (368:368:368)) + (PORT datac (582:582:582) (657:657:657)) + (PORT datad (282:282:282) (326:326:326)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (375:375:375) (451:451:451)) + (PORT datad (615:615:615) (730:730:730)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (716:716:716)) + (PORT datab (480:480:480) (559:559:559)) + (PORT datac (468:468:468) (558:558:558)) + (PORT datad (617:617:617) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (224:224:224)) + (PORT datab (377:377:377) (452:452:452)) + (PORT datac (335:335:335) (388:388:388)) + (PORT datad (175:175:175) (206:206:206)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (396:396:396)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (275:275:275) (316:316:316)) + (PORT datad (166:166:166) (196:196:196)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (667:667:667)) + (PORT datab (147:147:147) (198:198:198)) + (PORT datac (694:694:694) (801:801:801)) + (PORT datad (311:311:311) (358:358:358)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (464:464:464)) + (PORT datab (342:342:342) (402:402:402)) + (PORT datac (1234:1234:1234) (1417:1417:1417)) + (PORT datad (336:336:336) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (947:947:947)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (463:463:463) (526:526:526)) + (PORT datad (566:566:566) (641:641:641)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (548:548:548)) + (PORT datab (629:629:629) (726:726:726)) + (PORT datac (1238:1238:1238) (1422:1422:1422)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (463:463:463)) + (PORT datab (354:354:354) (420:420:420)) + (PORT datac (328:328:328) (381:381:381)) + (PORT datad (814:814:814) (917:917:917)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1226:1226:1226)) + (PORT datab (1093:1093:1093) (1284:1284:1284)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (304:304:304)) + (PORT datac (611:611:611) (714:714:714)) + (PORT datad (750:750:750) (894:894:894)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1273:1273:1273) (1401:1401:1401)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (908:908:908) (913:913:913)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (202:202:202)) + (PORT datab (331:331:331) (402:402:402)) + (PORT datac (356:356:356) (435:435:435)) + (PORT datad (197:197:197) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (262:262:262)) + (PORT datab (334:334:334) (394:394:394)) + (PORT datac (302:302:302) (359:359:359)) + (PORT datad (215:215:215) (264:264:264)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (392:392:392)) + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (133:133:133) (181:181:181)) + (PORT datad (423:423:423) (496:496:496)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (474:474:474)) + (PORT datab (384:384:384) (465:465:465)) + (PORT datac (365:365:365) (439:439:439)) + (PORT datad (354:354:354) (426:426:426)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (PORT datab (468:468:468) (541:541:541)) + (PORT datac (597:597:597) (674:674:674)) + (PORT datad (324:324:324) (378:378:378)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (859:859:859)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (489:489:489) (568:568:568)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (548:548:548)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (217:217:217) (269:269:269)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (628:628:628) (724:724:724)) + (PORT datac (1241:1241:1241) (1425:1425:1425)) + (PORT datad (217:217:217) (268:268:268)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (187:187:187) (225:225:225)) + (PORT datac (320:320:320) (371:371:371)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (769:769:769) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (169:169:169) (208:208:208)) + (PORT datad (440:440:440) (523:523:523)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (548:548:548)) + (PORT datab (629:629:629) (725:725:725)) + (PORT datac (326:326:326) (379:379:379)) + (PORT datad (364:364:364) (434:434:434)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (941:941:941)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (1241:1241:1241) (1425:1425:1425)) + (PORT datad (338:338:338) (399:399:399)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (306:306:306) (356:356:356)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (483:483:483) (586:586:586)) + (PORT datac (293:293:293) (334:334:334)) + (PORT datad (562:562:562) (642:642:642)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (631:631:631)) + (PORT datab (131:131:131) (166:166:166)) + (PORT datac (777:777:777) (897:897:897)) + (PORT datad (553:553:553) (659:659:659)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT datab (836:836:836) (986:986:986)) + (PORT datac (766:766:766) (919:919:919)) + (PORT datad (668:668:668) (789:789:789)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (656:656:656)) + (PORT datab (449:449:449) (521:521:521)) + (PORT datac (579:579:579) (662:662:662)) + (PORT datad (462:462:462) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (489:489:489) (567:567:567)) + (PORT datad (309:309:309) (355:355:355)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (147:147:147)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (114:114:114) (133:133:133)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_3) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (278:278:278)) + (PORT datab (176:176:176) (214:214:214)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (718:718:718)) + (PORT datab (468:468:468) (542:542:542)) + (PORT datac (1006:1006:1006) (1153:1153:1153)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (840:840:840)) + (PORT datab (445:445:445) (525:525:525)) + (PORT datac (567:567:567) (668:668:668)) + (PORT datad (597:597:597) (685:685:685)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (654:654:654)) + (PORT datab (496:496:496) (607:607:607)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (191:191:191) (228:228:228)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (1053:1053:1053)) + (PORT datab (149:149:149) (199:199:199)) + (PORT datac (95:95:95) (118:118:118)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1382:1382:1382)) + (PORT datab (520:520:520) (620:620:620)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1275:1275:1275) (1486:1486:1486)) + (PORT datab (422:422:422) (518:518:518)) + (PORT datac (974:974:974) (1117:1117:1117)) + (PORT datad (1009:1009:1009) (1175:1175:1175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (582:582:582)) + (PORT datab (617:617:617) (734:734:734)) + (PORT datac (682:682:682) (784:784:784)) + (PORT datad (171:171:171) (195:195:195)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (756:756:756)) + (PORT datab (632:632:632) (724:724:724)) + (PORT datad (341:341:341) (400:400:400)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (536:536:536) (629:629:629)) + (PORT datac (593:593:593) (674:674:674)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (173:173:173)) + (PORT datab (774:774:774) (907:907:907)) + (PORT datac (840:840:840) (969:969:969)) + (PORT datad (603:603:603) (700:700:700)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (645:645:645) (751:751:751)) + (PORT datac (618:618:618) (720:720:720)) + (PORT datad (576:576:576) (657:657:657)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~23) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (521:521:521)) + (PORT datab (542:542:542) (658:658:658)) + (PORT datac (185:185:185) (225:225:225)) + (PORT datad (201:201:201) (236:236:236)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (423:423:423)) + (PORT datab (473:473:473) (551:551:551)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (516:516:516) (602:602:602)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~21) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (527:527:527) (617:617:617)) + (PORT datac (309:309:309) (352:352:352)) + (PORT datad (324:324:324) (379:379:379)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (730:730:730)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (472:472:472) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (526:526:526) (605:605:605)) + (PORT datac (184:184:184) (223:223:223)) + (PORT datad (355:355:355) (418:418:418)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (370:370:370) (405:405:405)) + (PORT ena (894:894:894) (970:970:970)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (768:768:768)) + (PORT datab (219:219:219) (261:261:261)) + (PORT datad (705:705:705) (844:844:844)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (724:724:724)) + (PORT datac (119:119:119) (160:160:160)) + (PORT datad (166:166:166) (195:195:195)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (132:132:132) (175:175:175)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (653:653:653) (756:756:756)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (193:193:193) (229:229:229)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (481:481:481) (565:565:565)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (884:884:884)) + (PORT ena (1063:1063:1063) (1174:1174:1174)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (517:517:517)) + (PORT datab (573:573:573) (656:656:656)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (469:469:469)) + (PORT datab (782:782:782) (896:896:896)) + (PORT datac (342:342:342) (403:403:403)) + (PORT datad (815:815:815) (918:918:918)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (409:409:409)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (474:474:474)) + (PORT datad (324:324:324) (377:377:377)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (512:512:512) (568:568:568)) + (PORT ena (1056:1056:1056) (1165:1165:1165)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (852:852:852)) + (PORT datab (377:377:377) (449:449:449)) + (PORT datad (739:739:739) (850:850:850)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (886:886:886) (964:964:964)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (231:231:231)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (608:608:608) (701:701:701)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (343:343:343)) + (PORT datab (656:656:656) (759:759:759)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (190:190:190) (225:225:225)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (631:631:631) (700:700:700)) + (PORT ena (418:418:418) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (722:722:722)) + (PORT datab (354:354:354) (418:418:418)) + (PORT datad (187:187:187) (216:216:216)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (465:465:465) (508:508:508)) + (PORT ena (521:521:521) (565:565:565)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (463:463:463) (507:507:507)) + (PORT ena (418:418:418) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (131:131:131) (165:165:165)) + (PORT datad (282:282:282) (324:324:324)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (656:656:656) (766:766:766)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (592:592:592) (632:632:632)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT asdata (673:673:673) (758:758:758)) + (PORT ena (726:726:726) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (539:539:539)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (437:437:437) (506:506:506)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (934:934:934) (1032:1032:1032)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (461:461:461) (508:508:508)) + (PORT ena (493:493:493) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (241:241:241) (291:291:291)) + (PORT datad (635:635:635) (739:739:739)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (960:960:960) (1076:1076:1076)) + (PORT ena (740:740:740) (810:810:810)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (958:958:958) (1072:1072:1072)) + (PORT ena (760:760:760) (827:827:827)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (606:606:606)) + (PORT datab (488:488:488) (571:571:571)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (1125:1125:1125) (1270:1270:1270)) + (PORT ena (735:735:735) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (562:562:562)) + (PORT datab (678:678:678) (788:788:788)) + (PORT datad (294:294:294) (338:338:338)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (351:351:351) (382:382:382)) + (PORT ena (433:433:433) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (348:348:348) (378:378:378)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (458:458:458) (532:532:532)) + (PORT datac (417:417:417) (478:478:478)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (408:408:408)) + (PORT datab (282:282:282) (323:323:323)) + (PORT datac (596:596:596) (704:704:704)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (388:388:388)) + (PORT datab (357:357:357) (422:422:422)) + (PORT datac (365:365:365) (436:436:436)) + (PORT datad (170:170:170) (202:202:202)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (623:623:623)) + (PORT datab (502:502:502) (590:590:590)) + (PORT datac (311:311:311) (368:368:368)) + (PORT datad (351:351:351) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (706:706:706)) + (PORT datab (144:144:144) (181:181:181)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (488:488:488) (578:578:578)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (238:238:238)) + (PORT datab (191:191:191) (237:237:237)) + (PORT datac (765:765:765) (892:892:892)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (262:262:262)) + (PORT datab (757:757:757) (872:872:872)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (843:843:843) (977:977:977)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (283:283:283)) + (PORT datab (951:951:951) (1102:1102:1102)) + (PORT datac (760:760:760) (904:904:904)) + (PORT datad (613:613:613) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (583:583:583)) + (PORT datab (330:330:330) (385:385:385)) + (PORT datac (733:733:733) (839:839:839)) + (PORT datad (472:472:472) (545:545:545)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (552:552:552)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (495:495:495) (581:581:581)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (423:423:423)) + (PORT datab (342:342:342) (405:405:405)) + (PORT datac (328:328:328) (378:378:378)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (883:883:883)) + (PORT datab (660:660:660) (779:779:779)) + (PORT datac (466:466:466) (530:530:530)) + (PORT datad (441:441:441) (505:505:505)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datac (615:615:615) (717:717:717)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (276:276:276)) + (PORT datab (486:486:486) (572:572:572)) + (PORT datac (423:423:423) (502:502:502)) + (PORT datad (198:198:198) (248:248:248)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (615:615:615) (736:736:736)) + (PORT datac (470:470:470) (547:547:547)) + (PORT datad (617:617:617) (716:716:716)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (395:395:395)) + (PORT datab (203:203:203) (242:242:242)) + (PORT datac (452:452:452) (529:529:529)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (535:535:535)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (113:113:113) (140:140:140)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (158:158:158)) + (PORT datab (350:350:350) (414:414:414)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (924:924:924)) + (PORT datab (216:216:216) (272:272:272)) + (PORT datac (932:932:932) (1081:1081:1081)) + (PORT datad (466:466:466) (551:551:551)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (197:197:197)) + (PORT datab (144:144:144) (186:186:186)) + (PORT datad (132:132:132) (161:161:161)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datac (765:765:765) (892:892:892)) + (PORT datad (399:399:399) (455:455:455)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (859:859:859) (998:998:998)) + (PORT datac (744:744:744) (855:855:855)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (510:510:510)) + (PORT datab (760:760:760) (873:873:873)) + (PORT datac (462:462:462) (536:536:536)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (229:229:229)) + (PORT datab (652:652:652) (758:758:758)) + (PORT datac (331:331:331) (377:377:377)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (666:666:666)) + (PORT datab (230:230:230) (288:288:288)) + (PORT datac (708:708:708) (801:801:801)) + (PORT datad (118:118:118) (141:141:141)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (522:522:522) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (639:639:639) (739:739:739)) + (PORT datac (373:373:373) (449:449:449)) + (PORT datad (370:370:370) (443:443:443)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (591:591:591)) + (PORT datab (633:633:633) (738:738:738)) + (PORT datac (459:459:459) (533:533:533)) + (PORT datad (453:453:453) (524:524:524)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (211:211:211)) + (PORT datab (377:377:377) (451:451:451)) + (PORT datac (352:352:352) (400:400:400)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (300:300:300) (348:348:348)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (924:924:924)) + (PORT datac (129:129:129) (165:165:165)) + (PORT datad (836:836:836) (987:987:987)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (643:643:643)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (331:331:331) (386:386:386)) + (PORT datad (518:518:518) (587:587:587)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (927:927:927)) + (PORT datab (805:805:805) (920:920:920)) + (PORT datac (781:781:781) (931:931:931)) + (PORT datad (420:420:420) (478:478:478)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (960:960:960)) + (PORT datab (723:723:723) (862:862:862)) + (PORT datac (1139:1139:1139) (1319:1319:1319)) + (PORT datad (457:457:457) (521:521:521)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~16) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (762:762:762)) + (PORT datab (638:638:638) (727:727:727)) + (PORT datac (679:679:679) (801:801:801)) + (PORT datad (1292:1292:1292) (1495:1495:1495)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (796:796:796)) + (PORT datab (809:809:809) (940:940:940)) + (PORT datac (482:482:482) (552:552:552)) + (PORT datad (385:385:385) (457:457:457)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1144:1144:1144)) + (PORT datab (709:709:709) (821:821:821)) + (PORT datac (565:565:565) (676:676:676)) + (PORT datad (565:565:565) (667:667:667)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (368:368:368)) + (PORT datab (305:305:305) (352:352:352)) + (PORT datac (749:749:749) (858:858:858)) + (PORT datad (894:894:894) (1042:1042:1042)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~38) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (682:682:682)) + (PORT datab (359:359:359) (431:431:431)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (559:559:559) (668:668:668)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (421:421:421)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (351:351:351) (405:405:405)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (253:253:253)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (306:306:306) (353:353:353)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (429:429:429)) + (PORT datab (197:197:197) (232:232:232)) + (PORT datac (641:641:641) (739:739:739)) + (PORT datad (335:335:335) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (993:993:993)) + (PORT datab (737:737:737) (865:865:865)) + (PORT datac (460:460:460) (534:534:534)) + (PORT datad (649:649:649) (735:735:735)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (539:539:539)) + (PORT datab (387:387:387) (457:457:457)) + (PORT datac (625:625:625) (734:734:734)) + (PORT datad (486:486:486) (563:563:563)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (639:639:639)) + (PORT datac (537:537:537) (649:649:649)) + (PORT datad (556:556:556) (665:665:665)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (439:439:439)) + (PORT datac (1153:1153:1153) (1321:1321:1321)) + (PORT datad (483:483:483) (561:561:561)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (537:537:537)) + (PORT datab (625:625:625) (736:736:736)) + (PORT datac (707:707:707) (815:815:815)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (692:692:692)) + (PORT datab (479:479:479) (558:558:558)) + (PORT datac (697:697:697) (803:803:803)) + (PORT datad (873:873:873) (989:989:989)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (171:171:171)) + (PORT datab (476:476:476) (546:546:546)) + (PORT datad (298:298:298) (342:342:342)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (557:557:557)) + (PORT datab (480:480:480) (555:555:555)) + (PORT datac (363:363:363) (426:426:426)) + (PORT datad (485:485:485) (563:563:563)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (388:388:388)) + (PORT datab (200:200:200) (237:237:237)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (353:353:353) (411:411:411)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (599:599:599) (685:685:685)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (388:388:388)) + (PORT datab (351:351:351) (420:420:420)) + (PORT datac (593:593:593) (675:675:675)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (731:731:731)) + (PORT datab (373:373:373) (448:448:448)) + (PORT datac (355:355:355) (414:414:414)) + (PORT datad (777:777:777) (886:886:886)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (158:158:158)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (792:792:792) (923:923:923)) + (PORT datad (619:619:619) (702:702:702)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (586:586:586)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (336:336:336) (393:393:393)) + (PORT datad (296:296:296) (340:340:340)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (451:451:451)) + (PORT datab (673:673:673) (773:773:773)) + (PORT datac (615:615:615) (706:706:706)) + (PORT datad (341:341:341) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (399:399:399)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (628:628:628) (741:741:741)) + (PORT datad (483:483:483) (560:560:560)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (374:374:374)) + (PORT datab (474:474:474) (552:552:552)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (516:516:516) (602:602:602)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (555:555:555)) + (PORT datab (1231:1231:1231) (1457:1457:1457)) + (PORT datac (909:909:909) (1104:1104:1104)) + (PORT datad (1077:1077:1077) (1278:1278:1278)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (926:926:926) (1123:1123:1123)) + (PORT datac (630:630:630) (730:730:730)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (903:903:903) (1077:1077:1077)) + (PORT datac (705:705:705) (832:832:832)) + (PORT datad (893:893:893) (1043:1043:1043)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (942:942:942)) + (PORT datab (647:647:647) (747:747:747)) + (PORT datac (481:481:481) (557:557:557)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1307:1307:1307)) + (PORT datab (520:520:520) (611:611:611)) + (PORT datac (904:904:904) (1024:1024:1024)) + (PORT datad (512:512:512) (589:589:589)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (743:743:743)) + (PORT datac (710:710:710) (838:838:838)) + (PORT datad (888:888:888) (1053:1053:1053)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (883:883:883)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (219:219:219)) + (PORT datab (528:528:528) (630:630:630)) + (PORT datac (365:365:365) (446:446:446)) + (PORT datad (957:957:957) (1116:1116:1116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (1002:1002:1002)) + (PORT datab (351:351:351) (416:416:416)) + (PORT datac (602:602:602) (689:689:689)) + (PORT datad (596:596:596) (681:681:681)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (695:695:695)) + (PORT datab (594:594:594) (690:690:690)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (740:740:740) (837:837:837)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (854:854:854) (945:945:945)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (294:294:294) (334:334:334)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (854:854:854) (945:945:945)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (869:869:869) (967:967:967)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (911:911:911)) + (PORT asdata (300:300:300) (342:342:342)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (869:869:869) (967:967:967)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datad (120:120:120) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (581:581:581)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (495:495:495) (567:567:567)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (457:457:457) (531:531:531)) + (PORT datac (944:944:944) (1079:1079:1079)) + (PORT datad (662:662:662) (759:759:759)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1231:1231:1231)) + (PORT datab (796:796:796) (921:921:921)) + (PORT datac (1042:1042:1042) (1174:1174:1174)) + (PORT datad (466:466:466) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (391:391:391)) + (PORT datab (355:355:355) (419:419:419)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (338:338:338) (392:392:392)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (103:103:103) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (638:638:638)) + (PORT datab (325:325:325) (378:378:378)) + (PORT datac (975:975:975) (1125:1125:1125)) + (PORT datad (308:308:308) (356:356:356)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (605:605:605) (692:692:692)) + (PORT datac (296:296:296) (344:344:344)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (PORT ena (805:805:805) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (903:903:903)) + (PORT asdata (709:709:709) (808:808:808)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (643:643:643) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (897:897:897)) + (PORT asdata (500:500:500) (561:561:561)) + (PORT clrn (899:899:899) (886:886:886)) + (PORT ena (851:851:851) (943:943:943)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (746:746:746)) + (PORT datac (646:646:646) (746:746:746)) + (PORT datad (119:119:119) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (942:942:942) (1106:1106:1106)) + (PORT datad (1144:1144:1144) (1368:1368:1368)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1415:1415:1415)) + (PORT datab (593:593:593) (716:716:716)) + (PORT datac (543:543:543) (654:654:654)) + (PORT datad (816:816:816) (956:956:956)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (1041:1041:1041)) + (PORT datad (888:888:888) (1038:1038:1038)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (150:150:150)) + (PORT datab (442:442:442) (510:510:510)) + (PORT datac (570:570:570) (647:647:647)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (544:544:544)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (342:342:342) (405:405:405)) + (PORT datad (322:322:322) (374:374:374)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (1022:1022:1022)) + (PORT datab (302:302:302) (346:346:346)) + (PORT datac (451:451:451) (512:512:512)) + (PORT datad (640:640:640) (726:726:726)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (413:413:413)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (344:344:344) (405:405:405)) + (PORT datad (516:516:516) (612:612:612)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (754:754:754)) + (PORT datab (629:629:629) (721:721:721)) + (PORT datac (619:619:619) (716:716:716)) + (PORT datad (300:300:300) (345:345:345)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (1008:1008:1008)) + (PORT datab (566:566:566) (654:654:654)) + (PORT datac (718:718:718) (865:865:865)) + (PORT datad (626:626:626) (725:725:725)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (503:503:503)) + (PORT datab (834:834:834) (965:965:965)) + (PORT datac (505:505:505) (586:586:586)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (447:447:447)) + (PORT datab (640:640:640) (740:740:740)) + (PORT datac (294:294:294) (342:342:342)) + (PORT datad (684:684:684) (788:788:788)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1414:1414:1414)) + (PORT datab (759:759:759) (863:863:863)) + (PORT datac (562:562:562) (637:637:637)) + (PORT datad (542:542:542) (646:646:646)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (568:568:568)) + (PORT datab (681:681:681) (788:788:788)) + (PORT datac (322:322:322) (377:377:377)) + (PORT datad (428:428:428) (480:480:480)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (979:979:979)) + (PORT datac (539:539:539) (649:649:649)) + (PORT datad (1181:1181:1181) (1380:1380:1380)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (868:868:868)) + (PORT datab (153:153:153) (207:207:207)) + (PORT datac (638:638:638) (736:736:736)) + (PORT datad (647:647:647) (742:742:742)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (655:655:655) (754:754:754)) + (PORT datac (598:598:598) (676:676:676)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (773:773:773)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (320:320:320) (380:380:380)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1158:1158:1158)) + (PORT datab (526:526:526) (620:620:620)) + (PORT datac (318:318:318) (361:361:361)) + (PORT datad (853:853:853) (988:988:988)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (348:348:348)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (584:584:584) (662:662:662)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (1023:1023:1023)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (460:460:460) (548:548:548)) + (PORT datad (1041:1041:1041) (1193:1193:1193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (425:425:425)) + (PORT datab (190:190:190) (229:229:229)) + (PORT datac (593:593:593) (673:673:673)) + (PORT datad (457:457:457) (524:524:524)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (747:747:747)) + (PORT datab (1425:1425:1425) (1665:1665:1665)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (727:727:727) (829:829:829)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (742:742:742)) + (PORT datab (646:646:646) (744:744:744)) + (PORT datac (674:674:674) (801:801:801)) + (PORT datad (680:680:680) (788:788:788)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (299:299:299) (340:340:340)) + (PORT clrn (904:904:904) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (618:618:618) (725:725:725)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (899:899:899) (886:886:886)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (369:369:369) (416:416:416)) + (PORT clrn (899:899:899) (886:886:886)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (263:263:263)) + (PORT datad (723:723:723) (842:842:842)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (790:790:790)) + (PORT datab (644:644:644) (742:742:742)) + (PORT datac (674:674:674) (801:801:801)) + (PORT datad (905:905:905) (1023:1023:1023)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (571:571:571)) + (PORT datac (514:514:514) (605:605:605)) + (PORT datad (664:664:664) (766:766:766)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (323:323:323)) + (PORT datab (285:285:285) (334:334:334)) + (PORT datad (479:479:479) (553:553:553)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (803:803:803) (973:973:973)) - (PORT datac (739:739:739) (898:898:898)) - (PORT datad (1422:1422:1422) (1644:1644:1644)) + (PORT dataa (835:835:835) (987:987:987)) + (PORT datab (505:505:505) (606:606:606)) + (PORT datad (833:833:833) (971:971:971)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -31078,10 +31634,10 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datab (523:523:523) (603:603:603)) - (PORT datac (450:450:450) (516:516:516)) - (PORT datad (955:955:955) (1136:1136:1136)) + (PORT dataa (473:473:473) (553:553:553)) + (PORT datab (1232:1232:1232) (1458:1458:1458)) + (PORT datac (629:629:629) (728:728:728)) + (PORT datad (429:429:429) (491:491:491)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -31094,12 +31650,12 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (1080:1080:1080) (1282:1282:1282)) - (PORT datac (1189:1189:1189) (1393:1393:1393)) - (PORT datad (955:955:955) (1136:1136:1136)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (845:845:845) (996:996:996)) + (PORT datab (467:467:467) (557:557:557)) + (PORT datac (1051:1051:1051) (1243:1243:1243)) + (PORT datad (977:977:977) (1145:1145:1145)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31107,14 +31663,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) + (PORT clk (912:912:912) (898:898:898)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (615:615:615) (685:685:685)) - (PORT sload (758:758:758) (851:851:851)) - (PORT ena (778:778:778) (852:852:852)) + (PORT asdata (604:604:604) (683:683:683)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -31127,24 +31683,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT datac (767:767:767) (892:892:892)) - (PORT datad (1116:1116:1116) (1308:1308:1308)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (188:188:188) (223:223:223)) + (PORT datab (279:279:279) (322:322:322)) + (PORT datad (480:480:480) (554:554:554)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (499:499:499) (550:550:550)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (916:916:916)) + (PORT datab (607:607:607) (718:718:718)) + (PORT datac (606:606:606) (719:719:719)) + (PORT datad (620:620:620) (721:721:721)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (772:772:772)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datad (291:291:291) (332:332:332)) + (PORT dataa (479:479:479) (561:561:561)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (103:103:103) (121:121:121)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -31153,14 +31747,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) + (PORT clk (913:913:913) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (389:389:389) (447:447:447)) - (PORT sload (758:758:758) (851:851:851)) - (PORT ena (778:778:778) (852:852:852)) + (PORT asdata (484:484:484) (544:544:544)) + (PORT sload (647:647:647) (726:726:726)) + (PORT ena (1126:1126:1126) (1232:1232:1232)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -31173,25 +31767,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) + (INSTANCE z80_\|address_pins_\|abus\[6\]\~25) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1554:1554:1554)) - (PORT datad (789:789:789) (921:921:921)) + (PORT dataa (768:768:768) (915:915:915)) + (PORT datac (484:484:484) (575:575:575)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (171:171:171) (239:239:239)) - (PORT datac (491:491:491) (582:582:582)) - (PORT datad (340:340:340) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (118:118:118) (150:150:150)) + (PORT datab (341:341:341) (407:407:407)) + (PORT datad (481:481:481) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (488:488:488) (545:545:545)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datac (127:127:127) (168:168:168)) + (PORT datad (1332:1332:1332) (1561:1561:1561)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31199,14 +31825,116 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (331:331:331) (389:389:389)) - (PORT datab (710:710:710) (832:832:832)) - (PORT datac (399:399:399) (491:491:491)) - (PORT datad (328:328:328) (385:385:385)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (197:197:197) (236:236:236)) + (PORT datab (491:491:491) (573:573:573)) + (PORT datad (177:177:177) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (493:493:493) (555:555:555)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (566:566:566)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (490:490:490) (552:552:552)) + (PORT sload (647:647:647) (726:726:726)) + (PORT ena (1126:1126:1126) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (565:565:565)) + (PORT datab (173:173:173) (209:209:209)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (310:310:310) (357:357:357)) + (PORT sload (647:647:647) (726:726:726)) + (PORT ena (1126:1126:1126) (1232:1232:1232)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (735:735:735)) + (PORT datab (600:600:600) (710:710:710)) + (PORT datac (621:621:621) (737:737:737)) + (PORT datad (755:755:755) (888:888:888)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -31215,148 +31943,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (INSTANCE Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (249:249:249)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (98:98:98) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (417:417:417)) - (PORT datab (1610:1610:1610) (1880:1880:1880)) - (PORT datac (353:353:353) (411:411:411)) - (PORT datad (348:348:348) (411:411:411)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (151:151:151) (205:205:205)) - (PORT datab (515:515:515) (610:610:610)) - (PORT datac (547:547:547) (648:648:648)) - (PORT datad (144:144:144) (187:187:187)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (670:670:670)) - (PORT datac (153:153:153) (206:206:206)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (170:170:170) (237:237:237)) - (PORT datac (489:489:489) (580:580:580)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (765:765:765)) - (PORT datac (375:375:375) (458:458:458)) - (PORT datad (327:327:327) (399:399:399)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (182:182:182) (221:221:221)) + (PORT datac (596:596:596) (677:677:677)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (521:521:521)) - (PORT datab (174:174:174) (211:211:211)) - (PORT datad (105:105:105) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (888:888:888)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (420:420:420) (503:503:503)) - (PORT datac (243:243:243) (305:305:305)) - (PORT datad (495:495:495) (582:582:582)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -31365,89 +31959,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) + (INSTANCE D\[5\]\~26) (DELAY (ABSOLUTE - (PORT dataa (550:550:550) (652:652:652)) - (PORT datab (350:350:350) (427:427:427)) - (PORT datac (377:377:377) (460:460:460)) - (PORT datad (637:637:637) (736:736:736)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (217:217:217) (259:259:259)) + (PORT datac (190:190:190) (225:225:225)) + (PORT datad (614:614:614) (700:700:700)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (638:638:638)) - (PORT datab (417:417:417) (499:499:499)) - (PORT datac (383:383:383) (464:464:464)) - (PORT datad (525:525:525) (619:619:619)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (508:508:508)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (294:294:294) (341:341:341)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (899:899:899)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datad (620:620:620) (720:720:720)) + (PORT dataa (345:345:345) (403:403:403)) + (PORT datab (496:496:496) (579:579:579)) + (PORT datad (291:291:291) (333:333:333)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -31457,11 +31990,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (912:912:912) (898:898:898)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (468:468:468) (526:526:526)) - (PORT sload (642:642:642) (710:710:710)) - (PORT ena (769:769:769) (838:838:838)) + (PORT asdata (471:471:471) (533:533:533)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -31474,12 +32007,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~23) (DELAY (ABSOLUTE - (PORT datac (960:960:960) (1139:1139:1139)) - (PORT datad (1486:1486:1486) (1743:1743:1743)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (1356:1356:1356) (1591:1591:1591)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -31489,9 +32022,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (179:179:179) (215:215:215)) - (PORT datad (620:620:620) (720:720:720)) + (PORT dataa (287:287:287) (328:328:328)) + (PORT datab (339:339:339) (399:399:399)) + (PORT datad (478:478:478) (551:551:551)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -31503,11 +32036,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (912:912:912) (898:898:898)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (481:481:481) (539:539:539)) - (PORT sload (642:642:642) (710:710:710)) - (PORT ena (769:769:769) (838:838:838)) + (PORT asdata (947:947:947) (1075:1075:1075)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -31523,213 +32056,22 @@ (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1374:1374:1374) (1626:1626:1626)) - (PORT datad (943:943:943) (1097:1097:1097)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (715:715:715) (839:839:839)) - (PORT datac (394:394:394) (483:483:483)) + (PORT datab (533:533:533) (638:638:638)) + (PORT datac (842:842:842) (977:977:977)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (438:438:438) (533:533:533)) - (PORT datab (369:369:369) (441:441:441)) - (PORT datac (373:373:373) (447:447:447)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT datac (363:363:363) (433:433:433)) - (PORT datad (414:414:414) (504:504:504)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (479:479:479)) - (PORT datab (713:713:713) (837:837:837)) - (PORT datac (393:393:393) (482:482:482)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (423:423:423) (515:515:515)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (161:161:161) (221:221:221)) - (PORT datac (458:458:458) (526:526:526)) - (PORT datad (384:384:384) (469:469:469)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (449:449:449)) - (PORT datac (540:540:540) (637:637:637)) - (PORT datad (357:357:357) (424:424:424)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (570:570:570)) - (PORT datab (330:330:330) (384:384:384)) - (PORT datad (99:99:99) (119:119:119)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (420:420:420)) - (PORT datab (810:810:810) (927:927:927)) - (PORT datac (488:488:488) (569:569:569)) - (PORT datad (190:190:190) (236:236:236)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datad (620:620:620) (719:719:719)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (381:381:381) (437:437:437)) - (PORT sload (642:642:642) (710:710:710)) - (PORT ena (769:769:769) (838:838:838)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (990:990:990) (1163:1163:1163)) - (PORT datac (1285:1285:1285) (1512:1512:1512)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (227:227:227)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (623:623:623) (723:723:723)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (421:421:421) (491:491:491)) + (PORT datab (441:441:441) (510:510:510)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -31740,11 +32082,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (916:916:916) (903:903:903)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (389:389:389) (445:445:445)) - (PORT sload (642:642:642) (710:710:710)) - (PORT ena (769:769:769) (838:838:838)) + (PORT asdata (666:666:666) (760:760:760)) + (PORT sload (939:939:939) (1056:1056:1056)) + (PORT ena (756:756:756) (825:825:825)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -31757,164 +32099,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (250:250:250)) - (PORT datab (424:424:424) (517:517:517)) - (PORT datac (390:390:390) (475:475:475)) - (PORT datad (180:180:180) (210:210:210)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT datab (225:225:225) (286:286:286)) - (PORT datac (413:413:413) (499:499:499)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (419:419:419) (507:507:507)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT datab (800:800:800) (963:963:963)) + (PORT datac (131:131:131) (174:174:174)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (895:895:895) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (887:887:887) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1112:1112:1112) (1315:1315:1315)) - (PORT datac (1286:1286:1286) (1512:1512:1512)) - (PORT datad (355:355:355) (426:426:426)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) + (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (600:600:600)) - (PORT datab (536:536:536) (642:642:642)) - (PORT datad (109:109:109) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (668:668:668)) - (PORT datab (155:155:155) (208:208:208)) - (PORT datac (134:134:134) (179:179:179)) - (PORT datad (388:388:388) (473:473:473)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (670:670:670)) - (PORT datab (519:519:519) (614:614:614)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (243:243:243)) - (PORT datab (334:334:334) (398:398:398)) - (PORT datad (424:424:424) (487:487:487)) + (PORT dataa (679:679:679) (793:793:793)) + (PORT datab (643:643:643) (741:741:741)) + (PORT datac (675:675:675) (801:801:801)) + (PORT datad (907:907:907) (1024:1024:1024)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (345:345:345) (410:410:410)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (1193:1193:1193) (1384:1384:1384)) + (PORT datab (558:558:558) (654:654:654)) + (PORT datac (999:999:999) (1142:1142:1142)) + (PORT datad (114:114:114) (137:137:137)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -31923,96 +32143,49 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datac (1429:1429:1429) (1677:1677:1677)) - (PORT datad (653:653:653) (774:774:774)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (495:495:495)) - (PORT datab (507:507:507) (609:609:609)) - (PORT datac (410:410:410) (504:504:504)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (603:603:603)) - (PORT datab (390:390:390) (465:465:465)) - (PORT datac (390:390:390) (475:475:475)) - (PORT datad (190:190:190) (226:226:226)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT datab (533:533:533) (640:640:640)) + (PORT datac (843:843:843) (978:978:978)) + (PORT datad (665:665:665) (772:772:772)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) + (INSTANCE z80_\|address_pins_\|abus\[0\]\~24) (DELAY (ABSOLUTE - (PORT datab (115:115:115) (148:148:148)) - (PORT datac (239:239:239) (312:312:312)) - (PORT datad (337:337:337) (392:392:392)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (610:610:610) (720:720:720)) + (PORT datad (757:757:757) (891:891:891)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~27) (DELAY (ABSOLUTE - (PORT datab (262:262:262) (327:327:327)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (771:771:771) (919:919:919)) + (PORT datac (605:605:605) (717:717:717)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (889:889:889)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) + (INSTANCE z80_\|address_pins_\|abus\[2\]\~28) (DELAY (ABSOLUTE - (PORT dataa (389:389:389) (472:472:472)) - (PORT datad (407:407:407) (499:499:499)) + (PORT dataa (772:772:772) (920:920:920)) + (PORT datad (618:618:618) (719:719:719)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -32020,78 +32193,37 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) + (INSTANCE z80_\|address_pins_\|abus\[3\]\~29) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (249:249:249)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (144:144:144) (195:195:195)) + (PORT datad (1332:1332:1332) (1561:1561:1561)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (INSTANCE z80_\|address_pins_\|abus\[4\]\~30) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (772:772:772)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datad (165:165:165) (193:193:193)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (600:600:600) (710:710:710)) + (PORT datad (755:755:755) (889:889:889)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (386:386:386) (442:442:442)) - (PORT sload (758:758:758) (851:851:851)) - (PORT ena (778:778:778) (852:852:852)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (INSTANCE z80_\|address_pins_\|abus\[5\]\~31) (DELAY (ABSOLUTE - (PORT dataa (1311:1311:1311) (1550:1550:1550)) - (PORT datad (799:799:799) (933:933:933)) + (PORT dataa (769:769:769) (918:918:918)) + (PORT datac (621:621:621) (737:737:737)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -32100,11 +32232,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (769:769:769)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (482:482:482) (566:566:566)) + (PORT datad (159:159:159) (185:185:185)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32114,11 +32246,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) + (PORT clk (915:915:915) (902:902:902)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (381:381:381) (433:433:433)) - (PORT sload (758:758:758) (851:851:851)) - (PORT ena (778:778:778) (852:852:852)) + (PORT asdata (483:483:483) (544:544:544)) + (PORT sload (675:675:675) (763:763:763)) + (PORT ena (1038:1038:1038) (1143:1143:1143)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -32131,162 +32263,393 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (INSTANCE z80_\|address_pins_\|abus\[8\]\~17) (DELAY (ABSOLUTE - (PORT datab (515:515:515) (617:617:617)) - (PORT datad (1362:1362:1362) (1600:1600:1600)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (346:346:346) (416:416:416)) + (PORT datac (1090:1090:1090) (1287:1287:1287)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (456:456:456)) - (PORT datab (366:366:366) (441:441:441)) - (PORT datac (369:369:369) (430:430:430)) - (PORT datad (856:856:856) (988:988:988)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (1375:1375:1375) (1624:1624:1624)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (197:197:197) (236:236:236)) + (PORT datab (482:482:482) (566:566:566)) + (PORT datad (161:161:161) (190:190:190)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (902:902:902)) - (PORT asdata (302:302:302) (345:345:345)) - (PORT clrn (919:919:919) (901:901:901)) + (PORT clk (915:915:915) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (311:311:311) (353:353:353)) + (PORT sload (675:675:675) (763:763:763)) + (PORT ena (1038:1038:1038) (1143:1143:1143)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1447:1447:1447)) + (PORT datad (132:132:132) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datad (469:469:469) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (309:309:309) (356:356:356)) + (PORT sload (675:675:675) (763:763:763)) + (PORT ena (1038:1038:1038) (1143:1143:1143)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (416:416:416) (483:483:483)) + (PORT datad (1211:1211:1211) (1421:1421:1421)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (491:491:491)) + (PORT datab (190:190:190) (229:229:229)) + (PORT datad (320:320:320) (369:369:369)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (650:650:650) (737:737:737)) + (PORT sload (939:939:939) (1056:1056:1056)) + (PORT ena (756:756:756) (825:825:825)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (418:418:418)) + (PORT datac (622:622:622) (757:757:757)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (491:491:491)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datad (318:318:318) (369:369:369)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (628:628:628) (709:709:709)) + (PORT sload (939:939:939) (1056:1056:1056)) + (PORT ena (756:756:756) (825:825:825)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (781:781:781) (942:942:942)) + (PORT datad (128:128:128) (164:164:164)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (697:697:697) (798:798:798)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (714:714:714) (827:827:827)) + (PORT d[1] (655:655:655) (747:747:747)) + (PORT d[2] (718:718:718) (826:826:826)) + (PORT d[3] (1799:1799:1799) (2066:2066:2066)) + (PORT d[4] (1141:1141:1141) (1337:1337:1337)) + (PORT d[5] (704:704:704) (813:813:813)) + (PORT d[6] (681:681:681) (787:787:787)) + (PORT d[7] (880:880:880) (1017:1017:1017)) + (PORT d[8] (973:973:973) (1118:1118:1118)) + (PORT d[9] (1015:1015:1015) (1165:1165:1165)) + (PORT d[10] (1253:1253:1253) (1452:1452:1452)) + (PORT d[11] (973:973:973) (1112:1112:1112)) + (PORT d[12] (968:968:968) (1135:1135:1135)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1160:1160:1160) (1271:1271:1271)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1470:1470:1470) (1569:1569:1569)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (281:281:281) (301:301:301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (532:532:532) (602:602:602)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD asdata (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (901:901:901)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (549:549:549)) - (PORT datab (134:134:134) (184:184:184)) - (PORT datac (539:539:539) (626:626:626)) - (PORT datad (125:125:125) (165:165:165)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1695:1695:1695)) - (PORT datab (1122:1122:1122) (1325:1325:1325)) - (PORT datac (1570:1570:1570) (1835:1835:1835)) - (PORT datad (1216:1216:1216) (1397:1397:1397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1115:1115:1115) (1319:1319:1319)) - (PORT datac (1283:1283:1283) (1509:1509:1509)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1696:1696:1696)) - (PORT datab (1119:1119:1119) (1322:1322:1322)) - (PORT datac (1569:1569:1569) (1834:1834:1834)) - (PORT datad (1219:1219:1219) (1399:1399:1399)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (267:267:267)) - (PORT datab (688:688:688) (798:798:798)) - (PORT datac (694:694:694) (797:797:797)) - (PORT datad (768:768:768) (886:886:886)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (1194:1194:1194) (1384:1384:1384)) + (PORT datab (560:560:560) (657:657:657)) + (PORT datac (1000:1000:1000) (1143:1143:1143)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32296,344 +32659,22 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1089:1089:1089) (1298:1298:1298)) - (PORT datac (1131:1131:1131) (1334:1334:1334)) - (PORT datad (800:800:800) (938:938:938)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (319:319:319) (369:369:369)) - (PORT datad (500:500:500) (580:580:580)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (715:715:715) (837:837:837)) + (PORT datab (854:854:854) (1002:1002:1002)) + (PORT datad (664:664:664) (779:779:779)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (527:527:527) (594:594:594)) - (PORT sload (641:641:641) (709:709:709)) - (PORT ena (649:649:649) (704:704:704)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1628:1628:1628)) - (PORT datac (591:591:591) (688:688:688)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (936:936:936) (1084:1084:1084)) - (PORT datad (167:167:167) (199:199:199)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (494:494:494) (561:561:561)) - (PORT sload (861:861:861) (960:960:960)) - (PORT ena (764:764:764) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (732:732:732)) - (PORT datad (1361:1361:1361) (1599:1599:1599)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (544:544:544)) - (PORT datab (952:952:952) (1107:1107:1107)) - (PORT datad (484:484:484) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (897:897:897)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (677:677:677) (775:775:775)) - (PORT sload (709:709:709) (784:784:784)) - (PORT ena (743:743:743) (803:803:803)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (143:143:143) (192:192:192)) - (PORT datad (1357:1357:1357) (1594:1594:1594)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (918:918:918) (1059:1059:1059)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (472:472:472) (528:528:528)) - (PORT sload (861:861:861) (960:960:960)) - (PORT ena (764:764:764) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (153:153:153) (201:201:201)) - (PORT datad (197:197:197) (246:246:246)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (937:937:937) (1084:1084:1084)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (496:496:496) (554:554:554)) - (PORT sload (861:861:861) (960:960:960)) - (PORT ena (764:764:764) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datac (698:698:698) (834:834:834)) - (PORT datad (1354:1354:1354) (1591:1591:1591)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (280:280:280) (329:329:329)) - (PORT datab (935:935:935) (1082:1082:1082)) - (PORT datad (161:161:161) (185:185:185)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (926:926:926) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (310:310:310) (352:352:352)) - (PORT sload (861:861:861) (960:960:960)) - (PORT ena (764:764:764) (831:831:831)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datac (834:834:834) (976:976:976)) - (PORT datad (1358:1358:1358) (1595:1595:1595)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (665:665:665)) - (PORT datab (495:495:495) (568:568:568)) - (PORT datad (940:940:940) (1085:1085:1085)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (897:897:897)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (685:685:685) (785:785:785)) - (PORT sload (709:709:709) (784:784:784)) - (PORT ena (743:743:743) (803:803:803)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1373:1373:1373) (1625:1625:1625)) - (PORT datac (134:134:134) (177:177:177)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (726:726:726) (845:845:845)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (658:658:658) (746:746:746)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -32642,23 +32683,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1375:1375:1375) (1629:1629:1629)) - (PORT d[1] (1485:1485:1485) (1680:1680:1680)) - (PORT d[2] (1090:1090:1090) (1255:1255:1255)) - (PORT d[3] (723:723:723) (834:834:834)) - (PORT d[4] (1271:1271:1271) (1447:1447:1447)) - (PORT d[5] (731:731:731) (849:849:849)) - (PORT d[6] (806:806:806) (920:920:920)) - (PORT d[7] (1360:1360:1360) (1562:1562:1562)) - (PORT d[8] (1271:1271:1271) (1499:1499:1499)) - (PORT d[9] (596:596:596) (690:690:690)) - (PORT d[10] (577:577:577) (670:670:670)) - (PORT d[11] (814:814:814) (927:927:927)) - (PORT d[12] (427:427:427) (501:501:501)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1498:1498:1498) (1700:1700:1700)) + (PORT d[1] (1520:1520:1520) (1719:1719:1719)) + (PORT d[2] (1312:1312:1312) (1495:1495:1495)) + (PORT d[3] (472:472:472) (541:541:541)) + (PORT d[4] (1361:1361:1361) (1607:1607:1607)) + (PORT d[5] (1569:1569:1569) (1780:1780:1780)) + (PORT d[6] (2336:2336:2336) (2694:2694:2694)) + (PORT d[7] (769:769:769) (877:877:877)) + (PORT d[8] (646:646:646) (746:746:746)) + (PORT d[9] (522:522:522) (597:597:597)) + (PORT d[10] (540:540:540) (623:623:623)) + (PORT d[11] (1648:1648:1648) (1864:1864:1864)) + (PORT d[12] (1033:1033:1033) (1195:1195:1195)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -32667,11 +32708,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1008:1008:1008) (1096:1096:1096)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1534:1534:1534) (1681:1681:1681)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -32680,17 +32721,421 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1000:1000:1000) (1066:1066:1066)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1637:1637:1637) (1763:1763:1763)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1385:1385:1385)) + (PORT datab (561:561:561) (658:658:658)) + (PORT datac (1000:1000:1000) (1143:1143:1143)) + (PORT datad (116:116:116) (138:138:138)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (857:857:857) (1005:1005:1005)) + (PORT datac (692:692:692) (812:812:812)) + (PORT datad (663:663:663) (779:779:779)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (668:668:668) (747:747:747)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1869:1869:1869) (2125:2125:2125)) + (PORT d[1] (1750:1750:1750) (1988:1988:1988)) + (PORT d[2] (2303:2303:2303) (2611:2611:2611)) + (PORT d[3] (838:838:838) (958:958:958)) + (PORT d[4] (1541:1541:1541) (1806:1806:1806)) + (PORT d[5] (1831:1831:1831) (2093:2093:2093)) + (PORT d[6] (2176:2176:2176) (2517:2517:2517)) + (PORT d[7] (959:959:959) (1087:1087:1087)) + (PORT d[8] (2253:2253:2253) (2611:2611:2611)) + (PORT d[9] (2461:2461:2461) (2831:2831:2831)) + (PORT d[10] (2230:2230:2230) (2598:2598:2598)) + (PORT d[11] (670:670:670) (760:760:760)) + (PORT d[12] (1577:1577:1577) (1855:1855:1855)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1034:1034:1034) (1148:1148:1148)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1324:1324:1324) (1411:1411:1411)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (103:103:103) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (912:912:912)) + (PORT asdata (680:680:680) (771:771:771)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1266:1266:1266)) + (PORT datab (697:697:697) (813:813:813)) + (PORT datac (514:514:514) (601:601:601)) + (PORT datad (945:945:945) (1071:1071:1071)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (800:800:800) (964:964:964)) + (PORT datac (133:133:133) (175:175:175)) + (PORT datad (479:479:479) (561:561:561)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (705:705:705) (810:810:810)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1039:1039:1039) (1186:1186:1186)) + (PORT d[1] (1124:1124:1124) (1279:1279:1279)) + (PORT d[2] (733:733:733) (850:850:850)) + (PORT d[3] (1939:1939:1939) (2230:2230:2230)) + (PORT d[4] (1142:1142:1142) (1339:1339:1339)) + (PORT d[5] (523:523:523) (607:607:607)) + (PORT d[6] (524:524:524) (610:610:610)) + (PORT d[7] (676:676:676) (776:776:776)) + (PORT d[8] (956:956:956) (1107:1107:1107)) + (PORT d[9] (1009:1009:1009) (1163:1163:1163)) + (PORT d[10] (1446:1446:1446) (1671:1671:1671)) + (PORT d[11] (1155:1155:1155) (1319:1319:1319)) + (PORT d[12] (957:957:957) (1125:1125:1125)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1042:1042:1042) (1147:1147:1147)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1258:1258:1258) (1348:1348:1348)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -32700,7 +33145,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -32710,7 +33155,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -32720,7 +33165,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -32730,7 +33175,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1069:1069:1069) (1085:1085:1085)) @@ -32744,7 +33189,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (609:609:609) (617:617:617)) @@ -32753,7 +33198,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -32762,7 +33207,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -32772,7 +33217,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -32780,228 +33225,17 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1133:1133:1133)) - (PORT asdata (1105:1105:1105) (1235:1235:1235)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (948:948:948) (1074:1074:1074)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~12) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (627:627:627)) - (PORT datab (488:488:488) (565:565:565)) - (PORT datac (632:632:632) (729:729:729)) - (PORT datad (545:545:545) (632:632:632)) + (PORT dataa (563:563:563) (640:640:640)) + (PORT datab (859:859:859) (980:980:980)) + (PORT datac (814:814:814) (951:951:951)) + (PORT datad (716:716:716) (825:825:825)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1296:1296:1296)) - (PORT datac (1131:1131:1131) (1335:1335:1335)) - (PORT datad (798:798:798) (935:935:935)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (844:844:844) (957:957:957)) - (PORT clk (1087:1087:1087) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1132:1132:1132) (1327:1327:1327)) - (PORT d[1] (1413:1413:1413) (1585:1585:1585)) - (PORT d[2] (1512:1512:1512) (1758:1758:1758)) - (PORT d[3] (641:641:641) (732:732:732)) - (PORT d[4] (1385:1385:1385) (1601:1601:1601)) - (PORT d[5] (1798:1798:1798) (2049:2049:2049)) - (PORT d[6] (1232:1232:1232) (1397:1397:1397)) - (PORT d[7] (1025:1025:1025) (1147:1147:1147)) - (PORT d[8] (1409:1409:1409) (1643:1643:1643)) - (PORT d[9] (953:953:953) (1074:1074:1074)) - (PORT d[10] (1443:1443:1443) (1625:1625:1625)) - (PORT d[11] (2339:2339:2339) (2720:2720:2720)) - (PORT d[12] (1426:1426:1426) (1614:1614:1614)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1115:1115:1115) (1203:1203:1203)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1106:1106:1106)) - (PORT d[0] (1200:1200:1200) (1274:1274:1274)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (PORT datab (690:690:690) (800:800:800)) - (PORT datac (694:694:694) (798:798:798)) - (PORT datad (770:770:770) (887:887:887)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33009,236 +33243,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~13) (DELAY (ABSOLUTE - (PORT dataa (1088:1088:1088) (1297:1297:1297)) - (PORT datac (1131:1131:1131) (1334:1334:1334)) - (PORT datad (799:799:799) (936:936:936)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (464:464:464) (519:519:519)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1720:1720:1720) (2007:2007:2007)) - (PORT d[1] (1938:1938:1938) (2220:2220:2220)) - (PORT d[2] (859:859:859) (991:991:991)) - (PORT d[3] (2305:2305:2305) (2612:2612:2612)) - (PORT d[4] (1680:1680:1680) (1971:1971:1971)) - (PORT d[5] (2530:2530:2530) (2887:2887:2887)) - (PORT d[6] (1261:1261:1261) (1431:1431:1431)) - (PORT d[7] (2287:2287:2287) (2600:2600:2600)) - (PORT d[8] (864:864:864) (986:986:986)) - (PORT d[9] (1228:1228:1228) (1402:1402:1402)) - (PORT d[10] (1305:1305:1305) (1482:1482:1482)) - (PORT d[11] (1796:1796:1796) (2105:2105:2105)) - (PORT d[12] (2451:2451:2451) (2782:2782:2782)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1083:1083:1083) (1166:1166:1166)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1535:1535:1535) (1652:1652:1652)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (819:819:819) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (491:491:491) (554:554:554)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (269:269:269)) - (PORT datab (686:686:686) (796:796:796)) - (PORT datac (693:693:693) (797:797:797)) - (PORT datad (767:767:767) (884:884:884)) + (PORT dataa (728:728:728) (841:841:841)) + (PORT datab (989:989:989) (1162:1162:1162)) + (PORT datac (778:778:778) (892:892:892)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1293:1293:1293)) - (PORT datac (1132:1132:1132) (1335:1335:1335)) - (PORT datad (795:795:795) (931:931:931)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (720:720:720) (836:836:836)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1295:1295:1295) (1469:1469:1469)) + (PORT d[1] (1179:1179:1179) (1333:1333:1333)) + (PORT d[2] (1104:1104:1104) (1257:1257:1257)) + (PORT d[3] (665:665:665) (762:762:762)) + (PORT d[4] (1470:1470:1470) (1690:1690:1690)) + (PORT d[5] (1350:1350:1350) (1526:1526:1526)) + (PORT d[6] (2130:2130:2130) (2462:2462:2462)) + (PORT d[7] (953:953:953) (1085:1085:1085)) + (PORT d[8] (707:707:707) (812:812:812)) + (PORT d[9] (884:884:884) (1018:1018:1018)) + (PORT d[10] (1008:1008:1008) (1152:1152:1152)) + (PORT d[11] (983:983:983) (1111:1111:1111)) + (PORT d[12] (899:899:899) (1039:1039:1039)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -33247,98 +33284,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1235:1235:1235) (1473:1473:1473)) - (PORT d[1] (1304:1304:1304) (1475:1475:1475)) - (PORT d[2] (925:925:925) (1064:1064:1064)) - (PORT d[3] (1424:1424:1424) (1622:1622:1622)) - (PORT d[4] (1291:1291:1291) (1472:1472:1472)) - (PORT d[5] (895:895:895) (1031:1031:1031)) - (PORT d[6] (964:964:964) (1094:1094:1094)) - (PORT d[7] (1247:1247:1247) (1418:1418:1418)) - (PORT d[8] (1400:1400:1400) (1648:1648:1648)) - (PORT d[9] (616:616:616) (713:713:713)) - (PORT d[10] (977:977:977) (1120:1120:1120)) - (PORT d[11] (795:795:795) (908:908:908)) - (PORT d[12] (584:584:584) (674:674:674)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (859:859:859) (926:926:926)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1107:1107:1107) (1184:1184:1184)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (954:954:954) (1049:1049:1049)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) + (PORT clk (1077:1077:1077) (1093:1093:1093)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -33349,96 +33318,103 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (617:617:617) (625:625:625)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~50) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (584:584:584) (668:668:668)) - (PORT datab (829:829:829) (972:972:972)) - (PORT datac (760:760:760) (888:888:888)) - (PORT datad (838:838:838) (961:961:961)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT datad (2552:2552:2552) (2874:2874:2874)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~51) + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT dataa (735:735:735) (846:846:846)) - (PORT datab (1036:1036:1036) (1217:1217:1217)) - (PORT datac (945:945:945) (1071:1071:1071)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (1094:1094:1094) (1237:1237:1237)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (271:271:271)) - (PORT datab (682:682:682) (791:791:791)) - (PORT datac (693:693:693) (796:796:796)) - (PORT datad (764:764:764) (881:881:881)) + (PORT dataa (1193:1193:1193) (1384:1384:1384)) + (PORT datab (557:557:557) (653:653:653)) + (PORT datac (999:999:999) (1142:1142:1142)) + (PORT datad (114:114:114) (135:135:135)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT inclk[0] (91:91:91) (78:78:78)) + (PORT datad (364:364:364) (434:434:434)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -33447,12 +33423,12 @@ (INSTANCE ula_\|video_\|vram_address\~0) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (311:311:311)) - (PORT datab (521:521:521) (622:622:622)) - (PORT datac (383:383:383) (466:466:466)) - (PORT datad (397:397:397) (476:476:476)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (260:260:260) (336:336:336)) + (PORT datab (804:804:804) (979:979:979)) + (PORT datac (898:898:898) (1043:1043:1043)) + (PORT datad (149:149:149) (192:192:192)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33463,9 +33439,25 @@ (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) - (PORT asdata (531:531:531) (596:596:596)) - (PORT ena (421:421:421) (441:441:441)) + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (436:436:436) (467:467:467)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (897:897:897) (998:998:998)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33474,39 +33466,13 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (469:469:469) (543:543:543)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT datac (482:482:482) (575:575:575)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (398:398:398) (466:466:466)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -33515,9 +33481,9 @@ (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (441:441:441)) + (PORT ena (436:436:436) (467:467:467)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33531,8 +33497,8 @@ (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT datac (487:487:487) (580:580:580)) - (PORT datad (473:473:473) (556:556:556)) + (PORT datac (783:783:783) (928:928:928)) + (PORT datad (397:397:397) (466:466:466)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33543,9 +33509,9 @@ (INSTANCE ula_\|video_\|vram_address\[3\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (441:441:441)) + (PORT ena (436:436:436) (467:467:467)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33559,10 +33525,10 @@ (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (602:602:602)) - (PORT datab (487:487:487) (581:581:581)) - (PORT datad (473:473:473) (552:552:552)) - (IOPATH dataa combout (159:159:159) (173:173:173)) + (PORT dataa (805:805:805) (951:951:951)) + (PORT datab (407:407:407) (489:489:489)) + (PORT datad (398:398:398) (466:466:466)) + (IOPATH dataa combout (159:159:159) (165:165:165)) (IOPATH datab combout (161:161:161) (176:176:176)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33573,9 +33539,9 @@ (INSTANCE ula_\|video_\|vram_address\[4\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (441:441:441)) + (PORT ena (436:436:436) (467:467:467)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33589,8 +33555,8 @@ (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT dataa (699:699:699) (815:815:815)) - (PORT datab (328:328:328) (394:394:394)) + (PORT dataa (627:627:627) (741:741:741)) + (PORT datab (766:766:766) (914:914:914)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -33604,9 +33570,9 @@ (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (479:479:479)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (340:340:340) (414:414:414)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -33618,7 +33584,7 @@ (INSTANCE ula_\|video_\|Add4\~4) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (449:449:449)) + (PORT dataa (676:676:676) (798:798:798)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -33632,9 +33598,9 @@ (INSTANCE ula_\|video_\|Add4\~6) (DELAY (ABSOLUTE - (PORT datab (497:497:497) (585:585:585)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (361:361:361) (429:429:429)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -33646,14 +33612,14 @@ (INSTANCE ula_\|video_\|vram_address\[5\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (487:487:487) (511:511:511)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (458:458:458) (494:494:494)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -33662,9 +33628,9 @@ (INSTANCE ula_\|video_\|Add4\~8) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (601:601:601)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (443:443:443) (524:524:524)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -33676,14 +33642,14 @@ (INSTANCE ula_\|video_\|vram_address\[6\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (487:487:487) (511:511:511)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (349:349:349) (381:381:381)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -33692,7 +33658,7 @@ (INSTANCE ula_\|video_\|Add4\~10) (DELAY (ABSOLUTE - (PORT datab (508:508:508) (597:597:597)) + (PORT datab (352:352:352) (422:422:422)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -33706,14 +33672,14 @@ (INSTANCE ula_\|video_\|vram_address\[7\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (487:487:487) (511:511:511)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (710:710:710) (776:776:776)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -33722,7 +33688,7 @@ (INSTANCE ula_\|video_\|Add4\~12) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (468:468:468)) + (PORT dataa (403:403:403) (481:481:481)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -33736,10 +33702,10 @@ (INSTANCE ula_\|video_\|Selector6\~0) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (611:611:611)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (165:165:165) (173:173:173)) + (PORT dataa (184:184:184) (228:228:228)) + (PORT datac (307:307:307) (362:362:362)) + (PORT datad (494:494:494) (586:586:586)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33747,15 +33713,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (311:311:311)) - (PORT datab (519:519:519) (619:619:619)) - (PORT datac (383:383:383) (467:467:467)) - (PORT datad (396:396:396) (475:475:475)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (259:259:259) (335:335:335)) + (PORT datab (804:804:804) (978:978:978)) + (PORT datac (899:899:899) (1044:1044:1044)) + (PORT datad (149:149:149) (192:192:192)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33766,9 +33732,9 @@ (INSTANCE ula_\|video_\|vram_address\[8\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (501:501:501) (544:544:544)) + (PORT ena (742:742:742) (802:802:802)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33782,8 +33748,8 @@ (INSTANCE ula_\|video_\|Add4\~14) (DELAY (ABSOLUTE - (PORT dataa (599:599:599) (690:690:690)) - (IOPATH dataa combout (188:188:188) (193:193:193)) + (PORT datad (425:425:425) (495:495:495)) + (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -33793,10 +33759,10 @@ (INSTANCE ula_\|video_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (603:603:603)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (520:520:520) (618:618:618)) + (PORT datac (165:165:165) (199:199:199)) + (PORT datad (178:178:178) (211:211:211)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33807,9 +33773,9 @@ (INSTANCE ula_\|video_\|vram_address\[9\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (501:501:501) (544:544:544)) + (PORT ena (742:742:742) (802:802:802)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33823,12 +33789,12 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~2) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (311:311:311)) - (PORT datab (529:529:529) (630:630:630)) - (PORT datac (378:378:378) (461:461:461)) - (PORT datad (402:402:402) (481:481:481)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (261:261:261) (337:337:337)) + (PORT datab (805:805:805) (980:980:980)) + (PORT datac (896:896:896) (1042:1042:1042)) + (PORT datad (149:149:149) (194:194:194)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33839,11 +33805,11 @@ (INSTANCE ula_\|video_\|vram_address\[10\]\~3) (DELAY (ABSOLUTE - (PORT dataa (176:176:176) (214:214:214)) - (PORT datab (191:191:191) (230:230:230)) - (PORT datad (400:400:400) (479:479:479)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (261:261:261) (338:338:338)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (514:514:514) (577:577:577)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33854,7 +33820,7 @@ (INSTANCE ula_\|video_\|vram_address\[10\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -33868,8 +33834,8 @@ (INSTANCE ula_\|video_\|Selector3\~0) (DELAY (ABSOLUTE - (PORT datac (490:490:490) (586:586:586)) - (PORT datad (95:95:95) (113:113:113)) + (PORT datac (167:167:167) (201:201:201)) + (PORT datad (498:498:498) (591:591:591)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -33880,9 +33846,9 @@ (INSTANCE ula_\|video_\|vram_address\[11\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (501:501:501) (544:544:544)) + (PORT ena (742:742:742) (802:802:802)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33896,10 +33862,10 @@ (INSTANCE ula_\|video_\|Selector2\~0) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (602:602:602)) - (PORT datac (97:97:97) (121:121:121)) + (PORT dataa (522:522:522) (620:620:620)) + (PORT datad (177:177:177) (211:211:211)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -33908,9 +33874,9 @@ (INSTANCE ula_\|video_\|vram_address\[12\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (501:501:501) (544:544:544)) + (PORT ena (742:742:742) (802:802:802)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -33919,12 +33885,2024 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (866:866:866) (988:988:988)) + (PORT clk (1104:1104:1104) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2140:2140:2140) (2421:2421:2421)) + (PORT d[1] (2460:2460:2460) (2793:2793:2793)) + (PORT d[2] (1888:1888:1888) (2134:2134:2134)) + (PORT d[3] (1818:1818:1818) (2118:2118:2118)) + (PORT d[4] (1849:1849:1849) (2147:2147:2147)) + (PORT d[5] (1768:1768:1768) (2047:2047:2047)) + (PORT d[6] (1777:1777:1777) (2053:2053:2053)) + (PORT d[7] (2516:2516:2516) (2849:2849:2849)) + (PORT d[8] (1683:1683:1683) (1961:1961:1961)) + (PORT d[9] (1598:1598:1598) (1864:1864:1864)) + (PORT d[10] (1602:1602:1602) (1895:1895:1895)) + (PORT d[11] (1375:1375:1375) (1577:1577:1577)) + (PORT d[12] (1191:1191:1191) (1412:1412:1412)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1261:1261:1261) (1367:1367:1367)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1120:1120:1120)) + (PORT d[0] (3044:3044:3044) (2804:2804:2804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (791:791:791) (890:890:890)) + (PORT clk (1064:1064:1064) (1080:1080:1080)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2369:2369:2369) (2676:2676:2676)) + (PORT d[1] (2417:2417:2417) (2792:2792:2792)) + (PORT d[2] (2290:2290:2290) (2598:2598:2598)) + (PORT d[3] (2287:2287:2287) (2590:2590:2590)) + (PORT d[4] (2299:2299:2299) (2617:2617:2617)) + (PORT d[5] (2496:2496:2496) (2900:2900:2900)) + (PORT d[6] (2473:2473:2473) (2854:2854:2854)) + (PORT d[7] (2542:2542:2542) (2932:2932:2932)) + (PORT d[8] (2362:2362:2362) (2687:2687:2687)) + (PORT d[9] (2380:2380:2380) (2694:2694:2694)) + (PORT d[10] (2275:2275:2275) (2574:2574:2574)) + (PORT d[11] (2390:2390:2390) (2724:2724:2724)) + (PORT d[12] (2344:2344:2344) (2667:2667:2667)) + (PORT clk (1061:1061:1061) (1079:1079:1079)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1080:1080:1080)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1490:1490:1490) (1691:1691:1691)) + (PORT d[1] (1331:1331:1331) (1499:1499:1499)) + (PORT d[2] (1314:1314:1314) (1501:1501:1501)) + (PORT d[3] (493:493:493) (572:572:572)) + (PORT d[4] (1524:1524:1524) (1786:1786:1786)) + (PORT d[5] (1561:1561:1561) (1770:1770:1770)) + (PORT d[6] (2328:2328:2328) (2683:2683:2683)) + (PORT d[7] (792:792:792) (910:910:910)) + (PORT d[8] (830:830:830) (949:949:949)) + (PORT d[9] (833:833:833) (951:951:951)) + (PORT d[10] (361:361:361) (415:415:415)) + (PORT d[11] (1484:1484:1484) (1679:1679:1679)) + (PORT d[12] (991:991:991) (1141:1141:1141)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1104:1104:1104)) + (PORT d[0] (678:678:678) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (612:612:612)) + (PORT datab (528:528:528) (620:620:620)) + (PORT datac (929:929:929) (1062:1062:1062)) + (PORT datad (774:774:774) (885:885:885)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1220:1220:1220)) + (PORT datab (677:677:677) (783:783:783)) + (PORT datac (992:992:992) (1144:1144:1144)) + (PORT datad (788:788:788) (904:904:904)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (849:849:849) (968:968:968)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2234:2234:2234) (2539:2539:2539)) + (PORT d[1] (2129:2129:2129) (2422:2422:2422)) + (PORT d[2] (1940:1940:1940) (2204:2204:2204)) + (PORT d[3] (2025:2025:2025) (2356:2356:2356)) + (PORT d[4] (2023:2023:2023) (2350:2350:2350)) + (PORT d[5] (1686:1686:1686) (1923:1923:1923)) + (PORT d[6] (1789:1789:1789) (2070:2070:2070)) + (PORT d[7] (2606:2606:2606) (2954:2954:2954)) + (PORT d[8] (1880:1880:1880) (2188:2188:2188)) + (PORT d[9] (2095:2095:2095) (2422:2422:2422)) + (PORT d[10] (1818:1818:1818) (2115:2115:2115)) + (PORT d[11] (1703:1703:1703) (1943:1943:1943)) + (PORT d[12] (1237:1237:1237) (1450:1450:1450)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1353:1353:1353) (1472:1472:1472)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (PORT d[0] (3034:3034:3034) (3341:3341:3341)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1064:1064:1064)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (762:762:762) (859:859:859)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2387:2387:2387) (2705:2705:2705)) + (PORT d[1] (2403:2403:2403) (2778:2778:2778)) + (PORT d[2] (2288:2288:2288) (2608:2608:2608)) + (PORT d[3] (2288:2288:2288) (2594:2594:2594)) + (PORT d[4] (2301:2301:2301) (2607:2607:2607)) + (PORT d[5] (2400:2400:2400) (2807:2807:2807)) + (PORT d[6] (2462:2462:2462) (2856:2856:2856)) + (PORT d[7] (2416:2416:2416) (2787:2787:2787)) + (PORT d[8] (2323:2323:2323) (2637:2637:2637)) + (PORT d[9] (2346:2346:2346) (2672:2672:2672)) + (PORT d[10] (2322:2322:2322) (2618:2618:2618)) + (PORT d[11] (2385:2385:2385) (2722:2722:2722)) + (PORT d[12] (2359:2359:2359) (2683:2683:2683)) + (PORT clk (1046:1046:1046) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (970:970:970)) + (PORT datab (624:624:624) (727:727:727)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (859:859:859) (965:965:965)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (759:759:759)) + (PORT datab (961:961:961) (1097:1097:1097)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (423:423:423)) + (PORT datab (1277:1277:1277) (1465:1465:1465)) + (PORT datac (735:735:735) (845:845:845)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (451:451:451) (529:529:529)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (540:540:540)) + (PORT datab (139:139:139) (180:180:180)) + (PORT datac (812:812:812) (951:951:951)) + (PORT datad (1180:1180:1180) (1330:1330:1330)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (753:753:753)) + (PORT datab (926:926:926) (1123:1123:1123)) + (PORT datac (802:802:802) (940:940:940)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (162:162:162)) + (PORT datab (145:145:145) (182:182:182)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (339:339:339) (406:406:406)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (797:797:797) (901:901:901)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (434:434:434) (461:461:461)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT datab (528:528:528) (629:629:629)) + (PORT datac (366:366:366) (446:446:446)) + (PORT datad (959:959:959) (1117:1117:1117)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (1061:1061:1061)) + (PORT datab (973:973:973) (1111:1111:1111)) + (PORT datac (900:900:900) (1020:1020:1020)) + (PORT datad (1322:1322:1322) (1510:1510:1510)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (1042:1042:1042)) + (PORT datab (1206:1206:1206) (1384:1384:1384)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (1224:1224:1224) (1391:1391:1391)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (115:115:115) (147:147:147)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (505:505:505) (580:580:580)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1308:1308:1308)) + (PORT datab (1209:1209:1209) (1387:1387:1387)) + (PORT datac (978:978:978) (1120:1120:1120)) + (PORT datad (1225:1225:1225) (1393:1393:1393)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (648:648:648) (742:742:742)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (573:573:573)) + (PORT datab (375:375:375) (446:446:446)) + (PORT datac (624:624:624) (711:711:711)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (1169:1169:1169)) + (PORT datac (532:532:532) (625:625:625)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~59) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datab (961:961:961) (1098:1098:1098)) + (PORT datac (939:939:939) (1120:1120:1120)) + (PORT datad (470:470:470) (544:544:544)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (596:596:596) (677:677:677)) + (PORT datad (321:321:321) (372:372:372)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (324:324:324)) + (PORT datab (811:811:811) (943:943:943)) + (PORT datac (681:681:681) (797:797:797)) + (PORT datad (318:318:318) (368:368:368)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (614:614:614)) + (PORT datab (134:134:134) (170:170:170)) + (PORT datac (851:851:851) (977:977:977)) + (PORT datad (356:356:356) (415:415:415)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (819:819:819)) + (PORT datab (960:960:960) (1106:1106:1106)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (694:694:694) (816:816:816)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (527:527:527)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (624:624:624) (723:723:723)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (643:643:643) (742:742:742)) + (PORT datac (631:631:631) (714:714:714)) + (PORT datad (368:368:368) (430:430:430)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (550:550:550) (633:633:633)) + (PORT datac (782:782:782) (882:882:882)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (704:704:704) (814:814:814)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (901:901:901) (887:887:887)) + (PORT ena (1100:1100:1100) (1207:1207:1207)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (549:549:549) (653:653:653)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (893:893:893)) + (PORT ena (778:778:778) (846:846:846)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (602:602:602) (703:703:703)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (899:899:899) (886:886:886)) + (PORT ena (851:851:851) (943:943:943)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (121:121:121) (166:166:166)) + (PORT datad (602:602:602) (703:703:703)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (359:359:359)) + (PORT datab (638:638:638) (747:747:747)) + (PORT datac (644:644:644) (744:744:744)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (824:824:824)) + (PORT datab (645:645:645) (743:743:743)) + (PORT datac (627:627:627) (719:719:719)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (687:687:687) (781:781:781)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (546:546:546) (634:634:634)) + (PORT d[1] (719:719:719) (824:824:824)) + (PORT d[2] (548:548:548) (643:643:643)) + (PORT d[3] (1580:1580:1580) (1835:1835:1835)) + (PORT d[4] (716:716:716) (825:825:825)) + (PORT d[5] (1210:1210:1210) (1396:1396:1396)) + (PORT d[6] (496:496:496) (574:574:574)) + (PORT d[7] (517:517:517) (595:595:595)) + (PORT d[8] (622:622:622) (718:718:718)) + (PORT d[9] (829:829:829) (963:963:963)) + (PORT d[10] (1137:1137:1137) (1332:1332:1332)) + (PORT d[11] (1323:1323:1323) (1505:1505:1505)) + (PORT d[12] (769:769:769) (911:911:911)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (957:957:957) (1042:1042:1042)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (1113:1113:1113) (1183:1183:1183)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (724:724:724) (832:832:832)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (366:366:366) (426:426:426)) + (PORT d[1] (724:724:724) (829:829:829)) + (PORT d[2] (755:755:755) (874:874:874)) + (PORT d[3] (1443:1443:1443) (1677:1677:1677)) + (PORT d[4] (723:723:723) (833:833:833)) + (PORT d[5] (1198:1198:1198) (1379:1379:1379)) + (PORT d[6] (1079:1079:1079) (1252:1252:1252)) + (PORT d[7] (667:667:667) (770:770:770)) + (PORT d[8] (766:766:766) (881:881:881)) + (PORT d[9] (841:841:841) (976:976:976)) + (PORT d[10] (1155:1155:1155) (1354:1354:1354)) + (PORT d[11] (554:554:554) (646:646:646)) + (PORT d[12] (786:786:786) (934:934:934)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (999:999:999) (1086:1086:1086)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (1187:1187:1187) (1264:1264:1264)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (602:602:602) (611:611:611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (683:683:683) (775:775:775)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (551:551:551) (637:637:637)) + (PORT d[1] (712:712:712) (808:808:808)) + (PORT d[2] (552:552:552) (640:640:640)) + (PORT d[3] (1410:1410:1410) (1645:1645:1645)) + (PORT d[4] (530:530:530) (616:616:616)) + (PORT d[5] (508:508:508) (589:589:589)) + (PORT d[6] (1059:1059:1059) (1225:1225:1225)) + (PORT d[7] (663:663:663) (764:764:764)) + (PORT d[8] (770:770:770) (884:884:884)) + (PORT d[9] (989:989:989) (1139:1139:1139)) + (PORT d[10] (1058:1058:1058) (1241:1241:1241)) + (PORT d[11] (697:697:697) (807:807:807)) + (PORT d[12] (752:752:752) (888:888:888)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (972:972:972) (1058:1058:1058)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1244:1244:1244) (1328:1328:1328)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (701:701:701) (807:807:807)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1674:1674:1674) (1901:1901:1901)) + (PORT d[1] (1554:1554:1554) (1761:1761:1761)) + (PORT d[2] (1503:1503:1503) (1715:1715:1715)) + (PORT d[3] (1113:1113:1113) (1261:1261:1261)) + (PORT d[4] (2027:2027:2027) (2350:2350:2350)) + (PORT d[5] (1741:1741:1741) (1974:1974:1974)) + (PORT d[6] (1682:1682:1682) (1958:1958:1958)) + (PORT d[7] (539:539:539) (620:620:620)) + (PORT d[8] (802:802:802) (916:916:916)) + (PORT d[9] (2642:2642:2642) (3042:3042:3042)) + (PORT d[10] (2431:2431:2431) (2833:2833:2833)) + (PORT d[11] (2135:2135:2135) (2444:2444:2444)) + (PORT d[12] (786:786:786) (894:894:894)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1104:1104:1104) (1197:1197:1197)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (750:750:750) (768:768:768)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (801:801:801)) + (PORT datab (826:826:826) (963:963:963)) + (PORT datac (861:861:861) (981:981:981)) + (PORT datad (726:726:726) (828:828:828)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (912:912:912)) + (PORT datab (739:739:739) (856:856:856)) + (PORT datac (1094:1094:1094) (1259:1259:1259)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (710:710:710) (826:826:826)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1550:1550:1550) (1767:1767:1767)) + (PORT d[1] (1262:1262:1262) (1462:1462:1462)) + (PORT d[2] (1594:1594:1594) (1826:1826:1826)) + (PORT d[3] (1626:1626:1626) (1872:1872:1872)) + (PORT d[4] (2150:2150:2150) (2501:2501:2501)) + (PORT d[5] (1697:1697:1697) (1934:1934:1934)) + (PORT d[6] (1867:1867:1867) (2148:2148:2148)) + (PORT d[7] (1570:1570:1570) (1805:1805:1805)) + (PORT d[8] (1322:1322:1322) (1523:1523:1523)) + (PORT d[9] (1534:1534:1534) (1774:1774:1774)) + (PORT d[10] (1173:1173:1173) (1385:1385:1385)) + (PORT d[11] (1371:1371:1371) (1574:1574:1574)) + (PORT d[12] (1265:1265:1265) (1487:1487:1487)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1176:1176:1176) (1283:1283:1283)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (2114:2114:2114) (2316:2316:2316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1074:1074:1074)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (663:663:663) (753:753:753)) + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2374:2374:2374) (2733:2733:2733)) + (PORT d[1] (2438:2438:2438) (2819:2819:2819)) + (PORT d[2] (2397:2397:2397) (2724:2724:2724)) + (PORT d[3] (2383:2383:2383) (2716:2716:2716)) + (PORT d[4] (2337:2337:2337) (2654:2654:2654)) + (PORT d[5] (2379:2379:2379) (2751:2751:2751)) + (PORT d[6] (2461:2461:2461) (2859:2859:2859)) + (PORT d[7] (2393:2393:2393) (2730:2730:2730)) + (PORT d[8] (2356:2356:2356) (2651:2651:2651)) + (PORT d[9] (2309:2309:2309) (2609:2609:2609)) + (PORT d[10] (2269:2269:2269) (2555:2555:2555)) + (PORT d[11] (2319:2319:2319) (2648:2648:2648)) + (PORT d[12] (2394:2394:2394) (2702:2702:2702)) + (PORT clk (1056:1056:1056) (1076:1076:1076)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1098:1098:1098) (1246:1246:1246)) + (PORT d[1] (853:853:853) (960:960:960)) + (PORT d[2] (801:801:801) (911:911:911)) + (PORT d[3] (2046:2046:2046) (2342:2342:2342)) + (PORT d[4] (1220:1220:1220) (1406:1406:1406)) + (PORT d[5] (1090:1090:1090) (1235:1235:1235)) + (PORT d[6] (1976:1976:1976) (2285:2285:2285)) + (PORT d[7] (959:959:959) (1091:1091:1091)) + (PORT d[8] (728:728:728) (837:837:837)) + (PORT d[9] (742:742:742) (858:858:858)) + (PORT d[10] (696:696:696) (794:794:794)) + (PORT d[11] (995:995:995) (1129:1129:1129)) + (PORT d[12] (897:897:897) (1034:1034:1034)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (800:800:800) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (735:735:735) (829:829:829)) + (PORT d[0] (889:889:889) (1006:1006:1006)) (PORT clk (1094:1094:1094) (1112:1112:1112)) ) ) @@ -33937,19 +35915,19 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1608:1608:1608) (1867:1867:1867)) - (PORT d[1] (1744:1744:1744) (1971:1971:1971)) - (PORT d[2] (1135:1135:1135) (1322:1322:1322)) - (PORT d[3] (1254:1254:1254) (1442:1442:1442)) - (PORT d[4] (1170:1170:1170) (1365:1365:1365)) - (PORT d[5] (1078:1078:1078) (1241:1241:1241)) - (PORT d[6] (1331:1331:1331) (1531:1531:1531)) - (PORT d[7] (1089:1089:1089) (1253:1253:1253)) - (PORT d[8] (1806:1806:1806) (2077:2077:2077)) - (PORT d[9] (1197:1197:1197) (1383:1383:1383)) - (PORT d[10] (2072:2072:2072) (2375:2375:2375)) - (PORT d[11] (1367:1367:1367) (1575:1575:1575)) - (PORT d[12] (1169:1169:1169) (1350:1350:1350)) + (PORT d[0] (1381:1381:1381) (1579:1579:1579)) + (PORT d[1] (1401:1401:1401) (1621:1621:1621)) + (PORT d[2] (1616:1616:1616) (1851:1851:1851)) + (PORT d[3] (1468:1468:1468) (1709:1709:1709)) + (PORT d[4] (2323:2323:2323) (2696:2696:2696)) + (PORT d[5] (1735:1735:1735) (1989:1989:1989)) + (PORT d[6] (1437:1437:1437) (1668:1668:1668)) + (PORT d[7] (1396:1396:1396) (1609:1609:1609)) + (PORT d[8] (1028:1028:1028) (1198:1198:1198)) + (PORT d[9] (1923:1923:1923) (2223:2223:2223)) + (PORT d[10] (1159:1159:1159) (1369:1369:1369)) + (PORT d[11] (1562:1562:1562) (1790:1790:1790)) + (PORT d[12] (1121:1121:1121) (1320:1320:1320)) (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) @@ -33962,7 +35940,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1028:1028:1028) (1112:1112:1112)) + (PORT d[0] (1126:1126:1126) (1231:1231:1231)) (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) @@ -33976,7 +35954,7 @@ (DELAY (ABSOLUTE (PORT clk (1094:1094:1094) (1112:1112:1112)) - (PORT d[0] (1982:1982:1982) (1835:1835:1835)) + (PORT d[0] (2095:2095:2095) (1949:1949:1949)) ) ) ) @@ -34039,7 +36017,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1042:1042:1042) (1187:1187:1187)) + (PORT d[0] (621:621:621) (696:696:696)) (PORT clk (1054:1054:1054) (1072:1072:1072)) ) ) @@ -34052,19 +36030,19 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2529:2529:2529) (2874:2874:2874)) - (PORT d[1] (2502:2502:2502) (2849:2849:2849)) - (PORT d[2] (2529:2529:2529) (2862:2862:2862)) - (PORT d[3] (2417:2417:2417) (2749:2749:2749)) - (PORT d[4] (2461:2461:2461) (2781:2781:2781)) - (PORT d[5] (2504:2504:2504) (2838:2838:2838)) - (PORT d[6] (2487:2487:2487) (2825:2825:2825)) - (PORT d[7] (2498:2498:2498) (2836:2836:2836)) - (PORT d[8] (2604:2604:2604) (2962:2962:2962)) - (PORT d[9] (2455:2455:2455) (2815:2815:2815)) - (PORT d[10] (2483:2483:2483) (2787:2787:2787)) - (PORT d[11] (2491:2491:2491) (2833:2833:2833)) - (PORT d[12] (2454:2454:2454) (2779:2779:2779)) + (PORT d[0] (2335:2335:2335) (2654:2654:2654)) + (PORT d[1] (2360:2360:2360) (2694:2694:2694)) + (PORT d[2] (2388:2388:2388) (2722:2722:2722)) + (PORT d[3] (2374:2374:2374) (2708:2708:2708)) + (PORT d[4] (2424:2424:2424) (2775:2775:2775)) + (PORT d[5] (2503:2503:2503) (2924:2924:2924)) + (PORT d[6] (2439:2439:2439) (2833:2833:2833)) + (PORT d[7] (2390:2390:2390) (2724:2724:2724)) + (PORT d[8] (2339:2339:2339) (2631:2631:2631)) + (PORT d[9] (2367:2367:2367) (2690:2690:2690)) + (PORT d[10] (2404:2404:2404) (2727:2727:2727)) + (PORT d[11] (2353:2353:2353) (2684:2684:2684)) + (PORT d[12] (2322:2322:2322) (2655:2655:2655)) (PORT clk (1051:1051:1051) (1071:1071:1071)) ) ) @@ -34135,403 +36113,25 @@ (HOLD d (posedge clk) (90:90:90)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (822:822:822) (935:935:935)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (760:760:760)) - (PORT datab (718:718:718) (826:826:826)) - (PORT datac (810:810:810) (926:926:926)) - (PORT datad (645:645:645) (739:739:739)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (673:673:673) (757:757:757)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1787:1787:1787) (2069:2069:2069)) - (PORT d[1] (1219:1219:1219) (1392:1392:1392)) - (PORT d[2] (948:948:948) (1104:1104:1104)) - (PORT d[3] (898:898:898) (1029:1029:1029)) - (PORT d[4] (1523:1523:1523) (1770:1770:1770)) - (PORT d[5] (900:900:900) (1036:1036:1036)) - (PORT d[6] (1152:1152:1152) (1324:1324:1324)) - (PORT d[7] (1063:1063:1063) (1230:1230:1230)) - (PORT d[8] (1977:1977:1977) (2270:2270:2270)) - (PORT d[9] (1004:1004:1004) (1160:1160:1160)) - (PORT d[10] (963:963:963) (1117:1117:1117)) - (PORT d[11] (909:909:909) (1063:1063:1063)) - (PORT d[12] (986:986:986) (1141:1141:1141)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (786:786:786) (847:847:847)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1104:1104:1104)) - (PORT d[0] (1631:1631:1631) (1777:1777:1777)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1041:1041:1041) (1061:1061:1061)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (847:847:847) (964:964:964)) - (PORT clk (1046:1046:1046) (1064:1064:1064)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2496:2496:2496) (2834:2834:2834)) - (PORT d[1] (2448:2448:2448) (2754:2754:2754)) - (PORT d[2] (2471:2471:2471) (2795:2795:2795)) - (PORT d[3] (2427:2427:2427) (2753:2753:2753)) - (PORT d[4] (2452:2452:2452) (2797:2797:2797)) - (PORT d[5] (2475:2475:2475) (2817:2817:2817)) - (PORT d[6] (2455:2455:2455) (2758:2758:2758)) - (PORT d[7] (2458:2458:2458) (2799:2799:2799)) - (PORT d[8] (2517:2517:2517) (2872:2872:2872)) - (PORT d[9] (2509:2509:2509) (2856:2856:2856)) - (PORT d[10] (2527:2527:2527) (2866:2866:2866)) - (PORT d[11] (2535:2535:2535) (2877:2877:2877)) - (PORT d[12] (2446:2446:2446) (2777:2777:2777)) - (PORT clk (1043:1043:1043) (1063:1063:1063)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1064:1064:1064)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1881:1881:1881) (2187:2187:2187)) - (PORT d[1] (1935:1935:1935) (2211:2211:2211)) - (PORT d[2] (826:826:826) (944:944:944)) - (PORT d[3] (2281:2281:2281) (2583:2583:2583)) - (PORT d[4] (1690:1690:1690) (1986:1986:1986)) - (PORT d[5] (2522:2522:2522) (2878:2878:2878)) - (PORT d[6] (1589:1589:1589) (1811:1811:1811)) - (PORT d[7] (981:981:981) (1113:1113:1113)) - (PORT d[8] (1117:1117:1117) (1267:1267:1267)) - (PORT d[9] (1234:1234:1234) (1409:1409:1409)) - (PORT d[10] (1319:1319:1319) (1498:1498:1498)) - (PORT d[11] (1776:1776:1776) (2078:2078:2078)) - (PORT d[12] (2525:2525:2525) (2857:2857:2857)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1110:1110:1110)) - (PORT d[0] (1113:1113:1113) (1229:1229:1229)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (624:624:624)) - (PORT datab (167:167:167) (219:219:219)) - (PORT datac (509:509:509) (571:571:571)) - (PORT datad (576:576:576) (655:655:655)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1111:1111:1111) (1295:1295:1295)) - (PORT d[1] (1500:1500:1500) (1693:1693:1693)) - (PORT d[2] (1390:1390:1390) (1602:1602:1602)) - (PORT d[3] (1723:1723:1723) (1945:1945:1945)) - (PORT d[4] (1283:1283:1283) (1479:1479:1479)) - (PORT d[5] (1752:1752:1752) (1994:1994:1994)) - (PORT d[6] (1635:1635:1635) (1858:1858:1858)) - (PORT d[7] (1803:1803:1803) (2055:2055:2055)) - (PORT d[8] (1353:1353:1353) (1548:1548:1548)) - (PORT d[9] (1781:1781:1781) (2030:2030:2030)) - (PORT d[10] (1287:1287:1287) (1461:1461:1461)) - (PORT d[11] (1418:1418:1418) (1651:1651:1651)) - (PORT d[12] (1894:1894:1894) (2151:2151:2151)) - (PORT clk (1105:1105:1105) (1122:1122:1122)) + (PORT d[0] (1314:1314:1314) (1490:1490:1490)) + (PORT d[1] (1212:1212:1212) (1373:1373:1373)) + (PORT d[2] (1127:1127:1127) (1284:1284:1284)) + (PORT d[3] (646:646:646) (737:737:737)) + (PORT d[4] (1487:1487:1487) (1709:1709:1709)) + (PORT d[5] (1370:1370:1370) (1547:1547:1547)) + (PORT d[6] (1833:1833:1833) (2129:2129:2129)) + (PORT d[7] (790:790:790) (901:901:901)) + (PORT d[8] (562:562:562) (648:648:648)) + (PORT d[9] (549:549:549) (637:637:637)) + (PORT d[10] (1016:1016:1016) (1157:1157:1157)) + (PORT d[11] (1299:1299:1299) (1469:1469:1469)) + (PORT d[12] (723:723:723) (840:840:840)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) (TIMINGCHECK @@ -34543,8 +36143,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1122:1122:1122)) - (PORT d[0] (1878:1878:1878) (1681:1681:1681)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1071:1071:1071) (974:974:974)) ) ) ) @@ -34553,7 +36153,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -34563,7 +36163,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1087:1087:1087) (1103:1103:1103)) + (PORT clk (1074:1074:1074) (1090:1090:1090)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -34577,7 +36177,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (627:627:627) (635:635:635)) + (PORT clk (614:614:614) (622:622:622)) ) ) ) @@ -34586,7 +36186,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) + (PORT clk (615:615:615) (623:623:623)) ) ) ) @@ -34595,7 +36195,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) + (PORT clk (615:615:615) (623:623:623)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -34605,54 +36205,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) + (PORT clk (615:615:615) (623:623:623)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~48) + (INSTANCE Selector10\~0) (DELAY (ABSOLUTE - (PORT dataa (584:584:584) (668:668:668)) - (PORT datab (826:826:826) (960:960:960)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (942:942:942) (1075:1075:1075)) - (IOPATH dataa combout (188:188:188) (203:203:203)) + (PORT dataa (511:511:511) (611:611:611)) + (PORT datab (527:527:527) (619:619:619)) + (PORT datac (828:828:828) (931:931:931)) + (PORT datad (906:906:906) (1019:1019:1019)) + (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (759:759:759)) - (PORT datab (168:168:168) (220:220:220)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (890:890:890)) - (PORT datab (1311:1311:1311) (1547:1547:1547)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -34660,14 +36228,1395 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~52) + (INSTANCE Selector10\~1) (DELAY (ABSOLUTE - (PORT dataa (703:703:703) (816:816:816)) - (PORT datab (331:331:331) (384:384:384)) - (PORT datac (456:456:456) (529:529:529)) - (PORT datad (167:167:167) (198:198:198)) + (PORT dataa (811:811:811) (933:933:933)) + (PORT datab (624:624:624) (727:727:727)) + (PORT datac (949:949:949) (1117:1117:1117)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (477:477:477) (502:502:502)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (151:151:151) (208:208:208)) + (PORT datad (143:143:143) (186:186:186)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1816:1816:1816) (2028:2028:2028)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT asdata (298:298:298) (339:339:339)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (121:121:121) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datac (120:120:120) (162:162:162)) + (PORT datad (120:120:120) (158:158:158)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (892:892:892)) + (PORT ena (962:962:962) (1071:1071:1071)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (210:210:210)) + (PORT datab (214:214:214) (266:266:266)) + (PORT datad (135:135:135) (180:180:180)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (892:892:892)) + (PORT ena (962:962:962) (1071:1071:1071)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (151:151:151) (207:207:207)) + (PORT datad (134:134:134) (178:178:178)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (892:892:892)) + (PORT ena (962:962:962) (1071:1071:1071)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (216:216:216)) + (PORT datab (155:155:155) (211:211:211)) + (PORT datad (135:135:135) (181:181:181)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (892:892:892)) + (PORT ena (962:962:962) (1071:1071:1071)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (216:216:216)) + (PORT datab (155:155:155) (211:211:211)) + (PORT datad (136:136:136) (181:181:181)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (205:205:205)) + (PORT datab (147:147:147) (202:202:202)) + (PORT datac (1899:1899:1899) (2149:2149:2149)) + (PORT datad (142:142:142) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (203:203:203)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (633:633:633) (735:735:735)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1981:1981:1981) (2219:2219:2219)) + (PORT clrn (890:890:890) (894:894:894)) + (PORT ena (614:614:614) (651:651:651)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (188:188:188) (233:233:233)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (PORT ena (614:614:614) (651:651:651)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (325:325:325) (382:382:382)) + (PORT clrn (890:890:890) (894:894:894)) + (PORT ena (614:614:614) (651:651:651)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (868:868:868) (987:987:987)) + (PORT clrn (891:891:891) (894:894:894)) + (PORT ena (631:631:631) (675:675:675)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (757:757:757) (850:850:850)) + (PORT clrn (889:889:889) (893:893:893)) + (PORT ena (500:500:500) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (556:556:556) (636:636:636)) + (PORT clrn (890:890:890) (894:894:894)) + (PORT ena (614:614:614) (651:651:651)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (905:905:905)) + (PORT asdata (580:580:580) (666:666:666)) + (PORT clrn (894:894:894) (900:900:900)) + (PORT ena (802:802:802) (876:876:876)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (467:467:467)) + (PORT datac (377:377:377) (469:469:469)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (968:968:968) (1089:1089:1089)) + (PORT clrn (889:889:889) (893:893:893)) + (PORT ena (500:500:500) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (223:223:223) (278:278:278)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (893:893:893)) + (PORT ena (500:500:500) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (487:487:487)) + (PORT datab (517:517:517) (622:622:622)) + (PORT datac (381:381:381) (465:465:465)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (513:513:513)) + (PORT datab (625:625:625) (730:730:730)) + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (375:375:375) (454:454:454)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (227:227:227)) + (PORT datab (230:230:230) (291:291:291)) + (PORT datad (766:766:766) (900:900:900)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datac (382:382:382) (466:466:466)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1920:1920:1920) (2171:2171:2171)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (628:628:628) (730:730:730)) + (PORT datad (319:319:319) (371:371:371)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (892:892:892)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (210:210:210)) + (PORT datab (392:392:392) (476:476:476)) + (PORT datac (152:152:152) (212:212:212)) + (PORT datad (769:769:769) (903:903:903)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (512:512:512)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (609:609:609) (708:708:708)) + (PORT datad (218:218:218) (270:270:270)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (487:487:487)) + (PORT datab (128:128:128) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (PORT ena (692:692:692) (775:775:775)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (374:374:374) (457:457:457)) + (PORT datac (153:153:153) (213:213:213)) + (PORT datad (138:138:138) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (516:516:516)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (341:341:341) (399:399:399)) + (PORT datad (385:385:385) (465:465:465)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (468:468:468)) + (PORT datab (383:383:383) (468:468:468)) + (PORT datad (343:343:343) (393:393:393)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (237:237:237)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datad (240:240:240) (301:301:301)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (PORT datab (374:374:374) (456:456:456)) + (PORT datac (151:151:151) (209:209:209)) + (PORT datad (138:138:138) (178:178:178)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (431:431:431)) + (PORT datab (386:386:386) (471:471:471)) + (PORT datac (176:176:176) (214:214:214)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (259:259:259) (326:326:326)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (964:964:964) (1112:1112:1112)) + (PORT datac (1279:1279:1279) (1505:1505:1505)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (464:464:464)) + (PORT datac (382:382:382) (474:474:474)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (226:226:226)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datad (240:240:240) (301:301:301)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (611:611:611)) + (PORT datab (557:557:557) (666:666:666)) + (PORT datac (348:348:348) (406:406:406)) + (PORT datad (500:500:500) (601:601:601)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (639:639:639)) + (PORT datab (710:710:710) (836:836:836)) + (PORT datad (370:370:370) (448:448:448)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (413:413:413)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datad (323:323:323) (377:377:377)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (262:262:262)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (2211:2211:2211) (2558:2558:2558)) + (PORT datad (1815:1815:1815) (2099:2099:2099)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT datac (373:373:373) (443:443:443)) + (PORT datad (213:213:213) (269:269:269)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (630:630:630)) + (PORT datab (537:537:537) (634:634:634)) + (PORT datac (515:515:515) (610:610:610)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (634:634:634)) + (PORT datac (518:518:518) (606:606:606)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (465:465:465)) + (PORT datac (515:515:515) (610:610:610)) + (PORT datad (213:213:213) (270:270:270)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (138:138:138)) + (PORT datab (405:405:405) (490:490:490)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (114:114:114) (135:135:135)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (238:238:238)) + (PORT datab (375:375:375) (457:457:457)) + (PORT datac (110:110:110) (136:136:136)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT datab (409:409:409) (500:500:500)) + (PORT datac (460:460:460) (529:529:529)) + (PORT datad (507:507:507) (619:619:619)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (637:637:637)) + (PORT datab (709:709:709) (835:835:835)) + (PORT datac (555:555:555) (667:667:667)) + (PORT datad (571:571:571) (676:676:676)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (224:224:224)) + (PORT datab (391:391:391) (476:476:476)) + (PORT datad (494:494:494) (577:577:577)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (406:406:406) (502:502:502)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT datab (424:424:424) (524:524:524)) + (PORT datac (364:364:364) (436:436:436)) + (PORT datad (769:769:769) (904:904:904)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (478:478:478)) + (PORT datac (458:458:458) (527:527:527)) + (PORT datad (398:398:398) (480:480:480)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (221:221:221)) + (PORT datab (340:340:340) (398:398:398)) + (PORT datad (325:325:325) (381:381:381)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (202:202:202)) + (PORT datab (469:469:469) (558:558:558)) + (PORT datac (158:158:158) (213:213:213)) + (PORT datad (385:385:385) (472:472:472)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (664:664:664)) + (PORT datab (396:396:396) (481:481:481)) + (PORT datac (579:579:579) (674:674:674)) + (PORT datad (391:391:391) (481:481:481)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -34676,13 +37625,329 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~53) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) (DELAY (ABSOLUTE - (PORT dataa (1235:1235:1235) (1412:1412:1412)) - (PORT datab (332:332:332) (385:385:385)) - (PORT datac (947:947:947) (1099:1099:1099)) - (PORT datad (102:102:102) (119:119:119)) + (PORT dataa (415:415:415) (511:511:511)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (500:500:500) (597:597:597)) + (PORT datac (372:372:372) (443:443:443)) + (PORT datad (412:412:412) (503:503:503)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (402:402:402)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (179:179:179)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datac (835:835:835) (976:976:976)) + (PORT datad (1151:1151:1151) (1317:1317:1317)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (704:704:704) (829:829:829)) + (PORT datad (367:367:367) (445:445:445)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (430:430:430)) + (PORT datab (202:202:202) (238:238:238)) + (PORT datac (316:316:316) (361:361:361)) + (PORT datad (515:515:515) (603:603:603)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (544:544:544) (649:649:649)) + (PORT datad (465:465:465) (530:530:530)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (510:510:510)) + (PORT datab (395:395:395) (480:480:480)) + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (392:392:392) (483:483:483)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (463:463:463) (551:551:551)) + (PORT datac (154:154:154) (209:209:209)) + (PORT datad (390:390:390) (478:478:478)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (240:240:240)) + (PORT datab (376:376:376) (459:459:459)) + (PORT datac (109:109:109) (135:135:135)) + (PORT datad (773:773:773) (907:907:907)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (670:670:670)) + (PORT datab (309:309:309) (356:356:356)) + (PORT datad (313:313:313) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (273:273:273)) + (PORT datab (1206:1206:1206) (1406:1406:1406)) + (PORT datac (1133:1133:1133) (1294:1294:1294)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (330:330:330) (385:385:385)) + (PORT datad (326:326:326) (381:381:381)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~17) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1081:1081:1081)) + (PORT datab (534:534:534) (642:642:642)) + (PORT datac (191:191:191) (226:226:226)) + (PORT datad (619:619:619) (706:706:706)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~18) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (994:994:994)) + (PORT datab (535:535:535) (643:643:643)) + (PORT datac (191:191:191) (225:225:225)) + (PORT datad (615:615:615) (701:701:701)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (948:948:948)) + (PORT datab (903:903:903) (1024:1024:1024)) + (PORT datac (780:780:780) (892:892:892)) + (PORT datad (893:893:893) (1045:1045:1045)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (547:547:547) (640:640:640)) + (PORT datac (166:166:166) (200:200:200)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (562:562:562)) + (PORT datab (1053:1053:1053) (1205:1205:1205)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (361:361:361) (439:439:439)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -34695,43 +37960,11 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (789:789:789) (897:897:897)) - (PORT datac (600:600:600) (692:692:692)) - (PORT datad (179:179:179) (202:202:202)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (715:715:715)) - (PORT datab (811:811:811) (957:957:957)) - (PORT datac (1187:1187:1187) (1391:1391:1391)) - (PORT datad (953:953:953) (1134:1134:1134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1078:1078:1078)) - (PORT datab (281:281:281) (328:328:328)) - (PORT datac (544:544:544) (614:614:614)) - (PORT datad (620:620:620) (710:710:710)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (761:761:761) (866:866:866)) + (PORT datab (177:177:177) (215:215:215)) + (PORT datac (811:811:811) (950:950:950)) + (PORT datad (124:124:124) (155:155:155)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -34743,9 +37976,9 @@ (INSTANCE z80_\|data_pins_\|dout\[2\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) + (PORT clk (912:912:912) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (598:598:598) (635:635:635)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -34754,85 +37987,45 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (718:718:718)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datac (442:442:442) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datac (599:599:599) (690:690:690)) - (PORT datad (120:120:120) (144:144:144)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|bus_control_\|db\[2\]\~13) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (264:264:264)) - (PORT datab (134:134:134) (169:169:169)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (116:116:116) (140:140:140)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (329:329:329) (380:380:380)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (726:726:726)) - (PORT datab (1638:1638:1638) (1881:1881:1881)) - (PORT datac (782:782:782) (920:920:920)) - (PORT datad (451:451:451) (535:535:535)) + (PORT dataa (796:796:796) (925:925:925)) + (PORT datac (130:130:130) (165:165:165)) + (PORT datad (596:596:596) (704:704:704)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (608:608:608)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (208:208:208) (248:248:248)) + (PORT datad (134:134:134) (163:163:163)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|ir_\|opcode\[2\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (910:910:910)) - (PORT ena (1203:1203:1203) (1324:1324:1324)) + (PORT clrn (902:902:902) (888:888:888)) + (PORT ena (996:996:996) (1107:1107:1107)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -34844,13 +38037,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (INSTANCE z80_\|pla_decode_\|Equal8\~0) (DELAY (ABSOLUTE - (PORT dataa (1038:1038:1038) (1217:1217:1217)) - (PORT datab (957:957:957) (1143:1143:1143)) - (PORT datac (969:969:969) (1121:1121:1121)) - (PORT datad (475:475:475) (551:551:551)) + (PORT dataa (710:710:710) (849:849:849)) + (PORT datab (1013:1013:1013) (1218:1218:1218)) + (PORT datac (698:698:698) (821:821:821)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (699:699:699)) + (PORT datab (769:769:769) (891:891:891)) + (PORT datac (942:942:942) (1123:1123:1123)) + (PORT datad (1020:1020:1020) (1185:1185:1185)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (525:525:525)) + (PORT datab (456:456:456) (535:535:535)) + (PORT datac (626:626:626) (726:726:726)) + (PORT datad (324:324:324) (378:378:378)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -34860,47 +38083,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (INSTANCE z80_\|execute_\|ctl_ir_we\~17) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (417:417:417)) - (PORT datab (439:439:439) (510:510:510)) - (PORT datac (180:180:180) (210:210:210)) - (PORT datad (328:328:328) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (594:594:594)) - (PORT datab (663:663:663) (758:758:758)) - (PORT datac (641:641:641) (735:735:735)) - (PORT datad (646:646:646) (739:739:739)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (216:216:216)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (464:464:464) (530:530:530)) - (PORT datad (114:114:114) (136:136:136)) + (PORT dataa (642:642:642) (747:747:747)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datac (345:345:345) (409:409:409)) + (PORT datad (652:652:652) (748:748:748)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (1073:1073:1073) (1180:1180:1180)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datac (499:499:499) (593:593:593)) + (PORT datad (1055:1055:1055) (1255:1255:1255)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -34908,13 +38129,530 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (INSTANCE z80_\|pla_decode_\|Equal2\~3) (DELAY (ABSOLUTE - (PORT dataa (457:457:457) (535:535:535)) - (PORT datac (442:442:442) (510:510:510)) - (PORT datad (444:444:444) (504:504:504)) + (PORT dataa (453:453:453) (526:526:526)) + (PORT datab (144:144:144) (187:187:187)) + (PORT datac (386:386:386) (472:472:472)) + (PORT datad (137:137:137) (167:167:167)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (855:855:855)) + (PORT datab (341:341:341) (396:396:396)) + (PORT datac (645:645:645) (742:742:742)) + (PORT datad (711:711:711) (829:829:829)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (892:892:892) (1057:1057:1057)) + (PORT datac (484:484:484) (567:567:567)) + (PORT datad (1118:1118:1118) (1296:1296:1296)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT datab (400:400:400) (496:496:496)) + (PORT datad (398:398:398) (487:487:487)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (497:497:497)) + (PORT datab (144:144:144) (186:186:186)) + (PORT datac (450:450:450) (522:522:522)) + (PORT datad (138:138:138) (168:168:168)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (623:623:623)) + (PORT datab (357:357:357) (426:426:426)) + (PORT datad (831:831:831) (969:969:969)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (411:411:411)) + (PORT datab (305:305:305) (357:357:357)) + (PORT datac (490:490:490) (556:556:556)) + (PORT datad (437:437:437) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (880:880:880) (1053:1053:1053)) + (PORT datac (374:374:374) (450:450:450)) + (PORT datad (620:620:620) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (726:726:726)) + (PORT datab (479:479:479) (558:558:558)) + (PORT datac (470:470:470) (560:560:560)) + (PORT datad (617:617:617) (713:713:713)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (545:545:545)) + (PORT datab (174:174:174) (212:212:212)) + (PORT datac (358:358:358) (431:431:431)) + (PORT datad (174:174:174) (206:206:206)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (300:300:300) (348:348:348)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (184:184:184)) + (PORT datab (500:500:500) (583:583:583)) + (PORT datac (776:776:776) (895:895:895)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (550:550:550) (632:632:632)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (570:570:570) (661:661:661)) + (PORT d[1] (588:588:588) (681:681:681)) + (PORT d[2] (721:721:721) (835:835:835)) + (PORT d[3] (1263:1263:1263) (1475:1475:1475)) + (PORT d[4] (555:555:555) (644:644:644)) + (PORT d[5] (1024:1024:1024) (1182:1182:1182)) + (PORT d[6] (901:901:901) (1050:1050:1050)) + (PORT d[7] (683:683:683) (788:788:788)) + (PORT d[8] (777:777:777) (892:892:892)) + (PORT d[9] (807:807:807) (930:930:930)) + (PORT d[10] (964:964:964) (1136:1136:1136)) + (PORT d[11] (411:411:411) (486:486:486)) + (PORT d[12] (764:764:764) (903:903:903)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (841:841:841) (908:908:908)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1021:1021:1021) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (377:377:377) (435:435:435)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (742:742:742) (853:853:853)) + (PORT d[1] (1269:1269:1269) (1470:1470:1470)) + (PORT d[2] (2179:2179:2179) (2491:2491:2491)) + (PORT d[3] (1098:1098:1098) (1280:1280:1280)) + (PORT d[4] (737:737:737) (853:853:853)) + (PORT d[5] (1010:1010:1010) (1168:1168:1168)) + (PORT d[6] (739:739:739) (861:861:861)) + (PORT d[7] (868:868:868) (999:999:999)) + (PORT d[8] (2060:2060:2060) (2363:2363:2363)) + (PORT d[9] (1171:1171:1171) (1349:1349:1349)) + (PORT d[10] (1029:1029:1029) (1201:1201:1201)) + (PORT d[11] (559:559:559) (646:646:646)) + (PORT d[12] (947:947:947) (1110:1110:1110)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (801:801:801) (867:867:867)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (968:968:968) (1022:1022:1022)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (1404:1404:1404) (1612:1612:1612)) + (PORT datac (364:364:364) (446:446:446)) + (PORT datad (890:890:890) (1035:1035:1035)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -34922,88 +38660,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) + (INSTANCE D\[6\]\~43) (DELAY (ABSOLUTE - (PORT dataa (498:498:498) (576:576:576)) - (PORT datab (482:482:482) (564:564:564)) - (PORT datac (431:431:431) (494:494:494)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (372:372:372)) - (PORT datab (641:641:641) (739:739:739)) - (PORT datac (479:479:479) (569:569:569)) - (PORT datad (307:307:307) (359:359:359)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (728:728:728) (835:835:835)) - (PORT datac (339:339:339) (392:392:392)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (538:538:538)) - (PORT datab (364:364:364) (432:432:432)) - (PORT datac (444:444:444) (514:514:514)) - (PORT datad (445:445:445) (506:506:506)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (524:524:524)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (452:452:452) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (584:584:584)) - (PORT datab (343:343:343) (402:402:402)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (314:314:314) (365:365:365)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (802:802:802) (924:924:924)) + (PORT datab (735:735:735) (839:839:839)) + (PORT datac (350:350:350) (401:401:401)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (158:158:158) (173:173:173)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -35012,14 +38676,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (INSTANCE D\[6\]\~44) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (714:714:714)) - (PORT datab (133:133:133) (168:168:168)) - (PORT datad (659:659:659) (767:767:767)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (517:517:517) (597:597:597)) + (PORT datab (684:684:684) (806:806:806)) + (PORT datac (504:504:504) (594:594:594)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -35029,8 +38695,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (721:721:721) (836:836:836)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (557:557:557) (642:642:642)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) (TIMINGCHECK @@ -35042,20 +38708,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1394:1394:1394) (1654:1654:1654)) - (PORT d[1] (1497:1497:1497) (1696:1696:1696)) - (PORT d[2] (714:714:714) (817:817:817)) - (PORT d[3] (719:719:719) (824:824:824)) - (PORT d[4] (1134:1134:1134) (1301:1301:1301)) - (PORT d[5] (710:710:710) (820:820:820)) - (PORT d[6] (819:819:819) (938:938:938)) - (PORT d[7] (1361:1361:1361) (1563:1563:1563)) - (PORT d[8] (1402:1402:1402) (1657:1657:1657)) - (PORT d[9] (440:440:440) (517:517:517)) - (PORT d[10] (994:994:994) (1138:1138:1138)) - (PORT d[11] (649:649:649) (747:747:747)) - (PORT d[12] (413:413:413) (480:480:480)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) + (PORT d[0] (735:735:735) (846:846:846)) + (PORT d[1] (1281:1281:1281) (1484:1484:1484)) + (PORT d[2] (721:721:721) (831:831:831)) + (PORT d[3] (1254:1254:1254) (1457:1457:1457)) + (PORT d[4] (724:724:724) (839:839:839)) + (PORT d[5] (687:687:687) (798:798:798)) + (PORT d[6] (867:867:867) (1005:1005:1005)) + (PORT d[7] (848:848:848) (972:972:972)) + (PORT d[8] (2067:2067:2067) (2370:2370:2370)) + (PORT d[9] (1177:1177:1177) (1356:1356:1356)) + (PORT d[10] (934:934:934) (1096:1096:1096)) + (PORT d[11] (541:541:541) (625:625:625)) + (PORT d[12] (772:772:772) (912:912:912)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) (TIMINGCHECK @@ -35067,8 +38733,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1099:1099:1099)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) + (PORT d[0] (785:785:785) (839:839:839)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) (TIMINGCHECK @@ -35080,8 +38746,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (999:999:999) (1065:1065:1065)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1084:1084:1084) (1155:1155:1155)) ) ) ) @@ -35090,7 +38756,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -35100,7 +38766,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -35110,7 +38776,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -35120,7 +38786,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -35130,7 +38796,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) + (PORT clk (1072:1072:1072) (1088:1088:1088)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -35144,7 +38810,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) + (PORT clk (612:612:612) (620:620:620)) ) ) ) @@ -35153,7 +38819,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) + (PORT clk (613:613:613) (621:621:621)) ) ) ) @@ -35162,7 +38828,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) + (PORT clk (613:613:613) (621:621:621)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -35172,7 +38838,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) + (PORT clk (613:613:613) (621:621:621)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -35182,7 +38848,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (536:536:536) (602:602:602)) + (PORT d[0] (545:545:545) (624:624:624)) (PORT clk (1091:1091:1091) (1108:1108:1108)) ) ) @@ -35195,19 +38861,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1429:1429:1429) (1672:1672:1672)) - (PORT d[1] (704:704:704) (809:809:809)) - (PORT d[2] (954:954:954) (1113:1113:1113)) - (PORT d[3] (922:922:922) (1066:1066:1066)) - (PORT d[4] (1719:1719:1719) (1992:1992:1992)) - (PORT d[5] (707:707:707) (817:817:817)) - (PORT d[6] (884:884:884) (1026:1026:1026)) - (PORT d[7] (723:723:723) (837:837:837)) - (PORT d[8] (701:701:701) (818:818:818)) - (PORT d[9] (634:634:634) (737:737:737)) - (PORT d[10] (622:622:622) (725:725:725)) - (PORT d[11] (1272:1272:1272) (1486:1486:1486)) - (PORT d[12] (635:635:635) (743:743:743)) + (PORT d[0] (733:733:733) (846:846:846)) + (PORT d[1] (1297:1297:1297) (1504:1504:1504)) + (PORT d[2] (721:721:721) (837:837:837)) + (PORT d[3] (1391:1391:1391) (1622:1622:1622)) + (PORT d[4] (707:707:707) (819:819:819)) + (PORT d[5] (1036:1036:1036) (1201:1201:1201)) + (PORT d[6] (887:887:887) (1029:1029:1029)) + (PORT d[7] (671:671:671) (769:769:769)) + (PORT d[8] (2068:2068:2068) (2371:2371:2371)) + (PORT d[9] (828:828:828) (957:957:957)) + (PORT d[10] (948:948:948) (1115:1115:1115)) + (PORT d[11] (538:538:538) (623:623:623)) + (PORT d[12] (771:771:771) (911:911:911)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -35220,7 +38886,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (674:674:674) (711:711:711)) + (PORT d[0] (661:661:661) (707:707:707)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -35234,7 +38900,7 @@ (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1298:1298:1298) (1395:1395:1395)) + (PORT d[0] (1107:1107:1107) (1180:1180:1180)) ) ) ) @@ -35330,779 +38996,55 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (714:714:714) (831:831:831)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1565:1565:1565) (1849:1849:1849)) - (PORT d[1] (1665:1665:1665) (1885:1885:1885)) - (PORT d[2] (698:698:698) (799:799:799)) - (PORT d[3] (547:547:547) (641:641:641)) - (PORT d[4] (1165:1165:1165) (1328:1328:1328)) - (PORT d[5] (530:530:530) (613:613:613)) - (PORT d[6] (787:787:787) (900:900:900)) - (PORT d[7] (1536:1536:1536) (1760:1760:1760)) - (PORT d[8] (1422:1422:1422) (1679:1679:1679)) - (PORT d[9] (419:419:419) (488:488:488)) - (PORT d[10] (421:421:421) (496:496:496)) - (PORT d[11] (1641:1641:1641) (1917:1917:1917)) - (PORT d[12] (392:392:392) (458:458:458)) - (PORT clk (1080:1080:1080) (1098:1098:1098)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (687:687:687) (733:733:733)) - (PORT clk (1080:1080:1080) (1098:1098:1098)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1082:1082:1082) (1100:1100:1100)) - (PORT d[0] (783:783:783) (812:812:812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (602:602:602) (611:611:611)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (366:366:366) (419:419:419)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1562:1562:1562) (1830:1830:1830)) - (PORT d[1] (738:738:738) (848:848:848)) - (PORT d[2] (946:946:946) (1107:1107:1107)) - (PORT d[3] (892:892:892) (1029:1029:1029)) - (PORT d[4] (1710:1710:1710) (1975:1975:1975)) - (PORT d[5] (716:716:716) (826:826:826)) - (PORT d[6] (858:858:858) (995:995:995)) - (PORT d[7] (903:903:903) (1049:1049:1049)) - (PORT d[8] (879:879:879) (1017:1017:1017)) - (PORT d[9] (808:808:808) (935:935:935)) - (PORT d[10] (773:773:773) (895:895:895)) - (PORT d[11] (1077:1077:1077) (1257:1257:1257)) - (PORT d[12] (807:807:807) (938:938:938)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (695:695:695) (741:741:741)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1481:1481:1481) (1627:1627:1627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~103) + (INSTANCE D\[6\]\~42) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (913:913:913)) - (PORT datab (686:686:686) (788:788:788)) - (PORT datad (783:783:783) (893:893:893)) - (IOPATH dataa combout (195:195:195) (203:203:203)) + (PORT dataa (520:520:520) (597:597:597)) + (PORT datab (533:533:533) (608:608:608)) + (PORT datad (791:791:791) (923:923:923)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~104) + (INSTANCE D\[6\]\~45) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (982:982:982)) - (PORT datab (1036:1036:1036) (1216:1216:1216)) - (PORT datac (805:805:805) (919:919:919)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT dataa (931:931:931) (1102:1102:1102)) + (PORT datab (1096:1096:1096) (1253:1253:1253)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (165:165:165) (192:192:192)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (711:711:711) (800:800:800)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1615:1615:1615) (1876:1876:1876)) - (PORT d[1] (1067:1067:1067) (1221:1221:1221)) - (PORT d[2] (1116:1116:1116) (1300:1300:1300)) - (PORT d[3] (1254:1254:1254) (1439:1439:1439)) - (PORT d[4] (1344:1344:1344) (1567:1567:1567)) - (PORT d[5] (1077:1077:1077) (1240:1240:1240)) - (PORT d[6] (1333:1333:1333) (1537:1537:1537)) - (PORT d[7] (1260:1260:1260) (1457:1457:1457)) - (PORT d[8] (1796:1796:1796) (2065:2065:2065)) - (PORT d[9] (1038:1038:1038) (1201:1201:1201)) - (PORT d[10] (964:964:964) (1114:1114:1114)) - (PORT d[11] (1379:1379:1379) (1587:1587:1587)) - (PORT d[12] (1429:1429:1429) (1641:1641:1641)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1017:1017:1017) (1099:1099:1099)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1978:1978:1978) (1828:1828:1828)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1065:1065:1065)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1053:1053:1053) (1202:1202:1202)) - (PORT clk (1051:1051:1051) (1068:1068:1068)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2502:2502:2502) (2839:2839:2839)) - (PORT d[1] (2506:2506:2506) (2855:2855:2855)) - (PORT d[2] (2541:2541:2541) (2875:2875:2875)) - (PORT d[3] (2395:2395:2395) (2721:2721:2721)) - (PORT d[4] (2433:2433:2433) (2757:2757:2757)) - (PORT d[5] (2494:2494:2494) (2837:2837:2837)) - (PORT d[6] (2451:2451:2451) (2781:2781:2781)) - (PORT d[7] (2498:2498:2498) (2835:2835:2835)) - (PORT d[8] (2605:2605:2605) (2960:2960:2960)) - (PORT d[9] (2461:2461:2461) (2814:2814:2814)) - (PORT d[10] (2482:2482:2482) (2811:2811:2811)) - (PORT d[11] (2504:2504:2504) (2853:2853:2853)) - (PORT d[12] (2464:2464:2464) (2791:2791:2791)) - (PORT clk (1048:1048:1048) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1068:1068:1068)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1066:1066:1066)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (669:669:669) (765:765:765)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1616:1616:1616) (1877:1877:1877)) - (PORT d[1] (1062:1062:1062) (1215:1215:1215)) - (PORT d[2] (1317:1317:1317) (1534:1534:1534)) - (PORT d[3] (1261:1261:1261) (1445:1445:1445)) - (PORT d[4] (1345:1345:1345) (1566:1566:1566)) - (PORT d[5] (1070:1070:1070) (1232:1232:1232)) - (PORT d[6] (1065:1065:1065) (1235:1235:1235)) - (PORT d[7] (1070:1070:1070) (1230:1230:1230)) - (PORT d[8] (1789:1789:1789) (2052:2052:2052)) - (PORT d[9] (1027:1027:1027) (1187:1187:1187)) - (PORT d[10] (2260:2260:2260) (2590:2590:2590)) - (PORT d[11] (1385:1385:1385) (1593:1593:1593)) - (PORT d[12] (995:995:995) (1154:1154:1154)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (946:946:946) (1018:1018:1018)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (PORT d[0] (1654:1654:1654) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1043:1043:1043) (1063:1063:1063)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1034:1034:1034) (1178:1178:1178)) - (PORT clk (1048:1048:1048) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2498:2498:2498) (2836:2836:2836)) - (PORT d[1] (2472:2472:2472) (2812:2812:2812)) - (PORT d[2] (2474:2474:2474) (2809:2809:2809)) - (PORT d[3] (2399:2399:2399) (2725:2725:2725)) - (PORT d[4] (2442:2442:2442) (2759:2759:2759)) - (PORT d[5] (2503:2503:2503) (2850:2850:2850)) - (PORT d[6] (2484:2484:2484) (2825:2825:2825)) - (PORT d[7] (2478:2478:2478) (2809:2809:2809)) - (PORT d[8] (2621:2621:2621) (2980:2980:2980)) - (PORT d[9] (2503:2503:2503) (2852:2852:2852)) - (PORT d[10] (2504:2504:2504) (2845:2845:2845)) - (PORT d[11] (2543:2543:2543) (2885:2885:2885)) - (PORT d[12] (2459:2459:2459) (2789:2789:2789)) - (PORT clk (1045:1045:1045) (1065:1065:1065)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1431:1431:1431) (1666:1666:1666)) - (PORT d[1] (1553:1553:1553) (1763:1763:1763)) - (PORT d[2] (1311:1311:1311) (1527:1527:1527)) - (PORT d[3] (1232:1232:1232) (1407:1407:1407)) - (PORT d[4] (983:983:983) (1152:1152:1152)) - (PORT d[5] (1245:1245:1245) (1430:1430:1430)) - (PORT d[6] (1395:1395:1395) (1604:1604:1604)) - (PORT d[7] (1964:1964:1964) (2241:2241:2241)) - (PORT d[8] (1625:1625:1625) (1868:1868:1868)) - (PORT d[9] (1231:1231:1231) (1423:1423:1423)) - (PORT d[10] (1136:1136:1136) (1305:1305:1305)) - (PORT d[11] (1204:1204:1204) (1396:1396:1396)) - (PORT d[12] (1338:1338:1338) (1537:1537:1537)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1556:1556:1556) (1776:1776:1776)) + (PORT d[1] (1361:1361:1361) (1572:1572:1572)) + (PORT d[2] (1437:1437:1437) (1651:1651:1651)) + (PORT d[3] (1608:1608:1608) (1844:1844:1844)) + (PORT d[4] (2148:2148:2148) (2498:2498:2498)) + (PORT d[5] (1700:1700:1700) (1940:1940:1940)) + (PORT d[6] (1616:1616:1616) (1869:1869:1869)) + (PORT d[7] (1558:1558:1558) (1788:1788:1788)) + (PORT d[8] (1315:1315:1315) (1515:1515:1515)) + (PORT d[9] (1534:1534:1534) (1769:1769:1769)) + (PORT d[10] (1164:1164:1164) (1371:1371:1371)) + (PORT d[11] (1344:1344:1344) (1535:1535:1535)) + (PORT d[12] (1107:1107:1107) (1303:1303:1303)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) ) ) (TIMINGCHECK @@ -36114,8 +39056,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (PORT d[0] (1502:1502:1502) (1694:1694:1694)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (PORT d[0] (1617:1617:1617) (1802:1802:1802)) ) ) ) @@ -36124,7 +39066,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1098:1098:1098) (1116:1116:1116)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -36134,7 +39076,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1079:1079:1079) (1096:1096:1096)) + (PORT clk (1081:1081:1081) (1097:1097:1097)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -36148,7 +39090,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (628:628:628)) + (PORT clk (621:621:621) (629:629:629)) ) ) ) @@ -36157,7 +39099,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) + (PORT clk (622:622:622) (630:630:630)) ) ) ) @@ -36166,7 +39108,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) + (PORT clk (622:622:622) (630:630:630)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -36176,24 +39118,209 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) + (PORT clk (622:622:622) (630:630:630)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (746:746:746)) - (PORT datab (168:168:168) (222:222:222)) - (PORT datac (641:641:641) (738:738:738)) - (PORT datad (835:835:835) (939:939:939)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT d[0] (863:863:863) (981:981:981)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1399:1399:1399) (1600:1600:1600)) + (PORT d[1] (1391:1391:1391) (1605:1605:1605)) + (PORT d[2] (1783:1783:1783) (2042:2042:2042)) + (PORT d[3] (1614:1614:1614) (1875:1875:1875)) + (PORT d[4] (2324:2324:2324) (2696:2696:2696)) + (PORT d[5] (1345:1345:1345) (1542:1542:1542)) + (PORT d[6] (1428:1428:1428) (1660:1660:1660)) + (PORT d[7] (1376:1376:1376) (1582:1582:1582)) + (PORT d[8] (1508:1508:1508) (1736:1736:1736)) + (PORT d[9] (1932:1932:1932) (2233:2233:2233)) + (PORT d[10] (1159:1159:1159) (1367:1367:1367)) + (PORT d[11] (1576:1576:1576) (1807:1807:1807)) + (PORT d[12] (1081:1081:1081) (1280:1280:1280)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1087:1087:1087)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1922:1922:1922) (2094:2094:2094)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1065:1065:1065)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (820:820:820) (928:928:928)) + (PORT clk (1051:1051:1051) (1068:1068:1068)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2333:2333:2333) (2654:2654:2654)) + (PORT d[1] (2372:2372:2372) (2721:2721:2721)) + (PORT d[2] (2324:2324:2324) (2635:2635:2635)) + (PORT d[3] (2362:2362:2362) (2695:2695:2695)) + (PORT d[4] (2427:2427:2427) (2782:2782:2782)) + (PORT d[5] (2510:2510:2510) (2928:2928:2928)) + (PORT d[6] (2497:2497:2497) (2861:2861:2861)) + (PORT d[7] (2412:2412:2412) (2761:2761:2761)) + (PORT d[8] (2293:2293:2293) (2617:2617:2617)) + (PORT d[9] (2259:2259:2259) (2556:2556:2556)) + (PORT d[10] (2304:2304:2304) (2612:2612:2612)) + (PORT d[11] (2349:2349:2349) (2684:2684:2684)) + (PORT d[12] (2408:2408:2408) (2725:2725:2725)) + (PORT clk (1048:1048:1048) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1068:1068:1068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) @@ -36202,20 +39329,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1119:1119:1119) (1314:1314:1314)) - (PORT d[1] (1753:1753:1753) (2005:2005:2005)) - (PORT d[2] (1295:1295:1295) (1486:1486:1486)) - (PORT d[3] (2116:2116:2116) (2394:2394:2394)) - (PORT d[4] (1504:1504:1504) (1765:1765:1765)) - (PORT d[5] (2354:2354:2354) (2691:2691:2691)) - (PORT d[6] (1569:1569:1569) (1784:1784:1784)) - (PORT d[7] (2124:2124:2124) (2421:2421:2421)) - (PORT d[8] (1150:1150:1150) (1308:1308:1308)) - (PORT d[9] (1244:1244:1244) (1420:1420:1420)) - (PORT d[10] (1352:1352:1352) (1542:1542:1542)) - (PORT d[11] (1599:1599:1599) (1874:1874:1874)) - (PORT d[12] (2275:2275:2275) (2585:2585:2585)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (716:716:716) (827:827:827)) + (PORT d[1] (1153:1153:1153) (1316:1316:1316)) + (PORT d[2] (760:760:760) (873:873:873)) + (PORT d[3] (1460:1460:1460) (1689:1689:1689)) + (PORT d[4] (724:724:724) (834:834:834)) + (PORT d[5] (503:503:503) (583:583:583)) + (PORT d[6] (517:517:517) (606:606:606)) + (PORT d[7] (668:668:668) (766:766:766)) + (PORT d[8] (779:779:779) (896:896:896)) + (PORT d[9] (671:671:671) (775:775:775)) + (PORT d[10] (1155:1155:1155) (1354:1354:1354)) + (PORT d[11] (1296:1296:1296) (1474:1474:1474)) + (PORT d[12] (795:795:795) (944:944:944)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) ) ) (TIMINGCHECK @@ -36227,8 +39354,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1424:1424:1424) (1283:1283:1283)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (838:838:838) (756:756:756)) ) ) ) @@ -36237,7 +39364,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT clk (1083:1083:1083) (1101:1101:1101)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -36245,5454 +39372,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1073:1073:1073) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (849:849:849)) - (PORT datab (687:687:687) (790:790:790)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (584:584:584) (662:662:662)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (765:765:765)) - (PORT datab (171:171:171) (224:224:224)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (889:889:889)) - (PORT datab (1311:1311:1311) (1546:1546:1546)) - (PORT datac (91:91:91) (114:114:114)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~99) - (DELAY - (ABSOLUTE - (PORT datab (671:671:671) (798:798:798)) - (PORT datac (1429:1429:1429) (1677:1677:1677)) - (PORT datad (847:847:847) (982:982:982)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (1010:1010:1010)) - (PORT datab (227:227:227) (273:273:273)) - (PORT datac (308:308:308) (351:351:351)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (1257:1257:1257) (1443:1443:1443)) - (PORT datab (228:228:228) (273:273:273)) - (PORT datac (680:680:680) (804:804:804)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1165:1165:1165)) - (PORT datab (226:226:226) (266:266:266)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (621:621:621) (711:711:711)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (133:133:133) (168:168:168)) - (PORT datac (303:303:303) (360:360:360)) - (PORT datad (115:115:115) (139:139:139)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (356:356:356) (392:392:392)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1045:1045:1045) (1140:1140:1140)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (501:501:501)) - (PORT datac (1064:1064:1064) (1243:1243:1243)) - (PORT datad (944:944:944) (1091:1091:1091)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1146:1146:1146)) - (PORT datab (955:955:955) (1140:1140:1140)) - (PORT datac (589:589:589) (696:696:696)) - (PORT datad (1016:1016:1016) (1186:1186:1186)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (363:363:363)) - (PORT datab (142:142:142) (190:190:190)) - (PORT datac (326:326:326) (392:392:392)) - (PORT datad (625:625:625) (722:722:722)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (1068:1068:1068)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (192:192:192) (245:245:245)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (426:426:426) (512:512:512)) - (PORT datad (176:176:176) (234:234:234)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (632:632:632) (690:690:690)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (529:529:529)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (630:630:630) (727:727:727)) - (PORT datad (872:872:872) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (915:915:915)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (1053:1053:1053) (1195:1195:1195)) - (PORT clrn (925:925:925) (906:906:906)) - (PORT ena (508:508:508) (552:552:552)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (262:262:262)) - (PORT datab (160:160:160) (213:213:213)) - (PORT datad (138:138:138) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1516:1516:1516)) - (PORT datab (676:676:676) (786:786:786)) - (PORT datac (637:637:637) (738:738:738)) - (PORT datad (668:668:668) (759:759:759)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (138:138:138)) - (PORT datab (373:373:373) (438:438:438)) - (PORT datad (480:480:480) (559:559:559)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (925:925:925) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (980:980:980)) - (PORT datab (332:332:332) (383:383:383)) - (PORT datac (687:687:687) (790:790:790)) - (PORT datad (328:328:328) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (153:153:153)) - (PORT datab (113:113:113) (141:141:141)) - (PORT datac (311:311:311) (360:360:360)) - (PORT datad (105:105:105) (122:122:122)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (581:581:581)) - (PORT datab (347:347:347) (402:402:402)) - (PORT datac (450:450:450) (520:520:520)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (573:573:573)) - (PORT datab (851:851:851) (990:990:990)) - (PORT datac (309:309:309) (374:374:374)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (434:434:434)) - (PORT datab (460:460:460) (535:535:535)) - (PORT datac (480:480:480) (555:555:555)) - (PORT datad (578:578:578) (669:669:669)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (729:729:729)) - (PORT datab (674:674:674) (784:784:784)) - (PORT datac (732:732:732) (858:858:858)) - (PORT datad (1097:1097:1097) (1257:1257:1257)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (601:601:601)) - (PORT datab (1041:1041:1041) (1194:1194:1194)) - (PORT datac (653:653:653) (750:750:750)) - (PORT datad (460:460:460) (526:526:526)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (286:286:286)) - (PORT datab (591:591:591) (692:692:692)) - (PORT datac (748:748:748) (860:860:860)) - (PORT datad (595:595:595) (703:703:703)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (408:408:408)) - (PORT datab (818:818:818) (946:946:946)) - (PORT datac (815:815:815) (964:964:964)) - (PORT datad (908:908:908) (1052:1052:1052)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (398:398:398)) - (PORT datab (116:116:116) (150:150:150)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1917:1917:1917)) - (PORT datab (353:353:353) (423:423:423)) - (PORT datac (331:331:331) (381:381:381)) - (PORT datad (115:115:115) (132:132:132)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (276:276:276)) - (PORT datab (489:489:489) (569:569:569)) - (PORT datac (617:617:617) (709:709:709)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (381:381:381)) - (PORT datab (349:349:349) (417:417:417)) - (PORT datac (100:100:100) (127:127:127)) - (PORT datad (615:615:615) (709:709:709)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (747:747:747)) - (PORT datab (489:489:489) (566:566:566)) - (PORT datac (99:99:99) (127:127:127)) - (PORT datad (636:636:636) (731:731:731)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (557:557:557)) - (PORT datab (896:896:896) (1019:1019:1019)) - (PORT datac (633:633:633) (732:732:732)) - (PORT datad (783:783:783) (891:891:891)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (470:470:470) (543:543:543)) - (PORT datac (356:356:356) (421:421:421)) - (PORT datad (647:647:647) (746:746:746)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (558:558:558)) - (PORT datab (704:704:704) (809:809:809)) - (PORT datac (353:353:353) (418:418:418)) - (PORT datad (766:766:766) (874:874:874)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (923:923:923)) - (PORT datab (608:608:608) (711:711:711)) - (PORT datac (349:349:349) (416:416:416)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (613:613:613)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (357:357:357) (420:420:420)) - (PORT datac (334:334:334) (393:393:393)) - (PORT datad (323:323:323) (371:371:371)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (732:732:732)) - (PORT datab (521:521:521) (609:609:609)) - (PORT datac (313:313:313) (370:370:370)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (593:593:593)) - (PORT datab (355:355:355) (420:420:420)) - (PORT datac (519:519:519) (604:604:604)) - (PORT datad (594:594:594) (679:679:679)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (808:808:808) (954:954:954)) - (PORT datac (544:544:544) (614:614:614)) - (PORT datad (268:268:268) (304:304:304)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (258:258:258) (329:329:329)) - (PORT datac (537:537:537) (637:637:637)) - (PORT datad (324:324:324) (396:396:396)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (427:427:427) (519:519:519)) - (PORT datac (357:357:357) (422:422:422)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (249:249:249)) - (PORT datab (423:423:423) (515:515:515)) - (PORT datac (370:370:370) (438:438:438)) - (PORT datad (101:101:101) (124:124:124)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (521:521:521)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datad (326:326:326) (372:372:372)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (888:888:888)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (491:491:491)) - (PORT datac (511:511:511) (618:618:618)) - (PORT datad (493:493:493) (584:584:584)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (534:534:534)) - (PORT datab (347:347:347) (418:418:418)) - (PORT datac (498:498:498) (598:598:598)) - (PORT datad (145:145:145) (189:189:189)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (209:209:209)) - (PORT datab (512:512:512) (615:615:615)) - (PORT datac (503:503:503) (595:595:595)) - (PORT datad (418:418:418) (510:510:510)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (622:622:622)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) - (DELAY - (ABSOLUTE - (PORT datab (438:438:438) (533:533:533)) - (PORT datac (366:366:366) (436:436:436)) - (PORT datad (411:411:411) (500:500:500)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datab (393:393:393) (468:468:468)) - (PORT datac (487:487:487) (579:579:579)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (228:228:228)) - (PORT datab (326:326:326) (392:392:392)) - (PORT datac (355:355:355) (420:420:420)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (522:522:522)) - (PORT datab (218:218:218) (280:280:280)) - (PORT datad (525:525:525) (617:617:617)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (764:764:764)) - (PORT datab (340:340:340) (397:397:397)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (888:888:888)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (720:720:720) (835:835:835)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datac (485:485:485) (553:553:553)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (670:670:670)) - (PORT datac (458:458:458) (525:525:525)) - (PORT datad (384:384:384) (468:468:468)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT datab (412:412:412) (502:502:502)) - (PORT datac (698:698:698) (815:815:815)) - (PORT datad (529:529:529) (626:626:626)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (574:574:574) (687:687:687)) - (PORT datac (421:421:421) (512:512:512)) - (PORT datad (102:102:102) (124:124:124)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (501:501:501)) - (PORT datac (544:544:544) (636:636:636)) - (PORT datad (354:354:354) (420:420:420)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (582:582:582)) - (PORT datab (494:494:494) (566:566:566)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (889:889:889) (893:893:893)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datab (575:575:575) (687:687:687)) - (PORT datac (380:380:380) (455:455:455)) - (PORT datad (101:101:101) (124:124:124)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (658:658:658)) - (PORT datab (509:509:509) (586:586:586)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (889:889:889) (893:893:893)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (739:739:739)) - (PORT datab (397:397:397) (469:469:469)) - (PORT datac (116:116:116) (155:155:155)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (792:792:792)) - (PORT datac (541:541:541) (637:637:637)) - (PORT datad (357:357:357) (424:424:424)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datac (379:379:379) (453:453:453)) - (PORT datad (108:108:108) (129:129:129)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (508:508:508) (587:587:587)) - (PORT datad (312:312:312) (355:355:355)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (670:670:670)) - (PORT datab (223:223:223) (284:284:284)) - (PORT datac (538:538:538) (638:638:638)) - (PORT datad (316:316:316) (384:384:384)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (169:169:169) (229:229:229)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (370:370:370) (441:441:441)) - (PORT datad (344:344:344) (400:400:400)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (551:551:551)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (387:387:387) (472:472:472)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (392:392:392)) - (PORT datab (415:415:415) (495:495:495)) - (PORT datad (98:98:98) (119:119:119)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (489:489:489) (566:566:566)) - (PORT datac (119:119:119) (160:160:160)) - (PORT datad (781:781:781) (884:884:884)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (791:791:791)) - (PORT datab (709:709:709) (835:835:835)) - (PORT datac (380:380:380) (457:457:457)) - (PORT datad (395:395:395) (469:469:469)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (791:791:791)) - (PORT datac (543:543:543) (640:640:640)) - (PORT datad (359:359:359) (427:427:427)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (683:683:683)) - (PORT datab (518:518:518) (619:619:619)) - (PORT datac (488:488:488) (561:561:561)) - (PORT datad (390:390:390) (471:471:471)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (325:325:325) (383:383:383)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (335:335:335)) - (PORT datab (481:481:481) (574:574:574)) - (PORT datac (326:326:326) (385:385:385)) - (PORT datad (102:102:102) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (530:530:530) (637:637:637)) - (PORT datad (246:246:246) (305:305:305)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (889:889:889)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (457:457:457)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (1371:1371:1371) (1616:1616:1616)) - (PORT datad (486:486:486) (563:563:563)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (559:559:559)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (323:323:323) (378:378:378)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (692:692:692)) - (PORT datab (713:713:713) (845:845:845)) - (PORT datac (1471:1471:1471) (1729:1729:1729)) - (PORT datad (353:353:353) (414:414:414)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (618:618:618) (690:690:690)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1496:1496:1496) (1741:1741:1741)) - (PORT d[1] (2126:2126:2126) (2427:2427:2427)) - (PORT d[2] (1357:1357:1357) (1560:1560:1560)) - (PORT d[3] (2512:2512:2512) (2851:2851:2851)) - (PORT d[4] (1870:1870:1870) (2188:2188:2188)) - (PORT d[5] (2727:2727:2727) (3117:3117:3117)) - (PORT d[6] (1467:1467:1467) (1669:1669:1669)) - (PORT d[7] (784:784:784) (887:887:887)) - (PORT d[8] (1612:1612:1612) (1880:1880:1880)) - (PORT d[9] (1015:1015:1015) (1153:1153:1153)) - (PORT d[10] (959:959:959) (1086:1086:1086)) - (PORT d[11] (1981:1981:1981) (2318:2318:2318)) - (PORT d[12] (2725:2725:2725) (3085:3085:3085)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (912:912:912) (975:975:975)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1242:1242:1242) (1328:1328:1328)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (759:759:759)) - (PORT datab (366:366:366) (433:433:433)) - (PORT datac (771:771:771) (884:884:884)) - (PORT datad (602:602:602) (688:688:688)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (632:632:632) (706:706:706)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (965:965:965) (1149:1149:1149)) - (PORT d[1] (1619:1619:1619) (1828:1828:1828)) - (PORT d[2] (1371:1371:1371) (1567:1567:1567)) - (PORT d[3] (2502:2502:2502) (2839:2839:2839)) - (PORT d[4] (544:544:544) (629:629:629)) - (PORT d[5] (1237:1237:1237) (1403:1403:1403)) - (PORT d[6] (1468:1468:1468) (1670:1670:1670)) - (PORT d[7] (758:758:758) (852:852:852)) - (PORT d[8] (1599:1599:1599) (1859:1859:1859)) - (PORT d[9] (840:840:840) (949:949:949)) - (PORT d[10] (1112:1112:1112) (1256:1256:1256)) - (PORT d[11] (1982:1982:1982) (2319:2319:2319)) - (PORT d[12] (2790:2790:2790) (3157:3157:3157)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1456:1456:1456) (1585:1585:1585)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1228:1228:1228) (1312:1312:1312)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (409:409:409) (468:468:468)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1800:1800:1800) (2127:2127:2127)) - (PORT d[1] (925:925:925) (1072:1072:1072)) - (PORT d[2] (567:567:567) (658:658:658)) - (PORT d[3] (540:540:540) (624:624:624)) - (PORT d[4] (1894:1894:1894) (2181:2181:2181)) - (PORT d[5] (530:530:530) (613:613:613)) - (PORT d[6] (915:915:915) (1062:1062:1062)) - (PORT d[7] (539:539:539) (628:628:628)) - (PORT d[8] (709:709:709) (828:828:828)) - (PORT d[9] (604:604:604) (702:702:702)) - (PORT d[10] (580:580:580) (673:673:673)) - (PORT d[11] (1268:1268:1268) (1485:1485:1485)) - (PORT d[12] (620:620:620) (723:723:723)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (523:523:523) (550:550:550)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1662:1662:1662) (1834:1834:1834)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (561:561:561) (633:633:633)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1769:1769:1769) (2086:2086:2086)) - (PORT d[1] (923:923:923) (1067:1067:1067)) - (PORT d[2] (541:541:541) (628:628:628)) - (PORT d[3] (528:528:528) (614:614:614)) - (PORT d[4] (792:792:792) (905:905:905)) - (PORT d[5] (510:510:510) (589:589:589)) - (PORT d[6] (1081:1081:1081) (1253:1253:1253)) - (PORT d[7] (508:508:508) (588:588:588)) - (PORT d[8] (720:720:720) (838:838:838)) - (PORT d[9] (429:429:429) (500:500:500)) - (PORT d[10] (426:426:426) (500:500:500)) - (PORT d[11] (1459:1459:1459) (1705:1705:1705)) - (PORT d[12] (439:439:439) (517:517:517)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (360:360:360) (353:353:353)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (981:981:981) (1037:1037:1037)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1330:1330:1330) (1554:1554:1554)) - (PORT d[1] (1603:1603:1603) (1809:1809:1809)) - (PORT d[2] (1366:1366:1366) (1568:1568:1568)) - (PORT d[3] (2665:2665:2665) (3022:3022:3022)) - (PORT d[4] (556:556:556) (645:645:645)) - (PORT d[5] (1214:1214:1214) (1374:1374:1374)) - (PORT d[6] (513:513:513) (581:581:581)) - (PORT d[7] (734:734:734) (823:823:823)) - (PORT d[8] (1603:1603:1603) (1869:1869:1869)) - (PORT d[9] (832:832:832) (940:940:940)) - (PORT d[10] (1125:1125:1125) (1270:1270:1270)) - (PORT d[11] (2158:2158:2158) (2516:2516:2516)) - (PORT d[12] (2804:2804:2804) (3176:3176:3176)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (809:809:809) (745:745:745)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1267:1267:1267)) - (PORT datab (851:851:851) (984:984:984)) - (PORT datac (500:500:500) (563:563:563)) - (PORT datad (591:591:591) (675:675:675)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (486:486:486) (556:556:556)) - (PORT datac (771:771:771) (884:884:884)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (983:983:983)) - (PORT datab (628:628:628) (717:717:717)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (1017:1017:1017) (1172:1172:1172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (796:796:796) (904:904:904)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1418:1418:1418) (1643:1643:1643)) - (PORT d[1] (1567:1567:1567) (1789:1789:1789)) - (PORT d[2] (1482:1482:1482) (1705:1705:1705)) - (PORT d[3] (1939:1939:1939) (2194:2194:2194)) - (PORT d[4] (1324:1324:1324) (1555:1555:1555)) - (PORT d[5] (2153:2153:2153) (2452:2452:2452)) - (PORT d[6] (1462:1462:1462) (1666:1666:1666)) - (PORT d[7] (1936:1936:1936) (2205:2205:2205)) - (PORT d[8] (1666:1666:1666) (1901:1901:1901)) - (PORT d[9] (1585:1585:1585) (1810:1810:1810)) - (PORT d[10] (1499:1499:1499) (1705:1705:1705)) - (PORT d[11] (1426:1426:1426) (1677:1677:1677)) - (PORT d[12] (2085:2085:2085) (2366:2366:2366)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1792:1792:1792)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (2145:2145:2145) (1989:1989:1989)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1350:1350:1350) (1504:1504:1504)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2471:2471:2471) (2783:2783:2783)) - (PORT d[1] (2502:2502:2502) (2825:2825:2825)) - (PORT d[2] (2515:2515:2515) (2832:2832:2832)) - (PORT d[3] (2434:2434:2434) (2750:2750:2750)) - (PORT d[4] (2424:2424:2424) (2763:2763:2763)) - (PORT d[5] (2474:2474:2474) (2805:2805:2805)) - (PORT d[6] (2470:2470:2470) (2777:2777:2777)) - (PORT d[7] (2424:2424:2424) (2719:2719:2719)) - (PORT d[8] (2462:2462:2462) (2784:2784:2784)) - (PORT d[9] (2452:2452:2452) (2796:2796:2796)) - (PORT d[10] (2383:2383:2383) (2682:2682:2682)) - (PORT d[11] (2452:2452:2452) (2792:2792:2792)) - (PORT d[12] (2340:2340:2340) (2638:2638:2638)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1053:1053:1053) (1072:1072:1072)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (1498:1498:1498) (1759:1759:1759)) - (PORT datab (1390:1390:1390) (1610:1610:1610)) - (PORT datac (901:901:901) (1043:1043:1043)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (791:791:791) (890:890:890)) - (PORT clk (1091:1091:1091) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1114:1114:1114) (1308:1308:1308)) - (PORT d[1] (1755:1755:1755) (2009:2009:2009)) - (PORT d[2] (1046:1046:1046) (1206:1206:1206)) - (PORT d[3] (2118:2118:2118) (2399:2399:2399)) - (PORT d[4] (1509:1509:1509) (1776:1776:1776)) - (PORT d[5] (2340:2340:2340) (2670:2670:2670)) - (PORT d[6] (1547:1547:1547) (1757:1757:1757)) - (PORT d[7] (1139:1139:1139) (1288:1288:1288)) - (PORT d[8] (1138:1138:1138) (1289:1289:1289)) - (PORT d[9] (1415:1415:1415) (1616:1616:1616)) - (PORT d[10] (1512:1512:1512) (1723:1723:1723)) - (PORT d[11] (1592:1592:1592) (1869:1869:1869)) - (PORT d[12] (2685:2685:2685) (3043:3043:3043)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (857:857:857) (914:914:914)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (PORT d[0] (1808:1808:1808) (1970:1970:1970)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1066:1066:1066)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1205:1205:1205) (1342:1342:1342)) - (PORT clk (1051:1051:1051) (1069:1069:1069)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2531:2531:2531) (2860:2860:2860)) - (PORT d[1] (2492:2492:2492) (2813:2813:2813)) - (PORT d[2] (2475:2475:2475) (2783:2783:2783)) - (PORT d[3] (2451:2451:2451) (2772:2772:2772)) - (PORT d[4] (2449:2449:2449) (2806:2806:2806)) - (PORT d[5] (2451:2451:2451) (2771:2771:2771)) - (PORT d[6] (2479:2479:2479) (2782:2782:2782)) - (PORT d[7] (2447:2447:2447) (2787:2787:2787)) - (PORT d[8] (2504:2504:2504) (2820:2820:2820)) - (PORT d[9] (2535:2535:2535) (2871:2871:2871)) - (PORT d[10] (2420:2420:2420) (2729:2729:2729)) - (PORT d[11] (2509:2509:2509) (2845:2845:2845)) - (PORT d[12] (2348:2348:2348) (2648:2648:2648)) - (PORT clk (1048:1048:1048) (1068:1068:1068)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1069:1069:1069)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1070:1070:1070)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1411:1411:1411) (1643:1643:1643)) - (PORT d[1] (1391:1391:1391) (1581:1581:1581)) - (PORT d[2] (1332:1332:1332) (1552:1552:1552)) - (PORT d[3] (1272:1272:1272) (1464:1464:1464)) - (PORT d[4] (1165:1165:1165) (1361:1361:1361)) - (PORT d[5] (1406:1406:1406) (1606:1606:1606)) - (PORT d[6] (1424:1424:1424) (1638:1638:1638)) - (PORT d[7] (1799:1799:1799) (2059:2059:2059)) - (PORT d[8] (1604:1604:1604) (1846:1846:1846)) - (PORT d[9] (1413:1413:1413) (1632:1632:1632)) - (PORT d[10] (1880:1880:1880) (2160:2160:2160)) - (PORT d[11] (1187:1187:1187) (1372:1372:1372)) - (PORT d[12] (1360:1360:1360) (1566:1566:1566)) - (PORT clk (1099:1099:1099) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1117:1117:1117)) - (PORT d[0] (1510:1510:1510) (1695:1695:1695)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1081:1081:1081) (1098:1098:1098)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (621:621:621) (630:630:630)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (622:622:622) (631:631:631)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (622:622:622) (631:631:631)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (622:622:622) (631:631:631)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1751:1751:1751)) - (PORT datab (1391:1391:1391) (1611:1611:1611)) - (PORT datac (748:748:748) (848:848:848)) - (PORT datad (931:931:931) (1053:1053:1053)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (809:809:809)) - (PORT datab (415:415:415) (507:507:507)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1265:1265:1265)) - (PORT datab (104:104:104) (134:134:134)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (976:976:976)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1786:1786:1786)) - (PORT datab (518:518:518) (620:620:620)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (826:826:826) (943:943:943)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (170:170:170)) - (PORT datab (479:479:479) (545:545:545)) - (PORT datac (337:337:337) (396:396:396)) - (PORT datad (622:622:622) (712:712:712)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (259:259:259)) - (PORT datac (191:191:191) (242:242:242)) - (PORT datad (199:199:199) (238:238:238)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (802:802:802)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (470:470:470) (557:557:557)) - (PORT datad (301:301:301) (343:343:343)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1057:1057:1057) (1164:1164:1164)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1448:1448:1448)) - (PORT datac (887:887:887) (1059:1059:1059)) - (PORT datad (951:951:951) (1085:1085:1085)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (543:543:543)) - (PORT datab (1055:1055:1055) (1214:1214:1214)) - (PORT datac (616:616:616) (711:711:711)) - (PORT datad (340:340:340) (398:398:398)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (406:406:406)) - (PORT datab (105:105:105) (136:136:136)) - (PORT datac (633:633:633) (736:736:736)) - (PORT datad (455:455:455) (534:534:534)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (322:322:322) (370:370:370)) - (PORT datad (622:622:622) (712:712:712)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (837:837:837) (945:945:945)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1371:1371:1371) (1627:1627:1627)) - (PORT d[1] (1470:1470:1470) (1662:1662:1662)) - (PORT d[2] (897:897:897) (1029:1029:1029)) - (PORT d[3] (721:721:721) (835:835:835)) - (PORT d[4] (1130:1130:1130) (1291:1291:1291)) - (PORT d[5] (719:719:719) (830:830:830)) - (PORT d[6] (952:952:952) (1082:1082:1082)) - (PORT d[7] (1353:1353:1353) (1554:1554:1554)) - (PORT d[8] (1388:1388:1388) (1636:1636:1636)) - (PORT d[9] (597:597:597) (688:688:688)) - (PORT d[10] (988:988:988) (1132:1132:1132)) - (PORT d[11] (820:820:820) (939:939:939)) - (PORT d[12] (572:572:572) (661:661:661)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1008:1008:1008) (1096:1096:1096)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1161:1161:1161) (1245:1245:1245)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (824:824:824) (928:928:928)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1351:1351:1351) (1598:1598:1598)) - (PORT d[1] (1140:1140:1140) (1291:1291:1291)) - (PORT d[2] (1063:1063:1063) (1222:1222:1222)) - (PORT d[3] (1259:1259:1259) (1438:1438:1438)) - (PORT d[4] (1143:1143:1143) (1304:1304:1304)) - (PORT d[5] (913:913:913) (1051:1051:1051)) - (PORT d[6] (971:971:971) (1102:1102:1102)) - (PORT d[7] (1298:1298:1298) (1482:1482:1482)) - (PORT d[8] (1407:1407:1407) (1655:1655:1655)) - (PORT d[9] (674:674:674) (764:764:764)) - (PORT d[10] (925:925:925) (1050:1050:1050)) - (PORT d[11] (668:668:668) (767:767:767)) - (PORT d[12] (604:604:604) (700:700:700)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (878:878:878) (949:949:949)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1105:1105:1105) (1172:1172:1172)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (506:506:506) (567:567:567)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1711:1711:1711) (1997:1997:1997)) - (PORT d[1] (2087:2087:2087) (2382:2382:2382)) - (PORT d[2] (1116:1116:1116) (1274:1274:1274)) - (PORT d[3] (2313:2313:2313) (2621:2621:2621)) - (PORT d[4] (1841:1841:1841) (2153:2153:2153)) - (PORT d[5] (2688:2688:2688) (3070:3070:3070)) - (PORT d[6] (1269:1269:1269) (1440:1440:1440)) - (PORT d[7] (949:949:949) (1071:1071:1071)) - (PORT d[8] (1789:1789:1789) (2077:2077:2077)) - (PORT d[9] (1048:1048:1048) (1193:1193:1193)) - (PORT d[10] (1152:1152:1152) (1305:1305:1305)) - (PORT d[11] (1771:1771:1771) (2069:2069:2069)) - (PORT d[12] (2703:2703:2703) (3061:3061:3061)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1292:1292:1292) (1403:1403:1403)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1413:1413:1413) (1518:1518:1518)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (653:653:653) (753:753:753)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1515:1515:1515) (1766:1766:1766)) - (PORT d[1] (2121:2121:2121) (2428:2428:2428)) - (PORT d[2] (1203:1203:1203) (1382:1382:1382)) - (PORT d[3] (2480:2480:2480) (2814:2814:2814)) - (PORT d[4] (1872:1872:1872) (2192:2192:2192)) - (PORT d[5] (2696:2696:2696) (3075:3075:3075)) - (PORT d[6] (1469:1469:1469) (1677:1677:1677)) - (PORT d[7] (792:792:792) (896:896:896)) - (PORT d[8] (1791:1791:1791) (2085:2085:2085)) - (PORT d[9] (1044:1044:1044) (1190:1190:1190)) - (PORT d[10] (1129:1129:1129) (1278:1278:1278)) - (PORT d[11] (1957:1957:1957) (2290:2290:2290)) - (PORT d[12] (2706:2706:2706) (3060:3060:3060)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (862:862:862) (913:913:913)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (1379:1379:1379) (1480:1480:1480)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (511:511:511)) - (PORT datab (634:634:634) (755:755:755)) - (PORT datac (648:648:648) (764:764:764)) - (PORT datad (605:605:605) (691:691:691)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (794:794:794)) - (PORT datab (729:729:729) (840:840:840)) - (PORT datac (964:964:964) (1117:1117:1117)) - (PORT datad (161:161:161) (187:187:187)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1694:1694:1694)) - (PORT datab (1124:1124:1124) (1327:1327:1327)) - (PORT datac (1571:1571:1571) (1835:1835:1835)) - (PORT datad (1215:1215:1215) (1396:1396:1396)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (908:908:908) (1036:1036:1036)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1882:1882:1882) (2187:2187:2187)) - (PORT d[1] (1941:1941:1941) (2211:2211:2211)) - (PORT d[2] (1295:1295:1295) (1481:1481:1481)) - (PORT d[3] (2117:2117:2117) (2395:2395:2395)) - (PORT d[4] (1693:1693:1693) (1991:1991:1991)) - (PORT d[5] (2497:2497:2497) (2848:2848:2848)) - (PORT d[6] (1018:1018:1018) (1166:1166:1166)) - (PORT d[7] (1122:1122:1122) (1269:1269:1269)) - (PORT d[8] (1140:1140:1140) (1294:1294:1294)) - (PORT d[9] (1231:1231:1231) (1400:1400:1400)) - (PORT d[10] (1338:1338:1338) (1522:1522:1522)) - (PORT d[11] (1601:1601:1601) (1879:1879:1879)) - (PORT d[12] (2526:2526:2526) (2864:2864:2864)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (913:913:913) (980:980:980)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (1612:1612:1612) (1743:1743:1743)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1200:1200:1200) (1335:1335:1335)) - (PORT clk (1055:1055:1055) (1072:1072:1072)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2524:2524:2524) (2849:2849:2849)) - (PORT d[1] (2509:2509:2509) (2833:2833:2833)) - (PORT d[2] (2510:2510:2510) (2827:2827:2827)) - (PORT d[3] (2459:2459:2459) (2780:2780:2780)) - (PORT d[4] (2474:2474:2474) (2834:2834:2834)) - (PORT d[5] (2437:2437:2437) (2753:2753:2753)) - (PORT d[6] (2452:2452:2452) (2755:2755:2755)) - (PORT d[7] (2473:2473:2473) (2784:2784:2784)) - (PORT d[8] (2542:2542:2542) (2871:2871:2871)) - (PORT d[9] (2539:2539:2539) (2878:2878:2878)) - (PORT d[10] (2570:2570:2570) (2897:2897:2897)) - (PORT d[11] (2498:2498:2498) (2845:2845:2845)) - (PORT d[12] (2367:2367:2367) (2670:2670:2670)) - (PORT clk (1052:1052:1052) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (976:976:976) (1157:1157:1157)) - (PORT d[1] (943:943:943) (1059:1059:1059)) - (PORT d[2] (1312:1312:1312) (1530:1530:1530)) - (PORT d[3] (1053:1053:1053) (1188:1188:1188)) - (PORT d[4] (1348:1348:1348) (1556:1556:1556)) - (PORT d[5] (1449:1449:1449) (1643:1643:1643)) - (PORT d[6] (1107:1107:1107) (1264:1264:1264)) - (PORT d[7] (1147:1147:1147) (1306:1306:1306)) - (PORT d[8] (1176:1176:1176) (1369:1369:1369)) - (PORT d[9] (1141:1141:1141) (1286:1286:1286)) - (PORT d[10] (945:945:945) (1063:1063:1063)) - (PORT d[11] (2540:2540:2540) (2952:2952:2952)) - (PORT d[12] (1217:1217:1217) (1369:1369:1369)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (1170:1170:1170) (1282:1282:1282)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (877:877:877) (1008:1008:1008)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (928:928:928) (1096:1096:1096)) - (PORT d[1] (1731:1731:1731) (1979:1979:1979)) - (PORT d[2] (1482:1482:1482) (1700:1700:1700)) - (PORT d[3] (1930:1930:1930) (2182:2182:2182)) - (PORT d[4] (1501:1501:1501) (1768:1768:1768)) - (PORT d[5] (2167:2167:2167) (2473:2473:2473)) - (PORT d[6] (1282:1282:1282) (1459:1459:1459)) - (PORT d[7] (1930:1930:1930) (2196:2196:2196)) - (PORT d[8] (1666:1666:1666) (1902:1902:1902)) - (PORT d[9] (1436:1436:1436) (1645:1645:1645)) - (PORT d[10] (1509:1509:1509) (1717:1717:1717)) - (PORT d[11] (1417:1417:1417) (1665:1665:1665)) - (PORT d[12] (2715:2715:2715) (3081:3081:3081)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1793:1793:1793)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1951:1951:1951) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1071:1071:1071) (1195:1195:1195)) - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2476:2476:2476) (2793:2793:2793)) - (PORT d[1] (2474:2474:2474) (2790:2790:2790)) - (PORT d[2] (2491:2491:2491) (2810:2810:2810)) - (PORT d[3] (2356:2356:2356) (2668:2668:2668)) - (PORT d[4] (2441:2441:2441) (2785:2785:2785)) - (PORT d[5] (2460:2460:2460) (2779:2779:2779)) - (PORT d[6] (2451:2451:2451) (2753:2753:2753)) - (PORT d[7] (2323:2323:2323) (2607:2607:2607)) - (PORT d[8] (2452:2452:2452) (2765:2765:2765)) - (PORT d[9] (2430:2430:2430) (2768:2768:2768)) - (PORT d[10] (2382:2382:2382) (2679:2679:2679)) - (PORT d[11] (2528:2528:2528) (2870:2870:2870)) - (PORT d[12] (2437:2437:2437) (2729:2729:2729)) - (PORT clk (1051:1051:1051) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (946:946:946) (1118:1118:1118)) - (PORT d[1] (1572:1572:1572) (1788:1788:1788)) - (PORT d[2] (1233:1233:1233) (1425:1425:1425)) - (PORT d[3] (1921:1921:1921) (2172:2172:2172)) - (PORT d[4] (1323:1323:1323) (1554:1554:1554)) - (PORT d[5] (2135:2135:2135) (2430:2430:2430)) - (PORT d[6] (1452:1452:1452) (1652:1652:1652)) - (PORT d[7] (1937:1937:1937) (2211:2211:2211)) - (PORT d[8] (1659:1659:1659) (1893:1893:1893)) - (PORT d[9] (1608:1608:1608) (1837:1837:1837)) - (PORT d[10] (1310:1310:1310) (1495:1495:1495)) - (PORT d[11] (1404:1404:1404) (1647:1647:1647)) - (PORT d[12] (2083:2083:2083) (2363:2363:2363)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (PORT d[0] (1679:1679:1679) (1502:1502:1502)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1079:1079:1079) (1096:1096:1096)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (780:780:780)) - (PORT datab (383:383:383) (454:454:454)) - (PORT datac (746:746:746) (855:855:855)) - (PORT datad (779:779:779) (902:902:902)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (438:438:438)) - (PORT datab (602:602:602) (688:688:688)) - (PORT datac (871:871:871) (1020:1020:1020)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (544:544:544) (627:627:627)) - (PORT datad (336:336:336) (394:394:394)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (754:754:754)) - (PORT datab (1406:1406:1406) (1606:1606:1606)) - (PORT datac (664:664:664) (777:777:777)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (228:228:228)) - (PORT datab (230:230:230) (271:271:271)) - (PORT datac (653:653:653) (758:758:758)) - (PORT datad (623:623:623) (713:713:713)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (218:218:218) (259:259:259)) - (PORT datac (307:307:307) (352:352:352)) - (PORT datad (132:132:132) (169:169:169)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (350:350:350) (379:379:379)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1045:1045:1045) (1140:1140:1140)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (612:612:612) (706:706:706)) - (PORT datad (1095:1095:1095) (1255:1255:1255)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1651:1651:1651)) - (PORT datab (1169:1169:1169) (1377:1377:1377)) - (PORT datac (1417:1417:1417) (1670:1670:1670)) - (PORT datad (1038:1038:1038) (1195:1195:1195)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (1056:1056:1056)) - (PORT datab (289:289:289) (338:338:338)) - (PORT datac (458:458:458) (522:522:522)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (425:425:425)) - (PORT datab (494:494:494) (593:593:593)) - (PORT datac (802:802:802) (905:905:905)) - (PORT datad (645:645:645) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1279:1279:1279) (1484:1484:1484)) - (PORT datab (1233:1233:1233) (1454:1454:1454)) - (PORT datac (671:671:671) (778:778:778)) - (PORT datad (476:476:476) (568:568:568)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (906:906:906)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (890:890:890)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (509:509:509)) - (PORT datab (411:411:411) (504:504:504)) - (PORT datac (1059:1059:1059) (1237:1237:1237)) - (PORT datad (935:935:935) (1081:1081:1081)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (621:621:621)) - (PORT datab (656:656:656) (766:766:766)) - (PORT datac (1054:1054:1054) (1210:1210:1210)) - (PORT datad (787:787:787) (902:902:902)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (499:499:499) (542:542:542)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (498:498:498) (538:538:538)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (396:396:396)) - (PORT datab (510:510:510) (600:600:600)) - (PORT datad (190:190:190) (237:237:237)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (571:571:571)) - (PORT datab (552:552:552) (646:646:646)) - (PORT datac (319:319:319) (384:384:384)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (396:396:396)) - (PORT datab (110:110:110) (140:140:140)) - (PORT datac (635:635:635) (739:739:739)) - (PORT datad (451:451:451) (530:530:530)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (1000:1000:1000)) - (PORT datab (695:695:695) (804:804:804)) - (PORT datac (640:640:640) (731:731:731)) - (PORT datad (835:835:835) (954:954:954)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (404:404:404)) - (PORT datab (789:789:789) (910:910:910)) - (PORT datac (265:265:265) (302:302:302)) - (PORT datad (533:533:533) (621:621:621)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (497:497:497) (580:580:580)) - (PORT datad (334:334:334) (393:393:393)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (275:275:275) (315:315:315)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (621:621:621)) - (PORT datab (512:512:512) (615:615:615)) - (PORT datac (138:138:138) (183:183:183)) - (PORT datad (145:145:145) (190:190:190)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (400:400:400) (477:477:477)) - (PORT datad (550:550:550) (657:657:657)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (173:173:173) (211:211:211)) - (PORT datac (408:408:408) (499:499:499)) - (PORT datad (312:312:312) (361:361:361)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (420:420:420) (508:508:508)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (895:895:895) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (887:887:887) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (169:169:169) (235:235:235)) - (PORT datab (357:357:357) (430:430:430)) - (PORT datac (489:489:489) (580:580:580)) - (PORT datad (519:519:519) (620:620:620)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (509:509:509)) - (PORT datab (419:419:419) (501:501:501)) - (PORT datac (383:383:383) (465:465:465)) - (PORT datad (523:523:523) (617:617:617)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT datab (572:572:572) (684:684:684)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (413:413:413)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (376:376:376) (444:444:444)) - (PORT datad (270:270:270) (309:309:309)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (215:215:215)) - (PORT datab (423:423:423) (512:512:512)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (895:895:895) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (887:887:887) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (522:522:522) (613:613:613)) - (PORT datac (432:432:432) (489:489:489)) - (PORT datad (120:120:120) (157:157:157)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (258:258:258) (330:330:330)) - (PORT datab (551:551:551) (658:658:658)) - (PORT datac (348:348:348) (410:410:410)) - (PORT datad (329:329:329) (401:401:401)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (258:258:258) (330:330:330)) - (PORT datac (415:415:415) (501:501:501)) - (PORT datad (208:208:208) (260:260:260)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (683:683:683)) - (PORT datac (488:488:488) (561:561:561)) - (PORT datad (390:390:390) (471:471:471)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datad (309:309:309) (355:355:355)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (888:888:888)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (364:364:364)) - (PORT datab (572:572:572) (684:684:684)) - (PORT datac (394:394:394) (470:470:470)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (146:146:146)) - (PORT datab (292:292:292) (338:338:338)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (899:899:899)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (125:125:125) (159:159:159)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (507:507:507) (595:595:595)) - (PORT datad (334:334:334) (390:390:390)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (478:478:478)) - (PORT datab (562:562:562) (660:660:660)) - (PORT datac (535:535:535) (633:633:633)) - (PORT datad (311:311:311) (355:355:355)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (862:862:862)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (898:898:898) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (891:891:891) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (338:338:338) (412:412:412)) - (PORT datac (543:543:543) (643:643:643)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (493:493:493)) - (PORT datab (531:531:531) (638:638:638)) - (PORT datac (410:410:410) (505:505:505)) - (PORT datad (493:493:493) (584:584:584)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~69) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (332:332:332)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (510:510:510) (616:616:616)) - (PORT datad (103:103:103) (126:126:126)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (552:552:552)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (318:318:318) (374:374:374)) - (PORT datad (390:390:390) (474:474:474)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (224:224:224) (285:285:285)) - (PORT datac (413:413:413) (498:498:498)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (670:670:670)) - (PORT datab (316:316:316) (382:382:382)) - (PORT datac (545:545:545) (645:645:645)) - (PORT datad (321:321:321) (389:389:389)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~71) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (418:418:418)) - (PORT datab (406:406:406) (497:497:497)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (141:141:141) (184:184:184)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (404:404:404) (488:488:488)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (887:887:887)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (940:940:940)) - (PORT datac (1294:1294:1294) (1527:1527:1527)) - (PORT datad (488:488:488) (570:570:570)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (478:478:478)) - (PORT datac (536:536:536) (634:634:634)) - (PORT datad (312:312:312) (356:356:356)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (864:864:864)) - (PORT datab (562:562:562) (660:660:660)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (898:898:898) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (891:891:891) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (252:252:252)) - (PORT datab (391:391:391) (467:467:467)) - (PORT datac (488:488:488) (579:579:579)) - (PORT datad (105:105:105) (129:129:129)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (863:863:863)) - (PORT datab (520:520:520) (605:605:605)) - (PORT datad (322:322:322) (360:360:360)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (898:898:898) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (891:891:891) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (1621:1621:1621) (1900:1900:1900)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (569:569:569)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (1372:1372:1372) (1621:1621:1621)) - (PORT datad (327:327:327) (383:383:383)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (679:679:679) (775:775:775)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1569:1569:1569) (1852:1852:1852)) - (PORT d[1] (1661:1661:1661) (1877:1877:1877)) - (PORT d[2] (572:572:572) (661:661:661)) - (PORT d[3] (547:547:547) (638:638:638)) - (PORT d[4] (1167:1167:1167) (1338:1338:1338)) - (PORT d[5] (539:539:539) (625:625:625)) - (PORT d[6] (956:956:956) (1085:1085:1085)) - (PORT d[7] (1543:1543:1543) (1768:1768:1768)) - (PORT d[8] (1410:1410:1410) (1661:1661:1661)) - (PORT d[9] (415:415:415) (485:485:485)) - (PORT d[10] (408:408:408) (481:481:481)) - (PORT d[11] (1641:1641:1641) (1916:1916:1916)) - (PORT d[12] (232:232:232) (273:273:273)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (850:850:850) (918:918:918)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (794:794:794) (826:826:826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1064:1064:1064) (1081:1081:1081)) @@ -41706,7 +39385,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (604:604:604) (613:613:613)) @@ -41715,7 +39394,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE (PORT clk (605:605:605) (614:614:614)) @@ -41724,7 +39403,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (605:605:605) (614:614:614)) @@ -41734,7 +39413,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (605:605:605) (614:614:614)) @@ -41742,13 +39421,1909 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (926:926:926) (1067:1067:1067)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1732:1732:1732) (1975:1975:1975)) + (PORT d[1] (1077:1077:1077) (1254:1254:1254)) + (PORT d[2] (1598:1598:1598) (1828:1828:1828)) + (PORT d[3] (1856:1856:1856) (2123:2123:2123)) + (PORT d[4] (2151:2151:2151) (2502:2502:2502)) + (PORT d[5] (1698:1698:1698) (1935:1935:1935)) + (PORT d[6] (1447:1447:1447) (1682:1682:1682)) + (PORT d[7] (1396:1396:1396) (1608:1608:1608)) + (PORT d[8] (1323:1323:1323) (1524:1524:1524)) + (PORT d[9] (1377:1377:1377) (1591:1591:1591)) + (PORT d[10] (1178:1178:1178) (1392:1392:1392)) + (PORT d[11] (1395:1395:1395) (1606:1606:1606)) + (PORT d[12] (990:990:990) (1171:1171:1171)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1150:1150:1150) (1251:1251:1251)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (2104:2104:2104) (1957:1957:1957)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1053:1053:1053) (1072:1072:1072)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (641:641:641) (727:727:727)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2354:2354:2354) (2678:2678:2678)) + (PORT d[1] (2421:2421:2421) (2797:2797:2797)) + (PORT d[2] (2404:2404:2404) (2742:2742:2742)) + (PORT d[3] (2402:2402:2402) (2744:2744:2744)) + (PORT d[4] (2452:2452:2452) (2777:2777:2777)) + (PORT d[5] (2519:2519:2519) (2944:2944:2944)) + (PORT d[6] (2431:2431:2431) (2819:2819:2819)) + (PORT d[7] (2414:2414:2414) (2761:2761:2761)) + (PORT d[8] (2317:2317:2317) (2602:2602:2602)) + (PORT d[9] (2256:2256:2256) (2541:2541:2541)) + (PORT d[10] (2256:2256:2256) (2541:2541:2541)) + (PORT d[11] (2375:2375:2375) (2715:2715:2715)) + (PORT d[12] (2406:2406:2406) (2716:2716:2716)) + (PORT clk (1055:1055:1055) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1073:1073:1073)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (436:436:436)) + (PORT datab (680:680:680) (787:787:787)) + (PORT datac (674:674:674) (762:762:762)) + (PORT datad (687:687:687) (786:786:786)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (1015:1015:1015)) + (PORT datab (149:149:149) (201:201:201)) + (PORT datac (847:847:847) (953:953:953)) + (PORT datad (169:169:169) (200:200:200)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (924:924:924)) + (PORT datab (1415:1415:1415) (1622:1622:1622)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (163:163:163) (193:193:193)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (915:915:915)) + (PORT datab (644:644:644) (746:746:746)) + (PORT datac (511:511:511) (595:595:595)) + (PORT datad (165:165:165) (192:192:192)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (413:413:413)) + (PORT datab (137:137:137) (178:178:178)) + (PORT datac (810:810:810) (949:949:949)) + (PORT datad (1093:1093:1093) (1263:1263:1263)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (159:159:159)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (609:609:609) (703:703:703)) + (PORT datad (132:132:132) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (104:104:104) (121:121:121)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (902:902:902) (888:888:888)) + (PORT ena (996:996:996) (1107:1107:1107)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (882:882:882)) + (PORT datab (485:485:485) (564:564:564)) + (PORT datac (239:239:239) (301:301:301)) + (PORT datad (652:652:652) (748:748:748)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (813:813:813)) + (PORT datab (797:797:797) (922:922:922)) + (PORT datac (521:521:521) (617:617:617)) + (PORT datad (350:350:350) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datac (500:500:500) (566:566:566)) + (PORT datad (598:598:598) (665:665:665)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (91:91:91) (115:115:115)) + (PORT datad (794:794:794) (926:926:926)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (925:925:925)) + (PORT datab (731:731:731) (880:880:880)) + (PORT datac (1058:1058:1058) (1238:1238:1238)) + (PORT datad (685:685:685) (782:782:782)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (576:576:576)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (663:663:663) (753:753:753)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (830:830:830)) + (PORT datab (878:878:878) (1023:1023:1023)) + (PORT datac (666:666:666) (782:782:782)) + (PORT datad (1115:1115:1115) (1267:1267:1267)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (601:601:601)) + (PORT datab (854:854:854) (989:989:989)) + (PORT datac (685:685:685) (782:782:782)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (694:694:694)) + (PORT datab (660:660:660) (767:767:767)) + (PORT datac (526:526:526) (600:600:600)) + (PORT datad (510:510:510) (602:602:602)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1261:1261:1261)) + (PORT datab (720:720:720) (854:854:854)) + (PORT datac (526:526:526) (599:599:599)) + (PORT datad (662:662:662) (761:761:761)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (534:534:534) (632:632:632)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (556:556:556) (636:636:636)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1589:1589:1589) (1819:1819:1819)) + (PORT d[1] (1114:1114:1114) (1297:1297:1297)) + (PORT d[2] (2168:2168:2168) (2479:2479:2479)) + (PORT d[3] (880:880:880) (1020:1020:1020)) + (PORT d[4] (906:906:906) (1053:1053:1053)) + (PORT d[5] (1001:1001:1001) (1157:1157:1157)) + (PORT d[6] (1612:1612:1612) (1866:1866:1866)) + (PORT d[7] (843:843:843) (966:966:966)) + (PORT d[8] (1877:1877:1877) (2154:2154:2154)) + (PORT d[9] (1002:1002:1002) (1152:1152:1152)) + (PORT d[10] (1173:1173:1173) (1389:1389:1389)) + (PORT d[11] (1553:1553:1553) (1784:1784:1784)) + (PORT d[12] (956:956:956) (1120:1120:1120)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (491:491:491) (509:509:509)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1255:1255:1255) (1343:1343:1343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (309:309:309)) + (PORT datac (401:401:401) (488:488:488)) + (PORT datad (385:385:385) (470:470:470)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (783:783:783)) + (PORT datab (414:414:414) (507:507:507)) + (PORT datac (467:467:467) (556:556:556)) + (PORT datad (391:391:391) (478:478:478)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (412:412:412) (504:504:504)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (494:494:494) (576:576:576)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (540:540:540)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (894:894:894) (900:900:900)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (513:513:513)) + (PORT datab (176:176:176) (236:236:236)) + (PORT datac (453:453:453) (538:538:538)) + (PORT datad (218:218:218) (273:273:273)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (148:148:148)) + (PORT datab (473:473:473) (562:562:562)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (382:382:382) (468:468:468)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (390:390:390)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (441:441:441)) + (PORT datab (1209:1209:1209) (1410:1410:1410)) + (PORT datac (1134:1134:1134) (1295:1295:1295)) + (PORT datad (341:341:341) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (519:519:519)) + (PORT datab (516:516:516) (621:621:621)) + (PORT datac (379:379:379) (463:463:463)) + (PORT datad (655:655:655) (758:758:758)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (465:465:465)) + (PORT datac (379:379:379) (471:471:471)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (492:492:492)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (342:342:342) (399:399:399)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT datab (480:480:480) (555:555:555)) + (PORT datad (542:542:542) (646:646:646)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (464:464:464)) + (PORT datad (529:529:529) (627:627:627)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (634:634:634)) + (PORT datab (401:401:401) (485:485:485)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (635:635:635)) + (PORT datac (516:516:516) (605:605:605)) + (PORT datad (385:385:385) (465:465:465)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (649:649:649)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (516:516:516) (611:611:611)) + (PORT datad (361:361:361) (431:431:431)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (298:298:298)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (330:330:330) (381:381:381)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (672:672:672)) + (PORT datad (162:162:162) (189:189:189)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (677:677:677)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (981:981:981) (1122:1122:1122)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (635:635:635)) + (PORT datab (574:574:574) (688:688:688)) + (PORT datac (612:612:612) (726:726:726)) + (PORT datad (492:492:492) (572:572:572)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (710:710:710) (836:836:836)) + (PORT datad (370:370:370) (448:448:448)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (705:705:705)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (496:496:496) (581:581:581)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (702:702:702)) + (PORT datab (709:709:709) (835:835:835)) + (PORT datac (523:523:523) (612:612:612)) + (PORT datad (370:370:370) (447:447:447)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~72) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (704:704:704)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (492:492:492) (572:572:572)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (749:749:749)) + (PORT datac (557:557:557) (669:669:669)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (472:472:472) (545:545:545)) + (PORT datac (495:495:495) (580:580:580)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (543:543:543) (647:647:647)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (392:392:392) (478:478:478)) + (PORT datad (494:494:494) (576:576:576)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (516:516:516)) + (PORT datab (286:286:286) (332:332:332)) + (PORT datac (341:341:341) (398:398:398)) + (PORT datad (383:383:383) (464:464:464)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (579:579:579)) + (PORT datab (703:703:703) (829:829:829)) + (PORT datac (615:615:615) (730:730:730)) + (PORT datad (577:577:577) (682:682:682)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (539:539:539) (643:643:643)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (1815:1815:1815) (2102:2102:2102)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (2220:2220:2220) (2566:2566:2566)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (738:738:738)) + (PORT datab (686:686:686) (809:809:809)) + (PORT datad (493:493:493) (556:556:556)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (654:654:654)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datad (541:541:541) (644:644:644)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (518:518:518)) + (PORT datab (516:516:516) (622:622:622)) + (PORT datac (340:340:340) (397:397:397)) + (PORT datad (274:274:274) (310:310:310)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (416:416:416)) + (PORT datab (428:428:428) (525:525:525)) + (PORT datad (192:192:192) (225:225:225)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (179:179:179)) + (PORT datab (366:366:366) (446:446:446)) + (PORT datac (1253:1253:1253) (1428:1428:1428)) + (PORT datad (1245:1245:1245) (1462:1462:1462)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (307:307:307) (353:353:353)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (760:760:760)) + (PORT datab (795:795:795) (909:909:909)) + (PORT datac (914:914:914) (1057:1057:1057)) + (PORT datad (887:887:887) (1002:1002:1002)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~13) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (809:809:809)) + (PORT datab (534:534:534) (620:620:620)) + (PORT datac (861:861:861) (982:982:982)) + (PORT datad (118:118:118) (141:141:141)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (552:552:552) (631:631:631)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1582:1582:1582) (1812:1812:1812)) + (PORT d[1] (1106:1106:1106) (1288:1288:1288)) + (PORT d[2] (2162:2162:2162) (2474:2474:2474)) + (PORT d[3] (1056:1056:1056) (1233:1233:1233)) + (PORT d[4] (927:927:927) (1080:1080:1080)) + (PORT d[5] (1012:1012:1012) (1169:1169:1169)) + (PORT d[6] (1617:1617:1617) (1873:1873:1873)) + (PORT d[7] (988:988:988) (1132:1132:1132)) + (PORT d[8] (1876:1876:1876) (2153:2153:2153)) + (PORT d[9] (2319:2319:2319) (2680:2680:2680)) + (PORT d[10] (1153:1153:1153) (1362:1362:1362)) + (PORT d[11] (711:711:711) (824:824:824)) + (PORT d[12] (981:981:981) (1164:1164:1164)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (843:843:843) (909:909:909)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1300:1300:1300) (1398:1398:1398)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (902:902:902) (1014:1014:1014)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1392:1392:1392) (1595:1595:1595)) + (PORT d[1] (913:913:913) (1065:1065:1065)) + (PORT d[2] (1787:1787:1787) (2044:2044:2044)) + (PORT d[3] (1291:1291:1291) (1509:1509:1509)) + (PORT d[4] (2323:2323:2323) (2697:2697:2697)) + (PORT d[5] (1755:1755:1755) (2013:2013:2013)) + (PORT d[6] (1285:1285:1285) (1484:1484:1484)) + (PORT d[7] (1222:1222:1222) (1410:1410:1410)) + (PORT d[8] (1508:1508:1508) (1737:1737:1737)) + (PORT d[9] (1933:1933:1933) (2234:2234:2234)) + (PORT d[10] (1157:1157:1157) (1360:1360:1360)) + (PORT d[11] (1570:1570:1570) (1795:1795:1795)) + (PORT d[12] (1075:1075:1075) (1271:1271:1271)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1015:1015:1015) (1110:1110:1110)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (1759:1759:1759) (1911:1911:1911)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1043:1043:1043) (1063:1063:1063)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (505:505:505) (580:580:580)) + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2331:2331:2331) (2655:2655:2655)) + (PORT d[1] (2366:2366:2366) (2714:2714:2714)) + (PORT d[2] (2323:2323:2323) (2648:2648:2648)) + (PORT d[3] (2312:2312:2312) (2642:2642:2642)) + (PORT d[4] (2393:2393:2393) (2738:2738:2738)) + (PORT d[5] (2530:2530:2530) (2956:2956:2956)) + (PORT d[6] (2448:2448:2448) (2794:2794:2794)) + (PORT d[7] (2335:2335:2335) (2701:2701:2701)) + (PORT d[8] (2347:2347:2347) (2643:2643:2643)) + (PORT d[9] (2280:2280:2280) (2580:2580:2580)) + (PORT d[10] (2271:2271:2271) (2555:2555:2555)) + (PORT d[11] (2282:2282:2282) (2574:2574:2574)) + (PORT d[12] (2410:2410:2410) (2724:2724:2724)) + (PORT clk (1045:1045:1045) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1682:1682:1682) (1910:1910:1910)) + (PORT d[1] (1715:1715:1715) (1944:1944:1944)) + (PORT d[2] (1500:1500:1500) (1708:1708:1708)) + (PORT d[3] (653:653:653) (746:746:746)) + (PORT d[4] (1698:1698:1698) (1991:1991:1991)) + (PORT d[5] (1749:1749:1749) (1982:1982:1982)) + (PORT d[6] (2341:2341:2341) (2699:2699:2699)) + (PORT d[7] (950:950:950) (1077:1077:1077)) + (PORT d[8] (2264:2264:2264) (2625:2625:2625)) + (PORT d[9] (2638:2638:2638) (3037:3037:3037)) + (PORT d[10] (737:737:737) (851:851:851)) + (PORT d[11] (2124:2124:2124) (2428:2428:2428)) + (PORT d[12] (531:531:531) (610:610:610)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (543:543:543) (584:584:584)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~19) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (834:834:834)) + (PORT datab (857:857:857) (1005:1005:1005)) + (PORT datac (834:834:834) (954:954:954)) + (PORT datad (638:638:638) (737:737:737)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (520:520:520) (594:594:594)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (376:376:376) (434:434:434)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -41760,20 +41335,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1789:1789:1789) (2110:2110:2110)) - (PORT d[1] (922:922:922) (1066:1066:1066)) - (PORT d[2] (557:557:557) (647:647:647)) - (PORT d[3] (529:529:529) (616:616:616)) - (PORT d[4] (636:636:636) (733:733:733)) - (PORT d[5] (523:523:523) (605:605:605)) - (PORT d[6] (906:906:906) (1049:1049:1049)) - (PORT d[7] (533:533:533) (620:620:620)) - (PORT d[8] (725:725:725) (849:849:849)) - (PORT d[9] (441:441:441) (514:514:514)) - (PORT d[10] (414:414:414) (481:481:481)) - (PORT d[11] (1438:1438:1438) (1677:1677:1677)) - (PORT d[12] (604:604:604) (705:705:705)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1593:1593:1593) (1824:1824:1824)) + (PORT d[1] (1108:1108:1108) (1288:1288:1288)) + (PORT d[2] (2188:2188:2188) (2504:2504:2504)) + (PORT d[3] (1079:1079:1079) (1267:1267:1267)) + (PORT d[4] (741:741:741) (858:858:858)) + (PORT d[5] (866:866:866) (1004:1004:1004)) + (PORT d[6] (739:739:739) (861:861:861)) + (PORT d[7] (856:856:856) (981:981:981)) + (PORT d[8] (2059:2059:2059) (2364:2364:2364)) + (PORT d[9] (1158:1158:1158) (1331:1331:1331)) + (PORT d[10] (841:841:841) (984:984:984)) + (PORT d[11] (549:549:549) (633:633:633)) + (PORT d[12] (953:953:953) (1117:1117:1117)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -41785,8 +41360,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (505:505:505) (528:528:528)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (782:782:782) (843:843:843)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -41798,8 +41373,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (1133:1133:1133) (1212:1212:1212)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (812:812:812) (850:850:850)) ) ) ) @@ -41808,7 +41383,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -41818,7 +41393,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -41828,7 +41403,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -41838,7 +41413,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -41848,7 +41423,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1088:1088:1088)) + (PORT clk (1072:1072:1072) (1089:1089:1089)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -41862,7 +41437,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (612:612:612) (621:621:621)) ) ) ) @@ -41871,7 +41446,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (613:613:613) (622:622:622)) ) ) ) @@ -41880,7 +41455,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (613:613:613) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -41890,7 +41465,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (613:613:613) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -41900,7 +41475,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (556:556:556) (638:638:638)) + (PORT d[0] (560:560:560) (640:640:640)) (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) @@ -41913,19 +41488,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1763:1763:1763) (2080:2080:2080)) - (PORT d[1] (1091:1091:1091) (1257:1257:1257)) - (PORT d[2] (720:720:720) (825:825:825)) - (PORT d[3] (711:711:711) (823:823:823)) - (PORT d[4] (825:825:825) (948:948:948)) - (PORT d[5] (363:363:363) (421:421:421)) - (PORT d[6] (1069:1069:1069) (1235:1235:1235)) - (PORT d[7] (1705:1705:1705) (1949:1949:1949)) - (PORT d[8] (720:720:720) (839:839:839)) - (PORT d[9] (566:566:566) (657:657:657)) - (PORT d[10] (405:405:405) (472:472:472)) - (PORT d[11] (1460:1460:1460) (1706:1706:1706)) - (PORT d[12] (438:438:438) (516:516:516)) + (PORT d[0] (1422:1422:1422) (1631:1631:1631)) + (PORT d[1] (927:927:927) (1087:1087:1087)) + (PORT d[2] (1994:1994:1994) (2283:2283:2283)) + (PORT d[3] (1090:1090:1090) (1276:1276:1276)) + (PORT d[4] (942:942:942) (1096:1096:1096)) + (PORT d[5] (1165:1165:1165) (1333:1333:1333)) + (PORT d[6] (873:873:873) (1008:1008:1008)) + (PORT d[7] (1019:1019:1019) (1170:1170:1170)) + (PORT d[8] (1856:1856:1856) (2130:2130:2130)) + (PORT d[9] (2298:2298:2298) (2651:2651:2651)) + (PORT d[10] (1141:1141:1141) (1356:1356:1356)) + (PORT d[11] (1367:1367:1367) (1570:1570:1570)) + (PORT d[12] (984:984:984) (1163:1163:1163)) (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) @@ -41938,7 +41513,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (508:508:508) (531:531:531)) + (PORT d[0] (680:680:680) (722:722:722)) (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) @@ -41952,7 +41527,7 @@ (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (991:991:991) (1055:1055:1055)) + (PORT d[0] (984:984:984) (1042:1042:1042)) ) ) ) @@ -42050,499 +41625,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~62) + (INSTANCE Selector14\~10) (DELAY (ABSOLUTE - (PORT dataa (582:582:582) (697:697:697)) - (PORT datab (519:519:519) (617:617:617)) - (PORT datac (493:493:493) (556:556:556)) - (PORT datad (527:527:527) (600:600:600)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (789:789:789) (888:888:888)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1666:1666:1666)) - (PORT d[1] (1430:1430:1430) (1615:1615:1615)) - (PORT d[2] (1502:1502:1502) (1743:1743:1743)) - (PORT d[3] (2695:2695:2695) (3058:3058:3058)) - (PORT d[4] (1651:1651:1651) (1897:1897:1897)) - (PORT d[5] (1788:1788:1788) (2036:2036:2036)) - (PORT d[6] (813:813:813) (919:919:919)) - (PORT d[7] (781:781:781) (878:878:878)) - (PORT d[8] (1405:1405:1405) (1633:1633:1633)) - (PORT d[9] (939:939:939) (1059:1059:1059)) - (PORT d[10] (1457:1457:1457) (1645:1645:1645)) - (PORT d[11] (2158:2158:2158) (2516:2516:2516)) - (PORT d[12] (1423:1423:1423) (1606:1606:1606)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1107:1107:1107) (1194:1194:1194)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1065:1065:1065) (1125:1125:1125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (775:775:775)) - (PORT datab (865:865:865) (1022:1022:1022)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (749:749:749) (848:848:848)) + (PORT dataa (351:351:351) (409:409:409)) + (PORT datac (599:599:599) (700:700:700)) + (PORT datad (509:509:509) (579:579:579)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (870:870:870) (1008:1008:1008)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1432:1432:1432) (1667:1667:1667)) - (PORT d[1] (1238:1238:1238) (1414:1414:1414)) - (PORT d[2] (1398:1398:1398) (1616:1616:1616)) - (PORT d[3] (1224:1224:1224) (1399:1399:1399)) - (PORT d[4] (1159:1159:1159) (1354:1354:1354)) - (PORT d[5] (1331:1331:1331) (1523:1523:1523)) - (PORT d[6] (1337:1337:1337) (1536:1536:1536)) - (PORT d[7] (1984:1984:1984) (2268:2268:2268)) - (PORT d[8] (1616:1616:1616) (1855:1855:1855)) - (PORT d[9] (1220:1220:1220) (1409:1409:1409)) - (PORT d[10] (2067:2067:2067) (2374:2374:2374)) - (PORT d[11] (1226:1226:1226) (1423:1423:1423)) - (PORT d[12] (1176:1176:1176) (1359:1359:1359)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1108:1108:1108) (1198:1198:1198)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (1832:1832:1832) (2014:2014:2014)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1053:1053:1053) (1072:1072:1072)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1210:1210:1210) (1374:1374:1374)) - (PORT clk (1058:1058:1058) (1075:1075:1075)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2428:2428:2428) (2747:2747:2747)) - (PORT d[1] (2529:2529:2529) (2872:2872:2872)) - (PORT d[2] (2532:2532:2532) (2867:2867:2867)) - (PORT d[3] (2436:2436:2436) (2773:2773:2773)) - (PORT d[4] (2480:2480:2480) (2803:2803:2803)) - (PORT d[5] (2512:2512:2512) (2846:2846:2846)) - (PORT d[6] (2583:2583:2583) (2909:2909:2909)) - (PORT d[7] (2411:2411:2411) (2705:2705:2705)) - (PORT d[8] (2497:2497:2497) (2839:2839:2839)) - (PORT d[9] (2499:2499:2499) (2822:2822:2822)) - (PORT d[10] (2475:2475:2475) (2812:2812:2812)) - (PORT d[11] (2485:2485:2485) (2832:2832:2832)) - (PORT d[12] (2403:2403:2403) (2691:2691:2691)) - (PORT clk (1055:1055:1055) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1076:1076:1076)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1143:1143:1143) (1345:1345:1345)) - (PORT d[1] (1231:1231:1231) (1379:1379:1379)) - (PORT d[2] (1305:1305:1305) (1517:1517:1517)) - (PORT d[3] (963:963:963) (1098:1098:1098)) - (PORT d[4] (1296:1296:1296) (1502:1502:1502)) - (PORT d[5] (1585:1585:1585) (1801:1801:1801)) - (PORT d[6] (971:971:971) (1110:1110:1110)) - (PORT d[7] (1117:1117:1117) (1259:1259:1259)) - (PORT d[8] (1214:1214:1214) (1419:1419:1419)) - (PORT d[9] (1135:1135:1135) (1279:1279:1279)) - (PORT d[10] (1424:1424:1424) (1605:1605:1605)) - (PORT d[11] (2521:2521:2521) (2926:2926:2926)) - (PORT d[12] (1230:1230:1230) (1385:1385:1385)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1193:1193:1193) (1312:1312:1312)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE Selector14\~11) (DELAY (ABSOLUTE - (PORT dataa (499:499:499) (581:581:581)) - (PORT datab (434:434:434) (524:524:524)) - (PORT datac (672:672:672) (762:762:762)) - (PORT datad (937:937:937) (1068:1068:1068)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (682:682:682) (808:808:808)) + (PORT datab (709:709:709) (840:840:840)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (114:114:114) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -42552,8 +41658,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (824:824:824) (935:935:935)) - (PORT clk (1104:1104:1104) (1120:1120:1120)) + (PORT d[0] (880:880:880) (994:994:994)) + (PORT clk (1083:1083:1083) (1102:1102:1102)) ) ) (TIMINGCHECK @@ -42565,20 +41671,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1246:1246:1246) (1453:1453:1453)) - (PORT d[1] (1533:1533:1533) (1747:1747:1747)) - (PORT d[2] (1382:1382:1382) (1587:1587:1587)) - (PORT d[3] (1754:1754:1754) (1982:1982:1982)) - (PORT d[4] (1292:1292:1292) (1525:1525:1525)) - (PORT d[5] (1953:1953:1953) (2224:2224:2224)) - (PORT d[6] (1460:1460:1460) (1664:1664:1664)) - (PORT d[7] (1682:1682:1682) (1928:1928:1928)) - (PORT d[8] (1491:1491:1491) (1707:1707:1707)) - (PORT d[9] (1734:1734:1734) (1973:1973:1973)) - (PORT d[10] (1297:1297:1297) (1480:1480:1480)) - (PORT d[11] (1261:1261:1261) (1482:1482:1482)) - (PORT d[12] (2080:2080:2080) (2363:2363:2363)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) + (PORT d[0] (1224:1224:1224) (1406:1406:1406)) + (PORT d[1] (1110:1110:1110) (1290:1290:1290)) + (PORT d[2] (1805:1805:1805) (2067:2067:2067)) + (PORT d[3] (1281:1281:1281) (1495:1495:1495)) + (PORT d[4] (2490:2490:2490) (2884:2884:2884)) + (PORT d[5] (1753:1753:1753) (2008:2008:2008)) + (PORT d[6] (1270:1270:1270) (1461:1461:1461)) + (PORT d[7] (1209:1209:1209) (1389:1389:1389)) + (PORT d[8] (1679:1679:1679) (1933:1933:1933)) + (PORT d[9] (2101:2101:2101) (2427:2427:2427)) + (PORT d[10] (1162:1162:1162) (1365:1365:1365)) + (PORT d[11] (1570:1570:1570) (1795:1795:1795)) + (PORT d[12] (985:985:985) (1165:1165:1165)) + (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) (TIMINGCHECK @@ -42590,8 +41696,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1479:1479:1479) (1610:1610:1610)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) + (PORT d[0] (946:946:946) (1019:1019:1019)) + (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) (TIMINGCHECK @@ -42603,8 +41709,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1120:1120:1120)) - (PORT d[0] (2172:2172:2172) (2012:2012:2012)) + (PORT clk (1083:1083:1083) (1102:1102:1102)) + (PORT d[0] (1896:1896:1896) (1772:1772:1772)) ) ) ) @@ -42613,7 +41719,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) + (PORT clk (1084:1084:1084) (1103:1103:1103)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -42623,7 +41729,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) + (PORT clk (1084:1084:1084) (1103:1103:1103)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -42633,7 +41739,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) + (PORT clk (1084:1084:1084) (1103:1103:1103)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -42643,7 +41749,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) + (PORT clk (1084:1084:1084) (1103:1103:1103)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -42653,7 +41759,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) + (PORT clk (1038:1038:1038) (1059:1059:1059)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -42667,8 +41773,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1208:1208:1208) (1346:1346:1346)) - (PORT clk (1064:1064:1064) (1080:1080:1080)) + (PORT d[0] (560:560:560) (653:653:653)) + (PORT clk (1043:1043:1043) (1062:1062:1062)) ) ) (TIMINGCHECK @@ -42680,20 +41786,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2496:2496:2496) (2811:2811:2811)) - (PORT d[1] (2480:2480:2480) (2802:2802:2802)) - (PORT d[2] (2465:2465:2465) (2778:2778:2778)) - (PORT d[3] (2451:2451:2451) (2772:2772:2772)) - (PORT d[4] (2409:2409:2409) (2745:2745:2745)) - (PORT d[5] (2500:2500:2500) (2815:2815:2815)) - (PORT d[6] (2408:2408:2408) (2701:2701:2701)) - (PORT d[7] (2474:2474:2474) (2784:2784:2784)) - (PORT d[8] (2466:2466:2466) (2800:2800:2800)) - (PORT d[9] (2430:2430:2430) (2745:2745:2745)) - (PORT d[10] (2378:2378:2378) (2673:2673:2673)) - (PORT d[11] (2490:2490:2490) (2812:2812:2812)) - (PORT d[12] (2371:2371:2371) (2676:2676:2676)) - (PORT clk (1061:1061:1061) (1079:1079:1079)) + (PORT d[0] (2394:2394:2394) (2730:2730:2730)) + (PORT d[1] (2375:2375:2375) (2748:2748:2748)) + (PORT d[2] (2330:2330:2330) (2643:2643:2643)) + (PORT d[3] (2347:2347:2347) (2681:2681:2681)) + (PORT d[4] (2345:2345:2345) (2684:2684:2684)) + (PORT d[5] (2512:2512:2512) (2932:2932:2932)) + (PORT d[6] (2460:2460:2460) (2857:2857:2857)) + (PORT d[7] (2481:2481:2481) (2839:2839:2839)) + (PORT d[8] (2348:2348:2348) (2643:2643:2643)) + (PORT d[9] (2262:2262:2262) (2555:2555:2555)) + (PORT d[10] (2296:2296:2296) (2591:2591:2591)) + (PORT d[11] (2339:2339:2339) (2677:2677:2677)) + (PORT d[12] (2386:2386:2386) (2692:2692:2692)) + (PORT clk (1040:1040:1040) (1061:1061:1061)) ) ) (TIMINGCHECK @@ -42705,7 +41811,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1064:1064:1064) (1080:1080:1080)) + (PORT clk (1043:1043:1043) (1062:1062:1062)) ) ) ) @@ -42714,7 +41820,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) + (PORT clk (1044:1044:1044) (1063:1063:1063)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -42724,7 +41830,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) + (PORT clk (1044:1044:1044) (1063:1063:1063)) (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) ) ) @@ -42734,7 +41840,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) + (PORT clk (1044:1044:1044) (1063:1063:1063)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -42744,7 +41850,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) + (PORT clk (1044:1044:1044) (1063:1063:1063)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -42754,7 +41860,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) + (PORT clk (1039:1039:1039) (1060:1060:1060)) (IOPATH (posedge clk) q (164:164:164) (166:166:166)) ) ) @@ -42768,20 +41874,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1318:1318:1318) (1537:1537:1537)) - (PORT d[1] (608:608:608) (684:684:684)) - (PORT d[2] (1510:1510:1510) (1728:1728:1728)) - (PORT d[3] (2694:2694:2694) (3050:3050:3050)) - (PORT d[4] (563:563:563) (652:652:652)) - (PORT d[5] (1213:1213:1213) (1370:1370:1370)) - (PORT d[6] (1644:1644:1644) (1873:1873:1873)) - (PORT d[7] (776:776:776) (875:875:875)) - (PORT d[8] (1565:1565:1565) (1818:1818:1818)) - (PORT d[9] (829:829:829) (936:936:936)) - (PORT d[10] (1144:1144:1144) (1293:1293:1293)) - (PORT d[11] (2167:2167:2167) (2529:2529:2529)) - (PORT d[12] (956:956:956) (1078:1078:1078)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (883:883:883) (1016:1016:1016)) + (PORT d[1] (970:970:970) (1111:1111:1111)) + (PORT d[2] (693:693:693) (796:796:796)) + (PORT d[3] (1640:1640:1640) (1889:1889:1889)) + (PORT d[4] (1299:1299:1299) (1514:1514:1514)) + (PORT d[5] (681:681:681) (784:784:784)) + (PORT d[6] (685:685:685) (794:794:794)) + (PORT d[7] (867:867:867) (997:997:997)) + (PORT d[8] (954:954:954) (1094:1094:1094)) + (PORT d[9] (1014:1014:1014) (1164:1164:1164)) + (PORT d[10] (1414:1414:1414) (1632:1632:1632)) + (PORT d[11] (1126:1126:1126) (1285:1285:1285)) + (PORT d[12] (977:977:977) (1147:1147:1147)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -42793,8 +41899,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (817:817:817) (748:748:748)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1023:1023:1023) (923:923:923)) ) ) ) @@ -42803,7 +41909,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -42813,7 +41919,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) + (PORT clk (1071:1071:1071) (1087:1087:1087)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -42827,7 +41933,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) + (PORT clk (611:611:611) (619:619:619)) ) ) ) @@ -42836,7 +41942,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) + (PORT clk (612:612:612) (620:620:620)) ) ) ) @@ -42845,7 +41951,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) + (PORT clk (612:612:612) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -42855,38 +41961,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) + (PORT clk (612:612:612) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE Selector14\~20) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (734:734:734)) - (PORT datab (518:518:518) (592:592:592)) - (PORT datac (556:556:556) (650:650:650)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (434:434:434) (524:524:524)) - (PORT datac (1049:1049:1049) (1206:1206:1206)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (962:962:962) (1122:1122:1122)) + (PORT datab (830:830:830) (965:965:965)) + (PORT datac (692:692:692) (794:794:794)) + (PORT datad (863:863:863) (992:992:992)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -42894,15 +41984,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~120) + (INSTANCE Selector14\~9) (DELAY (ABSOLUTE - (PORT dataa (938:938:938) (1088:1088:1088)) - (PORT datab (1718:1718:1718) (2022:2022:2022)) + (PORT dataa (635:635:635) (744:744:744)) + (PORT datab (551:551:551) (645:645:645)) (PORT datac (90:90:90) (111:111:111)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT datad (112:112:112) (135:135:135)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -42910,45 +42000,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~64) + (INSTANCE Selector14\~12) (DELAY (ABSOLUTE - (PORT dataa (511:511:511) (590:590:590)) - (PORT datab (489:489:489) (566:566:566)) - (PORT datac (905:905:905) (1026:1026:1026)) - (PORT datad (95:95:95) (113:113:113)) + (PORT dataa (195:195:195) (234:234:234)) + (PORT datab (130:130:130) (163:163:163)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~65) + (INSTANCE Selector14\~14) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (788:788:788)) - (PORT datab (1681:1681:1681) (1921:1921:1921)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (792:792:792) (907:907:907)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (1144:1144:1144) (1322:1322:1322)) + (PORT datac (940:940:940) (1063:1063:1063)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (496:496:496)) + (PORT datab (494:494:494) (580:580:580)) + (PORT datac (1036:1036:1036) (1181:1181:1181)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (741:741:741)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (192:192:192) (229:229:229)) - (PORT datad (619:619:619) (708:708:708)) + (PORT dataa (451:451:451) (546:546:546)) + (PORT datab (822:822:822) (966:966:966)) + (PORT datac (975:975:975) (1098:1098:1098)) + (PORT datad (117:117:117) (148:148:148)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -42961,9 +42067,9 @@ (INSTANCE z80_\|data_pins_\|dout\[0\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) + (PORT clk (912:912:912) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -42974,30 +42080,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (INSTANCE z80_\|bus_control_\|db\[0\]\~11) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (168:168:168)) - (PORT datac (119:119:119) (148:148:148)) - (PORT datad (1184:1184:1184) (1351:1351:1351)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (501:501:501) (583:583:583)) + (PORT datab (514:514:514) (591:591:591)) + (PORT datac (779:779:779) (901:901:901)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (INSTANCE z80_\|bus_control_\|db\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (796:796:796) (905:905:905)) - (PORT datac (601:601:601) (693:693:693)) - (PORT datad (116:116:116) (139:139:139)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT dataa (125:125:125) (161:161:161)) + (PORT datab (462:462:462) (571:571:571)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (131:131:131) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -43005,12 +42113,3724 @@ (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (902:902:902) (888:888:888)) + (PORT ena (996:996:996) (1107:1107:1107)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (694:694:694)) + (PORT datab (619:619:619) (750:750:750)) + (PORT datac (950:950:950) (1099:1099:1099)) + (PORT datad (439:439:439) (509:509:509)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (499:499:499)) + (PORT datab (1062:1062:1062) (1261:1261:1261)) + (PORT datac (519:519:519) (603:603:603)) + (PORT datad (387:387:387) (480:480:480)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT datab (307:307:307) (358:358:358)) + (PORT datac (634:634:634) (742:742:742)) + (PORT datad (676:676:676) (799:799:799)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (1594:1594:1594) (1875:1875:1875)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (344:344:344) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (243:243:243)) + (PORT datab (770:770:770) (941:941:941)) + (PORT datac (455:455:455) (536:536:536)) + (PORT datad (976:976:976) (1144:1144:1144)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (570:570:570)) + (PORT datab (372:372:372) (435:435:435)) + (PORT datac (318:318:318) (368:368:368)) + (PORT datad (118:118:118) (142:142:142)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (1024:1024:1024)) + (PORT datab (604:604:604) (693:693:693)) + (PORT datac (1022:1022:1022) (1186:1186:1186)) + (PORT datad (988:988:988) (1139:1139:1139)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1122:1122:1122)) + (PORT datab (351:351:351) (411:411:411)) + (PORT datac (286:286:286) (327:327:327)) + (PORT datad (589:589:589) (670:670:670)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (509:509:509)) + (PORT datab (328:328:328) (384:384:384)) + (PORT datad (433:433:433) (496:496:496)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (427:427:427)) + (PORT datab (314:314:314) (369:369:369)) + (PORT datac (338:338:338) (401:401:401)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (548:548:548)) + (PORT datab (330:330:330) (389:389:389)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (327:327:327) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (542:542:542)) + (PORT datab (296:296:296) (344:344:344)) + (PORT datac (375:375:375) (452:452:452)) + (PORT datad (618:618:618) (713:713:713)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (568:568:568)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (320:320:320) (373:373:373)) + (PORT datad (280:280:280) (325:325:325)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1690:1690:1690) (1925:1925:1925)) + (PORT d[1] (1203:1203:1203) (1385:1385:1385)) + (PORT d[2] (1542:1542:1542) (1754:1754:1754)) + (PORT d[3] (1341:1341:1341) (1548:1548:1548)) + (PORT d[4] (1974:1974:1974) (2302:2302:2302)) + (PORT d[5] (1492:1492:1492) (1699:1699:1699)) + (PORT d[6] (1626:1626:1626) (1883:1883:1883)) + (PORT d[7] (1577:1577:1577) (1811:1811:1811)) + (PORT d[8] (1172:1172:1172) (1355:1355:1355)) + (PORT d[9] (1457:1457:1457) (1675:1675:1675)) + (PORT d[10] (1167:1167:1167) (1371:1371:1371)) + (PORT d[11] (1323:1323:1323) (1513:1513:1513)) + (PORT d[12] (1079:1079:1079) (1264:1264:1264)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1117:1117:1117)) + (PORT d[0] (1625:1625:1625) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1098:1098:1098)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (623:623:623) (631:631:631)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (623:623:623) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (623:623:623) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (925:925:925) (1070:1070:1070)) + (PORT clk (1105:1105:1105) (1123:1123:1123)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2149:2149:2149) (2438:2438:2438)) + (PORT d[1] (2641:2641:2641) (3002:3002:3002)) + (PORT d[2] (1742:1742:1742) (1970:1970:1970)) + (PORT d[3] (1697:1697:1697) (1982:1982:1982)) + (PORT d[4] (1836:1836:1836) (2140:2140:2140)) + (PORT d[5] (1661:1661:1661) (1891:1891:1891)) + (PORT d[6] (1930:1930:1930) (2224:2224:2224)) + (PORT d[7] (2236:2236:2236) (2531:2531:2531)) + (PORT d[8] (1525:1525:1525) (1782:1782:1782)) + (PORT d[9] (1891:1891:1891) (2183:2183:2183)) + (PORT d[10] (1350:1350:1350) (1594:1594:1594)) + (PORT d[11] (1349:1349:1349) (1541:1541:1541)) + (PORT d[12] (1358:1358:1358) (1603:1603:1603)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1265:1265:1265) (1376:1376:1376)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1123:1123:1123)) + (PORT d[0] (2704:2704:2704) (2967:2967:2967)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1080:1080:1080)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (778:778:778) (875:875:875)) + (PORT clk (1065:1065:1065) (1083:1083:1083)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2344:2344:2344) (2676:2676:2676)) + (PORT d[1] (2408:2408:2408) (2781:2781:2781)) + (PORT d[2] (2338:2338:2338) (2649:2649:2649)) + (PORT d[3] (2368:2368:2368) (2676:2676:2676)) + (PORT d[4] (2311:2311:2311) (2622:2622:2622)) + (PORT d[5] (2398:2398:2398) (2772:2772:2772)) + (PORT d[6] (2387:2387:2387) (2754:2754:2754)) + (PORT d[7] (2483:2483:2483) (2872:2872:2872)) + (PORT d[8] (2350:2350:2350) (2668:2668:2668)) + (PORT d[9] (2370:2370:2370) (2681:2681:2681)) + (PORT d[10] (2343:2343:2343) (2654:2654:2654)) + (PORT d[11] (2378:2378:2378) (2707:2707:2707)) + (PORT d[12] (2349:2349:2349) (2673:2673:2673)) + (PORT clk (1062:1062:1062) (1082:1082:1082)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1083:1083:1083)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2064:2064:2064) (2349:2349:2349)) + (PORT d[1] (2097:2097:2097) (2382:2382:2382)) + (PORT d[2] (1947:1947:1947) (2209:2209:2209)) + (PORT d[3] (2023:2023:2023) (2352:2352:2352)) + (PORT d[4] (1685:1685:1685) (1973:1973:1973)) + (PORT d[5] (1533:1533:1533) (1752:1752:1752)) + (PORT d[6] (1811:1811:1811) (2101:2101:2101)) + (PORT d[7] (2614:2614:2614) (2964:2964:2964)) + (PORT d[8] (1891:1891:1891) (2202:2202:2202)) + (PORT d[9] (2280:2280:2280) (2632:2632:2632)) + (PORT d[10] (1837:1837:1837) (2139:2139:2139)) + (PORT d[11] (1731:1731:1731) (1978:1978:1978)) + (PORT d[12] (1202:1202:1202) (1427:1427:1427)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (2825:2825:2825) (2536:2536:2536)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1073:1073:1073) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (812:812:812) (909:909:909)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2157:2157:2157) (2443:2443:2443)) + (PORT d[1] (2308:2308:2308) (2626:2626:2626)) + (PORT d[2] (1762:1762:1762) (2001:2001:2001)) + (PORT d[3] (1839:1839:1839) (2142:2142:2142)) + (PORT d[4] (1992:1992:1992) (2313:2313:2313)) + (PORT d[5] (1711:1711:1711) (1953:1953:1953)) + (PORT d[6] (1768:1768:1768) (2045:2045:2045)) + (PORT d[7] (2499:2499:2499) (2825:2825:2825)) + (PORT d[8] (1715:1715:1715) (2000:2000:2000)) + (PORT d[9] (1914:1914:1914) (2210:2210:2210)) + (PORT d[10] (1612:1612:1612) (1896:1896:1896)) + (PORT d[11] (1384:1384:1384) (1587:1587:1587)) + (PORT d[12] (1404:1404:1404) (1632:1632:1632)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1210:1210:1210) (1311:1311:1311)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (3132:3132:3132) (2878:2878:2878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1074:1074:1074)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (762:762:762) (860:860:860)) + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2368:2368:2368) (2671:2671:2671)) + (PORT d[1] (2430:2430:2430) (2791:2791:2791)) + (PORT d[2] (2294:2294:2294) (2606:2606:2606)) + (PORT d[3] (2263:2263:2263) (2562:2562:2562)) + (PORT d[4] (2368:2368:2368) (2667:2667:2667)) + (PORT d[5] (2425:2425:2425) (2836:2836:2836)) + (PORT d[6] (2461:2461:2461) (2843:2843:2843)) + (PORT d[7] (2448:2448:2448) (2827:2827:2827)) + (PORT d[8] (2331:2331:2331) (2648:2648:2648)) + (PORT d[9] (2362:2362:2362) (2678:2678:2678)) + (PORT d[10] (2260:2260:2260) (2557:2557:2557)) + (PORT d[11] (2402:2402:2402) (2741:2741:2741)) + (PORT d[12] (2320:2320:2320) (2638:2638:2638)) + (PORT clk (1056:1056:1056) (1076:1076:1076)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1075:1075:1075)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (567:567:567)) + (PORT datab (911:911:911) (1042:1042:1042)) + (PORT datac (642:642:642) (735:735:735)) + (PORT datad (675:675:675) (791:791:791)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (759:759:759)) + (PORT datab (561:561:561) (666:666:666)) + (PORT datac (895:895:895) (1016:1016:1016)) + (PORT datad (308:308:308) (357:357:357)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (546:546:546) (620:620:620)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1415:1415:1415) (1622:1622:1622)) + (PORT d[1] (1245:1245:1245) (1441:1441:1441)) + (PORT d[2] (1972:1972:1972) (2258:2258:2258)) + (PORT d[3] (1248:1248:1248) (1454:1454:1454)) + (PORT d[4] (2498:2498:2498) (2892:2892:2892)) + (PORT d[5] (1184:1184:1184) (1366:1366:1366)) + (PORT d[6] (1093:1093:1093) (1267:1267:1267)) + (PORT d[7] (1176:1176:1176) (1349:1349:1349)) + (PORT d[8] (1688:1688:1688) (1941:1941:1941)) + (PORT d[9] (2123:2123:2123) (2453:2453:2453)) + (PORT d[10] (1152:1152:1152) (1362:1362:1362)) + (PORT d[11] (1345:1345:1345) (1545:1545:1545)) + (PORT d[12] (1006:1006:1006) (1192:1192:1192)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (814:814:814) (872:872:872)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (PORT d[0] (1189:1189:1189) (1283:1283:1283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1084:1084:1084)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (617:617:617)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (624:624:624) (698:698:698)) + (PORT clk (1096:1096:1096) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2056:2056:2056) (2340:2340:2340)) + (PORT d[1] (1942:1942:1942) (2207:2207:2207)) + (PORT d[2] (2113:2113:2113) (2397:2397:2397)) + (PORT d[3] (2205:2205:2205) (2560:2560:2560)) + (PORT d[4] (1665:1665:1665) (1945:1945:1945)) + (PORT d[5] (1532:1532:1532) (1749:1749:1749)) + (PORT d[6] (1974:1974:1974) (2281:2281:2281)) + (PORT d[7] (2786:2786:2786) (3158:3158:3158)) + (PORT d[8] (2065:2065:2065) (2395:2395:2395)) + (PORT d[9] (2273:2273:2273) (2617:2617:2617)) + (PORT d[10] (2001:2001:2001) (2326:2326:2326)) + (PORT d[11] (1740:1740:1740) (1987:1987:1987)) + (PORT d[12] (1384:1384:1384) (1637:1637:1637)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (926:926:926) (981:981:981)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1112:1112:1112)) + (PORT d[0] (1628:1628:1628) (1752:1752:1752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (755:755:755) (876:876:876)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (550:550:550) (640:640:640)) + (PORT d[1] (1141:1141:1141) (1300:1300:1300)) + (PORT d[2] (736:736:736) (852:852:852)) + (PORT d[3] (1950:1950:1950) (2245:2245:2245)) + (PORT d[4] (1338:1338:1338) (1563:1563:1563)) + (PORT d[5] (529:529:529) (618:618:618)) + (PORT d[6] (517:517:517) (602:602:602)) + (PORT d[7] (686:686:686) (789:789:789)) + (PORT d[8] (799:799:799) (924:924:924)) + (PORT d[9] (835:835:835) (965:965:965)) + (PORT d[10] (1433:1433:1433) (1653:1653:1653)) + (PORT d[11] (1169:1169:1169) (1339:1339:1339)) + (PORT d[12] (783:783:783) (925:925:925)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1031:1031:1031) (1131:1131:1131)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1414:1414:1414) (1525:1525:1525)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (872:872:872) (981:981:981)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1662:1662:1662) (1887:1887:1887)) + (PORT d[1] (1544:1544:1544) (1749:1749:1749)) + (PORT d[2] (1489:1489:1489) (1698:1698:1698)) + (PORT d[3] (482:482:482) (553:553:553)) + (PORT d[4] (1490:1490:1490) (1737:1737:1737)) + (PORT d[5] (1716:1716:1716) (1942:1942:1942)) + (PORT d[6] (1859:1859:1859) (2159:2159:2159)) + (PORT d[7] (781:781:781) (890:890:890)) + (PORT d[8] (645:645:645) (741:741:741)) + (PORT d[9] (548:548:548) (632:632:632)) + (PORT d[10] (532:532:532) (612:612:612)) + (PORT d[11] (1657:1657:1657) (1875:1875:1875)) + (PORT d[12] (550:550:550) (644:644:644)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1524:1524:1524) (1666:1666:1666)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1499:1499:1499) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (1035:1035:1035)) + (PORT datab (768:768:768) (905:905:905)) + (PORT datac (671:671:671) (772:772:772)) + (PORT datad (789:789:789) (903:903:903)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (899:899:899)) + (PORT datab (771:771:771) (883:883:883)) + (PORT datac (1142:1142:1142) (1328:1328:1328)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (514:514:514)) + (PORT datab (627:627:627) (732:732:732)) + (PORT datac (379:379:379) (460:460:460)) + (PORT datad (371:371:371) (449:449:449)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (697:697:697)) + (PORT datab (785:785:785) (926:926:926)) + (PORT datac (528:528:528) (625:625:625)) + (PORT datad (693:693:693) (813:813:813)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (602:602:602)) + (PORT datab (432:432:432) (533:533:533)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (150:150:150)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1191:1191:1191)) + (PORT datab (671:671:671) (783:783:783)) + (PORT datac (116:116:116) (158:158:158)) + (PORT datad (349:349:349) (422:422:422)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (187:187:187)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (182:182:182)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (195:195:195)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (195:195:195)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (333:333:333) (386:386:386)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston_autofire_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (705:705:705)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (201:201:201)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (201:201:201)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (208:208:208) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (594:594:594)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (131:131:131) (173:173:173)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (279:279:279)) + (PORT datab (210:210:210) (264:264:264)) + (PORT datac (1973:1973:1973) (2229:2229:2229)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (560:560:560) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (470:470:470)) + (PORT datab (221:221:221) (277:277:277)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (129:129:129) (172:172:172)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (199:199:199)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (201:201:201)) + (PORT datab (142:142:142) (194:194:194)) + (PORT datac (128:128:128) (174:174:174)) + (PORT datad (343:343:343) (408:408:408)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (339:339:339)) + (PORT datab (336:336:336) (394:394:394)) + (PORT datac (270:270:270) (313:313:313)) + (PORT datad (322:322:322) (375:375:375)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (401:401:401)) + (PORT datab (1994:1994:1994) (2253:2253:2253)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (980:980:980)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_autofire_enabled\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_autofire_enabled) + (DELAY + (ABSOLUTE + (PORT clk (485:485:485) (439:439:439)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (291:291:291)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (134:134:134) (184:184:184)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[6\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[7\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[8\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (526:526:526) (584:584:584)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[9\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[10\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[11\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[12\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[13\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[14\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[15\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (266:266:266)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (206:206:206) (266:266:266)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (290:290:290)) + (PORT datab (139:139:139) (189:189:189)) + (PORT datac (124:124:124) (167:167:167)) + (PORT datad (125:125:125) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (199:199:199) (245:245:245)) + (PORT datad (122:122:122) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (124:124:124) (169:169:169)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (329:329:329) (388:388:388)) + (PORT datad (297:297:297) (343:343:343)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[16\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[17\]\~49) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (691:691:691) (772:772:772)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire\~0) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT sload (748:748:748) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (581:581:581)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (778:778:778) (897:897:897)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (483:483:483)) + (PORT datab (500:500:500) (596:596:596)) + (PORT datac (512:512:512) (605:605:605)) + (PORT datad (510:510:510) (599:599:599)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (382:382:382)) + (PORT datab (425:425:425) (526:526:526)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (492:492:492)) + (PORT datab (496:496:496) (585:585:585)) + (PORT datac (406:406:406) (494:494:494)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (385:385:385) (470:470:470)) + (PORT datac (507:507:507) (599:599:599)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (647:647:647)) + (PORT datab (426:426:426) (527:527:527)) + (PORT datad (325:325:325) (379:379:379)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (1214:1214:1214) (1431:1431:1431)) + (PORT datac (1413:1413:1413) (1597:1597:1597)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (509:509:509)) + (PORT datab (171:171:171) (232:232:232)) + (PORT datac (788:788:788) (911:911:911)) + (PORT datad (378:378:378) (457:457:457)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (472:472:472) (562:562:562)) + (PORT datad (393:393:393) (484:484:484)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (373:373:373)) + (PORT datab (332:332:332) (386:386:386)) + (PORT datad (539:539:539) (643:643:643)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (496:496:496)) + (PORT datab (247:247:247) (310:310:310)) + (PORT datad (413:413:413) (509:509:509)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (575:575:575)) + (PORT datab (408:408:408) (501:501:501)) + (PORT datac (155:155:155) (211:211:211)) + (PORT datad (391:391:391) (481:481:481)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (242:242:242)) + (PORT datab (416:416:416) (509:509:509)) + (PORT datac (398:398:398) (486:486:486)) + (PORT datad (315:315:315) (365:365:365)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (894:894:894) (900:900:900)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (425:425:425)) + (PORT datab (1319:1319:1319) (1517:1517:1517)) + (PORT datac (347:347:347) (409:409:409)) + (PORT datad (1127:1127:1127) (1339:1339:1339)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (227:227:227)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (484:484:484) (579:579:579)) + (PORT datac (209:209:209) (267:267:267)) + (PORT datad (416:416:416) (512:512:512)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT datab (394:394:394) (485:485:485)) + (PORT datad (383:383:383) (460:460:460)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (433:433:433)) + (PORT datac (376:376:376) (460:460:460)) + (PORT datad (510:510:510) (599:599:599)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (401:401:401)) + (PORT datab (181:181:181) (222:222:222)) + (PORT datad (97:97:97) (116:116:116)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (537:537:537)) + (PORT datab (1284:1284:1284) (1476:1476:1476)) + (PORT datac (525:525:525) (623:623:623)) + (PORT datad (961:961:961) (1115:1115:1115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (573:573:573)) + (PORT datab (457:457:457) (524:524:524)) + (PORT datac (443:443:443) (511:511:511)) + (PORT datad (324:324:324) (377:377:377)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~6) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (397:397:397)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (471:471:471) (544:544:544)) + (PORT datad (967:967:967) (1113:1113:1113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~7) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (451:451:451) (513:513:513)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (930:930:930)) + (PORT datab (608:608:608) (719:719:719)) + (PORT datac (669:669:669) (779:779:779)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (686:686:686)) + (PORT datab (138:138:138) (180:180:180)) + (PORT datac (811:811:811) (950:950:950)) + (PORT datad (496:496:496) (568:568:568)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (180:180:180)) + (PORT datac (345:345:345) (415:415:415)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (614:614:614)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datac (808:808:808) (937:937:937)) + (PORT datad (455:455:455) (538:538:538)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (196:196:196)) + (PORT datad (130:130:130) (159:159:159)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) (DELAY (ABSOLUTE (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (369:369:369) (404:404:404)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1045:1045:1045) (1140:1140:1140)) + (PORT asdata (279:279:279) (298:298:298)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (911:911:911) (1018:1018:1018)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43022,139 +45842,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (INSTANCE z80_\|execute_\|ctl_mRead\~10) (DELAY (ABSOLUTE - (PORT dataa (947:947:947) (1100:1100:1100)) - (PORT datab (745:745:745) (856:856:856)) - (PORT datac (111:111:111) (137:137:137)) - (PORT datad (730:730:730) (821:821:821)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1505:1505:1505)) - (PORT datab (1235:1235:1235) (1455:1455:1455)) - (PORT datac (1253:1253:1253) (1457:1457:1457)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (906:906:906)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (890:890:890)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datac (554:554:554) (653:653:653)) - (PORT datad (833:833:833) (966:966:966)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (565:565:565)) - (PORT datab (945:945:945) (1070:1070:1070)) - (PORT datac (592:592:592) (698:698:698)) - (PORT datad (464:464:464) (546:546:546)) + (PORT dataa (628:628:628) (738:738:738)) + (PORT datab (239:239:239) (299:299:299)) + (PORT datad (370:370:370) (442:442:442)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (405:405:405)) - (PORT datab (671:671:671) (784:784:784)) - (PORT datad (483:483:483) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (451:451:451) (524:524:524)) + (PORT datab (515:515:515) (599:599:599)) + (PORT datac (321:321:321) (386:386:386)) + (PORT datad (290:290:290) (332:332:332)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (721:721:721)) - (PORT datab (337:337:337) (393:393:393)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (325:325:325) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (419:419:419)) - (PORT datab (374:374:374) (453:453:453)) - (PORT datac (831:831:831) (962:962:962)) - (PORT datad (320:320:320) (380:380:380)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (757:757:757)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (334:334:334) (392:392:392)) - (PORT datad (435:435:435) (515:515:515)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43162,62 +45872,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~3) (DELAY (ABSOLUTE - (PORT dataa (691:691:691) (805:805:805)) - (PORT datab (200:200:200) (242:242:242)) - (PORT datac (517:517:517) (615:615:615)) - (PORT datad (763:763:763) (912:912:912)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (787:787:787)) - (PORT datab (846:846:846) (993:993:993)) - (PORT datac (309:309:309) (356:356:356)) - (PORT datad (468:468:468) (540:540:540)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (903:903:903)) - (PORT datab (1243:1243:1243) (1465:1465:1465)) - (PORT datac (889:889:889) (1019:1019:1019)) - (PORT datad (389:389:389) (462:462:462)) + (PORT dataa (493:493:493) (584:584:584)) + (PORT datab (479:479:479) (559:559:559)) + (PORT datac (591:591:591) (671:671:671)) + (PORT datad (617:617:617) (713:713:713)) (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (490:490:490)) - (PORT datab (346:346:346) (406:406:406)) - (PORT datac (886:886:886) (1007:1007:1007)) - (PORT datad (844:844:844) (973:973:973)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -43226,165 +45888,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (INSTANCE z80_\|alu_control_\|db\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (638:638:638) (739:739:739)) + (PORT dataa (651:651:651) (767:767:767)) + (PORT datab (198:198:198) (234:234:234)) + (PORT datad (347:347:347) (412:412:412)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (221:221:221)) + (PORT datab (377:377:377) (452:452:452)) + (PORT datac (306:306:306) (358:358:358)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) (PORT datab (103:103:103) (132:132:132)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (147:147:147)) - (PORT datab (340:340:340) (404:404:404)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (486:486:486) (567:567:567)) - (PORT datac (301:301:301) (347:347:347)) - (PORT datad (424:424:424) (492:492:492)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (371:371:371)) - (PORT datab (316:316:316) (370:370:370)) - (PORT datac (499:499:499) (581:581:581)) - (PORT datad (426:426:426) (494:494:494)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (166:166:166)) - (PORT datab (485:485:485) (566:566:566)) - (PORT datac (351:351:351) (416:416:416)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (719:719:719)) - (PORT datab (645:645:645) (745:745:745)) - (PORT datac (706:706:706) (809:809:809)) - (PORT datad (745:745:745) (865:865:865)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (406:406:406)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (459:459:459) (532:532:532)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (392:392:392)) - (PORT datac (345:345:345) (407:407:407)) - (PORT datad (459:459:459) (529:529:529)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (477:477:477) (560:560:560)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (553:553:553)) - (PORT datab (636:636:636) (736:736:736)) - (PORT datad (197:197:197) (235:235:235)) + (PORT datac (294:294:294) (341:341:341)) + (PORT datad (117:117:117) (140:140:140)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (INSTANCE z80_\|bus_control_\|db\[1\]\~9) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (328:328:328)) - (PORT datac (411:411:411) (497:497:497)) - (PORT datad (203:203:203) (255:255:255)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT dataa (472:472:472) (553:553:553)) + (PORT datac (184:184:184) (215:215:215)) + (PORT datad (737:737:737) (861:861:861)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43392,13 +45948,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (434:434:434)) - (PORT datac (537:537:537) (637:637:637)) - (PORT datad (325:325:325) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (246:246:246) (310:310:310)) + (PORT datac (400:400:400) (487:487:487)) + (PORT datad (384:384:384) (470:470:470)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (412:412:412) (504:504:504)) + (PORT datac (464:464:464) (553:553:553)) + (PORT datad (394:394:394) (481:481:481)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43406,12 +45976,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (139:139:139)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (311:311:311) (356:356:356)) + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datad (95:95:95) (113:113:113)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -43424,9 +45994,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) + (PORT clk (901:901:901) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (888:888:888)) + (PORT clrn (894:894:894) (900:900:900)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43437,12 +46007,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (422:422:422) (511:511:511)) - (PORT datad (103:103:103) (120:120:120)) + (PORT dataa (487:487:487) (557:557:557)) + (PORT datab (543:543:543) (648:648:648)) + (PORT datad (97:97:97) (117:117:117)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -43455,9 +46025,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (895:895:895) (900:900:900)) + (PORT clk (902:902:902) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (887:887:887) (891:891:891)) + (PORT clrn (895:895:895) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43468,28 +46038,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (991:991:991) (1165:1165:1165)) - (PORT datac (1285:1285:1285) (1511:1511:1511)) - (PORT datad (500:500:500) (582:582:582)) + (PORT dataa (367:367:367) (446:446:446)) + (PORT datab (1216:1216:1216) (1433:1433:1433)) + (PORT datac (1412:1412:1412) (1596:1596:1596)) + (PORT datad (332:332:332) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (174:174:174) (242:242:242)) - (PORT datab (361:361:361) (435:435:435)) - (PORT datac (494:494:494) (586:586:586)) - (PORT datad (521:521:521) (622:622:622)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (352:352:352) (414:414:414)) + (PORT datab (432:432:432) (529:529:529)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (653:653:653)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datad (540:540:540) (643:643:643)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1486:1486:1486)) + (PORT datab (202:202:202) (259:259:259)) + (PORT datac (1252:1252:1252) (1438:1438:1438)) + (PORT datad (197:197:197) (247:247:247)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -43498,14 +46132,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~38) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (460:460:460)) - (PORT datab (440:440:440) (536:536:536)) - (PORT datac (562:562:562) (667:667:667)) - (PORT datad (414:414:414) (504:504:504)) - (IOPATH dataa combout (195:195:195) (203:203:203)) + (PORT dataa (927:927:927) (1081:1081:1081)) + (PORT datab (373:373:373) (456:456:456)) + (PORT datac (149:149:149) (208:208:208)) + (PORT datad (137:137:137) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -43514,14 +46148,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) (DELAY (ABSOLUTE - (PORT dataa (384:384:384) (463:463:463)) - (PORT datab (438:438:438) (533:533:533)) - (PORT datac (558:558:558) (663:663:663)) - (PORT datad (411:411:411) (500:500:500)) - (IOPATH dataa combout (170:170:170) (165:165:165)) + (PORT dataa (525:525:525) (628:628:628)) + (PORT datab (398:398:398) (482:482:482)) + (PORT datac (522:522:522) (611:611:611)) + (PORT datad (529:529:529) (626:626:626)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -43533,12 +46167,10 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) (DELAY (ABSOLUTE - (PORT dataa (122:122:122) (155:155:155)) - (PORT datab (577:577:577) (690:690:690)) - (PORT datac (700:700:700) (818:818:818)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (532:532:532) (636:636:636)) + (PORT datac (516:516:516) (604:604:604)) + (PORT datad (385:385:385) (465:465:465)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43546,15 +46178,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) (DELAY (ABSOLUTE - (PORT dataa (394:394:394) (475:475:475)) - (PORT datab (718:718:718) (842:842:842)) - (PORT datac (90:90:90) (110:110:110)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (173:173:173)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (373:373:373) (451:451:451)) + (PORT datac (518:518:518) (610:610:610)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (510:510:510)) + (PORT datab (411:411:411) (504:504:504)) + (PORT datac (153:153:153) (209:209:209)) + (PORT datad (224:224:224) (280:280:280)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (510:510:510)) + (PORT datab (468:468:468) (556:556:556)) + (PORT datac (423:423:423) (482:482:482)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43562,14 +46226,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~39) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (484:484:484)) - (PORT datab (312:312:312) (357:357:357)) - (PORT datad (91:91:91) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (320:320:320) (379:379:379)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (388:388:388) (472:472:472)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43580,9 +46244,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (895:895:895) (900:900:900)) + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (888:888:888) (892:892:892)) + (PORT clrn (889:889:889) (893:893:893)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43593,29 +46257,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (410:410:410) (509:509:509)) - (PORT datab (398:398:398) (486:486:486)) - (PORT datac (401:401:401) (479:479:479)) - (PORT datad (550:550:550) (657:657:657)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (540:540:540) (644:644:644)) - (PORT datac (90:90:90) (113:113:113)) - (PORT datad (274:274:274) (315:315:315)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT datab (430:430:430) (531:531:531)) + (PORT datac (367:367:367) (439:439:439)) + (PORT datad (791:791:791) (915:915:915)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43623,13 +46271,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) (DELAY (ABSOLUTE - (PORT datab (569:569:569) (682:682:682)) - (PORT datac (242:242:242) (305:305:305)) - (PORT datad (496:496:496) (583:583:583)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (417:417:417) (514:514:514)) + (PORT datab (401:401:401) (493:493:493)) + (PORT datac (456:456:456) (541:541:541)) + (PORT datad (217:217:217) (272:272:272)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datac (159:159:159) (215:215:215)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43637,12 +46301,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (186:186:186) (180:180:180)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datad (171:171:171) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43653,9 +46317,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (893:893:893) (899:899:899)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (890:890:890)) + (PORT clrn (890:890:890) (893:893:893)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43666,153 +46330,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~3) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (603:603:603)) - (PORT datab (505:505:505) (589:589:589)) - (PORT datac (343:343:343) (410:410:410)) - (PORT datad (790:790:790) (900:900:900)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (158:158:158)) - (PORT datab (499:499:499) (586:586:586)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (91:91:91) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (336:336:336)) - (PORT datab (508:508:508) (610:610:610)) - (PORT datac (411:411:411) (506:506:506)) - (PORT datad (383:383:383) (464:464:464)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (347:347:347) (409:409:409)) - (PORT datac (513:513:513) (619:619:619)) - (PORT datad (479:479:479) (561:561:561)) + (PORT dataa (1029:1029:1029) (1192:1192:1192)) + (PORT datab (212:212:212) (266:266:266)) + (PORT datac (656:656:656) (761:761:761)) + (PORT datad (118:118:118) (155:155:155)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (264:264:264) (329:329:329)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (889:889:889)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (339:339:339)) - (PORT datab (531:531:531) (638:638:638)) - (PORT datac (411:411:411) (505:505:505)) - (PORT datad (385:385:385) (466:466:466)) - (IOPATH dataa combout (188:188:188) (203:203:203)) + (PORT datab (405:405:405) (500:500:500)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (494:494:494) (577:577:577)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (481:481:481)) - (PORT datab (713:713:713) (835:835:835)) - (PORT datac (404:404:404) (496:496:496)) - (PORT datad (160:160:160) (188:188:188)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (414:414:414) (496:496:496)) - (PORT datac (246:246:246) (309:309:309)) - (PORT datad (491:491:491) (578:578:578)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (405:405:405)) - (PORT datab (171:171:171) (209:209:209)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) + (PORT dataa (398:398:398) (489:489:489)) + (PORT datab (396:396:396) (480:480:480)) + (PORT datac (141:141:141) (189:189:189)) + (PORT datad (390:390:390) (485:485:485)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (487:487:487)) + (PORT datab (231:231:231) (293:293:293)) + (PORT datac (611:611:611) (710:710:710)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (144:144:144)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datad (324:324:324) (376:376:376)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43823,9 +46410,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (893:893:893) (899:899:899)) + (PORT clk (902:902:902) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (890:890:890)) + (PORT clrn (895:895:895) (901:901:901)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43836,15 +46423,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (424:424:424)) - (PORT datab (361:361:361) (430:430:430)) - (PORT datac (368:368:368) (429:429:429)) - (PORT datad (856:856:856) (989:989:989)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (323:323:323) (386:386:386)) + (PORT datab (544:544:544) (644:644:644)) + (PORT datac (506:506:506) (583:583:583)) + (PORT datad (771:771:771) (907:907:907)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43852,28 +46439,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) (DELAY (ABSOLUTE - (PORT datab (709:709:709) (835:835:835)) - (PORT datac (380:380:380) (457:457:457)) - (PORT datad (395:395:395) (469:469:469)) + (PORT datab (430:430:430) (531:531:531)) + (PORT datad (93:93:93) (111:111:111)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (735:735:735) (861:861:861)) - (PORT datab (356:356:356) (421:421:421)) - (PORT datad (322:322:322) (361:361:361)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -43881,12 +46452,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (898:898:898) (903:903:903)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (891:891:891) (894:894:894)) + (PORT clrn (890:890:890) (893:893:893)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43897,44 +46468,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (862:862:862)) - (PORT datab (563:563:563) (661:661:661)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (898:898:898) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (891:891:891) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (1619:1619:1619) (1898:1898:1898)) - (PORT datac (118:118:118) (159:159:159)) - (PORT datad (118:118:118) (155:155:155)) + (PORT dataa (2586:2586:2586) (2978:2978:2978)) + (PORT datab (1845:1845:1845) (2139:2139:2139)) + (PORT datac (341:341:341) (413:413:413)) + (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -43944,27 +46484,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (1372:1372:1372) (1622:1622:1622)) - (PORT datad (306:306:306) (353:353:353)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~4) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (584:584:584)) + (PORT datab (456:456:456) (523:523:523)) + (PORT datac (468:468:468) (540:540:540)) + (PORT datad (838:838:838) (968:968:968)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (724:724:724) (824:824:824)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (367:367:367) (426:426:426)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -43976,20 +46541,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1405:1405:1405) (1668:1668:1668)) - (PORT d[1] (1480:1480:1480) (1671:1671:1671)) - (PORT d[2] (720:720:720) (825:825:825)) - (PORT d[3] (707:707:707) (809:809:809)) - (PORT d[4] (1146:1146:1146) (1313:1313:1313)) - (PORT d[5] (707:707:707) (818:818:818)) - (PORT d[6] (799:799:799) (912:912:912)) - (PORT d[7] (1536:1536:1536) (1765:1765:1765)) - (PORT d[8] (1402:1402:1402) (1652:1652:1652)) - (PORT d[9] (440:440:440) (516:516:516)) - (PORT d[10] (415:415:415) (485:485:485)) - (PORT d[11] (676:676:676) (777:777:777)) - (PORT d[12] (405:405:405) (472:472:472)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (1406:1406:1406) (1614:1614:1614)) + (PORT d[1] (1091:1091:1091) (1272:1272:1272)) + (PORT d[2] (1985:1985:1985) (2270:2270:2270)) + (PORT d[3] (1080:1080:1080) (1264:1264:1264)) + (PORT d[4] (1071:1071:1071) (1238:1238:1238)) + (PORT d[5] (1174:1174:1174) (1344:1344:1344)) + (PORT d[6] (886:886:886) (1027:1027:1027)) + (PORT d[7] (1014:1014:1014) (1167:1167:1167)) + (PORT d[8] (1869:1869:1869) (2145:2145:2145)) + (PORT d[9] (2319:2319:2319) (2679:2679:2679)) + (PORT d[10] (1148:1148:1148) (1357:1357:1357)) + (PORT d[11] (1380:1380:1380) (1591:1591:1591)) + (PORT d[12] (998:998:998) (1182:1182:1182)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -44001,8 +46566,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (697:697:697) (745:745:745)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (659:659:659) (702:702:702)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -44014,8 +46579,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (932:932:932) (979:979:979)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1006:1006:1006) (1075:1075:1075)) ) ) ) @@ -44024,7 +46589,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -44034,7 +46599,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -44044,7 +46609,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -44054,7 +46619,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -44064,7 +46629,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1064:1064:1064) (1081:1081:1081)) + (PORT clk (1071:1071:1071) (1087:1087:1087)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -44078,7 +46643,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (604:604:604) (613:613:613)) + (PORT clk (611:611:611) (619:619:619)) ) ) ) @@ -44087,7 +46652,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) + (PORT clk (612:612:612) (620:620:620)) ) ) ) @@ -44096,7 +46661,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) + (PORT clk (612:612:612) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -44106,7 +46671,174 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~10) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (420:420:420)) + (PORT datac (610:610:610) (718:718:718)) + (PORT datad (844:844:844) (977:977:977)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (471:471:471) (530:530:530)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2045:2045:2045) (2327:2327:2327)) + (PORT d[1] (1933:1933:1933) (2196:2196:2196)) + (PORT d[2] (2124:2124:2124) (2411:2411:2411)) + (PORT d[3] (2213:2213:2213) (2570:2570:2570)) + (PORT d[4] (1839:1839:1839) (2145:2145:2145)) + (PORT d[5] (1533:1533:1533) (1747:1747:1747)) + (PORT d[6] (1987:1987:1987) (2301:2301:2301)) + (PORT d[7] (2780:2780:2780) (3146:3146:3146)) + (PORT d[8] (2074:2074:2074) (2408:2408:2408)) + (PORT d[9] (2273:2273:2273) (2618:2618:2618)) + (PORT d[10] (2019:2019:2019) (2348:2348:2348)) + (PORT d[11] (1896:1896:1896) (2164:2164:2164)) + (PORT d[12] (1372:1372:1372) (1619:1619:1619)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1452:1452:1452) (1593:1593:1593)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1233:1233:1233) (1313:1313:1313)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -44116,7 +46848,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (555:555:555) (637:637:637)) + (PORT d[0] (550:550:550) (642:642:642)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -44129,19 +46861,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1599:1599:1599) (1892:1892:1892)) - (PORT d[1] (1108:1108:1108) (1278:1278:1278)) - (PORT d[2] (545:545:545) (633:633:633)) - (PORT d[3] (531:531:531) (614:614:614)) - (PORT d[4] (799:799:799) (913:913:913)) - (PORT d[5] (517:517:517) (599:599:599)) - (PORT d[6] (626:626:626) (718:718:718)) - (PORT d[7] (1708:1708:1708) (1955:1955:1955)) - (PORT d[8] (901:901:901) (1048:1048:1048)) - (PORT d[9] (406:406:406) (473:473:473)) - (PORT d[10] (392:392:392) (457:457:457)) - (PORT d[11] (1449:1449:1449) (1693:1693:1693)) - (PORT d[12] (425:425:425) (499:499:499)) + (PORT d[0] (1421:1421:1421) (1630:1630:1630)) + (PORT d[1] (1081:1081:1081) (1256:1256:1256)) + (PORT d[2] (1976:1976:1976) (2261:2261:2261)) + (PORT d[3] (1101:1101:1101) (1290:1290:1290)) + (PORT d[4] (1109:1109:1109) (1285:1285:1285)) + (PORT d[5] (1009:1009:1009) (1160:1160:1160)) + (PORT d[6] (1447:1447:1447) (1685:1685:1685)) + (PORT d[7] (1033:1033:1033) (1190:1190:1190)) + (PORT d[8] (1689:1689:1689) (1941:1941:1941)) + (PORT d[9] (2124:2124:2124) (2454:2454:2454)) + (PORT d[10] (1164:1164:1164) (1374:1374:1374)) + (PORT d[11] (1349:1349:1349) (1547:1547:1547)) + (PORT d[12] (978:978:978) (1157:1157:1157)) (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) @@ -44154,7 +46886,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (517:517:517) (543:543:543)) + (PORT d[0] (681:681:681) (723:723:723)) (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) @@ -44168,7 +46900,7 @@ (DELAY (ABSOLUTE (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1842:1842:1842) (2033:2033:2033)) + (PORT d[0] (980:980:980) (1033:1033:1033)) ) ) ) @@ -44264,579 +46996,25 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (649:649:649) (722:722:722)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1504:1504:1504) (1750:1750:1750)) - (PORT d[1] (2131:2131:2131) (2426:2426:2426)) - (PORT d[2] (1343:1343:1343) (1541:1541:1541)) - (PORT d[3] (2503:2503:2503) (2842:2842:2842)) - (PORT d[4] (1858:1858:1858) (2171:2171:2171)) - (PORT d[5] (2713:2713:2713) (3096:3096:3096)) - (PORT d[6] (1458:1458:1458) (1658:1658:1658)) - (PORT d[7] (778:778:778) (875:875:875)) - (PORT d[8] (1780:1780:1780) (2069:2069:2069)) - (PORT d[9] (1017:1017:1017) (1155:1155:1155)) - (PORT d[10] (1114:1114:1114) (1260:1260:1260)) - (PORT d[11] (1969:1969:1969) (2299:2299:2299)) - (PORT d[12] (2785:2785:2785) (3155:3155:3155)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1068:1068:1068) (1183:1183:1183)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (1350:1350:1350) (1439:1439:1439)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (640:640:640)) - (PORT datab (665:665:665) (790:790:790)) - (PORT datac (510:510:510) (584:584:584)) - (PORT datad (578:578:578) (664:664:664)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (781:781:781) (873:873:873)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1432:1432:1432) (1660:1660:1660)) - (PORT d[1] (1402:1402:1402) (1577:1577:1577)) - (PORT d[2] (1505:1505:1505) (1749:1749:1749)) - (PORT d[3] (942:942:942) (1074:1074:1074)) - (PORT d[4] (1384:1384:1384) (1600:1600:1600)) - (PORT d[5] (1802:1802:1802) (2059:2059:2059)) - (PORT d[6] (1244:1244:1244) (1415:1415:1415)) - (PORT d[7] (959:959:959) (1087:1087:1087)) - (PORT d[8] (1370:1370:1370) (1592:1592:1592)) - (PORT d[9] (960:960:960) (1083:1083:1083)) - (PORT d[10] (1447:1447:1447) (1631:1631:1631)) - (PORT d[11] (2349:2349:2349) (2735:2735:2735)) - (PORT d[12] (1407:1407:1407) (1591:1591:1591)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1115:1115:1115) (1203:1203:1203)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1209:1209:1209) (1285:1285:1285)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (989:989:989)) - (PORT datab (679:679:679) (770:770:770)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (776:776:776) (880:880:880)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (835:835:835) (945:945:945)) - (PORT clk (1102:1102:1102) (1119:1119:1119)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1413:1413:1413) (1641:1641:1641)) - (PORT d[1] (1315:1315:1315) (1490:1490:1490)) - (PORT d[2] (1212:1212:1212) (1393:1393:1393)) - (PORT d[3] (1908:1908:1908) (2156:2156:2156)) - (PORT d[4] (1318:1318:1318) (1559:1559:1559)) - (PORT d[5] (2134:2134:2134) (2433:2433:2433)) - (PORT d[6] (1449:1449:1449) (1648:1648:1648)) - (PORT d[7] (1420:1420:1420) (1603:1603:1603)) - (PORT d[8] (1666:1666:1666) (1906:1906:1906)) - (PORT d[9] (1604:1604:1604) (1831:1831:1831)) - (PORT d[10] (1684:1684:1684) (1914:1914:1914)) - (PORT d[11] (1564:1564:1564) (1815:1815:1815)) - (PORT d[12] (2068:2068:2068) (2347:2347:2347)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1621:1621:1621) (1770:1770:1770)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (PORT d[0] (2171:2171:2171) (2012:2012:2012)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1076:1076:1076)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1208:1208:1208) (1345:1345:1345)) - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2497:2497:2497) (2815:2815:2815)) - (PORT d[1] (2496:2496:2496) (2815:2815:2815)) - (PORT d[2] (2504:2504:2504) (2835:2835:2835)) - (PORT d[3] (2441:2441:2441) (2755:2755:2755)) - (PORT d[4] (2407:2407:2407) (2744:2744:2744)) - (PORT d[5] (2478:2478:2478) (2782:2782:2782)) - (PORT d[6] (2412:2412:2412) (2708:2708:2708)) - (PORT d[7] (2486:2486:2486) (2802:2802:2802)) - (PORT d[8] (2535:2535:2535) (2891:2891:2891)) - (PORT d[9] (2436:2436:2436) (2771:2771:2771)) - (PORT d[10] (2354:2354:2354) (2645:2645:2645)) - (PORT d[11] (2472:2472:2472) (2820:2820:2820)) - (PORT d[12] (2358:2358:2358) (2657:2657:2657)) - (PORT clk (1059:1059:1059) (1078:1078:1078)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1077:1077:1077)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1289:1289:1289)) - (PORT d[1] (954:954:954) (1077:1077:1077)) - (PORT d[2] (1145:1145:1145) (1339:1339:1339)) - (PORT d[3] (1079:1079:1079) (1223:1223:1223)) - (PORT d[4] (1511:1511:1511) (1740:1740:1740)) - (PORT d[5] (1307:1307:1307) (1487:1487:1487)) - (PORT d[6] (960:960:960) (1100:1100:1100)) - (PORT d[7] (1149:1149:1149) (1302:1302:1302)) - (PORT d[8] (1036:1036:1036) (1208:1208:1208)) - (PORT d[9] (1155:1155:1155) (1306:1306:1306)) - (PORT d[10] (957:957:957) (1081:1081:1081)) - (PORT d[11] (2528:2528:2528) (2934:2934:2934)) - (PORT d[12] (945:945:945) (1060:1060:1060)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1577:1577:1577) (1798:1798:1798)) + (PORT d[1] (1244:1244:1244) (1438:1438:1438)) + (PORT d[2] (1536:1536:1536) (1748:1748:1748)) + (PORT d[3] (1604:1604:1604) (1846:1846:1846)) + (PORT d[4] (2127:2127:2127) (2474:2474:2474)) + (PORT d[5] (1678:1678:1678) (1912:1912:1912)) + (PORT d[6] (1626:1626:1626) (1882:1882:1882)) + (PORT d[7] (1563:1563:1563) (1791:1791:1791)) + (PORT d[8] (1302:1302:1302) (1500:1500:1500)) + (PORT d[9] (1541:1541:1541) (1777:1777:1777)) + (PORT d[10] (1172:1172:1172) (1379:1379:1379)) + (PORT d[11] (1363:1363:1363) (1557:1557:1557)) + (PORT d[12] (1128:1128:1128) (1335:1335:1335)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) ) ) (TIMINGCHECK @@ -44848,8 +47026,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (1118:1118:1118) (1024:1024:1024)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (1810:1810:1810) (1624:1624:1624)) ) ) ) @@ -44858,7 +47036,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT clk (1100:1100:1100) (1118:1118:1118)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -44868,7 +47046,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) + (PORT clk (1081:1081:1081) (1098:1098:1098)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -44882,7 +47060,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) + (PORT clk (621:621:621) (630:630:630)) ) ) ) @@ -44891,7 +47069,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (622:622:622) (631:631:631)) ) ) ) @@ -44900,7 +47078,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (622:622:622) (631:631:631)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -44910,30 +47088,18 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (622:622:622) (631:631:631)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1424:1424:1424) (1658:1658:1658)) - (PORT d[1] (1552:1552:1552) (1763:1763:1763)) - (PORT d[2] (1311:1311:1311) (1525:1525:1525)) - (PORT d[3] (1246:1246:1246) (1423:1423:1423)) - (PORT d[4] (1155:1155:1155) (1350:1350:1350)) - (PORT d[5] (1408:1408:1408) (1611:1611:1611)) - (PORT d[6] (1420:1420:1420) (1636:1636:1636)) - (PORT d[7] (1961:1961:1961) (2241:2241:2241)) - (PORT d[8] (1605:1605:1605) (1843:1843:1843)) - (PORT d[9] (1388:1388:1388) (1599:1599:1599)) - (PORT d[10] (1890:1890:1890) (2172:2172:2172)) - (PORT d[11] (1205:1205:1205) (1400:1400:1400)) - (PORT d[12] (1350:1350:1350) (1552:1552:1552)) - (PORT clk (1099:1099:1099) (1116:1116:1116)) + (PORT d[0] (801:801:801) (908:908:908)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) (TIMINGCHECK @@ -44942,30 +47108,98 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (PORT d[0] (1509:1509:1509) (1696:1696:1696)) + (PORT d[0] (1681:1681:1681) (1909:1909:1909)) + (PORT d[1] (1544:1544:1544) (1746:1746:1746)) + (PORT d[2] (1499:1499:1499) (1707:1707:1707)) + (PORT d[3] (972:972:972) (1106:1106:1106)) + (PORT d[4] (1886:1886:1886) (2200:2200:2200)) + (PORT d[5] (1735:1735:1735) (1962:1962:1962)) + (PORT d[6] (2355:2355:2355) (2719:2719:2719)) + (PORT d[7] (801:801:801) (917:917:917)) + (PORT d[8] (631:631:631) (719:719:719)) + (PORT d[9] (2639:2639:2639) (3038:3038:3038)) + (PORT d[10] (2418:2418:2418) (2813:2813:2813)) + (PORT d[11] (2121:2121:2121) (2423:2423:2423)) + (PORT d[12] (517:517:517) (593:593:593)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1709:1709:1709) (1881:1881:1881)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1642:1642:1642) (1768:1768:1768)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1100:1100:1100) (1117:1117:1117)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1081:1081:1081) (1097:1097:1097)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -44976,49 +47210,343 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (621:621:621) (629:629:629)) + (PORT clk (617:617:617) (625:625:625)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (622:622:622) (630:630:630)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (622:622:622) (630:630:630)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (622:622:622) (630:630:630)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~7) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (656:656:656)) + (PORT datab (673:673:673) (775:775:775)) + (PORT datac (778:778:778) (894:894:894)) + (PORT datad (200:200:200) (234:234:234)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~8) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (809:809:809)) + (PORT datac (942:942:942) (1093:1093:1093)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1355:1355:1355)) + (PORT datab (871:871:871) (989:989:989)) + (PORT datac (1135:1135:1135) (1291:1291:1291)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (714:714:714) (823:823:823)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1222:1222:1222) (1404:1404:1404)) + (PORT d[1] (910:910:910) (1062:1062:1062)) + (PORT d[2] (1806:1806:1806) (2067:2067:2067)) + (PORT d[3] (1272:1272:1272) (1484:1484:1484)) + (PORT d[4] (2497:2497:2497) (2891:2891:2891)) + (PORT d[5] (1923:1923:1923) (2203:2203:2203)) + (PORT d[6] (1426:1426:1426) (1656:1656:1656)) + (PORT d[7] (1203:1203:1203) (1386:1386:1386)) + (PORT d[8] (1174:1174:1174) (1362:1362:1362)) + (PORT d[9] (2115:2115:2115) (2444:2444:2444)) + (PORT d[10] (1160:1160:1160) (1370:1370:1370)) + (PORT d[11] (1156:1156:1156) (1323:1323:1323)) + (PORT d[12] (992:992:992) (1172:1172:1172)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (1026:1026:1026)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1104:1104:1104)) + (PORT d[0] (1888:1888:1888) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1041:1041:1041) (1061:1061:1061)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (713:713:713) (825:825:825)) + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2331:2331:2331) (2650:2650:2650)) + (PORT d[1] (2440:2440:2440) (2778:2778:2778)) + (PORT d[2] (2346:2346:2346) (2680:2680:2680)) + (PORT d[3] (2392:2392:2392) (2731:2731:2731)) + (PORT d[4] (2394:2394:2394) (2740:2740:2740)) + (PORT d[5] (2356:2356:2356) (2709:2709:2709)) + (PORT d[6] (2449:2449:2449) (2843:2843:2843)) + (PORT d[7] (2373:2373:2373) (2745:2745:2745)) + (PORT d[8] (2365:2365:2365) (2663:2663:2663)) + (PORT d[9] (2327:2327:2327) (2660:2660:2660)) + (PORT d[10] (2284:2284:2284) (2583:2583:2583)) + (PORT d[11] (2339:2339:2339) (2670:2670:2670)) + (PORT d[12] (2440:2440:2440) (2765:2765:2765)) + (PORT clk (1043:1043:1043) (1063:1063:1063)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1042:1042:1042) (1062:1062:1062)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~15) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (937:937:937)) + (PORT datab (1550:1550:1550) (1779:1779:1779)) + (PORT datac (506:506:506) (572:572:572)) + (PORT datad (779:779:779) (886:886:886)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1326:1326:1326)) + (PORT datab (558:558:558) (663:663:663)) + (PORT datac (122:122:122) (146:146:146)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (924:924:924) (1071:1071:1071)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (766:766:766) (862:862:862)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) ) ) (TIMINGCHECK @@ -45030,20 +47558,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1596:1596:1596) (1854:1854:1854)) - (PORT d[1] (1730:1730:1730) (1961:1961:1961)) - (PORT d[2] (1153:1153:1153) (1345:1345:1345)) - (PORT d[3] (1086:1086:1086) (1250:1250:1250)) - (PORT d[4] (1184:1184:1184) (1386:1386:1386)) - (PORT d[5] (1489:1489:1489) (1701:1701:1701)) - (PORT d[6] (1244:1244:1244) (1438:1438:1438)) - (PORT d[7] (1972:1972:1972) (2249:2249:2249)) - (PORT d[8] (1785:1785:1785) (2050:2050:2050)) - (PORT d[9] (1354:1354:1354) (1564:1564:1564)) - (PORT d[10] (1130:1130:1130) (1298:1298:1298)) - (PORT d[11] (1209:1209:1209) (1397:1397:1397)) - (PORT d[12] (1411:1411:1411) (1617:1617:1617)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT d[0] (2240:2240:2240) (2546:2546:2546)) + (PORT d[1] (2274:2274:2274) (2580:2580:2580)) + (PORT d[2] (1771:1771:1771) (2009:2009:2009)) + (PORT d[3] (2001:2001:2001) (2327:2327:2327)) + (PORT d[4] (2028:2028:2028) (2348:2348:2348)) + (PORT d[5] (1692:1692:1692) (1930:1930:1930)) + (PORT d[6] (1788:1788:1788) (2074:2074:2074)) + (PORT d[7] (2579:2579:2579) (2919:2919:2919)) + (PORT d[8] (1703:1703:1703) (1984:1984:1984)) + (PORT d[9] (2086:2086:2086) (2407:2407:2407)) + (PORT d[10] (1804:1804:1804) (2099:2099:2099)) + (PORT d[11] (1556:1556:1556) (1780:1780:1780)) + (PORT d[12] (1181:1181:1181) (1402:1402:1402)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) (TIMINGCHECK @@ -45055,8 +47583,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1131:1131:1131) (1240:1240:1240)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT d[0] (1363:1363:1363) (1490:1490:1490)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) (TIMINGCHECK @@ -45068,8 +47596,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1825:1825:1825) (1999:1999:1999)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (3016:3016:3016) (3315:3315:3315)) ) ) ) @@ -45078,7 +47606,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -45088,7 +47616,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -45098,7 +47626,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -45108,7 +47636,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -45118,7 +47646,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1051:1051:1051) (1071:1071:1071)) + (PORT clk (1049:1049:1049) (1068:1068:1068)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -45132,8 +47660,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1189:1189:1189) (1350:1350:1350)) - (PORT clk (1056:1056:1056) (1074:1074:1074)) + (PORT d[0] (743:743:743) (833:833:833)) + (PORT clk (1054:1054:1054) (1071:1071:1071)) ) ) (TIMINGCHECK @@ -45145,20 +47673,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2519:2519:2519) (2860:2860:2860)) - (PORT d[1] (2502:2502:2502) (2847:2847:2847)) - (PORT d[2] (2482:2482:2482) (2816:2816:2816)) - (PORT d[3] (2424:2424:2424) (2757:2757:2757)) - (PORT d[4] (2473:2473:2473) (2795:2795:2795)) - (PORT d[5] (2522:2522:2522) (2859:2859:2859)) - (PORT d[6] (2458:2458:2458) (2788:2788:2788)) - (PORT d[7] (2433:2433:2433) (2727:2727:2727)) - (PORT d[8] (2590:2590:2590) (2953:2953:2953)) - (PORT d[9] (2489:2489:2489) (2808:2808:2808)) - (PORT d[10] (2451:2451:2451) (2781:2781:2781)) - (PORT d[11] (2462:2462:2462) (2806:2806:2806)) - (PORT d[12] (2406:2406:2406) (2697:2697:2697)) - (PORT clk (1053:1053:1053) (1073:1073:1073)) + (PORT d[0] (2291:2291:2291) (2612:2612:2612)) + (PORT d[1] (2415:2415:2415) (2786:2786:2786)) + (PORT d[2] (2371:2371:2371) (2669:2669:2669)) + (PORT d[3] (2327:2327:2327) (2654:2654:2654)) + (PORT d[4] (2290:2290:2290) (2603:2603:2603)) + (PORT d[5] (2411:2411:2411) (2819:2819:2819)) + (PORT d[6] (2482:2482:2482) (2868:2868:2868)) + (PORT d[7] (2441:2441:2441) (2819:2819:2819)) + (PORT d[8] (2326:2326:2326) (2643:2643:2643)) + (PORT d[9] (2356:2356:2356) (2684:2684:2684)) + (PORT d[10] (2267:2267:2267) (2564:2564:2564)) + (PORT d[11] (2396:2396:2396) (2734:2734:2734)) + (PORT d[12] (2353:2353:2353) (2676:2676:2676)) + (PORT clk (1051:1051:1051) (1070:1070:1070)) ) ) (TIMINGCHECK @@ -45170,7 +47698,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1056:1056:1056) (1074:1074:1074)) + (PORT clk (1054:1054:1054) (1071:1071:1071)) ) ) ) @@ -45179,7 +47707,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -45189,7 +47717,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) ) ) ) @@ -45198,7 +47726,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -45208,22 +47736,119 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1964:1964:1964) (2214:2214:2214)) + (PORT d[1] (2499:2499:2499) (2843:2843:2843)) + (PORT d[2] (1623:1623:1623) (1832:1832:1832)) + (PORT d[3] (1668:1668:1668) (1950:1950:1950)) + (PORT d[4] (1696:1696:1696) (1973:1973:1973)) + (PORT d[5] (1526:1526:1526) (1743:1743:1743)) + (PORT d[6] (1926:1926:1926) (2214:2214:2214)) + (PORT d[7] (2216:2216:2216) (2509:2509:2509)) + (PORT d[8] (1503:1503:1503) (1756:1756:1756)) + (PORT d[9] (1741:1741:1741) (2016:2016:2016)) + (PORT d[10] (1484:1484:1484) (1749:1749:1749)) + (PORT d[11] (1356:1356:1356) (1550:1550:1550)) + (PORT d[12] (1376:1376:1376) (1622:1622:1622)) + (PORT clk (1105:1105:1105) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1122:1122:1122)) + (PORT d[0] (2176:2176:2176) (2418:2418:2418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~35) + (INSTANCE Selector12\~14) (DELAY (ABSOLUTE - (PORT dataa (500:500:500) (582:582:582)) - (PORT datab (432:432:432) (522:522:522)) - (PORT datac (820:820:820) (939:939:939)) - (PORT datad (648:648:648) (741:741:741)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (796:796:796) (932:932:932)) + (PORT datab (1552:1552:1552) (1781:1781:1781)) + (PORT datac (771:771:771) (878:878:878)) + (PORT datad (949:949:949) (1089:1089:1089)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -45231,47 +47856,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~36) + (INSTANCE Selector12\~6) (DELAY (ABSOLUTE - (PORT dataa (569:569:569) (649:649:649)) - (PORT datab (569:569:569) (665:665:665)) - (PORT datac (910:910:910) (1049:1049:1049)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (510:510:510)) - (PORT datab (993:993:993) (1154:1154:1154)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (1087:1087:1087)) - (PORT datab (1718:1718:1718) (2021:2021:2021)) - (PORT datac (91:91:91) (112:112:112)) + (PORT dataa (818:818:818) (958:958:958)) + (PORT datab (135:135:135) (166:166:166)) + (PORT datac (88:88:88) (110:110:110)) (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -45279,31 +47872,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~40) + (INSTANCE Selector12\~11) (DELAY (ABSOLUTE - (PORT dataa (521:521:521) (598:598:598)) - (PORT datab (490:490:490) (568:568:568)) - (PORT datac (901:901:901) (1022:1022:1022)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (224:224:224) (264:264:264)) + (PORT datab (451:451:451) (517:517:517)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~41) + (INSTANCE D\[1\]\~12) (DELAY (ABSOLUTE - (PORT dataa (638:638:638) (747:747:747)) - (PORT datab (806:806:806) (931:931:931)) - (PORT datac (1794:1794:1794) (2045:2045:2045)) + (PORT dataa (365:365:365) (429:429:429)) + (PORT datab (628:628:628) (760:760:760)) + (PORT datac (821:821:821) (943:943:943)) (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -45314,11 +47907,11 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (606:606:606)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (619:619:619) (708:708:708)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (487:487:487) (567:567:567)) + (PORT datab (826:826:826) (971:971:971)) + (PORT datac (716:716:716) (833:833:833)) + (PORT datad (122:122:122) (153:153:153)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -45330,9 +47923,9 @@ (INSTANCE z80_\|data_pins_\|dout\[1\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) + (PORT clk (912:912:912) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -45343,16 +47936,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (145:145:145) (194:194:194)) - (PORT datac (309:309:309) (354:354:354)) - (PORT datad (200:200:200) (236:236:236)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (486:486:486) (577:577:577)) + (PORT datac (319:319:319) (363:363:363)) + (PORT datad (471:471:471) (576:576:576)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -45363,77 +47956,39 @@ (DELAY (ABSOLUTE (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1045:1045:1045) (1140:1140:1140)) + (PORT asdata (632:632:632) (693:693:693)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (1073:1073:1073) (1180:1180:1180)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (INSTANCE z80_\|pla_decode_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (914:914:914) (1084:1084:1084)) - (PORT datab (1095:1095:1095) (1287:1287:1287)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (647:647:647) (736:736:736)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (906:906:906)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (890:890:890)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (504:504:504)) - (PORT datab (408:408:408) (501:501:501)) - (PORT datac (1062:1062:1062) (1241:1241:1241)) - (PORT datad (941:941:941) (1087:1087:1087)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (941:941:941) (1119:1119:1119)) + (PORT datad (544:544:544) (641:641:641)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (1177:1177:1177) (1402:1402:1402)) - (PORT datab (808:808:808) (961:961:961)) - (PORT datac (613:613:613) (692:692:692)) - (PORT datad (479:479:479) (558:558:558)) + (PORT dataa (425:425:425) (525:525:525)) + (PORT datab (498:498:498) (581:581:581)) + (PORT datac (665:665:665) (792:792:792)) + (PORT datad (331:331:331) (388:388:388)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -45443,559 +47998,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (INSTANCE z80_\|interrupts_\|iff1\~0) (DELAY (ABSOLUTE - (PORT dataa (900:900:900) (1049:1049:1049)) - (PORT datab (343:343:343) (401:401:401)) - (PORT datac (584:584:584) (688:688:688)) - (PORT datad (1478:1478:1478) (1681:1681:1681)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1169:1169:1169)) - (PORT datab (609:609:609) (721:721:721)) - (PORT datac (453:453:453) (522:522:522)) - (PORT datad (1457:1457:1457) (1656:1656:1656)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (562:562:562)) - (PORT datab (600:600:600) (709:709:709)) - (PORT datac (1035:1035:1035) (1193:1193:1193)) - (PORT datad (341:341:341) (399:399:399)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (1049:1049:1049)) - (PORT datab (1296:1296:1296) (1534:1534:1534)) - (PORT datac (345:345:345) (412:412:412)) - (PORT datad (548:548:548) (653:653:653)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (472:472:472)) - (PORT datab (513:513:513) (598:598:598)) - (PORT datac (816:816:816) (927:927:927)) - (PORT datad (357:357:357) (418:418:418)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (380:380:380)) - (PORT datab (628:628:628) (715:715:715)) - (PORT datac (293:293:293) (337:337:337)) - (PORT datad (336:336:336) (396:396:396)) + (PORT dataa (1037:1037:1037) (1225:1225:1225)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (191:191:191) (240:240:240)) + (PORT datad (1074:1074:1074) (1259:1259:1259)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (266:266:266) (332:332:332)) - (PORT datad (336:336:336) (390:390:390)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (889:889:889)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (249:249:249)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (269:269:269)) - (PORT datab (530:530:530) (615:615:615)) - (PORT datac (459:459:459) (521:521:521)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (341:341:341)) - (PORT datab (508:508:508) (610:610:610)) - (PORT datac (411:411:411) (506:506:506)) - (PORT datad (387:387:387) (469:469:469)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (424:424:424)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (239:239:239) (296:296:296)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (889:889:889)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT datab (422:422:422) (521:521:521)) - (PORT datac (695:695:695) (815:815:815)) - (PORT datad (133:133:133) (170:170:170)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (476:476:476)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (401:401:401) (493:493:493)) - (PORT datad (330:330:330) (387:387:387)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (333:333:333)) - (PORT datab (744:744:744) (846:846:846)) - (PORT datad (163:163:163) (186:186:186)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (899:899:899)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (837:837:837)) - (PORT datab (501:501:501) (576:576:576)) - (PORT datac (322:322:322) (381:381:381)) - (PORT datad (347:347:347) (417:417:417)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (448:448:448)) - (PORT datab (394:394:394) (472:472:472)) - (PORT datac (680:680:680) (786:786:786)) - (PORT datad (665:665:665) (763:763:763)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (381:381:381)) - (PORT datab (414:414:414) (493:493:493)) - (PORT datac (379:379:379) (456:456:456)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1554:1554:1554)) - (PORT datab (802:802:802) (943:943:943)) - (PORT datad (357:357:357) (433:433:433)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (164:164:164) (224:224:224)) - (PORT datab (517:517:517) (612:612:612)) - (PORT datac (540:540:540) (640:640:640)) - (PORT datad (386:386:386) (471:471:471)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (670:670:670)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datad (142:142:142) (184:184:184)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (244:244:244)) - (PORT datab (334:334:334) (398:398:398)) - (PORT datad (438:438:438) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (898:898:898)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (885:885:885) (890:890:890)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (341:341:341) (405:405:405)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (886:886:886) (891:891:891)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (524:524:524)) - (PORT datab (335:335:335) (391:391:391)) - (PORT datad (325:325:325) (372:372:372)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (897:897:897) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (883:883:883) (888:888:888)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (456:456:456)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datac (1371:1371:1371) (1616:1616:1616)) - (PORT datad (341:341:341) (404:404:404)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (375:375:375)) - (PORT datab (1426:1426:1426) (1673:1673:1673)) - (PORT datac (508:508:508) (597:597:597)) - (PORT datad (327:327:327) (379:379:379)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (746:746:746)) - (PORT datab (673:673:673) (768:768:768)) - (PORT datac (1910:1910:1910) (2251:2251:2251)) - (PORT datad (326:326:326) (378:378:378)) - (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -46003,12 +48013,315 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT d[0] (568:568:568) (653:653:653)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (628:628:628) (735:735:735)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (655:655:655) (767:767:767)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (149:149:149) (200:200:200)) + (PORT datac (1173:1173:1173) (1377:1377:1377)) + (PORT datad (134:134:134) (174:174:174)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (631:631:631) (685:685:685)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1807:1807:1807)) + (PORT datab (679:679:679) (797:797:797)) + (PORT datac (810:810:810) (935:935:935)) + (PORT datad (475:475:475) (555:555:555)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (1098:1098:1098) (1123:1123:1123)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (773:773:773)) + (PORT datab (367:367:367) (439:439:439)) + (PORT datac (792:792:792) (906:906:906)) + (PORT datad (128:128:128) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (419:419:419)) + (PORT datab (457:457:457) (541:541:541)) + (PORT datac (334:334:334) (394:394:394)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (416:416:416)) + (PORT datab (359:359:359) (422:422:422)) + (PORT datac (507:507:507) (598:598:598)) + (PORT datad (833:833:833) (971:971:971)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (890:890:890)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (940:940:940)) + (PORT datab (149:149:149) (201:201:201)) + (PORT datac (823:823:823) (966:966:966)) + (PORT datad (133:133:133) (173:173:173)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (186:186:186)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (678:678:678)) + (PORT datac (670:670:670) (795:795:795)) + (PORT datad (197:197:197) (247:247:247)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (1068:1068:1068)) + (PORT datac (854:854:854) (1003:1003:1003)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (632:632:632)) + (PORT datab (309:309:309) (364:364:364)) + (PORT datac (614:614:614) (702:702:702)) + (PORT datad (1004:1004:1004) (1153:1153:1153)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (576:576:576)) + (PORT datab (976:976:976) (1128:1128:1128)) + (PORT datac (538:538:538) (629:629:629)) + (PORT datad (1176:1176:1176) (1375:1375:1375)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1998:1998:1998) (2264:2264:2264)) + (PORT d[1] (2491:2491:2491) (2834:2834:2834)) + (PORT d[2] (1906:1906:1906) (2159:2159:2159)) + (PORT d[3] (1538:1538:1538) (1805:1805:1805)) + (PORT d[4] (1811:1811:1811) (2108:2108:2108)) + (PORT d[5] (1631:1631:1631) (1891:1891:1891)) + (PORT d[6] (1792:1792:1792) (2070:2070:2070)) + (PORT d[7] (2242:2242:2242) (2543:2543:2543)) + (PORT d[8] (1514:1514:1514) (1766:1766:1766)) + (PORT d[9] (1728:1728:1728) (1998:1998:1998)) + (PORT d[10] (1471:1471:1471) (1735:1735:1735)) + (PORT d[11] (1339:1339:1339) (1528:1528:1528)) + (PORT d[12] (1369:1369:1369) (1615:1615:1615)) + (PORT clk (1104:1104:1104) (1122:1122:1122)) ) ) (TIMINGCHECK @@ -46017,98 +48330,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1956:1956:1956) (2300:2300:2300)) - (PORT d[1] (901:901:901) (1036:1036:1036)) - (PORT d[2] (579:579:579) (672:672:672)) - (PORT d[3] (926:926:926) (1070:1070:1070)) - (PORT d[4] (1718:1718:1718) (1988:1988:1988)) - (PORT d[5] (531:531:531) (614:614:614)) - (PORT d[6] (909:909:909) (1060:1060:1060)) - (PORT d[7] (703:703:703) (813:813:813)) - (PORT d[8] (676:676:676) (792:792:792)) - (PORT d[9] (635:635:635) (743:743:743)) - (PORT d[10] (596:596:596) (691:691:691)) - (PORT d[11] (1276:1276:1276) (1491:1491:1491)) - (PORT d[12] (631:631:631) (738:738:738)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (648:648:648) (688:688:688)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1303:1303:1303) (1405:1405:1405)) + (PORT clk (1104:1104:1104) (1122:1122:1122)) + (PORT d[0] (2207:2207:2207) (2461:2461:2461)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) + (PORT clk (1105:1105:1105) (1123:1123:1123)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) + (PORT clk (1086:1086:1086) (1103:1103:1103)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -46119,49 +48364,49 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) + (PORT clk (626:626:626) (635:635:635)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (627:627:627) (636:636:636)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (627:627:627) (636:636:636)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (627:627:627) (636:636:636)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (544:544:544) (625:625:625)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (978:978:978) (1140:1140:1140)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) ) ) (TIMINGCHECK @@ -46170,23 +48415,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1972:1972:1972) (2319:2319:2319)) - (PORT d[1] (739:739:739) (857:857:857)) - (PORT d[2] (970:970:970) (1137:1137:1137)) - (PORT d[3] (916:916:916) (1059:1059:1059)) - (PORT d[4] (1706:1706:1706) (1978:1978:1978)) - (PORT d[5] (715:715:715) (825:825:825)) - (PORT d[6] (742:742:742) (865:865:865)) - (PORT d[7] (744:744:744) (867:867:867)) - (PORT d[8] (870:870:870) (1008:1008:1008)) - (PORT d[9] (645:645:645) (751:751:751)) - (PORT d[10] (609:609:609) (705:705:705)) - (PORT d[11] (1252:1252:1252) (1459:1459:1459)) - (PORT d[12] (794:794:794) (923:923:923)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (2168:2168:2168) (2457:2457:2457)) + (PORT d[1] (2316:2316:2316) (2637:2637:2637)) + (PORT d[2] (1464:1464:1464) (1658:1658:1658)) + (PORT d[3] (1842:1842:1842) (2147:2147:2147)) + (PORT d[4] (1844:1844:1844) (2148:2148:2148)) + (PORT d[5] (1603:1603:1603) (1854:1854:1854)) + (PORT d[6] (1784:1784:1784) (2063:2063:2063)) + (PORT d[7] (2396:2396:2396) (2714:2714:2714)) + (PORT d[8] (1706:1706:1706) (1987:1987:1987)) + (PORT d[9] (1923:1923:1923) (2223:2223:2223)) + (PORT d[10] (1633:1633:1633) (1914:1914:1914)) + (PORT d[11] (1370:1370:1370) (1566:1566:1566)) + (PORT d[12] (1197:1197:1197) (1423:1423:1423)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) ) ) (TIMINGCHECK @@ -46195,11 +48440,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (681:681:681) (725:725:725)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1266:1266:1266) (1377:1377:1377)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) ) ) (TIMINGCHECK @@ -46208,60 +48453,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1317:1317:1317) (1421:1421:1421)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (PORT d[0] (2872:2872:2872) (3159:3159:3159)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) + (PORT clk (1057:1057:1057) (1076:1076:1076)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -46272,48 +48517,441 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT d[0] (781:781:781) (876:876:876)) + (PORT clk (1062:1062:1062) (1079:1079:1079)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2365:2365:2365) (2666:2666:2666)) + (PORT d[1] (2414:2414:2414) (2779:2779:2779)) + (PORT d[2] (2311:2311:2311) (2626:2626:2626)) + (PORT d[3] (2296:2296:2296) (2603:2603:2603)) + (PORT d[4] (2302:2302:2302) (2618:2618:2618)) + (PORT d[5] (2357:2357:2357) (2720:2720:2720)) + (PORT d[6] (2463:2463:2463) (2843:2843:2843)) + (PORT d[7] (2485:2485:2485) (2862:2862:2862)) + (PORT d[8] (2343:2343:2343) (2661:2661:2661)) + (PORT d[9] (2337:2337:2337) (2666:2666:2666)) + (PORT d[10] (2298:2298:2298) (2592:2592:2592)) + (PORT d[11] (2361:2361:2361) (2690:2690:2690)) + (PORT d[12] (2335:2335:2335) (2656:2656:2656)) + (PORT clk (1059:1059:1059) (1078:1078:1078)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (511:511:511) (584:584:584)) + (PORT d[0] (764:764:764) (877:877:877)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1738:1738:1738) (1981:1981:1981)) + (PORT d[1] (924:924:924) (1072:1072:1072)) + (PORT d[2] (1616:1616:1616) (1850:1850:1850)) + (PORT d[3] (1480:1480:1480) (1725:1725:1725)) + (PORT d[4] (2316:2316:2316) (2688:2688:2688)) + (PORT d[5] (1559:1559:1559) (1784:1784:1784)) + (PORT d[6] (1436:1436:1436) (1645:1645:1645)) + (PORT d[7] (1383:1383:1383) (1588:1588:1588)) + (PORT d[8] (1496:1496:1496) (1724:1724:1724)) + (PORT d[9] (1733:1733:1733) (2003:2003:2003)) + (PORT d[10] (1324:1324:1324) (1556:1556:1556)) + (PORT d[11] (1388:1388:1388) (1593:1593:1593)) + (PORT d[12] (984:984:984) (1164:1164:1164)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1127:1127:1127) (1224:1224:1224)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (2103:2103:2103) (1956:1956:1956)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (839:839:839) (961:961:961)) + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2352:2352:2352) (2675:2675:2675)) + (PORT d[1] (2409:2409:2409) (2783:2783:2783)) + (PORT d[2] (2404:2404:2404) (2743:2743:2743)) + (PORT d[3] (2403:2403:2403) (2743:2743:2743)) + (PORT d[4] (2423:2423:2423) (2774:2774:2774)) + (PORT d[5] (2520:2520:2520) (2939:2939:2939)) + (PORT d[6] (2493:2493:2493) (2852:2852:2852)) + (PORT d[7] (2399:2399:2399) (2744:2744:2744)) + (PORT d[8] (2350:2350:2350) (2644:2644:2644)) + (PORT d[9] (2322:2322:2322) (2660:2660:2660)) + (PORT d[10] (2275:2275:2275) (2568:2568:2568)) + (PORT d[11] (2341:2341:2341) (2667:2667:2667)) + (PORT d[12] (2392:2392:2392) (2703:2703:2703)) + (PORT clk (1053:1053:1053) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1072:1072:1072)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1307:1307:1307) (1482:1482:1482)) + (PORT d[1] (1185:1185:1185) (1336:1336:1336)) + (PORT d[2] (1119:1119:1119) (1277:1277:1277)) + (PORT d[3] (662:662:662) (758:758:758)) + (PORT d[4] (1471:1471:1471) (1686:1686:1686)) + (PORT d[5] (1376:1376:1376) (1558:1558:1558)) + (PORT d[6] (2152:2152:2152) (2488:2488:2488)) + (PORT d[7] (965:965:965) (1105:1105:1105)) + (PORT d[8] (575:575:575) (669:669:669)) + (PORT d[9] (541:541:541) (623:623:623)) + (PORT d[10] (1022:1022:1022) (1168:1168:1168)) + (PORT d[11] (1284:1284:1284) (1454:1454:1454)) + (PORT d[12] (875:875:875) (1010:1010:1010)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1079:1079:1079) (978:978:978)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~5) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (774:774:774)) + (PORT datab (680:680:680) (787:787:787)) + (PORT datac (344:344:344) (411:411:411)) + (PORT datad (957:957:957) (1092:1092:1092)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (956:956:956)) + (PORT datab (246:246:246) (307:307:307)) + (PORT datac (988:988:988) (1149:1149:1149)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (731:731:731) (847:847:847)) (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) @@ -46323,22 +48961,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1568:1568:1568) (1836:1836:1836)) - (PORT d[1] (878:878:878) (1007:1007:1007)) - (PORT d[2] (774:774:774) (904:904:904)) - (PORT d[3] (752:752:752) (876:876:876)) - (PORT d[4] (1529:1529:1529) (1777:1777:1777)) - (PORT d[5] (892:892:892) (1032:1032:1032)) - (PORT d[6] (871:871:871) (1009:1009:1009)) - (PORT d[7] (887:887:887) (1025:1025:1025)) - (PORT d[8] (876:876:876) (1011:1011:1011)) - (PORT d[9] (966:966:966) (1116:1116:1116)) - (PORT d[10] (786:786:786) (911:911:911)) - (PORT d[11] (1079:1079:1079) (1263:1263:1263)) - (PORT d[12] (817:817:817) (952:952:952)) + (PORT d[0] (559:559:559) (651:651:651)) + (PORT d[1] (970:970:970) (1111:1111:1111)) + (PORT d[2] (556:556:556) (648:648:648)) + (PORT d[3] (1624:1624:1624) (1878:1878:1878)) + (PORT d[4] (1455:1455:1455) (1685:1685:1685)) + (PORT d[5] (524:524:524) (608:608:608)) + (PORT d[6] (671:671:671) (776:776:776)) + (PORT d[7] (849:849:849) (977:977:977)) + (PORT d[8] (944:944:944) (1082:1082:1082)) + (PORT d[9] (1021:1021:1021) (1177:1177:1177)) + (PORT d[10] (1426:1426:1426) (1645:1645:1645)) + (PORT d[11] (700:700:700) (812:812:812)) + (PORT d[12] (973:973:973) (1146:1146:1146)) (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) @@ -46348,10 +48986,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (712:712:712) (763:763:763)) + (PORT d[0] (1324:1324:1324) (1453:1453:1453)) (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) @@ -46361,17 +48999,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1305:1305:1305) (1425:1425:1425)) + (PORT d[0] (1354:1354:1354) (1451:1451:1451)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1108:1108:1108)) @@ -46381,7 +49019,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1108:1108:1108)) @@ -46391,7 +49029,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1108:1108:1108)) @@ -46401,7 +49039,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1108:1108:1108)) @@ -46411,7 +49049,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1070:1070:1070) (1086:1086:1086)) @@ -46425,7 +49063,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -46434,7 +49072,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -46443,7 +49081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -46453,7 +49091,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -46461,28 +49099,13 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (572:572:572)) - (PORT datab (684:684:684) (804:804:804)) - (PORT datad (506:506:506) (572:572:572)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (770:770:770) (901:901:901)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (904:904:904) (1050:1050:1050)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -46491,23 +49114,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1737:1737:1737) (2036:2036:2036)) - (PORT d[1] (1672:1672:1672) (1893:1893:1893)) - (PORT d[2] (558:558:558) (646:646:646)) - (PORT d[3] (727:727:727) (845:845:845)) - (PORT d[4] (1178:1178:1178) (1352:1352:1352)) - (PORT d[5] (521:521:521) (603:603:603)) - (PORT d[6] (646:646:646) (743:743:743)) - (PORT d[7] (1544:1544:1544) (1769:1769:1769)) - (PORT d[8] (895:895:895) (1036:1036:1036)) - (PORT d[9] (237:237:237) (279:279:279)) - (PORT d[10] (230:230:230) (272:272:272)) - (PORT d[11] (1620:1620:1620) (1888:1888:1888)) - (PORT d[12] (410:410:410) (481:481:481)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) + (PORT d[0] (1479:1479:1479) (1678:1678:1678)) + (PORT d[1] (1352:1352:1352) (1530:1530:1530)) + (PORT d[2] (1299:1299:1299) (1481:1481:1481)) + (PORT d[3] (499:499:499) (580:580:580)) + (PORT d[4] (1520:1520:1520) (1779:1779:1779)) + (PORT d[5] (1534:1534:1534) (1735:1735:1735)) + (PORT d[6] (2317:2317:2317) (2671:2671:2671)) + (PORT d[7] (782:782:782) (891:891:891)) + (PORT d[8] (528:528:528) (608:608:608)) + (PORT d[9] (846:846:846) (971:971:971)) + (PORT d[10] (1185:1185:1185) (1351:1351:1351)) + (PORT d[11] (1490:1490:1490) (1690:1690:1690)) + (PORT d[12] (730:730:730) (853:853:853)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -46516,11 +49139,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (695:695:695) (740:740:740)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) + (PORT d[0] (1365:1365:1365) (1481:1481:1481)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -46529,60 +49152,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (952:952:952) (1002:1002:1002)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1642:1642:1642) (1765:1765:1765)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) + (PORT clk (1070:1070:1070) (1087:1087:1087)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -46593,280 +49216,48 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) + (PORT clk (610:610:610) (619:619:619)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) + (PORT clk (611:611:611) (620:620:620)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) + (PORT clk (611:611:611) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (610:610:610)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (666:666:666) (783:783:783)) - (PORT datad (830:830:830) (931:931:931)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (653:653:653) (730:730:730)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1794:1794:1794) (2076:2076:2076)) - (PORT d[1] (1219:1219:1219) (1388:1388:1388)) - (PORT d[2] (937:937:937) (1091:1091:1091)) - (PORT d[3] (881:881:881) (1012:1012:1012)) - (PORT d[4] (1544:1544:1544) (1795:1795:1795)) - (PORT d[5] (899:899:899) (1035:1035:1035)) - (PORT d[6] (867:867:867) (999:999:999)) - (PORT d[7] (1087:1087:1087) (1259:1259:1259)) - (PORT d[8] (1991:1991:1991) (2288:2288:2288)) - (PORT d[9] (846:846:846) (983:983:983)) - (PORT d[10] (968:968:968) (1123:1123:1123)) - (PORT d[11] (1052:1052:1052) (1228:1228:1228)) - (PORT d[12] (974:974:974) (1128:1128:1128)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (843:843:843) (906:906:906)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (PORT d[0] (1758:1758:1758) (1639:1639:1639)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1042:1042:1042) (1062:1062:1062)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1013:1013:1013) (1151:1151:1151)) - (PORT clk (1047:1047:1047) (1065:1065:1065)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2513:2513:2513) (2845:2845:2845)) - (PORT d[1] (2464:2464:2464) (2777:2777:2777)) - (PORT d[2] (2478:2478:2478) (2811:2811:2811)) - (PORT d[3] (2418:2418:2418) (2748:2748:2748)) - (PORT d[4] (2440:2440:2440) (2745:2745:2745)) - (PORT d[5] (2489:2489:2489) (2844:2844:2844)) - (PORT d[6] (2482:2482:2482) (2797:2797:2797)) - (PORT d[7] (2475:2475:2475) (2809:2809:2809)) - (PORT d[8] (2516:2516:2516) (2871:2871:2871)) - (PORT d[9] (2535:2535:2535) (2906:2906:2906)) - (PORT d[10] (2539:2539:2539) (2877:2877:2877)) - (PORT d[11] (2523:2523:2523) (2865:2865:2865)) - (PORT d[12] (2439:2439:2439) (2762:2762:2762)) - (PORT clk (1044:1044:1044) (1064:1064:1064)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (611:611:611) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT clk (1043:1043:1043) (1063:1063:1063)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (664:664:664) (753:753:753)) + (PORT d[0] (567:567:567) (649:649:649)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -46876,22 +49267,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1794:1794:1794) (2077:2077:2077)) - (PORT d[1] (887:887:887) (1017:1017:1017)) - (PORT d[2] (932:932:932) (1085:1085:1085)) - (PORT d[3] (874:874:874) (1005:1005:1005)) - (PORT d[4] (1528:1528:1528) (1772:1772:1772)) - (PORT d[5] (892:892:892) (1027:1027:1027)) - (PORT d[6] (888:888:888) (1030:1030:1030)) - (PORT d[7] (937:937:937) (1093:1093:1093)) - (PORT d[8] (877:877:877) (1011:1011:1011)) - (PORT d[9] (832:832:832) (962:962:962)) - (PORT d[10] (806:806:806) (939:939:939)) - (PORT d[11] (1057:1057:1057) (1232:1232:1232)) - (PORT d[12] (818:818:818) (953:953:953)) + (PORT d[0] (559:559:559) (646:646:646)) + (PORT d[1] (551:551:551) (629:629:629)) + (PORT d[2] (573:573:573) (667:667:667)) + (PORT d[3] (1279:1279:1279) (1486:1486:1486)) + (PORT d[4] (538:538:538) (624:624:624)) + (PORT d[5] (515:515:515) (598:598:598)) + (PORT d[6] (523:523:523) (608:608:608)) + (PORT d[7] (662:662:662) (760:760:760)) + (PORT d[8] (794:794:794) (918:918:918)) + (PORT d[9] (983:983:983) (1133:1133:1133)) + (PORT d[10] (971:971:971) (1144:1144:1144)) + (PORT d[11] (713:713:713) (827:827:827)) + (PORT d[12] (764:764:764) (907:907:907)) (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) @@ -46901,10 +49292,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (777:777:777) (837:837:837)) + (PORT d[0] (832:832:832) (900:900:900)) (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) @@ -46914,17 +49305,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1455:1455:1455) (1578:1578:1578)) + (PORT d[0] (1101:1101:1101) (1172:1172:1172)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -46934,7 +49325,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -46944,7 +49335,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -46954,7 +49345,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1107:1107:1107)) @@ -46964,10 +49355,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) + (PORT clk (1069:1069:1069) (1085:1085:1085)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -46978,141 +49369,149 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1024:1024:1024) (1162:1162:1162)) - (PORT clk (1049:1049:1049) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2513:2513:2513) (2852:2852:2852)) - (PORT d[1] (2455:2455:2455) (2753:2753:2753)) - (PORT d[2] (2498:2498:2498) (2840:2840:2840)) - (PORT d[3] (2429:2429:2429) (2762:2762:2762)) - (PORT d[4] (2454:2454:2454) (2786:2786:2786)) - (PORT d[5] (2473:2473:2473) (2815:2815:2815)) - (PORT d[6] (2464:2464:2464) (2767:2767:2767)) - (PORT d[7] (2472:2472:2472) (2802:2802:2802)) - (PORT d[8] (2496:2496:2496) (2844:2844:2844)) - (PORT d[9] (2502:2502:2502) (2852:2852:2852)) - (PORT d[10] (2558:2558:2558) (2903:2903:2903)) - (PORT d[11] (2528:2528:2528) (2880:2880:2880)) - (PORT d[12] (2434:2434:2434) (2756:2756:2756)) - (PORT clk (1046:1046:1046) (1065:1065:1065)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1066:1066:1066)) + (PORT clk (609:609:609) (617:617:617)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1050:1050:1050) (1067:1067:1067)) + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (786:786:786) (881:881:881)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1498:1498:1498) (1699:1699:1699)) + (PORT d[1] (1349:1349:1349) (1526:1526:1526)) + (PORT d[2] (1322:1322:1322) (1508:1508:1508)) + (PORT d[3] (324:324:324) (370:370:370)) + (PORT d[4] (1513:1513:1513) (1776:1776:1776)) + (PORT d[5] (1556:1556:1556) (1759:1759:1759)) + (PORT d[6] (1862:1862:1862) (2161:2161:2161)) + (PORT d[7] (611:611:611) (699:699:699)) + (PORT d[8] (824:824:824) (943:943:943)) + (PORT d[9] (815:815:815) (929:929:929)) + (PORT d[10] (1188:1188:1188) (1350:1350:1350)) + (PORT d[11] (1498:1498:1498) (1699:1699:1699)) + (PORT d[12] (577:577:577) (674:674:674)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1011:1011:1011) (1115:1115:1115)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1325:1325:1325) (1410:1410:1410)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1050:1050:1050) (1067:1067:1067)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1431:1431:1431)) - (PORT d[1] (1385:1385:1385) (1574:1574:1574)) - (PORT d[2] (1425:1425:1425) (1650:1650:1650)) - (PORT d[3] (1351:1351:1351) (1538:1538:1538)) - (PORT d[4] (1149:1149:1149) (1336:1336:1336)) - (PORT d[5] (1410:1410:1410) (1611:1611:1611)) - (PORT d[6] (1438:1438:1438) (1657:1657:1657)) - (PORT d[7] (1453:1453:1453) (1675:1675:1675)) - (PORT d[8] (1418:1418:1418) (1627:1627:1627)) - (PORT d[9] (1406:1406:1406) (1619:1619:1619)) - (PORT d[10] (1723:1723:1723) (1984:1984:1984)) - (PORT d[11] (1177:1177:1177) (1361:1361:1361)) - (PORT d[12] (1361:1361:1361) (1566:1566:1566)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1117:1117:1117)) - (PORT d[0] (1530:1530:1530) (1728:1728:1728)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1101:1101:1101) (1118:1118:1118)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1082:1082:1082) (1098:1098:1098)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -47123,165 +49522,52 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (622:622:622) (630:630:630)) + (PORT clk (610:610:610) (619:619:619)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (623:623:623) (631:631:631)) + (PORT clk (611:611:611) (620:620:620)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (623:623:623) (631:631:631)) + (PORT clk (611:611:611) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (623:623:623) (631:631:631)) + (PORT clk (611:611:611) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~90) + (INSTANCE Selector8\~7) (DELAY (ABSOLUTE - (PORT dataa (672:672:672) (780:780:780)) - (PORT datab (383:383:383) (454:454:454)) - (PORT datac (516:516:516) (584:584:584)) - (PORT datad (667:667:667) (757:757:757)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1239:1239:1239) (1446:1446:1446)) - (PORT d[1] (1395:1395:1395) (1590:1590:1590)) - (PORT d[2] (1493:1493:1493) (1706:1706:1706)) - (PORT d[3] (1743:1743:1743) (1968:1968:1968)) - (PORT d[4] (1109:1109:1109) (1313:1313:1313)) - (PORT d[5] (1957:1957:1957) (2231:2231:2231)) - (PORT d[6] (1605:1605:1605) (1824:1824:1824)) - (PORT d[7] (1907:1907:1907) (2171:2171:2171)) - (PORT d[8] (1191:1191:1191) (1365:1365:1365)) - (PORT d[9] (1773:1773:1773) (2025:2025:2025)) - (PORT d[10] (1307:1307:1307) (1492:1492:1492)) - (PORT d[11] (1405:1405:1405) (1638:1638:1638)) - (PORT d[12] (1913:1913:1913) (2172:2172:2172)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1121:1121:1121)) - (PORT d[0] (1857:1857:1857) (1662:1662:1662)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1104:1104:1104) (1122:1122:1122)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1102:1102:1102)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (625:625:625) (634:634:634)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (576:576:576)) - (PORT datab (737:737:737) (854:854:854)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (890:890:890) (1007:1007:1007)) - (IOPATH dataa combout (188:188:188) (203:203:203)) + (PORT dataa (848:848:848) (989:989:989)) + (PORT datab (609:609:609) (695:695:695)) + (PORT datac (958:958:958) (1109:1109:1109)) + (PORT datad (780:780:780) (890:890:890)) + (IOPATH dataa combout (188:188:188) (193:193:193)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -47290,15 +49576,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~92) + (INSTANCE Selector8\~8) (DELAY (ABSOLUTE - (PORT dataa (541:541:541) (619:619:619)) - (PORT datab (380:380:380) (451:451:451)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (161:161:161) (187:187:187)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (961:961:961) (1101:1101:1101)) + (PORT datab (844:844:844) (979:979:979)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (1125:1125:1125) (1278:1278:1278)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47306,45 +49592,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~125) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) (DELAY (ABSOLUTE - (PORT dataa (1450:1450:1450) (1707:1707:1707)) - (PORT datab (756:756:756) (883:883:883)) - (PORT datac (294:294:294) (342:342:342)) - (PORT datad (163:163:163) (192:192:192)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (599:599:599)) - (PORT datab (498:498:498) (576:576:576)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (326:326:326) (379:379:379)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1445:1445:1445)) - (PORT datab (227:227:227) (273:273:273)) - (PORT datac (104:104:104) (126:126:126)) - (PORT datad (702:702:702) (825:825:825)) + (PORT dataa (542:542:542) (650:650:650)) + (PORT datab (374:374:374) (452:452:452)) + (PORT datac (515:515:515) (610:610:610)) + (PORT datad (213:213:213) (270:270:270)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -47354,60 +49608,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) (DELAY (ABSOLUTE - (PORT dataa (995:995:995) (1153:1153:1153)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (280:280:280) (320:320:320)) - (PORT datad (621:621:621) (711:711:711)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (540:540:540) (648:648:648)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (513:513:513) (610:610:610)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (431:431:431)) + (PORT datab (231:231:231) (287:287:287)) + (PORT datac (165:165:165) (200:200:200)) + (PORT datad (163:163:163) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (138:138:138)) + (PORT datab (340:340:340) (399:399:399)) + (PORT datad (513:513:513) (601:601:601)) + (IOPATH dataa combout (159:159:159) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) + (PORT clrn (891:891:891) (894:894:894)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (193:193:193)) - (PORT datab (218:218:218) (259:259:259)) - (PORT datad (198:198:198) (237:237:237)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datab (172:172:172) (210:210:210)) - (PORT datac (273:273:273) (312:312:312)) - (PORT datad (116:116:116) (140:140:140)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (111:111:111) (144:144:144)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datac (515:515:515) (610:610:610)) + (PORT datad (111:111:111) (131:131:131)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -47415,30 +49686,63 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (473:473:473) (516:516:516)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1057:1057:1057) (1164:1164:1164)) + (PORT dataa (197:197:197) (236:236:236)) + (PORT datab (183:183:183) (223:223:223)) + (PORT datad (328:328:328) (384:384:384)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~15) (DELAY (ABSOLUTE - (PORT datac (1072:1072:1072) (1238:1238:1238)) - (PORT datad (1443:1443:1443) (1657:1657:1657)) + (PORT dataa (857:857:857) (999:999:999)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (1151:1151:1151) (1318:1318:1318)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (541:541:541)) + (PORT datab (422:422:422) (515:515:515)) + (PORT datac (397:397:397) (489:489:489)) + (PORT datad (388:388:388) (475:475:475)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47446,15 +49750,154 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) (DELAY (ABSOLUTE - (PORT dataa (494:494:494) (576:576:576)) - (PORT datab (354:354:354) (415:415:415)) - (PORT datac (1153:1153:1153) (1375:1375:1375)) - (PORT datad (780:780:780) (882:882:882)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT dataa (119:119:119) (151:151:151)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (894:894:894) (900:900:900)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (612:612:612)) + (PORT datab (343:343:343) (403:403:403)) + (PORT datac (347:347:347) (406:406:406)) + (PORT datad (500:500:500) (601:601:601)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (554:554:554) (663:663:663)) + (PORT datad (240:240:240) (301:301:301)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (414:414:414)) + (PORT datab (2228:2228:2228) (2581:2581:2581)) + (PORT datac (115:115:115) (155:155:155)) + (PORT datad (1814:1814:1814) (2098:2098:2098)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (496:496:496)) + (PORT datac (380:380:380) (464:464:464)) + (PORT datad (380:380:380) (461:461:461)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (215:215:215)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datad (240:240:240) (301:301:301)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (294:294:294)) + (PORT datab (479:479:479) (573:573:573)) + (PORT datac (398:398:398) (485:485:485)) + (PORT datad (413:413:413) (508:508:508)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47462,13 +49905,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) (DELAY (ABSOLUTE - (PORT dataa (128:128:128) (164:164:164)) - (PORT datab (505:505:505) (584:584:584)) - (PORT datac (962:962:962) (1127:1127:1127)) - (PORT datad (351:351:351) (412:412:412)) + (PORT datab (413:413:413) (505:505:505)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (392:392:392) (480:480:480)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (500:500:500)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (372:372:372) (452:452:452)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (963:963:963) (1111:1111:1111)) + (PORT datac (1279:1279:1279) (1505:1505:1505)) + (PORT datad (327:327:327) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (639:639:639)) + (PORT datab (534:534:534) (636:636:636)) + (PORT datac (339:339:339) (394:394:394)) + (PORT datad (103:103:103) (121:121:121)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -47478,29 +49996,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (425:425:425)) - (PORT datab (208:208:208) (253:253:253)) - (PORT datac (812:812:812) (950:950:950)) - (PORT datad (188:188:188) (222:222:222)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (225:225:225) (292:292:292)) + (PORT datab (419:419:419) (511:511:511)) + (PORT datac (394:394:394) (486:486:486)) + (PORT datad (391:391:391) (478:478:478)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT dataa (1281:1281:1281) (1507:1507:1507)) - (PORT datab (900:900:900) (1024:1024:1024)) - (PORT datac (784:784:784) (945:945:945)) - (PORT datad (700:700:700) (796:796:796)) + (PORT dataa (705:705:705) (835:835:835)) + (PORT datab (527:527:527) (627:627:627)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (645:645:645)) + (PORT datab (535:535:535) (637:637:637)) + (PORT datac (161:161:161) (189:189:189)) + (PORT datad (326:326:326) (379:379:379)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (412:412:412) (504:504:504)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (494:494:494) (577:577:577)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (647:647:647)) + (PORT datab (407:407:407) (503:503:503)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (394:394:394) (475:475:475)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -47508,15 +50073,576 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (474:474:474) (549:549:549)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (654:654:654)) + (PORT datab (683:683:683) (806:806:806)) + (PORT datad (606:606:606) (713:713:713)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (673:673:673)) + (PORT datab (508:508:508) (578:578:578)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (417:417:417)) + (PORT datab (1207:1207:1207) (1408:1408:1408)) + (PORT datac (1133:1133:1133) (1295:1295:1295)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (405:405:405)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (311:311:311) (359:359:359)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1217:1217:1217)) + (PORT datab (1051:1051:1051) (1189:1189:1189)) + (PORT datac (873:873:873) (986:986:986)) + (PORT datad (966:966:966) (1111:1111:1111)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~9) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (658:658:658) (762:762:762)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (744:744:744)) + (PORT datab (620:620:620) (737:737:737)) + (PORT datac (748:748:748) (855:855:855)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (522:522:522)) + (PORT datab (831:831:831) (976:976:976)) + (PORT datac (488:488:488) (566:566:566)) + (PORT datad (126:126:126) (158:158:158)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (181:181:181)) + (PORT datac (346:346:346) (413:413:413)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (580:580:580)) + (PORT datab (559:559:559) (638:638:638)) + (PORT datac (804:804:804) (933:933:933)) + (PORT datad (492:492:492) (586:586:586)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (134:134:134) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (1073:1073:1073) (1180:1180:1180)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1167:1167:1167)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datac (454:454:454) (535:535:535)) + (PORT datad (536:536:536) (639:639:639)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT datab (622:622:622) (738:738:738)) + (PORT datac (370:370:370) (455:455:455)) + (PORT datad (382:382:382) (456:456:456)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT datac (608:608:608) (695:695:695)) + (PORT datad (318:318:318) (367:367:367)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~60) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (816:816:816)) + (PORT datab (516:516:516) (603:603:603)) + (PORT datac (1227:1227:1227) (1435:1435:1435)) + (PORT datad (821:821:821) (953:953:953)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1183:1183:1183)) + (PORT datab (521:521:521) (609:609:609)) + (PORT datac (511:511:511) (599:599:599)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1524:1524:1524)) + (PORT datab (348:348:348) (403:403:403)) + (PORT datac (679:679:679) (802:802:802)) + (PORT datad (605:605:605) (701:701:701)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (414:414:414)) + (PORT datab (375:375:375) (446:446:446)) + (PORT datac (480:480:480) (549:549:549)) + (PORT datad (333:333:333) (387:387:387)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (625:625:625) (712:712:712)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1300:1300:1300)) + (PORT datab (365:365:365) (429:429:429)) + (PORT datac (627:627:627) (713:713:713)) + (PORT datad (1169:1169:1169) (1326:1326:1326)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (780:780:780)) + (PORT datab (444:444:444) (503:503:503)) + (PORT datac (435:435:435) (505:505:505)) + (PORT datad (804:804:804) (920:920:920)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (856:856:856)) + (PORT datab (874:874:874) (1035:1035:1035)) + (PORT datac (615:615:615) (693:693:693)) + (PORT datad (801:801:801) (914:914:914)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (720:720:720)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (623:623:623) (712:712:712)) + (PORT datad (351:351:351) (413:413:413)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (581:581:581)) + (PORT datab (473:473:473) (543:543:543)) + (PORT datac (707:707:707) (817:817:817)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (681:681:681)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (663:663:663) (785:785:785)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (771:771:771) (942:942:942)) + (PORT datac (130:130:130) (171:171:171)) + (PORT datad (977:977:977) (1146:1146:1146)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT datac (537:537:537) (644:644:644)) + (PORT datad (461:461:461) (549:549:549)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|nmi_armed) + (DELAY + (ABSOLUTE + (PORT clk (1021:1021:1021) (1117:1117:1117)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (390:390:390) (408:408:408)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (919:919:919)) - (PORT asdata (639:639:639) (720:720:720)) - (PORT clrn (925:925:925) (906:906:906)) - (PORT ena (508:508:508) (552:552:552)) + (PORT clk (906:906:906) (910:910:910)) + (PORT asdata (600:600:600) (667:667:667)) + (PORT clrn (904:904:904) (890:890:890)) + (PORT ena (406:406:406) (423:423:423)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -47528,45 +50654,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (INSTANCE z80_\|interrupts_\|im1\~feeder) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (435:435:435)) - (PORT datab (497:497:497) (579:579:579)) - (PORT datac (585:585:585) (682:682:682)) - (PORT datad (653:653:653) (759:759:759)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (525:525:525)) - (PORT datab (621:621:621) (720:720:720)) - (PORT datac (555:555:555) (624:624:624)) - (PORT datad (445:445:445) (514:514:514)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (107:107:107) (127:127:127)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) + (INSTANCE z80_\|interrupts_\|im1) (DELAY (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) + (PORT clk (907:907:907) (912:912:912)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (448:448:448)) + (PORT clrn (905:905:905) (892:892:892)) + (PORT ena (911:911:911) (1018:1018:1018)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -47576,690 +50682,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (314:314:314) (375:375:375)) - (PORT datab (644:644:644) (744:744:744)) - (PORT datac (351:351:351) (426:426:426)) - (PORT datad (310:310:310) (362:362:362)) + (PORT dataa (299:299:299) (364:364:364)) + (PORT datab (246:246:246) (306:306:306)) + (PORT datac (683:683:683) (795:795:795)) + (PORT datad (368:368:368) (440:440:440)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~16) + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (566:566:566)) - (PORT datab (323:323:323) (380:380:380)) - (PORT datac (804:804:804) (920:920:920)) - (PORT datad (330:330:330) (385:385:385)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (605:605:605) (698:698:698)) - (PORT datac (460:460:460) (529:529:529)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (628:628:628) (737:737:737)) + (PORT datab (380:380:380) (455:455:455)) + (PORT datac (687:687:687) (799:799:799)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (830:830:830) (926:926:926)) - (PORT clk (1083:1083:1083) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1776:1776:1776) (2058:2058:2058)) - (PORT d[1] (1062:1062:1062) (1215:1215:1215)) - (PORT d[2] (960:960:960) (1119:1119:1119)) - (PORT d[3] (1261:1261:1261) (1446:1446:1446)) - (PORT d[4] (1353:1353:1353) (1575:1575:1575)) - (PORT d[5] (1163:1163:1163) (1337:1337:1337)) - (PORT d[6] (1074:1074:1074) (1247:1247:1247)) - (PORT d[7] (1114:1114:1114) (1293:1293:1293)) - (PORT d[8] (1960:1960:1960) (2249:2249:2249)) - (PORT d[9] (1032:1032:1032) (1197:1197:1197)) - (PORT d[10] (2242:2242:2242) (2565:2565:2565)) - (PORT d[11] (1534:1534:1534) (1760:1760:1760)) - (PORT d[12] (1444:1444:1444) (1655:1655:1655)) - (PORT clk (1081:1081:1081) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1307:1307:1307) (1441:1441:1441)) - (PORT clk (1081:1081:1081) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1102:1102:1102)) - (PORT d[0] (1633:1633:1633) (1777:1777:1777)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1038:1038:1038) (1059:1059:1059)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1011:1011:1011) (1149:1149:1149)) - (PORT clk (1043:1043:1043) (1062:1062:1062)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2450:2450:2450) (2773:2773:2773)) - (PORT d[1] (2425:2425:2425) (2759:2759:2759)) - (PORT d[2] (2450:2450:2450) (2792:2792:2792)) - (PORT d[3] (2397:2397:2397) (2725:2725:2725)) - (PORT d[4] (2481:2481:2481) (2811:2811:2811)) - (PORT d[5] (2487:2487:2487) (2829:2829:2829)) - (PORT d[6] (2432:2432:2432) (2730:2730:2730)) - (PORT d[7] (2467:2467:2467) (2797:2797:2797)) - (PORT d[8] (2458:2458:2458) (2776:2776:2776)) - (PORT d[9] (2504:2504:2504) (2850:2850:2850)) - (PORT d[10] (2495:2495:2495) (2826:2826:2826)) - (PORT d[11] (2542:2542:2542) (2884:2884:2884)) - (PORT d[12] (2379:2379:2379) (2691:2691:2691)) - (PORT clk (1040:1040:1040) (1061:1061:1061)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1043:1043:1043) (1062:1062:1062)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (953:953:953) (1121:1121:1121)) - (PORT d[1] (1588:1588:1588) (1781:1781:1781)) - (PORT d[2] (1506:1506:1506) (1725:1725:1725)) - (PORT d[3] (1439:1439:1439) (1627:1627:1627)) - (PORT d[4] (1363:1363:1363) (1567:1567:1567)) - (PORT d[5] (1649:1649:1649) (1884:1884:1884)) - (PORT d[6] (1613:1613:1613) (1832:1832:1832)) - (PORT d[7] (1832:1832:1832) (2090:2090:2090)) - (PORT d[8] (1309:1309:1309) (1495:1495:1495)) - (PORT d[9] (1795:1795:1795) (2050:2050:2050)) - (PORT d[10] (1317:1317:1317) (1500:1500:1500)) - (PORT d[11] (1431:1431:1431) (1669:1669:1669)) - (PORT d[12] (1737:1737:1737) (1972:1972:1972)) - (PORT clk (1106:1106:1106) (1123:1123:1123)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) - (PORT d[0] (1682:1682:1682) (1879:1879:1879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1104:1104:1104)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (785:785:785) (881:881:881)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1103:1103:1103) (1297:1297:1297)) - (PORT d[1] (1760:1760:1760) (2007:2007:2007)) - (PORT d[2] (1018:1018:1018) (1168:1168:1168)) - (PORT d[3] (2095:2095:2095) (2370:2370:2370)) - (PORT d[4] (1509:1509:1509) (1776:1776:1776)) - (PORT d[5] (2332:2332:2332) (2661:2661:2661)) - (PORT d[6] (1309:1309:1309) (1494:1494:1494)) - (PORT d[7] (2117:2117:2117) (2413:2413:2413)) - (PORT d[8] (1064:1064:1064) (1252:1252:1252)) - (PORT d[9] (1422:1422:1422) (1624:1624:1624)) - (PORT d[10] (1515:1515:1515) (1727:1727:1727)) - (PORT d[11] (1593:1593:1593) (1867:1867:1867)) - (PORT d[12] (2530:2530:2530) (2863:2863:2863)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1802:1802:1802) (1970:1970:1970)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (PORT d[0] (1950:1950:1950) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1064:1064:1064)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1194:1194:1194) (1331:1331:1331)) - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2452:2452:2452) (2779:2779:2779)) - (PORT d[1] (2493:2493:2493) (2817:2817:2817)) - (PORT d[2] (2441:2441:2441) (2771:2771:2771)) - (PORT d[3] (2429:2429:2429) (2742:2742:2742)) - (PORT d[4] (2401:2401:2401) (2731:2731:2731)) - (PORT d[5] (2450:2450:2450) (2769:2769:2769)) - (PORT d[6] (2440:2440:2440) (2740:2740:2740)) - (PORT d[7] (2336:2336:2336) (2624:2624:2624)) - (PORT d[8] (2481:2481:2481) (2800:2800:2800)) - (PORT d[9] (2543:2543:2543) (2882:2882:2882)) - (PORT d[10] (2375:2375:2375) (2669:2669:2669)) - (PORT d[11] (2459:2459:2459) (2799:2799:2799)) - (PORT d[12] (2337:2337:2337) (2636:2636:2636)) - (PORT clk (1046:1046:1046) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1045:1045:1045) (1065:1065:1065)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (986:986:986) (1169:1169:1169)) - (PORT d[1] (787:787:787) (890:890:890)) - (PORT d[2] (1313:1313:1313) (1526:1526:1526)) - (PORT d[3] (956:956:956) (1091:1091:1091)) - (PORT d[4] (1386:1386:1386) (1605:1605:1605)) - (PORT d[5] (1595:1595:1595) (1812:1812:1812)) - (PORT d[6] (1115:1115:1115) (1271:1271:1271)) - (PORT d[7] (957:957:957) (1081:1081:1081)) - (PORT d[8] (1223:1223:1223) (1429:1429:1429)) - (PORT d[9] (974:974:974) (1103:1103:1103)) - (PORT d[10] (1434:1434:1434) (1618:1618:1618)) - (PORT d[11] (2347:2347:2347) (2730:2730:2730)) - (PORT d[12] (777:777:777) (874:874:874)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1305:1305:1305) (1190:1190:1190)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) + (INSTANCE z80_\|bus_control_\|db\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (672:672:672) (780:780:780)) - (PORT datab (384:384:384) (455:455:455)) - (PORT datac (761:761:761) (868:868:868)) - (PORT datad (917:917:917) (1057:1057:1057)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (773:773:773)) - (PORT datab (381:381:381) (451:451:451)) - (PORT datac (1038:1038:1038) (1187:1187:1187)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (500:500:500) (582:582:582)) + (PORT datab (145:145:145) (184:184:184)) + (PORT datac (777:777:777) (899:899:899)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -48270,8 +50733,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (714:714:714) (826:826:826)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (541:541:541) (624:624:624)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -48283,20 +50746,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1332:1332:1332) (1566:1566:1566)) - (PORT d[1] (1292:1292:1292) (1461:1461:1461)) - (PORT d[2] (1060:1060:1060) (1218:1218:1218)) - (PORT d[3] (1424:1424:1424) (1625:1625:1625)) - (PORT d[4] (1157:1157:1157) (1327:1327:1327)) - (PORT d[5] (897:897:897) (1031:1031:1031)) - (PORT d[6] (983:983:983) (1120:1120:1120)) - (PORT d[7] (1347:1347:1347) (1557:1557:1557)) - (PORT d[8] (1406:1406:1406) (1654:1654:1654)) - (PORT d[9] (708:708:708) (811:811:811)) - (PORT d[10] (927:927:927) (1052:1052:1052)) - (PORT d[11] (653:653:653) (747:747:747)) - (PORT d[12] (591:591:591) (680:680:680)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (2063:2063:2063) (2348:2348:2348)) + (PORT d[1] (1931:1931:1931) (2192:2192:2192)) + (PORT d[2] (1953:1953:1953) (2216:2216:2216)) + (PORT d[3] (2182:2182:2182) (2532:2532:2532)) + (PORT d[4] (1547:1547:1547) (1813:1813:1813)) + (PORT d[5] (1360:1360:1360) (1550:1550:1550)) + (PORT d[6] (1965:1965:1965) (2274:2274:2274)) + (PORT d[7] (2761:2761:2761) (3126:3126:3126)) + (PORT d[8] (1884:1884:1884) (2192:2192:2192)) + (PORT d[9] (2281:2281:2281) (2633:2633:2633)) + (PORT d[10] (1987:1987:1987) (2310:2310:2310)) + (PORT d[11] (1744:1744:1744) (1993:1993:1993)) + (PORT d[12] (1390:1390:1390) (1649:1649:1649)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -48308,8 +50771,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (877:877:877) (948:948:948)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (933:933:933) (1000:1000:1000)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -48321,8 +50784,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (1122:1122:1122) (1200:1200:1200)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1398:1398:1398) (1498:1498:1498)) ) ) ) @@ -48331,7 +50794,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -48341,7 +50804,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -48351,7 +50814,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -48361,7 +50824,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -48371,7 +50834,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1088:1088:1088)) + (PORT clk (1075:1075:1075) (1091:1091:1091)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -48385,7 +50848,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (615:615:615) (623:623:623)) ) ) ) @@ -48394,7 +50857,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (616:616:616) (624:624:624)) ) ) ) @@ -48403,7 +50866,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (616:616:616) (624:624:624)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -48413,7 +50876,160 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) + (PORT clk (616:616:616) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (545:545:545) (619:619:619)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1881:1881:1881) (2139:2139:2139)) + (PORT d[1] (1743:1743:1743) (1977:1977:1977)) + (PORT d[2] (2134:2134:2134) (2420:2420:2420)) + (PORT d[3] (968:968:968) (1093:1093:1093)) + (PORT d[4] (1705:1705:1705) (1996:1996:1996)) + (PORT d[5] (1605:1605:1605) (1817:1817:1817)) + (PORT d[6] (2159:2159:2159) (2492:2492:2492)) + (PORT d[7] (986:986:986) (1117:1117:1117)) + (PORT d[8] (2066:2066:2066) (2399:2399:2399)) + (PORT d[9] (2456:2456:2456) (2832:2832:2832)) + (PORT d[10] (2206:2206:2206) (2568:2568:2568)) + (PORT d[11] (1932:1932:1932) (2209:2209:2209)) + (PORT d[12] (1578:1578:1578) (1862:1862:1862)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1027:1027:1027) (1137:1137:1137)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1328:1328:1328) (1415:1415:1415)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -48423,7 +51039,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (639:639:639) (714:714:714)) + (PORT d[0] (526:526:526) (587:587:587)) (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) @@ -48436,19 +51052,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1708:1708:1708) (1990:1990:1990)) - (PORT d[1] (1930:1930:1930) (2206:2206:2206)) - (PORT d[2] (1111:1111:1111) (1275:1275:1275)) - (PORT d[3] (2312:2312:2312) (2621:2621:2621)) - (PORT d[4] (1679:1679:1679) (1964:1964:1964)) - (PORT d[5] (2543:2543:2543) (2907:2907:2907)) - (PORT d[6] (1268:1268:1268) (1439:1439:1439)) - (PORT d[7] (973:973:973) (1104:1104:1104)) - (PORT d[8] (1803:1803:1803) (2097:2097:2097)) - (PORT d[9] (1062:1062:1062) (1215:1215:1215)) - (PORT d[10] (1165:1165:1165) (1326:1326:1326)) - (PORT d[11] (1786:1786:1786) (2092:2092:2092)) - (PORT d[12] (2544:2544:2544) (2884:2884:2884)) + (PORT d[0] (1882:1882:1882) (2140:2140:2140)) + (PORT d[1] (1909:1909:1909) (2167:2167:2167)) + (PORT d[2] (2139:2139:2139) (2428:2428:2428)) + (PORT d[3] (2203:2203:2203) (2555:2555:2555)) + (PORT d[4] (1537:1537:1537) (1806:1806:1806)) + (PORT d[5] (1552:1552:1552) (1772:1772:1772)) + (PORT d[6] (1981:1981:1981) (2291:2291:2291)) + (PORT d[7] (2793:2793:2793) (3165:3165:3165)) + (PORT d[8] (2075:2075:2075) (2409:2409:2409)) + (PORT d[9] (2466:2466:2466) (2844:2844:2844)) + (PORT d[10] (2033:2033:2033) (2369:2369:2369)) + (PORT d[11] (1907:1907:1907) (2178:2178:2178)) + (PORT d[12] (1373:1373:1373) (1620:1620:1620)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -48461,7 +51077,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (895:895:895) (956:956:956)) + (PORT d[0] (1446:1446:1446) (1586:1586:1586)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -48475,7 +51091,7 @@ (DELAY (ABSOLUTE (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1405:1405:1405) (1513:1513:1513)) + (PORT d[0] (1227:1227:1227) (1306:1306:1306)) ) ) ) @@ -48571,171 +51187,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (797:797:797) (892:892:892)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1310:1310:1310) (1528:1528:1528)) - (PORT d[1] (627:627:627) (710:710:710)) - (PORT d[2] (1532:1532:1532) (1755:1755:1755)) - (PORT d[3] (2695:2695:2695) (3058:3058:3058)) - (PORT d[4] (546:546:546) (625:625:625)) - (PORT d[5] (917:917:917) (1038:1038:1038)) - (PORT d[6] (801:801:801) (916:916:916)) - (PORT d[7] (785:785:785) (884:884:884)) - (PORT d[8] (1419:1419:1419) (1654:1654:1654)) - (PORT d[9] (639:639:639) (718:718:718)) - (PORT d[10] (1157:1157:1157) (1313:1313:1313)) - (PORT d[11] (2168:2168:2168) (2530:2530:2530)) - (PORT d[12] (1410:1410:1410) (1588:1588:1588)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1619:1619:1619) (1765:1765:1765)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1045:1045:1045) (1103:1103:1103)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) (DELAY (ABSOLUTE - (PORT dataa (460:460:460) (529:529:529)) - (PORT datab (683:683:683) (805:805:805)) - (PORT datac (807:807:807) (934:934:934)) - (PORT datad (797:797:797) (914:914:914)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (493:493:493) (565:565:565)) + (PORT datab (629:629:629) (733:733:733)) + (PORT datac (438:438:438) (494:494:494)) + (PORT datad (764:764:764) (901:901:901)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -48745,8 +51208,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (804:804:804) (912:912:912)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (553:553:553) (629:629:629)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) ) ) (TIMINGCHECK @@ -48758,20 +51221,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (971:971:971) (1147:1147:1147)) - (PORT d[1] (1250:1250:1250) (1411:1411:1411)) - (PORT d[2] (1323:1323:1323) (1541:1541:1541)) - (PORT d[3] (969:969:969) (1096:1096:1096)) - (PORT d[4] (1373:1373:1373) (1590:1590:1590)) - (PORT d[5] (1604:1604:1604) (1824:1824:1824)) - (PORT d[6] (1139:1139:1139) (1301:1301:1301)) - (PORT d[7] (976:976:976) (1105:1105:1105)) - (PORT d[8] (1209:1209:1209) (1408:1408:1408)) - (PORT d[9] (1122:1122:1122) (1267:1267:1267)) - (PORT d[10] (1260:1260:1260) (1423:1423:1423)) - (PORT d[11] (2508:2508:2508) (2913:2913:2913)) - (PORT d[12] (1250:1250:1250) (1413:1413:1413)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1854:1854:1854) (2109:2109:2109)) + (PORT d[1] (1741:1741:1741) (1977:1977:1977)) + (PORT d[2] (2303:2303:2303) (2612:2612:2612)) + (PORT d[3] (1116:1116:1116) (1268:1268:1268)) + (PORT d[4] (1709:1709:1709) (2006:2006:2006)) + (PORT d[5] (1984:1984:1984) (2267:2267:2267)) + (PORT d[6] (2334:2334:2334) (2691:2691:2691)) + (PORT d[7] (700:700:700) (797:797:797)) + (PORT d[8] (2263:2263:2263) (2624:2624:2624)) + (PORT d[9] (2462:2462:2462) (2832:2832:2832)) + (PORT d[10] (2245:2245:2245) (2620:2620:2620)) + (PORT d[11] (2100:2100:2100) (2400:2400:2400)) + (PORT d[12] (1578:1578:1578) (1856:1856:1856)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) (TIMINGCHECK @@ -48783,8 +51246,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1074:1074:1074) (1193:1193:1193)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1696:1696:1696) (1860:1860:1860)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) (TIMINGCHECK @@ -48796,8 +51259,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1045:1045:1045) (1097:1097:1097)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1637:1637:1637) (1759:1759:1759)) ) ) ) @@ -48806,7 +51269,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -48816,7 +51279,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -48826,7 +51289,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -48836,7 +51299,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -48846,7 +51309,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) + (PORT clk (1078:1078:1078) (1094:1094:1094)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -48860,7 +51323,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) @@ -48869,7 +51332,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) + (PORT clk (619:619:619) (627:627:627)) ) ) ) @@ -48878,7 +51341,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) + (PORT clk (619:619:619) (627:627:627)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -48888,37 +51351,680 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) + (PORT clk (619:619:619) (627:627:627)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (769:769:769)) - (PORT datab (948:948:948) (1103:1103:1103)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (968:968:968) (1109:1109:1109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (996:996:996) (1161:1161:1161)) + (PORT datab (602:602:602) (692:692:692)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (736:736:736) (829:829:829)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~112) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (1108:1108:1108)) - (PORT datab (355:355:355) (414:414:414)) - (PORT datac (333:333:333) (386:386:386)) - (PORT datad (162:162:162) (192:192:192)) - (IOPATH dataa combout (158:158:158) (173:173:173)) + (PORT d[0] (729:729:729) (832:832:832)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2241:2241:2241) (2547:2547:2547)) + (PORT d[1] (2284:2284:2284) (2597:2597:2597)) + (PORT d[2] (1774:1774:1774) (2014:2014:2014)) + (PORT d[3] (1840:1840:1840) (2143:2143:2143)) + (PORT d[4] (2016:2016:2016) (2343:2343:2343)) + (PORT d[5] (1706:1706:1706) (1948:1948:1948)) + (PORT d[6] (1603:1603:1603) (1867:1867:1867)) + (PORT d[7] (2414:2414:2414) (2734:2734:2734)) + (PORT d[8] (1716:1716:1716) (2001:2001:2001)) + (PORT d[9] (2074:2074:2074) (2394:2394:2394)) + (PORT d[10] (1640:1640:1640) (1916:1916:1916)) + (PORT d[11] (1544:1544:1544) (1766:1766:1766)) + (PORT d[12] (1421:1421:1421) (1658:1658:1658)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1095:1095:1095) (1187:1187:1187)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (3009:3009:3009) (3307:3307:3307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (628:628:628) (708:708:708)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2369:2369:2369) (2676:2676:2676)) + (PORT d[1] (2418:2418:2418) (2787:2787:2787)) + (PORT d[2] (2377:2377:2377) (2682:2682:2682)) + (PORT d[3] (2358:2358:2358) (2668:2668:2668)) + (PORT d[4] (2282:2282:2282) (2587:2587:2587)) + (PORT d[5] (2417:2417:2417) (2825:2825:2825)) + (PORT d[6] (2461:2461:2461) (2841:2841:2841)) + (PORT d[7] (2435:2435:2435) (2807:2807:2807)) + (PORT d[8] (2319:2319:2319) (2635:2635:2635)) + (PORT d[9] (2348:2348:2348) (2667:2667:2667)) + (PORT d[10] (2362:2362:2362) (2660:2660:2660)) + (PORT d[11] (2355:2355:2355) (2683:2683:2683)) + (PORT d[12] (2341:2341:2341) (2664:2664:2664)) + (PORT clk (1054:1054:1054) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1315:1315:1315) (1491:1491:1491)) + (PORT d[1] (1325:1325:1325) (1493:1493:1493)) + (PORT d[2] (1118:1118:1118) (1271:1271:1271)) + (PORT d[3] (661:661:661) (758:758:758)) + (PORT d[4] (1478:1478:1478) (1693:1693:1693)) + (PORT d[5] (1384:1384:1384) (1567:1567:1567)) + (PORT d[6] (2162:2162:2162) (2502:2502:2502)) + (PORT d[7] (789:789:789) (900:900:900)) + (PORT d[8] (553:553:553) (638:638:638)) + (PORT d[9] (555:555:555) (646:646:646)) + (PORT d[10] (1030:1030:1030) (1177:1177:1177)) + (PORT d[11] (1474:1474:1474) (1669:1669:1669)) + (PORT d[12] (857:857:857) (984:984:984)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (974:974:974) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (719:719:719) (826:826:826)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2223:2223:2223) (2529:2529:2529)) + (PORT d[1] (2120:2120:2120) (2411:2411:2411)) + (PORT d[2] (1946:1946:1946) (2210:2210:2210)) + (PORT d[3] (2022:2022:2022) (2351:2351:2351)) + (PORT d[4] (1538:1538:1538) (1802:1802:1802)) + (PORT d[5] (1545:1545:1545) (1767:1767:1767)) + (PORT d[6] (1798:1798:1798) (2080:2080:2080)) + (PORT d[7] (2600:2600:2600) (2943:2943:2943)) + (PORT d[8] (1890:1890:1890) (2201:2201:2201)) + (PORT d[9] (2094:2094:2094) (2415:2415:2415)) + (PORT d[10] (1836:1836:1836) (2138:2138:2138)) + (PORT d[11] (1713:1713:1713) (1954:1954:1954)) + (PORT d[12] (1379:1379:1379) (1605:1605:1605)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1030:1030:1030) (1107:1107:1107)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT d[0] (3312:3312:3312) (3040:3040:3040)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1066:1066:1066)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (774:774:774) (871:871:871)) + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2372:2372:2372) (2680:2680:2680)) + (PORT d[1] (2374:2374:2374) (2698:2698:2698)) + (PORT d[2] (2374:2374:2374) (2674:2674:2674)) + (PORT d[3] (2310:2310:2310) (2622:2622:2622)) + (PORT d[4] (2297:2297:2297) (2611:2611:2611)) + (PORT d[5] (2574:2574:2574) (3025:3025:3025)) + (PORT d[6] (2446:2446:2446) (2816:2816:2816)) + (PORT d[7] (2400:2400:2400) (2767:2767:2767)) + (PORT d[8] (2341:2341:2341) (2658:2658:2658)) + (PORT d[9] (2344:2344:2344) (2671:2671:2671)) + (PORT d[10] (2321:2321:2321) (2622:2622:2622)) + (PORT d[11] (2357:2357:2357) (2700:2700:2700)) + (PORT d[12] (2373:2373:2373) (2703:2703:2703)) + (PORT clk (1048:1048:1048) (1068:1068:1068)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1067:1067:1067)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1662:1662:1662) (1881:1881:1881)) + (PORT d[1] (2489:2489:2489) (2828:2828:2828)) + (PORT d[2] (1635:1635:1635) (1853:1853:1853)) + (PORT d[3] (1447:1447:1447) (1694:1694:1694)) + (PORT d[4] (1779:1779:1779) (2064:2064:2064)) + (PORT d[5] (1723:1723:1723) (1949:1949:1949)) + (PORT d[6] (1791:1791:1791) (2066:2066:2066)) + (PORT d[7] (1963:1963:1963) (2230:2230:2230)) + (PORT d[8] (1381:1381:1381) (1615:1615:1615)) + (PORT d[9] (1734:1734:1734) (2010:2010:2010)) + (PORT d[10] (1355:1355:1355) (1597:1597:1597)) + (PORT d[11] (1310:1310:1310) (1492:1492:1492)) + (PORT d[12] (1486:1486:1486) (1739:1739:1739)) + (PORT clk (1106:1106:1106) (1123:1123:1123)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (PORT d[0] (2257:2257:2257) (2031:2031:2031)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1107:1107:1107) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1104:1104:1104)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (629:629:629) (637:637:637)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (629:629:629) (637:637:637)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (629:629:629) (637:637:637)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (804:804:804)) + (PORT datab (691:691:691) (817:817:817)) + (PORT datac (566:566:566) (643:643:643)) + (PORT datad (881:881:881) (1008:1008:1008)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (939:939:939)) + (PORT datab (653:653:653) (748:748:748)) + (PORT datac (772:772:772) (891:891:891)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1712:1712:1712) (1964:1964:1964)) + (PORT datab (645:645:645) (740:740:740)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (165:165:165)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -48927,30 +52033,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~113) + (INSTANCE D\[5\]\~27) (DELAY (ABSOLUTE - (PORT dataa (1401:1401:1401) (1599:1599:1599)) - (PORT datab (369:369:369) (434:434:434)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (668:668:668) (770:770:770)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (528:528:528) (620:620:620)) + (PORT datab (749:749:749) (857:857:857)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (973:973:973) (1120:1120:1120)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (674:674:674)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (414:414:414)) - (PORT datab (634:634:634) (733:733:733)) - (PORT datac (118:118:118) (141:141:141)) - (PORT datad (857:857:857) (964:964:964)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (794:794:794) (915:915:915)) + (PORT datab (503:503:503) (600:600:600)) + (PORT datac (809:809:809) (948:948:948)) + (PORT datad (123:123:123) (154:154:154)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -48962,9 +52080,9 @@ (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) + (PORT clk (912:912:912) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -48975,13 +52093,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT datab (222:222:222) (275:275:275)) - (PORT datac (117:117:117) (145:145:145)) - (PORT datad (120:120:120) (144:144:144)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (143:143:143) (185:185:185)) + (PORT datac (566:566:566) (674:674:674)) + (PORT datad (131:131:131) (160:160:160)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -48989,16 +52107,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (528:528:528)) - (PORT datab (313:313:313) (365:365:365)) - (PORT datac (277:277:277) (316:316:316)) - (PORT datad (599:599:599) (688:688:688)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (515:515:515) (614:614:614)) + (PORT datab (456:456:456) (551:551:551)) + (PORT datac (806:806:806) (935:935:935)) + (PORT datad (636:636:636) (734:734:734)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -49008,242 +52126,84 @@ (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (1057:1057:1057) (1164:1164:1164)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (972:972:972) (1101:1101:1101)) + (PORT clrn (906:906:906) (893:893:893)) + (PORT ena (434:434:434) (461:461:461)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (INSTANCE z80_\|execute_\|comb\~1) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1407:1407:1407)) - (PORT datab (1130:1130:1130) (1300:1300:1300)) - (PORT datac (787:787:787) (939:939:939)) - (PORT datad (477:477:477) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (1167:1167:1167) (1361:1361:1361)) + (PORT datac (668:668:668) (783:783:783)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) + (INSTANCE z80_\|pla_decode_\|Equal4\~0) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (777:777:777)) - (PORT datab (358:358:358) (422:422:422)) - (PORT datac (803:803:803) (912:912:912)) - (PORT datad (170:170:170) (200:200:200)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT datac (582:582:582) (686:686:686)) - (PORT datad (318:318:318) (371:371:371)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (1056:1056:1056) (1215:1215:1215)) - (PORT datac (104:104:104) (125:125:125)) - (PORT datad (578:578:578) (666:666:666)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (759:759:759)) - (PORT datab (121:121:121) (152:152:152)) - (PORT datac (334:334:334) (392:392:392)) - (PORT datad (325:325:325) (376:376:376)) + (PORT dataa (353:353:353) (415:415:415)) + (PORT datab (399:399:399) (476:476:476)) + (PORT datac (518:518:518) (608:608:608)) + (PORT datad (1051:1051:1051) (1250:1250:1250)) (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (419:419:419)) + (PORT datab (373:373:373) (444:444:444)) + (PORT datac (802:802:802) (923:923:923)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT dataa (705:705:705) (823:823:823)) - (PORT datab (428:428:428) (514:514:514)) - (PORT datac (1064:1064:1064) (1205:1205:1205)) - (PORT datad (454:454:454) (515:515:515)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (409:409:409)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (840:840:840) (965:965:965)) - (PORT datad (352:352:352) (416:416:416)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (1063:1063:1063)) - (PORT datab (493:493:493) (577:577:577)) - (PORT datac (772:772:772) (892:892:892)) - (PORT datad (461:461:461) (523:523:523)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (424:424:424)) - (PORT datab (723:723:723) (847:847:847)) - (PORT datac (113:113:113) (134:134:134)) - (PORT datad (939:939:939) (1070:1070:1070)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (362:362:362) (423:423:423)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (529:529:529)) - (PORT datab (1306:1306:1306) (1527:1527:1527)) - (PORT datac (817:817:817) (959:959:959)) - (PORT datad (588:588:588) (692:692:692)) + (PORT dataa (576:576:576) (682:682:682)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (659:659:659) (780:780:780)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (569:569:569)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (301:301:301) (351:351:351)) - (PORT datac (329:329:329) (389:389:389)) - (PORT datad (770:770:770) (877:877:877)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (375:375:375) (447:447:447)) - (PORT datad (486:486:486) (563:563:563)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (INSTANCE z80_\|sequencer_\|T6) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (900:900:900) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -49255,121 +52215,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (INSTANCE z80_\|execute_\|setM1\~16) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (448:448:448)) - (PORT datac (376:376:376) (448:448:448)) - (PORT datad (485:485:485) (562:562:562)) + (PORT dataa (748:748:748) (858:858:858)) + (PORT datab (337:337:337) (396:396:396)) + (PORT datac (628:628:628) (724:724:724)) + (PORT datad (517:517:517) (601:601:601)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (142:142:142) (194:194:194)) - (PORT datac (377:377:377) (449:449:449)) - (PORT datad (484:484:484) (560:560:560)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (195:195:195)) - (PORT datac (374:374:374) (447:447:447)) - (PORT datad (487:487:487) (564:564:564)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT datac (384:384:384) (472:472:472)) - (PORT datad (1329:1329:1329) (1548:1548:1548)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (INSTANCE z80_\|execute_\|setM1\~17) (DELAY (ABSOLUTE - (PORT dataa (668:668:668) (789:789:789)) - (PORT datab (857:857:857) (994:994:994)) - (PORT datac (886:886:886) (1007:1007:1007)) - (PORT datad (521:521:521) (597:597:597)) + (PORT dataa (542:542:542) (643:643:643)) + (PORT datab (362:362:362) (429:429:429)) + (PORT datac (861:861:861) (993:993:993)) + (PORT datad (590:590:590) (689:689:689)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -49379,15 +52247,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) + (INSTANCE z80_\|execute_\|setM1\~18) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (709:709:709)) - (PORT datab (347:347:347) (410:410:410)) - (PORT datac (643:643:643) (754:754:754)) - (PORT datad (493:493:493) (583:583:583)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (352:352:352) (414:414:414)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (161:161:161) (190:190:190)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49395,14 +52261,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) + (INSTANCE z80_\|execute_\|setM1\~45) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (422:422:422)) - (PORT datab (722:722:722) (845:845:845)) - (PORT datac (336:336:336) (378:378:378)) - (PORT datad (458:458:458) (519:519:519)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (466:466:466) (550:550:550)) + (PORT datab (387:387:387) (465:465:465)) + (PORT datac (1020:1020:1020) (1190:1190:1190)) + (PORT datad (364:364:364) (423:423:423)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (852:852:852)) + (PORT datab (479:479:479) (555:555:555)) + (PORT datac (287:287:287) (328:328:328)) + (PORT datad (177:177:177) (209:209:209)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (399:399:399)) + (PORT datab (494:494:494) (569:569:569)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (755:755:755)) + (PORT datab (701:701:701) (804:804:804)) + (PORT datac (502:502:502) (569:569:569)) + (PORT datad (461:461:461) (521:521:521)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -49411,15 +52325,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) + (INSTANCE z80_\|execute_\|setM1\~53) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (754:754:754)) - (PORT datab (534:534:534) (623:623:623)) - (PORT datac (139:139:139) (179:179:179)) - (PORT datad (628:628:628) (724:724:724)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (301:301:301) (345:345:345)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datac (503:503:503) (585:585:585)) + (PORT datad (559:559:559) (636:636:636)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49427,63 +52341,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) + (INSTANCE z80_\|execute_\|setM1\~54) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (753:753:753)) - (PORT datab (331:331:331) (383:383:383)) - (PORT datac (466:466:466) (531:531:531)) - (PORT datad (458:458:458) (546:546:546)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (597:597:597)) - (PORT datab (811:811:811) (935:935:935)) - (PORT datac (1616:1616:1616) (1860:1860:1860)) - (PORT datad (125:125:125) (165:165:165)) + (PORT dataa (187:187:187) (233:233:233)) + (PORT datab (531:531:531) (631:631:631)) + (PORT datac (512:512:512) (600:600:600)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (976:976:976)) - (PORT datab (587:587:587) (672:672:672)) - (PORT datac (682:682:682) (803:803:803)) - (PORT datad (1183:1183:1183) (1384:1384:1384)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (700:700:700)) - (PORT datab (195:195:195) (235:235:235)) - (PORT datac (477:477:477) (569:569:569)) - (PORT datad (931:931:931) (1060:1060:1060)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49494,10 +52360,58 @@ (INSTANCE z80_\|execute_\|setM1\~24) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (508:508:508) (601:601:601)) - (PORT datac (472:472:472) (531:531:531)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (562:562:562) (657:657:657)) + (PORT datab (139:139:139) (187:187:187)) + (PORT datac (1100:1100:1100) (1288:1288:1288)) + (PORT datad (655:655:655) (775:775:775)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (831:831:831)) + (PORT datab (686:686:686) (812:812:812)) + (PORT datac (795:795:795) (927:927:927)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (699:699:699)) + (PORT datab (506:506:506) (587:587:587)) + (PORT datac (341:341:341) (404:404:404)) + (PORT datad (481:481:481) (556:556:556)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (527:527:527) (614:614:614)) + (PORT datac (592:592:592) (684:684:684)) + (PORT datad (729:729:729) (831:831:831)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -49510,45 +52424,13 @@ (INSTANCE z80_\|execute_\|setM1\~28) (DELAY (ABSOLUTE - (PORT dataa (283:283:283) (332:332:332)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (330:330:330) (386:386:386)) - (PORT datad (487:487:487) (553:553:553)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (723:723:723)) - (PORT datab (1081:1081:1081) (1237:1237:1237)) - (PORT datac (518:518:518) (616:616:616)) - (PORT datad (646:646:646) (755:755:755)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1107:1107:1107)) - (PORT datab (1126:1126:1126) (1264:1264:1264)) - (PORT datac (912:912:912) (1034:1034:1034)) - (PORT datad (882:882:882) (998:998:998)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (785:785:785) (918:918:918)) + (PORT datab (812:812:812) (959:959:959)) + (PORT datac (443:443:443) (509:509:509)) + (PORT datad (688:688:688) (797:797:797)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -49558,11 +52440,27 @@ (INSTANCE z80_\|execute_\|setM1\~29) (DELAY (ABSOLUTE - (PORT dataa (468:468:468) (560:560:560)) - (PORT datab (470:470:470) (568:568:568)) - (PORT datac (496:496:496) (579:579:579)) - (PORT datad (737:737:737) (854:854:854)) + (PORT dataa (778:778:778) (897:897:897)) + (PORT datab (614:614:614) (707:707:707)) + (PORT datac (760:760:760) (912:912:912)) + (PORT datad (612:612:612) (697:697:697)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1295:1295:1295)) + (PORT datab (795:795:795) (901:901:901)) + (PORT datac (347:347:347) (404:404:404)) + (PORT datad (532:532:532) (607:607:607)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -49571,31 +52469,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) + (INSTANCE z80_\|execute_\|setM1\~30) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (714:714:714)) - (PORT datab (479:479:479) (555:555:555)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (724:724:724) (844:844:844)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (586:586:586)) - (PORT datab (846:846:846) (985:985:985)) - (PORT datac (607:607:607) (708:708:708)) - (PORT datad (869:869:869) (1008:1008:1008)) + (PORT dataa (1014:1014:1014) (1159:1159:1159)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (608:608:608) (693:693:693)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49606,27 +52488,249 @@ (INSTANCE z80_\|execute_\|setM1\~34) (DELAY (ABSOLUTE - (PORT dataa (470:470:470) (557:557:557)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (449:449:449) (513:513:513)) - (PORT datad (926:926:926) (1044:1044:1044)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (532:532:532) (629:629:629)) + (PORT datab (833:833:833) (965:965:965)) + (PORT datac (471:471:471) (544:544:544)) + (PORT datad (321:321:321) (376:376:376)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1311:1311:1311)) + (PORT datab (782:782:782) (936:936:936)) + (PORT datac (545:545:545) (639:639:639)) + (PORT datad (655:655:655) (775:775:775)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (583:583:583)) + (PORT datab (670:670:670) (775:775:775)) + (PORT datac (182:182:182) (218:218:218)) + (PORT datad (339:339:339) (395:395:395)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (266:266:266)) + (PORT datab (516:516:516) (607:607:607)) + (PORT datac (529:529:529) (617:617:617)) + (PORT datad (690:690:690) (799:799:799)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (835:835:835)) + (PORT datab (118:118:118) (148:148:148)) + (PORT datac (307:307:307) (357:357:357)) + (PORT datad (667:667:667) (769:769:769)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (162:162:162)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1212:1212:1212)) + (PORT datab (1095:1095:1095) (1271:1271:1271)) + (PORT datac (306:306:306) (347:347:347)) + (PORT datad (655:655:655) (751:751:751)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1208:1208:1208)) + (PORT datab (354:354:354) (418:418:418)) + (PORT datac (512:512:512) (601:601:601)) + (PORT datad (329:329:329) (380:380:380)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (630:630:630) (731:731:731)) + (PORT datac (762:762:762) (915:915:915)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (373:373:373)) + (PORT datab (355:355:355) (416:416:416)) + (PORT datac (332:332:332) (395:395:395)) + (PORT datad (320:320:320) (373:373:373)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (390:390:390)) + (PORT datab (656:656:656) (752:752:752)) + (PORT datac (623:623:623) (717:717:717)) + (PORT datad (628:628:628) (727:727:727)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (772:772:772)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (1141:1141:1141) (1291:1291:1291)) + (PORT datad (338:338:338) (394:394:394)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (794:794:794)) + (PORT datab (735:735:735) (869:869:869)) + (PORT datac (633:633:633) (731:731:731)) + (PORT datad (698:698:698) (826:826:826)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT datab (823:823:823) (963:963:963)) + (PORT datac (493:493:493) (573:573:573)) + (PORT datad (503:503:503) (584:584:584)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (PORT datab (187:187:187) (225:225:225)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~20) (DELAY (ABSOLUTE - (PORT dataa (524:524:524) (609:609:609)) - (PORT datab (140:140:140) (188:188:188)) - (PORT datac (920:920:920) (1048:1048:1048)) - (PORT datad (503:503:503) (586:586:586)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (111:111:111) (146:146:146)) + (PORT datab (444:444:444) (518:518:518)) + (PORT datac (341:341:341) (402:402:402)) + (PORT datad (501:501:501) (582:582:582)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -49638,246 +52742,12 @@ (INSTANCE z80_\|execute_\|setM1\~21) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (752:752:752)) - (PORT datab (731:731:731) (853:853:853)) - (PORT datac (478:478:478) (546:546:546)) - (PORT datad (464:464:464) (546:546:546)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (394:394:394)) - (PORT datab (677:677:677) (787:787:787)) - (PORT datac (836:836:836) (978:978:978)) - (PORT datad (322:322:322) (377:377:377)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (317:317:317) (376:376:376)) - (PORT datad (1081:1081:1081) (1226:1226:1226)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (744:744:744)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (730:730:730) (827:827:827)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (754:754:754)) - (PORT datab (632:632:632) (720:720:720)) - (PORT datac (776:776:776) (893:893:893)) - (PORT datad (749:749:749) (871:871:871)) + (PORT dataa (325:325:325) (389:389:389)) + (PORT datab (459:459:459) (532:532:532)) + (PORT datac (328:328:328) (378:378:378)) + (PORT datad (498:498:498) (580:580:580)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (692:692:692)) - (PORT datab (899:899:899) (1063:1063:1063)) - (PORT datac (750:750:750) (842:842:842)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (575:575:575)) - (PORT datab (639:639:639) (755:755:755)) - (PORT datac (374:374:374) (460:460:460)) - (PORT datad (474:474:474) (551:551:551)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (574:574:574)) - (PORT datac (823:823:823) (969:969:969)) - (PORT datad (449:449:449) (507:507:507)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (145:145:145)) - (PORT datab (652:652:652) (761:761:761)) - (PORT datac (661:661:661) (768:768:768)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (587:587:587)) - (PORT datab (362:362:362) (429:429:429)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (1114:1114:1114) (1266:1266:1266)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (592:592:592)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (847:847:847) (975:975:975)) - (PORT datad (338:338:338) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (702:702:702)) - (PORT datab (631:631:631) (761:761:761)) - (PORT datac (294:294:294) (338:338:338)) - (PORT datad (419:419:419) (484:484:484)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1137:1137:1137)) - (PORT datab (1122:1122:1122) (1281:1281:1281)) - (PORT datac (515:515:515) (606:606:606)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (657:657:657)) - (PORT datab (555:555:555) (638:638:638)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (524:524:524) (612:612:612)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (958:958:958)) - (PORT datab (772:772:772) (879:879:879)) - (PORT datac (867:867:867) (1018:1018:1018)) - (PORT datad (323:323:323) (373:373:373)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49885,80 +52755,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) + (INSTANCE z80_\|execute_\|setM1\~55) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (132:132:132)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (178:178:178) (205:205:205)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (191:191:191)) - (PORT datac (374:374:374) (446:446:446)) - (PORT datad (487:487:487) (565:565:565)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (500:500:500) (600:600:600)) - (PORT datac (759:759:759) (859:859:859)) - (PORT datad (185:185:185) (215:215:215)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (386:386:386)) - (PORT datab (610:610:610) (700:700:700)) - (PORT datac (493:493:493) (595:595:595)) - (PORT datad (290:290:290) (331:331:331)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (1475:1475:1475) (1718:1718:1718)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -49968,9 +52774,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) (DELAY (ABSOLUTE - (PORT datab (390:390:390) (469:469:469)) - (PORT datad (490:490:490) (567:567:567)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (697:697:697) (825:825:825)) + (PORT datad (547:547:547) (644:644:644)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49981,9 +52787,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (900:900:900) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) + (PORT clrn (898:898:898) (885:885:885)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -49994,14 +52800,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) + (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (418:418:418)) - (PORT datab (394:394:394) (474:474:474)) - (PORT datad (484:484:484) (561:561:561)) + (PORT dataa (214:214:214) (274:274:274)) + (PORT datab (992:992:992) (1169:1169:1169)) + (PORT datad (756:756:756) (918:918:918)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50009,12 +52815,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) + (PORT clrn (1108:1108:1108) (1078:1078:1078)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50025,28 +52831,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT datab (537:537:537) (647:647:647)) - (PORT datac (681:681:681) (825:825:825)) - (PORT datad (522:522:522) (627:627:627)) + (PORT datad (894:894:894) (1068:1068:1068)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT asdata (298:298:298) (339:339:339)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (783:783:783)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datad (120:120:120) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT dataa (107:107:107) (141:141:141)) - (PORT datab (819:819:819) (955:955:955)) - (PORT datad (646:646:646) (743:743:743)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (350:350:350) (427:427:427)) + (PORT datad (446:446:446) (512:512:512)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50056,11 +52923,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (655:655:655) (770:770:770)) - (PORT datab (446:446:446) (514:514:514)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (195:195:195) (234:234:234)) + (PORT datab (493:493:493) (575:575:575)) + (PORT datad (495:495:495) (575:575:575)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50070,11 +52937,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) + (PORT clk (912:912:912) (898:898:898)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (368:368:368) (414:414:414)) - (PORT sload (758:758:758) (851:851:851)) - (PORT ena (778:778:778) (852:852:852)) + (PORT asdata (480:480:480) (536:536:536)) + (PORT sload (661:661:661) (747:747:747)) + (PORT ena (938:938:938) (1035:1035:1035)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -50087,13 +52954,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~66) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~2) (DELAY (ABSOLUTE - (PORT datab (488:488:488) (566:566:566)) - (PORT datac (490:490:490) (568:568:568)) - (PORT datad (95:95:95) (114:114:114)) + (PORT dataa (352:352:352) (411:411:411)) + (PORT datab (510:510:510) (611:611:611)) + (PORT datac (398:398:398) (487:487:487)) + (PORT datad (497:497:497) (566:566:566)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (583:583:583)) + (PORT datab (509:509:509) (610:610:610)) + (PORT datac (522:522:522) (593:593:593)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50101,31 +52986,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~67) + (INSTANCE Selector14\~15) (DELAY (ABSOLUTE - (PORT dataa (1552:1552:1552) (1783:1783:1783)) - (PORT datab (808:808:808) (947:947:947)) - (PORT datac (840:840:840) (960:960:960)) - (PORT datad (157:157:157) (183:183:183)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (716:716:716) (836:836:836)) + (PORT datab (565:565:565) (678:678:678)) + (PORT datac (832:832:832) (960:960:960)) + (PORT datad (692:692:692) (789:789:789)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~121) + (INSTANCE Selector14\~16) (DELAY (ABSOLUTE - (PORT dataa (1464:1464:1464) (1696:1696:1696)) - (PORT datab (1118:1118:1118) (1320:1320:1320)) - (PORT datac (1569:1569:1569) (1833:1833:1833)) - (PORT datad (1388:1388:1388) (1582:1582:1582)) + (PORT dataa (687:687:687) (793:793:793)) + (PORT datab (566:566:566) (678:678:678)) + (PORT datac (701:701:701) (796:796:796)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (474:474:474)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (338:338:338) (389:389:389)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (693:693:693)) + (PORT datab (985:985:985) (1136:1136:1136)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (643:643:643)) + (PORT datab (647:647:647) (775:775:775)) + (PORT datac (428:428:428) (485:485:485)) + (PORT datad (450:450:450) (509:509:509)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50133,13 +53066,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~68) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~5) (DELAY (ABSOLUTE - (PORT datab (368:368:368) (435:435:435)) - (PORT datac (606:606:606) (688:688:688)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (627:627:627) (721:721:721)) + (PORT datab (529:529:529) (631:631:631)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (766:766:766) (874:874:874)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~12) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (680:680:680)) + (PORT datab (658:658:658) (759:759:759)) + (PORT datac (616:616:616) (692:692:692)) + (PORT datad (785:785:785) (891:891:891)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50147,14 +53098,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~69) + (INSTANCE Selector12\~13) (DELAY (ABSOLUTE - (PORT dataa (1553:1553:1553) (1785:1785:1785)) - (PORT datab (529:529:529) (624:624:624)) - (PORT datac (839:839:839) (959:959:959)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (572:572:572) (684:684:684)) + (PORT datab (786:786:786) (902:902:902)) + (PORT datac (948:948:948) (1087:1087:1087)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (750:750:750)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (178:178:178) (205:205:205)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (188:188:188) (193:193:193)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50163,12 +53130,94 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~70) + (INSTANCE D\[1\]\~18) (DELAY (ABSOLUTE - (PORT datab (665:665:665) (766:766:766)) - (PORT datac (456:456:456) (528:528:528)) - (PORT datad (167:167:167) (198:198:198)) + (PORT dataa (653:653:653) (759:759:759)) + (PORT datab (628:628:628) (763:763:763)) + (PORT datac (827:827:827) (959:959:959)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (168:168:168) (202:202:202)) + (PORT datad (533:533:533) (620:620:620)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (564:564:564)) + (PORT datab (376:376:376) (464:464:464)) + (PORT datac (1035:1035:1035) (1179:1179:1179)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (476:476:476)) + (PORT datab (233:233:233) (295:295:295)) + (PORT datac (507:507:507) (577:577:577)) + (PORT datad (776:776:776) (886:886:886)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1099:1099:1099)) + (PORT datab (232:232:232) (295:295:295)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (825:825:825) (953:953:953)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (774:774:774)) + (PORT datab (681:681:681) (788:788:788)) + (PORT datac (346:346:346) (413:413:413)) + (PORT datad (957:957:957) (1091:1091:1091)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50177,70 +53226,203 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~71) + (INSTANCE Selector8\~3) (DELAY (ABSOLUTE - (PORT dataa (1238:1238:1238) (1415:1415:1415)) - (PORT datab (330:330:330) (383:383:383)) - (PORT datac (947:947:947) (1099:1099:1099)) + (PORT dataa (817:817:817) (959:959:959)) + (PORT datab (243:243:243) (304:304:304)) + (PORT datac (989:989:989) (1151:1151:1151)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (906:906:906)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (763:763:763)) + (PORT datab (762:762:762) (875:875:875)) + (PORT datac (626:626:626) (720:720:720)) (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~83) + (INSTANCE D\[4\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1551:1551:1551) (1782:1782:1782)) - (PORT datac (507:507:507) (601:601:601)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (233:233:233)) - (PORT datab (514:514:514) (594:594:594)) - (PORT datac (171:171:171) (197:197:197)) - (PORT datad (170:170:170) (200:200:200)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (600:600:600)) - (PORT datab (497:497:497) (575:575:575)) - (PORT datac (95:95:95) (119:119:119)) + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (97:97:97) (121:121:121)) + (PORT datad (1140:1140:1140) (1295:1295:1295)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~96) + (INSTANCE D\[4\]\~24) (DELAY (ABSOLUTE - (PORT dataa (715:715:715) (850:850:850)) - (PORT datab (227:227:227) (273:273:273)) - (PORT datac (1237:1237:1237) (1422:1422:1422)) + (PORT dataa (805:805:805) (930:930:930)) + (PORT datab (610:610:610) (721:721:721)) + (PORT datac (669:669:669) (779:779:779)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (597:597:597)) + (PORT datab (384:384:384) (470:470:470)) + (PORT datad (502:502:502) (570:570:570)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (414:414:414)) + (PORT datab (380:380:380) (466:466:466)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (500:500:500) (567:567:567)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1148:1148:1148)) + (PORT datab (153:153:153) (206:206:206)) + (PORT datac (844:844:844) (949:949:949)) + (PORT datad (850:850:850) (982:982:982)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (416:416:416)) + (PORT datab (1414:1414:1414) (1622:1622:1622)) + (PORT datac (673:673:673) (767:767:767)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (151:151:151) (204:204:204)) + (PORT datac (739:739:739) (853:853:853)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (952:952:952)) + (PORT datab (381:381:381) (465:465:465)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (139:139:139)) + (PORT datab (737:737:737) (840:840:840)) + (PORT datac (499:499:499) (589:589:589)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (916:916:916)) + (PORT datab (645:645:645) (747:747:747)) + (PORT datac (511:511:511) (595:595:595)) (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -50249,125 +53431,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1155:1155:1155)) - (PORT datab (1740:1740:1740) (2035:2035:2035)) - (PORT datac (331:331:331) (383:383:383)) - (PORT datad (164:164:164) (194:194:194)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (795:795:795)) - (PORT datab (360:360:360) (420:420:420)) - (PORT datac (1380:1380:1380) (1577:1577:1577)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~105) - (DELAY - (ABSOLUTE - (PORT datab (471:471:471) (550:550:550)) - (PORT datac (186:186:186) (221:221:221)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (806:806:806)) - (PORT datab (329:329:329) (382:382:382)) - (PORT datac (1226:1226:1226) (1395:1395:1395)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (1586:1586:1586) (1861:1861:1861)) - (PORT datab (1112:1112:1112) (1291:1291:1291)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (337:337:337) (394:394:394)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (794:794:794)) - (PORT datab (1407:1407:1407) (1607:1607:1607)) - (PORT datac (179:179:179) (208:208:208)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (PORT datac (463:463:463) (526:526:526)) - (PORT datad (124:124:124) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (389:389:389) (469:469:469)) - (PORT datac (352:352:352) (426:426:426)) - (PORT datad (318:318:318) (387:387:387)) + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (149:149:149) (199:199:199)) + (PORT datac (675:675:675) (800:800:800)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -50376,10 +53450,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (900:900:900) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50394,7 +53468,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (367:367:367) (438:438:438)) + (PORT datad (778:778:778) (893:893:893)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50404,10 +53478,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) + (PORT clk (910:910:910) (897:897:897)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) + (PORT clrn (899:899:899) (886:886:886)) + (PORT ena (851:851:851) (943:943:943)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50422,10 +53496,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT asdata (301:301:301) (343:343:343)) - (PORT clrn (917:917:917) (898:898:898)) - (PORT ena (667:667:667) (723:723:723)) + (PORT clk (910:910:910) (897:897:897)) + (PORT asdata (299:299:299) (339:339:339)) + (PORT clrn (899:899:899) (886:886:886)) + (PORT ena (851:851:851) (943:943:943)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50440,9 +53514,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (602:602:602)) - (PORT datab (138:138:138) (188:188:188)) - (PORT datad (122:122:122) (160:160:160)) + (PORT dataa (135:135:135) (187:187:187)) + (PORT datab (337:337:337) (406:406:406)) + (PORT datad (122:122:122) (161:161:161)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -50455,10 +53529,10 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (PORT datab (142:142:142) (195:195:195)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (94:94:94) (114:114:114)) + (PORT dataa (308:308:308) (360:360:360)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (603:603:603) (703:703:703)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -50489,9 +53563,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT clk (1141:1141:1141) (1102:1102:1102)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) + (PORT clrn (897:897:897) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50505,7 +53579,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (273:273:273)) + (PORT dataa (211:211:211) (271:271:271)) (PORT datab (136:136:136) (186:186:186)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) @@ -50520,9 +53594,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT clk (1141:1141:1141) (1102:1102:1102)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) + (PORT clrn (897:897:897) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50550,9 +53624,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT clk (1141:1141:1141) (1102:1102:1102)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) + (PORT clrn (897:897:897) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50580,9 +53654,66 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT clk (1141:1141:1141) (1102:1102:1102)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) + (PORT clrn (897:897:897) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1141:1141:1141) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1141:1141:1141) (1102:1102:1102)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50597,8 +53728,8 @@ (DELAY (ABSOLUTE (PORT dataa (136:136:136) (189:189:189)) - (PORT datab (143:143:143) (192:192:192)) - (PORT datac (121:121:121) (163:163:163)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (128:128:128) (169:169:169)) (PORT datad (122:122:122) (161:161:161)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -50607,104 +53738,29 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (121:121:121) (160:160:160)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1141:1141:1141) (1103:1103:1103)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (122:122:122) (165:165:165)) - (PORT datad (122:122:122) (160:160:160)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT ena (546:546:546) (522:522:522)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1109:1109:1109) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (PORT ena (851:851:851) (793:793:793)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (796:796:796) (743:743:743)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50719,7 +53775,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (217:217:217) (270:270:270)) + (PORT datad (139:139:139) (180:180:180)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50730,10 +53786,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (PORT ena (851:851:851) (793:793:793)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (896:896:896) (830:830:830)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50748,9 +53804,9 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (235:235:235) (295:295:295)) - (PORT datad (206:206:206) (261:261:261)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datad (152:152:152) (202:202:202)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50761,10 +53817,28 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (PORT ena (463:463:463) (442:442:442)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (896:896:896) (830:830:830)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1109:1109:1109) (1139:1139:1139)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (796:796:796) (743:743:743)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50779,9 +53853,9 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (306:306:306)) - (PORT datac (147:147:147) (196:196:196)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (343:343:343) (417:417:417)) + (PORT datac (321:321:321) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) ) ) @@ -50791,366 +53865,23 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (308:308:308)) - (PORT datac (298:298:298) (359:359:359)) - (PORT datad (467:467:467) (552:552:552)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~4) - (DELAY - (ABSOLUTE - (PORT datad (377:377:377) (457:457:457)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (276:276:276)) - (PORT datab (341:341:341) (413:413:413)) - (PORT datad (380:380:380) (463:463:463)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT datab (248:248:248) (309:309:309)) + (PORT datad (392:392:392) (479:479:479)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (308:308:308)) - (PORT datac (314:314:314) (371:371:371)) - (PORT datad (156:156:156) (200:200:200)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (315:315:315) (382:382:382)) - (PORT datac (342:342:342) (413:413:413)) - (PORT datad (455:455:455) (539:539:539)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (414:414:414)) - (PORT datab (336:336:336) (387:387:387)) - (PORT datac (338:338:338) (415:415:415)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (906:906:906)) - (PORT ena (637:637:637) (687:687:687)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (480:480:480)) - (PORT datad (205:205:205) (257:257:257)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (906:906:906)) - (PORT ena (654:654:654) (717:717:717)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) - (DELAY - (ABSOLUTE - (PORT dataa (139:139:139) (192:192:192)) - (PORT datab (144:144:144) (197:197:197)) - (PORT datad (198:198:198) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (239:239:239) (303:303:303)) - (PORT datac (148:148:148) (197:197:197)) - (PORT datad (347:347:347) (421:421:421)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (309:309:309)) - (PORT datac (316:316:316) (373:373:373)) - (PORT datad (158:158:158) (201:201:201)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (304:304:304)) - (PORT datac (148:148:148) (197:197:197)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (356:356:356) (384:384:384)) - (PORT clrn (898:898:898) (902:902:902)) - (PORT sload (460:460:460) (529:529:529)) - (PORT ena (851:851:851) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (482:482:482)) - (PORT datab (140:140:140) (194:194:194)) - (PORT datad (202:202:202) (254:254:254)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (906:906:906)) - (PORT ena (654:654:654) (717:717:717)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (211:211:211) (273:273:273)) - (PORT datac (473:473:473) (554:554:554)) - (PORT datad (131:131:131) (174:174:174)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (202:202:202)) - (PORT datab (171:171:171) (225:225:225)) - (PORT datac (297:297:297) (357:357:357)) - (PORT datad (330:330:330) (393:393:393)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (415:415:415)) - (PORT datab (351:351:351) (435:435:435)) - (PORT datac (341:341:341) (412:412:412)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (392:392:392)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (456:456:456) (540:540:540)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1121:1121:1121) (1153:1153:1153)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datac (353:353:353) (439:439:439)) - (PORT datad (230:230:230) (282:282:282)) + (PORT datab (483:483:483) (570:570:570)) + (PORT datac (310:310:310) (365:365:365)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -51168,10 +53899,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (277:277:277)) - (PORT datab (404:404:404) (492:492:492)) - (PORT datac (131:131:131) (173:173:173)) - (PORT datad (274:274:274) (291:291:291)) + (PORT dataa (226:226:226) (280:280:280)) + (PORT datab (249:249:249) (311:311:311)) + (PORT datac (142:142:142) (191:191:191)) + (PORT datad (366:366:366) (390:390:390)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -51184,13 +53915,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (176:176:176) (214:214:214)) - (PORT datab (344:344:344) (402:402:402)) - (PORT datac (321:321:321) (386:386:386)) + (PORT dataa (412:412:412) (504:504:504)) + (PORT datab (351:351:351) (408:408:408)) + (PORT datac (91:91:91) (113:113:113)) (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH dataa combout (172:172:172) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51200,11 +53931,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (423:423:423)) - (PORT datab (325:325:325) (375:375:375)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (225:225:225) (284:284:284)) + (PORT datac (430:430:430) (500:500:500)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51215,28 +53946,386 @@ (DELAY (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) - (PORT asdata (353:353:353) (387:387:387)) - (PORT clrn (900:900:900) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (911:911:911)) (PORT ena (421:421:421) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (505:505:505)) + (PORT datab (250:250:250) (312:312:312)) + (PORT datad (155:155:155) (197:197:197)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (482:482:482) (569:569:569)) + (PORT datac (142:142:142) (190:190:190)) + (PORT datad (154:154:154) (195:195:195)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (411:411:411)) + (PORT datac (223:223:223) (278:278:278)) + (PORT datad (268:268:268) (306:306:306)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT datad (231:231:231) (282:282:282)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (418:418:418)) + (PORT datab (151:151:151) (203:203:203)) + (PORT datac (318:318:318) (379:379:379)) + (PORT datad (149:149:149) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (237:237:237) (298:298:298)) + (PORT datac (144:144:144) (192:192:192)) + (PORT datad (153:153:153) (194:194:194)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (152:152:152)) + (PORT datab (322:322:322) (375:375:375)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (388:388:388) (474:474:474)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (234:234:234)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (329:329:329) (383:383:383)) + (PORT datad (426:426:426) (489:489:489)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (473:473:473) (497:497:497)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datad (139:139:139) (180:180:180)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (419:419:419)) + (PORT datac (321:321:321) (383:383:383)) + (PORT datad (277:277:277) (318:318:318)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (226:226:226)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (375:375:375) (410:410:410)) + (PORT clrn (908:908:908) (914:914:914)) + (PORT sload (457:457:457) (522:522:522)) + (PORT ena (813:813:813) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (308:308:308)) + (PORT datad (135:135:135) (176:176:176)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (473:473:473) (497:497:497)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (286:286:286)) + (PORT datab (242:242:242) (304:304:304)) + (PORT datad (138:138:138) (179:179:179)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (473:473:473) (497:497:497)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (PORT datab (151:151:151) (203:203:203)) + (PORT datac (203:203:203) (250:250:250)) + (PORT datad (221:221:221) (271:271:271)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (198:198:198)) + (PORT datab (158:158:158) (212:212:212)) + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (140:140:140) (182:182:182)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (258:258:258)) + (PORT datab (452:452:452) (528:528:528)) + (PORT datac (185:185:185) (217:217:217)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (448:448:448) (520:520:520)) + (PORT datad (147:147:147) (191:191:191)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (908:908:908) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT datab (247:247:247) (307:307:307)) - (PORT datac (312:312:312) (368:368:368)) - (PORT datad (154:154:154) (196:196:196)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (484:484:484) (572:572:572)) + (PORT datac (145:145:145) (193:193:193)) + (PORT datad (153:153:153) (194:194:194)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51246,9 +54335,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (416:416:416)) - (PORT datab (332:332:332) (383:383:383)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (213:213:213) (258:258:258)) + (PORT datab (449:449:449) (521:521:521)) + (PORT datad (263:263:263) (301:301:301)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -51261,9 +54350,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1121:1121:1121) (1153:1153:1153)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) + (PORT clrn (908:908:908) (914:914:914)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51277,12 +54366,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (148:148:148) (201:201:201)) - (PORT datab (474:474:474) (568:568:568)) - (PORT datac (424:424:424) (499:499:499)) - (PORT datad (467:467:467) (552:552:552)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (191:191:191) (181:181:181)) + (PORT dataa (344:344:344) (418:418:418)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (321:321:321) (383:383:383)) + (PORT datad (154:154:154) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51293,7 +54382,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (160:160:160) (215:215:215)) + (PORT datab (174:174:174) (238:238:238)) (IOPATH datab combout (192:192:192) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51302,14 +54391,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (312:312:312) (376:376:376)) - (PORT datab (490:490:490) (585:585:585)) - (PORT datac (324:324:324) (388:388:388)) - (PORT datad (379:379:379) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (327:327:327) (396:396:396)) + (PORT datab (236:236:236) (289:289:289)) + (PORT datac (388:388:388) (414:414:414)) + (PORT datad (198:198:198) (242:242:242)) + (IOPATH dataa combout (188:188:188) (184:184:184)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51321,12 +54410,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (320:320:320) (376:376:376)) - (PORT datab (239:239:239) (292:292:292)) - (PORT datac (419:419:419) (490:490:490)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (355:355:355) (427:427:427)) + (PORT datab (430:430:430) (493:493:493)) + (PORT datac (456:456:456) (537:537:537)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51337,11 +54426,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) + (PORT clk (1096:1096:1096) (1118:1118:1118)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1454:1454:1454) (1619:1619:1619)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT sload (865:865:865) (791:791:791)) + (PORT asdata (1206:1206:1206) (1333:1333:1333)) + (PORT clrn (906:906:906) (911:911:911)) + (PORT sload (691:691:691) (643:643:643)) (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -51359,9 +54448,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (160:160:160) (217:217:217)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (161:161:161) (223:223:223)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -51373,11 +54462,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) + (PORT clk (1096:1096:1096) (1118:1118:1118)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1455:1455:1455) (1620:1620:1620)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT sload (865:865:865) (791:791:791)) + (PORT asdata (1206:1206:1206) (1333:1333:1333)) + (PORT clrn (906:906:906) (911:911:911)) + (PORT sload (691:691:691) (643:643:643)) (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -51395,9 +54484,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (166:166:166) (229:229:229)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (164:164:164) (225:225:225)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -51409,10 +54498,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) + (PORT clk (1096:1096:1096) (1118:1118:1118)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT sload (865:865:865) (791:791:791)) + (PORT clrn (906:906:906) (911:911:911)) + (PORT sload (691:691:691) (643:643:643)) (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -51430,9 +54519,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (163:163:163) (217:217:217)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (157:157:157) (212:212:212)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -51444,11 +54533,43 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) + (PORT clk (1096:1096:1096) (1118:1118:1118)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1455:1455:1455) (1620:1620:1620)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT sload (865:865:865) (791:791:791)) + (PORT asdata (1206:1206:1206) (1334:1334:1334)) + (PORT clrn (906:906:906) (911:911:911)) + (PORT sload (691:691:691) (643:643:643)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datad (149:149:149) (193:193:193)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1118:1118:1118)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (911:911:911)) + (PORT sload (691:691:691) (643:643:643)) (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -51466,58 +54587,26 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (295:295:295)) - (PORT datab (161:161:161) (221:221:221)) - (PORT datac (152:152:152) (212:212:212)) - (PORT datad (152:152:152) (197:197:197)) + (PORT dataa (167:167:167) (231:231:231)) + (PORT datab (169:169:169) (231:231:231)) + (PORT datac (166:166:166) (225:225:225)) + (PORT datad (146:146:146) (191:191:191)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (165:165:165) (226:226:226)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1131:1131:1131)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT sload (865:865:865) (791:791:791)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (210:210:210) (259:259:259)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datac (321:321:321) (384:384:384)) + (PORT datad (262:262:262) (298:298:298)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51528,11 +54617,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (273:273:273)) - (PORT datab (252:252:252) (312:312:312)) - (PORT datad (463:463:463) (547:547:547)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (151:151:151) (204:204:204)) + (PORT datac (125:125:125) (171:171:171)) + (PORT datad (150:150:150) (195:195:195)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51542,13 +54631,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (330:330:330)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datac (141:141:141) (187:187:187)) - (PORT datad (347:347:347) (421:421:421)) + (PORT dataa (119:119:119) (151:151:151)) + (PORT datab (169:169:169) (226:226:226)) + (PORT datac (126:126:126) (172:172:172)) + (PORT datad (279:279:279) (320:320:320)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51558,10 +54647,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (229:229:229) (292:292:292)) - (PORT datac (140:140:140) (189:189:189)) - (PORT datad (120:120:120) (145:145:145)) + (PORT dataa (104:104:104) (137:137:137)) + (PORT datab (454:454:454) (530:530:530)) + (PORT datac (193:193:193) (229:229:229)) + (PORT datad (143:143:143) (187:187:187)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -51574,11 +54663,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (488:488:488) (569:569:569)) - (PORT datab (332:332:332) (390:390:390)) + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (454:454:454) (526:526:526)) (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51589,9 +54678,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) + (PORT clrn (908:908:908) (914:914:914)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51605,11 +54694,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (172:172:172)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datad (214:214:214) (267:267:267)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (PORT dataa (141:141:141) (196:196:196)) + (PORT datab (455:455:455) (532:532:532)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51620,10 +54709,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (898:898:898) (902:902:902)) - (PORT ena (851:851:851) (793:793:793)) + (PORT clrn (908:908:908) (914:914:914)) + (PORT ena (813:813:813) (759:759:759)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51638,12 +54727,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (371:371:371) (458:458:458)) - (PORT datac (323:323:323) (388:388:388)) - (PORT datad (380:380:380) (463:463:463)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (166:166:166) (226:226:226)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datac (393:393:393) (481:481:481)) + (PORT datad (158:158:158) (208:208:208)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51654,10 +54743,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (138:138:138)) - (PORT datac (320:320:320) (384:384:384)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (188:188:188) (193:193:193)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (389:389:389) (475:475:475)) + (PORT datad (322:322:322) (370:370:370)) + (IOPATH datab combout (188:188:188) (193:193:193)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51669,9 +54758,9 @@ (DELAY (ABSOLUTE (PORT clk (868:868:868) (887:887:887)) - (PORT d (556:556:556) (509:509:509)) + (PORT d (576:576:576) (521:521:521)) (PORT aload (1008:1008:1008) (1051:1051:1051)) - (PORT ena (382:382:382) (363:363:363)) + (PORT ena (472:472:472) (443:443:443)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) (IOPATH (posedge aload) q (286:286:286) (280:280:280)) ) @@ -51688,368 +54777,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1109:1109:1109) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) - (PORT ena (546:546:546) (522:522:522)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (294:294:294)) - (PORT datab (158:158:158) (217:217:217)) - (PORT datac (147:147:147) (205:205:205)) - (PORT datad (147:147:147) (191:191:191)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (318:318:318) (383:383:383)) - (PORT datad (461:461:461) (545:545:545)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (296:296:296)) - (PORT datab (162:162:162) (222:222:222)) - (PORT datac (156:156:156) (211:211:211)) - (PORT datad (153:153:153) (198:198:198)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (169:169:169) (235:235:235)) - (PORT datab (302:302:302) (344:344:344)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (147:147:147) (192:192:192)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (170:170:170) (237:237:237)) - (PORT datab (161:161:161) (217:217:217)) - (PORT datac (155:155:155) (210:210:210)) - (PORT datad (152:152:152) (198:198:198)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (340:340:340)) - (PORT datab (160:160:160) (218:218:218)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (146:146:146) (191:191:191)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (335:335:335)) - (PORT datac (368:368:368) (444:444:444)) - (PORT datad (359:359:359) (430:430:430)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT datab (152:152:152) (205:205:205)) - (PORT datac (147:147:147) (197:197:197)) - (PORT datad (221:221:221) (280:280:280)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (190:190:190) (232:232:232)) - (PORT datac (147:147:147) (197:197:197)) - (PORT datad (116:116:116) (139:139:139)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (566:566:566)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (218:218:218) (271:271:271)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT sclr (643:643:643) (746:746:746)) - (PORT ena (485:485:485) (516:516:516)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) - (DELAY - (ABSOLUTE - (PORT datab (332:332:332) (398:398:398)) - (PORT datac (244:244:244) (309:309:309)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (294:294:294)) - (PORT datab (189:189:189) (230:230:230)) - (PORT datac (146:146:146) (196:196:196)) - (PORT datad (222:222:222) (282:282:282)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (170:170:170)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datac (142:142:142) (191:191:191)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (567:567:567)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (216:216:216) (269:269:269)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT ena (496:496:496) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (389:389:389)) - (PORT datac (243:243:243) (308:308:308)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT ena (496:496:496) (536:536:536)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (171:171:171) (238:238:238)) - (PORT datab (162:162:162) (222:222:222)) - (PORT datac (155:155:155) (211:211:211)) - (PORT datad (153:153:153) (198:198:198)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (239:239:239)) - (PORT datac (157:157:157) (212:212:212)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (378:378:378)) - (PORT datab (179:179:179) (218:218:218)) - (PORT datac (368:368:368) (444:444:444)) - (PORT datad (360:360:360) (431:431:431)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (184:184:184)) - (PORT datab (429:429:429) (509:509:509)) - (PORT datac (247:247:247) (313:313:313)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT ena (496:496:496) (536:536:536)) + (PORT clrn (907:907:907) (911:911:911)) + (PORT ena (796:796:796) (743:743:743)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52064,10 +54795,22 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (170:170:170) (237:237:237)) - (PORT datab (161:161:161) (221:221:221)) - (PORT datac (154:154:154) (210:210:210)) - (PORT datad (147:147:147) (193:193:193)) + (PORT datac (147:147:147) (205:205:205)) + (PORT datad (149:149:149) (193:193:193)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (221:221:221)) + (PORT datab (162:162:162) (223:223:223)) + (PORT datac (155:155:155) (212:212:212)) + (PORT datad (149:149:149) (192:192:192)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -52075,16 +54818,48 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (391:391:391)) + (PORT datab (388:388:388) (475:475:475)) + (PORT datac (372:372:372) (450:450:450)) + (PORT datad (254:254:254) (286:286:286)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (453:453:453)) - (PORT datab (343:343:343) (405:405:405)) - (PORT datac (367:367:367) (444:444:444)) - (PORT datad (171:171:171) (200:200:200)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (164:164:164) (228:228:228)) + (PORT datab (224:224:224) (281:281:281)) + (PORT datac (149:149:149) (206:206:206)) + (PORT datad (149:149:149) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (389:389:389)) + (PORT datab (387:387:387) (474:474:474)) + (PORT datac (371:371:371) (448:448:448)) + (PORT datad (317:317:317) (370:370:370)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52093,29 +54868,183 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (431:431:431) (510:510:510)) - (PORT datac (245:245:245) (310:310:310)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (429:429:429) (524:524:524)) + (PORT datab (386:386:386) (473:473:473)) + (PORT datac (370:370:370) (447:447:447)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (168:168:168) (230:230:230)) + (PORT datab (410:410:410) (501:501:501)) + (PORT datac (390:390:390) (478:478:478)) + (PORT datad (182:182:182) (217:217:217)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (176:176:176) (237:237:237)) + (PORT datac (291:291:291) (346:346:346)) + (PORT datad (428:428:428) (491:491:491)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT ena (496:496:496) (536:536:536)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT sclr (612:612:612) (721:721:721)) + (PORT ena (595:595:595) (633:633:633)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (216:216:216)) + (PORT datab (167:167:167) (230:230:230)) + (PORT datac (164:164:164) (223:223:223)) + (PORT datad (150:150:150) (194:194:194)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~6) + (DELAY + (ABSOLUTE + (PORT datab (159:159:159) (213:213:213)) + (PORT datad (151:151:151) (199:199:199)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (436:436:436) (509:509:509)) + (PORT datac (164:164:164) (223:223:223)) + (PORT datad (150:150:150) (203:203:203)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (183:183:183)) + (PORT datac (404:404:404) (498:498:498)) + (PORT datad (319:319:319) (373:373:373)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (169:169:169) (230:230:230)) + (PORT datab (410:410:410) (501:501:501)) + (PORT datac (300:300:300) (364:364:364)) + (PORT datad (182:182:182) (217:217:217)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (414:414:414) (503:503:503)) + (PORT datac (328:328:328) (381:381:381)) + (PORT datad (388:388:388) (473:473:473)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (190:190:190) (228:228:228)) + (PORT datac (430:430:430) (501:501:501)) + (PORT datad (211:211:211) (260:260:260)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (640:640:640) (702:702:702)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52127,14 +55056,162 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (398:398:398)) - (PORT datab (329:329:329) (395:395:395)) - (PORT datad (188:188:188) (231:231:231)) + (PORT dataa (168:168:168) (232:232:232)) + (PORT datab (225:225:225) (282:282:282)) + (PORT datac (167:167:167) (226:226:226)) + (PORT datad (152:152:152) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (168:168:168) (231:231:231)) + (PORT datac (165:165:165) (224:224:224)) + (PORT datad (431:431:431) (493:493:493)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT datab (132:132:132) (180:180:180)) + (PORT datac (407:407:407) (501:501:501)) + (PORT datad (404:404:404) (461:461:461)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (640:640:640) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (523:523:523)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (381:381:381) (457:457:457)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (640:640:640) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (525:525:525)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (384:384:384) (459:459:459)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (640:640:640) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (231:231:231)) + (PORT datab (169:169:169) (231:231:231)) + (PORT datac (166:166:166) (225:225:225)) + (PORT datad (146:146:146) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (267:267:267)) + (PORT datab (403:403:403) (491:491:491)) + (PORT datad (414:414:414) (472:472:472)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52144,11 +55221,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT sload (630:630:630) (715:715:715)) - (PORT ena (609:609:609) (659:659:659)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT sload (754:754:754) (851:851:851)) + (PORT ena (653:653:653) (715:715:715)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52162,14 +55239,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (337:337:337) (397:397:397)) - (PORT datac (241:241:241) (306:306:306)) - (PORT datad (198:198:198) (249:249:249)) + (PORT datab (214:214:214) (270:270:270)) + (PORT datac (406:406:406) (499:499:499)) + (PORT datad (512:512:512) (579:579:579)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52179,11 +55256,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT sclr (643:643:643) (746:746:746)) - (PORT ena (496:496:496) (536:536:536)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT sclr (612:612:612) (721:721:721)) + (PORT ena (640:640:640) (702:702:702)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52196,11 +55273,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~7) (DELAY (ABSOLUTE - (PORT datac (249:249:249) (315:315:315)) - (PORT datad (120:120:120) (158:158:158)) + (PORT datac (407:407:407) (501:501:501)) + (PORT datad (118:118:118) (154:154:154)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52211,11 +55288,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (897:897:897) (902:902:902)) - (PORT sclr (643:643:643) (746:746:746)) - (PORT ena (485:485:485) (516:516:516)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT sclr (612:612:612) (721:721:721)) + (PORT ena (595:595:595) (633:633:633)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52231,10 +55308,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (430:430:430)) - (PORT datab (470:470:470) (564:564:564)) - (PORT datac (215:215:215) (261:261:261)) - (PORT datad (465:465:465) (550:550:550)) + (PORT dataa (362:362:362) (442:442:442)) + (PORT datab (168:168:168) (227:227:227)) + (PORT datac (359:359:359) (432:432:432)) + (PORT datad (388:388:388) (472:472:472)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52247,10 +55324,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (176:176:176) (217:217:217)) - (PORT datab (402:402:402) (490:490:490)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (273:273:273) (291:291:291)) + (PORT dataa (105:105:105) (138:138:138)) + (PORT datab (174:174:174) (235:235:235)) + (PORT datac (319:319:319) (375:375:375)) + (PORT datad (272:272:272) (289:289:289)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52263,13 +55340,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (405:405:405) (493:493:493)) - (PORT datac (352:352:352) (438:438:438)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (168:168:168) (229:229:229)) + (PORT datab (174:174:174) (234:234:234)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52279,13 +55356,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (404:404:404) (493:493:493)) - (PORT datac (353:353:353) (438:438:438)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (164:164:164) (225:225:225)) + (PORT datab (171:171:171) (231:231:231)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52295,12 +55372,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (439:439:439) (528:528:528)) - (PORT datab (123:123:123) (154:154:154)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (339:339:339) (401:401:401)) + (PORT datab (414:414:414) (503:503:503)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (91:91:91) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52313,8 +55390,8 @@ (ABSOLUTE (PORT clk (871:871:871) (889:889:889)) (PORT d (381:381:381) (356:356:356)) - (PORT aload (1011:1011:1011) (1052:1052:1052)) - (PORT ena (518:518:518) (488:488:488)) + (PORT aload (1017:1017:1017) (1059:1059:1059)) + (PORT ena (742:742:742) (687:687:687)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) (IOPATH (posedge aload) q (286:286:286) (280:280:280)) ) @@ -52346,12 +55423,232 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux38\~0) + (INSTANCE sdram_\|Mux4\~3) (DELAY (ABSOLUTE - (PORT dataa (862:862:862) (1012:1012:1012)) - (PORT datab (726:726:726) (840:840:840)) - (PORT datad (95:95:95) (115:115:115)) + (PORT dataa (397:397:397) (486:486:486)) + (PORT datac (371:371:371) (445:445:445)) + (PORT datad (379:379:379) (451:451:451)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (716:716:716)) + (PORT datac (626:626:626) (759:759:759)) + (PORT datad (608:608:608) (735:735:735)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (731:731:731)) + (PORT datac (565:565:565) (674:674:674)) + (PORT datad (692:692:692) (817:817:817)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (650:650:650)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (665:665:665) (781:781:781)) + (PORT datad (735:735:735) (874:874:874)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (732:732:732)) + (PORT datad (581:581:581) (690:690:690)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (900:900:900)) + (PORT datad (673:673:673) (792:792:792)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (919:919:919)) + (PORT asdata (844:844:844) (945:945:945)) + (PORT ena (423:423:423) (455:455:455)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (919:919:919)) + (PORT asdata (545:545:545) (613:613:613)) + (PORT ena (423:423:423) (455:455:455)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (461:461:461)) + (PORT datab (682:682:682) (787:787:787)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (919:919:919)) + (PORT asdata (1764:1764:1764) (1999:1999:1999)) + (PORT ena (423:423:423) (455:455:455)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (846:846:846)) + (PORT datab (625:625:625) (761:761:761)) + (PORT datac (625:625:625) (758:758:758)) + (PORT datad (876:876:876) (1043:1043:1043)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (722:722:722)) + (PORT datac (476:476:476) (558:558:558)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (615:615:615)) + (PORT datab (832:832:832) (963:963:963)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (920:920:920)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~3) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (929:929:929)) + (PORT datab (534:534:534) (640:640:640)) + (PORT datac (864:864:864) (1014:1014:1014)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (644:644:644)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (165:165:165) (190:190:190)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -52364,7 +55661,7 @@ (INSTANCE sdram_\|r\.rd_pending) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) + (PORT clk (913:913:913) (920:920:920)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -52373,12 +55670,162 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1607:1607:1607) (1844:1844:1844)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (235:235:235) (300:300:300)) + (PORT datad (372:372:372) (446:446:446)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (647:647:647)) + (PORT datab (591:591:591) (702:702:702)) + (PORT datac (634:634:634) (731:731:731)) + (PORT datad (692:692:692) (817:817:817)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (547:547:547)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (565:565:565) (675:675:675)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT datab (529:529:529) (633:633:633)) + (PORT datac (594:594:594) (715:715:715)) + (PORT datad (735:735:735) (874:874:874)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (700:700:700)) + (PORT datab (547:547:547) (661:661:661)) + (PORT datac (594:594:594) (715:715:715)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (650:650:650)) + (PORT datab (593:593:593) (704:704:704)) + (PORT datac (632:632:632) (729:729:729)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (576:576:576)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (476:476:476) (537:537:537)) + (PORT datad (463:463:463) (524:524:524)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datac (912:912:912) (1080:1080:1080)) + (PORT datad (857:857:857) (1008:1008:1008)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) + (PORT datab (134:134:134) (184:184:184)) (IOPATH datab combout (192:192:192) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52387,16 +55834,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (INSTANCE sdram_\|r\.rf_counter\[8\]\~32) (DELAY (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (522:522:522) (621:621:621)) - (PORT datac (353:353:353) (412:412:412)) - (PORT datad (757:757:757) (898:898:898)) + (PORT dataa (209:209:209) (247:247:247)) + (PORT datab (379:379:379) (456:456:456)) + (PORT datac (912:912:912) (1081:1081:1081)) + (PORT datad (857:857:857) (1008:1008:1008)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52408,7 +55855,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52422,9 +55869,9 @@ (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52438,7 +55885,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52452,7 +55899,7 @@ (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) + (PORT datab (135:135:135) (184:184:184)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52468,7 +55915,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52482,7 +55929,7 @@ (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) + (PORT dataa (136:136:136) (188:188:188)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52498,7 +55945,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52507,14 +55954,30 @@ (HOLD sclr (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52528,7 +55991,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52542,9 +56005,9 @@ (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (135:135:135) (186:186:186)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52558,7 +56021,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52572,9 +56035,9 @@ (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (187:187:187)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52588,7 +56051,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52618,7 +56081,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52627,28 +56090,12 @@ (HOLD sclr (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (137:137:137) (191:191:191)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datac (122:122:122) (166:166:166)) - (PORT datad (123:123:123) (163:163:163)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) + (PORT datab (135:135:135) (184:184:184)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52664,7 +56111,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52673,29 +56120,13 @@ (HOLD sclr (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (139:139:139) (190:190:190)) - (PORT datac (124:124:124) (168:168:168)) - (PORT datad (125:125:125) (165:165:165)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) (DELAY (ABSOLUTE - (PORT datad (121:121:121) (160:160:160)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -52707,7 +56138,7 @@ (ABSOLUTE (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (321:321:321) (375:375:375)) + (PORT sclr (321:321:321) (376:376:376)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52718,15 +56149,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~2) + (INSTANCE sdram_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (175:175:175) (213:213:213)) - (PORT datab (136:136:136) (185:185:185)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (122:122:122) (160:160:160)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52734,13 +56165,17 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~8) + (INSTANCE sdram_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT datab (774:774:774) (923:923:923)) - (PORT datac (508:508:508) (600:600:600)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52749,9 +56184,9 @@ (INSTANCE sdram_\|Mux37\~0) (DELAY (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (367:367:367) (433:433:433)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (379:379:379) (457:457:457)) + (PORT datad (106:106:106) (123:123:123)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -52775,32 +56210,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~0) + (INSTANCE sdram_\|Mux4\~1) (DELAY (ABSOLUTE - (PORT dataa (416:416:416) (510:510:510)) - (PORT datab (411:411:411) (505:505:505)) - (PORT datac (359:359:359) (440:440:440)) - (PORT datad (460:460:460) (536:536:536)) + (PORT dataa (511:511:511) (612:612:612)) + (PORT datab (555:555:555) (664:664:664)) + (PORT datac (483:483:483) (563:563:563)) + (PORT datad (549:549:549) (664:664:664)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~1) + (INSTANCE sdram_\|Mux4\~4) (DELAY (ABSOLUTE - (PORT dataa (456:456:456) (560:560:560)) - (PORT datab (557:557:557) (664:664:664)) - (PORT datac (718:718:718) (858:858:858)) - (PORT datad (297:297:297) (341:341:341)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (709:709:709) (845:845:845)) + (PORT datab (642:642:642) (776:776:776)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (444:444:444) (502:502:502)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52810,27 +56245,27 @@ (INSTANCE sdram_\|Mux4\~2) (DELAY (ABSOLUTE - (PORT dataa (455:455:455) (560:560:560)) - (PORT datab (556:556:556) (663:663:663)) - (PORT datac (718:718:718) (857:857:857)) - (PORT datad (297:297:297) (340:340:340)) + (PORT dataa (160:160:160) (212:212:212)) + (PORT datab (154:154:154) (207:207:207)) + (PORT datac (998:998:998) (1153:1153:1153)) + (PORT datad (146:146:146) (192:192:192)) (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~3) + (INSTANCE sdram_\|Mux4\~5) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (412:412:412)) - (PORT datab (166:166:166) (221:221:221)) - (PORT datad (329:329:329) (384:384:384)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (347:347:347) (400:400:400)) + (PORT datab (502:502:502) (586:586:586)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52841,7 +56276,7 @@ (INSTANCE sdram_\|r\.state\[8\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) + (PORT clk (921:921:921) (928:928:928)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -52852,13 +56287,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (INSTANCE sdram_\|process_0\~4) (DELAY (ABSOLUTE - (PORT dataa (730:730:730) (872:872:872)) - (PORT datab (610:610:610) (729:729:729)) - (PORT datac (759:759:759) (874:874:874)) - (PORT datad (549:549:549) (652:652:652)) + (PORT datac (127:127:127) (168:168:168)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (646:646:646)) + (PORT datab (597:597:597) (725:725:725)) + (PORT datac (536:536:536) (628:628:628)) + (PORT datad (746:746:746) (862:862:862)) (IOPATH dataa combout (159:159:159) (173:173:173)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -52868,113 +56315,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~2) + (INSTANCE sdram_\|r\.act_row\[2\]\~1) (DELAY (ABSOLUTE - (PORT datac (144:144:144) (187:187:187)) - (PORT datad (158:158:158) (201:201:201)) + (PORT dataa (740:740:740) (868:868:868)) + (PORT datab (867:867:867) (1011:1011:1011)) + (PORT datac (641:641:641) (742:742:742)) + (PORT datad (337:337:337) (393:393:393)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (189:189:189) (231:231:231)) - (PORT datac (569:569:569) (683:683:683)) - (PORT datad (551:551:551) (655:655:655)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (495:495:495) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (870:870:870) (972:972:972)) - (PORT ena (495:495:495) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (664:664:664) (768:768:768)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (495:495:495) (532:532:532)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (819:819:819)) - (PORT datab (682:682:682) (791:791:791)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.act_row\[1\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (730:730:730) (824:824:824)) - (PORT ena (495:495:495) (532:532:532)) + (PORT clk (913:913:913) (919:919:919)) + (PORT asdata (1223:1223:1223) (1394:1394:1394)) + (PORT ena (423:423:423) (455:455:455)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -52988,9 +56350,9 @@ (INSTANCE sdram_\|r\.act_row\[0\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT asdata (1745:1745:1745) (1998:1998:1998)) - (PORT ena (495:495:495) (532:532:532)) + (PORT clk (913:913:913) (919:919:919)) + (PORT asdata (715:715:715) (803:803:803)) + (PORT ena (423:423:423) (455:455:455)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53004,9 +56366,9 @@ (INSTANCE sdram_\|Equal7\~0) (DELAY (ABSOLUTE - (PORT dataa (1584:1584:1584) (1848:1848:1848)) - (PORT datab (566:566:566) (669:669:669)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (661:661:661) (763:763:763)) + (PORT datab (1059:1059:1059) (1238:1238:1238)) + (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -53019,116 +56381,13 @@ (INSTANCE sdram_\|Equal7\~2) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (272:272:272)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (897:897:897)) - (PORT datab (570:570:570) (680:680:680)) - (PORT datac (568:568:568) (682:682:682)) - (PORT datad (591:591:591) (705:705:705)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~1) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (841:841:841)) - (PORT datac (300:300:300) (351:351:351)) - (PORT datad (172:172:172) (204:204:204)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~2) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (351:351:351) (409:409:409)) - (PORT datad (753:753:753) (863:863:863)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.wr_pending) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~8) - (DELAY - (ABSOLUTE - (PORT datac (636:636:636) (750:750:750)) - (PORT datad (600:600:600) (722:722:722)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~9) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (295:295:295)) - (PORT datab (318:318:318) (377:377:377)) - (PORT datac (365:365:365) (447:447:447)) - (PORT datad (158:158:158) (201:201:201)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux6\~3) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (844:844:844)) - (PORT datab (171:171:171) (225:225:225)) - (PORT datac (104:104:104) (125:125:125)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (186:186:186) (180:180:180)) + (PORT dataa (1608:1608:1608) (1845:1845:1845)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (106:106:106) (130:130:130)) + (PORT datad (122:122:122) (162:162:162)) + (IOPATH dataa combout (159:159:159) (173:173:173)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53138,11 +56397,55 @@ (INSTANCE sdram_\|Mux6\~4) (DELAY (ABSOLUTE - (PORT datab (375:375:375) (462:462:462)) - (PORT datac (297:297:297) (349:349:349)) - (PORT datad (690:690:690) (811:811:811)) + (PORT dataa (517:517:517) (612:612:612)) + (PORT datab (431:431:431) (530:530:530)) + (PORT datad (615:615:615) (737:737:737)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (628:628:628)) + (PORT datab (430:430:430) (528:528:528)) + (PORT datac (496:496:496) (594:594:594)) + (PORT datad (496:496:496) (580:580:580)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT datac (630:630:630) (769:769:769)) + (PORT datad (665:665:665) (773:773:773)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (148:148:148)) + (PORT datab (637:637:637) (768:768:768)) + (PORT datac (493:493:493) (602:602:602)) + (PORT datad (95:95:95) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53152,11 +56455,11 @@ (INSTANCE sdram_\|Mux6\~2) (DELAY (ABSOLUTE - (PORT dataa (706:706:706) (839:839:839)) - (PORT datac (637:637:637) (751:751:751)) - (PORT datad (601:601:601) (722:722:722)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (678:678:678) (798:798:798)) + (PORT datac (625:625:625) (764:764:764)) + (PORT datad (621:621:621) (745:745:745)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53166,10 +56469,10 @@ (INSTANCE sdram_\|Mux6\~5) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (525:525:525) (624:624:624)) - (PORT datad (90:90:90) (108:108:108)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (548:548:548) (649:649:649)) + (PORT datad (92:92:92) (111:111:111)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -53179,13 +56482,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~3) + (INSTANCE sdram_\|process_0\~2) (DELAY (ABSOLUTE - (PORT dataa (495:495:495) (586:586:586)) - (PORT datac (435:435:435) (497:497:497)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (429:429:429) (528:528:528)) + (PORT datad (495:495:495) (579:579:579)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53194,12 +56497,12 @@ (INSTANCE sdram_\|Mux6\~0) (DELAY (ABSOLUTE - (PORT dataa (161:161:161) (220:220:220)) - (PORT datab (401:401:401) (490:490:490)) - (PORT datac (106:106:106) (130:130:130)) - (PORT datad (399:399:399) (485:485:485)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (161:161:161) (174:174:174)) + (PORT dataa (516:516:516) (624:624:624)) + (PORT datab (647:647:647) (787:787:787)) + (PORT datac (105:105:105) (133:133:133)) + (PORT datad (665:665:665) (773:773:773)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53210,13 +56513,13 @@ (INSTANCE sdram_\|Mux6\~1) (DELAY (ABSOLUTE - (PORT dataa (154:154:154) (209:209:209)) - (PORT datab (163:163:163) (218:218:218)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (399:399:399) (485:485:485)) + (PORT dataa (400:400:400) (485:485:485)) + (PORT datab (853:853:853) (993:993:993)) + (PORT datac (344:344:344) (400:400:400)) + (PORT datad (380:380:380) (451:451:451)) (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53226,10 +56529,10 @@ (INSTANCE sdram_\|Mux6\~6) (DELAY (ABSOLUTE - (PORT datab (166:166:166) (220:220:220)) - (PORT datac (329:329:329) (385:385:385)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (160:160:160) (218:218:218)) + (PORT datac (514:514:514) (586:586:586)) + (PORT datad (321:321:321) (364:364:364)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53240,7 +56543,7 @@ (INSTANCE sdram_\|r\.state\[6\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) + (PORT clk (921:921:921) (928:928:928)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53251,29 +56554,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~6) + (INSTANCE sdram_\|Mux5\~7) (DELAY (ABSOLUTE - (PORT dataa (732:732:732) (873:873:873)) - (PORT datac (567:567:567) (681:681:681)) - (PORT datad (546:546:546) (649:649:649)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~2) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (363:363:363)) - (PORT datab (774:774:774) (905:905:905)) - (PORT datac (366:366:366) (449:449:449)) - (PORT datad (597:597:597) (718:718:718)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (543:543:543) (655:655:655)) + (PORT datab (530:530:530) (633:633:633)) + (PORT datac (679:679:679) (792:792:792)) + (PORT datad (695:695:695) (820:820:820)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53281,159 +56570,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~3) + (INSTANCE sdram_\|Mux5\~8) (DELAY (ABSOLUTE - (PORT datab (456:456:456) (558:558:558)) - (PORT datac (436:436:436) (536:536:536)) - (PORT datad (478:478:478) (557:557:557)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~3) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (600:600:600)) - (PORT datab (165:165:165) (221:221:221)) - (PORT datad (400:400:400) (486:486:486)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~4) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (160:160:160) (215:215:215)) - (PORT datac (479:479:479) (561:561:561)) - (PORT datad (151:151:151) (195:195:195)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~5) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (583:583:583)) - (PORT datab (165:165:165) (221:221:221)) - (PORT datac (382:382:382) (469:469:469)) + (PORT dataa (607:607:607) (727:727:727)) + (PORT datab (584:584:584) (702:702:702)) + (PORT datac (509:509:509) (621:621:621)) (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~0) - (DELAY - (ABSOLUTE - (PORT datab (537:537:537) (639:639:639)) - (PORT datac (697:697:697) (823:823:823)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~7) - (DELAY - (ABSOLUTE - (PORT datac (711:711:711) (850:850:850)) - (PORT datad (535:535:535) (635:635:635)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~10) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (572:572:572)) - (PORT datab (541:541:541) (644:644:644)) - (PORT datac (700:700:700) (829:829:829)) - (PORT datad (378:378:378) (463:463:463)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (258:258:258)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (558:558:558) (666:666:666)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~6) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (502:502:502)) - (PORT datab (175:175:175) (210:210:210)) - (PORT datac (142:142:142) (192:192:192)) - (PORT datad (444:444:444) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.state\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux5\~2) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (231:231:231)) - (PORT datab (715:715:715) (847:847:847)) - (PORT datac (521:521:521) (618:618:618)) - (PORT datad (178:178:178) (211:211:211)) + (PORT dataa (711:711:711) (848:848:848)) + (PORT datab (616:616:616) (735:735:735)) + (PORT datac (107:107:107) (129:129:129)) + (PORT datad (184:184:184) (214:214:214)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -53446,13 +56605,13 @@ (INSTANCE sdram_\|Mux5\~10) (DELAY (ABSOLUTE - (PORT dataa (418:418:418) (512:512:512)) - (PORT datab (411:411:411) (506:506:506)) - (PORT datac (432:432:432) (527:527:527)) - (PORT datad (381:381:381) (459:459:459)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (706:706:706) (841:841:841)) + (PORT datab (612:612:612) (730:730:730)) + (PORT datac (538:538:538) (646:646:646)) + (PORT datad (549:549:549) (665:665:665)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53462,13 +56621,13 @@ (INSTANCE sdram_\|Mux5\~3) (DELAY (ABSOLUTE - (PORT dataa (450:450:450) (553:553:553)) - (PORT datab (554:554:554) (661:661:661)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (90:90:90) (108:108:108)) + (PORT dataa (687:687:687) (816:816:816)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (597:597:597) (711:711:711)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53478,61 +56637,29 @@ (INSTANCE sdram_\|Mux5\~4) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (223:223:223)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (710:710:710) (849:849:849)) - (PORT datad (395:395:395) (477:477:477)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~7) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (218:218:218)) - (PORT datab (417:417:417) (509:509:509)) - (PORT datac (480:480:480) (562:562:562)) - (PORT datad (488:488:488) (573:573:573)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (737:737:737) (881:881:881)) + (PORT datab (594:594:594) (719:719:719)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~8) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (219:219:219)) - (PORT datab (166:166:166) (222:222:222)) - (PORT datac (381:381:381) (468:468:468)) - (PORT datad (153:153:153) (198:198:198)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux5\~5) (DELAY (ABSOLUTE - (PORT dataa (511:511:511) (602:602:602)) - (PORT datab (404:404:404) (493:493:493)) - (PORT datac (438:438:438) (500:500:500)) - (PORT datad (151:151:151) (195:195:195)) + (PORT dataa (507:507:507) (611:611:611)) + (PORT datab (381:381:381) (470:470:470)) + (PORT datac (571:571:571) (686:686:686)) + (PORT datad (502:502:502) (586:586:586)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53542,11 +56669,11 @@ (INSTANCE sdram_\|Mux5\~6) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (289:289:289)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (343:343:343) (401:401:401)) - (PORT datad (501:501:501) (580:580:580)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (102:102:102) (131:131:131)) + (PORT datad (620:620:620) (743:743:743)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53558,12 +56685,12 @@ (INSTANCE sdram_\|Mux5\~9) (DELAY (ABSOLUTE - (PORT dataa (153:153:153) (207:207:207)) - (PORT datab (359:359:359) (423:423:423)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (633:633:633) (725:725:725)) + (PORT datab (151:151:151) (204:204:204)) + (PORT datac (474:474:474) (542:542:542)) + (PORT datad (481:481:481) (552:552:552)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53574,7 +56701,7 @@ (INSTANCE sdram_\|r\.state\[7\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (919:919:919)) + (PORT clk (921:921:921) (928:928:928)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53588,56 +56715,90 @@ (INSTANCE sdram_\|n\~2) (DELAY (ABSOLUTE - (PORT datab (568:568:568) (678:678:678)) - (PORT datac (544:544:544) (653:653:653)) - (PORT datad (556:556:556) (655:655:655)) + (PORT datab (555:555:555) (665:665:665)) + (PORT datac (494:494:494) (586:586:586)) + (PORT datad (549:549:549) (664:664:664)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (413:413:413)) + (PORT datab (486:486:486) (577:577:577)) + (PORT datac (500:500:500) (588:588:588)) + (PORT datad (825:825:825) (957:957:957)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (515:515:515) (608:608:608)) + (PORT datac (498:498:498) (587:587:587)) + (PORT datad (824:824:824) (956:956:956)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (611:611:611)) + (PORT datab (443:443:443) (539:539:539)) + (PORT datac (473:473:473) (557:557:557)) + (PORT datad (414:414:414) (498:498:498)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (523:523:523)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (496:496:496) (584:584:584)) + (PORT datad (335:335:335) (387:387:387)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux8\~3) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (228:228:228)) - (PORT datab (697:697:697) (819:819:819)) - (PORT datac (871:871:871) (1024:1024:1024)) - (PORT datad (894:894:894) (1047:1047:1047)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~4) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (942:942:942)) - (PORT datab (831:831:831) (970:970:970)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (694:694:694) (811:811:811)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~10) - (DELAY - (ABSOLUTE - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (637:637:637) (752:752:752)) - (PORT datad (601:601:601) (723:723:723)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (429:429:429) (524:524:524)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (461:461:461) (531:531:531)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53645,7 +56806,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (INSTANCE sdram_\|r\.init_counter\[0\]\~44) (DELAY (ABSOLUTE (IOPATH datac combout (190:190:190) (195:195:195)) @@ -53657,7 +56818,7 @@ (INSTANCE sdram_\|r\.init_counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (928:928:928)) + (PORT clk (912:912:912) (919:919:919)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53668,20 +56829,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~1) + (INSTANCE sdram_\|r\.init_counter\[1\]\~15) (DELAY (ABSOLUTE - (PORT datab (403:403:403) (488:488:488)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (214:214:214) (273:273:273)) + (IOPATH dataa cout (226:226:226) (171:171:171)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~2) + (INSTANCE sdram_\|r\.init_counter\[1\]\~16) (DELAY (ABSOLUTE - (PORT datab (153:153:153) (201:201:201)) + (PORT datab (141:141:141) (190:190:190)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53695,7 +56856,7 @@ (INSTANCE sdram_\|r\.init_counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53706,7 +56867,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~4) + (INSTANCE sdram_\|r\.init_counter\[2\]\~18) (DELAY (ABSOLUTE (PORT dataa (142:142:142) (193:193:193)) @@ -53723,7 +56884,7 @@ (INSTANCE sdram_\|r\.init_counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53734,34 +56895,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~6) + (INSTANCE sdram_\|r\.init_counter\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (279:279:279)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (174:174:174) (210:210:210)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.init_counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53772,7 +56923,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~8) + (INSTANCE sdram_\|r\.init_counter\[4\]\~22) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -53789,7 +56940,7 @@ (INSTANCE sdram_\|r\.init_counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53800,7 +56951,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~10) + (INSTANCE sdram_\|r\.init_counter\[5\]\~24) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -53817,7 +56968,7 @@ (INSTANCE sdram_\|r\.init_counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53828,7 +56979,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~12) + (INSTANCE sdram_\|r\.init_counter\[6\]\~26) (DELAY (ABSOLUTE (PORT datab (142:142:142) (190:190:190)) @@ -53845,7 +56996,7 @@ (INSTANCE sdram_\|r\.init_counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53856,10 +57007,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~14) + (INSTANCE sdram_\|r\.init_counter\[7\]\~28) (DELAY (ABSOLUTE - (PORT datab (154:154:154) (202:202:202)) + (PORT datab (142:142:142) (190:190:190)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53873,7 +57024,7 @@ (INSTANCE sdram_\|r\.init_counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53884,7 +57035,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~16) + (INSTANCE sdram_\|r\.init_counter\[8\]\~30) (DELAY (ABSOLUTE (PORT datab (142:142:142) (190:190:190)) @@ -53901,7 +57052,7 @@ (INSTANCE sdram_\|r\.init_counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53912,10 +57063,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~18) + (INSTANCE sdram_\|r\.init_counter\[9\]\~32) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) + (PORT datab (134:134:134) (183:183:183)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53929,7 +57080,7 @@ (INSTANCE sdram_\|r\.init_counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53940,10 +57091,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~20) + (INSTANCE sdram_\|r\.init_counter\[10\]\~34) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) + (PORT dataa (136:136:136) (187:187:187)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53957,7 +57108,7 @@ (INSTANCE sdram_\|r\.init_counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -53968,37 +57119,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (279:279:279)) - (PORT datab (232:232:232) (290:290:290)) - (PORT datac (204:204:204) (256:256:256)) - (PORT datad (213:213:213) (264:264:264)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (233:233:233) (291:291:291)) - (PORT datac (217:217:217) (272:272:272)) - (PORT datad (131:131:131) (170:170:170)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~22) + (INSTANCE sdram_\|r\.init_counter\[11\]\~36) (DELAY (ABSOLUTE (PORT datab (135:135:135) (184:184:184)) @@ -54015,7 +57136,7 @@ (INSTANCE sdram_\|r\.init_counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54026,10 +57147,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~24) + (INSTANCE sdram_\|r\.init_counter\[12\]\~38) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (188:188:188)) + (PORT dataa (143:143:143) (194:194:194)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54043,7 +57164,7 @@ (INSTANCE sdram_\|r\.init_counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54054,10 +57175,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~26) + (INSTANCE sdram_\|r\.init_counter\[13\]\~40) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) + (PORT datab (141:141:141) (190:190:190)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54071,7 +57192,7 @@ (INSTANCE sdram_\|r\.init_counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54082,10 +57203,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~28) + (INSTANCE sdram_\|r\.init_counter\[14\]\~42) (DELAY (ABSOLUTE - (PORT dataa (134:134:134) (187:187:187)) + (PORT dataa (142:142:142) (193:193:193)) (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -54096,7 +57217,7 @@ (INSTANCE sdram_\|r\.init_counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (925:925:925)) + (PORT clk (911:911:911) (918:918:918)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54105,15 +57226,45 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (232:232:232) (286:286:286)) + (PORT datac (215:215:215) (267:267:267)) + (PORT datad (201:201:201) (245:245:245)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|process_0\~5) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) + (PORT dataa (213:213:213) (272:272:272)) (PORT datab (137:137:137) (187:187:187)) - (PORT datac (124:124:124) (168:168:168)) - (PORT datad (125:125:125) (164:164:164)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (273:273:273)) + (PORT datab (311:311:311) (374:374:374)) + (PORT datac (201:201:201) (247:247:247)) + (PORT datad (205:205:205) (251:251:251)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -54126,58 +57277,12 @@ (INSTANCE sdram_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (204:204:204) (252:252:252)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~11) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (511:511:511)) - (PORT datab (166:166:166) (223:223:223)) - (PORT datad (416:416:416) (498:498:498)) + (PORT dataa (217:217:217) (274:274:274)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (168:168:168) (203:203:203)) + (PORT datad (95:95:95) (115:115:115)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~12) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (356:356:356)) - (PORT datab (367:367:367) (433:433:433)) - (PORT datac (893:893:893) (1043:1043:1043)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~13) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (1002:1002:1002)) - (PORT datab (774:774:774) (919:919:919)) - (PORT datac (295:295:295) (335:335:335)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (186:186:186) (179:179:179)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54188,27 +57293,11 @@ (INSTANCE sdram_\|Mux8\~0) (DELAY (ABSOLUTE - (PORT dataa (705:705:705) (838:838:838)) - (PORT datab (775:775:775) (905:905:905)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (481:481:481) (552:552:552)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~1) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (813:813:813)) - (PORT datab (523:523:523) (620:620:620)) - (PORT datac (525:525:525) (624:624:624)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (155:155:155) (212:212:212)) + (PORT datab (225:225:225) (282:282:282)) + (PORT datac (214:214:214) (265:265:265)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54217,12 +57306,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~2) + (INSTANCE sdram_\|Mux8\~4) (DELAY (ABSOLUTE - (PORT dataa (389:389:389) (472:472:472)) - (PORT datac (637:637:637) (718:718:718)) - (PORT datad (484:484:484) (550:550:550)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (474:474:474) (559:559:559)) + (PORT datad (328:328:328) (380:380:380)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~5) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (214:214:214)) + (PORT datac (330:330:330) (379:379:379)) + (PORT datad (313:313:313) (354:354:354)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54234,7 +57339,7 @@ (INSTANCE sdram_\|r\.state\[4\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (922:922:922)) + (PORT clk (921:921:921) (928:928:928)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54248,12 +57353,10 @@ (INSTANCE sdram_\|Mux72\~0) (DELAY (ABSOLUTE - (PORT datab (1733:1733:1733) (1978:1978:1978)) - (PORT datac (506:506:506) (604:604:604)) - (PORT datad (155:155:155) (203:203:203)) + (PORT datab (949:949:949) (1095:1095:1095)) + (PORT datac (553:553:553) (666:666:666)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54262,12 +57365,12 @@ (INSTANCE sdram_\|Mux72\~1) (DELAY (ABSOLUTE - (PORT dataa (547:547:547) (650:650:650)) - (PORT datab (1732:1732:1732) (1978:1978:1978)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (186:186:186) (216:216:216)) + (PORT dataa (406:406:406) (486:486:486)) + (PORT datab (181:181:181) (239:239:239)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (351:351:351) (405:405:405)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54278,8 +57381,8 @@ (INSTANCE sdram_\|Mux84\~0) (DELAY (ABSOLUTE - (PORT datac (140:140:140) (187:187:187)) - (PORT datad (400:400:400) (486:486:486)) + (PORT datac (160:160:160) (213:213:213)) + (PORT datad (136:136:136) (178:178:178)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54290,13 +57393,13 @@ (INSTANCE sdram_\|Mux84\~1) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (289:289:289)) - (PORT datab (166:166:166) (222:222:222)) - (PORT datac (146:146:146) (196:196:196)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (160:160:160) (217:217:217)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (145:145:145) (187:187:187)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54306,11 +57409,9 @@ (INSTANCE sdram_\|Mux3\~0) (DELAY (ABSOLUTE - (PORT datab (1735:1735:1735) (1980:1980:1980)) - (PORT datac (631:631:631) (730:730:730)) - (PORT datad (152:152:152) (199:199:199)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (631:631:631) (762:762:762)) + (PORT datad (936:936:936) (1072:1072:1072)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54320,13 +57421,13 @@ (INSTANCE sdram_\|Mux3\~1) (DELAY (ABSOLUTE - (PORT dataa (550:550:550) (653:653:653)) - (PORT datab (1735:1735:1735) (1981:1981:1981)) - (PORT datac (159:159:159) (186:186:186)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (178:178:178) (235:235:235)) + (PORT datac (388:388:388) (467:467:467)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54336,12 +57437,10 @@ (INSTANCE sdram_\|Mux2\~0) (DELAY (ABSOLUTE - (PORT datab (1732:1732:1732) (1978:1978:1978)) - (PORT datac (619:619:619) (722:722:722)) - (PORT datad (156:156:156) (204:204:204)) + (PORT datab (846:846:846) (975:975:975)) + (PORT datac (507:507:507) (609:609:609)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54350,12 +57449,12 @@ (INSTANCE sdram_\|Mux2\~1) (DELAY (ABSOLUTE - (PORT dataa (551:551:551) (655:655:655)) - (PORT datab (1736:1736:1736) (1983:1983:1983)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (351:351:351) (405:405:405)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (316:316:316) (378:378:378)) + (PORT datab (183:183:183) (241:241:241)) + (PORT datac (353:353:353) (407:407:407)) + (PORT datad (783:783:783) (894:894:894)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54366,11 +57465,9 @@ (INSTANCE sdram_\|Mux1\~0) (DELAY (ABSOLUTE - (PORT datab (1736:1736:1736) (1982:1982:1982)) - (PORT datac (618:618:618) (725:725:725)) - (PORT datad (151:151:151) (198:198:198)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (1010:1010:1010) (1158:1158:1158)) + (PORT datad (357:357:357) (429:429:429)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54380,13 +57477,13 @@ (INSTANCE sdram_\|Mux1\~1) (DELAY (ABSOLUTE - (PORT dataa (548:548:548) (652:652:652)) - (PORT datab (1733:1733:1733) (1979:1979:1979)) - (PORT datac (318:318:318) (362:362:362)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (427:427:427) (516:516:516)) + (PORT datab (633:633:633) (728:728:728)) + (PORT datac (744:744:744) (850:850:850)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54396,11 +57493,9 @@ (INSTANCE sdram_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT datab (1734:1734:1734) (1979:1979:1979)) - (PORT datac (529:529:529) (632:632:632)) - (PORT datad (153:153:153) (202:202:202)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (1010:1010:1010) (1158:1158:1158)) + (PORT datad (207:207:207) (263:263:263)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54410,13 +57505,13 @@ (INSTANCE sdram_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (550:550:550) (655:655:655)) - (PORT datab (1736:1736:1736) (1982:1982:1982)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (344:344:344) (394:394:394)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (590:590:590) (672:672:672)) + (PORT datab (179:179:179) (236:236:236)) + (PORT datac (387:387:387) (466:466:466)) + (PORT datad (334:334:334) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54426,25 +57521,9 @@ (INSTANCE sdram_\|Mux73\~0) (DELAY (ABSOLUTE - (PORT datab (1733:1733:1733) (1979:1979:1979)) - (PORT datac (849:849:849) (989:989:989)) - (PORT datad (154:154:154) (202:202:202)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux73\~1) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (652:652:652)) - (PORT datab (1734:1734:1734) (1980:1980:1980)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (345:345:345) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (596:596:596) (677:677:677)) + (PORT datac (452:452:452) (514:514:514)) + (PORT datad (106:106:106) (124:124:124)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54456,11 +57535,9 @@ (INSTANCE sdram_\|Mux74\~0) (DELAY (ABSOLUTE - (PORT datab (1736:1736:1736) (1982:1982:1982)) - (PORT datac (506:506:506) (607:607:607)) - (PORT datad (152:152:152) (198:198:198)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (495:495:495) (572:572:572)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54470,13 +57547,13 @@ (INSTANCE sdram_\|Mux74\~1) (DELAY (ABSOLUTE - (PORT dataa (548:548:548) (651:651:651)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (1712:1712:1712) (1956:1956:1956)) - (PORT datad (357:357:357) (412:412:412)) + (PORT dataa (409:409:409) (489:489:489)) + (PORT datab (475:475:475) (549:549:549)) + (PORT datac (163:163:163) (216:216:216)) + (PORT datad (330:330:330) (383:383:383)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54486,9 +57563,23 @@ (INSTANCE sdram_\|Mux75\~0) (DELAY (ABSOLUTE - (PORT datac (850:850:850) (999:999:999)) - (PORT datad (745:745:745) (858:858:858)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (417:417:417) (500:500:500)) + (PORT datab (454:454:454) (531:531:531)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE LED\~0) + (DELAY + (ABSOLUTE + (PORT datac (731:731:731) (840:840:840)) + (PORT datad (818:818:818) (947:947:947)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54507,9 +57598,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1122:1122:1122) (1155:1155:1155)) + (PORT clk (1111:1111:1111) (1141:1141:1141)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (906:906:906)) + (PORT clrn (903:903:903) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54524,7 +57615,7 @@ (DELAY (ABSOLUTE (PORT clk (891:891:891) (913:913:913)) - (PORT d (549:549:549) (502:502:502)) + (PORT d (531:531:531) (491:491:491)) (PORT clrn (1020:1020:1020) (1065:1065:1065)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) @@ -54535,13 +57626,29 @@ (HOLD d (posedge clk) (56:56:56)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT datab (367:367:367) (448:448:448)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (566:566:566) (665:665:665)) + (IOPATH dataa cout (226:226:226) (171:171:171)) ) ) ) @@ -54564,10 +57671,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (110:110:110) (131:131:131)) + (PORT dataa (125:125:125) (161:161:161)) + (PORT datac (92:92:92) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54576,9 +57683,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (905:905:905)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54592,9 +57699,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (272:272:272)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (222:222:222) (282:282:282)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54606,8 +57713,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datac (161:161:161) (190:190:190)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (168:168:168) (197:197:197)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54616,9 +57723,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (906:906:906)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54632,9 +57739,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (284:284:284)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (221:221:221) (281:281:281)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54646,7 +57753,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datad (293:293:293) (340:340:340)) + (PORT datad (167:167:167) (196:196:196)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54656,9 +57763,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1122:1122:1122) (1155:1155:1155)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (906:906:906)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54672,7 +57779,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (137:137:137) (187:187:187)) + (PORT datab (135:135:135) (186:186:186)) (IOPATH datab combout (188:188:188) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54686,10 +57793,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (111:111:111) (132:132:132)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (131:131:131) (168:168:168)) + (PORT datac (90:90:90) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -54698,9 +57805,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (905:905:905)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54714,7 +57821,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (287:287:287)) + (PORT dataa (209:209:209) (273:273:273)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54728,8 +57835,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (162:162:162) (189:189:189)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (162:162:162) (191:191:191)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -54738,9 +57845,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (906:906:906)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54754,13 +57861,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (271:271:271)) - (PORT datab (134:134:134) (184:184:184)) - (PORT datac (202:202:202) (258:258:258)) - (PORT datad (201:201:201) (255:255:255)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (211:211:211) (275:275:275)) + (PORT datab (224:224:224) (283:283:283)) + (PORT datac (124:124:124) (167:167:167)) + (PORT datad (202:202:202) (254:254:254)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54770,7 +57877,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (220:220:220) (280:280:280)) + (PORT datab (223:223:223) (283:283:283)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -54784,7 +57891,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (168:168:168) (197:197:197)) + (PORT datad (160:160:160) (187:187:187)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54794,9 +57901,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (906:906:906)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54810,9 +57917,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (270:270:270)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (208:208:208) (268:268:268)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54824,8 +57931,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datac (169:169:169) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (169:169:169) (198:198:198)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54834,9 +57941,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (906:906:906)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54864,10 +57971,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (105:105:105) (135:135:135)) - (PORT datad (112:112:112) (132:132:132)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (132:132:132) (169:169:169)) + (PORT datac (92:92:92) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -54876,9 +57983,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1140:1140:1140)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (902:902:902) (905:905:905)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54892,7 +57999,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (199:199:199) (248:248:248)) + (PORT datad (204:204:204) (259:259:259)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -54903,8 +58010,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datac (174:174:174) (209:209:209)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (170:170:170) (200:200:200)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54913,9 +58020,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1109:1109:1109) (1139:1139:1139)) + (PORT clk (1112:1112:1112) (1142:1142:1142)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (905:905:905)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -54929,13 +58036,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (271:271:271)) - (PORT datab (219:219:219) (275:275:275)) - (PORT datac (120:120:120) (162:162:162)) - (PORT datad (204:204:204) (257:257:257)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (223:223:223) (283:283:283)) + (PORT datab (206:206:206) (266:266:266)) + (PORT datac (205:205:205) (262:262:262)) + (PORT datad (119:119:119) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54945,41 +58052,24 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (133:133:133) (183:183:183)) - (PORT datac (160:160:160) (189:189:189)) - (PORT datad (351:351:351) (425:425:425)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (543:543:543) (641:641:641)) + (PORT datad (120:120:120) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT asdata (278:278:278) (297:297:297)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (521:521:521) (608:608:608)) - (PORT datad (123:123:123) (163:163:163)) - (IOPATH datab combout (192:192:192) (181:181:181)) + (PORT datad (681:681:681) (780:780:780)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54990,7 +58080,7 @@ (DELAY (ABSOLUTE (PORT clk (889:889:889) (911:911:911)) - (PORT d (751:751:751) (802:802:802)) + (PORT d (849:849:849) (939:939:939)) (PORT clrn (1018:1018:1018) (1063:1063:1063)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) @@ -55007,7 +58097,7 @@ (DELAY (ABSOLUTE (PORT clk (891:891:891) (912:912:912)) - (PORT d (747:747:747) (799:799:799)) + (PORT d (1034:1034:1034) (1136:1136:1136)) (PORT clrn (1020:1020:1020) (1064:1064:1064)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) @@ -55018,37 +58108,6 @@ (HOLD d (posedge clk) (56:56:56)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (260:260:260)) - (PORT datab (525:525:525) (613:613:613)) - (PORT datad (115:115:115) (139:139:139)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) @@ -55062,22 +58121,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT datac (102:102:102) (123:123:123)) + (PORT datab (402:402:402) (485:485:485)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (192:192:192)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (667:667:667)) + (PORT datab (692:692:692) (800:800:800)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (382:382:382) (458:458:458)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (906:906:906) (910:910:910)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (909:909:909)) + (PORT clrn (895:895:895) (898:898:898)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55088,15 +58177,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) + (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (497:497:497) (576:576:576)) - (PORT datab (148:148:148) (203:203:203)) - (PORT datac (109:109:109) (133:133:133)) + (PORT datab (368:368:368) (448:448:448)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (434:434:434)) + (PORT datab (551:551:551) (646:646:646)) + (PORT datac (117:117:117) (151:151:151)) + (PORT datad (118:118:118) (148:148:148)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (896:896:896) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (474:474:474)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (542:542:542)) + (PORT datab (561:561:561) (658:658:658)) + (PORT datac (137:137:137) (182:182:182)) + (PORT datad (343:343:343) (398:398:398)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (896:896:896) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (356:356:356) (427:427:427)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (391:391:391)) + (PORT datab (553:553:553) (648:648:648)) + (PORT datac (116:116:116) (150:150:150)) + (PORT datad (117:117:117) (147:147:147)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (896:896:896) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (477:477:477)) + (PORT datab (364:364:364) (443:443:443)) + (PORT datac (120:120:120) (164:164:164)) + (PORT datad (354:354:354) (425:425:425)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (172:172:172)) + (PORT datab (552:552:552) (647:647:647)) + (PORT datad (338:338:338) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (896:896:896) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (205:205:205)) + (PORT datad (341:341:341) (396:396:396)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (896:896:896) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (167:167:167)) + (PORT datab (559:559:559) (655:655:655)) + (PORT datac (111:111:111) (145:145:145)) + (PORT datad (128:128:128) (171:171:171)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -55105,12 +58406,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (301:301:301) (329:329:329)) - (PORT clrn (906:906:906) (909:909:909)) - (PORT sload (797:797:797) (886:886:886)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (541:541:541) (604:604:604)) + (PORT clrn (896:896:896) (901:901:901)) + (PORT sload (854:854:854) (962:962:962)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55141,12 +58442,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (300:300:300) (327:327:327)) - (PORT clrn (906:906:906) (909:909:909)) - (PORT sload (797:797:797) (886:886:886)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (543:543:543) (606:606:606)) + (PORT clrn (896:896:896) (901:901:901)) + (PORT sload (854:854:854) (962:962:962)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55160,10 +58461,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~10) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) + (PORT datab (142:142:142) (190:190:190)) (IOPATH datab combout (188:188:188) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55177,12 +58478,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (299:299:299) (327:327:327)) - (PORT clrn (906:906:906) (909:909:909)) - (PORT sload (797:797:797) (886:886:886)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (543:543:543) (606:606:606)) + (PORT clrn (896:896:896) (901:901:901)) + (PORT sload (854:854:854) (962:962:962)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55196,10 +58497,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~12) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) + (PORT datab (135:135:135) (184:184:184)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55213,12 +58514,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (298:298:298) (326:326:326)) - (PORT clrn (906:906:906) (909:909:909)) - (PORT sload (797:797:797) (886:886:886)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (543:543:543) (607:607:607)) + (PORT clrn (896:896:896) (901:901:901)) + (PORT sload (854:854:854) (962:962:962)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55232,10 +58533,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~14) (DELAY (ABSOLUTE - (PORT dataa (146:146:146) (201:201:201)) + (PORT dataa (141:141:141) (194:194:194)) (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -55246,12 +58547,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (298:298:298) (326:326:326)) - (PORT clrn (906:906:906) (909:909:909)) - (PORT sload (797:797:797) (886:886:886)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (544:544:544) (608:608:608)) + (PORT clrn (896:896:896) (901:901:901)) + (PORT sload (854:854:854) (962:962:962)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55268,10 +58569,10 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (269:269:269)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datac (121:121:121) (163:163:163)) - (PORT datad (122:122:122) (162:162:162)) + (PORT dataa (212:212:212) (271:271:271)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (120:120:120) (163:163:163)) + (PORT datad (122:122:122) (161:161:161)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -55281,265 +58582,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) + (INSTANCE ula_\|i2s_intf_\|LessThan0\~1) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (262:262:262)) - (PORT datab (285:285:285) (326:326:326)) - (PORT datac (133:133:133) (182:182:182)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (126:126:126) (173:173:173)) + (PORT datad (95:95:95) (114:114:114)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (289:289:289)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (137:137:137) (187:187:187)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (287:287:287)) - (PORT datab (526:526:526) (613:613:613)) - (PORT datac (162:162:162) (190:190:190)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT datab (302:302:302) (367:367:367)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (262:262:262)) - (PORT datab (524:524:524) (611:611:611)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (171:171:171) (200:200:200)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (289:289:289)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (474:474:474) (539:539:539)) - (PORT datad (117:117:117) (141:141:141)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (260:260:260)) - (PORT datab (526:526:526) (613:613:613)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (174:174:174) (203:203:203)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (186:186:186)) - (PORT datab (133:133:133) (183:183:183)) - (PORT datac (121:121:121) (163:163:163)) - (PORT datad (289:289:289) (344:344:344)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (132:132:132) (165:165:165)) - (PORT datad (209:209:209) (263:263:263)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT dataa (113:113:113) (147:147:147)) - (PORT datac (132:132:132) (181:181:181)) - (PORT datad (137:137:137) (182:182:182)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (330:330:330)) - (PORT datab (148:148:148) (202:202:202)) - (PORT datac (481:481:481) (551:551:551)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (132:132:132) (172:172:172)) + (PORT datab (133:133:133) (171:171:171)) + (PORT datad (536:536:536) (622:622:622)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55550,7 +58613,7 @@ (DELAY (ABSOLUTE (PORT clk (888:888:888) (910:910:910)) - (PORT d (814:814:814) (884:884:884)) + (PORT d (1169:1169:1169) (1298:1298:1298)) (PORT clrn (1017:1017:1017) (1062:1062:1062)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) @@ -55566,7 +58629,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (521:521:521) (595:595:595)) + (PORT datad (360:360:360) (418:418:418)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55576,12 +58639,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT datab (1084:1084:1084) (1288:1288:1288)) - (PORT datac (1740:1740:1740) (2036:2036:2036)) - (PORT datad (1447:1447:1447) (1663:1663:1663)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (692:692:692) (825:825:825)) + (PORT datab (642:642:642) (740:740:740)) + (PORT datac (629:629:629) (721:721:721)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -55590,13 +58653,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (1451:1451:1451) (1709:1709:1709)) - (PORT datab (675:675:675) (802:802:802)) - (PORT datac (1190:1190:1190) (1383:1383:1383)) - (PORT datad (590:590:590) (658:658:658)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (676:676:676) (789:789:789)) + (PORT datab (932:932:932) (1085:1085:1085)) + (PORT datac (675:675:675) (801:801:801)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55606,9 +58669,9 @@ (INSTANCE ula_\|pcm_outl\[13\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (510:510:510) (556:556:556)) + (PORT ena (867:867:867) (942:942:942)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55619,15 +58682,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (288:288:288) (336:336:336)) - (PORT datab (154:154:154) (209:209:209)) - (PORT datac (135:135:135) (184:184:184)) - (PORT datad (99:99:99) (121:121:121)) + (PORT dataa (139:139:139) (192:192:192)) + (PORT datab (494:494:494) (583:583:583)) + (PORT datad (679:679:679) (777:777:777)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (493:493:493) (582:582:582)) + (PORT datad (680:680:680) (779:779:779)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (118:118:118) (159:159:159)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (765:765:765) (834:834:834)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (127:127:127) (165:165:165)) + (PORT datac (128:128:128) (174:174:174)) + (PORT datad (128:128:128) (171:171:171)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55644,14 +58797,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (640:640:640)) - (PORT datab (293:293:293) (341:341:341)) - (PORT datad (422:422:422) (452:452:452)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (507:507:507) (594:594:594)) + (PORT datab (281:281:281) (349:349:349)) + (PORT datad (436:436:436) (468:468:468)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55662,9 +58815,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1144:1144:1144)) + (PORT clk (1096:1096:1096) (1116:1116:1116)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) + (PORT clrn (904:904:904) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55675,27 +58828,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (512:512:512) (595:595:595)) - (PORT datad (120:120:120) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (263:263:263) (322:322:322)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]\~1) (DELAY (ABSOLUTE - (PORT dataa (497:497:497) (576:576:576)) - (PORT datab (152:152:152) (208:208:208)) - (PORT datac (106:106:106) (130:130:130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (128:128:128) (167:167:167)) + (PORT datab (560:560:560) (656:656:656)) + (PORT datac (109:109:109) (142:142:142)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -55704,40 +58859,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT datac (521:521:521) (606:606:606)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55752,22 +58877,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (179:179:179)) - (PORT datac (518:518:518) (603:603:603)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datab (291:291:291) (360:360:360)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55782,22 +58907,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datac (515:515:515) (599:599:599)) - (PORT datad (118:118:118) (154:154:154)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (282:282:282) (350:350:350)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55812,22 +58937,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (184:184:184)) - (PORT datac (522:522:522) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datab (292:292:292) (362:362:362)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55842,22 +58967,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT datac (517:517:517) (602:602:602)) + (PORT datab (290:290:290) (359:359:359)) (PORT datad (118:118:118) (155:155:155)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55872,22 +58997,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datac (525:525:525) (610:610:610)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (279:279:279) (347:347:347)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55902,22 +59027,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (178:178:178)) - (PORT datac (528:528:528) (614:614:614)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (259:259:259) (318:318:318)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55932,22 +59057,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datac (527:527:527) (613:613:613)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (283:283:283) (351:351:351)) + (PORT datad (117:117:117) (155:155:155)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55962,22 +59087,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datac (523:523:523) (609:609:609)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datac (119:119:119) (161:161:161)) + (PORT datad (274:274:274) (335:335:335)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55992,22 +59117,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datac (529:529:529) (615:615:615)) - (PORT datad (118:118:118) (154:154:154)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (288:288:288) (357:357:357)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -56022,22 +59147,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datac (513:513:513) (597:597:597)) - (PORT datad (120:120:120) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (270:270:270) (330:330:330)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -56047,119 +59172,27 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (296:296:296)) - (PORT datab (525:525:525) (612:612:612)) - (PORT datad (128:128:128) (169:169:169)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (296:296:296)) - (PORT datab (525:525:525) (612:612:612)) - (PORT datad (127:127:127) (169:169:169)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outr\~0) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1630:1630:1630) (1808:1808:1808)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datac (516:516:516) (601:601:601)) - (PORT datad (192:192:192) (239:239:239)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT datac (118:118:118) (159:159:159)) + (PORT datad (264:264:264) (323:323:323)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -56174,24 +59207,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (786:786:786) (914:914:914)) - (PORT datac (510:510:510) (594:594:594)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (293:293:293) (363:363:363)) + (PORT datac (684:684:684) (803:803:803)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -56201,42 +59234,64 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (303:303:303) (349:349:349)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (510:510:510) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datac (514:514:514) (598:598:598)) - (PORT datad (850:850:850) (990:990:990)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (666:666:666) (771:771:771)) + (PORT datac (364:364:364) (434:434:434)) + (PORT datad (671:671:671) (780:780:780)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1131:1131:1131)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (897:897:897)) + (PORT ena (637:637:637) (689:689:689)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT asdata (292:292:292) (312:312:312)) + (PORT ena (1201:1201:1201) (1314:1314:1314)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (DELAY + (ABSOLUTE + (PORT datab (528:528:528) (621:621:621)) + (PORT datac (350:350:350) (419:419:419)) + (PORT datad (489:489:489) (577:577:577)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -56246,10 +59301,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (923:923:923) (931:931:931)) + (PORT clk (1100:1100:1100) (1130:1130:1130)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (911:911:911)) - (PORT ena (711:711:711) (764:764:764)) + (PORT clrn (898:898:898) (904:904:904)) + (PORT ena (641:641:641) (698:698:698)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -56261,11 +59316,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~2) (DELAY (ABSOLUTE - (PORT datab (328:328:328) (384:384:384)) - (PORT datad (354:354:354) (428:428:428)) + (PORT datab (286:286:286) (355:355:355)) + (PORT datad (518:518:518) (609:609:609)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -56276,10 +59331,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1149:1149:1149)) + (PORT clk (915:915:915) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (904:904:904) (907:907:907)) - (PORT ena (756:756:756) (822:822:822)) + (PORT clrn (904:904:904) (908:908:908)) + (PORT ena (918:918:918) (1001:1001:1001)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -56294,7 +59349,7 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (327:327:327) (382:382:382)) + (PORT datab (294:294:294) (364:364:364)) (PORT datad (119:119:119) (156:156:156)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -56307,9 +59362,9 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (609:609:609) (642:642:642)) + (PORT d (525:525:525) (558:558:558)) (PORT clrn (1022:1022:1022) (1066:1066:1066)) - (PORT ena (447:447:447) (471:471:471)) + (PORT ena (804:804:804) (880:880:880)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -56323,116 +59378,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (636:636:636) (725:725:725)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (961:961:961) (1066:1066:1066)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (205:205:205)) - (PORT datab (141:141:141) (188:188:188)) - (PORT datac (127:127:127) (167:167:167)) - (PORT datad (128:128:128) (164:164:164)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (154:154:154) (204:204:204)) - (PORT datab (153:153:153) (201:201:201)) - (PORT datac (209:209:209) (253:253:253)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (286:286:286)) - (PORT datab (148:148:148) (199:199:199)) - (PORT datad (128:128:128) (165:165:165)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (287:287:287)) - (PORT datab (353:353:353) (421:421:421)) - (PORT datac (321:321:321) (382:382:382)) - (PORT datad (269:269:269) (304:304:304)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (151:151:151) (205:205:205)) - (PORT datab (157:157:157) (204:204:204)) - (PORT datac (174:174:174) (209:209:209)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (508:508:508) (580:580:580)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (710:710:710) (796:796:796)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -56441,12 +59391,12 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (311:311:311)) - (PORT datab (526:526:526) (627:627:627)) - (PORT datac (380:380:380) (462:462:462)) - (PORT datad (400:400:400) (479:479:479)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (261:261:261) (337:337:337)) + (PORT datab (805:805:805) (980:980:980)) + (PORT datac (895:895:895) (1040:1040:1040)) + (PORT datad (150:150:150) (194:194:194)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -56454,12 +59404,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT clk (1118:1118:1118) (1149:1149:1149)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) + (PORT ena (902:902:902) (989:989:989)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -56473,25 +59423,98 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (311:311:311)) - (PORT datab (522:522:522) (622:622:622)) - (PORT datac (382:382:382) (465:465:465)) - (PORT datad (397:397:397) (476:476:476)) + (PORT dataa (342:342:342) (409:409:409)) + (PORT datab (903:903:903) (1047:1047:1047)) + (PORT datad (328:328:328) (390:390:390)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (775:775:775) (870:870:870)) + (PORT ena (640:640:640) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (673:673:673) (777:777:777)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1118:1118:1118) (1149:1149:1149)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (902:902:902) (989:989:989)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (814:814:814) (923:923:923)) + (PORT ena (922:922:922) (1003:1003:1003)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1118:1118:1118) (1149:1149:1149)) + (PORT asdata (819:819:819) (910:910:910)) + (PORT ena (902:902:902) (989:989:989)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (614:614:614) (686:686:686)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (787:787:787) (891:891:891)) + (PORT ena (640:640:640) (703:703:703)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -56505,10 +59528,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (647:647:647) (744:744:744)) - (PORT datad (124:124:124) (163:163:163)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (119:119:119) (149:149:149)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) ) ) ) @@ -56517,13 +59539,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1102:1102:1102) (1123:1123:1123)) - (PORT asdata (268:268:268) (288:288:288)) + (PORT clk (922:922:922) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL @@ -56531,8 +59553,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (258:258:258)) - (PORT datab (135:135:135) (185:185:185)) + (PORT dataa (525:525:525) (621:621:621)) + (PORT datab (130:130:130) (178:178:178)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -56546,9 +59568,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (946:946:946) (1033:1033:1033)) + (PORT ena (931:931:931) (1018:1018:1018)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -56576,9 +59598,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (946:946:946) (1033:1033:1033)) + (PORT ena (931:931:931) (1018:1018:1018)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -56606,9 +59628,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (946:946:946) (1033:1033:1033)) + (PORT ena (931:931:931) (1018:1018:1018)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -56622,25 +59644,35 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (200:200:200) (246:246:246)) + (PORT datad (124:124:124) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (922:922:922)) - (PORT asdata (340:340:340) (365:365:365)) - (PORT ena (946:946:946) (1033:1033:1033)) + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (931:931:931) (1018:1018:1018)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -56649,31 +59681,21 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (358:358:358) (427:427:427)) + (PORT datad (119:119:119) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (595:595:595) (672:672:672)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (311:311:311)) - (PORT datab (523:523:523) (624:624:624)) - (PORT datac (381:381:381) (464:464:464)) - (PORT datad (398:398:398) (478:478:478)) + (PORT dataa (261:261:261) (338:338:338)) + (PORT datab (806:806:806) (980:980:980)) + (PORT datac (895:895:895) (1040:1040:1040)) + (PORT datad (151:151:151) (195:195:195)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -56681,279 +59703,51 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (716:716:716) (820:820:820)) - (PORT ena (642:642:642) (689:689:689)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (793:793:793) (898:898:898)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (523:523:523) (594:594:594)) - (PORT ena (642:642:642) (689:689:689)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (524:524:524) (604:604:604)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (352:352:352) (426:426:426)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (689:689:689)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (506:506:506) (577:577:577)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (529:529:529) (602:602:602)) - (PORT ena (642:642:642) (689:689:689)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (170:170:170) (225:225:225)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datad (198:198:198) (241:241:241)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (168:168:168) (225:225:225)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (573:573:573) (644:644:644)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT asdata (639:639:639) (696:696:696)) + (PORT ena (730:730:730) (795:795:795)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (351:351:351) (422:422:422)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (602:602:602) (671:671:671)) + (PORT ena (922:922:922) (1003:1003:1003)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (503:503:503) (574:574:574)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT asdata (804:804:804) (887:887:887)) + (PORT ena (730:730:730) (795:795:795)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -56962,9 +59756,25 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (810:810:810) (921:921:921)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (515:515:515) (582:582:582)) + (PORT ena (922:922:922) (1003:1003:1003)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT asdata (885:885:885) (969:969:969)) + (PORT ena (730:730:730) (795:795:795)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -56973,38 +59783,12 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (351:351:351) (404:404:404)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (350:350:350) (422:422:422)) + (PORT datad (716:716:716) (826:826:826)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57014,9 +59798,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (689:689:689)) + (PORT ena (922:922:922) (1003:1003:1003)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57025,29 +59809,19 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (515:515:515) (592:592:592)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1124:1124:1124)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (638:638:638) (699:699:699)) + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT asdata (657:657:657) (722:722:722)) + (PORT ena (730:730:730) (795:795:795)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -57056,9 +59830,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (618:618:618) (692:692:692)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (600:600:600) (672:672:672)) + (PORT ena (922:922:922) (1003:1003:1003)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57072,11 +59846,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (173:173:173) (231:231:231)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (201:201:201) (245:245:245)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT dataa (130:130:130) (179:179:179)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datad (143:143:143) (188:188:188)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57087,9 +59861,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (174:174:174) (231:231:231)) - (PORT datab (130:130:130) (177:177:177)) - (PORT datad (89:89:89) (106:106:106)) + (PORT dataa (159:159:159) (215:215:215)) + (PORT datab (133:133:133) (181:181:181)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -57099,14 +59873,162 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[2\]\~0) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) + (PORT datad (447:447:447) (502:502:502)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (730:730:730) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (795:795:795) (902:902:902)) + (PORT ena (640:640:640) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT asdata (827:827:827) (923:923:923)) + (PORT ena (730:730:730) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (891:891:891) (999:999:999)) + (PORT ena (922:922:922) (1003:1003:1003)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (828:828:828) (949:949:949)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (730:730:730) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (742:742:742) (832:832:832)) + (PORT ena (922:922:922) (1003:1003:1003)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1124:1124:1124)) + (PORT asdata (816:816:816) (907:907:907)) + (PORT ena (730:730:730) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (930:930:930) (1049:1049:1049)) + (PORT ena (922:922:922) (1003:1003:1003)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (259:259:259)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datad (145:145:145) (189:189:189)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57114,96 +60036,102 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT datad (792:792:792) (897:897:897)) + (PORT dataa (156:156:156) (213:213:213)) + (PORT datab (210:210:210) (265:265:265)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (532:532:532) (610:610:610)) - (PORT ena (642:642:642) (689:689:689)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT datad (351:351:351) (404:404:404)) + (PORT dataa (359:359:359) (437:437:437)) + (PORT datab (172:172:172) (206:206:206)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (532:532:532) (606:606:606)) - (PORT ena (766:766:766) (838:838:838)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (113:113:113) (149:149:149)) - (PORT datad (184:184:184) (228:228:228)) - (IOPATH dataa combout (165:165:165) (173:173:173)) + (PORT dataa (218:218:218) (274:274:274)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (143:143:143) (191:191:191)) + (PORT datad (128:128:128) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (212:212:212)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (144:144:144) (186:186:186)) + (PORT datad (99:99:99) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (199:199:199)) + (PORT datad (133:133:133) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (275:275:275)) + (PORT datab (145:145:145) (194:194:194)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (191:191:191) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57214,10 +60142,10 @@ (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (286:286:286)) - (PORT datab (158:158:158) (208:208:208)) - (PORT datac (139:139:139) (185:185:185)) - (PORT datad (146:146:146) (185:185:185)) + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (159:159:159) (208:208:208)) + (PORT datac (145:145:145) (188:188:188)) + (PORT datad (137:137:137) (179:179:179)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -57230,57 +60158,13 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (408:408:408)) - (PORT datab (243:243:243) (300:300:300)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (184:184:184) (213:213:213)) + (PORT dataa (165:165:165) (219:219:219)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (139:139:139) (186:186:186)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (287:287:287)) - (PORT datab (244:244:244) (301:301:301)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (141:141:141) (192:192:192)) - (PORT datad (137:137:137) (177:177:177)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (411:411:411)) - (PORT datab (141:141:141) (190:190:190)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57290,49 +60174,23 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (268:268:268) (305:305:305)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (938:938:938)) - (PORT datab (123:123:123) (155:155:155)) - (PORT datac (166:166:166) (197:197:197)) - (PORT datad (109:109:109) (128:128:128)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (593:593:593) (671:671:671)) + (PORT dataa (288:288:288) (327:327:327)) + (PORT datab (303:303:303) (355:355:355)) + (PORT datad (274:274:274) (300:300:300)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[6\]) + (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) + (PORT ena (765:765:765) (834:834:834)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57341,14 +60199,110 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (222:222:222)) + (PORT datab (153:153:153) (205:205:205)) + (PORT datac (141:141:141) (189:189:189)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (199:199:199)) + (PORT datab (145:145:145) (195:195:195)) + (PORT datac (202:202:202) (249:249:249)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (487:487:487)) + (PORT datab (221:221:221) (274:274:274)) + (PORT datac (349:349:349) (414:414:414)) + (PORT datad (294:294:294) (335:335:335)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (279:279:279)) + (PORT datab (215:215:215) (269:269:269)) + (PORT datac (169:169:169) (201:201:201)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (149:149:149)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (910:910:910) (1034:1034:1034)) + (PORT datad (186:186:186) (216:216:216)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1118:1118:1118) (1149:1149:1149)) + (PORT asdata (632:632:632) (687:687:687)) + (PORT ena (902:902:902) (989:989:989)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (520:520:520) (585:585:585)) - (PORT ena (671:671:671) (738:738:738)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (504:504:504) (566:566:566)) + (PORT ena (621:621:621) (677:677:677)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57362,11 +60316,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (188:188:188) (224:224:224)) - (PORT datab (606:606:606) (691:691:691)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (218:218:218) (260:260:260)) + (PORT datab (310:310:310) (365:365:365)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57377,21 +60331,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (228:228:228)) - (PORT datab (127:127:127) (160:160:160)) - (PORT datac (167:167:167) (197:197:197)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (213:213:213) (252:252:252)) + (PORT datac (108:108:108) (133:133:133)) + (PORT datad (186:186:186) (216:216:216)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (738:738:738) (826:826:826)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57401,51 +60345,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1059:1059:1059) (1163:1163:1163)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (522:522:522) (602:602:602)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (543:543:543) (613:613:613)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1084:1084:1084) (1204:1204:1204)) + (PORT ena (765:765:765) (834:834:834)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57459,8 +60361,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (573:573:573) (645:645:645)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (461:461:461) (520:520:520)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -57469,9 +60371,61 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT clk (1118:1118:1118) (1149:1149:1149)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) + (PORT ena (902:902:902) (989:989:989)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (396:396:396)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (640:640:640) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (828:828:828) (950:950:950)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1118:1118:1118) (1149:1149:1149)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (902:902:902) (989:989:989)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57482,12 +60436,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) + (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (758:758:758) (855:855:855)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (941:941:941) (1065:1065:1065)) + (PORT ena (922:922:922) (1003:1003:1003)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57501,9 +60455,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (151:151:151)) - (PORT datad (119:119:119) (155:155:155)) - (IOPATH dataa combout (165:165:165) (173:173:173)) + (PORT datab (198:198:198) (253:253:253)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57514,12 +60468,12 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (128:128:128) (161:161:161)) - (PORT datac (467:467:467) (548:548:548)) - (PORT datad (164:164:164) (192:192:192)) + (PORT dataa (903:903:903) (1040:1040:1040)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (402:402:402) (452:452:452)) + (PORT datad (188:188:188) (218:218:218)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57530,75 +60484,23 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (225:225:225)) - (PORT datac (308:308:308) (352:352:352)) - (PORT datad (160:160:160) (188:188:188)) + (PORT dataa (122:122:122) (156:156:156)) + (PORT datac (190:190:190) (227:227:227)) + (PORT datad (184:184:184) (215:215:215)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (308:308:308) (350:350:350)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (908:908:908) (996:996:996)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (505:505:505) (576:576:576)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (926:926:926)) - (PORT asdata (521:521:521) (592:592:592)) - (PORT ena (766:766:766) (838:838:838)) + (PORT clk (908:908:908) (912:912:912)) + (PORT asdata (856:856:856) (943:943:943)) + (PORT ena (869:869:869) (942:942:942)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57607,13 +60509,65 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (629:629:629) (714:714:714)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1118:1118:1118) (1149:1149:1149)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (902:902:902) (989:989:989)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (466:466:466) (548:548:548)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (640:640:640) (703:703:703)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (518:518:518) (596:596:596)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (481:481:481) (548:548:548)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -57622,9 +60576,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT clk (1118:1118:1118) (1149:1149:1149)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (635:635:635) (688:688:688)) + (PORT ena (902:902:902) (989:989:989)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57638,9 +60592,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) - (PORT asdata (525:525:525) (591:591:591)) - (PORT ena (642:642:642) (689:689:689)) + (PORT clk (922:922:922) (927:927:927)) + (PORT asdata (619:619:619) (696:696:696)) + (PORT ena (922:922:922) (1003:1003:1003)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57654,9 +60608,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (197:197:197) (253:253:253)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (213:213:213) (268:268:268)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57667,12 +60621,12 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (991:991:991) (1148:1148:1148)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (187:187:187) (222:222:222)) - (PORT datad (191:191:191) (223:223:223)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (737:737:737) (853:853:853)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57683,35 +60637,21 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (224:224:224)) - (PORT datab (180:180:180) (220:220:220)) - (PORT datad (193:193:193) (226:226:226)) + (PORT dataa (358:358:358) (414:414:414)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datad (188:188:188) (219:219:219)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (566:566:566)) - (PORT datac (455:455:455) (529:529:529)) - (PORT datad (617:617:617) (713:713:713)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (923:923:923)) + (PORT clk (922:922:922) (927:927:927)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -57720,14 +60660,28 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (493:493:493)) + (PORT datac (387:387:387) (467:467:467)) + (PORT datad (870:870:870) (1005:1005:1005)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (205:205:205) (250:250:250)) - (PORT datad (187:187:187) (217:217:217)) + (PORT dataa (111:111:111) (146:146:146)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -57741,7 +60695,7 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (1277:1277:1277) (1374:1374:1374)) + (PORT d (1020:1020:1020) (1102:1102:1102)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -57755,7 +60709,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (925:925:925)) + (PORT clk (922:922:922) (926:926:926)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -57769,11 +60723,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (158:158:158) (215:215:215)) - (PORT datab (275:275:275) (318:318:318)) - (PORT datad (817:817:817) (933:933:933)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (123:123:123) (153:153:153)) + (PORT datad (395:395:395) (470:470:470)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57785,7 +60739,7 @@ (DELAY (ABSOLUTE (PORT clk (892:892:892) (914:914:914)) - (PORT d (867:867:867) (946:946:946)) + (PORT d (912:912:912) (984:984:984)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -57799,7 +60753,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (137:137:137) (177:177:177)) + (PORT datad (136:136:136) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57809,10 +60763,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (900:900:900) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -57827,10 +60781,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT asdata (293:293:293) (332:332:332)) - (PORT clrn (918:918:918) (901:901:901)) - (PORT ena (646:646:646) (704:704:704)) + (PORT clk (900:900:900) (905:905:905)) + (PORT asdata (297:297:297) (337:337:337)) + (PORT clrn (898:898:898) (885:885:885)) + (PORT ena (745:745:745) (791:791:791)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -57845,7 +60799,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (136:136:136) (176:176:176)) + (PORT datad (130:130:130) (169:169:169)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57856,9 +60810,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (798:798:798) (916:916:916)) - (PORT datad (137:137:137) (178:178:178)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT datab (2452:2452:2452) (2806:2806:2806)) + (PORT datad (797:797:797) (898:898:898)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57868,11 +60822,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (624:624:624)) - (PORT datac (2038:2038:2038) (2329:2329:2329)) - (PORT datad (304:304:304) (349:349:349)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (2017:2017:2017) (2262:2262:2262)) + (PORT datab (380:380:380) (444:444:444)) + (PORT datad (655:655:655) (744:744:744)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57882,9 +60836,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (510:510:510) (556:556:556)) + (PORT ena (867:867:867) (942:942:942)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -57898,39 +60852,25 @@ (INSTANCE sdram_\|Mux26\~4) (DELAY (ABSOLUTE - (PORT dataa (1316:1316:1316) (1556:1556:1556)) - (PORT datab (520:520:520) (599:599:599)) - (PORT datad (798:798:798) (932:932:932)) + (PORT dataa (1226:1226:1226) (1448:1448:1448)) + (PORT datac (1065:1065:1065) (1202:1202:1202)) + (PORT datad (133:133:133) (171:171:171)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~7) + (INSTANCE sdram_\|r\.bank\[0\]\~6) (DELAY (ABSOLUTE - (PORT datac (572:572:572) (676:676:676)) - (PORT datad (1014:1014:1014) (1180:1180:1180)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (582:582:582)) - (PORT datab (457:457:457) (559:559:559)) - (PORT datac (436:436:436) (536:536:536)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (887:887:887) (1051:1051:1051)) + (PORT datac (1021:1021:1021) (1202:1202:1202)) + (PORT datad (749:749:749) (896:896:896)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -57940,10 +60880,10 @@ (INSTANCE sdram_\|r\.bank\[0\]\~4) (DELAY (ABSOLUTE - (PORT datab (160:160:160) (209:209:209)) - (PORT datac (303:303:303) (356:356:356)) - (PORT datad (157:157:157) (201:201:201)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (498:498:498) (593:593:593)) + (PORT datac (708:708:708) (841:841:841)) + (PORT datad (886:886:886) (1037:1037:1037)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57954,28 +60894,42 @@ (INSTANCE sdram_\|r\.bank\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (573:573:573) (681:681:681)) - (PORT datab (556:556:556) (656:656:656)) - (PORT datac (578:578:578) (690:690:690)) - (PORT datad (317:317:317) (369:369:369)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (746:746:746) (873:873:873)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (485:485:485) (574:574:574)) + (PORT datad (460:460:460) (529:529:529)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~6) + (INSTANCE sdram_\|r\.bank\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (726:726:726) (865:865:865)) - (PORT datab (1052:1052:1052) (1235:1235:1235)) - (PORT datac (573:573:573) (677:677:677)) - (PORT datad (426:426:426) (487:487:487)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (726:726:726) (867:867:867)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (461:461:461) (530:530:530)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (1053:1053:1053)) + (PORT datac (1021:1021:1021) (1202:1202:1202)) + (PORT datad (748:748:748) (894:894:894)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -57986,27 +60940,13 @@ (INSTANCE sdram_\|r\.bank\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (707:707:707) (837:837:837)) - (PORT datac (1035:1035:1035) (1217:1217:1217)) - (PORT datad (561:561:561) (661:661:661)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (585:585:585)) - (PORT datab (456:456:456) (557:557:557)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (770:770:770) (922:922:922)) + (PORT datab (502:502:502) (596:596:596)) + (PORT datac (867:867:867) (1031:1031:1031)) + (PORT datad (704:704:704) (838:838:838)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58016,12 +60956,60 @@ (INSTANCE sdram_\|r\.bank\[0\]\~9) (DELAY (ABSOLUTE - (PORT dataa (727:727:727) (865:865:865)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (893:893:893) (1059:1059:1059)) + (PORT datab (480:480:480) (555:555:555)) + (PORT datac (1019:1019:1019) (1200:1200:1200)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (875:875:875)) + (PORT datab (890:890:890) (1040:1040:1040)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (1060:1060:1060)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (1019:1019:1019) (1200:1200:1200)) + (PORT datad (742:742:742) (887:887:887)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (889:889:889) (1039:1039:1039)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (193:193:193)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -58033,8 +61021,8 @@ (DELAY (ABSOLUTE (PORT clk (895:895:895) (920:920:920)) - (PORT d (980:980:980) (1073:1073:1073)) - (PORT ena (941:941:941) (1026:1026:1026)) + (PORT d (1172:1172:1172) (1307:1307:1307)) + (PORT ena (780:780:780) (866:866:866)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -58050,11 +61038,11 @@ (INSTANCE sdram_\|Mux25\~4) (DELAY (ABSOLUTE - (PORT dataa (1316:1316:1316) (1556:1556:1556)) - (PORT datab (804:804:804) (945:945:945)) - (PORT datad (508:508:508) (576:576:576)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (429:429:429) (506:506:506)) + (PORT datab (1081:1081:1081) (1226:1226:1226)) + (PORT datad (1212:1212:1212) (1423:1423:1423)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58065,8 +61053,8 @@ (DELAY (ABSOLUTE (PORT clk (896:896:896) (921:921:921)) - (PORT d (1315:1315:1315) (1459:1459:1459)) - (PORT ena (852:852:852) (930:930:930)) + (PORT d (1026:1026:1026) (1140:1140:1140)) + (PORT ena (781:781:781) (867:867:867)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -58079,74 +61067,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~5) + (INSTANCE sdram_\|Mux71\~6) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (733:733:733)) - (PORT datab (568:568:568) (679:679:679)) - (PORT datac (632:632:632) (733:733:733)) - (PORT datad (556:556:556) (655:655:655)) + (PORT dataa (897:897:897) (1069:1069:1069)) + (PORT datab (642:642:642) (776:776:776)) + (PORT datac (588:588:588) (697:697:697)) + (PORT datad (610:610:610) (737:737:737)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~0) - (DELAY - (ABSOLUTE - (PORT datab (793:793:793) (945:945:945)) - (PORT datac (870:870:870) (1025:1025:1025)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~7) - (DELAY - (ABSOLUTE - (PORT datab (975:975:975) (1160:1160:1160)) - (PORT datac (120:120:120) (162:162:162)) - (PORT datad (1486:1486:1486) (1744:1744:1744)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (460:460:460)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~1) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (871:871:871)) - (PORT datab (816:816:816) (951:951:951)) - (PORT datac (872:872:872) (1027:1027:1027)) - (PORT datad (774:774:774) (921:921:921)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58156,13 +61086,9 @@ (INSTANCE sdram_\|Mux71\~2) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (870:870:870)) - (PORT datab (576:576:576) (687:687:687)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (97:97:97) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (622:622:622) (754:754:754)) + (PORT datad (873:873:873) (1039:1039:1039)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58172,12 +61098,41 @@ (INSTANCE sdram_\|Mux71\~3) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (694:694:694)) + (PORT dataa (709:709:709) (845:845:845)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (610:610:610) (736:736:736)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (836:836:836)) + (PORT datad (843:843:843) (983:983:983)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (469:469:469)) (PORT datab (113:113:113) (145:145:145)) - (PORT datac (594:594:594) (707:707:707)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (254:254:254) (288:288:288)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -58188,10 +61143,42 @@ (INSTANCE sdram_\|Mux71\~4) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (565:565:565) (666:666:666)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (330:330:330) (392:392:392)) + (PORT datad (696:696:696) (820:820:820)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~8) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (313:313:313)) + (PORT datab (491:491:491) (575:575:575)) + (PORT datac (589:589:589) (699:699:699)) + (PORT datad (329:329:329) (396:396:396)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~5) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (625:625:625) (760:760:760)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (98:98:98) (118:118:118)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -58205,7 +61192,7 @@ (DELAY (ABSOLUTE (PORT clk (894:894:894) (918:918:918)) - (PORT d (815:815:815) (883:883:883)) + (PORT d (829:829:829) (912:912:912)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -58220,7 +61207,7 @@ (DELAY (ABSOLUTE (PORT clk (894:894:894) (918:918:918)) - (PORT d (808:808:808) (875:875:875)) + (PORT d (829:829:829) (912:912:912)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -58231,41 +61218,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~10) + (INSTANCE sdram_\|n\~6) (DELAY (ABSOLUTE - (PORT datac (864:864:864) (1018:1018:1018)) - (PORT datad (564:564:564) (666:666:666)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~3) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (230:230:230)) - (PORT datab (830:830:830) (968:968:968)) - (PORT datac (769:769:769) (913:913:913)) - (PORT datad (182:182:182) (209:209:209)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~5) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (296:296:296)) - (PORT datab (383:383:383) (471:471:471)) - (PORT datac (304:304:304) (356:356:356)) - (PORT datad (157:157:157) (201:201:201)) + (PORT dataa (509:509:509) (610:610:610)) + (PORT datab (556:556:556) (665:665:665)) + (PORT datac (484:484:484) (564:564:564)) + (PORT datad (549:549:549) (664:664:664)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -58275,15 +61234,169 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~4) + (INSTANCE sdram_\|Mux9\~0) (DELAY (ABSOLUTE - (PORT dataa (174:174:174) (216:216:216)) - (PORT datab (757:757:757) (892:892:892)) - (PORT datac (467:467:467) (531:531:531)) - (PORT datad (812:812:812) (945:945:945)) + (PORT dataa (372:372:372) (437:437:437)) + (PORT datab (430:430:430) (527:527:527)) + (PORT datac (423:423:423) (518:518:518)) + (PORT datad (467:467:467) (547:547:547)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~6) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (413:413:413)) + (PORT datab (515:515:515) (608:608:608)) + (PORT datac (423:423:423) (519:519:519)) + (PORT datad (350:350:350) (409:409:409)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~7) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (522:522:522)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (468:468:468) (553:553:553)) + (PORT datad (413:413:413) (504:504:504)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datac (424:424:424) (520:520:520)) + (PORT datad (410:410:410) (501:501:501)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (216:216:216)) + (PORT datab (228:228:228) (286:286:286)) + (PORT datac (213:213:213) (264:264:264)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (232:232:232)) + (PORT datab (227:227:227) (281:281:281)) + (PORT datac (211:211:211) (263:263:263)) + (PORT datad (197:197:197) (240:240:240)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (275:275:275)) + (PORT datac (212:212:212) (264:264:264)) + (PORT datad (146:146:146) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (210:210:210) (262:262:262)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (289:289:289)) + (PORT datab (226:226:226) (283:283:283)) + (PORT datac (201:201:201) (248:248:248)) + (PORT datad (143:143:143) (187:187:187)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (273:273:273)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (102:102:102) (122:122:122)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (412:412:412)) + (PORT datab (430:430:430) (528:528:528)) + (PORT datac (422:422:422) (517:517:517)) + (PORT datad (413:413:413) (494:494:494)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -58294,27 +61407,11 @@ (INSTANCE sdram_\|Mux9\~2) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (942:942:942)) - (PORT datab (757:757:757) (891:891:891)) - (PORT datac (465:465:465) (530:530:530)) - (PORT datad (693:693:693) (810:810:810)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (521:521:521)) - (PORT datab (161:161:161) (216:216:216)) - (PORT datac (352:352:352) (414:414:414)) - (PORT datad (415:415:415) (498:498:498)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (181:181:181) (220:220:220)) + (PORT datab (352:352:352) (420:420:420)) + (PORT datac (342:342:342) (392:392:392)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -58323,122 +61420,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~2) - (DELAY - (ABSOLUTE - (PORT datab (233:233:233) (291:291:291)) - (PORT datac (218:218:218) (272:272:272)) - (PORT datad (310:310:310) (366:366:366)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~3) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (281:281:281)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (224:224:224) (272:272:272)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (282:282:282)) - (PORT datab (234:234:234) (292:292:292)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (216:216:216) (266:266:266)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~4) + (INSTANCE sdram_\|Mux9\~3) (DELAY (ABSOLUTE (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (224:224:224) (279:279:279)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (376:376:376) (452:452:452)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~5) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (932:932:932)) - (PORT datab (910:910:910) (1069:1069:1069)) - (PORT datac (739:739:739) (873:873:873)) - (PORT datad (174:174:174) (204:204:204)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (501:501:501) (589:589:589)) + (PORT datad (89:89:89) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~0) - (DELAY - (ABSOLUTE - (PORT datab (758:758:758) (892:892:892)) - (PORT datad (892:892:892) (1045:1045:1045)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~7) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (702:702:702) (824:824:824)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58448,8 +61439,8 @@ (INSTANCE sdram_\|r\.state\[2\]) (DELAY (ABSOLUTE - (PORT clk (889:889:889) (911:911:911)) - (PORT d (814:814:814) (895:895:895)) + (PORT clk (883:883:883) (902:902:902)) + (PORT d (892:892:892) (984:984:984)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -58460,48 +61451,80 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~11) + (INSTANCE sdram_\|Mux10\~6) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (675:675:675)) - (PORT datab (567:567:567) (678:678:678)) - (PORT datac (632:632:632) (734:734:734)) - (PORT datad (558:558:558) (657:657:657)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (750:750:750) (900:900:900)) + (PORT datab (530:530:530) (633:633:633)) + (PORT datac (590:590:590) (710:710:710)) + (PORT datad (694:694:694) (819:819:819)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~6) + (INSTANCE sdram_\|Mux10\~10) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (731:731:731)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (590:590:590) (671:671:671)) - (PORT datad (555:555:555) (657:657:657)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (897:897:897) (1068:1068:1068)) + (PORT datab (626:626:626) (763:763:763)) + (PORT datac (335:335:335) (390:390:390)) + (PORT datad (340:340:340) (395:395:395)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (900:900:900)) + (PORT datab (490:490:490) (590:590:590)) + (PORT datac (566:566:566) (675:675:675)) + (PORT datad (694:694:694) (819:819:819)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (899:899:899)) + (PORT datab (488:488:488) (588:588:588)) + (PORT datac (565:565:565) (674:674:674)) + (PORT datad (690:690:690) (815:815:815)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux10\~5) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (870:870:870)) - (PORT datab (793:793:793) (945:945:945)) - (PORT datac (542:542:542) (650:650:650)) - (PORT datad (342:342:342) (402:402:402)) + (PORT dataa (608:608:608) (727:727:727)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (635:635:635) (732:732:732)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58511,13 +61534,45 @@ (INSTANCE sdram_\|Mux10\~7) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (732:732:732)) - (PORT datab (794:794:794) (947:947:947)) - (PORT datac (544:544:544) (653:653:653)) - (PORT datad (556:556:556) (657:657:657)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (533:533:533) (645:645:645)) + (PORT datab (547:547:547) (662:662:662)) + (PORT datac (586:586:586) (705:705:705)) + (PORT datad (691:691:691) (815:815:815)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (719:719:719)) + (PORT datab (535:535:535) (627:627:627)) + (PORT datac (328:328:328) (380:380:380)) + (PORT datad (337:337:337) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~12) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (717:717:717)) + (PORT datab (624:624:624) (760:760:760)) + (PORT datac (331:331:331) (393:393:393)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58527,40 +61582,24 @@ (INSTANCE sdram_\|Mux10\~8) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (577:577:577) (688:688:688)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (94:94:94) (113:113:113)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (627:627:627) (764:764:764)) + (PORT datac (340:340:340) (394:394:394)) + (PORT datad (93:93:93) (111:111:111)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~9) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.state\[1\]) (DELAY (ABSOLUTE - (PORT clk (889:889:889) (911:911:911)) - (PORT d (700:700:700) (771:771:771)) + (PORT clk (883:883:883) (902:902:902)) + (PORT d (711:711:711) (782:782:782)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -58599,16 +61638,50 @@ (HOLD d (posedge clk) (57:57:57)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (812:812:812)) + (PORT datab (591:591:591) (715:715:715)) + (PORT datac (682:682:682) (816:816:816)) + (PORT datad (724:724:724) (855:855:855)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (406:406:406)) + (PORT datab (612:612:612) (731:731:731)) + (PORT datac (683:683:683) (818:818:818)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux11\~2) (DELAY (ABSOLUTE - (PORT dataa (420:420:420) (511:511:511)) - (PORT datab (430:430:430) (521:521:521)) - (PORT datad (153:153:153) (198:198:198)) + (PORT dataa (308:308:308) (361:361:361)) + (PORT datab (606:606:606) (721:721:721)) + (PORT datac (321:321:321) (371:371:371)) + (PORT datad (600:600:600) (713:713:713)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58618,29 +61691,13 @@ (INSTANCE sdram_\|Mux11\~3) (DELAY (ABSOLUTE - (PORT dataa (857:857:857) (1002:1002:1002)) - (PORT datab (362:362:362) (427:427:427)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (793:793:793) (918:918:918)) + (PORT dataa (741:741:741) (885:885:885)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (1012:1012:1012) (1190:1190:1190)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~4) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (936:936:936)) - (PORT datab (758:758:758) (893:893:893)) - (PORT datac (344:344:344) (400:400:400)) - (PORT datad (166:166:166) (196:196:196)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58650,12 +61707,12 @@ (INSTANCE sdram_\|Mux11\~5) (DELAY (ABSOLUTE - (PORT dataa (784:784:784) (935:935:935)) - (PORT datab (758:758:758) (893:893:893)) - (PORT datac (877:877:877) (1031:1031:1031)) - (PORT datad (698:698:698) (815:815:815)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (191:191:191) (188:188:188)) + (PORT dataa (710:710:710) (846:846:846)) + (PORT datab (593:593:593) (717:717:717)) + (PORT datac (497:497:497) (590:590:590)) + (PORT datad (595:595:595) (709:709:709)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -58666,13 +61723,13 @@ (INSTANCE sdram_\|Mux11\~6) (DELAY (ABSOLUTE - (PORT dataa (563:563:563) (678:678:678)) - (PORT datab (579:579:579) (691:691:691)) - (PORT datac (597:597:597) (711:711:711)) - (PORT datad (558:558:558) (660:660:660)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (173:173:173) (214:214:214)) + (PORT datab (498:498:498) (583:583:583)) + (PORT datac (535:535:535) (643:643:643)) + (PORT datad (548:548:548) (664:664:664)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58682,42 +61739,10 @@ (INSTANCE sdram_\|Mux11\~7) (DELAY (ABSOLUTE - (PORT dataa (497:497:497) (588:588:588)) - (PORT datab (454:454:454) (556:556:556)) - (PORT datac (437:437:437) (538:538:538)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~9) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (932:932:932)) - (PORT datab (700:700:700) (822:822:822)) - (PORT datac (468:468:468) (533:533:533)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~8) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (315:315:315) (363:363:363)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (434:434:434) (497:497:497)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -58731,7 +61756,7 @@ (DELAY (ABSOLUTE (PORT clk (887:887:887) (907:907:907)) - (PORT d (1006:1006:1006) (1123:1123:1123)) + (PORT d (872:872:872) (963:963:963)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -58742,31 +61767,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~2) + (INSTANCE sdram_\|Mux24\~5) (DELAY (ABSOLUTE - (PORT dataa (418:418:418) (512:512:512)) - (PORT datab (410:410:410) (505:505:505)) - (PORT datac (431:431:431) (526:526:526)) - (PORT datad (458:458:458) (534:534:534)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (2049:2049:2049)) - (PORT datab (318:318:318) (383:383:383)) - (PORT datac (588:588:588) (703:703:703)) - (PORT datad (341:341:341) (404:404:404)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (663:663:663) (766:766:766)) + (PORT datab (363:363:363) (436:436:436)) + (PORT datac (538:538:538) (627:627:627)) + (PORT datad (352:352:352) (407:407:407)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -58774,31 +61783,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~0) + (INSTANCE sdram_\|Mux24\~6) (DELAY (ABSOLUTE - (PORT dataa (323:323:323) (369:369:369)) - (PORT datab (539:539:539) (641:641:641)) - (PORT datad (90:90:90) (108:108:108)) + (PORT dataa (179:179:179) (218:218:218)) + (PORT datab (363:363:363) (436:436:436)) + (PORT datac (729:729:729) (861:861:861)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~9) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (935:935:935)) - (PORT datab (703:703:703) (826:826:826)) - (PORT datac (878:878:878) (1032:1032:1032)) - (PORT datad (810:810:810) (943:943:943)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58808,10 +61802,10 @@ (INSTANCE sdram_\|Mux13\~4) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (943:943:943)) - (PORT datab (696:696:696) (817:817:817)) - (PORT datac (868:868:868) (1022:1022:1022)) - (PORT datad (813:813:813) (946:946:946)) + (PORT dataa (1033:1033:1033) (1216:1216:1216)) + (PORT datab (604:604:604) (719:719:719)) + (PORT datac (565:565:565) (673:673:673)) + (PORT datad (600:600:600) (712:712:712)) (IOPATH dataa combout (181:181:181) (184:184:184)) (IOPATH datab combout (182:182:182) (188:188:188)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -58819,16 +61813,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1216:1216:1216)) + (PORT datab (605:605:605) (721:721:721)) + (PORT datac (564:564:564) (672:672:672)) + (PORT datad (600:600:600) (713:713:713)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux13\~5) (DELAY (ABSOLUTE - (PORT datab (757:757:757) (891:891:891)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datac (724:724:724) (860:860:860)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58838,11 +61848,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (925:925:925)) + (PORT clk (912:912:912) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (271:271:271) (292:292:292)) - (PORT sload (872:872:872) (996:996:996)) - (PORT ena (663:663:663) (715:715:715)) + (PORT asdata (477:477:477) (521:521:521)) + (PORT sload (1062:1062:1062) (1218:1218:1218)) + (PORT ena (671:671:671) (726:726:726)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -58853,18 +61863,30 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (544:544:544)) + (PORT datab (460:460:460) (534:534:534)) + (PORT datac (342:342:342) (415:415:415)) + (PORT datad (1014:1014:1014) (1188:1188:1188)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux24\~3) (DELAY (ABSOLUTE - (PORT dataa (1761:1761:1761) (2049:2049:2049)) - (PORT datab (318:318:318) (384:384:384)) - (PORT datac (193:193:193) (231:231:231)) - (PORT datad (341:341:341) (403:403:403)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (254:254:254) (319:319:319)) + (PORT datad (754:754:754) (896:896:896)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58874,13 +61896,27 @@ (INSTANCE sdram_\|Mux24\~4) (DELAY (ABSOLUTE - (PORT dataa (490:490:490) (571:571:571)) - (PORT datab (320:320:320) (385:385:385)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (603:603:603) (700:700:700)) + (PORT dataa (383:383:383) (469:469:469)) + (PORT datab (362:362:362) (436:436:436)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (266:266:266) (302:302:302)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (400:400:400)) + (PORT datab (913:913:913) (1073:1073:1073)) + (PORT datad (165:165:165) (195:195:195)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58890,11 +61926,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (576:576:576) (685:685:685)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (749:749:749) (889:889:889)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58905,8 +61941,8 @@ (DELAY (ABSOLUTE (PORT clk (890:890:890) (910:910:910)) - (PORT d (1122:1122:1122) (1241:1241:1241)) - (PORT ena (905:905:905) (1003:1003:1003)) + (PORT d (936:936:936) (1030:1030:1030)) + (PORT ena (1032:1032:1032) (1151:1151:1151)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -58919,24 +61955,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (INSTANCE sdram_\|Mux23\~1) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) + (PORT dataa (949:949:949) (1127:1127:1127)) + (PORT datab (381:381:381) (449:449:449)) + (PORT datac (440:440:440) (502:502:502)) + (PORT datad (766:766:766) (903:903:903)) (IOPATH dataa combout (170:170:170) (163:163:163)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~4) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (676:676:676)) - (PORT datab (135:135:135) (184:184:184)) - (PORT datac (716:716:716) (840:840:840)) - (PORT datad (173:173:173) (205:205:205)) - (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -58945,14 +61971,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal5\~0) + (INSTANCE sdram_\|r\.address\[1\]\~8) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (515:515:515)) - (PORT datab (430:430:430) (521:521:521)) - (PORT datac (348:348:348) (409:409:409)) - (PORT datad (151:151:151) (196:196:196)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (949:949:949) (1127:1127:1127)) + (PORT datab (782:782:782) (930:930:930)) + (PORT datad (447:447:447) (512:512:512)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (840:840:840)) + (PORT datab (691:691:691) (813:813:813)) + (PORT datad (751:751:751) (892:892:892)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1127:1127:1127)) + (PORT datab (779:779:779) (926:926:926)) + (PORT datac (503:503:503) (592:592:592)) + (PORT datad (870:870:870) (1012:1012:1012)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -58961,14 +62015,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~5) + (INSTANCE sdram_\|r\.address\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (564:564:564) (678:678:678)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (539:539:539) (633:633:633)) - (PORT datad (482:482:482) (551:551:551)) - (IOPATH dataa combout (170:170:170) (165:165:165)) + (PORT datab (884:884:884) (1035:1035:1035)) + (PORT datac (305:305:305) (350:350:350)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (181:181:181) (175:175:175)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -58977,16 +62045,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~6) + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (565:565:565) (680:680:680)) - (PORT datab (609:609:609) (728:728:728)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (471:471:471) (531:531:531)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (501:501:501) (569:569:569)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -58996,13 +62058,13 @@ (INSTANCE sdram_\|Mux19\~0) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (823:823:823)) - (PORT datab (596:596:596) (708:708:708)) - (PORT datac (709:709:709) (838:838:838)) - (PORT datad (540:540:540) (634:634:634)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (740:740:740) (883:883:883)) + (PORT datab (591:591:591) (700:700:700)) + (PORT datac (671:671:671) (789:789:789)) + (PORT datad (595:595:595) (705:705:705)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59012,11 +62074,11 @@ (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) + (PORT clk (916:916:916) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (272:272:272) (294:294:294)) - (PORT sload (997:997:997) (899:899:899)) - (PORT ena (676:676:676) (745:745:745)) + (PORT asdata (753:753:753) (825:825:825)) + (PORT sload (1310:1310:1310) (1177:1177:1177)) + (PORT ena (645:645:645) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -59027,31 +62089,17 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~2) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (881:881:881)) - (PORT datab (186:186:186) (228:228:228)) - (PORT datac (538:538:538) (632:632:632)) - (PORT datad (540:540:540) (641:641:641)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux23\~3) (DELAY (ABSOLUTE - (PORT dataa (740:740:740) (882:882:882)) - (PORT datac (269:269:269) (311:311:311)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT dataa (786:786:786) (920:920:920)) + (PORT datab (371:371:371) (434:434:434)) + (PORT datac (514:514:514) (610:610:610)) + (PORT datad (1029:1029:1029) (1205:1205:1205)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59059,45 +62107,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~1) + (INSTANCE sdram_\|Mux23\~4) (DELAY (ABSOLUTE - (PORT dataa (735:735:735) (877:877:877)) - (PORT datab (1478:1478:1478) (1732:1732:1732)) - (PORT datac (939:939:939) (1097:1097:1097)) - (PORT datad (543:543:543) (645:645:645)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (355:355:355) (423:423:423)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (770:770:770) (894:894:894)) + (PORT datad (591:591:591) (709:709:709)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (732:732:732)) + (PORT datab (492:492:492) (579:579:579)) + (PORT datac (402:402:402) (490:490:490)) + (PORT datad (498:498:498) (588:588:588)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~5) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (917:917:917)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (591:591:591) (709:709:709)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (568:568:568) (682:682:682)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (357:357:357) (424:424:424)) + (PORT datac (726:726:726) (863:863:863)) + (PORT datad (342:342:342) (391:391:391)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -59107,8 +62173,8 @@ (DELAY (ABSOLUTE (PORT clk (897:897:897) (921:921:921)) - (PORT d (820:820:820) (903:903:903)) - (PORT ena (1041:1041:1041) (1145:1145:1145)) + (PORT d (978:978:978) (1076:1076:1076)) + (PORT ena (1185:1185:1185) (1318:1318:1318)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59121,28 +62187,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~8) + (INSTANCE sdram_\|r\.address\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (731:731:731) (872:872:872)) - (PORT datab (557:557:557) (657:657:657)) - (PORT datac (568:568:568) (681:681:681)) - (PORT datad (547:547:547) (649:649:649)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (897:897:897) (1068:1068:1068)) + (PORT datab (626:626:626) (762:762:762)) + (PORT datac (588:588:588) (698:698:698)) + (PORT datad (664:664:664) (775:775:775)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~9) + (INSTANCE sdram_\|r\.address\[3\]\~12) (DELAY (ABSOLUTE - (PORT datab (556:556:556) (656:656:656)) - (PORT datad (722:722:722) (853:853:853)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT datac (572:572:572) (680:680:680)) + (PORT datad (595:595:595) (705:705:705)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59152,11 +62218,11 @@ (INSTANCE sdram_\|Mux21\~0) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (161:161:161)) - (PORT datab (605:605:605) (723:723:723)) - (PORT datac (160:160:160) (187:187:187)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (488:488:488) (564:564:564)) + (PORT datab (712:712:712) (833:833:833)) + (PORT datac (532:532:532) (611:611:611)) + (PORT datad (492:492:492) (566:566:566)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59168,90 +62234,26 @@ (INSTANCE sdram_\|Mux22\~0) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (439:439:439)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (475:475:475) (537:537:537)) - (PORT datad (336:336:336) (391:391:391)) + (PORT dataa (881:881:881) (1021:1021:1021)) + (PORT datab (630:630:630) (723:723:723)) + (PORT datac (102:102:102) (124:124:124)) + (PORT datad (481:481:481) (549:549:549)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1027:1027:1027) (1206:1206:1206)) - (PORT datab (574:574:574) (686:686:686)) - (PORT datac (437:437:437) (537:537:537)) - (PORT datad (435:435:435) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (455:455:455) (557:557:557)) - (PORT datac (1035:1035:1035) (1216:1216:1216)) - (PORT datad (561:561:561) (662:662:662)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (580:580:580)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (1034:1034:1034) (1216:1216:1216)) - (PORT datad (677:677:677) (792:792:792)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (864:864:864)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (768:768:768) (886:886:886)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1027:1027:1027) (1205:1205:1205)) - (PORT datab (575:575:575) (686:686:686)) - (PORT datac (436:436:436) (537:537:537)) - (PORT datad (436:436:436) (532:532:532)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (746:746:746) (894:894:894)) + (PORT datac (535:535:535) (643:643:643)) + (PORT datad (578:578:578) (692:692:692)) + (IOPATH datab combout (188:188:188) (181:181:181)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59262,12 +62264,28 @@ (INSTANCE sdram_\|r\.address\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (495:495:495) (586:586:586)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (768:768:768) (885:885:885)) - (PORT datad (561:561:561) (662:662:662)) + (PORT dataa (704:704:704) (838:838:838)) + (PORT datab (748:748:748) (895:895:895)) + (PORT datac (485:485:485) (565:565:565)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (691:691:691)) + (PORT datab (593:593:593) (717:717:717)) + (PORT datac (534:534:534) (642:642:642)) + (PORT datad (723:723:723) (855:855:855)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59278,12 +62296,12 @@ (INSTANCE sdram_\|r\.address\[3\]\~16) (DELAY (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (672:672:672) (787:787:787)) + (PORT dataa (704:704:704) (839:839:839)) + (PORT datab (699:699:699) (829:829:829)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (196:196:196) (192:192:192)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59294,11 +62312,59 @@ (INSTANCE sdram_\|r\.address\[3\]\~17) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datac (569:569:569) (673:673:673)) + (PORT dataa (772:772:772) (924:924:924)) + (PORT datab (503:503:503) (598:598:598)) + (PORT datac (709:709:709) (842:842:842)) + (PORT datad (886:886:886) (1037:1037:1037)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (919:919:919)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (869:869:869) (1034:1034:1034)) + (PORT datad (461:461:461) (530:530:530)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (889:889:889) (1039:1039:1039)) + (PORT datac (429:429:429) (489:489:489)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (872:872:872)) + (PORT datac (339:339:339) (392:392:392)) (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59309,8 +62375,8 @@ (DELAY (ABSOLUTE (PORT clk (897:897:897) (921:921:921)) - (PORT d (1029:1029:1029) (1142:1142:1142)) - (PORT ena (998:998:998) (1091:1091:1091)) + (PORT d (915:915:915) (1016:1016:1016)) + (PORT ena (939:939:939) (1038:1038:1038)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59326,12 +62392,12 @@ (INSTANCE sdram_\|Mux21\~1) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (439:439:439)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (339:339:339) (395:395:395)) + (PORT dataa (880:880:880) (1020:1020:1020)) + (PORT datab (814:814:814) (930:930:930)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (481:481:481) (550:550:550)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59343,8 +62409,8 @@ (DELAY (ABSOLUTE (PORT clk (896:896:896) (921:921:921)) - (PORT d (863:863:863) (948:948:948)) - (PORT ena (873:873:873) (946:946:946)) + (PORT d (681:681:681) (735:735:735)) + (PORT ena (846:846:846) (919:919:919)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59357,45 +62423,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~4) + (INSTANCE sdram_\|Mux24\~7) (DELAY (ABSOLUTE - (PORT dataa (425:425:425) (517:517:517)) - (PORT datab (430:430:430) (521:521:521)) - (PORT datad (149:149:149) (194:194:194)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~7) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (665:665:665)) - (PORT datab (1501:1501:1501) (1765:1765:1765)) - (PORT datac (963:963:963) (1143:1143:1143)) - (PORT datad (513:513:513) (599:599:599)) - (IOPATH dataa combout (158:158:158) (173:173:173)) + (PORT dataa (511:511:511) (606:606:606)) + (PORT datab (430:430:430) (528:528:528)) + (PORT datac (495:495:495) (593:593:593)) + (PORT datad (619:619:619) (742:742:742)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~7) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (556:556:556)) - (PORT datab (479:479:479) (561:561:561)) - (PORT datac (715:715:715) (855:855:855)) - (PORT datad (436:436:436) (506:506:506)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59403,14 +62439,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~8) + (INSTANCE sdram_\|Mux20\~4) (DELAY (ABSOLUTE - (PORT dataa (576:576:576) (684:684:684)) - (PORT datab (518:518:518) (601:601:601)) - (PORT datac (710:710:710) (839:839:839)) - (PORT datad (680:680:680) (795:795:795)) - (IOPATH dataa combout (188:188:188) (193:193:193)) + (PORT dataa (1090:1090:1090) (1289:1289:1289)) + (PORT datab (334:334:334) (389:389:389)) + (PORT datac (912:912:912) (1076:1076:1076)) + (PORT datad (126:126:126) (167:167:167)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59419,14 +62455,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~10) + (INSTANCE sdram_\|Mux20\~2) (DELAY (ABSOLUTE - (PORT dataa (698:698:698) (827:827:827)) - (PORT datab (353:353:353) (423:423:423)) - (PORT datac (304:304:304) (347:347:347)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (181:181:181) (180:180:180)) + (PORT dataa (949:949:949) (1127:1127:1127)) + (PORT datab (139:139:139) (190:190:190)) + (PORT datac (625:625:625) (714:714:714)) + (PORT datad (363:363:363) (424:424:424)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59435,15 +62471,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~9) + (INSTANCE sdram_\|Mux20\~3) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (823:823:823)) - (PORT datab (357:357:357) (428:428:428)) - (PORT datac (302:302:302) (344:344:344)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (186:186:186) (179:179:179)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (949:949:949) (1127:1127:1127)) + (PORT datac (473:473:473) (539:539:539)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59451,16 +62485,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~11) + (INSTANCE sdram_\|r\.address\[4\]\~2) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (280:280:280)) - (PORT datab (494:494:494) (580:580:580)) - (PORT datac (160:160:160) (193:193:193)) + (PORT datab (883:883:883) (1033:1033:1033)) + (PORT datac (90:90:90) (111:111:111)) (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (95:95:95) (114:114:114)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59470,11 +62512,11 @@ (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (926:926:926)) + (PORT clk (912:912:912) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (354:354:354) (379:379:379)) - (PORT sload (893:893:893) (1021:1021:1021)) - (PORT ena (503:503:503) (534:534:534)) + (PORT asdata (271:271:271) (292:292:292)) + (PORT sload (1199:1199:1199) (1379:1379:1379)) + (PORT ena (780:780:780) (855:855:855)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -59487,32 +62529,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~12) + (INSTANCE sdram_\|Mux20\~5) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (483:483:483)) - (PORT datab (1165:1165:1165) (1369:1369:1369)) - (PORT datac (1285:1285:1285) (1515:1515:1515)) - (PORT datad (488:488:488) (560:560:560)) + (PORT dataa (684:684:684) (805:805:805)) + (PORT datab (716:716:716) (852:852:852)) + (PORT datac (838:838:838) (984:984:984)) + (PORT datad (761:761:761) (898:898:898)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~5) + (INSTANCE sdram_\|Mux20\~10) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (361:361:361) (426:426:426)) - (PORT datac (896:896:896) (1047:1047:1047)) - (PORT datad (89:89:89) (107:107:107)) + (PORT dataa (684:684:684) (805:805:805)) + (PORT datab (883:883:883) (1033:1033:1033)) + (PORT datac (839:839:839) (985:985:985)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59522,27 +62564,57 @@ (INSTANCE sdram_\|Mux20\~6) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (387:387:387)) - (PORT datab (495:495:495) (580:580:580)) - (PORT datac (553:553:553) (660:660:660)) - (PORT datad (200:200:200) (253:253:253)) - (IOPATH dataa combout (170:170:170) (165:165:165)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (238:238:238) (303:303:303)) + (PORT datad (374:374:374) (448:448:448)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[4\]\~2) + (INSTANCE sdram_\|Mux20\~7) (DELAY (ABSOLUTE - (PORT dataa (695:695:695) (824:824:824)) - (PORT datab (339:339:339) (400:400:400)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (166:166:166) (159:159:159)) + (PORT dataa (948:948:948) (1126:1126:1126)) + (PORT datab (773:773:773) (920:920:920)) + (PORT datac (190:190:190) (223:223:223)) + (PORT datad (868:868:868) (1010:1010:1010)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (870:870:870) (1012:1012:1012)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (190:190:190)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59552,10 +62624,10 @@ (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (596:596:596) (709:709:709)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (907:907:907) (1068:1068:1068)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59567,8 +62639,8 @@ (DELAY (ABSOLUTE (PORT clk (898:898:898) (922:922:922)) - (PORT d (933:933:933) (1008:1008:1008)) - (PORT ena (1262:1262:1262) (1417:1417:1417)) + (PORT d (911:911:911) (983:983:983)) + (PORT ena (1459:1459:1459) (1603:1603:1603)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59581,15 +62653,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~1) + (INSTANCE sdram_\|Mux19\~4) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (519:519:519)) - (PORT datab (430:430:430) (521:521:521)) - (PORT datac (351:351:351) (412:412:412)) - (PORT datad (148:148:148) (193:193:193)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (117:117:117) (149:149:149)) + (PORT datac (325:325:325) (372:372:372)) + (PORT datad (850:850:850) (988:988:988)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59597,13 +62667,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~4) + (INSTANCE sdram_\|Mux19\~6) (DELAY (ABSOLUTE - (PORT dataa (696:696:696) (825:825:825)) - (PORT datac (303:303:303) (346:346:346)) - (PORT datad (316:316:316) (369:369:369)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (806:806:806) (971:971:971)) + (PORT datab (916:916:916) (1076:1076:1076)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (769:769:769) (914:914:914)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59614,28 +62686,12 @@ (INSTANCE sdram_\|Mux19\~5) (DELAY (ABSOLUTE - (PORT dataa (699:699:699) (828:828:828)) - (PORT datab (584:584:584) (699:699:699)) - (PORT datac (711:711:711) (840:840:840)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~6) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (828:828:828)) - (PORT datab (584:584:584) (700:700:700)) - (PORT datac (711:711:711) (840:840:840)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (801:801:801) (964:964:964)) + (PORT datab (911:911:911) (1071:1071:1071)) + (PORT datac (180:180:180) (219:219:219)) + (PORT datad (768:768:768) (913:913:913)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -59646,11 +62702,11 @@ (INSTANCE sdram_\|Mux19\~7) (DELAY (ABSOLUTE - (PORT dataa (770:770:770) (881:881:881)) - (PORT datab (213:213:213) (274:274:274)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (213:213:213) (271:271:271)) (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datad (776:776:776) (889:889:889)) + (IOPATH dataa combout (181:181:181) (193:193:193)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59662,11 +62718,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (926:926:926)) + (PORT clk (912:912:912) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (273:273:273) (295:295:295)) - (PORT sload (893:893:893) (1021:1021:1021)) - (PORT ena (503:503:503) (534:534:534)) + (PORT asdata (351:351:351) (381:381:381)) + (PORT sload (1062:1062:1062) (1218:1218:1218)) + (PORT ena (805:805:805) (897:897:897)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -59677,18 +62733,34 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (412:412:412)) + (PORT datab (655:655:655) (766:766:766)) + (PORT datac (198:198:198) (250:250:250)) + (PORT datad (768:768:768) (913:913:913)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~2) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (500:500:500) (582:582:582)) - (PORT datac (893:893:893) (1044:1044:1044)) - (PORT datad (352:352:352) (422:422:422)) + (PORT dataa (507:507:507) (611:611:611)) + (PORT datab (647:647:647) (788:788:788)) + (PORT datac (412:412:412) (510:510:510)) + (PORT datad (616:616:616) (738:738:738)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59698,13 +62770,13 @@ (INSTANCE sdram_\|Mux19\~3) (DELAY (ABSOLUTE - (PORT dataa (337:337:337) (386:386:386)) - (PORT datab (587:587:587) (703:703:703)) - (PORT datac (755:755:755) (858:858:858)) - (PORT datad (201:201:201) (253:253:253)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (324:324:324) (377:377:377)) + (PORT datab (212:212:212) (270:270:270)) + (PORT datac (329:329:329) (379:379:379)) + (PORT datad (776:776:776) (889:889:889)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59714,11 +62786,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~3) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (830:830:830)) - (PORT datab (350:350:350) (411:411:411)) - (PORT datad (93:93:93) (110:110:110)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (916:916:916) (1076:1076:1076)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59728,12 +62800,12 @@ (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (134:134:134)) - (PORT datab (597:597:597) (710:710:710)) - (PORT datac (95:95:95) (119:119:119)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (762:762:762) (907:907:907)) + (PORT datad (103:103:103) (121:121:121)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -59743,8 +62815,8 @@ (DELAY (ABSOLUTE (PORT clk (896:896:896) (920:920:920)) - (PORT d (788:788:788) (858:858:858)) - (PORT ena (1184:1184:1184) (1305:1305:1305)) + (PORT d (680:680:680) (742:742:742)) + (PORT ena (1098:1098:1098) (1214:1214:1214)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59760,9 +62832,9 @@ (INSTANCE sdram_\|Mux18\~0) (DELAY (ABSOLUTE - (PORT dataa (1372:1372:1372) (1624:1624:1624)) - (PORT datac (699:699:699) (835:835:835)) - (PORT datad (361:361:361) (414:414:414)) + (PORT dataa (771:771:771) (920:920:920)) + (PORT datac (622:622:622) (739:739:739)) + (PORT datad (858:858:858) (993:993:993)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59775,8 +62847,8 @@ (DELAY (ABSOLUTE (PORT clk (896:896:896) (921:921:921)) - (PORT d (852:852:852) (930:930:930)) - (PORT ena (873:873:873) (946:946:946)) + (PORT d (838:838:838) (906:906:906)) + (PORT ena (846:846:846) (919:919:919)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59789,12 +62861,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux17\~0) + (INSTANCE sdram_\|Mux17\~2) (DELAY (ABSOLUTE - (PORT dataa (1371:1371:1371) (1623:1623:1623)) - (PORT datac (834:834:834) (976:976:976)) - (PORT datad (361:361:361) (414:414:414)) + (PORT dataa (772:772:772) (921:921:921)) + (PORT datac (483:483:483) (574:574:574)) + (PORT datad (858:858:858) (993:993:993)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59807,8 +62879,8 @@ (DELAY (ABSOLUTE (PORT clk (894:894:894) (918:918:918)) - (PORT d (1086:1086:1086) (1203:1203:1203)) - (PORT ena (903:903:903) (1016:1016:1016)) + (PORT d (1080:1080:1080) (1202:1202:1202)) + (PORT ena (986:986:986) (1098:1098:1098)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -59821,12 +62893,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux16\~0) + (INSTANCE sdram_\|Mux16\~2) (DELAY (ABSOLUTE - (PORT dataa (1377:1377:1377) (1630:1630:1630)) - (PORT datac (132:132:132) (175:175:175)) - (PORT datad (362:362:362) (414:414:414)) + (PORT dataa (773:773:773) (922:922:922)) + (PORT datac (624:624:624) (730:730:730)) + (PORT datad (859:859:859) (994:994:994)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -59839,8 +62911,8 @@ (DELAY (ABSOLUTE (PORT clk (889:889:889) (908:908:908)) - (PORT d (1203:1203:1203) (1344:1344:1344)) - (PORT ena (761:761:761) (844:844:844)) + (PORT d (1001:1001:1001) (1113:1113:1113)) + (PORT ena (981:981:981) (1104:1104:1104)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -59856,11 +62928,11 @@ (INSTANCE sdram_\|Mux15\~2) (DELAY (ABSOLUTE - (PORT dataa (1380:1380:1380) (1633:1633:1633)) - (PORT datab (515:515:515) (618:618:618)) - (PORT datad (362:362:362) (415:415:415)) + (PORT dataa (769:769:769) (917:917:917)) + (PORT datac (759:759:759) (888:888:888)) + (PORT datad (856:856:856) (991:991:991)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59871,8 +62943,8 @@ (DELAY (ABSOLUTE (PORT clk (890:890:890) (910:910:910)) - (PORT d (1210:1210:1210) (1359:1359:1359)) - (PORT ena (779:779:779) (872:872:872)) + (PORT d (1134:1134:1134) (1252:1252:1252)) + (PORT ena (978:978:978) (1099:1099:1099)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -59885,79 +62957,23 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~0) + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (374:374:374) (440:440:440)) - (PORT datab (391:391:391) (486:486:486)) - (PORT datac (700:700:700) (829:829:829)) (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~1) + (INSTANCE sdram_\|n\~5) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (436:436:436)) - (PORT datab (213:213:213) (271:271:271)) - (PORT datac (584:584:584) (699:699:699)) - (PORT datad (335:335:335) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[10\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (539:539:539) (641:641:641)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (271:271:271) (292:292:292)) - (PORT sload (872:872:872) (996:996:996)) - (PORT ena (663:663:663) (715:715:715)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~4) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (554:554:554)) - (PORT datab (212:212:212) (269:269:269)) - (PORT datac (370:370:370) (442:442:442)) - (PORT datad (364:364:364) (431:431:431)) + (PORT dataa (509:509:509) (603:603:603)) + (PORT datab (429:429:429) (528:528:528)) + (PORT datac (497:497:497) (595:595:595)) + (PORT datad (212:212:212) (261:261:261)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -59970,13 +62986,13 @@ (INSTANCE sdram_\|Mux14\~2) (DELAY (ABSOLUTE - (PORT dataa (375:375:375) (441:441:441)) - (PORT datab (391:391:391) (486:486:486)) - (PORT datac (701:701:701) (830:830:830)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (517:517:517) (626:626:626)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (104:104:104) (132:132:132)) + (PORT datad (618:618:618) (741:741:741)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -59986,12 +63002,78 @@ (INSTANCE sdram_\|Mux14\~3) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (211:211:211) (268:268:268)) - (PORT datac (194:194:194) (232:232:232)) - (PORT datad (340:340:340) (403:403:403)) + (PORT dataa (356:356:356) (425:425:425)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (162:162:162) (185:185:185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (920:920:920)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (273:273:273) (295:295:295)) + (PORT sload (1042:1042:1042) (1197:1197:1197)) + (PORT ena (433:433:433) (461:461:461)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (356:356:356)) + (PORT datab (145:145:145) (195:195:195)) + (PORT datac (594:594:594) (704:704:704)) + (PORT datad (344:344:344) (400:400:400)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (626:626:626)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (103:103:103) (131:131:131)) + (PORT datad (619:619:619) (742:742:742)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (602:602:602) (716:716:716)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (167:167:167) (195:195:195)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -60002,12 +63084,12 @@ (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (576:576:576) (686:686:686)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (742:742:742) (886:886:886)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (93:93:93) (116:116:116)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -60017,8 +63099,8 @@ (DELAY (ABSOLUTE (PORT clk (882:882:882) (902:902:902)) - (PORT d (804:804:804) (883:883:883)) - (PORT ena (891:891:891) (989:989:989)) + (PORT d (879:879:879) (970:970:970)) + (PORT ena (887:887:887) (996:996:996)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -60031,13 +63113,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~18) + (INSTANCE sdram_\|r\.address\[11\]\~21) (DELAY (ABSOLUTE - (PORT datab (411:411:411) (505:505:505)) - (PORT datac (710:710:710) (849:849:849)) - (PORT datad (397:397:397) (486:486:486)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (801:801:801) (964:964:964)) + (PORT datab (911:911:911) (1071:1071:1071)) + (PORT datac (577:577:577) (665:665:665)) + (PORT datad (360:360:360) (431:431:431)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (913:913:913) (1072:1072:1072)) + (PORT datac (1007:1007:1007) (1173:1173:1173)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -60048,24 +63146,13 @@ (INSTANCE sdram_\|r\.address\[11\]\~5) (DELAY (ABSOLUTE - (PORT dataa (558:558:558) (661:661:661)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (123:123:123) (166:166:166)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (186:186:186) (179:179:179)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (153:153:153)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (916:916:916) (1076:1076:1076)) + (PORT datad (301:301:301) (348:348:348)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -60074,11 +63161,11 @@ (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (924:924:924)) + (PORT clk (912:912:912) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (279:279:279) (304:304:304)) - (PORT sload (708:708:708) (811:811:811)) - (PORT ena (683:683:683) (755:755:755)) + (PORT asdata (451:451:451) (486:486:486)) + (PORT sload (1062:1062:1062) (1218:1218:1218)) + (PORT ena (671:671:671) (726:726:726)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -60094,11 +63181,11 @@ (INSTANCE sdram_\|Mux13\~10) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (PORT datac (435:435:435) (532:532:532)) - (PORT datad (384:384:384) (462:462:462)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (806:806:806) (970:970:970)) + (PORT datac (116:116:116) (158:158:158)) + (PORT datad (895:895:895) (1048:1048:1048)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -60108,13 +63195,13 @@ (INSTANCE sdram_\|Mux13\~6) (DELAY (ABSOLUTE - (PORT dataa (448:448:448) (551:551:551)) - (PORT datab (476:476:476) (558:558:558)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (435:435:435) (504:504:504)) + (PORT dataa (323:323:323) (376:376:376)) + (PORT datab (660:660:660) (772:772:772)) + (PORT datac (787:787:787) (952:952:952)) + (PORT datad (162:162:162) (186:186:186)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -60124,12 +63211,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (151:151:151)) - (PORT datab (410:410:410) (502:502:502)) - (PORT datac (100:100:100) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (746:746:746) (885:885:885)) + (PORT datad (164:164:164) (192:192:192)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -60138,9 +63225,9 @@ (INSTANCE sdram_\|r\.address\[11\]) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (913:913:913)) - (PORT d (701:701:701) (770:770:770)) - (PORT ena (736:736:736) (803:803:803)) + (PORT clk (885:885:885) (904:904:904)) + (PORT d (864:864:864) (960:960:960)) + (PORT ena (1218:1218:1218) (1362:1362:1362)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) @@ -60156,12 +63243,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (116:116:116) (152:152:152)) - (PORT datab (410:410:410) (502:502:502)) - (PORT datac (101:101:101) (129:129:129)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (746:746:746) (885:885:885)) + (PORT datad (164:164:164) (192:192:192)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -60171,8 +63258,8 @@ (DELAY (ABSOLUTE (PORT clk (887:887:887) (907:907:907)) - (PORT d (951:951:951) (1044:1044:1044)) - (PORT ena (909:909:909) (1008:1008:1008)) + (PORT d (990:990:990) (1093:1093:1093)) + (PORT ena (1211:1211:1211) (1355:1355:1355)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index ae6cb77..754b3cf 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -65,6 +65,12 @@ source_file = 1, /home/benny/work/fpga/spectrum/ram_video.v source_file = 1, /home/benny/work/fpga/spectrum/sdram.vhdl source_file = 1, /home/benny/work/fpga/spectrum/sdram_clk_gen.qip source_file = 1, /home/benny/work/fpga/spectrum/sdram_clk_gen.v +source_file = 1, /home/benny/work/fpga/spectrum/sdram.v +source_file = 1, /home/benny/work/fpga/spectrum/sdram_ctrl.v +source_file = 1, /home/benny/work/fpga/spectrum/sdram_controller.v +source_file = 1, /home/benny/work/fpga/spectrum/pll_sdram.qip +source_file = 1, /home/benny/work/fpga/spectrum/pll_sdram.v +source_file = 1, /home/benny/work/fpga/spectrum/debouncer.v source_file = 1, /home/benny/work/fpga/spectrum/db/spectrum.cbx.xml source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/globals.vh source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh @@ -164,8 +170,6 @@ instance = comp, \GPIO_1[24]~output , GPIO_1[24]~output, spectrum, 1 instance = comp, \GPIO_1[25]~output , GPIO_1[25]~output, spectrum, 1 instance = comp, \GPIO_1[26]~output , GPIO_1[26]~output, spectrum, 1 instance = comp, \GPIO_1[31]~output , GPIO_1[31]~output, spectrum, 1 -instance = comp, \GPIO_1[32]~output , GPIO_1[32]~output, spectrum, 1 -instance = comp, \GPIO_1[33]~output , GPIO_1[33]~output, spectrum, 1 instance = comp, \buzzer_out~output , buzzer_out~output, spectrum, 1 instance = comp, \DRAM_BA[0]~output , DRAM_BA[0]~output, spectrum, 1 instance = comp, \DRAM_BA[1]~output , DRAM_BA[1]~output, spectrum, 1 @@ -190,6 +194,7 @@ instance = comp, \DRAM_ADDR[9]~output , DRAM_ADDR[9]~output, spectrum, 1 instance = comp, \DRAM_ADDR[10]~output , DRAM_ADDR[10]~output, spectrum, 1 instance = comp, \DRAM_ADDR[11]~output , DRAM_ADDR[11]~output, spectrum, 1 instance = comp, \DRAM_ADDR[12]~output , DRAM_ADDR[12]~output, spectrum, 1 +instance = comp, \kempston_gnd~output , kempston_gnd~output, spectrum, 1 instance = comp, \I2C_SCLK~output , I2C_SCLK~output, spectrum, 1 instance = comp, \I2C_SDAT~output , I2C_SDAT~output, spectrum, 1 instance = comp, \DRAM_DQ[0]~output , DRAM_DQ[0]~output, spectrum, 1 @@ -211,26 +216,83 @@ instance = comp, \DRAM_DQ[15]~output , DRAM_DQ[15]~output, spectrum, 1 instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|pll1 , ula_|pll_|altpll_component|auto_generated|pll1, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, spectrum, 1 +instance = comp, \turbo_button~input , turbo_button~input, spectrum, 1 +instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[0]~21 , debounce_turbo|r_Count[0]~21, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[1]~23 , debounce_turbo|r_Count[1]~23, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[1] , debounce_turbo|r_Count[1], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[2]~25 , debounce_turbo|r_Count[2]~25, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[2] , debounce_turbo|r_Count[2], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[3]~27 , debounce_turbo|r_Count[3]~27, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[3] , debounce_turbo|r_Count[3], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[4]~29 , debounce_turbo|r_Count[4]~29, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[4] , debounce_turbo|r_Count[4], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[5]~31 , debounce_turbo|r_Count[5]~31, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[5] , debounce_turbo|r_Count[5], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[6]~33 , debounce_turbo|r_Count[6]~33, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[6] , debounce_turbo|r_Count[6], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[7]~35 , debounce_turbo|r_Count[7]~35, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[7] , debounce_turbo|r_Count[7], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[8]~37 , debounce_turbo|r_Count[8]~37, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[8] , debounce_turbo|r_Count[8], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[9]~39 , debounce_turbo|r_Count[9]~39, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[9] , debounce_turbo|r_Count[9], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[10]~41 , debounce_turbo|r_Count[10]~41, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[10] , debounce_turbo|r_Count[10], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[11]~43 , debounce_turbo|r_Count[11]~43, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[11] , debounce_turbo|r_Count[11], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[12]~45 , debounce_turbo|r_Count[12]~45, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[12] , debounce_turbo|r_Count[12], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[13]~47 , debounce_turbo|r_Count[13]~47, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[13] , debounce_turbo|r_Count[13], spectrum, 1 +instance = comp, \debounce_turbo|r_State~7 , debounce_turbo|r_State~7, spectrum, 1 +instance = comp, \debounce_turbo|LessThan0~0 , debounce_turbo|LessThan0~0, spectrum, 1 +instance = comp, \debounce_turbo|LessThan0~1 , debounce_turbo|LessThan0~1, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[14]~49 , debounce_turbo|r_Count[14]~49, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[14] , debounce_turbo|r_Count[14], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[15]~51 , debounce_turbo|r_Count[15]~51, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[15] , debounce_turbo|r_Count[15], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[16]~53 , debounce_turbo|r_Count[16]~53, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[16] , debounce_turbo|r_Count[16], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[17]~55 , debounce_turbo|r_Count[17]~55, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[17] , debounce_turbo|r_Count[17], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[18]~57 , debounce_turbo|r_Count[18]~57, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[18] , debounce_turbo|r_Count[18], spectrum, 1 +instance = comp, \debounce_turbo|r_Count[19]~59 , debounce_turbo|r_Count[19]~59, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[19] , debounce_turbo|r_Count[19], spectrum, 1 +instance = comp, \debounce_turbo|always0~0 , debounce_turbo|always0~0, spectrum, 1 +instance = comp, \debounce_turbo|always0~1 , debounce_turbo|always0~1, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[20]~61 , debounce_turbo|r_Count[20]~61, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[20] , debounce_turbo|r_Count[20], spectrum, 1 +instance = comp, \debounce_turbo|always0~2 , debounce_turbo|always0~2, spectrum, 1 +instance = comp, \debounce_turbo|r_Count[0] , debounce_turbo|r_Count[0], spectrum, 1 +instance = comp, \debounce_turbo|r_State~4 , debounce_turbo|r_State~4, spectrum, 1 +instance = comp, \debounce_turbo|r_State~2 , debounce_turbo|r_State~2, spectrum, 1 +instance = comp, \debounce_turbo|r_State~0 , debounce_turbo|r_State~0, spectrum, 1 +instance = comp, \debounce_turbo|r_State~1 , debounce_turbo|r_State~1, spectrum, 1 +instance = comp, \debounce_turbo|r_State~3 , debounce_turbo|r_State~3, spectrum, 1 +instance = comp, \debounce_turbo|r_State~5 , debounce_turbo|r_State~5, spectrum, 1 +instance = comp, \debounce_turbo|r_State~6 , debounce_turbo|r_State~6, spectrum, 1 +instance = comp, \debounce_turbo|r_State , debounce_turbo|r_State, spectrum, 1 +instance = comp, \turbo~0 , turbo~0, spectrum, 1 instance = comp, \ula_|clocks_|counter[0]~0 , ula_|clocks_|counter[0]~0, spectrum, 1 instance = comp, \ula_|clocks_|counter[0] , ula_|clocks_|counter[0], spectrum, 1 -instance = comp, \SW[2]~input , SW[2]~input, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~0 , ula_|clocks_|clk_cpu~0, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu , ula_|clocks_|clk_cpu, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~clkctrl , ula_|clocks_|clk_cpu~clkctrl, spectrum, 1 -instance = comp, \KEY[1]~input , KEY[1]~input, spectrum, 1 -instance = comp, \z80_|interrupts_|nmi_armed~feeder , z80_|interrupts_|nmi_armed~feeder, spectrum, 1 instance = comp, \KEY[0]~input , KEY[0]~input, spectrum, 1 instance = comp, \z80_|resets_|x1~0 , z80_|resets_|x1~0, spectrum, 1 instance = comp, \z80_|fpga_reset~feeder , z80_|fpga_reset~feeder, spectrum, 1 instance = comp, \z80_|fpga_reset , z80_|fpga_reset, spectrum, 1 instance = comp, \z80_|fpga_reset~clkctrl , z80_|fpga_reset~clkctrl, spectrum, 1 instance = comp, \z80_|resets_|x1 , z80_|resets_|x1, spectrum, 1 -instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \KEY[1]~input , KEY[1]~input, spectrum, 1 +instance = comp, \z80_|interrupts_|nmi_armed~feeder , z80_|interrupts_|nmi_armed~feeder, spectrum, 1 instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, spectrum, 1 instance = comp, \ula_|video_|Add0~0 , ula_|video_|Add0~0, spectrum, 1 instance = comp, \ula_|video_|vga_hc~3 , ula_|video_|vga_hc~3, spectrum, 1 @@ -242,17 +304,11 @@ instance = comp, \ula_|video_|Add0~4 , ula_|video_|Add0~4, spectrum, 1 instance = comp, \ula_|video_|vga_hc[2] , ula_|video_|vga_hc[2], spectrum, 1 instance = comp, \ula_|video_|Add0~6 , ula_|video_|Add0~6, spectrum, 1 instance = comp, \ula_|video_|vga_hc[3] , ula_|video_|vga_hc[3], spectrum, 1 +instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 instance = comp, \ula_|video_|Add0~8 , ula_|video_|Add0~8, spectrum, 1 instance = comp, \ula_|video_|vga_hc[4] , ula_|video_|vga_hc[4], spectrum, 1 -instance = comp, \ula_|video_|Add0~10 , ula_|video_|Add0~10, spectrum, 1 -instance = comp, \ula_|video_|vga_hc~0 , ula_|video_|vga_hc~0, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[5] , ula_|video_|vga_hc[5], spectrum, 1 -instance = comp, \ula_|video_|Add0~12 , ula_|video_|Add0~12, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[6] , ula_|video_|vga_hc[6], spectrum, 1 -instance = comp, \ula_|video_|Add0~14 , ula_|video_|Add0~14, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[7] , ula_|video_|vga_hc[7], spectrum, 1 -instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 instance = comp, \ula_|video_|Equal0~1 , ula_|video_|Equal0~1, spectrum, 1 +instance = comp, \ula_|video_|Add0~14 , ula_|video_|Add0~14, spectrum, 1 instance = comp, \ula_|video_|Add0~16 , ula_|video_|Add0~16, spectrum, 1 instance = comp, \ula_|video_|vga_hc~2 , ula_|video_|vga_hc~2, spectrum, 1 instance = comp, \ula_|video_|vga_hc[8] , ula_|video_|vga_hc[8], spectrum, 1 @@ -260,22 +316,15 @@ instance = comp, \ula_|video_|Add0~18 , ula_|video_|Add0~18, spectrum, 1 instance = comp, \ula_|video_|vga_hc~1 , ula_|video_|vga_hc~1, spectrum, 1 instance = comp, \ula_|video_|vga_hc[9] , ula_|video_|vga_hc[9], spectrum, 1 instance = comp, \ula_|video_|Equal1~0 , ula_|video_|Equal1~0, spectrum, 1 +instance = comp, \ula_|video_|Add0~10 , ula_|video_|Add0~10, spectrum, 1 +instance = comp, \ula_|video_|vga_hc~0 , ula_|video_|vga_hc~0, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[5] , ula_|video_|vga_hc[5], spectrum, 1 +instance = comp, \ula_|video_|Add0~12 , ula_|video_|Add0~12, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[6] , ula_|video_|vga_hc[6], spectrum, 1 +instance = comp, \ula_|video_|vga_hc[7] , ula_|video_|vga_hc[7], spectrum, 1 instance = comp, \ula_|video_|Add1~0 , ula_|video_|Add1~0, spectrum, 1 -instance = comp, \ula_|video_|Add1~2 , ula_|video_|Add1~2, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 -instance = comp, \ula_|video_|Add1~4 , ula_|video_|Add1~4, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[2]~2 , ula_|video_|vga_vc[2]~2, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[2] , ula_|video_|vga_vc[2], spectrum, 1 -instance = comp, \ula_|video_|Add1~6 , ula_|video_|Add1~6, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[3]~3 , ula_|video_|vga_vc[3]~3, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[3] , ula_|video_|vga_vc[3], spectrum, 1 -instance = comp, \ula_|video_|Add1~8 , ula_|video_|Add1~8, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[4]~5 , ula_|video_|vga_vc[4]~5, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[4] , ula_|video_|vga_vc[4], spectrum, 1 +instance = comp, \ula_|video_|Equal3~0 , ula_|video_|Equal3~0, spectrum, 1 instance = comp, \ula_|video_|Add1~10 , ula_|video_|Add1~10, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[5]~8 , ula_|video_|vga_vc[5]~8, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[5] , ula_|video_|vga_vc[5], spectrum, 1 instance = comp, \ula_|video_|Add1~12 , ula_|video_|Add1~12, spectrum, 1 instance = comp, \ula_|video_|vga_vc[6]~4 , ula_|video_|vga_vc[6]~4, spectrum, 1 instance = comp, \ula_|video_|vga_vc[6] , ula_|video_|vga_vc[6], spectrum, 1 @@ -288,902 +337,827 @@ instance = comp, \ula_|video_|vga_vc[8] , ula_|video_|vga_vc[8], spectrum, 1 instance = comp, \ula_|video_|Add1~18 , ula_|video_|Add1~18, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9]~9 , ula_|video_|vga_vc[9]~9, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9] , ula_|video_|vga_vc[9], spectrum, 1 -instance = comp, \ula_|video_|Equal3~0 , ula_|video_|Equal3~0, spectrum, 1 instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~1 , ula_|video_|Equal3~1, spectrum, 1 instance = comp, \ula_|video_|vga_vc[0]~0 , ula_|video_|vga_vc[0]~0, spectrum, 1 instance = comp, \ula_|video_|vga_vc[0] , ula_|video_|vga_vc[0], spectrum, 1 +instance = comp, \ula_|video_|Add1~2 , ula_|video_|Add1~2, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 +instance = comp, \ula_|video_|Add1~4 , ula_|video_|Add1~4, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[2]~2 , ula_|video_|vga_vc[2]~2, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[2] , ula_|video_|vga_vc[2], spectrum, 1 +instance = comp, \ula_|video_|Add1~6 , ula_|video_|Add1~6, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[3]~3 , ula_|video_|vga_vc[3]~3, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[3] , ula_|video_|vga_vc[3], spectrum, 1 +instance = comp, \ula_|video_|Add1~8 , ula_|video_|Add1~8, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[4]~5 , ula_|video_|vga_vc[4]~5, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[4] , ula_|video_|vga_vc[4], spectrum, 1 +instance = comp, \ula_|video_|vga_vc[5]~8 , ula_|video_|vga_vc[5]~8, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[5] , ula_|video_|vga_vc[5], spectrum, 1 instance = comp, \ula_|video_|Equal2~1 , ula_|video_|Equal2~1, spectrum, 1 instance = comp, \ula_|video_|Equal2~2 , ula_|video_|Equal2~2, spectrum, 1 instance = comp, \SW[1]~input , SW[1]~input, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 , z80_|interrupts_|SYNTHESIZED_WIRE_13~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal0~0 , z80_|pla_decode_|Equal0~0, spectrum, 1 +instance = comp, \z80_|ir_|opcode[4]~feeder , z80_|ir_|opcode[4]~feeder, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M3_ff~0 , z80_|sequencer_|DFFE_M3_ff~0, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M3_ff , z80_|sequencer_|DFFE_M3_ff, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 , z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 -instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 -instance = comp, \z80_|clk_delay_|DFF_inst5~feeder , z80_|clk_delay_|DFF_inst5~feeder, spectrum, 1 -instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 -instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 -instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M4_ff~0 , z80_|sequencer_|DFFE_M4_ff~0, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M4_ff , z80_|sequencer_|DFFE_M4_ff, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~2 , z80_|execute_|ctl_state_alu~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 -instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~3 , z80_|execute_|ctl_mRead~3, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~3 , z80_|execute_|ctl_state_alu~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 -instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 -instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~0 , z80_|execute_|fMWrite~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~97 , z80_|execute_|ctl_inc_cy~97, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~96 , z80_|execute_|ctl_inc_cy~96, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~98 , z80_|execute_|ctl_inc_cy~98, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~1 , z80_|execute_|fMWrite~1, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~17 , z80_|execute_|ctl_mWrite~17, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~51 , z80_|execute_|ctl_bus_inc_oe~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~17 , z80_|pin_control_|bus_db_pin_oe~17, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~8 , z80_|execute_|ctl_reg_sys_hilo[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~15 , z80_|pin_control_|bus_db_pin_oe~15, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~16 , z80_|pin_control_|bus_db_pin_oe~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 -instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorq~feeder , z80_|memory_ifc_|wait_iorq~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 -instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~18 , z80_|execute_|ctl_mWrite~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~21 , z80_|execute_|ctl_flags_alu~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~20 , z80_|execute_|ctl_flags_alu~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~22 , z80_|execute_|ctl_flags_alu~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mwr~feeder , z80_|memory_ifc_|wait_mwr~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|mwr_wr~feeder , z80_|memory_ifc_|mwr_wr~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_m1_ff1 , z80_|memory_ifc_|DFFE_m1_ff1, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_m1_ff3 , z80_|memory_ifc_|DFFE_m1_ff3, spectrum, 1 instance = comp, \z80_|memory_ifc_|nRD_out~0 , z80_|memory_ifc_|nRD_out~0, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~0 , z80_|pla_decode_|Equal1~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~1 , z80_|pla_decode_|Equal1~1, spectrum, 1 instance = comp, \z80_|execute_|ctl_mRead~2 , z80_|execute_|ctl_mRead~2, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 -instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~2 , z80_|execute_|ctl_state_alu~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~3 , z80_|execute_|ctl_mRead~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~2 , z80_|execute_|ctl_sw_1d~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 -instance = comp, \z80_|execute_|setM1~57 , z80_|execute_|setM1~57, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 -instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~33 , z80_|execute_|pc_inc_hold~33, spectrum, 1 -instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~9 , z80_|execute_|ctl_reg_sys_hilo[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~2 , z80_|pla_decode_|Equal40~2, spectrum, 1 -instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~14 , z80_|execute_|pc_inc_hold~14, spectrum, 1 -instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 -instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 +instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~0 , z80_|reg_control_|reg_sys_we_lo~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~1 , z80_|reg_control_|reg_sys_we_lo~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 -instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3~feeder , z80_|memory_ifc_|DFFE_mrd_ff3~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nRD_out~2 , z80_|memory_ifc_|nRD_out~2, spectrum, 1 -instance = comp, \Equal2~1 , Equal2~1, spectrum, 1 -instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 -instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 -instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3]~feeder , ula_|ps2_keyboard_|clk_filter[3]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~50 , ula_|zx_keyboard_|keys[3][2]~50, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~15 , ula_|zx_keyboard_|keys[7][4]~15, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~52 , ula_|zx_keyboard_|keys[2][2]~52, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~53 , ula_|zx_keyboard_|keys[2][2]~53, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 -instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 -instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9~feeder , z80_|resets_|SYNTHESIZED_WIRE_9~feeder, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 -instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~38 , z80_|execute_|ctl_reg_sys_hilo[1]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~3 , z80_|execute_|ctl_sw_1d~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~20 , z80_|execute_|ctl_reg_sys_hilo~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~17 , z80_|execute_|ctl_reg_sys_hilo[1]~17, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~16 , z80_|execute_|ctl_reg_sys_hilo~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~6 , z80_|execute_|ctl_alu_bs_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~2 , z80_|execute_|ctl_alu_sel_op2_neg~2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_iy_set~0 , z80_|execute_|ctl_state_iy_set~0, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 +instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~1 , z80_|decode_state_|SYNTHESIZED_WIRE_0~1, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 +instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~3 , z80_|execute_|ixy_d~3, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~2 , z80_|execute_|ixy_d~2, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~19 , z80_|execute_|ctl_mWrite~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~22 , z80_|execute_|ctl_flags_alu~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~8 , z80_|execute_|ctl_bus_db_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~16 , z80_|execute_|ctl_ir_we~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~0 , z80_|reg_control_|reg_sys_we_lo~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~1 , z80_|reg_control_|reg_sys_we_lo~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 +instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 +instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9 , z80_|execute_|ctl_reg_sys_hilo_pla56M5T3_9, spectrum, 1 instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 -instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~94 , z80_|execute_|ctl_inc_cy~94, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~99 , z80_|execute_|ctl_inc_cy~99, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~30 , z80_|execute_|ctl_reg_sys_hilo[1]~30, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~31 , z80_|execute_|ctl_reg_sys_hilo[1]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~32 , z80_|execute_|ctl_reg_sys_hilo[1]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~0 , z80_|execute_|ctl_reg_sys_we_lo~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~1 , z80_|execute_|ctl_reg_sys_we_lo~1, spectrum, 1 -instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~20 , z80_|execute_|ctl_flags_alu~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~21 , z80_|execute_|ctl_flags_alu~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~19 , z80_|execute_|ctl_flags_alu~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~2 , z80_|pla_decode_|Equal6~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 +instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~12 , z80_|execute_|ctl_reg_gp_sel[0]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_bs_oe~7 , z80_|execute_|ctl_alu_bs_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~6 , z80_|execute_|ctl_alu_bs_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_zero_oe~3 , z80_|execute_|ctl_bus_zero_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 +instance = comp, \z80_|sw1_|SYNTHESIZED_WIRE_1[1] , z80_|sw1_|SYNTHESIZED_WIRE_1[1], spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~19 , z80_|execute_|ctl_flags_xy_we~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal76~2 , z80_|pla_decode_|Equal76~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~8 , z80_|alu_flags_|DFFE_inst_latch_nf~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~13 , z80_|execute_|ctl_alu_op_low~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~12 , z80_|execute_|ctl_alu_op_low~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 +instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel~7 , z80_|execute_|ctl_reg_gp_sel~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~10 , z80_|execute_|ctl_pf_sel[0]~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~11 , z80_|execute_|ctl_flags_pf_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal10~1 , z80_|pla_decode_|Equal10~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~9 , z80_|execute_|ctl_flags_pf_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~13 , z80_|execute_|ctl_pf_sel[0]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~16 , z80_|execute_|ctl_reg_gp_sel[0]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~17 , z80_|execute_|ctl_reg_gp_sel[0]~17, spectrum, 1 +instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~8 , z80_|execute_|ctl_alu_op_low~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~31 , z80_|execute_|ctl_reg_gp_hilo[1]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~32 , z80_|execute_|ctl_reg_gp_hilo[1]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~35 , z80_|execute_|ctl_reg_gp_hilo[0]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~28 , z80_|execute_|ctl_inc_cy~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 +instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~4 , z80_|execute_|ctl_reg_out_lo~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~5 , z80_|execute_|ctl_reg_out_lo~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 , z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~3 , z80_|execute_|ctl_state_alu~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~34 , z80_|execute_|ctl_reg_gp_hilo[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~30 , z80_|execute_|ctl_reg_sys_hilo[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel~13 , z80_|execute_|ctl_reg_gp_sel~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~19 , z80_|execute_|ctl_ir_we~19, spectrum, 1 +instance = comp, \z80_|execute_|setM1~58 , z80_|execute_|setM1~58, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~3 , z80_|execute_|ctl_reg_out_lo~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~29 , z80_|execute_|ctl_inc_cy~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~3 , z80_|execute_|ctl_reg_out_hi~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~9 , z80_|execute_|ctl_sw_2u~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~18 , z80_|execute_|ctl_mWrite~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~3 , z80_|pla_decode_|Equal13~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~13 , z80_|execute_|ctl_reg_in_hi~13, spectrum, 1 instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~21 , z80_|execute_|ctl_reg_sel_wz~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~20 , z80_|execute_|ctl_reg_sel_wz~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~37 , z80_|execute_|ctl_reg_sys_hilo[0]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~11 , z80_|execute_|ctl_reg_sys_hilo[0]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~36 , z80_|execute_|ctl_reg_sys_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~12 , z80_|execute_|ctl_reg_sys_hilo[0]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~29 , z80_|execute_|ctl_reg_sys_hilo[0]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 -instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~4 , z80_|reg_control_|reg_sel_pc~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 -instance = comp, \z80_|execute_|setM1~56 , z80_|execute_|setM1~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~25 , z80_|execute_|ctl_reg_gp_sel[0]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~86 , z80_|execute_|ctl_inc_cy~86, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~52 , z80_|execute_|ctl_bus_inc_oe~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~49 , z80_|execute_|ctl_bus_inc_oe~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~8 , z80_|execute_|ctl_sw_2u~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~14 , z80_|execute_|ctl_flags_hf_cpl~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 +instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 +instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 +instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~9 , z80_|execute_|ctl_sw_4d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~8 , z80_|execute_|ctl_flags_hf_cpl~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 -instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 -instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~23 , z80_|execute_|ctl_reg_gp_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~13 , z80_|execute_|ctl_reg_gp_sel[0]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~12 , z80_|execute_|ctl_reg_gp_sel[0]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 -instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~14 , z80_|execute_|ctl_reg_gp_sel[0]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~20 , z80_|execute_|ctl_reg_gp_sel[1]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~21 , z80_|execute_|ctl_reg_gp_sel[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~5 , z80_|execute_|ctl_reg_gp_sel[1]~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~37 , z80_|execute_|ctl_reg_gp_sel[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~22 , z80_|execute_|ctl_reg_gp_sel[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~36 , z80_|execute_|ctl_reg_gp_sel[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~2 , z80_|reg_control_|reg_sel_de2~2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~50 , z80_|execute_|ctl_bus_inc_oe~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~35 , z80_|execute_|ctl_reg_gp_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~51 , z80_|execute_|ctl_reg_gp_hilo[0]~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~30 , z80_|execute_|ctl_reg_gp_hilo[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~28 , z80_|execute_|ctl_reg_gp_hilo[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~29 , z80_|execute_|ctl_reg_gp_hilo[0]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~31 , z80_|execute_|ctl_reg_gp_hilo[0]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~32 , z80_|execute_|ctl_reg_gp_hilo[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~27 , z80_|execute_|ctl_reg_gp_hilo[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~50 , z80_|execute_|ctl_reg_gp_hilo[0]~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~26 , z80_|execute_|ctl_reg_gp_hilo[0]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~34 , z80_|execute_|ctl_reg_gp_hilo[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~25 , z80_|execute_|ctl_reg_gp_hilo[0]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~38 , z80_|execute_|ctl_reg_gp_hilo[0]~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~9 , z80_|execute_|ctl_reg_gp_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~7 , z80_|execute_|ctl_reg_gp_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~8 , z80_|execute_|ctl_reg_gp_we~8, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~41 , z80_|execute_|ctl_alu_op_low~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~12 , z80_|execute_|ctl_alu_core_hf~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 +instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~10 , z80_|alu_control_|db[6]~10, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~11 , z80_|alu_control_|db[6]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~2 , z80_|pla_decode_|Equal1~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal10~1 , z80_|pla_decode_|Equal10~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~2 , z80_|execute_|ctl_alu_sel_op2_neg~2, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~23 , z80_|execute_|ctl_flags_alu~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~2 , z80_|execute_|ctl_reg_out_hi~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_op_low~16 , z80_|execute_|ctl_alu_op_low~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~3 , z80_|execute_|ctl_alu_sel_op2_neg~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~10 , z80_|execute_|ctl_alu_op_low~10, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~3 , z80_|execute_|ctl_alu_sel_op2_neg~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~39 , z80_|execute_|ctl_alu_op_low~39, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~23 , z80_|execute_|ctl_flags_alu~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~11 , z80_|execute_|ctl_alu_op2_sel_bus~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 +instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~6 , z80_|execute_|ctl_flags_xy_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~8 , z80_|execute_|ctl_pf_sel[0]~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~15 , z80_|execute_|ctl_bus_inc_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~0 , z80_|execute_|ctl_flags_pf_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~1 , z80_|execute_|ctl_flags_pf_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~7 , z80_|execute_|ctl_flags_xy_we~7, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~19 , z80_|execute_|ctl_flags_alu~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~12 , z80_|execute_|ctl_alu_op2_sel_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~18 , z80_|execute_|ctl_alu_op1_sel_bus~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~17 , z80_|execute_|ctl_alu_op1_sel_bus~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~0 , z80_|alu_|db_high[3]~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~39 , z80_|execute_|ctl_reg_gp_hilo[1]~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~40 , z80_|execute_|ctl_reg_gp_hilo[1]~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~53 , z80_|execute_|ctl_reg_gp_hilo[1]~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~52 , z80_|execute_|ctl_reg_gp_hilo[1]~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~16 , z80_|execute_|ctl_alu_oe~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~50 , z80_|execute_|ctl_alu_shift_oe~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~4 , z80_|execute_|ctl_alu_op1_sel_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~5 , z80_|execute_|ctl_alu_op1_sel_bus~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~49 , z80_|execute_|ctl_alu_shift_oe~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~51 , z80_|execute_|ctl_alu_shift_oe~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~48 , z80_|execute_|ctl_alu_shift_oe~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~4 , z80_|execute_|ctl_alu_op2_sel_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~5 , z80_|execute_|ctl_alu_op2_sel_bus~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~1 , z80_|alu_|db_high[3]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~17 , z80_|execute_|ctl_alu_oe~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~45 , z80_|execute_|ctl_reg_gp_hilo[1]~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~41 , z80_|execute_|ctl_reg_gp_hilo[1]~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~42 , z80_|execute_|ctl_reg_gp_hilo[1]~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~43 , z80_|execute_|ctl_reg_gp_hilo[1]~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~44 , z80_|execute_|ctl_reg_gp_hilo[1]~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~46 , z80_|execute_|ctl_reg_gp_hilo[1]~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 , z80_|reg_file_|b2v_latch_af_hi|db[3]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_52 , z80_|reg_file_|SYNTHESIZED_WIRE_52, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~32 , z80_|reg_file_|gdfx_temp1[3]~32, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~3 , z80_|reg_control_|reg_sel_de2~3, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~31 , z80_|reg_file_|gdfx_temp1[3]~31, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~34 , z80_|reg_file_|gdfx_temp1[3]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~36 , z80_|reg_file_|gdfx_temp1[3]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~33 , z80_|reg_file_|gdfx_temp1[3]~33, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~35 , z80_|reg_file_|gdfx_temp1[3]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~37 , z80_|reg_file_|gdfx_temp1[3]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~38 , z80_|reg_file_|gdfx_temp1[3]~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~39 , z80_|reg_file_|gdfx_temp1[3]~39, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~13 , z80_|alu_|db[3]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~9 , z80_|alu_|db[7]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~27 , z80_|execute_|ctl_reg_sel_wz~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~14 , z80_|execute_|ctl_reg_sel_wz~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~21 , z80_|execute_|ctl_reg_sel_wz~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~22 , z80_|execute_|ctl_reg_sel_wz~22, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal5~2 , z80_|pla_decode_|Equal5~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~14 , z80_|execute_|ctl_reg_gp_hilo[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~36 , z80_|execute_|ctl_inc_cy~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~33 , z80_|execute_|ctl_inc_cy~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~7 , z80_|execute_|ctl_sw_4d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~9 , z80_|execute_|ctl_reg_sys_hilo[1]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~3 , z80_|execute_|ctl_al_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 +instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~2 , z80_|execute_|ctl_al_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~9 , z80_|execute_|ctl_pf_sel[0]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 +instance = comp, \z80_|sw1_|SYNTHESIZED_WIRE_2[2] , z80_|sw1_|SYNTHESIZED_WIRE_2[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~2 , z80_|execute_|ctl_alu_op1_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~35 , z80_|execute_|ctl_alu_op_low~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 +instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~2 , z80_|alu_|db_low[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~3 , z80_|alu_|db_low[3]~3, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~4 , z80_|alu_|db_low[3]~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~34 , z80_|execute_|ctl_inc_cy~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~35 , z80_|execute_|ctl_inc_cy~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~24 , z80_|execute_|ctl_reg_sel_wz~24, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~7 , z80_|execute_|ctl_reg_sys_hilo[1]~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~25 , z80_|execute_|ctl_reg_sel_wz~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3 , z80_|execute_|ctl_reg_gp_sel_pla24M4T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3 , z80_|execute_|ctl_reg_gp_sel_pla24M5T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~32 , z80_|execute_|ctl_inc_cy~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~14 , z80_|execute_|ctl_bus_inc_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla5M1T5_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~26 , z80_|execute_|ctl_bus_inc_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~0 , z80_|execute_|ctl_reg_gp_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~27 , z80_|execute_|ctl_reg_gp_hilo[1]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0 , z80_|execute_|ctl_reg_gp_hilo_pla12M3T4_3~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~16 , z80_|execute_|ctl_reg_in_hi~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~22 , z80_|execute_|ctl_reg_sel_pc~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~16 , z80_|execute_|ctl_reg_sys_hilo[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 +instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~16 , z80_|execute_|pc_inc_hold~16, spectrum, 1 +instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~20 , z80_|execute_|ctl_bus_inc_oe~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~21 , z80_|execute_|ctl_bus_inc_oe~21, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~18 , z80_|execute_|pc_inc_hold~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~19 , z80_|execute_|ctl_bus_inc_oe~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~0 , z80_|execute_|ctl_reg_sys_we_lo~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~1 , z80_|execute_|ctl_reg_sys_we_lo~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~20 , z80_|execute_|ctl_reg_sel_wz~20, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~17 , z80_|execute_|ctl_reg_sys_hilo~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~6 , z80_|execute_|ctl_reg_sys_hilo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~20 , z80_|execute_|ctl_reg_sys_hilo[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~17 , z80_|execute_|pc_inc_hold~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~8 , z80_|execute_|ctl_reg_sys_hilo~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~11 , z80_|execute_|ctl_reg_sys_hilo[1]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~30 , z80_|execute_|ctl_reg_sel_wz~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~12 , z80_|execute_|ctl_reg_sys_hilo[1]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~29 , z80_|execute_|ctl_reg_sys_hilo[1]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~8 , z80_|execute_|ctl_sw_4d~8, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~8 , z80_|reg_file_|db_hi_as[3]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~9 , z80_|reg_file_|db_hi_as[3]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~46 , z80_|execute_|ctl_reg_gp_hilo[1]~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~17 , z80_|execute_|ctl_bus_inc_oe~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~18 , z80_|execute_|ctl_bus_inc_oe~18, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~25 , z80_|execute_|ctl_bus_inc_oe~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~27 , z80_|execute_|ctl_bus_inc_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~24 , z80_|execute_|ctl_bus_inc_oe~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~22 , z80_|execute_|ctl_bus_inc_oe~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~23 , z80_|execute_|ctl_bus_inc_oe~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~3 , z80_|reg_file_|db_hi_as[0]~3, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~10 , z80_|reg_file_|db_hi_as[3]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~25 , z80_|execute_|ctl_reg_gp_hilo[1]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~26 , z80_|execute_|ctl_reg_gp_hilo[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~1 , z80_|execute_|ctl_reg_gp_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~17 , z80_|execute_|ctl_reg_in_hi~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~14 , z80_|execute_|ctl_reg_gp_sel[0]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~14 , z80_|execute_|ctl_reg_in_hi~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~15 , z80_|execute_|ctl_reg_in_hi~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~16 , z80_|execute_|ctl_reg_gp_hilo[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~17 , z80_|execute_|ctl_reg_gp_hilo[1]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~28 , z80_|execute_|ctl_reg_gp_hilo[1]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~29 , z80_|execute_|ctl_reg_gp_hilo[1]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~23 , z80_|execute_|ctl_reg_gp_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~30 , z80_|execute_|ctl_reg_gp_hilo[1]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~15 , z80_|execute_|ctl_reg_gp_hilo[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~33 , z80_|execute_|ctl_reg_gp_hilo[1]~33, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~3 , z80_|pla_decode_|Equal1~3, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~4 , z80_|pla_decode_|Equal2~4, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~25 , z80_|execute_|ctl_reg_gp_sel[1]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~43 , z80_|execute_|ctl_reg_gp_sel[1]~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~27 , z80_|execute_|ctl_reg_gp_sel[1]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~28 , z80_|execute_|ctl_reg_gp_sel[1]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~42 , z80_|execute_|ctl_reg_gp_sel[1]~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~20 , z80_|execute_|ctl_reg_gp_sel[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~41 , z80_|execute_|ctl_reg_gp_sel[1]~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~21 , z80_|execute_|ctl_reg_gp_sel[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~22 , z80_|execute_|ctl_reg_gp_sel[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~24 , z80_|execute_|ctl_reg_gp_sel[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~36 , z80_|execute_|ctl_reg_gp_sel[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~38 , z80_|execute_|ctl_reg_gp_sel[0]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~39 , z80_|execute_|ctl_reg_gp_sel[0]~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~37 , z80_|execute_|ctl_reg_gp_sel[0]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~40 , z80_|execute_|ctl_reg_gp_sel[0]~40, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~5 , z80_|reg_control_|reg_sel_de2~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~6 , z80_|reg_control_|reg_sel_de2~6, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~7 , z80_|execute_|ctl_reg_gp_we~7, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_52 , z80_|reg_file_|SYNTHESIZED_WIRE_52, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~23 , z80_|execute_|ctl_reg_sel_wz~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~29 , z80_|execute_|ctl_reg_sel_wz~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~26 , z80_|execute_|ctl_reg_sel_wz~26, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_32 , z80_|reg_file_|SYNTHESIZED_WIRE_32, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~31 , z80_|reg_file_|gdfx_temp1[3]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|db[3]~1 , z80_|reg_file_|b2v_latch_de2_hi|db[3]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~32 , z80_|reg_file_|gdfx_temp1[3]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~33 , z80_|reg_file_|gdfx_temp1[3]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_ix_hi|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~34 , z80_|reg_file_|gdfx_temp1[3]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~36 , z80_|reg_file_|gdfx_temp1[3]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~35 , z80_|reg_file_|gdfx_temp1[3]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~37 , z80_|reg_file_|gdfx_temp1[3]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~38 , z80_|reg_file_|gdfx_temp1[3]~38, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~39 , z80_|reg_file_|gdfx_temp1[3]~39, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~13 , z80_|alu_|db[3]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 @@ -1191,268 +1165,244 @@ instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_w instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 -instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 -instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[3]~3 , z80_|sw1_|db_down[3]~3, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~44 , z80_|reg_file_|gdfx_temp0[3]~44, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~46 , z80_|reg_file_|gdfx_temp0[3]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~47 , z80_|reg_file_|gdfx_temp0[3]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_latch_de2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3] , z80_|reg_file_|b2v_latch_de_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~42 , z80_|reg_file_|gdfx_temp0[3]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~43 , z80_|reg_file_|gdfx_temp0[3]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~50 , z80_|reg_file_|gdfx_temp0[3]~50, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~91 , z80_|reg_file_|gdfx_temp0[0]~91, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~88 , z80_|execute_|ctl_inc_cy~88, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~25 , z80_|execute_|pc_inc_hold~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~18 , z80_|execute_|pc_inc_hold~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~17 , z80_|execute_|pc_inc_hold~17, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~19 , z80_|execute_|pc_inc_hold~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~20 , z80_|execute_|pc_inc_hold~20, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~15 , z80_|execute_|pc_inc_hold~15, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~16 , z80_|execute_|pc_inc_hold~16, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~21 , z80_|execute_|pc_inc_hold~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~22 , z80_|execute_|pc_inc_hold~22, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~23 , z80_|execute_|pc_inc_hold~23, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~24 , z80_|execute_|pc_inc_hold~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~95 , z80_|execute_|ctl_inc_cy~95, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~27 , z80_|execute_|pc_inc_hold~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~32 , z80_|alu_control_|db[3]~32, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~33 , z80_|alu_control_|db[3]~33, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~78 , z80_|execute_|ctl_inc_cy~78, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~26 , z80_|execute_|pc_inc_hold~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~89 , z80_|execute_|ctl_inc_cy~89, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~90 , z80_|execute_|ctl_inc_cy~90, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~91 , z80_|execute_|ctl_inc_cy~91, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~100 , z80_|execute_|ctl_inc_cy~100, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~92 , z80_|execute_|ctl_inc_cy~92, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~33 , z80_|execute_|pc_inc_hold~33, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 instance = comp, \z80_|execute_|pc_inc_hold~32 , z80_|execute_|pc_inc_hold~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~93 , z80_|execute_|ctl_inc_cy~93, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~10 , z80_|alu_control_|db[0]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~22 , z80_|reg_file_|gdfx_temp1[0]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 , z80_|reg_file_|b2v_latch_af_hi|db[0]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~24 , z80_|reg_file_|gdfx_temp1[0]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~26 , z80_|reg_file_|gdfx_temp1[0]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~28 , z80_|reg_file_|gdfx_temp1[0]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~29 , z80_|reg_file_|gdfx_temp1[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~38 , z80_|execute_|pc_inc_hold~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~26 , z80_|execute_|pc_inc_hold~26, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~27 , z80_|execute_|pc_inc_hold~27, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~24 , z80_|execute_|pc_inc_hold~24, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~21 , z80_|execute_|pc_inc_hold~21, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~22 , z80_|execute_|pc_inc_hold~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~20 , z80_|execute_|pc_inc_hold~20, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~23 , z80_|execute_|pc_inc_hold~23, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~37 , z80_|execute_|pc_inc_hold~37, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~19 , z80_|execute_|pc_inc_hold~19, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~25 , z80_|execute_|pc_inc_hold~25, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~41 , z80_|execute_|ctl_inc_cy~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~40 , z80_|execute_|ctl_inc_cy~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~42 , z80_|execute_|ctl_inc_cy~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~43 , z80_|execute_|ctl_inc_cy~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~30 , z80_|execute_|ctl_inc_cy~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~31 , z80_|execute_|ctl_inc_cy~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~38 , z80_|execute_|ctl_inc_cy~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~39 , z80_|execute_|ctl_inc_cy~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla21M3T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~37 , z80_|execute_|ctl_inc_cy~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[3]~feeder , z80_|address_latch_|Q[3]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~37 , z80_|execute_|ctl_reg_gp_hilo[0]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~38 , z80_|execute_|ctl_reg_gp_hilo[0]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~39 , z80_|execute_|ctl_reg_gp_hilo[0]~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~50 , z80_|execute_|ctl_reg_gp_hilo[0]~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~51 , z80_|execute_|ctl_reg_gp_hilo[0]~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~42 , z80_|execute_|ctl_reg_gp_hilo[0]~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~40 , z80_|execute_|ctl_reg_gp_hilo[0]~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~41 , z80_|execute_|ctl_reg_gp_hilo[0]~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~43 , z80_|execute_|ctl_reg_gp_hilo[0]~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~44 , z80_|execute_|ctl_reg_gp_hilo[0]~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~45 , z80_|execute_|ctl_reg_gp_hilo[0]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~93 , z80_|reg_file_|gdfx_temp0[0]~93, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~36 , z80_|execute_|ctl_reg_sys_hilo[0]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~31 , z80_|execute_|ctl_reg_sys_hilo[0]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~32 , z80_|execute_|ctl_reg_sys_hilo[0]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 , z80_|reg_file_|b2v_latch_wz_lo|db[2]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~9 , z80_|alu_|db_low[2]~9, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~10 , z80_|alu_|db_low[2]~10, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~1 , z80_|alu_|db_high[3]~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~10 , z80_|alu_flags_|DFFE_inst_latch_nf~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~17 , z80_|alu_flags_|DFFE_inst_latch_nf~17, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~18 , z80_|alu_flags_|DFFE_inst_latch_nf~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~38 , z80_|execute_|ctl_alu_op_low~38, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~11 , z80_|alu_flags_|DFFE_inst_latch_nf~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~12 , z80_|alu_flags_|DFFE_inst_latch_nf~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S , z80_|execute_|ctl_alu_core_S, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~40 , z80_|execute_|ctl_alu_op_low~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~59 , z80_|reg_file_|gdfx_temp1[7]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~58 , z80_|reg_file_|gdfx_temp1[7]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 , z80_|reg_file_|b2v_latch_af_hi|db[7]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~61 , z80_|reg_file_|gdfx_temp1[7]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~62 , z80_|reg_file_|gdfx_temp1[7]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~63 , z80_|reg_file_|gdfx_temp1[7]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~60 , z80_|reg_file_|gdfx_temp1[7]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~64 , z80_|reg_file_|gdfx_temp1[7]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~65 , z80_|reg_file_|gdfx_temp1[7]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~16 , z80_|reg_file_|db_hi_as[7]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~17 , z80_|reg_file_|db_hi_as[7]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 , z80_|reg_file_|b2v_latch_af_hi|db[1]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~42 , z80_|reg_file_|gdfx_temp0[2]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~43 , z80_|reg_file_|gdfx_temp0[2]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~33 , z80_|reg_file_|gdfx_temp0[1]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~13 , z80_|reg_file_|db_lo_as[3]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~14 , z80_|reg_file_|db_lo_as[3]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~15 , z80_|reg_file_|db_lo_as[3]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~55 , z80_|reg_file_|gdfx_temp0[3]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~57 , z80_|reg_file_|gdfx_temp0[3]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~58 , z80_|reg_file_|gdfx_temp0[3]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~60 , z80_|reg_file_|gdfx_temp0[3]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~59 , z80_|reg_file_|gdfx_temp0[3]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~56 , z80_|reg_file_|gdfx_temp0[3]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~61 , z80_|reg_file_|gdfx_temp0[3]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3] , z80_|reg_file_|b2v_latch_de_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_latch_de2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~54 , z80_|reg_file_|gdfx_temp0[3]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~62 , z80_|reg_file_|gdfx_temp0[3]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~63 , z80_|reg_file_|gdfx_temp0[3]~63, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~14 , z80_|alu_|db[3]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[1]~10 , z80_|reg_file_|gdfx_temp1[1]~10, spectrum, 1 @@ -1462,844 +1412,888 @@ instance = comp, \z80_|reg_file_|gdfx_temp1[1]~13 , z80_|reg_file_|gdfx_temp1[1] instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[1]~11 , z80_|reg_file_|gdfx_temp1[1]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[1]~14 , z80_|reg_file_|gdfx_temp1[1]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 , z80_|reg_file_|b2v_latch_af_hi|db[1]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[1]~15 , z80_|reg_file_|gdfx_temp1[1]~15, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[1]~21 , z80_|reg_file_|gdfx_temp1[1]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~0 , z80_|reg_file_|db_hi_as[1]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~15 , z80_|alu_|db[1]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~5 , z80_|reg_file_|db_hi_as[0]~5, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~6 , z80_|reg_file_|db_hi_as[0]~6, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[8] , z80_|address_latch_|abusz[8], spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~12 , z80_|execute_|ctl_al_we~12, spectrum, 1 instance = comp, \z80_|address_latch_|Q[8] , z80_|address_latch_|Q[8], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~82 , z80_|reg_file_|gdfx_temp0[7]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~81 , z80_|reg_file_|gdfx_temp0[7]~81, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~12 , z80_|alu_control_|db[6]~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_34 , z80_|alu_flags_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_sf , z80_|alu_flags_|DFFE_inst_latch_sf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~18 , z80_|alu_control_|db[7]~18, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~19 , z80_|alu_control_|db[7]~19, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~20 , z80_|alu_control_|db[7]~20, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~37 , z80_|alu_control_|db[7]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~3 , z80_|reg_file_|db_hi_as[1]~3, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[9] , z80_|address_latch_|abusz[9], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[9] , z80_|address_latch_|Q[9], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~44 , z80_|reg_file_|gdfx_temp1[2]~44, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~45 , z80_|reg_file_|gdfx_temp1[2]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~42 , z80_|reg_file_|gdfx_temp1[2]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~43 , z80_|reg_file_|gdfx_temp1[2]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~46 , z80_|reg_file_|gdfx_temp1[2]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~40 , z80_|reg_file_|gdfx_temp1[2]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 , z80_|reg_file_|b2v_latch_af_hi|db[2]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~41 , z80_|reg_file_|gdfx_temp1[2]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~47 , z80_|reg_file_|gdfx_temp1[2]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~48 , z80_|reg_file_|gdfx_temp1[2]~48, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~10 , z80_|reg_file_|db_hi_as[2]~10, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[4]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~68 , z80_|reg_file_|gdfx_temp0[4]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~66 , z80_|reg_file_|gdfx_temp0[4]~66, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~67 , z80_|reg_file_|gdfx_temp0[4]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~64 , z80_|reg_file_|gdfx_temp0[4]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~65 , z80_|reg_file_|gdfx_temp0[4]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[4]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~70 , z80_|reg_file_|gdfx_temp0[4]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[4]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~69 , z80_|reg_file_|gdfx_temp0[4]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~71 , z80_|reg_file_|gdfx_temp0[4]~71, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~72 , z80_|reg_file_|gdfx_temp0[4]~72, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~73 , z80_|reg_file_|gdfx_temp0[4]~73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~16 , z80_|reg_file_|db_lo_as[4]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~17 , z80_|reg_file_|db_lo_as[4]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~18 , z80_|reg_file_|db_lo_as[4]~18, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~44 , z80_|reg_file_|gdfx_temp0[5]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~49 , z80_|reg_file_|gdfx_temp0[5]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~14 , z80_|alu_|db_low[1]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~16 , z80_|alu_|db_low[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[1]~0 , z80_|alu_|alu_op1[1]~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~2 , z80_|alu_flags_|DFFE_inst_latch_nf~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~3 , z80_|alu_flags_|DFFE_inst_latch_nf~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal72~0 , z80_|pla_decode_|Equal72~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~20 , z80_|execute_|ctl_mWrite~20, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~0 , z80_|execute_|ctl_flags_cf_cpl~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~1 , z80_|execute_|ctl_flags_cf_cpl~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~23 , z80_|reg_file_|gdfx_temp0[0]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[0]~4 , z80_|reg_file_|db_lo_ds[0]~4, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~23 , z80_|alu_control_|db[0]~23, spectrum, 1 +instance = comp, \z80_|sw1_|SYNTHESIZED_WIRE_2[0] , z80_|sw1_|SYNTHESIZED_WIRE_2[0], spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~24 , z80_|alu_control_|db[0]~24, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~25 , z80_|alu_control_|db[0]~25, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT3_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~0 , z80_|execute_|ctl_flags_cf2_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~1 , z80_|execute_|ctl_flags_cf2_we~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~0 , z80_|execute_|ctl_flags_cf2_sel_shift~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~1 , z80_|execute_|ctl_flags_cf2_sel_shift~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder , z80_|reg_file_|b2v_latch_hl_hi|latch[7]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~77 , z80_|reg_file_|gdfx_temp1[7]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~13 , z80_|reg_file_|b2v_latch_af_hi|db[7]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~79 , z80_|reg_file_|gdfx_temp1[7]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~80 , z80_|reg_file_|gdfx_temp1[7]~80, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~81 , z80_|reg_file_|gdfx_temp1[7]~81, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~78 , z80_|reg_file_|gdfx_temp1[7]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~82 , z80_|reg_file_|gdfx_temp1[7]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~76 , z80_|reg_file_|gdfx_temp1[7]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~83 , z80_|reg_file_|gdfx_temp1[7]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~23 , z80_|reg_file_|db_hi_as[7]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~24 , z80_|reg_file_|db_hi_as[7]~24, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15] , z80_|address_latch_|b2v_inst_inc_dec|address[15], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~25 , z80_|reg_file_|db_hi_as[7]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~84 , z80_|reg_file_|gdfx_temp1[7]~84, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~19 , z80_|alu_|db[7]~19, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~20 , z80_|alu_|db[7]~20, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~12 , z80_|execute_|ctl_alu_core_S~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal71~2 , z80_|pla_decode_|Equal71~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~16 , z80_|execute_|ctl_alu_core_hf~16, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~5 , z80_|alu_flags_|DFFE_inst_latch_nf~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~14 , z80_|execute_|ctl_alu_core_hf~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~4 , z80_|execute_|ctl_flags_nf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~4 , z80_|alu_flags_|DFFE_inst_latch_nf~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~6 , z80_|alu_flags_|DFFE_inst_latch_nf~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~7 , z80_|alu_flags_|DFFE_inst_latch_nf~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~8 , z80_|execute_|ctl_flags_cf_cpl~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~15 , z80_|execute_|ctl_alu_core_hf~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~17 , z80_|execute_|ctl_alu_core_hf~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~39 , z80_|execute_|ctl_alu_core_hf~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~40 , z80_|execute_|ctl_alu_core_hf~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 +instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[0]~1 , z80_|alu_|alu_op1[0]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S , z80_|execute_|ctl_alu_core_S, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[1]~1 , z80_|alu_|alu_op2[1]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~14 , z80_|alu_|db_high[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~59 , z80_|reg_file_|gdfx_temp1[4]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder , z80_|reg_file_|b2v_latch_bc2_hi|latch[4]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~60 , z80_|reg_file_|gdfx_temp1[4]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~62 , z80_|reg_file_|gdfx_temp1[4]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~63 , z80_|reg_file_|gdfx_temp1[4]~63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~61 , z80_|reg_file_|gdfx_temp1[4]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~64 , z80_|reg_file_|gdfx_temp1[4]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~9 , z80_|reg_file_|b2v_latch_af_hi|db[4]~9, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~58 , z80_|reg_file_|gdfx_temp1[4]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~65 , z80_|reg_file_|gdfx_temp1[4]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~66 , z80_|reg_file_|gdfx_temp1[4]~66, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~17 , z80_|reg_file_|db_hi_as[4]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~18 , z80_|reg_file_|db_hi_as[4]~18, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~19 , z80_|reg_file_|db_hi_as[4]~19, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_52, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~14 , z80_|reg_file_|db_hi_as[5]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~15 , z80_|reg_file_|db_hi_as[5]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~16 , z80_|reg_file_|db_hi_as[5]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~49 , z80_|reg_file_|gdfx_temp1[5]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~52 , z80_|reg_file_|gdfx_temp1[5]~52, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~54 , z80_|reg_file_|gdfx_temp1[5]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~51 , z80_|reg_file_|gdfx_temp1[5]~51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~53 , z80_|reg_file_|gdfx_temp1[5]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~55 , z80_|reg_file_|gdfx_temp1[5]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~11 , z80_|reg_file_|b2v_latch_af_hi|db[5]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~50 , z80_|reg_file_|gdfx_temp1[5]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~56 , z80_|reg_file_|gdfx_temp1[5]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~57 , z80_|reg_file_|gdfx_temp1[5]~57, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~23 , z80_|alu_|db[5]~23, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[1] , z80_|alu_|b2v_op1_latch_mux_high|Q[1], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[1] , z80_|alu_|op1_high[1], spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~1, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~6 , z80_|alu_|db_low[2]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~7 , z80_|alu_|db_low[2]~7, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~8 , z80_|alu_|db_low[2]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~9 , z80_|alu_|db_low[2]~9, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[2] , z80_|reg_file_|b2v_latch_pc_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[2]~11 , z80_|reg_file_|db_hi_as[2]~11, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[2]~12 , z80_|reg_file_|db_hi_as[2]~12, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[10] , z80_|address_latch_|abusz[10], spectrum, 1 instance = comp, \z80_|address_latch_|Q[10] , z80_|address_latch_|Q[10], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~50 , z80_|reg_file_|gdfx_temp1[4]~50, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 , z80_|reg_file_|b2v_latch_af_hi|db[4]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~49 , z80_|reg_file_|gdfx_temp1[4]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~51 , z80_|reg_file_|gdfx_temp1[4]~51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~52 , z80_|reg_file_|gdfx_temp1[4]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~13 , z80_|reg_file_|db_hi_as[2]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~8 , z80_|reg_file_|b2v_latch_af_hi|db[2]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~41 , z80_|reg_file_|gdfx_temp1[2]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~40 , z80_|reg_file_|gdfx_temp1[2]~40, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~43 , z80_|reg_file_|gdfx_temp1[2]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_wz_hi|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~45 , z80_|reg_file_|gdfx_temp1[2]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc2_hi|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~42 , z80_|reg_file_|gdfx_temp1[2]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~44 , z80_|reg_file_|gdfx_temp1[2]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~46 , z80_|reg_file_|gdfx_temp1[2]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~47 , z80_|reg_file_|gdfx_temp1[2]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~48 , z80_|reg_file_|gdfx_temp1[2]~48, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~11 , z80_|alu_|db[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~12 , z80_|alu_|db[2]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~10 , z80_|alu_|db_low[2]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~11 , z80_|alu_|db_low[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~8 , z80_|alu_control_|db[5]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[5]~0 , z80_|reg_file_|db_lo_ds[5]~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~9 , z80_|alu_control_|db[5]~9, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~12 , z80_|alu_control_|db[5]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~47 , z80_|reg_file_|gdfx_temp0[5]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~48 , z80_|reg_file_|gdfx_temp0[5]~48, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~50 , z80_|reg_file_|gdfx_temp0[5]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~46 , z80_|reg_file_|gdfx_temp0[5]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~51 , z80_|reg_file_|gdfx_temp0[5]~51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~45 , z80_|reg_file_|gdfx_temp0[5]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~52 , z80_|reg_file_|gdfx_temp0[5]~52, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~53 , z80_|reg_file_|gdfx_temp0[5]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~10 , z80_|reg_file_|db_lo_as[5]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~11 , z80_|reg_file_|db_lo_as[5]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~12 , z80_|reg_file_|db_lo_as[5]~12, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|db[6]~0 , z80_|reg_file_|b2v_latch_wz_lo|db[6]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~81 , z80_|reg_file_|gdfx_temp0[6]~81, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~82 , z80_|reg_file_|gdfx_temp0[6]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~91 , z80_|reg_file_|gdfx_temp0[7]~91, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~92 , z80_|reg_file_|gdfx_temp0[7]~92, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~7 , z80_|reg_file_|db_hi_as[0]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~22 , z80_|reg_file_|gdfx_temp1[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|db[0]~0 , z80_|reg_file_|b2v_latch_de2_hi|db[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_bc2_hi|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~24 , z80_|reg_file_|gdfx_temp1[0]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~26 , z80_|reg_file_|gdfx_temp1[0]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~28 , z80_|reg_file_|gdfx_temp1[0]~28, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~29 , z80_|reg_file_|gdfx_temp1[0]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~17 , z80_|alu_|db[0]~17, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~12 , z80_|alu_|db_low[1]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~13 , z80_|alu_|db_low[1]~13, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~17 , z80_|alu_|db_low[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~16 , z80_|alu_|db[1]~16, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~3 , z80_|alu_control_|b2v_inst_shift_mux|out~3, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~18 , z80_|alu_|db_low[0]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~19 , z80_|alu_|db_low[0]~19, spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~20 , z80_|alu_|db_low[0]~20, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~22 , z80_|alu_|db_low[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~23 , z80_|alu_|db_low[0]~23, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~20 , z80_|alu_|db_high[0]~20, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 instance = comp, \z80_|alu_|db[4]~8 , z80_|alu_|db[4]~8, spectrum, 1 instance = comp, \z80_|alu_|db[4]~10 , z80_|alu_|db[4]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~53 , z80_|reg_file_|gdfx_temp1[4]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~54 , z80_|reg_file_|gdfx_temp1[4]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~55 , z80_|reg_file_|gdfx_temp1[4]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~56 , z80_|reg_file_|gdfx_temp1[4]~56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~57 , z80_|reg_file_|gdfx_temp1[4]~57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~13 , z80_|reg_file_|db_hi_as[4]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~14 , z80_|reg_file_|db_hi_as[4]~14, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~15 , z80_|reg_file_|db_hi_as[4]~15, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~76 , z80_|reg_file_|gdfx_temp1[5]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~77 , z80_|reg_file_|gdfx_temp1[5]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~79 , z80_|reg_file_|gdfx_temp1[5]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[1] , z80_|alu_|b2v_op1_latch_mux_high|Q[1], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 -instance = comp, \z80_|alu_|op1_high[1] , z80_|alu_|op1_high[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~18 , z80_|alu_|db_low[1]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~19 , z80_|alu_|db_low[1]~19, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~16 , z80_|alu_|db_low[1]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~17 , z80_|alu_|db_low[1]~17, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~20 , z80_|alu_|db_low[1]~20, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[1]~2 , z80_|alu_|alu_op2[1]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~8 , z80_|alu_|db_high[2]~8, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~68 , z80_|reg_file_|gdfx_temp1[6]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~67 , z80_|reg_file_|gdfx_temp1[6]~67, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~0 , z80_|alu_|db_low[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~1 , z80_|alu_|db_low[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~5 , z80_|alu_|db_low[3]~5, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[3]~2 , z80_|alu_|alu_op2[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[3]~2 , z80_|alu_|alu_op1[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~19 , z80_|alu_control_|db[2]~19, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~26 , z80_|alu_control_|db[2]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[2]~5 , z80_|reg_file_|db_lo_ds[2]~5, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~27 , z80_|alu_control_|db[2]~27, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~1 , z80_|alu_flags_|DFFE_inst_latch_pf~1, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~2 , z80_|decode_state_|DFFE_instNonRep~2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~1 , z80_|decode_state_|DFFE_instNonRep~1, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~4 , z80_|decode_state_|DFFE_instNonRep~4, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~5 , z80_|decode_state_|DFFE_instNonRep~5, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep , z80_|decode_state_|DFFE_instNonRep, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~2 , z80_|alu_flags_|DFFE_inst_latch_pf~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~3 , z80_|alu_flags_|DFFE_inst_latch_pf~3, spectrum, 1 +instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 +instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 +instance = comp, \z80_|alu_|alu_parity_out , z80_|alu_|alu_parity_out, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~7 , z80_|alu_flags_|DFFE_inst_latch_pf~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~8 , z80_|alu_flags_|DFFE_inst_latch_pf~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~9 , z80_|alu_flags_|DFFE_inst_latch_pf~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~10 , z80_|alu_flags_|DFFE_inst_latch_pf~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf , z80_|alu_flags_|DFFE_inst_latch_pf, spectrum, 1 +instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_12 , z80_|alu_flags_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_3 , z80_|alu_flags_|SYNTHESIZED_WIRE_3, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~0 , z80_|alu_control_|b2v_inst_cond_mux|out~0, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~1 , z80_|alu_control_|b2v_inst_cond_mux|out~1, spectrum, 1 +instance = comp, \z80_|alu_control_|flags_cond_true~0 , z80_|alu_control_|flags_cond_true~0, spectrum, 1 +instance = comp, \z80_|alu_control_|flags_cond_true , z80_|alu_control_|flags_cond_true, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~28 , z80_|execute_|ctl_reg_sel_wz~28, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~20 , z80_|execute_|ctl_reg_sel_pc~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~23 , z80_|execute_|ctl_reg_sel_pc~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~21 , z80_|execute_|ctl_reg_sel_pc~21, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~2 , z80_|reg_file_|db_hi_as[1]~2, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~4 , z80_|reg_file_|db_hi_as[1]~4, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[9] , z80_|address_latch_|abusz[9], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[9] , z80_|address_latch_|Q[9], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~20 , z80_|reg_file_|db_hi_as[6]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~21 , z80_|reg_file_|db_hi_as[6]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~22 , z80_|reg_file_|db_hi_as[6]~22, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 , z80_|reg_file_|b2v_latch_af_hi|db[6]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~12 , z80_|reg_file_|b2v_latch_af_hi|db[6]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~67 , z80_|reg_file_|gdfx_temp1[6]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder , z80_|reg_file_|b2v_latch_hl_hi|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~68 , z80_|reg_file_|gdfx_temp1[6]~68, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[6]~72 , z80_|reg_file_|gdfx_temp1[6]~72, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[6]~70 , z80_|reg_file_|gdfx_temp1[6]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~71 , z80_|reg_file_|gdfx_temp1[6]~71, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[6]~69 , z80_|reg_file_|gdfx_temp1[6]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~71 , z80_|reg_file_|gdfx_temp1[6]~71, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[6]~73 , z80_|reg_file_|gdfx_temp1[6]~73, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[6]~74 , z80_|reg_file_|gdfx_temp1[6]~74, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~19 , z80_|reg_file_|db_hi_as[6]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~20 , z80_|reg_file_|db_hi_as[6]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~21 , z80_|reg_file_|db_hi_as[6]~21, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[6]~75 , z80_|reg_file_|gdfx_temp1[6]~75, spectrum, 1 instance = comp, \z80_|alu_|db[6]~21 , z80_|alu_|db[6]~21, spectrum, 1 instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~14 , z80_|alu_|db_high[1]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~23 , z80_|alu_|db[5]~23, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~80 , z80_|reg_file_|gdfx_temp1[5]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~81 , z80_|reg_file_|gdfx_temp1[5]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~78 , z80_|reg_file_|gdfx_temp1[5]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~82 , z80_|reg_file_|gdfx_temp1[5]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 , z80_|reg_file_|b2v_latch_af_hi|db[5]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~83 , z80_|reg_file_|gdfx_temp1[5]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~84 , z80_|reg_file_|gdfx_temp1[5]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~22 , z80_|reg_file_|db_hi_as[5]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~23 , z80_|reg_file_|db_hi_as[5]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~24 , z80_|reg_file_|db_hi_as[5]~24, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15] , z80_|address_latch_|b2v_inst_inc_dec|address[15], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~18 , z80_|reg_file_|db_hi_as[7]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~66 , z80_|reg_file_|gdfx_temp1[7]~66, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~19 , z80_|alu_|db[7]~19, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~20 , z80_|alu_|db[7]~20, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[3]~0 , z80_|alu_|alu_op1[3]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[2]~1 , z80_|alu_|alu_op2[2]~1, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~8 , z80_|alu_|db_high[2]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[2]~0 , z80_|alu_|alu_op2[2]~0, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~4 , z80_|execute_|ctl_flags_cf2_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~6 , z80_|execute_|ctl_flags_cf2_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~5 , z80_|execute_|ctl_flags_cf2_we~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~0 , z80_|alu_control_|b2v_inst_shift_mux|out~0, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~22 , z80_|alu_|db_low[0]~22, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~24 , z80_|alu_|db_low[0]~24, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~23 , z80_|alu_|db_low[0]~23, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~25 , z80_|alu_|db_low[0]~25, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~27 , z80_|alu_|db_low[0]~27, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~36 , z80_|execute_|ctl_alu_op_low~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~35 , z80_|execute_|ctl_alu_op_low~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~13 , z80_|execute_|ctl_alu_core_hf~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~14 , z80_|execute_|ctl_alu_core_hf~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~15 , z80_|execute_|ctl_alu_core_hf~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~16 , z80_|execute_|ctl_alu_core_hf~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~17 , z80_|execute_|ctl_alu_core_hf~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~37 , z80_|execute_|ctl_alu_op_low~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 -instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~20 , z80_|alu_|db_high[0]~20, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[0]~1 , z80_|alu_|alu_op1[0]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~11 , z80_|alu_|db_low[2]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~12 , z80_|alu_|db_low[2]~12, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~13 , z80_|alu_|db_low[2]~13, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~14 , z80_|alu_|db_low[2]~14, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~11 , z80_|alu_|db[2]~11, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~12 , z80_|alu_|db[2]~12, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~24 , z80_|alu_control_|db[2]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~3 , z80_|execute_|ctl_reg_out_lo~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 , z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~4 , z80_|execute_|ctl_reg_out_lo~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~5 , z80_|execute_|ctl_reg_out_lo~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[2]~1 , z80_|reg_file_|db_lo_ds[2]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~29 , z80_|alu_control_|db[2]~29, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~30 , z80_|alu_control_|db[2]~30, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~63 , z80_|reg_file_|gdfx_temp0[5]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~68 , z80_|reg_file_|gdfx_temp0[5]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~62 , z80_|reg_file_|gdfx_temp0[5]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~70 , z80_|reg_file_|gdfx_temp0[5]~70, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~71 , z80_|reg_file_|gdfx_temp0[5]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~16 , z80_|reg_file_|db_lo_as[5]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~17 , z80_|reg_file_|db_lo_as[5]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~18 , z80_|reg_file_|db_lo_as[5]~18, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~73 , z80_|reg_file_|gdfx_temp0[6]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~72 , z80_|reg_file_|gdfx_temp0[6]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 , z80_|reg_file_|b2v_latch_wz_lo|db[6]~1, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~4 , z80_|reg_file_|db_hi_as[0]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~5 , z80_|reg_file_|db_hi_as[0]~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~6 , z80_|reg_file_|db_hi_as[0]~6, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~17 , z80_|alu_|db[0]~17, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 -instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~11 , z80_|alu_control_|db[0]~11, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~14 , z80_|alu_control_|db[0]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 , z80_|reg_file_|b2v_latch_hl_lo|db[0]~2, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~23 , z80_|reg_file_|gdfx_temp0[1]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[1]~feeder , z80_|address_latch_|Q[1]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~51 , z80_|reg_file_|gdfx_temp0[3]~51, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~36 , z80_|alu_control_|db[3]~36, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~14 , z80_|alu_|db[3]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~4 , z80_|alu_|db_low[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~5 , z80_|alu_|db_low[3]~5, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~6 , z80_|alu_|db_low[3]~6, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~7 , z80_|alu_|db_low[3]~7, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~8 , z80_|alu_|db_low[3]~8, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~26 , z80_|alu_|db_low[3]~26, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[3]~0 , z80_|alu_|alu_op2[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~4 , z80_|alu_|db_high[3]~4, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~2 , z80_|alu_|db_high[3]~2, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~3 , z80_|alu_|db_high[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~6 , z80_|alu_|db_high[3]~6, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~7 , z80_|alu_|db_high[3]~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~14 , z80_|alu_flags_|DFFE_inst_latch_nf~14, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~13 , z80_|alu_flags_|DFFE_inst_latch_nf~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~15 , z80_|alu_flags_|DFFE_inst_latch_nf~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~16 , z80_|alu_flags_|DFFE_inst_latch_nf~16, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_set~0 , z80_|execute_|ctl_flags_cf_set~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~17, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~1 , z80_|execute_|ctl_flags_cf_cpl~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~0 , z80_|execute_|ctl_flags_cf_cpl~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~3 , z80_|execute_|ctl_flags_hf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~4 , z80_|execute_|ctl_flags_hf_we~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~0 , z80_|alu_flags_|DFFE_inst_latch_hf~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~1 , z80_|alu_flags_|DFFE_inst_latch_hf~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf , z80_|alu_flags_|DFFE_inst_latch_hf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~9 , z80_|execute_|ctl_flags_hf_cpl~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf , z80_|alu_flags_|flags_hf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~33 , z80_|alu_control_|db[4]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~52 , z80_|reg_file_|gdfx_temp0[4]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~2 , z80_|decode_state_|DFFE_instNonRep~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~1 , z80_|decode_state_|DFFE_instNonRep~1, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~4 , z80_|decode_state_|DFFE_instNonRep~4, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~5 , z80_|decode_state_|DFFE_instNonRep~5, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep , z80_|decode_state_|DFFE_instNonRep, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~1 , z80_|alu_flags_|DFFE_inst_latch_pf~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~2 , z80_|alu_flags_|DFFE_inst_latch_pf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~3 , z80_|alu_flags_|DFFE_inst_latch_pf~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~7 , z80_|alu_flags_|DFFE_inst_latch_pf~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[1]~12 , z80_|execute_|ctl_pf_sel[1]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~11 , z80_|execute_|ctl_pf_sel[0]~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 -instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 -instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_parity_out , z80_|alu_|alu_parity_out, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~8 , z80_|alu_flags_|DFFE_inst_latch_pf~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~9 , z80_|alu_flags_|DFFE_inst_latch_pf~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf , z80_|alu_flags_|DFFE_inst_latch_pf, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11 , z80_|alu_flags_|SYNTHESIZED_WIRE_11, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~0 , z80_|alu_control_|b2v_inst_cond_mux|out~0, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~1 , z80_|alu_control_|b2v_inst_cond_mux|out~1, spectrum, 1 -instance = comp, \z80_|alu_control_|flags_cond_true~0 , z80_|alu_control_|flags_cond_true~0, spectrum, 1 -instance = comp, \z80_|alu_control_|flags_cond_true , z80_|alu_control_|flags_cond_true, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~14 , z80_|execute_|ctl_reg_sel_wz~14, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~7 , z80_|reg_file_|db_hi_as[3]~7, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~8 , z80_|reg_file_|db_hi_as[3]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~9 , z80_|reg_file_|db_hi_as[3]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_34 , z80_|alu_flags_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_sf , z80_|alu_flags_|DFFE_inst_latch_sf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~13 , z80_|alu_control_|db[7]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[7]~1 , z80_|reg_file_|db_lo_ds[7]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~14 , z80_|alu_control_|db[7]~14, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~15 , z80_|alu_control_|db[7]~15, spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~4 , z80_|bus_control_|db[7]~4, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~36 , z80_|execute_|fMRead~36, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~37 , z80_|execute_|fMRead~37, spectrum, 1 +instance = comp, \z80_|execute_|nextM~16 , z80_|execute_|nextM~16, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~20 , z80_|execute_|ctl_ir_we~20, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~38 , z80_|execute_|fMRead~38, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~0 , z80_|execute_|fMWrite~0, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 +instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_re~2 , z80_|pin_control_|bus_db_pin_re~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorq~feeder , z80_|memory_ifc_|wait_iorq~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 +instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~17 , z80_|execute_|ctl_mWrite~17, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 +instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~1 , z80_|execute_|fMWrite~1, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~17 , z80_|pin_control_|bus_db_pin_oe~17, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~15 , z80_|pin_control_|bus_db_pin_oe~15, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~16 , z80_|pin_control_|bus_db_pin_oe~16, spectrum, 1 +instance = comp, \D[0]~49 , D[0]~49, spectrum, 1 +instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorqinta~feeder , z80_|memory_ifc_|wait_iorqinta~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 +instance = comp, \Equal5~0 , Equal5~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[1]~1 , z80_|address_pins_|DFFE_apin_latch[1]~1, spectrum, 1 instance = comp, \z80_|execute_|ctl_apin_mux2~0 , z80_|execute_|ctl_apin_mux2~0, spectrum, 1 instance = comp, \z80_|pin_control_|bus_ab_pin_we~2 , z80_|pin_control_|bus_ab_pin_we~2, spectrum, 1 instance = comp, \z80_|pin_control_|bus_ab_pin_we~3 , z80_|pin_control_|bus_ab_pin_we~3, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[11]~19 , z80_|address_pins_|abus[11]~19, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[10]~20 , z80_|address_pins_|abus[10]~20, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~19 , ula_|zx_keyboard_|keys[7][1]~19, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~48 , ula_|zx_keyboard_|keys[7][4]~48, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~51 , ula_|zx_keyboard_|keys[3][2]~51, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 -instance = comp, \D[2]~43 , D[2]~43, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~11 , ula_|zx_keyboard_|keys[0][0]~11, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~62 , ula_|zx_keyboard_|keys[5][0]~62, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~32 , ula_|zx_keyboard_|keys[6][1]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~63 , ula_|zx_keyboard_|keys[6][2]~63, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~64 , ula_|zx_keyboard_|keys[6][2]~64, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~65 , ula_|zx_keyboard_|keys[6][2]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[1] , z80_|address_pins_|DFFE_apin_latch[1], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[2]~2 , z80_|address_pins_|DFFE_apin_latch[2]~2, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[2] , z80_|address_pins_|DFFE_apin_latch[2], spectrum, 1 +instance = comp, \Equal3~0 , Equal3~0, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[6]~6 , z80_|address_pins_|DFFE_apin_latch[6]~6, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[6] , z80_|address_pins_|DFFE_apin_latch[6], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[6]~25 , z80_|address_pins_|abus[6]~25, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[7]~7 , z80_|address_pins_|DFFE_apin_latch[7]~7, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[7] , z80_|address_pins_|DFFE_apin_latch[7], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[7]~26 , z80_|address_pins_|abus[7]~26, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[3]~3 , z80_|address_pins_|DFFE_apin_latch[3]~3, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[3] , z80_|address_pins_|DFFE_apin_latch[3], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[4]~4 , z80_|address_pins_|DFFE_apin_latch[4]~4, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[4] , z80_|address_pins_|DFFE_apin_latch[4], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[5]~5 , z80_|address_pins_|DFFE_apin_latch[5]~5, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[5] , z80_|address_pins_|DFFE_apin_latch[5], spectrum, 1 +instance = comp, \Equal3~1 , Equal3~1, spectrum, 1 +instance = comp, \Equal3~2 , Equal3~2, spectrum, 1 +instance = comp, \D[5]~26 , D[5]~26, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[15]~15 , z80_|address_pins_|DFFE_apin_latch[15]~15, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[15] , z80_|address_pins_|DFFE_apin_latch[15], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[15]~21 , z80_|address_pins_|abus[15]~21, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[15]~23 , z80_|address_pins_|abus[15]~23, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[14]~14 , z80_|address_pins_|DFFE_apin_latch[14]~14, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[14] , z80_|address_pins_|DFFE_apin_latch[14], spectrum, 1 instance = comp, \z80_|address_pins_|abus[14]~22 , z80_|address_pins_|abus[14]~22, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~57 , ula_|zx_keyboard_|keys[7][2]~57, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~58 , ula_|zx_keyboard_|keys[7][2]~58, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~59 , ula_|zx_keyboard_|keys[5][4]~59, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~28 , ula_|zx_keyboard_|keys[7][2]~28, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~60 , ula_|zx_keyboard_|keys[7][2]~60, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~56 , ula_|zx_keyboard_|keys[7][2]~56, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 -instance = comp, \D[2]~44 , D[2]~44, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[12]~24 , z80_|address_pins_|abus[12]~24, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[13] , z80_|address_pins_|DFFE_apin_latch[13], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~29 , ula_|zx_keyboard_|keys[5][2]~29, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~54 , ula_|zx_keyboard_|keys[5][2]~54, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~55 , ula_|zx_keyboard_|keys[5][2]~55, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~1 , ula_|zx_keyboard_|key_row~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~127 , ula_|zx_keyboard_|keys[3][4]~127, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~66 , ula_|zx_keyboard_|keys[4][2]~66, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~128 , ula_|zx_keyboard_|keys[4][2]~128, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~67 , ula_|zx_keyboard_|keys[4][2]~67, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 -instance = comp, \D[2]~45 , D[2]~45, spectrum, 1 -instance = comp, \z80_|address_pins_|abus[0]~16 , z80_|address_pins_|abus[0]~16, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~43 , ula_|zx_keyboard_|keys[6][4]~43, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~44 , ula_|zx_keyboard_|keys[6][4]~44, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2]~45 , ula_|zx_keyboard_|keys[1][2]~45, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2]~46 , ula_|zx_keyboard_|keys[1][2]~46, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~47 , ula_|zx_keyboard_|keys[0][2]~47, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~49 , ula_|zx_keyboard_|keys[0][2]~49, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[9]~17 , z80_|address_pins_|abus[9]~17, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[13]~20 , z80_|address_pins_|abus[13]~20, spectrum, 1 +instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[0]~24 , z80_|address_pins_|abus[0]~24, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[1]~27 , z80_|address_pins_|abus[1]~27, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[2]~28 , z80_|address_pins_|abus[2]~28, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[3]~29 , z80_|address_pins_|abus[3]~29, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[4]~30 , z80_|address_pins_|abus[4]~30, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[5]~31 , z80_|address_pins_|abus[5]~31, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[8]~18 , z80_|address_pins_|abus[8]~18, spectrum, 1 -instance = comp, \D[2]~42 , D[2]~42, spectrum, 1 -instance = comp, \D[2]~46 , D[2]~46, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3~feeder , z80_|memory_ifc_|DFFE_intr_ff3~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 -instance = comp, \z80_|control_pins_|pin_nIORQ~1 , z80_|control_pins_|pin_nIORQ~1, spectrum, 1 -instance = comp, \Equal2~0 , Equal2~0, spectrum, 1 -instance = comp, \z80_|address_pins_|abus[13]~23 , z80_|address_pins_|abus[13]~23, spectrum, 1 -instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[8]~17 , z80_|address_pins_|abus[8]~17, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[9]~16 , z80_|address_pins_|abus[9]~16, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[10]~19 , z80_|address_pins_|abus[10]~19, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[11]~18 , z80_|address_pins_|abus[11]~18, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[12]~21 , z80_|address_pins_|abus[12]~21, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[1]~1 , z80_|address_pins_|DFFE_apin_latch[1]~1, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[1] , z80_|address_pins_|DFFE_apin_latch[1], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[1]~25 , z80_|address_pins_|abus[1]~25, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[2]~2 , z80_|address_pins_|DFFE_apin_latch[2]~2, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[2] , z80_|address_pins_|DFFE_apin_latch[2], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[2]~26 , z80_|address_pins_|abus[2]~26, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[3]~3 , z80_|address_pins_|DFFE_apin_latch[3]~3, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[3] , z80_|address_pins_|DFFE_apin_latch[3], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[3]~27 , z80_|address_pins_|abus[3]~27, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[4]~4 , z80_|address_pins_|DFFE_apin_latch[4]~4, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[4] , z80_|address_pins_|DFFE_apin_latch[4], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[4]~28 , z80_|address_pins_|abus[4]~28, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[5]~5 , z80_|address_pins_|DFFE_apin_latch[5]~5, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[5] , z80_|address_pins_|DFFE_apin_latch[5], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[5]~29 , z80_|address_pins_|abus[5]~29, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[6]~6 , z80_|address_pins_|DFFE_apin_latch[6]~6, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[6] , z80_|address_pins_|DFFE_apin_latch[6], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[6]~30 , z80_|address_pins_|abus[6]~30, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[7]~7 , z80_|address_pins_|DFFE_apin_latch[7]~7, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[7] , z80_|address_pins_|DFFE_apin_latch[7], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[7]~31 , z80_|address_pins_|abus[7]~31, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 -instance = comp, \D[2]~50 , D[2]~50, spectrum, 1 -instance = comp, \D[2]~51 , D[2]~51, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0, spectrum, 1 -instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~13, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0] , ram0|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] , ram0|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1, spectrum, 1 instance = comp, \~GND , ~GND, spectrum, 1 +instance = comp, \ula_|video_|vram_address[0]~feeder , ula_|video_|vram_address[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address~0 , ula_|video_|vram_address~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[0] , ula_|video_|vram_address[0], spectrum, 1 -instance = comp, \ula_|video_|vram_address[1]~feeder , ula_|video_|vram_address[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address[1] , ula_|video_|vram_address[1], spectrum, 1 instance = comp, \ula_|video_|vram_address[2]~4 , ula_|video_|vram_address[2]~4, spectrum, 1 instance = comp, \ula_|video_|vram_address[2] , ula_|video_|vram_address[2], spectrum, 1 @@ -2318,7 +2312,7 @@ instance = comp, \ula_|video_|Add4~10 , ula_|video_|Add4~10, spectrum, 1 instance = comp, \ula_|video_|vram_address[7] , ula_|video_|vram_address[7], spectrum, 1 instance = comp, \ula_|video_|Add4~12 , ula_|video_|Add4~12, spectrum, 1 instance = comp, \ula_|video_|Selector6~0 , ula_|video_|Selector6~0, spectrum, 1 -instance = comp, \ula_|video_|vram_address[8]~1 , ula_|video_|vram_address[8]~1, spectrum, 1 +instance = comp, \ula_|video_|vram_address[9]~1 , ula_|video_|vram_address[9]~1, spectrum, 1 instance = comp, \ula_|video_|vram_address[8] , ula_|video_|vram_address[8], spectrum, 1 instance = comp, \ula_|video_|Add4~14 , ula_|video_|Add4~14, spectrum, 1 instance = comp, \ula_|video_|Selector5~0 , ula_|video_|Selector5~0, spectrum, 1 @@ -2330,534 +2324,750 @@ instance = comp, \ula_|video_|Selector3~0 , ula_|video_|Selector3~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[11] , ula_|video_|vram_address[11], spectrum, 1 instance = comp, \ula_|video_|Selector2~0 , ula_|video_|Selector2~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[12] , ula_|video_|vram_address[12], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0] , ram0|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] , ram0|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \Selector0~0 , Selector0~0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \Selector0~1 , Selector0~1, spectrum, 1 +instance = comp, \D[7]~36 , D[7]~36, spectrum, 1 +instance = comp, \D[7]~37 , D[7]~37, spectrum, 1 +instance = comp, \D[7]~48 , D[7]~48, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_2 , z80_|data_pins_|SYNTHESIZED_WIRE_2, spectrum, 1 +instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~6 , z80_|bus_control_|db[7]~6, spectrum, 1 +instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~9 , z80_|execute_|ctl_alu_op_low~9, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 +instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 +instance = comp, \z80_|execute_|setM1~59 , z80_|execute_|setM1~59, spectrum, 1 +instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3~feeder , z80_|memory_ifc_|DFFE_mrd_ff3~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nRD_out~2 , z80_|memory_ifc_|nRD_out~2, spectrum, 1 +instance = comp, \Equal5~1 , Equal5~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~1, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \D[2]~47 , D[2]~47, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \D[2]~48 , D[2]~48, spectrum, 1 -instance = comp, \D[2]~49 , D[2]~49, spectrum, 1 -instance = comp, \D[2]~119 , D[2]~119, spectrum, 1 -instance = comp, \D[2]~52 , D[2]~52, spectrum, 1 -instance = comp, \D[2]~53 , D[2]~53, spectrum, 1 +instance = comp, \Selector10~0 , Selector10~0, spectrum, 1 +instance = comp, \Selector10~1 , Selector10~1, spectrum, 1 +instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 +instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 +instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[7]~feeder , ula_|ps2_keyboard_|shiftreg[7]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~51 , ula_|zx_keyboard_|keys[3][2]~51, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~feeder , ula_|ps2_keyboard_|shiftreg[0]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~21 , ula_|zx_keyboard_|keys[7][1]~21, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~49 , ula_|zx_keyboard_|keys[7][4]~49, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~52 , ula_|zx_keyboard_|keys[3][2]~52, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~17 , ula_|zx_keyboard_|keys[7][4]~17, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~53 , ula_|zx_keyboard_|keys[2][2]~53, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~54 , ula_|zx_keyboard_|keys[2][2]~54, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[2]~5 , ula_|zx_keyboard_|key_row[2]~5, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~48 , ula_|zx_keyboard_|keys[0][2]~48, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~50 , ula_|zx_keyboard_|keys[0][2]~50, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~46 , ula_|zx_keyboard_|keys[3][3]~46, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~45 , ula_|zx_keyboard_|keys[6][4]~45, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2]~47 , ula_|zx_keyboard_|keys[1][2]~47, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[2]~4 , ula_|zx_keyboard_|key_row[2]~4, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~60 , ula_|zx_keyboard_|keys[7][2]~60, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~62 , ula_|zx_keyboard_|keys[5][4]~62, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~30 , ula_|zx_keyboard_|keys[7][2]~30, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~63 , ula_|zx_keyboard_|keys[7][2]~63, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~13 , ula_|zx_keyboard_|keys[0][0]~13, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~59 , ula_|zx_keyboard_|keys[7][2]~59, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~64 , ula_|zx_keyboard_|keys[7][2]~64, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~66 , ula_|zx_keyboard_|keys[6][2]~66, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~41 , ula_|zx_keyboard_|keys[6][1]~41, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~67 , ula_|zx_keyboard_|keys[6][2]~67, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~65 , ula_|zx_keyboard_|keys[5][0]~65, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~68 , ula_|zx_keyboard_|keys[6][2]~68, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[2]~7 , ula_|zx_keyboard_|key_row[2]~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~55 , ula_|zx_keyboard_|keys[5][2]~55, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~31 , ula_|zx_keyboard_|keys[5][2]~31, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~56 , ula_|zx_keyboard_|keys[5][2]~56, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~57 , ula_|zx_keyboard_|keys[4][2]~57, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~129 , ula_|zx_keyboard_|keys[4][2]~129, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~128 , ula_|zx_keyboard_|keys[3][4]~128, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~58 , ula_|zx_keyboard_|keys[4][2]~58, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[2]~6 , ula_|zx_keyboard_|key_row[2]~6, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[2] , ula_|zx_keyboard_|key_row[2], spectrum, 1 +instance = comp, \Selector14~17 , Selector14~17, spectrum, 1 +instance = comp, \Selector14~18 , Selector14~18, spectrum, 1 +instance = comp, \kempston[1]~input , kempston[1]~input, spectrum, 1 +instance = comp, \Selector10~2 , Selector10~2, spectrum, 1 +instance = comp, \Selector10~3 , Selector10~3, spectrum, 1 +instance = comp, \D[2]~13 , D[2]~13, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_re~2 , z80_|pin_control_|bus_db_pin_re~2, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_2 , z80_|data_pins_|SYNTHESIZED_WIRE_2, spectrum, 1 instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~12 , z80_|bus_control_|db[2]~12, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~6 , z80_|bus_control_|db[0]~6, spectrum, 1 instance = comp, \z80_|bus_control_|db[2]~13 , z80_|bus_control_|db[2]~13, spectrum, 1 -instance = comp, \z80_|ir_|opcode[2]~feeder , z80_|ir_|opcode[2]~feeder, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~14 , z80_|bus_control_|db[2]~14, spectrum, 1 instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~33 , z80_|execute_|ctl_reg_gp_hilo[0]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~13 , z80_|alu_control_|db[6]~13, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~21 , z80_|alu_control_|db[6]~21, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~22 , z80_|alu_control_|db[6]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[6]~0 , z80_|reg_file_|db_lo_ds[6]~0, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[6]~1 , z80_|sw1_|db_down[6]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~23 , z80_|alu_control_|db[6]~23, spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~17 , z80_|execute_|ctl_ir_we~17, spectrum, 1 +instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~3 , z80_|pla_decode_|Equal2~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_cb_set~2 , z80_|execute_|ctl_state_tbl_cb_set~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 +instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe~4 , z80_|execute_|ctl_66_oe~4, spectrum, 1 +instance = comp, \z80_|sw1_|SYNTHESIZED_WIRE_1[0] , z80_|sw1_|SYNTHESIZED_WIRE_1[0], spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~16 , z80_|alu_control_|db[6]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[6]~2 , z80_|reg_file_|db_lo_ds[6]~2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~17 , z80_|alu_control_|db[6]~17, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~18 , z80_|alu_control_|db[6]~18, spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~7 , z80_|bus_control_|db[6]~7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 +instance = comp, \D[6]~28 , D[6]~28, spectrum, 1 +instance = comp, \D[6]~43 , D[6]~43, spectrum, 1 +instance = comp, \D[6]~44 , D[6]~44, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 -instance = comp, \D[6]~103 , D[6]~103, spectrum, 1 -instance = comp, \D[6]~104 , D[6]~104, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \D[6]~42 , D[6]~42, spectrum, 1 +instance = comp, \D[6]~45 , D[6]~45, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \D[6]~100 , D[6]~100, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \D[6]~101 , D[6]~101, spectrum, 1 -instance = comp, \D[6]~102 , D[6]~102, spectrum, 1 -instance = comp, \D[6]~127 , D[6]~127, spectrum, 1 -instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 -instance = comp, \D[6]~99 , D[6]~99, spectrum, 1 -instance = comp, \D[6]~114 , D[6]~114, spectrum, 1 -instance = comp, \D[6]~115 , D[6]~115, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \Mux1~0 , Mux1~0, spectrum, 1 +instance = comp, \D[6]~41 , D[6]~41, spectrum, 1 +instance = comp, \D[6]~46 , D[6]~46, spectrum, 1 +instance = comp, \D[6]~47 , D[6]~47, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 instance = comp, \z80_|data_pins_|dout[6] , z80_|data_pins_|dout[6], spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~9 , z80_|bus_control_|db[6]~9, spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 +instance = comp, \z80_|ir_|opcode[6]~feeder , z80_|ir_|opcode[6]~feeder, spectrum, 1 instance = comp, \z80_|ir_|opcode[6] , z80_|ir_|opcode[6], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~18 , z80_|execute_|ctl_ir_we~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~16 , z80_|execute_|ctl_bus_inc_oe~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~10 , z80_|execute_|ctl_bus_db_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~9 , z80_|execute_|ctl_bus_db_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~83 , ula_|zx_keyboard_|keys[4][0]~83, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~82 , ula_|zx_keyboard_|keys[4][0]~82, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~34 , ula_|zx_keyboard_|keys[5][1]~34, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~35 , ula_|zx_keyboard_|keys[5][1]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~84 , ula_|zx_keyboard_|keys[4][0]~84, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~79 , ula_|zx_keyboard_|keys[5][0]~79, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~80 , ula_|zx_keyboard_|keys[5][0]~80, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~81 , ula_|zx_keyboard_|keys[5][0]~81, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[0]~10 , ula_|zx_keyboard_|key_row[0]~10, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~88 , ula_|zx_keyboard_|keys[6][0]~88, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~89 , ula_|zx_keyboard_|keys[6][0]~89, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~90 , ula_|zx_keyboard_|keys[6][0]~90, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~85 , ula_|zx_keyboard_|keys[7][0]~85, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~76 , ula_|zx_keyboard_|keys[3][0]~76, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~130 , ula_|zx_keyboard_|keys[7][0]~130, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~86 , ula_|zx_keyboard_|keys[7][0]~86, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~87 , ula_|zx_keyboard_|keys[7][0]~87, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[0]~11 , ula_|zx_keyboard_|key_row[0]~11, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~29 , ula_|zx_keyboard_|keys[4][1]~29, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~74 , ula_|zx_keyboard_|keys~74, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~72 , ula_|zx_keyboard_|keys~72, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~71 , ula_|zx_keyboard_|keys[4][3]~71, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~73 , ula_|zx_keyboard_|keys[0][0]~73, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~75 , ula_|zx_keyboard_|keys[0][0]~75, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~22 , ula_|zx_keyboard_|keys[5][4]~22, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~23 , ula_|zx_keyboard_|keys[1][4]~23, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~69 , ula_|zx_keyboard_|keys[1][0]~69, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~70 , ula_|zx_keyboard_|keys[1][0]~70, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[0]~8 , ula_|zx_keyboard_|key_row[0]~8, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~24 , ula_|zx_keyboard_|keys[2][1]~24, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0]~78 , ula_|zx_keyboard_|keys[2][0]~78, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~26 , ula_|zx_keyboard_|keys[3][1]~26, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~77 , ula_|zx_keyboard_|keys[3][0]~77, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[0]~9 , ula_|zx_keyboard_|key_row[0]~9, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[0] , ula_|zx_keyboard_|key_row[0], spectrum, 1 +instance = comp, \kempston[3]~input , kempston[3]~input, spectrum, 1 +instance = comp, \Selector14~8 , Selector14~8, spectrum, 1 +instance = comp, \Selector14~13 , Selector14~13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \Selector14~19 , Selector14~19, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 +instance = comp, \Selector14~10 , Selector14~10, spectrum, 1 +instance = comp, \Selector14~11 , Selector14~11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \Selector14~20 , Selector14~20, spectrum, 1 +instance = comp, \Selector14~9 , Selector14~9, spectrum, 1 +instance = comp, \Selector14~12 , Selector14~12, spectrum, 1 +instance = comp, \Selector14~14 , Selector14~14, spectrum, 1 +instance = comp, \D[0]~14 , D[0]~14, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~11 , z80_|bus_control_|db[0]~11, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~12 , z80_|bus_control_|db[0]~12, spectrum, 1 +instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~13 , z80_|execute_|ctl_flags_hf_cpl~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~0 , z80_|alu_flags_|DFFE_inst_latch_hf~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~3 , z80_|execute_|ctl_flags_hf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~4 , z80_|execute_|ctl_flags_hf_we~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~1 , z80_|alu_flags_|DFFE_inst_latch_hf~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf , z80_|alu_flags_|DFFE_inst_latch_hf, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf , z80_|alu_flags_|flags_hf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~29 , z80_|alu_control_|db[4]~29, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~30 , z80_|alu_control_|db[4]~30, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \Selector6~0 , Selector6~0, spectrum, 1 +instance = comp, \Selector6~1 , Selector6~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~18 , ula_|zx_keyboard_|keys[6][4]~18, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~114 , ula_|zx_keyboard_|keys[6][4]~114, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~115 , ula_|zx_keyboard_|keys[6][4]~115, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~113 , ula_|zx_keyboard_|keys[7][4]~113, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[4]~16 , ula_|zx_keyboard_|key_row[4]~16, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[0]~21 , debounce_autofire|r_Count[0]~21, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[1]~23 , debounce_autofire|r_Count[1]~23, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[1] , debounce_autofire|r_Count[1], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[2]~25 , debounce_autofire|r_Count[2]~25, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[2] , debounce_autofire|r_Count[2], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[3]~27 , debounce_autofire|r_Count[3]~27, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[3] , debounce_autofire|r_Count[3], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[4]~29 , debounce_autofire|r_Count[4]~29, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[4] , debounce_autofire|r_Count[4], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[5]~31 , debounce_autofire|r_Count[5]~31, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[5] , debounce_autofire|r_Count[5], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[6]~33 , debounce_autofire|r_Count[6]~33, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[6] , debounce_autofire|r_Count[6], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[7]~35 , debounce_autofire|r_Count[7]~35, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[7] , debounce_autofire|r_Count[7], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[8]~37 , debounce_autofire|r_Count[8]~37, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[8] , debounce_autofire|r_Count[8], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[9]~39 , debounce_autofire|r_Count[9]~39, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[9] , debounce_autofire|r_Count[9], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[10]~41 , debounce_autofire|r_Count[10]~41, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[10] , debounce_autofire|r_Count[10], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[11]~43 , debounce_autofire|r_Count[11]~43, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[11] , debounce_autofire|r_Count[11], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[12]~45 , debounce_autofire|r_Count[12]~45, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[12] , debounce_autofire|r_Count[12], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[13]~47 , debounce_autofire|r_Count[13]~47, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[13] , debounce_autofire|r_Count[13], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[14]~49 , debounce_autofire|r_Count[14]~49, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[14] , debounce_autofire|r_Count[14], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[15]~51 , debounce_autofire|r_Count[15]~51, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[15] , debounce_autofire|r_Count[15], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[16]~53 , debounce_autofire|r_Count[16]~53, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[16] , debounce_autofire|r_Count[16], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[17]~55 , debounce_autofire|r_Count[17]~55, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[17] , debounce_autofire|r_Count[17], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[18]~57 , debounce_autofire|r_Count[18]~57, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[18] , debounce_autofire|r_Count[18], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[19]~59 , debounce_autofire|r_Count[19]~59, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[19] , debounce_autofire|r_Count[19], spectrum, 1 +instance = comp, \debounce_autofire|r_Count[20]~61 , debounce_autofire|r_Count[20]~61, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[20] , debounce_autofire|r_Count[20], spectrum, 1 +instance = comp, \kempston_autofire_button~input , kempston_autofire_button~input, spectrum, 1 +instance = comp, \debounce_autofire|r_State~7 , debounce_autofire|r_State~7, spectrum, 1 +instance = comp, \debounce_autofire|LessThan0~0 , debounce_autofire|LessThan0~0, spectrum, 1 +instance = comp, \debounce_autofire|LessThan0~1 , debounce_autofire|LessThan0~1, spectrum, 1 +instance = comp, \debounce_autofire|always0~0 , debounce_autofire|always0~0, spectrum, 1 +instance = comp, \debounce_autofire|always0~1 , debounce_autofire|always0~1, spectrum, 1 +instance = comp, \debounce_autofire|always0~2 , debounce_autofire|always0~2, spectrum, 1 +instance = comp, \debounce_autofire|r_Count[0] , debounce_autofire|r_Count[0], spectrum, 1 +instance = comp, \debounce_autofire|r_State~4 , debounce_autofire|r_State~4, spectrum, 1 +instance = comp, \debounce_autofire|r_State~5 , debounce_autofire|r_State~5, spectrum, 1 +instance = comp, \debounce_autofire|r_State~2 , debounce_autofire|r_State~2, spectrum, 1 +instance = comp, \debounce_autofire|r_State~0 , debounce_autofire|r_State~0, spectrum, 1 +instance = comp, \debounce_autofire|r_State~1 , debounce_autofire|r_State~1, spectrum, 1 +instance = comp, \debounce_autofire|r_State~3 , debounce_autofire|r_State~3, spectrum, 1 +instance = comp, \debounce_autofire|r_State~6 , debounce_autofire|r_State~6, spectrum, 1 +instance = comp, \debounce_autofire|r_State , debounce_autofire|r_State, spectrum, 1 +instance = comp, \kempston_autofire_enabled~0 , kempston_autofire_enabled~0, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[0]~51 , kempston_auto_fire_counter[0]~51, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[0] , kempston_auto_fire_counter[0], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[1]~17 , kempston_auto_fire_counter[1]~17, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[1] , kempston_auto_fire_counter[1], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[2]~19 , kempston_auto_fire_counter[2]~19, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[2] , kempston_auto_fire_counter[2], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[3]~21 , kempston_auto_fire_counter[3]~21, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[3] , kempston_auto_fire_counter[3], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[4]~23 , kempston_auto_fire_counter[4]~23, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[4] , kempston_auto_fire_counter[4], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[5]~25 , kempston_auto_fire_counter[5]~25, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[5] , kempston_auto_fire_counter[5], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[6]~27 , kempston_auto_fire_counter[6]~27, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[6] , kempston_auto_fire_counter[6], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[7]~29 , kempston_auto_fire_counter[7]~29, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[7] , kempston_auto_fire_counter[7], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[8]~31 , kempston_auto_fire_counter[8]~31, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[8] , kempston_auto_fire_counter[8], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[9]~33 , kempston_auto_fire_counter[9]~33, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[9] , kempston_auto_fire_counter[9], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[10]~35 , kempston_auto_fire_counter[10]~35, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[10] , kempston_auto_fire_counter[10], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[11]~37 , kempston_auto_fire_counter[11]~37, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[11] , kempston_auto_fire_counter[11], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[12]~39 , kempston_auto_fire_counter[12]~39, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[12] , kempston_auto_fire_counter[12], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[13]~41 , kempston_auto_fire_counter[13]~41, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[13] , kempston_auto_fire_counter[13], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[14]~43 , kempston_auto_fire_counter[14]~43, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[14] , kempston_auto_fire_counter[14], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[15]~45 , kempston_auto_fire_counter[15]~45, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[15] , kempston_auto_fire_counter[15], spectrum, 1 +instance = comp, \Equal2~3 , Equal2~3, spectrum, 1 +instance = comp, \Equal2~2 , Equal2~2, spectrum, 1 +instance = comp, \Equal2~0 , Equal2~0, spectrum, 1 +instance = comp, \Equal2~1 , Equal2~1, spectrum, 1 +instance = comp, \Equal2~4 , Equal2~4, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[16]~47 , kempston_auto_fire_counter[16]~47, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[16] , kempston_auto_fire_counter[16], spectrum, 1 +instance = comp, \kempston_auto_fire_counter[17]~49 , kempston_auto_fire_counter[17]~49, spectrum, 1 +instance = comp, \kempston_auto_fire_counter[17] , kempston_auto_fire_counter[17], spectrum, 1 +instance = comp, \kempston_auto_fire~0 , kempston_auto_fire~0, spectrum, 1 +instance = comp, \Selector6~2 , Selector6~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~116 , ula_|zx_keyboard_|keys[5][4]~116, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~117 , ula_|zx_keyboard_|keys[5][4]~117, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~118 , ula_|zx_keyboard_|keys[4][4]~118, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~119 , ula_|zx_keyboard_|keys[4][4]~119, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~120 , ula_|zx_keyboard_|keys[4][4]~120, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[4]~17 , ula_|zx_keyboard_|key_row[4]~17, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~121 , ula_|zx_keyboard_|keys[3][4]~121, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~133 , ula_|zx_keyboard_|keys[3][4]~133, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~122 , ula_|zx_keyboard_|keys[3][4]~122, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~93 , ula_|zx_keyboard_|keys[2][4]~93, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~123 , ula_|zx_keyboard_|keys[2][4]~123, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~124 , ula_|zx_keyboard_|keys[2][4]~124, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~125 , ula_|zx_keyboard_|keys[2][4]~125, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 +instance = comp, \Selector6~3 , Selector6~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~126 , ula_|zx_keyboard_|keys[1][4]~126, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~95 , ula_|zx_keyboard_|keys[0][4]~95, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~108 , ula_|zx_keyboard_|keys[0][4]~108, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~27 , ula_|zx_keyboard_|keys[3][1]~27, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~127 , ula_|zx_keyboard_|keys[0][4]~127, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 +instance = comp, \Selector6~4 , Selector6~4, spectrum, 1 +instance = comp, \Selector6~5 , Selector6~5, spectrum, 1 +instance = comp, \kempston[4]~input , kempston[4]~input, spectrum, 1 +instance = comp, \Selector6~6 , Selector6~6, spectrum, 1 +instance = comp, \Selector6~7 , Selector6~7, spectrum, 1 +instance = comp, \D[4]~39 , D[4]~39, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~17 , z80_|bus_control_|db[4]~17, spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 +instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 +instance = comp, \z80_|sw1_|SYNTHESIZED_WIRE_2[1] , z80_|sw1_|SYNTHESIZED_WIRE_2[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[1]~3 , z80_|reg_file_|db_lo_ds[1]~3, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~20 , z80_|alu_control_|db[1]~20, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~21 , z80_|alu_control_|db[1]~21, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~22 , z80_|alu_control_|db[1]~22, spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~9 , z80_|bus_control_|db[1]~9, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~33 , ula_|zx_keyboard_|keys[5][1]~33, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~36 , ula_|zx_keyboard_|keys[5][1]~36, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~37 , ula_|zx_keyboard_|keys[5][1]~37, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~32 , ula_|zx_keyboard_|keys[4][1]~32, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[1]~2 , ula_|zx_keyboard_|key_row[1]~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~28 , ula_|zx_keyboard_|keys[3][1]~28, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~25 , ula_|zx_keyboard_|keys[2][1]~25, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[1]~1 , ula_|zx_keyboard_|key_row[1]~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~38 , ula_|zx_keyboard_|keys[7][1]~38, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~7 , ula_|zx_keyboard_|WideOr16~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~5 , ula_|zx_keyboard_|WideOr16~5, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~6 , ula_|zx_keyboard_|WideOr16~6, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~39 , ula_|zx_keyboard_|keys[7][1]~39, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~40 , ula_|zx_keyboard_|keys[6][1]~40, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~42 , ula_|zx_keyboard_|keys[6][1]~42, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~43 , ula_|zx_keyboard_|keys[6][1]~43, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~44 , ula_|zx_keyboard_|keys[6][1]~44, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[1]~3 , ula_|zx_keyboard_|key_row[1]~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~12 , ula_|zx_keyboard_|keys[0][1]~12, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~15 , ula_|zx_keyboard_|keys[0][1]~15, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~16 , ula_|zx_keyboard_|keys[0][1]~16, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~19 , ula_|zx_keyboard_|keys[1][1]~19, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~20 , ula_|zx_keyboard_|keys[1][1]~20, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[1]~0 , ula_|zx_keyboard_|key_row[1]~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[1] , ula_|zx_keyboard_|key_row[1], spectrum, 1 +instance = comp, \kempston[2]~input , kempston[2]~input, spectrum, 1 +instance = comp, \Selector12~4 , Selector12~4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \Selector12~10 , Selector12~10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 +instance = comp, \Selector12~7 , Selector12~7, spectrum, 1 +instance = comp, \Selector12~8 , Selector12~8, spectrum, 1 +instance = comp, \Selector12~9 , Selector12~9, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \Selector12~15 , Selector12~15, spectrum, 1 +instance = comp, \Selector12~5 , Selector12~5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \Selector12~14 , Selector12~14, spectrum, 1 +instance = comp, \Selector12~6 , Selector12~6, spectrum, 1 +instance = comp, \Selector12~11 , Selector12~11, spectrum, 1 +instance = comp, \D[1]~12 , D[1]~12, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 +instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 instance = comp, \z80_|interrupts_|iff1~1 , z80_|interrupts_|iff1~1, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_15 , z80_|interrupts_|SYNTHESIZED_WIRE_15, spectrum, 1 instance = comp, \z80_|interrupts_|iff1 , z80_|interrupts_|iff1, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13 , z80_|interrupts_|SYNTHESIZED_WIRE_13, spectrum, 1 instance = comp, \z80_|interrupts_|int_armed , z80_|interrupts_|int_armed, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_inst44~feeder , z80_|interrupts_|DFFE_inst44~feeder, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~4 , z80_|interrupts_|test1~4, spectrum, 1 instance = comp, \z80_|interrupts_|DFFE_inst44 , z80_|interrupts_|DFFE_inst44, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~37 , z80_|execute_|fMRead~37, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~36 , z80_|execute_|fMRead~36, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~103 , ula_|zx_keyboard_|keys[5][3]~103, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~20 , ula_|zx_keyboard_|keys[5][4]~20, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~21 , ula_|zx_keyboard_|keys[1][4]~21, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~104 , ula_|zx_keyboard_|keys[5][3]~104, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~73 , ula_|zx_keyboard_|keys[3][0]~73, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~129 , ula_|zx_keyboard_|keys[4][3]~129, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~1 , ula_|zx_keyboard_|WideOr16~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~105 , ula_|zx_keyboard_|keys[4][3]~105, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~130 , ula_|zx_keyboard_|keys[4][3]~130, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~107 , ula_|zx_keyboard_|keys[4][3]~107, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 -instance = comp, \D[3]~74 , D[3]~74, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~39 , ula_|zx_keyboard_|keys[5][1]~39, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~100 , ula_|zx_keyboard_|keys[2][3]~100, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~99 , ula_|zx_keyboard_|keys[2][3]~99, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~102 , ula_|zx_keyboard_|keys[2][3]~102, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~97 , ula_|zx_keyboard_|keys[3][3]~97, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~98 , ula_|zx_keyboard_|keys[3][3]~98, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 -instance = comp, \D[3]~73 , D[3]~73, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~108 , ula_|zx_keyboard_|keys[0][4]~108, spectrum, 1 +instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 +instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 +instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_zero_oe~2 , z80_|execute_|ctl_bus_zero_oe~2, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~3 , z80_|bus_control_|db[0]~3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \Selector8~5 , Selector8~5, spectrum, 1 +instance = comp, \Selector8~6 , Selector8~6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \Selector8~7 , Selector8~7, spectrum, 1 +instance = comp, \Selector8~8 , Selector8~8, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~111 , ula_|zx_keyboard_|keys[6][3]~111, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~112 , ula_|zx_keyboard_|keys[6][3]~112, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~134 , ula_|zx_keyboard_|keys[6][3]~134, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~135 , ula_|zx_keyboard_|keys[6][3]~135, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3]~109 , ula_|zx_keyboard_|keys[7][3]~109, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3]~110 , ula_|zx_keyboard_|keys[7][3]~110, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][3] , ula_|zx_keyboard_|keys[7][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~111 , ula_|zx_keyboard_|keys[6][3]~111, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~112 , ula_|zx_keyboard_|keys[6][3]~112, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~132 , ula_|zx_keyboard_|keys[6][3]~132, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~133 , ula_|zx_keyboard_|keys[6][3]~133, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 -instance = comp, \D[3]~75 , D[3]~75, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[3]~15 , ula_|zx_keyboard_|key_row[3]~15, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[0][3]~94 , ula_|zx_keyboard_|keys[0][3]~94, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~93 , ula_|zx_keyboard_|keys[2][4]~93, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~95 , ula_|zx_keyboard_|keys[0][4]~95, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[0][3]~96 , ula_|zx_keyboard_|keys[0][3]~96, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[1][3]~91 , ula_|zx_keyboard_|keys[1][3]~91, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[1][3]~92 , ula_|zx_keyboard_|keys[1][3]~92, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 -instance = comp, \D[3]~72 , D[3]~72, spectrum, 1 -instance = comp, \D[3]~76 , D[3]~76, spectrum, 1 -instance = comp, \D[3]~122 , D[3]~122, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \D[3]~79 , D[3]~79, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \D[3]~77 , D[3]~77, spectrum, 1 -instance = comp, \D[3]~80 , D[3]~80, spectrum, 1 -instance = comp, \D[3]~81 , D[3]~81, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \D[3]~124 , D[3]~124, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \D[3]~123 , D[3]~123, spectrum, 1 -instance = comp, \D[3]~78 , D[3]~78, spectrum, 1 -instance = comp, \D[3]~82 , D[3]~82, spectrum, 1 -instance = comp, \D[3]~108 , D[3]~108, spectrum, 1 -instance = comp, \D[3]~109 , D[3]~109, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[3]~12 , ula_|zx_keyboard_|key_row[3]~12, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~97 , ula_|zx_keyboard_|keys[3][3]~97, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~98 , ula_|zx_keyboard_|keys[3][3]~98, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~100 , ula_|zx_keyboard_|keys[2][3]~100, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~99 , ula_|zx_keyboard_|keys[2][3]~99, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~102 , ula_|zx_keyboard_|keys[2][3]~102, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[3]~13 , ula_|zx_keyboard_|key_row[3]~13, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~105 , ula_|zx_keyboard_|keys[4][3]~105, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~131 , ula_|zx_keyboard_|keys[4][3]~131, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~132 , ula_|zx_keyboard_|keys[4][3]~132, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~107 , ula_|zx_keyboard_|keys[4][3]~107, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~103 , ula_|zx_keyboard_|keys[5][3]~103, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~104 , ula_|zx_keyboard_|keys[5][3]~104, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[3]~14 , ula_|zx_keyboard_|key_row[3]~14, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row[3] , ula_|zx_keyboard_|key_row[3], spectrum, 1 +instance = comp, \kempston[0]~input , kempston[0]~input, spectrum, 1 +instance = comp, \Selector8~4 , Selector8~4, spectrum, 1 +instance = comp, \Selector8~9 , Selector8~9, spectrum, 1 +instance = comp, \D[3]~38 , D[3]~38, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] , z80_|data_pins_|SYNTHESIZED_WIRE_0[3], spectrum, 1 instance = comp, \z80_|data_pins_|dout[3] , z80_|data_pins_|dout[3], spectrum, 1 +instance = comp, \z80_|bus_control_|db[3]~19 , z80_|bus_control_|db[3]~19, spectrum, 1 instance = comp, \z80_|bus_control_|db[3]~20 , z80_|bus_control_|db[3]~20, spectrum, 1 -instance = comp, \z80_|bus_control_|db[3]~21 , z80_|bus_control_|db[3]~21, spectrum, 1 +instance = comp, \z80_|ir_|opcode[3]~feeder , z80_|ir_|opcode[3]~feeder, spectrum, 1 instance = comp, \z80_|ir_|opcode[3] , z80_|ir_|opcode[3], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~5 , z80_|bus_control_|db[7]~5, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3, spectrum, 1 -instance = comp, \D[5]~97 , D[5]~97, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 -instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 -instance = comp, \D[7]~116 , D[7]~116, spectrum, 1 -instance = comp, \D[7]~117 , D[7]~117, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~7 , z80_|bus_control_|db[7]~7, spectrum, 1 -instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~11 , z80_|execute_|ctl_alu_op_low~11, spectrum, 1 +instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 +instance = comp, \z80_|execute_|setM1~60 , z80_|execute_|setM1~60, spectrum, 1 +instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 +instance = comp, \z80_|execute_|nextM~17 , z80_|execute_|nextM~17, spectrum, 1 +instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 +instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 +instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 +instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 +instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 +instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 +instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 +instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 +instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 +instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED, spectrum, 1 +instance = comp, \z80_|interrupts_|im1~feeder , z80_|interrupts_|im1~feeder, spectrum, 1 instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~88 , ula_|zx_keyboard_|keys[6][0]~88, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~89 , ula_|zx_keyboard_|keys[6][0]~89, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~90 , ula_|zx_keyboard_|keys[6][0]~90, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~84 , ula_|zx_keyboard_|keys[7][0]~84, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~78 , ula_|zx_keyboard_|keys[5][0]~78, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~85 , ula_|zx_keyboard_|keys[7][0]~85, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~86 , ula_|zx_keyboard_|keys[7][0]~86, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~87 , ula_|zx_keyboard_|keys[7][0]~87, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 -instance = comp, \D[0]~57 , D[0]~57, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~81 , ula_|zx_keyboard_|keys[4][0]~81, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~82 , ula_|zx_keyboard_|keys[4][0]~82, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~40 , ula_|zx_keyboard_|keys[5][1]~40, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~83 , ula_|zx_keyboard_|keys[4][0]~83, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~79 , ula_|zx_keyboard_|keys[5][0]~79, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~80 , ula_|zx_keyboard_|keys[5][0]~80, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 -instance = comp, \D[0]~56 , D[0]~56, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~76 , ula_|zx_keyboard_|keys[1][0]~76, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~77 , ula_|zx_keyboard_|keys[1][0]~77, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~68 , ula_|zx_keyboard_|keys[4][3]~68, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~69 , ula_|zx_keyboard_|keys~69, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~70 , ula_|zx_keyboard_|keys[0][0]~70, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~27 , ula_|zx_keyboard_|keys[4][1]~27, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~71 , ula_|zx_keyboard_|keys~71, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~72 , ula_|zx_keyboard_|keys[0][0]~72, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~2 , ula_|zx_keyboard_|key_row~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~22 , ula_|zx_keyboard_|keys[2][1]~22, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0]~75 , ula_|zx_keyboard_|keys[2][0]~75, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~24 , ula_|zx_keyboard_|keys[3][1]~24, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~74 , ula_|zx_keyboard_|keys[3][0]~74, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 -instance = comp, \D[0]~54 , D[0]~54, spectrum, 1 -instance = comp, \D[0]~55 , D[0]~55, spectrum, 1 -instance = comp, \D[0]~58 , D[0]~58, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 -instance = comp, \D[0]~62 , D[0]~62, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \D[0]~63 , D[0]~63, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \D[0]~59 , D[0]~59, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \D[0]~60 , D[0]~60, spectrum, 1 -instance = comp, \D[0]~61 , D[0]~61, spectrum, 1 -instance = comp, \D[0]~120 , D[0]~120, spectrum, 1 -instance = comp, \D[0]~64 , D[0]~64, spectrum, 1 -instance = comp, \D[0]~65 , D[0]~65, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~16 , z80_|bus_control_|db[0]~16, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~17 , z80_|bus_control_|db[0]~17, spectrum, 1 -instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 -instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~9 , z80_|alu_|db[7]~9, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~15 , z80_|alu_|db[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~16 , z80_|alu_|db[1]~16, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~25 , z80_|alu_control_|db[1]~25, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~26 , z80_|alu_control_|db[1]~26, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[1]~2 , z80_|sw1_|db_down[1]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~27 , z80_|alu_control_|db[1]~27, spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~38 , ula_|zx_keyboard_|keys[5][1]~38, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~41 , ula_|zx_keyboard_|keys[5][1]~41, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~42 , ula_|zx_keyboard_|keys[5][1]~42, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~30 , ula_|zx_keyboard_|keys[4][1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~0 , ula_|zx_keyboard_|key_row~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~36 , ula_|zx_keyboard_|keys[7][1]~36, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~0 , ula_|zx_keyboard_|WideOr16~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~37 , ula_|zx_keyboard_|keys[7][1]~37, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~33 , ula_|zx_keyboard_|keys[6][1]~33, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~34 , ula_|zx_keyboard_|keys[6][1]~34, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~31 , ula_|zx_keyboard_|keys[6][1]~31, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~35 , ula_|zx_keyboard_|keys[6][1]~35, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 -instance = comp, \D[1]~32 , D[1]~32, spectrum, 1 -instance = comp, \D[1]~33 , D[1]~33, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~16 , ula_|zx_keyboard_|keys[6][4]~16, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~17 , ula_|zx_keyboard_|keys[1][1]~17, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~18 , ula_|zx_keyboard_|keys[1][1]~18, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~12 , ula_|zx_keyboard_|keys[0][1]~12, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~13 , ula_|zx_keyboard_|keys[0][1]~13, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~10 , ula_|zx_keyboard_|keys[0][1]~10, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 -instance = comp, \D[1]~30 , D[1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~25 , ula_|zx_keyboard_|keys[3][1]~25, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~26 , ula_|zx_keyboard_|keys[3][1]~26, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~23 , ula_|zx_keyboard_|keys[2][1]~23, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 -instance = comp, \D[1]~31 , D[1]~31, spectrum, 1 -instance = comp, \D[1]~34 , D[1]~34, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 -instance = comp, \D[1]~38 , D[1]~38, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \D[1]~39 , D[1]~39, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \D[1]~35 , D[1]~35, spectrum, 1 -instance = comp, \D[1]~36 , D[1]~36, spectrum, 1 -instance = comp, \D[1]~37 , D[1]~37, spectrum, 1 -instance = comp, \D[1]~118 , D[1]~118, spectrum, 1 -instance = comp, \D[1]~40 , D[1]~40, spectrum, 1 -instance = comp, \D[1]~41 , D[1]~41, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~11 , z80_|bus_control_|db[1]~11, spectrum, 1 -instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~126 , ula_|zx_keyboard_|keys[6][4]~126, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~125 , ula_|zx_keyboard_|keys[7][4]~125, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 -instance = comp, \D[4]~88 , D[4]~88, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~120 , ula_|zx_keyboard_|keys[5][4]~120, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~121 , ula_|zx_keyboard_|keys[5][4]~121, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~122 , ula_|zx_keyboard_|keys[4][4]~122, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~123 , ula_|zx_keyboard_|keys[4][4]~123, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~124 , ula_|zx_keyboard_|keys[4][4]~124, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 -instance = comp, \D[4]~87 , D[4]~87, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~115 , ula_|zx_keyboard_|keys[2][4]~115, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~116 , ula_|zx_keyboard_|keys[2][4]~116, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~117 , ula_|zx_keyboard_|keys[2][4]~117, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~3 , ula_|zx_keyboard_|key_row~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~118 , ula_|zx_keyboard_|keys[3][4]~118, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~131 , ula_|zx_keyboard_|keys[3][4]~131, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~119 , ula_|zx_keyboard_|keys[3][4]~119, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~114 , ula_|zx_keyboard_|keys[0][4]~114, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~113 , ula_|zx_keyboard_|keys[1][4]~113, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 -instance = comp, \D[4]~85 , D[4]~85, spectrum, 1 -instance = comp, \D[4]~86 , D[4]~86, spectrum, 1 -instance = comp, \D[4]~89 , D[4]~89, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 -instance = comp, \D[4]~93 , D[4]~93, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 -instance = comp, \D[4]~94 , D[4]~94, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \D[4]~90 , D[4]~90, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \D[4]~91 , D[4]~91, spectrum, 1 -instance = comp, \D[4]~92 , D[4]~92, spectrum, 1 -instance = comp, \D[4]~125 , D[4]~125, spectrum, 1 -instance = comp, \D[4]~110 , D[4]~110, spectrum, 1 -instance = comp, \D[4]~111 , D[4]~111, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 -instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal43~0 , z80_|pla_decode_|Equal43~0, spectrum, 1 -instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 -instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 -instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[5]~0 , z80_|sw1_|db_down[5]~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~15 , z80_|alu_control_|db[5]~15, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~16 , z80_|alu_control_|db[5]~16, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~17 , z80_|alu_control_|db[5]~17, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~5 , z80_|bus_control_|db[0]~5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \Mux2~0 , Mux2~0, spectrum, 1 -instance = comp, \Mux2~1 , Mux2~1, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1, spectrum, 1 -instance = comp, \D[5]~112 , D[5]~112, spectrum, 1 -instance = comp, \D[5]~113 , D[5]~113, spectrum, 1 +instance = comp, \Selector4~0 , Selector4~0, spectrum, 1 +instance = comp, \Selector4~1 , Selector4~1, spectrum, 1 +instance = comp, \D[5]~25 , D[5]~25, spectrum, 1 +instance = comp, \D[5]~27 , D[5]~27, spectrum, 1 +instance = comp, \D[5]~40 , D[5]~40, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] , z80_|data_pins_|SYNTHESIZED_WIRE_0[5], spectrum, 1 instance = comp, \z80_|data_pins_|dout[5] , z80_|data_pins_|dout[5], spectrum, 1 -instance = comp, \z80_|bus_control_|db[5]~14 , z80_|bus_control_|db[5]~14, spectrum, 1 instance = comp, \z80_|bus_control_|db[5]~15 , z80_|bus_control_|db[5]~15, spectrum, 1 +instance = comp, \z80_|bus_control_|db[5]~16 , z80_|bus_control_|db[5]~16, spectrum, 1 instance = comp, \z80_|ir_|opcode[5] , z80_|ir_|opcode[5], spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 -instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 -instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 -instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 -instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 -instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 -instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 -instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 -instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 -instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 -instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 -instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 -instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 -instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 -instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 -instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 -instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 -instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 -instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 -instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 -instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 -instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 -instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 -instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 -instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 -instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 -instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 -instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 -instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 -instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 -instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 -instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 -instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 -instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 -instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 -instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 -instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 -instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 -instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 -instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 -instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 +instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 -instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 -instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 -instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 -instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 +instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 +instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 +instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 +instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 +instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 +instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 +instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 +instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 +instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 +instance = comp, \z80_|execute_|setM1~57 , z80_|execute_|setM1~57, spectrum, 1 +instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 +instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 +instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 +instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 +instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 +instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 +instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 +instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 +instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 +instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 +instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 +instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 +instance = comp, \z80_|execute_|setM1~56 , z80_|execute_|setM1~56, spectrum, 1 +instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 +instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 +instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 +instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 +instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 +instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 +instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 +instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 +instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 +instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 +instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9~feeder , z80_|resets_|SYNTHESIZED_WIRE_9~feeder, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 +instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[0]~0 , z80_|address_pins_|DFFE_apin_latch[0]~0, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[0] , z80_|address_pins_|DFFE_apin_latch[0], spectrum, 1 -instance = comp, \D[0]~66 , D[0]~66, spectrum, 1 -instance = comp, \D[0]~67 , D[0]~67, spectrum, 1 -instance = comp, \D[0]~121 , D[0]~121, spectrum, 1 -instance = comp, \D[1]~68 , D[1]~68, spectrum, 1 -instance = comp, \D[1]~69 , D[1]~69, spectrum, 1 -instance = comp, \D[2]~70 , D[2]~70, spectrum, 1 -instance = comp, \D[2]~71 , D[2]~71, spectrum, 1 -instance = comp, \D[3]~83 , D[3]~83, spectrum, 1 -instance = comp, \D[3]~84 , D[3]~84, spectrum, 1 -instance = comp, \D[4]~95 , D[4]~95, spectrum, 1 -instance = comp, \D[4]~96 , D[4]~96, spectrum, 1 -instance = comp, \D[5]~126 , D[5]~126, spectrum, 1 -instance = comp, \D[5]~98 , D[5]~98, spectrum, 1 -instance = comp, \D[6]~105 , D[6]~105, spectrum, 1 -instance = comp, \D[6]~106 , D[6]~106, spectrum, 1 -instance = comp, \D[7]~128 , D[7]~128, spectrum, 1 -instance = comp, \D[7]~107 , D[7]~107, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~3, spectrum, 1 +instance = comp, \Selector14~15 , Selector14~15, spectrum, 1 +instance = comp, \Selector14~16 , Selector14~16, spectrum, 1 +instance = comp, \D[0]~15 , D[0]~15, spectrum, 1 +instance = comp, \D[0]~16 , D[0]~16, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~5, spectrum, 1 +instance = comp, \Selector12~12 , Selector12~12, spectrum, 1 +instance = comp, \Selector12~13 , Selector12~13, spectrum, 1 +instance = comp, \D[1]~17 , D[1]~17, spectrum, 1 +instance = comp, \D[1]~18 , D[1]~18, spectrum, 1 +instance = comp, \D[2]~19 , D[2]~19, spectrum, 1 +instance = comp, \D[2]~20 , D[2]~20, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7, spectrum, 1 +instance = comp, \Selector8~2 , Selector8~2, spectrum, 1 +instance = comp, \Selector8~3 , Selector8~3, spectrum, 1 +instance = comp, \D[3]~21 , D[3]~21, spectrum, 1 +instance = comp, \D[3]~22 , D[3]~22, spectrum, 1 +instance = comp, \D[4]~23 , D[4]~23, spectrum, 1 +instance = comp, \D[4]~24 , D[4]~24, spectrum, 1 +instance = comp, \D[6]~32 , D[6]~32, spectrum, 1 +instance = comp, \D[6]~33 , D[6]~33, spectrum, 1 +instance = comp, \D[6]~29 , D[6]~29, spectrum, 1 +instance = comp, \D[6]~30 , D[6]~30, spectrum, 1 +instance = comp, \D[6]~31 , D[6]~31, spectrum, 1 +instance = comp, \D[6]~50 , D[6]~50, spectrum, 1 +instance = comp, \D[6]~34 , D[6]~34, spectrum, 1 +instance = comp, \D[6]~35 , D[6]~35, spectrum, 1 instance = comp, \z80_|nM1_int~3 , z80_|nM1_int~3, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 , z80_|memory_ifc_|SYNTHESIZED_WIRE_16, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder, spectrum, 1 @@ -2866,6 +3076,7 @@ instance = comp, \z80_|memory_ifc_|DFFE_mreq_ff2 , z80_|memory_ifc_|DFFE_mreq_ff instance = comp, \z80_|memory_ifc_|nMREQ_out~0 , z80_|memory_ifc_|nMREQ_out~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|nMREQ_out~1 , z80_|memory_ifc_|nMREQ_out~1, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle~feeder , ula_|i2c_loader_|state.Idle~feeder, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[0]~15 , ula_|i2c_loader_|divider[0]~15, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[0] , ula_|i2c_loader_|divider[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[1]~5 , ula_|i2c_loader_|divider[1]~5, spectrum, 1 @@ -2874,36 +3085,42 @@ instance = comp, \ula_|i2c_loader_|divider[2]~7 , ula_|i2c_loader_|divider[2]~7, instance = comp, \ula_|i2c_loader_|divider[2] , ula_|i2c_loader_|divider[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[3]~9 , ula_|i2c_loader_|divider[3]~9, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[3] , ula_|i2c_loader_|divider[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[4]~11 , ula_|i2c_loader_|divider[4]~11, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[4] , ula_|i2c_loader_|divider[4], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[5]~13 , ula_|i2c_loader_|divider[5]~13, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[5] , ula_|i2c_loader_|divider[5], spectrum, 1 +instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|WideAnd0 , ula_|i2c_loader_|WideAnd0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Idle~feeder , ula_|i2c_loader_|state.Idle~feeder, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Idle , ula_|i2c_loader_|state.Idle, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase~0 , ula_|i2c_loader_|phase~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase[0] , ula_|i2c_loader_|phase[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|phase~1 , ula_|i2c_loader_|phase~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase[1] , ula_|i2c_loader_|phase[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2c_loader_|Mux42~0 , ula_|i2c_loader_|Mux42~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte~0 , ula_|i2c_loader_|nbyte~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~4 , ula_|i2c_loader_|nbit~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0]~7 , ula_|i2c_loader_|thisbyte[0]~7, spectrum, 1 +instance = comp, \I2C_SDAT~input , I2C_SDAT~input, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~1 , ula_|i2c_loader_|nbyte[0]~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~2 , ula_|i2c_loader_|nbyte[0]~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~3 , ula_|i2c_loader_|nbyte[0]~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte~4 , ula_|i2c_loader_|nbyte~4, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[1] , ula_|i2c_loader_|nbyte[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~4 , ula_|i2c_loader_|nbit[0]~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~6 , ula_|i2c_loader_|nbit~6, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 instance = comp, \ula_|i2c_loader_|nbit~0 , ula_|i2c_loader_|nbit~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbit[2] , ula_|i2c_loader_|nbit[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 @@ -2911,18 +3128,12 @@ instance = comp, \ula_|i2c_loader_|state.Idle~0 , ula_|i2c_loader_|state.Idle~0, instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0]~7 , ula_|i2c_loader_|thisbyte[0]~7, spectrum, 1 -instance = comp, \I2C_SDAT~input , I2C_SDAT~input, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0]~1 , ula_|i2c_loader_|nbyte[0]~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0]~2 , ula_|i2c_loader_|nbyte[0]~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0]~3 , ula_|i2c_loader_|nbyte[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Stop~0 , ula_|i2c_loader_|state.Stop~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Stop~1 , ula_|i2c_loader_|state.Stop~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Stop , ula_|i2c_loader_|state.Stop, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause~2 , ula_|i2c_loader_|state.Pause~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[1]~5 , ula_|i2c_loader_|nbyte[1]~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0]~5 , ula_|i2c_loader_|nbyte[0]~5, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0]~18 , ula_|i2c_loader_|thisbyte[0]~18, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0] , ula_|i2c_loader_|thisbyte[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[1]~10 , ula_|i2c_loader_|thisbyte[1]~10, spectrum, 1 @@ -2931,9 +3142,9 @@ instance = comp, \ula_|i2c_loader_|thisbyte[2]~12 , ula_|i2c_loader_|thisbyte[2] instance = comp, \ula_|i2c_loader_|thisbyte[2] , ula_|i2c_loader_|thisbyte[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[3]~14 , ula_|i2c_loader_|thisbyte[3]~14, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[3] , ula_|i2c_loader_|thisbyte[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|Equal2~0 , ula_|i2c_loader_|Equal2~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[4]~16 , ula_|i2c_loader_|thisbyte[4]~16, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[4] , ula_|i2c_loader_|thisbyte[4], spectrum, 1 +instance = comp, \ula_|i2c_loader_|Equal2~0 , ula_|i2c_loader_|Equal2~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause~3 , ula_|i2c_loader_|state.Pause~3, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out~0 , ula_|i2c_loader_|scl_out~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause~4 , ula_|i2c_loader_|state.Pause~4, spectrum, 1 @@ -2946,38 +3157,37 @@ instance = comp, \ula_|i2c_loader_|scl_out~1 , ula_|i2c_loader_|scl_out~1, spect instance = comp, \ula_|i2c_loader_|scl_out~2 , ula_|i2c_loader_|scl_out~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out , ula_|i2c_loader_|scl_out, spectrum, 1 instance = comp, \ula_|i2c_loader_|sda_out~_Duplicate_1 , ula_|i2c_loader_|sda_out~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|Mux35~0 , ula_|i2c_loader_|Mux35~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~4 , ula_|i2c_loader_|shiftreg~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~17 , ula_|i2c_loader_|shiftreg~17, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~24 , ula_|i2c_loader_|shiftreg[0]~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~27 , ula_|i2c_loader_|shiftreg[0]~27, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~28 , ula_|i2c_loader_|shiftreg[0]~28, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~6 , ula_|i2c_loader_|shiftreg~6, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~23 , ula_|i2c_loader_|shiftreg~23, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~25 , ula_|i2c_loader_|shiftreg[0]~25, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~6 , ula_|i2c_loader_|shiftreg[0]~6, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~7 , ula_|i2c_loader_|shiftreg[0]~7, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~8 , ula_|i2c_loader_|shiftreg[0]~8, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~24 , ula_|i2c_loader_|shiftreg~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6]~9 , ula_|i2c_loader_|shiftreg[6]~9, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6]~10 , ula_|i2c_loader_|shiftreg[6]~10, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6]~11 , ula_|i2c_loader_|shiftreg[6]~11, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[6]~12 , ula_|i2c_loader_|shiftreg[6]~12, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[1] , ula_|i2c_loader_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~17 , ula_|i2c_loader_|shiftreg~17, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~27 , ula_|i2c_loader_|shiftreg~27, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~26 , ula_|i2c_loader_|shiftreg~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~25 , ula_|i2c_loader_|shiftreg~25, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[4] , ula_|i2c_loader_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 +instance = comp, \ula_|i2c_loader_|Mux35~0 , ula_|i2c_loader_|Mux35~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~12 , ula_|i2c_loader_|shiftreg~12, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[5] , ula_|i2c_loader_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~9 , ula_|i2c_loader_|shiftreg~9, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~8 , ula_|i2c_loader_|shiftreg~8, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6] , ula_|i2c_loader_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[7]~5 , ula_|i2c_loader_|shiftreg[7]~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[7]~7 , ula_|i2c_loader_|shiftreg[7]~7, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[7] , ula_|i2c_loader_|shiftreg[7], spectrum, 1 instance = comp, \ula_|i2c_loader_|sda_out~0 , ula_|i2c_loader_|sda_out~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|sda_out~1 , ula_|i2c_loader_|sda_out~1, spectrum, 1 @@ -2987,10 +3197,35 @@ instance = comp, \ula_|i2c_loader_|sda_out~4 , ula_|i2c_loader_|sda_out~4, spect instance = comp, \ula_|i2c_loader_|sda_out , ula_|i2c_loader_|sda_out, spectrum, 1 instance = comp, \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 , sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1, spectrum, 1 instance = comp, \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, spectrum, 1 -instance = comp, \sdram_|Mux38~0 , sdram_|Mux38~0, spectrum, 1 +instance = comp, \sdram_|Mux4~3 , sdram_|Mux4~3, spectrum, 1 +instance = comp, \sdram_|Mux4~0 , sdram_|Mux4~0, spectrum, 1 +instance = comp, \sdram_|r.address[3]~6 , sdram_|r.address[3]~6, spectrum, 1 +instance = comp, \sdram_|Mux7~2 , sdram_|Mux7~2, spectrum, 1 +instance = comp, \sdram_|Mux23~0 , sdram_|Mux23~0, spectrum, 1 +instance = comp, \sdram_|Mux13~7 , sdram_|Mux13~7, spectrum, 1 +instance = comp, \sdram_|r.act_row[2] , sdram_|r.act_row[2], spectrum, 1 +instance = comp, \sdram_|r.act_row[3] , sdram_|r.act_row[3], spectrum, 1 +instance = comp, \sdram_|Equal7~1 , sdram_|Equal7~1, spectrum, 1 +instance = comp, \sdram_|r.act_row[4] , sdram_|r.act_row[4], spectrum, 1 +instance = comp, \sdram_|Mux39~0 , sdram_|Mux39~0, spectrum, 1 +instance = comp, \sdram_|Mux39~1 , sdram_|Mux39~1, spectrum, 1 +instance = comp, \sdram_|Mux39~2 , sdram_|Mux39~2, spectrum, 1 +instance = comp, \sdram_|r.wr_pending , sdram_|r.wr_pending, spectrum, 1 +instance = comp, \sdram_|Mux38~3 , sdram_|Mux38~3, spectrum, 1 +instance = comp, \sdram_|Mux38~2 , sdram_|Mux38~2, spectrum, 1 instance = comp, \sdram_|r.rd_pending , sdram_|r.rd_pending, spectrum, 1 +instance = comp, \sdram_|n~3 , sdram_|n~3, spectrum, 1 +instance = comp, \sdram_|n~4 , sdram_|n~4, spectrum, 1 +instance = comp, \sdram_|Mux10~9 , sdram_|Mux10~9, spectrum, 1 +instance = comp, \sdram_|Mux7~1 , sdram_|Mux7~1, spectrum, 1 +instance = comp, \sdram_|Mux7~3 , sdram_|Mux7~3, spectrum, 1 +instance = comp, \sdram_|Mux7~4 , sdram_|Mux7~4, spectrum, 1 +instance = comp, \sdram_|Mux7~5 , sdram_|Mux7~5, spectrum, 1 +instance = comp, \sdram_|Mux7~6 , sdram_|Mux7~6, spectrum, 1 +instance = comp, \sdram_|r.state[5] , sdram_|r.state[5], spectrum, 1 +instance = comp, \sdram_|Mux13~8 , sdram_|Mux13~8, spectrum, 1 instance = comp, \sdram_|r.rf_counter[0]~12 , sdram_|r.rf_counter[0]~12, spectrum, 1 -instance = comp, \sdram_|r.rf_counter[3]~32 , sdram_|r.rf_counter[3]~32, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[8]~32 , sdram_|r.rf_counter[8]~32, spectrum, 1 instance = comp, \sdram_|r.rf_counter[0] , sdram_|r.rf_counter[0], spectrum, 1 instance = comp, \sdram_|r.rf_counter[1]~14 , sdram_|r.rf_counter[1]~14, spectrum, 1 instance = comp, \sdram_|r.rf_counter[1] , sdram_|r.rf_counter[1], spectrum, 1 @@ -2998,6 +3233,7 @@ instance = comp, \sdram_|r.rf_counter[2]~16 , sdram_|r.rf_counter[2]~16, spectru instance = comp, \sdram_|r.rf_counter[2] , sdram_|r.rf_counter[2], spectrum, 1 instance = comp, \sdram_|r.rf_counter[3]~18 , sdram_|r.rf_counter[3]~18, spectrum, 1 instance = comp, \sdram_|r.rf_counter[3] , sdram_|r.rf_counter[3], spectrum, 1 +instance = comp, \sdram_|Equal0~0 , sdram_|Equal0~0, spectrum, 1 instance = comp, \sdram_|r.rf_counter[4]~20 , sdram_|r.rf_counter[4]~20, spectrum, 1 instance = comp, \sdram_|r.rf_counter[4] , sdram_|r.rf_counter[4], spectrum, 1 instance = comp, \sdram_|r.rf_counter[5]~22 , sdram_|r.rf_counter[5]~22, spectrum, 1 @@ -3006,116 +3242,91 @@ instance = comp, \sdram_|r.rf_counter[6]~24 , sdram_|r.rf_counter[6]~24, spectru instance = comp, \sdram_|r.rf_counter[6] , sdram_|r.rf_counter[6], spectrum, 1 instance = comp, \sdram_|r.rf_counter[7]~26 , sdram_|r.rf_counter[7]~26, spectrum, 1 instance = comp, \sdram_|r.rf_counter[7] , sdram_|r.rf_counter[7], spectrum, 1 -instance = comp, \sdram_|Equal0~1 , sdram_|Equal0~1, spectrum, 1 instance = comp, \sdram_|r.rf_counter[8]~28 , sdram_|r.rf_counter[8]~28, spectrum, 1 instance = comp, \sdram_|r.rf_counter[8] , sdram_|r.rf_counter[8], spectrum, 1 -instance = comp, \sdram_|Equal0~0 , sdram_|Equal0~0, spectrum, 1 instance = comp, \sdram_|r.rf_counter[9]~30 , sdram_|r.rf_counter[9]~30, spectrum, 1 instance = comp, \sdram_|r.rf_counter[9] , sdram_|r.rf_counter[9], spectrum, 1 +instance = comp, \sdram_|Equal0~1 , sdram_|Equal0~1, spectrum, 1 instance = comp, \sdram_|Equal0~2 , sdram_|Equal0~2, spectrum, 1 -instance = comp, \sdram_|Mux13~8 , sdram_|Mux13~8, spectrum, 1 instance = comp, \sdram_|Mux37~0 , sdram_|Mux37~0, spectrum, 1 instance = comp, \sdram_|r.rf_pending , sdram_|r.rf_pending, spectrum, 1 -instance = comp, \sdram_|Mux4~0 , sdram_|Mux4~0, spectrum, 1 instance = comp, \sdram_|Mux4~1 , sdram_|Mux4~1, spectrum, 1 +instance = comp, \sdram_|Mux4~4 , sdram_|Mux4~4, spectrum, 1 instance = comp, \sdram_|Mux4~2 , sdram_|Mux4~2, spectrum, 1 -instance = comp, \sdram_|Mux4~3 , sdram_|Mux4~3, spectrum, 1 +instance = comp, \sdram_|Mux4~5 , sdram_|Mux4~5, spectrum, 1 instance = comp, \sdram_|r.state[8] , sdram_|r.state[8], spectrum, 1 -instance = comp, \sdram_|r.act_row[1]~0 , sdram_|r.act_row[1]~0, spectrum, 1 -instance = comp, \sdram_|process_0~2 , sdram_|process_0~2, spectrum, 1 -instance = comp, \sdram_|r.act_row[1]~1 , sdram_|r.act_row[1]~1, spectrum, 1 -instance = comp, \sdram_|r.act_row[4] , sdram_|r.act_row[4], spectrum, 1 -instance = comp, \sdram_|r.act_row[3] , sdram_|r.act_row[3], spectrum, 1 -instance = comp, \sdram_|r.act_row[2]~feeder , sdram_|r.act_row[2]~feeder, spectrum, 1 -instance = comp, \sdram_|r.act_row[2] , sdram_|r.act_row[2], spectrum, 1 -instance = comp, \sdram_|Equal7~1 , sdram_|Equal7~1, spectrum, 1 +instance = comp, \sdram_|process_0~4 , sdram_|process_0~4, spectrum, 1 +instance = comp, \sdram_|r.act_row[2]~0 , sdram_|r.act_row[2]~0, spectrum, 1 +instance = comp, \sdram_|r.act_row[2]~1 , sdram_|r.act_row[2]~1, spectrum, 1 instance = comp, \sdram_|r.act_row[1] , sdram_|r.act_row[1], spectrum, 1 instance = comp, \sdram_|r.act_row[0] , sdram_|r.act_row[0], spectrum, 1 instance = comp, \sdram_|Equal7~0 , sdram_|Equal7~0, spectrum, 1 instance = comp, \sdram_|Equal7~2 , sdram_|Equal7~2, spectrum, 1 -instance = comp, \sdram_|Mux39~0 , sdram_|Mux39~0, spectrum, 1 -instance = comp, \sdram_|Mux39~1 , sdram_|Mux39~1, spectrum, 1 -instance = comp, \sdram_|Mux39~2 , sdram_|Mux39~2, spectrum, 1 -instance = comp, \sdram_|r.wr_pending , sdram_|r.wr_pending, spectrum, 1 -instance = comp, \sdram_|Mux9~8 , sdram_|Mux9~8, spectrum, 1 -instance = comp, \sdram_|Mux9~9 , sdram_|Mux9~9, spectrum, 1 -instance = comp, \sdram_|Mux6~3 , sdram_|Mux6~3, spectrum, 1 instance = comp, \sdram_|Mux6~4 , sdram_|Mux6~4, spectrum, 1 +instance = comp, \sdram_|Mux9~5 , sdram_|Mux9~5, spectrum, 1 +instance = comp, \sdram_|Mux9~4 , sdram_|Mux9~4, spectrum, 1 +instance = comp, \sdram_|Mux6~3 , sdram_|Mux6~3, spectrum, 1 instance = comp, \sdram_|Mux6~2 , sdram_|Mux6~2, spectrum, 1 instance = comp, \sdram_|Mux6~5 , sdram_|Mux6~5, spectrum, 1 -instance = comp, \sdram_|process_0~3 , sdram_|process_0~3, spectrum, 1 +instance = comp, \sdram_|process_0~2 , sdram_|process_0~2, spectrum, 1 instance = comp, \sdram_|Mux6~0 , sdram_|Mux6~0, spectrum, 1 instance = comp, \sdram_|Mux6~1 , sdram_|Mux6~1, spectrum, 1 instance = comp, \sdram_|Mux6~6 , sdram_|Mux6~6, spectrum, 1 instance = comp, \sdram_|r.state[6] , sdram_|r.state[6], spectrum, 1 -instance = comp, \sdram_|r.address[3]~6 , sdram_|r.address[3]~6, spectrum, 1 -instance = comp, \sdram_|Mux7~2 , sdram_|Mux7~2, spectrum, 1 -instance = comp, \sdram_|n~3 , sdram_|n~3, spectrum, 1 -instance = comp, \sdram_|Mux7~3 , sdram_|Mux7~3, spectrum, 1 -instance = comp, \sdram_|Mux7~4 , sdram_|Mux7~4, spectrum, 1 -instance = comp, \sdram_|Mux7~5 , sdram_|Mux7~5, spectrum, 1 -instance = comp, \sdram_|Mux23~0 , sdram_|Mux23~0, spectrum, 1 -instance = comp, \sdram_|Mux13~7 , sdram_|Mux13~7, spectrum, 1 -instance = comp, \sdram_|Mux10~10 , sdram_|Mux10~10, spectrum, 1 -instance = comp, \sdram_|Mux7~1 , sdram_|Mux7~1, spectrum, 1 -instance = comp, \sdram_|Mux7~6 , sdram_|Mux7~6, spectrum, 1 -instance = comp, \sdram_|r.state[5] , sdram_|r.state[5], spectrum, 1 +instance = comp, \sdram_|Mux5~7 , sdram_|Mux5~7, spectrum, 1 +instance = comp, \sdram_|Mux5~8 , sdram_|Mux5~8, spectrum, 1 instance = comp, \sdram_|Mux5~2 , sdram_|Mux5~2, spectrum, 1 instance = comp, \sdram_|Mux5~10 , sdram_|Mux5~10, spectrum, 1 instance = comp, \sdram_|Mux5~3 , sdram_|Mux5~3, spectrum, 1 instance = comp, \sdram_|Mux5~4 , sdram_|Mux5~4, spectrum, 1 -instance = comp, \sdram_|Mux5~7 , sdram_|Mux5~7, spectrum, 1 -instance = comp, \sdram_|Mux5~8 , sdram_|Mux5~8, spectrum, 1 instance = comp, \sdram_|Mux5~5 , sdram_|Mux5~5, spectrum, 1 instance = comp, \sdram_|Mux5~6 , sdram_|Mux5~6, spectrum, 1 instance = comp, \sdram_|Mux5~9 , sdram_|Mux5~9, spectrum, 1 instance = comp, \sdram_|r.state[7] , sdram_|r.state[7], spectrum, 1 instance = comp, \sdram_|n~2 , sdram_|n~2, spectrum, 1 -instance = comp, \sdram_|Mux8~3 , sdram_|Mux8~3, spectrum, 1 -instance = comp, \sdram_|Mux8~4 , sdram_|Mux8~4, spectrum, 1 -instance = comp, \sdram_|Mux9~10 , sdram_|Mux9~10, spectrum, 1 -instance = comp, \sdram_|r.init_counter[0]~0 , sdram_|r.init_counter[0]~0, spectrum, 1 -instance = comp, \sdram_|r.init_counter[0] , sdram_|r.init_counter[0], spectrum, 1 -instance = comp, \sdram_|Add1~1 , sdram_|Add1~1, spectrum, 1 -instance = comp, \sdram_|Add1~2 , sdram_|Add1~2, spectrum, 1 -instance = comp, \sdram_|r.init_counter[1] , sdram_|r.init_counter[1], spectrum, 1 -instance = comp, \sdram_|Add1~4 , sdram_|Add1~4, spectrum, 1 -instance = comp, \sdram_|r.init_counter[2] , sdram_|r.init_counter[2], spectrum, 1 -instance = comp, \sdram_|Add1~6 , sdram_|Add1~6, spectrum, 1 -instance = comp, \sdram_|r.init_counter[3]~1 , sdram_|r.init_counter[3]~1, spectrum, 1 -instance = comp, \sdram_|r.init_counter[3] , sdram_|r.init_counter[3], spectrum, 1 -instance = comp, \sdram_|Add1~8 , sdram_|Add1~8, spectrum, 1 -instance = comp, \sdram_|r.init_counter[4] , sdram_|r.init_counter[4], spectrum, 1 -instance = comp, \sdram_|Add1~10 , sdram_|Add1~10, spectrum, 1 -instance = comp, \sdram_|r.init_counter[5] , sdram_|r.init_counter[5], spectrum, 1 -instance = comp, \sdram_|Add1~12 , sdram_|Add1~12, spectrum, 1 -instance = comp, \sdram_|r.init_counter[6] , sdram_|r.init_counter[6], spectrum, 1 -instance = comp, \sdram_|Add1~14 , sdram_|Add1~14, spectrum, 1 -instance = comp, \sdram_|r.init_counter[7] , sdram_|r.init_counter[7], spectrum, 1 -instance = comp, \sdram_|Add1~16 , sdram_|Add1~16, spectrum, 1 -instance = comp, \sdram_|r.init_counter[8] , sdram_|r.init_counter[8], spectrum, 1 -instance = comp, \sdram_|Add1~18 , sdram_|Add1~18, spectrum, 1 -instance = comp, \sdram_|r.init_counter[9] , sdram_|r.init_counter[9], spectrum, 1 -instance = comp, \sdram_|Add1~20 , sdram_|Add1~20, spectrum, 1 -instance = comp, \sdram_|r.init_counter[10] , sdram_|r.init_counter[10], spectrum, 1 -instance = comp, \sdram_|Equal2~0 , sdram_|Equal2~0, spectrum, 1 -instance = comp, \sdram_|Equal2~1 , sdram_|Equal2~1, spectrum, 1 -instance = comp, \sdram_|Add1~22 , sdram_|Add1~22, spectrum, 1 -instance = comp, \sdram_|r.init_counter[11] , sdram_|r.init_counter[11], spectrum, 1 -instance = comp, \sdram_|Add1~24 , sdram_|Add1~24, spectrum, 1 -instance = comp, \sdram_|r.init_counter[12] , sdram_|r.init_counter[12], spectrum, 1 -instance = comp, \sdram_|Add1~26 , sdram_|Add1~26, spectrum, 1 -instance = comp, \sdram_|r.init_counter[13] , sdram_|r.init_counter[13], spectrum, 1 -instance = comp, \sdram_|Add1~28 , sdram_|Add1~28, spectrum, 1 -instance = comp, \sdram_|r.init_counter[14] , sdram_|r.init_counter[14], spectrum, 1 -instance = comp, \sdram_|process_0~5 , sdram_|process_0~5, spectrum, 1 -instance = comp, \sdram_|Equal2~2 , sdram_|Equal2~2, spectrum, 1 -instance = comp, \sdram_|Mux9~11 , sdram_|Mux9~11, spectrum, 1 -instance = comp, \sdram_|Mux9~12 , sdram_|Mux9~12, spectrum, 1 -instance = comp, \sdram_|Mux9~13 , sdram_|Mux9~13, spectrum, 1 -instance = comp, \sdram_|Mux8~0 , sdram_|Mux8~0, spectrum, 1 +instance = comp, \sdram_|Mux8~6 , sdram_|Mux8~6, spectrum, 1 +instance = comp, \sdram_|Mux8~7 , sdram_|Mux8~7, spectrum, 1 instance = comp, \sdram_|Mux8~1 , sdram_|Mux8~1, spectrum, 1 instance = comp, \sdram_|Mux8~2 , sdram_|Mux8~2, spectrum, 1 +instance = comp, \sdram_|Mux8~3 , sdram_|Mux8~3, spectrum, 1 +instance = comp, \sdram_|r.init_counter[0]~44 , sdram_|r.init_counter[0]~44, spectrum, 1 +instance = comp, \sdram_|r.init_counter[0] , sdram_|r.init_counter[0], spectrum, 1 +instance = comp, \sdram_|r.init_counter[1]~15 , sdram_|r.init_counter[1]~15, spectrum, 1 +instance = comp, \sdram_|r.init_counter[1]~16 , sdram_|r.init_counter[1]~16, spectrum, 1 +instance = comp, \sdram_|r.init_counter[1] , sdram_|r.init_counter[1], spectrum, 1 +instance = comp, \sdram_|r.init_counter[2]~18 , sdram_|r.init_counter[2]~18, spectrum, 1 +instance = comp, \sdram_|r.init_counter[2] , sdram_|r.init_counter[2], spectrum, 1 +instance = comp, \sdram_|r.init_counter[3]~20 , sdram_|r.init_counter[3]~20, spectrum, 1 +instance = comp, \sdram_|r.init_counter[3] , sdram_|r.init_counter[3], spectrum, 1 +instance = comp, \sdram_|r.init_counter[4]~22 , sdram_|r.init_counter[4]~22, spectrum, 1 +instance = comp, \sdram_|r.init_counter[4] , sdram_|r.init_counter[4], spectrum, 1 +instance = comp, \sdram_|r.init_counter[5]~24 , sdram_|r.init_counter[5]~24, spectrum, 1 +instance = comp, \sdram_|r.init_counter[5] , sdram_|r.init_counter[5], spectrum, 1 +instance = comp, \sdram_|r.init_counter[6]~26 , sdram_|r.init_counter[6]~26, spectrum, 1 +instance = comp, \sdram_|r.init_counter[6] , sdram_|r.init_counter[6], spectrum, 1 +instance = comp, \sdram_|r.init_counter[7]~28 , sdram_|r.init_counter[7]~28, spectrum, 1 +instance = comp, \sdram_|r.init_counter[7] , sdram_|r.init_counter[7], spectrum, 1 +instance = comp, \sdram_|r.init_counter[8]~30 , sdram_|r.init_counter[8]~30, spectrum, 1 +instance = comp, \sdram_|r.init_counter[8] , sdram_|r.init_counter[8], spectrum, 1 +instance = comp, \sdram_|r.init_counter[9]~32 , sdram_|r.init_counter[9]~32, spectrum, 1 +instance = comp, \sdram_|r.init_counter[9] , sdram_|r.init_counter[9], spectrum, 1 +instance = comp, \sdram_|r.init_counter[10]~34 , sdram_|r.init_counter[10]~34, spectrum, 1 +instance = comp, \sdram_|r.init_counter[10] , sdram_|r.init_counter[10], spectrum, 1 +instance = comp, \sdram_|r.init_counter[11]~36 , sdram_|r.init_counter[11]~36, spectrum, 1 +instance = comp, \sdram_|r.init_counter[11] , sdram_|r.init_counter[11], spectrum, 1 +instance = comp, \sdram_|r.init_counter[12]~38 , sdram_|r.init_counter[12]~38, spectrum, 1 +instance = comp, \sdram_|r.init_counter[12] , sdram_|r.init_counter[12], spectrum, 1 +instance = comp, \sdram_|r.init_counter[13]~40 , sdram_|r.init_counter[13]~40, spectrum, 1 +instance = comp, \sdram_|r.init_counter[13] , sdram_|r.init_counter[13], spectrum, 1 +instance = comp, \sdram_|r.init_counter[14]~42 , sdram_|r.init_counter[14]~42, spectrum, 1 +instance = comp, \sdram_|r.init_counter[14] , sdram_|r.init_counter[14], spectrum, 1 +instance = comp, \sdram_|Equal2~1 , sdram_|Equal2~1, spectrum, 1 +instance = comp, \sdram_|process_0~5 , sdram_|process_0~5, spectrum, 1 +instance = comp, \sdram_|Equal2~0 , sdram_|Equal2~0, spectrum, 1 +instance = comp, \sdram_|Equal2~2 , sdram_|Equal2~2, spectrum, 1 +instance = comp, \sdram_|Mux8~0 , sdram_|Mux8~0, spectrum, 1 +instance = comp, \sdram_|Mux8~4 , sdram_|Mux8~4, spectrum, 1 +instance = comp, \sdram_|Mux8~5 , sdram_|Mux8~5, spectrum, 1 instance = comp, \sdram_|r.state[4] , sdram_|r.state[4], spectrum, 1 instance = comp, \sdram_|Mux72~0 , sdram_|Mux72~0, spectrum, 1 instance = comp, \sdram_|Mux72~1 , sdram_|Mux72~1, spectrum, 1 @@ -3130,13 +3341,14 @@ instance = comp, \sdram_|Mux1~1 , sdram_|Mux1~1, spectrum, 1 instance = comp, \sdram_|Mux0~0 , sdram_|Mux0~0, spectrum, 1 instance = comp, \sdram_|Mux0~1 , sdram_|Mux0~1, spectrum, 1 instance = comp, \sdram_|Mux73~0 , sdram_|Mux73~0, spectrum, 1 -instance = comp, \sdram_|Mux73~1 , sdram_|Mux73~1, spectrum, 1 instance = comp, \sdram_|Mux74~0 , sdram_|Mux74~0, spectrum, 1 instance = comp, \sdram_|Mux74~1 , sdram_|Mux74~1, spectrum, 1 instance = comp, \sdram_|Mux75~0 , sdram_|Mux75~0, spectrum, 1 +instance = comp, \LED~0 , LED~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r~0 , ula_|i2s_intf_|mclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r~_Duplicate_1 , ula_|i2s_intf_|mclk_r~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r , ula_|i2s_intf_|mclk_r, spectrum, 1 +instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2 , ula_|i2s_intf_|lrclk_r~_Duplicate_2, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add0~1 , ula_|i2s_intf_|Add0~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add0~2 , ula_|i2s_intf_|Add0~2, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrdivider~2 , ula_|i2s_intf_|lrdivider~2, spectrum, 1 @@ -3168,27 +3380,10 @@ instance = comp, \ula_|i2s_intf_|lrdivider[9]~3 , ula_|i2s_intf_|lrdivider[9]~3, instance = comp, \ula_|i2s_intf_|lrdivider[9] , ula_|i2s_intf_|lrdivider[9], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~0 , ula_|i2s_intf_|Equal0~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~2 , ula_|i2s_intf_|Equal0~2, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2 , ula_|i2s_intf_|lrclk_r~_Duplicate_2, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~0 , ula_|i2s_intf_|lrclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r , ula_|i2s_intf_|lrclk_r, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_1 , ula_|i2s_intf_|lrclk_r~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[0]~5 , ula_|i2s_intf_|bitcount[0]~5, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder , ula_|i2s_intf_|bclk_r~_Duplicate_1feeder, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1 , ula_|i2s_intf_|bclk_r~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[4]~15 , ula_|i2s_intf_|bitcount[4]~15, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[0] , ula_|i2s_intf_|bitcount[0], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[1]~7 , ula_|i2s_intf_|bitcount[1]~7, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[1] , ula_|i2s_intf_|bitcount[1], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[2]~9 , ula_|i2s_intf_|bitcount[2]~9, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[2] , ula_|i2s_intf_|bitcount[2], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[3]~11 , ula_|i2s_intf_|bitcount[3]~11, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[3] , ula_|i2s_intf_|bitcount[3], spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[4]~13 , ula_|i2s_intf_|bitcount[4]~13, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bitcount[4] , ula_|i2s_intf_|bitcount[4], spectrum, 1 -instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[1]~1 , ula_|i2s_intf_|shiftreg[1]~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~7 , ula_|i2s_intf_|Add2~7, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~8 , ula_|i2s_intf_|Add2~8, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~20 , ula_|i2s_intf_|Add2~20, spectrum, 1 @@ -3203,72 +3398,83 @@ instance = comp, \ula_|i2s_intf_|Add2~14 , ula_|i2s_intf_|Add2~14, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~16 , ula_|i2s_intf_|Add2~16, spectrum, 1 instance = comp, \ula_|i2s_intf_|bdivider[4] , ula_|i2s_intf_|bdivider[4], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~0 , ula_|i2s_intf_|Equal1~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~1 , ula_|i2s_intf_|Equal1~1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1 , ula_|i2s_intf_|bclk_r~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[4]~9 , ula_|i2s_intf_|bitcount[4]~9, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[0] , ula_|i2s_intf_|bitcount[0], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[1]~7 , ula_|i2s_intf_|bitcount[1]~7, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[1] , ula_|i2s_intf_|bitcount[1], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[2]~10 , ula_|i2s_intf_|bitcount[2]~10, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[2] , ula_|i2s_intf_|bitcount[2], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[3]~12 , ula_|i2s_intf_|bitcount[3]~12, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[3] , ula_|i2s_intf_|bitcount[3], spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[4]~14 , ula_|i2s_intf_|bitcount[4]~14, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bitcount[4] , ula_|i2s_intf_|bitcount[4], spectrum, 1 +instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|LessThan0~1 , ula_|i2s_intf_|LessThan0~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~0 , ula_|i2s_intf_|bclk_r~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bclk_r~1 , ula_|i2s_intf_|bclk_r~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r , ula_|i2s_intf_|bclk_r, spectrum, 1 instance = comp, \ula_|pcm_outl[13]~feeder , ula_|pcm_outl[13]~feeder, spectrum, 1 instance = comp, \ula_|always0~2 , ula_|always0~2, spectrum, 1 instance = comp, \ula_|always0~3 , ula_|always0~3, spectrum, 1 instance = comp, \ula_|pcm_outl[13] , ula_|pcm_outl[13], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[0]~19 , ula_|i2s_intf_|shiftreg[0]~19, spectrum, 1 -instance = comp, \AUD_ADCDAT~input , AUD_ADCDAT~input, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[0]~20 , ula_|i2s_intf_|shiftreg[0]~20, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[0] , ula_|i2s_intf_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~18 , ula_|i2s_intf_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[1]~2 , ula_|i2s_intf_|shiftreg[1]~2, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[1] , ula_|i2s_intf_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~17 , ula_|i2s_intf_|shiftreg~17, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[2] , ula_|i2s_intf_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~16 , ula_|i2s_intf_|shiftreg~16, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[3] , ula_|i2s_intf_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~15 , ula_|i2s_intf_|shiftreg~15, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[4] , ula_|i2s_intf_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~14 , ula_|i2s_intf_|shiftreg~14, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[5] , ula_|i2s_intf_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~13 , ula_|i2s_intf_|shiftreg~13, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[6] , ula_|i2s_intf_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~12 , ula_|i2s_intf_|shiftreg~12, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[7] , ula_|i2s_intf_|shiftreg[7], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~11 , ula_|i2s_intf_|shiftreg~11, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[8] , ula_|i2s_intf_|shiftreg[8], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~10 , ula_|i2s_intf_|shiftreg~10, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[9] , ula_|i2s_intf_|shiftreg[9], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~9 , ula_|i2s_intf_|shiftreg~9, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[10] , ula_|i2s_intf_|shiftreg[10], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~8 , ula_|i2s_intf_|shiftreg~8, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[11] , ula_|i2s_intf_|shiftreg[11], spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg~7 , ula_|i2s_intf_|shiftreg~7, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[12] , ula_|i2s_intf_|shiftreg[12], spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INR[14]~0 , ula_|i2s_intf_|PCM_INR[14]~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INR[14] , ula_|i2s_intf_|PCM_INR[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INL[14]~0 , ula_|i2s_intf_|PCM_INL[14]~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INL[14] , ula_|i2s_intf_|PCM_INL[14], spectrum, 1 instance = comp, \ula_|pcm_outr~0 , ula_|pcm_outr~0, spectrum, 1 instance = comp, \ula_|pcm_outl[12] , ula_|pcm_outl[12], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[0]~18 , ula_|i2s_intf_|shiftreg[0]~18, spectrum, 1 +instance = comp, \AUD_ADCDAT~input , AUD_ADCDAT~input, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[0]~19 , ula_|i2s_intf_|shiftreg[0]~19, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[0] , ula_|i2s_intf_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~17 , ula_|i2s_intf_|shiftreg~17, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[7]~1 , ula_|i2s_intf_|shiftreg[7]~1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[1] , ula_|i2s_intf_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~16 , ula_|i2s_intf_|shiftreg~16, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[2] , ula_|i2s_intf_|shiftreg[2], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~15 , ula_|i2s_intf_|shiftreg~15, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[3] , ula_|i2s_intf_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~14 , ula_|i2s_intf_|shiftreg~14, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[4] , ula_|i2s_intf_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~13 , ula_|i2s_intf_|shiftreg~13, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[5] , ula_|i2s_intf_|shiftreg[5], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~12 , ula_|i2s_intf_|shiftreg~12, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[6] , ula_|i2s_intf_|shiftreg[6], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~11 , ula_|i2s_intf_|shiftreg~11, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[7] , ula_|i2s_intf_|shiftreg[7], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~10 , ula_|i2s_intf_|shiftreg~10, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[8] , ula_|i2s_intf_|shiftreg[8], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~9 , ula_|i2s_intf_|shiftreg~9, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[9] , ula_|i2s_intf_|shiftreg[9], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~8 , ula_|i2s_intf_|shiftreg~8, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[10] , ula_|i2s_intf_|shiftreg[10], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~7 , ula_|i2s_intf_|shiftreg~7, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[11] , ula_|i2s_intf_|shiftreg[11], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~6 , ula_|i2s_intf_|shiftreg~6, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[13] , ula_|i2s_intf_|shiftreg[13], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[12] , ula_|i2s_intf_|shiftreg[12], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~5 , ula_|i2s_intf_|shiftreg~5, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[14] , ula_|i2s_intf_|shiftreg[14], spectrum, 1 -instance = comp, \ula_|pcm_outl[14]~feeder , ula_|pcm_outl[14]~feeder, spectrum, 1 -instance = comp, \ula_|pcm_outl[14] , ula_|pcm_outl[14], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[13] , ula_|i2s_intf_|shiftreg[13], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~4 , ula_|i2s_intf_|shiftreg~4, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[15] , ula_|i2s_intf_|shiftreg[15], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[14] , ula_|i2s_intf_|shiftreg[14], spectrum, 1 +instance = comp, \ula_|pcm_outl[14] , ula_|pcm_outl[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~3 , ula_|i2s_intf_|shiftreg~3, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[15] , ula_|i2s_intf_|shiftreg[15], spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg~2 , ula_|i2s_intf_|shiftreg~2, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[16] , ula_|i2s_intf_|shiftreg[16], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~0 , ula_|i2s_intf_|shiftreg~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[17] , ula_|i2s_intf_|shiftreg[17], spectrum, 1 -instance = comp, \ula_|border[1]~feeder , ula_|border[1]~feeder, spectrum, 1 -instance = comp, \ula_|border[1] , ula_|border[1], spectrum, 1 -instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 -instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 -instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[7]~feeder , ula_|video_|attr_prefetch[7]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|Decoder0~1 , ula_|video_|Decoder0~1, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[7] , ula_|video_|attr_prefetch[7], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 instance = comp, \ula_|video_|Decoder0~0 , ula_|video_|Decoder0~0, spectrum, 1 +instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 +instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[7] , ula_|video_|attr_prefetch[7], spectrum, 1 instance = comp, \ula_|video_|attr[7] , ula_|video_|attr[7], spectrum, 1 instance = comp, \ula_|video_|frame[0]~12 , ula_|video_|frame[0]~12, spectrum, 1 instance = comp, \ula_|video_|frame[0] , ula_|video_|frame[0], spectrum, 1 @@ -3279,75 +3485,67 @@ instance = comp, \ula_|video_|frame[2] , ula_|video_|frame[2], spectrum, 1 instance = comp, \ula_|video_|frame[3]~8 , ula_|video_|frame[3]~8, spectrum, 1 instance = comp, \ula_|video_|frame[3] , ula_|video_|frame[3], spectrum, 1 instance = comp, \ula_|video_|frame[4]~10 , ula_|video_|frame[4]~10, spectrum, 1 +instance = comp, \ula_|video_|frame[4]~feeder , ula_|video_|frame[4]~feeder, spectrum, 1 instance = comp, \ula_|video_|frame[4] , ula_|video_|frame[4], spectrum, 1 instance = comp, \ula_|video_|inverted , ula_|video_|inverted, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[6]~feeder , ula_|video_|bits_prefetch[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|Decoder0~2 , ula_|video_|Decoder0~2, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[6] , ula_|video_|bits_prefetch[6], spectrum, 1 -instance = comp, \ula_|video_|bits[6] , ula_|video_|bits[6], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[4]~feeder , ula_|video_|bits_prefetch[4]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[4] , ula_|video_|bits_prefetch[4], spectrum, 1 -instance = comp, \ula_|video_|bits[4] , ula_|video_|bits[4], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[5]~feeder , ula_|video_|bits_prefetch[5]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[5] , ula_|video_|bits_prefetch[5], spectrum, 1 -instance = comp, \ula_|video_|bits[5]~feeder , ula_|video_|bits[5]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits[5] , ula_|video_|bits[5], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[7]~feeder , ula_|video_|bits_prefetch[7]~feeder, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[7] , ula_|video_|bits_prefetch[7], spectrum, 1 -instance = comp, \ula_|video_|bits[7] , ula_|video_|bits[7], spectrum, 1 -instance = comp, \ula_|video_|Mux0~0 , ula_|video_|Mux0~0, spectrum, 1 -instance = comp, \ula_|video_|Mux0~1 , ula_|video_|Mux0~1, spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[2]~feeder , ula_|video_|bits_prefetch[2]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[2] , ula_|video_|bits_prefetch[2], spectrum, 1 -instance = comp, \ula_|video_|bits[2]~feeder , ula_|video_|bits[2]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits[2] , ula_|video_|bits[2], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[0]~feeder , ula_|video_|bits_prefetch[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[0] , ula_|video_|bits_prefetch[0], spectrum, 1 instance = comp, \ula_|video_|bits[0] , ula_|video_|bits[0], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[1]~feeder , ula_|video_|bits_prefetch[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[1] , ula_|video_|bits_prefetch[1], spectrum, 1 instance = comp, \ula_|video_|bits[1]~feeder , ula_|video_|bits[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits[1] , ula_|video_|bits[1], spectrum, 1 -instance = comp, \ula_|video_|bits_prefetch[3]~feeder , ula_|video_|bits_prefetch[3]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[3] , ula_|video_|bits_prefetch[3], spectrum, 1 instance = comp, \ula_|video_|bits[3] , ula_|video_|bits[3], spectrum, 1 instance = comp, \ula_|video_|Mux0~2 , ula_|video_|Mux0~2, spectrum, 1 instance = comp, \ula_|video_|Mux0~3 , ula_|video_|Mux0~3, spectrum, 1 -instance = comp, \ula_|video_|cindex[2]~0 , ula_|video_|cindex[2]~0, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 -instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 -instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[6]~feeder , ula_|video_|bits_prefetch[6]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[6] , ula_|video_|bits_prefetch[6], spectrum, 1 +instance = comp, \ula_|video_|bits[6] , ula_|video_|bits[6], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[4] , ula_|video_|bits_prefetch[4], spectrum, 1 +instance = comp, \ula_|video_|bits[4] , ula_|video_|bits[4], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[5]~feeder , ula_|video_|bits_prefetch[5]~feeder, spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[5] , ula_|video_|bits_prefetch[5], spectrum, 1 +instance = comp, \ula_|video_|bits[5] , ula_|video_|bits[5], spectrum, 1 +instance = comp, \ula_|video_|bits_prefetch[7] , ula_|video_|bits_prefetch[7], spectrum, 1 +instance = comp, \ula_|video_|bits[7] , ula_|video_|bits[7], spectrum, 1 +instance = comp, \ula_|video_|Mux0~0 , ula_|video_|Mux0~0, spectrum, 1 +instance = comp, \ula_|video_|Mux0~1 , ula_|video_|Mux0~1, spectrum, 1 +instance = comp, \ula_|video_|cindex[1]~0 , ula_|video_|cindex[1]~0, spectrum, 1 instance = comp, \ula_|video_|cindex[1]~1 , ula_|video_|cindex[1]~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 instance = comp, \ula_|video_|LessThan3~0 , ula_|video_|LessThan3~0, spectrum, 1 instance = comp, \ula_|video_|LessThan0~0 , ula_|video_|LessThan0~0, spectrum, 1 instance = comp, \ula_|video_|disp_enable~0 , ula_|video_|disp_enable~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 instance = comp, \ula_|video_|disp_enable~1 , ula_|video_|disp_enable~1, spectrum, 1 +instance = comp, \ula_|border[1] , ula_|border[1], spectrum, 1 +instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 +instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 +instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 instance = comp, \ula_|video_|VGA_R[0]~0 , ula_|video_|VGA_R[0]~0, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[6]~feeder , ula_|video_|attr_prefetch[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[6] , ula_|video_|attr_prefetch[6], spectrum, 1 instance = comp, \ula_|video_|attr[6] , ula_|video_|attr[6], spectrum, 1 instance = comp, \ula_|video_|VGA_B[1]~0 , ula_|video_|VGA_B[1]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_R[1]~1 , ula_|video_|VGA_R[1]~1, spectrum, 1 -instance = comp, \ula_|border[2]~feeder , ula_|border[2]~feeder, spectrum, 1 instance = comp, \ula_|border[2] , ula_|border[2], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[2]~feeder , ula_|video_|attr_prefetch[2]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[2] , ula_|video_|attr_prefetch[2], spectrum, 1 +instance = comp, \ula_|video_|attr[2]~feeder , ula_|video_|attr[2]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr[2] , ula_|video_|attr[2], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[5]~feeder , ula_|video_|attr_prefetch[5]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[5] , ula_|video_|attr_prefetch[5], spectrum, 1 instance = comp, \ula_|video_|attr[5] , ula_|video_|attr[5], spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[2]~feeder , ula_|video_|attr_prefetch[2]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[2] , ula_|video_|attr_prefetch[2], spectrum, 1 -instance = comp, \ula_|video_|attr[2] , ula_|video_|attr[2], spectrum, 1 instance = comp, \ula_|video_|cindex[2]~2 , ula_|video_|cindex[2]~2, spectrum, 1 instance = comp, \ula_|video_|VGA_G[0]~0 , ula_|video_|VGA_G[0]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_G[1]~1 , ula_|video_|VGA_G[1]~1, spectrum, 1 -instance = comp, \ula_|border[0]~feeder , ula_|border[0]~feeder, spectrum, 1 instance = comp, \ula_|border[0] , ula_|border[0], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[0]~feeder , ula_|video_|attr_prefetch[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[0] , ula_|video_|attr_prefetch[0], spectrum, 1 +instance = comp, \ula_|video_|attr[0]~feeder , ula_|video_|attr[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr[0] , ula_|video_|attr[0], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[3]~feeder , ula_|video_|attr_prefetch[3]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[3] , ula_|video_|attr_prefetch[3], spectrum, 1 @@ -3355,8 +3553,8 @@ instance = comp, \ula_|video_|attr[3] , ula_|video_|attr[3], spectrum, 1 instance = comp, \ula_|video_|cindex[0]~3 , ula_|video_|cindex[0]~3, spectrum, 1 instance = comp, \ula_|video_|VGA_B[0]~1 , ula_|video_|VGA_B[0]~1, spectrum, 1 instance = comp, \ula_|video_|VGA_B[1]~2 , ula_|video_|VGA_B[1]~2, spectrum, 1 -instance = comp, \ula_|video_|Equal0~2 , ula_|video_|Equal0~2, spectrum, 1 instance = comp, \ula_|video_|VGA_HS~_Duplicate_1 , ula_|video_|VGA_HS~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|video_|Equal0~2 , ula_|video_|Equal0~2, spectrum, 1 instance = comp, \ula_|video_|Selector0~0 , ula_|video_|Selector0~0, spectrum, 1 instance = comp, \ula_|video_|VGA_HS , ula_|video_|VGA_HS, spectrum, 1 instance = comp, \ula_|video_|VGA_VS~_Duplicate_1 , ula_|video_|VGA_VS~_Duplicate_1, spectrum, 1 @@ -3370,118 +3568,126 @@ instance = comp, \z80_|memory_ifc_|nM1_out , z80_|memory_ifc_|nM1_out, spectrum, instance = comp, \ula_|beep~0 , ula_|beep~0, spectrum, 1 instance = comp, \ula_|beep , ula_|beep, spectrum, 1 instance = comp, \sdram_|Mux26~4 , sdram_|Mux26~4, spectrum, 1 -instance = comp, \sdram_|r.bank[0]~7 , sdram_|r.bank[0]~7, spectrum, 1 -instance = comp, \sdram_|r.bank[0]~11 , sdram_|r.bank[0]~11, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~6 , sdram_|r.bank[0]~6, spectrum, 1 instance = comp, \sdram_|r.bank[0]~4 , sdram_|r.bank[0]~4, spectrum, 1 instance = comp, \sdram_|r.bank[0]~5 , sdram_|r.bank[0]~5, spectrum, 1 -instance = comp, \sdram_|r.bank[0]~6 , sdram_|r.bank[0]~6, spectrum, 1 -instance = comp, \sdram_|r.bank[0]~8 , sdram_|r.bank[0]~8, spectrum, 1 instance = comp, \sdram_|r.bank[0]~12 , sdram_|r.bank[0]~12, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~7 , sdram_|r.bank[0]~7, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~8 , sdram_|r.bank[0]~8, spectrum, 1 instance = comp, \sdram_|r.bank[0]~9 , sdram_|r.bank[0]~9, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~10 , sdram_|r.bank[0]~10, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~13 , sdram_|r.bank[0]~13, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~11 , sdram_|r.bank[0]~11, spectrum, 1 instance = comp, \sdram_|r.bank[0] , sdram_|r.bank[0], spectrum, 1 instance = comp, \sdram_|Mux25~4 , sdram_|Mux25~4, spectrum, 1 instance = comp, \sdram_|r.bank[1] , sdram_|r.bank[1], spectrum, 1 -instance = comp, \sdram_|Mux24~5 , sdram_|Mux24~5, spectrum, 1 -instance = comp, \sdram_|Mux71~0 , sdram_|Mux71~0, spectrum, 1 -instance = comp, \sdram_|process_0~7 , sdram_|process_0~7, spectrum, 1 -instance = comp, \sdram_|process_0~4 , sdram_|process_0~4, spectrum, 1 -instance = comp, \sdram_|Mux71~1 , sdram_|Mux71~1, spectrum, 1 +instance = comp, \sdram_|Mux71~6 , sdram_|Mux71~6, spectrum, 1 instance = comp, \sdram_|Mux71~2 , sdram_|Mux71~2, spectrum, 1 instance = comp, \sdram_|Mux71~3 , sdram_|Mux71~3, spectrum, 1 +instance = comp, \sdram_|process_0~8 , sdram_|process_0~8, spectrum, 1 +instance = comp, \sdram_|process_0~3 , sdram_|process_0~3, spectrum, 1 instance = comp, \sdram_|Mux71~4 , sdram_|Mux71~4, spectrum, 1 +instance = comp, \sdram_|Mux24~8 , sdram_|Mux24~8, spectrum, 1 +instance = comp, \sdram_|Mux71~5 , sdram_|Mux71~5, spectrum, 1 instance = comp, \sdram_|r.dq_masks[0] , sdram_|r.dq_masks[0], spectrum, 1 instance = comp, \sdram_|r.dq_masks[1] , sdram_|r.dq_masks[1], spectrum, 1 -instance = comp, \sdram_|r.bank[0]~10 , sdram_|r.bank[0]~10, spectrum, 1 -instance = comp, \sdram_|Mux9~3 , sdram_|Mux9~3, spectrum, 1 -instance = comp, \sdram_|n~5 , sdram_|n~5, spectrum, 1 -instance = comp, \sdram_|Mux9~4 , sdram_|Mux9~4, spectrum, 1 -instance = comp, \sdram_|Mux9~2 , sdram_|Mux9~2, spectrum, 1 -instance = comp, \sdram_|Equal2~3 , sdram_|Equal2~3, spectrum, 1 -instance = comp, \sdram_|Mux10~2 , sdram_|Mux10~2, spectrum, 1 -instance = comp, \sdram_|Mux10~3 , sdram_|Mux10~3, spectrum, 1 -instance = comp, \sdram_|process_0~6 , sdram_|process_0~6, spectrum, 1 -instance = comp, \sdram_|Mux10~4 , sdram_|Mux10~4, spectrum, 1 -instance = comp, \sdram_|Mux9~5 , sdram_|Mux9~5, spectrum, 1 -instance = comp, \sdram_|Mux7~0 , sdram_|Mux7~0, spectrum, 1 +instance = comp, \sdram_|n~6 , sdram_|n~6, spectrum, 1 +instance = comp, \sdram_|Mux9~0 , sdram_|Mux9~0, spectrum, 1 instance = comp, \sdram_|Mux9~6 , sdram_|Mux9~6, spectrum, 1 instance = comp, \sdram_|Mux9~7 , sdram_|Mux9~7, spectrum, 1 +instance = comp, \sdram_|Mux7~0 , sdram_|Mux7~0, spectrum, 1 +instance = comp, \sdram_|Equal2~3 , sdram_|Equal2~3, spectrum, 1 +instance = comp, \sdram_|process_0~6 , sdram_|process_0~6, spectrum, 1 +instance = comp, \sdram_|Equal5~0 , sdram_|Equal5~0, spectrum, 1 +instance = comp, \sdram_|Equal5~1 , sdram_|Equal5~1, spectrum, 1 +instance = comp, \sdram_|process_0~7 , sdram_|process_0~7, spectrum, 1 +instance = comp, \sdram_|Mux10~2 , sdram_|Mux10~2, spectrum, 1 +instance = comp, \sdram_|Mux9~1 , sdram_|Mux9~1, spectrum, 1 +instance = comp, \sdram_|Mux9~2 , sdram_|Mux9~2, spectrum, 1 +instance = comp, \sdram_|Mux9~3 , sdram_|Mux9~3, spectrum, 1 instance = comp, \sdram_|r.state[2] , sdram_|r.state[2], spectrum, 1 -instance = comp, \sdram_|Mux10~11 , sdram_|Mux10~11, spectrum, 1 instance = comp, \sdram_|Mux10~6 , sdram_|Mux10~6, spectrum, 1 +instance = comp, \sdram_|Mux10~10 , sdram_|Mux10~10, spectrum, 1 +instance = comp, \sdram_|Mux10~3 , sdram_|Mux10~3, spectrum, 1 +instance = comp, \sdram_|Mux10~4 , sdram_|Mux10~4, spectrum, 1 instance = comp, \sdram_|Mux10~5 , sdram_|Mux10~5, spectrum, 1 instance = comp, \sdram_|Mux10~7 , sdram_|Mux10~7, spectrum, 1 +instance = comp, \sdram_|Mux10~11 , sdram_|Mux10~11, spectrum, 1 +instance = comp, \sdram_|Mux10~12 , sdram_|Mux10~12, spectrum, 1 instance = comp, \sdram_|Mux10~8 , sdram_|Mux10~8, spectrum, 1 -instance = comp, \sdram_|Mux10~9 , sdram_|Mux10~9, spectrum, 1 instance = comp, \sdram_|r.state[1] , sdram_|r.state[1], spectrum, 1 instance = comp, \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK , sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK, spectrum, 1 +instance = comp, \sdram_|Mux11~4 , sdram_|Mux11~4, spectrum, 1 +instance = comp, \sdram_|Mux11~8 , sdram_|Mux11~8, spectrum, 1 instance = comp, \sdram_|Mux11~2 , sdram_|Mux11~2, spectrum, 1 instance = comp, \sdram_|Mux11~3 , sdram_|Mux11~3, spectrum, 1 -instance = comp, \sdram_|Mux11~4 , sdram_|Mux11~4, spectrum, 1 instance = comp, \sdram_|Mux11~5 , sdram_|Mux11~5, spectrum, 1 instance = comp, \sdram_|Mux11~6 , sdram_|Mux11~6, spectrum, 1 instance = comp, \sdram_|Mux11~7 , sdram_|Mux11~7, spectrum, 1 -instance = comp, \sdram_|Mux11~9 , sdram_|Mux11~9, spectrum, 1 -instance = comp, \sdram_|Mux11~8 , sdram_|Mux11~8, spectrum, 1 instance = comp, \sdram_|r.state[0] , sdram_|r.state[0], spectrum, 1 -instance = comp, \sdram_|Mux24~2 , sdram_|Mux24~2, spectrum, 1 -instance = comp, \sdram_|r.address[0]~7 , sdram_|r.address[0]~7, spectrum, 1 -instance = comp, \sdram_|r.address[0]~0 , sdram_|r.address[0]~0, spectrum, 1 -instance = comp, \sdram_|Mux13~9 , sdram_|Mux13~9, spectrum, 1 +instance = comp, \sdram_|Mux24~5 , sdram_|Mux24~5, spectrum, 1 +instance = comp, \sdram_|Mux24~6 , sdram_|Mux24~6, spectrum, 1 instance = comp, \sdram_|Mux13~4 , sdram_|Mux13~4, spectrum, 1 +instance = comp, \sdram_|Mux13~9 , sdram_|Mux13~9, spectrum, 1 instance = comp, \sdram_|Mux13~5 , sdram_|Mux13~5, spectrum, 1 instance = comp, \sdram_|r.address[0]~_Duplicate_1 , sdram_|r.address[0]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux24~2 , sdram_|Mux24~2, spectrum, 1 instance = comp, \sdram_|Mux24~3 , sdram_|Mux24~3, spectrum, 1 instance = comp, \sdram_|Mux24~4 , sdram_|Mux24~4, spectrum, 1 +instance = comp, \sdram_|r.address[0]~0 , sdram_|r.address[0]~0, spectrum, 1 instance = comp, \sdram_|r.address[0]~SLOAD_MUX , sdram_|r.address[0]~SLOAD_MUX, spectrum, 1 instance = comp, \sdram_|r.address[0] , sdram_|r.address[0], spectrum, 1 +instance = comp, \sdram_|Mux23~1 , sdram_|Mux23~1, spectrum, 1 +instance = comp, \sdram_|r.address[1]~8 , sdram_|r.address[1]~8, spectrum, 1 +instance = comp, \sdram_|r.address[1]~9 , sdram_|r.address[1]~9, spectrum, 1 +instance = comp, \sdram_|r.address[1]~7 , sdram_|r.address[1]~7, spectrum, 1 +instance = comp, \sdram_|r.address[1]~10 , sdram_|r.address[1]~10, spectrum, 1 +instance = comp, \sdram_|r.address[1]~1 , sdram_|r.address[1]~1, spectrum, 1 instance = comp, \sdram_|r.address[1]~_Duplicate_1feeder , sdram_|r.address[1]~_Duplicate_1feeder, spectrum, 1 -instance = comp, \sdram_|Mux23~4 , sdram_|Mux23~4, spectrum, 1 -instance = comp, \sdram_|Equal5~0 , sdram_|Equal5~0, spectrum, 1 -instance = comp, \sdram_|Mux23~5 , sdram_|Mux23~5, spectrum, 1 -instance = comp, \sdram_|Mux23~6 , sdram_|Mux23~6, spectrum, 1 instance = comp, \sdram_|Mux19~0 , sdram_|Mux19~0, spectrum, 1 instance = comp, \sdram_|r.address[1]~_Duplicate_1 , sdram_|r.address[1]~_Duplicate_1, spectrum, 1 -instance = comp, \sdram_|Mux23~2 , sdram_|Mux23~2, spectrum, 1 instance = comp, \sdram_|Mux23~3 , sdram_|Mux23~3, spectrum, 1 -instance = comp, \sdram_|Mux23~1 , sdram_|Mux23~1, spectrum, 1 -instance = comp, \sdram_|r.address[1]~1 , sdram_|r.address[1]~1, spectrum, 1 +instance = comp, \sdram_|Mux23~4 , sdram_|Mux23~4, spectrum, 1 +instance = comp, \sdram_|Mux23~2 , sdram_|Mux23~2, spectrum, 1 +instance = comp, \sdram_|Mux23~5 , sdram_|Mux23~5, spectrum, 1 instance = comp, \sdram_|r.address[1]~SLOAD_MUX , sdram_|r.address[1]~SLOAD_MUX, spectrum, 1 instance = comp, \sdram_|r.address[1] , sdram_|r.address[1], spectrum, 1 -instance = comp, \sdram_|r.address[3]~8 , sdram_|r.address[3]~8, spectrum, 1 -instance = comp, \sdram_|r.address[3]~9 , sdram_|r.address[3]~9, spectrum, 1 -instance = comp, \sdram_|Mux21~0 , sdram_|Mux21~0, spectrum, 1 -instance = comp, \sdram_|Mux22~0 , sdram_|Mux22~0, spectrum, 1 -instance = comp, \sdram_|r.address[3]~10 , sdram_|r.address[3]~10, spectrum, 1 instance = comp, \sdram_|r.address[3]~11 , sdram_|r.address[3]~11, spectrum, 1 instance = comp, \sdram_|r.address[3]~12 , sdram_|r.address[3]~12, spectrum, 1 -instance = comp, \sdram_|r.address[3]~13 , sdram_|r.address[3]~13, spectrum, 1 +instance = comp, \sdram_|Mux21~0 , sdram_|Mux21~0, spectrum, 1 +instance = comp, \sdram_|Mux22~0 , sdram_|Mux22~0, spectrum, 1 instance = comp, \sdram_|r.address[3]~14 , sdram_|r.address[3]~14, spectrum, 1 instance = comp, \sdram_|r.address[3]~15 , sdram_|r.address[3]~15, spectrum, 1 +instance = comp, \sdram_|r.address[3]~13 , sdram_|r.address[3]~13, spectrum, 1 instance = comp, \sdram_|r.address[3]~16 , sdram_|r.address[3]~16, spectrum, 1 instance = comp, \sdram_|r.address[3]~17 , sdram_|r.address[3]~17, spectrum, 1 +instance = comp, \sdram_|r.address[3]~18 , sdram_|r.address[3]~18, spectrum, 1 +instance = comp, \sdram_|r.address[3]~19 , sdram_|r.address[3]~19, spectrum, 1 +instance = comp, \sdram_|r.address[3]~20 , sdram_|r.address[3]~20, spectrum, 1 instance = comp, \sdram_|r.address[2] , sdram_|r.address[2], spectrum, 1 instance = comp, \sdram_|Mux21~1 , sdram_|Mux21~1, spectrum, 1 instance = comp, \sdram_|r.address[3] , sdram_|r.address[3], spectrum, 1 +instance = comp, \sdram_|Mux24~7 , sdram_|Mux24~7, spectrum, 1 instance = comp, \sdram_|Mux20~4 , sdram_|Mux20~4, spectrum, 1 -instance = comp, \sdram_|Mux20~7 , sdram_|Mux20~7, spectrum, 1 -instance = comp, \sdram_|Mux23~7 , sdram_|Mux23~7, spectrum, 1 -instance = comp, \sdram_|Mux20~8 , sdram_|Mux20~8, spectrum, 1 -instance = comp, \sdram_|Mux20~10 , sdram_|Mux20~10, spectrum, 1 -instance = comp, \sdram_|Mux20~9 , sdram_|Mux20~9, spectrum, 1 -instance = comp, \sdram_|Mux20~11 , sdram_|Mux20~11, spectrum, 1 -instance = comp, \sdram_|r.address[4]~_Duplicate_1 , sdram_|r.address[4]~_Duplicate_1, spectrum, 1 -instance = comp, \sdram_|Mux20~12 , sdram_|Mux20~12, spectrum, 1 -instance = comp, \sdram_|Mux20~5 , sdram_|Mux20~5, spectrum, 1 -instance = comp, \sdram_|Mux20~6 , sdram_|Mux20~6, spectrum, 1 +instance = comp, \sdram_|Mux20~2 , sdram_|Mux20~2, spectrum, 1 +instance = comp, \sdram_|Mux20~3 , sdram_|Mux20~3, spectrum, 1 instance = comp, \sdram_|r.address[4]~2 , sdram_|r.address[4]~2, spectrum, 1 +instance = comp, \sdram_|r.address[4]~_Duplicate_1feeder , sdram_|r.address[4]~_Duplicate_1feeder, spectrum, 1 +instance = comp, \sdram_|r.address[4]~_Duplicate_1 , sdram_|r.address[4]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux20~5 , sdram_|Mux20~5, spectrum, 1 +instance = comp, \sdram_|Mux20~10 , sdram_|Mux20~10, spectrum, 1 +instance = comp, \sdram_|Mux20~6 , sdram_|Mux20~6, spectrum, 1 +instance = comp, \sdram_|Mux20~7 , sdram_|Mux20~7, spectrum, 1 +instance = comp, \sdram_|Mux20~8 , sdram_|Mux20~8, spectrum, 1 +instance = comp, \sdram_|Mux20~9 , sdram_|Mux20~9, spectrum, 1 instance = comp, \sdram_|r.address[4]~SLOAD_MUX , sdram_|r.address[4]~SLOAD_MUX, spectrum, 1 instance = comp, \sdram_|r.address[4] , sdram_|r.address[4], spectrum, 1 -instance = comp, \sdram_|Mux19~1 , sdram_|Mux19~1, spectrum, 1 instance = comp, \sdram_|Mux19~4 , sdram_|Mux19~4, spectrum, 1 -instance = comp, \sdram_|Mux19~5 , sdram_|Mux19~5, spectrum, 1 instance = comp, \sdram_|Mux19~6 , sdram_|Mux19~6, spectrum, 1 +instance = comp, \sdram_|Mux19~5 , sdram_|Mux19~5, spectrum, 1 instance = comp, \sdram_|Mux19~7 , sdram_|Mux19~7, spectrum, 1 instance = comp, \sdram_|r.address[5]~_Duplicate_1 , sdram_|r.address[5]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux19~1 , sdram_|Mux19~1, spectrum, 1 instance = comp, \sdram_|Mux19~2 , sdram_|Mux19~2, spectrum, 1 instance = comp, \sdram_|Mux19~3 , sdram_|Mux19~3, spectrum, 1 instance = comp, \sdram_|r.address[5]~3 , sdram_|r.address[5]~3, spectrum, 1 @@ -3489,24 +3695,25 @@ instance = comp, \sdram_|r.address[5]~SLOAD_MUX , sdram_|r.address[5]~SLOAD_MUX, instance = comp, \sdram_|r.address[5] , sdram_|r.address[5], spectrum, 1 instance = comp, \sdram_|Mux18~0 , sdram_|Mux18~0, spectrum, 1 instance = comp, \sdram_|r.address[6] , sdram_|r.address[6], spectrum, 1 -instance = comp, \sdram_|Mux17~0 , sdram_|Mux17~0, spectrum, 1 +instance = comp, \sdram_|Mux17~2 , sdram_|Mux17~2, spectrum, 1 instance = comp, \sdram_|r.address[7] , sdram_|r.address[7], spectrum, 1 -instance = comp, \sdram_|Mux16~0 , sdram_|Mux16~0, spectrum, 1 +instance = comp, \sdram_|Mux16~2 , sdram_|Mux16~2, spectrum, 1 instance = comp, \sdram_|r.address[8] , sdram_|r.address[8], spectrum, 1 instance = comp, \sdram_|Mux15~2 , sdram_|Mux15~2, spectrum, 1 instance = comp, \sdram_|r.address[9] , sdram_|r.address[9], spectrum, 1 -instance = comp, \sdram_|Mux14~0 , sdram_|Mux14~0, spectrum, 1 -instance = comp, \sdram_|Mux14~1 , sdram_|Mux14~1, spectrum, 1 -instance = comp, \sdram_|r.address[10]~4 , sdram_|r.address[10]~4, spectrum, 1 -instance = comp, \sdram_|r.address[10]~_Duplicate_1 , sdram_|r.address[10]~_Duplicate_1, spectrum, 1 -instance = comp, \sdram_|n~4 , sdram_|n~4, spectrum, 1 +instance = comp, \sdram_|r.address[10]~_Duplicate_1feeder , sdram_|r.address[10]~_Duplicate_1feeder, spectrum, 1 +instance = comp, \sdram_|n~5 , sdram_|n~5, spectrum, 1 instance = comp, \sdram_|Mux14~2 , sdram_|Mux14~2, spectrum, 1 instance = comp, \sdram_|Mux14~3 , sdram_|Mux14~3, spectrum, 1 +instance = comp, \sdram_|r.address[10]~_Duplicate_1 , sdram_|r.address[10]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux14~1 , sdram_|Mux14~1, spectrum, 1 +instance = comp, \sdram_|Mux14~0 , sdram_|Mux14~0, spectrum, 1 +instance = comp, \sdram_|r.address[10]~4 , sdram_|r.address[10]~4, spectrum, 1 instance = comp, \sdram_|r.address[10]~SLOAD_MUX , sdram_|r.address[10]~SLOAD_MUX, spectrum, 1 instance = comp, \sdram_|r.address[10] , sdram_|r.address[10], spectrum, 1 -instance = comp, \sdram_|r.address[11]~18 , sdram_|r.address[11]~18, spectrum, 1 +instance = comp, \sdram_|r.address[11]~21 , sdram_|r.address[11]~21, spectrum, 1 +instance = comp, \sdram_|r.address[11]~22 , sdram_|r.address[11]~22, spectrum, 1 instance = comp, \sdram_|r.address[11]~5 , sdram_|r.address[11]~5, spectrum, 1 -instance = comp, \sdram_|r.address[11]~_Duplicate_2feeder , sdram_|r.address[11]~_Duplicate_2feeder, spectrum, 1 instance = comp, \sdram_|r.address[11]~_Duplicate_2 , sdram_|r.address[11]~_Duplicate_2, spectrum, 1 instance = comp, \sdram_|Mux13~10 , sdram_|Mux13~10, spectrum, 1 instance = comp, \sdram_|Mux13~6 , sdram_|Mux13~6, spectrum, 1 @@ -3515,6 +3722,7 @@ instance = comp, \sdram_|r.address[11] , sdram_|r.address[11], spectrum, 1 instance = comp, \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX , sdram_|r.address[11]~_Duplicate_1SLOAD_MUX, spectrum, 1 instance = comp, \sdram_|r.address[11]~_Duplicate_1 , sdram_|r.address[11]~_Duplicate_1, spectrum, 1 instance = comp, \SW[0]~input , SW[0]~input, spectrum, 1 +instance = comp, \SW[2]~input , SW[2]~input, spectrum, 1 instance = comp, \SW[3]~input , SW[3]~input, spectrum, 1 instance = comp, \I2C_SCLK~input , I2C_SCLK~input, spectrum, 1 instance = comp, \DRAM_DQ[0]~input , DRAM_DQ[0]~input, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index ce14b52..5cf87db 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/02/2022 14:51:22") + (DATE "04/06/2022 13:58:29") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1504:1504:1504) (1598:1598:1598)) - (PORT oe (1712:1712:1712) (1779:1779:1779)) + (PORT i (2372:2372:2372) (2462:2462:2462)) + (PORT oe (4863:4863:4863) (5015:5015:5015)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2050:2050:2050) (2110:2110:2110)) - (PORT oe (1688:1688:1688) (1781:1781:1781)) + (PORT i (1718:1718:1718) (1802:1802:1802)) + (PORT oe (3583:3583:3583) (3656:3656:3656)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (2228:2228:2228) (2262:2262:2262)) - (PORT oe (1688:1688:1688) (1781:1781:1781)) + (PORT i (1337:1337:1337) (1397:1397:1397)) + (PORT oe (3583:3583:3583) (3656:3656:3656)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1814:1814:1814) (1854:1854:1854)) - (PORT oe (2105:2105:2105) (2195:2195:2195)) + (PORT i (1578:1578:1578) (1619:1619:1619)) + (PORT oe (3400:3400:3400) (3499:3499:3499)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1890:1890:1890) (1931:1931:1931)) - (PORT oe (2105:2105:2105) (2195:2195:2195)) + (PORT i (1624:1624:1624) (1691:1691:1691)) + (PORT oe (3400:3400:3400) (3499:3499:3499)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1532:1532:1532) (1676:1676:1676)) - (PORT oe (2346:2346:2346) (2450:2450:2450)) + (PORT i (1329:1329:1329) (1397:1397:1397)) + (PORT oe (3135:3135:3135) (3272:3272:3272)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1646:1646:1646) (1694:1694:1694)) - (PORT oe (2346:2346:2346) (2450:2450:2450)) + (PORT i (1405:1405:1405) (1507:1507:1507)) + (PORT oe (3135:3135:3135) (3272:3272:3272)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1651:1651:1651) (1747:1747:1747)) - (PORT oe (2346:2346:2346) (2450:2450:2450)) + (PORT i (1437:1437:1437) (1497:1497:1497)) + (PORT oe (3135:3135:3135) (3272:3272:3272)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1458:1458:1458) (1517:1517:1517)) - (PORT oe (2627:2627:2627) (2741:2741:2741)) + (PORT i (1171:1171:1171) (1225:1225:1225)) + (PORT oe (2940:2940:2940) (3068:3068:3068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1614:1614:1614) (1659:1659:1659)) - (PORT oe (2627:2627:2627) (2741:2741:2741)) + (PORT i (1364:1364:1364) (1413:1413:1413)) + (PORT oe (2940:2940:2940) (3068:3068:3068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1699:1699:1699) (1833:1833:1833)) - (PORT oe (2364:2364:2364) (2456:2456:2456)) + (PORT i (1467:1467:1467) (1493:1493:1493)) + (PORT oe (3206:3206:3206) (3319:3319:3319)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1560:1560:1560) (1602:1602:1602)) - (PORT oe (2627:2627:2627) (2741:2741:2741)) + (PORT i (1469:1469:1469) (1491:1491:1491)) + (PORT oe (2940:2940:2940) (3068:3068:3068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1639:1639:1639) (1709:1709:1709)) - (PORT oe (1712:1712:1712) (1796:1796:1796)) + (PORT i (2163:2163:2163) (2267:2267:2267)) + (PORT oe (3618:3618:3618) (3692:3692:3692)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1649:1649:1649) (1732:1732:1732)) - (PORT oe (2364:2364:2364) (2456:2456:2456)) + (PORT i (1598:1598:1598) (1641:1641:1641)) + (PORT oe (3206:3206:3206) (3319:3319:3319)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1435:1435:1435) (1557:1557:1557)) - (PORT oe (2114:2114:2114) (2280:2280:2280)) + (PORT i (1086:1086:1086) (1154:1154:1154)) + (PORT oe (2619:2619:2619) (2764:2764:2764)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1807:1807:1807) (1861:1861:1861)) - (PORT oe (1901:1901:1901) (1995:1995:1995)) + (PORT i (1542:1542:1542) (1579:1579:1579)) + (PORT oe (3573:3573:3573) (3648:3648:3648)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1165:1165:1165) (1241:1241:1241)) - (PORT oe (1397:1397:1397) (1462:1462:1462)) + (PORT i (1624:1624:1624) (1682:1682:1682)) + (PORT oe (1869:1869:1869) (1913:1913:1913)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1217:1217:1217) (1281:1281:1281)) - (PORT oe (1676:1676:1676) (1756:1756:1756)) + (PORT i (1429:1429:1429) (1518:1518:1518)) + (PORT oe (2686:2686:2686) (2737:2737:2737)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1447:1447:1447) (1518:1518:1518)) - (PORT oe (1644:1644:1644) (1702:1702:1702)) + (PORT i (1383:1383:1383) (1456:1456:1456)) + (PORT oe (2340:2340:2340) (2399:2399:2399)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1400:1400:1400) (1428:1428:1428)) - (PORT oe (1397:1397:1397) (1462:1462:1462)) + (PORT i (1165:1165:1165) (1242:1242:1242)) + (PORT oe (1869:1869:1869) (1913:1913:1913)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1625:1625:1625) (1682:1682:1682)) - (PORT oe (1412:1412:1412) (1478:1478:1478)) + (PORT i (1419:1419:1419) (1486:1486:1486)) + (PORT oe (2064:2064:2064) (2094:2094:2094)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1530:1530:1530)) - (PORT oe (1701:1701:1701) (1755:1755:1755)) + (PORT i (1557:1557:1557) (1627:1627:1627)) + (PORT oe (2342:2342:2342) (2374:2374:2374)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1615:1615:1615) (1704:1704:1704)) - (PORT oe (1627:1627:1627) (1676:1676:1676)) + (PORT i (1389:1389:1389) (1450:1450:1450)) + (PORT oe (2092:2092:2092) (2121:2121:2121)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1389:1389:1389) (1468:1468:1468)) - (PORT oe (1392:1392:1392) (1455:1455:1455)) + (PORT i (1623:1623:1623) (1694:1694:1694)) + (PORT oe (2372:2372:2372) (2427:2427:2427)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1446:1446:1446) (1447:1447:1447)) - (PORT oe (1534:1534:1534) (1631:1631:1631)) + (PORT i (1946:1946:1946) (1917:1917:1917)) + (PORT oe (3719:3719:3719) (3789:3789:3789)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1260:1260:1260) (1241:1241:1241)) - (PORT oe (1901:1901:1901) (1995:1995:1995)) + (PORT i (1569:1569:1569) (1477:1477:1477)) + (PORT oe (3573:3573:3573) (3648:3648:3648)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1183:1183:1183) (1166:1166:1166)) - (PORT oe (1856:1856:1856) (1947:1947:1947)) - (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (PORT i (1968:1968:1968) (1962:1962:1962)) + (PORT oe (3995:3995:3995) (4077:4077:4077)) + (IOPATH i o (2502:2502:2502) (2582:2582:2582)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1167:1167:1167) (1158:1158:1158)) - (PORT oe (1000:1000:1000) (1069:1069:1069)) + (PORT i (1941:1941:1941) (1926:1926:1926)) + (PORT oe (4286:4286:4286) (4394:4394:4394)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -377,7 +377,17 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1615:1615:1615) (1516:1516:1516)) + (PORT i (1746:1746:1746) (1668:1668:1668)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2215:2215:2215) (2341:2341:2341)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -387,7 +397,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1031:1031:1031) (1018:1018:1018)) + (PORT i (1510:1510:1510) (1624:1624:1624)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -397,8 +407,48 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1473:1473:1473) (1574:1574:1574)) - (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + (PORT i (1516:1516:1516) (1478:1478:1478)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1265:1265:1265) (1258:1258:1258)) + (IOPATH i o (2502:2502:2502) (2582:2582:2582)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1258:1258:1258) (1255:1255:1255)) + (IOPATH i o (4127:4127:4127) (4477:4477:4477)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1251:1251:1251) (1240:1240:1240)) + (IOPATH i o (2378:2378:2378) (2455:2455:2455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (319:319:319) (322:322:322)) + (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) ) @@ -452,7 +502,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1116:1116:1116) (1178:1178:1178)) + (PORT i (1035:1035:1035) (1041:1041:1041)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +512,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1137:1137:1137) (1173:1173:1173)) + (PORT i (997:997:997) (995:995:995)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +522,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (869:869:869) (884:884:884)) + (PORT i (1008:1008:1008) (996:996:996)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +532,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (820:820:820) (820:820:820)) + (PORT i (540:540:540) (536:536:536)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +542,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (576:576:576) (580:580:580)) + (PORT i (716:716:716) (701:701:701)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +552,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (555:555:555) (581:581:581)) + (PORT i (728:728:728) (700:700:700)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +562,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1290:1290:1290)) + (PORT i (1309:1309:1309) (1310:1310:1310)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +572,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1290:1290:1290)) + (PORT i (1309:1309:1309) (1310:1310:1310)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -532,7 +582,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1111:1111:1111) (1161:1161:1161)) + (PORT i (1076:1076:1076) (1094:1094:1094)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -542,7 +592,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1244:1244:1244) (1229:1229:1229)) + (PORT i (1040:1040:1040) (1057:1057:1057)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +602,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1131:1131:1131) (1197:1197:1197)) + (PORT i (1060:1060:1060) (1082:1082:1082)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -562,7 +612,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1135:1135:1135) (1193:1193:1193)) + (PORT i (1072:1072:1072) (1091:1091:1091)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -590,7 +640,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1748:1748:1748) (1663:1663:1663)) + (PORT i (1882:1882:1882) (1835:1835:1835)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -600,7 +650,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1132:1132:1132) (1158:1158:1158)) + (PORT i (1356:1356:1356) (1377:1377:1377)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -610,7 +660,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (888:888:888) (865:865:865)) + (PORT i (308:308:308) (313:313:313)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -620,7 +670,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1643:1643:1643) (1721:1721:1721)) + (PORT i (1593:1593:1593) (1644:1644:1644)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -838,8 +888,8 @@ (INSTANCE DRAM_DQ\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1255:1255:1255) (1335:1335:1335)) - (PORT oe (1717:1717:1717) (1786:1786:1786)) + (PORT i (1153:1153:1153) (1208:1208:1208)) + (PORT oe (1433:1433:1433) (1474:1474:1474)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -850,8 +900,8 @@ (INSTANCE DRAM_DQ\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1398:1398:1398) (1454:1454:1454)) - (PORT oe (1717:1717:1717) (1786:1786:1786)) + (PORT i (1427:1427:1427) (1504:1504:1504)) + (PORT oe (1433:1433:1433) (1474:1474:1474)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -862,8 +912,8 @@ (INSTANCE DRAM_DQ\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1113:1113:1113) (1148:1148:1148)) - (PORT oe (1376:1376:1376) (1434:1434:1434)) + (PORT i (1337:1337:1337) (1372:1372:1372)) + (PORT oe (1409:1409:1409) (1442:1442:1442)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -874,8 +924,8 @@ (INSTANCE DRAM_DQ\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1206:1206:1206) (1278:1278:1278)) - (PORT oe (1471:1471:1471) (1583:1583:1583)) + (PORT i (1477:1477:1477) (1575:1575:1575)) + (PORT oe (1617:1617:1617) (1743:1743:1743)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -886,8 +936,8 @@ (INSTANCE DRAM_DQ\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1183:1183:1183) (1228:1228:1228)) - (PORT oe (1200:1200:1200) (1240:1240:1240)) + (PORT i (1495:1495:1495) (1585:1585:1585)) + (PORT oe (1528:1528:1528) (1603:1603:1603)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -898,8 +948,8 @@ (INSTANCE DRAM_DQ\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1419:1419:1419) (1515:1515:1515)) - (PORT oe (1364:1364:1364) (1339:1339:1339)) + (PORT i (1442:1442:1442) (1530:1530:1530)) + (PORT oe (1257:1257:1257) (1320:1320:1320)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -910,8 +960,8 @@ (INSTANCE DRAM_DQ\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1148:1148:1148) (1200:1200:1200)) - (PORT oe (1364:1364:1364) (1339:1339:1339)) + (PORT i (975:975:975) (1055:1055:1055)) + (PORT oe (1257:1257:1257) (1320:1320:1320)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -922,8 +972,8 @@ (INSTANCE DRAM_DQ\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (558:558:558) (558:558:558)) - (PORT oe (1367:1367:1367) (1406:1406:1406)) + (PORT i (1419:1419:1419) (1473:1473:1473)) + (PORT oe (1575:1575:1575) (1681:1681:1681)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -934,7 +984,7 @@ (INSTANCE DRAM_DQ\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (1686:1686:1686) (1628:1628:1628)) + (PORT i (1622:1622:1622) (1528:1528:1528)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -944,7 +994,7 @@ (INSTANCE DRAM_DQ\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1476:1476:1476) (1402:1402:1402)) + (PORT i (1589:1589:1589) (1486:1486:1486)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -954,7 +1004,7 @@ (INSTANCE DRAM_DQ\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1459:1459:1459) (1382:1382:1382)) + (PORT i (1602:1602:1602) (1499:1499:1499)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -964,7 +1014,7 @@ (INSTANCE DRAM_DQ\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1459:1459:1459) (1382:1382:1382)) + (PORT i (1602:1602:1602) (1499:1499:1499)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -974,7 +1024,7 @@ (INSTANCE DRAM_DQ\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1653:1653:1653) (1629:1629:1629)) + (PORT i (1592:1592:1592) (1501:1501:1501)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -984,7 +1034,7 @@ (INSTANCE DRAM_DQ\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1679:1679:1679) (1615:1615:1615)) + (PORT i (1623:1623:1623) (1523:1523:1523)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -994,7 +1044,7 @@ (INSTANCE DRAM_DQ\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1679:1679:1679) (1615:1615:1615)) + (PORT i (1623:1623:1623) (1523:1523:1523)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -1004,7 +1054,7 @@ (INSTANCE DRAM_DQ\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1240:1240:1240) (1200:1200:1200)) + (PORT i (1603:1603:1603) (1528:1528:1528)) (IOPATH i o (2502:2502:2502) (2582:2582:2582)) ) ) @@ -1036,6 +1086,887 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE turbo_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (481:481:481) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (154:154:154) (138:138:138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (362:362:362)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (354:354:354)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (362:362:362)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (342:342:342)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (351:351:351)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (353:353:353)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT datab (440:440:440) (507:507:507)) + (PORT datac (607:607:607) (658:658:658)) + (PORT datad (403:403:403) (465:465:465)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (393:393:393)) + (PORT datab (418:418:418) (490:490:490)) + (PORT datac (234:234:234) (319:319:319)) + (PORT datad (235:235:235) (310:310:310)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (358:358:358)) + (PORT datab (262:262:262) (351:351:351)) + (PORT datac (626:626:626) (643:643:643)) + (PORT datad (248:248:248) (320:320:320)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (339:339:339)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (260:260:260) (348:348:348)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (232:232:232) (308:308:308)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (817:817:817) (872:872:872)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (679:679:679)) + (PORT datab (252:252:252) (335:335:335)) + (PORT datac (3699:3699:3699) (4050:4050:4050)) + (PORT datad (683:683:683) (741:741:741)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1087:1087:1087) (1133:1133:1133)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (743:743:743)) + (PORT datab (419:419:419) (488:488:488)) + (PORT datac (231:231:231) (316:316:316)) + (PORT datad (232:232:232) (308:308:308)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (358:358:358)) + (PORT datab (262:262:262) (351:351:351)) + (PORT datac (234:234:234) (318:318:318)) + (PORT datad (234:234:234) (311:311:311)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (365:365:365)) + (PORT datab (690:690:690) (745:745:745)) + (PORT datac (243:243:243) (325:325:325)) + (PORT datad (245:245:245) (318:318:318)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (640:640:640) (652:652:652)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (638:638:638) (647:647:647)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_turbo\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (3737:3737:3737) (4091:4091:4091)) + (PORT datad (593:593:593) (605:605:605)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_turbo\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1756:1756:1756)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE turbo\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE turbo) + (DELAY + (ABSOLUTE + (PORT clk (864:864:864) (796:796:796)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|counter\[0\]\~0) @@ -1050,7 +1981,7 @@ (INSTANCE ula_\|clocks_\|counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1925:1925:1925) (1951:1951:1951)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1059,23 +1990,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE SW\[2\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (551:551:551) (574:574:574)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (880:880:880) (972:972:972)) + (PORT datad (649:649:649) (725:725:725)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1086,7 +2008,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu) (DELAY (ABSOLUTE - (PORT clk (1925:1925:1925) (1951:1951:1951)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1100,16 +2022,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (720:720:720) (751:751:751)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[1\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (481:481:481) (733:733:733)) + (PORT inclk[0] (727:727:727) (752:752:752)) ) ) ) @@ -1127,8 +2040,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1565:1565:1565) (1526:1526:1526)) - (PORT datad (529:529:529) (525:525:525)) + (PORT datac (1566:1566:1566) (1527:1527:1527)) + (PORT datad (531:531:531) (524:524:524)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1139,7 +2052,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) + (PORT datad (1828:1828:1828) (1899:1899:1899)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1149,7 +2062,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1539:1539:1539)) + (PORT clk (1535:1535:1535) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1163,7 +2076,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (753:753:753) (788:788:788)) + (PORT inclk[0] (712:712:712) (740:740:740)) ) ) ) @@ -1172,9 +2085,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1540:1540:1540)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1552:1552:1552)) + (PORT clrn (1563:1563:1563) (1546:1546:1546)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -1184,69 +2097,11 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[1\]\~input) (DELAY (ABSOLUTE - (PORT dataa (1901:1901:1901) (2085:2085:2085)) - (PORT datac (1463:1463:1463) (1532:1532:1532)) - (PORT datad (1153:1153:1153) (1264:1264:1264)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1554:1554:1554)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT datac (727:727:727) (823:823:823)) - (PORT datad (308:308:308) (411:411:411)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (2148:2148:2148) (2241:2241:2241)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1481:1481:1481) (1494:1494:1494)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (2234:2234:2234) (2331:2331:2331)) + (IOPATH i o (481:481:481) (733:733:733)) ) ) ) @@ -1255,13 +2110,66 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (1470:1470:1470) (1557:1557:1557)) - (PORT datad (1650:1650:1650) (1825:1825:1825)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (1829:1829:1829) (2002:2002:2002)) + (PORT datad (1582:1582:1582) (1705:1705:1705)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1347:1347:1347)) + (PORT datac (239:239:239) (315:315:315)) + (PORT datad (972:972:972) (1036:1036:1036)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (4802:4802:4802) (4948:4948:4948)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (1216:1216:1216) (1281:1281:1281)) + (PORT datad (980:980:980) (1041:1041:1041)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -1276,7 +2184,7 @@ (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (741:741:741)) + (PORT dataa (680:680:680) (750:750:750)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1288,10 +2196,10 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (372:372:372) (407:407:407)) - (PORT datad (630:630:630) (642:642:642)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (761:761:761) (768:768:768)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -1300,7 +2208,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1314,7 +2222,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (460:460:460) (524:524:524)) + (PORT datab (655:655:655) (734:734:734)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1328,7 +2236,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (344:344:344)) + (PORT datad (809:809:809) (842:842:842)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1338,7 +2246,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1352,7 +2260,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (411:411:411) (488:488:488)) + (PORT datab (672:672:672) (743:743:743)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1366,8 +2274,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (865:865:865) (873:873:873)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1644:1644:1644) (1682:1682:1682)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1380,9 +2288,9 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (643:643:643) (698:698:698)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (643:643:643) (737:737:737)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1394,13 +2302,29 @@ (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (870:870:870) (883:883:883)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (585:585:585)) + (PORT datab (1407:1407:1407) (1558:1558:1558)) + (PORT datac (1640:1640:1640) (1700:1700:1700)) + (PORT datad (272:272:272) (352:352:352)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL @@ -1408,7 +2332,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (711:711:711)) + (PORT dataa (419:419:419) (490:490:490)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1422,8 +2346,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (876:876:876) (877:877:877)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (516:516:516) (546:546:546)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1433,10 +2357,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT datab (827:827:827) (881:881:881)) + (PORT dataa (1582:1582:1582) (1611:1611:1611)) + (PORT datab (1401:1401:1401) (1478:1478:1478)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (661:661:661) (723:723:723)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (693:693:693) (775:775:775)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1445,126 +2385,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (626:626:626) (651:651:651)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (518:518:518) (549:549:549)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT datab (1373:1373:1373) (1418:1418:1418)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (658:658:658) (673:673:673)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (731:731:731)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1457:1457:1457) (1474:1474:1474)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (542:542:542)) - (PORT datab (973:973:973) (1044:1044:1044)) - (PORT datac (708:708:708) (773:773:773)) - (PORT datad (740:740:740) (794:794:794)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1238:1238:1238) (1307:1307:1307)) - (PORT datab (920:920:920) (963:963:963)) - (PORT datac (651:651:651) (705:705:705)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (1079:1079:1079) (1140:1140:1140)) + (PORT dataa (416:416:416) (490:490:490)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1578,8 +2404,8 @@ (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (626:626:626) (651:651:651)) + (PORT datab (646:646:646) (668:668:668)) + (PORT datad (174:174:174) (198:198:198)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1590,8 +2416,8 @@ (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (868:868:868) (876:876:876)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1535:1535:1535) (1613:1613:1613)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1604,8 +2430,8 @@ (INSTANCE ula_\|video_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datab (265:265:265) (348:348:348)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datad (670:670:670) (749:749:749)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -1615,8 +2441,8 @@ (INSTANCE ula_\|video_\|vga_hc\~1) (DELAY (ABSOLUTE - (PORT datab (344:344:344) (377:377:377)) - (PORT datad (627:627:627) (653:653:653)) + (PORT datab (646:646:646) (668:668:668)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1627,8 +2453,8 @@ (INSTANCE ula_\|video_\|vga_hc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1429:1429:1429) (1430:1430:1430)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (661:661:661) (677:677:677)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1641,35 +2467,23 @@ (INSTANCE ula_\|video_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (269:269:269)) - (PORT datab (1253:1253:1253) (1334:1334:1334)) - (PORT datac (909:909:909) (963:963:963)) - (PORT datad (873:873:873) (928:928:928)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (1591:1591:1591) (1646:1646:1646)) + (PORT datac (696:696:696) (764:764:764)) + (PORT datad (720:720:720) (765:765:765)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (1244:1244:1244) (1316:1316:1316)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (711:711:711) (769:769:769)) + (PORT datab (1351:1351:1351) (1394:1394:1394)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1680,39 +2494,36 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT dataa (656:656:656) (703:703:703)) - (PORT datab (1503:1503:1503) (1521:1521:1521)) - (PORT datad (594:594:594) (607:607:607)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (647:647:647) (669:669:669)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1541:1541:1541) (1586:1586:1586)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~4) + (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (678:678:678) (738:738:738)) + (PORT datab (705:705:705) (779:779:779)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1721,172 +2532,84 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (705:705:705)) - (PORT datab (638:638:638) (664:664:664)) - (PORT datad (1466:1466:1466) (1485:1485:1485)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[2\]) + (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (694:694:694) (728:728:728)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datab (704:704:704) (764:764:764)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (701:701:701)) - (PORT datab (1504:1504:1504) (1520:1520:1520)) - (PORT datad (597:597:597) (611:611:611)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[3\]) + (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (516:516:516) (547:547:547)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~8) + (INSTANCE ula_\|video_\|Add1\~0) (DELAY (ABSOLUTE - (PORT dataa (965:965:965) (1008:1008:1008)) + (PORT dataa (771:771:771) (834:834:834)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (704:704:704)) - (PORT datab (669:669:669) (683:683:683)) - (PORT datad (1464:1464:1464) (1484:1484:1484)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1692:1692:1692) (1765:1765:1765)) + (PORT datab (648:648:648) (701:701:701)) + (PORT datac (732:732:732) (794:794:794)) + (PORT datad (720:720:720) (777:777:777)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT datab (735:735:735) (804:804:804)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (612:612:612) (672:672:672)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (706:706:706)) - (PORT datab (1508:1508:1508) (1524:1524:1524)) - (PORT datad (585:585:585) (600:600:600)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT dataa (966:966:966) (1010:1010:1010)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (631:631:631) (686:686:686)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1898,11 +2621,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (701:701:701) (726:726:726)) - (PORT datab (586:586:586) (616:616:616)) - (PORT datad (775:775:775) (772:772:772)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (719:719:719) (748:748:748)) + (PORT datab (568:568:568) (584:584:584)) + (PORT datad (1643:1643:1643) (1683:1683:1683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1913,7 +2636,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1927,7 +2650,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (965:965:965) (1025:1025:1025)) + (PORT datab (948:948:948) (1001:1001:1001)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -1941,9 +2664,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (699:699:699) (723:723:723)) - (PORT datab (1070:1070:1070) (1068:1068:1068)) - (PORT datad (558:558:558) (576:576:576)) + (PORT dataa (710:710:710) (738:738:738)) + (PORT datab (796:796:796) (789:789:789)) + (PORT datad (1638:1638:1638) (1675:1675:1675)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -1956,7 +2679,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -1970,9 +2693,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (954:954:954) (1004:1004:1004)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (676:676:676) (729:729:729)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -1984,9 +2707,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (726:726:726)) - (PORT datab (1128:1128:1128) (1126:1126:1126)) - (PORT datad (558:558:558) (578:578:578)) + (PORT dataa (708:708:708) (737:737:737)) + (PORT datab (760:760:760) (776:776:776)) + (PORT datad (1638:1638:1638) (1675:1675:1675)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -1999,7 +2722,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -2013,8 +2736,8 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (644:644:644) (702:702:702)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (770:770:770) (831:831:831)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -2024,11 +2747,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (702:702:702) (724:724:724)) - (PORT datab (586:586:586) (613:613:613)) - (PORT datad (781:781:781) (782:782:782)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (707:707:707) (735:735:735)) + (PORT datab (528:528:528) (551:551:551)) + (PORT datad (1638:1638:1638) (1675:1675:1675)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2039,7 +2762,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -2048,31 +2771,15 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (378:378:378)) - (PORT datab (715:715:715) (775:775:775)) - (PORT datac (648:648:648) (714:714:714)) - (PORT datad (1179:1179:1179) (1245:1245:1245)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (493:493:493)) - (PORT datab (290:290:290) (374:374:374)) - (PORT datac (250:250:250) (333:333:333)) - (PORT datad (421:421:421) (482:482:482)) + (PORT dataa (272:272:272) (362:362:362)) + (PORT datab (290:290:290) (375:375:375)) + (PORT datac (268:268:268) (354:354:354)) + (PORT datad (250:250:250) (325:325:325)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2085,10 +2792,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (484:484:484)) - (PORT datab (873:873:873) (896:896:896)) - (PORT datac (620:620:620) (674:674:674)) - (PORT datad (590:590:590) (603:603:603)) + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (962:962:962) (1011:1011:1011)) + (PORT datac (584:584:584) (634:634:634)) + (PORT datad (566:566:566) (571:571:571)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2101,11 +2808,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (704:704:704)) - (PORT datab (1503:1503:1503) (1523:1523:1523)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (712:712:712) (741:741:741)) + (PORT datab (531:531:531) (559:559:559)) + (PORT datad (1639:1639:1639) (1677:1677:1677)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2116,7 +2823,209 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (759:759:759) (818:818:818)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (746:746:746)) + (PORT datab (537:537:537) (557:557:557)) + (PORT datad (1642:1642:1642) (1681:1681:1681)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (648:648:648) (706:706:706)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1222:1222:1222)) + (PORT datab (561:561:561) (582:582:582)) + (PORT datac (1111:1111:1111) (1119:1119:1119)) + (PORT datad (1053:1053:1053) (1064:1064:1064)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT asdata (865:865:865) (883:883:883)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1690:1690:1690) (1763:1763:1763)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (733:733:733)) + (PORT datab (573:573:573) (598:598:598)) + (PORT datad (1637:1637:1637) (1674:1674:1674)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (944:944:944) (1001:1001:1001)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (747:747:747)) + (PORT datab (533:533:533) (549:549:549)) + (PORT datad (1643:1643:1643) (1676:1676:1676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (749:749:749)) + (PORT datab (568:568:568) (587:587:587)) + (PORT datad (1643:1643:1643) (1683:1683:1683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1555:1555:1555)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -2130,10 +3039,10 @@ (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (488:488:488)) - (PORT datab (715:715:715) (775:775:775)) - (PORT datac (648:648:648) (712:712:712)) - (PORT datad (372:372:372) (442:442:442)) + (PORT dataa (771:771:771) (838:838:838)) + (PORT datab (651:651:651) (707:707:707)) + (PORT datac (727:727:727) (785:785:785)) + (PORT datad (1662:1662:1662) (1717:1717:1717)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2146,11 +3055,11 @@ (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (385:385:385)) - (PORT datac (620:620:620) (674:674:674)) - (PORT datad (591:591:591) (604:604:604)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (610:610:610) (669:669:669)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (562:562:562) (567:567:567)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -2169,10 +3078,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (919:919:919) (997:997:997)) - (PORT datab (946:946:946) (1004:1004:1004)) - (PORT datac (905:905:905) (970:970:970)) - (PORT datad (1292:1292:1292) (1213:1213:1213)) + (PORT dataa (665:665:665) (739:739:739)) + (PORT datab (712:712:712) (790:790:790)) + (PORT datac (655:655:655) (724:724:724)) + (PORT datad (1468:1468:1468) (1399:1399:1399)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2182,54 +3091,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (INSTANCE z80_\|ir_\|opcode\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (1393:1393:1393) (1460:1460:1460)) - (PORT datad (1899:1899:1899) (2006:2006:2006)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (242:242:242) (284:284:284)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (784:784:784) (852:852:852)) - (PORT datab (1496:1496:1496) (1609:1609:1609)) - (PORT datac (1839:1839:1839) (1973:1973:1973)) - (PORT datad (1690:1690:1690) (1763:1763:1763)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1270:1270:1270) (1342:1342:1342)) + (PORT datab (421:421:421) (491:491:491)) + (PORT datad (983:983:983) (1038:1038:1038)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (1772:1772:1772) (1878:1878:1878)) - (PORT datad (331:331:331) (359:359:359)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (408:408:408) (485:485:485)) - (PORT datab (707:707:707) (759:759:759)) - (PORT datad (898:898:898) (912:912:912)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1258:1258:1258) (1328:1328:1328)) + (PORT datab (408:408:408) (483:483:483)) + (PORT datad (978:978:978) (1042:1042:1042)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2240,9 +3150,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -2251,284 +3161,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1418:1418:1418) (1546:1546:1546)) - (PORT datad (934:934:934) (1041:1041:1041)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1912:1912:1912) (2001:2001:2001)) - (PORT datab (207:207:207) (250:250:250)) - (PORT datac (622:622:622) (681:681:681)) - (PORT datad (1605:1605:1605) (1758:1758:1758)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1771:1771:1771) (1874:1874:1874)) - (PORT datab (1642:1642:1642) (1796:1796:1796)) - (PORT datad (1883:1883:1883) (1955:1955:1955)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1549:1549:1549) (1644:1644:1644)) - (PORT datab (263:263:263) (310:310:310)) - (PORT datac (1465:1465:1465) (1503:1503:1503)) - (PORT datad (1184:1184:1184) (1237:1237:1237)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (855:855:855)) - (PORT datab (770:770:770) (837:837:837)) - (PORT datac (1831:1831:1831) (1966:1966:1966)) - (PORT datad (1685:1685:1685) (1757:1757:1757)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1295:1295:1295)) - (PORT datac (924:924:924) (977:977:977)) - (PORT datad (1184:1184:1184) (1237:1237:1237)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (713:713:713)) - (PORT datac (679:679:679) (726:726:726)) - (PORT datad (895:895:895) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1515:1515:1515)) - (PORT datab (2217:2217:2217) (2404:2404:2404)) - (PORT datac (387:387:387) (452:452:452)) - (PORT datad (308:308:308) (411:411:411)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1182:1182:1182) (1247:1247:1247)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datad (1180:1180:1180) (1243:1243:1243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (1537:1537:1537) (1637:1637:1637)) - (PORT datac (1180:1180:1180) (1248:1248:1248)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1263:1263:1263)) - (PORT datab (1222:1222:1222) (1236:1236:1236)) - (PORT datac (2271:2271:2271) (2399:2399:2399)) - (PORT datad (364:364:364) (396:396:396)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2287:2287:2287) (2396:2396:2396)) - (PORT datab (2178:2178:2178) (2359:2359:2359)) - (PORT datac (1216:1216:1216) (1300:1300:1300)) - (PORT datad (874:874:874) (939:939:939)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (434:434:434)) - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (1000:1000:1000) (1080:1080:1080)) - (PORT datad (1503:1503:1503) (1556:1556:1556)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (420:420:420) (502:502:502)) - (PORT datab (708:708:708) (757:757:757)) - (PORT datad (899:899:899) (915:915:915)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1247:1247:1247) (1320:1320:1320)) + (PORT datab (265:265:265) (348:348:348)) + (PORT datad (985:985:985) (1039:1039:1039)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2539,9 +3181,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -2550,2264 +3192,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2484:2484:2484) (2682:2682:2682)) - (PORT datab (1562:1562:1562) (1651:1651:1651)) - (PORT datac (1193:1193:1193) (1280:1280:1280)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2561:2561:2561) (2633:2633:2633)) - (PORT datac (2429:2429:2429) (2625:2625:2625)) - (PORT datad (1838:1838:1838) (1929:1929:1929)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1982:1982:1982) (2048:2048:2048)) - (PORT datab (2103:2103:2103) (2239:2239:2239)) - (PORT datac (1465:1465:1465) (1540:1540:1540)) - (PORT datad (209:209:209) (246:246:246)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT datab (2490:2490:2490) (2690:2690:2690)) - (PORT datac (2152:2152:2152) (2252:2252:2252)) - (PORT datad (1470:1470:1470) (1560:1560:1560)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (722:722:722)) - (PORT datac (1428:1428:1428) (1511:1511:1511)) - (PORT datad (659:659:659) (735:735:735)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT datac (590:590:590) (659:659:659)) - (PORT datad (661:661:661) (738:738:738)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT datab (1181:1181:1181) (1258:1258:1258)) - (PORT datac (1491:1491:1491) (1604:1604:1604)) - (PORT datad (1204:1204:1204) (1275:1275:1275)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~2) - (DELAY - (ABSOLUTE - (PORT datab (1624:1624:1624) (1780:1780:1780)) - (PORT datad (1680:1680:1680) (1802:1802:1802)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2561:2561:2561) (2630:2630:2630)) - (PORT datab (2468:2468:2468) (2666:2666:2666)) - (PORT datac (1469:1469:1469) (1544:1544:1544)) - (PORT datad (1838:1838:1838) (1932:1932:1932)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (258:258:258) (308:308:308)) - (PORT datab (897:897:897) (907:907:907)) - (PORT datac (1280:1280:1280) (1332:1332:1332)) - (PORT datad (793:793:793) (839:839:839)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datab (1654:1654:1654) (1808:1808:1808)) - (PORT datad (1815:1815:1815) (1894:1894:1894)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (501:501:501)) - (PORT datad (247:247:247) (319:319:319)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1699:1699:1699) (1795:1795:1795)) - (PORT datab (1125:1125:1125) (1202:1202:1202)) - (PORT datac (896:896:896) (937:937:937)) - (PORT datad (1966:1966:1966) (2037:2037:2037)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1044:1044:1044) (1135:1135:1135)) - (PORT datad (1269:1269:1269) (1357:1357:1357)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1067:1067:1067)) - (PORT datab (1506:1506:1506) (1576:1576:1576)) - (PORT datac (1078:1078:1078) (1094:1094:1094)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1081:1081:1081)) - (PORT datab (741:741:741) (845:845:845)) - (PORT datac (909:909:909) (983:983:983)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (705:705:705) (809:809:809)) - (PORT datad (697:697:697) (796:796:796)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (681:681:681)) - (PORT datab (640:640:640) (663:663:663)) - (PORT datac (341:341:341) (362:362:362)) - (PORT datad (609:609:609) (621:621:621)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1625:1625:1625) (1667:1667:1667)) - (PORT datad (616:616:616) (648:648:648)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (922:922:922)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (1049:1049:1049) (1089:1089:1089)) - (PORT datad (1211:1211:1211) (1321:1321:1321)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~3) - (DELAY - (ABSOLUTE - (PORT datab (745:745:745) (845:845:845)) - (PORT datac (970:970:970) (1032:1032:1032)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT datab (1607:1607:1607) (1747:1747:1747)) - (PORT datad (1859:1859:1859) (1958:1958:1958)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (286:286:286)) - (PORT datab (1368:1368:1368) (1395:1395:1395)) - (PORT datac (1649:1649:1649) (1746:1746:1746)) - (PORT datad (1692:1692:1692) (1750:1750:1750)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datac (667:667:667) (737:737:737)) - (PORT datad (669:669:669) (753:753:753)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (1044:1044:1044) (1136:1136:1136)) - (PORT datad (1269:1269:1269) (1359:1359:1359)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2136:2136:2136) (2306:2306:2306)) - (PORT datab (1472:1472:1472) (1496:1496:1496)) - (PORT datac (1120:1120:1120) (1150:1150:1150)) - (PORT datad (648:648:648) (671:671:671)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1181:1181:1181)) - (PORT datab (899:899:899) (952:952:952)) - (PORT datac (1409:1409:1409) (1473:1473:1473)) - (PORT datad (637:637:637) (678:678:678)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1859:1859:1859) (1941:1941:1941)) - (PORT datab (1653:1653:1653) (1803:1803:1803)) - (PORT datac (1713:1713:1713) (1796:1796:1796)) - (PORT datad (879:879:879) (896:896:896)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT datab (1578:1578:1578) (1721:1721:1721)) - (PORT datac (1756:1756:1756) (1850:1850:1850)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1491:1491:1491)) - (PORT datab (1499:1499:1499) (1601:1601:1601)) - (PORT datac (1236:1236:1236) (1278:1278:1278)) - (PORT datad (1212:1212:1212) (1250:1250:1250)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (1120:1120:1120) (1175:1175:1175)) - (PORT datac (1695:1695:1695) (1735:1735:1735)) - (PORT datad (989:989:989) (1018:1018:1018)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (948:948:948)) - (PORT datab (683:683:683) (708:708:708)) - (PORT datac (2084:2084:2084) (2256:2256:2256)) - (PORT datad (909:909:909) (931:931:931)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1700:1700:1700) (1791:1791:1791)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (899:899:899) (937:937:937)) - (PORT datad (928:928:928) (989:989:989)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1659:1659:1659) (1811:1811:1811)) - (PORT datad (1814:1814:1814) (1891:1891:1891)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1700:1700:1700) (1795:1795:1795)) - (PORT datab (250:250:250) (298:298:298)) - (PORT datac (898:898:898) (934:934:934)) - (PORT datad (1153:1153:1153) (1208:1208:1208)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1678:1678:1678) (1695:1695:1695)) - (PORT datab (1374:1374:1374) (1396:1396:1396)) - (PORT datac (2514:2514:2514) (2557:2557:2557)) - (PORT datad (1128:1128:1128) (1145:1145:1145)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (940:940:940)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1113:1113:1113) (1189:1189:1189)) - (PORT datad (961:961:961) (1053:1053:1053)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (510:510:510)) - (PORT datab (706:706:706) (761:761:761)) - (PORT datad (892:892:892) (915:915:915)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1079:1079:1079)) - (PORT datac (670:670:670) (776:776:776)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (2272:2272:2272) (2458:2458:2458)) - (PORT datad (1247:1247:1247) (1340:1340:1340)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (677:677:677)) - (PORT datab (1376:1376:1376) (1393:1393:1393)) - (PORT datac (1649:1649:1649) (1659:1659:1659)) - (PORT datad (908:908:908) (928:928:928)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (938:938:938)) - (PORT datab (348:348:348) (377:377:377)) - (PORT datac (614:614:614) (637:637:637)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1325:1325:1325) (1382:1382:1382)) - (PORT datab (967:967:967) (991:991:991)) - (PORT datac (1402:1402:1402) (1542:1542:1542)) - (PORT datad (1180:1180:1180) (1240:1240:1240)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (260:260:260) (343:343:343)) - (PORT datac (234:234:234) (310:310:310)) - (PORT datad (391:391:391) (462:462:462)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (503:503:503)) - (PORT datab (1696:1696:1696) (1768:1768:1768)) - (PORT datac (1831:1831:1831) (1963:1963:1963)) - (PORT datad (780:780:780) (842:842:842)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (504:504:504)) - (PORT datab (1697:1697:1697) (1767:1767:1767)) - (PORT datac (1832:1832:1832) (1964:1964:1964)) - (PORT datad (781:781:781) (840:840:840)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (505:505:505)) - (PORT datab (1700:1700:1700) (1770:1770:1770)) - (PORT datac (1842:1842:1842) (1975:1975:1975)) - (PORT datad (787:787:787) (845:845:845)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1501:1501:1501)) - (PORT datab (641:641:641) (679:679:679)) - (PORT datac (647:647:647) (693:693:693)) - (PORT datad (648:648:648) (679:679:679)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (774:774:774)) - (PORT datab (1409:1409:1409) (1519:1519:1519)) - (PORT datac (1370:1370:1370) (1480:1480:1480)) - (PORT datad (682:682:682) (744:744:744)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1272:1272:1272)) - (PORT datab (969:969:969) (1014:1014:1014)) - (PORT datac (672:672:672) (779:779:779)) - (PORT datad (693:693:693) (794:794:794)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1407:1407:1407)) - (PORT datab (1154:1154:1154) (1254:1254:1254)) - (PORT datac (671:671:671) (779:779:779)) - (PORT datad (693:693:693) (794:794:794)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (2512:2512:2512) (2579:2579:2579)) - (PORT datab (239:239:239) (277:277:277)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1711:1711:1711) (1689:1689:1689)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (935:935:935)) - (PORT datab (348:348:348) (381:381:381)) - (PORT datad (336:336:336) (362:362:362)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1633:1633:1633) (1765:1765:1765)) - (PORT datab (1559:1559:1559) (1648:1648:1648)) - (PORT datac (1677:1677:1677) (1756:1756:1756)) - (PORT datad (1743:1743:1743) (1852:1852:1852)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1190:1190:1190)) - (PORT datab (1492:1492:1492) (1531:1531:1531)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (781:781:781) (835:835:835)) - (PORT datac (973:973:973) (1029:1029:1029)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1813:1813:1813) (1882:1882:1882)) - (PORT datab (1074:1074:1074) (1139:1139:1139)) - (PORT datac (1722:1722:1722) (1803:1803:1803)) - (PORT datad (217:217:217) (256:256:256)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1474:1474:1474)) - (PORT datad (1994:1994:1994) (2071:2071:2071)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1484:1484:1484)) - (PORT datab (854:854:854) (902:902:902)) - (PORT datac (909:909:909) (971:971:971)) - (PORT datad (616:616:616) (647:647:647)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1296:1296:1296)) - (PORT datab (266:266:266) (314:314:314)) - (PORT datac (928:928:928) (983:983:983)) - (PORT datad (1184:1184:1184) (1243:1243:1243)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (591:591:591)) - (PORT datab (1349:1349:1349) (1470:1470:1470)) - (PORT datac (808:808:808) (820:820:820)) - (PORT datad (834:834:834) (910:910:910)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1860:1860:1860) (1945:1945:1945)) - (PORT datab (1656:1656:1656) (1813:1813:1813)) - (PORT datac (1723:1723:1723) (1804:1804:1804)) - (PORT datad (880:880:880) (899:899:899)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT datab (1616:1616:1616) (1771:1771:1771)) - (PORT datac (1389:1389:1389) (1456:1456:1456)) - (PORT datad (1311:1311:1311) (1374:1374:1374)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT datab (2076:2076:2076) (2209:2209:2209)) - (PORT datad (933:933:933) (1039:1039:1039)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (985:985:985)) - (PORT datab (1376:1376:1376) (1394:1394:1394)) - (PORT datac (1649:1649:1649) (1659:1659:1659)) - (PORT datad (1168:1168:1168) (1213:1213:1213)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (935:935:935)) - (PORT datab (698:698:698) (760:760:760)) - (PORT datac (915:915:915) (959:959:959)) - (PORT datad (661:661:661) (719:719:719)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1181:1181:1181) (1224:1224:1224)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (873:873:873) (934:934:934)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1059:1059:1059)) - (PORT datab (1999:1999:1999) (2042:2042:2042)) - (PORT datac (1001:1001:1001) (1029:1029:1029)) - (PORT datad (1097:1097:1097) (1148:1148:1148)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) - (DELAY - (ABSOLUTE - (PORT dataa (2428:2428:2428) (2599:2599:2599)) - (PORT datab (1208:1208:1208) (1296:1296:1296)) - (PORT datac (1399:1399:1399) (1508:1508:1508)) - (PORT datad (555:555:555) (574:574:574)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (509:509:509)) - (PORT datab (767:767:767) (841:841:841)) - (PORT datac (1069:1069:1069) (1085:1085:1085)) - (PORT datad (787:787:787) (850:850:850)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2204:2204:2204) (2398:2398:2398)) - (PORT datab (686:686:686) (707:707:707)) - (PORT datac (835:835:835) (875:875:875)) - (PORT datad (1872:1872:1872) (2005:2005:2005)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1772:1772:1772) (1872:1872:1872)) - (PORT datab (739:739:739) (800:800:800)) - (PORT datac (1861:1861:1861) (1915:1915:1915)) - (PORT datad (1607:1607:1607) (1753:1753:1753)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (894:894:894)) - (PORT datab (1876:1876:1876) (2012:2012:2012)) - (PORT datac (328:328:328) (351:351:351)) - (PORT datad (1690:1690:1690) (1763:1763:1763)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (1013:1013:1013)) - (PORT datab (1893:1893:1893) (2038:2038:2038)) - (PORT datac (2174:2174:2174) (2358:2358:2358)) - (PORT datad (955:955:955) (995:995:995)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT datab (1677:1677:1677) (1729:1729:1729)) - (PORT datad (2190:2190:2190) (2227:2227:2227)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_ir_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1356:1356:1356)) - (PORT datab (662:662:662) (720:720:720)) - (PORT datac (856:856:856) (884:884:884)) - (PORT datad (846:846:846) (874:874:874)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1482:1482:1482)) - (PORT datab (1494:1494:1494) (1558:1558:1558)) - (PORT datac (1227:1227:1227) (1257:1257:1257)) - (PORT datad (932:932:932) (1002:1002:1002)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (897:897:897) (961:961:961)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1756:1756:1756) (1851:1851:1851)) - (PORT datab (1657:1657:1657) (1809:1809:1809)) - (PORT datad (1812:1812:1812) (1893:1893:1893)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (994:994:994) (1075:1075:1075)) - (PORT datac (1310:1310:1310) (1404:1404:1404)) - (PORT datad (914:914:914) (958:958:958)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (2680:2680:2680) (2765:2765:2765)) - (PORT datab (751:751:751) (781:781:781)) - (PORT datac (998:998:998) (1052:1052:1052)) - (PORT datad (890:890:890) (939:939:939)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1052:1052:1052)) - (PORT datac (1080:1080:1080) (1095:1095:1095)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datab (1557:1557:1557) (1643:1643:1643)) - (PORT datac (1196:1196:1196) (1284:1284:1284)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (994:994:994) (1076:1076:1076)) - (PORT datab (1450:1450:1450) (1484:1484:1484)) - (PORT datac (1313:1313:1313) (1404:1404:1404)) - (PORT datad (917:917:917) (957:957:957)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1288:1288:1288)) - (PORT datab (627:627:627) (676:676:676)) - (PORT datac (1171:1171:1171) (1187:1187:1187)) - (PORT datad (1954:1954:1954) (2068:2068:2068)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1328:1328:1328)) - (PORT datab (1374:1374:1374) (1512:1512:1512)) - (PORT datac (2247:2247:2247) (2354:2354:2354)) - (PORT datad (2399:2399:2399) (2556:2556:2556)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (885:885:885)) - (PORT datab (1869:1869:1869) (2005:2005:2005)) - (PORT datac (325:325:325) (347:347:347)) - (PORT datad (1684:1684:1684) (1756:1756:1756)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1393:1393:1393)) - (PORT datab (650:650:650) (695:695:695)) - (PORT datac (2228:2228:2228) (2301:2301:2301)) - (PORT datad (2014:2014:2014) (2108:2108:2108)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1327:1327:1327)) - (PORT datab (1429:1429:1429) (1544:1544:1544)) - (PORT datac (2248:2248:2248) (2352:2352:2352)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (810:810:810) (838:838:838)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1654:1654:1654) (1725:1725:1725)) - (PORT datac (907:907:907) (930:930:930)) - (PORT datad (1391:1391:1391) (1460:1460:1460)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1571:1571:1571) (1642:1642:1642)) - (PORT datab (2001:2001:2001) (2042:2042:2042)) - (PORT datac (1133:1133:1133) (1159:1159:1159)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2683:2683:2683) (2764:2764:2764)) - (PORT datab (1030:1030:1030) (1061:1061:1061)) - (PORT datac (798:798:798) (876:876:876)) - (PORT datad (715:715:715) (740:740:740)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (624:624:624)) - (PORT datab (789:789:789) (834:834:834)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (1008:1008:1008)) - (PORT datab (1184:1184:1184) (1250:1250:1250)) - (PORT datac (1904:1904:1904) (1966:1966:1966)) - (PORT datad (644:644:644) (669:669:669)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1681:1681:1681) (1756:1756:1756)) - (PORT datab (574:574:574) (580:580:580)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (352:352:352) (375:375:375)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (418:418:418)) - (PORT datab (925:925:925) (988:988:988)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1103:1103:1103) (1103:1103:1103)) + (PORT dataa (972:972:972) (1071:1071:1071)) + (PORT datac (977:977:977) (1074:1074:1074)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT datab (1374:1374:1374) (1494:1494:1494)) - (PORT datad (976:976:976) (1058:1058:1058)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (657:657:657)) - (PORT datab (814:814:814) (879:879:879)) - (PORT datac (1743:1743:1743) (1807:1807:1807)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1255:1255:1255)) - (PORT datab (805:805:805) (887:887:887)) - (PORT datac (798:798:798) (880:880:880)) - (PORT datad (889:889:889) (937:937:937)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1253:1253:1253) (1284:1284:1284)) - (PORT datac (1036:1036:1036) (1054:1054:1054)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (909:909:909)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (656:656:656)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (353:353:353) (384:384:384)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT datab (1558:1558:1558) (1645:1645:1645)) - (PORT datac (1678:1678:1678) (1754:1754:1754)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1468:1468:1468)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1209:1209:1209) (1317:1317:1317)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1935:1935:1935) (2103:2103:2103)) - (PORT datac (1169:1169:1169) (1247:1247:1247)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (295:295:295)) - (PORT datab (1549:1549:1549) (1663:1663:1663)) - (PORT datac (1712:1712:1712) (1799:1799:1799)) - (PORT datad (1313:1313:1313) (1326:1326:1326)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1524:1524:1524) (1519:1519:1519)) - (PORT datab (1191:1191:1191) (1249:1249:1249)) - (PORT datac (630:630:630) (682:682:682)) - (PORT datad (632:632:632) (687:687:687)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1044:1044:1044) (1133:1133:1133)) - (PORT datad (1271:1271:1271) (1354:1354:1354)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2306:2306:2306) (2424:2424:2424)) - (PORT datac (1346:1346:1346) (1529:1529:1529)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1886:1886:1886) (2000:2000:2000)) - (PORT datab (1612:1612:1612) (1752:1752:1752)) - (PORT datac (1469:1469:1469) (1530:1530:1530)) - (PORT datad (1053:1053:1053) (1100:1100:1100)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (658:658:658)) - (PORT datab (1360:1360:1360) (1377:1377:1377)) - (PORT datac (631:631:631) (639:639:639)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1212:1212:1212)) - (PORT datab (661:661:661) (716:716:716)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (595:595:595) (628:628:628)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1557:1557:1557)) - (PORT ena (1244:1244:1244) (1252:1252:1252)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1539:1539:1539)) - (PORT asdata (702:702:702) (770:770:770)) - (PORT clrn (1579:1579:1579) (1556:1556:1556)) - (PORT ena (1442:1442:1442) (1450:1450:1450)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (655:655:655) (727:727:727)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT asdata (567:567:567) (643:643:643)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (250:250:250) (333:333:333)) - (PORT datad (655:655:655) (722:722:722)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1644:1644:1644)) - (PORT datac (1464:1464:1464) (1503:1503:1503)) - (PORT datad (1184:1184:1184) (1237:1237:1237)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (278:278:278)) - (PORT datab (221:221:221) (268:268:268)) - (PORT datac (996:996:996) (1082:1082:1082)) - (PORT datad (1499:1499:1499) (1549:1549:1549)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1276:1276:1276)) - (PORT datab (1869:1869:1869) (1945:1945:1945)) - (PORT datac (1029:1029:1029) (1095:1095:1095)) - (PORT datad (1021:1021:1021) (1078:1078:1078)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1764:1764:1764) (1856:1856:1856)) - (PORT datab (654:654:654) (690:690:690)) - (PORT datad (1598:1598:1598) (1743:1743:1743)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (958:958:958)) - (PORT datab (1244:1244:1244) (1298:1298:1298)) - (PORT datac (827:827:827) (870:870:870)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1017:1017:1017)) - (PORT datab (993:993:993) (1040:1040:1040)) - (PORT datac (2018:2018:2018) (2124:2124:2124)) - (PORT datad (1484:1484:1484) (1600:1600:1600)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (1506:1506:1506) (1597:1597:1597)) - (PORT datac (1719:1719:1719) (1859:1859:1859)) - (PORT datad (646:646:646) (663:663:663)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (658:658:658)) - (PORT datab (1777:1777:1777) (1839:1839:1839)) - (PORT datac (901:901:901) (951:951:951)) - (PORT datad (577:577:577) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (640:640:640)) - (PORT datab (656:656:656) (693:693:693)) - (PORT datac (1397:1397:1397) (1513:1513:1513)) - (PORT datad (1771:1771:1771) (1867:1867:1867)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (674:674:674)) - (PORT datab (1187:1187:1187) (1225:1225:1225)) - (PORT datac (905:905:905) (945:945:945)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (647:647:647)) - (PORT datab (1785:1785:1785) (1851:1851:1851)) - (PORT datac (843:843:843) (884:884:884)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datab (2599:2599:2599) (2784:2784:2784)) - (PORT datac (2013:2013:2013) (2151:2151:2151)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1681:1681:1681) (1696:1696:1696)) - (PORT datab (1665:1665:1665) (1691:1691:1691)) - (PORT datac (1340:1340:1340) (1357:1357:1357)) - (PORT datad (1137:1137:1137) (1157:1157:1157)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (966:966:966)) - (PORT datab (1226:1226:1226) (1311:1311:1311)) - (PORT datac (667:667:667) (748:748:748)) - (PORT datad (672:672:672) (721:721:721)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (763:763:763)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1172:1172:1172) (1211:1211:1211)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1266:1266:1266) (1320:1320:1320)) - (PORT datab (1090:1090:1090) (1146:1146:1146)) - (PORT datac (1387:1387:1387) (1457:1457:1457)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1553:1553:1553)) - (PORT datab (1507:1507:1507) (1626:1626:1626)) - (PORT datac (1410:1410:1410) (1520:1520:1520)) - (PORT datad (1406:1406:1406) (1453:1453:1453)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (640:640:640) (681:681:681)) - (PORT datac (1761:1761:1761) (1841:1841:1841)) - (PORT datad (650:650:650) (681:681:681)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT datac (1195:1195:1195) (1279:1279:1279)) - (PORT datad (1192:1192:1192) (1245:1245:1245)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1453:1453:1453) (1558:1558:1558)) - (PORT datab (1151:1151:1151) (1192:1192:1192)) - (PORT datac (647:647:647) (693:693:693)) - (PORT datad (1478:1478:1478) (1588:1588:1588)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT datac (1200:1200:1200) (1285:1285:1285)) - (PORT datad (1195:1195:1195) (1248:1248:1248)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (698:698:698)) - (PORT datab (247:247:247) (290:290:290)) - (PORT datac (913:913:913) (969:969:969)) - (PORT datad (845:845:845) (863:863:863)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (966:966:966)) - (PORT datab (897:897:897) (948:948:948)) - (PORT datac (882:882:882) (919:919:919)) - (PORT datad (593:593:593) (606:606:606)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1541:1541:1541)) - (PORT datad (1222:1222:1222) (1311:1311:1311)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (655:655:655)) - (PORT datab (821:821:821) (865:865:865)) - (PORT datac (1104:1104:1104) (1130:1130:1130)) - (PORT datad (2384:2384:2384) (2430:2430:2430)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1585:1585:1585) (1562:1562:1562)) - (PORT ena (1197:1197:1197) (1197:1197:1197)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (288:288:288)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1585:1585:1585) (1562:1562:1562)) - (PORT ena (1171:1171:1171) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (882:882:882) (959:959:959)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (248:248:248) (331:331:331)) - (PORT datac (1026:1026:1026) (1073:1073:1073)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) @@ -4817,16 +3209,16 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clk (1526:1526:1526) (1530:1530:1530)) + (PORT asdata (1127:1127:1127) (1165:1165:1165)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1223:1223:1223) (1226:1226:1226)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -4835,8 +3227,8 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (217:217:217) (293:293:293)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -4845,10 +3237,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT clk (1526:1526:1526) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1223:1223:1223) (1226:1226:1226)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -4863,10 +3255,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1541:1541:1541)) - (PORT asdata (566:566:566) (642:642:642)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1280:1280:1280) (1296:1296:1296)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (568:568:568) (646:646:646)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1254:1254:1254) (1275:1275:1275)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -4881,9 +3273,9 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1120:1120:1120) (1187:1187:1187)) - (PORT datab (249:249:249) (332:332:332)) - (PORT datad (1382:1382:1382) (1442:1442:1442)) + (PORT dataa (1160:1160:1160) (1246:1246:1246)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datad (435:435:435) (499:499:499)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -4891,17 +3283,109 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1610:1610:1610) (1767:1767:1767)) + (PORT datab (1245:1245:1245) (1336:1336:1336)) + (PORT datac (2396:2396:2396) (2519:2519:2519)) + (PORT datad (1247:1247:1247) (1385:1385:1385)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1363:1363:1363)) + (PORT datac (1559:1559:1559) (1714:1714:1714)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT datac (1505:1505:1505) (1643:1643:1643)) + (PORT datad (1810:1810:1810) (1897:1897:1897)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (907:907:907) (979:979:979)) + (PORT datad (1870:1870:1870) (2002:2002:2002)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1294:1294:1294)) + (PORT datab (1229:1229:1229) (1313:1313:1313)) + (PORT datac (708:708:708) (779:779:779)) + (PORT datad (243:243:243) (296:296:296)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (993:993:993) (1073:1073:1073)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (1079:1079:1079) (1095:1095:1095)) - (PORT datad (1469:1469:1469) (1538:1538:1538)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (729:729:729) (769:769:769)) + (PORT datac (2939:2939:2939) (3072:3072:3072)) + (PORT datad (1124:1124:1124) (1159:1159:1159)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datab (1571:1571:1571) (1697:1697:1697)) + (PORT datac (1289:1289:1289) (1402:1402:1402)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datac (1052:1052:1052) (1157:1157:1157)) + (PORT datad (2076:2076:2076) (2218:2218:2218)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -4909,91 +3393,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) + (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT dataa (1309:1309:1309) (1371:1371:1371)) - (PORT datab (927:927:927) (1024:1024:1024)) - (PORT datac (1164:1164:1164) (1225:1225:1225)) - (PORT datad (1430:1430:1430) (1462:1462:1462)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1845:1845:1845)) - (PORT datab (1652:1652:1652) (1803:1803:1803)) - (PORT datac (1044:1044:1044) (1103:1103:1103)) - (PORT datad (1815:1815:1815) (1893:1893:1893)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datab (1607:1607:1607) (1746:1746:1746)) - (PORT datad (1856:1856:1856) (1958:1958:1958)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (311:311:311)) - (PORT datab (1677:1677:1677) (1826:1826:1826)) - (PORT datac (1288:1288:1288) (1378:1378:1378)) - (PORT datad (2871:2871:2871) (2927:2927:2927)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (312:312:312)) - (PORT datab (927:927:927) (1024:1024:1024)) - (PORT datac (1164:1164:1164) (1225:1225:1225)) - (PORT datad (1753:1753:1753) (1784:1784:1784)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1179:1179:1179)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1409:1409:1409) (1398:1398:1398)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datac (1484:1484:1484) (1559:1559:1559)) + (PORT datad (1217:1217:1217) (1295:1295:1295)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -5001,41 +3405,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) + (INSTANCE z80_\|execute_\|ctl_mRead\~3) (DELAY (ABSOLUTE - (PORT dataa (1622:1622:1622) (1658:1658:1658)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT dataa (448:448:448) (509:509:509)) - (PORT datad (602:602:602) (624:624:624)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (1454:1454:1454) (1538:1538:1538)) - (PORT datab (1435:1435:1435) (1471:1471:1471)) - (PORT datac (1347:1347:1347) (1529:1529:1529)) - (PORT datad (2534:2534:2534) (2622:2622:2622)) + (PORT dataa (1558:1558:1558) (1587:1587:1587)) + (PORT datab (725:725:725) (762:762:762)) + (PORT datac (2943:2943:2943) (3066:3066:3066)) + (PORT datad (1123:1123:1123) (1156:1156:1156)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -5043,337 +3419,121 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1194:1194:1194)) + (PORT datab (679:679:679) (714:714:714)) + (PORT datac (1449:1449:1449) (1513:1513:1513)) + (PORT datad (1129:1129:1129) (1153:1153:1153)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1370:1370:1370)) + (PORT datab (1689:1689:1689) (1864:1864:1864)) + (PORT datac (1228:1228:1228) (1340:1340:1340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1298:1298:1298)) + (PORT datac (1496:1496:1496) (1565:1565:1565)) + (PORT datad (2598:2598:2598) (2706:2706:2706)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (1455:1455:1455) (1620:1620:1620)) + (PORT datad (1251:1251:1251) (1383:1383:1383)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1558:1558:1558)) + (PORT datab (1277:1277:1277) (1342:1342:1342)) + (PORT datac (609:609:609) (624:624:624)) + (PORT datad (1252:1252:1252) (1367:1367:1367)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2130:2130:2130) (2347:2347:2347)) + (PORT datab (1568:1568:1568) (1699:1699:1699)) + (PORT datac (891:891:891) (940:940:940)) + (PORT datad (2016:2016:2016) (2098:2098:2098)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|decode_state_\|DFFE_instED) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (980:980:980) (1001:1001:1001)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (968:968:968) (972:972:972)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (INSTANCE z80_\|pla_decode_\|Equal6\~0) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (447:447:447)) - (PORT datab (862:862:862) (915:915:915)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1642:1642:1642)) - (PORT datab (265:265:265) (310:310:310)) - (PORT datac (1461:1461:1461) (1499:1499:1499)) - (PORT datad (1184:1184:1184) (1243:1243:1243)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1788:1788:1788)) - (PORT datab (243:243:243) (287:287:287)) - (PORT datac (1764:1764:1764) (1827:1827:1827)) - (PORT datad (810:810:810) (866:866:866)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (489:489:489)) - (PORT datab (1270:1270:1270) (1351:1351:1351)) - (PORT datac (1326:1326:1326) (1377:1377:1377)) - (PORT datad (651:651:651) (674:674:674)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT datab (654:654:654) (678:678:678)) - (PORT datac (852:852:852) (873:873:873)) - (PORT datad (866:866:866) (881:881:881)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (510:510:510)) - (PORT datab (1700:1700:1700) (1774:1774:1774)) - (PORT datac (1844:1844:1844) (1971:1971:1971)) - (PORT datad (788:788:788) (851:851:851)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT datab (1461:1461:1461) (1510:1510:1510)) - (PORT datac (1183:1183:1183) (1237:1237:1237)) - (PORT datad (1434:1434:1434) (1514:1514:1514)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (855:855:855)) - (PORT datab (768:768:768) (840:840:840)) - (PORT datac (1827:1827:1827) (1972:1972:1972)) - (PORT datad (1687:1687:1687) (1760:1760:1760)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (928:928:928)) - (PORT datab (1029:1029:1029) (1113:1113:1113)) - (PORT datac (1460:1460:1460) (1500:1500:1500)) - (PORT datad (1502:1502:1502) (1555:1555:1555)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (960:960:960)) - (PORT datab (880:880:880) (969:969:969)) - (PORT datac (1051:1051:1051) (1088:1088:1088)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT datab (631:631:631) (694:694:694)) - (PORT datac (802:802:802) (833:833:833)) - (PORT datad (852:852:852) (894:894:894)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1545:1545:1545) (1645:1645:1645)) - (PORT datac (1461:1461:1461) (1503:1503:1503)) - (PORT datad (1184:1184:1184) (1243:1243:1243)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1495:1495:1495) (1540:1540:1540)) - (PORT datab (958:958:958) (1015:1015:1015)) - (PORT datac (1200:1200:1200) (1255:1255:1255)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1240:1240:1240)) - (PORT datab (660:660:660) (687:687:687)) - (PORT datac (1667:1667:1667) (1700:1700:1700)) - (PORT datad (907:907:907) (984:984:984)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1812:1812:1812) (1880:1880:1880)) - (PORT datab (1075:1075:1075) (1143:1143:1143)) - (PORT datac (1721:1721:1721) (1798:1798:1798)) - (PORT datad (218:218:218) (257:257:257)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2132:2132:2132) (2307:2307:2307)) - (PORT datab (2626:2626:2626) (2718:2718:2718)) - (PORT datac (1370:1370:1370) (1475:1475:1475)) - (PORT datad (874:874:874) (899:899:899)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2265:2265:2265) (2343:2343:2343)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (623:623:623) (663:663:663)) - (PORT datad (1014:1014:1014) (1053:1053:1053)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT datab (1599:1599:1599) (1667:1667:1667)) - (PORT datac (1208:1208:1208) (1265:1265:1265)) - (PORT datad (1110:1110:1110) (1156:1156:1156)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1318:1318:1318) (1375:1375:1375)) - (PORT datab (970:970:970) (996:996:996)) - (PORT datac (1388:1388:1388) (1527:1527:1527)) - (PORT datad (1184:1184:1184) (1246:1246:1246)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (928:928:928)) - (PORT datab (1028:1028:1028) (1113:1113:1113)) - (PORT datac (1466:1466:1466) (1505:1505:1505)) - (PORT datad (1497:1497:1497) (1547:1547:1547)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (834:834:834)) - (PORT datab (606:606:606) (630:630:630)) - (PORT datac (1624:1624:1624) (1671:1671:1671)) - (PORT datad (1597:1597:1597) (1618:1618:1618)) + (PORT dataa (1738:1738:1738) (1849:1849:1849)) + (PORT datab (985:985:985) (1061:1061:1061)) + (PORT datac (680:680:680) (745:745:745)) + (PORT datad (872:872:872) (922:922:922)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -5383,12 +3543,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (703:703:703)) - (PORT datac (1119:1119:1119) (1126:1126:1126)) - (PORT datad (794:794:794) (865:865:865)) + (PORT dataa (1176:1176:1176) (1196:1196:1196)) + (PORT datac (1207:1207:1207) (1285:1285:1285)) + (PORT datad (808:808:808) (829:829:829)) (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -5397,1858 +3557,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (2137:2137:2137) (2307:2307:2307)) - (PORT datab (686:686:686) (711:711:711)) - (PORT datac (1044:1044:1044) (1121:1121:1121)) - (PORT datad (863:863:863) (904:904:904)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (407:407:407)) - (PORT datab (389:389:389) (421:421:421)) - (PORT datac (657:657:657) (706:706:706)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1421:1421:1421) (1449:1449:1449)) - (PORT datab (1932:1932:1932) (2005:2005:2005)) - (PORT datac (896:896:896) (938:938:938)) - (PORT datad (226:226:226) (261:261:261)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (3083:3083:3083) (3178:3178:3178)) - (PORT datab (849:849:849) (890:890:890)) - (PORT datac (1445:1445:1445) (1544:1544:1544)) - (PORT datad (1991:1991:1991) (2046:2046:2046)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT datab (1812:1812:1812) (1916:1916:1916)) - (PORT datad (2317:2317:2317) (2381:2381:2381)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (910:910:910)) - (PORT datab (393:393:393) (426:426:426)) - (PORT datac (1765:1765:1765) (1827:1827:1827)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1249:1249:1249)) - (PORT datab (1776:1776:1776) (1843:1843:1843)) - (PORT datac (593:593:593) (619:619:619)) - (PORT datad (613:613:613) (635:635:635)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (894:894:894) (917:917:917)) - (PORT datac (935:935:935) (977:977:977)) - (PORT datad (586:586:586) (595:595:595)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1910:1910:1910) (1994:1994:1994)) - (PORT datab (1648:1648:1648) (1797:1797:1797)) - (PORT datac (611:611:611) (649:649:649)) - (PORT datad (1744:1744:1744) (1826:1826:1826)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (901:901:901)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (2016:2016:2016) (2128:2128:2128)) - (PORT datad (1098:1098:1098) (1111:1111:1111)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~14) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (275:275:275)) - (PORT datab (264:264:264) (310:310:310)) - (PORT datac (339:339:339) (366:366:366)) - (PORT datad (194:194:194) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1218:1218:1218)) - (PORT datab (662:662:662) (682:682:682)) - (PORT datac (928:928:928) (996:996:996)) - (PORT datad (1139:1139:1139) (1210:1210:1210)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1791:1791:1791)) - (PORT datab (1366:1366:1366) (1397:1397:1397)) - (PORT datac (1763:1763:1763) (1830:1830:1830)) - (PORT datad (219:219:219) (255:255:255)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (624:624:624) (657:657:657)) - (PORT datad (827:827:827) (857:857:857)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1250:1250:1250)) - (PORT datab (366:366:366) (399:399:399)) - (PORT datac (1834:1834:1834) (1907:1907:1907)) - (PORT datad (603:603:603) (616:616:616)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2560:2560:2560) (2631:2631:2631)) - (PORT datab (2467:2467:2467) (2664:2664:2664)) - (PORT datad (1837:1837:1837) (1931:1931:1931)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1916:1916:1916) (2018:2018:2018)) - (PORT datab (894:894:894) (927:927:927)) - (PORT datac (1604:1604:1604) (1723:1723:1723)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1703:1703:1703) (1792:1792:1792)) - (PORT datab (1079:1079:1079) (1158:1158:1158)) - (PORT datac (897:897:897) (935:935:935)) - (PORT datad (225:225:225) (260:260:260)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (978:978:978)) - (PORT datab (1423:1423:1423) (1444:1444:1444)) - (PORT datac (618:618:618) (657:657:657)) - (PORT datad (823:823:823) (839:839:839)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1910:1910:1910) (1993:1993:1993)) - (PORT datab (1647:1647:1647) (1796:1796:1796)) - (PORT datac (610:610:610) (648:648:648)) - (PORT datad (1744:1744:1744) (1826:1826:1826)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2257:2257:2257) (2334:2334:2334)) - (PORT datab (879:879:879) (911:911:911)) - (PORT datac (1573:1573:1573) (1705:1705:1705)) - (PORT datad (1688:1688:1688) (1747:1747:1747)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (940:940:940)) - (PORT datab (1609:1609:1609) (1651:1651:1651)) - (PORT datac (1191:1191:1191) (1251:1251:1251)) - (PORT datad (1658:1658:1658) (1714:1714:1714)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (796:796:796)) - (PORT datab (1599:1599:1599) (1668:1668:1668)) - (PORT datac (1208:1208:1208) (1265:1265:1265)) - (PORT datad (1111:1111:1111) (1156:1156:1156)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2134:2134:2134) (2303:2303:2303)) - (PORT datab (1470:1470:1470) (1496:1496:1496)) - (PORT datac (1118:1118:1118) (1150:1150:1150)) - (PORT datad (645:645:645) (670:670:670)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (988:988:988)) - (PORT datab (557:557:557) (587:587:587)) - (PORT datac (569:569:569) (575:575:575)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (221:221:221) (250:250:250)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (956:956:956)) - (PORT datab (691:691:691) (757:757:757)) - (PORT datac (1338:1338:1338) (1342:1342:1342)) - (PORT datad (1183:1183:1183) (1212:1212:1212)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (954:954:954)) - (PORT datab (1459:1459:1459) (1512:1512:1512)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (919:919:919)) - (PORT datab (689:689:689) (761:761:761)) - (PORT datac (320:320:320) (344:344:344)) - (PORT datad (842:842:842) (871:871:871)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (686:686:686)) - (PORT datab (895:895:895) (931:931:931)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (882:882:882) (910:910:910)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (506:506:506)) - (PORT datab (1099:1099:1099) (1115:1115:1115)) - (PORT datac (742:742:742) (814:814:814)) - (PORT datad (730:730:730) (803:803:803)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (659:659:659)) - (PORT datab (660:660:660) (693:693:693)) - (PORT datac (576:576:576) (604:604:604)) - (PORT datad (663:663:663) (683:683:683)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (891:891:891)) - (PORT datab (616:616:616) (645:645:645)) - (PORT datac (1506:1506:1506) (1571:1571:1571)) - (PORT datad (192:192:192) (225:225:225)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (899:899:899) (928:928:928)) - (PORT datac (570:570:570) (592:592:592)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (660:660:660)) - (PORT datab (1247:1247:1247) (1277:1277:1277)) - (PORT datad (874:874:874) (919:919:919)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1236:1236:1236)) - (PORT datab (638:638:638) (670:670:670)) - (PORT datac (200:200:200) (236:236:236)) - (PORT datad (2384:2384:2384) (2430:2430:2430)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (835:835:835)) - (PORT datab (590:590:590) (599:599:599)) - (PORT datac (836:836:836) (870:870:870)) - (PORT datad (988:988:988) (1049:1049:1049)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1280:1280:1280) (1296:1296:1296)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (235:235:235) (312:312:312)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (340:340:340)) - (PORT datad (234:234:234) (311:311:311)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (824:824:824) (842:842:842)) - (PORT datac (202:202:202) (240:240:240)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (1866:1866:1866) (2020:2020:2020)) - (PORT datac (3074:3074:3074) (3300:3300:3300)) - (PORT datad (2568:2568:2568) (2680:2680:2680)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (843:843:843) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (373:373:373)) - (PORT datab (291:291:291) (383:383:383)) - (PORT datad (249:249:249) (334:334:334)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (3310:3310:3310) (3637:3637:3637)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (302:302:302)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (240:240:240) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (375:375:375) (441:441:441)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (224:224:224) (304:304:304)) - (PORT datad (228:228:228) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (225:225:225) (304:304:304)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (346:346:346)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (225:225:225) (308:308:308)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1547:1547:1547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (368:368:368)) - (PORT datab (277:277:277) (367:367:367)) - (PORT datad (249:249:249) (333:333:333)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (374:374:374)) - (PORT datab (293:293:293) (386:386:386)) - (PORT datad (250:250:250) (330:330:330)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (377:377:377)) - (PORT datab (289:289:289) (381:381:381)) - (PORT datad (247:247:247) (326:326:326)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (PORT ena (2142:2142:2142) (2242:2242:2242)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (373:373:373)) - (PORT datab (292:292:292) (384:384:384)) - (PORT datad (250:250:250) (329:329:329)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (373:373:373)) - (PORT datab (276:276:276) (369:369:369)) - (PORT datac (384:384:384) (445:445:445)) - (PORT datad (3313:3313:3313) (3645:3645:3645)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (368:368:368)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1497:1497:1497) (1608:1608:1608)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (3641:3641:3641) (3987:3987:3987)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (703:703:703) (765:765:765)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (613:613:613) (718:718:718)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (1312:1312:1312) (1370:1370:1370)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (PORT ena (1685:1685:1685) (1687:1687:1687)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (1237:1237:1237) (1318:1318:1318)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (1368:1368:1368) (1443:1443:1443)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (PORT ena (1425:1425:1425) (1453:1453:1453)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (1184:1184:1184) (1233:1233:1233)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (PORT ena (1425:1425:1425) (1453:1453:1453)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT asdata (608:608:608) (699:699:699)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (PORT ena (1425:1425:1425) (1453:1453:1453)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT asdata (1274:1274:1274) (1331:1331:1331)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (PORT ena (1641:1641:1641) (1638:1638:1638)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (416:416:416)) - (PORT datab (930:930:930) (1010:1010:1010)) - (PORT datac (251:251:251) (336:336:336)) - (PORT datad (944:944:944) (1019:1019:1019)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (879:879:879)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (927:927:927) (986:986:986)) - (PORT datad (264:264:264) (344:344:344)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (422:422:422)) - (PORT datab (985:985:985) (1056:1056:1056)) - (PORT datad (264:264:264) (344:344:344)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (985:985:985)) - (PORT datab (960:960:960) (1023:1023:1023)) - (PORT datad (755:755:755) (838:838:838)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (311:311:311) (327:327:327)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (692:692:692)) - (PORT datab (3347:3347:3347) (3682:3682:3682)) - (PORT datac (1498:1498:1498) (1609:1609:1609)) - (PORT datad (185:185:185) (215:215:215)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (714:714:714)) - (PORT datab (877:877:877) (947:947:947)) - (PORT datad (704:704:704) (775:775:775)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (795:795:795)) - (PORT datab (791:791:791) (877:877:877)) - (PORT datac (707:707:707) (797:797:797)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (814:814:814)) - (PORT datad (750:750:750) (828:828:828)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (717:717:717)) - (PORT datad (699:699:699) (766:766:766)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (PORT ena (1489:1489:1489) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (409:409:409)) - (PORT datab (677:677:677) (741:741:741)) - (PORT datac (912:912:912) (970:970:970)) - (PORT datad (268:268:268) (348:348:348)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (690:690:690)) - (PORT datab (762:762:762) (850:850:850)) - (PORT datac (182:182:182) (219:219:219)) - (PORT datad (1129:1129:1129) (1155:1155:1155)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (436:436:436)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1901:1901:1901) (2085:2085:2085)) - (PORT datab (1495:1495:1495) (1563:1563:1563)) - (PORT datad (1153:1153:1153) (1262:1262:1262)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1931:1931:1931) (1907:1907:1907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (949:949:949) (997:997:997)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) - (PORT asdata (568:568:568) (646:646:646)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (728:728:728)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1278:1278:1278) (1382:1382:1382)) - (PORT datab (977:977:977) (1078:1078:1078)) - (PORT datac (624:624:624) (676:676:676)) - (PORT datad (886:886:886) (918:918:918)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1916:1916:1916) (2016:2016:2016)) - (PORT datab (1192:1192:1192) (1204:1204:1204)) - (PORT datac (1608:1608:1608) (1722:1722:1722)) - (PORT datad (856:856:856) (886:886:886)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1916:1916:1916) (2016:2016:2016)) - (PORT datab (893:893:893) (925:925:925)) - (PORT datac (1608:1608:1608) (1721:1721:1721)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1915:1915:1915) (2019:2019:2019)) - (PORT datab (1746:1746:1746) (1780:1780:1780)) - (PORT datac (1605:1605:1605) (1722:1722:1722)) - (PORT datad (856:856:856) (890:890:890)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (300:300:300)) - (PORT datac (256:256:256) (311:311:311)) - (PORT datad (245:245:245) (296:296:296)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (667:667:667)) - (PORT datac (1675:1675:1675) (1746:1746:1746)) - (PORT datad (1137:1137:1137) (1176:1176:1176)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (683:683:683)) - (PORT datac (621:621:621) (640:640:640)) - (PORT datad (1221:1221:1221) (1279:1279:1279)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (700:700:700)) - (PORT datab (1445:1445:1445) (1504:1504:1504)) - (PORT datac (586:586:586) (606:606:606)) - (PORT datad (1117:1117:1117) (1138:1138:1138)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (686:686:686)) - (PORT datab (939:939:939) (980:980:980)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (887:887:887) (909:909:909)) + (PORT dataa (1733:1733:1733) (1843:1843:1843)) + (PORT datab (982:982:982) (1054:1054:1054)) + (PORT datac (675:675:675) (737:737:737)) + (PORT datad (868:868:868) (918:918:918)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -7258,717 +3573,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT datab (1493:1493:1493) (1554:1554:1554)) - (PORT datac (1223:1223:1223) (1253:1253:1253)) - (PORT datad (1403:1403:1403) (1470:1470:1470)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1394:1394:1394)) - (PORT datab (1605:1605:1605) (1734:1734:1734)) - (PORT datac (622:622:622) (664:664:664)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1978:1978:1978) (2137:2137:2137)) - (PORT datab (2591:2591:2591) (2768:2768:2768)) - (PORT datad (1697:1697:1697) (1792:1792:1792)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1523:1523:1523)) - (PORT datab (976:976:976) (983:983:983)) - (PORT datac (868:868:868) (907:907:907)) - (PORT datad (918:918:918) (955:955:955)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT dataa (2356:2356:2356) (2462:2462:2462)) - (PORT datac (1864:1864:1864) (1892:1892:1892)) - (PORT datad (1772:1772:1772) (1886:1886:1886)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1020:1020:1020)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1271:1271:1271)) - (PORT datab (627:627:627) (649:649:649)) - (PORT datac (902:902:902) (931:931:931)) - (PORT datad (859:859:859) (879:879:879)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (891:891:891) (925:925:925)) - (PORT datac (619:619:619) (660:660:660)) - (PORT datad (620:620:620) (668:668:668)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (907:907:907)) - (PORT datab (1517:1517:1517) (1628:1628:1628)) - (PORT datac (622:622:622) (674:674:674)) - (PORT datad (1219:1219:1219) (1277:1277:1277)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (185:185:185) (224:224:224)) - (PORT datad (1252:1252:1252) (1309:1309:1309)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT datab (2733:2733:2733) (2908:2908:2908)) - (PORT datac (1737:1737:1737) (1813:1813:1813)) - (PORT datad (839:839:839) (867:867:867)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1578:1578:1578) (1687:1687:1687)) - (PORT datab (2007:2007:2007) (2122:2122:2122)) - (PORT datac (2198:2198:2198) (2304:2304:2304)) - (PORT datad (1762:1762:1762) (1853:1853:1853)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1771:1771:1771) (1876:1876:1876)) - (PORT datab (356:356:356) (392:392:392)) - (PORT datac (1865:1865:1865) (1919:1919:1919)) - (PORT datad (1599:1599:1599) (1746:1746:1746)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2343:2343:2343) (2509:2509:2509)) - (PORT datab (1128:1128:1128) (1167:1167:1167)) - (PORT datac (1549:1549:1549) (1649:1649:1649)) - (PORT datad (1983:1983:1983) (2085:2085:2085)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (931:931:931)) - (PORT datab (822:822:822) (869:869:869)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (1639:1639:1639) (1711:1711:1711)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (650:650:650) (707:707:707)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1214:1214:1214)) - (PORT datab (849:849:849) (876:876:876)) - (PORT datac (1180:1180:1180) (1245:1245:1245)) - (PORT datad (894:894:894) (941:941:941)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1536:1536:1536) (1600:1600:1600)) - (PORT datab (1096:1096:1096) (1128:1128:1128)) - (PORT datac (1717:1717:1717) (1793:1793:1793)) - (PORT datad (1165:1165:1165) (1203:1203:1203)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1531:1531:1531) (1599:1599:1599)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (1264:1264:1264) (1333:1333:1333)) - (PORT datad (1159:1159:1159) (1219:1219:1219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (348:348:348)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (248:248:248) (306:306:306)) - (PORT datad (1436:1436:1436) (1458:1458:1458)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (632:632:632)) - (PORT datab (853:853:853) (859:859:859)) - (PORT datac (371:371:371) (388:388:388)) - (PORT datad (899:899:899) (949:949:949)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (615:615:615)) - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (1119:1119:1119) (1151:1151:1151)) - (PORT datad (880:880:880) (918:918:918)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1164:1164:1164)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1166:1166:1166)) - (PORT datab (2009:2009:2009) (2098:2098:2098)) - (PORT datac (1374:1374:1374) (1482:1482:1482)) - (PORT datad (1892:1892:1892) (1950:1950:1950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1682:1682:1682) (1789:1789:1789)) - (PORT datab (654:654:654) (672:672:672)) - (PORT datac (1764:1764:1764) (1827:1827:1827)) - (PORT datad (1054:1054:1054) (1101:1101:1101)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1793:1793:1793)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (1763:1763:1763) (1832:1832:1832)) - (PORT datad (1052:1052:1052) (1102:1102:1102)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1238:1238:1238)) - (PORT datab (886:886:886) (929:929:929)) - (PORT datac (942:942:942) (998:998:998)) - (PORT datad (944:944:944) (995:995:995)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (436:436:436)) - (PORT datab (948:948:948) (982:982:982)) - (PORT datac (584:584:584) (628:628:628)) - (PORT datad (223:223:223) (253:253:253)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (962:962:962)) - (PORT datab (942:942:942) (963:963:963)) - (PORT datac (638:638:638) (669:669:669)) - (PORT datad (1172:1172:1172) (1244:1244:1244)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1052:1052:1052)) - (PORT datab (987:987:987) (1030:1030:1030)) - (PORT datac (1171:1171:1171) (1219:1219:1219)) - (PORT datad (986:986:986) (1036:1036:1036)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (673:673:673)) - (PORT datab (1462:1462:1462) (1514:1514:1514)) - (PORT datac (830:830:830) (908:908:908)) - (PORT datad (1914:1914:1914) (1984:1984:1984)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT datac (1322:1322:1322) (1471:1471:1471)) - (PORT datad (2189:2189:2189) (2361:2361:2361)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (881:881:881)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (1159:1159:1159) (1177:1177:1177)) - (PORT datad (639:639:639) (677:677:677)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (999:999:999)) - (PORT datab (1472:1472:1472) (1516:1516:1516)) - (PORT datac (1410:1410:1410) (1502:1502:1502)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (645:645:645)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (826:826:826) (838:838:838)) - (PORT datad (789:789:789) (845:845:845)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2078:2078:2078)) - (PORT datab (611:611:611) (626:626:626)) - (PORT datac (831:831:831) (870:870:870)) - (PORT datad (705:705:705) (742:742:742)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1665:1665:1665) (1731:1731:1731)) - (PORT datab (1778:1778:1778) (1843:1843:1843)) - (PORT datac (897:897:897) (948:948:948)) - (PORT datad (703:703:703) (737:737:737)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (936:936:936)) - (PORT datab (1991:1991:1991) (2053:2053:2053)) - (PORT datac (1786:1786:1786) (1813:1813:1813)) - (PORT datad (1444:1444:1444) (1438:1438:1438)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (644:644:644)) - (PORT datab (740:740:740) (777:777:777)) - (PORT datac (1151:1151:1151) (1208:1208:1208)) - (PORT datad (804:804:804) (817:817:817)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (658:658:658)) - (PORT datab (742:742:742) (780:780:780)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (607:607:607) (632:632:632)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (376:376:376)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1656:1656:1656) (1674:1674:1674)) - (PORT datab (832:832:832) (856:856:856)) - (PORT datac (874:874:874) (900:900:900)) - (PORT datad (583:583:583) (602:602:602)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1662:1662:1662) (1727:1727:1727)) - (PORT datab (609:609:609) (623:623:623)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (1964:1964:1964) (2030:2030:2030)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (874:874:874)) - (PORT datab (1111:1111:1111) (1163:1163:1163)) - (PORT datac (760:760:760) (817:817:817)) - (PORT datad (648:648:648) (669:669:669)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (816:816:816)) - (PORT datab (2351:2351:2351) (2480:2480:2480)) - (PORT datac (750:750:750) (859:859:859)) - (PORT datad (1843:1843:1843) (1894:1894:1894)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (615:615:615) (668:668:668)) - (PORT datac (355:355:355) (385:385:385)) - (PORT datad (820:820:820) (847:847:847)) + (PORT dataa (906:906:906) (936:936:936)) + (PORT datab (2523:2523:2523) (2632:2632:2632)) + (PORT datac (1501:1501:1501) (1545:1545:1545)) + (PORT datad (1168:1168:1168) (1198:1198:1198)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -7981,8 +3592,95 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) (DELAY (ABSOLUTE - (PORT datac (2110:2110:2110) (2222:2222:2222)) - (PORT datad (1649:1649:1649) (1827:1827:1827)) + (PORT dataa (1221:1221:1221) (1327:1327:1327)) + (PORT datad (2392:2392:2392) (2524:2524:2524)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1254:1254:1254)) + (PORT datab (426:426:426) (506:506:506)) + (PORT datad (436:436:436) (503:503:503)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1170:1170:1170)) + (PORT datab (1231:1231:1231) (1310:1310:1310)) + (PORT datad (315:315:315) (326:326:326)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (1332:1332:1332) (1402:1402:1402)) + (PORT datac (1502:1502:1502) (1540:1540:1540)) + (PORT datad (1167:1167:1167) (1194:1194:1194)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1673:1673:1673)) + (PORT datac (1749:1749:1749) (1885:1885:1885)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1361:1361:1361)) + (PORT datab (354:354:354) (389:389:389)) + (PORT datac (1557:1557:1557) (1714:1714:1714)) + (PORT datad (1416:1416:1416) (1491:1491:1491)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -7990,15 +3688,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (886:886:886) (924:924:924)) - (PORT datad (364:364:364) (387:387:387)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1817:1817:1817) (1912:1912:1912)) + (PORT datab (1952:1952:1952) (2047:2047:2047)) + (PORT datac (1429:1429:1429) (1521:1521:1521)) + (PORT datad (657:657:657) (703:703:703)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8006,13 +3704,398 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~3) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (389:389:389)) - (PORT datab (613:613:613) (635:635:635)) - (PORT datac (585:585:585) (595:595:595)) - (PORT datad (816:816:816) (824:824:824)) + (PORT dataa (1404:1404:1404) (1470:1470:1470)) + (PORT datab (1220:1220:1220) (1262:1262:1262)) + (PORT datac (1149:1149:1149) (1196:1196:1196)) + (PORT datad (828:828:828) (861:861:861)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1016:1016:1016)) + (PORT datab (1441:1441:1441) (1511:1511:1511)) + (PORT datac (1453:1453:1453) (1526:1526:1526)) + (PORT datad (1029:1029:1029) (1119:1119:1119)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1603:1603:1603) (1703:1703:1703)) + (PORT datab (1483:1483:1483) (1651:1651:1651)) + (PORT datad (1255:1255:1255) (1388:1388:1388)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2612:2612:2612) (2697:2697:2697)) + (PORT datab (1480:1480:1480) (1568:1568:1568)) + (PORT datac (1259:1259:1259) (1347:1347:1347)) + (PORT datad (1321:1321:1321) (1402:1402:1402)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (762:762:762)) + (PORT datab (1129:1129:1129) (1244:1244:1244)) + (PORT datac (1105:1105:1105) (1196:1196:1196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (958:958:958)) + (PORT datab (1098:1098:1098) (1224:1224:1224)) + (PORT datac (1684:1684:1684) (1781:1781:1781)) + (PORT datad (899:899:899) (930:930:930)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT datab (1422:1422:1422) (1500:1500:1500)) + (PORT datac (214:214:214) (257:257:257)) + (PORT datad (985:985:985) (1083:1083:1083)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1351:1351:1351)) + (PORT datab (243:243:243) (290:290:290)) + (PORT datac (1391:1391:1391) (1466:1466:1466)) + (PORT datad (985:985:985) (1083:1083:1083)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1918:1918:1918) (1959:1959:1959)) + (PORT datab (1216:1216:1216) (1272:1272:1272)) + (PORT datad (928:928:928) (968:968:968)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1293:1293:1293)) + (PORT datac (1199:1199:1199) (1284:1284:1284)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1680:1680:1680) (1732:1732:1732)) + (PORT datab (269:269:269) (331:331:331)) + (PORT datac (708:708:708) (774:774:774)) + (PORT datad (249:249:249) (300:300:300)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (597:597:597)) + (PORT datab (665:665:665) (721:721:721)) + (PORT datac (2606:2606:2606) (2699:2699:2699)) + (PORT datad (1349:1349:1349) (1385:1385:1385)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (376:376:376)) + (PORT datac (1200:1200:1200) (1284:1284:1284)) + (PORT datad (983:983:983) (1037:1037:1037)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (280:280:280)) + (PORT datab (2981:2981:2981) (3109:3109:3109)) + (PORT datac (1174:1174:1174) (1223:1223:1223)) + (PORT datad (690:690:690) (720:720:720)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1255:1255:1255)) + (PORT datab (1335:1335:1335) (1448:1448:1448)) + (PORT datac (539:539:539) (556:556:556)) + (PORT datad (633:633:633) (679:679:679)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1150:1150:1150)) + (PORT datac (1634:1634:1634) (1816:1816:1816)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~3) + (DELAY + (ABSOLUTE + (PORT datac (1196:1196:1196) (1296:1296:1296)) + (PORT datad (1223:1223:1223) (1333:1333:1333)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT datac (1425:1425:1425) (1521:1521:1521)) + (PORT datad (1209:1209:1209) (1299:1299:1299)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1440:1440:1440) (1554:1554:1554)) + (PORT datad (1627:1627:1627) (1725:1725:1725)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (1572:1572:1572) (1697:1697:1697)) + (PORT datac (1407:1407:1407) (1473:1473:1473)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1099:1099:1099)) + (PORT datab (1195:1195:1195) (1248:1248:1248)) + (PORT datac (1406:1406:1406) (1439:1439:1439)) + (PORT datad (1839:1839:1839) (1886:1886:1886)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1237:1237:1237)) + (PORT datab (890:890:890) (920:920:920)) + (PORT datac (1813:1813:1813) (1879:1879:1879)) + (PORT datad (1295:1295:1295) (1368:1368:1368)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1417:1417:1417)) + (PORT datab (700:700:700) (777:777:777)) + (PORT datad (667:667:667) (743:743:743)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1151:1151:1151)) + (PORT datab (1251:1251:1251) (1328:1328:1328)) + (PORT datac (1626:1626:1626) (1826:1826:1826)) + (PORT datad (2008:2008:2008) (2036:2036:2036)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1582:1582:1582)) + (PORT datab (897:897:897) (929:929:929)) + (PORT datac (1511:1511:1511) (1556:1556:1556)) + (PORT datad (1758:1758:1758) (1800:1800:1800)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -8022,15 +4105,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (INSTANCE z80_\|execute_\|ixy_d\~9) (DELAY (ABSOLUTE - (PORT dataa (276:276:276) (346:346:346)) - (PORT datab (1766:1766:1766) (1810:1810:1810)) - (PORT datac (251:251:251) (310:310:310)) - (PORT datad (225:225:225) (265:265:265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (949:949:949) (1003:1003:1003)) + (PORT datab (706:706:706) (750:750:750)) + (PORT datac (1691:1691:1691) (1786:1786:1786)) + (PORT datad (542:542:542) (565:565:565)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (677:677:677)) + (PORT datab (593:593:593) (622:622:622)) + (PORT datac (616:616:616) (633:633:633)) + (PORT datad (223:223:223) (260:260:260)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (599:599:599)) + (PORT datab (647:647:647) (667:667:667)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (842:842:842) (871:871:871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1116:1116:1116)) + (PORT datac (2027:2027:2027) (2142:2142:2142)) + (PORT datad (940:940:940) (1023:1023:1023)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8038,13 +4167,277 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (INSTANCE z80_\|execute_\|ixy_d\~10) (DELAY (ABSOLUTE - (PORT dataa (927:927:927) (1008:1008:1008)) - (PORT datab (964:964:964) (1028:1028:1028)) - (PORT datac (1904:1904:1904) (1967:1967:1967)) - (PORT datad (644:644:644) (671:671:671)) + (PORT dataa (770:770:770) (864:864:864)) + (PORT datab (1303:1303:1303) (1409:1409:1409)) + (PORT datac (647:647:647) (732:732:732)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1133:1133:1133)) + (PORT datab (565:565:565) (597:597:597)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2320:2320:2320) (2443:2443:2443)) + (PORT datab (1332:1332:1332) (1447:1447:1447)) + (PORT datac (1144:1144:1144) (1219:1219:1219)) + (PORT datad (1832:1832:1832) (1992:1992:1992)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1152:1152:1152)) + (PORT datac (1639:1639:1639) (1834:1834:1834)) + (PORT datad (999:999:999) (1109:1109:1109)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1426:1426:1426)) + (PORT datab (886:886:886) (915:915:915)) + (PORT datac (443:443:443) (518:518:518)) + (PORT datad (1156:1156:1156) (1198:1198:1198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1739:1739:1739) (1849:1849:1849)) + (PORT datab (710:710:710) (780:780:780)) + (PORT datac (954:954:954) (1026:1026:1026)) + (PORT datad (2639:2639:2639) (2724:2724:2724)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1372:1372:1372)) + (PORT datab (1278:1278:1278) (1396:1396:1396)) + (PORT datac (1664:1664:1664) (1837:1837:1837)) + (PORT datad (392:392:392) (420:420:420)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1683:1683:1683)) + (PORT datab (1576:1576:1576) (1717:1717:1717)) + (PORT datac (819:819:819) (834:834:834)) + (PORT datad (1049:1049:1049) (1080:1080:1080)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1447:1447:1447)) + (PORT datab (864:864:864) (891:891:891)) + (PORT datac (718:718:718) (821:821:821)) + (PORT datad (1222:1222:1222) (1332:1332:1332)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (700:700:700)) + (PORT datab (864:864:864) (892:892:892)) + (PORT datac (1392:1392:1392) (1425:1425:1425)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1886:1886:1886)) + (PORT datab (1714:1714:1714) (1812:1812:1812)) + (PORT datac (1007:1007:1007) (1082:1082:1082)) + (PORT datad (849:849:849) (867:867:867)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (907:907:907) (978:978:978)) + (PORT datad (1870:1870:1870) (2001:2001:2001)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (623:623:623)) + (PORT datab (2973:2973:2973) (3100:3100:3100)) + (PORT datac (1380:1380:1380) (1409:1409:1409)) + (PORT datad (693:693:693) (725:725:725)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1776:1776:1776) (1889:1889:1889)) + (PORT datad (1583:1583:1583) (1710:1710:1710)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (717:717:717)) + (PORT datab (575:575:575) (595:595:595)) + (PORT datac (871:871:871) (913:913:913)) + (PORT datad (1401:1401:1401) (1450:1450:1450)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1331:1331:1331)) + (PORT datab (955:955:955) (970:970:970)) + (PORT datac (861:861:861) (879:879:879)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1429:1429:1429)) + (PORT datab (884:884:884) (913:913:913)) + (PORT datac (443:443:443) (519:519:519)) + (PORT datad (1159:1159:1159) (1198:1198:1198)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8054,369 +4447,674 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) (DELAY (ABSOLUTE - (PORT dataa (958:958:958) (1056:1056:1056)) - (PORT datab (1415:1415:1415) (1547:1547:1547)) - (PORT datac (943:943:943) (1040:1040:1040)) - (PORT datad (818:818:818) (824:824:824)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (717:717:717)) - (PORT datab (1612:1612:1612) (1652:1652:1652)) - (PORT datac (1279:1279:1279) (1317:1317:1317)) - (PORT datad (1153:1153:1153) (1159:1159:1159)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT datac (1943:1943:1943) (2004:2004:2004)) - (PORT datad (2062:2062:2062) (2197:2197:2197)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (266:266:266)) - (PORT datab (1497:1497:1497) (1573:1573:1573)) - (PORT datac (1953:1953:1953) (2008:2008:2008)) - (PORT datad (206:206:206) (244:244:244)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1982:1982:1982) (2045:2045:2045)) - (PORT datab (2098:2098:2098) (2238:2238:2238)) - (PORT datac (1468:1468:1468) (1539:1539:1539)) - (PORT datad (211:211:211) (249:249:249)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1990:1990:1990) (2089:2089:2089)) - (PORT datab (1214:1214:1214) (1264:1264:1264)) - (PORT datac (1724:1724:1724) (1792:1792:1792)) - (PORT datad (935:935:935) (979:979:979)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1544:1544:1544)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1386:1386:1386) (1421:1421:1421)) - (PORT datad (614:614:614) (649:649:649)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1199:1199:1199)) - (PORT datab (1612:1612:1612) (1652:1652:1652)) - (PORT datac (885:885:885) (930:930:930)) - (PORT datad (893:893:893) (940:940:940)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (178:178:178) (215:215:215)) - (PORT datad (211:211:211) (242:242:242)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT datab (2102:2102:2102) (2242:2242:2242)) - (PORT datac (1464:1464:1464) (1539:1539:1539)) - (PORT datad (208:208:208) (246:246:246)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (1474:1474:1474) (1558:1558:1558)) - (PORT datac (2114:2114:2114) (2223:2223:2223)) - (PORT datad (1649:1649:1649) (1828:1828:1828)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1004:1004:1004)) - (PORT datab (1085:1085:1085) (1111:1111:1111)) - (PORT datac (644:644:644) (684:684:684)) - (PORT datad (629:629:629) (644:644:644)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (629:629:629)) - (PORT datab (917:917:917) (949:949:949)) - (PORT datac (586:586:586) (598:598:598)) - (PORT datad (1627:1627:1627) (1648:1648:1648)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2329:2329:2329)) - (PORT datab (1611:1611:1611) (1741:1741:1741)) - (PORT datac (847:847:847) (879:879:879)) - (PORT datad (871:871:871) (887:887:887)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (686:686:686)) - (PORT datab (874:874:874) (906:906:906)) - (PORT datac (1698:1698:1698) (1732:1732:1732)) - (PORT datad (1500:1500:1500) (1556:1556:1556)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1213:1213:1213)) - (PORT datab (624:624:624) (655:655:655)) - (PORT datac (657:657:657) (701:701:701)) - (PORT datad (1183:1183:1183) (1213:1213:1213)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1005:1005:1005) (1109:1109:1109)) + (PORT datac (710:710:710) (802:802:802)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (INSTANCE z80_\|pla_decode_\|Equal46\~0) (DELAY (ABSOLUTE - (PORT dataa (1234:1234:1234) (1292:1292:1292)) - (PORT datab (986:986:986) (1027:1027:1027)) - (PORT datac (1677:1677:1677) (1709:1709:1709)) - (PORT datad (1375:1375:1375) (1426:1426:1426)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (1011:1011:1011) (1072:1072:1072)) - (PORT datac (1770:1770:1770) (1905:1905:1905)) - (PORT datad (1375:1375:1375) (1425:1425:1425)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1014:1014:1014)) - (PORT datab (946:946:946) (992:992:992)) - (PORT datad (890:890:890) (963:963:963)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (271:271:271)) - (PORT datab (989:989:989) (1051:1051:1051)) - (PORT datac (804:804:804) (824:824:824)) - (PORT datad (1395:1395:1395) (1406:1406:1406)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1775:1775:1775) (1871:1871:1871)) - (PORT datab (1638:1638:1638) (1787:1787:1787)) - (PORT datad (1885:1885:1885) (1952:1952:1952)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1146:1146:1146)) - (PORT datac (1745:1745:1745) (1882:1882:1882)) - (PORT datad (635:635:635) (694:694:694)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1159:1159:1159)) - (PORT datab (921:921:921) (984:984:984)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (566:566:566) (581:581:581)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1917:1917:1917) (2022:2022:2022)) - (PORT datab (1506:1506:1506) (1587:1587:1587)) - (PORT datac (1606:1606:1606) (1725:1725:1725)) - (PORT datad (857:857:857) (891:891:891)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (2089:2089:2089) (2234:2234:2234)) + (PORT datab (1577:1577:1577) (1677:1677:1677)) + (PORT datac (2099:2099:2099) (2270:2270:2270)) + (PORT datad (1001:1001:1001) (1109:1109:1109)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1424:1424:1424)) + (PORT datab (286:286:286) (377:377:377)) + (PORT datac (1166:1166:1166) (1182:1182:1182)) + (PORT datad (1155:1155:1155) (1198:1198:1198)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1194:1194:1194)) + (PORT datab (1458:1458:1458) (1546:1546:1546)) + (PORT datac (1709:1709:1709) (1725:1725:1725)) + (PORT datad (387:387:387) (408:408:408)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (1021:1021:1021)) + (PORT datab (1562:1562:1562) (1657:1657:1657)) + (PORT datac (860:860:860) (912:912:912)) + (PORT datad (909:909:909) (980:980:980)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1371:1371:1371)) + (PORT datab (1280:1280:1280) (1398:1398:1398)) + (PORT datac (1667:1667:1667) (1837:1837:1837)) + (PORT datad (392:392:392) (419:419:419)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1423:1423:1423)) + (PORT datab (1581:1581:1581) (1721:1721:1721)) + (PORT datac (1467:1467:1467) (1496:1496:1496)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (412:412:412)) + (PORT datab (628:628:628) (643:643:643)) + (PORT datac (642:642:642) (689:689:689)) + (PORT datad (876:876:876) (903:903:903)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT datab (732:732:732) (833:833:833)) + (PORT datad (385:385:385) (417:417:417)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1329:1329:1329)) + (PORT datab (1252:1252:1252) (1326:1326:1326)) + (PORT datad (1237:1237:1237) (1310:1310:1310)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1266:1266:1266)) + (PORT datac (2068:2068:2068) (2251:2251:2251)) + (PORT datad (1708:1708:1708) (1804:1804:1804)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1770:1770:1770) (1859:1859:1859)) + (PORT datab (1260:1260:1260) (1349:1349:1349)) + (PORT datad (1718:1718:1718) (1791:1791:1791)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1774:1774:1774) (1859:1859:1859)) + (PORT datab (1235:1235:1235) (1313:1313:1313)) + (PORT datac (2079:2079:2079) (2188:2188:2188)) + (PORT datad (1723:1723:1723) (1793:1793:1793)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1811:1811:1811)) + (PORT datab (248:248:248) (290:290:290)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (384:384:384)) + (PORT datab (1761:1761:1761) (1832:1832:1832)) + (PORT datac (1742:1742:1742) (1818:1818:1818)) + (PORT datad (1237:1237:1237) (1315:1315:1315)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1771:1771:1771) (1857:1857:1857)) + (PORT datab (658:658:658) (689:689:689)) + (PORT datac (2074:2074:2074) (2183:2183:2183)) + (PORT datad (1719:1719:1719) (1788:1788:1788)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1329:1329:1329)) + (PORT datab (1252:1252:1252) (1325:1325:1325)) + (PORT datad (1237:1237:1237) (1310:1310:1310)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (934:934:934) (957:957:957)) + (PORT datac (802:802:802) (825:825:825)) + (PORT datad (1221:1221:1221) (1304:1304:1304)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (442:442:442)) + (PORT datab (372:372:372) (399:399:399)) + (PORT datac (571:571:571) (595:595:595)) + (PORT datad (944:944:944) (1008:1008:1008)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (660:660:660)) + (PORT datab (2975:2975:2975) (3104:3104:3104)) + (PORT datac (909:909:909) (968:968:968)) + (PORT datad (690:690:690) (723:723:723)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1247:1247:1247)) + (PORT datab (2974:2974:2974) (3098:3098:3098)) + (PORT datac (586:586:586) (616:616:616)) + (PORT datad (693:693:693) (723:723:723)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1371:1371:1371)) + (PORT datab (1280:1280:1280) (1398:1398:1398)) + (PORT datac (1666:1666:1666) (1836:1836:1836)) + (PORT datad (340:340:340) (364:364:364)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (921:921:921)) + (PORT datab (271:271:271) (337:337:337)) + (PORT datac (709:709:709) (779:779:779)) + (PORT datad (259:259:259) (309:309:309)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1729:1729:1729)) + (PORT datab (272:272:272) (332:332:332)) + (PORT datac (708:708:708) (774:774:774)) + (PORT datad (264:264:264) (308:308:308)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (750:750:750)) + (PORT datab (270:270:270) (330:330:330)) + (PORT datac (709:709:709) (778:778:778)) + (PORT datad (260:260:260) (310:310:310)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (917:917:917)) + (PORT datab (845:845:845) (903:903:903)) + (PORT datac (610:610:610) (659:659:659)) + (PORT datad (640:640:640) (696:696:696)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (624:624:624)) + (PORT datab (2975:2975:2975) (3101:3101:3101)) + (PORT datac (1380:1380:1380) (1412:1412:1412)) + (PORT datad (688:688:688) (729:729:729)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1603:1603:1603)) + (PORT datab (1406:1406:1406) (1442:1442:1442)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1351:1351:1351) (1334:1334:1334)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2136:2136:2136) (2285:2285:2285)) + (PORT datad (970:970:970) (1056:1056:1056)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1845:1845:1845) (1897:1897:1897)) + (PORT datab (1276:1276:1276) (1339:1339:1339)) + (PORT datac (1645:1645:1645) (1660:1660:1660)) + (PORT datad (1150:1150:1150) (1174:1174:1174)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (400:400:400)) + (PORT datab (1278:1278:1278) (1339:1339:1339)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2106:2106:2106) (2267:2267:2267)) + (PORT datab (2646:2646:2646) (2747:2747:2747)) + (PORT datac (1902:1902:1902) (1989:1989:1989)) + (PORT datad (200:200:200) (228:228:228)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (446:446:446)) + (PORT datab (939:939:939) (961:961:961)) + (PORT datac (1442:1442:1442) (1475:1475:1475)) + (PORT datad (355:355:355) (375:375:375)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (1186:1186:1186) (1214:1214:1214)) + (PORT datac (1443:1443:1443) (1476:1476:1476)) + (PORT datad (215:215:215) (241:241:241)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1335:1335:1335)) + (PORT datab (401:401:401) (479:479:479)) + (PORT datad (985:985:985) (1042:1042:1042)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT datab (1215:1215:1215) (1343:1343:1343)) + (PORT datad (2027:2027:2027) (2164:2164:2164)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (690:690:690)) + (PORT datab (270:270:270) (320:320:320)) + (PORT datac (1931:1931:1931) (1981:1981:1981)) + (PORT datad (885:885:885) (906:906:906)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M5T3_9) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (735:735:735)) + (PORT datab (2031:2031:2031) (2121:2121:2121)) + (PORT datad (1590:1590:1590) (1702:1702:1702)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1577:1577:1577) (1599:1599:1599)) + (PORT datab (1460:1460:1460) (1524:1524:1524)) + (PORT datac (859:859:859) (878:878:878)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1376:1376:1376)) + (PORT datab (1458:1458:1458) (1527:1527:1527)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (637:637:637) (696:696:696)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1427:1427:1427)) + (PORT datab (885:885:885) (917:917:917)) + (PORT datac (443:443:443) (518:518:518)) + (PORT datad (1157:1157:1157) (1198:1198:1198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1151:1151:1151)) + (PORT datab (1254:1254:1254) (1329:1329:1329)) + (PORT datac (1628:1628:1628) (1816:1816:1816)) + (PORT datad (2009:2009:2009) (2040:2040:2040)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (949:949:949)) + (PORT datab (752:752:752) (851:851:851)) + (PORT datac (673:673:673) (782:782:782)) + (PORT datad (262:262:262) (308:308:308)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8427,10 +5125,312 @@ (INSTANCE z80_\|execute_\|ctl_state_alu\~7) (DELAY (ABSOLUTE - (PORT dataa (1474:1474:1474) (1533:1533:1533)) - (PORT datab (1245:1245:1245) (1280:1280:1280)) - (PORT datac (931:931:931) (1004:1004:1004)) - (PORT datad (845:845:845) (854:854:854)) + (PORT dataa (1718:1718:1718) (1791:1791:1791)) + (PORT datab (1206:1206:1206) (1240:1240:1240)) + (PORT datac (1128:1128:1128) (1166:1166:1166)) + (PORT datad (244:244:244) (281:281:281)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1135:1135:1135)) + (PORT datab (2131:2131:2131) (2174:2174:2174)) + (PORT datac (573:573:573) (589:589:589)) + (PORT datad (244:244:244) (281:281:281)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1377:1377:1377)) + (PORT datab (1270:1270:1270) (1388:1388:1388)) + (PORT datac (1659:1659:1659) (1825:1825:1825)) + (PORT datad (393:393:393) (425:425:425)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1372:1372:1372)) + (PORT datab (1276:1276:1276) (1394:1394:1394)) + (PORT datac (1663:1663:1663) (1835:1835:1835)) + (PORT datad (394:394:394) (423:423:423)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (996:996:996)) + (PORT datab (1190:1190:1190) (1216:1216:1216)) + (PORT datac (1051:1051:1051) (1159:1159:1159)) + (PORT datad (2076:2076:2076) (2218:2218:2218)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (964:964:964)) + (PORT datab (896:896:896) (928:928:928)) + (PORT datac (1514:1514:1514) (1557:1557:1557)) + (PORT datad (1757:1757:1757) (1804:1804:1804)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1204:1204:1204)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1306:1306:1306) (1341:1341:1341)) + (PORT datad (244:244:244) (280:280:280)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1419:1419:1419)) + (PORT datab (284:284:284) (375:375:375)) + (PORT datac (1167:1167:1167) (1178:1178:1178)) + (PORT datad (1155:1155:1155) (1192:1192:1192)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1695:1695:1695)) + (PORT datab (2156:2156:2156) (2311:2311:2311)) + (PORT datac (1126:1126:1126) (1162:1162:1162)) + (PORT datad (1104:1104:1104) (1161:1161:1161)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1236:1236:1236)) + (PORT datab (882:882:882) (937:937:937)) + (PORT datac (933:933:933) (980:980:980)) + (PORT datad (1135:1135:1135) (1173:1173:1173)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (953:953:953)) + (PORT datab (282:282:282) (345:345:345)) + (PORT datac (673:673:673) (786:786:786)) + (PORT datad (1380:1380:1380) (1407:1407:1407)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2191:2191:2191) (2299:2299:2299)) + (PORT datab (1440:1440:1440) (1467:1467:1467)) + (PORT datac (1509:1509:1509) (1600:1600:1600)) + (PORT datad (913:913:913) (928:928:928)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1429:1429:1429)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (1166:1166:1166) (1178:1178:1178)) + (PORT datad (1159:1159:1159) (1199:1199:1199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1957:1957:1957) (2024:2024:2024)) + (PORT datab (953:953:953) (986:986:986)) + (PORT datac (1509:1509:1509) (1598:1598:1598)) + (PORT datad (2152:2152:2152) (2251:2251:2251)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (699:699:699)) + (PORT datab (902:902:902) (936:936:936)) + (PORT datac (925:925:925) (963:963:963)) + (PORT datad (894:894:894) (918:918:918)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (720:720:720) (787:787:787)) + (PORT datac (1836:1836:1836) (2007:2007:2007)) + (PORT datad (1736:1736:1736) (1849:1849:1849)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (416:416:416)) + (PORT datab (269:269:269) (331:331:331)) + (PORT datac (709:709:709) (775:775:775)) + (PORT datad (249:249:249) (300:300:300)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1340:1340:1340)) + (PORT datab (1242:1242:1242) (1313:1313:1313)) + (PORT datac (2038:2038:2038) (2087:2087:2087)) + (PORT datad (1404:1404:1404) (1429:1429:1429)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1018:1018:1018)) + (PORT datab (1430:1430:1430) (1464:1464:1464)) + (PORT datac (1420:1420:1420) (1466:1466:1466)) + (PORT datad (1235:1235:1235) (1290:1290:1290)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8440,63 +5440,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (1965:1965:1965) (2057:2057:2057)) - (PORT datac (1434:1434:1434) (1491:1491:1491)) - (PORT datad (1510:1510:1510) (1653:1653:1653)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1364:1364:1364) (1466:1466:1466)) - (PORT datab (1561:1561:1561) (1650:1650:1650)) - (PORT datac (2446:2446:2446) (2642:2642:2642)) - (PORT datad (1222:1222:1222) (1355:1355:1355)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1651:1651:1651) (1723:1723:1723)) - (PORT datab (935:935:935) (964:964:964)) - (PORT datac (2570:2570:2570) (2619:2619:2619)) - (PORT datad (771:771:771) (818:818:818)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1479:1479:1479) (1540:1540:1540)) - (PORT datab (603:603:603) (620:620:620)) - (PORT datac (1131:1131:1131) (1166:1166:1166)) - (PORT datad (578:578:578) (596:596:596)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (627:627:627) (653:653:653)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (721:721:721) (783:783:783)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8504,47 +5456,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) (DELAY (ABSOLUTE - (PORT dataa (1475:1475:1475) (1536:1536:1536)) - (PORT datab (1418:1418:1418) (1464:1464:1464)) - (PORT datac (928:928:928) (1006:1006:1006)) - (PORT datad (1413:1413:1413) (1432:1432:1432)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1777:1777:1777) (1900:1900:1900)) - (PORT datab (217:217:217) (256:256:256)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (797:797:797)) - (PORT datab (1182:1182:1182) (1233:1233:1233)) - (PORT datac (1221:1221:1221) (1278:1278:1278)) - (PORT datad (894:894:894) (946:946:946)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1441:1441:1441) (1472:1472:1472)) + (PORT datac (723:723:723) (821:821:821)) + (PORT datad (1792:1792:1792) (1909:1909:1909)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -8552,13 +5470,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) (DELAY (ABSOLUTE - (PORT dataa (817:817:817) (896:896:896)) - (PORT datab (1880:1880:1880) (2010:2010:2010)) - (PORT datac (329:329:329) (351:351:351)) - (PORT datad (1691:1691:1691) (1766:1766:1766)) + (PORT dataa (1887:1887:1887) (1971:1971:1971)) + (PORT datab (927:927:927) (970:970:970)) + (PORT datac (1722:1722:1722) (1804:1804:1804)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (651:651:651) (709:709:709)) + (PORT datac (1090:1090:1090) (1128:1128:1128)) + (PORT datad (324:324:324) (347:347:347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (973:973:973) (1027:1027:1027)) + (PORT datac (313:313:313) (343:343:343)) + (PORT datad (584:584:584) (604:604:604)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1199:1199:1199)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (794:794:794) (809:809:809)) + (PORT datad (1099:1099:1099) (1106:1106:1106)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8571,13 +5537,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (2180:2180:2180) (2359:2359:2359)) - (PORT datab (1395:1395:1395) (1458:1458:1458)) - (PORT datac (1425:1425:1425) (1436:1436:1436)) - (PORT datad (2268:2268:2268) (2359:2359:2359)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (1761:1761:1761) (1866:1866:1866)) + (PORT datab (960:960:960) (973:973:973)) + (PORT datac (1771:1771:1771) (1901:1901:1901)) + (PORT datad (2046:2046:2046) (2143:2143:2143)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -8587,90 +5553,42 @@ (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (1302:1302:1302) (1373:1373:1373)) - (PORT datab (1199:1199:1199) (1239:1239:1239)) - (PORT datac (650:650:650) (720:720:720)) - (PORT datad (1152:1152:1152) (1181:1181:1181)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1404:1404:1404) (1423:1423:1423)) + (PORT datac (846:846:846) (871:871:871)) + (PORT datad (1487:1487:1487) (1576:1576:1576)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1449:1449:1449)) + (PORT datab (1456:1456:1456) (1500:1500:1500)) + (PORT datac (189:189:189) (230:230:230)) + (PORT datad (1482:1482:1482) (1573:1573:1573)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) (DELAY (ABSOLUTE - (PORT dataa (1459:1459:1459) (1482:1482:1482)) - (PORT datab (1177:1177:1177) (1245:1245:1245)) - (PORT datac (653:653:653) (721:721:721)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) - (DELAY - (ABSOLUTE - (PORT dataa (2144:2144:2144) (2265:2265:2265)) - (PORT datab (1689:1689:1689) (1868:1868:1868)) - (PORT datac (1147:1147:1147) (1206:1206:1206)) - (PORT datad (1953:1953:1953) (2015:2015:2015)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (894:894:894)) - (PORT datab (919:919:919) (952:952:952)) - (PORT datac (564:564:564) (581:581:581)) - (PORT datad (1104:1104:1104) (1103:1103:1103)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (938:938:938)) - (PORT datab (1034:1034:1034) (1098:1098:1098)) - (PORT datac (1178:1178:1178) (1210:1210:1210)) - (PORT datad (634:634:634) (667:667:667)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (687:687:687)) - (PORT datab (662:662:662) (710:710:710)) - (PORT datac (629:629:629) (681:681:681)) - (PORT datad (1142:1142:1142) (1152:1152:1152)) + (PORT dataa (1765:1765:1765) (1869:1869:1869)) + (PORT datab (1404:1404:1404) (1428:1428:1428)) + (PORT datac (930:930:930) (938:938:938)) + (PORT datad (1025:1025:1025) (1080:1080:1080)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8680,13 +5598,203 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (670:670:670)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1177:1177:1177) (1212:1212:1212)) - (PORT datad (560:560:560) (587:587:587)) + (PORT dataa (1430:1430:1430) (1448:1448:1448)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (841:841:841) (869:869:869)) + (PORT datad (1026:1026:1026) (1081:1081:1081)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1431:1431:1431) (1472:1472:1472)) + (PORT datab (953:953:953) (985:985:985)) + (PORT datac (845:845:845) (873:873:873)) + (PORT datad (1808:1808:1808) (1892:1892:1892)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (667:667:667)) + (PORT datab (707:707:707) (752:752:752)) + (PORT datac (1220:1220:1220) (1262:1262:1262)) + (PORT datad (1657:1657:1657) (1733:1733:1733)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT datab (865:865:865) (901:901:901)) + (PORT datac (790:790:790) (822:822:822)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2152:2152:2152) (2277:2277:2277)) + (PORT datab (2120:2120:2120) (2264:2264:2264)) + (PORT datac (940:940:940) (1007:1007:1007)) + (PORT datad (1318:1318:1318) (1489:1489:1489)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (880:880:880)) + (PORT datab (1034:1034:1034) (1054:1054:1054)) + (PORT datac (869:869:869) (910:910:910)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (857:857:857)) + (PORT datab (927:927:927) (960:960:960)) + (PORT datac (611:611:611) (676:676:676)) + (PORT datad (551:551:551) (569:569:569)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1079:1079:1079)) + (PORT datab (1101:1101:1101) (1110:1110:1110)) + (PORT datac (1394:1394:1394) (1483:1483:1483)) + (PORT datad (2008:2008:2008) (2038:2038:2038)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1135:1135:1135)) + (PORT datab (914:914:914) (966:966:966)) + (PORT datac (607:607:607) (658:658:658)) + (PORT datad (637:637:637) (694:694:694)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1162:1162:1162)) + (PORT datab (859:859:859) (910:910:910)) + (PORT datac (649:649:649) (714:714:714)) + (PORT datad (1402:1402:1402) (1451:1451:1451)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1370:1370:1370)) + (PORT datab (1279:1279:1279) (1397:1397:1397)) + (PORT datac (1665:1665:1665) (1836:1836:1836)) + (PORT datad (340:340:340) (363:363:363)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1194:1194:1194)) + (PORT datab (1111:1111:1111) (1135:1135:1135)) + (PORT datac (650:650:650) (716:716:716)) + (PORT datad (595:595:595) (624:624:624)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (367:367:367)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (652:652:652) (714:714:714)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8694,158 +5802,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1325:1325:1325) (1384:1384:1384)) - (PORT datab (1536:1536:1536) (1559:1559:1559)) - (PORT datac (1403:1403:1403) (1539:1539:1539)) - (PORT datad (2538:2538:2538) (2656:2656:2656)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1532:1532:1532)) - (PORT datab (1506:1506:1506) (1597:1597:1597)) - (PORT datac (1663:1663:1663) (1679:1679:1679)) - (PORT datad (1485:1485:1485) (1617:1617:1617)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1306:1306:1306)) - (PORT datab (672:672:672) (706:706:706)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (678:678:678) (701:701:701)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2311:2311:2311) (2479:2479:2479)) - (PORT datab (2245:2245:2245) (2328:2328:2328)) - (PORT datac (1401:1401:1401) (1542:1542:1542)) - (PORT datad (1158:1158:1158) (1220:1220:1220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1759:1759:1759) (1850:1850:1850)) - (PORT datab (1660:1660:1660) (1809:1809:1809)) - (PORT datac (1036:1036:1036) (1100:1100:1100)) - (PORT datad (1815:1815:1815) (1892:1892:1892)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1550:1550:1550)) - (PORT datab (1149:1149:1149) (1188:1188:1188)) - (PORT datac (809:809:809) (820:820:820)) - (PORT datad (1490:1490:1490) (1622:1622:1622)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1127:1127:1127)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (1714:1714:1714) (1797:1797:1797)) - (PORT datad (1525:1525:1525) (1626:1626:1626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal76\~2) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (691:691:691)) - (PORT datac (2229:2229:2229) (2297:2297:2297)) - (PORT datad (1684:1684:1684) (1744:1744:1744)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (670:670:670)) - (PORT datab (1492:1492:1492) (1549:1549:1549)) - (PORT datac (1215:1215:1215) (1263:1263:1263)) - (PORT datad (558:558:558) (582:582:582)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1853:1853:1853) (1956:1956:1956)) - (PORT datab (895:895:895) (912:912:912)) - (PORT datac (850:850:850) (899:899:899)) - (PORT datad (1512:1512:1512) (1544:1544:1544)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (1285:1285:1285) (1348:1348:1348)) + (PORT datab (394:394:394) (429:429:429)) + (PORT datac (1106:1106:1106) (1149:1149:1149)) + (PORT datad (1402:1402:1402) (1425:1425:1425)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -8854,13 +5820,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) (DELAY (ABSOLUTE - (PORT dataa (1106:1106:1106) (1144:1144:1144)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1215:1215:1215) (1263:1263:1263)) - (PORT datad (914:914:914) (954:954:954)) + (PORT dataa (928:928:928) (965:965:965)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1440:1440:1440) (1535:1535:1535)) + (PORT datad (1104:1104:1104) (1161:1161:1161)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1784:1784:1784) (1888:1888:1888)) + (PORT datab (1710:1710:1710) (1810:1810:1810)) + (PORT datac (1009:1009:1009) (1083:1083:1083)) + (PORT datad (847:847:847) (865:865:865)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (421:421:421)) + (PORT datab (564:564:564) (586:586:586)) + (PORT datac (1904:1904:1904) (2047:2047:2047)) + (PORT datad (1800:1800:1800) (1912:1912:1912)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -8873,10 +5871,150 @@ (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) + (PORT dataa (1527:1527:1527) (1600:1600:1600)) + (PORT datab (395:395:395) (426:426:426)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1107:1107:1107) (1163:1163:1163)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1900:1900:1900) (1990:1990:1990)) + (PORT datab (1094:1094:1094) (1221:1221:1221)) + (PORT datac (1463:1463:1463) (1531:1531:1531)) + (PORT datad (899:899:899) (933:933:933)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1884:1884:1884)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (850:850:850) (866:866:866)) + (PORT datad (951:951:951) (1015:1015:1015)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1107:1107:1107)) + (PORT datab (1780:1780:1780) (1911:1911:1911)) + (PORT datac (1853:1853:1853) (1971:1971:1971)) + (PORT datad (610:610:610) (664:664:664)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (812:812:812)) + (PORT datab (1492:1492:1492) (1578:1578:1578)) + (PORT datac (915:915:915) (947:947:947)) + (PORT datad (1809:1809:1809) (1891:1891:1891)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1848:1848:1848)) + (PORT datab (1837:1837:1837) (2019:2019:2019)) + (PORT datac (920:920:920) (957:957:957)) + (PORT datad (2247:2247:2247) (2369:2369:2369)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1699:1699:1699) (1875:1875:1875)) + (PORT datac (1239:1239:1239) (1351:1351:1351)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1126:1126:1126)) + (PORT datab (1092:1092:1092) (1217:1217:1217)) + (PORT datac (1679:1679:1679) (1775:1775:1775)) + (PORT datad (811:811:811) (828:828:828)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (2083:2083:2083)) + (PORT datab (846:846:846) (908:908:908)) + (PORT datac (371:371:371) (398:398:398)) + (PORT datad (1799:1799:1799) (1911:1911:1911)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) (PORT datab (197:197:197) (236:236:236)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (172:172:172) (198:198:198)) + (PORT datac (802:802:802) (814:814:814)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -8886,13 +6024,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (705:705:705)) - (PORT datab (384:384:384) (412:412:412)) - (PORT datac (1156:1156:1156) (1181:1181:1181)) - (PORT datad (941:941:941) (985:985:985)) + (PORT dataa (939:939:939) (969:969:969)) + (PORT datab (846:846:846) (891:891:891)) + (PORT datac (881:881:881) (916:916:916)) + (PORT datad (1140:1140:1140) (1143:1143:1143)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -8905,122 +6043,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) (DELAY (ABSOLUTE - (PORT dataa (1248:1248:1248) (1328:1328:1328)) - (PORT datab (986:986:986) (1055:1055:1055)) - (PORT datac (840:840:840) (878:878:878)) - (PORT datad (1355:1355:1355) (1447:1447:1447)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (936:936:936)) - (PORT datab (1220:1220:1220) (1268:1268:1268)) - (PORT datac (1208:1208:1208) (1289:1289:1289)) - (PORT datad (683:683:683) (740:740:740)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (2075:2075:2075) (2210:2210:2210)) - (PORT datab (1511:1511:1511) (1577:1577:1577)) - (PORT datac (590:590:590) (639:639:639)) - (PORT datad (2101:2101:2101) (2201:2201:2201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (976:976:976)) - (PORT datab (251:251:251) (299:299:299)) - (PORT datac (1219:1219:1219) (1264:1264:1264)) - (PORT datad (1755:1755:1755) (1827:1827:1827)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (296:296:296)) - (PORT datab (645:645:645) (664:664:664)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1069:1069:1069)) - (PORT datab (877:877:877) (902:902:902)) - (PORT datac (1046:1046:1046) (1134:1134:1134)) - (PORT datad (1269:1269:1269) (1355:1355:1355)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (913:913:913)) - (PORT datab (636:636:636) (660:660:660)) - (PORT datac (1654:1654:1654) (1746:1746:1746)) - (PORT datad (1116:1116:1116) (1186:1186:1186)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (791:791:791)) - (PORT datab (1248:1248:1248) (1307:1307:1307)) - (PORT datac (1288:1288:1288) (1402:1402:1402)) - (PORT datad (896:896:896) (946:946:946)) + (PORT dataa (1206:1206:1206) (1290:1290:1290)) + (PORT datab (1512:1512:1512) (1590:1590:1590)) + (PORT datac (926:926:926) (963:963:963)) + (PORT datad (1219:1219:1219) (1293:1293:1293)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -9030,125 +6056,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (427:427:427)) - (PORT datab (1208:1208:1208) (1268:1268:1268)) - (PORT datac (959:959:959) (1038:1038:1038)) - (PORT datad (1924:1924:1924) (2082:2082:2082)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1318:1318:1318) (1375:1375:1375)) - (PORT datab (1540:1540:1540) (1661:1661:1661)) - (PORT datac (2217:2217:2217) (2299:2299:2299)) - (PORT datad (919:919:919) (967:967:967)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2766:2766:2766)) - (PORT datab (1244:1244:1244) (1298:1298:1298)) - (PORT datac (873:873:873) (937:937:937)) - (PORT datad (2161:2161:2161) (2331:2331:2331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1265:1265:1265) (1296:1296:1296)) - (PORT datac (1421:1421:1421) (1419:1419:1419)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (671:671:671)) - (PORT datab (1250:1250:1250) (1279:1279:1279)) - (PORT datac (1879:1879:1879) (2050:2050:2050)) - (PORT datad (1649:1649:1649) (1832:1832:1832)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (1359:1359:1359) (1475:1475:1475)) + (PORT datab (982:982:982) (1022:1022:1022)) + (PORT datac (2333:2333:2333) (2437:2437:2437)) + (PORT datad (1745:1745:1745) (1798:1798:1798)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1274:1274:1274)) - (PORT datab (571:571:571) (582:582:582)) - (PORT datac (2046:2046:2046) (2173:2173:2173)) - (PORT datad (1308:1308:1308) (1448:1448:1448)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1012:1012:1012) (1114:1114:1114)) + (PORT datad (993:993:993) (1086:1086:1086)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (686:686:686) (703:703:703)) - (PORT datac (878:878:878) (936:936:936)) - (PORT datad (312:312:312) (329:329:329)) + (PORT dataa (944:944:944) (987:987:987)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (561:561:561) (570:570:570)) + (PORT datad (1165:1165:1165) (1226:1226:1226)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1672:1672:1672)) - (PORT datab (1493:1493:1493) (1610:1610:1610)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (694:694:694) (748:748:748)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9156,28 +6100,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (INSTANCE z80_\|pla_decode_\|Equal48\~0) (DELAY (ABSOLUTE - (PORT datac (2148:2148:2148) (2195:2195:2195)) - (PORT datad (1421:1421:1421) (1470:1470:1470)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1275:1275:1275)) - (PORT datab (1443:1443:1443) (1483:1483:1483)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (1433:1433:1433) (1518:1518:1518)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (2614:2614:2614) (2701:2701:2701)) + (PORT datab (1480:1480:1480) (1572:1572:1572)) + (PORT datac (1261:1261:1261) (1350:1350:1350)) + (PORT datad (1318:1318:1318) (1402:1402:1402)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -9187,12 +6119,12 @@ (INSTANCE z80_\|pla_decode_\|Equal69\~0) (DELAY (ABSOLUTE - (PORT dataa (1981:1981:1981) (2045:2045:2045)) - (PORT datab (2097:2097:2097) (2238:2238:2238)) - (PORT datac (1468:1468:1468) (1539:1539:1539)) - (PORT datad (211:211:211) (249:249:249)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (2618:2618:2618) (2700:2700:2700)) + (PORT datab (1479:1479:1479) (1568:1568:1568)) + (PORT datac (1264:1264:1264) (1348:1348:1348)) + (PORT datad (1319:1319:1319) (1397:1397:1397)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9200,13 +6132,477 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1873:1873:1873) (1941:1941:1941)) - (PORT datab (1345:1345:1345) (1486:1486:1486)) - (PORT datac (2046:2046:2046) (2172:2172:2172)) - (PORT datad (2102:2102:2102) (2203:2203:2203)) + (PORT dataa (352:352:352) (385:385:385)) + (PORT datab (928:928:928) (936:936:936)) + (PORT datac (1571:1571:1571) (1675:1675:1675)) + (PORT datad (623:623:623) (651:651:651)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1142:1142:1142) (1180:1180:1180)) + (PORT datad (1673:1673:1673) (1727:1727:1727)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1824:1824:1824) (1890:1890:1890)) + (PORT datab (1424:1424:1424) (1433:1433:1433)) + (PORT datac (1738:1738:1738) (1800:1800:1800)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (769:769:769)) + (PORT datab (1099:1099:1099) (1172:1172:1172)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (688:688:688) (757:757:757)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (718:718:718) (821:821:821)) + (PORT datad (383:383:383) (413:413:413)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) + (DELAY + (ABSOLUTE + (PORT datac (1254:1254:1254) (1345:1345:1345)) + (PORT datad (1217:1217:1217) (1336:1336:1336)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1254:1254:1254)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (1008:1008:1008) (1084:1084:1084)) + (PORT datad (1267:1267:1267) (1351:1351:1351)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (888:888:888)) + (PORT datab (681:681:681) (754:754:754)) + (PORT datac (1112:1112:1112) (1144:1144:1144)) + (PORT datad (1344:1344:1344) (1364:1364:1364)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (379:379:379)) + (PORT datab (922:922:922) (978:978:978)) + (PORT datac (1143:1143:1143) (1193:1193:1193)) + (PORT datad (532:532:532) (541:541:541)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1684:1684:1684)) + (PORT datac (962:962:962) (1030:1030:1030)) + (PORT datad (1190:1190:1190) (1306:1306:1306)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2228:2228:2228) (2321:2321:2321)) + (PORT datab (947:947:947) (989:989:989)) + (PORT datac (956:956:956) (981:981:981)) + (PORT datad (882:882:882) (922:922:922)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1539:1539:1539) (1650:1650:1650)) + (PORT datad (1192:1192:1192) (1308:1308:1308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1223:1223:1223)) + (PORT datab (685:685:685) (747:747:747)) + (PORT datac (1118:1118:1118) (1152:1152:1152)) + (PORT datad (1186:1186:1186) (1216:1216:1216)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (976:976:976)) + (PORT datab (995:995:995) (1100:1100:1100)) + (PORT datac (1226:1226:1226) (1304:1304:1304)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1472:1472:1472) (1535:1535:1535)) + (PORT datab (2071:2071:2071) (2150:2150:2150)) + (PORT datac (1320:1320:1320) (1415:1415:1415)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1294:1294:1294)) + (PORT datac (1494:1494:1494) (1561:1561:1561)) + (PORT datad (2599:2599:2599) (2706:2706:2706)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1294:1294:1294)) + (PORT datab (744:744:744) (802:802:802)) + (PORT datac (1712:1712:1712) (1798:1798:1798)) + (PORT datad (1358:1358:1358) (1397:1397:1397)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1371:1371:1371)) + (PORT datab (1266:1266:1266) (1384:1384:1384)) + (PORT datac (1654:1654:1654) (1826:1826:1826)) + (PORT datad (339:339:339) (363:363:363)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1292:1292:1292)) + (PORT datab (1397:1397:1397) (1449:1449:1449)) + (PORT datac (1799:1799:1799) (1853:1853:1853)) + (PORT datad (1129:1129:1129) (1176:1176:1176)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (940:940:940)) + (PORT datab (406:406:406) (436:436:436)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1246:1246:1246)) + (PORT datab (729:729:729) (768:768:768)) + (PORT datac (1235:1235:1235) (1255:1255:1255)) + (PORT datad (1872:1872:1872) (1997:1997:1997)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (873:873:873)) + (PORT datab (1951:1951:1951) (1993:1993:1993)) + (PORT datac (1454:1454:1454) (1529:1529:1529)) + (PORT datad (1622:1622:1622) (1648:1648:1648)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (252:252:252)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (579:579:579) (610:610:610)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT datac (1195:1195:1195) (1297:1297:1297)) + (PORT datad (387:387:387) (415:415:415)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1763:1763:1763)) + (PORT datad (1223:1223:1223) (1330:1330:1330)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (767:767:767)) + (PORT datab (1100:1100:1100) (1171:1171:1171)) + (PORT datac (1616:1616:1616) (1690:1690:1690)) + (PORT datad (689:689:689) (753:753:753)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1538:1538:1538)) + (PORT datab (1027:1027:1027) (1079:1079:1079)) + (PORT datac (1504:1504:1504) (1527:1527:1527)) + (PORT datad (1207:1207:1207) (1259:1259:1259)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1702:1702:1702)) + (PORT datab (1485:1485:1485) (1658:1658:1658)) + (PORT datad (1253:1253:1253) (1386:1386:1386)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1918:1918:1918) (1960:1960:1960)) + (PORT datab (965:965:965) (1011:1011:1011)) + (PORT datac (1943:1943:1943) (2015:2015:2015)) + (PORT datad (1174:1174:1174) (1236:1236:1236)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1483:1483:1483)) + (PORT datab (1392:1392:1392) (1495:1495:1495)) + (PORT datac (1400:1400:1400) (1416:1416:1416)) + (PORT datad (1343:1343:1343) (1442:1442:1442)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1243:1243:1243)) + (PORT datab (893:893:893) (924:924:924)) + (PORT datac (1812:1812:1812) (1882:1882:1882)) + (PORT datad (1290:1290:1290) (1364:1364:1364)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1239:1239:1239)) + (PORT datab (1848:1848:1848) (1912:1912:1912)) + (PORT datac (1500:1500:1500) (1540:1540:1540)) + (PORT datad (1288:1288:1288) (1360:1360:1360)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -9216,31 +6612,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) (DELAY (ABSOLUTE - (PORT dataa (1755:1755:1755) (1823:1823:1823)) - (PORT datab (924:924:924) (949:949:949)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (621:621:621) (652:652:652)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (641:641:641) (662:662:662)) - (PORT datac (603:603:603) (623:623:623)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (940:940:940) (993:993:993)) + (PORT datab (1524:1524:1524) (1594:1594:1594)) + (PORT datac (1652:1652:1652) (1708:1708:1708)) + (PORT datad (1936:1936:1936) (2036:2036:2036)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9248,29 +6628,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) (DELAY (ABSOLUTE - (PORT dataa (995:995:995) (1066:1066:1066)) - (PORT datab (876:876:876) (900:900:900)) - (PORT datac (1640:1640:1640) (1827:1827:1827)) - (PORT datad (2138:2138:2138) (2305:2305:2305)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (915:915:915) (948:948:948)) + (PORT datab (1228:1228:1228) (1310:1310:1310)) + (PORT datac (618:618:618) (663:663:663)) + (PORT datad (240:240:240) (292:292:292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) (DELAY (ABSOLUTE - (PORT dataa (1112:1112:1112) (1152:1152:1152)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (863:863:863) (899:899:899)) + (PORT dataa (856:856:856) (866:866:866)) + (PORT datab (666:666:666) (702:702:702)) + (PORT datac (1402:1402:1402) (1435:1435:1435)) + (PORT datad (1808:1808:1808) (1891:1891:1891)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~13) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (953:953:953)) + (PORT datab (271:271:271) (334:334:334)) + (PORT datac (1089:1089:1089) (1107:1107:1107)) + (PORT datad (259:259:259) (307:307:307)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1153:1153:1153)) + (PORT datab (1026:1026:1026) (1145:1145:1145)) + (PORT datac (1638:1638:1638) (1828:1828:1828)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~58) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (626:626:626)) + (PORT datab (736:736:736) (833:833:833)) + (PORT datac (1191:1191:1191) (1283:1283:1283)) + (PORT datad (1588:1588:1588) (1652:1652:1652)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -9278,17 +6706,367 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (961:961:961)) + (PORT datab (643:643:643) (694:694:694)) + (PORT datac (871:871:871) (905:905:905)) + (PORT datad (1172:1172:1172) (1192:1192:1192)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (862:862:862) (901:901:901)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (940:940:940)) + (PORT datac (860:860:860) (868:868:868)) + (PORT datad (1135:1135:1135) (1144:1144:1144)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1242:1242:1242)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (635:635:635) (682:682:682)) + (PORT datad (1176:1176:1176) (1248:1248:1248)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~29) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1057:1057:1057)) + (PORT datab (1144:1144:1144) (1179:1179:1179)) + (PORT datac (1149:1149:1149) (1185:1185:1185)) + (PORT datad (2197:2197:2197) (2275:2275:2275)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1099:1099:1099)) + (PORT datab (995:995:995) (1099:1099:1099)) + (PORT datac (917:917:917) (935:935:935)) + (PORT datad (187:187:187) (222:222:222)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (795:795:795)) + (PORT datab (408:408:408) (439:439:439)) + (PORT datac (1626:1626:1626) (1651:1651:1651)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1699:1699:1699)) + (PORT datab (1278:1278:1278) (1423:1423:1423)) + (PORT datac (1455:1455:1455) (1620:1620:1620)) + (PORT datad (862:862:862) (899:899:899)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1005:1005:1005)) + (PORT datab (1858:1858:1858) (2004:2004:2004)) + (PORT datac (2264:2264:2264) (2329:2329:2329)) + (PORT datad (1177:1177:1177) (1229:1229:1229)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (933:933:933)) + (PORT datab (750:750:750) (821:821:821)) + (PORT datac (1736:1736:1736) (1797:1797:1797)) + (PORT datad (866:866:866) (882:882:882)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2348:2348:2348) (2562:2562:2562)) + (PORT datab (727:727:727) (761:761:761)) + (PORT datac (1323:1323:1323) (1391:1391:1391)) + (PORT datad (1870:1870:1870) (1996:1996:1996)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1226:1226:1226) (1294:1294:1294)) + (PORT datab (1247:1247:1247) (1286:1286:1286)) + (PORT datac (699:699:699) (737:737:737)) + (PORT datad (926:926:926) (985:985:985)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1083:1083:1083)) + (PORT datab (932:932:932) (962:962:962)) + (PORT datac (624:624:624) (681:681:681)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1904:1904:1904) (2042:2042:2042)) + (PORT datab (1311:1311:1311) (1413:1413:1413)) + (PORT datac (935:935:935) (980:980:980)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (564:564:564)) + (PORT datab (868:868:868) (883:883:883)) + (PORT datac (1058:1058:1058) (1084:1084:1084)) + (PORT datad (1402:1402:1402) (1440:1440:1440)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (770:770:770)) + (PORT datab (717:717:717) (795:795:795)) + (PORT datac (1061:1061:1061) (1072:1072:1072)) + (PORT datad (1174:1174:1174) (1204:1204:1204)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1535:1535:1535) (1560:1560:1560)) + (PORT datab (924:924:924) (948:948:948)) + (PORT datac (944:944:944) (990:990:990)) + (PORT datad (931:931:931) (942:942:942)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1694:1694:1694) (1763:1763:1763)) + (PORT datab (1709:1709:1709) (1745:1745:1745)) + (PORT datac (844:844:844) (878:878:878)) + (PORT datad (1561:1561:1561) (1659:1659:1659)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1615:1615:1615) (1693:1693:1693)) + (PORT datab (1807:1807:1807) (1889:1889:1889)) + (PORT datac (1349:1349:1349) (1411:1411:1411)) + (PORT datad (571:571:571) (579:579:579)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (911:911:911)) + (PORT datab (1006:1006:1006) (1090:1090:1090)) + (PORT datac (1009:1009:1009) (1086:1086:1086)) + (PORT datad (812:812:812) (831:831:831)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1415:1415:1415)) + (PORT datab (1566:1566:1566) (1696:1696:1696)) + (PORT datac (1807:1807:1807) (1909:1909:1909)) + (PORT datad (343:343:343) (367:367:367)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (922:922:922)) + (PORT datab (230:230:230) (280:280:280)) + (PORT datac (1357:1357:1357) (1394:1394:1394)) + (PORT datad (1074:1074:1074) (1101:1101:1101)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (352:352:352)) - (PORT datab (251:251:251) (304:304:304)) - (PORT datac (1170:1170:1170) (1219:1219:1219)) - (PORT datad (248:248:248) (302:302:302)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (1550:1550:1550) (1602:1602:1602)) + (PORT datab (965:965:965) (1008:1008:1008)) + (PORT datac (1887:1887:1887) (1918:1918:1918)) + (PORT datad (1174:1174:1174) (1233:1233:1233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -9299,10 +7077,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) (DELAY (ABSOLUTE - (PORT dataa (1554:1554:1554) (1689:1689:1689)) - (PORT datab (1993:1993:1993) (2047:2047:2047)) - (PORT datac (873:873:873) (939:939:939)) - (PORT datad (1697:1697:1697) (1792:1792:1792)) + (PORT dataa (1754:1754:1754) (1821:1821:1821)) + (PORT datab (1521:1521:1521) (1651:1651:1651)) + (PORT datac (1491:1491:1491) (1653:1653:1653)) + (PORT datad (2202:2202:2202) (2322:2322:2322)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -9315,13 +7093,13 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (1238:1238:1238) (1290:1290:1290)) - (PORT datab (616:616:616) (641:641:641)) - (PORT datac (619:619:619) (670:670:670)) - (PORT datad (890:890:890) (915:915:915)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (630:630:630) (649:649:649)) + (PORT datab (836:836:836) (850:850:850)) + (PORT datac (618:618:618) (686:686:686)) + (PORT datad (1216:1216:1216) (1283:1283:1283)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -9331,686 +7109,42 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) (DELAY (ABSOLUTE - (PORT dataa (1847:1847:1847) (1963:1963:1963)) - (PORT datab (926:926:926) (986:986:986)) - (PORT datad (638:638:638) (671:671:671)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT datab (722:722:722) (792:792:792)) + (PORT datac (1102:1102:1102) (1125:1125:1125)) + (PORT datad (635:635:635) (654:654:654)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1154:1154:1154) (1181:1181:1181)) - (PORT datac (320:320:320) (344:344:344)) - (PORT datad (663:663:663) (726:726:726)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (227:227:227) (267:267:267)) - (PORT datac (613:613:613) (637:637:637)) + (PORT dataa (1160:1160:1160) (1164:1164:1164)) + (PORT datab (344:344:344) (379:379:379)) + (PORT datac (836:836:836) (859:859:859)) + (PORT datad (601:601:601) (623:623:623)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1960:1960:1960)) - (PORT datab (674:674:674) (708:708:708)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (903:903:903) (947:947:947)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1091:1091:1091)) - (PORT datab (1843:1843:1843) (1936:1936:1936)) - (PORT datac (990:990:990) (1056:1056:1056)) - (PORT datad (1223:1223:1223) (1265:1265:1265)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2284:2284:2284) (2463:2463:2463)) - (PORT datab (1844:1844:1844) (1935:1935:1935)) - (PORT datac (867:867:867) (913:913:913)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (886:886:886)) - (PORT datab (1403:1403:1403) (1513:1513:1513)) - (PORT datac (650:650:650) (711:711:711)) - (PORT datad (671:671:671) (755:755:755)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (277:277:277) (348:348:348)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (247:247:247) (306:306:306)) - (PORT datad (1203:1203:1203) (1275:1275:1275)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (857:857:857)) - (PORT datab (630:630:630) (708:708:708)) - (PORT datac (832:832:832) (885:885:885)) - (PORT datad (661:661:661) (724:724:724)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (1562:1562:1562) (1606:1606:1606)) - (PORT datac (2770:2770:2770) (2816:2816:2816)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (703:703:703)) - (PORT datab (377:377:377) (403:403:403)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (896:896:896) (921:921:921)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1375:1375:1375)) - (PORT datab (1004:1004:1004) (1054:1054:1054)) - (PORT datac (959:959:959) (1026:1026:1026)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1372:1372:1372)) - (PORT datab (1005:1005:1005) (1052:1052:1052)) - (PORT datac (959:959:959) (1023:1023:1023)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1461:1461:1461) (1557:1557:1557)) - (PORT datab (1071:1071:1071) (1131:1131:1131)) - (PORT datac (1183:1183:1183) (1237:1237:1237)) - (PORT datad (1422:1422:1422) (1471:1471:1471)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (656:656:656)) - (PORT datab (204:204:204) (244:244:244)) - (PORT datac (1380:1380:1380) (1388:1388:1388)) - (PORT datad (1256:1256:1256) (1311:1311:1311)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1542:1542:1542) (1647:1647:1647)) - (PORT datab (1761:1761:1761) (1804:1804:1804)) - (PORT datac (605:605:605) (628:628:628)) - (PORT datad (631:631:631) (654:654:654)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT datab (688:688:688) (737:737:737)) - (PORT datac (381:381:381) (410:410:410)) - (PORT datad (853:853:853) (891:891:891)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (939:939:939)) - (PORT datab (1244:1244:1244) (1260:1260:1260)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (1433:1433:1433) (1449:1449:1449)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (925:925:925)) - (PORT datab (684:684:684) (737:737:737)) - (PORT datac (875:875:875) (914:914:914)) - (PORT datad (1472:1472:1472) (1513:1513:1513)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (671:671:671)) - (PORT datab (684:684:684) (737:737:737)) - (PORT datac (1663:1663:1663) (1676:1676:1676)) - (PORT datad (367:367:367) (388:388:388)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (673:673:673)) - (PORT datab (1692:1692:1692) (1710:1710:1710)) - (PORT datac (836:836:836) (839:839:839)) - (PORT datad (827:827:827) (859:859:859)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (669:669:669)) - (PORT datab (901:901:901) (931:931:931)) - (PORT datac (1661:1661:1661) (1674:1674:1674)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT datab (637:637:637) (657:657:657)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1496:1496:1496)) - (PORT datac (1960:1960:1960) (2130:2130:2130)) - (PORT datad (1151:1151:1151) (1205:1205:1205)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1873:1873:1873)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datac (880:880:880) (894:894:894)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (979:979:979)) - (PORT datac (1035:1035:1035) (1109:1109:1109)) - (PORT datad (617:617:617) (626:626:626)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1681:1681:1681) (1791:1791:1791)) - (PORT datab (1812:1812:1812) (1917:1917:1917)) - (PORT datac (1337:1337:1337) (1365:1365:1365)) - (PORT datad (637:637:637) (687:687:687)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (974:974:974)) - (PORT datab (1062:1062:1062) (1114:1114:1114)) - (PORT datac (1488:1488:1488) (1575:1575:1575)) - (PORT datad (1194:1194:1194) (1262:1262:1262)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (250:250:250)) - (PORT datab (1520:1520:1520) (1602:1602:1602)) - (PORT datac (1087:1087:1087) (1105:1105:1105)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (960:960:960)) - (PORT datab (1658:1658:1658) (1699:1699:1699)) - (PORT datac (1280:1280:1280) (1331:1331:1331)) - (PORT datad (1594:1594:1594) (1614:1614:1614)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (668:668:668)) - (PORT datac (1213:1213:1213) (1256:1256:1256)) - (PORT datad (886:886:886) (936:936:936)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1479:1479:1479)) - (PORT datab (646:646:646) (667:667:667)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (939:939:939) (976:976:976)) - (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) (DELAY (ABSOLUTE - (PORT datac (588:588:588) (596:596:596)) - (PORT datad (863:863:863) (883:883:883)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (830:830:830) (842:842:842)) + (PORT dataa (717:717:717) (791:791:791)) + (PORT datab (1256:1256:1256) (1335:1335:1335)) + (PORT datac (643:643:643) (716:716:716)) + (PORT datad (2264:2264:2264) (2302:2302:2302)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT datab (366:366:366) (387:387:387)) - (PORT datac (593:593:593) (608:608:608)) - (PORT datad (614:614:614) (631:631:631)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1357:1357:1357)) - (PORT datab (1610:1610:1610) (1651:1651:1651)) - (PORT datac (968:968:968) (1039:1039:1039)) - (PORT datad (2195:2195:2195) (2176:2176:2176)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (859:859:859)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (965:965:965) (1009:1009:1009)) - (PORT datad (1114:1114:1114) (1140:1140:1140)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1199:1199:1199)) - (PORT datab (902:902:902) (932:932:932)) - (PORT datac (956:956:956) (1022:1022:1022)) - (PORT datad (196:196:196) (233:233:233)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1279:1279:1279) (1383:1383:1383)) - (PORT datab (637:637:637) (659:659:659)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (955:955:955) (1046:1046:1046)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT datab (1245:1245:1245) (1295:1295:1295)) - (PORT datac (935:935:935) (984:984:984)) - (PORT datad (898:898:898) (966:966:966)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1219:1219:1219)) - (PORT datab (911:911:911) (944:944:944)) - (PORT datac (1136:1136:1136) (1156:1156:1156)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (1342:1342:1342) (1372:1372:1372)) - (PORT datad (1144:1144:1144) (1175:1175:1175)) (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (670:670:670)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (817:817:817) (835:835:835)) - (PORT datad (822:822:822) (842:842:842)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (675:675:675)) - (PORT datab (983:983:983) (1074:1074:1074)) - (PORT datac (1087:1087:1087) (1097:1097:1097)) - (PORT datad (1806:1806:1806) (1916:1916:1916)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10018,89 +7152,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (652:652:652) (674:674:674)) - (PORT datab (947:947:947) (979:979:979)) - (PORT datac (371:371:371) (399:399:399)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (618:618:618) (631:631:631)) - (PORT datac (871:871:871) (877:877:877)) - (PORT datad (577:577:577) (595:595:595)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1376:1376:1376)) - (PORT datab (978:978:978) (1026:1026:1026)) - (PORT datac (966:966:966) (1015:1015:1015)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT dataa (1276:1276:1276) (1362:1362:1362)) - (PORT datab (973:973:973) (1025:1025:1025)) - (PORT datac (974:974:974) (1023:1023:1023)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (536:536:536) (565:565:565)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (969:969:969)) - (PORT datab (2629:2629:2629) (2685:2685:2685)) - (PORT datac (187:187:187) (228:228:228)) - (PORT datad (1382:1382:1382) (1417:1417:1417)) + (PORT dataa (858:858:858) (874:874:874)) + (PORT datab (619:619:619) (644:644:644)) + (PORT datac (590:590:590) (603:603:603)) + (PORT datad (914:914:914) (963:963:963)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -10110,110 +7168,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~8) (DELAY (ABSOLUTE - (PORT dataa (1904:1904:1904) (2087:2087:2087)) - (PORT datab (1498:1498:1498) (1565:1565:1565)) - (PORT datad (1153:1153:1153) (1185:1185:1185)) + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1129:1129:1129) (1168:1168:1168)) + (PORT datac (906:906:906) (947:947:947)) + (PORT datad (814:814:814) (815:815:815)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1931:1931:1931) (1907:1907:1907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1652:1652:1652) (1684:1684:1684)) - (PORT datab (1728:1728:1728) (1737:1737:1737)) - (PORT datac (1191:1191:1191) (1239:1239:1239)) - (PORT datad (1223:1223:1223) (1265:1265:1265)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) (DELAY (ABSOLUTE - (PORT dataa (1220:1220:1220) (1242:1242:1242)) - (PORT datab (1206:1206:1206) (1263:1263:1263)) - (PORT datac (1663:1663:1663) (1680:1680:1680)) - (PORT datad (577:577:577) (596:596:596)) + (PORT dataa (631:631:631) (706:706:706)) + (PORT datac (688:688:688) (784:784:784)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1541:1541:1541)) - (PORT datab (957:957:957) (1012:1012:1012)) - (PORT datac (1200:1200:1200) (1254:1254:1254)) - (PORT datad (1188:1188:1188) (1238:1238:1238)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) (DELAY (ABSOLUTE - (PORT dataa (618:618:618) (653:653:653)) - (PORT datab (1866:1866:1866) (1943:1943:1943)) - (PORT datac (1028:1028:1028) (1092:1092:1092)) - (PORT datad (2619:2619:2619) (2697:2697:2697)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1223:1223:1223) (1275:1275:1275)) - (PORT datab (1259:1259:1259) (1303:1303:1303)) - (PORT datac (863:863:863) (935:935:935)) - (PORT datad (890:890:890) (967:967:967)) + (PORT dataa (1038:1038:1038) (1109:1109:1109)) + (PORT datab (587:587:587) (609:609:609)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (202:202:202) (233:233:233)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (395:395:395)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (925:925:925) (968:968:968)) + (PORT datad (1436:1436:1436) (1453:1453:1453)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10221,12 +7228,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (INSTANCE z80_\|execute_\|setM1\~49) (DELAY (ABSOLUTE - (PORT datab (908:908:908) (944:944:944)) - (PORT datac (636:636:636) (655:655:655)) - (PORT datad (196:196:196) (221:221:221)) + (PORT datab (856:856:856) (900:900:900)) + (PORT datac (1990:1990:1990) (2053:2053:2053)) + (PORT datad (1807:1807:1807) (1897:1897:1897)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT datab (1101:1101:1101) (1165:1165:1165)) + (PORT datac (788:788:788) (826:826:826)) + (PORT datad (1111:1111:1111) (1156:1156:1156)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -10235,13 +7256,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (INSTANCE z80_\|execute_\|setM1\~52) (DELAY (ABSOLUTE - (PORT datab (232:232:232) (283:283:283)) - (PORT datac (2706:2706:2706) (2903:2903:2903)) - (PORT datad (218:218:218) (253:253:253)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (657:657:657) (672:672:672)) + (PORT datab (960:960:960) (996:996:996)) + (PORT datac (849:849:849) (896:896:896)) + (PORT datad (667:667:667) (718:718:718)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10249,31 +7272,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~9) (DELAY (ABSOLUTE - (PORT dataa (1596:1596:1596) (1646:1646:1646)) - (PORT datab (1499:1499:1499) (1573:1573:1573)) - (PORT datac (1471:1471:1471) (1570:1570:1570)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1329:1329:1329)) - (PORT datab (984:984:984) (1057:1057:1057)) - (PORT datac (1948:1948:1948) (2028:2028:2028)) - (PORT datad (1356:1356:1356) (1450:1450:1450)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT datab (1272:1272:1272) (1389:1389:1389)) + (PORT datac (1661:1661:1661) (1831:1831:1831)) + (PORT datad (393:393:393) (424:424:424)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10281,237 +7286,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (1478:1478:1478) (1539:1539:1539)) - (PORT datab (1303:1303:1303) (1403:1403:1403)) - (PORT datac (929:929:929) (1005:1005:1005)) - (PORT datad (1508:1508:1508) (1652:1652:1652)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1003:1003:1003)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (592:592:592) (642:642:642)) - (PORT datad (1235:1235:1235) (1275:1275:1275)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1525:1525:1525) (1588:1588:1588)) - (PORT datab (901:901:901) (934:934:934)) - (PORT datac (1455:1455:1455) (1495:1495:1495)) - (PORT datad (682:682:682) (736:736:736)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (956:956:956) (974:974:974)) - (PORT datac (625:625:625) (647:647:647)) - (PORT datad (575:575:575) (606:606:606)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (725:725:725)) - (PORT datab (1120:1120:1120) (1176:1176:1176)) - (PORT datac (1928:1928:1928) (1998:1998:1998)) - (PORT datad (809:809:809) (845:845:845)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (989:989:989)) - (PORT datab (556:556:556) (587:587:587)) - (PORT datac (963:963:963) (1008:1008:1008)) - (PORT datad (929:929:929) (951:951:951)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (376:376:376)) - (PORT datab (249:249:249) (290:290:290)) - (PORT datac (963:963:963) (1005:1005:1005)) - (PORT datad (929:929:929) (948:948:948)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1101:1101:1101)) - (PORT datab (783:783:783) (890:890:890)) - (PORT datac (726:726:726) (838:838:838)) - (PORT datad (626:626:626) (675:675:675)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1286:1286:1286)) - (PORT datab (342:342:342) (372:372:372)) - (PORT datac (1901:1901:1901) (2064:2064:2064)) - (PORT datad (617:617:617) (629:629:629)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (278:278:278)) - (PORT datab (397:397:397) (437:437:437)) - (PORT datac (975:975:975) (1014:1014:1014)) - (PORT datad (812:812:812) (837:837:837)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (1213:1213:1213) (1257:1257:1257)) - (PORT datad (323:323:323) (347:347:347)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1627:1627:1627) (1675:1675:1675)) - (PORT datab (1195:1195:1195) (1246:1246:1246)) - (PORT datac (1289:1289:1289) (1403:1403:1403)) - (PORT datad (691:691:691) (746:746:746)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (614:614:614) (638:638:638)) - (PORT datac (1132:1132:1132) (1151:1151:1151)) - (PORT datad (696:696:696) (744:744:744)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (726:726:726) (791:791:791)) - (PORT datab (668:668:668) (719:719:719)) - (PORT datac (639:639:639) (684:684:684)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (1154:1154:1154) (1175:1175:1175)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1277:1277:1277) (1396:1396:1396)) + (PORT datac (1664:1664:1664) (1837:1837:1837)) + (PORT datad (391:391:391) (421:421:421)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -10522,10 +7303,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (639:639:639)) - (PORT datab (1176:1176:1176) (1220:1220:1220)) - (PORT datac (1428:1428:1428) (1462:1462:1462)) - (PORT datad (862:862:862) (888:888:888)) + (PORT dataa (1293:1293:1293) (1334:1334:1334)) + (PORT datab (1417:1417:1417) (1431:1431:1431)) + (PORT datac (1163:1163:1163) (1241:1241:1241)) + (PORT datad (656:656:656) (693:693:693)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -10538,881 +7319,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (239:239:239) (291:291:291)) - (PORT datab (986:986:986) (1028:1028:1028)) - (PORT datac (645:645:645) (702:702:702)) - (PORT datad (319:319:319) (331:331:331)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT datab (3601:3601:3601) (3704:3704:3704)) - (PORT datad (1514:1514:1514) (1586:1586:1586)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (641:641:641)) - (PORT datab (1172:1172:1172) (1203:1203:1203)) - (PORT datac (626:626:626) (659:659:659)) - (PORT datad (828:828:828) (846:846:846)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1853:1853:1853) (1955:1955:1955)) - (PORT datab (899:899:899) (946:946:946)) - (PORT datac (894:894:894) (920:920:920)) - (PORT datad (854:854:854) (879:879:879)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT datab (672:672:672) (700:700:700)) - (PORT datad (1120:1120:1120) (1145:1145:1145)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT datab (885:885:885) (918:918:918)) - (PORT datac (1069:1069:1069) (1130:1130:1130)) - (PORT datad (1496:1496:1496) (1538:1538:1538)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (390:390:390)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (552:552:552) (564:564:564)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1826:1826:1826)) - (PORT datab (1263:1263:1263) (1332:1332:1332)) - (PORT datac (1375:1375:1375) (1403:1403:1403)) - (PORT datad (588:588:588) (608:608:608)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2328:2328:2328)) - (PORT datab (879:879:879) (911:911:911)) - (PORT datac (1575:1575:1575) (1707:1707:1707)) - (PORT datad (1688:1688:1688) (1747:1747:1747)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout 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z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (655:655:655) (688:688:688)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (975:975:975)) - (PORT datab (986:986:986) (1041:1041:1041)) - (PORT datac (871:871:871) (933:933:933)) - (PORT datad (885:885:885) (915:915:915)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE 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datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (901:901:901)) - (PORT datab (211:211:211) (255:255:255)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1560:1560:1560) (1654:1654:1654)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (631:631:631)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (628:628:628) (658:658:658)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout 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(1710:1710:1710)) - (PORT datad (985:985:985) (1038:1038:1038)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1100:1100:1100)) - (PORT datab (759:759:759) (866:866:866)) - (PORT datac (608:608:608) (629:629:629)) - (PORT datad (884:884:884) (917:917:917)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1204:1204:1204)) - (PORT datab (372:372:372) (397:397:397)) - (PORT datac (920:920:920) (973:973:973)) - (PORT datad (818:818:818) (865:865:865)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (242:242:242) (289:289:289)) - (PORT datac (202:202:202) (247:247:247)) - (PORT datad (868:868:868) (925:925:925)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1598:1598:1598)) - (PORT datab (1027:1027:1027) (1116:1116:1116)) - (PORT datac (337:337:337) (366:366:366)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1398:1398:1398) (1425:1425:1425)) - (PORT datab (1123:1123:1123) (1145:1145:1145)) - (PORT datac (1387:1387:1387) (1417:1417:1417)) - (PORT datad (337:337:337) (362:362:362)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (955:955:955)) - (PORT datab (705:705:705) (772:772:772)) - (PORT datac (665:665:665) (748:748:748)) - (PORT datad (575:575:575) (591:591:591)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (500:500:500)) - (PORT datab (269:269:269) (353:353:353)) - (PORT datac (1395:1395:1395) (1507:1507:1507)) - (PORT datad (1175:1175:1175) (1258:1258:1258)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1596:1596:1596) (1729:1729:1729)) - (PORT datab (1938:1938:1938) (2043:2043:2043)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (2588:2588:2588) (2666:2666:2666)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2229:2229:2229) (2274:2274:2274)) - (PORT datab (2486:2486:2486) (2693:2693:2693)) - (PORT datac (2230:2230:2230) (2299:2299:2299)) - (PORT datad (1642:1642:1642) (1694:1694:1694)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1286:1286:1286)) - (PORT datab (879:879:879) (905:905:905)) - (PORT datac (2230:2230:2230) (2302:2302:2302)) - (PORT datad (2452:2452:2452) (2652:2652:2652)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (2068:2068:2068) (2112:2112:2112)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (865:865:865)) - (PORT datab (828:828:828) (846:846:846)) - (PORT datac (1565:1565:1565) (1694:1694:1694)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (400:400:400)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (1200:1200:1200) (1252:1252:1252)) - (PORT datad (861:861:861) (911:911:911)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) - (DELAY - (ABSOLUTE - (PORT datac (858:858:858) (869:869:869)) - (PORT datad (1351:1351:1351) (1366:1366:1366)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1515:1515:1515)) - (PORT datab (1191:1191:1191) (1239:1239:1239)) - (PORT datac (1752:1752:1752) (1874:1874:1874)) - (PORT datad (1446:1446:1446) (1521:1521:1521)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (947:947:947)) - (PORT datab (683:683:683) (705:705:705)) - (PORT datac (2071:2071:2071) (2251:2251:2251)) - (PORT datad (1432:1432:1432) (1451:1451:1451)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (844:844:844)) - (PORT datab (887:887:887) (909:909:909)) - (PORT datad (1197:1197:1197) (1224:1224:1224)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (306:306:306) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (842:842:842)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (788:788:788) (792:792:792)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1149:1149:1149)) - (PORT datab (922:922:922) (983:983:983)) - (PORT datac (1898:1898:1898) (2064:2064:2064)) - (PORT datad (1207:1207:1207) (1289:1289:1289)) + (PORT dataa (1216:1216:1216) (1262:1262:1262)) + (PORT datab (1636:1636:1636) (1661:1661:1661)) + (PORT datac (1173:1173:1173) (1214:1214:1214)) + (PORT datad (316:316:316) (338:338:338)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -11422,1231 +7332,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (895:895:895) (939:939:939)) - (PORT datab (457:457:457) (532:532:532)) - (PORT datac (420:420:420) (489:489:489)) - (PORT datad (984:984:984) (1034:1034:1034)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1830:1830:1830) (1974:1974:1974)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (678:678:678) (727:727:727)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1151:1151:1151)) - (PORT datab (1237:1237:1237) (1272:1272:1272)) - (PORT datac (1201:1201:1201) (1255:1255:1255)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (759:759:759)) - (PORT datab (1508:1508:1508) (1551:1551:1551)) - (PORT datac (1985:1985:1985) (2041:2041:2041)) - (PORT datad (1440:1440:1440) (1501:1501:1501)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (933:933:933)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (316:316:316) (335:335:335)) - (PORT datad (590:590:590) (623:623:623)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (2828:2828:2828) (3036:3036:3036)) - (PORT datab (1101:1101:1101) (1114:1114:1114)) - (PORT datac (1504:1504:1504) (1566:1566:1566)) - (PORT datad (1269:1269:1269) (1342:1342:1342)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (900:900:900)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1558:1558:1558) (1654:1654:1654)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1205:1205:1205) (1284:1284:1284)) - (PORT datab (1396:1396:1396) (1445:1445:1445)) - (PORT datac (1194:1194:1194) (1232:1232:1232)) - (PORT datad (1411:1411:1411) (1507:1507:1507)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1304:1304:1304)) - (PORT datab (865:865:865) (920:920:920)) - (PORT datac (1734:1734:1734) (1769:1769:1769)) - (PORT datad (823:823:823) (888:888:888)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (790:790:790)) - (PORT datac (1371:1371:1371) (1479:1479:1479)) - (PORT datad (672:672:672) (752:752:752)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1120:1120:1120)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (1374:1374:1374) (1452:1452:1452)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (773:773:773)) - (PORT datab (666:666:666) (735:735:735)) - (PORT datac (1203:1203:1203) (1259:1259:1259)) - (PORT datad (1108:1108:1108) (1151:1151:1151)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1172:1172:1172)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (2260:2260:2260) (2337:2337:2337)) - (PORT datac (1572:1572:1572) (1704:1704:1704)) - (PORT datad (1683:1683:1683) (1743:1743:1743)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1491:1491:1491)) - (PORT datab (1113:1113:1113) (1143:1143:1143)) - (PORT datac (321:321:321) (347:347:347)) - (PORT datad (606:606:606) (641:641:641)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1280:1280:1280) (1380:1380:1380)) - (PORT datab (980:980:980) (1076:1076:1076)) - (PORT datac (892:892:892) (917:917:917)) - (PORT datad (615:615:615) (665:665:665)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (661:661:661)) - (PORT datab (1481:1481:1481) (1539:1539:1539)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (1257:1257:1257) (1315:1315:1315)) + (PORT dataa (583:583:583) (600:600:600)) + (PORT datab (1201:1201:1201) (1229:1229:1229)) + (PORT datac (1714:1714:1714) (1772:1772:1772)) + (PORT datad (1171:1171:1171) (1220:1220:1220)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1063:1063:1063)) - (PORT datab (906:906:906) (923:923:923)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (890:890:890) (926:926:926)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (233:233:233) (284:284:284)) - (PORT datac (865:865:865) (890:890:890)) - (PORT datad (217:217:217) (249:249:249)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2362:2362:2362) (2435:2435:2435)) - (PORT datab (2736:2736:2736) (2936:2936:2936)) - (PORT datad (869:869:869) (926:926:926)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (668:668:668)) - (PORT datab (632:632:632) (661:661:661)) - (PORT datac (624:624:624) (652:652:652)) - (PORT datad (1153:1153:1153) (1193:1193:1193)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (664:664:664)) - (PORT datab (641:641:641) (658:658:658)) - (PORT datac (649:649:649) (669:669:669)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (1429:1429:1429) (1578:1578:1578)) - (PORT datab (948:948:948) (1000:1000:1000)) - (PORT datac (1287:1287:1287) (1342:1342:1342)) - (PORT datad (1181:1181:1181) (1244:1244:1244)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (973:973:973)) - (PORT datab (1342:1342:1342) (1392:1392:1392)) - (PORT datac (326:326:326) (353:353:353)) - (PORT datad (1427:1427:1427) (1449:1449:1449)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (656:656:656) (678:678:678)) - (PORT datac (928:928:928) (941:941:941)) - (PORT datad (180:180:180) (211:211:211)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (914:914:914)) - (PORT datab (1416:1416:1416) (1546:1546:1546)) - (PORT datac (565:565:565) (575:575:575)) - (PORT datad (936:936:936) (1040:1040:1040)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1375:1375:1375)) - (PORT datab (1855:1855:1855) (2010:2010:2010)) - (PORT datac (1899:1899:1899) (2062:2062:2062)) - (PORT datad (1056:1056:1056) (1088:1088:1088)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (294:294:294)) - (PORT datab (908:908:908) (935:935:935)) - (PORT datac (1721:1721:1721) (1807:1807:1807)) - (PORT datad (644:644:644) (655:655:655)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1022:1022:1022)) - (PORT datab (1458:1458:1458) (1479:1479:1479)) - (PORT datac (1863:1863:1863) (1883:1883:1883)) - (PORT datad (891:891:891) (942:942:942)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (899:899:899) (963:963:963)) - (PORT datac (1275:1275:1275) (1353:1353:1353)) - (PORT datad (819:819:819) (820:820:820)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1011:1011:1011)) - (PORT datab (1539:1539:1539) (1661:1661:1661)) - (PORT datac (2217:2217:2217) (2294:2294:2294)) - (PORT datad (1527:1527:1527) (1620:1620:1620)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (950:950:950) (1002:1002:1002)) - (PORT datab (1222:1222:1222) (1268:1268:1268)) - (PORT datac (825:825:825) (834:834:834)) - (PORT datad (586:586:586) (604:604:604)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1191:1191:1191) (1202:1202:1202)) - (PORT datac (550:550:550) (570:570:570)) - (PORT datad (623:623:623) (657:657:657)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1148:1148:1148) (1198:1198:1198)) - (PORT datab (1473:1473:1473) (1535:1535:1535)) - (PORT datac (1063:1063:1063) (1084:1084:1084)) - (PORT datad (1433:1433:1433) (1485:1485:1485)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (842:842:842) (885:885:885)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (433:433:433)) - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (1189:1189:1189) (1253:1253:1253)) - (PORT datad (646:646:646) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (875:875:875)) - (PORT datab (1717:1717:1717) (1789:1789:1789)) - (PORT datad (1811:1811:1811) (1901:1901:1901)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (846:846:846)) - (PORT datab (887:887:887) (908:908:908)) - (PORT datad (1196:1196:1196) (1223:1223:1223)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (750:750:750) (841:841:841)) - (PORT datab (248:248:248) (331:331:331)) - (PORT datac (787:787:787) (792:792:792)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datac (1412:1412:1412) (1417:1417:1417)) - (PORT datad (1852:1852:1852) (1892:1892:1892)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (287:287:287)) - (PORT datac (1407:1407:1407) (1415:1415:1415)) - (PORT datad (1854:1854:1854) (1894:1894:1894)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (991:991:991) (1026:1026:1026)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1717:1717:1717) (1793:1793:1793)) - (PORT datac (821:821:821) (841:841:841)) - (PORT datad (1809:1809:1809) (1899:1899:1899)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (994:994:994) (1029:1029:1029)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (319:319:319)) - (PORT datab (1080:1080:1080) (1115:1115:1115)) - (PORT datad (360:360:360) (421:421:421)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1479:1479:1479) (1540:1540:1540)) - (PORT datab (1114:1114:1114) (1149:1149:1149)) - (PORT datac (926:926:926) (1002:1002:1002)) - (PORT datad (579:579:579) (597:597:597)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (437:437:437)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (204:204:204) (249:249:249)) - (PORT datad (1311:1311:1311) (1345:1345:1345)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (2034:2034:2034) (2206:2206:2206)) - (PORT datab (1368:1368:1368) (1522:1522:1522)) - (PORT datac (1094:1094:1094) (1159:1159:1159)) - (PORT datad (902:902:902) (911:911:911)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1003:1003:1003)) - (PORT datab (1101:1101:1101) (1135:1135:1135)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (876:876:876) (901:901:901)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1199:1199:1199)) - (PORT datab (961:961:961) (1031:1031:1031)) - (PORT datac (1199:1199:1199) (1282:1282:1282)) - (PORT datad (2867:2867:2867) (2961:2961:2961)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1363:1363:1363) (1378:1378:1378)) - (PORT datad (644:644:644) (658:658:658)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2294:2294:2294) (2473:2473:2473)) - (PORT datab (1742:1742:1742) (1828:1828:1828)) - (PORT datac (1441:1441:1441) (1490:1490:1490)) - (PORT datad (1101:1101:1101) (1143:1143:1143)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1146:1146:1146)) - (PORT datab (1219:1219:1219) (1250:1250:1250)) - (PORT datac (1199:1199:1199) (1241:1241:1241)) - (PORT datad (2219:2219:2219) (2243:2243:2243)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1207:1207:1207)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (838:838:838) (886:886:886)) - (PORT datad (2017:2017:2017) (2045:2045:2045)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1272:1272:1272)) - (PORT datab (1362:1362:1362) (1402:1402:1402)) - (PORT datac (892:892:892) (931:931:931)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1355:1355:1355)) - (PORT datad (870:870:870) (922:922:922)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (986:986:986)) - (PORT datab (653:653:653) (692:692:692)) - (PORT datac (1951:1951:1951) (2031:2031:2031)) - (PORT datad (1598:1598:1598) (1743:1743:1743)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (958:958:958) (975:975:975)) - (PORT datab (978:978:978) (1029:1029:1029)) - (PORT datac (1362:1362:1362) (1399:1399:1399)) - (PORT datad (597:597:597) (611:611:611)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1210:1210:1210)) - (PORT datab (654:654:654) (692:692:692)) - (PORT datac (923:923:923) (937:937:937)) - (PORT datad (855:855:855) (865:865:865)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (301:301:301)) - (PORT datab (928:928:928) (974:974:974)) - (PORT datac (1453:1453:1453) (1529:1529:1529)) - (PORT datad (845:845:845) (857:857:857)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (574:574:574) (585:585:585)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (720:720:720)) - (PORT datab (1610:1610:1610) (1651:1651:1651)) - (PORT datac (1280:1280:1280) (1319:1319:1319)) - (PORT datad (891:891:891) (939:939:939)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (634:634:634)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (614:614:614) (636:636:636)) - (PORT datad (913:913:913) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (386:386:386)) - (PORT datab (1199:1199:1199) (1267:1267:1267)) - (PORT datac (1595:1595:1595) (1618:1618:1618)) - (PORT datad (972:972:972) (1026:1026:1026)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (622:622:622) (668:668:668)) - (PORT datad (869:869:869) (889:889:889)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1286:1286:1286)) - (PORT datab (1475:1475:1475) (1512:1512:1512)) - (PORT datac (1132:1132:1132) (1166:1166:1166)) - (PORT datad (1185:1185:1185) (1228:1228:1228)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (381:381:381)) - (PORT datab (1367:1367:1367) (1378:1378:1378)) - (PORT datac (1077:1077:1077) (1101:1101:1101)) - (PORT datad (1342:1342:1342) (1364:1364:1364)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (741:741:741)) - (PORT datab (919:919:919) (951:951:951)) - (PORT datad (1175:1175:1175) (1224:1224:1224)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) - (DELAY - (ABSOLUTE - (PORT dataa (2212:2212:2212) (2402:2402:2402)) - (PORT datab (1581:1581:1581) (1722:1722:1722)) - (PORT datac (1487:1487:1487) (1611:1611:1611)) - (PORT datad (861:861:861) (890:890:890)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1871:1871:1871)) - (PORT datab (1184:1184:1184) (1250:1250:1250)) - (PORT datac (1904:1904:1904) (1967:1967:1967)) - (PORT datad (1103:1103:1103) (1118:1118:1118)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (401:401:401)) - (PORT datab (641:641:641) (670:670:670)) - (PORT datac (635:635:635) (656:656:656)) - (PORT datad (592:592:592) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1171:1171:1171)) - (PORT datab (882:882:882) (919:919:919)) - (PORT datac (1764:1764:1764) (1841:1841:1841)) - (PORT datad (1133:1133:1133) (1176:1176:1176)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1028:1028:1028)) - (PORT datab (890:890:890) (914:914:914)) - (PORT datac (933:933:933) (977:977:977)) - (PORT datad (1405:1405:1405) (1453:1453:1453)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1187:1187:1187) (1232:1232:1232)) - (PORT datad (616:616:616) (660:660:660)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1278:1278:1278)) - (PORT datab (971:971:971) (1028:1028:1028)) - (PORT datac (871:871:871) (935:935:935)) - (PORT datad (1211:1211:1211) (1261:1261:1261)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (605:605:605) (631:631:631)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) (DELAY (ABSOLUTE - (PORT dataa (1244:1244:1244) (1332:1332:1332)) - (PORT datab (983:983:983) (1057:1057:1057)) - (PORT datac (644:644:644) (684:684:684)) - (PORT datad (1355:1355:1355) (1453:1453:1453)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (983:983:983) (1082:1082:1082)) + (PORT datab (1158:1158:1158) (1188:1188:1188)) + (PORT datac (2045:2045:2045) (2175:2175:2175)) + (PORT datad (904:904:904) (972:972:972)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (971:971:971)) - (PORT datab (1396:1396:1396) (1491:1491:1491)) - (PORT datac (646:646:646) (684:684:684)) - (PORT datad (359:359:359) (387:387:387)) + (PORT dataa (1420:1420:1420) (1489:1489:1489)) + (PORT datab (695:695:695) (751:751:751)) + (PORT datac (605:605:605) (662:662:662)) + (PORT datad (1060:1060:1060) (1056:1056:1056)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -12656,345 +7380,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (1912:1912:1912) (1997:1997:1997)) - (PORT datab (1642:1642:1642) (1792:1792:1792)) - (PORT datac (607:607:607) (647:647:647)) - (PORT datad (1742:1742:1742) (1827:1827:1827)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (684:684:684) (736:736:736)) + (PORT datad (345:345:345) (369:369:369)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1111:1111:1111) (1149:1149:1149)) - (PORT datab (933:933:933) (967:967:967)) - (PORT datac (2220:2220:2220) (2323:2323:2323)) - (PORT datad (1600:1600:1600) (1743:1743:1743)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1383:1383:1383)) - (PORT datab (934:934:934) (970:970:970)) - (PORT datac (2216:2216:2216) (2296:2296:2296)) - (PORT datad (1503:1503:1503) (1626:1626:1626)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1067:1067:1067)) - (PORT datab (877:877:877) (898:898:898)) - (PORT datac (210:210:210) (250:250:250)) - (PORT datad (202:202:202) (229:229:229)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (699:699:699)) - (PORT datab (1206:1206:1206) (1268:1268:1268)) - (PORT datac (1250:1250:1250) (1284:1284:1284)) - (PORT datad (568:568:568) (578:578:578)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1039:1039:1039)) - (PORT datab (1167:1167:1167) (1188:1188:1188)) - (PORT datac (1404:1404:1404) (1438:1438:1438)) - (PORT datad (912:912:912) (940:940:940)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (677:677:677)) - (PORT datab (921:921:921) (977:977:977)) - (PORT datac (1473:1473:1473) (1537:1537:1537)) - (PORT datad (1145:1145:1145) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (933:933:933)) - (PORT datab (1131:1131:1131) (1170:1170:1170)) - (PORT datac (367:367:367) (395:395:395)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (414:414:414) (443:443:443)) + (PORT datab (604:604:604) (620:620:620)) + (PORT datac (673:673:673) (707:707:707)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1285:1285:1285)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (186:186:186) (225:225:225)) - (PORT datad (2031:2031:2031) (2148:2148:2148)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (237:237:237) (281:281:281)) - (PORT datac (208:208:208) (249:249:249)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (3682:3682:3682) (3765:3765:3765)) - (PORT datab (960:960:960) (1060:1060:1060)) - (PORT datac (1232:1232:1232) (1308:1308:1308)) - (PORT datad (669:669:669) (723:723:723)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1998:1998:1998) (2157:2157:2157)) - (PORT datab (1471:1471:1471) (1519:1519:1519)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (1320:1320:1320) (1494:1494:1494)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (790:790:790)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (1592:1592:1592) (1634:1634:1634)) - (PORT datad (1467:1467:1467) (1572:1572:1572)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1102:1102:1102)) - (PORT datab (786:786:786) (892:892:892)) - (PORT datac (1471:1471:1471) (1536:1536:1536)) - (PORT datad (633:633:633) (692:692:692)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2044:2044:2044) (2134:2134:2134)) - (PORT datab (1124:1124:1124) (1155:1155:1155)) - (PORT datac (860:860:860) (892:892:892)) - (PORT datad (666:666:666) (722:722:722)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1100:1100:1100)) - (PORT datab (759:759:759) (866:866:866)) - (PORT datac (1473:1473:1473) (1536:1536:1536)) - (PORT datad (893:893:893) (939:939:939)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1473:1473:1473) (1522:1522:1522)) - (PORT datac (1014:1014:1014) (1048:1048:1048)) - (PORT datad (607:607:607) (642:642:642)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (997:997:997)) - (PORT datab (1257:1257:1257) (1285:1285:1285)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (867:867:867) (902:902:902)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1728:1728:1728) (1837:1837:1837)) - (PORT datac (1359:1359:1359) (1427:1427:1427)) - (PORT datad (1691:1691:1691) (1791:1791:1791)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (649:649:649)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1066:1066:1066) (1088:1088:1088)) - (PORT datad (841:841:841) (877:877:877)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (672:672:672)) - (PORT datab (1188:1188:1188) (1223:1223:1223)) - (PORT datac (506:506:506) (518:518:518)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (653:653:653) (697:697:697)) + (PORT datac (928:928:928) (962:962:962)) + (PORT datad (893:893:893) (916:916:916)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) (DELAY (ABSOLUTE - (PORT dataa (957:957:957) (1055:1055:1055)) - (PORT datab (1495:1495:1495) (1572:1572:1572)) - (PORT datac (190:190:190) (232:232:232)) - (PORT datad (205:205:205) (242:242:242)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1583:1583:1583) (1769:1769:1769)) + (PORT datac (1549:1549:1549) (1691:1691:1691)) + (PORT datad (687:687:687) (752:752:752)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13005,11 +7439,39 @@ (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) (DELAY (ABSOLUTE - (PORT dataa (1404:1404:1404) (1572:1572:1572)) - (PORT datac (1211:1211:1211) (1292:1292:1292)) - (PORT datad (1320:1320:1320) (1484:1484:1484)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1560:1560:1560) (1637:1637:1637)) + (PORT datab (1349:1349:1349) (1459:1459:1459)) + (PORT datad (1016:1016:1016) (1138:1138:1138)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (2972:2972:2972) (3099:3099:3099)) + (PORT datac (910:910:910) (979:979:979)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2420:2420:2420) (2568:2568:2568)) + (PORT datab (663:663:663) (692:692:692)) + (PORT datac (1260:1260:1260) (1346:1346:1346)) + (PORT datad (1321:1321:1321) (1402:1402:1402)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13019,28 +7481,28 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) (DELAY (ABSOLUTE - (PORT dataa (1404:1404:1404) (1567:1567:1567)) - (PORT datab (1663:1663:1663) (1731:1731:1731)) - (PORT datac (1737:1737:1737) (1850:1850:1850)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1242:1242:1242) (1314:1314:1314)) + (PORT datab (1272:1272:1272) (1376:1376:1376)) + (PORT datac (818:818:818) (822:822:822)) + (PORT datad (620:620:620) (663:663:663)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) (DELAY (ABSOLUTE - (PORT dataa (1403:1403:1403) (1571:1571:1571)) - (PORT datab (2575:2575:2575) (2767:2767:2767)) - (PORT datac (1204:1204:1204) (1249:1249:1249)) - (PORT datad (887:887:887) (915:915:915)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (713:713:713) (792:792:792)) + (PORT datac (1151:1151:1151) (1177:1177:1177)) + (PORT datad (1173:1173:1173) (1202:1202:1202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13051,12 +7513,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) (DELAY (ABSOLUTE - (PORT dataa (1241:1241:1241) (1265:1265:1265)) - (PORT datab (618:618:618) (643:643:643)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (350:350:350) (390:390:390)) + (PORT datab (1105:1105:1105) (1137:1137:1137)) + (PORT datac (196:196:196) (229:229:229)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13064,30 +7526,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1682:1682:1682) (1783:1783:1783)) - (PORT datab (2598:2598:2598) (2784:2784:2784)) - (PORT datac (1652:1652:1652) (1819:1819:1819)) - (PORT datad (1573:1573:1573) (1595:1595:1595)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1265:1265:1265) (1319:1319:1319)) - (PORT datab (1090:1090:1090) (1145:1145:1145)) - (PORT datac (1586:1586:1586) (1738:1738:1738)) - (PORT datad (1474:1474:1474) (1508:1508:1508)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1392:1392:1392) (1400:1400:1400)) + (PORT datab (1623:1623:1623) (1756:1756:1756)) + (PORT datac (907:907:907) (980:980:980)) + (PORT datad (650:650:650) (700:700:700)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13096,13 +7542,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) + (INSTANCE z80_\|pla_decode_\|Equal10\~1) (DELAY (ABSOLUTE - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (1089:1089:1089) (1133:1133:1133)) - (PORT datad (218:218:218) (256:256:256)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT datac (1560:1560:1560) (1661:1661:1661)) + (PORT datad (1255:1255:1255) (1387:1387:1387)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1746:1746:1746) (1793:1793:1793)) + (PORT datab (1486:1486:1486) (1656:1656:1656)) + (PORT datac (1391:1391:1391) (1450:1450:1450)) + (PORT datad (188:188:188) (222:222:222)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (900:900:900)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1465:1465:1465) (1549:1549:1549)) + (PORT datad (1084:1084:1084) (1110:1110:1110)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13110,31 +7586,539 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) (DELAY (ABSOLUTE - (PORT dataa (1475:1475:1475) (1530:1530:1530)) - (PORT datab (1552:1552:1552) (1583:1583:1583)) - (PORT datac (1503:1503:1503) (1583:1583:1583)) - (PORT datad (1969:1969:1969) (2022:2022:2022)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (639:639:639) (659:659:659)) + (PORT datab (849:849:849) (897:897:897)) + (PORT datac (1652:1652:1652) (1699:1699:1699)) + (PORT datad (1506:1506:1506) (1550:1550:1550)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1895:1895:1895) (1956:1956:1956)) + (PORT datab (1654:1654:1654) (1684:1684:1684)) + (PORT datac (711:711:711) (755:755:755)) + (PORT datad (621:621:621) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1560:1560:1560) (1639:1639:1639)) + (PORT datac (1318:1318:1318) (1431:1431:1431)) + (PORT datad (1418:1418:1418) (1468:1468:1468)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (887:887:887)) + (PORT datab (969:969:969) (1005:1005:1005)) + (PORT datac (1887:1887:1887) (1916:1916:1916)) + (PORT datad (1176:1176:1176) (1231:1231:1231)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (841:841:841)) + (PORT datab (862:862:862) (884:884:884)) + (PORT datac (586:586:586) (605:605:605)) + (PORT datad (828:828:828) (843:843:843)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (205:205:205) (248:248:248)) + (PORT datac (823:823:823) (866:866:866)) + (PORT datad (1432:1432:1432) (1491:1491:1491)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1919:1919:1919) (1955:1955:1955)) + (PORT datab (1212:1212:1212) (1268:1268:1268)) + (PORT datac (876:876:876) (901:901:901)) + (PORT datad (834:834:834) (863:863:863)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (638:638:638) (688:688:688)) + (PORT datac (1003:1003:1003) (1032:1032:1032)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1111:1111:1111)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (730:730:730) (820:820:820)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (1092:1092:1092) (1112:1112:1112)) + (PORT datad (1054:1054:1054) (1061:1061:1061)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (2618:2618:2618) (2706:2706:2706)) + (PORT datab (692:692:692) (737:737:737)) + (PORT datac (1476:1476:1476) (1528:1528:1528)) + (PORT datad (1320:1320:1320) (1396:1396:1396)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2143:2143:2143) (2167:2167:2167)) + (PORT datab (677:677:677) (755:755:755)) + (PORT datac (1109:1109:1109) (1145:1145:1145)) + (PORT datad (1342:1342:1342) (1364:1364:1364)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1204:1204:1204)) + (PORT datab (917:917:917) (942:942:942)) + (PORT datac (1176:1176:1176) (1217:1217:1217)) + (PORT datad (2375:2375:2375) (2378:2378:2378)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1015:1015:1015)) + (PORT datab (1894:1894:1894) (2026:2026:2026)) + (PORT datac (910:910:910) (967:967:967)) + (PORT datad (716:716:716) (799:799:799)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1601:1601:1601) (1742:1742:1742)) + (PORT datab (1577:1577:1577) (1679:1679:1679)) + (PORT datac (1072:1072:1072) (1099:1099:1099)) + (PORT datad (630:630:630) (652:652:652)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (456:456:456)) + (PORT datab (1460:1460:1460) (1546:1546:1546)) + (PORT datac (656:656:656) (690:690:690)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (693:693:693)) + (PORT datab (942:942:942) (965:965:965)) + (PORT datac (551:551:551) (557:557:557)) + (PORT datad (614:614:614) (628:628:628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (898:898:898)) + (PORT datab (1370:1370:1370) (1420:1420:1420)) + (PORT datac (179:179:179) (218:218:218)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2059:2059:2059) (2175:2175:2175)) + (PORT datab (1544:1544:1544) (1669:1669:1669)) + (PORT datac (1139:1139:1139) (1215:1215:1215)) + (PORT datad (1570:1570:1570) (1584:1584:1584)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1122:1122:1122)) + (PORT datab (1498:1498:1498) (1562:1562:1562)) + (PORT datac (849:849:849) (866:866:866)) + (PORT datad (1134:1134:1134) (1147:1147:1147)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1403:1403:1403)) + (PORT datab (2424:2424:2424) (2550:2550:2550)) + (PORT datac (1153:1153:1153) (1213:1213:1213)) + (PORT datad (195:195:195) (231:231:231)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (721:721:721)) + (PORT datac (637:637:637) (662:662:662)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (960:960:960)) + (PORT datab (1848:1848:1848) (1918:1918:1918)) + (PORT datac (1513:1513:1513) (1556:1556:1556)) + (PORT datad (1675:1675:1675) (1725:1725:1725)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT datab (1140:1140:1140) (1160:1160:1160)) + (PORT datac (502:502:502) (515:515:515)) + (PORT datad (1092:1092:1092) (1122:1122:1122)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) (DELAY (ABSOLUTE - (PORT dataa (944:944:944) (982:982:982)) - (PORT datab (685:685:685) (707:707:707)) - (PORT datac (623:623:623) (648:648:648)) - (PORT datad (195:195:195) (220:220:220)) + (PORT dataa (869:869:869) (881:881:881)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (182:182:182) (221:221:221)) + (PORT datad (899:899:899) (936:936:936)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1006:1006:1006)) + (PORT datab (1759:1759:1759) (1865:1865:1865)) + (PORT datac (946:946:946) (1010:1010:1010)) + (PORT datad (1636:1636:1636) (1698:1698:1698)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1395:1395:1395)) + (PORT datab (1759:1759:1759) (1866:1866:1866)) + (PORT datac (1523:1523:1523) (1638:1638:1638)) + (PORT datad (1222:1222:1222) (1286:1286:1286)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1375:1375:1375)) + (PORT datab (737:737:737) (835:835:835)) + (PORT datac (976:976:976) (1074:1074:1074)) + (PORT datad (994:994:994) (1020:1020:1020)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (310:310:310)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datad (1076:1076:1076) (1094:1094:1094)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1601:1601:1601) (1746:1746:1746)) + (PORT datab (1582:1582:1582) (1698:1698:1698)) + (PORT datac (609:609:609) (656:656:656)) + (PORT datad (613:613:613) (666:666:666)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1005:1005:1005)) + (PORT datab (1897:1897:1897) (2027:2027:2027)) + (PORT datac (907:907:907) (963:963:963)) + (PORT datad (718:718:718) (799:799:799)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1535:1535:1535) (1581:1581:1581)) + (PORT datab (919:919:919) (965:965:965)) + (PORT datac (919:919:919) (951:951:951)) + (PORT datad (1808:1808:1808) (1894:1894:1894)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1184:1184:1184)) + (PORT datab (1846:1846:1846) (1931:1931:1931)) + (PORT datac (1190:1190:1190) (1239:1239:1239)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (707:707:707)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (835:835:835) (876:876:876)) + (PORT datad (531:531:531) (537:537:537)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1195:1195:1195)) + (PORT datab (1379:1379:1379) (1425:1425:1425)) + (PORT datac (1518:1518:1518) (1583:1583:1583)) + (PORT datad (1075:1075:1075) (1093:1093:1093)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13145,10 +8129,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (256:256:256)) - (PORT datab (648:648:648) (674:674:674)) - (PORT datac (902:902:902) (952:952:952)) - (PORT datad (923:923:923) (972:972:972)) + (PORT dataa (1337:1337:1337) (1334:1334:1334)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (617:617:617) (644:644:644)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -13161,179 +8145,9 @@ (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) (DELAY (ABSOLUTE - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (1346:1346:1346) (1374:1374:1374)) - (PORT datad (825:825:825) (853:853:853)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (907:907:907)) - (PORT datab (1078:1078:1078) (1132:1132:1132)) - (PORT datac (515:515:515) (534:534:534)) - (PORT datad (522:522:522) (533:533:533)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1320:1320:1320) (1381:1381:1381)) - (PORT datab (2246:2246:2246) (2335:2335:2335)) - (PORT datac (1395:1395:1395) (1531:1531:1531)) - (PORT datad (908:908:908) (933:933:933)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1222:1222:1222)) - (PORT datab (1197:1197:1197) (1273:1273:1273)) - (PORT datac (877:877:877) (942:942:942)) - (PORT datad (1209:1209:1209) (1259:1259:1259)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (986:986:986)) - (PORT datab (935:935:935) (974:974:974)) - (PORT datac (1208:1208:1208) (1267:1267:1267)) - (PORT datad (580:580:580) (609:609:609)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1309:1309:1309) (1367:1367:1367)) - (PORT datab (1760:1760:1760) (1823:1823:1823)) - (PORT datac (780:780:780) (832:832:832)) - (PORT datad (2119:2119:2119) (2113:2113:2113)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1164:1164:1164)) - (PORT datab (1248:1248:1248) (1297:1297:1297)) - (PORT datad (900:900:900) (967:967:967)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1008:1008:1008)) - (PORT datab (667:667:667) (689:689:689)) - (PORT datac (844:844:844) (882:882:882)) - (PORT datad (865:865:865) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (1146:1146:1146) (1171:1171:1171)) - (PORT datac (202:202:202) (240:240:240)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (705:705:705)) - (PORT datab (344:344:344) (376:376:376)) - (PORT datac (1158:1158:1158) (1183:1183:1183)) - (PORT datad (942:942:942) (987:987:987)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1155:1155:1155)) - (PORT datab (660:660:660) (713:713:713)) - (PORT datac (904:904:904) (922:922:922)) - (PORT datad (820:820:820) (840:840:840)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (240:240:240) (286:286:286)) - (PORT datac (211:211:211) (254:254:254)) + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (384:384:384) (413:413:413)) + (PORT datac (878:878:878) (904:904:904)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -13342,127 +8156,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) (DELAY (ABSOLUTE - (PORT dataa (1301:1301:1301) (1320:1320:1320)) - (PORT datab (2020:2020:2020) (2143:2143:2143)) - (PORT datac (1955:1955:1955) (2058:2058:2058)) - (PORT datad (1295:1295:1295) (1376:1376:1376)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1262:1262:1262)) - (PORT datab (1197:1197:1197) (1269:1269:1269)) - (PORT datac (1021:1021:1021) (1050:1050:1050)) - (PORT datad (315:315:315) (333:333:333)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2144:2144:2144) (2265:2265:2265)) - (PORT datab (1690:1690:1690) (1867:1867:1867)) - (PORT datac (604:604:604) (619:619:619)) - (PORT datad (2025:2025:2025) (2071:2071:2071)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (2076:2076:2076) (2173:2173:2173)) - (PORT datab (1169:1169:1169) (1260:1260:1260)) - (PORT datac (1442:1442:1442) (1488:1488:1488)) - (PORT datad (1368:1368:1368) (1396:1396:1396)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (942:942:942)) - (PORT datab (677:677:677) (721:721:721)) - (PORT datac (1761:1761:1761) (1841:1841:1841)) - (PORT datad (1762:1762:1762) (1819:1819:1819)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1482:1482:1482)) - (PORT datab (910:910:910) (937:937:937)) - (PORT datac (1440:1440:1440) (1519:1519:1519)) - (PORT datad (838:838:838) (870:870:870)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (961:961:961)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (619:619:619) (672:672:672)) - (PORT datad (598:598:598) (648:648:648)) + (PORT dataa (841:841:841) (934:934:934)) + (PORT datab (885:885:885) (903:903:903)) + (PORT datac (1055:1055:1055) (1102:1102:1102)) + (PORT datad (1086:1086:1086) (1124:1124:1124)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (911:911:911)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (812:812:812) (847:847:847)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13470,563 +8172,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (693:693:693)) - (PORT datab (661:661:661) (693:693:693)) - (PORT datac (634:634:634) (677:677:677)) - (PORT datad (348:348:348) (370:370:370)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1319:1319:1319)) - (PORT datab (1236:1236:1236) (1274:1274:1274)) - (PORT datac (625:625:625) (679:679:679)) - (PORT datad (1191:1191:1191) (1247:1247:1247)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (950:950:950) (979:979:979)) - (PORT datad (624:624:624) (649:649:649)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2353:2353:2353) (2461:2461:2461)) - (PORT datab (976:976:976) (1005:1005:1005)) - (PORT datac (1088:1088:1088) (1104:1104:1104)) - (PORT datad (1772:1772:1772) (1890:1890:1890)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (907:907:907) (918:918:918)) - (PORT datac (1188:1188:1188) (1230:1230:1230)) - (PORT datad (1430:1430:1430) (1500:1500:1500)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datac (1693:1693:1693) (1727:1727:1727)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (672:672:672)) - (PORT datab (578:578:578) (605:605:605)) - (PORT datac (1476:1476:1476) (1572:1572:1572)) - (PORT datad (1639:1639:1639) (1701:1701:1701)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1315:1315:1315)) - (PORT datab (1165:1165:1165) (1196:1196:1196)) - (PORT datac (912:912:912) (969:969:969)) - (PORT datad (314:314:314) (333:333:333)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1047:1047:1047) (1053:1053:1053)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1758:1758:1758) (1900:1900:1900)) - (PORT datab (902:902:902) (950:950:950)) - (PORT datac (1212:1212:1212) (1261:1261:1261)) - (PORT datad (2454:2454:2454) (2652:2652:2652)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT datab (664:664:664) (686:686:686)) - (PORT datac (185:185:185) (223:223:223)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1193:1193:1193) (1290:1290:1290)) - (PORT datab (1597:1597:1597) (1747:1747:1747)) - (PORT datac (1512:1512:1512) (1646:1646:1646)) - (PORT datad (1772:1772:1772) (1860:1860:1860)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (2076:2076:2076) (2171:2171:2171)) - (PORT datab (1273:1273:1273) (1341:1341:1341)) - (PORT datac (1497:1497:1497) (1578:1578:1578)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (420:420:420)) - (PORT datab (1273:1273:1273) (1342:1342:1342)) - (PORT datac (1152:1152:1152) (1193:1193:1193)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datab (601:601:601) (645:645:645)) - (PORT datac (1369:1369:1369) (1405:1405:1405)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (725:725:725)) - (PORT datab (952:952:952) (1009:1009:1009)) - (PORT datac (1500:1500:1500) (1582:1582:1582)) - (PORT datad (1167:1167:1167) (1248:1248:1248)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (1458:1458:1458) (1477:1477:1477)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1377:1377:1377)) - (PORT datab (1178:1178:1178) (1247:1247:1247)) - (PORT datac (1503:1503:1503) (1562:1562:1562)) - (PORT datad (642:642:642) (693:693:693)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (1217:1217:1217) (1266:1266:1266)) - (PORT datac (1500:1500:1500) (1564:1564:1564)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1389:1389:1389) (1465:1465:1465)) - (PORT datab (1685:1685:1685) (1852:1852:1852)) - (PORT datac (982:982:982) (980:980:980)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1140:1140:1140) (1183:1183:1183)) - (PORT datab (662:662:662) (713:713:713)) - (PORT datac (627:627:627) (681:681:681)) - (PORT datad (640:640:640) (676:676:676)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1655:1655:1655) (1726:1726:1726)) - (PORT datab (1375:1375:1375) (1391:1391:1391)) - (PORT datac (1118:1118:1118) (1174:1174:1174)) - (PORT datad (624:624:624) (643:643:643)) + (PORT dataa (925:925:925) (961:961:961)) + (PORT datab (1417:1417:1417) (1473:1473:1473)) + (PORT datac (1652:1652:1652) (1707:1707:1707)) + (PORT datad (1487:1487:1487) (1555:1555:1555)) (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) (DELAY (ABSOLUTE - (PORT dataa (1183:1183:1183) (1210:1210:1210)) - (PORT datab (1380:1380:1380) (1398:1398:1398)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (257:257:257)) - (PORT datab (663:663:663) (690:690:690)) - (PORT datac (188:188:188) (229:229:229)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (384:384:384)) - (PORT datab (811:811:811) (819:819:819)) - (PORT datac (1421:1421:1421) (1484:1484:1484)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (1256:1256:1256) (1322:1322:1322)) + (PORT datab (951:951:951) (987:987:987)) + (PORT datac (1107:1107:1107) (1146:1146:1146)) + (PORT datad (1934:1934:1934) (2036:2036:2036)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (1645:1645:1645) (1680:1680:1680)) - (PORT datab (1246:1246:1246) (1316:1316:1316)) - (PORT datac (1499:1499:1499) (1579:1579:1579)) - (PORT datad (2049:2049:2049) (2131:2131:2131)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (1066:1066:1066) (1146:1146:1146)) + (PORT datab (919:919:919) (992:992:992)) + (PORT datac (1106:1106:1106) (1143:1143:1143)) + (PORT datad (2265:2265:2265) (2302:2302:2302)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (285:285:285)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (552:552:552) (565:565:565)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1799:1799:1799) (1901:1901:1901)) - (PORT datab (1594:1594:1594) (1745:1745:1745)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1620:1620:1620) (1635:1635:1635)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1533:1533:1533) (1601:1601:1601)) - (PORT datab (1750:1750:1750) (1829:1829:1829)) - (PORT datac (1522:1522:1522) (1600:1600:1600)) - (PORT datad (337:337:337) (356:356:356)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (761:761:761)) - (PORT datab (915:915:915) (968:968:968)) - (PORT datac (1718:1718:1718) (1796:1796:1796)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1531:1531:1531) (1599:1599:1599)) - (PORT datab (1097:1097:1097) (1130:1130:1130)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1896:1896:1896) (1969:1969:1969)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (761:761:761)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1068:1068:1068) (1100:1100:1100)) - (PORT datad (1691:1691:1691) (1730:1730:1730)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1483:1483:1483)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (631:631:631) (655:655:655)) - (PORT datad (1901:1901:1901) (1974:1974:1974)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (690:690:690)) - (PORT datab (610:610:610) (635:635:635)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1482:1482:1482)) - (PORT datab (979:979:979) (1023:1023:1023)) - (PORT datac (1196:1196:1196) (1241:1241:1241)) - (PORT datad (1188:1188:1188) (1214:1214:1214)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1204:1204:1204)) - (PORT datab (1148:1148:1148) (1184:1184:1184)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) (DELAY (ABSOLUTE - (PORT dataa (1749:1749:1749) (1821:1821:1821)) - (PORT datab (1396:1396:1396) (1445:1445:1445)) - (PORT datac (1206:1206:1206) (1248:1248:1248)) - (PORT datad (1501:1501:1501) (1578:1578:1578)) + (PORT dataa (938:938:938) (968:968:968)) + (PORT datab (907:907:907) (922:922:922)) + (PORT datac (1186:1186:1186) (1234:1234:1234)) + (PORT datad (1409:1409:1409) (1429:1429:1429)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14039,12 +8255,60 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) (DELAY (ABSOLUTE - (PORT dataa (1747:1747:1747) (1821:1821:1821)) - (PORT datab (1398:1398:1398) (1449:1449:1449)) - (PORT datac (1474:1474:1474) (1513:1513:1513)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1532:1532:1532) (1578:1578:1578)) + (PORT datab (1445:1445:1445) (1467:1467:1467)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (911:911:911) (925:925:925)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1675:1675:1675)) + (PORT datab (1290:1290:1290) (1292:1292:1292)) + (PORT datac (1749:1749:1749) (1883:1883:1883)) + (PORT datad (637:637:637) (688:688:688)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (1621:1621:1621) (1754:1754:1754)) + (PORT datab (1721:1721:1721) (1762:1762:1762)) + (PORT datac (1102:1102:1102) (1143:1143:1143)) + (PORT datad (1733:1733:1733) (1842:1842:1842)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1172:1172:1172)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1116:1116:1116) (1172:1172:1172)) + (PORT datad (798:798:798) (804:804:804)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14055,10 +8319,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) (DELAY (ABSOLUTE - (PORT dataa (1260:1260:1260) (1306:1306:1306)) - (PORT datab (1543:1543:1543) (1626:1626:1626)) - (PORT datac (912:912:912) (982:982:982)) - (PORT datad (959:959:959) (1003:1003:1003)) + (PORT dataa (1151:1151:1151) (1192:1192:1192)) + (PORT datab (681:681:681) (718:718:718)) + (PORT datac (1131:1131:1131) (1165:1165:1165)) + (PORT datad (1105:1105:1105) (1161:1161:1161)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14071,44 +8335,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) (DELAY (ABSOLUTE - (PORT dataa (1181:1181:1181) (1240:1240:1240)) - (PORT datab (994:994:994) (1040:1040:1040)) - (PORT datac (909:909:909) (977:977:977)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (984:984:984)) - (PORT datab (1911:1911:1911) (2074:2074:2074)) - (PORT datac (1899:1899:1899) (2060:2060:2060)) - (PORT datad (1058:1058:1058) (1086:1086:1086)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1286:1286:1286)) - (PORT datab (1215:1215:1215) (1233:1233:1233)) - (PORT datac (833:833:833) (881:881:881)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1132:1132:1132) (1205:1205:1205)) + (PORT datab (1094:1094:1094) (1119:1119:1119)) + (PORT datac (1130:1130:1130) (1168:1168:1168)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14119,12 +8351,76 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (624:624:624) (649:649:649)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (367:367:367) (408:408:408)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (769:769:769) (783:783:783)) + (PORT datad (601:601:601) (627:627:627)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1531:1531:1531)) + (PORT datab (921:921:921) (951:951:951)) + (PORT datac (1695:1695:1695) (1732:1732:1732)) + (PORT datad (964:964:964) (1058:1058:1058)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (954:954:954)) + (PORT datab (1592:1592:1592) (1691:1691:1691)) + (PORT datac (619:619:619) (686:686:686)) + (PORT datad (887:887:887) (907:907:907)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (724:724:724)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (858:858:858) (880:880:880)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (308:308:308)) + (PORT datab (1679:1679:1679) (1718:1718:1718)) + (PORT datac (1916:1916:1916) (2000:2000:2000)) + (PORT datad (342:342:342) (353:353:353)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14135,10 +8431,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (926:926:926)) - (PORT datab (875:875:875) (918:918:918)) - (PORT datac (635:635:635) (664:664:664)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (1101:1101:1101) (1123:1123:1123)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (985:985:985) (987:987:987)) + (PORT datad (195:195:195) (220:220:220)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -14148,15 +8444,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~50) (DELAY (ABSOLUTE - (PORT dataa (2896:2896:2896) (2954:2954:2954)) - (PORT datab (1052:1052:1052) (1116:1116:1116)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (2591:2591:2591) (2649:2649:2649)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1045:1045:1045) (1183:1183:1183)) + (PORT datab (1473:1473:1473) (1564:1564:1564)) + (PORT datac (560:560:560) (571:571:571)) + (PORT datad (893:893:893) (899:899:899)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14164,15 +8460,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1270:1270:1270)) - (PORT datab (1101:1101:1101) (1135:1135:1135)) - (PORT datac (1363:1363:1363) (1380:1380:1380)) - (PORT datad (1191:1191:1191) (1245:1245:1245)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1260:1260:1260) (1356:1356:1356)) + (PORT datab (902:902:902) (942:942:942)) + (PORT datac (1171:1171:1171) (1226:1226:1226)) + (PORT datad (1161:1161:1161) (1191:1191:1191)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14180,15 +8476,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) (DELAY (ABSOLUTE - (PORT dataa (1384:1384:1384) (1464:1464:1464)) - (PORT datab (628:628:628) (673:673:673)) - (PORT datac (611:611:611) (637:637:637)) - (PORT datad (697:697:697) (744:744:744)) + (PORT dataa (1361:1361:1361) (1449:1449:1449)) + (PORT datab (642:642:642) (696:696:696)) + (PORT datac (1261:1261:1261) (1352:1352:1352)) + (PORT datad (628:628:628) (656:656:656)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1587:1587:1587)) + (PORT datab (1233:1233:1233) (1294:1294:1294)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1129:1129:1129) (1176:1176:1176)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT datac (806:806:806) (814:814:814)) + (PORT datad (335:335:335) (354:354:354)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1461:1461:1461)) + (PORT datab (916:916:916) (988:988:988)) + (PORT datac (1652:1652:1652) (1712:1712:1712)) + (PORT datad (1488:1488:1488) (1556:1556:1556)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (944:944:944)) + (PORT datab (1190:1190:1190) (1265:1265:1265)) + (PORT datac (932:932:932) (950:950:950)) + (PORT datad (913:913:913) (945:945:945)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14196,13 +8552,535 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (853:853:853) (883:883:883)) - (PORT datab (877:877:877) (946:946:946)) - (PORT datac (2034:2034:2034) (2072:2072:2072)) - (PORT datad (821:821:821) (867:867:867)) + (PORT dataa (611:611:611) (652:652:652)) + (PORT datab (907:907:907) (925:925:925)) + (PORT datac (916:916:916) (949:949:949)) + (PORT datad (1807:1807:1807) (1896:1896:1896)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (857:857:857) (901:901:901)) + (PORT datac (631:631:631) (669:669:669)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (830:830:830)) + (PORT datab (1496:1496:1496) (1556:1556:1556)) + (PORT datac (1290:1290:1290) (1403:1403:1403)) + (PORT datad (925:925:925) (942:942:942)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (832:832:832)) + (PORT datab (922:922:922) (966:966:966)) + (PORT datac (808:808:808) (819:819:819)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (965:965:965)) + (PORT datab (1443:1443:1443) (1506:1506:1506)) + (PORT datac (1247:1247:1247) (1308:1308:1308)) + (PORT datad (1042:1042:1042) (1057:1057:1057)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1586:1586:1586) (1605:1605:1605)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~51) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (402:402:402)) + (PORT datab (2163:2163:2163) (2293:2293:2293)) + (PORT datac (1532:1532:1532) (1659:1659:1659)) + (PORT datad (1753:1753:1753) (1887:1887:1887)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1191:1191:1191) (1272:1272:1272)) + (PORT datac (1113:1113:1113) (1173:1173:1173)) + (PORT datad (196:196:196) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1561:1561:1561) (1690:1690:1690)) + (PORT datac (351:351:351) (378:378:378)) + (PORT datad (1790:1790:1790) (1874:1874:1874)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1675:1675:1675)) + (PORT datab (1678:1678:1678) (1721:1721:1721)) + (PORT datac (622:622:622) (663:663:663)) + (PORT datad (1568:1568:1568) (1662:1662:1662)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (590:590:590) (599:599:599)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1865:1865:1865) (1966:1966:1966)) + (PORT datab (882:882:882) (905:905:905)) + (PORT datac (2364:2364:2364) (2512:2512:2512)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1623:1623:1623)) + (PORT datab (1197:1197:1197) (1221:1221:1221)) + (PORT datac (830:830:830) (850:850:850)) + (PORT datad (314:314:314) (333:333:333)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (692:692:692) (719:719:719)) + (PORT datac (576:576:576) (585:585:585)) + (PORT datad (890:890:890) (930:930:930)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1087:1087:1087)) + (PORT datab (702:702:702) (742:742:742)) + (PORT datac (602:602:602) (664:664:664)) + (PORT datad (1141:1141:1141) (1142:1142:1142)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (733:733:733)) + (PORT datab (1390:1390:1390) (1430:1430:1430)) + (PORT datac (1293:1293:1293) (1288:1288:1288)) + (PORT datad (1156:1156:1156) (1232:1232:1232)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1193:1193:1193)) + (PORT datab (1112:1112:1112) (1135:1135:1135)) + (PORT datac (1515:1515:1515) (1580:1580:1580)) + (PORT datad (1144:1144:1144) (1172:1172:1172)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1379:1379:1379) (1422:1422:1422)) + (PORT datac (633:633:633) (695:695:695)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1286:1286:1286)) + (PORT datab (1246:1246:1246) (1298:1298:1298)) + (PORT datac (817:817:817) (830:830:830)) + (PORT datad (1062:1062:1062) (1106:1106:1106)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (910:910:910) (932:932:932)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1441:1441:1441)) + (PORT datab (1524:1524:1524) (1615:1615:1615)) + (PORT datac (846:846:846) (871:871:871)) + (PORT datad (1023:1023:1023) (1080:1080:1080)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1127:1127:1127)) + (PORT datab (220:220:220) (257:257:257)) + (PORT datac (1412:1412:1412) (1455:1455:1455)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (969:969:969)) + (PORT datab (680:680:680) (699:699:699)) + (PORT datac (589:589:589) (604:604:604)) + (PORT datad (643:643:643) (656:656:656)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (592:592:592) (599:599:599)) + (PORT datad (185:185:185) (217:217:217)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (585:585:585)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (768:768:768) (802:802:802)) + (PORT datad (847:847:847) (869:869:869)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1132:1132:1132)) + (PORT datab (748:748:748) (801:801:801)) + (PORT datac (1727:1727:1727) (1785:1785:1785)) + (PORT datad (1374:1374:1374) (1390:1390:1390)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (2073:2073:2073) (2186:2186:2186)) + (PORT datab (1400:1400:1400) (1425:1425:1425)) + (PORT datac (1772:1772:1772) (1899:1899:1899)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1132:1132:1132)) + (PORT datab (962:962:962) (975:975:975)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (712:712:712) (762:762:762)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (663:663:663)) + (PORT datab (1519:1519:1519) (1611:1611:1611)) + (PORT datac (934:934:934) (944:944:944)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1868:1868:1868)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (938:938:938) (1003:1003:1003)) + (PORT datad (1024:1024:1024) (1086:1086:1086)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1519:1519:1519) (1613:1613:1613)) + (PORT datac (1729:1729:1729) (1823:1823:1823)) + (PORT datad (853:853:853) (863:863:863)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (634:634:634)) + (PORT datab (1456:1456:1456) (1500:1500:1500)) + (PORT datac (941:941:941) (1004:1004:1004)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (908:908:908) (948:948:948)) + (PORT datad (583:583:583) (620:620:620)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (914:914:914)) + (PORT datab (1176:1176:1176) (1233:1233:1233)) + (PORT datac (1349:1349:1349) (1376:1376:1376)) + (PORT datad (1340:1340:1340) (1388:1388:1388)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14212,42 +9090,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (2352:2352:2352) (2460:2460:2460)) - (PORT datab (979:979:979) (1005:1005:1005)) - (PORT datac (1863:1863:1863) (1892:1892:1892)) - (PORT datad (1775:1775:1775) (1890:1890:1890)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1179:1179:1179) (1246:1246:1246)) - (PORT datad (1693:1693:1693) (1817:1817:1817)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (2042:2042:2042) (2132:2132:2132)) - (PORT datab (661:661:661) (679:679:679)) - (PORT datac (861:861:861) (893:893:893)) - (PORT datad (666:666:666) (723:723:723)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (945:945:945) (1008:1008:1008)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (923:923:923) (969:969:969)) + (PORT datad (224:224:224) (265:265:265)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14256,94 +9106,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~17) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (859:859:859) (874:874:874)) - (PORT datad (340:340:340) (363:363:363)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (866:866:866) (892:892:892)) + (PORT datab (1557:1557:1557) (1673:1673:1673)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1279:1279:1279) (1383:1383:1383)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (1882:1882:1882) (2069:2069:2069)) - (PORT datab (1503:1503:1503) (1598:1598:1598)) - (PORT datac (1200:1200:1200) (1277:1277:1277)) - (PORT datad (613:613:613) (652:652:652)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (591:591:591) (609:609:609)) - (PORT datad (832:832:832) (884:884:884)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1622:1622:1622) (1656:1656:1656)) - (PORT datab (1011:1011:1011) (1122:1122:1122)) - (PORT datac (2246:2246:2246) (2401:2401:2401)) - (PORT datad (640:640:640) (657:657:657)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (399:399:399)) - (PORT datab (886:886:886) (926:926:926)) - (PORT datac (2213:2213:2213) (2293:2293:2293)) - (PORT datad (1158:1158:1158) (1220:1220:1220)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (649:649:649)) - (PORT datab (610:610:610) (643:643:643)) - (PORT datac (1089:1089:1089) (1103:1103:1103)) - (PORT datad (1426:1426:1426) (1497:1497:1497)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (2047:2047:2047) (2141:2141:2141)) + (PORT datab (705:705:705) (759:759:759)) + (PORT datac (1941:1941:1941) (1985:1985:1985)) + (PORT datad (1314:1314:1314) (1347:1347:1347)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14352,16 +9138,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (970:970:970) (1047:1047:1047)) - (PORT datab (1328:1328:1328) (1357:1357:1357)) - (PORT datac (1395:1395:1395) (1452:1452:1452)) - (PORT datad (180:180:180) (211:211:211)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (254:254:254) (313:313:313)) + (PORT datab (625:625:625) (654:654:654)) + (PORT datac (1912:1912:1912) (1997:1997:1997)) + (PORT datad (1653:1653:1653) (1681:1681:1681)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1726:1726:1726)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (882:882:882) (914:914:914)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (674:674:674)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (189:189:189) (233:233:233)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1106:1106:1106)) + (PORT datab (1192:1192:1192) (1252:1252:1252)) + (PORT datac (893:893:893) (936:936:936)) + (PORT datad (1452:1452:1452) (1569:1569:1569)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14371,1242 +9205,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) (DELAY (ABSOLUTE - (PORT dataa (1158:1158:1158) (1195:1195:1195)) - (PORT datab (908:908:908) (926:926:926)) - (PORT datac (616:616:616) (647:647:647)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1546:1546:1546)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (953:953:953)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (606:606:606) (625:625:625)) - (PORT datad (1433:1433:1433) (1446:1446:1446)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (955:955:955)) - (PORT datab (968:968:968) (1012:1012:1012)) - (PORT datac (766:766:766) (778:778:778)) - (PORT datad (180:180:180) (210:210:210)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (661:661:661)) - (PORT datab (1887:1887:1887) (1914:1914:1914)) - (PORT datac (951:951:951) (996:996:996)) - (PORT datad (1256:1256:1256) (1314:1314:1314)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (574:574:574) (617:617:617)) - (PORT datad (1077:1077:1077) (1104:1104:1104)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (396:396:396)) - (PORT datab (632:632:632) (663:663:663)) - (PORT datac (612:612:612) (624:624:624)) - (PORT datad (624:624:624) (639:639:639)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (950:950:950)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (1118:1118:1118) (1174:1174:1174)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (904:904:904)) - (PORT datab (2215:2215:2215) (2381:2381:2381)) - (PORT datac (1232:1232:1232) (1373:1373:1373)) - (PORT datad (2798:2798:2798) (2994:2994:2994)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (638:638:638)) - (PORT datab (687:687:687) (717:717:717)) - (PORT datac (934:934:934) (966:966:966)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (631:631:631)) - (PORT datac (895:895:895) (905:905:905)) - (PORT datad (841:841:841) (853:853:853)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1988:1988:1988) (2068:2068:2068)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datad (869:869:869) (931:931:931)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1589:1589:1589) (1566:1566:1566)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1475:1475:1475)) - (PORT datab (1193:1193:1193) (1241:1241:1241)) - (PORT datac (846:846:846) (891:891:891)) - (PORT datad (1379:1379:1379) (1380:1380:1380)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT dataa (1682:1682:1682) (1803:1803:1803)) - (PORT datac (632:632:632) (678:678:678)) - (PORT datad (1446:1446:1446) (1513:1513:1513)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1183:1183:1183) (1262:1262:1262)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1554:1554:1554)) - (PORT datab (656:656:656) (705:705:705)) - (PORT datad (1630:1630:1630) (1739:1739:1739)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT dataa (1285:1285:1285) (1362:1362:1362)) - (PORT datab (897:897:897) (934:934:934)) - (PORT datac (1431:1431:1431) (1496:1496:1496)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1464:1464:1464) (1531:1531:1531)) - (PORT datac (876:876:876) (924:924:924)) - (PORT datad (1249:1249:1249) (1317:1317:1317)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1014:1014:1014) (1056:1056:1056)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1381:1381:1381)) - (PORT datab (894:894:894) (929:929:929)) - (PORT datac (1433:1433:1433) (1499:1499:1499)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1016:1016:1016) (1059:1059:1059)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1468:1468:1468) (1530:1530:1530)) - (PORT datac (879:879:879) (925:925:925)) - (PORT datad (1241:1241:1241) (1311:1311:1311)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (977:977:977)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (893:893:893) (937:937:937)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (842:842:842)) - (PORT datab (249:249:249) (332:332:332)) - (PORT datac (787:787:787) (792:792:792)) - (PORT datad (199:199:199) (237:237:237)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1462:1462:1462) (1531:1531:1531)) - (PORT datac (860:860:860) (902:902:902)) - (PORT datad (1246:1246:1246) (1318:1318:1318)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (841:841:841)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datac (787:787:787) (791:791:791)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1466:1466:1466) (1528:1528:1528)) - (PORT datac (844:844:844) (888:888:888)) - (PORT datad (1241:1241:1241) (1313:1313:1313)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1468:1468:1468) (1532:1532:1532)) - (PORT datac (861:861:861) (900:900:900)) - (PORT datad (1254:1254:1254) (1327:1327:1327)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1423:1423:1423) (1482:1482:1482)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1465:1465:1465) (1532:1532:1532)) - (PORT datac (841:841:841) (888:888:888)) - (PORT datad (1245:1245:1245) (1318:1318:1318)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1421:1421:1421) (1478:1478:1478)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (1057:1057:1057)) - (PORT datab (966:966:966) (1013:1013:1013)) - (PORT datad (357:357:357) (414:414:414)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (854:854:854) (911:911:911)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1527:1527:1527)) - (PORT datab (1198:1198:1198) (1246:1246:1246)) - (PORT datac (1748:1748:1748) (1867:1867:1867)) - (PORT datad (1449:1449:1449) (1522:1522:1522)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (1615:1615:1615) (1723:1723:1723)) - (PORT datac (1085:1085:1085) (1141:1141:1141)) - (PORT datad (346:346:346) (373:373:373)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (1612:1612:1612) (1721:1721:1721)) - (PORT datac (1083:1083:1083) (1140:1140:1140)) - (PORT datad (343:343:343) (371:371:371)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datab (1611:1611:1611) (1718:1718:1718)) - (PORT datad (1731:1731:1731) (1794:1794:1794)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1529:1529:1529)) - (PORT datab (1784:1784:1784) (1902:1902:1902)) - (PORT datac (337:337:337) (362:362:362)) - (PORT datad (1160:1160:1160) (1205:1205:1205)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1411:1411:1411) (1470:1470:1470)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT datab (1610:1610:1610) (1716:1716:1716)) - (PORT datac (1084:1084:1084) (1136:1136:1136)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1497:1497:1497) (1513:1513:1513)) - (PORT datab (376:376:376) (408:408:408)) - (PORT datac (1753:1753:1753) (1874:1874:1874)) - (PORT datad (1153:1153:1153) (1198:1198:1198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (552:552:552)) - (PORT datab (498:498:498) (554:554:554)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (599:599:599) (636:636:636)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1476:1476:1476)) - (PORT datab (1193:1193:1193) (1241:1241:1241)) - (PORT datac (341:341:341) (367:367:367)) - (PORT datad (1380:1380:1380) (1380:1380:1380)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1514:1514:1514) (1527:1527:1527)) - (PORT datab (371:371:371) (402:402:402)) - (PORT datac (1398:1398:1398) (1441:1441:1441)) - (PORT datad (1158:1158:1158) (1204:1204:1204)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (706:706:706)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2055:2055:2055) (2081:2081:2081)) - (PORT datab (1404:1404:1404) (1511:1511:1511)) - (PORT datac (2090:2090:2090) (2260:2260:2260)) - (PORT datad (875:875:875) (901:901:901)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1073:1073:1073)) - (PORT datab (1268:1268:1268) (1350:1350:1350)) - (PORT datac (1926:1926:1926) (1930:1930:1930)) - (PORT datad (363:363:363) (385:385:385)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datac (588:588:588) (636:636:636)) - (PORT datad (822:822:822) (847:847:847)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (721:721:721)) - (PORT datab (218:218:218) (264:264:264)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (860:860:860) (875:875:875)) - (PORT datad (642:642:642) (659:659:659)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (964:964:964) (1041:1041:1041)) - (PORT datac (916:916:916) (968:968:968)) - (PORT datad (1214:1214:1214) (1282:1282:1282)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (950:950:950) (983:983:983)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1034:1034:1034)) - (PORT datac (915:915:915) (966:966:966)) - (PORT datad (1213:1213:1213) (1277:1277:1277)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (959:959:959) (999:999:999)) - (PORT datad (880:880:880) (921:921:921)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1526:1526:1526)) - (PORT datab (1196:1196:1196) (1249:1249:1249)) - (PORT datac (341:341:341) (369:369:369)) - (PORT datad (582:582:582) (643:643:643)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1526:1526:1526)) - (PORT datab (611:611:611) (683:683:683)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (1156:1156:1156) (1205:1205:1205)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1439:1439:1439) (1498:1498:1498)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1506:1506:1506) (1523:1523:1523)) - (PORT datab (609:609:609) (680:680:680)) - (PORT datac (340:340:340) (366:366:366)) - (PORT datad (1150:1150:1150) (1203:1203:1203)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1444:1444:1444) (1503:1503:1503)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1511:1511:1511) (1527:1527:1527)) - (PORT datab (1197:1197:1197) (1246:1246:1246)) - (PORT datac (341:341:341) (368:368:368)) - (PORT datad (582:582:582) (639:639:639)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (705:705:705)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (626:626:626) (663:663:663)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1429:1429:1429) (1476:1476:1476)) - (PORT datab (1197:1197:1197) (1247:1247:1247)) - (PORT datac (850:850:850) (893:893:893)) - (PORT datad (1383:1383:1383) (1381:1381:1381)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1488:1488:1488) (1561:1561:1561)) - (PORT datab (902:902:902) (929:929:929)) - (PORT datad (1637:1637:1637) (1751:1751:1751)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1609:1609:1609) (1656:1656:1656)) - (PORT datac (887:887:887) (932:932:932)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1674:1674:1674) (1748:1748:1748)) - (PORT datab (392:392:392) (418:418:418)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (886:886:886) (902:902:902)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1558:1558:1558)) - (PORT datab (908:908:908) (935:935:935)) - (PORT datad (1629:1629:1629) (1743:1743:1743)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1414:1414:1414) (1474:1474:1474)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1031:1031:1031)) - (PORT datab (1291:1291:1291) (1331:1331:1331)) - (PORT datad (874:874:874) (906:906:906)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (1320:1320:1320) (1335:1335:1335)) - (PORT datac (335:335:335) (358:358:358)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (672:672:672)) - (PORT datab (555:555:555) (576:576:576)) - (PORT datac (825:825:825) (840:840:840)) - (PORT datad (1032:1032:1032) (1101:1101:1101)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (385:385:385)) - (PORT datab (1380:1380:1380) (1398:1398:1398)) - (PORT datac (1123:1123:1123) (1180:1180:1180)) - (PORT datad (622:622:622) (640:640:640)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (732:732:732)) - (PORT datab (891:891:891) (930:930:930)) - (PORT datac (1215:1215:1215) (1263:1263:1263)) - (PORT datad (560:560:560) (577:577:577)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) + (PORT dataa (1211:1211:1211) (1327:1327:1327)) (PORT datab (875:875:875) (893:893:893)) - (PORT datac (344:344:344) (372:372:372)) - (PORT datad (1110:1110:1110) (1122:1122:1122)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (615:615:615) (641:641:641)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (593:593:593)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (962:962:962)) - (PORT datab (1357:1357:1357) (1408:1408:1408)) - (PORT datac (1375:1375:1375) (1378:1378:1378)) - (PORT datad (793:793:793) (845:845:845)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (658:658:658)) - (PORT datab (1361:1361:1361) (1409:1409:1409)) - (PORT datac (412:412:412) (449:449:449)) - (PORT datad (209:209:209) (242:242:242)) + (PORT datac (2173:2173:2173) (2262:2262:2262)) + (PORT datad (1470:1470:1470) (1572:1572:1572)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -15616,16 +9218,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) (DELAY (ABSOLUTE - (PORT dataa (1495:1495:1495) (1563:1563:1563)) - (PORT datab (841:841:841) (869:869:869)) - (PORT datac (809:809:809) (891:891:891)) - (PORT datad (837:837:837) (886:886:886)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (646:646:646) (661:661:661)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1005:1005:1005) (1030:1030:1030)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -15635,13 +9237,13 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (994:994:994)) - (PORT datab (1403:1403:1403) (1460:1460:1460)) - (PORT datac (1085:1085:1085) (1138:1138:1138)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1534:1534:1534) (1584:1584:1584)) + (PORT datab (896:896:896) (955:955:955)) + (PORT datac (1366:1366:1366) (1364:1364:1364)) + (PORT datad (372:372:372) (401:401:401)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -15651,12 +9253,12 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) (DELAY (ABSOLUTE - (PORT dataa (1124:1124:1124) (1165:1165:1165)) - (PORT datab (1867:1867:1867) (1942:1942:1942)) - (PORT datac (842:842:842) (905:905:905)) - (PORT datad (626:626:626) (662:662:662)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1234:1234:1234) (1295:1295:1295)) + (PORT datab (1382:1382:1382) (1435:1435:1435)) + (PORT datac (1798:1798:1798) (1854:1854:1854)) + (PORT datad (371:371:371) (401:401:401)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15667,11 +9269,11 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) (DELAY (ABSOLUTE - (PORT dataa (1190:1190:1190) (1209:1209:1209)) - (PORT datab (1474:1474:1474) (1514:1514:1514)) - (PORT datac (1094:1094:1094) (1102:1102:1102)) - (PORT datad (1208:1208:1208) (1297:1297:1297)) - (IOPATH dataa combout (337:337:337) (338:338:338)) + (PORT dataa (1245:1245:1245) (1308:1308:1308)) + (PORT datab (940:940:940) (1014:1014:1014)) + (PORT datac (1966:1966:1966) (2013:2013:2013)) + (PORT datad (636:636:636) (685:685:685)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -15683,12 +9285,12 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) (DELAY (ABSOLUTE - (PORT dataa (1236:1236:1236) (1289:1289:1289)) - (PORT datab (1163:1163:1163) (1196:1196:1196)) - (PORT datac (917:917:917) (959:959:959)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (665:665:665) (722:722:722)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1692:1692:1692) (1745:1745:1745)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15699,1204 +9301,10 @@ (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) (DELAY (ABSOLUTE - (PORT dataa (854:854:854) (896:896:896)) - (PORT datab (814:814:814) (835:835:835)) - (PORT datac (1604:1604:1604) (1624:1624:1624)) - (PORT datad (1091:1091:1091) (1104:1104:1104)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1081:1081:1081)) - (PORT datab (643:643:643) (686:686:686)) - (PORT datac (880:880:880) (916:916:916)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1506:1506:1506) (1583:1583:1583)) - (PORT datab (645:645:645) (676:676:676)) - (PORT datac (924:924:924) (965:965:965)) - (PORT datad (1191:1191:1191) (1244:1244:1244)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1363:1363:1363) (1381:1381:1381)) - (PORT datad (584:584:584) (632:632:632)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1468:1468:1468)) - (PORT datab (376:376:376) (404:404:404)) - (PORT datac (631:631:631) (672:672:672)) - (PORT datad (695:695:695) (746:746:746)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1011:1011:1011)) - (PORT datab (845:845:845) (882:882:882)) - (PORT datac (544:544:544) (563:563:563)) - (PORT datad (1121:1121:1121) (1121:1121:1121)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1168:1168:1168)) - (PORT datab (927:927:927) (955:955:955)) - (PORT datac (1207:1207:1207) (1250:1250:1250)) - (PORT datad (1220:1220:1220) (1269:1269:1269)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1132:1132:1132)) - (PORT datab (613:613:613) (653:653:653)) - (PORT datac (186:186:186) (227:227:227)) - (PORT datad (836:836:836) (844:844:844)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT datab (2020:2020:2020) (2146:2146:2146)) - (PORT datac (1954:1954:1954) (2061:2061:2061)) - (PORT datad (1620:1620:1620) (1793:1793:1793)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1426:1426:1426)) - (PORT datab (1201:1201:1201) (1270:1270:1270)) - (PORT datac (1175:1175:1175) (1230:1230:1230)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datac (842:842:842) (866:866:866)) - (PORT datad (625:625:625) (636:636:636)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (592:592:592)) - (PORT datab (387:387:387) (415:415:415)) - (PORT datac (1088:1088:1088) (1123:1123:1123)) - (PORT datad (809:809:809) (841:841:841)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1660:1660:1660)) - (PORT datab (1645:1645:1645) (1688:1688:1688)) - (PORT datac (1674:1674:1674) (1745:1745:1745)) - (PORT datad (1153:1153:1153) (1190:1190:1190)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (717:717:717)) - (PORT datab (1418:1418:1418) (1466:1466:1466)) - (PORT datac (927:927:927) (1002:1002:1002)) - (PORT datad (320:320:320) (342:342:342)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (453:453:453)) - (PORT datab (381:381:381) (414:414:414)) - (PORT datac (948:948:948) (997:997:997)) - (PORT datad (902:902:902) (929:929:929)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (924:924:924)) - (PORT datab (1172:1172:1172) (1217:1217:1217)) - (PORT datad (586:586:586) (617:617:617)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (665:665:665)) - (PORT datab (400:400:400) (448:448:448)) - (PORT datac (903:903:903) (950:950:950)) - (PORT datad (1154:1154:1154) (1178:1178:1178)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1171:1171:1171)) - (PORT datad (1850:1850:1850) (1892:1892:1892)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1190:1190:1190)) - (PORT datab (1154:1154:1154) (1186:1186:1186)) - (PORT datac (1365:1365:1365) (1404:1404:1404)) - (PORT datad (1108:1108:1108) (1127:1127:1127)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (413:413:413)) - (PORT datab (1708:1708:1708) (1765:1765:1765)) - (PORT datac (1580:1580:1580) (1686:1686:1686)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (1414:1414:1414) (1421:1421:1421)) - (PORT datad (1852:1852:1852) (1893:1893:1893)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1191:1191:1191)) - (PORT datab (1155:1155:1155) (1186:1186:1186)) - (PORT datac (1366:1366:1366) (1405:1405:1405)) - (PORT datad (826:826:826) (842:842:842)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (681:681:681) (708:708:708)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (413:413:413)) - (PORT datab (1709:1709:1709) (1766:1766:1766)) - (PORT datac (1579:1579:1579) (1681:1681:1681)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (325:325:325)) - (PORT datab (1404:1404:1404) (1519:1519:1519)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1374:1374:1374)) - (PORT datac (1019:1019:1019) (1043:1043:1043)) - (PORT datad (1368:1368:1368) (1412:1412:1412)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1174:1174:1174)) - (PORT datab (371:371:371) (403:403:403)) - (PORT datad (1851:1851:1851) (1894:1894:1894)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1369:1369:1369)) - (PORT datac (1018:1018:1018) (1041:1041:1041)) - (PORT datad (1364:1364:1364) (1407:1407:1407)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1699:1699:1699) (1727:1727:1727)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (905:905:905) (954:954:954)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1172:1172:1172)) - (PORT datab (368:368:368) (402:402:402)) - (PORT datad (1853:1853:1853) (1893:1893:1893)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (663:663:663)) - (PORT datab (940:940:940) (1000:1000:1000)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (1281:1281:1281) (1368:1368:1368)) - (PORT datab (1005:1005:1005) (1055:1055:1055)) - (PORT datac (915:915:915) (968:968:968)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1394:1394:1394)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (1112:1112:1112) (1132:1132:1132)) - (PORT datad (596:596:596) (654:654:654)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (838:838:838)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (859:859:859) (867:867:867)) - (PORT datad (1351:1351:1351) (1364:1364:1364)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (970:970:970) (999:999:999)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1256:1256:1256)) - (PORT datab (676:676:676) (714:714:714)) - (PORT datad (959:959:959) (992:992:992)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (1275:1275:1275) (1362:1362:1362)) - (PORT datab (1010:1010:1010) (1056:1056:1056)) - (PORT datac (916:916:916) (969:969:969)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (969:969:969) (1001:1001:1001)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (197:197:197) (236:236:236)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1527:1527:1527)) - (PORT datab (1196:1196:1196) (1250:1250:1250)) - (PORT datac (1752:1752:1752) (1873:1873:1873)) - (PORT datad (543:543:543) (551:551:551)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1136:1136:1136) (1158:1158:1158)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1742:1742:1742) (1856:1856:1856)) - (PORT datab (1391:1391:1391) (1393:1393:1393)) - (PORT datac (1113:1113:1113) (1130:1130:1130)) - (PORT datad (1127:1127:1127) (1128:1128:1128)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1151:1151:1151) (1170:1170:1170)) - (PORT datab (624:624:624) (692:692:692)) - (PORT datac (1345:1345:1345) (1352:1352:1352)) - (PORT datad (823:823:823) (830:830:830)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1134:1134:1134) (1155:1155:1155)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1395:1395:1395)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (1113:1113:1113) (1134:1134:1134)) - (PORT datad (597:597:597) (655:655:655)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datad (211:211:211) (244:244:244)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (696:696:696)) - (PORT datab (660:660:660) (673:673:673)) - (PORT datac (762:762:762) (771:771:771)) - (PORT datad (596:596:596) (645:645:645)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT dataa (1296:1296:1296) (1377:1377:1377)) - (PORT datac (840:840:840) (891:891:891)) - (PORT datad (1367:1367:1367) (1411:1411:1411)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1381:1381:1381)) - (PORT datac (861:861:861) (899:899:899)) - (PORT datad (1371:1371:1371) (1413:1413:1413)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1380:1380:1380)) - (PORT datac (861:861:861) (899:899:899)) - (PORT datad (1371:1371:1371) (1413:1413:1413)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1201:1201:1201) (1221:1221:1221)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (676:676:676) (712:712:712)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1381:1381:1381)) - (PORT datac (841:841:841) (888:888:888)) - (PORT datad (1369:1369:1369) (1414:1414:1414)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (449:449:449) (481:481:481)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1109:1109:1109) (1118:1118:1118)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1107:1107:1107) (1116:1116:1116)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (312:312:312)) - (PORT datab (1080:1080:1080) (1119:1119:1119)) - (PORT datad (362:362:362) (415:415:415)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (701:701:701)) - (PORT datab (642:642:642) (676:676:676)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1879:1879:1879) (1937:1937:1937)) - (PORT datab (1816:1816:1816) (1903:1903:1903)) - (PORT datac (209:209:209) (252:252:252)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (892:892:892)) - (PORT datab (878:878:878) (922:922:922)) - (PORT datac (538:538:538) (540:540:540)) - (PORT datad (617:617:617) (645:645:645)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1222:1222:1222)) - (PORT datab (1045:1045:1045) (1100:1100:1100)) - (PORT datac (695:695:695) (747:747:747)) - (PORT datad (1116:1116:1116) (1134:1134:1134)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1256:1256:1256)) - (PORT datab (677:677:677) (742:742:742)) - (PORT datac (546:546:546) (556:556:556)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (548:548:548)) - (PORT datab (646:646:646) (698:698:698)) - (PORT datac (641:641:641) (670:670:670)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1518:1518:1518)) - (PORT datab (576:576:576) (596:596:596)) - (PORT datad (642:642:642) (669:669:669)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (460:460:460)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (607:607:607) (629:629:629)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1052:1052:1052)) - (PORT datab (442:442:442) (513:513:513)) - (PORT datac (1170:1170:1170) (1219:1219:1219)) - (PORT datad (423:423:423) (496:496:496)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1867:1867:1867)) - (PORT datab (1235:1235:1235) (1271:1271:1271)) - (PORT datac (1201:1201:1201) (1255:1255:1255)) - (PORT datad (985:985:985) (1038:1038:1038)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (910:910:910) (962:962:962)) - (PORT datad (182:182:182) (214:214:214)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1762:1762:1762) (1747:1747:1747)) - (PORT datab (1212:1212:1212) (1248:1248:1248)) - (PORT datac (634:634:634) (657:657:657)) - (PORT datad (825:825:825) (876:876:876)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (685:685:685)) - (PORT datab (647:647:647) (666:666:666)) - (PORT datad (880:880:880) (928:928:928)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (963:963:963)) - (PORT datab (1141:1141:1141) (1159:1159:1159)) - (PORT datac (1626:1626:1626) (1670:1670:1670)) - (PORT datad (878:878:878) (910:910:910)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (371:371:371)) - (PORT datab (915:915:915) (950:950:950)) - (PORT datac (1075:1075:1075) (1082:1082:1082)) - (PORT datad (1088:1088:1088) (1108:1108:1108)) + (PORT dataa (601:601:601) (613:613:613)) + (PORT datab (1161:1161:1161) (1190:1190:1190)) + (PORT datac (1554:1554:1554) (1560:1560:1560)) + (PORT datad (518:518:518) (534:534:534)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16906,31 +9314,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (INSTANCE z80_\|alu_\|db\[7\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1162:1162:1162) (1199:1199:1199)) - (PORT datab (826:826:826) (911:911:911)) - (PORT datac (1135:1135:1135) (1158:1158:1158)) - (PORT datad (788:788:788) (836:836:836)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1136:1136:1136)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (997:997:997) (1023:1023:1023)) - (PORT datad (886:886:886) (940:940:940)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (943:943:943) (988:988:988)) + (PORT datac (909:909:909) (961:961:961)) + (PORT datad (656:656:656) (703:703:703)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16938,205 +9328,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (INSTANCE z80_\|address_latch_\|abusz\[14\]) (DELAY (ABSOLUTE - (PORT dataa (1004:1004:1004) (1084:1084:1084)) - (PORT datab (954:954:954) (1049:1049:1049)) - (PORT datac (1094:1094:1094) (1101:1101:1101)) - (PORT datad (195:195:195) (232:232:232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (947:947:947)) - (PORT datab (837:837:837) (839:839:839)) - (PORT datac (413:413:413) (484:484:484)) - (PORT datad (636:636:636) (716:716:716)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1162:1162:1162)) - (PORT datab (392:392:392) (471:471:471)) - (PORT datac (1098:1098:1098) (1115:1115:1115)) - (PORT datad (640:640:640) (718:718:718)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (636:636:636)) - (PORT datab (1622:1622:1622) (1684:1684:1684)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (862:862:862) (899:899:899)) + (PORT dataa (678:678:678) (712:712:712)) + (PORT datac (629:629:629) (646:646:646)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT dataa (728:728:728) (795:795:795)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (983:983:983) (1020:1020:1020)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1469:1469:1469) (1520:1520:1520)) - (PORT datab (636:636:636) (670:670:670)) - (PORT datac (1209:1209:1209) (1261:1261:1261)) - (PORT datad (653:653:653) (675:675:675)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~25) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (453:453:453)) - (PORT datab (293:293:293) (385:385:385)) - (PORT datad (251:251:251) (325:325:325)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (700:700:700)) - (PORT datab (1035:1035:1035) (1050:1050:1050)) - (PORT datac (1203:1203:1203) (1278:1278:1278)) - (PORT datad (2028:2028:2028) (2053:2053:2053)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1105:1105:1105)) - (PORT datab (783:783:783) (893:893:893)) - (PORT datac (1472:1472:1472) (1539:1539:1539)) - (PORT datad (893:893:893) (943:943:943)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (830:830:830)) - (PORT datab (2475:2475:2475) (2536:2536:2536)) - (PORT datac (1334:1334:1334) (1380:1380:1380)) - (PORT datad (707:707:707) (810:810:810)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (867:867:867)) - (PORT datab (655:655:655) (692:692:692)) - (PORT datac (845:845:845) (859:859:859)) - (PORT datad (831:831:831) (863:863:863)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1085:1085:1085)) - (PORT datab (899:899:899) (926:926:926)) - (PORT datac (925:925:925) (1014:1014:1014)) - (PORT datad (194:194:194) (228:228:228)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (926:926:926) (999:999:999)) + (PORT datab (1496:1496:1496) (1557:1557:1557)) + (PORT datac (791:791:791) (799:799:799)) + (PORT datad (921:921:921) (982:982:982)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17144,93 +9356,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (INSTANCE z80_\|execute_\|fMRead\~10) (DELAY (ABSOLUTE - (PORT dataa (1046:1046:1046) (1122:1122:1122)) - (PORT datab (196:196:196) (234:234:234)) + (PORT dataa (603:603:603) (632:632:632)) + (PORT datab (1000:1000:1000) (1048:1048:1048)) + (PORT datac (711:711:711) (758:758:758)) + (PORT datad (541:541:541) (556:556:556)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (795:795:795)) + (PORT datab (1000:1000:1000) (1044:1044:1044)) + (PORT datac (635:635:635) (680:680:680)) (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1258:1258:1258)) - (PORT datab (1956:1956:1956) (2026:2026:2026)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (575:575:575) (577:577:577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1423:1423:1423) (1498:1498:1498)) - (PORT datab (1500:1500:1500) (1572:1572:1572)) - (PORT datac (866:866:866) (926:926:926)) - (PORT datad (1174:1174:1174) (1212:1212:1212)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1205:1205:1205)) - (PORT datab (873:873:873) (884:884:884)) - (PORT datac (670:670:670) (726:726:726)) - (PORT datad (1092:1092:1092) (1114:1114:1114)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1724:1724:1724) (1770:1770:1770)) - (PORT datab (1956:1956:1956) (2027:2027:2027)) - (PORT datac (609:609:609) (664:664:664)) - (PORT datad (828:828:828) (846:846:846)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1195:1195:1195) (1241:1241:1241)) - (PORT datab (704:704:704) (759:759:759)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (683:683:683) (746:746:746)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17238,47 +9388,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (INSTANCE z80_\|execute_\|fMRead\~9) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (614:614:614) (645:645:645)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1261:1261:1261) (1306:1306:1306)) + (PORT datab (999:999:999) (1045:1045:1045)) + (PORT datac (1076:1076:1076) (1084:1084:1084)) + (PORT datad (1108:1108:1108) (1123:1123:1123)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) (DELAY (ABSOLUTE - (PORT dataa (2201:2201:2201) (2281:2281:2281)) - (PORT datab (1459:1459:1459) (1512:1512:1512)) - (PORT datac (730:730:730) (781:781:781)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (981:981:981) (1046:1046:1046)) + (PORT datac (180:180:180) (218:218:218)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~27) (DELAY (ABSOLUTE - (PORT dataa (1006:1006:1006) (1082:1082:1082)) - (PORT datab (957:957:957) (1052:1052:1052)) - (PORT datac (599:599:599) (626:626:626)) - (PORT datad (1185:1185:1185) (1214:1214:1214)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (1441:1441:1441) (1473:1473:1473)) + (PORT datab (923:923:923) (968:968:968)) + (PORT datac (652:652:652) (754:754:754)) + (PORT datad (1794:1794:1794) (1909:1909:1909)) + (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT datab (1572:1572:1572) (1702:1702:1702)) + (PORT datac (1412:1412:1412) (1479:1479:1479)) + (PORT datad (1138:1138:1138) (1156:1156:1156)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17286,705 +9448,65 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (636:636:636)) - (PORT datab (580:580:580) (603:603:603)) - (PORT datac (2168:2168:2168) (2243:2243:2243)) - (PORT datad (533:533:533) (549:549:549)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1199:1199:1199) (1235:1235:1235)) + (PORT datab (644:644:644) (659:659:659)) + (PORT datac (856:856:856) (909:909:909)) + (PORT datad (1134:1134:1134) (1157:1157:1157)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (955:955:955)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (1494:1494:1494) (1581:1581:1581)) + (PORT datac (823:823:823) (866:866:866)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (884:884:884)) + (PORT datad (829:829:829) (844:844:844)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) (DELAY (ABSOLUTE - (PORT dataa (1375:1375:1375) (1410:1410:1410)) - (PORT datab (757:757:757) (812:812:812)) - (PORT datac (2169:2169:2169) (2240:2240:2240)) - (PORT datad (1276:1276:1276) (1310:1310:1310)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (989:989:989) (1068:1068:1068)) - (PORT datab (1342:1342:1342) (1431:1431:1431)) - (PORT datac (728:728:728) (781:781:781)) - (PORT datad (915:915:915) (953:953:953)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~20) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) + (PORT dataa (857:857:857) (876:876:876)) (PORT datab (236:236:236) (281:281:281)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (899:899:899)) - (PORT datab (777:777:777) (885:885:885)) - (PORT datac (628:628:628) (674:674:674)) - (PORT datad (707:707:707) (811:811:811)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~15) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (642:642:642)) - (PORT datab (744:744:744) (781:781:781)) - (PORT datac (1960:1960:1960) (2018:2018:2018)) - (PORT datad (808:808:808) (821:821:821)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~16) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (853:853:853)) - (PORT datab (779:779:779) (885:885:885)) - (PORT datac (754:754:754) (860:860:860)) - (PORT datad (1842:1842:1842) (1891:1891:1891)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~21) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (720:720:720)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (525:525:525) (536:536:536)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1178:1178:1178)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (809:809:809) (833:833:833)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1655:1655:1655) (1672:1672:1672)) - (PORT datab (1989:1989:1989) (2051:2051:2051)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (1449:1449:1449) (1444:1444:1444)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT datab (777:777:777) (881:881:881)) - (PORT datac (751:751:751) (853:853:853)) - (PORT datad (1014:1014:1014) (1034:1034:1034)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (725:725:725) (827:827:827)) - (PORT datab (2350:2350:2350) (2475:2475:2475)) - (PORT datac (751:751:751) (853:853:853)) - (PORT datad (649:649:649) (694:694:694)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~22) - (DELAY - (ABSOLUTE - (PORT datab (1154:1154:1154) (1254:1254:1254)) - (PORT datac (908:908:908) (984:984:984)) - (PORT datad (695:695:695) (796:796:796)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~23) - (DELAY - (ABSOLUTE - (PORT dataa (2509:2509:2509) (2581:2581:2581)) - (PORT datab (930:930:930) (981:981:981)) - (PORT datac (1138:1138:1138) (1158:1158:1158)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (935:935:935)) - (PORT datab (776:776:776) (881:881:881)) - (PORT datac (751:751:751) (854:854:854)) - (PORT datad (563:563:563) (572:572:572)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~24) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (240:240:240)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (207:207:207) (237:237:237)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT datab (390:390:390) (430:430:430)) - (PORT datad (887:887:887) (895:895:895)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1104:1104:1104)) - (PORT datab (452:452:452) (487:487:487)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1994:1994:1994) (2001:2001:2001)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1075:1075:1075)) - (PORT datab (1343:1343:1343) (1437:1437:1437)) - (PORT datac (2168:2168:2168) (2246:2246:2246)) - (PORT datad (914:914:914) (958:958:958)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (389:389:389)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1584:1584:1584) (1620:1620:1620)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (726:726:726)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (882:882:882) (905:905:905)) - (PORT datad (1416:1416:1416) (1450:1450:1450)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1449:1449:1449) (1484:1484:1484)) - (PORT datac (344:344:344) (368:368:368)) - (PORT datad (215:215:215) (248:248:248)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (899:899:899)) - (PORT datab (2351:2351:2351) (2480:2480:2480)) - (PORT datac (628:628:628) (672:672:672)) - (PORT datad (671:671:671) (769:769:769)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (718:718:718)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (524:524:524) (535:535:535)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~27) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (237:237:237) (282:282:282)) - (PORT datac (727:727:727) (782:782:782)) - (PORT datad (217:217:217) (251:251:251)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (439:439:439)) - (PORT datab (296:296:296) (390:390:390)) - (PORT datac (1137:1137:1137) (1168:1168:1168)) - (PORT datad (250:250:250) (323:323:323)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT dataa (2200:2200:2200) (2281:2281:2281)) - (PORT datab (236:236:236) (278:278:278)) - (PORT datac (602:602:602) (659:659:659)) - (PORT datad (1039:1039:1039) (1034:1034:1034)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (1452:1452:1452) (1485:1485:1485)) - (PORT datac (1451:1451:1451) (1488:1488:1488)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (594:594:594)) - (PORT datab (550:550:550) (563:563:563)) - (PORT datac (1357:1357:1357) (1370:1370:1370)) - (PORT datad (647:647:647) (674:674:674)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (584:584:584)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (634:634:634) (678:678:678)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (607:607:607) (648:648:648)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (902:902:902)) - (PORT datab (2019:2019:2019) (2038:2038:2038)) - (PORT datac (811:811:811) (824:824:824)) - (PORT datad (887:887:887) (895:895:895)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~26) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (262:262:262)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (212:212:212) (244:244:244)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1970:1970:1970) (2029:2029:2029)) - (PORT datac (826:826:826) (890:890:890)) - (PORT datad (544:544:544) (549:549:549)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (415:415:415)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (608:608:608) (631:631:631)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (219:219:219) (258:258:258)) (PORT datac (193:193:193) (226:226:226)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (658:658:658)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (336:336:336) (360:360:360)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1241:1241:1241)) - (PORT datab (451:451:451) (487:487:487)) - (PORT datac (746:746:746) (800:800:800)) - (PORT datad (1929:1929:1929) (1986:1986:1986)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1218:1218:1218) (1238:1238:1238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1992:1992:1992) (2003:2003:2003)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (957:957:957)) - (PORT datab (948:948:948) (988:988:988)) - (PORT datac (952:952:952) (1040:1040:1040)) - (PORT datad (1244:1244:1244) (1337:1337:1337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (920:920:920)) - (PORT datab (555:555:555) (584:584:584)) - (PORT datac (2651:2651:2651) (2699:2699:2699)) - (PORT datad (325:325:325) (347:347:347)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1107:1107:1107)) - (PORT datab (787:787:787) (896:896:896)) - (PORT datac (722:722:722) (831:831:831)) - (PORT datad (1631:1631:1631) (1626:1626:1626)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (546:546:546) (547:547:547)) - (PORT datad (1991:1991:1991) (2002:2002:2002)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1360:1360:1360)) - (PORT datab (1487:1487:1487) (1548:1548:1548)) - (PORT datac (611:611:611) (675:675:675)) - (PORT datad (827:827:827) (876:876:876)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (906:906:906)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (1102:1102:1102) (1091:1091:1091)) - (PORT datad (362:362:362) (397:397:397)) + (PORT datad (1144:1144:1144) (1174:1174:1174)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -17994,519 +9516,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) (DELAY (ABSOLUTE - (PORT dataa (2510:2510:2510) (2578:2578:2578)) - (PORT datab (968:968:968) (1013:1013:1013)) - (PORT datac (1329:1329:1329) (1335:1335:1335)) - (PORT datad (869:869:869) (880:880:880)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (476:476:476)) - (PORT datab (968:968:968) (1011:1011:1011)) - (PORT datac (1340:1340:1340) (1390:1390:1390)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (475:475:475)) - (PORT datab (896:896:896) (921:921:921)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (389:389:389)) - (PORT datab (388:388:388) (429:429:429)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (886:886:886) (895:895:895)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (1994:1994:1994) (2001:2001:2001)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (1398:1398:1398) (1449:1449:1449)) - (PORT datac (1373:1373:1373) (1416:1416:1416)) - (PORT datad (1070:1070:1070) (1118:1118:1118)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (990:990:990) (1026:1026:1026)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (990:990:990) (1026:1026:1026)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (664:664:664)) - (PORT datab (941:941:941) (1002:1002:1002)) - (PORT datad (216:216:216) (285:285:285)) + (PORT dataa (1197:1197:1197) (1255:1255:1255)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datad (1079:1079:1079) (1143:1143:1143)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (679:679:679) (694:694:694)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (448:448:448)) - (PORT datab (941:941:941) (971:971:971)) - (PORT datac (952:952:952) (1001:1001:1001)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (920:920:920)) - (PORT datab (889:889:889) (924:924:924)) - (PORT datac (807:807:807) (828:828:828)) - (PORT datad (558:558:558) (581:581:581)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1257:1257:1257) (1295:1295:1295)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1260:1260:1260) (1299:1299:1299)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1050:1050:1050)) - (PORT datab (965:965:965) (1007:1007:1007)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (978:978:978) (1023:1023:1023)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (637:637:637) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (979:979:979)) - (PORT datab (934:934:934) (981:981:981)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1132:1132:1132) (1209:1209:1209)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1562:1562:1562)) - (PORT datab (665:665:665) (715:715:715)) - (PORT datad (1640:1640:1640) (1755:1755:1755)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (631:631:631) (671:671:671)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1005:1005:1005) (1051:1051:1051)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (957:957:957) (994:994:994)) - (PORT datad (880:880:880) (927:927:927)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1153:1153:1153) (1205:1205:1205)) - (PORT ena (1204:1204:1204) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1497:1497:1497) (1521:1521:1521)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (744:744:744)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (587:587:587) (604:604:604)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1256:1256:1256) (1290:1290:1290)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1257:1257:1257) (1292:1292:1292)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (708:708:708)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (625:625:625) (661:661:661)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT asdata (1551:1551:1551) (1646:1646:1646)) - (PORT ena (1256:1256:1256) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (912:912:912)) - (PORT datab (1255:1255:1255) (1305:1305:1305)) - (PORT datad (635:635:635) (652:652:652)) - (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) (DELAY (ABSOLUTE - (PORT dataa (643:643:643) (685:685:685)) - (PORT datab (803:803:803) (863:863:863)) - (PORT datac (602:602:602) (611:611:611)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1327:1327:1327) (1388:1388:1388)) + (PORT datab (1241:1241:1241) (1298:1298:1298)) + (PORT datac (988:988:988) (1040:1040:1040)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (935:935:935)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (906:906:906) (956:956:956)) + (PORT datad (1158:1158:1158) (1199:1199:1199)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~22) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (638:638:638) (681:681:681)) + (PORT datac (1570:1570:1570) (1640:1640:1640)) + (PORT datad (566:566:566) (574:574:574)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18516,317 +9576,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (INSTANCE z80_\|pla_decode_\|Equal5\~2) (DELAY (ABSOLUTE - (PORT dataa (844:844:844) (867:867:867)) - (PORT datab (1027:1027:1027) (1075:1075:1075)) - (PORT datac (339:339:339) (360:360:360)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1174:1174:1174)) - (PORT datab (1389:1389:1389) (1427:1427:1427)) - (PORT datac (932:932:932) (1001:1001:1001)) - (PORT datad (1353:1353:1353) (1389:1389:1389)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (2598:2598:2598) (2655:2655:2655)) - (PORT datab (203:203:203) (244:244:244)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datac (1110:1110:1110) (1142:1142:1142)) - (PORT datad (1438:1438:1438) (1486:1486:1486)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (710:710:710)) - (PORT datab (940:940:940) (967:967:967)) - (PORT datac (1128:1128:1128) (1173:1173:1173)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1209:1209:1209)) - (PORT datac (912:912:912) (935:935:935)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1206:1206:1206)) - (PORT datab (943:943:943) (970:970:970)) - (PORT datac (1105:1105:1105) (1135:1135:1135)) - (PORT datad (1434:1434:1434) (1479:1479:1479)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (493:493:493)) - (PORT datac (568:568:568) (586:586:586)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (690:690:690) (717:717:717)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (690:690:690) (717:717:717)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (665:665:665)) - (PORT datab (946:946:946) (1002:1002:1002)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1265:1265:1265) (1314:1314:1314)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1265:1265:1265) (1316:1316:1316)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (312:312:312)) - (PORT datab (1085:1085:1085) (1113:1113:1113)) - (PORT datad (357:357:357) (417:417:417)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (919:919:919) (943:943:943)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (919:919:919) (943:943:943)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (457:457:457)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (417:417:417) (444:444:444)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1412:1412:1412) (1427:1427:1427)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1376:1376:1376)) - (PORT datab (1003:1003:1003) (1047:1047:1047)) - (PORT datad (892:892:892) (942:942:942)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1471:1471:1471) (1507:1507:1507)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1489:1489:1489) (1614:1614:1614)) - (PORT datab (1521:1521:1521) (1656:1656:1656)) - (PORT datac (2142:2142:2142) (2142:2142:2142)) - (PORT datad (646:646:646) (662:662:662)) + (PORT dataa (1816:1816:1816) (1908:1908:1908)) + (PORT datab (2116:2116:2116) (2267:2267:2267)) + (PORT datac (592:592:592) (610:610:610)) + (PORT datad (1468:1468:1468) (1543:1543:1543)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -18836,1403 +9592,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (284:284:284)) - (PORT datab (736:736:736) (799:799:799)) - (PORT datac (897:897:897) (948:948:948)) - (PORT datad (1169:1169:1169) (1226:1226:1226)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (952:952:952)) - (PORT datab (644:644:644) (665:665:665)) - (PORT datac (1286:1286:1286) (1331:1331:1331)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (829:829:829) (884:884:884)) - (PORT datac (710:710:710) (803:803:803)) - (PORT datad (644:644:644) (666:666:666)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (942:942:942)) - (PORT datab (1388:1388:1388) (1430:1430:1430)) - (PORT datac (205:205:205) (241:241:241)) - (PORT datad (172:172:172) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (207:207:207) (245:245:245)) - (PORT datad (1277:1277:1277) (1328:1328:1328)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1277:1277:1277)) - (PORT datac (2040:2040:2040) (2164:2164:2164)) - (PORT datad (1304:1304:1304) (1444:1444:1444)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (693:693:693)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (546:546:546) (555:555:555)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (2136:2136:2136)) - (PORT datab (1507:1507:1507) (1522:1522:1522)) - (PORT datac (1089:1089:1089) (1120:1120:1120)) - (PORT datad (1570:1570:1570) (1713:1713:1713)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1803:1803:1803) (1900:1900:1900)) - (PORT datab (1596:1596:1596) (1748:1748:1748)) - (PORT datac (3144:3144:3144) (3233:3233:3233)) - (PORT datad (1902:1902:1902) (2090:2090:2090)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1474:1474:1474) (1525:1525:1525)) - (PORT datab (1976:1976:1976) (2075:2075:2075)) - (PORT datac (1520:1520:1520) (1551:1551:1551)) - (PORT datad (1771:1771:1771) (1858:1858:1858)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (1561:1561:1561) (1627:1627:1627)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (643:643:643)) - (PORT datab (602:602:602) (655:655:655)) - (PORT datac (616:616:616) (660:660:660)) - (PORT datad (343:343:343) (363:363:363)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (665:665:665) (693:693:693)) - (PORT datac (1025:1025:1025) (1030:1030:1030)) - (PORT datad (584:584:584) (607:607:607)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (975:975:975)) - (PORT datab (657:657:657) (694:694:694)) - (PORT datac (1759:1759:1759) (1816:1816:1816)) - (PORT datad (562:562:562) (580:580:580)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (638:638:638)) - (PORT datab (656:656:656) (696:696:696)) - (PORT datac (178:178:178) (217:217:217)) - (PORT datad (943:943:943) (992:992:992)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT datac (555:555:555) (591:591:591)) - (PORT datad (1085:1085:1085) (1092:1092:1092)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2156:2156:2156)) - (PORT datab (1422:1422:1422) (1488:1488:1488)) - (PORT datad (1323:1323:1323) (1495:1495:1495)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (1021:1021:1021)) - (PORT datab (993:993:993) (1042:1042:1042)) - (PORT datac (1464:1464:1464) (1524:1524:1524)) - (PORT datad (1227:1227:1227) (1313:1313:1313)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datab (965:965:965) (1025:1025:1025)) - (PORT datac (912:912:912) (977:977:977)) - (PORT datad (958:958:958) (998:998:998)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1890:1890:1890)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (584:584:584) (639:639:639)) - (PORT datad (1583:1583:1583) (1570:1570:1570)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1386:1386:1386) (1474:1474:1474)) - (PORT datab (1349:1349:1349) (1521:1521:1521)) - (PORT datac (1103:1103:1103) (1126:1126:1126)) - (PORT datad (1358:1358:1358) (1519:1519:1519)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datab (642:642:642) (688:688:688)) - (PORT datad (333:333:333) (358:358:358)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1128:1128:1128)) - (PORT datab (820:820:820) (850:850:850)) - (PORT datac (558:558:558) (591:591:591)) - (PORT datad (546:546:546) (551:551:551)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1074:1074:1074)) - (PORT datab (881:881:881) (904:904:904)) - (PORT datac (1049:1049:1049) (1138:1138:1138)) - (PORT datad (1271:1271:1271) (1360:1360:1360)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (734:734:734)) - (PORT datab (924:924:924) (980:980:980)) - (PORT datac (1471:1471:1471) (1536:1536:1536)) - (PORT datad (1149:1149:1149) (1181:1181:1181)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1132:1132:1132)) - (PORT datab (360:360:360) (393:393:393)) - (PORT datac (555:555:555) (590:590:590)) - (PORT datad (1061:1061:1061) (1074:1074:1074)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT datab (226:226:226) (267:267:267)) - (PORT datac (601:601:601) (626:626:626)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (861:861:861) (894:894:894)) - (PORT datad (593:593:593) (607:607:607)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (694:694:694)) - (PORT datab (1536:1536:1536) (1599:1599:1599)) - (PORT datac (961:961:961) (990:990:990)) - (PORT datad (1384:1384:1384) (1458:1458:1458)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (893:893:893)) - (PORT datab (563:563:563) (581:581:581)) - (PORT datac (801:801:801) (807:807:807)) - (PORT datad (831:831:831) (859:859:859)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (340:340:340)) - (PORT datab (1770:1770:1770) (1810:1810:1810)) - (PORT datac (255:255:255) (312:312:312)) - (PORT datad (1200:1200:1200) (1271:1271:1271)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1728:1728:1728) (1834:1834:1834)) - (PORT datab (887:887:887) (890:890:890)) - (PORT datac (859:859:859) (902:902:902)) - (PORT datad (1842:1842:1842) (2007:2007:2007)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1729:1729:1729) (1835:1835:1835)) - (PORT datab (1714:1714:1714) (1825:1825:1825)) - (PORT datac (859:859:859) (903:903:903)) - (PORT datad (2100:2100:2100) (2296:2296:2296)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (250:250:250)) - (PORT datab (221:221:221) (269:269:269)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (201:201:201) (229:229:229)) + (PORT dataa (357:357:357) (400:400:400)) + (PORT datab (614:614:614) (651:651:651)) + (PORT datac (200:200:200) (237:237:237)) + (PORT datad (921:921:921) (963:963:963)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (719:719:719) (745:745:745)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (718:718:718) (747:747:747)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (982:982:982)) - (PORT datab (937:937:937) (984:984:984)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1270:1270:1270) (1302:1302:1302)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1271:1271:1271) (1304:1304:1304)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1056:1056:1056)) - (PORT datab (968:968:968) (1014:1014:1014)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (999:999:999) (1040:1040:1040)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1562:1562:1562)) - (PORT datab (657:657:657) (709:709:709)) - (PORT datad (1632:1632:1632) (1751:1751:1751)) - (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1772:1772:1772) (1847:1847:1847)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1916:1916:1916) (1967:1967:1967)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (700:700:700)) - (PORT datab (498:498:498) (553:553:553)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT asdata (1475:1475:1475) (1524:1524:1524)) - (PORT ena (1256:1256:1256) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (921:921:921)) - (PORT datab (672:672:672) (692:692:692)) - (PORT datad (1219:1219:1219) (1269:1269:1269)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (913:913:913) (927:927:927)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (972:972:972)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (917:917:917) (961:961:961)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1003:1003:1003) (1054:1054:1054)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1001:1001:1001) (1054:1054:1054)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (706:706:706)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (625:625:625) (656:656:656)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (666:666:666)) - (PORT datab (831:831:831) (898:898:898)) - (PORT datac (578:578:578) (588:588:588)) - (PORT datad (591:591:591) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (843:843:843)) - (PORT datab (1032:1032:1032) (1063:1063:1063)) - (PORT datac (813:813:813) (859:859:859)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1040:1040:1040)) - (PORT datac (960:960:960) (1021:1021:1021)) - (PORT datad (1216:1216:1216) (1283:1283:1283)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1164:1164:1164) (1183:1183:1183)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1036:1036:1036)) - (PORT datab (992:992:992) (1052:1052:1052)) - (PORT datac (1247:1247:1247) (1332:1332:1332)) - (PORT datad (1118:1118:1118) (1138:1138:1138)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (1926:1926:1926) (1967:1967:1967)) + (PORT datab (1148:1148:1148) (1185:1185:1185)) + (PORT datac (1146:1146:1146) (1185:1185:1185)) + (PORT datad (1925:1925:1925) (1953:1953:1953)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) (DELAY (ABSOLUTE - (PORT dataa (1491:1491:1491) (1578:1578:1578)) - (PORT datab (588:588:588) (620:620:620)) - (PORT datad (574:574:574) (600:600:600)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1029:1029:1029) (1114:1114:1114)) + (PORT datab (627:627:627) (649:649:649)) + (PORT datac (1538:1538:1538) (1668:1668:1668)) + (PORT datad (1102:1102:1102) (1120:1120:1120)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) (DELAY (ABSOLUTE - (PORT datab (979:979:979) (1030:1030:1030)) - (PORT datac (935:935:935) (999:999:999)) - (PORT datad (1216:1216:1216) (1283:1283:1283)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1181:1181:1181) (1228:1228:1228)) + (PORT datab (1461:1461:1461) (1489:1489:1489)) + (PORT datac (1114:1114:1114) (1146:1146:1146)) + (PORT datad (1508:1508:1508) (1559:1559:1559)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1793:1793:1793) (1856:1856:1856)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (917:917:917) (937:937:937)) + (PORT datad (1423:1423:1423) (1450:1450:1450)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) (DELAY (ABSOLUTE - (PORT datab (973:973:973) (1024:1024:1024)) - (PORT datac (931:931:931) (993:993:993)) - (PORT datad (1213:1213:1213) (1277:1277:1277)) + (PORT dataa (238:238:238) (289:289:289)) + (PORT datab (651:651:651) (704:704:704)) + (PORT datac (893:893:893) (945:945:945)) + (PORT datad (896:896:896) (956:956:956)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (565:565:565) (592:592:592)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1019:1019:1019) (1071:1071:1071)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1018:1018:1018) (1071:1071:1071)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1051:1051:1051)) - (PORT datab (965:965:965) (1008:1008:1008)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (914:914:914) (930:930:930)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (914:914:914) (930:930:930)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (978:978:978)) - (PORT datab (931:931:931) (977:977:977)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1218:1218:1218) (1256:1256:1256)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1558:1558:1558)) - (PORT datab (659:659:659) (703:703:703)) - (PORT datad (1630:1630:1630) (1743:1743:1743)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1214:1214:1214) (1253:1253:1253)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1211:1211:1211) (1250:1250:1250)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (712:712:712)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (623:623:623) (658:658:658)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (697:697:697) (721:721:721)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (968:968:968)) - (PORT datab (959:959:959) (996:996:996)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1223:1223:1223) (1248:1248:1248)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1227:1227:1227) (1258:1258:1258)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (520:520:520)) - (PORT datab (498:498:498) (554:554:554)) - (PORT datad (627:627:627) (659:659:659)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1229:1229:1229) (1261:1261:1261)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1035:1035:1035)) - (PORT datab (1291:1291:1291) (1330:1330:1330)) - (PORT datad (1490:1490:1490) (1545:1545:1545)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (369:369:369)) - (PORT datab (654:654:654) (670:670:670)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (382:382:382)) - (PORT datab (615:615:615) (642:642:642)) - (PORT datac (632:632:632) (658:658:658)) - (PORT datad (613:613:613) (637:637:637)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (847:847:847)) - (PORT datab (405:405:405) (445:445:445)) - (PORT datac (1349:1349:1349) (1373:1373:1373)) - (PORT datad (593:593:593) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (895:895:895) (905:905:905)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (1250:1250:1250) (1323:1323:1323)) - (PORT datad (563:563:563) (584:584:584)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (327:327:327)) - (PORT datab (589:589:589) (623:623:623)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (405:405:405)) - (PORT datac (883:883:883) (935:935:935)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (179:179:179) (218:218:218)) - (PORT datad (603:603:603) (621:621:621)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20240,47 +9688,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (236:236:236) (288:288:288)) - (PORT datab (680:680:680) (738:738:738)) - (PORT datac (1196:1196:1196) (1238:1238:1238)) - (PORT datad (1772:1772:1772) (1834:1834:1834)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (908:908:908) (948:948:948)) + (PORT datab (1000:1000:1000) (1060:1060:1060)) + (PORT datac (1625:1625:1625) (1656:1656:1656)) + (PORT datad (631:631:631) (682:682:682)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (860:860:860)) - (PORT datab (1104:1104:1104) (1147:1147:1147)) - (PORT datac (1002:1002:1002) (1071:1071:1071)) - (PORT datad (847:847:847) (873:873:873)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1078:1078:1078) (1094:1094:1094)) + (PORT datad (343:343:343) (363:363:363)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (944:944:944)) + (PORT datab (628:628:628) (665:665:665)) + (PORT datac (855:855:855) (878:878:878)) + (PORT datad (561:561:561) (587:587:587)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~7) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (941:941:941)) - (PORT datab (916:916:916) (948:948:948)) - (PORT datac (338:338:338) (357:357:357)) - (PORT datad (854:854:854) (893:893:893)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (968:968:968) (1035:1035:1035)) + (PORT datab (1634:1634:1634) (1659:1659:1659)) + (PORT datac (1183:1183:1183) (1225:1225:1225)) + (PORT datad (946:946:946) (980:980:980)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20291,58 +9753,322 @@ (INSTANCE z80_\|execute_\|ctl_al_we\~8) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (453:453:453)) - (PORT datab (1472:1472:1472) (1490:1490:1490)) - (PORT datac (1016:1016:1016) (1077:1077:1077)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (647:647:647) (693:693:693)) + (PORT datab (2028:2028:2028) (2071:2071:2071)) + (PORT datac (1456:1456:1456) (1525:1525:1525)) + (PORT datad (928:928:928) (945:945:945)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1033:1033:1033)) + (PORT datab (1229:1229:1229) (1256:1256:1256)) + (PORT datac (1153:1153:1153) (1236:1236:1236)) + (PORT datad (1150:1150:1150) (1170:1170:1170)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1481:1481:1481) (1505:1505:1505)) + (PORT datab (374:374:374) (397:397:397)) + (PORT datac (1422:1422:1422) (1480:1480:1480)) + (PORT datad (1121:1121:1121) (1190:1190:1190)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (763:763:763)) + (PORT datab (657:657:657) (713:713:713)) + (PORT datac (1710:1710:1710) (1755:1755:1755)) + (PORT datad (1160:1160:1160) (1199:1199:1199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (872:872:872)) + (PORT datac (690:690:690) (799:799:799)) + (PORT datad (962:962:962) (1055:1055:1055)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1580:1580:1580)) + (PORT datab (897:897:897) (929:929:929)) + (PORT datac (1513:1513:1513) (1557:1557:1557)) + (PORT datad (1759:1759:1759) (1804:1804:1804)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_al_we\~11) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (374:374:374)) - (PORT datab (663:663:663) (676:676:676)) - (PORT datac (551:551:551) (566:566:566)) - (PORT datad (616:616:616) (633:633:633)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1211:1211:1211) (1274:1274:1274)) + (PORT datab (1260:1260:1260) (1377:1377:1377)) + (PORT datac (1648:1648:1648) (1819:1819:1819)) + (PORT datad (397:397:397) (426:426:426)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (INSTANCE z80_\|execute_\|ctl_al_we\~4) (DELAY (ABSOLUTE - (PORT dataa (1147:1147:1147) (1215:1215:1215)) - (PORT datab (1209:1209:1209) (1278:1278:1278)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (827:827:827) (839:839:839)) + (PORT dataa (404:404:404) (435:435:435)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (1194:1194:1194) (1234:1234:1234)) + (PORT datad (382:382:382) (412:412:412)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1239:1239:1239)) + (PORT datab (1847:1847:1847) (1912:1912:1912)) + (PORT datac (1506:1506:1506) (1541:1541:1541)) + (PORT datad (1295:1295:1295) (1364:1364:1364)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1278:1278:1278)) + (PORT datac (1761:1761:1761) (1845:1845:1845)) + (PORT datad (1131:1131:1131) (1154:1154:1154)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (422:422:422)) + (PORT datab (918:918:918) (969:969:969)) + (PORT datac (608:608:608) (627:627:627)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1383:1383:1383)) + (PORT datab (1960:1960:1960) (2010:2010:2010)) + (PORT datac (792:792:792) (822:822:822)) + (PORT datad (2106:2106:2106) (2137:2137:2137)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1856:1856:1856)) + (PORT datab (1757:1757:1757) (1827:1827:1827)) + (PORT datac (2074:2074:2074) (2182:2182:2182)) + (PORT datad (1232:1232:1232) (1305:1305:1305)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT datab (1735:1735:1735) (1780:1780:1780)) + (PORT datac (1149:1149:1149) (1176:1176:1176)) + (PORT datad (1330:1330:1330) (1363:1363:1363)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1280:1280:1280)) + (PORT datab (585:585:585) (608:608:608)) + (PORT datac (652:652:652) (702:702:702)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1810:1810:1810) (1863:1863:1863)) + (PORT datab (1124:1124:1124) (1167:1167:1167)) + (PORT datac (1121:1121:1121) (1144:1144:1144)) + (PORT datad (1670:1670:1670) (1693:1693:1693)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1190:1190:1190)) + (PORT datab (596:596:596) (625:625:625)) + (PORT datac (1134:1134:1134) (1160:1160:1160)) + (PORT datad (225:225:225) (260:260:260)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (741:741:741)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1106:1106:1106) (1133:1133:1133)) + (PORT datad (658:658:658) (680:680:680)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1336:1336:1336)) + (PORT datab (991:991:991) (1048:1048:1048)) + (PORT datac (580:580:580) (634:634:634)) + (PORT datad (1470:1470:1470) (1539:1539:1539)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) + (INSTANCE z80_\|address_latch_\|Q\[14\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -20352,626 +10078,65 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (900:900:900) (908:908:908)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (900:900:900) (911:911:911)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (318:318:318)) - (PORT datab (1081:1081:1081) (1113:1113:1113)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1215:1215:1215) (1256:1256:1256)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1217:1217:1217) (1254:1254:1254)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (462:462:462)) - (PORT datab (452:452:452) (481:481:481)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (621:621:621) (651:651:651)) - (PORT datac (1318:1318:1318) (1334:1334:1334)) - (PORT datad (1133:1133:1133) (1166:1166:1166)) + (PORT dataa (1532:1532:1532) (1562:1562:1562)) + (PORT datab (2538:2538:2538) (2566:2566:2566)) + (PORT datac (945:945:945) (994:994:994)) + (PORT datad (931:931:931) (945:945:945)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (596:596:596)) - (PORT datab (1148:1148:1148) (1164:1164:1164)) - (PORT datac (1083:1083:1083) (1082:1082:1082)) - (PORT datad (819:819:819) (843:843:843)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (835:835:835)) - (PORT datab (390:390:390) (417:417:417)) - (PORT datac (1069:1069:1069) (1074:1074:1074)) - (PORT datad (1075:1075:1075) (1109:1109:1109)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (685:685:685)) - (PORT datab (1345:1345:1345) (1363:1363:1363)) - (PORT datac (653:653:653) (717:717:717)) - (PORT datad (1140:1140:1140) (1170:1170:1170)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (952:952:952)) - (PORT datab (882:882:882) (913:913:913)) - (PORT datac (1082:1082:1082) (1120:1120:1120)) - (PORT datad (836:836:836) (859:859:859)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (911:911:911)) - (PORT datab (599:599:599) (619:619:619)) - (PORT datac (802:802:802) (820:820:820)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (952:952:952)) - (PORT datab (903:903:903) (934:934:934)) - (PORT datac (806:806:806) (826:826:826)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (954:954:954)) - (PORT datab (891:891:891) (915:915:915)) - (PORT datac (862:862:862) (932:932:932)) - (PORT datad (1058:1058:1058) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1695:1695:1695) (1745:1745:1745)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) (DELAY (ABSOLUTE - (PORT datad (1005:1005:1005) (1047:1047:1047)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (847:847:847)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (710:710:710)) - (PORT datab (244:244:244) (289:289:289)) - (PORT datad (547:547:547) (596:596:596)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1690:1690:1690) (1722:1722:1722)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1694:1694:1694) (1745:1745:1745)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1687:1687:1687) (1719:1719:1719)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (759:759:759)) - (PORT datab (676:676:676) (718:718:718)) - (PORT datad (629:629:629) (658:658:658)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (458:458:458)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1445:1445:1445) (1462:1462:1462)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1445:1445:1445) (1465:1465:1465)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (661:661:661)) - (PORT datab (941:941:941) (1000:1000:1000)) - (PORT datad (216:216:216) (284:284:284)) + (PORT dataa (1522:1522:1522) (1674:1674:1674)) + (PORT datab (1832:1832:1832) (2023:2023:2023)) + (PORT datac (1749:1749:1749) (1883:1883:1883)) + (PORT datad (1529:1529:1529) (1629:1629:1629)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (622:622:622)) - (PORT datab (801:801:801) (823:823:823)) - (PORT datac (647:647:647) (685:685:685)) - (PORT datad (828:828:828) (870:870:870)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (704:704:704)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (622:622:622) (661:661:661)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (899:899:899)) - (PORT datab (353:353:353) (392:392:392)) - (PORT datac (1132:1132:1132) (1184:1184:1184)) - (PORT datad (670:670:670) (701:701:701)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (672:672:672) (695:695:695)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) (DELAY (ABSOLUTE - (PORT dataa (1469:1469:1469) (1520:1520:1520)) - (PORT datab (820:820:820) (835:835:835)) - (PORT datad (653:653:653) (675:675:675)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (912:912:912) (928:928:928)) + (PORT datab (954:954:954) (1013:1013:1013)) + (PORT datac (889:889:889) (915:915:915)) + (PORT datad (1490:1490:1490) (1513:1513:1513)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (607:607:607) (630:630:630)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT datab (704:704:704) (782:782:782)) - (PORT datad (796:796:796) (798:798:798)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1209:1209:1209) (1265:1265:1265)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1132:1132:1132)) - (PORT datad (634:634:634) (652:652:652)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1250:1250:1250)) - (PORT datab (904:904:904) (935:935:935)) - (PORT datac (384:384:384) (452:452:452)) - (PORT datad (911:911:911) (971:971:971)) + (PORT datab (691:691:691) (715:715:715)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (891:891:891) (930:930:930)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (390:390:390) (464:464:464)) - (PORT datad (189:189:189) (222:222:222)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20979,14 +10144,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (INSTANCE z80_\|pla_decode_\|Equal62\~2) (DELAY (ABSOLUTE - (PORT dataa (1543:1543:1543) (1611:1611:1611)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (432:432:432) (479:479:479)) - (PORT datad (319:319:319) (341:341:341)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datac (1127:1127:1127) (1186:1186:1186)) + (PORT datad (1027:1027:1027) (1133:1133:1133)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (492:492:492)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (903:903:903) (942:942:942)) + (PORT datad (421:421:421) (486:486:486)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1371:1371:1371)) + (PORT datab (1733:1733:1733) (1812:1812:1812)) + (PORT datac (1131:1131:1131) (1186:1186:1186)) + (PORT datad (1024:1024:1024) (1129:1129:1129)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20995,445 +10188,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) (DELAY (ABSOLUTE - (PORT datac (880:880:880) (934:934:934)) - (PORT datad (313:313:313) (333:333:333)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (892:892:892) (909:909:909)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1387:1387:1387) (1394:1394:1394)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1035:1035:1035)) - (PORT datab (1288:1288:1288) (1327:1327:1327)) - (PORT datad (831:831:831) (901:901:901)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1200:1200:1200) (1214:1214:1214)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (957:957:957) (998:998:998)) - (PORT datad (879:879:879) (924:924:924)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1245:1245:1245) (1259:1259:1259)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1245:1245:1245) (1259:1259:1259)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (706:706:706)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (621:621:621) (655:655:655)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1206:1206:1206) (1211:1211:1211)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1386:1386:1386) (1392:1392:1392)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (513:513:513)) - (PORT datab (498:498:498) (557:557:557)) - (PORT datad (622:622:622) (662:662:662)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (674:674:674)) - (PORT datab (845:845:845) (862:862:862)) - (PORT datac (584:584:584) (597:597:597)) - (PORT datad (575:575:575) (585:585:585)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1426:1426:1426) (1436:1436:1436)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1076:1076:1076) (1088:1088:1088)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1056:1056:1056)) - (PORT datab (964:964:964) (1012:1012:1012)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1210:1210:1210) (1217:1217:1217)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1556:1556:1556)) - (PORT datab (656:656:656) (706:706:706)) - (PORT datad (1631:1631:1631) (1740:1740:1740)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (709:709:709) (736:736:736)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (709:709:709) (736:736:736)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (977:977:977)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (899:899:899) (938:938:938)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (672:672:672)) - (PORT datab (674:674:674) (694:694:694)) - (PORT datac (855:855:855) (905:905:905)) - (PORT datad (319:319:319) (339:339:339)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (579:579:579)) - (PORT datab (400:400:400) (438:438:438)) - (PORT datac (1346:1346:1346) (1369:1369:1369)) - (PORT datad (569:569:569) (587:587:587)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (694:694:694)) - (PORT datab (621:621:621) (667:667:667)) - (PORT datad (582:582:582) (592:592:592)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (403:403:403) (482:482:482)) - (PORT datad (585:585:585) (610:610:610)) + (PORT dataa (971:971:971) (1046:1046:1046)) + (PORT datab (707:707:707) (763:763:763)) + (PORT datac (1491:1491:1491) (1589:1589:1589)) + (PORT datad (1500:1500:1500) (1593:1593:1593)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1542:1542:1542)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1392:1392:1392) (1448:1448:1448)) + (PORT datad (1090:1090:1090) (1101:1101:1101)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (535:535:535)) + (PORT datab (2099:2099:2099) (2168:2168:2168)) + (PORT datac (1127:1127:1127) (1186:1186:1186)) + (PORT datad (1025:1025:1025) (1131:1131:1131)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21441,328 +10236,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (508:508:508)) - (PORT datab (905:905:905) (932:932:932)) - (PORT datac (415:415:415) (484:484:484)) - (PORT datad (188:188:188) (218:218:218)) + (PORT dataa (255:255:255) (315:315:315)) + (PORT datab (858:858:858) (886:886:886)) + (PORT datac (1500:1500:1500) (1562:1562:1562)) + (PORT datad (1096:1096:1096) (1134:1134:1134)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (909:909:909) (948:948:948)) + (PORT datac (637:637:637) (668:668:668)) + (PORT datad (600:600:600) (639:639:639)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (611:611:611)) + (PORT datab (1035:1035:1035) (1047:1047:1047)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (190:190:190) (224:224:224)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1540:1540:1540) (1609:1609:1609)) - (PORT datab (380:380:380) (414:414:414)) - (PORT datac (435:435:435) (484:484:484)) - (PORT datad (359:359:359) (378:378:378)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (883:883:883) (940:940:940)) - (PORT datad (333:333:333) (350:350:350)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (503:503:503)) - (PORT datab (904:904:904) (930:930:930)) - (PORT datac (414:414:414) (483:483:483)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (2165:2165:2165) (2195:2195:2195)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (2167:2167:2167) (2197:2197:2197)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[2\]) (DELAY (ABSOLUTE - (PORT dataa (918:918:918) (982:982:982)) - (PORT datab (932:932:932) (982:982:982)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1965:1965:1965) (2001:2001:2001)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1563:1563:1563)) - (PORT datab (662:662:662) (714:714:714)) - (PORT datad (1637:1637:1637) (1748:1748:1748)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (959:959:959) (984:984:984)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (961:961:961) (982:982:982)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1058:1058:1058)) - (PORT datab (964:964:964) (1012:1012:1012)) - (PORT datad (353:353:353) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1767:1767:1767) (1800:1800:1800)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1768:1768:1768) (1802:1802:1802)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (711:711:711)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (622:622:622) (656:656:656)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1910:1910:1910) (1926:1926:1926)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1990:1990:1990) (2006:2006:2006)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (514:514:514)) - (PORT datab (497:497:497) (558:558:558)) - (PORT datad (621:621:621) (655:655:655)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1990:1990:1990) (2008:2008:2008)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1111:1111:1111)) - (PORT datab (882:882:882) (895:895:895)) - (PORT datac (824:824:824) (834:834:834)) - (PORT datad (1128:1128:1128) (1146:1146:1146)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1167:1167:1167) (1252:1252:1252)) + (PORT datab (714:714:714) (758:758:758)) + (PORT datac (1577:1577:1577) (1594:1594:1594)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21770,91 +10300,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~10) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (715:715:715)) - (PORT datab (1096:1096:1096) (1104:1104:1104)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (950:950:950) (981:981:981)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1034:1034:1034)) - (PORT datab (1288:1288:1288) (1327:1327:1327)) - (PORT datad (844:844:844) (907:907:907)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (2137:2137:2137) (2157:2157:2157)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (327:327:327)) - (PORT datab (957:957:957) (993:993:993)) - (PORT datad (879:879:879) (921:921:921)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (701:701:701)) - (PORT datab (651:651:651) (704:704:704)) - (PORT datac (614:614:614) (661:661:661)) - (PORT datad (632:632:632) (653:653:653)) + (PORT dataa (1458:1458:1458) (1527:1527:1527)) + (PORT datab (1191:1191:1191) (1267:1267:1267)) + (PORT datac (1209:1209:1209) (1271:1271:1271)) + (PORT datad (1798:1798:1798) (1823:1823:1823)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -21862,488 +10314,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (636:636:636)) - (PORT datab (654:654:654) (706:706:706)) - (PORT datac (844:844:844) (895:895:895)) - (PORT datad (172:172:172) (196:196:196)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1377:1377:1377) (1408:1408:1408)) - (PORT datab (643:643:643) (692:692:692)) - (PORT datac (543:543:543) (567:567:567)) - (PORT datad (373:373:373) (401:401:401)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1137:1137:1137) (1157:1157:1157)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1648:1648:1648)) - (PORT datab (588:588:588) (621:621:621)) - (PORT datad (575:575:575) (600:600:600)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (565:565:565) (592:592:592)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (589:589:589)) - (PORT datab (711:711:711) (747:747:747)) - (PORT datac (381:381:381) (458:458:458)) - (PORT datad (623:623:623) (682:682:682)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (475:475:475) (521:521:521)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (519:519:519) (550:550:550)) - (PORT datad (1502:1502:1502) (1569:1569:1569)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (903:903:903) (949:949:949)) - (PORT datac (795:795:795) (815:815:815)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (591:591:591)) - (PORT datab (712:712:712) (749:749:749)) - (PORT datac (380:380:380) (454:454:454)) - (PORT datad (624:624:624) (682:682:682)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (508:508:508)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (963:963:963) (1022:1022:1022)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (962:962:962) (1021:1021:1021)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1057:1057:1057)) - (PORT datab (969:969:969) (1008:1008:1008)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (678:678:678) (714:714:714)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (678:678:678) (714:714:714)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (982:982:982)) - (PORT datab (937:937:937) (981:981:981)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (893:893:893) (927:927:927)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1710:1710:1710) (1763:1763:1763)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (700:700:700)) - (PORT datab (501:501:501) (558:558:558)) - (PORT datad (620:620:620) (655:655:655)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1710:1710:1710) (1761:1761:1761)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1144:1144:1144)) - (PORT datab (705:705:705) (763:763:763)) - (PORT datac (1078:1078:1078) (1114:1114:1114)) - (PORT datad (188:188:188) (223:223:223)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1291:1291:1291)) - (PORT datab (808:808:808) (845:845:845)) - (PORT datac (818:818:818) (868:868:868)) - (PORT datad (804:804:804) (813:813:813)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1330:1330:1330)) - (PORT datab (985:985:985) (1056:1056:1056)) - (PORT datac (647:647:647) (686:686:686)) - (PORT datad (1360:1360:1360) (1453:1453:1453)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (388:388:388)) - (PORT datab (889:889:889) (946:946:946)) - (PORT datac (612:612:612) (646:646:646)) - (PORT datad (933:933:933) (987:987:987)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (970:970:970)) - (PORT datab (287:287:287) (346:346:346)) - (PORT datad (853:853:853) (856:856:856)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datab (285:285:285) (345:345:345)) - (PORT datad (854:854:854) (856:856:856)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) (DELAY (ABSOLUTE - (PORT dataa (2000:2000:2000) (2162:2162:2162)) - (PORT datac (1090:1090:1090) (1122:1122:1122)) - (PORT datad (1323:1323:1323) (1497:1497:1497)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (1580:1580:1580) (1683:1683:1683)) + (PORT datac (1558:1558:1558) (1700:1700:1700)) + (PORT datad (651:651:651) (698:698:698)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -22353,12 +10333,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (945:945:945) (967:967:967)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (888:888:888) (937:937:937)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (653:653:653) (700:700:700)) + (PORT datab (1336:1336:1336) (1384:1384:1384)) + (PORT datac (1002:1002:1002) (1027:1027:1027)) + (PORT datad (314:314:314) (334:334:334)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22366,13 +10346,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datac (698:698:698) (765:765:765)) - (PORT datad (855:855:855) (908:908:908)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (239:239:239) (288:288:288)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1613:1613:1613) (1765:1765:1765)) + (PORT datab (1371:1371:1371) (1395:1395:1395)) + (PORT datac (1383:1383:1383) (1423:1423:1423)) + (PORT datad (1273:1273:1273) (1357:1357:1357)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22380,13 +10376,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) (DELAY (ABSOLUTE - (PORT datab (224:224:224) (265:265:265)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1323:1323:1323) (1378:1378:1378)) + (PORT dataa (636:636:636) (671:671:671)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (615:615:615) (653:653:653)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (965:965:965)) + (PORT datab (1230:1230:1230) (1309:1309:1309)) + (PORT datac (901:901:901) (933:933:933)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1527:1527:1527)) + (PORT datab (660:660:660) (703:703:703)) + (PORT datac (1214:1214:1214) (1276:1276:1276)) + (PORT datad (1351:1351:1351) (1352:1352:1352)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2208:2208:2208) (2424:2424:2424)) + (PORT datab (984:984:984) (1064:1064:1064)) + (PORT datac (1509:1509:1509) (1543:1543:1543)) + (PORT datad (1172:1172:1172) (1236:1236:1236)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1310:1310:1310)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1425:1425:1425) (1491:1491:1491)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (929:929:929) (974:974:974)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (1401:1401:1401) (1424:1424:1424)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -22394,91 +10472,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) (DELAY (ABSOLUTE - (PORT dataa (1541:1541:1541) (1629:1629:1629)) - (PORT datab (1591:1591:1591) (1670:1670:1670)) - (PORT datac (857:857:857) (918:918:918)) - (PORT datad (398:398:398) (467:467:467)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (507:507:507)) - (PORT datab (587:587:587) (606:606:606)) - (PORT datac (849:849:849) (909:909:909)) - (PORT datad (239:239:239) (282:282:282)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (662:662:662) (679:679:679)) - (PORT ena (1474:1474:1474) (1475:1475:1475)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (663:663:663)) - (PORT datab (1117:1117:1117) (1151:1151:1151)) - (PORT datad (847:847:847) (870:870:870)) + (PORT dataa (950:950:950) (1015:1015:1015)) + (PORT datab (1896:1896:1896) (2024:2024:2024)) + (PORT datac (914:914:914) (971:971:971)) + (PORT datad (718:718:718) (797:797:797)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (662:662:662)) - (PORT datab (1316:1316:1316) (1369:1369:1369)) - (PORT datac (209:209:209) (247:247:247)) - (PORT datad (841:841:841) (848:848:848)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (252:252:252) (311:311:311)) - (PORT datad (347:347:347) (371:371:371)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (933:933:933) (971:971:971)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (928:928:928) (983:983:983)) + (PORT datad (1369:1369:1369) (1395:1395:1395)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -22488,10 +10507,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (419:419:419)) - (PORT datab (1011:1011:1011) (1072:1072:1072)) - (PORT datac (1687:1687:1687) (1750:1750:1750)) - (PORT datad (1175:1175:1175) (1233:1233:1233)) + (PORT dataa (239:239:239) (290:290:290)) + (PORT datab (1157:1157:1157) (1198:1198:1198)) + (PORT datac (1291:1291:1291) (1405:1405:1405)) + (PORT datad (925:925:925) (941:941:941)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -22501,16 +10520,154 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (586:586:586) (607:607:607)) - (PORT datac (918:918:918) (934:934:934)) - (PORT datad (852:852:852) (859:859:859)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1787:1787:1787) (1839:1839:1839)) + (PORT datab (1447:1447:1447) (1469:1469:1469)) + (PORT datac (630:630:630) (666:666:666)) + (PORT datad (910:910:910) (923:923:923)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (969:969:969)) + (PORT datab (1447:1447:1447) (1470:1470:1470)) + (PORT datac (885:885:885) (929:929:929)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1818:1818:1818) (1920:1920:1920)) + (PORT datab (1563:1563:1563) (1693:1693:1693)) + (PORT datad (216:216:216) (241:241:241)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1205:1205:1205)) + (PORT datab (2276:2276:2276) (2317:2317:2317)) + (PORT datac (1130:1130:1130) (1165:1165:1165)) + (PORT datad (1979:1979:1979) (2101:2101:2101)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1206:1206:1206)) + (PORT datab (1237:1237:1237) (1284:1284:1284)) + (PORT datac (1128:1128:1128) (1167:1167:1167)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (896:896:896)) + (PORT datab (379:379:379) (402:402:402)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (441:441:441)) + (PORT datab (2145:2145:2145) (2210:2210:2210)) + (PORT datac (1175:1175:1175) (1254:1254:1254)) + (PORT datad (1368:1368:1368) (1417:1417:1417)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (389:389:389)) + (PORT datab (1350:1350:1350) (1386:1386:1386)) + (PORT datac (361:361:361) (381:381:381)) + (PORT datad (881:881:881) (938:938:938)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1490:1490:1490)) + (PORT datab (831:831:831) (869:869:869)) + (PORT datac (569:569:569) (588:588:588)) + (PORT datad (909:909:909) (934:934:934)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (947:947:947) (1009:1009:1009)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -22520,23 +10677,23 @@ (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) (DELAY (ABSOLUTE - (PORT datab (593:593:593) (612:612:612)) - (PORT datac (250:250:250) (307:307:307)) - (PORT datad (858:858:858) (860:860:860)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1453:1453:1453) (1482:1482:1482)) + (PORT datab (837:837:837) (874:874:874)) + (PORT datad (904:904:904) (964:964:964)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT clk (1516:1516:1516) (1520:1520:1520)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -22550,1685 +10707,39 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (921:921:921)) - (PORT datab (1005:1005:1005) (1064:1064:1064)) - (PORT datac (1691:1691:1691) (1755:1755:1755)) - (PORT datad (1168:1168:1168) (1225:1225:1225)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (957:957:957) (1024:1024:1024)) - (PORT datab (1075:1075:1075) (1139:1139:1139)) - (PORT datac (867:867:867) (925:925:925)) - (PORT datad (646:646:646) (678:678:678)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (731:731:731)) - (PORT datab (660:660:660) (692:692:692)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (913:913:913) (955:955:955)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (725:725:725)) - (PORT datab (663:663:663) (713:713:713)) - (PORT datac (627:627:627) (659:659:659)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1454:1454:1454) (1593:1593:1593)) - (PORT datab (927:927:927) (972:972:972)) - (PORT datac (587:587:587) (604:604:604)) - (PORT datad (1544:1544:1544) (1686:1686:1686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (951:951:951)) - (PORT datab (989:989:989) (1033:1033:1033)) - (PORT datac (1425:1425:1425) (1436:1436:1436)) - (PORT datad (651:651:651) (670:670:670)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1306:1306:1306)) - (PORT datab (621:621:621) (668:668:668)) - (PORT datac (1465:1465:1465) (1520:1520:1520)) - (PORT datad (628:628:628) (636:636:636)) + (PORT dataa (1721:1721:1721) (1772:1772:1772)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (2071:2071:2071) (2177:2177:2177)) + (PORT datad (215:215:215) (240:240:240)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1281:1281:1281)) - (PORT datab (1244:1244:1244) (1294:1294:1294)) - (PORT datac (877:877:877) (941:941:941)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1306:1306:1306)) - (PORT datab (1263:1263:1263) (1349:1349:1349)) - (PORT datac (2128:2128:2128) (2214:2214:2214)) - (PORT datad (1440:1440:1440) (1511:1511:1511)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (408:408:408)) - (PORT datab (654:654:654) (669:669:669)) - (PORT datac (357:357:357) (377:377:377)) - (PORT datad (316:316:316) (335:335:335)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (392:392:392)) - (PORT datab (337:337:337) (369:369:369)) - (PORT datac (870:870:870) (876:876:876)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (293:293:293)) - (PORT datab (893:893:893) (901:901:901)) - (PORT datac (366:366:366) (393:393:393)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (998:998:998)) - (PORT datab (218:218:218) (255:255:255)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (610:610:610) (646:646:646)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1381:1381:1381)) - (PORT datab (674:674:674) (719:719:719)) - (PORT datac (640:640:640) (688:688:688)) - (PORT datad (913:913:913) (955:955:955)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (661:661:661)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (699:699:699)) - (PORT datab (247:247:247) (288:288:288)) - (PORT datac (828:828:828) (858:858:858)) - (PORT datad (843:843:843) (860:860:860)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (508:508:508)) - (PORT datab (867:867:867) (892:892:892)) - (PORT datac (604:604:604) (651:651:651)) - (PORT datad (566:566:566) (585:585:585)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1252:1252:1252)) - (PORT datab (574:574:574) (587:587:587)) - (PORT datac (861:861:861) (886:886:886)) - (PORT datad (1797:1797:1797) (1884:1884:1884)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1255:1255:1255)) - (PORT datab (572:572:572) (588:588:588)) - (PORT datac (858:858:858) (886:886:886)) - (PORT datad (1798:1798:1798) (1887:1887:1887)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (298:298:298)) - (PORT datab (554:554:554) (571:571:571)) - (PORT datac (228:228:228) (266:266:266)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (214:214:214) (259:259:259)) - (PORT datad (204:204:204) (235:235:235)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (825:825:825) (834:834:834)) - (PORT datac (556:556:556) (572:572:572)) - (PORT datad (330:330:330) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT asdata (690:690:690) (711:711:711)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1079:1079:1079)) - (PORT datab (664:664:664) (707:707:707)) - (PORT datac (633:633:633) (680:680:680)) - (PORT datad (584:584:584) (611:611:611)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datac (625:625:625) (657:657:657)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (992:992:992) (1100:1100:1100)) - (PORT datab (1591:1591:1591) (1671:1671:1671)) - (PORT datac (857:857:857) (917:917:917)) - (PORT datad (421:421:421) (491:491:491)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (710:710:710) (805:805:805)) - (PORT datad (847:847:847) (895:895:895)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (943:943:943)) - (PORT datab (1389:1389:1389) (1433:1433:1433)) - (PORT datac (204:204:204) (242:242:242)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (514:514:514)) - (PORT datab (270:270:270) (325:325:325)) - (PORT datad (605:605:605) (628:628:628)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (886:886:886)) - (PORT datab (812:812:812) (875:875:875)) - (PORT datac (607:607:607) (626:626:626)) - (PORT datad (617:617:617) (630:630:630)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (843:843:843) (913:913:913)) - (PORT datad (662:662:662) (672:672:672)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1717:1717:1717) (1813:1813:1813)) - (PORT ena (1475:1475:1475) (1479:1479:1479)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1717:1717:1717) (1813:1813:1813)) - (PORT ena (1485:1485:1485) (1497:1497:1497)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (976:976:976)) - (PORT datab (932:932:932) (975:975:975)) - (PORT datad (214:214:214) (282:282:282)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1677:1677:1677) (1751:1751:1751)) - (PORT ena (1546:1546:1546) (1548:1548:1548)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1074:1074:1074) (1150:1150:1150)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1446:1446:1446) (1455:1455:1455)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1053:1053:1053)) - (PORT datab (967:967:967) (1008:1008:1008)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1419:1419:1419) (1492:1492:1492)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1488:1488:1488) (1562:1562:1562)) - (PORT datab (663:663:663) (712:712:712)) - (PORT datad (1638:1638:1638) (1752:1752:1752)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (957:957:957) (989:989:989)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (956:956:956) (987:987:987)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (970:970:970)) - (PORT datab (956:956:956) (998:998:998)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1182:1182:1182) (1255:1255:1255)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1429:1429:1429) (1502:1502:1502)) - (PORT ena (1196:1196:1196) (1165:1165:1165)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (689:689:689)) - (PORT datab (456:456:456) (531:531:531)) - (PORT datad (627:627:627) (664:664:664)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1431:1431:1431) (1502:1502:1502)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (1431:1431:1431) (1503:1503:1503)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (706:706:706)) - (PORT datab (239:239:239) (320:320:320)) - (PORT datad (626:626:626) (662:662:662)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (1427:1427:1427) (1500:1500:1500)) - (PORT ena (1256:1256:1256) (1255:1255:1255)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1033:1033:1033)) - (PORT datab (1290:1290:1290) (1329:1329:1329)) - (PORT datad (808:808:808) (878:878:878)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (403:403:403)) - (PORT datab (862:862:862) (914:914:914)) - (PORT datac (576:576:576) (606:606:606)) - (PORT datad (807:807:807) (828:828:828)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (614:614:614)) - (PORT datab (839:839:839) (859:859:859)) - (PORT datac (619:619:619) (659:659:659)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT datab (902:902:902) (944:944:944)) - (PORT datad (877:877:877) (887:887:887)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (510:510:510)) - (PORT datab (213:213:213) (259:259:259)) - (PORT datac (584:584:584) (636:636:636)) - (PORT datad (673:673:673) (710:710:710)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (761:761:761) (801:801:801)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (621:621:621) (663:663:663)) - (PORT datad (560:560:560) (586:586:586)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (538:538:538) (569:569:569)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (606:606:606) (648:648:648)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (395:395:395) (466:466:466)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1539:1539:1539) (1609:1609:1609)) - (PORT datab (534:534:534) (553:553:553)) - (PORT datac (434:434:434) (481:481:481)) - (PORT datad (345:345:345) (369:369:369)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1357:1357:1357) (1408:1408:1408)) - (PORT datac (420:420:420) (460:460:460)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1067:1067:1067)) - (PORT datab (879:879:879) (898:898:898)) - (PORT datac (1268:1268:1268) (1345:1345:1345)) - (PORT datad (1057:1057:1057) (1068:1068:1068)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (721:721:721)) - (PORT datab (1094:1094:1094) (1099:1099:1099)) - (PORT datac (994:994:994) (1030:1030:1030)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (743:743:743) (837:837:837)) - (PORT datac (199:199:199) (234:234:234)) - (PORT datad (227:227:227) (256:256:256)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (882:882:882) (933:933:933)) - (PORT datac (1359:1359:1359) (1403:1403:1403)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (674:674:674)) - (PORT datab (413:413:413) (463:463:463)) - (PORT datac (855:855:855) (912:912:912)) - (PORT datad (242:242:242) (285:285:285)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (728:728:728)) - (PORT datab (860:860:860) (903:903:903)) - (PORT datac (2033:2033:2033) (2070:2070:2070)) - (PORT datad (836:836:836) (928:928:928)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (445:445:445)) - (PORT datab (1316:1316:1316) (1370:1370:1370)) - (PORT datac (609:609:609) (627:627:627)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (915:915:915)) - (PORT datab (354:354:354) (389:389:389)) - (PORT datac (610:610:610) (623:623:623)) - (PORT datad (640:640:640) (654:654:654)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (949:949:949)) - (PORT datab (600:600:600) (621:621:621)) - (PORT datac (196:196:196) (230:230:230)) - (PORT datad (809:809:809) (832:832:832)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (744:744:744)) - (PORT datab (874:874:874) (931:931:931)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (217:217:217) (255:255:255)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1036:1036:1036)) - (PORT datab (1285:1285:1285) (1323:1323:1323)) - (PORT datad (1367:1367:1367) (1447:1447:1447)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1476:1476:1476) (1478:1478:1478)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (905:905:905) (935:935:935)) - (PORT ena (1186:1186:1186) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (326:326:326)) - (PORT datab (959:959:959) (996:996:996)) - (PORT datad (880:880:880) (920:920:920)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (966:966:966) (1015:1015:1015)) - (PORT ena (1163:1163:1163) (1152:1152:1152)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1528:1528:1528)) - (PORT asdata (969:969:969) (1017:1017:1017)) - (PORT ena (1213:1213:1213) (1212:1212:1212)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (711:711:711)) - (PORT datab (378:378:378) (450:450:450)) - (PORT datad (620:620:620) (653:653:653)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (1052:1052:1052) (1055:1055:1055)) - (PORT datad (328:328:328) (344:344:344)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1215:1215:1215) (1257:1257:1257)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1488:1488:1488) (1562:1562:1562)) - (PORT datab (662:662:662) (713:713:713)) - (PORT datad (1636:1636:1636) (1747:1747:1747)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (846:846:846)) - (PORT datab (915:915:915) (949:949:949)) - (PORT datac (338:338:338) (359:359:359)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (644:644:644)) - (PORT datab (645:645:645) (697:697:697)) - (PORT datac (1345:1345:1345) (1373:1373:1373)) - (PORT datad (375:375:375) (406:406:406)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (866:866:866) (878:878:878)) - (PORT ena (1164:1164:1164) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (608:608:608)) - (PORT datab (622:622:622) (664:664:664)) - (PORT datac (425:425:425) (498:498:498)) - (PORT datad (563:563:563) (590:590:590)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (520:520:520)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (584:584:584) (613:613:613)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1538:1538:1538) (1606:1606:1606)) - (PORT datab (586:586:586) (605:605:605)) - (PORT datac (435:435:435) (481:481:481)) - (PORT datad (348:348:348) (372:372:372)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (902:902:902) (948:948:948)) - (PORT datac (775:775:775) (783:783:783)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datab (711:711:711) (744:744:744)) - (PORT datac (392:392:392) (466:466:466)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (887:887:887)) - (PORT datad (867:867:867) (907:907:907)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1559:1559:1559)) - (PORT ena (1762:1762:1762) (1780:1780:1780)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1143:1143:1143) (1199:1199:1199)) - (PORT datab (399:399:399) (474:474:474)) - (PORT datac (670:670:670) (691:691:691)) - (PORT datad (1153:1153:1153) (1200:1200:1200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (548:548:548) (605:605:605)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1542:1542:1542) (1611:1611:1611)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (431:431:431) (485:485:485)) - (PORT datad (526:526:526) (542:542:542)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (638:638:638)) - (PORT datab (400:400:400) (442:442:442)) - (PORT datac (1344:1344:1344) (1372:1372:1372)) - (PORT datad (551:551:551) (569:569:569)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1249:1249:1249)) - (PORT datab (882:882:882) (895:895:895)) - (PORT datac (567:567:567) (583:583:583)) - (PORT datad (1058:1058:1058) (1064:1064:1064)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (721:721:721)) - (PORT datab (1094:1094:1094) (1103:1103:1103)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (813:813:813) (871:871:871)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (491:491:491)) - (PORT datab (1860:1860:1860) (1955:1955:1955)) - (PORT datac (1054:1054:1054) (1101:1101:1101)) - (PORT datad (244:244:244) (315:315:315)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (861:861:861)) - (PORT datab (385:385:385) (404:404:404)) - (PORT datac (252:252:252) (308:308:308)) - (PORT datad (343:343:343) (357:357:357)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (431:431:431)) - (PORT datab (591:591:591) (610:610:610)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (857:857:857) (859:859:859)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (436:436:436)) - (PORT datab (285:285:285) (345:345:345)) - (PORT datad (856:856:856) (862:862:862)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (835:835:835) (870:870:870)) + (PORT datac (570:570:570) (586:586:586)) + (PORT datad (905:905:905) (965:965:965)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (869:869:869)) + (PORT datad (908:908:908) (970:970:970)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -24238,7 +10749,7 @@ (INSTANCE z80_\|alu_\|op1_high\[3\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT clk (1516:1516:1516) (1520:1520:1520)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -24251,29 +10762,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) (DELAY (ABSOLUTE - (PORT dataa (868:868:868) (926:926:926)) - (PORT datab (716:716:716) (777:777:777)) - (PORT datad (886:886:886) (910:910:910)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (703:703:703)) - (PORT datab (606:606:606) (624:624:624)) - (PORT datac (249:249:249) (307:307:307)) - (PORT datad (554:554:554) (572:572:572)) + (PORT dataa (916:916:916) (945:945:945)) + (PORT datab (1202:1202:1202) (1299:1299:1299)) + (PORT datac (1944:1944:1944) (2011:2011:2011)) + (PORT datad (902:902:902) (939:939:939)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24281,107 +10778,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) (DELAY (ABSOLUTE - (PORT datab (885:885:885) (899:899:899)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (608:608:608)) - (PORT datab (718:718:718) (786:786:786)) - (PORT datac (966:966:966) (1066:1066:1066)) - (PORT datad (995:995:995) (1046:1046:1046)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (723:723:723)) - (PORT datab (618:618:618) (649:649:649)) - (PORT datac (628:628:628) (663:663:663)) - (PORT datad (356:356:356) (387:387:387)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (532:532:532)) - (PORT datab (870:870:870) (896:896:896)) - (PORT datac (519:519:519) (536:536:536)) - (PORT datad (399:399:399) (466:466:466)) + (PORT dataa (1109:1109:1109) (1138:1138:1138)) + (PORT datab (700:700:700) (725:725:725)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (802:802:802) (809:809:809)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (497:497:497)) - (PORT datab (1023:1023:1023) (1072:1072:1072)) - (PORT datac (819:819:819) (866:866:866)) - (PORT datad (625:625:625) (636:636:636)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24389,103 +10794,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) (DELAY (ABSOLUTE - (PORT dataa (375:375:375) (399:399:399)) - (PORT datab (1228:1228:1228) (1318:1318:1318)) - (PORT datac (696:696:696) (757:757:757)) - (PORT datad (886:886:886) (912:912:912)) + (PORT dataa (1651:1651:1651) (1726:1726:1726)) + (PORT datab (1097:1097:1097) (1166:1166:1166)) + (PORT datac (629:629:629) (663:663:663)) + (PORT datad (685:685:685) (750:750:750)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT datac (383:383:383) (414:414:414)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (663:663:663)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (585:585:585) (600:600:600)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (456:456:456)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (328:328:328) (349:349:349)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT datab (646:646:646) (675:675:675)) - (PORT datac (810:810:810) (825:825:825)) - (PORT datad (655:655:655) (668:668:668)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (861:861:861)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (350:350:350) (366:366:366)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (668:668:668) (691:691:691)) - (PORT datac (842:842:842) (879:879:879)) - (PORT datad (931:931:931) (964:964:964)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -24493,521 +10810,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (1005:1005:1005)) - (PORT datab (216:216:216) (260:260:260)) - (PORT datac (547:547:547) (557:557:557)) - (PORT datad (1236:1236:1236) (1277:1277:1277)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1342:1342:1342)) - (PORT datab (2282:2282:2282) (2366:2366:2366)) - (PORT datac (1180:1180:1180) (1239:1239:1239)) - (PORT datad (1331:1331:1331) (1363:1363:1363)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (622:622:622)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1252:1252:1252) (1287:1287:1287)) - (PORT datad (952:952:952) (991:991:991)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (556:556:556)) - (PORT datab (854:854:854) (864:864:864)) - (PORT datac (547:547:547) (558:558:558)) - (PORT datad (610:610:610) (649:649:649)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (844:844:844) (872:872:872)) - (PORT datac (829:829:829) (842:842:842)) - (PORT datad (1173:1173:1173) (1229:1229:1229)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1899:1899:1899)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1834:1834:1834) (1965:1965:1965)) - (PORT datad (1601:1601:1601) (1748:1748:1748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1649:1649:1649) (1760:1760:1760)) - (PORT datac (1397:1397:1397) (1433:1433:1433)) - (PORT datad (2275:2275:2275) (2370:2370:2370)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (272:272:272) (362:362:362)) - (PORT datab (1863:1863:1863) (1958:1958:1958)) - (PORT datac (1087:1087:1087) (1133:1133:1133)) - (PORT datad (246:246:246) (318:318:318)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (359:359:359)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT datab (952:952:952) (1016:1016:1016)) - (PORT datac (1076:1076:1076) (1122:1122:1122)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1608:1608:1608) (1639:1639:1639)) - (PORT datab (964:964:964) (1002:1002:1002)) - (PORT datac (1030:1030:1030) (1064:1064:1064)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (694:694:694)) - (PORT datab (286:286:286) (344:344:344)) - (PORT datac (201:201:201) (239:239:239)) - (PORT datad (549:549:549) (567:567:567)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (884:884:884) (897:897:897)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (436:436:436) (530:530:530)) - (PORT datab (1590:1590:1590) (1672:1672:1672)) - (PORT datac (858:858:858) (922:922:922)) - (PORT datad (599:599:599) (660:660:660)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT asdata (669:669:669) (691:691:691)) - (PORT ena (1535:1535:1535) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (510:510:510)) - (PORT datab (586:586:586) (606:606:606)) - (PORT datac (850:850:850) (911:911:911)) - (PORT datad (240:240:240) (284:284:284)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (912:912:912)) - (PORT datab (367:367:367) (387:387:387)) - (PORT datad (598:598:598) (630:630:630)) + (PORT dataa (919:919:919) (972:972:972)) + (PORT datab (604:604:604) (618:618:618)) + (PORT datac (1984:1984:1984) (2057:2057:2057)) + (PORT datad (656:656:656) (676:676:676)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (859:859:859)) - (PORT datab (669:669:669) (685:685:685)) - (PORT datac (574:574:574) (583:583:583)) - (PORT datad (342:342:342) (354:354:354)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (991:991:991)) - (PORT datab (1072:1072:1072) (1137:1137:1137)) - (PORT datac (580:580:580) (650:650:650)) - (PORT datad (642:642:642) (673:673:673)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (726:726:726)) - (PORT datab (999:999:999) (1052:1052:1052)) - (PORT datac (627:627:627) (664:664:664)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (723:723:723)) - (PORT datab (665:665:665) (708:708:708)) - (PORT datac (575:575:575) (604:604:604)) - (PORT datad (972:972:972) (1013:1013:1013)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT datac (628:628:628) (662:662:662)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (528:528:528)) - (PORT datab (591:591:591) (625:625:625)) - (PORT datac (435:435:435) (513:513:513)) - (PORT datad (830:830:830) (856:856:856)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (304:304:304)) - (PORT datab (554:554:554) (570:570:570)) - (PORT datac (554:554:554) (586:586:586)) - (PORT datad (1081:1081:1081) (1087:1087:1087)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) (DELAY (ABSOLUTE - (PORT dataa (866:866:866) (892:892:892)) - (PORT datab (1082:1082:1082) (1083:1083:1083)) - (PORT datac (801:801:801) (808:808:808)) - (PORT datad (782:782:782) (795:795:795)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) - (DELAY - (ABSOLUTE - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (217:217:217) (261:261:261)) - (PORT datad (831:831:831) (859:859:859)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (217:217:217) (258:258:258)) - (PORT datad (832:832:832) (857:857:857)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1591:1591:1591)) - (PORT datab (1459:1459:1459) (1480:1480:1480)) - (PORT datac (1862:1862:1862) (1880:1880:1880)) - (PORT datad (1327:1327:1327) (1360:1360:1360)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1137:1137:1137)) - (PORT datab (1392:1392:1392) (1450:1450:1450)) - (PORT datac (798:798:798) (814:814:814)) - (PORT datad (1298:1298:1298) (1369:1369:1369)) + (PORT dataa (722:722:722) (771:771:771)) + (PORT datab (1595:1595:1595) (1710:1710:1710)) + (PORT datac (1544:1544:1544) (1685:1685:1685)) + (PORT datad (1542:1542:1542) (1642:1642:1642)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -25017,47 +10842,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) (DELAY (ABSOLUTE - (PORT dataa (1937:1937:1937) (2026:2026:2026)) - (PORT datab (212:212:212) (256:256:256)) - (PORT datac (1953:1953:1953) (2056:2056:2056)) - (PORT datad (1615:1615:1615) (1688:1688:1688)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (854:854:854) (917:917:917)) + (PORT datab (1067:1067:1067) (1089:1089:1089)) + (PORT datac (772:772:772) (784:784:784)) + (PORT datad (822:822:822) (889:889:889)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1152:1152:1152)) - (PORT datab (370:370:370) (396:396:396)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (824:824:824) (863:863:863)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (343:343:343) (381:381:381)) + (PORT datab (601:601:601) (618:618:618)) + (PORT datac (543:543:543) (563:563:563)) + (PORT datad (1344:1344:1344) (1425:1425:1425)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (528:528:528) (540:540:540)) - (PORT datad (580:580:580) (593:593:593)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (1871:1871:1871) (2039:2039:2039)) + (PORT datab (1543:1543:1543) (1671:1671:1671)) + (PORT datac (817:817:817) (835:835:835)) + (PORT datad (1851:1851:1851) (1930:1930:1930)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -25065,45 +10890,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (INSTANCE z80_\|pla_decode_\|Equal21\~2) (DELAY (ABSOLUTE - (PORT datab (1770:1770:1770) (1810:1810:1810)) - (PORT datac (1173:1173:1173) (1220:1220:1220)) - (PORT datad (1440:1440:1440) (1461:1461:1461)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1425:1425:1425) (1503:1503:1503)) + (PORT datac (218:218:218) (262:262:262)) + (PORT datad (986:986:986) (1086:1086:1086)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (340:340:340)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (254:254:254) (313:313:313)) - (PORT datad (1200:1200:1200) (1271:1271:1271)) + (PORT dataa (857:857:857) (897:897:897)) + (PORT datab (966:966:966) (1008:1008:1008)) + (PORT datac (1944:1944:1944) (2015:2015:2015)) + (PORT datad (1176:1176:1176) (1235:1235:1235)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2211:2211:2211) (2401:2401:2401)) - (PORT datab (1578:1578:1578) (1721:1721:1721)) - (PORT datac (1756:1756:1756) (1850:1850:1850)) - (PORT datad (857:857:857) (888:888:888)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -25111,109 +10920,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (1859:1859:1859) (1955:1955:1955)) - (PORT datac (605:605:605) (631:631:631)) - (PORT datad (944:944:944) (992:992:992)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1804:1804:1804) (1902:1902:1902)) - (PORT datab (1429:1429:1429) (1461:1461:1461)) - (PORT datac (1430:1430:1430) (1464:1464:1464)) - (PORT datad (2319:2319:2319) (2472:2472:2472)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1547:1547:1547) (1642:1642:1642)) - (PORT datab (1225:1225:1225) (1267:1267:1267)) - (PORT datac (1428:1428:1428) (1462:1462:1462)) - (PORT datad (1636:1636:1636) (1711:1711:1711)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1464:1464:1464) (1499:1499:1499)) - (PORT datab (684:684:684) (724:724:724)) - (PORT datac (1191:1191:1191) (1233:1233:1233)) - (PORT datad (1662:1662:1662) (1693:1693:1693)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (671:671:671)) - (PORT datab (2007:2007:2007) (2122:2122:2122)) - (PORT datac (1547:1547:1547) (1649:1649:1649)) - (PORT datad (2319:2319:2319) (2472:2472:2472)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1548:1548:1548) (1643:1643:1643)) - (PORT datab (680:680:680) (721:721:721)) - (PORT datac (1534:1534:1534) (1622:1622:1622)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (681:681:681) (728:728:728)) - (PORT datac (2002:2002:2002) (2034:2034:2034)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1128:1128:1128) (1164:1164:1164)) + (PORT datab (923:923:923) (985:985:985)) + (PORT datac (380:380:380) (415:415:415)) + (PORT datad (613:613:613) (634:634:634)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -25223,3413 +10936,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_alu_op_low) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (378:378:378)) - (PORT datab (375:375:375) (401:401:401)) - (PORT datac (317:317:317) (348:348:348)) - (PORT datad (875:875:875) (912:912:912)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (698:698:698)) - (PORT datab (643:643:643) (669:669:669)) - (PORT datac (1186:1186:1186) (1232:1232:1232)) - (PORT datad (366:366:366) (388:388:388)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (986:986:986)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (1404:1404:1404) (1439:1439:1439)) - (PORT datad (619:619:619) (649:649:649)) + (PORT dataa (661:661:661) (702:702:702)) + (PORT datab (893:893:893) (935:935:935)) + (PORT datac (1566:1566:1566) (1576:1576:1576)) + (PORT datad (179:179:179) (209:209:209)) (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (704:704:704)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1184:1184:1184) (1224:1224:1224)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (680:680:680)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (581:581:581) (598:598:598)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1590:1590:1590)) - (PORT datab (1459:1459:1459) (1480:1480:1480)) - (PORT datac (1045:1045:1045) (1092:1092:1092)) - (PORT datad (1326:1326:1326) (1360:1360:1360)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (927:927:927) (983:983:983)) - (PORT datac (900:900:900) (967:967:967)) - (PORT datad (2255:2255:2255) (2330:2330:2330)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1389:1389:1389)) - (PORT datab (1282:1282:1282) (1317:1317:1317)) - (PORT datac (903:903:903) (968:968:968)) - (PORT datad (1147:1147:1147) (1224:1224:1224)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1478:1478:1478)) - (PORT datab (991:991:991) (1033:1033:1033)) - (PORT datac (382:382:382) (406:406:406)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (399:399:399)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (523:523:523) (528:528:528)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (896:896:896)) - (PORT datab (650:650:650) (675:675:675)) - (PORT datac (342:342:342) (365:365:365)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (882:882:882)) - (PORT datab (639:639:639) (683:683:683)) - (PORT datac (811:811:811) (813:813:813)) - (PORT datad (1234:1234:1234) (1284:1284:1284)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (704:704:704)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (554:554:554) (564:564:564)) - (PORT datac (178:178:178) (216:216:216)) - (PORT datad (584:584:584) (600:600:600)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (549:549:549)) - (PORT datab (1591:1591:1591) (1671:1671:1671)) - (PORT datac (998:998:998) (1082:1082:1082)) - (PORT datad (844:844:844) (897:897:897)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (726:726:726) (802:802:802)) - (PORT datac (204:204:204) (242:242:242)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (712:712:712)) - (PORT datab (1350:1350:1350) (1417:1417:1417)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (674:674:674)) - (PORT datab (413:413:413) (463:463:463)) - (PORT datac (854:854:854) (913:913:913)) - (PORT datad (244:244:244) (285:285:285)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (878:878:878)) - (PORT datab (1313:1313:1313) (1370:1370:1370)) - (PORT datac (768:768:768) (840:840:840)) - (PORT datad (753:753:753) (788:788:788)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (915:915:915)) - (PORT datab (354:354:354) (384:384:384)) - (PORT datac (570:570:570) (580:580:580)) - (PORT datad (640:640:640) (657:657:657)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (692:692:692)) - (PORT datab (288:288:288) (346:346:346)) - (PORT datad (853:853:853) (857:857:857)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (1027:1027:1027) (1080:1080:1080)) - (PORT datac (998:998:998) (1082:1082:1082)) - (PORT datad (598:598:598) (658:658:658)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (524:524:524)) - (PORT datab (593:593:593) (621:621:621)) - (PORT datac (435:435:435) (509:509:509)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (867:867:867) (892:892:892)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (587:587:587) (604:604:604)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (302:302:302)) - (PORT datab (256:256:256) (302:302:302)) - (PORT datac (525:525:525) (539:539:539)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (455:455:455)) - (PORT datab (394:394:394) (418:418:418)) - (PORT datac (381:381:381) (403:403:403)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (407:407:407)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (587:587:587) (602:602:602)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (612:612:612) (629:629:629)) - (PORT datac (184:184:184) (224:224:224)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT asdata (558:558:558) (589:589:589)) - (PORT ena (1535:1535:1535) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (379:379:379) (448:448:448)) - (PORT datad (845:845:845) (867:867:867)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (961:961:961)) - (PORT datab (715:715:715) (786:786:786)) - (PORT datac (1555:1555:1555) (1630:1630:1630)) - (PORT datad (399:399:399) (466:466:466)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (500:500:500)) - (PORT datad (602:602:602) (625:625:625)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (836:836:836)) - (PORT datab (1100:1100:1100) (1140:1140:1140)) - (PORT datac (379:379:379) (412:412:412)) - (PORT datad (895:895:895) (920:920:920)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (808:808:808)) - (PORT datab (676:676:676) (693:693:693)) - (PORT datac (345:345:345) (369:369:369)) - (PORT datad (327:327:327) (345:345:345)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1118:1118:1118)) - (PORT datab (884:884:884) (901:901:901)) - (PORT datac (1027:1027:1027) (1078:1078:1078)) - (PORT datad (981:981:981) (1014:1014:1014)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (683:683:683)) - (PORT datab (1094:1094:1094) (1101:1101:1101)) - (PORT datac (530:530:530) (542:542:542)) - (PORT datad (658:658:658) (677:677:677)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (662:662:662)) - (PORT datab (676:676:676) (735:735:735)) - (PORT datac (1314:1314:1314) (1328:1328:1328)) - (PORT datad (1142:1142:1142) (1172:1172:1172)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1027:1027:1027) (1032:1032:1032)) - (PORT datab (1108:1108:1108) (1163:1163:1163)) - (PORT datad (1085:1085:1085) (1076:1076:1076)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (384:384:384) (458:458:458)) - (PORT datac (379:379:379) (440:440:440)) - (PORT datad (386:386:386) (446:446:446)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1041:1041:1041)) - (PORT datab (2280:2280:2280) (2375:2375:2375)) - (PORT datad (2190:2190:2190) (2361:2361:2361)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (605:605:605) (655:655:655)) - (PORT datac (802:802:802) (820:820:820)) - (PORT datad (1419:1419:1419) (1423:1423:1423)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1395:1395:1395) (1451:1451:1451)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1286:1286:1286)) - (PORT datab (947:947:947) (992:992:992)) - (PORT datac (1206:1206:1206) (1235:1235:1235)) - (PORT datad (1186:1186:1186) (1199:1199:1199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (346:346:346)) - (PORT datab (1765:1765:1765) (1806:1806:1806)) - (PORT datac (247:247:247) (305:305:305)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (671:671:671)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (1094:1094:1094) (1107:1107:1107)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (885:885:885)) - (PORT datab (910:910:910) (959:959:959)) - (PORT datac (827:827:827) (862:862:862)) - (PORT datad (816:816:816) (839:839:839)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (906:906:906)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (630:630:630) (665:665:665)) - (PORT datad (625:625:625) (641:641:641)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (864:864:864)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (885:885:885) (913:913:913)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (328:328:328)) - (PORT datab (1135:1135:1135) (1215:1215:1215)) - (PORT datad (1221:1221:1221) (1258:1258:1258)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (547:547:547) (582:582:582)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (923:923:923) (953:953:953)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (847:847:847)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1256:1256:1256)) - (PORT datab (682:682:682) (747:747:747)) - (PORT datad (875:875:875) (945:945:945)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (625:625:625) (679:679:679)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (547:547:547) (582:582:582)) - (PORT ena (1275:1275:1275) (1314:1314:1314)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (787:787:787)) - (PORT datab (729:729:729) (781:781:781)) - (PORT datad (1021:1021:1021) (1061:1061:1061)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (680:680:680)) - (PORT datab (611:611:611) (638:638:638)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (412:412:412)) - (PORT datab (612:612:612) (639:639:639)) - (PORT datac (309:309:309) (325:325:325)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (262:262:262)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (816:816:816) (831:831:831)) - (PORT datad (1118:1118:1118) (1134:1134:1134)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1241:1241:1241) (1251:1251:1251)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1126:1126:1126)) - (PORT datab (219:219:219) (259:259:259)) - (PORT datad (1117:1117:1117) (1141:1141:1141)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (624:624:624) (639:639:639)) - (PORT datac (666:666:666) (695:695:695)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (450:450:450)) - (PORT datab (626:626:626) (654:654:654)) - (PORT datac (1197:1197:1197) (1250:1250:1250)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1140:1140:1140)) - (PORT datad (880:880:880) (895:895:895)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1362:1362:1362)) - (PORT datad (370:370:370) (394:394:394)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT asdata (934:934:934) (951:951:951)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (PORT ena (2020:2020:2020) (2056:2056:2056)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (673:673:673)) - (PORT datab (614:614:614) (636:636:636)) - (PORT datac (590:590:590) (657:657:657)) - (PORT datad (665:665:665) (729:729:729)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (617:617:617) (639:639:639)) - (PORT datac (613:613:613) (666:666:666)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1222:1222:1222) (1224:1224:1224)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (950:950:950) (978:978:978)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (950:950:950) (976:976:976)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (316:316:316)) - (PORT datab (1080:1080:1080) (1115:1115:1115)) - (PORT datad (355:355:355) (415:415:415)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1773:1773:1773) (1846:1846:1846)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1773:1773:1773) (1845:1845:1845)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (244:244:244) (292:292:292)) - (PORT datad (211:211:211) (244:244:244)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1770:1770:1770) (1824:1824:1824)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1253:1253:1253)) - (PORT datab (675:675:675) (717:717:717)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1772:1772:1772) (1824:1824:1824)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (456:456:456)) - (PORT datab (195:195:195) (234:234:234)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1111:1111:1111) (1133:1133:1133)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (327:327:327)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (1377:1377:1377) (1480:1480:1480)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (953:953:953) (981:981:981)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (953:953:953) (981:981:981)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (661:661:661)) - (PORT datab (942:942:942) (999:999:999)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (849:849:849)) - (PORT datab (643:643:643) (660:660:660)) - (PORT datac (593:593:593) (636:636:636)) - (PORT datad (620:620:620) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1238:1238:1238)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1221:1221:1221) (1239:1239:1239)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (459:459:459)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (417:417:417) (449:449:449)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (699:699:699)) - (PORT datab (864:864:864) (869:869:869)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (896:896:896)) - (PORT datab (400:400:400) (430:430:430)) - (PORT datac (1133:1133:1133) (1187:1187:1187)) - (PORT datad (666:666:666) (703:703:703)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1521:1521:1521)) - (PORT datab (675:675:675) (709:709:709)) - (PORT datad (326:326:326) (344:344:344)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (635:635:635)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (606:606:606) (629:629:629)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (894:894:894)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1210:1210:1210) (1264:1264:1264)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1140:1140:1140)) - (PORT datad (625:625:625) (641:641:641)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1181:1181:1181)) - (PORT datab (1473:1473:1473) (1524:1524:1524)) - (PORT datac (1184:1184:1184) (1245:1245:1245)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (623:623:623)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (624:624:624) (671:671:671)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1466:1466:1466) (1490:1490:1490)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1462:1462:1462) (1486:1486:1486)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (308:308:308)) - (PORT datab (1080:1080:1080) (1120:1120:1120)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1250:1250:1250)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1249:1249:1249)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (463:463:463)) - (PORT datab (449:449:449) (477:477:477)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1192:1192:1192) (1211:1211:1211)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1274:1274:1274) (1361:1361:1361)) - (PORT datab (1009:1009:1009) (1055:1055:1055)) - (PORT datad (895:895:895) (946:946:946)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1870:1870:1870) (1916:1916:1916)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (322:322:322)) - (PORT datab (1137:1137:1137) (1215:1215:1215)) - (PORT datad (855:855:855) (880:880:880)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (970:970:970) (997:997:997)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (958:958:958) (996:996:996)) - (PORT ena (1275:1275:1275) (1314:1314:1314)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1226:1226:1226)) - (PORT datab (725:725:725) (775:775:775)) - (PORT datad (1020:1020:1020) (1061:1061:1061)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (958:958:958) (999:999:999)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1252:1252:1252)) - (PORT datab (676:676:676) (740:740:740)) - (PORT datad (656:656:656) (714:714:714)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (692:692:692)) - (PORT datab (643:643:643) (692:692:692)) - (PORT datac (572:572:572) (583:583:583)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1247:1247:1247) (1278:1278:1278)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (640:640:640) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (660:660:660)) - (PORT datab (942:942:942) (998:998:998)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (649:649:649)) - (PORT datab (327:327:327) (355:355:355)) - (PORT datac (341:341:341) (363:363:363)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (685:685:685)) - (PORT datab (701:701:701) (738:738:738)) - (PORT datac (1136:1136:1136) (1185:1185:1185)) - (PORT datad (522:522:522) (540:540:540)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (848:848:848) (860:860:860)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1518:1518:1518)) - (PORT datab (384:384:384) (417:417:417)) - (PORT datad (643:643:643) (665:665:665)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (734:734:734)) - (PORT datab (332:332:332) (360:360:360)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (874:874:874)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1197:1197:1197) (1251:1251:1251)) - (PORT datad (383:383:383) (403:403:403)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datab (802:802:802) (828:828:828)) - (PORT datad (1064:1064:1064) (1089:1089:1089)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (876:876:876) (905:905:905)) - (PORT datac (623:623:623) (669:669:669)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (579:579:579) (585:585:585)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1247:1247:1247)) - (PORT datab (907:907:907) (936:936:936)) - (PORT datac (385:385:385) (451:451:451)) - (PORT datad (914:914:914) (972:972:972)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (894:894:894) (915:915:915)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (694:694:694)) - (PORT datab (622:622:622) (668:668:668)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (608:608:608) (648:648:648)) - (PORT datad (418:418:418) (490:490:490)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (406:406:406)) - (PORT datab (403:403:403) (433:433:433)) - (PORT datac (434:434:434) (479:479:479)) - (PORT datad (1502:1502:1502) (1569:1569:1569)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (656:656:656)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (550:550:550) (571:571:571)) - (PORT datad (1321:1321:1321) (1374:1374:1374)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (909:909:909)) - (PORT datab (873:873:873) (928:928:928)) - (PORT datac (632:632:632) (677:677:677)) - (PORT datad (805:805:805) (833:833:833)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1808:1808:1808) (1853:1853:1853)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (572:572:572) (589:589:589)) - (PORT datad (220:220:220) (259:259:259)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (912:912:912)) - (PORT datad (809:809:809) (836:836:836)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (1225:1225:1225) (1265:1265:1265)) - (PORT datac (878:878:878) (918:918:918)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (900:900:900)) - (PORT datab (1164:1164:1164) (1207:1207:1207)) - (PORT datac (1156:1156:1156) (1177:1177:1177)) - (PORT datad (612:612:612) (661:661:661)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1256:1256:1256)) - (PORT datab (676:676:676) (714:714:714)) - (PORT datad (1092:1092:1092) (1117:1117:1117)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT asdata (1354:1354:1354) (1395:1395:1395)) - (PORT ena (1263:1263:1263) (1252:1252:1252)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1381:1381:1381)) - (PORT datab (920:920:920) (933:933:933)) - (PORT datad (1369:1369:1369) (1414:1414:1414)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1193:1193:1193) (1215:1215:1215)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1187:1187:1187) (1217:1217:1217)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1189:1189:1189) (1217:1217:1217)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (464:464:464)) - (PORT datab (450:450:450) (488:488:488)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (832:832:832)) - (PORT datab (631:631:631) (666:666:666)) - (PORT datad (614:614:614) (639:639:639)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (992:992:992) (1028:1028:1028)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (990:990:990) (1027:1027:1027)) - (PORT ena (961:961:961) (970:970:970)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (459:459:459)) - (PORT datab (245:245:245) (293:293:293)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1181:1181:1181) (1196:1196:1196)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1178:1178:1178) (1193:1193:1193)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (330:330:330)) - (PORT datab (1409:1409:1409) (1523:1523:1523)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (605:605:605) (642:642:642)) - (PORT datac (377:377:377) (418:418:418)) - (PORT datad (312:312:312) (331:331:331)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (676:676:676)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (522:522:522) (536:536:536)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1068:1068:1068)) - (PORT datab (1183:1183:1183) (1199:1199:1199)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (660:660:660) (693:693:693)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1154:1154:1154) (1163:1163:1163)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1517:1517:1517)) - (PORT datab (1185:1185:1185) (1225:1225:1225)) - (PORT datad (651:651:651) (673:673:673)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (370:370:370)) - (PORT datac (665:665:665) (694:694:694)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (444:444:444)) - (PORT datab (220:220:220) (257:257:257)) - (PORT datac (1193:1193:1193) (1246:1246:1246)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (880:880:880) (936:936:936)) - (PORT datad (786:786:786) (788:788:788)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1451:1451:1451) (1493:1493:1493)) - (PORT datab (1095:1095:1095) (1151:1151:1151)) - (PORT datac (670:670:670) (690:690:690)) - (PORT datad (1103:1103:1103) (1138:1138:1138)) - (IOPATH dataa combout (350:350:350) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (746:746:746)) - (PORT datab (1400:1400:1400) (1451:1451:1451)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (1354:1354:1354) (1397:1397:1397)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1252:1252:1252) (1240:1240:1240)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1457:1457:1457) (1516:1516:1516)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1460:1460:1460) (1519:1519:1519)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (462:462:462)) - (PORT datab (449:449:449) (476:476:476)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (989:989:989) (1030:1030:1030)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1552:1552:1552)) - (PORT asdata (1378:1378:1378) (1437:1437:1437)) - (PORT ena (841:841:841) (847:847:847)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1254:1254:1254)) - (PORT datab (678:678:678) (743:743:743)) - (PORT datad (876:876:876) (941:941:941)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (1476:1476:1476) (1497:1497:1497)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1423:1423:1423) (1461:1461:1461)) - (PORT ena (1243:1243:1243) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (768:768:768)) - (PORT datab (677:677:677) (714:714:714)) - (PORT datad (632:632:632) (658:658:658)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1422:1422:1422) (1461:1461:1461)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (461:461:461)) - (PORT datab (195:195:195) (234:234:234)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (911:911:911) (922:922:922)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (965:965:965)) - (PORT datab (1338:1338:1338) (1383:1383:1383)) - (PORT datac (840:840:840) (853:853:853)) - (PORT datad (840:840:840) (891:891:891)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (375:375:375)) - (PORT datab (619:619:619) (654:654:654)) - (PORT datad (319:319:319) (337:337:337)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (931:931:931) (962:962:962)) - (PORT ena (1426:1426:1426) (1409:1409:1409)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (587:587:587) (620:620:620)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (318:318:318)) - (PORT datab (1080:1080:1080) (1113:1113:1113)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1220:1220:1220) (1247:1247:1247)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (641:641:641) (675:675:675)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (940:940:940) (1003:1003:1003)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (525:525:525) (543:543:543)) - (PORT datab (371:371:371) (391:391:391)) - (PORT datac (833:833:833) (839:839:839)) - (PORT datad (313:313:313) (322:322:322)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (843:843:843)) - (PORT datab (573:573:573) (588:588:588)) - (PORT datac (1136:1136:1136) (1189:1189:1189)) - (PORT datad (665:665:665) (698:698:698)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (850:850:850) (858:858:858)) - (PORT ena (1237:1237:1237) (1220:1220:1220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1517:1517:1517)) - (PORT datab (384:384:384) (414:414:414)) - (PORT datad (644:644:644) (664:664:664)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (735:735:735)) - (PORT datac (217:217:217) (294:294:294)) - (PORT datad (334:334:334) (353:353:353)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (446:446:446)) - (PORT datab (1227:1227:1227) (1282:1282:1282)) - (PORT datac (178:178:178) (215:215:215)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1359:1359:1359)) - (PORT datad (533:533:533) (544:544:544)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (565:565:565) (575:575:575)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (745:745:745)) - (PORT datab (1138:1138:1138) (1179:1179:1179)) - (PORT datac (669:669:669) (689:689:689)) - (PORT datad (1408:1408:1408) (1445:1445:1445)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (1399:1399:1399) (1450:1450:1450)) - (PORT datac (1371:1371:1371) (1414:1414:1414)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (678:678:678)) - (PORT datab (615:615:615) (637:637:637)) - (PORT datac (592:592:592) (659:659:659)) - (PORT datad (667:667:667) (730:730:730)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1239:1239:1239) (1295:1295:1295)) - (PORT datac (880:880:880) (914:914:914)) - (PORT datad (215:215:215) (249:249:249)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (368:368:368)) - (PORT datab (707:707:707) (740:740:740)) - (PORT datac (1132:1132:1132) (1184:1184:1184)) - (PORT datad (367:367:367) (391:391:391)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (630:630:630)) - (PORT datab (412:412:412) (440:440:440)) - (PORT datac (542:542:542) (555:555:555)) - (PORT datad (611:611:611) (637:637:637)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datab (1115:1115:1115) (1142:1142:1142)) - (PORT datac (844:844:844) (866:866:866)) - (PORT datad (341:341:341) (362:362:362)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (300:300:300)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (572:572:572) (590:590:590)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (744:744:744) (833:833:833)) - (PORT datac (206:206:206) (244:244:244)) - (PORT datad (220:220:220) (248:248:248)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (945:945:945)) - (PORT datab (674:674:674) (710:710:710)) - (PORT datac (1356:1356:1356) (1400:1400:1400)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT asdata (889:889:889) (895:895:895)) - (PORT ena (1615:1615:1615) (1626:1626:1626)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (979:979:979)) - (PORT datab (1586:1586:1586) (1671:1671:1671)) - (PORT datac (857:857:857) (920:920:920)) - (PORT datad (419:419:419) (492:492:492)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (873:873:873)) - (PORT datab (262:262:262) (317:317:317)) - (PORT datac (849:849:849) (911:911:911)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (874:874:874)) - (PORT datab (880:880:880) (945:945:945)) - (PORT datad (741:741:741) (783:783:783)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~26) - (DELAY - (ABSOLUTE - (PORT datab (1309:1309:1309) (1365:1365:1365)) - (PORT datac (209:209:209) (249:249:249)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28640,13 +10955,13 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) (DELAY (ABSOLUTE - (PORT dataa (924:924:924) (999:999:999)) - (PORT datab (1075:1075:1075) (1142:1142:1142)) - (PORT datac (885:885:885) (962:962:962)) - (PORT datad (648:648:648) (680:680:680)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (957:957:957) (1021:1021:1021)) + (PORT datab (1200:1200:1200) (1249:1249:1249)) + (PORT datac (877:877:877) (942:942:942)) + (PORT datad (1050:1050:1050) (1128:1128:1128)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28656,13 +10971,27 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) (DELAY (ABSOLUTE - (PORT dataa (673:673:673) (726:726:726)) - (PORT datab (844:844:844) (863:863:863)) - (PORT datac (626:626:626) (661:661:661)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1071:1071:1071) (1104:1104:1104)) + (PORT datab (857:857:857) (876:876:876)) + (PORT datac (613:613:613) (644:644:644)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT datab (1203:1203:1203) (1256:1256:1256)) + (PORT datac (1140:1140:1140) (1175:1175:1175)) + (PORT datad (823:823:823) (838:838:838)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28672,9 +11001,9 @@ (INSTANCE z80_\|alu_\|op2_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT clk (1517:1517:1517) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -28685,119 +11014,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (INSTANCE z80_\|alu_\|db_low\[3\]\~2) (DELAY (ABSOLUTE - (PORT dataa (668:668:668) (724:724:724)) - (PORT datab (849:849:849) (909:909:909)) - (PORT datac (819:819:819) (834:834:834)) - (PORT datad (635:635:635) (671:671:671)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (665:665:665)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (536:536:536)) - (PORT datab (592:592:592) (622:622:622)) - (PORT datac (651:651:651) (713:713:713)) - (PORT datad (832:832:832) (855:855:855)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (387:387:387)) - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (180:180:180) (209:209:209)) + (PORT dataa (1375:1375:1375) (1489:1489:1489)) + (PORT datab (1718:1718:1718) (1749:1749:1749)) + (PORT datac (359:359:359) (424:424:424)) + (PORT datad (679:679:679) (728:728:728)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (390:390:390)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (344:344:344) (373:373:373)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (719:719:719)) - (PORT datab (857:857:857) (902:902:902)) - (PORT datac (2037:2037:2037) (2075:2075:2075)) - (PORT datad (827:827:827) (920:920:920)) - (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (953:953:953) (1017:1017:1017)) - (PORT datac (663:663:663) (701:701:701)) - (PORT datad (629:629:629) (658:658:658)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28805,544 +11030,119 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (INSTANCE z80_\|alu_\|db_low\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1608:1608:1608) (1638:1638:1638)) - (PORT datab (724:724:724) (761:761:761)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (970:970:970) (1003:1003:1003)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (514:514:514)) - (PORT datab (266:266:266) (322:322:322)) - (PORT datad (605:605:605) (629:629:629)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (647:647:647)) - (PORT datab (587:587:587) (595:595:595)) - (PORT datac (850:850:850) (906:906:906)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (925:925:925) (946:946:946)) + (PORT datab (634:634:634) (654:654:654)) + (PORT datac (1297:1297:1297) (1364:1364:1364)) + (PORT datad (884:884:884) (899:899:899)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) (DELAY (ABSOLUTE - (PORT dataa (577:577:577) (594:594:594)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1677:1677:1677) (1734:1734:1734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (965:965:965)) + (PORT datac (806:806:806) (841:841:841)) + (PORT datad (374:374:374) (429:429:429)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2224:2224:2224) (2316:2316:2316)) (PORT datab (227:227:227) (269:269:269)) - (PORT datac (843:843:843) (914:914:914)) - (PORT datad (777:777:777) (827:827:827)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (729:729:729)) - (PORT datab (1152:1152:1152) (1160:1160:1160)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (538:538:538) (551:551:551)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1889:1889:1889)) - (PORT datab (205:205:205) (246:246:246)) - (PORT datac (885:885:885) (932:932:932)) - (PORT datad (330:330:330) (354:354:354)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1134:1134:1134)) - (PORT datab (1396:1396:1396) (1456:1456:1456)) - (PORT datac (796:796:796) (811:811:811)) - (PORT datad (563:563:563) (577:577:577)) + (PORT datac (918:918:918) (934:934:934)) + (PORT datad (186:186:186) (218:218:218)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (823:823:823)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (1051:1051:1051) (1079:1079:1079)) - (PORT datad (1041:1041:1041) (1076:1076:1076)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (268:268:268)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (601:601:601) (617:617:617)) - (PORT datad (589:589:589) (602:602:602)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (990:990:990)) - (PORT datab (932:932:932) (968:968:968)) - (PORT datac (1207:1207:1207) (1265:1265:1265)) - (PORT datad (620:620:620) (652:652:652)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (859:859:859) (877:877:877)) - (PORT datad (619:619:619) (659:659:659)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (1534:1534:1534) (1581:1581:1581)) - (PORT datac (1206:1206:1206) (1250:1250:1250)) - (PORT datad (685:685:685) (739:739:739)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) - (DELAY - (ABSOLUTE - (PORT datac (186:186:186) (225:225:225)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (827:827:827)) - (PORT datab (362:362:362) (398:398:398)) - (PORT datac (521:521:521) (537:537:537)) - (PORT datad (812:812:812) (823:823:823)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (663:663:663)) - (PORT datab (666:666:666) (681:681:681)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (640:640:640)) - (PORT datab (1418:1418:1418) (1463:1463:1463)) - (PORT datac (1454:1454:1454) (1487:1487:1487)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1281:1281:1281)) - (PORT datab (1419:1419:1419) (1462:1462:1462)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (831:831:831) (848:848:848)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1013:1013:1013)) - (PORT datab (1181:1181:1181) (1227:1227:1227)) - (PORT datac (632:632:632) (648:648:648)) - (PORT datad (1362:1362:1362) (1411:1411:1411)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (848:848:848)) - (PORT datab (1395:1395:1395) (1453:1453:1453)) - (PORT datac (1074:1074:1074) (1096:1096:1096)) - (PORT datad (1683:1683:1683) (1743:1743:1743)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (1811:1811:1811) (1879:1879:1879)) - (PORT datab (676:676:676) (715:715:715)) - (PORT datac (1045:1045:1045) (1109:1109:1109)) - (PORT datad (333:333:333) (359:359:359)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (875:875:875)) - (PORT datab (631:631:631) (658:658:658)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (617:617:617) (665:665:665)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (570:570:570)) - (PORT datab (641:641:641) (662:662:662)) - (PORT datac (570:570:570) (588:588:588)) - (PORT datad (321:321:321) (344:344:344)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (946:946:946)) - (PORT datab (1101:1101:1101) (1148:1148:1148)) - (PORT datac (813:813:813) (870:870:870)) - (PORT datad (589:589:589) (601:601:601)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (943:943:943)) - (PORT datab (440:440:440) (502:502:502)) - (PORT datac (322:322:322) (346:346:346)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT datab (956:956:956) (1019:1019:1019)) - (PORT datac (686:686:686) (722:722:722)) - (PORT datad (935:935:935) (962:962:962)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (710:710:710)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (616:616:616) (639:639:639)) - (PORT datad (1569:1569:1569) (1593:1593:1593)) - (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (879:879:879)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (222:222:222) (303:303:303)) - (PORT datad (174:174:174) (199:199:199)) + (PORT datac (1209:1209:1209) (1285:1285:1285)) + (PORT datad (2183:2183:2183) (2383:2383:2383)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1395:1395:1395)) + (PORT datab (971:971:971) (1027:1027:1027)) + (PORT datac (983:983:983) (1037:1037:1037)) + (PORT datad (1203:1203:1203) (1284:1284:1284)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1379:1379:1379)) + (PORT datab (1102:1102:1102) (1129:1129:1129)) + (PORT datad (991:991:991) (1084:1084:1084)) (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (880:880:880)) - (PORT datab (350:350:350) (384:384:384)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1571:1571:1571) (1597:1597:1597)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1404:1404:1404) (1572:1572:1572)) - (PORT datab (2576:2576:2576) (2768:2768:2768)) - (PORT datac (1211:1211:1211) (1292:1292:1292)) - (PORT datad (1321:1321:1321) (1487:1487:1487)) + (PORT dataa (1306:1306:1306) (1445:1445:1445)) + (PORT datab (908:908:908) (952:952:952)) + (PORT datac (936:936:936) (1031:1031:1031)) + (PORT datad (1386:1386:1386) (1511:1511:1511)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (436:436:436)) - (PORT datab (642:642:642) (698:698:698)) - (PORT datac (1721:1721:1721) (1770:1770:1770)) - (PORT datad (842:842:842) (847:847:847)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (688:688:688)) - (PORT datab (673:673:673) (705:705:705)) - (PORT datad (1121:1121:1121) (1149:1149:1149)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1852:1852:1852) (1960:1960:1960)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (811:811:811) (834:834:834)) - (PORT datad (1186:1186:1186) (1218:1218:1218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1152:1152:1152)) - (PORT datab (850:850:850) (888:888:888)) - (PORT datac (1161:1161:1161) (1194:1194:1194)) - (PORT datad (1113:1113:1113) (1135:1135:1135)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29350,31 +11150,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (250:250:250) (340:340:340)) - (PORT datab (260:260:260) (342:342:342)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (853:853:853) (853:853:853)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1071:1071:1071)) - (PORT datab (877:877:877) (903:903:903)) - (PORT datac (1043:1043:1043) (1136:1136:1136)) - (PORT datad (1269:1269:1269) (1356:1356:1356)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (852:852:852) (893:893:893)) + (PORT datac (930:930:930) (980:980:980)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29382,185 +11164,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (283:283:283)) - (PORT datab (1397:1397:1397) (1493:1493:1493)) - (PORT datac (1951:1951:1951) (2029:2029:2029)) - (PORT datad (909:909:909) (935:935:935)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (994:994:994) (1065:1065:1065)) - (PORT datac (1181:1181:1181) (1238:1238:1238)) - (PORT datad (1433:1433:1433) (1519:1519:1519)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1166:1166:1166)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (638:638:638) (669:669:669)) - (PORT datad (883:883:883) (915:915:915)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (689:689:689)) - (PORT datab (1238:1238:1238) (1272:1272:1272)) - (PORT datac (185:185:185) (224:224:224)) - (PORT datad (633:633:633) (665:665:665)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (665:665:665)) - (PORT datab (628:628:628) (640:640:640)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (320:320:320) (341:341:341)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT datac (962:962:962) (1026:1026:1026)) - (PORT datad (841:841:841) (860:860:860)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (629:629:629) (639:639:639)) - (PORT datac (207:207:207) (246:246:246)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (941:941:941)) - (PORT datab (1982:1982:1982) (2090:2090:2090)) - (PORT datac (1348:1348:1348) (1372:1372:1372)) - (PORT datad (2100:2100:2100) (2296:2296:2296)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (906:906:906)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (217:217:217) (260:260:260)) - (PORT datad (196:196:196) (229:229:229)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (914:914:914)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1205:1205:1205) (1266:1266:1266)) - (PORT datad (904:904:904) (932:932:932)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (1175:1175:1175) (1240:1240:1240)) - (PORT datad (184:184:184) (215:215:215)) + (PORT dataa (1772:1772:1772) (1857:1857:1857)) + (PORT datab (1757:1757:1757) (1827:1827:1827)) + (PORT datac (2074:2074:2074) (2182:2182:2182)) + (PORT datad (968:968:968) (1013:1013:1013)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1307:1307:1307)) - (PORT datab (684:684:684) (724:724:724)) - (PORT datac (794:794:794) (837:837:837)) - (PORT datad (1662:1662:1662) (1693:1693:1693)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29568,29 +11180,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) (DELAY (ABSOLUTE - (PORT dataa (590:590:590) (607:607:607)) - (PORT datab (815:815:815) (829:829:829)) - (PORT datac (585:585:585) (610:610:610)) - (PORT datad (651:651:651) (668:668:668)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (673:673:673) (690:690:690)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (619:619:619) (643:643:643)) + (PORT dataa (1458:1458:1458) (1568:1568:1568)) + (PORT datab (933:933:933) (956:956:956)) + (PORT datac (803:803:803) (825:825:825)) + (PORT datad (1218:1218:1218) (1300:1300:1300)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -29600,77 +11196,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~24) (DELAY (ABSOLUTE - (PORT dataa (1355:1355:1355) (1407:1407:1407)) - (PORT datab (927:927:927) (984:984:984)) - (PORT datac (1048:1048:1048) (1096:1096:1096)) - (PORT datad (1421:1421:1421) (1444:1444:1444)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (847:847:847) (877:877:877)) + (PORT datab (863:863:863) (911:911:911)) + (PORT datac (1684:1684:1684) (1755:1755:1755)) + (PORT datad (1780:1780:1780) (1866:1866:1866)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (INSTANCE z80_\|execute_\|fMRead\~8) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (401:401:401)) - (PORT datab (629:629:629) (655:655:655)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (834:834:834) (861:861:861)) + (PORT datab (698:698:698) (764:764:764)) + (PORT datac (1434:1434:1434) (1463:1463:1463)) + (PORT datad (796:796:796) (846:846:846)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (730:730:730)) - (PORT datab (988:988:988) (1020:1020:1020)) - (PORT datac (2018:2018:2018) (2126:2126:2126)) - (PORT datad (326:326:326) (345:345:345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (826:826:826)) - (PORT datac (215:215:215) (257:257:257)) - (PORT datad (831:831:831) (857:857:857)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (345:345:345) (376:376:376)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (613:613:613) (625:625:625)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29678,15 +11228,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~7) (DELAY (ABSOLUTE - (PORT dataa (621:621:621) (648:648:648)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (575:575:575) (577:577:577)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (1198:1198:1198) (1238:1238:1238)) + (PORT datab (882:882:882) (939:939:939)) + (PORT datac (903:903:903) (952:952:952)) + (PORT datad (1164:1164:1164) (1199:1199:1199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1265:1265:1265)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (780:780:780) (854:854:854)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29694,13 +11260,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) (DELAY (ABSOLUTE - (PORT dataa (1117:1117:1117) (1153:1153:1153)) - (PORT datab (1198:1198:1198) (1239:1239:1239)) - (PORT datac (1173:1173:1173) (1228:1228:1228)) - (PORT datad (1368:1368:1368) (1397:1397:1397)) + (PORT dataa (714:714:714) (763:763:763)) + (PORT datab (714:714:714) (790:790:790)) + (PORT datac (1915:1915:1915) (1978:1978:1978)) + (PORT datad (1060:1060:1060) (1128:1128:1128)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -29710,433 +11276,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M4T2_3) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1151:1151:1151)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (528:528:528) (546:546:546)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT datab (847:847:847) (854:854:854)) - (PORT datac (1082:1082:1082) (1133:1133:1133)) - (PORT datad (828:828:828) (834:834:834)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (829:829:829)) - (PORT datab (897:897:897) (933:933:933)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (965:965:965)) - (PORT datab (912:912:912) (924:924:924)) - (PORT datac (1409:1409:1409) (1449:1449:1449)) - (PORT datad (873:873:873) (900:900:900)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1258:1258:1258)) - (PORT datab (887:887:887) (920:920:920)) - (PORT datac (1132:1132:1132) (1158:1158:1158)) - (PORT datad (950:950:950) (979:979:979)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1284:1284:1284)) - (PORT datab (1418:1418:1418) (1466:1466:1466)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (532:532:532) (548:548:548)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (702:702:702)) - (PORT datab (652:652:652) (733:733:733)) - (PORT datac (1060:1060:1060) (1092:1092:1092)) - (PORT datad (543:543:543) (547:547:547)) + (PORT dataa (1080:1080:1080) (1128:1128:1128)) + (PORT datab (1508:1508:1508) (1603:1603:1603)) + (PORT datac (1513:1513:1513) (1591:1591:1591)) + (PORT datad (578:578:578) (595:595:595)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (746:746:746)) - (PORT datab (1346:1346:1346) (1366:1366:1366)) - (PORT datac (956:956:956) (1016:1016:1016)) - (PORT datad (374:374:374) (392:392:392)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (1175:1175:1175) (1216:1216:1216)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (590:590:590) (618:618:618)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (606:606:606)) - (PORT datab (829:829:829) (843:843:843)) - (PORT datac (563:563:563) (578:578:578)) - (PORT datad (562:562:562) (578:578:578)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1024:1024:1024) (1052:1052:1052)) - (PORT ena (984:984:984) (983:983:983)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1024:1024:1024) (1053:1053:1053)) - (PORT ena (923:923:923) (907:907:907)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (464:464:464)) - (PORT datab (450:450:450) (485:485:485)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1257:1257:1257)) - (PORT datab (852:852:852) (879:879:879)) - (PORT datad (594:594:594) (619:619:619)) - (IOPATH dataa combout (301:301:301) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1191:1191:1191) (1216:1216:1216)) - (PORT ena (1248:1248:1248) (1256:1256:1256)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1010:1010:1010) (1041:1041:1041)) - (PORT ena (1712:1712:1712) (1752:1752:1752)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1012:1012:1012) (1044:1044:1044)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (329:329:329)) - (PORT datab (1408:1408:1408) (1522:1522:1522)) - (PORT datad (216:216:216) (284:284:284)) + (PORT dataa (1478:1478:1478) (1560:1560:1560)) + (PORT datab (781:781:781) (868:868:868)) + (PORT datac (694:694:694) (784:784:784)) + (PORT datad (935:935:935) (1001:1001:1001)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT datab (681:681:681) (743:743:743)) - (PORT datad (608:608:608) (631:631:631)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT asdata (969:969:969) (995:995:995)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1189:1189:1189) (1215:1215:1215)) - (PORT ena (1275:1275:1275) (1314:1314:1314)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (787:787:787)) - (PORT datab (725:725:725) (775:775:775)) - (PORT datad (1020:1020:1020) (1061:1061:1061)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1197:1197:1197) (1218:1218:1218)) - (PORT ena (1147:1147:1147) (1143:1143:1143)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1195:1195:1195) (1219:1219:1219)) - (PORT ena (1248:1248:1248) (1262:1262:1262)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (667:667:667)) - (PORT datab (947:947:947) (1004:1004:1004)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla24M5T2_3) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1168:1168:1168) (1161:1161:1161)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1083:1083:1083) (1130:1130:1130)) + (PORT datab (606:606:606) (633:633:633)) + (PORT datac (1511:1511:1511) (1588:1588:1588)) + (PORT datad (610:610:610) (645:645:645)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1052:1052:1052)) + (PORT datab (1441:1441:1441) (1474:1474:1474)) + (PORT datac (694:694:694) (788:788:788)) + (PORT datad (743:743:743) (830:830:830)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) (DELAY (ABSOLUTE (PORT dataa (665:665:665) (697:697:697)) - (PORT datab (636:636:636) (670:670:670)) - (PORT datac (376:376:376) (420:420:420)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1486:1486:1486) (1517:1517:1517)) + (PORT datad (1639:1639:1639) (1659:1659:1659)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30144,60 +11356,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (811:811:811) (832:832:832)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (638:638:638) (670:670:670)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1182:1182:1182) (1199:1199:1199)) - (PORT datac (1095:1095:1095) (1092:1092:1092)) - (PORT datad (659:659:659) (693:693:693)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1517:1517:1517)) - (PORT datab (670:670:670) (708:708:708)) - (PORT datad (839:839:839) (834:834:834)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (480:480:480)) - (PORT datac (666:666:666) (693:693:693)) - (PORT datad (331:331:331) (347:347:347)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30205,104 +11372,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (422:422:422) (511:511:511)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (591:591:591)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (1211:1211:1211) (1265:1265:1265)) - (PORT datad (625:625:625) (637:637:637)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1133:1133:1133)) - (PORT datad (860:860:860) (861:861:861)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (2023:2023:2023) (2039:2039:2039)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (509:509:509)) - (PORT datab (392:392:392) (466:466:466)) - (PORT datac (243:243:243) (322:322:322)) - (PORT datad (237:237:237) (305:305:305)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (527:527:527)) - (PORT datab (420:420:420) (490:490:490)) - (PORT datac (392:392:392) (467:467:467)) - (PORT datad (239:239:239) (308:308:308)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1365:1365:1365)) - (PORT datab (705:705:705) (774:774:774)) - (PORT datac (594:594:594) (664:664:664)) - (PORT datad (239:239:239) (309:309:309)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (1261:1261:1261) (1305:1305:1305)) + (PORT datab (1047:1047:1047) (1126:1126:1126)) + (PORT datac (980:980:980) (1025:1025:1025)) + (PORT datad (539:539:539) (553:553:553)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -30311,15 +11388,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla5M1T5_2) (DELAY (ABSOLUTE - (PORT dataa (425:425:425) (509:509:509)) - (PORT datab (411:411:411) (493:493:493)) - (PORT datac (550:550:550) (609:609:609)) - (PORT datad (376:376:376) (439:439:439)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (2596:2596:2596) (2742:2742:2742)) + (PORT datac (607:607:607) (640:640:640)) + (PORT datad (1184:1184:1184) (1274:1274:1274)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (372:372:372)) + (PORT datab (1461:1461:1461) (1460:1460:1460)) + (PORT datac (978:978:978) (1022:1022:1022)) + (PORT datad (1021:1021:1021) (1091:1091:1091)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30327,13 +11418,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) (DELAY (ABSOLUTE - (PORT dataa (868:868:868) (895:895:895)) - (PORT datab (822:822:822) (844:844:844)) - (PORT datac (609:609:609) (631:631:631)) - (PORT datad (629:629:629) (662:662:662)) + (PORT dataa (667:667:667) (721:721:721)) + (PORT datab (1048:1048:1048) (1127:1127:1127)) + (PORT datac (976:976:976) (1020:1020:1020)) + (PORT datad (574:574:574) (587:587:587)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1118:1118:1118)) + (PORT datab (1049:1049:1049) (1133:1133:1133)) + (PORT datac (975:975:975) (1018:1018:1018)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1045:1045:1045)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (196:196:196) (222:222:222)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30343,44 +11466,463 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1069:1069:1069)) - (PORT datab (684:684:684) (720:720:720)) - (PORT datad (623:623:623) (638:638:638)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1591:1591:1591) (1660:1660:1660)) + (PORT datab (1803:1803:1803) (1862:1862:1862)) + (PORT datac (1438:1438:1438) (1463:1463:1463)) + (PORT datad (672:672:672) (729:729:729)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) (DELAY (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1553:1553:1553)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + (PORT dataa (1624:1624:1624) (1752:1752:1752)) + (PORT datab (1689:1689:1689) (1774:1774:1774)) + (PORT datac (1101:1101:1101) (1140:1140:1140)) + (PORT datad (1735:1735:1735) (1840:1840:1840)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (1023:1023:1023)) - (PORT datab (637:637:637) (662:662:662)) - (PORT datac (843:843:843) (877:877:877)) - (PORT datad (636:636:636) (678:678:678)) + (PORT dataa (1923:1923:1923) (1952:1952:1952)) + (PORT datab (1273:1273:1273) (1380:1380:1380)) + (PORT datac (1690:1690:1690) (1714:1714:1714)) + (PORT datad (730:730:730) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (912:912:912)) + (PORT datab (1349:1349:1349) (1382:1382:1382)) + (PORT datac (996:996:996) (1029:1029:1029)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (831:831:831)) + (PORT datab (1970:1970:1970) (2040:2040:2040)) + (PORT datad (636:636:636) (730:730:730)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (380:380:380)) + (PORT datab (1472:1472:1472) (1509:1509:1509)) + (PORT datac (1320:1320:1320) (1360:1360:1360)) + (PORT datad (185:185:185) (218:218:218)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T4_3\~0) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (849:849:849)) + (PORT datac (675:675:675) (772:772:772)) + (PORT datad (1444:1444:1444) (1467:1467:1467)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1081:1081:1081)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (788:788:788) (817:817:817)) + (PORT datad (634:634:634) (648:648:648)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1587:1587:1587)) + (PORT datab (834:834:834) (844:844:844)) + (PORT datac (1150:1150:1150) (1177:1177:1177)) + (PORT datad (1165:1165:1165) (1216:1216:1216)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1068:1068:1068)) + (PORT datab (1721:1721:1721) (1793:1793:1793)) + (PORT datac (1103:1103:1103) (1164:1164:1164)) + (PORT datad (803:803:803) (816:816:816)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~16) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (884:884:884)) + (PORT datab (866:866:866) (884:884:884)) + (PORT datac (820:820:820) (838:838:838)) + (PORT datad (212:212:212) (244:244:244)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1262:1262:1262)) + (PORT datab (604:604:604) (629:629:629)) + (PORT datac (676:676:676) (691:691:691)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1365:1365:1365)) + (PORT datab (1234:1234:1234) (1274:1274:1274)) + (PORT datac (1415:1415:1415) (1452:1452:1452)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (685:685:685)) + (PORT datab (997:997:997) (1050:1050:1050)) + (PORT datac (674:674:674) (701:701:701)) + (PORT datad (1168:1168:1168) (1220:1220:1220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (977:977:977)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (285:285:285)) + (PORT datab (709:709:709) (737:737:737)) + (PORT datac (874:874:874) (904:904:904)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~22) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (309:309:309)) + (PORT datab (1273:1273:1273) (1361:1361:1361)) + (PORT datac (950:950:950) (1071:1071:1071)) + (PORT datad (1130:1130:1130) (1154:1154:1154)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (400:400:400)) + (PORT datab (248:248:248) (290:290:290)) + (PORT datac (675:675:675) (703:703:703)) + (PORT datad (920:920:920) (972:972:972)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (550:550:550) (566:566:566)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (639:639:639)) + (PORT datab (1233:1233:1233) (1281:1281:1281)) + (PORT datac (1635:1635:1635) (1655:1655:1655)) + (PORT datad (644:644:644) (681:681:681)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (897:897:897)) + (PORT datab (961:961:961) (1016:1016:1016)) + (PORT datac (1110:1110:1110) (1139:1139:1139)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1573:1573:1573) (1679:1679:1679)) + (PORT datab (1131:1131:1131) (1172:1172:1172)) + (PORT datac (1498:1498:1498) (1561:1561:1561)) + (PORT datad (1569:1569:1569) (1662:1662:1662)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (889:889:889)) + (PORT datab (1837:1837:1837) (1929:1929:1929)) + (PORT datac (781:781:781) (855:855:855)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (690:690:690)) + (PORT datab (1119:1119:1119) (1154:1154:1154)) + (PORT datac (822:822:822) (875:875:875)) + (PORT datad (830:830:830) (878:878:878)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT datab (1217:1217:1217) (1268:1268:1268)) + (PORT datac (1130:1130:1130) (1157:1157:1157)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (885:885:885)) + (PORT datab (1216:1216:1216) (1270:1270:1270)) + (PORT datad (931:931:931) (966:966:966)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1581:1581:1581)) + (PORT datab (1849:1849:1849) (1918:1918:1918)) + (PORT datac (1514:1514:1514) (1557:1557:1557)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (680:680:680)) + (PORT datab (568:568:568) (604:604:604)) + (PORT datac (347:347:347) (370:370:370)) + (PORT datad (1066:1066:1066) (1089:1089:1089)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (832:832:832)) + (PORT datab (661:661:661) (718:718:718)) + (PORT datac (660:660:660) (712:712:712)) + (PORT datad (668:668:668) (719:719:719)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (741:741:741)) + (PORT datab (936:936:936) (979:979:979)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (619:619:619) (653:653:653)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30390,85 +11932,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~21) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (631:631:631)) - (PORT datab (2626:2626:2626) (2719:2719:2719)) - (PORT datac (2090:2090:2090) (2263:2263:2263)) - (PORT datad (1434:1434:1434) (1452:1452:1452)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (604:604:604)) - (PORT datab (608:608:608) (677:677:677)) - (PORT datad (1145:1145:1145) (1180:1180:1180)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (446:446:446)) - (PORT datac (721:721:721) (815:815:815)) - (PORT datad (268:268:268) (348:348:348)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (990:990:990) (1052:1052:1052)) + (PORT datab (907:907:907) (951:951:951)) + (PORT datac (1272:1272:1272) (1325:1325:1325)) + (PORT datad (1167:1167:1167) (1239:1239:1239)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1240:1240:1240) (1269:1269:1269)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1554:1554:1554) (1545:1545:1545)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1364:1364:1364) (1421:1421:1421)) - (PORT datac (853:853:853) (901:901:901)) - (PORT datad (232:232:232) (309:309:309)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (736:736:736) (834:834:834)) + (PORT datac (975:975:975) (1071:1071:1071)) + (PORT datad (990:990:990) (1088:1088:1088)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30476,47 +11962,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) (DELAY (ABSOLUTE - (PORT dataa (260:260:260) (352:352:352)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (983:983:983) (1029:1029:1029)) - (PORT datad (837:837:837) (875:875:875)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1021:1021:1021) (1068:1068:1068)) - (PORT datab (1361:1361:1361) (1418:1418:1418)) - (PORT datac (607:607:607) (631:631:631)) - (PORT datad (920:920:920) (974:974:974)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (914:914:914)) - (PORT datab (641:641:641) (700:700:700)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (636:636:636) (677:677:677)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (1751:1751:1751) (1806:1806:1806)) + (PORT datab (2051:2051:2051) (2112:2112:2112)) + (PORT datac (1227:1227:1227) (1300:1300:1300)) + (PORT datad (837:837:837) (853:853:853)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (1510:1510:1510) (1606:1606:1606)) + (PORT datac (1759:1759:1759) (1827:1827:1827)) + (PORT datad (1180:1180:1180) (1257:1257:1257)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30524,95 +11994,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~19) (DELAY (ABSOLUTE - (PORT dataa (1022:1022:1022) (1066:1066:1066)) - (PORT datab (2171:2171:2171) (2355:2355:2355)) - (PORT datac (1335:1335:1335) (1387:1387:1387)) - (PORT datad (1335:1335:1335) (1492:1492:1492)) + (PORT dataa (1151:1151:1151) (1233:1233:1233)) + (PORT datab (727:727:727) (790:790:790)) + (PORT datac (865:865:865) (912:912:912)) + (PORT datad (1441:1441:1441) (1459:1459:1459)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1026:1026:1026) (1071:1071:1071)) - (PORT datab (932:932:932) (993:993:993)) - (PORT datac (607:607:607) (627:627:627)) - (PORT datad (837:837:837) (870:870:870)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (918:918:918)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (636:636:636) (681:681:681)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (387:387:387)) - (PORT datab (258:258:258) (300:300:300)) - (PORT datac (364:364:364) (389:389:389)) - (PORT datad (575:575:575) (588:588:588)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1867:1867:1867) (1883:1883:1883)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (414:414:414)) - (PORT datab (355:355:355) (391:391:391)) - (PORT datac (321:321:321) (346:346:346)) - (PORT datad (193:193:193) (218:218:218)) + (PORT dataa (864:864:864) (897:897:897)) + (PORT datab (1139:1139:1139) (1210:1210:1210)) + (PORT datac (1440:1440:1440) (1532:1532:1532)) + (PORT datad (1208:1208:1208) (1244:1244:1244)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30620,26 +12026,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) (DELAY (ABSOLUTE - (PORT datab (1247:1247:1247) (1295:1295:1295)) - (PORT datad (788:788:788) (792:792:792)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1483:1483:1483) (1570:1570:1570)) + (PORT datab (2039:2039:2039) (2143:2143:2143)) + (PORT datad (1180:1180:1180) (1228:1228:1228)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (509:509:509) (518:518:518)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (1502:1502:1502) (1585:1585:1585)) + (PORT datab (1248:1248:1248) (1320:1320:1320)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1794:1794:1794) (1875:1875:1875)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -30649,216 +12056,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (473:473:473)) - (PORT datab (966:966:966) (1019:1019:1019)) - (PORT datac (957:957:957) (996:996:996)) - (PORT datad (930:930:930) (961:961:961)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (1008:1008:1008)) - (PORT datab (792:792:792) (810:810:810)) - (PORT datac (831:831:831) (846:846:846)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1526:1526:1526)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1210:1210:1210) (1277:1277:1277)) - (PORT datab (1010:1010:1010) (1070:1070:1070)) - (PORT datac (1149:1149:1149) (1202:1202:1202)) - (PORT datad (1136:1136:1136) (1189:1189:1189)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (2229:2229:2229) (2339:2339:2339)) + (PORT datab (1731:1731:1731) (1749:1749:1749)) + (PORT datac (1721:1721:1721) (1805:1805:1805)) + (PORT datad (1858:1858:1858) (1927:1927:1927)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (701:701:701)) - (PORT datab (228:228:228) (269:269:269)) - (PORT datac (538:538:538) (560:560:560)) - (PORT datad (348:348:348) (372:372:372)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (866:866:866)) - (PORT datab (626:626:626) (642:642:642)) - (PORT datac (556:556:556) (572:572:572)) - (PORT datad (542:542:542) (555:555:555)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (1147:1147:1147) (1156:1156:1156)) - (PORT datac (312:312:312) (331:331:331)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (662:662:662)) - (PORT datab (1297:1297:1297) (1354:1354:1354)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (699:699:699)) - (PORT datab (941:941:941) (1002:1002:1002)) - (PORT datac (1172:1172:1172) (1234:1234:1234)) - (PORT datad (786:786:786) (778:778:778)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (827:827:827)) - (PORT datab (677:677:677) (738:738:738)) - (PORT datac (656:656:656) (722:722:722)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (727:727:727)) - (PORT datab (986:986:986) (1058:1058:1058)) - (PORT datad (504:504:504) (504:504:504)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1360:1360:1360)) - (PORT datab (995:995:995) (1071:1071:1071)) - (PORT datac (1112:1112:1112) (1137:1137:1137)) - (PORT datad (1570:1570:1570) (1618:1618:1618)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -30869,10 +12075,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) (DELAY (ABSOLUTE - (PORT dataa (1476:1476:1476) (1520:1520:1520)) - (PORT datab (1155:1155:1155) (1181:1181:1181)) - (PORT datac (1087:1087:1087) (1097:1097:1097)) - (PORT datad (600:600:600) (614:614:614)) + (PORT dataa (1887:1887:1887) (1973:1973:1973)) + (PORT datab (387:387:387) (407:407:407)) + (PORT datac (897:897:897) (936:936:936)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30885,10 +12091,10 @@ (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (667:667:667)) - (PORT datab (227:227:227) (267:267:267)) - (PORT datac (613:613:613) (637:637:637)) - (PORT datad (173:173:173) (197:197:197)) + (PORT dataa (907:907:907) (943:943:943)) + (PORT datab (650:650:650) (675:675:675)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (830:830:830) (858:858:858)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -30898,27 +12104,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) (DELAY (ABSOLUTE - (PORT dataa (963:963:963) (1037:1037:1037)) - (PORT datac (957:957:957) (1023:1023:1023)) - (PORT datad (1214:1214:1214) (1280:1280:1280)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (990:990:990) (1083:1083:1083)) + (PORT datab (1031:1031:1031) (1113:1113:1113)) + (PORT datac (1373:1373:1373) (1486:1486:1486)) + (PORT datad (920:920:920) (966:966:966)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (692:692:692)) - (PORT datab (1444:1444:1444) (1500:1500:1500)) - (PORT datac (590:590:590) (630:630:630)) - (PORT datad (582:582:582) (612:612:612)) + (PORT dataa (674:674:674) (696:696:696)) + (PORT datab (1801:1801:1801) (1857:1857:1857)) + (PORT datac (1442:1442:1442) (1467:1467:1467)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1694:1694:1694)) + (PORT datab (1786:1786:1786) (1917:1917:1917)) + (PORT datac (1764:1764:1764) (1858:1858:1858)) + (PORT datad (1760:1760:1760) (1895:1895:1895)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1557:1557:1557)) + (PORT datab (1635:1635:1635) (1661:1661:1661)) + (PORT datac (1184:1184:1184) (1225:1225:1225)) + (PORT datad (920:920:920) (933:933:933)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1131:1131:1131)) + (PORT datab (986:986:986) (1043:1043:1043)) + (PORT datac (1223:1223:1223) (1301:1301:1301)) + (PORT datad (1472:1472:1472) (1537:1537:1537)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (428:428:428)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (906:906:906) (956:956:956)) + (PORT datad (1159:1159:1159) (1198:1198:1198)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -30927,32 +12199,323 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~6) (DELAY (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT asdata (752:752:752) (788:788:788)) - (PORT ena (1203:1203:1203) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1281:1281:1281) (1378:1378:1378)) + (PORT datab (1028:1028:1028) (1123:1123:1123)) + (PORT datad (947:947:947) (1032:1032:1032)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (690:690:690)) - (PORT datab (622:622:622) (668:668:668)) - (PORT datad (598:598:598) (635:635:635)) + (PORT dataa (694:694:694) (762:762:762)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (661:661:661) (715:715:715)) + (PORT datad (929:929:929) (969:969:969)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (974:974:974)) + (PORT datac (606:606:606) (628:628:628)) + (PORT datad (624:624:624) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1507:1507:1507)) + (PORT datad (1121:1121:1121) (1194:1194:1194)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1160:1160:1160)) + (PORT datab (1570:1570:1570) (1699:1699:1699)) + (PORT datac (1290:1290:1290) (1404:1404:1404)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~8) + (DELAY + (ABSOLUTE + (PORT datab (1095:1095:1095) (1222:1222:1222)) + (PORT datac (802:802:802) (821:821:821)) + (PORT datad (1874:1874:1874) (1947:1947:1947)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (984:984:984)) + (PORT datab (844:844:844) (880:880:880)) + (PORT datac (965:965:965) (997:997:997)) + (PORT datad (663:663:663) (724:724:724)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1220:1220:1220)) + (PORT datab (654:654:654) (729:729:729)) + (PORT datac (1171:1171:1171) (1164:1164:1164)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (276:276:276)) + (PORT datab (1445:1445:1445) (1515:1515:1515)) + (PORT datac (864:864:864) (910:910:910)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (634:634:634)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (622:622:622) (678:678:678)) + (PORT datad (2002:2002:2002) (2032:2032:2032)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (866:866:866)) + (PORT datab (889:889:889) (924:924:924)) + (PORT datac (689:689:689) (795:795:795)) + (PORT datad (657:657:657) (676:676:676)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datab (993:993:993) (1043:1043:1043)) + (PORT datac (366:366:366) (394:394:394)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (953:953:953)) + (PORT datab (635:635:635) (678:678:678)) + (PORT datac (1571:1571:1571) (1642:1642:1642)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (699:699:699)) + (PORT datab (994:994:994) (1043:1043:1043)) + (PORT datac (599:599:599) (610:610:610)) + (PORT datad (617:617:617) (651:651:651)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (932:932:932)) + (PORT datab (225:225:225) (267:267:267)) + (PORT datac (1722:1722:1722) (1801:1801:1801)) + (PORT datad (1858:1858:1858) (1924:1924:1924)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~30) + (DELAY + (ABSOLUTE + (PORT dataa (2293:2293:2293) (2372:2372:2372)) + (PORT datab (760:760:760) (859:859:859)) + (PORT datac (652:652:652) (759:759:759)) + (PORT datad (1798:1798:1798) (1917:1917:1917)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1887:1887:1887) (1967:1967:1967)) + (PORT datab (411:411:411) (430:430:430)) + (PORT datac (896:896:896) (935:935:935)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (871:871:871)) + (PORT datab (679:679:679) (757:757:757)) + (PORT datac (994:994:994) (1085:1085:1085)) + (PORT datad (1365:1365:1365) (1404:1404:1404)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (855:855:855)) + (PORT datab (1455:1455:1455) (1548:1548:1548)) + (PORT datac (1006:1006:1006) (1029:1029:1029)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (766:766:766) (789:789:789)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (994:994:994)) + (PORT datac (354:354:354) (391:391:391)) + (PORT datad (644:644:644) (701:701:701)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -30962,9 +12525,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1185:1185:1185) (1164:1164:1164)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30973,16 +12536,199 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (417:417:417)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (334:334:334) (353:353:353)) + (PORT datad (1237:1237:1237) (1300:1300:1300)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (664:664:664)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (616:616:616) (637:637:637)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2613:2613:2613) (2702:2702:2702)) + (PORT datac (1264:1264:1264) (1351:1351:1351)) + (PORT datad (1319:1319:1319) (1400:1400:1400)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (677:677:677) (757:757:757)) + (PORT datac (639:639:639) (697:697:697)) + (PORT datad (1253:1253:1253) (1369:1369:1369)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (290:290:290)) + (PORT datab (915:915:915) (976:976:976)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1487:1487:1487) (1555:1555:1555)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (978:978:978)) + (PORT datab (1079:1079:1079) (1089:1089:1089)) + (PORT datac (1106:1106:1106) (1130:1130:1130)) + (PORT datad (351:351:351) (375:375:375)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1839:1839:1839) (1955:1955:1955)) + (PORT datab (993:993:993) (1042:1042:1042)) + (PORT datac (1196:1196:1196) (1237:1237:1237)) + (PORT datad (840:840:840) (848:848:848)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (672:672:672) (700:700:700)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (447:447:447)) + (PORT datab (683:683:683) (737:737:737)) + (PORT datac (538:538:538) (539:539:539)) + (PORT datad (876:876:876) (910:910:910)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT datab (684:684:684) (739:739:739)) + (PORT datac (355:355:355) (388:388:388)) + (PORT datad (566:566:566) (575:575:575)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (890:890:890) (906:906:906)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (687:687:687) (743:743:743)) + (PORT datac (358:358:358) (391:391:391)) + (PORT datad (564:564:564) (571:571:571)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (581:581:581)) - (PORT datab (592:592:592) (627:627:627)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1515:1515:1515) (1611:1611:1611)) + (PORT datab (1308:1308:1308) (1422:1422:1422)) + (PORT datad (1163:1163:1163) (1199:1199:1199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -30992,24 +12738,332 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) (DELAY (ABSOLUTE - (PORT dataa (474:474:474) (523:523:523)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1498:1498:1498) (1562:1562:1562)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (428:428:428) (493:493:493)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1144:1144:1144) (1165:1165:1165)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1156:1156:1156)) + (PORT datab (916:916:916) (945:945:945)) + (PORT datac (1639:1639:1639) (1833:1833:1833)) + (PORT datad (880:880:880) (906:906:906)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (696:696:696)) + (PORT datab (1681:1681:1681) (1718:1718:1718)) + (PORT datac (1695:1695:1695) (1768:1768:1768)) + (PORT datad (1698:1698:1698) (1732:1732:1732)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1289:1289:1289)) + (PORT datab (949:949:949) (1017:1017:1017)) + (PORT datac (902:902:902) (922:922:922)) + (PORT datad (1209:1209:1209) (1222:1222:1222)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1376:1376:1376)) + (PORT datab (880:880:880) (933:933:933)) + (PORT datac (1197:1197:1197) (1297:1297:1297)) + (PORT datad (1123:1123:1123) (1169:1169:1169)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1470:1470:1470)) + (PORT datab (881:881:881) (940:940:940)) + (PORT datac (937:937:937) (1032:1032:1032)) + (PORT datad (1386:1386:1386) (1509:1509:1509)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (923:923:923)) + (PORT datab (746:746:746) (815:815:815)) + (PORT datac (910:910:910) (981:981:981)) + (PORT datad (1436:1436:1436) (1531:1531:1531)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (1011:1011:1011) (1064:1064:1064)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (954:954:954)) + (PORT datac (1199:1199:1199) (1284:1284:1284)) + (PORT datad (1380:1380:1380) (1407:1407:1407)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (678:678:678)) + (PORT datab (1196:1196:1196) (1225:1225:1225)) + (PORT datac (1229:1229:1229) (1275:1275:1275)) + (PORT datad (782:782:782) (805:805:805)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (610:610:610)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (844:844:844) (858:858:858)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (670:670:670)) + (PORT datab (645:645:645) (699:699:699)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (619:619:619) (642:642:642)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (944:944:944)) + (PORT datab (1195:1195:1195) (1242:1242:1242)) + (PORT datac (611:611:611) (637:637:637)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1707:1707:1707) (1746:1746:1746)) + (PORT datab (1510:1510:1510) (1607:1607:1607)) + (PORT datac (1760:1760:1760) (1829:1829:1829)) + (PORT datad (2026:2026:2026) (2076:2076:2076)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1804:1804:1804)) + (PORT datab (1219:1219:1219) (1281:1281:1281)) + (PORT datac (696:696:696) (789:789:789)) + (PORT datad (743:743:743) (828:828:828)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1073:1073:1073)) + (PORT datab (1201:1201:1201) (1238:1238:1238)) + (PORT datac (904:904:904) (953:953:953)) + (PORT datad (1900:1900:1900) (1905:1905:1905)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (930:930:930)) + (PORT datac (866:866:866) (902:902:902)) + (PORT datad (861:861:861) (910:910:910)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (875:875:875) (898:898:898)) + (PORT datac (628:628:628) (650:650:650)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (680:680:680)) + (PORT datad (614:614:614) (635:635:635)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1247:1247:1247)) + (PORT datab (1310:1310:1310) (1421:1421:1421)) + (PORT datac (1148:1148:1148) (1171:1171:1171)) + (PORT datad (1122:1122:1122) (1143:1143:1143)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT datac (880:880:880) (938:938:938)) - (PORT datad (349:349:349) (365:365:365)) + (PORT datac (1195:1195:1195) (1224:1224:1224)) + (PORT datad (596:596:596) (606:606:606)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31020,10 +13074,10 @@ (INSTANCE z80_\|address_latch_\|Q\[11\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (1783:1783:1783) (1814:1814:1814)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -31038,8 +13092,134 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT datac (415:415:415) (481:481:481)) - (PORT datad (341:341:341) (363:363:363)) + (PORT datab (709:709:709) (786:786:786)) + (PORT datad (602:602:602) (647:647:647)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (549:549:549)) + (PORT datab (403:403:403) (434:434:434)) + (PORT datac (1159:1159:1159) (1194:1194:1194)) + (PORT datad (629:629:629) (667:667:667)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1140:1140:1140)) + (PORT datab (934:934:934) (1002:1002:1002)) + (PORT datac (906:906:906) (947:947:947)) + (PORT datad (771:771:771) (785:785:785)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (424:424:424)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1269:1269:1269)) + (PORT datab (1517:1517:1517) (1572:1572:1572)) + (PORT datac (1191:1191:1191) (1239:1239:1239)) + (PORT datad (511:511:511) (525:525:525)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1394:1394:1394)) + (PORT datab (957:957:957) (1007:1007:1007)) + (PORT datac (982:982:982) (1038:1038:1038)) + (PORT datad (838:838:838) (846:846:846)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (284:284:284)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (1676:1676:1676) (1720:1720:1720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (825:825:825) (840:840:840)) + (PORT datac (882:882:882) (927:927:927)) + (PORT datad (1322:1322:1322) (1339:1339:1339)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1059:1059:1059)) + (PORT datab (1437:1437:1437) (1477:1477:1477)) + (PORT datac (888:888:888) (937:937:937)) + (PORT datad (1160:1160:1160) (1210:1210:1210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31047,14 +13227,18390 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~17) (DELAY (ABSOLUTE - (PORT dataa (1176:1176:1176) (1262:1262:1262)) - (PORT datab (390:390:390) (410:410:410)) - (PORT datad (553:553:553) (555:555:555)) + (PORT dataa (2418:2418:2418) (2563:2563:2563)) + (PORT datab (1346:1346:1346) (1485:1485:1485)) + (PORT datac (851:851:851) (897:897:897)) + (PORT datad (927:927:927) (986:986:986)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (969:969:969)) + (PORT datac (1653:1653:1653) (1707:1707:1707)) + (PORT datad (1191:1191:1191) (1260:1260:1260)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1217:1217:1217)) + (PORT datab (614:614:614) (640:640:640)) + (PORT datac (1689:1689:1689) (1742:1742:1742)) + (PORT datad (623:623:623) (676:676:676)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (618:618:618)) + (PORT datab (1783:1783:1783) (1915:1915:1915)) + (PORT datac (1169:1169:1169) (1195:1195:1195)) + (PORT datad (1346:1346:1346) (1504:1504:1504)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (893:893:893)) + (PORT datab (613:613:613) (634:634:634)) + (PORT datac (616:616:616) (644:644:644)) + (PORT datad (1105:1105:1105) (1120:1120:1120)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1153:1153:1153)) + (PORT datab (207:207:207) (247:247:247)) + (PORT datac (599:599:599) (643:643:643)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (1543:1543:1543) (1670:1670:1670)) + (PORT datac (1253:1253:1253) (1293:1293:1293)) + (PORT datad (2028:2028:2028) (2132:2132:2132)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1145:1145:1145)) + (PORT datab (613:613:613) (660:660:660)) + (PORT datac (1142:1142:1142) (1182:1182:1182)) + (PORT datad (915:915:915) (949:949:949)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1585:1585:1585)) + (PORT datab (940:940:940) (958:958:958)) + (PORT datac (353:353:353) (369:369:369)) + (PORT datad (324:324:324) (344:344:344)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~15) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (950:950:950)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (792:792:792)) + (PORT datab (1654:1654:1654) (1681:1681:1681)) + (PORT datac (1149:1149:1149) (1212:1212:1212)) + (PORT datad (903:903:903) (965:965:965)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1216:1216:1216)) + (PORT datab (954:954:954) (990:990:990)) + (PORT datac (1686:1686:1686) (1738:1738:1738)) + (PORT datad (626:626:626) (676:676:676)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1549:1549:1549)) + (PORT datab (1383:1383:1383) (1433:1433:1433)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (894:894:894) (930:930:930)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1203:1203:1203)) + (PORT datab (231:231:231) (279:279:279)) + (PORT datac (844:844:844) (877:877:877)) + (PORT datad (870:870:870) (908:908:908)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1298:1298:1298)) + (PORT datab (1214:1214:1214) (1253:1253:1253)) + (PORT datac (913:913:913) (937:937:937)) + (PORT datad (1720:1720:1720) (1754:1754:1754)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1720:1720:1720) (1779:1779:1779)) + (PORT datab (615:615:615) (641:641:641)) + (PORT datac (755:755:755) (789:789:789)) + (PORT datad (312:312:312) (324:324:324)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (407:407:407) (441:441:441)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1591:1591:1591) (1658:1658:1658)) + (PORT datab (1804:1804:1804) (1861:1861:1861)) + (PORT datac (1404:1404:1404) (1439:1439:1439)) + (PORT datad (1839:1839:1839) (1889:1889:1889)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (679:679:679)) + (PORT datab (674:674:674) (688:688:688)) + (PORT datac (624:624:624) (658:658:658)) + (PORT datad (1127:1127:1127) (1145:1145:1145)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (960:960:960)) + (PORT datab (1193:1193:1193) (1238:1238:1238)) + (PORT datac (1147:1147:1147) (1169:1169:1169)) + (PORT datad (621:621:621) (659:659:659)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (946:946:946)) + (PORT datab (224:224:224) (265:265:265)) + (PORT datad (1159:1159:1159) (1205:1205:1205)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (1706:1706:1706) (1755:1755:1755)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1167:1167:1167)) + (PORT datab (1502:1502:1502) (1540:1540:1540)) + (PORT datac (673:673:673) (697:697:697)) + (PORT datad (911:911:911) (934:934:934)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (881:881:881)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (573:573:573) (590:590:590)) + (PORT datad (1089:1089:1089) (1093:1093:1093)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (723:723:723) (764:764:764)) + (PORT datac (911:911:911) (970:970:970)) + (PORT datad (1869:1869:1869) (2001:2001:2001)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2233:2233:2233) (2412:2412:2412)) + (PORT datab (619:619:619) (646:646:646)) + (PORT datad (1501:1501:1501) (1594:1594:1594)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1330:1330:1330)) + (PORT datab (2646:2646:2646) (2748:2748:2748)) + (PORT datac (1226:1226:1226) (1319:1319:1319)) + (PORT datad (1579:1579:1579) (1727:1727:1727)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1293:1293:1293)) + (PORT datab (746:746:746) (855:855:855)) + (PORT datad (1194:1194:1194) (1277:1277:1277)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datac (871:871:871) (905:905:905)) + (PORT datad (902:902:902) (928:928:928)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (895:895:895)) + (PORT datab (658:658:658) (685:685:685)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (890:890:890) (941:941:941)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (1142:1142:1142) (1159:1159:1159)) + (PORT datac (583:583:583) (599:599:599)) + (PORT datad (322:322:322) (335:335:335)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (833:833:833)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (627:627:627) (662:662:662)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1872:1872:1872) (1974:1974:1974)) + (PORT datab (1340:1340:1340) (1460:1460:1460)) + (PORT datac (674:674:674) (736:736:736)) + (PORT datad (867:867:867) (916:916:916)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1362:1362:1362)) + (PORT datab (1587:1587:1587) (1747:1747:1747)) + (PORT datac (1904:1904:1904) (1992:1992:1992)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (2109:2109:2109) (2269:2269:2269)) + (PORT datab (664:664:664) (709:709:709)) + (PORT datac (1760:1760:1760) (1913:1913:1913)) + (PORT datad (1415:1415:1415) (1486:1486:1486)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (2109:2109:2109) (2271:2271:2271)) + (PORT datab (2739:2739:2739) (2867:2867:2867)) + (PORT datac (1759:1759:1759) (1914:1914:1914)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1733:1733:1733) (1848:1848:1848)) + (PORT datab (983:983:983) (1058:1058:1058)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1416:1416:1416) (1489:1489:1489)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1535:1535:1535)) + (PORT datab (1195:1195:1195) (1240:1240:1240)) + (PORT datac (953:953:953) (1022:1022:1022)) + (PORT datad (835:835:835) (844:844:844)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1183:1183:1183)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datac (1660:1660:1660) (1743:1743:1743)) + (PORT datad (1215:1215:1215) (1304:1304:1304)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (971:971:971)) + (PORT datab (1085:1085:1085) (1103:1103:1103)) + (PORT datac (737:737:737) (736:736:736)) + (PORT datad (1069:1069:1069) (1078:1078:1078)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (978:978:978) (1041:1041:1041)) + (PORT datac (526:526:526) (540:540:540)) + (PORT datad (315:315:315) (333:333:333)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (366:366:366)) + (PORT datab (369:369:369) (388:388:388)) + (PORT datac (315:315:315) (334:334:334)) + (PORT datad (543:543:543) (553:553:553)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1281:1281:1281)) + (PORT datac (621:621:621) (649:649:649)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (900:900:900)) + (PORT datab (986:986:986) (1058:1058:1058)) + (PORT datac (931:931:931) (972:972:972)) + (PORT datad (1718:1718:1718) (1748:1748:1748)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (1895:1895:1895) (1984:1984:1984)) + (PORT datad (958:958:958) (1000:1000:1000)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (907:907:907)) + (PORT datab (1350:1350:1350) (1385:1385:1385)) + (PORT datac (978:978:978) (1074:1074:1074)) + (PORT datad (1239:1239:1239) (1343:1343:1343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (627:627:627)) + (PORT datab (1194:1194:1194) (1220:1220:1220)) + (PORT datac (1231:1231:1231) (1275:1275:1275)) + (PORT datad (1313:1313:1313) (1344:1344:1344)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1294:1294:1294)) + (PORT datab (1084:1084:1084) (1191:1191:1191)) + (PORT datac (1106:1106:1106) (1164:1164:1164)) + (PORT datad (2076:2076:2076) (2218:2218:2218)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1252:1252:1252)) + (PORT datab (270:270:270) (318:318:318)) + (PORT datac (1379:1379:1379) (1451:1451:1451)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (677:677:677)) + (PORT datab (226:226:226) (268:268:268)) + (PORT datac (924:924:924) (941:941:941)) + (PORT datad (926:926:926) (965:965:965)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (406:406:406)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (841:841:841) (845:845:845)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1694:1694:1694) (1753:1753:1753)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (907:907:907) (941:941:941)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1009:1009:1009)) + (PORT datab (854:854:854) (861:861:861)) + (PORT datac (2057:2057:2057) (2150:2150:2150)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1309:1309:1309)) + (PORT datab (1499:1499:1499) (1536:1536:1536)) + (PORT datac (1229:1229:1229) (1274:1274:1274)) + (PORT datad (1159:1159:1159) (1184:1184:1184)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1960:1960:1960)) + (PORT datab (994:994:994) (1041:1041:1041)) + (PORT datad (872:872:872) (917:917:917)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1741:1741:1741) (1826:1826:1826)) + (PORT datab (987:987:987) (1058:1058:1058)) + (PORT datac (534:534:534) (548:548:548)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1009:1009:1009)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1881:1881:1881)) + (PORT datab (921:921:921) (966:966:966)) + (PORT datac (901:901:901) (967:967:967)) + (PORT datad (934:934:934) (1029:1029:1029)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (332:332:332) (359:359:359)) + (PORT datad (923:923:923) (961:961:961)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (341:341:341)) + (PORT datab (1192:1192:1192) (1231:1231:1231)) + (PORT datac (1382:1382:1382) (1468:1468:1468)) + (PORT datad (708:708:708) (813:813:813)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1432:1432:1432)) + (PORT datab (231:231:231) (279:279:279)) + (PORT datac (843:843:843) (862:862:862)) + (PORT datad (1131:1131:1131) (1174:1174:1174)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1233:1233:1233)) + (PORT datab (581:581:581) (610:610:610)) + (PORT datad (1136:1136:1136) (1206:1206:1206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1296:1296:1296)) + (PORT datab (749:749:749) (860:860:860)) + (PORT datad (1192:1192:1192) (1276:1276:1276)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (306:306:306) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (338:338:338)) + (PORT datab (1191:1191:1191) (1229:1229:1229)) + (PORT datac (1382:1382:1382) (1466:1466:1466)) + (PORT datad (711:711:711) (812:812:812)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (965:965:965)) + (PORT datab (1267:1267:1267) (1346:1346:1346)) + (PORT datad (639:639:639) (681:681:681)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (341:341:341)) + (PORT datab (1192:1192:1192) (1232:1232:1232)) + (PORT datac (1382:1382:1382) (1470:1470:1470)) + (PORT datad (707:707:707) (815:815:815)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1233:1233:1233)) + (PORT datab (589:589:589) (615:615:615)) + (PORT datad (1136:1136:1136) (1207:1207:1207)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (342:342:342)) + (PORT datab (1195:1195:1195) (1233:1233:1233)) + (PORT datac (1382:1382:1382) (1470:1470:1470)) + (PORT datad (707:707:707) (812:812:812)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (962:962:962)) + (PORT datab (1270:1270:1270) (1346:1346:1346)) + (PORT datad (633:633:633) (675:675:675)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1098:1098:1098)) + (PORT datab (542:542:542) (564:564:564)) + (PORT datac (848:848:848) (926:926:926)) + (PORT datad (519:519:519) (526:526:526)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (988:988:988)) + (PORT datac (1093:1093:1093) (1158:1158:1158)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2316:2316:2316) (2436:2436:2436)) + (PORT datab (1543:1543:1543) (1667:1667:1667)) + (PORT datac (865:865:865) (884:884:884)) + (PORT datad (2031:2031:2031) (2135:2135:2135)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (996:996:996)) + (PORT datab (1219:1219:1219) (1294:1294:1294)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1130:1130:1130) (1166:1166:1166)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datac (665:665:665) (696:696:696)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1263:1263:1263)) + (PORT datab (1033:1033:1033) (1105:1105:1105)) + (PORT datad (642:642:642) (665:665:665)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1579:1579:1579)) + (PORT datab (1497:1497:1497) (1576:1576:1576)) + (PORT datac (1382:1382:1382) (1448:1448:1448)) + (PORT datad (632:632:632) (689:689:689)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (689:689:689)) + (PORT datac (1109:1109:1109) (1179:1179:1179)) + (PORT datad (194:194:194) (229:229:229)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~23) + (DELAY + (ABSOLUTE + (PORT datab (1183:1183:1183) (1220:1220:1220)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~29) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (700:700:700)) + (PORT datab (722:722:722) (791:791:791)) + (PORT datac (1102:1102:1102) (1122:1122:1122)) + (PORT datad (179:179:179) (209:209:209)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~26) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (362:362:362) (391:391:391)) + (PORT datac (619:619:619) (669:669:669)) + (PORT datad (609:609:609) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (427:427:427)) + (PORT datab (711:711:711) (763:763:763)) + (PORT datad (645:645:645) (697:697:697)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1513:1513:1513) (1574:1574:1574)) + (PORT datab (1501:1501:1501) (1574:1574:1574)) + (PORT datac (1378:1378:1378) (1442:1442:1442)) + (PORT datad (634:634:634) (691:691:691)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (424:424:424)) + (PORT datab (830:830:830) (838:838:838)) + (PORT datac (1052:1052:1052) (1091:1091:1091)) + (PORT datad (814:814:814) (824:824:824)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1385:1385:1385) (1476:1476:1476)) + (PORT datab (1543:1543:1543) (1633:1633:1633)) + (PORT datac (348:348:348) (386:386:386)) + (PORT datad (1524:1524:1524) (1607:1607:1607)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1653:1653:1653)) + (PORT datab (1546:1546:1546) (1634:1634:1634)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (702:702:702) (798:798:798)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1881:1881:1881)) + (PORT datab (921:921:921) (967:967:967)) + (PORT datac (901:901:901) (967:967:967)) + (PORT datad (934:934:934) (1029:1029:1029)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (968:968:968)) + (PORT datab (1268:1268:1268) (1340:1340:1340)) + (PORT datad (1208:1208:1208) (1218:1218:1218)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1643:1643:1643)) + (PORT datab (1543:1543:1543) (1624:1624:1624)) + (PORT datac (351:351:351) (386:386:386)) + (PORT datad (705:705:705) (803:803:803)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (891:891:891) (896:896:896)) + (PORT datad (205:205:205) (235:235:235)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1646:1646:1646)) + (PORT datab (1546:1546:1546) (1626:1626:1626)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (1233:1233:1233) (1360:1360:1360)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1139:1139:1139)) + (PORT datab (1240:1240:1240) (1273:1273:1273)) + (PORT datac (492:492:492) (511:511:511)) + (PORT datad (576:576:576) (611:611:611)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1228:1228:1228)) + (PORT datab (1084:1084:1084) (1093:1093:1093)) + (PORT datad (1137:1137:1137) (1213:1213:1213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (970:970:970)) + (PORT datab (1264:1264:1264) (1337:1337:1337)) + (PORT datad (643:643:643) (685:685:685)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1210:1210:1210) (1241:1241:1241)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (970:970:970)) + (PORT datab (1263:1263:1263) (1337:1337:1337)) + (PORT datad (633:633:633) (675:675:675)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1211:1211:1211) (1244:1244:1244)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (897:897:897)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (838:838:838) (848:848:848)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (578:578:578)) + (PORT datac (1141:1141:1141) (1188:1188:1188)) + (PORT datad (1137:1137:1137) (1213:1213:1213)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1805:1805:1805) (1892:1892:1892)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (581:581:581) (615:615:615)) + (PORT datac (1145:1145:1145) (1196:1196:1196)) + (PORT datad (1137:1137:1137) (1210:1210:1210)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1805:1805:1805) (1892:1892:1892)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1231:1231:1231)) + (PORT datab (581:581:581) (613:613:613)) + (PORT datad (1137:1137:1137) (1212:1212:1212)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (908:908:908)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (986:986:986)) + (PORT datac (1094:1094:1094) (1157:1157:1157)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1652:1652:1652)) + (PORT datab (398:398:398) (431:431:431)) + (PORT datac (1507:1507:1507) (1600:1600:1600)) + (PORT datad (704:704:704) (804:804:804)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1851:1851:1851) (1958:1958:1958)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1558:1558:1558) (1654:1654:1654)) + (PORT datab (397:397:397) (428:428:428)) + (PORT datac (1511:1511:1511) (1601:1601:1601)) + (PORT datad (704:704:704) (801:801:801)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1853:1853:1853) (1959:1959:1959)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (754:754:754)) + (PORT datab (668:668:668) (711:711:711)) + (PORT datad (356:356:356) (414:414:414)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (964:964:964)) + (PORT datab (1272:1272:1272) (1346:1346:1346)) + (PORT datad (1209:1209:1209) (1218:1218:1218)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1347:1347:1347) (1401:1401:1401)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1475:1475:1475) (1566:1566:1566)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1650:1650:1650)) + (PORT datab (1274:1274:1274) (1405:1405:1405)) + (PORT datac (1507:1507:1507) (1598:1598:1598)) + (PORT datad (362:362:362) (393:393:393)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (983:983:983)) + (PORT datab (896:896:896) (938:938:938)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1645:1645:1645)) + (PORT datab (1542:1542:1542) (1626:1626:1626)) + (PORT datac (1358:1358:1358) (1438:1438:1438)) + (PORT datad (364:364:364) (390:390:390)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (956:956:956) (978:978:978)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (430:430:430)) + (PORT datab (711:711:711) (765:765:765)) + (PORT datad (644:644:644) (701:701:701)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (962:962:962) (983:983:983)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datab (464:464:464) (504:504:504)) + (PORT datad (1157:1157:1157) (1213:1213:1213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT datab (635:635:635) (689:689:689)) + (PORT datac (1102:1102:1102) (1175:1175:1175)) + (PORT datad (193:193:193) (227:227:227)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1202:1202:1202) (1222:1222:1222)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (925:925:925)) + (PORT datab (1236:1236:1236) (1262:1262:1262)) + (PORT datad (860:860:860) (865:865:865)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (410:410:410)) + (PORT datab (638:638:638) (655:655:655)) + (PORT datac (344:344:344) (368:368:368)) + (PORT datad (604:604:604) (641:641:641)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1220:1220:1220)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (605:605:605) (660:660:660)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1467:1467:1467) (1463:1463:1463)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (852:852:852) (898:898:898)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (403:403:403)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (592:592:592) (616:616:616)) + (PORT datad (579:579:579) (587:587:587)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (963:963:963)) + (PORT datab (1101:1101:1101) (1135:1135:1135)) + (PORT datac (907:907:907) (958:958:958)) + (PORT datad (901:901:901) (944:944:944)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1544:1544:1544)) + (PORT datab (937:937:937) (1010:1010:1010)) + (PORT datac (597:597:597) (658:658:658)) + (PORT datad (612:612:612) (669:669:669)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (953:953:953)) + (PORT datab (848:848:848) (892:892:892)) + (PORT datad (1141:1141:1141) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1563:1563:1563)) + (PORT datab (923:923:923) (951:951:951)) + (PORT datac (946:946:946) (995:995:995)) + (PORT datad (905:905:905) (956:956:956)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1363:1363:1363) (1384:1384:1384)) + (PORT datab (884:884:884) (925:925:925)) + (PORT datac (937:937:937) (980:980:980)) + (PORT datad (1191:1191:1191) (1250:1250:1250)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1558:1558:1558)) + (PORT datab (1462:1462:1462) (1495:1495:1495)) + (PORT datac (1650:1650:1650) (1738:1738:1738)) + (PORT datad (797:797:797) (847:847:847)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (586:586:586)) + (PORT datab (983:983:983) (1024:1024:1024)) + (PORT datac (495:495:495) (503:503:503)) + (PORT datad (1079:1079:1079) (1076:1076:1076)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (701:701:701)) + (PORT datab (1112:1112:1112) (1138:1138:1138)) + (PORT datac (756:756:756) (766:766:766)) + (PORT datad (775:775:775) (835:835:835)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1177:1177:1177)) + (PORT datab (346:346:346) (380:380:380)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (558:558:558) (562:562:562)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (952:952:952) (976:976:976)) + (PORT datac (867:867:867) (882:882:882)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (1273:1273:1273) (1379:1379:1379)) + (PORT datac (1212:1212:1212) (1277:1277:1277)) + (PORT datad (1419:1419:1419) (1483:1483:1483)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (657:657:657) (703:703:703)) + (PORT datac (901:901:901) (933:933:933)) + (PORT datad (1195:1195:1195) (1273:1273:1273)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (270:270:270)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1054:1054:1054)) + (PORT datab (869:869:869) (898:898:898)) + (PORT datac (1859:1859:1859) (1856:1856:1856)) + (PORT datad (1111:1111:1111) (1142:1142:1142)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1130:1130:1130)) + (PORT datab (578:578:578) (604:604:604)) + (PORT datac (682:682:682) (742:742:742)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (601:601:601)) + (PORT datab (896:896:896) (907:907:907)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (822:822:822)) + (PORT datab (708:708:708) (790:790:790)) + (PORT datac (1415:1415:1415) (1429:1429:1429)) + (PORT datad (1112:1112:1112) (1130:1130:1130)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (275:275:275)) + (PORT datab (946:946:946) (972:972:972)) + (PORT datac (1110:1110:1110) (1136:1136:1136)) + (PORT datad (1407:1407:1407) (1461:1461:1461)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1514:1514:1514)) + (PORT datab (1167:1167:1167) (1198:1198:1198)) + (PORT datac (1416:1416:1416) (1484:1484:1484)) + (PORT datad (626:626:626) (666:666:666)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1413:1413:1413) (1487:1487:1487)) + (PORT datad (196:196:196) (237:237:237)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1303:1303:1303)) + (PORT datab (1829:1829:1829) (1892:1892:1892)) + (PORT datac (618:618:618) (647:647:647)) + (PORT datad (1048:1048:1048) (1107:1107:1107)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1342:1342:1342)) + (PORT datab (751:751:751) (851:851:851)) + (PORT datac (697:697:697) (800:800:800)) + (PORT datad (1222:1222:1222) (1251:1251:1251)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1112:1112:1112)) + (PORT datac (1238:1238:1238) (1325:1325:1325)) + (PORT datad (222:222:222) (260:260:260)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (261:261:261)) + (PORT datab (1751:1751:1751) (1801:1801:1801)) + (PORT datac (1451:1451:1451) (1615:1615:1615)) + (PORT datad (806:806:806) (821:821:821)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (871:871:871)) + (PORT datab (1524:1524:1524) (1560:1560:1560)) + (PORT datac (1083:1083:1083) (1088:1088:1088)) + (PORT datad (319:319:319) (341:341:341)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1441:1441:1441)) + (PORT datab (882:882:882) (941:941:941)) + (PORT datac (1254:1254:1254) (1346:1346:1346)) + (PORT datad (1013:1013:1013) (1138:1138:1138)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1037:1037:1037)) + (PORT datab (999:999:999) (1030:1030:1030)) + (PORT datac (1625:1625:1625) (1664:1664:1664)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1203:1203:1203)) + (PORT datab (894:894:894) (948:948:948)) + (PORT datac (1412:1412:1412) (1488:1488:1488)) + (PORT datad (1187:1187:1187) (1199:1199:1199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1703:1703:1703)) + (PORT datab (933:933:933) (960:960:960)) + (PORT datac (806:806:806) (828:828:828)) + (PORT datad (1218:1218:1218) (1303:1303:1303)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1112:1112:1112)) + (PORT datab (1303:1303:1303) (1409:1409:1409)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (545:545:545) (565:565:565)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (680:680:680)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (920:920:920) (943:943:943)) + (PORT datad (608:608:608) (649:649:649)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (390:390:390)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (610:610:610) (616:616:616)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1442:1442:1442)) + (PORT datab (909:909:909) (950:950:950)) + (PORT datac (1253:1253:1253) (1344:1344:1344)) + (PORT datad (1016:1016:1016) (1139:1139:1139)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (717:717:717)) + (PORT datab (908:908:908) (963:963:963)) + (PORT datac (566:566:566) (592:592:592)) + (PORT datad (588:588:588) (608:608:608)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (655:655:655) (677:677:677)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (833:833:833) (865:865:865)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (638:638:638)) + (PORT datab (627:627:627) (644:644:644)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (875:875:875) (921:921:921)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (887:887:887) (938:938:938)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1363:1363:1363)) + (PORT datab (588:588:588) (607:607:607)) + (PORT datac (1208:1208:1208) (1245:1245:1245)) + (PORT datad (1737:1737:1737) (1795:1795:1795)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1242:1242:1242)) + (PORT datab (426:426:426) (502:502:502)) + (PORT datad (438:438:438) (498:498:498)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (963:963:963)) + (PORT datab (1720:1720:1720) (1795:1795:1795)) + (PORT datac (1274:1274:1274) (1324:1324:1324)) + (PORT datad (974:974:974) (1027:1027:1027)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (929:929:929) (998:998:998)) + (PORT datac (641:641:641) (690:690:690)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (905:905:905)) + (PORT datab (1162:1162:1162) (1176:1176:1176)) + (PORT datac (1346:1346:1346) (1374:1374:1374)) + (PORT datad (882:882:882) (905:905:905)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1157:1157:1157)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1454:1454:1454) (1505:1505:1505)) + (PORT datad (343:343:343) (366:366:366)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1068:1068:1068)) + (PORT datab (1096:1096:1096) (1143:1143:1143)) + (PORT datac (905:905:905) (954:954:954)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT datab (1361:1361:1361) (1428:1428:1428)) + (PORT datad (1336:1336:1336) (1389:1389:1389)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1486:1486:1486)) + (PORT datab (361:361:361) (394:394:394)) + (PORT datac (1141:1141:1141) (1208:1208:1208)) + (PORT datad (1064:1064:1064) (1100:1100:1100)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (749:749:749)) + (PORT datab (1473:1473:1473) (1509:1509:1509)) + (PORT datac (874:874:874) (900:900:900)) + (PORT datad (1225:1225:1225) (1250:1250:1250)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (909:909:909)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (1166:1166:1166) (1173:1173:1173)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (817:817:817)) + (PORT datab (1830:1830:1830) (1892:1892:1892)) + (PORT datac (682:682:682) (759:759:759)) + (PORT datad (1224:1224:1224) (1302:1302:1302)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (195:195:195) (230:230:230)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (381:381:381)) + (PORT datab (585:585:585) (605:605:605)) + (PORT datac (636:636:636) (685:685:685)) + (PORT datad (547:547:547) (559:559:559)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (262:262:262)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (906:906:906) (933:933:933)) + (PORT datad (588:588:588) (617:617:617)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (641:641:641) (689:689:689)) + (PORT datad (317:317:317) (335:335:335)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1443:1443:1443)) + (PORT datab (880:880:880) (938:938:938)) + (PORT datac (936:936:936) (1032:1032:1032)) + (PORT datad (1388:1388:1388) (1510:1510:1510)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (654:654:654) (673:673:673)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (833:833:833) (861:861:861)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (637:637:637)) + (PORT datad (875:875:875) (921:921:921)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1218:1218:1218)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (1100:1100:1100) (1124:1124:1124)) + (PORT datad (1168:1168:1168) (1186:1186:1186)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1189:1189:1189)) + (PORT datab (1795:1795:1795) (1857:1857:1857)) + (PORT datac (1484:1484:1484) (1515:1515:1515)) + (PORT datad (1456:1456:1456) (1522:1522:1522)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (935:935:935)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (1668:1668:1668) (1703:1703:1703)) + (PORT datad (1456:1456:1456) (1525:1525:1525)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (799:799:799)) + (PORT datab (1464:1464:1464) (1462:1462:1462)) + (PORT datac (1627:1627:1627) (1654:1654:1654)) + (PORT datad (631:631:631) (644:644:644)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (712:712:712)) + (PORT datab (972:972:972) (1028:1028:1028)) + (PORT datac (1215:1215:1215) (1268:1268:1268)) + (PORT datad (1202:1202:1202) (1282:1282:1282)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1381:1381:1381) (1391:1391:1391)) + (PORT datad (1159:1159:1159) (1197:1197:1197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~30) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (950:950:950)) + (PORT datab (1011:1011:1011) (1054:1054:1054)) + (PORT datac (971:971:971) (1026:1026:1026)) + (PORT datad (1020:1020:1020) (1094:1094:1094)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~31) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1006:1006:1006)) + (PORT datab (209:209:209) (252:252:252)) + (PORT datac (918:918:918) (958:958:958)) + (PORT datad (900:900:900) (933:933:933)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (417:417:417)) + (PORT datab (1760:1760:1760) (1818:1818:1818)) + (PORT datac (1126:1126:1126) (1134:1134:1134)) + (PORT datad (545:545:545) (556:556:556)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (896:896:896)) + (PORT datab (867:867:867) (903:903:903)) + (PORT datac (1726:1726:1726) (1786:1786:1786)) + (PORT datad (614:614:614) (636:636:636)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1237:1237:1237)) + (PORT datab (1201:1201:1201) (1235:1235:1235)) + (PORT datac (905:905:905) (951:951:951)) + (PORT datad (602:602:602) (617:617:617)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (479:479:479)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (968:968:968) (1000:1000:1000)) + (PORT datad (585:585:585) (603:603:603)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (479:479:479)) + (PORT datab (1954:1954:1954) (2006:2006:2006)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1434:1434:1434) (1530:1530:1530)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1242:1242:1242)) + (PORT datab (1237:1237:1237) (1278:1278:1278)) + (PORT datac (1416:1416:1416) (1453:1453:1453)) + (PORT datad (871:871:871) (912:912:912)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1477:1477:1477)) + (PORT datab (1804:1804:1804) (1863:1863:1863)) + (PORT datac (1442:1442:1442) (1467:1467:1467)) + (PORT datad (672:672:672) (729:729:729)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1276:1276:1276)) + (PORT datab (681:681:681) (723:723:723)) + (PORT datac (1635:1635:1635) (1657:1657:1657)) + (PORT datad (1117:1117:1117) (1177:1177:1177)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1188:1188:1188)) + (PORT datab (880:880:880) (894:894:894)) + (PORT datac (351:351:351) (379:379:379)) + (PORT datad (605:605:605) (616:616:616)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1362:1362:1362)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (641:641:641) (690:690:690)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (478:478:478)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1625:1625:1625) (1665:1665:1665)) + (PORT datad (586:586:586) (606:606:606)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1472:1472:1472)) + (PORT datab (459:459:459) (536:536:536)) + (PORT datac (1127:1127:1127) (1203:1203:1203)) + (PORT datad (395:395:395) (463:463:463)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1470:1470:1470)) + (PORT datab (998:998:998) (1028:1028:1028)) + (PORT datac (813:813:813) (846:846:846)) + (PORT datad (588:588:588) (604:604:604)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1570:1570:1570)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (943:943:943) (999:999:999)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (978:978:978)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (928:928:928) (965:965:965)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1439:1439:1439)) + (PORT datab (1524:1524:1524) (1560:1560:1560)) + (PORT datac (834:834:834) (845:845:845)) + (PORT datad (1194:1194:1194) (1276:1276:1276)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (682:682:682)) + (PORT datab (222:222:222) (270:270:270)) + (PORT datac (1384:1384:1384) (1435:1435:1435)) + (PORT datad (835:835:835) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla21M3T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (821:821:821)) + (PORT datab (1835:1835:1835) (1893:1893:1893)) + (PORT datac (1209:1209:1209) (1258:1258:1258)) + (PORT datad (1128:1128:1128) (1194:1194:1194)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (833:833:833) (851:851:851)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (942:942:942)) + (PORT datab (911:911:911) (984:984:984)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (581:581:581) (595:595:595)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (720:720:720)) + (PORT datad (805:805:805) (806:806:806)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1362:1362:1362) (1431:1431:1431)) + (PORT datab (1361:1361:1361) (1431:1431:1431)) + (PORT datac (1116:1116:1116) (1171:1171:1171)) + (PORT datad (1359:1359:1359) (1414:1414:1414)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datac (871:871:871) (905:905:905)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1214:1214:1214)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (2230:2230:2230) (2271:2271:2271)) + (PORT datad (1159:1159:1159) (1205:1205:1205)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1263:1263:1263)) + (PORT datab (1244:1244:1244) (1282:1282:1282)) + (PORT datac (983:983:983) (1041:1041:1041)) + (PORT datad (877:877:877) (942:942:942)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (732:732:732) (770:770:770)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (2485:2485:2485) (2527:2527:2527)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1295:1295:1295)) + (PORT datab (2818:2818:2818) (2933:2933:2933)) + (PORT datac (1500:1500:1500) (1565:1565:1565)) + (PORT datad (548:548:548) (560:560:560)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1374:1374:1374)) + (PORT datab (1710:1710:1710) (1774:1774:1774)) + (PORT datac (1195:1195:1195) (1300:1300:1300)) + (PORT datad (1121:1121:1121) (1167:1167:1167)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (925:925:925)) + (PORT datab (689:689:689) (751:751:751)) + (PORT datac (1525:1525:1525) (1625:1625:1625)) + (PORT datad (903:903:903) (944:944:944)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1168:1168:1168)) + (PORT datab (1176:1176:1176) (1191:1191:1191)) + (PORT datac (815:815:815) (849:849:849)) + (PORT datad (1233:1233:1233) (1285:1285:1285)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (700:700:700)) + (PORT datab (932:932:932) (998:998:998)) + (PORT datac (1491:1491:1491) (1548:1548:1548)) + (PORT datad (887:887:887) (930:930:930)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1022:1022:1022)) + (PORT datab (932:932:932) (967:967:967)) + (PORT datac (1752:1752:1752) (1833:1833:1833)) + (PORT datad (977:977:977) (1053:1053:1053)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (647:647:647) (665:665:665)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1301:1301:1301)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (877:877:877) (906:906:906)) + (PORT datad (627:627:627) (640:640:640)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (385:385:385)) + (PORT datab (1196:1196:1196) (1226:1226:1226)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (1084:1084:1084) (1142:1142:1142)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (1190:1190:1190) (1222:1222:1222)) + (PORT datac (1093:1093:1093) (1153:1153:1153)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (992:992:992)) + (PORT datab (1264:1264:1264) (1337:1337:1337)) + (PORT datad (1208:1208:1208) (1215:1215:1215)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1194:1194:1194)) + (PORT datad (1172:1172:1172) (1208:1208:1208)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1501:1501:1501) (1568:1568:1568)) + (PORT datab (234:234:234) (279:279:279)) + (PORT datac (1472:1472:1472) (1537:1537:1537)) + (PORT datad (1234:1234:1234) (1360:1360:1360)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1514:1514:1514) (1575:1575:1575)) + (PORT datab (1498:1498:1498) (1572:1572:1572)) + (PORT datac (1384:1384:1384) (1449:1449:1449)) + (PORT datad (332:332:332) (349:349:349)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1227:1227:1227)) + (PORT datab (236:236:236) (282:282:282)) + (PORT datac (1110:1110:1110) (1181:1181:1181)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1827:1827:1827) (1962:1962:1962)) + (PORT datab (682:682:682) (792:792:792)) + (PORT datac (2257:2257:2257) (2333:2333:2333)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (844:844:844)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (612:612:612) (655:655:655)) + (PORT datad (1430:1430:1430) (1511:1511:1511)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (364:364:364) (392:392:392)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (803:803:803) (811:811:811)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT datab (668:668:668) (727:727:727)) + (PORT datac (677:677:677) (727:727:727)) + (PORT datad (370:370:370) (400:400:400)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1224:1224:1224)) + (PORT datac (1112:1112:1112) (1181:1181:1181)) + (PORT datad (194:194:194) (227:227:227)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (610:610:610)) + (PORT datab (644:644:644) (653:653:653)) + (PORT datac (905:905:905) (927:927:927)) + (PORT datad (584:584:584) (594:594:594)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT datab (722:722:722) (795:795:795)) + (PORT datac (734:734:734) (831:831:831)) + (PORT datad (652:652:652) (687:687:687)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (908:908:908)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1570:1570:1570)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (1470:1470:1470) (1536:1536:1536)) + (PORT datad (671:671:671) (768:768:768)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1573:1573:1573)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (1470:1470:1470) (1539:1539:1539)) + (PORT datad (673:673:673) (769:769:769)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1704:1704:1704)) + (PORT datab (427:427:427) (459:459:459)) + (PORT datac (582:582:582) (586:586:586)) + (PORT datad (390:390:390) (413:413:413)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (703:703:703)) + (PORT datab (239:239:239) (285:285:285)) + (PORT datac (515:515:515) (526:526:526)) + (PORT datad (325:325:325) (348:348:348)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT datab (1123:1123:1123) (1187:1187:1187)) + (PORT datac (1160:1160:1160) (1187:1187:1187)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (340:340:340) (360:360:360)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (268:268:268)) + (PORT datac (1167:1167:1167) (1192:1192:1192)) + (PORT datad (1085:1085:1085) (1143:1143:1143)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1265:1265:1265) (1293:1293:1293)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (278:278:278)) + (PORT datab (1197:1197:1197) (1227:1227:1227)) + (PORT datac (1095:1095:1095) (1158:1158:1158)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1262:1262:1262) (1289:1289:1289)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1045:1045:1045)) + (PORT datab (741:741:741) (776:776:776)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1221:1221:1221)) + (PORT datab (1171:1171:1171) (1225:1225:1225)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1489:1489:1489)) + (PORT datab (1452:1452:1452) (1522:1522:1522)) + (PORT datac (194:194:194) (240:240:240)) + (PORT datad (1460:1460:1460) (1535:1535:1535)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (538:538:538) (568:568:568)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1477:1477:1477)) + (PORT datab (1029:1029:1029) (1025:1025:1025)) + (PORT datad (810:810:810) (811:811:811)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1230:1230:1230)) + (PORT datac (1114:1114:1114) (1183:1183:1183)) + (PORT datad (196:196:196) (231:231:231)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (999:999:999) (1050:1050:1050)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (630:630:630) (677:677:677)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1227:1227:1227)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (1110:1110:1110) (1181:1181:1181)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (734:734:734)) + (PORT datab (724:724:724) (773:773:773)) + (PORT datad (364:364:364) (424:424:424)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (627:627:627) (674:674:674)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (986:986:986)) + (PORT datab (1272:1272:1272) (1347:1347:1347)) + (PORT datad (1209:1209:1209) (1216:1216:1216)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (277:277:277)) + (PORT datab (1501:1501:1501) (1574:1574:1574)) + (PORT datac (1475:1475:1475) (1535:1535:1535)) + (PORT datad (1507:1507:1507) (1610:1610:1610)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (996:996:996) (1047:1047:1047)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (696:696:696)) + (PORT datab (680:680:680) (731:731:731)) + (PORT datad (894:894:894) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (827:827:827)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (812:812:812)) + (PORT datab (1503:1503:1503) (1577:1577:1577)) + (PORT datac (197:197:197) (243:243:243)) + (PORT datad (1429:1429:1429) (1486:1486:1486)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (808:808:808)) + (PORT datab (1498:1498:1498) (1571:1571:1571)) + (PORT datac (194:194:194) (236:236:236)) + (PORT datad (1427:1427:1427) (1483:1483:1483)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1159:1159:1159) (1186:1186:1186)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (721:721:721)) + (PORT datab (421:421:421) (461:461:461)) + (PORT datad (386:386:386) (415:415:415)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT datab (663:663:663) (724:724:724)) + (PORT datac (676:676:676) (731:731:731)) + (PORT datad (369:369:369) (406:406:406)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1160:1160:1160) (1184:1184:1184)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (933:933:933) (957:957:957)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (646:646:646)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (839:839:839) (868:868:868)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (986:986:986)) + (PORT datab (1261:1261:1261) (1341:1341:1341)) + (PORT datad (632:632:632) (675:675:675)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (986:986:986)) + (PORT datab (1262:1262:1262) (1339:1339:1339)) + (PORT datad (643:643:643) (685:685:685)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (985:985:985)) + (PORT datab (1272:1272:1272) (1347:1347:1347)) + (PORT datad (634:634:634) (675:675:675)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1242:1242:1242) (1262:1262:1262)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (990:990:990)) + (PORT datab (1272:1272:1272) (1344:1344:1344)) + (PORT datad (641:641:641) (682:682:682)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1242:1242:1242) (1262:1262:1262)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (999:999:999)) + (PORT datab (966:966:966) (1017:1017:1017)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (581:581:581) (605:605:605)) + (PORT datad (339:339:339) (358:358:358)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (929:929:929)) + (PORT datab (882:882:882) (889:889:889)) + (PORT datac (922:922:922) (952:952:952)) + (PORT datad (576:576:576) (587:587:587)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (447:447:447)) + (PORT datab (957:957:957) (990:990:990)) + (PORT datad (631:631:631) (680:680:680)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (889:889:889) (902:902:902)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (447:447:447)) + (PORT datab (960:960:960) (991:991:991)) + (PORT datad (639:639:639) (685:685:685)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1307:1307:1307)) + (PORT datab (660:660:660) (701:701:701)) + (PORT datad (648:648:648) (673:673:673)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (447:447:447)) + (PORT datab (668:668:668) (726:726:726)) + (PORT datad (564:564:564) (571:571:571)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (452:452:452)) + (PORT datab (662:662:662) (724:724:724)) + (PORT datad (566:566:566) (575:575:575)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (665:665:665) (681:681:681)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (724:724:724)) + (PORT datab (667:667:667) (691:691:691)) + (PORT datac (1215:1215:1215) (1266:1266:1266)) + (PORT datad (644:644:644) (667:667:667)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT datac (631:631:631) (677:677:677)) + (PORT datad (1078:1078:1078) (1110:1110:1110)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1182:1182:1182) (1208:1208:1208)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1182:1182:1182) (1207:1207:1207)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1038:1038:1038)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (704:704:704) (741:741:741)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1205:1205:1205) (1227:1227:1227)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1479:1479:1479)) + (PORT datab (838:838:838) (850:850:850)) + (PORT datad (809:809:809) (813:813:813)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1441:1441:1441) (1456:1456:1456)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (904:904:904) (941:941:941)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (737:737:737)) + (PORT datab (727:727:727) (774:774:774)) + (PORT datad (360:360:360) (419:419:419)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (955:955:955) (983:983:983)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (480:480:480)) + (PORT datab (418:418:418) (454:454:454)) + (PORT datad (386:386:386) (412:412:412)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (957:957:957) (980:980:980)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (933:933:933) (957:957:957)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (904:904:904) (944:944:944)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1441:1441:1441) (1458:1458:1458)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (717:717:717)) + (PORT datab (677:677:677) (727:727:727)) + (PORT datad (890:890:890) (918:918:918)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (701:701:701)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (891:891:891) (905:905:905)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1188:1188:1188) (1209:1209:1209)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1188:1188:1188) (1210:1210:1210)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (994:994:994)) + (PORT datab (962:962:962) (1011:1011:1011)) + (PORT datad (215:215:215) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (596:596:596) (623:623:623)) + (PORT datad (316:316:316) (336:336:336)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (866:866:866)) + (PORT datab (866:866:866) (881:881:881)) + (PORT datac (558:558:558) (572:572:572)) + (PORT datad (600:600:600) (615:615:615)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (876:876:876) (886:886:886)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1304:1304:1304)) + (PORT datab (1130:1130:1130) (1137:1137:1137)) + (PORT datad (649:649:649) (670:670:670)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (326:326:326)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (664:664:664) (681:681:681)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (723:723:723)) + (PORT datab (567:567:567) (586:586:586)) + (PORT datac (226:226:226) (271:271:271)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (712:712:712)) + (PORT datad (775:775:775) (790:790:790)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (359:359:359)) + (PORT datab (578:578:578) (599:599:599)) + (PORT datac (630:630:630) (677:677:677)) + (PORT datad (1077:1077:1077) (1109:1109:1109)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (723:723:723)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (224:224:224) (269:269:269)) + (PORT datad (1029:1029:1029) (1022:1022:1022)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (713:713:713)) + (PORT datad (852:852:852) (855:855:855)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (662:662:662)) + (PORT datad (245:245:245) (318:318:318)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datab (660:660:660) (712:712:712)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1151:1151:1151)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (853:853:853) (872:872:872)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1254:1254:1254) (1306:1306:1306)) + (PORT datab (823:823:823) (859:859:859)) + (PORT datad (645:645:645) (668:668:668)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (331:331:331)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (663:663:663) (679:679:679)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (724:724:724)) + (PORT datab (829:829:829) (850:850:850)) + (PORT datac (225:225:225) (269:269:269)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (802:802:802) (827:827:827)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1147:1147:1147) (1156:1156:1156)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (910:910:910) (935:935:935)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1707:1707:1707)) + (PORT datab (850:850:850) (877:877:877)) + (PORT datad (394:394:394) (420:420:420)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (912:912:912) (935:935:935)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~58) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (235:235:235)) + (PORT datad (938:938:938) (958:958:958)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1194:1194:1194) (1212:1212:1212)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (846:846:846) (865:865:865)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (459:459:459)) + (PORT datab (836:836:836) (853:853:853)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (935:935:935) (962:962:962)) + (PORT ena (1226:1226:1226) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (931:931:931) (960:960:960)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (885:885:885) (909:909:909)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1286:1286:1286) (1318:1318:1318)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (731:731:731)) + (PORT datab (417:417:417) (483:483:483)) + (PORT datad (687:687:687) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (372:372:372)) + (PORT datab (624:624:624) (639:639:639)) + (PORT datac (557:557:557) (563:563:563)) + (PORT datad (845:845:845) (856:856:856)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (595:595:595) (608:608:608)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (968:968:968) (987:987:987)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1045:1045:1045)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (701:701:701) (746:746:746)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (630:630:630)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (589:589:589) (601:601:601)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (858:858:858)) + (PORT datab (652:652:652) (683:683:683)) + (PORT datac (882:882:882) (886:886:886)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (393:393:393)) + (PORT datab (1136:1136:1136) (1147:1147:1147)) + (PORT datac (384:384:384) (413:413:413)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (397:397:397)) + (PORT datab (377:377:377) (413:413:413)) + (PORT datac (1305:1305:1305) (1292:1292:1292)) + (PORT datad (616:616:616) (633:633:633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (750:750:750)) + (PORT datab (268:268:268) (320:320:320)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (764:764:764) (780:780:780)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1479:1479:1479) (1541:1541:1541)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (869:869:869)) + (PORT datab (1234:1234:1234) (1268:1268:1268)) + (PORT datad (859:859:859) (877:877:877)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1941:1941:1941) (2022:2022:2022)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1942:1942:1942) (2022:2022:2022)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (755:755:755)) + (PORT datab (670:670:670) (714:714:714)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (536:536:536) (566:566:566)) + (PORT ena (2046:2046:2046) (2144:2144:2144)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1772:1772:1772) (1839:1839:1839)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (734:734:734)) + (PORT datab (458:458:458) (504:504:504)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1620:1620:1620) (1689:1689:1689)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1617:1617:1617) (1686:1686:1686)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (976:976:976)) + (PORT datab (896:896:896) (929:929:929)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (895:895:895)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (546:546:546) (569:569:569)) + (PORT datad (801:801:801) (849:849:849)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1482:1482:1482) (1550:1550:1550)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1451:1451:1451)) + (PORT datab (1366:1366:1366) (1446:1446:1446)) + (PORT datad (871:871:871) (897:897:897)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1523:1523:1523)) + (PORT asdata (1192:1192:1192) (1252:1252:1252)) + (PORT ena (1490:1490:1490) (1524:1524:1524)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1483:1483:1483) (1547:1547:1547)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (969:969:969)) + (PORT datab (876:876:876) (966:966:966)) + (PORT datad (992:992:992) (1049:1049:1049)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1218:1218:1218) (1275:1275:1275)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1218:1218:1218) (1275:1275:1275)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (904:904:904)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (837:837:837) (854:854:854)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (888:888:888)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (366:366:366) (393:393:393)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (708:708:708)) + (PORT datab (237:237:237) (281:281:281)) + (PORT datac (372:372:372) (398:398:398)) + (PORT datad (599:599:599) (615:615:615)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1014:1014:1014)) + (PORT datab (906:906:906) (987:987:987)) + (PORT datac (560:560:560) (583:583:583)) + (PORT datad (660:660:660) (700:700:700)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (717:717:717) (745:745:745)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1247:1247:1247)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (1271:1271:1271) (1376:1376:1376)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (630:630:630)) + (PORT datac (1101:1101:1101) (1119:1119:1119)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (887:887:887) (910:910:910)) + (PORT datad (351:351:351) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1535:1535:1535)) + (PORT ena (1964:1964:1964) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datad (246:246:246) (319:319:319)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (1077:1077:1077) (1108:1108:1108)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (703:703:703)) + (PORT datac (633:633:633) (654:654:654)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1569:1569:1569) (1588:1588:1588)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (922:922:922) (940:940:940)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (998:998:998)) + (PORT datab (963:963:963) (1015:1015:1015)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (688:688:688) (717:717:717)) + (PORT ena (1179:1179:1179) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (884:884:884) (903:903:903)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (887:887:887) (907:907:907)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (462:462:462)) + (PORT datab (834:834:834) (846:846:846)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (883:883:883)) + (PORT datad (330:330:330) (348:348:348)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1529:1529:1529) (1551:1551:1551)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1527:1527:1527) (1549:1549:1549)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1045:1045:1045)) + (PORT datab (740:740:740) (780:780:780)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1177:1177:1177)) + (PORT datab (1145:1145:1145) (1164:1164:1164)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1129:1129:1129) (1128:1128:1128)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1430:1430:1430) (1432:1432:1432)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (428:428:428) (462:462:462)) + (PORT datad (390:390:390) (417:417:417)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (635:635:635) (667:667:667)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (985:985:985) (1009:1009:1009)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (737:737:737)) + (PORT datab (418:418:418) (485:485:485)) + (PORT datad (686:686:686) (732:732:732)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (643:643:643)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (905:905:905) (928:928:928)) + (PORT datad (629:629:629) (642:642:642)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (886:886:886)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1052:1052:1052) (1054:1054:1054)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (920:920:920) (934:934:934)) + (PORT datac (633:633:633) (644:644:644)) + (PORT datad (1418:1418:1418) (1446:1446:1446)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (679:679:679) (705:705:705)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1300:1300:1300)) + (PORT datab (655:655:655) (670:670:670)) + (PORT datad (650:650:650) (675:675:675)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (663:663:663) (683:683:683)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (723:723:723)) + (PORT datab (810:810:810) (825:825:825)) + (PORT datac (225:225:225) (269:269:269)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datac (1193:1193:1193) (1221:1221:1221)) + (PORT datad (552:552:552) (561:561:561)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (692:692:692)) + (PORT datab (632:632:632) (700:700:700)) + (PORT datac (238:238:238) (328:328:328)) + (PORT datad (622:622:622) (637:637:637)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1255:1255:1255) (1261:1261:1261)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1311:1311:1311) (1339:1339:1339)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1315:1315:1315) (1344:1344:1344)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1038:1038:1038)) + (PORT datab (743:743:743) (786:786:786)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1168:1168:1168) (1185:1185:1185)) + (PORT ena (1226:1226:1226) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1165:1165:1165) (1181:1181:1181)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (234:234:234) (279:279:279)) + (PORT datad (210:210:210) (241:241:241)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1160:1160:1160) (1180:1180:1180)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (1014:1014:1014)) + (PORT datac (796:796:796) (828:828:828)) + (PORT datad (601:601:601) (628:628:628)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (809:809:809)) + (PORT datab (1367:1367:1367) (1398:1398:1398)) + (PORT datac (1048:1048:1048) (1129:1129:1129)) + (PORT datad (713:713:713) (772:772:772)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (680:680:680)) + (PORT datab (1170:1170:1170) (1204:1204:1204)) + (PORT datac (1149:1149:1149) (1177:1177:1177)) + (PORT datad (827:827:827) (835:835:835)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (889:889:889)) + (PORT datab (1717:1717:1717) (1745:1745:1745)) + (PORT datac (1348:1348:1348) (1452:1452:1452)) + (PORT datad (689:689:689) (739:739:739)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (536:536:536) (567:567:567)) + (PORT ena (1671:1671:1671) (1717:1717:1717)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (345:345:345)) + (PORT datab (280:280:280) (341:341:341)) + (PORT datac (1254:1254:1254) (1299:1299:1299)) + (PORT datad (244:244:244) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (969:969:969)) + (PORT datab (841:841:841) (860:860:860)) + (PORT datac (606:606:606) (645:645:645)) + (PORT datad (781:781:781) (829:829:829)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (642:642:642)) + (PORT datab (681:681:681) (714:714:714)) + (PORT datac (1046:1046:1046) (1072:1072:1072)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1491:1491:1491)) + (PORT datab (839:839:839) (859:859:859)) + (PORT datac (632:632:632) (657:657:657)) + (PORT datad (915:915:915) (974:974:974)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (804:804:804)) + (PORT datac (1048:1048:1048) (1128:1128:1128)) + (PORT datad (711:711:711) (771:771:771)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (422:422:422)) + (PORT datab (882:882:882) (942:942:942)) + (PORT datac (1468:1468:1468) (1500:1500:1500)) + (PORT datad (226:226:226) (265:265:265)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (904:904:904) (945:945:945)) + (PORT datad (337:337:337) (365:365:365)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2567:2567:2567)) + (PORT datab (959:959:959) (1000:1000:1000)) + (PORT datac (1184:1184:1184) (1264:1264:1264)) + (PORT datad (1217:1217:1217) (1295:1295:1295)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (756:756:756)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (926:926:926) (963:963:963)) + (PORT datad (656:656:656) (698:698:698)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (636:636:636) (679:679:679)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (831:831:831)) + (PORT datab (644:644:644) (667:667:667)) + (PORT datac (636:636:636) (665:665:665)) + (PORT datad (531:531:531) (539:539:539)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~0) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (532:532:532)) + (PORT datab (2098:2098:2098) (2171:2171:2171)) + (PORT datac (1131:1131:1131) (1191:1191:1191)) + (PORT datad (1023:1023:1023) (1128:1128:1128)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (902:902:902)) + (PORT datab (1088:1088:1088) (1116:1116:1116)) + (PORT datac (611:611:611) (676:676:676)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1296:1296:1296)) + (PORT datab (1835:1835:1835) (1895:1895:1895)) + (PORT datac (1362:1362:1362) (1393:1393:1393)) + (PORT datad (1227:1227:1227) (1305:1305:1305)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1173:1173:1173)) + (PORT datab (1089:1089:1089) (1116:1116:1116)) + (PORT datac (614:614:614) (674:674:674)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (537:537:537)) + (PORT datab (2096:2096:2096) (2170:2170:2170)) + (PORT datac (1126:1126:1126) (1187:1187:1187)) + (PORT datad (1025:1025:1025) (1130:1130:1130)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (898:898:898)) + (PORT datab (860:860:860) (875:875:875)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (957:957:957)) + (PORT datad (957:957:957) (1062:1062:1062)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (892:892:892)) + (PORT datab (893:893:893) (937:937:937)) + (PORT datac (630:630:630) (666:666:666)) + (PORT datad (611:611:611) (631:631:631)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (875:875:875) (921:921:921)) + (PORT datac (865:865:865) (882:882:882)) + (PORT datad (213:213:213) (247:247:247)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2316:2316:2316) (2437:2437:2437)) + (PORT datab (843:843:843) (864:864:864)) + (PORT datac (1296:1296:1296) (1411:1411:1411)) + (PORT datad (1401:1401:1401) (1447:1447:1447)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (895:895:895)) + (PORT datab (1228:1228:1228) (1263:1263:1263)) + (PORT datac (626:626:626) (663:663:663)) + (PORT datad (615:615:615) (636:636:636)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1358:1358:1358)) + (PORT datab (357:357:357) (391:391:391)) + (PORT datac (1557:1557:1557) (1711:1711:1711)) + (PORT datad (1418:1418:1418) (1491:1491:1491)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (965:965:965)) + (PORT datab (1199:1199:1199) (1296:1296:1296)) + (PORT datac (1945:1945:1945) (2013:2013:2013)) + (PORT datad (898:898:898) (936:936:936)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (640:640:640) (708:708:708)) + (PORT datac (584:584:584) (623:623:623)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1603:1603:1603)) + (PORT datab (1213:1213:1213) (1267:1267:1267)) + (PORT datac (358:358:358) (380:380:380)) + (PORT datad (927:927:927) (963:963:963)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1337:1337:1337) (1352:1352:1352)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1516:1516:1516) (1615:1615:1615)) + (PORT datad (1566:1566:1566) (1661:1661:1661)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (406:406:406)) + (PORT datab (936:936:936) (976:976:976)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1815:1815:1815) (1814:1814:1814)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (922:922:922)) + (PORT datab (933:933:933) (974:974:974)) + (PORT datac (602:602:602) (620:620:620)) + (PORT datad (1828:1828:1828) (1898:1898:1898)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~20) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1067:1067:1067)) + (PORT datab (1009:1009:1009) (1110:1110:1110)) + (PORT datad (2097:2097:2097) (2243:2243:2243)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (883:883:883)) + (PORT datab (854:854:854) (915:915:915)) + (PORT datac (602:602:602) (623:623:623)) + (PORT datad (878:878:878) (919:919:919)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (547:547:547) (576:576:576)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (997:997:997)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datac (208:208:208) (251:251:251)) + (PORT datad (1389:1389:1389) (1443:1443:1443)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (458:458:458)) + (PORT datab (881:881:881) (913:913:913)) + (PORT datac (343:343:343) (369:369:369)) + (PORT datad (1010:1010:1010) (1068:1068:1068)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (991:991:991)) + (PORT datab (671:671:671) (693:693:693)) + (PORT datac (1299:1299:1299) (1337:1337:1337)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (642:642:642) (667:667:667)) + (PORT datac (603:603:603) (622:622:622)) + (PORT datad (612:612:612) (660:660:660)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (539:539:539) (570:570:570)) + (PORT ena (1190:1190:1190) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1269:1269:1269)) + (PORT datab (1182:1182:1182) (1219:1219:1219)) + (PORT datad (580:580:580) (598:598:598)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1199:1199:1199) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (543:543:543) (597:597:597)) + (PORT datad (601:601:601) (622:622:622)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (1171:1171:1171) (1261:1261:1261)) + (PORT datac (180:180:180) (219:219:219)) + (PORT datad (583:583:583) (597:597:597)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (737:737:737)) + (PORT datab (343:343:343) (374:374:374)) + (PORT datac (208:208:208) (248:248:248)) + (PORT datad (607:607:607) (629:629:629)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1514:1514:1514) (1541:1541:1541)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1196:1196:1196) (1227:1227:1227)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (226:226:226) (268:268:268)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1809:1809:1809) (1838:1838:1838)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1810:1810:1810) (1839:1839:1839)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1041:1041:1041)) + (PORT datab (740:740:740) (780:780:780)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (2306:2306:2306) (2350:2350:2350)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (2278:2278:2278) (2302:2302:2302)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datad (661:661:661) (711:711:711)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (2803:2803:2803) (2797:2797:2797)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (394:394:394)) + (PORT datad (938:938:938) (962:962:962)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (315:315:315) (334:334:334)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1179:1179:1179) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (2553:2553:2553) (2567:2567:2567)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (456:456:456)) + (PORT datab (383:383:383) (457:457:457)) + (PORT datad (639:639:639) (653:653:653)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1448:1448:1448) (1477:1477:1477)) + (PORT datab (839:839:839) (852:852:852)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (864:864:864) (866:866:866)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (373:373:373)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (2628:2628:2628) (2644:2644:2644)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (963:963:963) (991:991:991)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (736:736:736)) + (PORT datab (727:727:727) (767:767:767)) + (PORT datad (382:382:382) (441:441:441)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (658:658:658)) + (PORT datab (870:870:870) (889:889:889)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (930:930:930)) + (PORT datab (951:951:951) (986:986:986)) + (PORT datac (596:596:596) (616:616:616)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1718:1718:1718) (1746:1746:1746)) + (PORT datab (890:890:890) (903:903:903)) + (PORT datac (873:873:873) (902:902:902)) + (PORT datad (1136:1136:1136) (1145:1145:1145)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (674:674:674)) + (PORT datac (559:559:559) (577:577:577)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1241:1241:1241)) + (PORT datab (707:707:707) (749:749:749)) + (PORT datac (918:918:918) (930:930:930)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (735:735:735)) + (PORT datab (602:602:602) (617:617:617)) + (PORT datac (909:909:909) (942:942:942)) + (PORT datad (835:835:835) (830:830:830)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (528:528:528) (541:541:541)) + (PORT datad (353:353:353) (374:374:374)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1219:1219:1219)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datac (592:592:592) (613:613:613)) + (PORT datad (400:400:400) (447:447:447)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1185:1185:1185)) + (PORT datab (1352:1352:1352) (1463:1463:1463)) + (PORT datac (1461:1461:1461) (1528:1528:1528)) + (PORT datad (1062:1062:1062) (1086:1086:1086)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (992:992:992)) + (PORT datab (215:215:215) (257:257:257)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1167:1167:1167) (1229:1229:1229)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1580:1580:1580)) + (PORT datab (963:963:963) (1020:1020:1020)) + (PORT datac (1687:1687:1687) (1746:1746:1746)) + (PORT datad (215:215:215) (240:240:240)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (309:309:309)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (201:201:201) (230:230:230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1296:1296:1296)) + (PORT datab (1211:1211:1211) (1223:1223:1223)) + (PORT datac (935:935:935) (978:978:978)) + (PORT datad (1331:1331:1331) (1336:1336:1336)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (849:849:849)) + (PORT datab (637:637:637) (662:662:662)) + (PORT datac (838:838:838) (851:851:851)) + (PORT datad (542:542:542) (547:547:547)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1253:1253:1253)) + (PORT datac (2400:2400:2400) (2523:2523:2523)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1336:1336:1336) (1367:1367:1367)) + (PORT datab (924:924:924) (972:972:972)) + (PORT datad (793:793:793) (791:791:791)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1381:1381:1381)) + (PORT datab (658:658:658) (711:711:711)) + (PORT datac (618:618:618) (636:636:636)) + (PORT datad (1741:1741:1741) (1799:1799:1799)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (655:655:655)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (514:514:514) (528:528:528)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (695:695:695)) + (PORT datab (1971:1971:1971) (2032:2032:2032)) + (PORT datac (814:814:814) (830:830:830)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1147:1147:1147)) + (PORT datab (858:858:858) (871:871:871)) + (PORT datac (631:631:631) (646:646:646)) + (PORT datad (697:697:697) (762:762:762)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1620:1620:1620) (1753:1753:1753)) + (PORT datab (1144:1144:1144) (1204:1204:1204)) + (PORT datac (1810:1810:1810) (1924:1924:1924)) + (PORT datad (1650:1650:1650) (1753:1753:1753)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (956:956:956)) + (PORT datab (638:638:638) (664:664:664)) + (PORT datac (202:202:202) (245:245:245)) + (PORT datad (840:840:840) (889:889:889)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1145:1145:1145) (1182:1182:1182)) + (PORT datac (1054:1054:1054) (1068:1068:1068)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1132:1132:1132)) + (PORT datab (1027:1027:1027) (1143:1143:1143)) + (PORT datac (1216:1216:1216) (1293:1293:1293)) + (PORT datad (880:880:880) (901:901:901)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~1) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (1399:1399:1399) (1472:1472:1472)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1821:1821:1821) (1890:1890:1890)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (698:698:698)) + (PORT datab (1971:1971:1971) (2031:2031:2031)) + (PORT datac (330:330:330) (365:365:365)) + (PORT datad (890:890:890) (918:918:918)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1163:1163:1163) (1217:1217:1217)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1677:1677:1677) (1775:1775:1775)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (908:908:908)) + (PORT datab (239:239:239) (320:320:320)) + (PORT datad (840:840:840) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (992:992:992) (1051:1051:1051)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1448:1448:1448)) + (PORT datab (1365:1365:1365) (1445:1445:1445)) + (PORT datad (871:871:871) (897:897:897)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1013:1013:1013) (1061:1061:1061)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1013:1013:1013) (1064:1064:1064)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (982:982:982)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (863:863:863) (895:895:895)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (984:984:984) (1027:1027:1027)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (925:925:925)) + (PORT datab (1233:1233:1233) (1269:1269:1269)) + (PORT datad (911:911:911) (931:931:931)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (665:665:665) (686:686:686)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (327:327:327)) + (PORT datab (457:457:457) (498:498:498)) + (PORT datad (1156:1156:1156) (1206:1206:1206)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1694:1694:1694) (1774:1774:1774)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1694:1694:1694) (1771:1771:1771)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (752:752:752)) + (PORT datab (671:671:671) (717:717:717)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (867:867:867)) + (PORT datab (372:372:372) (396:396:396)) + (PORT datac (616:616:616) (662:662:662)) + (PORT datad (784:784:784) (852:852:852)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1523:1523:1523)) + (PORT asdata (1544:1544:1544) (1603:1603:1603)) + (PORT ena (1490:1490:1490) (1524:1524:1524)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (991:991:991) (1048:1048:1048)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (970:970:970)) + (PORT datab (851:851:851) (954:954:954)) + (PORT datad (991:991:991) (1049:1049:1049)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (443:443:443)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (893:893:893) (915:915:915)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1879:1879:1879) (1962:1962:1962)) + (PORT datab (1315:1315:1315) (1420:1420:1420)) + (PORT datad (1164:1164:1164) (1194:1194:1194)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (487:487:487)) + (PORT datac (1146:1146:1146) (1169:1169:1169)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (712:712:712)) + (PORT datac (641:641:641) (660:660:660)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (671:671:671)) + (PORT datab (896:896:896) (911:911:911)) + (PORT datac (881:881:881) (927:927:927)) + (PORT datad (691:691:691) (749:749:749)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (393:393:393)) + (PORT datab (398:398:398) (437:437:437)) + (PORT datac (1162:1162:1162) (1200:1200:1200)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (756:756:756)) + (PORT datab (605:605:605) (652:652:652)) + (PORT datac (616:616:616) (668:668:668)) + (PORT datad (826:826:826) (847:847:847)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1036:1036:1036)) + (PORT datab (638:638:638) (674:674:674)) + (PORT datac (912:912:912) (963:963:963)) + (PORT datad (654:654:654) (701:701:701)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (267:267:267) (321:321:321)) + (PORT datac (814:814:814) (833:833:833)) + (PORT datad (894:894:894) (933:933:933)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (869:869:869)) + (PORT datac (891:891:891) (917:917:917)) + (PORT datad (1213:1213:1213) (1252:1252:1252)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1212:1212:1212)) + (PORT datac (605:605:605) (646:646:646)) + (PORT datad (813:813:813) (822:822:822)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1210:1210:1210)) + (PORT datab (612:612:612) (655:655:655)) + (PORT datac (831:831:831) (837:837:837)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (612:612:612) (654:654:654)) + (PORT datad (514:514:514) (528:528:528)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1160:1160:1160)) + (PORT datab (261:261:261) (342:342:342)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1809:1809:1809)) + (PORT datab (1020:1020:1020) (1114:1114:1114)) + (PORT datac (1370:1370:1370) (1419:1419:1419)) + (PORT datad (1433:1433:1433) (1514:1514:1514)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1301:1301:1301)) + (PORT datab (1748:1748:1748) (1799:1799:1799)) + (PORT datac (1454:1454:1454) (1621:1621:1621)) + (PORT datad (189:189:189) (223:223:223)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1589:1589:1589) (1734:1734:1734)) + (PORT datab (2048:2048:2048) (2150:2150:2150)) + (PORT datac (1126:1126:1126) (1163:1163:1163)) + (PORT datad (1100:1100:1100) (1161:1161:1161)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (878:878:878)) + (PORT datab (735:735:735) (802:802:802)) + (PORT datac (595:595:595) (614:614:614)) + (PORT datad (1081:1081:1081) (1102:1102:1102)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1381:1381:1381)) + (PORT datab (1727:1727:1727) (1752:1752:1752)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (630:630:630) (688:688:688)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1563:1563:1563)) + (PORT datab (2046:2046:2046) (2147:2147:2147)) + (PORT datac (2362:2362:2362) (2509:2509:2509)) + (PORT datad (387:387:387) (405:405:405)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (378:378:378) (401:401:401)) + (PORT datac (851:851:851) (874:874:874)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1104:1104:1104)) + (PORT datab (895:895:895) (915:915:915)) + (PORT datac (867:867:867) (916:916:916)) + (PORT datad (1033:1033:1033) (1062:1062:1062)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (606:606:606)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (633:633:633) (662:662:662)) + (PORT datad (654:654:654) (708:708:708)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (383:383:383)) + (PORT datab (233:233:233) (278:278:278)) + (PORT datac (533:533:533) (537:537:537)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (886:886:886)) + (PORT datab (1000:1000:1000) (1066:1066:1066)) + (PORT datac (2267:2267:2267) (2409:2409:2409)) + (PORT datad (1757:1757:1757) (1881:1881:1881)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (888:888:888)) + (PORT datab (1164:1164:1164) (1205:1205:1205)) + (PORT datac (2266:2266:2266) (2411:2411:2411)) + (PORT datad (1756:1756:1756) (1885:1885:1885)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (889:889:889)) + (PORT datab (1180:1180:1180) (1219:1219:1219)) + (PORT datac (2266:2266:2266) (2410:2410:2410)) + (PORT datad (1756:1756:1756) (1883:1883:1883)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (915:915:915)) + (PORT datac (774:774:774) (785:785:785)) + (PORT datad (1034:1034:1034) (1051:1051:1051)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (955:955:955) (1006:1006:1006)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (536:536:536)) + (PORT datab (2097:2097:2097) (2166:2166:2166)) + (PORT datac (1127:1127:1127) (1184:1184:1184)) + (PORT datad (1028:1028:1028) (1134:1134:1134)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (662:662:662)) + (PORT datab (2979:2979:2979) (3106:3106:3106)) + (PORT datac (568:568:568) (583:583:583)) + (PORT datad (1340:1340:1340) (1383:1383:1383)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1017:1017:1017)) + (PORT datab (620:620:620) (646:646:646)) + (PORT datad (507:507:507) (522:522:522)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1001:1001:1001)) + (PORT datab (1478:1478:1478) (1557:1557:1557)) + (PORT datac (2332:2332:2332) (2440:2440:2440)) + (PORT datad (1745:1745:1745) (1802:1802:1802)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1105:1105:1105)) + (PORT datab (874:874:874) (922:922:922)) + (PORT datac (866:866:866) (915:915:915)) + (PORT datad (1088:1088:1088) (1120:1120:1120)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (312:312:312)) + (PORT datab (960:960:960) (1016:1016:1016)) + (PORT datac (613:613:613) (627:627:627)) + (PORT datad (836:836:836) (845:845:845)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1742:1742:1742) (1825:1825:1825)) + (PORT datab (1546:1546:1546) (1654:1654:1654)) + (PORT datac (351:351:351) (378:378:378)) + (PORT datad (2479:2479:2479) (2584:2584:2584)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (931:931:931) (960:960:960)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (229:229:229) (270:270:270)) + (PORT datac (802:802:802) (798:798:798)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (892:892:892)) + (PORT datab (873:873:873) (943:943:943)) + (PORT datac (2267:2267:2267) (2412:2412:2412)) + (PORT datad (1757:1757:1757) (1887:1887:1887)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1001:1001:1001)) + (PORT datab (917:917:917) (961:961:961)) + (PORT datac (2331:2331:2331) (2438:2438:2438)) + (PORT datad (1442:1442:1442) (1517:1517:1517)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1704:1704:1704) (1753:1753:1753)) + (PORT datab (947:947:947) (1020:1020:1020)) + (PORT datac (945:945:945) (1014:1014:1014)) + (PORT datad (1635:1635:1635) (1701:1701:1701)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (884:884:884) (907:907:907)) + (PORT datac (315:315:315) (342:342:342)) + (PORT datad (214:214:214) (249:249:249)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1339:1339:1339)) + (PORT datab (427:427:427) (483:483:483)) + (PORT datac (349:349:349) (378:378:378)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1177:1177:1177)) + (PORT datab (800:800:800) (828:828:828)) + (PORT datac (610:610:610) (675:675:675)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1165:1165:1165) (1217:1217:1217)) + (PORT datad (518:518:518) (525:525:525)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (815:815:815) (826:826:826)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (884:884:884)) + (PORT datab (609:609:609) (648:648:648)) + (PORT datac (1307:1307:1307) (1381:1381:1381)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1755:1755:1755) (1815:1815:1815)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (561:561:561) (578:578:578)) + (PORT datad (611:611:611) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (858:858:858) (943:943:943)) + (PORT datac (1717:1717:1717) (1775:1775:1775)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1750:1750:1750) (1808:1808:1808)) + (PORT datab (1443:1443:1443) (1484:1484:1484)) + (PORT datac (608:608:608) (634:634:634)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (268:268:268)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (814:814:814) (866:866:866)) + (PORT datad (222:222:222) (251:251:251)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1002:1002:1002) (1030:1030:1030)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1413:1413:1413) (1476:1476:1476)) + (PORT datab (1716:1716:1716) (1764:1764:1764)) + (PORT datac (359:359:359) (385:385:385)) + (PORT datad (1180:1180:1180) (1205:1205:1205)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (657:657:657) (711:711:711)) + (PORT datac (1392:1392:1392) (1457:1457:1457)) + (PORT datad (1097:1097:1097) (1132:1132:1132)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (612:612:612)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (1195:1195:1195) (1213:1213:1213)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (626:626:626) (693:693:693)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (997:997:997)) + (PORT datab (1414:1414:1414) (1480:1480:1480)) + (PORT datac (362:362:362) (386:386:386)) + (PORT datad (1182:1182:1182) (1203:1203:1203)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datab (1242:1242:1242) (1340:1340:1340)) + (PORT datac (896:896:896) (957:957:957)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (308:308:308)) + (PORT datab (939:939:939) (996:996:996)) + (PORT datac (525:525:525) (543:543:543)) + (PORT datad (923:923:923) (981:981:981)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (265:265:265)) + (PORT datab (1156:1156:1156) (1191:1191:1191)) + (PORT datac (837:837:837) (880:880:880)) + (PORT datad (658:658:658) (709:709:709)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (934:934:934)) + (PORT datab (882:882:882) (910:910:910)) + (PORT datac (411:411:411) (449:449:449)) + (PORT datad (1010:1010:1010) (1065:1065:1065)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (407:407:407)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (221:221:221) (249:249:249)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (698:698:698)) + (PORT datab (684:684:684) (738:738:738)) + (PORT datac (963:963:963) (1025:1025:1025)) + (PORT datad (1419:1419:1419) (1496:1496:1496)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (2135:2135:2135) (2284:2284:2284)) + (PORT datab (1448:1448:1448) (1506:1506:1506)) + (PORT datac (981:981:981) (1074:1074:1074)) + (PORT datad (1424:1424:1424) (1498:1498:1498)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (412:412:412)) + (PORT datab (400:400:400) (427:427:427)) + (PORT datac (1192:1192:1192) (1207:1207:1207)) + (PORT datad (339:339:339) (359:359:359)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1356:1356:1356)) + (PORT datab (1098:1098:1098) (1140:1140:1140)) + (PORT datac (333:333:333) (361:361:361)) + (PORT datad (1161:1161:1161) (1189:1189:1189)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1356:1356:1356)) + (PORT datab (1577:1577:1577) (1688:1688:1688)) + (PORT datac (1501:1501:1501) (1638:1638:1638)) + (PORT datad (1157:1157:1157) (1187:1187:1187)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (958:958:958)) + (PORT datab (1318:1318:1318) (1360:1360:1360)) + (PORT datac (337:337:337) (364:364:364)) + (PORT datad (1216:1216:1216) (1284:1284:1284)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1252:1252:1252) (1322:1322:1322)) + (PORT datac (615:615:615) (683:683:683)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1319:1319:1319)) + (PORT datab (904:904:904) (946:946:946)) + (PORT datac (1503:1503:1503) (1640:1640:1640)) + (PORT datad (1230:1230:1230) (1314:1314:1314)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (202:202:202) (247:247:247)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (765:765:765)) + (PORT datab (1594:1594:1594) (1708:1708:1708)) + (PORT datac (1547:1547:1547) (1688:1688:1688)) + (PORT datad (1542:1542:1542) (1718:1718:1718)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1103:1103:1103) (1170:1170:1170)) + (PORT datac (818:818:818) (866:866:866)) + (PORT datad (1175:1175:1175) (1203:1203:1203)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (853:853:853)) + (PORT datab (1190:1190:1190) (1211:1211:1211)) + (PORT datac (532:532:532) (545:545:545)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (893:893:893)) + (PORT datab (859:859:859) (901:901:901)) + (PORT datad (1510:1510:1510) (1557:1557:1557)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (373:373:373)) + (PORT datab (1215:1215:1215) (1271:1271:1271)) + (PORT datac (1945:1945:1945) (2016:2016:2016)) + (PORT datad (928:928:928) (969:969:969)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (470:470:470)) + (PORT datab (636:636:636) (673:673:673)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (339:339:339) (360:360:360)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (769:769:769) (826:826:826)) + (PORT datac (365:365:365) (399:399:399)) + (PORT datad (790:790:790) (788:788:788)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT datab (658:658:658) (693:693:693)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (869:869:869)) + (PORT datac (595:595:595) (635:635:635)) + (PORT datad (908:908:908) (970:970:970)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (674:674:674)) + (PORT datab (830:830:830) (872:872:872)) + (PORT datac (1421:1421:1421) (1450:1450:1450)) + (PORT datad (1110:1110:1110) (1142:1142:1142)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (951:951:951) (1010:1010:1010)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (769:769:769)) + (PORT datab (1236:1236:1236) (1290:1290:1290)) + (PORT datac (1164:1164:1164) (1215:1215:1215)) + (PORT datad (1047:1047:1047) (1125:1125:1125)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (855:855:855) (880:880:880)) + (PORT datac (1140:1140:1140) (1172:1172:1172)) + (PORT datad (874:874:874) (902:902:902)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (865:865:865)) + (PORT datac (398:398:398) (460:460:460)) + (PORT datad (368:368:368) (427:427:427)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (732:732:732) (788:788:788)) + (PORT datac (676:676:676) (729:729:729)) + (PORT datad (1051:1051:1051) (1126:1126:1126)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1120:1120:1120)) + (PORT datab (235:235:235) (277:277:277)) + (PORT datac (795:795:795) (801:801:801)) + (PORT datad (826:826:826) (840:840:840)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (419:419:419)) + (PORT datab (576:576:576) (598:598:598)) + (PORT datac (1361:1361:1361) (1381:1381:1381)) + (PORT datad (1131:1131:1131) (1200:1200:1200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (265:265:265)) + (PORT datab (876:876:876) (905:905:905)) + (PORT datac (1765:1765:1765) (1884:1884:1884)) + (PORT datad (1357:1357:1357) (1370:1370:1370)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2267:2267:2267) (2306:2306:2306)) + (PORT datab (2862:2862:2862) (2989:2989:2989)) + (PORT datac (972:972:972) (1039:1039:1039)) + (PORT datad (1353:1353:1353) (1367:1367:1367)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (934:934:934)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1325:1325:1325)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (814:814:814) (885:885:885)) + (PORT datad (605:605:605) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1065:1065:1065)) + (PORT datab (260:260:260) (341:341:341)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (915:915:915)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (880:880:880) (897:897:897)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (896:896:896)) + (PORT datac (850:850:850) (889:889:889)) + (PORT datad (863:863:863) (925:925:925)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (943:943:943)) + (PORT datac (616:616:616) (628:628:628)) + (PORT datad (362:362:362) (389:389:389)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (915:915:915)) + (PORT datab (1202:1202:1202) (1257:1257:1257)) + (PORT datac (1151:1151:1151) (1179:1179:1179)) + (PORT datad (822:822:822) (839:839:839)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (1143:1143:1143) (1176:1176:1176)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (719:719:719)) + (PORT datab (703:703:703) (760:760:760)) + (PORT datac (575:575:575) (604:604:604)) + (PORT datad (1035:1035:1035) (1052:1052:1052)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (264:264:264)) + (PORT datac (603:603:603) (612:612:612)) + (PORT datad (362:362:362) (386:386:386)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (262:262:262)) + (PORT datab (748:748:748) (806:806:806)) + (PORT datac (1048:1048:1048) (1127:1127:1127)) + (PORT datad (697:697:697) (755:755:755)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (910:910:910)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (339:339:339) (359:359:359)) + (PORT datad (190:190:190) (226:226:226)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (807:807:807)) + (PORT datab (1353:1353:1353) (1372:1372:1372)) + (PORT datac (1225:1225:1225) (1346:1346:1346)) + (PORT datad (667:667:667) (718:718:718)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (354:354:354)) + (PORT datab (287:287:287) (349:349:349)) + (PORT datad (246:246:246) (289:289:289)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (442:442:442)) + (PORT datab (392:392:392) (422:422:422)) + (PORT datac (1398:1398:1398) (1449:1449:1449)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1459:1459:1459)) + (PORT datac (1119:1119:1119) (1171:1171:1171)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (890:890:890) (903:903:903)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1827:1827:1827) (1910:1910:1910)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1827:1827:1827) (1909:1909:1909)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (905:905:905)) + (PORT datab (416:416:416) (502:502:502)) + (PORT datad (838:838:838) (853:853:853)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (2043:2043:2043) (2144:2144:2144)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (817:817:817) (874:874:874)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (748:748:748)) + (PORT datab (672:672:672) (717:717:717)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1660:1660:1660) (1702:1702:1702)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1199:1199:1199)) + (PORT datab (1237:1237:1237) (1263:1263:1263)) + (PORT datad (861:861:861) (878:878:878)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2046:2046:2046) (2144:2144:2144)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1727:1727:1727) (1806:1806:1806)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (704:704:704)) + (PORT datab (457:457:457) (504:504:504)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1444:1444:1444) (1514:1514:1514)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1444:1444:1444) (1514:1514:1514)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (978:978:978)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datad (864:864:864) (894:894:894)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (864:864:864)) + (PORT datab (557:557:557) (592:592:592)) + (PORT datac (987:987:987) (1031:1031:1031)) + (PORT datad (355:355:355) (385:385:385)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1187:1187:1187) (1228:1228:1228)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1446:1446:1446)) + (PORT datab (1368:1368:1368) (1449:1449:1449)) + (PORT datad (870:870:870) (894:894:894)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1829:1829:1829) (1915:1915:1915)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1183:1183:1183) (1224:1224:1224)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (972:972:972)) + (PORT datab (652:652:652) (743:743:743)) + (PORT datad (991:991:991) (1047:1047:1047)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (416:416:416)) + (PORT datab (794:794:794) (835:835:835)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (602:602:602)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (638:638:638) (673:673:673)) + (PORT datad (816:816:816) (866:866:866)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1239:1239:1239)) + (PORT datab (1314:1314:1314) (1418:1418:1418)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (359:359:359)) + (PORT datac (1100:1100:1100) (1117:1117:1117)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (746:746:746)) + (PORT datab (711:711:711) (789:789:789)) + (PORT datac (815:815:815) (841:841:841)) + (PORT datad (600:600:600) (645:645:645)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1194:1194:1194) (1236:1236:1236)) + (PORT datac (663:663:663) (703:703:703)) + (PORT datad (370:370:370) (397:397:397)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datac (1191:1191:1191) (1217:1217:1217)) + (PORT datad (603:603:603) (619:619:619)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1664:1664:1664) (1739:1739:1739)) + (PORT datab (655:655:655) (701:701:701)) + (PORT datac (1073:1073:1073) (1116:1116:1116)) + (PORT datad (642:642:642) (700:700:700)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (711:711:711)) + (PORT datad (329:329:329) (352:352:352)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1152:1152:1152)) + (PORT datab (651:651:651) (697:697:697)) + (PORT datac (866:866:866) (925:925:925)) + (PORT datad (1624:1624:1624) (1694:1694:1694)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (691:691:691)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (918:918:918) (968:968:968)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (703:703:703) (732:732:732)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1246:1246:1246)) + (PORT datab (1309:1309:1309) (1415:1415:1415)) + (PORT datad (1072:1072:1072) (1106:1106:1106)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (394:394:394)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (1105:1105:1105) (1124:1124:1124)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (686:686:686)) + (PORT datab (1193:1193:1193) (1230:1230:1230)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (375:375:375) (400:400:400)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (939:939:939) (974:974:974)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (939:939:939) (973:973:973)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (328:328:328)) + (PORT datab (244:244:244) (290:290:290)) + (PORT datad (555:555:555) (562:562:562)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1476:1476:1476) (1502:1502:1502)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1476:1476:1476) (1503:1503:1503)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (977:977:977)) + (PORT datab (896:896:896) (932:932:932)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (903:903:903) (914:914:914)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (458:458:458) (497:497:497)) + (PORT datad (1153:1153:1153) (1204:1204:1204)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (951:951:951) (994:994:994)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (951:951:951) (992:992:992)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (754:754:754)) + (PORT datab (669:669:669) (714:714:714)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (967:967:967) (1020:1020:1020)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (924:924:924)) + (PORT datab (1235:1235:1235) (1261:1261:1261)) + (PORT datad (862:862:862) (875:875:875)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (637:637:637)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (541:541:541) (569:569:569)) + (PORT datad (577:577:577) (615:615:615)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (972:972:972) (1023:1023:1023)) + (PORT ena (1471:1471:1471) (1443:1443:1443)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (857:857:857)) + (PORT datab (1177:1177:1177) (1217:1217:1217)) + (PORT datad (1321:1321:1321) (1366:1366:1366)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1368:1368:1368) (1440:1440:1440)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1366:1366:1366) (1439:1439:1439)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (905:905:905)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (840:840:840) (849:849:849)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1121:1121:1121)) + (PORT datab (637:637:637) (685:685:685)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (577:577:577) (594:594:594)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (750:750:750)) + (PORT datab (666:666:666) (687:687:687)) + (PORT datac (619:619:619) (669:669:669)) + (PORT datad (629:629:629) (668:668:668)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (750:750:750)) + (PORT datab (798:798:798) (816:816:816)) + (PORT datac (920:920:920) (972:972:972)) + (PORT datad (1484:1484:1484) (1552:1552:1552)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (981:981:981)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (367:367:367) (406:406:406)) + (PORT datad (321:321:321) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (377:377:377)) + (PORT datab (371:371:371) (416:416:416)) + (PORT datac (1351:1351:1351) (1382:1382:1382)) + (PORT datad (1525:1525:1525) (1547:1547:1547)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (655:655:655)) + (PORT datab (1372:1372:1372) (1425:1425:1425)) + (PORT datac (571:571:571) (593:593:593)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (677:677:677)) + (PORT datab (1176:1176:1176) (1233:1233:1233)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (327:327:327) (353:353:353)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT datab (829:829:829) (864:864:864)) + (PORT datac (632:632:632) (658:658:658)) + (PORT datad (913:913:913) (970:970:970)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (1076:1076:1076) (1163:1163:1163)) + (PORT datac (868:868:868) (938:938:938)) + (PORT datad (1124:1124:1124) (1196:1196:1196)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (939:939:939)) + (PORT datab (226:226:226) (267:267:267)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (926:926:926)) + (PORT datab (897:897:897) (965:965:965)) + (PORT datac (828:828:828) (860:860:860)) + (PORT datad (871:871:871) (877:877:877)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (881:881:881)) + (PORT datab (394:394:394) (422:422:422)) + (PORT datac (598:598:598) (612:612:612)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (925:925:925)) + (PORT datab (395:395:395) (422:422:422)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1677:1677:1677) (1734:1734:1734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1283:1283:1283)) + (PORT datab (1204:1204:1204) (1256:1256:1256)) + (PORT datac (673:673:673) (737:737:737)) + (PORT datad (1047:1047:1047) (1127:1127:1127)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (916:916:916)) + (PORT datab (855:855:855) (878:878:878)) + (PORT datac (1138:1138:1138) (1173:1173:1173)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1487:1487:1487)) + (PORT datab (1717:1717:1717) (1746:1746:1746)) + (PORT datac (869:869:869) (939:939:939)) + (PORT datad (380:380:380) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (280:280:280) (340:340:340)) + (PORT datad (244:244:244) (286:286:286)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (341:341:341)) + (PORT datab (570:570:570) (585:585:585)) + (PORT datac (1251:1251:1251) (1294:1294:1294)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (965:965:965)) + (PORT datac (380:380:380) (437:437:437)) + (PORT datad (785:785:785) (837:837:837)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1268:1268:1268)) + (PORT datab (899:899:899) (907:907:907)) + (PORT datac (816:816:816) (833:833:833)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (701:701:701) (728:728:728)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1540:1540:1540) (1612:1612:1612)) + (PORT datab (1314:1314:1314) (1418:1418:1418)) + (PORT datad (1164:1164:1164) (1193:1193:1193)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1211:1211:1211)) + (PORT datab (600:600:600) (671:671:671)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (890:890:890) (913:913:913)) + (PORT datad (543:543:543) (557:557:557)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1535:1535:1535)) + (PORT ena (1964:1964:1964) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (689:689:689)) + (PORT datab (927:927:927) (981:981:981)) + (PORT datac (612:612:612) (646:646:646)) + (PORT datad (1031:1031:1031) (1050:1050:1050)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (912:912:912)) + (PORT datab (1057:1057:1057) (1087:1087:1087)) + (PORT datac (241:241:241) (328:328:328)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (371:371:371)) + (PORT datab (397:397:397) (437:437:437)) + (PORT datac (1155:1155:1155) (1195:1195:1195)) + (PORT datad (569:569:569) (590:590:590)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1705:1705:1705) (1755:1755:1755)) + (PORT ena (1493:1493:1493) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1451:1451:1451)) + (PORT datab (1365:1365:1365) (1446:1446:1446)) + (PORT datad (870:870:870) (899:899:899)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1207:1207:1207) (1259:1259:1259)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1210:1210:1210) (1263:1263:1263)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (910:910:910)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (841:841:841) (856:856:856)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (928:928:928) (941:941:941)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1706:1706:1706) (1752:1752:1752)) + (PORT ena (1531:1531:1531) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (968:968:968)) + (PORT datab (652:652:652) (743:743:743)) + (PORT datad (993:993:993) (1050:1050:1050)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1843:1843:1843) (1900:1900:1900)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1842:1842:1842) (1899:1899:1899)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (978:978:978)) + (PORT datab (898:898:898) (931:931:931)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (915:915:915) (929:929:929)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (458:458:458) (504:504:504)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (910:910:910) (941:941:941)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1455:1455:1455) (1536:1536:1536)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (753:753:753)) + (PORT datab (672:672:672) (718:718:718)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1467:1467:1467) (1513:1513:1513)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (908:908:908)) + (PORT datab (1241:1241:1241) (1274:1274:1274)) + (PORT datad (892:892:892) (907:907:907)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (824:824:824)) + (PORT datab (639:639:639) (681:681:681)) + (PORT datac (779:779:779) (834:834:834)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (369:369:369) (407:407:407)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (695:695:695)) + (PORT datab (645:645:645) (697:697:697)) + (PORT datac (689:689:689) (718:718:718)) + (PORT datad (592:592:592) (625:625:625)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (757:757:757)) + (PORT datab (908:908:908) (979:979:979)) + (PORT datac (911:911:911) (962:962:962)) + (PORT datad (597:597:597) (623:623:623)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (269:269:269) (325:325:325)) + (PORT datac (1134:1134:1134) (1152:1152:1152)) + (PORT datad (901:901:901) (943:943:943)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1701:1701:1701) (1725:1725:1725)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (893:893:893) (910:910:910)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (616:616:616)) + (PORT datab (675:675:675) (705:705:705)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (832:832:832) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1481:1481:1481)) + (PORT datab (620:620:620) (660:660:660)) + (PORT datac (803:803:803) (837:837:837)) + (PORT datad (838:838:838) (866:866:866)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (943:943:943) (1004:1004:1004)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (262:262:262) (343:343:343)) + (PORT datac (236:236:236) (311:311:311)) + (PORT datad (236:236:236) (304:304:304)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (497:497:497)) + (PORT datab (262:262:262) (344:344:344)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (623:623:623)) + (PORT datab (714:714:714) (802:802:802)) + (PORT datac (1145:1145:1145) (1194:1194:1194)) + (PORT datad (546:546:546) (563:563:563)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (839:839:839)) + (PORT datab (851:851:851) (859:859:859)) + (PORT datac (637:637:637) (660:660:660)) + (PORT datad (775:775:775) (832:832:832)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (280:280:280)) + (PORT datab (244:244:244) (326:326:326)) + (PORT datac (682:682:682) (738:738:738)) + (PORT datad (1165:1165:1165) (1175:1175:1175)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (953:953:953)) + (PORT datab (893:893:893) (914:914:914)) + (PORT datac (1084:1084:1084) (1122:1122:1122)) + (PORT datad (1137:1137:1137) (1155:1155:1155)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (600:600:600)) + (PORT datab (1111:1111:1111) (1166:1166:1166)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (575:575:575) (569:569:569)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (399:399:399)) + (PORT datab (242:242:242) (287:287:287)) + (PORT datac (674:674:674) (702:702:702)) + (PORT datad (565:565:565) (579:579:579)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1703:1703:1703)) + (PORT datab (427:427:427) (459:459:459)) + (PORT datad (771:771:771) (795:795:795)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1161:1161:1161) (1182:1182:1182)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (937:937:937) (960:960:960)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (700:700:700) (715:715:715)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (214:214:214) (240:240:240)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1423:1423:1423) (1404:1404:1404)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (459:459:459)) + (PORT datab (836:836:836) (851:851:851)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (626:626:626) (660:660:660)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1545:1545:1545) (1565:1565:1565)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (731:731:731)) + (PORT datab (387:387:387) (460:460:460)) + (PORT datad (687:687:687) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (365:365:365)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (563:563:563) (582:582:582)) + (PORT datad (789:789:789) (793:793:793)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1295:1295:1295) (1325:1325:1325)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1297:1297:1297) (1327:1327:1327)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (999:999:999)) + (PORT datab (963:963:963) (1015:1015:1015)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (394:394:394)) + (PORT datab (665:665:665) (698:698:698)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (929:929:929)) + (PORT datab (951:951:951) (986:986:986)) + (PORT datac (831:831:831) (844:844:844)) + (PORT datad (586:586:586) (603:603:603)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (671:671:671) (691:691:691)) + (PORT ena (1222:1222:1222) (1210:1210:1210)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1299:1299:1299)) + (PORT datab (973:973:973) (979:979:979)) + (PORT datad (649:649:649) (674:674:674)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (244:244:244) (326:326:326)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (663:663:663) (680:680:680)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (720:720:720)) + (PORT datab (634:634:634) (649:649:649)) + (PORT datac (227:227:227) (272:272:272)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datac (1195:1195:1195) (1224:1224:1224)) + (PORT datad (529:529:529) (540:540:540)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (267:267:267) (363:363:363)) + (PORT datab (859:859:859) (884:884:884)) + (PORT datac (1099:1099:1099) (1165:1165:1165)) + (PORT datad (1364:1364:1364) (1395:1395:1395)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1254:1254:1254) (1282:1282:1282)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1255:1255:1255) (1284:1284:1284)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1045:1045:1045)) + (PORT datab (740:740:740) (781:781:781)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (801:801:801) (810:810:810)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1415:1415:1415) (1428:1428:1428)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (462:462:462)) + (PORT datab (423:423:423) (459:459:459)) + (PORT datad (387:387:387) (414:414:414)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1520:1520:1520) (1543:1543:1543)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (993:993:993) (1036:1036:1036)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (962:962:962)) + (PORT datab (680:680:680) (731:731:731)) + (PORT datad (600:600:600) (652:652:652)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (968:968:968) (973:973:973)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1705:1705:1705)) + (PORT datab (630:630:630) (658:658:658)) + (PORT datac (882:882:882) (926:926:926)) + (PORT datad (1068:1068:1068) (1072:1072:1072)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1203:1203:1203) (1240:1240:1240)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (450:450:450)) + (PORT datab (711:711:711) (763:763:763)) + (PORT datad (636:636:636) (686:686:686)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (695:695:695)) + (PORT datab (598:598:598) (612:612:612)) + (PORT datac (571:571:571) (595:595:595)) + (PORT datad (606:606:606) (617:617:617)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1256:1256:1256) (1274:1274:1274)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1257:1257:1257) (1276:1276:1276)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1000:1000:1000)) + (PORT datab (966:966:966) (1018:1018:1018)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (991:991:991) (1033:1033:1033)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1517:1517:1517) (1540:1540:1540)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (735:735:735)) + (PORT datab (421:421:421) (485:485:485)) + (PORT datad (688:688:688) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (368:368:368)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (925:925:925)) + (PORT datab (920:920:920) (943:943:943)) + (PORT datac (918:918:918) (946:946:946)) + (PORT datad (887:887:887) (901:901:901)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (536:536:536) (567:567:567)) + (PORT ena (1190:1190:1190) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1268:1268:1268)) + (PORT datab (940:940:940) (988:988:988)) + (PORT datad (582:582:582) (598:598:598)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1199:1199:1199) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (668:668:668)) + (PORT datac (316:316:316) (336:336:336)) + (PORT datad (355:355:355) (415:415:415)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1441:1441:1441)) + (PORT datab (632:632:632) (702:702:702)) + (PORT datac (1097:1097:1097) (1164:1164:1164)) + (PORT datad (833:833:833) (846:846:846)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (480:480:480)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (633:633:633) (655:655:655)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (657:657:657) (693:693:693)) + (PORT datad (608:608:608) (631:631:631)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (1222:1222:1222) (1253:1253:1253)) + (PORT datad (639:639:639) (661:661:661)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (1723:1723:1723) (1718:1718:1718)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1291:1291:1291)) + (PORT datab (1213:1213:1213) (1307:1307:1307)) + (PORT datac (591:591:591) (647:647:647)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (695:695:695)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (645:645:645) (708:708:708)) + (PORT datad (540:540:540) (553:553:553)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1199:1199:1199) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1223:1223:1223) (1253:1253:1253)) + (PORT ena (1521:1521:1521) (1517:1517:1517)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1221:1221:1221) (1252:1252:1252)) + (PORT ena (1494:1494:1494) (1487:1487:1487)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1046:1046:1046)) + (PORT datab (741:741:741) (777:777:777)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1236:1236:1236) (1259:1259:1259)) + (PORT ena (1509:1509:1509) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1236:1236:1236) (1262:1262:1262)) + (PORT ena (1472:1472:1472) (1462:1462:1462)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1000:1000:1000)) + (PORT datab (967:967:967) (1018:1018:1018)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1223:1223:1223) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1401:1401:1401)) + (PORT datab (646:646:646) (665:665:665)) + (PORT datac (214:214:214) (289:289:289)) + (PORT datad (771:771:771) (793:793:793)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1239:1239:1239) (1275:1275:1275)) + (PORT ena (1257:1257:1257) (1253:1253:1253)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1202:1202:1202) (1229:1229:1229)) + (PORT ena (1521:1521:1521) (1526:1526:1526)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (957:957:957)) + (PORT datab (680:680:680) (727:727:727)) + (PORT datad (380:380:380) (443:443:443)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1160:1160:1160) (1165:1165:1165)) + (PORT ena (1174:1174:1174) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1386:1386:1386) (1381:1381:1381)) + (PORT ena (1504:1504:1504) (1480:1480:1480)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (477:477:477)) + (PORT datab (425:425:425) (463:463:463)) + (PORT datad (386:386:386) (416:416:416)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1388:1388:1388) (1381:1381:1381)) + (PORT ena (1534:1534:1534) (1522:1522:1522)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datad (932:932:932) (957:957:957)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1203:1203:1203) (1232:1232:1232)) + (PORT ena (1235:1235:1235) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1527:1527:1527)) + (PORT asdata (1240:1240:1240) (1275:1275:1275)) + (PORT ena (1197:1197:1197) (1187:1187:1187)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (732:732:732)) + (PORT datab (390:390:390) (467:467:467)) + (PORT datad (687:687:687) (727:727:727)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (899:899:899) (924:924:924)) + (PORT datac (597:597:597) (617:617:617)) + (PORT datad (861:861:861) (881:881:881)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (601:601:601) (618:618:618)) + (PORT datac (599:599:599) (618:618:618)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (609:609:609)) + (PORT datab (842:842:842) (863:863:863)) + (PORT datac (1082:1082:1082) (1103:1103:1103)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (870:870:870) (888:888:888)) + (PORT ena (1190:1190:1190) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1262:1262:1262)) + (PORT datab (923:923:923) (982:982:982)) + (PORT datad (585:585:585) (603:603:603)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (333:333:333)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (601:601:601) (626:626:626)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (1069:1069:1069) (1087:1087:1087)) + (PORT datac (657:657:657) (692:692:692)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT datac (1351:1351:1351) (1346:1346:1346)) + (PORT datad (1841:1841:1841) (1843:1843:1843)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (716:716:716) (738:738:738)) + (PORT clrn (1556:1556:1556) (1538:1538:1538)) + (PORT ena (1699:1699:1699) (1696:1696:1696)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (689:689:689)) + (PORT datab (928:928:928) (981:981:981)) + (PORT datac (613:613:613) (646:646:646)) + (PORT datad (1031:1031:1031) (1050:1050:1050)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1188:1188:1188) (1235:1235:1235)) + (PORT datac (362:362:362) (388:388:388)) + (PORT datad (369:369:369) (398:398:398)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1214:1214:1214) (1231:1231:1231)) + (PORT ena (1471:1471:1471) (1443:1443:1443)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1213:1213:1213) (1240:1240:1240)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1213:1213:1213) (1239:1239:1239)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (907:907:907)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (837:837:837) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1193:1193:1193) (1217:1217:1217)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (1194:1194:1194) (1217:1217:1217)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1231:1231:1231)) + (PORT datab (581:581:581) (610:610:610)) + (PORT datad (1141:1141:1141) (1207:1207:1207)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (839:839:839)) + (PORT datab (245:245:245) (290:290:290)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (979:979:979) (990:990:990)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (981:981:981) (992:992:992)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (463:463:463) (500:500:500)) + (PORT datad (1156:1156:1156) (1206:1206:1206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (992:992:992) (1025:1025:1025)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (989:989:989) (1023:1023:1023)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (975:975:975)) + (PORT datab (897:897:897) (928:928:928)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1702:1702:1702) (1716:1716:1716)) + (PORT ena (1252:1252:1252) (1257:1257:1257)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1175:1175:1175) (1207:1207:1207)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1206:1206:1206) (1172:1172:1172)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (755:755:755)) + (PORT datab (668:668:668) (708:708:708)) + (PORT datad (399:399:399) (467:467:467)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (1216:1216:1216) (1232:1232:1232)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (923:923:923)) + (PORT datab (1238:1238:1238) (1265:1265:1265)) + (PORT datad (865:865:865) (879:879:879)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (412:412:412)) + (PORT datab (637:637:637) (665:665:665)) + (PORT datac (341:341:341) (372:372:372)) + (PORT datad (604:604:604) (642:642:642)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (660:660:660) (751:751:751)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (711:711:711)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datac (373:373:373) (404:404:404)) + (PORT datad (625:625:625) (637:637:637)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (936:936:936)) + (PORT datab (615:615:615) (652:652:652)) + (PORT datac (215:215:215) (248:248:248)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1245:1245:1245)) + (PORT datab (268:268:268) (324:324:324)) + (PORT datac (567:567:567) (591:591:591)) + (PORT datad (899:899:899) (939:939:939)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (389:389:389) (417:417:417)) + (PORT datac (1401:1401:1401) (1448:1448:1448)) + (PORT datad (593:593:593) (612:612:612)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1377:1377:1377) (1414:1414:1414)) + (PORT datac (363:363:363) (396:396:396)) + (PORT datad (1524:1524:1524) (1552:1552:1552)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (639:639:639)) + (PORT datac (650:650:650) (679:679:679)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (983:983:983)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (674:674:674) (690:690:690)) + (PORT datad (242:242:242) (281:281:281)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (738:738:738)) + (PORT datab (1197:1197:1197) (1242:1242:1242)) + (PORT datac (2792:2792:2792) (2903:2903:2903)) + (PORT datad (814:814:814) (834:834:834)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1538:1538:1538) (1609:1609:1609)) + (PORT datab (963:963:963) (1037:1037:1037)) + (PORT datac (2790:2790:2790) (2900:2900:2900)) + (PORT datad (1212:1212:1212) (1250:1250:1250)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~3) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1496:1496:1496) (1568:1568:1568)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (424:424:424)) + (PORT datac (1399:1399:1399) (1448:1448:1448)) + (PORT datad (750:750:750) (753:753:753)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (388:388:388) (421:421:421)) + (PORT datac (1350:1350:1350) (1379:1379:1379)) + (PORT datad (1525:1525:1525) (1551:1551:1551)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (865:865:865)) + (PORT datab (906:906:906) (931:931:931)) + (PORT datac (399:399:399) (460:460:460)) + (PORT datad (368:368:368) (426:426:426)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (907:907:907)) + (PORT datac (612:612:612) (623:623:623)) + (PORT datad (358:358:358) (384:384:384)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (913:913:913)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (582:582:582) (596:596:596)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (950:950:950) (958:958:958)) + (PORT ena (1677:1677:1677) (1734:1734:1734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (347:347:347)) + (PORT datab (279:279:279) (339:339:339)) + (PORT datac (1254:1254:1254) (1299:1299:1299)) + (PORT datad (243:243:243) (284:284:284)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (987:987:987)) + (PORT datab (1720:1720:1720) (1750:1750:1750)) + (PORT datac (1344:1344:1344) (1447:1447:1447)) + (PORT datad (371:371:371) (430:430:430)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (969:969:969)) + (PORT datab (614:614:614) (669:669:669)) + (PORT datac (797:797:797) (851:851:851)) + (PORT datad (806:806:806) (809:809:809)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (637:637:637) (653:653:653)) + (PORT datac (646:646:646) (672:672:672)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1104:1104:1104)) + (PORT datab (900:900:900) (936:936:936)) + (PORT datac (1171:1171:1171) (1223:1223:1223)) + (PORT datad (816:816:816) (830:830:830)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datac (1142:1142:1142) (1176:1176:1176)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (502:502:502)) + (PORT datab (1711:1711:1711) (1740:1740:1740)) + (PORT datac (676:676:676) (729:729:729)) + (PORT datad (1522:1522:1522) (1638:1638:1638)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (410:410:410)) + (PORT datac (1398:1398:1398) (1447:1447:1447)) + (PORT datad (320:320:320) (343:343:343)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1254:1254:1254)) + (PORT datab (1138:1138:1138) (1168:1168:1168)) + (PORT datac (341:341:341) (363:363:363)) + (PORT datad (600:600:600) (619:619:619)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (354:354:354)) + (PORT datab (286:286:286) (348:348:348)) + (PORT datad (245:245:245) (288:288:288)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (635:635:635)) + (PORT datab (338:338:338) (371:371:371)) + (PORT datac (1293:1293:1293) (1359:1359:1359)) + (PORT datad (816:816:816) (831:831:831)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (686:686:686)) + (PORT datab (928:928:928) (993:993:993)) + (PORT datac (605:605:605) (616:616:616)) + (PORT datad (628:628:628) (649:649:649)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (457:457:457)) + (PORT datab (882:882:882) (980:980:980)) + (PORT datac (915:915:915) (966:966:966)) + (PORT datad (660:660:660) (702:702:702)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (992:992:992)) + (PORT datab (267:267:267) (322:322:322)) + (PORT datac (813:813:813) (821:821:821)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1201:1201:1201)) + (PORT datac (1154:1154:1154) (1229:1229:1229)) + (PORT datad (892:892:892) (907:907:907)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (906:906:906)) + (PORT datab (900:900:900) (907:907:907)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1674:1674:1674) (1683:1683:1683)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (680:680:680) (713:713:713)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (828:828:828) (872:872:872)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (927:927:927)) + (PORT datab (642:642:642) (678:678:678)) + (PORT datac (1167:1167:1167) (1221:1221:1221)) + (PORT datad (826:826:826) (836:836:836)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1142:1142:1142) (1169:1169:1169)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (860:860:860)) + (PORT datab (417:417:417) (480:480:480)) + (PORT datac (360:360:360) (426:426:426)) + (PORT datad (877:877:877) (892:892:892)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1416:1416:1416)) + (PORT datab (717:717:717) (780:780:780)) + (PORT datac (638:638:638) (703:703:703)) + (PORT datad (861:861:861) (865:865:865)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datab (668:668:668) (689:689:689)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1143:1143:1143)) + (PORT datab (714:714:714) (776:776:776)) + (PORT datac (641:641:641) (706:706:706)) + (PORT datad (633:633:633) (650:650:650)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (831:831:831) (861:861:861)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT datac (591:591:591) (611:611:611)) + (PORT datad (401:401:401) (444:444:444)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (374:374:374)) + (PORT datab (987:987:987) (1028:1028:1028)) + (PORT datad (640:640:640) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (987:987:987)) + (PORT datab (610:610:610) (615:615:615)) + (PORT datac (1075:1075:1075) (1085:1085:1085)) + (PORT datad (546:546:546) (561:561:561)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (680:680:680) (739:739:739)) + (PORT datad (1095:1095:1095) (1166:1166:1166)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1178:1178:1178)) + (PORT datab (897:897:897) (910:910:910)) + (PORT datac (870:870:870) (906:906:906)) + (PORT datad (1139:1139:1139) (1149:1149:1149)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (394:394:394)) + (PORT datab (709:709:709) (735:735:735)) + (PORT datac (623:623:623) (640:640:640)) + (PORT datad (343:343:343) (364:364:364)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (654:654:654)) + (PORT datab (378:378:378) (411:411:411)) + (PORT datac (538:538:538) (542:542:542)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1091:1091:1091)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (1234:1234:1234) (1281:1281:1281)) + (PORT datad (583:583:583) (605:605:605)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (761:761:761)) + (PORT datab (622:622:622) (652:652:652)) + (PORT datac (2210:2210:2210) (2286:2286:2286)) + (PORT datad (624:624:624) (653:653:653)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1579:1579:1579)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (850:850:850) (861:861:861)) + (PORT datad (1053:1053:1053) (1062:1062:1062)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (907:907:907)) + (PORT datab (1138:1138:1138) (1155:1155:1155)) + (PORT datac (2210:2210:2210) (2291:2291:2291)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (759:759:759)) + (PORT datab (662:662:662) (693:693:693)) + (PORT datac (593:593:593) (619:619:619)) + (PORT datad (1543:1543:1543) (1532:1532:1532)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1958:1958:1958)) + (PORT datab (1908:1908:1908) (2021:2021:2021)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (465:465:465) (540:540:540)) + (PORT datac (1126:1126:1126) (1207:1207:1207)) + (PORT datad (1305:1305:1305) (1428:1428:1428)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2299:2299:2299) (2269:2269:2269)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1572:1572:1572) (1566:1566:1566)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (367:367:367)) + (PORT datab (633:633:633) (704:704:704)) + (PORT datac (665:665:665) (725:725:725)) + (PORT datad (371:371:371) (439:439:439)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (461:461:461)) + (PORT datab (644:644:644) (691:691:691)) + (PORT datac (574:574:574) (627:627:627)) + (PORT datad (409:409:409) (468:468:468)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (686:686:686)) + (PORT datab (694:694:694) (758:758:758)) + (PORT datac (241:241:241) (329:329:329)) + (PORT datad (822:822:822) (866:866:866)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (801:801:801)) + (PORT datab (699:699:699) (780:780:780)) + (PORT datac (664:664:664) (739:739:739)) + (PORT datad (646:646:646) (703:703:703)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (667:667:667)) + (PORT datab (884:884:884) (898:898:898)) + (PORT datac (1079:1079:1079) (1100:1100:1100)) + (PORT datad (603:603:603) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1379:1379:1379)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (902:902:902) (939:939:939)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1563:1563:1563) (1545:1545:1545)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (904:904:904)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (223:223:223) (303:303:303)) + (PORT datad (413:413:413) (477:477:477)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1136:1136:1136) (1155:1155:1155)) + (PORT datac (2214:2214:2214) (2292:2292:2292)) + (PORT datad (414:414:414) (478:478:478)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (359:359:359) (391:391:391)) + (PORT datac (606:606:606) (616:616:616)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1413:1413:1413) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (363:363:363)) + (PORT datad (771:771:771) (829:829:829)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (904:904:904)) + (PORT datab (1137:1137:1137) (1154:1154:1154)) + (PORT datac (593:593:593) (616:616:616)) + (PORT datad (649:649:649) (709:709:709)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1574:1574:1574)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (2214:2214:2214) (2292:2292:2292)) + (PORT datad (627:627:627) (655:655:655)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (583:583:583) (592:592:592)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (855:855:855) (917:917:917)) + (PORT datac (548:548:548) (572:572:572)) + (PORT datad (1043:1043:1043) (1050:1050:1050)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1032:1032:1032)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (1394:1394:1394) (1471:1471:1471)) + (PORT datad (987:987:987) (1088:1088:1088)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT datab (1494:1494:1494) (1627:1627:1627)) + (PORT datac (1376:1376:1376) (1473:1473:1473)) + (PORT datad (1208:1208:1208) (1300:1300:1300)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1084:1084:1084)) + (PORT datab (849:849:849) (854:854:854)) + (PORT datac (1080:1080:1080) (1087:1087:1087)) + (PORT datad (871:871:871) (887:887:887)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datab (880:880:880) (940:940:940)) + (PORT datad (579:579:579) (602:602:602)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (213:213:213) (246:246:246)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_3) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (466:466:466)) + (PORT datab (343:343:343) (375:375:375)) + (PORT datac (342:342:342) (363:363:363)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1178:1178:1178)) + (PORT datab (868:868:868) (900:900:900)) + (PORT datac (1772:1772:1772) (1869:1869:1869)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1366:1366:1366)) + (PORT datab (830:830:830) (873:873:873)) + (PORT datac (985:985:985) (1040:1040:1040)) + (PORT datad (1086:1086:1086) (1122:1122:1122)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (812:812:812) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1084:1084:1084)) + (PORT datab (880:880:880) (968:968:968)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (360:360:360) (393:393:393)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1601:1601:1601) (1712:1712:1712)) + (PORT datab (274:274:274) (361:361:361)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2084:2084:2084) (2217:2217:2217)) + (PORT datab (931:931:931) (1010:1010:1010)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~28) + (DELAY + (ABSOLUTE + (PORT dataa (2230:2230:2230) (2341:2341:2341)) + (PORT datab (760:760:760) (857:857:857)) + (PORT datac (1722:1722:1722) (1802:1802:1802)) + (PORT datad (1798:1798:1798) (1917:1917:1917)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (945:945:945)) + (PORT datab (1153:1153:1153) (1210:1210:1210)) + (PORT datac (1217:1217:1217) (1267:1267:1267)) + (PORT datad (329:329:329) (341:341:341)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1241:1241:1241)) + (PORT datab (1172:1172:1172) (1192:1192:1192)) + (PORT datad (620:620:620) (653:653:653)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (428:428:428)) + (PORT datab (967:967:967) (1019:1019:1019)) + (PORT datac (1068:1068:1068) (1113:1113:1113)) + (PORT datad (203:203:203) (233:233:233)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (314:314:314)) + (PORT datab (1423:1423:1423) (1489:1489:1489)) + (PORT datac (1501:1501:1501) (1565:1565:1565)) + (PORT datad (1096:1096:1096) (1137:1137:1137)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1173:1173:1173) (1216:1216:1216)) + (PORT datac (1134:1134:1134) (1178:1178:1178)) + (PORT datad (1055:1055:1055) (1083:1083:1083)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~23) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (870:870:870)) + (PORT datab (987:987:987) (1091:1091:1091)) + (PORT datac (363:363:363) (392:392:392)) + (PORT datad (383:383:383) (414:414:414)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (701:701:701)) + (PORT datab (860:860:860) (906:906:906)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (924:924:924) (962:962:962)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~21) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (946:946:946) (1006:1006:1006)) + (PORT datac (564:564:564) (597:597:597)) + (PORT datad (600:600:600) (627:627:627)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1199:1199:1199)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (856:856:856) (875:875:875)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (990:990:990)) + (PORT datac (355:355:355) (387:387:387)) + (PORT datad (645:645:645) (697:697:697)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (716:716:716) (739:739:739)) + (PORT ena (1666:1666:1666) (1653:1653:1653)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1243:1243:1243)) + (PORT datab (403:403:403) (449:449:449)) + (PORT datad (1271:1271:1271) (1375:1375:1375)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1137:1137:1137) (1160:1160:1160)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (327:327:327) (345:345:345)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (243:243:243) (322:322:322)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1190:1190:1190) (1232:1232:1232)) + (PORT datac (350:350:350) (378:378:378)) + (PORT datad (369:369:369) (394:394:394)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (890:890:890) (913:913:913)) + (PORT datad (324:324:324) (336:336:336)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1535:1535:1535)) + (PORT ena (1964:1964:1964) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (906:906:906)) + (PORT datab (1061:1061:1061) (1089:1089:1089)) + (PORT datac (238:238:238) (321:321:321)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (794:794:794)) + (PORT datab (1384:1384:1384) (1454:1454:1454)) + (PORT datac (617:617:617) (667:667:667)) + (PORT datad (1481:1481:1481) (1521:1521:1521)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (686:686:686)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (728:728:728) (790:790:790)) + (PORT datad (588:588:588) (629:629:629)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (973:973:973) (989:989:989)) + (PORT ena (1957:1957:1957) (1949:1949:1949)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1272:1272:1272) (1364:1364:1364)) + (PORT datab (695:695:695) (747:747:747)) + (PORT datad (1354:1354:1354) (1362:1362:1362)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1650:1650:1650) (1628:1628:1628)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (404:404:404)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (1106:1106:1106) (1125:1125:1125)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (597:597:597)) + (PORT datab (1195:1195:1195) (1235:1235:1235)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (370:370:370) (393:393:393)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1184:1184:1184) (1216:1216:1216)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1215:1215:1215)) + (PORT datab (634:634:634) (689:689:689)) + (PORT datad (353:353:353) (377:377:377)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (892:892:892) (915:915:915)) + (PORT ena (1004:1004:1004) (1013:1013:1013)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (891:891:891) (913:913:913)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datad (554:554:554) (560:560:560)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1175:1175:1175) (1237:1237:1237)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1142:1142:1142) (1123:1123:1123)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT asdata (1237:1237:1237) (1302:1302:1302)) + (PORT ena (1392:1392:1392) (1380:1380:1380)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (899:899:899)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (838:838:838) (849:849:849)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1723:1723:1723) (1736:1736:1736)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT asdata (900:900:900) (916:916:916)) + (PORT ena (963:963:963) (961:961:961)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (459:459:459) (501:501:501)) + (PORT datad (1153:1153:1153) (1209:1209:1209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1721:1721:1721) (1782:1782:1782)) + (PORT ena (1407:1407:1407) (1397:1397:1397)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1718:1718:1718) (1780:1780:1780)) + (PORT ena (1446:1446:1446) (1420:1420:1420)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (983:983:983)) + (PORT datab (902:902:902) (939:939:939)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (2023:2023:2023) (2065:2065:2065)) + (PORT ena (1399:1399:1399) (1367:1367:1367)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (917:917:917)) + (PORT datab (1237:1237:1237) (1273:1273:1273)) + (PORT datad (548:548:548) (573:573:573)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (678:678:678) (702:702:702)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (674:674:674) (698:698:698)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (399:399:399)) + (PORT datab (869:869:869) (872:872:872)) + (PORT datac (767:767:767) (798:798:798)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (672:672:672)) + (PORT datab (548:548:548) (559:559:559)) + (PORT datac (1043:1043:1043) (1102:1102:1102)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (642:642:642)) + (PORT datab (645:645:645) (697:697:697)) + (PORT datac (689:689:689) (713:713:713)) + (PORT datad (338:338:338) (358:358:358)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1011:1011:1011)) + (PORT datab (905:905:905) (974:974:974)) + (PORT datac (587:587:587) (621:621:621)) + (PORT datad (660:660:660) (701:701:701)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1150:1150:1150)) + (PORT datab (268:268:268) (321:321:321)) + (PORT datac (176:176:176) (211:211:211)) + (PORT datad (903:903:903) (942:942:942)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (417:417:417)) + (PORT datab (369:369:369) (414:414:414)) + (PORT datac (1397:1397:1397) (1450:1450:1450)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (453:453:453)) + (PORT datab (1380:1380:1380) (1412:1412:1412)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1526:1526:1526) (1552:1552:1552)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (502:502:502)) + (PORT datab (1723:1723:1723) (1754:1754:1754)) + (PORT datac (1351:1351:1351) (1453:1453:1453)) + (PORT datad (1127:1127:1127) (1197:1197:1197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (952:952:952)) + (PORT datab (614:614:614) (631:631:631)) + (PORT datac (1298:1298:1298) (1368:1368:1368)) + (PORT datad (861:861:861) (885:885:885)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (921:921:921)) + (PORT datab (396:396:396) (425:425:425)) + (PORT datac (896:896:896) (961:961:961)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (688:688:688)) + (PORT datab (648:648:648) (662:662:662)) + (PORT datac (606:606:606) (630:630:630)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1448:1448:1448)) + (PORT datab (1205:1205:1205) (1255:1255:1255)) + (PORT datac (861:861:861) (876:876:876)) + (PORT datad (820:820:820) (832:832:832)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (1136:1136:1136) (1166:1166:1166)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (492:492:492)) + (PORT datab (905:905:905) (931:931:931)) + (PORT datac (806:806:806) (825:825:825)) + (PORT datad (379:379:379) (439:439:439)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (1080:1080:1080) (1164:1164:1164)) + (PORT datac (869:869:869) (936:936:936)) + (PORT datad (1127:1127:1127) (1197:1197:1197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (650:650:650)) + (PORT datab (395:395:395) (422:422:422)) + (PORT datac (834:834:834) (863:863:863)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (879:879:879)) + (PORT datab (203:203:203) (243:243:243)) + (PORT datac (210:210:210) (253:253:253)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (285:285:285)) + (PORT datab (668:668:668) (685:685:685)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1487:1487:1487)) + (PORT datab (418:418:418) (480:480:480)) + (PORT datac (1684:1684:1684) (1716:1716:1716)) + (PORT datad (882:882:882) (932:932:932)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (348:348:348)) + (PORT datab (271:271:271) (334:334:334)) + (PORT datad (244:244:244) (287:287:287)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (452:452:452)) + (PORT datac (1397:1397:1397) (1451:1451:1451)) + (PORT datad (750:750:750) (756:756:756)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (423:423:423)) + (PORT datab (1561:1561:1561) (1586:1586:1586)) + (PORT datac (1350:1350:1350) (1378:1378:1378)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (849:849:849)) + (PORT datab (1377:1377:1377) (1430:1430:1430)) + (PORT datac (869:869:869) (879:879:879)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (398:398:398)) + (PORT datab (1175:1175:1175) (1235:1235:1235)) + (PORT datac (600:600:600) (619:619:619)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (1060:1060:1060)) + (PORT datab (426:426:426) (484:484:484)) + (PORT datac (1286:1286:1286) (1302:1302:1302)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (999:999:999) (995:995:995)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (1195:1195:1195) (1210:1210:1210)) + (PORT datac (678:678:678) (735:735:735)) + (PORT datad (681:681:681) (732:732:732)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (949:949:949)) + (PORT datab (1169:1169:1169) (1191:1191:1191)) + (PORT datac (862:862:862) (872:872:872)) + (PORT datad (836:836:836) (847:847:847)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (372:372:372)) + (PORT datab (707:707:707) (740:740:740)) + (PORT datac (646:646:646) (668:668:668)) + (PORT datad (342:342:342) (364:364:364)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (250:250:250)) + (PORT datab (243:243:243) (287:287:287)) + (PORT datac (575:575:575) (587:587:587)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1474:1474:1474)) + (PORT datac (233:233:233) (286:286:286)) + (PORT datad (1451:1451:1451) (1538:1538:1538)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1081:1081:1081)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (624:624:624) (640:640:640)) + (PORT datad (920:920:920) (965:965:965)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1475:1475:1475)) + (PORT datab (1461:1461:1461) (1493:1493:1493)) + (PORT datac (1378:1378:1378) (1490:1490:1490)) + (PORT datad (805:805:805) (816:816:816)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1569:1569:1569)) + (PORT datab (1303:1303:1303) (1410:1410:1410)) + (PORT datac (2028:2028:2028) (2141:2141:2141)) + (PORT datad (842:842:842) (871:871:871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1260:1260:1260)) + (PORT datab (1144:1144:1144) (1208:1208:1208)) + (PORT datac (1198:1198:1198) (1307:1307:1307)) + (PORT datad (2338:2338:2338) (2445:2445:2445)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1273:1273:1273)) + (PORT datab (1446:1446:1446) (1521:1521:1521)) + (PORT datac (865:865:865) (916:916:916)) + (PORT datad (692:692:692) (755:755:755)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1668:1668:1668) (1859:1859:1859)) + (PORT datab (1254:1254:1254) (1330:1330:1330)) + (PORT datac (995:995:995) (1110:1110:1110)) + (PORT datad (1000:1000:1000) (1104:1104:1104)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (627:627:627)) + (PORT datab (593:593:593) (604:604:604)) + (PORT datac (1352:1352:1352) (1416:1416:1416)) + (PORT datad (1592:1592:1592) (1654:1654:1654)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1118:1118:1118)) + (PORT datab (644:644:644) (707:707:707)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (994:994:994) (1090:1090:1090)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (691:691:691)) + (PORT datab (372:372:372) (394:394:394)) + (PORT datac (618:618:618) (670:670:670)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (431:431:431)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (571:571:571) (583:583:583)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (705:705:705)) + (PORT datab (386:386:386) (406:406:406)) + (PORT datac (1171:1171:1171) (1214:1214:1214)) + (PORT datad (615:615:615) (642:642:642)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1587:1587:1587)) + (PORT datab (1330:1330:1330) (1403:1403:1403)) + (PORT datac (866:866:866) (893:893:893)) + (PORT datad (1169:1169:1169) (1196:1196:1196)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (893:893:893)) + (PORT datab (689:689:689) (750:750:750)) + (PORT datac (1158:1158:1158) (1236:1236:1236)) + (PORT datad (895:895:895) (911:911:911)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1074:1074:1074)) + (PORT datac (973:973:973) (1068:1068:1068)) + (PORT datad (991:991:991) (1084:1084:1084)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (744:744:744)) + (PORT datac (2044:2044:2044) (2097:2097:2097)) + (PORT datad (893:893:893) (910:910:910)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (893:893:893)) + (PORT datab (1079:1079:1079) (1162:1162:1162)) + (PORT datac (1261:1261:1261) (1297:1297:1297)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1156:1156:1156)) + (PORT datab (895:895:895) (917:917:917)) + (PORT datac (1251:1251:1251) (1294:1294:1294)) + (PORT datad (1568:1568:1568) (1587:1587:1587)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (308:308:308)) + (PORT datab (878:878:878) (913:913:913)) + (PORT datad (568:568:568) (589:589:589)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (925:925:925)) + (PORT datab (874:874:874) (915:915:915)) + (PORT datac (651:651:651) (700:700:700)) + (PORT datad (895:895:895) (908:908:908)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (659:659:659)) + (PORT datab (383:383:383) (415:415:415)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (656:656:656) (697:697:697)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1109:1109:1109) (1154:1154:1154)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (643:643:643)) + (PORT datab (634:634:634) (691:691:691)) + (PORT datac (1096:1096:1096) (1111:1111:1111)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1196:1196:1196)) + (PORT datab (657:657:657) (731:731:731)) + (PORT datac (637:637:637) (667:667:667)) + (PORT datad (1415:1415:1415) (1415:1415:1415)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (280:280:280)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1417:1417:1417) (1490:1490:1490)) + (PORT datad (1124:1124:1124) (1144:1144:1144)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (960:960:960)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (601:601:601) (647:647:647)) + (PORT datad (574:574:574) (589:589:589)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (743:743:743)) + (PORT datab (1219:1219:1219) (1273:1273:1273)) + (PORT datac (1133:1133:1133) (1161:1161:1161)) + (PORT datad (623:623:623) (658:658:658)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (690:690:690)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1161:1161:1161) (1240:1240:1240)) + (PORT datad (893:893:893) (907:907:907)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (646:646:646)) + (PORT datab (860:860:860) (907:907:907)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (924:924:924) (962:962:962)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (918:918:918)) + (PORT datab (2172:2172:2172) (2342:2342:2342)) + (PORT datac (1559:1559:1559) (1744:1744:1744)) + (PORT datad (1897:1897:1897) (2012:2012:2012)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (1593:1593:1593) (1774:1774:1774)) + (PORT datac (1141:1141:1141) (1169:1169:1169)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1578:1578:1578) (1718:1718:1718)) + (PORT datac (1288:1288:1288) (1383:1383:1383)) + (PORT datad (1582:1582:1582) (1719:1719:1719)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1535:1535:1535)) + (PORT datab (1194:1194:1194) (1233:1233:1233)) + (PORT datac (879:879:879) (932:932:932)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1956:1956:1956) (2051:2051:2051)) + (PORT datab (945:945:945) (991:991:991)) + (PORT datac (1612:1612:1612) (1657:1657:1657)) + (PORT datad (918:918:918) (942:942:942)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1223:1223:1223)) + (PORT datac (1292:1292:1292) (1388:1388:1388)) + (PORT datad (1554:1554:1554) (1681:1681:1681)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1397:1397:1397) (1448:1448:1448)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (384:384:384)) + (PORT datab (985:985:985) (1061:1061:1061)) + (PORT datac (678:678:678) (742:742:742)) + (PORT datad (1707:1707:1707) (1803:1803:1803)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1619:1619:1619)) + (PORT datab (672:672:672) (690:690:690)) + (PORT datac (1082:1082:1082) (1124:1124:1124)) + (PORT datad (1096:1096:1096) (1123:1123:1123)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1128:1128:1128)) + (PORT datab (1115:1115:1115) (1133:1133:1133)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1346:1346:1346) (1387:1387:1387)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1563:1563:1563) (1598:1598:1598)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (560:560:560) (634:634:634)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1563:1563:1563) (1598:1598:1598)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (296:296:296)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1593:1593:1593) (1635:1635:1635)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1541:1541:1541)) + (PORT asdata (567:567:567) (646:646:646)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (1593:1593:1593) (1635:1635:1635)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (341:341:341)) + (PORT datad (223:223:223) (295:295:295)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (966:966:966)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (193:193:193) (225:225:225)) + (PORT datad (899:899:899) (925:925:925)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (847:847:847) (874:874:874)) + (PORT datac (1718:1718:1718) (1715:1715:1715)) + (PORT datad (1217:1217:1217) (1247:1247:1247)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1959:1959:1959) (2001:2001:2001)) + (PORT datab (1439:1439:1439) (1494:1494:1494)) + (PORT datac (1855:1855:1855) (1888:1888:1888)) + (PORT datad (873:873:873) (882:882:882)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (665:665:665)) + (PORT datab (650:650:650) (679:679:679)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (637:637:637) (648:648:648)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (195:195:195) (228:228:228)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1075:1075:1075)) + (PORT datab (616:616:616) (639:639:639)) + (PORT datac (1739:1739:1739) (1802:1802:1802)) + (PORT datad (595:595:595) (619:619:619)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (1120:1120:1120) (1143:1143:1143)) + (PORT datac (562:562:562) (582:582:582)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1487:1487:1487) (1502:1502:1502)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1530:1530:1530)) + (PORT asdata (1306:1306:1306) (1378:1378:1378)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1223:1223:1223) (1226:1226:1226)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT asdata (947:947:947) (1011:1011:1011)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1221:1221:1221)) + (PORT datac (1132:1132:1132) (1198:1198:1198)) + (PORT datad (221:221:221) (292:292:292)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datac (1689:1689:1689) (1798:1798:1798)) + (PORT datad (1932:1932:1932) (2117:2117:2117)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2140:2140:2140) (2292:2292:2292)) + (PORT datab (1044:1044:1044) (1164:1164:1164)) + (PORT datac (981:981:981) (1070:1070:1070)) + (PORT datad (1460:1460:1460) (1581:1581:1581)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1629:1629:1629)) + (PORT datad (1565:1565:1565) (1659:1659:1659)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (268:268:268)) + (PORT datab (822:822:822) (839:839:839)) + (PORT datac (1067:1067:1067) (1094:1094:1094)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (909:909:909)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (639:639:639) (668:668:668)) + (PORT datad (590:590:590) (610:610:610)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1656:1656:1656)) + (PORT datab (573:573:573) (597:597:597)) + (PORT datac (815:815:815) (853:853:853)) + (PORT datad (1161:1161:1161) (1212:1212:1212)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (684:684:684)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (633:633:633) (660:660:660)) + (PORT datad (948:948:948) (1032:1032:1032)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1240:1240:1240)) + (PORT datab (1170:1170:1170) (1187:1187:1187)) + (PORT datac (1126:1126:1126) (1176:1176:1176)) + (PORT datad (573:573:573) (591:591:591)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1628:1628:1628)) + (PORT datab (1056:1056:1056) (1074:1074:1074)) + (PORT datac (1287:1287:1287) (1400:1400:1400)) + (PORT datad (1142:1142:1142) (1183:1183:1183)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (825:825:825)) + (PORT datab (1496:1496:1496) (1556:1556:1556)) + (PORT datac (892:892:892) (943:943:943)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (747:747:747)) + (PORT datab (1194:1194:1194) (1241:1241:1241)) + (PORT datac (573:573:573) (591:591:591)) + (PORT datad (1231:1231:1231) (1265:1265:1265)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2140:2140:2140) (2291:2291:2291)) + (PORT datab (1400:1400:1400) (1445:1445:1445)) + (PORT datac (1045:1045:1045) (1075:1075:1075)) + (PORT datad (971:971:971) (1060:1060:1060)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (943:943:943)) + (PORT datab (1258:1258:1258) (1304:1304:1304)) + (PORT datac (612:612:612) (635:635:635)) + (PORT datad (784:784:784) (804:804:804)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1622:1622:1622)) + (PORT datac (977:977:977) (1066:1066:1066)) + (PORT datad (2094:2094:2094) (2238:2238:2238)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1418:1418:1418)) + (PORT datab (284:284:284) (374:374:374)) + (PORT datac (1167:1167:1167) (1179:1179:1179)) + (PORT datad (1155:1155:1155) (1191:1191:1191)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1228:1228:1228) (1217:1217:1217)) + (PORT datac (1078:1078:1078) (1102:1102:1102)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1274:1274:1274)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (610:610:610) (631:631:631)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1786:1786:1786) (1866:1866:1866)) + (PORT datab (966:966:966) (1013:1013:1013)) + (PORT datac (615:615:615) (624:624:624)) + (PORT datad (1516:1516:1516) (1553:1553:1553)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (394:394:394)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (592:592:592)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1056:1056:1056) (1068:1068:1068)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1592:1592:1592) (1661:1661:1661)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (788:788:788) (860:860:860)) + (PORT datad (1840:1840:1840) (1890:1890:1890)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (688:688:688)) + (PORT datab (377:377:377) (399:399:399)) + (PORT datac (1068:1068:1068) (1108:1108:1108)) + (PORT datad (842:842:842) (878:878:878)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1223:1223:1223)) + (PORT datab (2537:2537:2537) (2642:2642:2642)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1332:1332:1332) (1343:1343:1343)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1215:1215:1215)) + (PORT datab (1163:1163:1163) (1208:1208:1208)) + (PORT datac (1214:1214:1214) (1289:1289:1289)) + (PORT datad (1206:1206:1206) (1262:1262:1262)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1145:1145:1145) (1194:1194:1194)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1534:1534:1534)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (710:710:710) (770:770:770)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (465:465:465)) + (PORT datad (1256:1256:1256) (1328:1328:1328)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1272:1272:1272)) + (PORT datab (1162:1162:1162) (1210:1210:1210)) + (PORT datac (1211:1211:1211) (1291:1291:1291)) + (PORT datad (1623:1623:1623) (1664:1664:1664)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (929:929:929)) + (PORT datac (943:943:943) (984:984:984)) + (PORT datad (1213:1213:1213) (1229:1229:1229)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (563:563:563)) + (PORT datab (556:556:556) (577:577:577)) + (PORT datad (863:863:863) (917:917:917)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31064,11 +31620,11 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (1382:1382:1382) (1568:1568:1568)) - (PORT datac (1328:1328:1328) (1469:1469:1469)) - (PORT datad (2533:2533:2533) (2621:2621:2621)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1522:1522:1522) (1626:1626:1626)) + (PORT datab (938:938:938) (1011:1011:1011)) + (PORT datad (1498:1498:1498) (1593:1593:1593)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31078,10 +31634,10 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1163:1163:1163)) - (PORT datab (924:924:924) (979:979:979)) - (PORT datac (820:820:820) (846:846:846)) - (PORT datad (1655:1655:1655) (1830:1830:1830)) + (PORT dataa (864:864:864) (916:916:916)) + (PORT datab (2172:2172:2172) (2345:2345:2345)) + (PORT datac (1140:1140:1140) (1171:1171:1171)) + (PORT datad (802:802:802) (810:810:810)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -31094,12 +31650,12 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1914:1914:1914) (2085:2085:2085)) - (PORT datac (2116:2116:2116) (2227:2227:2227)) - (PORT datad (1650:1650:1650) (1834:1834:1834)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1515:1515:1515) (1643:1643:1643)) + (PORT datab (827:827:827) (874:874:874)) + (PORT datac (1854:1854:1854) (1974:1974:1974)) + (PORT datad (1755:1755:1755) (1874:1874:1874)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31107,14 +31663,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1184:1184:1184) (1229:1229:1229)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) + (PORT asdata (1172:1172:1172) (1215:1215:1215)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31127,24 +31683,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT datac (1399:1399:1399) (1483:1483:1483)) - (PORT datad (1955:1955:1955) (2153:2153:2153)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (369:369:369) (392:392:392)) + (PORT datab (540:540:540) (559:559:559)) + (PORT datad (863:863:863) (918:918:918)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (961:961:961) (1001:1001:1001)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1480:1480:1480)) + (PORT datab (1122:1122:1122) (1187:1187:1187)) + (PORT datac (1126:1126:1126) (1187:1187:1187)) + (PORT datad (1141:1141:1141) (1208:1208:1208)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1180:1180:1180) (1258:1258:1258)) - (PORT datab (195:195:195) (234:234:234)) - (PORT datad (566:566:566) (578:578:578)) + (PORT dataa (880:880:880) (936:936:936)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (196:196:196) (221:221:221)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -31153,14 +31747,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT clk (1524:1524:1524) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (753:753:753) (819:819:819)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) + (PORT asdata (936:936:936) (990:990:990)) + (PORT sload (1231:1231:1231) (1309:1309:1309)) + (PORT ena (2105:2105:2105) (2109:2109:2109)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31173,104 +31767,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) + (INSTANCE z80_\|address_pins_\|abus\[6\]\~25) (DELAY (ABSOLUTE - (PORT dataa (2315:2315:2315) (2530:2530:2530)) - (PORT datad (1404:1404:1404) (1520:1520:1520)) + (PORT dataa (1332:1332:1332) (1475:1475:1475)) + (PORT datac (875:875:875) (953:953:953)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) (DELAY (ABSOLUTE - (PORT dataa (303:303:303) (420:420:420)) - (PORT datac (915:915:915) (973:973:973)) - (PORT datad (643:643:643) (704:704:704)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (640:640:640)) - (PORT datab (1304:1304:1304) (1358:1358:1358)) - (PORT datac (728:728:728) (812:812:812)) - (PORT datad (618:618:618) (638:638:638)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (436:436:436)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (221:221:221) (266:266:266)) + (PORT datab (634:634:634) (659:659:659)) + (PORT datad (864:864:864) (915:915:915)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (PORT asdata (942:942:942) (989:989:989)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE z80_\|address_pins_\|abus\[7\]\~26) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (716:716:716)) - (PORT datab (2772:2772:2772) (2956:2956:2956)) - (PORT datac (648:648:648) (682:682:682)) - (PORT datad (637:637:637) (706:706:706)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (367:367:367)) - (PORT datab (955:955:955) (1021:1021:1021)) - (PORT datac (1004:1004:1004) (1065:1065:1065)) - (PORT datad (262:262:262) (340:340:340)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (234:234:234) (310:310:310)) + (PORT datad (2373:2373:2373) (2488:2488:2488)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31278,27 +31825,133 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1065:1065:1065) (1138:1138:1138)) - (PORT datac (266:266:266) (360:360:360)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (383:383:383) (411:411:411)) + (PORT datab (886:886:886) (952:952:952)) + (PORT datad (346:346:346) (362:362:362)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (949:949:949) (1005:1005:1005)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (940:940:940)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (947:947:947) (1004:1004:1004)) + (PORT sload (1231:1231:1231) (1309:1309:1309)) + (PORT ena (2105:2105:2105) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (942:942:942)) + (PORT datab (337:337:337) (367:367:367)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (584:584:584) (672:672:672)) + (PORT sload (1231:1231:1231) (1309:1309:1309)) + (PORT ena (2105:2105:2105) (2109:2109:2109)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1235:1235:1235)) + (PORT datab (1107:1107:1107) (1189:1189:1189)) + (PORT datac (1129:1129:1129) (1199:1199:1199)) + (PORT datad (1308:1308:1308) (1432:1432:1432)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (INSTANCE Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (299:299:299) (419:419:419)) - (PORT datac (911:911:911) (974:974:974)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (356:356:356) (387:387:387)) + (PORT datac (1098:1098:1098) (1129:1129:1129)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -31306,148 +31959,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (INSTANCE D\[5\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1228:1228:1228) (1254:1254:1254)) - (PORT datac (699:699:699) (766:766:766)) - (PORT datad (614:614:614) (688:688:688)) + (PORT dataa (417:417:417) (452:452:452)) + (PORT datac (364:364:364) (395:395:395)) + (PORT datad (1087:1087:1087) (1153:1153:1153)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (869:869:869)) - (PORT datab (336:336:336) (364:364:364)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT datab (772:772:772) (854:854:854)) - (PORT datac (461:461:461) (534:534:534)) - (PORT datad (928:928:928) (988:988:988)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1071:1071:1071)) - (PORT datab (656:656:656) (730:730:730)) - (PORT datac (702:702:702) (766:766:766)) - (PORT datad (1186:1186:1186) (1205:1205:1205)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1062:1062:1062)) - (PORT datab (770:770:770) (851:851:851)) - (PORT datac (697:697:697) (772:772:772)) - (PORT datad (969:969:969) (1035:1035:1035)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (838:838:838)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (562:562:562) (579:579:579)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (1121:1121:1121) (1187:1187:1187)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (650:650:650) (668:668:668)) + (PORT datab (892:892:892) (960:960:960)) + (PORT datad (570:570:570) (574:574:574)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31457,11 +31990,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (895:895:895) (951:951:951)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) + (PORT asdata (902:902:902) (966:966:966)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31474,12 +32007,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~23) (DELAY (ABSOLUTE - (PORT datac (1681:1681:1681) (1850:1850:1850)) - (PORT datad (2616:2616:2616) (2812:2812:2812)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2416:2416:2416) (2538:2538:2538)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31489,9 +32022,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (350:350:350) (377:377:377)) - (PORT datad (1120:1120:1120) (1184:1184:1184)) + (PORT dataa (557:557:557) (570:570:570)) + (PORT datab (639:639:639) (665:665:665)) + (PORT datad (859:859:859) (917:917:917)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -31503,11 +32036,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (928:928:928) (977:977:977)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) + (PORT asdata (1735:1735:1735) (1808:1808:1808)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31523,214 +32056,23 @@ (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) (DELAY (ABSOLUTE - (PORT dataa (2421:2421:2421) (2631:2631:2631)) - (PORT datad (1663:1663:1663) (1788:1788:1788)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (1293:1293:1293) (1369:1369:1369)) - (PORT datac (707:707:707) (797:797:797)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (948:948:948) (1035:1035:1035)) + (PORT datac (1471:1471:1471) (1591:1591:1591)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (871:871:871)) - (PORT datab (699:699:699) (763:763:763)) - (PORT datac (704:704:704) (770:770:770)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT datac (680:680:680) (750:750:750)) - (PORT datad (740:740:740) (823:823:823)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (817:817:817)) - (PORT datab (1292:1292:1292) (1364:1364:1364)) - (PORT datac (707:707:707) (793:793:793)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (762:762:762) (842:842:842)) - (PORT datad (206:206:206) (236:236:236)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (396:396:396)) - (PORT datac (848:848:848) (867:867:867)) - (PORT datad (709:709:709) (783:783:783)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (757:757:757)) - (PORT datac (984:984:984) (1047:1047:1047)) - (PORT datad (652:652:652) (732:732:732)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (942:942:942)) - (PORT datab (605:605:605) (646:646:646)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (712:712:712)) - (PORT datab (1468:1468:1468) (1492:1492:1492)) - (PORT datac (912:912:912) (969:969:969)) - (PORT datad (362:362:362) (421:421:421)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datad (1120:1120:1120) (1184:1184:1184)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (726:726:726) (799:799:799)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (1811:1811:1811) (1928:1928:1928)) - (PORT datac (2265:2265:2265) (2463:2463:2463)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (397:397:397)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datad (1124:1124:1124) (1188:1188:1188)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (807:807:807) (833:833:833)) + (PORT datab (814:814:814) (849:849:849)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -31740,11 +32082,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (741:741:741) (815:815:815)) - (PORT sload (1199:1199:1199) (1277:1277:1277)) - (PORT ena (1447:1447:1447) (1469:1469:1469)) + (PORT asdata (1262:1262:1262) (1310:1310:1310)) + (PORT sload (1742:1742:1742) (1823:1823:1823)) + (PORT ena (1431:1431:1431) (1435:1435:1435)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -31757,505 +32099,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (436:436:436)) - (PORT datab (764:764:764) (853:853:853)) - (PORT datac (695:695:695) (784:784:784)) - (PORT datad (346:346:346) (371:371:371)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT datab (426:426:426) (500:500:500)) - (PORT datac (745:745:745) (821:821:821)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (259:259:259)) - (PORT datab (769:769:769) (850:850:850)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1971:1971:1971) (2134:2134:2134)) - (PORT datac (2268:2268:2268) (2463:2463:2463)) - (PORT datad (668:668:668) (730:730:730)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (1011:1011:1011)) - (PORT datab (983:983:983) (1055:1055:1055)) - (PORT datad (204:204:204) (233:233:233)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1104:1104:1104)) - (PORT datab (287:287:287) (378:378:378)) - (PORT datac (245:245:245) (328:328:328)) - (PORT datad (709:709:709) (788:788:788)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1139:1139:1139)) - (PORT datab (956:956:956) (1026:1026:1026)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (436:436:436)) - (PORT datab (631:631:631) (655:655:655)) - (PORT datad (794:794:794) (817:817:817)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (634:634:634) (705:705:705)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1412:1412:1412) (1526:1526:1526)) + (PORT datac (242:242:242) (321:321:321)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datac (2534:2534:2534) (2773:2773:2773)) - (PORT datad (1184:1184:1184) (1290:1290:1290)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (825:825:825)) - (PORT datab (932:932:932) (1013:1013:1013)) - (PORT datac (754:754:754) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (992:992:992)) - (PORT datab (738:738:738) (804:804:804)) - (PORT datac (695:695:695) (782:782:782)) - (PORT datad (355:355:355) (387:387:387)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (471:471:471) (550:550:550)) - (PORT datad (633:633:633) (650:650:650)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (572:572:572)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (728:728:728) (813:813:813)) - (PORT datad (750:750:750) (828:828:828)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (441:441:441)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1258:1258:1258)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datad (319:319:319) (337:337:337)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (736:736:736) (808:808:808)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2312:2312:2312) (2526:2526:2526)) - (PORT datad (1425:1425:1425) (1538:1538:1538)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1257:1257:1257)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (734:734:734) (795:795:795)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (931:931:931) (1029:1029:1029)) - (PORT datad (2391:2391:2391) (2584:2584:2584)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (785:785:785)) - (PORT datab (676:676:676) (757:757:757)) - (PORT datac (673:673:673) (715:715:715)) - (PORT datad (1494:1494:1494) (1586:1586:1586)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (2355:2355:2355) (2578:2578:2578)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1533:1533:1533)) - (PORT asdata (569:569:569) (649:649:649)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (232:232:232) (306:306:306)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (994:994:994) (1049:1049:1049)) - (PORT datad (230:230:230) (303:303:303)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2634:2634:2634) (2764:2764:2764)) - (PORT datab (1939:1939:1939) (2080:2080:2080)) - (PORT datac (2770:2770:2770) (3002:3002:3002)) - (PORT datad (2212:2212:2212) (2284:2284:2284)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1973:1973:1973) (2138:2138:2138)) - (PORT datac (2265:2265:2265) (2462:2462:2462)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -32264,953 +32114,26 @@ (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (2634:2634:2634) (2769:2769:2769)) - (PORT datab (1937:1937:1937) (2082:2082:2082)) - (PORT datac (2770:2770:2770) (3003:3003:3003)) - (PORT datad (2214:2214:2214) (2287:2287:2287)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1206:1206:1206) (1274:1274:1274)) + (PORT datab (1163:1163:1163) (1210:1210:1210)) + (PORT datac (1212:1212:1212) (1292:1292:1292)) + (PORT datad (1623:1623:1623) (1665:1665:1665)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (462:462:462)) - (PORT datab (1257:1257:1257) (1295:1295:1295)) - (PORT datac (1233:1233:1233) (1265:1265:1265)) - (PORT datad (1391:1391:1391) (1417:1417:1417)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1921:1921:1921) (2116:2116:2116)) - (PORT datac (1982:1982:1982) (2198:2198:2198)) - (PORT datad (1426:1426:1426) (1533:1533:1533)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (253:253:253)) - (PORT datab (616:616:616) (630:630:630)) - (PORT datad (908:908:908) (944:944:944)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (995:995:995) (1050:1050:1050)) - (PORT sload (1199:1199:1199) (1276:1276:1276)) - (PORT ena (1212:1212:1212) (1237:1237:1237)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2422:2422:2422) (2631:2631:2631)) - (PORT datac (1069:1069:1069) (1151:1151:1151)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1695:1695:1695) (1773:1773:1773)) - (PORT datad (325:325:325) (351:351:351)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (938:938:938) (1005:1005:1005)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1227:1227:1227)) - (PORT datad (2391:2391:2391) (2584:2584:2584)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (891:891:891)) - (PORT datab (1716:1716:1716) (1784:1784:1784)) - (PORT datad (875:875:875) (908:908:908)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1270:1270:1270) (1328:1328:1328)) - (PORT sload (1357:1357:1357) (1408:1408:1408)) - (PORT ena (1406:1406:1406) (1406:1406:1406)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (345:345:345)) - (PORT datad (2385:2385:2385) (2578:2578:2578)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datad (1658:1658:1658) (1733:1733:1733)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (899:899:899) (959:959:959)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (282:282:282) (364:364:364)) - (PORT datad (377:377:377) (439:439:439)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1695:1695:1695) (1769:1769:1769)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (959:959:959) (1008:1008:1008)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datac (1237:1237:1237) (1358:1358:1358)) - (PORT datad (2381:2381:2381) (2572:2572:2572)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (561:561:561)) - (PORT datab (1692:1692:1692) (1769:1769:1769)) - (PORT datad (316:316:316) (329:329:329)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (588:588:588) (666:666:666)) - (PORT sload (1638:1638:1638) (1687:1687:1687)) - (PORT ena (1450:1450:1450) (1447:1447:1447)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datac (1495:1495:1495) (1601:1601:1601)) - (PORT datad (2387:2387:2387) (2578:2578:2578)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1094:1094:1094)) - (PORT datab (898:898:898) (948:948:948)) - (PORT datad (1691:1691:1691) (1747:1747:1747)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1266:1266:1266) (1347:1347:1347)) - (PORT sload (1357:1357:1357) (1408:1408:1408)) - (PORT ena (1406:1406:1406) (1406:1406:1406)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (2419:2419:2419) (2625:2625:2625)) - (PORT datac (245:245:245) (324:324:324)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1325:1325:1325) (1393:1393:1393)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2362:2362:2362) (2570:2570:2570)) - (PORT d[1] (2582:2582:2582) (2663:2663:2663)) - (PORT d[2] (1885:1885:1885) (2005:2005:2005)) - (PORT d[3] (1262:1262:1262) (1338:1338:1338)) - (PORT d[4] (2266:2266:2266) (2355:2355:2355)) - (PORT d[5] (1286:1286:1286) (1366:1366:1366)) - (PORT d[6] (1452:1452:1452) (1480:1480:1480)) - (PORT d[7] (2355:2355:2355) (2491:2491:2491)) - (PORT d[8] (2239:2239:2239) (2395:2395:2395)) - (PORT d[9] (1053:1053:1053) (1110:1110:1110)) - (PORT d[10] (1026:1026:1026) (1074:1074:1074)) - (PORT d[11] (1436:1436:1436) (1501:1501:1501)) - (PORT d[12] (756:756:756) (816:816:816)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1782:1782:1782) (1767:1767:1767)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (1825:1825:1825) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1887:1887:1887) (1911:1911:1911)) - (PORT asdata (2020:2020:2020) (2056:2056:2056)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1760:1760:1760) (1806:1806:1806)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1013:1013:1013)) - (PORT datab (895:895:895) (947:947:947)) - (PORT datac (1141:1141:1141) (1200:1200:1200)) - (PORT datad (964:964:964) (1019:1019:1019)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1919:1919:1919) (2115:2115:2115)) - (PORT datac (1982:1982:1982) (2200:2200:2200)) - (PORT datad (1422:1422:1422) (1531:1531:1531)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1512:1512:1512) (1551:1551:1551)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1938:1938:1938) (2080:2080:2080)) - (PORT d[1] (2501:2501:2501) (2527:2527:2527)) - (PORT d[2] (2588:2588:2588) (2765:2765:2765)) - (PORT d[3] (1139:1139:1139) (1178:1178:1178)) - (PORT d[4] (2415:2415:2415) (2565:2565:2565)) - (PORT d[5] (3170:3170:3170) (3226:3226:3226)) - (PORT d[6] (2192:2192:2192) (2289:2289:2289)) - (PORT d[7] (1851:1851:1851) (1867:1867:1867)) - (PORT d[8] (2510:2510:2510) (2632:2632:2632)) - (PORT d[9] (1705:1705:1705) (1750:1750:1750)) - (PORT d[10] (2512:2512:2512) (2611:2611:2611)) - (PORT d[11] (4013:4013:4013) (4323:4323:4323)) - (PORT d[12] (2512:2512:2512) (2564:2564:2564)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2002:2002:2002) (1964:1964:1964)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (PORT d[0] (2197:2197:2197) (2152:2152:2152)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (462:462:462)) - (PORT datab (1257:1257:1257) (1300:1300:1300)) - (PORT datac (1234:1234:1234) (1270:1270:1270)) - (PORT datad (1392:1392:1392) (1420:1420:1420)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1920:1920:1920) (2115:2115:2115)) - (PORT datac (1982:1982:1982) (2197:2197:2197)) - (PORT datad (1425:1425:1425) (1529:1529:1529)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (852:852:852) (854:854:854)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2917:2917:2917) (3108:3108:3108)) - (PORT d[1] (3323:3323:3323) (3498:3498:3498)) - (PORT d[2] (1499:1499:1499) (1573:1573:1573)) - (PORT d[3] (3966:3966:3966) (4139:4139:4139)) - (PORT d[4] (2897:2897:2897) (3086:3086:3086)) - (PORT d[5] (4427:4427:4427) (4564:4564:4564)) - (PORT d[6] (2208:2208:2208) (2294:2294:2294)) - (PORT d[7] (3987:3987:3987) (4071:4071:4071)) - (PORT d[8] (1521:1521:1521) (1551:1551:1551)) - (PORT d[9] (2130:2130:2130) (2218:2218:2218)) - (PORT d[10] (2303:2303:2303) (2371:2371:2371)) - (PORT d[11] (3139:3139:3139) (3345:3345:3345)) - (PORT d[12] (4131:4131:4131) (4403:4403:4403)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1928:1928:1928) (1901:1901:1901)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2721:2721:2721) (2738:2738:2738)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1492:1492:1492) (1564:1564:1564)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (944:944:944) (997:997:997)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (465:465:465)) - (PORT datab (1252:1252:1252) (1298:1298:1298)) - (PORT datac (1232:1232:1232) (1268:1268:1268)) - (PORT datad (1391:1391:1391) (1418:1418:1418)) + (PORT dataa (2097:2097:2097) (2228:2228:2228)) + (PORT datab (998:998:998) (1054:1054:1054)) + (PORT datac (1756:1756:1756) (1816:1816:1816)) + (PORT datad (217:217:217) (252:252:252)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -33223,6227 +32146,323 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1915:1915:1915) (2111:2111:2111)) - (PORT datac (1984:1984:1984) (2198:2198:2198)) - (PORT datad (1420:1420:1420) (1527:1527:1527)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1308:1308:1308) (1374:1374:1374)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2112:2112:2112) (2310:2310:2310)) - (PORT d[1] (2254:2254:2254) (2334:2334:2334)) - (PORT d[2] (1596:1596:1596) (1699:1699:1699)) - (PORT d[3] (2501:2501:2501) (2593:2593:2593)) - (PORT d[4] (2291:2291:2291) (2367:2367:2367)) - (PORT d[5] (1576:1576:1576) (1652:1652:1652)) - (PORT d[6] (1720:1720:1720) (1763:1763:1763)) - (PORT d[7] (2216:2216:2216) (2273:2273:2273)) - (PORT d[8] (2483:2483:2483) (2655:2655:2655)) - (PORT d[9] (1067:1067:1067) (1146:1146:1146)) - (PORT d[10] (1734:1734:1734) (1816:1816:1816)) - (PORT d[11] (1425:1425:1425) (1474:1474:1474)) - (PORT d[12] (1019:1019:1019) (1090:1090:1090)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1513:1513:1513) (1529:1529:1529)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2023:2023:2023) (2001:2001:2001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1125:1125:1125)) - (PORT datab (1546:1546:1546) (1595:1595:1595)) - (PORT datac (1417:1417:1417) (1491:1491:1491)) - (PORT datad (1479:1479:1479) (1560:1560:1560)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1351:1351:1351)) - (PORT datab (1832:1832:1832) (1977:1977:1977)) - (PORT datac (1662:1662:1662) (1715:1715:1715)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (463:463:463)) - (PORT datab (1250:1250:1250) (1293:1293:1293)) - (PORT datac (1232:1232:1232) (1265:1265:1265)) - (PORT datad (1387:1387:1387) (1415:1415:1415)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (950:950:950) (1036:1036:1036)) + (PORT datac (1472:1472:1472) (1595:1595:1595)) + (PORT datad (1170:1170:1170) (1274:1274:1274)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~24) (DELAY (ABSOLUTE - (PORT inclk[0] (154:154:154) (138:138:138)) + (PORT datab (1125:1125:1125) (1189:1189:1189)) + (PORT datad (1308:1308:1308) (1432:1432:1432)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~27) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (541:541:541)) - (PORT datab (973:973:973) (1044:1044:1044)) - (PORT datac (711:711:711) (774:774:774)) - (PORT datad (740:740:740) (796:796:796)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1336:1336:1336) (1482:1482:1482)) + (PORT datac (1124:1124:1124) (1185:1185:1185)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1481:1481:1481)) + (PORT datad (1139:1139:1139) (1205:1205:1205)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datad (2373:2373:2373) (2488:2488:2488)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (1107:1107:1107) (1190:1190:1190)) + (PORT datad (1307:1307:1307) (1432:1432:1432)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1483:1483:1483)) + (PORT datac (1128:1128:1128) (1200:1200:1200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (875:875:875) (935:935:935)) + (PORT datad (310:310:310) (328:328:328)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT asdata (996:996:996) (1046:1046:1046)) - (PORT ena (817:817:817) (814:814:814)) + (PORT clk (1525:1525:1525) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (933:933:933) (988:988:988)) + (PORT sload (1276:1276:1276) (1363:1363:1363)) + (PORT ena (1928:1928:1928) (1942:1942:1942)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (INSTANCE z80_\|address_pins_\|abus\[8\]\~17) (DELAY (ABSOLUTE - (PORT datad (885:885:885) (926:926:926)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (911:911:911) (966:966:966)) + (PORT dataa (644:644:644) (710:710:710)) + (PORT datac (1923:1923:1923) (2049:2049:2049)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) (DELAY (ABSOLUTE - (PORT datac (915:915:915) (971:971:971)) - (PORT datad (883:883:883) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (1011:1011:1011)) - (PORT datab (911:911:911) (982:982:982)) - (PORT datad (876:876:876) (933:933:933)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (817:817:817) (814:814:814)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1271:1271:1271) (1341:1341:1341)) - (PORT datab (629:629:629) (682:682:682)) + (PORT dataa (387:387:387) (415:415:415)) + (PORT datab (876:876:876) (937:937:937)) + (PORT datad (314:314:314) (334:334:334)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) (DELAY (ABSOLUTE - (PORT dataa (744:744:744) (808:808:808)) + (PORT clk (1525:1525:1525) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1276:1276:1276) (1363:1363:1363)) + (PORT ena (1928:1928:1928) (1942:1942:1942)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2171:2171:2171) (2320:2320:2320)) + (PORT datad (244:244:244) (316:316:316)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (756:756:756)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (941:941:941) (983:983:983)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (946:946:946) (928:928:928)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1009:1009:1009)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (946:946:946) (928:928:928)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT datab (959:959:959) (1008:1008:1008)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (946:946:946) (928:928:928)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (781:781:781)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (960:960:960) (1021:1021:1021)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (447:447:447) (541:541:541)) - (PORT datab (970:970:970) (1040:1040:1040)) - (PORT datac (712:712:712) (775:775:775)) - (PORT datad (738:738:738) (793:793:793)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1173:1173:1173)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1015:1015:1015)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (542:542:542)) - (PORT datab (979:979:979) (1050:1050:1050)) - (PORT datac (707:707:707) (769:769:769)) - (PORT datad (744:744:744) (801:801:801)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (375:375:375)) - (PORT datab (378:378:378) (404:404:404)) - (PORT datad (742:742:742) (802:802:802)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datac (920:920:920) (981:981:981)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (954:954:954) (1014:1014:1014)) - (PORT datac (182:182:182) (220:220:220)) + (PORT dataa (342:342:342) (379:379:379)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datad (849:849:849) (899:899:899)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT clk (1525:1525:1525) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (980:980:980) (984:984:984)) + (PORT asdata (583:583:583) (666:666:666)) + (PORT sload (1276:1276:1276) (1363:1363:1363)) + (PORT ena (1928:1928:1928) (1942:1942:1942)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1277:1277:1277) (1338:1338:1338)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2788:2788:2788) (2939:2939:2939)) - (PORT d[1] (2965:2965:2965) (3112:3112:3112)) - (PORT d[2] (1934:1934:1934) (2074:2074:2074)) - (PORT d[3] (2167:2167:2167) (2291:2291:2291)) - (PORT d[4] (2059:2059:2059) (2183:2183:2183)) - (PORT d[5] (1870:1870:1870) (1973:1973:1973)) - (PORT d[6] (2323:2323:2323) (2459:2459:2459)) - (PORT d[7] (1899:1899:1899) (1971:1971:1971)) - (PORT d[8] (3189:3189:3189) (3291:3291:3291)) - (PORT d[9] (2017:2017:2017) (2163:2163:2163)) - (PORT d[10] (3596:3596:3596) (3781:3781:3781)) - (PORT d[11] (2378:2378:2378) (2513:2513:2513)) - (PORT d[12] (1977:1977:1977) (2130:2130:2130)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1790:1790:1790) (1802:1802:1802)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3272:3272:3272) (3205:3205:3205)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1867:1867:1867) (1911:1911:1911)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4490:4490:4490) (4600:4600:4600)) - (PORT d[1] (4410:4410:4410) (4523:4523:4523)) - (PORT d[2] (4538:4538:4538) (4602:4602:4602)) - (PORT d[3] (4281:4281:4281) (4370:4370:4370)) - (PORT d[4] (4381:4381:4381) (4456:4456:4456)) - (PORT d[5] (4418:4418:4418) (4548:4548:4548)) - (PORT d[6] (4415:4415:4415) (4506:4506:4506)) - (PORT d[7] (4377:4377:4377) (4507:4507:4507)) - (PORT d[8] (4645:4645:4645) (4750:4750:4750)) - (PORT d[9] (4429:4429:4429) (4513:4513:4513)) - (PORT d[10] (4448:4448:4448) (4509:4509:4509)) - (PORT d[11] (4414:4414:4414) (4551:4551:4551)) - (PORT d[12] (4365:4365:4365) (4449:4449:4449)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~19) (DELAY (ABSOLUTE - (PORT datad (1452:1452:1452) (1517:1517:1517)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (288:288:288)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1252:1252:1252)) - (PORT datab (1269:1269:1269) (1318:1318:1318)) - (PORT datac (1435:1435:1435) (1491:1491:1491)) - (PORT datad (1131:1131:1131) (1204:1204:1204)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datac (796:796:796) (844:844:844)) + (PORT datad (2143:2143:2143) (2273:2273:2273)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1222:1222:1222) (1232:1232:1232)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3085:3085:3085) (3257:3257:3257)) - (PORT d[1] (2119:2119:2119) (2225:2225:2225)) - (PORT d[2] (1627:1627:1627) (1738:1738:1738)) - (PORT d[3] (1538:1538:1538) (1637:1637:1637)) - (PORT d[4] (2666:2666:2666) (2815:2815:2815)) - (PORT d[5] (1574:1574:1574) (1655:1655:1655)) - (PORT d[6] (2028:2028:2028) (2134:2134:2134)) - (PORT d[7] (1881:1881:1881) (1932:1932:1932)) - (PORT d[8] (3473:3473:3473) (3592:3592:3592)) - (PORT d[9] (1702:1702:1702) (1822:1822:1822)) - (PORT d[10] (1648:1648:1648) (1760:1760:1760)) - (PORT d[11] (1603:1603:1603) (1685:1685:1685)) - (PORT d[12] (1677:1677:1677) (1804:1804:1804)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1434:1434:1434) (1404:1404:1404)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (2896:2896:2896) (2932:2932:2932)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1800:1800:1800)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1527:1527:1527) (1568:1568:1568)) - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4450:4450:4450) (4537:4537:4537)) - (PORT d[1] (4347:4347:4347) (4424:4424:4424)) - (PORT d[2] (4406:4406:4406) (4467:4467:4467)) - (PORT d[3] (4294:4294:4294) (4374:4374:4374)) - (PORT d[4] (4350:4350:4350) (4425:4425:4425)) - (PORT d[5] (4369:4369:4369) (4474:4474:4474)) - (PORT d[6] (4390:4390:4390) (4426:4426:4426)) - (PORT d[7] (4335:4335:4335) (4462:4462:4462)) - (PORT d[8] (4444:4444:4444) (4576:4576:4576)) - (PORT d[9] (4472:4472:4472) (4577:4577:4577)) - (PORT d[10] (4487:4487:4487) (4606:4606:4606)) - (PORT d[11] (4466:4466:4466) (4582:4582:4582)) - (PORT d[12] (4367:4367:4367) (4452:4452:4452)) - (PORT clk (1807:1807:1807) (1802:1802:1802)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3185:3185:3185) (3417:3417:3417)) - (PORT d[1] (3332:3332:3332) (3484:3484:3484)) - (PORT d[2] (1430:1430:1430) (1497:1497:1497)) - (PORT d[3] (3934:3934:3934) (4092:4092:4092)) - (PORT d[4] (2918:2918:2918) (3104:3104:3104)) - (PORT d[5] (4421:4421:4421) (4553:4553:4553)) - (PORT d[6] (2796:2796:2796) (2911:2911:2911)) - (PORT d[7] (1726:1726:1726) (1774:1774:1774)) - (PORT d[8] (1980:1980:1980) (2009:2009:2009)) - (PORT d[9] (2141:2141:2141) (2210:2210:2210)) - (PORT d[10] (2312:2312:2312) (2391:2391:2391)) - (PORT d[11] (3101:3101:3101) (3331:3331:3331)) - (PORT d[12] (4277:4277:4277) (4540:4540:4540)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (1940:1940:1940) (1958:1958:1958)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~47) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) (DELAY (ABSOLUTE - (PORT dataa (926:926:926) (1021:1021:1021)) - (PORT datab (305:305:305) (397:397:397)) - (PORT datac (887:887:887) (916:916:916)) - (PORT datad (1045:1045:1045) (1066:1066:1066)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1950:1950:1950) (2052:2052:2052)) - (PORT d[1] (2560:2560:2560) (2687:2687:2687)) - (PORT d[2] (2359:2359:2359) (2509:2509:2509)) - (PORT d[3] (3005:3005:3005) (3111:3111:3111)) - (PORT d[4] (2278:2278:2278) (2362:2362:2362)) - (PORT d[5] (3097:3097:3097) (3185:3185:3185)) - (PORT d[6] (2841:2841:2841) (2965:2965:2965)) - (PORT d[7] (3148:3148:3148) (3225:3225:3225)) - (PORT d[8] (2385:2385:2385) (2466:2466:2466)) - (PORT d[9] (3043:3043:3043) (3176:3176:3176)) - (PORT d[10] (2289:2289:2289) (2338:2338:2338)) - (PORT d[11] (2469:2469:2469) (2631:2631:2631)) - (PORT d[12] (3226:3226:3226) (3408:3408:3408)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2959:2959:2959) (2871:2871:2871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1122:1122:1122)) - (PORT datab (1468:1468:1468) (1531:1531:1531)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1667:1667:1667) (1758:1758:1758)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (807:807:807) (834:834:834)) + (PORT datab (363:363:363) (396:396:396)) + (PORT datad (584:584:584) (598:598:598)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1231:1231:1231)) - (PORT datab (307:307:307) (400:400:400)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1483:1483:1483)) - (PORT datab (2298:2298:2298) (2535:2535:2535)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1308:1308:1308)) - (PORT datab (635:635:635) (668:668:668)) - (PORT datac (844:844:844) (889:889:889)) - (PORT datad (327:327:327) (350:350:350)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2195:2195:2195) (2276:2276:2276)) - (PORT datab (637:637:637) (668:668:668)) - (PORT datac (1697:1697:1697) (1792:1792:1792)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (1431:1431:1431) (1450:1450:1450)) - (PORT datac (1093:1093:1093) (1122:1122:1122)) - (PORT datad (344:344:344) (358:358:358)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1131:1131:1131) (1163:1163:1163)) - (PORT datab (1474:1474:1474) (1564:1564:1564)) - (PORT datac (2114:2114:2114) (2227:2227:2227)) - (PORT datad (1651:1651:1651) (1831:1831:1831)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1762:1762:1762)) - (PORT datab (537:537:537) (564:564:564)) - (PORT datac (1014:1014:1014) (1023:1023:1023)) - (PORT datad (1124:1124:1124) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) + (PORT asdata (1216:1216:1216) (1271:1271:1271)) + (PORT sload (1742:1742:1742) (1823:1823:1823)) + (PORT ena (1431:1431:1431) (1435:1435:1435)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1166:1166:1166)) - (PORT datab (245:245:245) (289:289:289)) - (PORT datac (847:847:847) (855:855:855)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (253:253:253)) - (PORT datac (1091:1091:1091) (1119:1119:1119)) - (PORT datad (224:224:224) (259:259:259)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (470:470:470)) - (PORT datab (253:253:253) (303:303:303)) - (PORT datac (340:340:340) (362:362:362)) - (PORT datad (217:217:217) (254:254:254)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (621:621:621) (634:634:634)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1207:1207:1207)) - (PORT datab (2915:2915:2915) (2999:2999:2999)) - (PORT datac (1369:1369:1369) (1427:1427:1427)) - (PORT datad (800:800:800) (850:850:850)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1568:1568:1568)) - (PORT ena (2213:2213:2213) (2213:2213:2213)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1858:1858:1858) (1939:1939:1939)) - (PORT datab (1661:1661:1661) (1809:1809:1809)) - (PORT datac (1723:1723:1723) (1805:1805:1805)) - (PORT datad (882:882:882) (900:900:900)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (711:711:711)) - (PORT datab (826:826:826) (874:874:874)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (611:611:611) (623:623:623)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (958:958:958)) - (PORT datab (1170:1170:1170) (1229:1229:1229)) - (PORT datac (1138:1138:1138) (1178:1178:1178)) - (PORT datad (1161:1161:1161) (1197:1197:1197)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (377:377:377)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (867:867:867) (893:893:893)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (892:892:892)) - (PORT datac (794:794:794) (839:839:839)) - (PORT datad (815:815:815) (833:833:833)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (954:954:954)) - (PORT datab (902:902:902) (931:931:931)) - (PORT datac (806:806:806) (822:822:822)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (639:639:639)) - (PORT datab (1166:1166:1166) (1208:1208:1208)) - (PORT datac (909:909:909) (953:953:953)) - (PORT datad (585:585:585) (613:613:613)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1349:1349:1349) (1369:1369:1369)) - (PORT datac (628:628:628) (663:663:663)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (884:884:884)) - (PORT datab (668:668:668) (707:707:707)) - (PORT datac (825:825:825) (860:860:860)) - (PORT datad (819:819:819) (837:837:837)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (855:855:855)) - (PORT datac (354:354:354) (381:381:381)) - (PORT datad (849:849:849) (871:871:871)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (950:950:950)) - (PORT datab (637:637:637) (657:657:657)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (594:594:594) (606:606:606)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1160:1160:1160)) - (PORT datab (246:246:246) (293:293:293)) - (PORT datad (1182:1182:1182) (1220:1220:1220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1316:1316:1316) (1375:1375:1375)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2397:2397:2397) (2589:2589:2589)) - (PORT d[1] (2605:2605:2605) (2682:2682:2682)) - (PORT d[2] (1244:1244:1244) (1312:1312:1312)) - (PORT d[3] (1263:1263:1263) (1323:1323:1323)) - (PORT d[4] (2021:2021:2021) (2110:2110:2110)) - (PORT d[5] (1254:1254:1254) (1323:1323:1323)) - (PORT d[6] (1478:1478:1478) (1511:1511:1511)) - (PORT d[7] (2356:2356:2356) (2492:2492:2492)) - (PORT d[8] (2505:2505:2505) (2668:2668:2668)) - (PORT d[9] (775:775:775) (840:840:840)) - (PORT d[10] (1752:1752:1752) (1831:1831:1831)) - (PORT d[11] (1174:1174:1174) (1217:1217:1217)) - (PORT d[12] (728:728:728) (783:783:783)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1797:1797:1797) (1781:1781:1781)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (1825:1825:1825) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (961:961:961) (961:961:961)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2420:2420:2420) (2630:2630:2630)) - (PORT d[1] (1241:1241:1241) (1313:1313:1313)) - (PORT d[2] (1662:1662:1662) (1741:1741:1741)) - (PORT d[3] (1596:1596:1596) (1691:1691:1691)) - (PORT d[4] (2978:2978:2978) (3155:3155:3155)) - (PORT d[5] (1264:1264:1264) (1317:1317:1317)) - (PORT d[6] (1560:1560:1560) (1657:1657:1657)) - (PORT d[7] (1291:1291:1291) (1338:1338:1338)) - (PORT d[8] (1256:1256:1256) (1319:1319:1319)) - (PORT d[9] (1080:1080:1080) (1170:1170:1170)) - (PORT d[10] (1071:1071:1071) (1158:1158:1158)) - (PORT d[11] (2213:2213:2213) (2338:2338:2338)) - (PORT d[12] (1088:1088:1088) (1179:1179:1179)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1220:1220:1220) (1163:1163:1163)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2327:2327:2327) (2302:2302:2302)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1310:1310:1310) (1368:1368:1368)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2700:2700:2700) (2899:2899:2899)) - (PORT d[1] (2882:2882:2882) (2995:2995:2995)) - (PORT d[2] (1236:1236:1236) (1287:1287:1287)) - (PORT d[3] (979:979:979) (1033:1033:1033)) - (PORT d[4] (2053:2053:2053) (2138:2138:2138)) - (PORT d[5] (951:951:951) (1003:1003:1003)) - (PORT d[6] (1440:1440:1440) (1451:1451:1451)) - (PORT d[7] (2650:2650:2650) (2803:2803:2803)) - (PORT d[8] (2518:2518:2518) (2699:2699:2699)) - (PORT d[9] (743:743:743) (798:798:798)) - (PORT d[10] (755:755:755) (811:811:811)) - (PORT d[11] (2821:2821:2821) (3003:3003:3003)) - (PORT d[12] (715:715:715) (752:752:752)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1241:1241:1241) (1217:1217:1217)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1869:1869:1869)) - (PORT d[0] (1450:1450:1450) (1417:1417:1417)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1828:1828:1828)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (986:986:986) (991:991:991)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (677:677:677) (699:699:699)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2669:2669:2669) (2901:2901:2901)) - (PORT d[1] (1288:1288:1288) (1360:1360:1360)) - (PORT d[2] (1665:1665:1665) (1743:1743:1743)) - (PORT d[3] (1565:1565:1565) (1640:1640:1640)) - (PORT d[4] (2970:2970:2970) (3148:3148:3148)) - (PORT d[5] (1271:1271:1271) (1329:1329:1329)) - (PORT d[6] (1509:1509:1509) (1602:1602:1602)) - (PORT d[7] (1615:1615:1615) (1649:1649:1649)) - (PORT d[8] (1553:1553:1553) (1653:1653:1653)) - (PORT d[9] (1383:1383:1383) (1478:1478:1478)) - (PORT d[10] (1335:1335:1335) (1424:1424:1424)) - (PORT d[11] (1876:1876:1876) (1999:1999:1999)) - (PORT d[12] (1381:1381:1381) (1486:1486:1486)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1214:1214:1214)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2701:2701:2701) (2725:2725:2725)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1532:1532:1532)) - (PORT datab (1228:1228:1228) (1286:1286:1286)) - (PORT datad (1444:1444:1444) (1432:1432:1432)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1583:1583:1583)) - (PORT datab (1831:1831:1831) (1977:1977:1977)) - (PORT datac (1437:1437:1437) (1482:1482:1482)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1260:1260:1260) (1277:1277:1277)) - (PORT clk (1852:1852:1852) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2793:2793:2793) (2950:2950:2950)) - (PORT d[1] (1830:1830:1830) (1942:1942:1942)) - (PORT d[2] (1907:1907:1907) (2035:2035:2035)) - (PORT d[3] (2153:2153:2153) (2289:2289:2289)) - (PORT d[4] (2370:2370:2370) (2502:2502:2502)) - (PORT d[5] (1869:1869:1869) (1972:1972:1972)) - (PORT d[6] (2343:2343:2343) (2464:2464:2464)) - (PORT d[7] (2215:2215:2215) (2277:2277:2277)) - (PORT d[8] (3168:3168:3168) (3268:3268:3268)) - (PORT d[9] (1739:1739:1739) (1883:1883:1883)) - (PORT d[10] (1634:1634:1634) (1763:1763:1763)) - (PORT d[11] (2386:2386:2386) (2535:2535:2535)) - (PORT d[12] (2455:2455:2455) (2610:2610:2610)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1782:1782:1782) (1793:1793:1793)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (PORT d[0] (3271:3271:3271) (3211:3211:3211)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1805:1805:1805)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1887:1887:1887) (1934:1934:1934)) - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4443:4443:4443) (4548:4548:4548)) - (PORT d[1] (4421:4421:4421) (4559:4559:4559)) - (PORT d[2] (4547:4547:4547) (4625:4625:4625)) - (PORT d[3] (4250:4250:4250) (4323:4323:4323)) - (PORT d[4] (4357:4357:4357) (4435:4435:4435)) - (PORT d[5] (4381:4381:4381) (4503:4503:4503)) - (PORT d[6] (4351:4351:4351) (4470:4470:4470)) - (PORT d[7] (4377:4377:4377) (4506:4506:4506)) - (PORT d[8] (4630:4630:4630) (4748:4748:4748)) - (PORT d[9] (4422:4422:4422) (4527:4527:4527)) - (PORT d[10] (4416:4416:4416) (4515:4515:4515)) - (PORT d[11] (4442:4442:4442) (4583:4583:4583)) - (PORT d[12] (4386:4386:4386) (4473:4473:4473)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1807:1807:1807)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1270:1270:1270)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2794:2794:2794) (2951:2951:2951)) - (PORT d[1] (1828:1828:1828) (1938:1938:1938)) - (PORT d[2] (2259:2259:2259) (2395:2395:2395)) - (PORT d[3] (2157:2157:2157) (2295:2295:2295)) - (PORT d[4] (2357:2357:2357) (2500:2500:2500)) - (PORT d[5] (1865:1865:1865) (1964:1964:1964)) - (PORT d[6] (1845:1845:1845) (1965:1965:1965)) - (PORT d[7] (1871:1871:1871) (1918:1918:1918)) - (PORT d[8] (3142:3142:3142) (3254:3254:3254)) - (PORT d[9] (1716:1716:1716) (1858:1858:1858)) - (PORT d[10] (3925:3925:3925) (4111:4111:4111)) - (PORT d[11] (2389:2389:2389) (2540:2540:2540)) - (PORT d[12] (1686:1686:1686) (1819:1819:1819)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1704:1704:1704) (1656:1656:1656)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (2935:2935:2935) (2984:2984:2984)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1853:1853:1853) (1917:1917:1917)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4455:4455:4455) (4544:4544:4544)) - (PORT d[1] (4366:4366:4366) (4482:4482:4482)) - (PORT d[2] (4416:4416:4416) (4497:4497:4497)) - (PORT d[3] (4264:4264:4264) (4327:4327:4327)) - (PORT d[4] (4354:4354:4354) (4419:4419:4419)) - (PORT d[5] (4403:4403:4403) (4526:4526:4526)) - (PORT d[6] (4425:4425:4425) (4522:4522:4522)) - (PORT d[7] (4346:4346:4346) (4468:4468:4468)) - (PORT d[8] (4655:4655:4655) (4776:4776:4776)) - (PORT d[9] (4485:4485:4485) (4573:4573:4573)) - (PORT d[10] (4462:4462:4462) (4577:4577:4577)) - (PORT d[11] (4470:4470:4470) (4590:4590:4590)) - (PORT d[12] (4386:4386:4386) (4471:4471:4471)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2492:2492:2492) (2622:2622:2622)) - (PORT d[1] (2647:2647:2647) (2790:2790:2790)) - (PORT d[2] (2231:2231:2231) (2391:2391:2391)) - (PORT d[3] (2097:2097:2097) (2237:2237:2237)) - (PORT d[4] (1753:1753:1753) (1859:1859:1859)) - (PORT d[5] (2146:2146:2146) (2271:2271:2271)) - (PORT d[6] (2408:2408:2408) (2553:2553:2553)) - (PORT d[7] (3417:3417:3417) (3493:3493:3493)) - (PORT d[8] (2875:2875:2875) (2972:2972:2972)) - (PORT d[9] (2055:2055:2055) (2224:2224:2224)) - (PORT d[10] (1917:1917:1917) (2062:2062:2062)) - (PORT d[11] (2114:2114:2114) (2235:2235:2235)) - (PORT d[12] (2265:2265:2265) (2423:2423:2423)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2593:2593:2593) (2672:2672:2672)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1225:1225:1225)) - (PORT datab (307:307:307) (399:399:399)) - (PORT datac (1148:1148:1148) (1222:1222:1222)) - (PORT datad (1447:1447:1447) (1525:1525:1525)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1960:1960:1960) (2070:2070:2070)) - (PORT d[1] (3002:3002:3002) (3172:3172:3172)) - (PORT d[2] (2265:2265:2265) (2363:2363:2363)) - (PORT d[3] (3641:3641:3641) (3796:3796:3796)) - (PORT d[4] (2594:2594:2594) (2773:2773:2773)) - (PORT d[5] (4146:4146:4146) (4262:4262:4262)) - (PORT d[6] (2765:2765:2765) (2873:2873:2873)) - (PORT d[7] (3716:3716:3716) (3795:3795:3795)) - (PORT d[8] (2020:2020:2020) (2071:2071:2071)) - (PORT d[9] (2145:2145:2145) (2236:2236:2236)) - (PORT d[10] (2368:2368:2368) (2463:2463:2463)) - (PORT d[11] (2810:2810:2810) (2995:2995:2995)) - (PORT d[12] (3841:3841:3841) (4091:4091:4091)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) - (PORT d[0] (2266:2266:2266) (2242:2242:2242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1342:1342:1342)) - (PORT datab (1229:1229:1229) (1288:1288:1288)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1047:1047:1047) (1066:1066:1066)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1237:1237:1237)) - (PORT datab (309:309:309) (401:401:401)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1483:1483:1483)) - (PORT datab (2298:2298:2298) (2535:2535:2535)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~99) - (DELAY - (ABSOLUTE - (PORT datab (1221:1221:1221) (1330:1330:1330)) - (PORT datac (2534:2534:2534) (2774:2774:2774)) - (PORT datad (1462:1462:1462) (1583:1583:1583)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (1558:1558:1558) (1597:1597:1597)) - (PORT datab (435:435:435) (477:477:477)) - (PORT datac (597:597:597) (599:599:599)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (2243:2243:2243) (2321:2321:2321)) - (PORT datab (436:436:436) (477:477:477)) - (PORT datac (1209:1209:1209) (1322:1322:1322)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (1886:1886:1886) (1930:1930:1930)) - (PORT datab (426:426:426) (464:464:464)) - (PORT datac (349:349:349) (377:377:377)) - (PORT datad (1129:1129:1129) (1163:1163:1163)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (252:252:252) (303:303:303)) - (PORT datac (575:575:575) (628:628:628)) - (PORT datad (216:216:216) (251:251:251)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (694:694:694) (717:717:717)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (INSTANCE z80_\|address_pins_\|abus\[11\]\~18) (DELAY (ABSOLUTE - (PORT dataa (779:779:779) (847:847:847)) - (PORT datac (1845:1845:1845) (1972:1972:1972)) - (PORT datad (1691:1691:1691) (1766:1766:1766)) - (IOPATH dataa combout (303:303:303) (308:308:308)) + (PORT datab (651:651:651) (725:725:725)) + (PORT datac (1094:1094:1094) (1213:1213:1213)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) (DELAY (ABSOLUTE - (PORT dataa (1757:1757:1757) (1850:1850:1850)) - (PORT datab (1655:1655:1655) (1806:1806:1806)) - (PORT datac (1039:1039:1039) (1104:1104:1104)) - (PORT datad (1816:1816:1816) (1892:1892:1892)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (608:608:608)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (614:614:614) (677:677:677)) - (PORT datad (1147:1147:1147) (1181:1181:1181)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1698:1698:1698)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (366:366:366) (433:433:433)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (760:760:760) (855:855:855)) - (PORT datad (307:307:307) (414:414:414)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (806:806:806) (835:835:835)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datad (589:589:589) (604:604:604)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1526:1526:1526) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1224:1224:1224) (1228:1228:1228)) + (PORT asdata (1176:1176:1176) (1236:1236:1236)) + (PORT sload (1742:1742:1742) (1823:1823:1823)) + (PORT ena (1431:1431:1431) (1435:1435:1435)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (883:883:883)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (1149:1149:1149) (1212:1212:1212)) - (PORT datad (1552:1552:1552) (1679:1679:1679)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1560:1560:1560) (1552:1552:1552)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1861:1861:1861) (1999:1999:1999)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (PORT ena (993:993:993) (1000:1000:1000)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (459:459:459)) - (PORT datab (294:294:294) (388:388:388)) - (PORT datad (252:252:252) (326:326:326)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2306:2306:2306) (2453:2453:2453)) - (PORT datab (1239:1239:1239) (1285:1285:1285)) - (PORT datac (1152:1152:1152) (1203:1203:1203)) - (PORT datad (1219:1219:1219) (1229:1229:1229)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (703:703:703) (722:722:722)) - (PORT datad (905:905:905) (936:936:936)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1544:1544:1544) (1649:1649:1649)) - (PORT datab (634:634:634) (661:661:661)) - (PORT datac (1250:1250:1250) (1279:1279:1279)) - (PORT datad (632:632:632) (654:654:654)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datac (1378:1378:1378) (1490:1490:1490)) + (PORT datad (237:237:237) (304:304:304)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (270:270:270)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (590:590:590) (610:610:610)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (949:949:949)) - (PORT datab (631:631:631) (656:656:656)) - (PORT datac (835:835:835) (860:860:860)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (935:935:935)) - (PORT datab (1457:1457:1457) (1548:1548:1548)) - (PORT datac (589:589:589) (657:657:657)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (716:716:716)) - (PORT datab (861:861:861) (893:893:893)) - (PORT datac (854:854:854) (895:895:895)) - (PORT datad (1006:1006:1006) (1056:1056:1056)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1204:1204:1204)) - (PORT datab (1249:1249:1249) (1294:1294:1294)) - (PORT datac (1289:1289:1289) (1340:1340:1340)) - (PORT datad (1967:1967:1967) (2036:2036:2036)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (945:945:945)) - (PORT datab (1896:1896:1896) (1915:1915:1915)) - (PORT datac (1165:1165:1165) (1201:1201:1201)) - (PORT datad (827:827:827) (850:850:850)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (492:492:492)) - (PORT datab (1030:1030:1030) (1095:1095:1095)) - (PORT datac (1325:1325:1325) (1379:1379:1379)) - (PORT datad (1076:1076:1076) (1126:1126:1126)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (677:677:677)) - (PORT datab (1463:1463:1463) (1517:1517:1517)) - (PORT datac (1482:1482:1482) (1554:1554:1554)) - (PORT datad (1619:1619:1619) (1692:1692:1692)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (2969:2969:2969) (3039:3039:3039)) - (PORT datab (641:641:641) (702:702:702)) - (PORT datac (613:613:613) (625:625:625)) - (PORT datad (215:215:215) (241:241:241)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (478:478:478)) - (PORT datab (895:895:895) (922:922:922)) - (PORT datac (1121:1121:1121) (1142:1142:1142)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (645:645:645)) - (PORT datab (644:644:644) (686:686:686)) - (PORT datac (188:188:188) (228:228:228)) - (PORT datad (1149:1149:1149) (1174:1174:1174)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1207:1207:1207)) - (PORT datab (916:916:916) (951:951:951)) - (PORT datac (188:188:188) (231:231:231)) - (PORT datad (1147:1147:1147) (1187:1187:1187)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (921:921:921)) - (PORT datab (1617:1617:1617) (1648:1648:1648)) - (PORT datac (1115:1115:1115) (1177:1177:1177)) - (PORT datad (1411:1411:1411) (1437:1437:1437)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (886:886:886) (911:911:911)) - (PORT datac (648:648:648) (694:694:694)) - (PORT datad (1181:1181:1181) (1217:1217:1217)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (944:944:944)) - (PORT datab (1282:1282:1282) (1314:1314:1314)) - (PORT datac (648:648:648) (693:693:693)) - (PORT datad (1402:1402:1402) (1434:1434:1434)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1502:1502:1502)) - (PORT datab (1085:1085:1085) (1133:1133:1133)) - (PORT datac (651:651:651) (687:687:687)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1015:1015:1015)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (654:654:654) (703:703:703)) - (PORT datac (610:610:610) (654:654:654)) - (PORT datad (624:624:624) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1183:1183:1183)) - (PORT datab (954:954:954) (995:995:995)) - (PORT datac (602:602:602) (625:625:625)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (952:952:952)) - (PORT datab (673:673:673) (691:691:691)) - (PORT datac (958:958:958) (973:973:973)) - (PORT datad (1082:1082:1082) (1103:1103:1103)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (1455:1455:1455) (1545:1545:1545)) - (PORT datac (1016:1016:1016) (1022:1022:1022)) - (PORT datad (509:509:509) (525:525:525)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (577:577:577)) - (PORT datac (977:977:977) (1064:1064:1064)) - (PORT datad (614:614:614) (684:684:684)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (774:774:774) (853:853:853)) - (PORT datac (679:679:679) (730:730:730)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (431:431:431)) - (PORT datab (763:763:763) (849:849:849)) - (PORT datac (702:702:702) (763:763:763)) - (PORT datad (193:193:193) (229:229:229)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (870:870:870)) - (PORT datab (200:200:200) (238:238:238)) - (PORT datad (591:591:591) (603:603:603)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (820:820:820)) - (PORT datac (935:935:935) (1021:1021:1021)) - (PORT datad (904:904:904) (975:975:975)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (879:879:879)) - (PORT datab (652:652:652) (684:684:684)) - (PORT datac (896:896:896) (981:981:981)) - (PORT datad (267:267:267) (345:345:345)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (376:376:376)) - (PORT datab (931:931:931) (1011:1011:1011)) - (PORT datac (928:928:928) (989:989:989)) - (PORT datad (753:753:753) (839:839:839)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (1020:1020:1020)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) - (DELAY - (ABSOLUTE - (PORT datab (789:789:789) (873:873:873)) - (PORT datac (683:683:683) (751:751:751)) - (PORT datad (735:735:735) (817:817:817)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (412:412:412)) - (PORT datab (740:740:740) (807:807:807)) - (PORT datac (888:888:888) (952:952:952)) - (PORT datad (199:199:199) (235:235:235)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (399:399:399)) - (PORT datab (624:624:624) (685:685:685)) - (PORT datac (677:677:677) (727:727:727)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (870:870:870)) - (PORT datab (416:416:416) (496:496:496)) - (PORT datad (936:936:936) (1016:1016:1016)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1227:1227:1227) (1254:1254:1254)) - (PORT datab (632:632:632) (647:647:647)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1342:1342:1342)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datac (882:882:882) (907:907:907)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1137:1137:1137)) - (PORT datac (848:848:848) (867:867:867)) - (PORT datad (708:708:708) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT datab (740:740:740) (830:830:830)) - (PORT datac (1262:1262:1262) (1334:1334:1334)) - (PORT datad (969:969:969) (1032:1032:1032)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1060:1060:1060) (1130:1130:1130)) - (PORT datac (759:759:759) (838:838:838)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (303:303:303) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (855:855:855)) - (PORT datac (971:971:971) (1051:1051:1051)) - (PORT datad (645:645:645) (724:724:724)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (948:948:948)) - (PORT datab (888:888:888) (920:920:920)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (395:395:395)) - (PORT datab (1062:1062:1062) (1131:1131:1131)) - (PORT datac (708:708:708) (773:773:773)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1087:1087:1087)) - (PORT datab (920:920:920) (962:962:962)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1513:1513:1513) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1548:1548:1548) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1214:1214:1214)) - (PORT datab (714:714:714) (771:771:771)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1236:1236:1236) (1327:1327:1327)) - (PORT datac (984:984:984) (1047:1047:1047)) - (PORT datad (651:651:651) (732:732:732)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (705:705:705) (774:774:774)) - (PORT datad (204:204:204) (235:235:235)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (923:923:923) (952:952:952)) - (PORT datad (573:573:573) (604:604:604)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1138:1138:1138)) - (PORT datab (420:420:420) (502:502:502)) - (PORT datac (998:998:998) (1056:1056:1056)) - (PORT datad (603:603:603) (663:663:663)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (404:404:404)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (665:665:665) (729:729:729)) - (PORT datad (635:635:635) (652:652:652)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (907:907:907)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (711:711:711) (785:785:785)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (663:663:663)) - (PORT datab (759:759:759) (844:844:844)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (909:909:909) (965:965:965)) - (PORT datac (217:217:217) (293:293:293)) - (PORT datad (1398:1398:1398) (1439:1439:1439)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1327:1327:1327)) - (PORT datab (1300:1300:1300) (1375:1375:1375)) - (PORT datac (685:685:685) (784:784:784)) - (PORT datad (717:717:717) (806:806:806)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1326:1326:1326)) - (PORT datac (985:985:985) (1050:1050:1050)) - (PORT datad (653:653:653) (736:736:736)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1125:1125:1125)) - (PORT datab (948:948:948) (1016:1016:1016)) - (PORT datac (900:900:900) (914:914:914)) - (PORT datad (729:729:729) (803:803:803)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (619:619:619) (630:630:630)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (588:588:588)) - (PORT datab (887:887:887) (942:942:942)) - (PORT datac (616:616:616) (637:637:637)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (973:973:973) (1052:1052:1052)) - (PORT datad (462:462:462) (533:533:533)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (751:751:751)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datac (2427:2427:2427) (2603:2603:2603)) - (PORT datad (882:882:882) (935:935:935)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (920:920:920)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (344:344:344) (365:365:365)) - (PORT datad (615:615:615) (626:626:626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1131:1131:1131)) - (PORT datab (1259:1259:1259) (1374:1374:1374)) - (PORT datac (2575:2575:2575) (2806:2806:2806)) - (PORT datad (635:635:635) (671:671:671)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1113:1113:1113)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2540:2540:2540) (2718:2718:2718)) - (PORT d[1] (3611:3611:3611) (3828:3828:3828)) - (PORT d[2] (2390:2390:2390) (2485:2485:2485)) - (PORT d[3] (4294:4294:4294) (4502:4502:4502)) - (PORT d[4] (3192:3192:3192) (3431:3431:3431)) - (PORT d[5] (4755:4755:4755) (4922:4922:4922)) - (PORT d[6] (2539:2539:2539) (2642:2642:2642)) - (PORT d[7] (1407:1407:1407) (1444:1444:1444)) - (PORT d[8] (2834:2834:2834) (2992:2992:2992)) - (PORT d[9] (1811:1811:1811) (1840:1840:1840)) - (PORT d[10] (1723:1723:1723) (1759:1759:1759)) - (PORT d[11] (3413:3413:3413) (3683:3683:3683)) - (PORT d[12] (4600:4600:4600) (4890:4890:4890)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1678:1678:1678) (1622:1622:1622)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2247:2247:2247) (2230:2230:2230)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1276:1276:1276)) - (PORT datab (667:667:667) (705:705:705)) - (PORT datac (1386:1386:1386) (1467:1467:1467)) - (PORT datad (1101:1101:1101) (1113:1113:1113)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1145:1145:1145) (1137:1137:1137)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1692:1692:1692) (1821:1821:1821)) - (PORT d[1] (2831:2831:2831) (2904:2904:2904)) - (PORT d[2] (2412:2412:2412) (2479:2479:2479)) - (PORT d[3] (4272:4272:4272) (4479:4479:4479)) - (PORT d[4] (990:990:990) (1023:1023:1023)) - (PORT d[5] (2242:2242:2242) (2271:2271:2271)) - (PORT d[6] (2540:2540:2540) (2643:2643:2643)) - (PORT d[7] (1371:1371:1371) (1386:1386:1386)) - (PORT d[8] (2806:2806:2806) (2960:2960:2960)) - (PORT d[9] (1487:1487:1487) (1517:1517:1517)) - (PORT d[10] (1989:1989:1989) (2026:2026:2026)) - (PORT d[11] (3414:3414:3414) (3684:3684:3684)) - (PORT d[12] (4681:4681:4681) (4989:4989:4989)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2538:2538:2538) (2548:2548:2548)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (2226:2226:2226) (2231:2231:2231)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (743:743:743) (772:772:772)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3064:3064:3064) (3319:3319:3319)) - (PORT d[1] (1624:1624:1624) (1726:1726:1726)) - (PORT d[2] (1003:1003:1003) (1056:1056:1056)) - (PORT d[3] (954:954:954) (1004:1004:1004)) - (PORT d[4] (3267:3267:3267) (3445:3445:3445)) - (PORT d[5] (969:969:969) (999:999:999)) - (PORT d[6] (1577:1577:1577) (1697:1697:1697)) - (PORT d[7] (987:987:987) (1009:1009:1009)) - (PORT d[8] (1275:1275:1275) (1343:1343:1343)) - (PORT d[9] (1064:1064:1064) (1130:1130:1130)) - (PORT d[10] (1030:1030:1030) (1088:1088:1088)) - (PORT d[11] (2187:2187:2187) (2344:2344:2344)) - (PORT d[12] (1076:1076:1076) (1160:1160:1160)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (956:956:956) (917:917:917)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2993:2993:2993) (3045:3045:3045)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (997:997:997) (1025:1025:1025)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3012:3012:3012) (3251:3251:3251)) - (PORT d[1] (1609:1609:1609) (1697:1697:1697)) - (PORT d[2] (983:983:983) (1016:1016:1016)) - (PORT d[3] (961:961:961) (994:994:994)) - (PORT d[4] (1434:1434:1434) (1457:1457:1457)) - (PORT d[5] (948:948:948) (977:977:977)) - (PORT d[6] (1862:1862:1862) (1998:1998:1998)) - (PORT d[7] (940:940:940) (959:959:959)) - (PORT d[8] (1274:1274:1274) (1339:1339:1339)) - (PORT d[9] (752:752:752) (813:813:813)) - (PORT d[10] (755:755:755) (815:815:815)) - (PORT d[11] (2517:2517:2517) (2676:2676:2676)) - (PORT d[12] (773:773:773) (837:837:837)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (682:682:682) (624:624:624)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (1782:1782:1782) (1777:1777:1777)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2263:2263:2263) (2427:2427:2427)) - (PORT d[1] (2806:2806:2806) (2855:2855:2855)) - (PORT d[2] (2405:2405:2405) (2483:2483:2483)) - (PORT d[3] (4558:4558:4558) (4765:4765:4765)) - (PORT d[4] (1002:1002:1002) (1050:1050:1050)) - (PORT d[5] (2195:2195:2195) (2238:2238:2238)) - (PORT d[6] (924:924:924) (944:944:944)) - (PORT d[7] (1330:1330:1330) (1332:1332:1332)) - (PORT d[8] (2826:2826:2826) (2976:2976:2976)) - (PORT d[9] (1473:1473:1473) (1523:1523:1523)) - (PORT d[10] (1998:1998:1998) (2047:2047:2047)) - (PORT d[11] (3718:3718:3718) (4008:4008:4008)) - (PORT d[12] (4709:4709:4709) (5022:5022:5022)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (1305:1305:1305) (1337:1337:1337)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1966:1966:1966) (2027:2027:2027)) - (PORT datab (1520:1520:1520) (1598:1598:1598)) - (PORT datac (885:885:885) (908:908:908)) - (PORT datad (1061:1061:1061) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (915:915:915) (934:934:934)) - (PORT datac (1386:1386:1386) (1466:1466:1466)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1589:1589:1589)) - (PORT datab (1130:1130:1130) (1152:1152:1152)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1801:1801:1801) (1899:1899:1899)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1489:1489:1489)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2489:2489:2489) (2600:2600:2600)) - (PORT d[1] (2698:2698:2698) (2838:2838:2838)) - (PORT d[2] (2572:2572:2572) (2698:2698:2698)) - (PORT d[3] (3356:3356:3356) (3488:3488:3488)) - (PORT d[4] (2297:2297:2297) (2449:2449:2449)) - (PORT d[5] (3794:3794:3794) (3901:3901:3901)) - (PORT d[6] (2564:2564:2564) (2676:2676:2676)) - (PORT d[7] (3403:3403:3403) (3457:3457:3457)) - (PORT d[8] (2931:2931:2931) (3032:3032:3032)) - (PORT d[9] (2737:2737:2737) (2834:2834:2834)) - (PORT d[10] (2604:2604:2604) (2714:2714:2714)) - (PORT d[11] (2512:2512:2512) (2702:2702:2702)) - (PORT d[12] (3523:3523:3523) (3743:3743:3743)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2846:2846:2846) (2893:2893:2893)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (3535:3535:3535) (3484:3484:3484)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2458:2458:2458) (2451:2451:2451)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4479:4479:4479) (4514:4514:4514)) - (PORT d[1] (4465:4465:4465) (4517:4517:4517)) - (PORT d[2] (4544:4544:4544) (4551:4551:4551)) - (PORT d[3] (4403:4403:4403) (4415:4415:4415)) - (PORT d[4] (4292:4292:4292) (4432:4432:4432)) - (PORT d[5] (4375:4375:4375) (4440:4440:4440)) - (PORT d[6] (4446:4446:4446) (4486:4486:4486)) - (PORT d[7] (4358:4358:4358) (4399:4399:4399)) - (PORT d[8] (4409:4409:4409) (4489:4489:4489)) - (PORT d[9] (4419:4419:4419) (4498:4498:4498)) - (PORT d[10] (4270:4270:4270) (4305:4305:4305)) - (PORT d[11] (4393:4393:4393) (4493:4493:4493)) - (PORT d[12] (4247:4247:4247) (4253:4253:4253)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (2618:2618:2618) (2852:2852:2852)) - (PORT datab (2469:2469:2469) (2595:2595:2595)) - (PORT datac (1575:1575:1575) (1686:1686:1686)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1395:1395:1395) (1438:1438:1438)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1950:1950:1950) (2069:2069:2069)) - (PORT d[1] (3022:3022:3022) (3167:3167:3167)) - (PORT d[2] (1806:1806:1806) (1910:1910:1910)) - (PORT d[3] (3658:3658:3658) (3808:3808:3808)) - (PORT d[4] (2619:2619:2619) (2778:2778:2778)) - (PORT d[5] (4118:4118:4118) (4230:4230:4230)) - (PORT d[6] (2735:2735:2735) (2827:2827:2827)) - (PORT d[7] (1984:1984:1984) (2046:2046:2046)) - (PORT d[8] (1994:1994:1994) (2040:2040:2040)) - (PORT d[9] (2437:2437:2437) (2548:2548:2548)) - (PORT d[10] (2646:2646:2646) (2757:2757:2757)) - (PORT d[11] (2789:2789:2789) (2994:2994:2994)) - (PORT d[12] (4582:4582:4582) (4832:4832:4832)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1561:1561:1561) (1515:1515:1515)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3203:3203:3203) (3240:3240:3240)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2190:2190:2190) (2181:2181:2181)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4546:4546:4546) (4580:4580:4580)) - (PORT d[1] (4461:4461:4461) (4513:4513:4513)) - (PORT d[2] (4466:4466:4466) (4476:4476:4476)) - (PORT d[3] (4422:4422:4422) (4460:4460:4460)) - (PORT d[4] (4363:4363:4363) (4523:4523:4523)) - (PORT d[5] (4348:4348:4348) (4415:4415:4415)) - (PORT d[6] (4445:4445:4445) (4467:4467:4467)) - (PORT d[7] (4345:4345:4345) (4449:4449:4449)) - (PORT d[8] (4480:4480:4480) (4560:4560:4560)) - (PORT d[9] (4577:4577:4577) (4641:4641:4641)) - (PORT d[10] (4311:4311:4311) (4390:4390:4390)) - (PORT d[11] (4436:4436:4436) (4532:4532:4532)) - (PORT d[12] (4251:4251:4251) (4274:4274:4274)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2469:2469:2469) (2602:2602:2602)) - (PORT d[1] (2377:2377:2377) (2524:2524:2524)) - (PORT d[2] (2274:2274:2274) (2431:2431:2431)) - (PORT d[3] (2180:2180:2180) (2330:2330:2330)) - (PORT d[4] (2086:2086:2086) (2172:2172:2172)) - (PORT d[5] (2417:2417:2417) (2540:2540:2540)) - (PORT d[6] (2442:2442:2442) (2606:2606:2606)) - (PORT d[7] (3149:3149:3149) (3211:3211:3211)) - (PORT d[8] (2864:2864:2864) (2942:2942:2942)) - (PORT d[9] (2362:2362:2362) (2550:2550:2550)) - (PORT d[10] (3296:3296:3296) (3440:3440:3440)) - (PORT d[11] (2098:2098:2098) (2200:2200:2200)) - (PORT d[12] (2283:2283:2283) (2461:2461:2461)) - (PORT clk (1859:1859:1859) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (PORT d[0] (2575:2575:2575) (2667:2667:2667)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1848:1848:1848)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1012:1012:1012)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1012:1012:1012)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1012:1012:1012)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (2613:2613:2613) (2845:2845:2845)) - (PORT datab (2470:2470:2470) (2597:2597:2597)) - (PORT datac (1305:1305:1305) (1374:1374:1374)) - (PORT datad (1662:1662:1662) (1719:1719:1719)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1292:1292:1292)) - (PORT datab (741:741:741) (851:851:851)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (1965:1965:1965) (2023:2023:2023)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1550:1550:1550) (1580:1580:1580)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (2783:2783:2783) (2886:2886:2886)) - (PORT datab (938:938:938) (1032:1032:1032)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (1506:1506:1506) (1530:1530:1530)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (297:297:297)) - (PORT datab (859:859:859) (885:885:885)) - (PORT datac (623:623:623) (656:656:656)) - (PORT datad (1129:1129:1129) (1160:1160:1160)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (420:420:420) (450:450:450)) - (PORT datac (363:363:363) (431:431:431)) - (PORT datad (386:386:386) (412:412:412)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1315:1315:1315)) - (PORT datab (372:372:372) (397:397:397)) - (PORT datac (825:825:825) (876:876:876)) - (PORT datad (567:567:567) (578:578:578)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1940:1940:1940) (1962:1962:1962)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2328:2328:2328)) - (PORT datac (1575:1575:1575) (1707:1707:1707)) - (PORT datad (1688:1688:1688) (1747:1747:1747)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (897:897:897)) - (PORT datab (1870:1870:1870) (1946:1946:1946)) - (PORT datac (1151:1151:1151) (1176:1176:1176)) - (PORT datad (624:624:624) (661:661:661)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (678:678:678)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (1170:1170:1170) (1209:1209:1209)) - (PORT datad (844:844:844) (899:899:899)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (458:458:458)) - (PORT datab (603:603:603) (621:621:621)) - (PORT datad (1132:1132:1132) (1160:1160:1160)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1500:1500:1500) (1546:1546:1546)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2373:2373:2373) (2567:2567:2567)) - (PORT d[1] (2551:2551:2551) (2651:2651:2651)) - (PORT d[2] (1549:1549:1549) (1634:1634:1634)) - (PORT d[3] (1265:1265:1265) (1340:1340:1340)) - (PORT d[4] (2004:2004:2004) (2083:2083:2083)) - (PORT d[5] (1260:1260:1260) (1335:1335:1335)) - (PORT d[6] (1712:1712:1712) (1742:1742:1742)) - (PORT d[7] (2350:2350:2350) (2481:2481:2481)) - (PORT d[8] (2475:2475:2475) (2633:2633:2633)) - (PORT d[9] (1038:1038:1038) (1095:1095:1095)) - (PORT d[10] (1743:1743:1743) (1843:1843:1843)) - (PORT d[11] (1460:1460:1460) (1528:1528:1528)) - (PORT d[12] (1011:1011:1011) (1068:1068:1068)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1776:1776:1776) (1775:1775:1775)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2106:2106:2106) (2095:2095:2095)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1472:1472:1472) (1514:1514:1514)) + (PORT d[0] (1278:1278:1278) (1312:1312:1312)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -39456,19 +32475,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2336:2336:2336) (2510:2510:2510)) - (PORT d[1] (1981:1981:1981) (2064:2064:2064)) - (PORT d[2] (1851:1851:1851) (1954:1954:1954)) - (PORT d[3] (2217:2217:2217) (2311:2311:2311)) - (PORT d[4] (2028:2028:2028) (2096:2096:2096)) - (PORT d[5] (1586:1586:1586) (1680:1680:1680)) - (PORT d[6] (1724:1724:1724) (1771:1771:1771)) - (PORT d[7] (2272:2272:2272) (2376:2376:2376)) - (PORT d[8] (2487:2487:2487) (2660:2660:2660)) - (PORT d[9] (1183:1183:1183) (1248:1248:1248)) - (PORT d[10] (1648:1648:1648) (1719:1719:1719)) - (PORT d[11] (1194:1194:1194) (1243:1243:1243)) - (PORT d[12] (1050:1050:1050) (1129:1129:1129)) + (PORT d[0] (1262:1262:1262) (1331:1331:1331)) + (PORT d[1] (1212:1212:1212) (1237:1237:1237)) + (PORT d[2] (1271:1271:1271) (1322:1322:1322)) + (PORT d[3] (3082:3082:3082) (3281:3281:3281)) + (PORT d[4] (1956:1956:1956) (2111:2111:2111)) + (PORT d[5] (1272:1272:1272) (1312:1312:1312)) + (PORT d[6] (1230:1230:1230) (1267:1267:1267)) + (PORT d[7] (1564:1564:1564) (1636:1636:1636)) + (PORT d[8] (1722:1722:1722) (1799:1799:1799)) + (PORT d[9] (1787:1787:1787) (1851:1851:1851)) + (PORT d[10] (2180:2180:2180) (2343:2343:2343)) + (PORT d[11] (1692:1692:1692) (1782:1782:1782)) + (PORT d[12] (1656:1656:1656) (1809:1809:1809)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -39481,7 +32500,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1540:1540:1540) (1561:1561:1561)) + (PORT d[0] (2032:2032:2032) (2055:2055:2055)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -39495,7 +32514,7 @@ (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (1987:1987:1987) (1984:1984:1984)) + (PORT d[0] (2616:2616:2616) (2631:2631:2631)) ) ) ) @@ -39591,13 +32610,254 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (538:538:538) (569:569:569)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1011:1011:1011) (1066:1066:1066)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (2096:2096:2096) (2229:2229:2229)) + (PORT datab (1000:1000:1000) (1056:1056:1056)) + (PORT datac (1757:1757:1757) (1816:1816:1816)) + (PORT datad (218:218:218) (253:253:253)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1390:1390:1390)) + (PORT datab (1520:1520:1520) (1621:1621:1621)) + (PORT datad (1234:1234:1234) (1303:1303:1303)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1187:1187:1187) (1224:1224:1224)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2600:2600:2600) (2703:2703:2703)) + (PORT d[1] (2784:2784:2784) (2796:2796:2796)) + (PORT d[2] (2301:2301:2301) (2377:2377:2377)) + (PORT d[3] (862:862:862) (890:890:890)) + (PORT d[4] (2343:2343:2343) (2564:2564:2564)) + (PORT d[5] (2790:2790:2790) (2837:2837:2837)) + (PORT d[6] (4037:4037:4037) (4243:4243:4243)) + (PORT d[7] (1417:1417:1417) (1423:1423:1423)) + (PORT d[8] (1185:1185:1185) (1217:1217:1217)) + (PORT d[9] (932:932:932) (960:960:960)) + (PORT d[10] (968:968:968) (1021:1021:1021)) + (PORT d[11] (2849:2849:2849) (2976:2976:2976)) + (PORT d[12] (1858:1858:1858) (1904:1904:1904)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2752:2752:2752) (2713:2713:2713)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (3004:3004:3004) (2955:2955:2955)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (2098:2098:2098) (2224:2224:2224)) + (PORT datab (1000:1000:1000) (1057:1057:1057)) + (PORT datac (1760:1760:1760) (1813:1813:1813)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1524:1524:1524) (1626:1626:1626)) + (PORT datac (1219:1219:1219) (1348:1348:1348)) + (PORT datad (1233:1233:1233) (1301:1301:1301)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (914:914:914) (933:933:933)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1217:1217:1217) (1199:1199:1199)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -39609,20 +32869,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2902:2902:2902) (3119:3119:3119)) - (PORT d[1] (3573:3573:3573) (3763:3763:3763)) - (PORT d[2] (1956:1956:1956) (2034:2034:2034)) - (PORT d[3] (3972:3972:3972) (4152:4152:4152)) - (PORT d[4] (3177:3177:3177) (3389:3389:3389)) - (PORT d[5] (4728:4728:4728) (4845:4845:4845)) - (PORT d[6] (2221:2221:2221) (2292:2292:2292)) - (PORT d[7] (1688:1688:1688) (1718:1718:1718)) - (PORT d[8] (3114:3114:3114) (3291:3291:3291)) - (PORT d[9] (1819:1819:1819) (1883:1883:1883)) - (PORT d[10] (2034:2034:2034) (2098:2098:2098)) - (PORT d[11] (3078:3078:3078) (3310:3310:3310)) - (PORT d[12] (4587:4587:4587) (4856:4856:4856)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (3218:3218:3218) (3366:3366:3366)) + (PORT d[1] (3138:3138:3138) (3202:3202:3202)) + (PORT d[2] (3967:3967:3967) (4131:4131:4131)) + (PORT d[3] (1479:1479:1479) (1555:1555:1555)) + (PORT d[4] (2661:2661:2661) (2910:2910:2910)) + (PORT d[5] (3233:3233:3233) (3334:3334:3334)) + (PORT d[6] (3724:3724:3724) (3961:3961:3961)) + (PORT d[7] (1705:1705:1705) (1751:1751:1751)) + (PORT d[8] (3906:3906:3906) (4176:4176:4176)) + (PORT d[9] (4191:4191:4191) (4486:4486:4486)) + (PORT d[10] (3831:3831:3831) (4152:4152:4152)) + (PORT d[11] (1177:1177:1177) (1228:1228:1228)) + (PORT d[12] (2684:2684:2684) (2937:2937:2937)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -39634,8 +32894,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2278:2278:2278) (2264:2264:2264)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1825:1825:1825) (1875:1875:1875)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -39647,8 +32907,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2520:2520:2520) (2539:2539:2539)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2401:2401:2401) (2380:2380:2380)) ) ) ) @@ -39657,7 +32917,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -39667,7 +32927,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -39677,7 +32937,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -39687,7 +32947,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -39695,159 +32955,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1187:1187:1187) (1212:1212:1212)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2569:2569:2569) (2756:2756:2756)) - (PORT d[1] (3637:3637:3637) (3813:3813:3813)) - (PORT d[2] (2109:2109:2109) (2190:2190:2190)) - (PORT d[3] (4259:4259:4259) (4451:4451:4451)) - (PORT d[4] (3209:3209:3209) (3444:3444:3444)) - (PORT d[5] (4699:4699:4699) (4855:4855:4855)) - (PORT d[6] (2574:2574:2574) (2667:2667:2667)) - (PORT d[7] (1420:1420:1420) (1439:1439:1439)) - (PORT d[8] (3134:3134:3134) (3310:3310:3310)) - (PORT d[9] (1832:1832:1832) (1888:1888:1888)) - (PORT d[10] (2003:2003:2003) (2057:2057:2057)) - (PORT d[11] (3398:3398:3398) (3651:3651:3651)) - (PORT d[12] (4571:4571:4571) (4836:4836:4836)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1591:1591:1591) (1527:1527:1527)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2499:2499:2499) (2455:2455:2455)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -39861,7 +32968,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -39870,7 +32977,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39879,7 +32986,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39889,7 +32996,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39899,59 +33006,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (844:844:844)) - (PORT datab (1180:1180:1180) (1276:1276:1276)) - (PORT datac (1196:1196:1196) (1251:1251:1251)) - (PORT datad (1097:1097:1097) (1132:1132:1132)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) + (PORT datac (195:195:195) (228:228:228)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1245:1245:1245) (1338:1338:1338)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1985:1985:1985) (2039:2039:2039)) + (PORT datab (1274:1274:1274) (1328:1328:1328)) + (PORT datac (923:923:923) (978:978:978)) + (PORT datad (1666:1666:1666) (1729:1729:1729)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1234:1234:1234) (1290:1290:1290)) - (PORT datab (1272:1272:1272) (1332:1332:1332)) - (PORT datac (1738:1738:1738) (1814:1814:1814)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (2634:2634:2634) (2764:2764:2764)) - (PORT datab (1940:1940:1940) (2085:2085:2085)) - (PORT datac (2774:2774:2774) (3006:3006:3006)) - (PORT datad (2211:2211:2211) (2282:2282:2282)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (1413:1413:1413) (1528:1528:1528)) + (PORT datac (244:244:244) (325:325:325)) + (PORT datad (884:884:884) (949:949:949)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1585:1585:1585) (1668:1668:1668)) - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (1298:1298:1298) (1336:1336:1336)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -39960,23 +33087,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3186:3186:3186) (3418:3418:3418)) - (PORT d[1] (3339:3339:3339) (3475:3475:3475)) - (PORT d[2] (2251:2251:2251) (2357:2357:2357)) - (PORT d[3] (3642:3642:3642) (3797:3797:3797)) - (PORT d[4] (2928:2928:2928) (3138:3138:3138)) - (PORT d[5] (4390:4390:4390) (4507:4507:4507)) - (PORT d[6] (1780:1780:1780) (1859:1859:1859)) - (PORT d[7] (1974:1974:1974) (2019:2019:2019)) - (PORT d[8] (2011:2011:2011) (2055:2055:2055)) - (PORT d[9] (2117:2117:2117) (2203:2203:2203)) - (PORT d[10] (2341:2341:2341) (2430:2430:2430)) - (PORT d[11] (2795:2795:2795) (3008:3008:3008)) - (PORT d[12] (4293:4293:4293) (4549:4549:4549)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (1817:1817:1817) (1888:1888:1888)) + (PORT d[1] (2038:2038:2038) (2075:2075:2075)) + (PORT d[2] (1311:1311:1311) (1365:1365:1365)) + (PORT d[3] (3348:3348:3348) (3550:3550:3550)) + (PORT d[4] (1968:1968:1968) (2123:2123:2123)) + (PORT d[5] (959:959:959) (996:996:996)) + (PORT d[6] (959:959:959) (1001:1001:1001)) + (PORT d[7] (1200:1200:1200) (1265:1265:1265)) + (PORT d[8] (1721:1721:1721) (1783:1783:1783)) + (PORT d[9] (1802:1802:1802) (1855:1855:1855)) + (PORT d[10] (2503:2503:2503) (2690:2690:2690)) + (PORT d[11] (2004:2004:2004) (2098:2098:2098)) + (PORT d[12] (1666:1666:1666) (1803:1803:1803)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -39985,11 +33112,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1653:1653:1653) (1635:1635:1635)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT d[0] (1863:1863:1863) (1835:1835:1835)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -39998,60 +33125,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (PORT d[0] (2870:2870:2870) (2886:2886:2886)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2259:2259:2259) (2277:2277:2277)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1887:1887:1887)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1813:1813:1813) (1811:1811:1811)) + (PORT clk (1807:1807:1807) (1834:1834:1834)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40062,108 +33189,92 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2178:2178:2178) (2158:2158:2158)) - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4523:4523:4523) (4579:4579:4579)) - (PORT d[1] (4471:4471:4471) (4537:4537:4537)) - (PORT d[2] (4520:4520:4520) (4549:4549:4549)) - (PORT d[3] (4434:4434:4434) (4448:4448:4448)) - (PORT d[4] (4399:4399:4399) (4562:4562:4562)) - (PORT d[5] (4336:4336:4336) (4388:4388:4388)) - (PORT d[6] (4419:4419:4419) (4461:4461:4461)) - (PORT d[7] (4386:4386:4386) (4436:4436:4436)) - (PORT d[8] (4545:4545:4545) (4646:4646:4646)) - (PORT d[9] (4542:4542:4542) (4602:4602:4602)) - (PORT d[10] (4589:4589:4589) (4649:4649:4649)) - (PORT d[11] (4439:4439:4439) (4545:4545:4545)) - (PORT d[12] (4288:4288:4288) (4293:4293:4293)) - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (992:992:992) (997:997:997)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (993:993:993) (998:998:998)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1818:1818:1818)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1075:1075:1075)) + (PORT datab (1587:1587:1587) (1635:1635:1635)) + (PORT datac (1476:1476:1476) (1557:1557:1557)) + (PORT datad (1251:1251:1251) (1331:1331:1331)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1353:1353:1353)) + (PORT datab (1816:1816:1816) (1884:1884:1884)) + (PORT datac (1387:1387:1387) (1431:1431:1431)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1682:1682:1682) (1815:1815:1815)) - (PORT d[1] (1648:1648:1648) (1686:1686:1686)) - (PORT d[2] (2268:2268:2268) (2431:2431:2431)) - (PORT d[3] (1863:1863:1863) (1918:1918:1918)) - (PORT d[4] (2378:2378:2378) (2506:2506:2506)) - (PORT d[5] (2549:2549:2549) (2590:2590:2590)) - (PORT d[6] (1990:1990:1990) (2063:2063:2063)) - (PORT d[7] (2031:2031:2031) (2099:2099:2099)) - (PORT d[8] (2125:2125:2125) (2219:2219:2219)) - (PORT d[9] (2009:2009:2009) (2078:2078:2078)) - (PORT d[10] (1655:1655:1655) (1716:1716:1716)) - (PORT d[11] (4351:4351:4351) (4669:4669:4669)) - (PORT d[12] (2155:2155:2155) (2206:2206:2206)) + (PORT d[0] (2282:2282:2282) (2345:2345:2345)) + (PORT d[1] (2186:2186:2186) (2203:2203:2203)) + (PORT d[2] (1989:1989:1989) (2022:2022:2022)) + (PORT d[3] (1174:1174:1174) (1217:1217:1217)) + (PORT d[4] (2551:2551:2551) (2690:2690:2690)) + (PORT d[5] (2435:2435:2435) (2453:2453:2453)) + (PORT d[6] (3702:3702:3702) (3892:3892:3892)) + (PORT d[7] (1720:1720:1720) (1724:1724:1724)) + (PORT d[8] (1257:1257:1257) (1274:1274:1274)) + (PORT d[9] (1584:1584:1584) (1662:1662:1662)) + (PORT d[10] (1795:1795:1795) (1851:1851:1851)) + (PORT d[11] (1701:1701:1701) (1786:1786:1786)) + (PORT d[12] (1562:1562:1562) (1628:1628:1628)) (PORT clk (1856:1856:1856) (1882:1882:1882)) ) ) @@ -40177,7 +33288,7 @@ (DELAY (ABSOLUTE (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (2116:2116:2116) (2085:2085:2085)) + (PORT d[0] (1667:1667:1667) (1687:1687:1687)) ) ) ) @@ -40243,13 +33354,544 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (4389:4389:4389) (4567:4567:4567)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (2000:2000:2000) (2071:2071:2071)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2097:2097:2097) (2228:2228:2228)) + (PORT datab (997:997:997) (1054:1054:1054)) + (PORT datac (1756:1756:1756) (1816:1816:1816)) + (PORT datad (217:217:217) (251:251:251)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (663:663:663) (726:726:726)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (587:587:587)) + (PORT datab (1409:1409:1409) (1559:1559:1559)) + (PORT datac (1641:1641:1641) (1702:1702:1702)) + (PORT datad (272:272:272) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1668:1668:1668) (1703:1703:1703)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (722:722:722) (771:771:771)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1384:1384:1384) (1463:1463:1463)) + (PORT datad (721:721:721) (771:771:771)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1503:1503:1503)) + (PORT datab (731:731:731) (802:802:802)) + (PORT datad (721:721:721) (772:772:772)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (843:843:843) (857:857:857)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1248:1248:1248)) + (PORT datab (1375:1375:1375) (1493:1493:1493)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT datab (626:626:626) (699:699:699)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1304:1304:1304)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (737:737:737)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (888:888:888) (889:889:889)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (841:841:841) (904:904:904)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (680:680:680) (700:700:700)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (724:724:724)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1346:1346:1346) (1347:1347:1347)) + (PORT ena (1222:1222:1222) (1213:1213:1213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (814:814:814)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (397:397:397)) + (PORT datac (606:606:606) (621:621:621)) + (PORT datad (925:925:925) (982:982:982)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (585:585:585)) + (PORT datab (1411:1411:1411) (1560:1560:1560)) + (PORT datac (1643:1643:1643) (1707:1707:1707)) + (PORT datad (275:275:275) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (798:798:798) (845:845:845)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1036:1036:1036)) + (PORT datac (320:320:320) (351:351:351)) + (PORT datad (347:347:347) (371:371:371)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (592:592:592)) + (PORT datab (1407:1407:1407) (1564:1564:1564)) + (PORT datac (1641:1641:1641) (1703:1703:1703)) + (PORT datad (275:275:275) (356:356:356)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (588:588:588)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (972:972:972) (965:965:965)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (324:324:324) (355:355:355)) + (PORT datad (926:926:926) (989:989:989)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1037:1037:1037)) + (PORT datad (345:345:345) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1405:1405:1405) (1389:1389:1389)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1562:1562:1562) (1663:1663:1663)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (1542:1542:1542) (1597:1597:1597)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) ) ) (TIMINGCHECK @@ -40261,20 +33903,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1624:1624:1624) (1739:1739:1739)) - (PORT d[1] (2987:2987:2987) (3136:3136:3136)) - (PORT d[2] (2558:2558:2558) (2693:2693:2693)) - (PORT d[3] (3334:3334:3334) (3467:3467:3467)) - (PORT d[4] (2606:2606:2606) (2786:2786:2786)) - (PORT d[5] (3822:3822:3822) (3934:3934:3934)) - (PORT d[6] (2246:2246:2246) (2338:2338:2338)) - (PORT d[7] (3413:3413:3413) (3468:3468:3468)) - (PORT d[8] (2931:2931:2931) (3033:3033:3033)) - (PORT d[9] (2477:2477:2477) (2573:2573:2573)) - (PORT d[10] (2626:2626:2626) (2737:2737:2737)) - (PORT d[11] (2491:2491:2491) (2679:2679:2679)) - (PORT d[12] (4641:4641:4641) (4882:4882:4882)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (3709:3709:3709) (3843:3843:3843)) + (PORT d[1] (4318:4318:4318) (4447:4447:4447)) + (PORT d[2] (3267:3267:3267) (3395:3395:3395)) + (PORT d[3] (3158:3158:3158) (3390:3390:3390)) + (PORT d[4] (3183:3183:3183) (3450:3450:3450)) + (PORT d[5] (3060:3060:3060) (3230:3230:3230)) + (PORT d[6] (3068:3068:3068) (3241:3241:3241)) + (PORT d[7] (4376:4376:4376) (4586:4586:4586)) + (PORT d[8] (2982:2982:2982) (3153:3153:3153)) + (PORT d[9] (2769:2769:2769) (2980:2980:2980)) + (PORT d[10] (2730:2730:2730) (3000:3000:3000)) + (PORT d[11] (2383:2383:2383) (2510:2510:2510)) + (PORT d[12] (2039:2039:2039) (2260:2260:2260)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) ) ) (TIMINGCHECK @@ -40286,8 +33928,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2847:2847:2847) (2894:2894:2894)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (2236:2236:2236) (2216:2216:2216)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) ) ) (TIMINGCHECK @@ -40299,8 +33941,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3233:3233:3233) (3186:3186:3186)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (5003:5003:5003) (4909:4909:4909)) ) ) ) @@ -40309,7 +33951,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -40319,7 +33961,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -40329,7 +33971,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -40339,7 +33981,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -40349,7 +33991,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) + (PORT clk (1824:1824:1824) (1820:1820:1820)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40363,8 +34005,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1943:1943:1943) (1936:1936:1936)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT d[0] (1436:1436:1436) (1454:1454:1454)) + (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) (TIMINGCHECK @@ -40376,20 +34018,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4480:4480:4480) (4505:4505:4505)) - (PORT d[1] (4433:4433:4433) (4489:4489:4489)) - (PORT d[2] (4515:4515:4515) (4513:4513:4513)) - (PORT d[3] (4207:4207:4207) (4267:4267:4267)) - (PORT d[4] (4326:4326:4326) (4470:4470:4470)) - (PORT d[5] (4354:4354:4354) (4405:4405:4405)) - (PORT d[6] (4409:4409:4409) (4469:4469:4469)) - (PORT d[7] (4149:4149:4149) (4196:4196:4196)) - (PORT d[8] (4390:4390:4390) (4446:4446:4446)) - (PORT d[9] (4387:4387:4387) (4446:4446:4446)) - (PORT d[10] (4288:4288:4288) (4373:4373:4373)) - (PORT d[11] (4468:4468:4468) (4585:4585:4585)) - (PORT d[12] (4406:4406:4406) (4382:4382:4382)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT d[0] (4205:4205:4205) (4290:4290:4290)) + (PORT d[1] (4273:4273:4273) (4458:4458:4458)) + (PORT d[2] (4102:4102:4102) (4182:4182:4182)) + (PORT d[3] (4090:4090:4090) (4128:4128:4128)) + (PORT d[4] (4141:4141:4141) (4179:4179:4179)) + (PORT d[5] (4398:4398:4398) (4597:4597:4597)) + (PORT d[6] (4328:4328:4328) (4519:4519:4519)) + (PORT d[7] (4480:4480:4480) (4639:4639:4639)) + (PORT d[8] (4196:4196:4196) (4247:4247:4247)) + (PORT d[9] (4204:4204:4204) (4293:4293:4293)) + (PORT d[10] (4098:4098:4098) (4163:4163:4163)) + (PORT d[11] (4235:4235:4235) (4314:4314:4314)) + (PORT d[12] (4184:4184:4184) (4228:4228:4228)) + (PORT clk (1830:1830:1830) (1822:1822:1822)) ) ) (TIMINGCHECK @@ -40401,7 +34043,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) ) @@ -40410,7 +34052,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -40420,7 +34062,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) @@ -40430,7 +34072,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -40440,7 +34082,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -40450,7 +34092,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1812:1812:1812)) + (PORT clk (1826:1826:1826) (1822:1822:1822)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40464,20 +34106,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1665:1665:1665) (1779:1779:1779)) - (PORT d[1] (2703:2703:2703) (2833:2833:2833)) - (PORT d[2] (2113:2113:2113) (2246:2246:2246)) - (PORT d[3] (3328:3328:3328) (3453:3453:3453)) - (PORT d[4] (2296:2296:2296) (2448:2448:2448)) - (PORT d[5] (3758:3758:3758) (3880:3880:3880)) - (PORT d[6] (2543:2543:2543) (2630:2630:2630)) - (PORT d[7] (3441:3441:3441) (3488:3488:3488)) - (PORT d[8] (2926:2926:2926) (3023:3023:3023)) - (PORT d[9] (2768:2768:2768) (2881:2881:2881)) - (PORT d[10] (2335:2335:2335) (2395:2395:2395)) - (PORT d[11] (2478:2478:2478) (2654:2654:2654)) - (PORT d[12] (3520:3520:3520) (3735:3735:3735)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (2594:2594:2594) (2693:2693:2693)) + (PORT d[1] (2461:2461:2461) (2483:2483:2483)) + (PORT d[2] (2316:2316:2316) (2388:2388:2388)) + (PORT d[3] (902:902:902) (935:935:935)) + (PORT d[4] (2614:2614:2614) (2828:2828:2828)) + (PORT d[5] (2783:2783:2783) (2824:2824:2824)) + (PORT d[6] (4030:4030:4030) (4216:4216:4216)) + (PORT d[7] (1467:1467:1467) (1480:1480:1480)) + (PORT d[8] (1488:1488:1488) (1521:1521:1521)) + (PORT d[9] (1469:1469:1469) (1534:1534:1534)) + (PORT d[10] (658:658:658) (690:690:690)) + (PORT d[11] (2561:2561:2561) (2687:2687:2687)) + (PORT d[12] (1787:1787:1787) (1844:1844:1844)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -40489,8 +34131,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (PORT d[0] (2653:2653:2653) (2588:2588:2588)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (PORT d[0] (1095:1095:1095) (1112:1112:1112)) ) ) ) @@ -40499,7 +34141,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT clk (1848:1848:1848) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -40509,7 +34151,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1824:1824:1824) (1850:1850:1850)) + (PORT clk (1810:1810:1810) (1836:1836:1836)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40523,7 +34165,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1009:1009:1009) (1013:1013:1013)) + (PORT clk (995:995:995) (999:999:999)) ) ) ) @@ -40532,7 +34174,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1010:1010:1010) (1014:1014:1014)) + (PORT clk (996:996:996) (1000:1000:1000)) ) ) ) @@ -40541,7 +34183,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1010:1010:1010) (1014:1014:1014)) + (PORT clk (996:996:996) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -40551,21 +34193,21 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1010:1010:1010) (1014:1014:1014)) + (PORT clk (996:996:996) (1000:1000:1000)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (INSTANCE Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1288:1288:1288)) - (PORT datab (724:724:724) (782:782:782)) - (PORT datac (1333:1333:1333) (1353:1353:1353)) - (PORT datad (1400:1400:1400) (1484:1484:1484)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (948:948:948) (1037:1037:1037)) + (PORT datab (950:950:950) (1009:1009:1009)) + (PORT datac (1666:1666:1666) (1698:1698:1698)) + (PORT datad (1395:1395:1395) (1435:1435:1435)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -40574,48 +34216,277 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (701:701:701) (765:765:765)) - (PORT datab (1092:1092:1092) (1091:1091:1091)) - (PORT datac (1528:1528:1528) (1658:1658:1658)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (1922:1922:1922) (1986:1986:1986)) + (PORT datab (1228:1228:1228) (1267:1267:1267)) + (PORT datac (1758:1758:1758) (1828:1828:1828)) + (PORT datad (1410:1410:1410) (1449:1449:1449)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1524:1524:1524) (1563:1563:1563)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3814:3814:3814) (4007:4007:4007)) + (PORT d[1] (3759:3759:3759) (3869:3869:3869)) + (PORT d[2] (3397:3397:3397) (3501:3501:3501)) + (PORT d[3] (3498:3498:3498) (3752:3752:3752)) + (PORT d[4] (3472:3472:3472) (3768:3768:3768)) + (PORT d[5] (2962:2962:2962) (3067:3067:3067)) + (PORT d[6] (3092:3092:3092) (3270:3270:3270)) + (PORT d[7] (4484:4484:4484) (4711:4711:4711)) + (PORT d[8] (3304:3304:3304) (3520:3520:3520)) + (PORT d[9] (3614:3614:3614) (3836:3836:3836)) + (PORT d[10] (3140:3140:3140) (3423:3423:3423)) + (PORT d[11] (2935:2935:2935) (3078:3078:3078)) + (PORT d[12] (2171:2171:2171) (2332:2332:2332)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2395:2395:2395) (2407:2407:2407)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (5285:5285:5285) (5387:5387:5387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1374:1374:1374) (1378:1378:1378)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4263:4263:4263) (4317:4317:4317)) + (PORT d[1] (4248:4248:4248) (4422:4422:4422)) + (PORT d[2] (4119:4119:4119) (4218:4218:4218)) + (PORT d[3] (4113:4113:4113) (4136:4136:4136)) + (PORT d[4] (4133:4133:4133) (4161:4161:4161)) + (PORT d[5] (4212:4212:4212) (4409:4409:4409)) + (PORT d[6] (4225:4225:4225) (4521:4521:4521)) + (PORT d[7] (4241:4241:4241) (4397:4397:4397)) + (PORT d[8] (4118:4118:4118) (4165:4165:4165)) + (PORT d[9] (4188:4188:4188) (4257:4257:4257)) + (PORT d[10] (4147:4147:4147) (4197:4197:4197)) + (PORT d[11] (4247:4247:4247) (4292:4292:4292)) + (PORT d[12] (4201:4201:4201) (4265:4265:4265)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1610:1610:1610)) + (PORT datab (1166:1166:1166) (1239:1239:1239)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (1530:1530:1530) (1567:1567:1567)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~116) + (INSTANCE D\[7\]\~36) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (973:973:973) (999:999:999)) - (PORT datad (615:615:615) (641:641:641)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1184:1184:1184) (1244:1244:1244)) + (PORT datab (1695:1695:1695) (1769:1769:1769)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~117) + (INSTANCE D\[7\]\~37) (DELAY (ABSOLUTE - (PORT dataa (1229:1229:1229) (1241:1241:1241)) - (PORT datab (2477:2477:2477) (2583:2583:2583)) - (PORT datac (1187:1187:1187) (1273:1273:1273)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (669:669:669) (736:736:736)) + (PORT datab (2229:2229:2229) (2318:2318:2318)) + (PORT datac (1368:1368:1368) (1422:1422:1422)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (843:843:843) (875:875:875)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -40625,25 +34496,41 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (398:398:398)) - (PORT datab (431:431:431) (467:467:467)) - (PORT datac (1157:1157:1157) (1229:1229:1229)) - (PORT datad (1131:1131:1131) (1158:1158:1158)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (903:903:903) (909:909:909)) + (PORT datab (256:256:256) (315:315:315)) + (PORT datac (1484:1484:1484) (1531:1531:1531)) + (PORT datad (2098:2098:2098) (2140:2140:2140)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1209:1209:1209)) + (PORT datab (1593:1593:1593) (1775:1775:1775)) + (PORT datac (1473:1473:1473) (1520:1520:1520)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|data_pins_\|dout\[7\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT clk (1520:1520:1520) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -40654,16 +34541,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (INSTANCE z80_\|bus_control_\|db\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (420:420:420) (454:454:454)) - (PORT datac (594:594:594) (602:602:602)) - (PORT datad (240:240:240) (310:310:310)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (272:272:272) (328:328:328)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (625:625:625) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -40673,10 +34560,10 @@ (INSTANCE z80_\|ir_\|opcode\[7\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (675:675:675) (698:698:698)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1430:1430:1430) (1462:1462:1462)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (841:841:841) (847:847:847)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -40688,11 +34575,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT datac (1095:1095:1095) (1167:1167:1167)) - (PORT datad (1964:1964:1964) (2035:2035:2035)) + (PORT datab (983:983:983) (1061:1061:1061)) + (PORT datac (679:679:679) (742:742:742)) + (PORT datad (1705:1705:1705) (1803:1803:1803)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40700,47 +34589,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) (DELAY (ABSOLUTE - (PORT dataa (2561:2561:2561) (2630:2630:2630)) - (PORT datab (2099:2099:2099) (2235:2235:2235)) - (PORT datac (2435:2435:2435) (2634:2634:2634)) - (PORT datad (1838:1838:1838) (1932:1932:1932)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1582:1582:1582) (1716:1716:1716)) + (PORT datab (1699:1699:1699) (1758:1758:1758)) + (PORT datac (1609:1609:1609) (1656:1656:1656)) + (PORT datad (2362:2362:2362) (2450:2450:2450)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1616:1616:1616) (1664:1664:1664)) - (PORT datab (568:568:568) (584:584:584)) - (PORT datac (848:848:848) (863:863:863)) - (PORT datad (172:172:172) (198:198:198)) + (PORT dataa (1638:1638:1638) (1692:1692:1692)) + (PORT datab (2151:2151:2151) (2221:2221:2221)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (2201:2201:2201) (2266:2266:2266)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (221:221:221) (265:265:265)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (893:893:893) (956:956:956)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (699:699:699)) - (PORT datab (856:856:856) (930:930:930)) - (PORT datac (1457:1457:1457) (1472:1472:1472)) - (PORT datad (1160:1160:1160) (1214:1214:1214)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40748,49 +34637,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (2288:2288:2288) (2394:2394:2394)) - (PORT datab (2179:2179:2179) (2358:2358:2358)) - (PORT datac (1178:1178:1178) (1292:1292:1292)) - (PORT datad (819:819:819) (892:892:892)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (855:855:855)) - (PORT datab (770:770:770) (837:837:837)) - (PORT datac (1830:1830:1830) (1968:1968:1968)) - (PORT datad (1686:1686:1686) (1757:1757:1757)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1959:1959:1959) (2051:2051:2051)) + (PORT datab (2153:2153:2153) (2226:2226:2226)) + (PORT datac (1744:1744:1744) (1774:1774:1774)) + (PORT datad (2203:2203:2203) (2269:2269:2269)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40798,184 +34653,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (INSTANCE z80_\|execute_\|fIORead\~3) (DELAY (ABSOLUTE - (PORT dataa (930:930:930) (1012:1012:1012)) - (PORT datab (1179:1179:1179) (1247:1247:1247)) - (PORT datac (1905:1905:1905) (1971:1971:1971)) - (PORT datad (1431:1431:1431) (1464:1464:1464)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (929:929:929) (946:946:946)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (968:968:968) (972:972:972)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (674:674:674)) - (PORT datab (968:968:968) (1029:1029:1029)) - (PORT datad (359:359:359) (423:423:423)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (959:959:959)) - (PORT datab (989:989:989) (1031:1031:1031)) - (PORT datac (617:617:617) (643:643:643)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (674:674:674)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (1172:1172:1172) (1212:1212:1212)) - (PORT datad (839:839:839) (895:895:895)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1508:1508:1508) (1611:1611:1611)) - (PORT datab (1253:1253:1253) (1278:1278:1278)) - (PORT datac (1153:1153:1153) (1183:1183:1183)) - (PORT datad (1488:1488:1488) (1524:1524:1524)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1178:1178:1178) (1217:1217:1217)) + (PORT datad (180:180:180) (209:209:209)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datab (1453:1453:1453) (1487:1487:1487)) - (PORT datac (508:508:508) (517:517:517)) - (PORT datad (952:952:952) (989:989:989)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (617:617:617) (659:659:659)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (382:382:382) (410:410:410)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (525:525:525) (533:533:533)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1019:1019:1019)) - (PORT datab (931:931:931) (1012:1012:1012)) - (PORT datac (252:252:252) (337:337:337)) - (PORT datad (268:268:268) (347:347:347)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (738:738:738) (815:815:815)) - (PORT datad (1023:1023:1023) (1090:1090:1090)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (437:437:437)) - (PORT datab (337:337:337) (366:366:366)) - (PORT datac (734:734:734) (821:821:821)) - (PORT datad (581:581:581) (597:597:597)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40983,422 +34669,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (771:771:771) (850:850:850)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (301:301:301) (418:418:418)) - (PORT datab (680:680:680) (747:747:747)) - (PORT datac (912:912:912) (975:975:975)) - (PORT datad (946:946:946) (1019:1019:1019)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (838:838:838)) - (PORT datab (771:771:771) (853:853:853)) - (PORT datac (697:697:697) (771:771:771)) - (PORT datad (966:966:966) (1032:1032:1032)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT datab (1063:1063:1063) (1128:1128:1128)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (684:684:684)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (710:710:710) (772:772:772)) - (PORT datad (520:520:520) (531:531:531)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (376:376:376)) - (PORT datab (775:775:775) (855:855:855)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (947:947:947) (978:978:978)) - (PORT datac (785:785:785) (819:819:819)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (573:573:573)) - (PORT datab (1005:1005:1005) (1093:1093:1093)) - (PORT datac (669:669:669) (725:725:725)) - (PORT datad (618:618:618) (686:686:686)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (573:573:573)) - (PORT datac (755:755:755) (829:829:829)) - (PORT datad (392:392:392) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1127:1127:1127)) - (PORT datac (901:901:901) (915:915:915)) - (PORT datad (729:729:729) (803:803:803)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (246:246:246)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datad (576:576:576) (586:586:586)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (620:620:620)) - (PORT datab (1063:1063:1063) (1128:1128:1128)) - (PORT datac (731:731:731) (807:807:807)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (559:559:559) (578:578:578)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (233:233:233) (282:282:282)) - (PORT datab (228:228:228) (268:268:268)) - (PORT datac (931:931:931) (977:977:977)) - (PORT datad (617:617:617) (661:661:661)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (817:817:817)) - (PORT datab (1016:1016:1016) (1083:1083:1083)) - (PORT datac (962:962:962) (1040:1040:1040)) - (PORT datad (577:577:577) (602:602:602)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1396:1396:1396)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (706:706:706)) - (PORT datac (1000:1000:1000) (1060:1060:1060)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (735:735:735) (825:825:825)) - (PORT datab (970:970:970) (1056:1056:1056)) - (PORT datac (753:753:753) (841:841:841)) - (PORT datad (904:904:904) (978:978:978)) + (PORT dataa (909:909:909) (932:932:932)) + (PORT datab (690:690:690) (737:737:737)) + (PORT datac (1110:1110:1110) (1168:1168:1168)) + (PORT datad (597:597:597) (627:627:627)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~69) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (584:584:584)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (937:937:937) (1017:1017:1017)) - (PORT datad (192:192:192) (225:225:225)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (905:905:905)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (606:606:606) (617:617:617)) - (PORT datad (714:714:714) (785:785:785)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (425:425:425) (501:501:501)) - (PORT datac (745:745:745) (823:823:823)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1137:1137:1137)) - (PORT datab (593:593:593) (663:663:663)) - (PORT datac (1004:1004:1004) (1060:1060:1060)) - (PORT datad (609:609:609) (666:666:666)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (688:688:688)) - (PORT datab (750:750:750) (829:829:829)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (262:262:262) (341:341:341)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1812:1812:1812) (1848:1848:1848)) + (PORT datac (959:959:959) (1025:1025:1025)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41406,168 +34699,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (INSTANCE z80_\|execute_\|setM1\~59) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (245:245:245)) - (PORT datab (744:744:744) (816:816:816)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1542:1542:1542) (1535:1535:1535)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1478:1478:1478) (1551:1551:1551)) - (PORT datac (2279:2279:2279) (2486:2486:2486)) - (PORT datad (872:872:872) (942:942:942)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (814:814:814)) - (PORT datac (962:962:962) (1038:1038:1038)) - (PORT datad (578:578:578) (600:600:600)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (1295:1295:1295) (1399:1399:1399)) - (PORT datab (1016:1016:1016) (1082:1082:1082)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (436:436:436)) - (PORT datab (739:739:739) (806:806:806)) - (PORT datac (888:888:888) (956:956:956)) - (PORT datad (198:198:198) (235:235:235)) + (PORT dataa (1027:1027:1027) (1149:1149:1149)) + (PORT datab (1711:1711:1711) (1757:1757:1757)) + (PORT datac (1626:1626:1626) (1824:1824:1824)) + (PORT datad (882:882:882) (907:907:907)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1399:1399:1399)) - (PORT datab (957:957:957) (996:996:996)) - (PORT datad (592:592:592) (615:615:615)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (2799:2799:2799) (3004:3004:3004)) - (PORT datac (215:215:215) (290:290:290)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41575,26 +34715,252 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) + (INSTANCE z80_\|execute_\|setM1\~41) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (931:931:931)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (2354:2354:2354) (2577:2577:2577)) - (PORT datad (621:621:621) (631:631:631)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1106:1106:1106) (1105:1105:1105)) + (PORT datad (579:579:579) (602:602:602)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (560:560:560)) + (PORT datab (1478:1478:1478) (1574:1574:1574)) + (PORT datac (1218:1218:1218) (1309:1309:1309)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) (DELAY (ABSOLUTE - (PORT d[0] (1207:1207:1207) (1245:1245:1245)) + (PORT dataa (934:934:934) (997:997:997)) + (PORT datab (248:248:248) (297:297:297)) + (PORT datac (1543:1543:1543) (1571:1571:1571)) + (PORT datad (654:654:654) (671:671:671)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1332:1332:1332)) + (PORT datab (1717:1717:1717) (1765:1765:1765)) + (PORT datac (363:363:363) (390:390:390)) + (PORT datad (1218:1218:1218) (1307:1307:1307)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (887:887:887)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1125:1125:1125) (1181:1181:1181)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (435:435:435)) + (PORT datab (1162:1162:1162) (1218:1218:1218)) + (PORT datac (1144:1144:1144) (1154:1154:1154)) + (PORT datad (656:656:656) (713:713:713)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (983:983:983) (1043:1043:1043)) + (PORT datac (1407:1407:1407) (1437:1437:1437)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1324:1324:1324) (1365:1365:1365)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1539:1539:1539)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1540:1540:1540)) + (PORT ena (2003:2003:2003) (2031:2031:2031)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (985:985:985) (1073:1073:1073)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1563:1563:1563) (1545:1545:1545)) + (PORT ena (1458:1458:1458) (1463:1463:1463)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1091:1091:1091) (1160:1160:1160)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (1090:1090:1090) (1162:1162:1162)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (619:619:619)) + (PORT datab (1161:1161:1161) (1228:1228:1228)) + (PORT datac (1130:1130:1130) (1197:1197:1197)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1328:1328:1328)) + (PORT datab (1163:1163:1163) (1212:1212:1212)) + (PORT datac (1131:1131:1131) (1177:1177:1177)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1209:1209:1209) (1270:1270:1270)) (PORT clk (1843:1843:1843) (1871:1871:1871)) ) ) @@ -41604,22 +34970,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2687:2687:2687) (2899:2899:2899)) - (PORT d[1] (2871:2871:2871) (2966:2966:2966)) - (PORT d[2] (1020:1020:1020) (1070:1070:1070)) - (PORT d[3] (974:974:974) (1029:1029:1029)) - (PORT d[4] (2049:2049:2049) (2146:2146:2146)) - (PORT d[5] (972:972:972) (1026:1026:1026)) - (PORT d[6] (1699:1699:1699) (1745:1745:1745)) - (PORT d[7] (2654:2654:2654) (2813:2813:2813)) - (PORT d[8] (2491:2491:2491) (2668:2668:2668)) - (PORT d[9] (756:756:756) (799:799:799)) - (PORT d[10] (747:747:747) (789:789:789)) - (PORT d[11] (2820:2820:2820) (3002:3002:3002)) - (PORT d[12] (430:430:430) (463:463:463)) + (PORT d[0] (995:995:995) (1040:1040:1040)) + (PORT d[1] (1269:1269:1269) (1326:1326:1326)) + (PORT d[2] (1006:1006:1006) (1044:1044:1044)) + (PORT d[3] (2781:2781:2781) (2932:2932:2932)) + (PORT d[4] (1252:1252:1252) (1314:1314:1314)) + (PORT d[5] (2152:2152:2152) (2248:2248:2248)) + (PORT d[6] (922:922:922) (959:959:959)) + (PORT d[7] (924:924:924) (977:977:977)) + (PORT d[8] (1134:1134:1134) (1170:1170:1170)) + (PORT d[9] (1495:1495:1495) (1553:1553:1553)) + (PORT d[10] (1955:1955:1955) (2133:2133:2133)) + (PORT d[11] (2280:2280:2280) (2387:2387:2387)) + (PORT d[12] (1360:1360:1360) (1475:1475:1475)) (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) @@ -41629,10 +34995,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1529:1529:1529) (1497:1497:1497)) + (PORT d[0] (1737:1737:1737) (1706:1706:1706)) (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) @@ -41642,17 +35008,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (1469:1469:1469) (1447:1447:1447)) + (PORT d[0] (2000:2000:2000) (2004:2004:2004)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41662,7 +35028,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41672,7 +35038,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41682,7 +35048,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1872:1872:1872)) @@ -41692,7 +35058,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1803:1803:1803) (1830:1830:1830)) @@ -41706,7 +35072,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (988:988:988) (993:993:993)) @@ -41715,7 +35081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) (DELAY (ABSOLUTE (PORT clk (989:989:989) (994:994:994)) @@ -41724,7 +35090,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (989:989:989) (994:994:994)) @@ -41734,7 +35100,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (989:989:989) (994:994:994)) @@ -41742,12 +35108,6221 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1291:1291:1291) (1358:1358:1358)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (671:671:671) (709:709:709)) + (PORT d[1] (1279:1279:1279) (1316:1316:1316)) + (PORT d[2] (1326:1326:1326) (1397:1397:1397)) + (PORT d[3] (2492:2492:2492) (2661:2661:2661)) + (PORT d[4] (1257:1257:1257) (1322:1322:1322)) + (PORT d[5] (2125:2125:2125) (2217:2217:2217)) + (PORT d[6] (1884:1884:1884) (2017:2017:2017)) + (PORT d[7] (1212:1212:1212) (1263:1263:1263)) + (PORT d[8] (1393:1393:1393) (1433:1433:1433)) + (PORT d[9] (1507:1507:1507) (1580:1580:1580)) + (PORT d[10] (1989:1989:1989) (2151:2151:2151)) + (PORT d[11] (984:984:984) (1056:1056:1056)) + (PORT d[12] (1373:1373:1373) (1504:1504:1504)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1765:1765:1765) (1766:1766:1766)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (2149:2149:2149) (2144:2144:2144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1208:1208:1208) (1250:1250:1250)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (982:982:982) (1038:1038:1038)) + (PORT d[1] (1268:1268:1268) (1296:1296:1296)) + (PORT d[2] (986:986:986) (1035:1035:1035)) + (PORT d[3] (2483:2483:2483) (2625:2625:2625)) + (PORT d[4] (952:952:952) (997:997:997)) + (PORT d[5] (941:941:941) (980:980:980)) + (PORT d[6] (1852:1852:1852) (1978:1978:1978)) + (PORT d[7] (1204:1204:1204) (1255:1255:1255)) + (PORT d[8] (1401:1401:1401) (1435:1435:1435)) + (PORT d[9] (1741:1741:1741) (1825:1825:1825)) + (PORT d[10] (1865:1865:1865) (2003:2003:2003)) + (PORT d[11] (1232:1232:1232) (1318:1318:1318)) + (PORT d[12] (1320:1320:1320) (1419:1419:1419)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1769:1769:1769) (1719:1719:1719)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2279:2279:2279) (2264:2264:2264)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1261:1261:1261) (1331:1331:1331)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2898:2898:2898) (3019:3019:3019)) + (PORT d[1] (2821:2821:2821) (2858:2858:2858)) + (PORT d[2] (2624:2624:2624) (2719:2719:2719)) + (PORT d[3] (1970:1970:1970) (2047:2047:2047)) + (PORT d[4] (3473:3473:3473) (3759:3759:3759)) + (PORT d[5] (3082:3082:3082) (3145:3145:3145)) + (PORT d[6] (2902:2902:2902) (3092:3092:3092)) + (PORT d[7] (959:959:959) (1001:1001:1001)) + (PORT d[8] (1452:1452:1452) (1486:1486:1486)) + (PORT d[9] (4507:4507:4507) (4803:4803:4803)) + (PORT d[10] (4180:4180:4180) (4510:4510:4510)) + (PORT d[11] (3619:3619:3619) (3841:3841:3841)) + (PORT d[12] (1413:1413:1413) (1419:1419:1419)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1999:1999:1999) (1945:1945:1945)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT d[0] (1398:1398:1398) (1357:1357:1357)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1280:1280:1280)) + (PORT datab (1494:1494:1494) (1568:1568:1568)) + (PORT datac (1577:1577:1577) (1632:1632:1632)) + (PORT datad (1335:1335:1335) (1350:1350:1350)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1473:1473:1473)) + (PORT datab (1277:1277:1277) (1374:1374:1374)) + (PORT datac (1953:1953:1953) (2048:2048:2048)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1296:1296:1296) (1366:1366:1366)) + (PORT clk (1862:1862:1862) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2673:2673:2673) (2781:2781:2781)) + (PORT d[1] (2244:2244:2244) (2356:2356:2356)) + (PORT d[2] (2750:2750:2750) (2894:2894:2894)) + (PORT d[3] (2861:2861:2861) (2992:2992:2992)) + (PORT d[4] (3687:3687:3687) (4010:4010:4010)) + (PORT d[5] (2963:2963:2963) (3074:3074:3074)) + (PORT d[6] (3293:3293:3293) (3400:3400:3400)) + (PORT d[7] (2712:2712:2712) (2857:2857:2857)) + (PORT d[8] (2331:2331:2331) (2442:2442:2442)) + (PORT d[9] (2661:2661:2661) (2840:2840:2840)) + (PORT d[10] (2024:2024:2024) (2216:2216:2216)) + (PORT d[11] (2375:2375:2375) (2507:2507:2507)) + (PORT d[12] (2201:2201:2201) (2391:2391:2391)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2044:2044:2044) (2083:2083:2083)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (PORT d[0] (3741:3741:3741) (3791:3791:3791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1226:1226:1226) (1240:1240:1240)) + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4206:4206:4206) (4343:4343:4343)) + (PORT d[1] (4289:4289:4289) (4496:4496:4496)) + (PORT d[2] (4252:4252:4252) (4350:4350:4350)) + (PORT d[3] (4244:4244:4244) (4337:4337:4337)) + (PORT d[4] (4164:4164:4164) (4250:4250:4250)) + (PORT d[5] (4168:4168:4168) (4329:4329:4329)) + (PORT d[6] (4273:4273:4273) (4568:4568:4568)) + (PORT d[7] (4280:4280:4280) (4385:4385:4385)) + (PORT d[8] (4234:4234:4234) (4215:4215:4215)) + (PORT d[9] (4134:4134:4134) (4185:4185:4185)) + (PORT d[10] (4052:4052:4052) (4112:4112:4112)) + (PORT d[11] (4145:4145:4145) (4217:4217:4217)) + (PORT d[12] (4307:4307:4307) (4292:4292:4292)) + (PORT clk (1823:1823:1823) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1827:1827:1827) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1828:1828:1828) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1939:1939:1939) (2003:2003:2003)) + (PORT d[1] (1588:1588:1588) (1605:1605:1605)) + (PORT d[2] (1420:1420:1420) (1454:1454:1454)) + (PORT d[3] (3510:3510:3510) (3709:3709:3709)) + (PORT d[4] (2090:2090:2090) (2225:2225:2225)) + (PORT d[5] (1955:1955:1955) (1979:1979:1979)) + (PORT d[6] (3427:3427:3427) (3618:3618:3618)) + (PORT d[7] (1722:1722:1722) (1745:1745:1745)) + (PORT d[8] (1287:1287:1287) (1309:1309:1309)) + (PORT d[9] (1315:1315:1315) (1359:1359:1359)) + (PORT d[10] (1227:1227:1227) (1265:1265:1265)) + (PORT d[11] (1728:1728:1728) (1816:1816:1816)) + (PORT d[12] (1556:1556:1556) (1630:1630:1630)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1383:1383:1383) (1400:1400:1400)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1551:1551:1551) (1614:1614:1614)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2400:2400:2400) (2498:2498:2498)) + (PORT d[1] (2515:2515:2515) (2622:2622:2622)) + (PORT d[2] (2765:2765:2765) (2930:2930:2930)) + (PORT d[3] (2539:2539:2539) (2707:2707:2707)) + (PORT d[4] (3975:3975:3975) (4317:4317:4317)) + (PORT d[5] (3017:3017:3017) (3162:3162:3162)) + (PORT d[6] (2528:2528:2528) (2645:2645:2645)) + (PORT d[7] (2410:2410:2410) (2549:2549:2549)) + (PORT d[8] (1835:1835:1835) (1906:1906:1906)) + (PORT d[9] (3321:3321:3321) (3533:3533:3533)) + (PORT d[10] (1998:1998:1998) (2203:2203:2203)) + (PORT d[11] (2703:2703:2703) (2835:2835:2835)) + (PORT d[12] (1934:1934:1934) (2122:2122:2122)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2022:2022:2022) (2001:2001:2001)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3471:3471:3471) (3424:3424:3424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1158:1158:1158)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4097:4097:4097) (4228:4228:4228)) + (PORT d[1] (4171:4171:4171) (4282:4282:4282)) + (PORT d[2] (4245:4245:4245) (4381:4381:4381)) + (PORT d[3] (4224:4224:4224) (4317:4317:4317)) + (PORT d[4] (4301:4301:4301) (4392:4392:4392)) + (PORT d[5] (4273:4273:4273) (4585:4585:4585)) + (PORT d[6] (4237:4237:4237) (4529:4529:4529)) + (PORT d[7] (4249:4249:4249) (4365:4365:4365)) + (PORT d[8] (4215:4215:4215) (4200:4200:4200)) + (PORT d[9] (4238:4238:4238) (4255:4255:4255)) + (PORT d[10] (4252:4252:4252) (4359:4359:4359)) + (PORT d[11] (4197:4197:4197) (4279:4279:4279)) + (PORT d[12] (4193:4193:4193) (4244:4244:4244)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2296:2296:2296) (2377:2377:2377)) + (PORT d[1] (2238:2238:2238) (2253:2253:2253)) + (PORT d[2] (2005:2005:2005) (2058:2058:2058)) + (PORT d[3] (1143:1143:1143) (1188:1188:1188)) + (PORT d[4] (2571:2571:2571) (2706:2706:2706)) + (PORT d[5] (2455:2455:2455) (2474:2474:2474)) + (PORT d[6] (3178:3178:3178) (3374:3374:3374)) + (PORT d[7] (1440:1440:1440) (1447:1447:1447)) + (PORT d[8] (1004:1004:1004) (1027:1027:1027)) + (PORT d[9] (974:974:974) (1023:1023:1023)) + (PORT d[10] (1781:1781:1781) (1851:1851:1851)) + (PORT d[11] (2257:2257:2257) (2360:2360:2360)) + (PORT d[12] (1252:1252:1252) (1336:1336:1336)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (1706:1706:1706) (1691:1691:1691)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1035:1035:1035)) + (PORT datab (950:950:950) (1006:1006:1006)) + (PORT datac (1437:1437:1437) (1476:1476:1476)) + (PORT datad (1573:1573:1573) (1642:1642:1642)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1533:1533:1533)) + (PORT datab (1166:1166:1166) (1241:1241:1241)) + (PORT datac (1663:1663:1663) (1805:1805:1805)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (842:842:842) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (374:374:374)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datad (262:262:262) (344:344:344)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3135:3135:3135) (3397:3397:3397)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (224:224:224) (297:297:297)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (300:300:300)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (297:297:297)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (341:341:341)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (224:224:224) (303:303:303)) + (PORT datad (225:225:225) (297:297:297)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (259:259:259)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datac (220:220:220) (297:297:297)) + (PORT datad (224:224:224) (295:295:295)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (375:375:375)) + (PORT datab (411:411:411) (475:475:475)) + (PORT datad (247:247:247) (328:328:328)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (374:374:374)) + (PORT datab (278:278:278) (374:374:374)) + (PORT datad (247:247:247) (329:329:329)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (386:386:386)) + (PORT datab (282:282:282) (377:377:377)) + (PORT datad (248:248:248) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (1759:1759:1759) (1782:1782:1782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (387:387:387)) + (PORT datab (280:280:280) (375:375:375)) + (PORT datad (246:246:246) (326:326:326)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (368:368:368)) + (PORT datab (273:273:273) (368:368:368)) + (PORT datac (3268:3268:3268) (3567:3567:3567)) + (PORT datad (260:260:260) (339:339:339)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (366:366:366)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (1111:1111:1111) (1164:1164:1164)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (3424:3424:3424) (3746:3746:3746)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (359:359:359) (419:419:419)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (610:610:610) (708:708:708)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1573:1573:1573) (1667:1667:1667)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (PORT ena (1223:1223:1223) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1433:1433:1433) (1472:1472:1472)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (974:974:974) (967:967:967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (1051:1051:1051) (1114:1114:1114)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1195:1195:1195) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1066:1066:1066) (1148:1148:1148)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (PORT ena (1534:1534:1534) (1521:1521:1521)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (771:771:771)) + (PORT datac (701:701:701) (780:780:780)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT asdata (1824:1824:1824) (1867:1867:1867)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (974:974:974) (967:967:967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (421:421:421) (489:489:489)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (PORT ena (974:974:974) (967:967:967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (820:820:820)) + (PORT datab (952:952:952) (1024:1024:1024)) + (PORT datac (700:700:700) (769:769:769)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (855:855:855)) + (PORT datab (1172:1172:1172) (1238:1238:1238)) + (PORT datac (254:254:254) (339:339:339)) + (PORT datad (690:690:690) (761:761:761)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (404:404:404)) + (PORT datab (433:433:433) (514:514:514)) + (PORT datad (1428:1428:1428) (1499:1499:1499)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3305:3305:3305) (3605:3605:3605)) + (PORT datab (210:210:210) (252:252:252)) + (PORT datac (1108:1108:1108) (1160:1160:1160)) + (PORT datad (600:600:600) (614:614:614)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (374:374:374)) + (PORT datab (729:729:729) (799:799:799)) + (PORT datac (269:269:269) (368:368:368)) + (PORT datad (1429:1429:1429) (1502:1502:1502)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (848:848:848)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1143:1143:1143) (1201:1201:1201)) + (PORT datad (410:410:410) (477:477:477)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (814:814:814)) + (PORT datab (238:238:238) (282:282:282)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1543:1543:1543)) + (PORT ena (1310:1310:1310) (1353:1353:1353)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (688:688:688) (764:764:764)) + (PORT datac (271:271:271) (373:373:373)) + (PORT datad (253:253:253) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (860:860:860)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (617:617:617) (663:663:663)) + (PORT datad (690:690:690) (766:766:766)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (780:780:780)) + (PORT datab (702:702:702) (774:774:774)) + (PORT datad (624:624:624) (660:660:660)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (412:412:412)) + (PORT datab (362:362:362) (393:393:393)) + (PORT datad (449:449:449) (525:525:525)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datab (690:690:690) (764:764:764)) + (PORT datac (269:269:269) (371:371:371)) + (PORT datad (252:252:252) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (713:713:713)) + (PORT datab (694:694:694) (775:775:775)) + (PORT datac (348:348:348) (371:371:371)) + (PORT datad (361:361:361) (377:377:377)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (487:487:487) (567:567:567)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (331:331:331)) + (PORT datab (1703:1703:1703) (1789:1789:1789)) + (PORT datac (2220:2220:2220) (2417:2417:2417)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (768:768:768)) + (PORT datac (706:706:706) (782:782:782)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (396:396:396)) + (PORT datab (365:365:365) (396:396:396)) + (PORT datad (448:448:448) (529:529:529)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1014:1014:1014)) + (PORT datab (1025:1025:1025) (1100:1100:1100)) + (PORT datac (636:636:636) (674:674:674)) + (PORT datad (924:924:924) (982:982:982)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1077:1077:1077)) + (PORT datab (1285:1285:1285) (1358:1358:1358)) + (PORT datad (679:679:679) (757:757:757)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (727:727:727)) + (PORT datab (209:209:209) (253:253:253)) + (PORT datad (607:607:607) (629:629:629)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (460:460:460)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datac (3820:3820:3820) (4056:4056:4056)) + (PORT datad (3190:3190:3190) (3353:3353:3353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT datac (692:692:692) (763:763:763)) + (PORT datad (405:405:405) (473:473:473)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1050:1050:1050)) + (PORT datab (1000:1000:1000) (1067:1067:1067)) + (PORT datac (941:941:941) (1012:1012:1012)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1054:1054:1054)) + (PORT datac (966:966:966) (1027:1027:1027)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (798:798:798)) + (PORT datac (941:941:941) (1012:1012:1012)) + (PORT datad (408:408:408) (471:471:471)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (744:744:744) (827:827:827)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (413:413:413)) + (PORT datab (688:688:688) (760:760:760)) + (PORT datac (208:208:208) (248:248:248)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT datab (748:748:748) (828:828:828)) + (PORT datac (850:850:850) (874:874:874)) + (PORT datad (944:944:944) (1031:1031:1031)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1012:1012:1012) (1076:1076:1076)) + (PORT datab (1283:1283:1283) (1355:1355:1355)) + (PORT datac (1018:1018:1018) (1116:1116:1116)) + (PORT datad (1034:1034:1034) (1136:1136:1136)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (389:389:389)) + (PORT datab (751:751:751) (815:815:815)) + (PORT datad (922:922:922) (962:962:962)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (742:742:742) (828:828:828)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT datab (759:759:759) (860:860:860)) + (PORT datac (665:665:665) (731:731:731)) + (PORT datad (1437:1437:1437) (1501:1501:1501)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (752:752:752) (815:815:815)) + (PORT datac (850:850:850) (870:870:870)) + (PORT datad (722:722:722) (789:789:789)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (385:385:385)) + (PORT datab (639:639:639) (659:659:659)) + (PORT datad (607:607:607) (620:620:620)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (364:364:364)) + (PORT datab (884:884:884) (949:949:949)) + (PORT datac (283:283:283) (376:376:376)) + (PORT datad (708:708:708) (783:783:783)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1106:1106:1106)) + (PORT datab (736:736:736) (805:805:805)) + (PORT datac (1090:1090:1090) (1130:1130:1130)) + (PORT datad (720:720:720) (811:811:811)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (853:853:853)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (927:927:927) (992:992:992)) + (PORT datac (666:666:666) (736:736:736)) + (PORT datad (728:728:728) (829:829:829)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (668:668:668)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datac (1502:1502:1502) (1547:1547:1547)) + (PORT datad (2003:2003:2003) (2105:2105:2105)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (1276:1276:1276) (1351:1351:1351)) + (PORT datad (676:676:676) (754:754:754)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (744:744:744)) + (PORT datab (395:395:395) (419:419:419)) + (PORT datac (608:608:608) (618:618:618)) + (PORT datad (963:963:963) (1021:1021:1021)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1009:1009:1009) (1076:1076:1076)) + (PORT datad (872:872:872) (888:888:888)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (862:862:862)) + (PORT datab (734:734:734) (802:802:802)) + (PORT datac (244:244:244) (326:326:326)) + (PORT datad (734:734:734) (809:809:809)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (380:380:380)) + (PORT datab (880:880:880) (941:941:941)) + (PORT datac (282:282:282) (372:372:372)) + (PORT datad (712:712:712) (787:787:787)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (418:418:418)) + (PORT datab (694:694:694) (767:767:767)) + (PORT datac (209:209:209) (247:247:247)) + (PORT datad (1432:1432:1432) (1505:1505:1505)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1105:1105:1105)) + (PORT datab (602:602:602) (613:613:613)) + (PORT datad (595:595:595) (611:611:611)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (487:487:487)) + (PORT datab (2116:2116:2116) (2266:2266:2266)) + (PORT datac (2005:2005:2005) (2080:2080:2080)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (604:604:604) (643:643:643)) + (PORT datad (609:609:609) (622:622:622)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1669:1669:1669) (1781:1781:1781)) + (PORT datab (940:940:940) (1028:1028:1028)) + (PORT datac (366:366:366) (397:397:397)) + (PORT datad (1092:1092:1092) (1158:1158:1158)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1640:1640:1640)) + (PORT datab (940:940:940) (1029:1029:1029)) + (PORT datac (363:363:363) (397:397:397)) + (PORT datad (1089:1089:1089) (1156:1156:1156)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1514:1514:1514)) + (PORT datab (1678:1678:1678) (1699:1699:1699)) + (PORT datac (1417:1417:1417) (1479:1479:1479)) + (PORT datad (1523:1523:1523) (1648:1648:1648)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (999:999:999) (1025:1025:1025)) + (PORT datac (324:324:324) (353:353:353)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (938:938:938)) + (PORT datab (1896:1896:1896) (1931:1931:1931)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (668:668:668) (746:746:746)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1445:1445:1445)) + (PORT datab (343:343:343) (378:378:378)) + (PORT datac (1483:1483:1483) (1532:1532:1532)) + (PORT datad (228:228:228) (276:276:276)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1476:1476:1476)) + (PORT datac (234:234:234) (287:287:287)) + (PORT datad (1064:1064:1064) (1107:1107:1107)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (970:970:970)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (382:382:382) (427:427:427)) + (PORT datad (246:246:246) (293:293:293)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1537:1537:1537)) + (PORT ena (1830:1830:1830) (1880:1880:1880)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1372:1372:1372)) + (PORT datab (1697:1697:1697) (1873:1873:1873)) + (PORT datac (1238:1238:1238) (1350:1350:1350)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1155:1155:1155)) + (PORT datab (1403:1403:1403) (1476:1476:1476)) + (PORT datac (1637:1637:1637) (1830:1830:1830)) + (PORT datad (1823:1823:1823) (1893:1893:1893)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (868:868:868)) + (PORT datab (861:861:861) (885:885:885)) + (PORT datac (1109:1109:1109) (1183:1183:1183)) + (PORT datad (610:610:610) (623:623:623)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1212:1212:1212)) + (PORT datab (361:361:361) (396:396:396)) + (PORT datac (606:606:606) (668:668:668)) + (PORT datad (1160:1160:1160) (1197:1197:1197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1989:1989:1989) (1994:1994:1994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (982:982:982)) + (PORT datad (1872:1872:1872) (2002:2002:2002)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (862:862:862)) + (PORT datab (268:268:268) (330:330:330)) + (PORT datac (708:708:708) (774:774:774)) + (PORT datad (248:248:248) (299:299:299)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1413:1413:1413)) + (PORT datab (635:635:635) (655:655:655)) + (PORT datac (1122:1122:1122) (1203:1203:1203)) + (PORT datad (1256:1256:1256) (1306:1306:1306)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1565:1565:1565) (1697:1697:1697)) + (PORT datac (888:888:888) (938:938:938)) + (PORT datad (2016:2016:2016) (2101:2101:2101)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT datab (702:702:702) (818:818:818)) + (PORT datad (715:715:715) (812:812:812)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (816:816:816)) + (PORT datab (270:270:270) (333:333:333)) + (PORT datac (808:808:808) (848:848:848)) + (PORT datad (257:257:257) (304:304:304)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1045:1045:1045)) + (PORT datab (636:636:636) (704:704:704)) + (PORT datad (1497:1497:1497) (1590:1590:1590)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_1\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (713:713:713)) + (PORT datab (576:576:576) (605:605:605)) + (PORT datac (883:883:883) (921:921:921)) + (PORT datad (805:805:805) (811:811:811)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (1550:1550:1550) (1651:1651:1651)) + (PORT datac (680:680:680) (734:734:734)) + (PORT datad (1158:1158:1158) (1170:1170:1170)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1200:1200:1200)) + (PORT datab (894:894:894) (916:916:916)) + (PORT datac (873:873:873) (909:909:909)) + (PORT datad (1138:1138:1138) (1154:1154:1154)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (898:898:898)) + (PORT datab (338:338:338) (369:369:369)) + (PORT datac (675:675:675) (703:703:703)) + (PORT datad (342:342:342) (362:362:362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (576:576:576) (587:587:587)) + (PORT datad (218:218:218) (252:252:252)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (320:320:320)) + (PORT datab (907:907:907) (965:965:965)) + (PORT datac (1409:1409:1409) (1433:1433:1433)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (992:992:992) (1036:1036:1036)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1011:1011:1011) (1077:1077:1077)) + (PORT d[1] (1051:1051:1051) (1117:1117:1117)) + (PORT d[2] (1284:1284:1284) (1340:1340:1340)) + (PORT d[3] (2196:2196:2196) (2345:2345:2345)) + (PORT d[4] (998:998:998) (1037:1037:1037)) + (PORT d[5] (1837:1837:1837) (1908:1908:1908)) + (PORT d[6] (1589:1589:1589) (1703:1703:1703)) + (PORT d[7] (1218:1218:1218) (1286:1286:1286)) + (PORT d[8] (1393:1393:1393) (1446:1446:1446)) + (PORT d[9] (1437:1437:1437) (1482:1482:1482)) + (PORT d[10] (1666:1666:1666) (1825:1825:1825)) + (PORT d[11] (754:754:754) (810:810:810)) + (PORT d[12] (1333:1333:1333) (1458:1458:1458)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1502:1502:1502) (1486:1486:1486)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1873:1873:1873) (1846:1846:1846)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (698:698:698) (718:718:718)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1287:1287:1287) (1368:1368:1368)) + (PORT d[1] (2235:2235:2235) (2359:2359:2359)) + (PORT d[2] (3681:3681:3681) (3911:3911:3911)) + (PORT d[3] (1915:1915:1915) (2049:2049:2049)) + (PORT d[4] (1279:1279:1279) (1357:1357:1357)) + (PORT d[5] (1826:1826:1826) (1906:1906:1906)) + (PORT d[6] (1307:1307:1307) (1388:1388:1388)) + (PORT d[7] (1539:1539:1539) (1600:1600:1600)) + (PORT d[8] (3549:3549:3549) (3752:3752:3752)) + (PORT d[9] (2040:2040:2040) (2159:2159:2159)) + (PORT d[10] (1814:1814:1814) (1946:1946:1946)) + (PORT d[11] (998:998:998) (1058:1058:1058)) + (PORT d[12] (1634:1634:1634) (1765:1765:1765)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1480:1480:1480) (1455:1455:1455)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1778:1778:1778) (1761:1761:1761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (2496:2496:2496) (2597:2597:2597)) + (PORT datac (662:662:662) (738:738:738)) + (PORT datad (1510:1510:1510) (1650:1650:1650)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1524:1524:1524)) + (PORT datab (1341:1341:1341) (1379:1379:1379)) + (PORT datac (639:639:639) (660:660:660)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (963:963:963)) + (PORT datab (1255:1255:1255) (1328:1328:1328)) + (PORT datac (939:939:939) (976:976:976)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1022:1022:1022) (1040:1040:1040)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1284:1284:1284) (1363:1363:1363)) + (PORT d[1] (2243:2243:2243) (2382:2382:2382)) + (PORT d[2] (1270:1270:1270) (1317:1317:1317)) + (PORT d[3] (2185:2185:2185) (2328:2328:2328)) + (PORT d[4] (1266:1266:1266) (1337:1337:1337)) + (PORT d[5] (1232:1232:1232) (1272:1272:1272)) + (PORT d[6] (1531:1531:1531) (1631:1631:1631)) + (PORT d[7] (1501:1501:1501) (1585:1585:1585)) + (PORT d[8] (3552:3552:3552) (3755:3755:3755)) + (PORT d[9] (2042:2042:2042) (2163:2163:2163)) + (PORT d[10] (1613:1613:1613) (1745:1745:1745)) + (PORT d[11] (972:972:972) (1026:1026:1026)) + (PORT d[12] (1338:1338:1338) (1468:1468:1468)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1436:1436:1436) (1380:1380:1380)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2014:2014:2014) (1988:1988:1988)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (987:987:987) (1008:1008:1008)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1297:1297:1297) (1364:1364:1364)) + (PORT d[1] (2268:2268:2268) (2410:2410:2410)) + (PORT d[2] (1289:1289:1289) (1339:1339:1339)) + (PORT d[3] (2463:2463:2463) (2609:2609:2609)) + (PORT d[4] (1254:1254:1254) (1311:1311:1311)) + (PORT d[5] (1863:1863:1863) (1939:1939:1939)) + (PORT d[6] (1561:1561:1561) (1671:1671:1671)) + (PORT d[7] (1191:1191:1191) (1256:1256:1256)) + (PORT d[8] (3553:3553:3553) (3756:3756:3756)) + (PORT d[9] (1457:1457:1457) (1522:1522:1522)) + (PORT d[10] (1653:1653:1653) (1795:1795:1795)) + (PORT d[11] (986:986:986) (1028:1028:1028)) + (PORT d[12] (1337:1337:1337) (1467:1467:1467)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1200:1200:1200) (1178:1178:1178)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2034:2034:2034) (2014:2014:2014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (960:960:960)) + (PORT datab (948:948:948) (965:965:965)) + (PORT datad (1456:1456:1456) (1522:1522:1522)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1736:1736:1736)) + (PORT datab (1984:1984:1984) (2027:2027:2027)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (319:319:319) (336:336:336)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2685:2685:2685) (2802:2802:2802)) + (PORT d[1] (2447:2447:2447) (2530:2530:2530)) + (PORT d[2] (2475:2475:2475) (2617:2617:2617)) + (PORT d[3] (2822:2822:2822) (2958:2958:2958)) + (PORT d[4] (3706:3706:3706) (4011:4011:4011)) + (PORT d[5] (2973:2973:2973) (3107:3107:3107)) + (PORT d[6] (2830:2830:2830) (2945:2945:2945)) + (PORT d[7] (2670:2670:2670) (2854:2854:2854)) + (PORT d[8] (2326:2326:2326) (2433:2433:2433)) + (PORT d[9] (2642:2642:2642) (2830:2830:2830)) + (PORT d[10] (2008:2008:2008) (2190:2190:2190)) + (PORT d[11] (2324:2324:2324) (2409:2409:2409)) + (PORT d[12] (1926:1926:1926) (2093:2093:2093)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (2798:2798:2798) (2863:2863:2863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1504:1504:1504) (1587:1587:1587)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2427:2427:2427) (2536:2536:2536)) + (PORT d[1] (2493:2493:2493) (2605:2605:2605)) + (PORT d[2] (3062:3062:3062) (3228:3228:3228)) + (PORT d[3] (2803:2803:2803) (3000:3000:3000)) + (PORT d[4] (3975:3975:3975) (4317:4317:4317)) + (PORT d[5] (2368:2368:2368) (2477:2477:2477)) + (PORT d[6] (2521:2521:2521) (2626:2626:2626)) + (PORT d[7] (2372:2372:2372) (2534:2534:2534)) + (PORT d[8] (2637:2637:2637) (2773:2773:2773)) + (PORT d[9] (3329:3329:3329) (3532:3532:3532)) + (PORT d[10] (2003:2003:2003) (2185:2185:2185)) + (PORT d[11] (2716:2716:2716) (2865:2865:2865)) + (PORT d[12] (1884:1884:1884) (2069:2069:2069)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1756:1756:1756) (1774:1774:1774)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (3419:3419:3419) (3446:3446:3446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1805:1805:1805)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1474:1474:1474) (1506:1506:1506)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4111:4111:4111) (4231:4231:4231)) + (PORT d[1] (4204:4204:4204) (4318:4318:4318)) + (PORT d[2] (4133:4133:4133) (4227:4227:4227)) + (PORT d[3] (4215:4215:4215) (4294:4294:4294)) + (PORT d[4] (4312:4312:4312) (4428:4428:4428)) + (PORT d[5] (4283:4283:4283) (4614:4614:4614)) + (PORT d[6] (4442:4442:4442) (4583:4583:4583)) + (PORT d[7] (4306:4306:4306) (4402:4402:4402)) + (PORT d[8] (4117:4117:4117) (4168:4168:4168)) + (PORT d[9] (4079:4079:4079) (4053:4053:4053)) + (PORT d[10] (4140:4140:4140) (4198:4198:4198)) + (PORT d[11] (4214:4214:4214) (4273:4273:4273)) + (PORT d[12] (4360:4360:4360) (4361:4361:4361)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1268:1268:1268) (1338:1338:1338)) + (PORT d[1] (2087:2087:2087) (2131:2131:2131)) + (PORT d[2] (1333:1333:1333) (1395:1395:1395)) + (PORT d[3] (2508:2508:2508) (2683:2683:2683)) + (PORT d[4] (1258:1258:1258) (1323:1323:1323)) + (PORT d[5] (938:938:938) (975:975:975)) + (PORT d[6] (965:965:965) (1011:1011:1011)) + (PORT d[7] (1193:1193:1193) (1252:1252:1252)) + (PORT d[8] (1402:1402:1402) (1454:1454:1454)) + (PORT d[9] (1216:1216:1216) (1259:1259:1259)) + (PORT d[10] (1990:1990:1990) (2152:2152:2152)) + (PORT d[11] (2250:2250:2250) (2333:2333:2333)) + (PORT d[12] (1379:1379:1379) (1516:1516:1516)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1867:1867:1867)) + (PORT d[0] (1359:1359:1359) (1357:1357:1357)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1868:1868:1868)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1639:1639:1639) (1727:1727:1727)) + (PORT clk (1860:1860:1860) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2991:2991:2991) (3120:3120:3120)) + (PORT d[1] (1923:1923:1923) (2019:2019:2019)) + (PORT d[2] (2737:2737:2737) (2892:2892:2892)) + (PORT d[3] (3280:3280:3280) (3407:3407:3407)) + (PORT d[4] (3688:3688:3688) (4011:4011:4011)) + (PORT d[5] (2963:2963:2963) (3075:3075:3075)) + (PORT d[6] (2544:2544:2544) (2644:2644:2644)) + (PORT d[7] (2403:2403:2403) (2572:2572:2572)) + (PORT d[8] (2331:2331:2331) (2443:2443:2443)) + (PORT d[9] (2375:2375:2375) (2547:2547:2547)) + (PORT d[10] (2035:2035:2035) (2222:2222:2222)) + (PORT d[11] (2411:2411:2411) (2566:2566:2566)) + (PORT d[12] (1697:1697:1697) (1874:1874:1874)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2056:2056:2056) (2030:2030:2030)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (PORT d[0] (3482:3482:3482) (3430:3430:3430)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1176:1176:1176) (1198:1198:1198)) + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4124:4124:4124) (4261:4261:4261)) + (PORT d[1] (4264:4264:4264) (4468:4468:4468)) + (PORT d[2] (4278:4278:4278) (4394:4394:4394)) + (PORT d[3] (4271:4271:4271) (4371:4371:4371)) + (PORT d[4] (4399:4399:4399) (4428:4428:4428)) + (PORT d[5] (4294:4294:4294) (4643:4643:4643)) + (PORT d[6] (4213:4213:4213) (4514:4514:4514)) + (PORT d[7] (4303:4303:4303) (4402:4402:4402)) + (PORT d[8] (4172:4172:4172) (4153:4153:4153)) + (PORT d[9] (4045:4045:4045) (4053:4053:4053)) + (PORT d[10] (4033:4033:4033) (4060:4060:4060)) + (PORT d[11] (4226:4226:4226) (4315:4315:4315)) + (PORT d[12] (4347:4347:4347) (4348:4348:4348)) + (PORT clk (1821:1821:1821) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (757:757:757)) + (PORT datab (1231:1231:1231) (1269:1269:1269)) + (PORT datac (1183:1183:1183) (1213:1213:1213)) + (PORT datad (1230:1230:1230) (1278:1278:1278)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1566:1566:1566) (1643:1643:1643)) + (PORT datab (278:278:278) (364:364:364)) + (PORT datac (1461:1461:1461) (1522:1522:1522)) + (PORT datad (327:327:327) (350:350:350)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1526:1526:1526)) + (PORT datab (2521:2521:2521) (2610:2610:2610)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (317:317:317) (338:338:338)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1509:1509:1509)) + (PORT datab (1183:1183:1183) (1226:1226:1226)) + (PORT datac (913:913:913) (955:955:955)) + (PORT datad (323:323:323) (340:340:340)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (690:690:690)) + (PORT datab (255:255:255) (314:314:314)) + (PORT datac (1482:1482:1482) (1530:1530:1530)) + (PORT datad (1924:1924:1924) (1963:1963:1963)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (291:291:291)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1126:1126:1126) (1179:1179:1179)) + (PORT datad (247:247:247) (293:293:293)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1537:1537:1537)) + (PORT ena (1830:1830:1830) (1880:1880:1880)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1430:1430:1430)) + (PORT datab (883:883:883) (913:913:913)) + (PORT datac (444:444:444) (520:520:520)) + (PORT datad (1160:1160:1160) (1200:1200:1200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1357:1357:1357)) + (PORT datab (1438:1438:1438) (1496:1496:1496)) + (PORT datac (939:939:939) (1039:1039:1039)) + (PORT datad (652:652:652) (679:679:679)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (899:899:899) (918:918:918)) + (PORT datad (1105:1105:1105) (1110:1110:1110)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1434:1434:1434) (1528:1528:1528)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1497:1497:1497)) + (PORT datab (1283:1283:1283) (1422:1422:1422)) + (PORT datac (1867:1867:1867) (1999:1999:1999)) + (PORT datad (1210:1210:1210) (1244:1244:1244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (964:964:964)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1162:1162:1162) (1203:1203:1203)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1348:1348:1348)) + (PORT datab (1574:1574:1574) (1640:1640:1640)) + (PORT datac (1220:1220:1220) (1284:1284:1284)) + (PORT datad (1936:1936:1936) (2038:2038:2038)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (996:996:996)) + (PORT datab (1524:1524:1524) (1592:1592:1592)) + (PORT datac (1213:1213:1213) (1250:1250:1250)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1162:1162:1162)) + (PORT datab (1201:1201:1201) (1247:1247:1247)) + (PORT datac (935:935:935) (980:980:980)) + (PORT datad (925:925:925) (986:986:986)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1907:1907:1907) (2042:2042:2042)) + (PORT datab (1314:1314:1314) (1413:1413:1413)) + (PORT datac (936:936:936) (977:977:977)) + (PORT datad (1184:1184:1184) (1249:1249:1249)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (955:955:955) (1015:1015:1015)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1030:1030:1030)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2757:2757:2757) (2871:2871:2871)) + (PORT d[1] (1970:1970:1970) (2094:2094:2094)) + (PORT d[2] (3675:3675:3675) (3898:3898:3898)) + (PORT d[3] (1552:1552:1552) (1634:1634:1634)) + (PORT d[4] (1575:1575:1575) (1673:1673:1673)) + (PORT d[5] (1806:1806:1806) (1887:1887:1887)) + (PORT d[6] (2818:2818:2818) (2928:2928:2928)) + (PORT d[7] (1458:1458:1458) (1559:1559:1559)) + (PORT d[8] (3243:3243:3243) (3423:3423:3423)) + (PORT d[9] (1741:1741:1741) (1834:1834:1834)) + (PORT d[10] (2020:2020:2020) (2229:2229:2229)) + (PORT d[11] (2722:2722:2722) (2820:2820:2820)) + (PORT d[12] (1639:1639:1639) (1788:1788:1788)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (917:917:917) (868:868:868)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2288:2288:2288) (2284:2284:2284)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT datab (469:469:469) (547:547:547)) + (PORT datac (720:720:720) (804:804:804)) + (PORT datad (697:697:697) (783:783:783)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1308:1308:1308)) + (PORT datab (771:771:771) (844:844:844)) + (PORT datac (855:855:855) (920:920:920)) + (PORT datad (720:720:720) (794:794:794)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (832:832:832)) + (PORT datac (850:850:850) (871:871:871)) + (PORT datad (920:920:920) (962:962:962)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (909:909:909)) + (PORT datad (360:360:360) (388:388:388)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (851:851:851)) + (PORT datab (315:315:315) (412:412:412)) + (PORT datac (855:855:855) (912:912:912)) + (PORT datad (413:413:413) (485:485:485)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (266:266:266)) + (PORT datab (890:890:890) (953:953:953)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (703:703:703) (779:779:779)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (333:333:333) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (647:647:647)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (759:759:759)) + (PORT datab (2119:2119:2119) (2270:2270:2270)) + (PORT datac (2006:2006:2006) (2083:2083:2083)) + (PORT datad (633:633:633) (687:687:687)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (864:864:864)) + (PORT datab (952:952:952) (1021:1021:1021)) + (PORT datac (699:699:699) (766:766:766)) + (PORT datad (1185:1185:1185) (1242:1242:1242)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (770:770:770)) + (PORT datac (703:703:703) (780:780:780)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (812:812:812)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (617:617:617) (666:666:666)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT datab (915:915:915) (932:932:932)) + (PORT datad (979:979:979) (1064:1064:1064)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (798:798:798)) + (PORT datad (947:947:947) (1024:1024:1024)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1059:1059:1059)) + (PORT datab (741:741:741) (828:828:828)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1054:1054:1054)) + (PORT datac (965:965:965) (1026:1026:1026)) + (PORT datad (706:706:706) (786:786:786)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1068:1068:1068)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (940:940:940) (1016:1016:1016)) + (PORT datad (666:666:666) (740:740:740)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (520:520:520)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (626:626:626) (649:649:649)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1106:1106:1106)) + (PORT datad (316:316:316) (334:334:334)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1077:1077:1077)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datac (1692:1692:1692) (1798:1798:1798)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1074:1074:1074)) + (PORT datab (1052:1052:1052) (1151:1151:1151)) + (PORT datac (1141:1141:1141) (1217:1217:1217)) + (PORT datad (909:909:909) (953:953:953)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (1285:1285:1285) (1358:1358:1358)) + (PORT datad (679:679:679) (757:757:757)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1184:1184:1184)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (911:911:911) (960:960:960)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1181:1181:1181)) + (PORT datab (1284:1284:1284) (1356:1356:1356)) + (PORT datac (981:981:981) (1036:1036:1036)) + (PORT datad (678:678:678) (757:757:757)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~72) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1186:1186:1186)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (348:348:348) (374:374:374)) + (PORT datad (909:909:909) (953:953:953)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~71) + (DELAY + (ABSOLUTE + (PORT datab (1172:1172:1172) (1252:1252:1252)) + (PORT datac (1019:1019:1019) (1120:1120:1120)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (859:859:859) (887:887:887)) + (PORT datac (911:911:911) (961:961:961)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (1009:1009:1009) (1072:1072:1072)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (751:751:751) (819:819:819)) + (PORT datad (920:920:920) (962:962:962)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (860:860:860)) + (PORT datab (546:546:546) (571:571:571)) + (PORT datac (617:617:617) (666:666:666)) + (PORT datad (690:690:690) (766:766:766)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (966:966:966)) + (PORT datab (1275:1275:1275) (1351:1351:1351)) + (PORT datac (1144:1144:1144) (1220:1220:1220)) + (PORT datad (1038:1038:1038) (1141:1141:1141)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (1005:1005:1005) (1070:1070:1070)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (3182:3182:3182) (3335:3335:3335)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (3843:3843:3843) (4045:4045:4045)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1226:1226:1226)) + (PORT datab (1274:1274:1274) (1325:1325:1325)) + (PORT datad (907:907:907) (925:925:925)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1107:1107:1107)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datad (978:978:978) (1063:1063:1063)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (862:862:862)) + (PORT datab (952:952:952) (1022:1022:1022)) + (PORT datac (615:615:615) (663:663:663)) + (PORT datad (522:522:522) (535:535:535)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (693:693:693)) + (PORT datab (762:762:762) (868:868:868)) + (PORT datad (371:371:371) (394:394:394)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (694:694:694) (749:749:749)) + (PORT datac (2243:2243:2243) (2311:2311:2311)) + (PORT datad (2170:2170:2170) (2360:2360:2360)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (575:575:575) (584:584:584)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1213:1213:1213)) + (PORT datab (1448:1448:1448) (1508:1508:1508)) + (PORT datac (1627:1627:1627) (1729:1729:1729)) + (PORT datad (1645:1645:1645) (1661:1661:1661)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1339:1339:1339)) + (PORT datab (964:964:964) (990:990:990)) + (PORT datac (1578:1578:1578) (1632:1632:1632)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (990:990:990) (1022:1022:1022)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2755:2755:2755) (2866:2866:2866)) + (PORT d[1] (1967:1967:1967) (2088:2088:2088)) + (PORT d[2] (3689:3689:3689) (3898:3898:3898)) + (PORT d[3] (1862:1862:1862) (1981:1981:1981)) + (PORT d[4] (1594:1594:1594) (1706:1706:1706)) + (PORT d[5] (1813:1813:1813) (1910:1910:1910)) + (PORT d[6] (2823:2823:2823) (2949:2949:2949)) + (PORT d[7] (1737:1737:1737) (1833:1833:1833)) + (PORT d[8] (3243:3243:3243) (3423:3423:3423)) + (PORT d[9] (3980:3980:3980) (4212:4212:4212)) + (PORT d[10] (1992:1992:1992) (2193:2193:2193)) + (PORT d[11] (1251:1251:1251) (1305:1305:1305)) + (PORT d[12] (1704:1704:1704) (1861:1861:1861)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1517:1517:1517) (1507:1507:1507)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2337:2337:2337) (2337:2337:2337)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1630:1630:1630)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2436:2436:2436) (2535:2535:2535)) + (PORT d[1] (1636:1636:1636) (1732:1732:1732)) + (PORT d[2] (3049:3049:3049) (3226:3226:3226)) + (PORT d[3] (2235:2235:2235) (2404:2404:2404)) + (PORT d[4] (3974:3974:3974) (4319:4319:4319)) + (PORT d[5] (3038:3038:3038) (3183:3183:3183)) + (PORT d[6] (2232:2232:2232) (2345:2345:2345)) + (PORT d[7] (2113:2113:2113) (2261:2261:2261)) + (PORT d[8] (2638:2638:2638) (2774:2774:2774)) + (PORT d[9] (3330:3330:3330) (3533:3533:3533)) + (PORT d[10] (1982:1982:1982) (2166:2166:2166)) + (PORT d[11] (2692:2692:2692) (2838:2838:2838)) + (PORT d[12] (1889:1889:1889) (2062:2062:2062)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1801:1801:1801) (1815:1815:1815)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (3133:3133:3133) (3156:3156:3156)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (922:922:922) (946:946:946)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4113:4113:4113) (4233:4233:4233)) + (PORT d[1] (4194:4194:4194) (4328:4328:4328)) + (PORT d[2] (4141:4141:4141) (4265:4265:4265)) + (PORT d[3] (4135:4135:4135) (4218:4218:4218)) + (PORT d[4] (4258:4258:4258) (4351:4351:4351)) + (PORT d[5] (4319:4319:4319) (4667:4667:4667)) + (PORT d[6] (4337:4337:4337) (4453:4453:4453)) + (PORT d[7] (4151:4151:4151) (4292:4292:4292)) + (PORT d[8] (4234:4234:4234) (4221:4221:4221)) + (PORT d[9] (4109:4109:4109) (4088:4088:4088)) + (PORT d[10] (4056:4056:4056) (4117:4117:4117)) + (PORT d[11] (4078:4078:4078) (4079:4079:4079)) + (PORT d[12] (4346:4346:4346) (4363:4363:4363)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2903:2903:2903) (3029:3029:3029)) + (PORT d[1] (3106:3106:3106) (3142:3142:3142)) + (PORT d[2] (2608:2608:2608) (2704:2704:2704)) + (PORT d[3] (1163:1163:1163) (1202:1202:1202)) + (PORT d[4] (2921:2921:2921) (3198:3198:3198)) + (PORT d[5] (3087:3087:3087) (3152:3152:3152)) + (PORT d[6] (3990:3990:3990) (4244:4244:4244)) + (PORT d[7] (1711:1711:1711) (1713:1713:1713)) + (PORT d[8] (3924:3924:3924) (4175:4175:4175)) + (PORT d[9] (4517:4517:4517) (4792:4792:4792)) + (PORT d[10] (1285:1285:1285) (1368:1368:1368)) + (PORT d[11] (3609:3609:3609) (3824:3824:3824)) + (PORT d[12] (952:952:952) (969:969:969)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1001:1001:1001) (954:954:954)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1387:1387:1387)) + (PORT datab (1523:1523:1523) (1625:1625:1625)) + (PORT datac (1467:1467:1467) (1536:1536:1536)) + (PORT datad (1160:1160:1160) (1184:1184:1184)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (947:947:947) (971:971:971)) + (PORT d[0] (698:698:698) (719:719:719)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -41760,19 +41335,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3042:3042:3042) (3290:3290:3290)) - (PORT d[1] (1608:1608:1608) (1696:1696:1696)) - (PORT d[2] (994:994:994) (1040:1040:1040)) - (PORT d[3] (946:946:946) (995:995:995)) - (PORT d[4] (1164:1164:1164) (1193:1193:1193)) - (PORT d[5] (957:957:957) (1004:1004:1004)) - (PORT d[6] (1556:1556:1556) (1674:1674:1674)) - (PORT d[7] (976:976:976) (1018:1018:1018)) - (PORT d[8] (1289:1289:1289) (1377:1377:1377)) - (PORT d[9] (775:775:775) (838:838:838)) - (PORT d[10] (729:729:729) (784:784:784)) - (PORT d[11] (2477:2477:2477) (2650:2650:2650)) - (PORT d[12] (1069:1069:1069) (1134:1134:1134)) + (PORT d[0] (2761:2761:2761) (2876:2876:2876)) + (PORT d[1] (1952:1952:1952) (2075:2075:2075)) + (PORT d[2] (3703:3703:3703) (3935:3935:3935)) + (PORT d[3] (1899:1899:1899) (2036:2036:2036)) + (PORT d[4] (1303:1303:1303) (1369:1369:1369)) + (PORT d[5] (1548:1548:1548) (1617:1617:1617)) + (PORT d[6] (1306:1306:1306) (1390:1390:1390)) + (PORT d[7] (1513:1513:1513) (1578:1578:1578)) + (PORT d[8] (3565:3565:3565) (3759:3759:3759)) + (PORT d[9] (2028:2028:2028) (2134:2134:2134)) + (PORT d[10] (1485:1485:1485) (1568:1568:1568)) + (PORT d[11] (977:977:977) (1034:1034:1034)) + (PORT d[12] (1635:1635:1635) (1784:1784:1784)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -41785,7 +41360,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (940:940:940) (896:896:896)) + (PORT d[0] (1429:1429:1429) (1388:1388:1388)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -41799,7 +41374,7 @@ (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2042:2042:2042) (2033:2033:2033)) + (PORT d[0] (1505:1505:1505) (1490:1490:1490)) ) ) ) @@ -41900,8 +41475,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1001:1001:1001) (1045:1045:1045)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (993:993:993) (1028:1028:1028)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) ) ) (TIMINGCHECK @@ -41913,20 +41488,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3024:3024:3024) (3251:3251:3251)) - (PORT d[1] (1903:1903:1903) (2000:2000:2000)) - (PORT d[2] (1280:1280:1280) (1322:1322:1322)) - (PORT d[3] (1267:1267:1267) (1318:1318:1318)) - (PORT d[4] (1471:1471:1471) (1527:1527:1527)) - (PORT d[5] (661:661:661) (688:688:688)) - (PORT d[6] (1836:1836:1836) (1967:1967:1967)) - (PORT d[7] (2929:2929:2929) (3085:3085:3085)) - (PORT d[8] (1275:1275:1275) (1340:1340:1340)) - (PORT d[9] (1006:1006:1006) (1059:1059:1059)) - (PORT d[10] (723:723:723) (773:773:773)) - (PORT d[11] (2518:2518:2518) (2677:2677:2677)) - (PORT d[12] (772:772:772) (836:836:836)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (2472:2472:2472) (2584:2584:2584)) + (PORT d[1] (1671:1671:1671) (1770:1770:1770)) + (PORT d[2] (3388:3388:3388) (3597:3597:3597)) + (PORT d[3] (1900:1900:1900) (2043:2043:2043)) + (PORT d[4] (1641:1641:1641) (1723:1723:1723)) + (PORT d[5] (2061:2061:2061) (2135:2135:2135)) + (PORT d[6] (1548:1548:1548) (1630:1630:1630)) + (PORT d[7] (1773:1773:1773) (1890:1890:1890)) + (PORT d[8] (3230:3230:3230) (3392:3392:3392)) + (PORT d[9] (3939:3939:3939) (4184:4184:4184)) + (PORT d[10] (1998:1998:1998) (2186:2186:2186)) + (PORT d[11] (2402:2402:2402) (2499:2499:2499)) + (PORT d[12] (1690:1690:1690) (1866:1866:1866)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -41938,8 +41513,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (942:942:942) (897:897:897)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1227:1227:1227) (1193:1193:1193)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -41951,8 +41526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (1808:1808:1808) (1808:1808:1808)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1775:1775:1775) (1781:1781:1781)) ) ) ) @@ -41961,7 +41536,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -41971,7 +41546,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -41981,7 +41556,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -41991,7 +41566,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -41999,4419 +41574,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1055:1055:1055) (1145:1145:1145)) - (PORT datab (960:960:960) (1036:1036:1036)) - (PORT datac (887:887:887) (907:907:907)) - (PORT datad (932:932:932) (969:969:969)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1406:1406:1406) (1432:1432:1432)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2471:2471:2471) (2605:2605:2605)) - (PORT d[1] (2523:2523:2523) (2576:2576:2576)) - (PORT d[2] (2567:2567:2567) (2747:2747:2747)) - (PORT d[3] (4593:4593:4593) (4820:4820:4820)) - (PORT d[4] (2930:2930:2930) (3056:3056:3056)) - (PORT d[5] (3148:3148:3148) (3203:3203:3203)) - (PORT d[6] (1481:1481:1481) (1477:1477:1477)) - (PORT d[7] (1396:1396:1396) (1430:1430:1430)) - (PORT d[8] (2490:2490:2490) (2615:2615:2615)) - (PORT d[9] (1697:1697:1697) (1729:1729:1729)) - (PORT d[10] (2540:2540:2540) (2643:2643:2643)) - (PORT d[11] (3702:3702:3702) (3993:3993:3993)) - (PORT d[12] (2490:2490:2490) (2565:2565:2565)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1996:1996:1996) (1955:1955:1955)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (1950:1950:1950) (1919:1919:1919)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1219:1219:1219)) - (PORT datab (1550:1550:1550) (1670:1670:1670)) - (PORT datac (349:349:349) (375:375:375)) - (PORT datad (1314:1314:1314) (1366:1366:1366)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1654:1654:1654)) - (PORT clk (1860:1860:1860) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2492:2492:2492) (2623:2623:2623)) - (PORT d[1] (2117:2117:2117) (2250:2250:2250)) - (PORT d[2] (2413:2413:2413) (2548:2548:2548)) - (PORT d[3] (2100:2100:2100) (2226:2226:2226)) - (PORT d[4] (2068:2068:2068) (2175:2175:2175)) - (PORT d[5] (2319:2319:2319) (2438:2438:2438)) - (PORT d[6] (2333:2333:2333) (2448:2448:2448)) - (PORT d[7] (3448:3448:3448) (3532:3532:3532)) - (PORT d[8] (2854:2854:2854) (2949:2949:2949)) - (PORT d[9] (2032:2032:2032) (2198:2198:2198)) - (PORT d[10] (3609:3609:3609) (3784:3784:3784)) - (PORT d[11] (2147:2147:2147) (2282:2282:2282)) - (PORT d[12] (1982:1982:1982) (2139:2139:2139)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1972:1972:1972) (1939:1939:1939)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1886:1886:1886)) - (PORT d[0] (3223:3223:3223) (3296:3296:3296)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2151:2151:2151) (2201:2201:2201)) - (PORT clk (1825:1825:1825) (1817:1817:1817)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4343:4343:4343) (4403:4403:4403)) - (PORT d[1] (4498:4498:4498) (4585:4585:4585)) - (PORT d[2] (4548:4548:4548) (4611:4611:4611)) - (PORT d[3] (4307:4307:4307) (4402:4402:4402)) - (PORT d[4] (4392:4392:4392) (4483:4483:4483)) - (PORT d[5] (4431:4431:4431) (4542:4542:4542)) - (PORT d[6] (4555:4555:4555) (4660:4660:4660)) - (PORT d[7] (4287:4287:4287) (4335:4335:4335)) - (PORT d[8] (4389:4389:4389) (4493:4493:4493)) - (PORT d[9] (4480:4480:4480) (4525:4525:4525)) - (PORT d[10] (4429:4429:4429) (4529:4529:4529)) - (PORT d[11] (4427:4427:4427) (4554:4554:4554)) - (PORT d[12] (4332:4332:4332) (4318:4318:4318)) - (PORT clk (1821:1821:1821) (1813:1813:1813)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1818:1818:1818)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1978:1978:1978) (2105:2105:2105)) - (PORT d[1] (2195:2195:2195) (2216:2216:2216)) - (PORT d[2] (2233:2233:2233) (2405:2405:2405)) - (PORT d[3] (1730:1730:1730) (1765:1765:1765)) - (PORT d[4] (2301:2301:2301) (2429:2429:2429)) - (PORT d[5] (2806:2806:2806) (2865:2865:2865)) - (PORT d[6] (1746:1746:1746) (1828:1828:1828)) - (PORT d[7] (1972:1972:1972) (2011:2011:2011)) - (PORT d[8] (2183:2183:2183) (2302:2302:2302)) - (PORT d[9] (2006:2006:2006) (2072:2072:2072)) - (PORT d[10] (2505:2505:2505) (2578:2578:2578)) - (PORT d[11] (4321:4321:4321) (4631:4631:4631)) - (PORT d[12] (2164:2164:2164) (2232:2232:2232)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (2147:2147:2147) (2137:2137:2137)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (978:978:978)) - (PORT datab (772:772:772) (880:880:880)) - (PORT datac (1200:1200:1200) (1239:1239:1239)) - (PORT datad (1667:1667:1667) (1720:1720:1720)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1483:1483:1483) (1518:1518:1518)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2205:2205:2205) (2306:2306:2306)) - (PORT d[1] (2632:2632:2632) (2785:2785:2785)) - (PORT d[2] (2362:2362:2362) (2492:2492:2492)) - (PORT d[3] (3051:3051:3051) (3158:3158:3158)) - (PORT d[4] (2271:2271:2271) (2411:2411:2411)) - (PORT d[5] (3452:3452:3452) (3554:3554:3554)) - (PORT d[6] (2543:2543:2543) (2661:2661:2661)) - (PORT d[7] (2952:2952:2952) (3038:3038:3038)) - (PORT d[8] (2643:2643:2643) (2727:2727:2727)) - (PORT d[9] (2971:2971:2971) (3112:3112:3112)) - (PORT d[10] (2322:2322:2322) (2378:2378:2378)) - (PORT d[11] (2215:2215:2215) (2364:2364:2364)) - (PORT d[12] (3539:3539:3539) (3735:3735:3735)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2575:2575:2575) (2593:2593:2593)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (3571:3571:3571) (3500:3500:3500)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2190:2190:2190) (2175:2175:2175)) - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4505:4505:4505) (4525:4525:4525)) - (PORT d[1] (4469:4469:4469) (4501:4501:4501)) - (PORT d[2] (4469:4469:4469) (4476:4476:4476)) - (PORT d[3] (4421:4421:4421) (4437:4437:4437)) - (PORT d[4] (4275:4275:4275) (4372:4372:4372)) - (PORT d[5] (4447:4447:4447) (4521:4521:4521)) - (PORT d[6] (4240:4240:4240) (4335:4335:4335)) - (PORT d[7] (4388:4388:4388) (4448:4448:4448)) - (PORT d[8] (4382:4382:4382) (4489:4489:4489)) - (PORT d[9] (4346:4346:4346) (4404:4404:4404)) - (PORT d[10] (4279:4279:4279) (4347:4347:4347)) - (PORT d[11] (4488:4488:4488) (4529:4529:4529)) - (PORT d[12] (4294:4294:4294) (4294:4294:4294)) - (PORT clk (1830:1830:1830) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2240:2240:2240) (2401:2401:2401)) - (PORT d[1] (1094:1094:1094) (1093:1093:1093)) - (PORT d[2] (2654:2654:2654) (2732:2732:2732)) - (PORT d[3] (4596:4596:4596) (4810:4810:4810)) - (PORT d[4] (1006:1006:1006) (1054:1054:1054)) - (PORT d[5] (2205:2205:2205) (2223:2223:2223)) - (PORT d[6] (2849:2849:2849) (2950:2950:2950)) - (PORT d[7] (1412:1412:1412) (1409:1409:1409)) - (PORT d[8] (2768:2768:2768) (2898:2898:2898)) - (PORT d[9] (1486:1486:1486) (1518:1518:1518)) - (PORT d[10] (2026:2026:2026) (2083:2083:2083)) - (PORT d[11] (3734:3734:3734) (3998:3998:3998)) - (PORT d[12] (1704:1704:1704) (1711:1711:1711)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1879:1879:1879)) - (PORT d[0] (1336:1336:1336) (1345:1345:1345)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1202:1202:1202)) - (PORT datab (947:947:947) (970:970:970)) - (PORT datac (998:998:998) (1057:1057:1057)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (772:772:772) (884:884:884)) - (PORT datac (1893:1893:1893) (1938:1938:1938)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (1727:1727:1727) (1787:1787:1787)) - (PORT datab (3006:3006:3006) (3258:3258:3258)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (966:966:966)) - (PORT datab (902:902:902) (924:924:924)) - (PORT datac (1649:1649:1649) (1666:1666:1666)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1288:1288:1288)) - (PORT datab (2963:2963:2963) (3072:3072:3072)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (1441:1441:1441) (1491:1491:1491)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1194:1194:1194)) - (PORT datab (424:424:424) (459:459:459)) - (PORT datac (371:371:371) (400:400:400)) - (PORT datad (1127:1127:1127) (1155:1155:1155)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (253:253:253) (299:299:299)) - (PORT datac (220:220:220) (264:264:264)) - (PORT datad (2132:2132:2132) (2201:2201:2201)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (1434:1434:1434) (1471:1471:1471)) - (PORT datac (1092:1092:1092) (1123:1123:1123)) - (PORT datad (217:217:217) (254:254:254)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (714:714:714) (741:741:741)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1683:1683:1683) (1793:1793:1793)) - (PORT datab (1366:1366:1366) (1396:1396:1396)) - (PORT datac (208:208:208) (251:251:251)) - (PORT datad (1331:1331:1331) (1338:1338:1338)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2302:2302:2302) (2437:2437:2437)) - (PORT datab (2181:2181:2181) (2361:2361:2361)) - (PORT datac (2247:2247:2247) (2350:2350:2350)) - (PORT datad (365:365:365) (398:398:398)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT datac (996:996:996) (1081:1081:1081)) - (PORT datad (1502:1502:1502) (1553:1553:1553)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (948:948:948)) - (PORT datab (1697:1697:1697) (1728:1728:1728)) - (PORT datac (1067:1067:1067) (1109:1109:1109)) - (PORT datad (812:812:812) (861:861:861)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (662:662:662)) - (PORT datab (1244:1244:1244) (1274:1274:1274)) - (PORT datad (871:871:871) (916:916:916)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1153:1153:1153)) - (PORT datab (609:609:609) (654:654:654)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (597:597:597) (613:613:613)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (719:719:719)) - (PORT datab (700:700:700) (775:775:775)) - (PORT datac (1424:1424:1424) (1508:1508:1508)) - (PORT datad (601:601:601) (661:661:661)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1234:1234:1234)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (610:610:610) (637:637:637)) - (PORT datad (772:772:772) (823:823:823)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1333:1333:1333)) - (PORT datab (390:390:390) (423:423:423)) - (PORT datac (956:956:956) (1024:1024:1024)) - (PORT datad (1355:1355:1355) (1444:1444:1444)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1284:1284:1284)) - (PORT datab (1539:1539:1539) (1640:1640:1640)) - (PORT datac (578:578:578) (588:588:588)) - (PORT datad (863:863:863) (880:880:880)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1463:1463:1463)) - (PORT datab (2126:2126:2126) (2263:2263:2263)) - (PORT datac (1615:1615:1615) (1658:1658:1658)) - (PORT datad (695:695:695) (742:742:742)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (791:791:791)) - (PORT datab (649:649:649) (670:670:670)) - (PORT datac (1593:1593:1593) (1630:1630:1630)) - (PORT datad (1465:1465:1465) (1570:1570:1570)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1216:1216:1216)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (PORT datab (627:627:627) (678:678:678)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (349:349:349) (364:364:364)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (874:874:874) (925:925:925)) - (PORT datac (570:570:570) (586:586:586)) - (PORT datad (809:809:809) (832:832:832)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (621:621:621)) - (PORT datab (601:601:601) (620:620:620)) - (PORT datac (899:899:899) (936:936:936)) - (PORT datad (809:809:809) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (297:297:297)) - (PORT datab (874:874:874) (928:928:928)) - (PORT datac (650:650:650) (693:693:693)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1133:1133:1133)) - (PORT datab (1173:1173:1173) (1212:1212:1212)) - (PORT datac (1315:1315:1315) (1328:1328:1328)) - (PORT datad (1358:1358:1358) (1425:1425:1425)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (661:661:661)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (851:851:851) (873:873:873)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (649:649:649)) - (PORT datac (630:630:630) (662:662:662)) - (PORT datad (838:838:838) (858:858:858)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (883:883:883) (909:909:909)) - (PORT datad (177:177:177) (203:203:203)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (910:910:910)) - (PORT datab (1157:1157:1157) (1201:1201:1201)) - (PORT datad (384:384:384) (414:414:414)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (573:573:573)) - (PORT datac (751:751:751) (825:825:825)) - (PORT datad (387:387:387) (454:454:454)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (764:764:764)) - (PORT datac (977:977:977) (1063:1063:1063)) - (PORT datad (614:614:614) (686:686:686)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (578:578:578) (587:587:587)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (774:774:774) (851:851:851)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1506:1506:1506) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1546:1546:1546) (1539:1539:1539)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) - (DELAY - (ABSOLUTE - (PORT datab (1813:1813:1813) (1930:1930:1930)) - (PORT datac (2265:2265:2265) (2466:2466:2466)) - (PORT datad (915:915:915) (970:970:970)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (422:422:422)) - (PORT datab (682:682:682) (750:750:750)) - (PORT datac (916:916:916) (978:978:978)) - (PORT datad (948:948:948) (1021:1021:1021)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (792:792:792)) - (PORT datab (793:793:793) (875:875:875)) - (PORT datac (1034:1034:1034) (1097:1097:1097)) - (PORT datad (738:738:738) (822:822:822)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (796:796:796)) - (PORT datab (792:792:792) (873:873:873)) - (PORT datac (1031:1031:1031) (1096:1096:1096)) - (PORT datad (735:735:735) (819:819:819)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (1063:1063:1063) (1131:1131:1131)) - (PORT datac (1262:1262:1262) (1333:1333:1333)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (816:816:816)) - (PORT datab (1297:1297:1297) (1371:1371:1371)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (812:812:812)) - (PORT datab (607:607:607) (611:611:611)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1507:1507:1507) (1521:1521:1521)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1547:1547:1547) (1540:1540:1540)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (837:837:837)) - (PORT datab (726:726:726) (804:804:804)) - (PORT datac (739:739:739) (817:817:817)) - (PORT datad (1023:1023:1023) (1086:1086:1086)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (995:995:995) (1074:1074:1074)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (522:522:522) (541:541:541)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1126:1126:1126)) - (PORT datac (461:461:461) (535:535:535)) - (PORT datad (928:928:928) (988:988:988)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (988:988:988)) - (PORT datab (945:945:945) (1001:1001:1001)) - (PORT datac (641:641:641) (696:696:696)) - (PORT datad (1431:1431:1431) (1449:1449:1449)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (281:281:281)) - (PORT datab (921:921:921) (969:969:969)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (591:591:591)) - (PORT datab (930:930:930) (1017:1017:1017)) - (PORT datac (753:753:753) (840:840:840)) - (PORT datad (703:703:703) (775:775:775)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (652:652:652) (674:674:674)) - (PORT datac (937:937:937) (1024:1024:1024)) - (PORT datad (888:888:888) (925:925:925)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (500:500:500) (572:572:572)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (594:594:594)) - (PORT datab (970:970:970) (1057:1057:1057)) - (PORT datac (753:753:753) (842:842:842)) - (PORT datad (702:702:702) (779:779:779)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (733:733:733) (820:820:820)) - (PORT datab (1305:1305:1305) (1362:1362:1362)) - (PORT datac (732:732:732) (817:817:817)) - (PORT datad (312:312:312) (329:329:329)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (767:767:767) (847:847:847)) - (PORT datac (462:462:462) (540:540:540)) - (PORT datad (925:925:925) (984:984:984)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (674:674:674)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (724:724:724)) - (PORT datab (669:669:669) (741:741:741)) - (PORT datac (672:672:672) (714:714:714)) - (PORT datad (1494:1494:1494) (1585:1585:1585)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (1299:1299:1299) (1375:1375:1375)) - (PORT datac (685:685:685) (784:784:784)) - (PORT datad (717:717:717) (806:806:806)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1291:1291:1291) (1397:1397:1397)) - (PORT datab (659:659:659) (682:682:682)) - (PORT datad (593:593:593) (616:616:616)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1401:1401:1401)) - (PORT datab (1016:1016:1016) (1083:1083:1083)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1509:1509:1509) (1524:1524:1524)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1550:1550:1550) (1542:1542:1542)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (2798:2798:2798) (3000:3000:3000)) - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (2352:2352:2352) (2576:2576:2576)) - (PORT datad (570:570:570) (582:582:582)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1278:1278:1278) (1317:1317:1317)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2420:2420:2420) (2614:2614:2614)) - (PORT d[1] (2542:2542:2542) (2641:2641:2641)) - (PORT d[2] (1265:1265:1265) (1333:1333:1333)) - (PORT d[3] (1256:1256:1256) (1301:1301:1301)) - (PORT d[4] (2037:2037:2037) (2116:2116:2116)) - (PORT d[5] (1268:1268:1268) (1326:1326:1326)) - (PORT d[6] (1448:1448:1448) (1473:1473:1473)) - (PORT d[7] (2668:2668:2668) (2814:2814:2814)) - (PORT d[8] (2486:2486:2486) (2658:2658:2658)) - (PORT d[9] (774:774:774) (839:839:839)) - (PORT d[10] (732:732:732) (787:787:787)) - (PORT d[11] (1198:1198:1198) (1240:1240:1240)) - (PORT d[12] (723:723:723) (773:773:773)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1249:1249:1249) (1220:1220:1220)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (1711:1711:1711) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1001:1001:1001) (1024:1024:1024)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2737:2737:2737) (2961:2961:2961)) - (PORT d[1] (1936:1936:1936) (2018:2018:2018)) - (PORT d[2] (998:998:998) (1029:1029:1029)) - (PORT d[3] (969:969:969) (994:994:994)) - (PORT d[4] (1425:1425:1425) (1469:1469:1469)) - (PORT d[5] (958:958:958) (992:992:992)) - (PORT d[6] (1158:1158:1158) (1170:1170:1170)) - (PORT d[7] (2950:2950:2950) (3104:3104:3104)) - (PORT d[8] (1588:1588:1588) (1675:1675:1675)) - (PORT d[9] (737:737:737) (777:777:777)) - (PORT d[10] (715:715:715) (752:752:752)) - (PORT d[11] (2487:2487:2487) (2667:2667:2667)) - (PORT d[12] (760:760:760) (814:814:814)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (948:948:948) (922:922:922)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (3281:3281:3281) (3342:3342:3342)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1192:1192:1192) (1163:1163:1163)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2546:2546:2546) (2729:2729:2729)) - (PORT d[1] (3618:3618:3618) (3824:3824:3824)) - (PORT d[2] (2381:2381:2381) (2458:2458:2458)) - (PORT d[3] (4288:4288:4288) (4492:4492:4492)) - (PORT d[4] (3170:3170:3170) (3405:3405:3405)) - (PORT d[5] (4727:4727:4727) (4889:4889:4889)) - (PORT d[6] (2532:2532:2532) (2627:2627:2627)) - (PORT d[7] (1392:1392:1392) (1407:1407:1407)) - (PORT d[8] (3122:3122:3122) (3282:3282:3282)) - (PORT d[9] (1802:1802:1802) (1840:1840:1840)) - (PORT d[10] (1997:1997:1997) (2034:2034:2034)) - (PORT d[11] (3401:3401:3401) (3659:3659:3659)) - (PORT d[12] (4693:4693:4693) (4992:4992:4992)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1888:1888:1888) (1943:1943:1943)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2445:2445:2445) (2405:2405:2405)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (983:983:983) (1077:1077:1077)) - (PORT datab (1231:1231:1231) (1326:1326:1326)) - (PORT datac (912:912:912) (954:954:954)) - (PORT datad (1090:1090:1090) (1094:1094:1094)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1370:1370:1370) (1410:1410:1410)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2461:2461:2461) (2613:2613:2613)) - (PORT d[1] (2479:2479:2479) (2511:2511:2511)) - (PORT d[2] (2577:2577:2577) (2775:2775:2775)) - (PORT d[3] (1707:1707:1707) (1744:1744:1744)) - (PORT d[4] (2415:2415:2415) (2564:2564:2564)) - (PORT d[5] (3183:3183:3183) (3261:3261:3261)) - (PORT d[6] (2218:2218:2218) (2320:2320:2320)) - (PORT d[7] (1719:1719:1719) (1754:1754:1754)) - (PORT d[8] (2452:2452:2452) (2554:2554:2554)) - (PORT d[9] (1710:1710:1710) (1761:1761:1761)) - (PORT d[10] (2530:2530:2530) (2628:2628:2628)) - (PORT d[11] (4031:4031:4031) (4326:4326:4326)) - (PORT d[12] (2475:2475:2475) (2545:2545:2545)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2002:2002:2002) (1964:1964:1964)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2204:2204:2204) (2160:2160:2160)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1636:1636:1636)) - (PORT datab (1198:1198:1198) (1226:1226:1226)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1384:1384:1384) (1422:1422:1422)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1498:1498:1498) (1529:1529:1529)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2502:2502:2502) (2600:2600:2600)) - (PORT d[1] (2280:2280:2280) (2376:2376:2376)) - (PORT d[2] (2063:2063:2063) (2187:2187:2187)) - (PORT d[3] (3319:3319:3319) (3431:3431:3431)) - (PORT d[4] (2302:2302:2302) (2458:2458:2458)) - (PORT d[5] (3776:3776:3776) (3885:3885:3885)) - (PORT d[6] (2525:2525:2525) (2638:2638:2638)) - (PORT d[7] (2494:2494:2494) (2555:2555:2555)) - (PORT d[8] (2947:2947:2947) (3049:3049:3049)) - (PORT d[9] (2749:2749:2749) (2863:2863:2863)) - (PORT d[10] (2929:2929:2929) (3041:3041:3041)) - (PORT d[11] (2742:2742:2742) (2907:2907:2907)) - (PORT d[12] (3512:3512:3512) (3716:3716:3716)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2834:2834:2834) (2862:2862:2862)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (3571:3571:3571) (3500:3500:3500)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2189:2189:2189) (2175:2175:2175)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4520:4520:4520) (4545:4545:4545)) - (PORT d[1] (4445:4445:4445) (4516:4516:4516)) - (PORT d[2] (4525:4525:4525) (4596:4596:4596)) - (PORT d[3] (4398:4398:4398) (4408:4408:4408)) - (PORT d[4] (4281:4281:4281) (4404:4404:4404)) - (PORT d[5] (4393:4393:4393) (4465:4465:4465)) - (PORT d[6] (4259:4259:4259) (4355:4355:4355)) - (PORT d[7] (4414:4414:4414) (4478:4478:4478)) - (PORT d[8] (4545:4545:4545) (4666:4666:4666)) - (PORT d[9] (4382:4382:4382) (4434:4434:4434)) - (PORT d[10] (4247:4247:4247) (4300:4300:4300)) - (PORT d[11] (4433:4433:4433) (4558:4558:4558)) - (PORT d[12] (4266:4266:4266) (4271:4271:4271)) - (PORT clk (1827:1827:1827) (1820:1820:1820)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1902:1902:1902) (2025:2025:2025)) - (PORT d[1] (1666:1666:1666) (1705:1705:1705)) - (PORT d[2] (1974:1974:1974) (2139:2139:2139)) - (PORT d[3] (1912:1912:1912) (1969:1969:1969)) - (PORT d[4] (2671:2671:2671) (2790:2790:2790)) - (PORT d[5] (2298:2298:2298) (2357:2357:2357)) - (PORT d[6] (1731:1731:1731) (1793:1793:1793)) - (PORT d[7] (2013:2013:2013) (2076:2076:2076)) - (PORT d[8] (1842:1842:1842) (1934:1934:1934)) - (PORT d[9] (2037:2037:2037) (2110:2110:2110)) - (PORT d[10] (1682:1682:1682) (1747:1747:1747)) - (PORT d[11] (4325:4325:4325) (4639:4639:4639)) - (PORT d[12] (1649:1649:1649) (1703:1703:1703)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (1818:1818:1818) (1849:1849:1849)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2479:2479:2479) (2628:2628:2628)) - (PORT d[1] (2661:2661:2661) (2805:2805:2805)) - (PORT d[2] (2218:2218:2218) (2383:2383:2383)) - (PORT d[3] (2113:2113:2113) (2258:2258:2258)) - (PORT d[4] (2079:2079:2079) (2164:2164:2164)) - (PORT d[5] (2439:2439:2439) (2558:2558:2558)) - (PORT d[6] (2443:2443:2443) (2606:2606:2606)) - (PORT d[7] (3431:3431:3431) (3496:3496:3496)) - (PORT d[8] (2846:2846:2846) (2932:2932:2932)) - (PORT d[9] (2326:2326:2326) (2495:2495:2495)) - (PORT d[10] (3304:3304:3304) (3449:3449:3449)) - (PORT d[11] (2127:2127:2127) (2238:2238:2238)) - (PORT d[12] (2274:2274:2274) (2444:2444:2444)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2586:2586:2586) (2674:2674:2674)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1617:1617:1617) (1708:1708:1708)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2779:2779:2779) (2918:2918:2918)) - (PORT d[1] (2949:2949:2949) (3110:3110:3110)) - (PORT d[2] (1977:1977:1977) (2112:2112:2112)) - (PORT d[3] (1867:1867:1867) (1994:1994:1994)) - (PORT d[4] (2099:2099:2099) (2223:2223:2223)) - (PORT d[5] (2640:2640:2640) (2717:2717:2717)) - (PORT d[6] (2148:2148:2148) (2291:2291:2291)) - (PORT d[7] (3421:3421:3421) (3502:3502:3502)) - (PORT d[8] (3155:3155:3155) (3258:3258:3258)) - (PORT d[9] (2282:2282:2282) (2439:2439:2439)) - (PORT d[10] (1914:1914:1914) (2041:2041:2041)) - (PORT d[11] (2100:2100:2100) (2231:2231:2231)) - (PORT d[12] (2417:2417:2417) (2564:2564:2564)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2032:2032:2032) (1996:1996:1996)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3200:3200:3200) (3274:3274:3274)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2121:2121:2121) (2166:2166:2166)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4469:4469:4469) (4578:4578:4578)) - (PORT d[1] (4411:4411:4411) (4529:4529:4529)) - (PORT d[2] (4405:4405:4405) (4501:4501:4501)) - (PORT d[3] (4285:4285:4285) (4378:4378:4378)) - (PORT d[4] (4390:4390:4390) (4479:4479:4479)) - (PORT d[5] (4452:4452:4452) (4565:4565:4565)) - (PORT d[6] (4355:4355:4355) (4476:4476:4476)) - (PORT d[7] (4330:4330:4330) (4373:4373:4373)) - (PORT d[8] (4626:4626:4626) (4732:4732:4732)) - (PORT d[9] (4460:4460:4460) (4519:4519:4519)) - (PORT d[10] (4392:4392:4392) (4490:4490:4490)) - (PORT d[11] (4393:4393:4393) (4515:4515:4515)) - (PORT d[12] (4353:4353:4353) (4336:4336:4336)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (978:978:978)) - (PORT datab (772:772:772) (879:879:879)) - (PORT datac (1450:1450:1450) (1528:1528:1528)) - (PORT datad (1149:1149:1149) (1208:1208:1208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1095:1095:1095)) - (PORT datab (1028:1028:1028) (1086:1086:1086)) - (PORT datac (1634:1634:1634) (1682:1682:1682)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (855:855:855)) - (PORT datab (1736:1736:1736) (1857:1857:1857)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (1727:1727:1727) (1788:1788:1788)) - (PORT datab (3006:3006:3006) (3259:3259:3259)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (952:952:952)) - (PORT datab (904:904:904) (927:927:927)) - (PORT datac (1645:1645:1645) (1661:1661:1661)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1251:1251:1251)) - (PORT datab (1465:1465:1465) (1529:1529:1529)) - (PORT datac (3210:3210:3210) (3305:3305:3305)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (424:424:424) (459:459:459)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1128:1128:1128) (1155:1155:1155)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (596:596:596) (602:602:602)) - (PORT datad (384:384:384) (411:411:411)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1558:1558:1558)) - (PORT ena (1917:1917:1917) (1918:1918:1918)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1731:1731:1731)) - (PORT datab (1942:1942:1942) (2048:2048:2048)) - (PORT datac (365:365:365) (407:407:407)) - (PORT datad (1162:1162:1162) (1219:1219:1219)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1545:1545:1545)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (849:849:849)) - (PORT datab (767:767:767) (837:837:837)) - (PORT datac (1838:1838:1838) (1974:1974:1974)) - (PORT datad (1691:1691:1691) (1759:1759:1759)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2118:2118:2118) (2286:2286:2286)) - (PORT datab (1408:1408:1408) (1515:1515:1515)) - (PORT datac (1119:1119:1119) (1147:1147:1147)) - (PORT datad (878:878:878) (904:904:904)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1656:1656:1656)) - (PORT datab (641:641:641) (673:673:673)) - (PORT datac (1029:1029:1029) (1091:1091:1091)) - (PORT datad (2619:2619:2619) (2695:2695:2695)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (1812:1812:1812) (1882:1882:1882)) - (PORT datab (1076:1076:1076) (1143:1143:1143)) - (PORT datac (829:829:829) (850:850:850)) - (PORT datad (2598:2598:2598) (2658:2658:2658)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (938:938:938)) - (PORT datab (1059:1059:1059) (1129:1129:1129)) - (PORT datac (1832:1832:1832) (1913:1913:1913)) - (PORT datad (626:626:626) (665:665:665)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1622:1622:1622) (1655:1655:1655)) - (PORT datab (2274:2274:2274) (2434:2434:2434)) - (PORT datac (617:617:617) (675:675:675)) - (PORT datad (986:986:986) (1083:1083:1083)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (768:768:768)) - (PORT datab (947:947:947) (968:968:968)) - (PORT datac (1488:1488:1488) (1481:1481:1481)) - (PORT datad (637:637:637) (690:690:690)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (645:645:645)) - (PORT datab (1172:1172:1172) (1176:1176:1176)) - (PORT datac (553:553:553) (580:580:580)) - (PORT datad (640:640:640) (656:656:656)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (501:501:501) (575:575:575)) - (PORT datad (632:632:632) (650:650:650)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (441:441:441)) - (PORT datab (383:383:383) (413:413:413)) - (PORT datad (188:188:188) (221:221:221)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (477:477:477)) - (PORT datab (947:947:947) (1001:1001:1001)) - (PORT datac (849:849:849) (861:861:861)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (595:595:595)) - (PORT datab (932:932:932) (1014:1014:1014)) - (PORT datac (754:754:754) (837:837:837)) - (PORT datad (707:707:707) (775:775:775)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (702:702:702)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (456:456:456) (525:525:525)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1504:1504:1504) (1518:1518:1518)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT datab (785:785:785) (866:866:866)) - (PORT datac (1271:1271:1271) (1329:1329:1329)) - (PORT datad (241:241:241) (310:310:310)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (818:818:818)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (729:729:729) (816:816:816)) - (PORT datad (620:620:620) (641:641:641)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (578:578:578)) - (PORT datab (1381:1381:1381) (1376:1376:1376)) - (PORT datad (316:316:316) (326:326:326)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1520:1520:1520)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1270:1270:1270) (1344:1344:1344)) - (PORT datab (912:912:912) (941:941:941)) - (PORT datac (606:606:606) (657:657:657)) - (PORT datad (645:645:645) (700:700:700)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (755:755:755)) - (PORT datab (722:722:722) (807:807:807)) - (PORT datac (1231:1231:1231) (1295:1295:1295)) - (PORT datad (1207:1207:1207) (1281:1281:1281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (647:647:647)) - (PORT datab (754:754:754) (844:844:844)) - (PORT datac (685:685:685) (783:783:783)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2314:2314:2314) (2533:2533:2533)) - (PORT datab (1430:1430:1430) (1559:1559:1559)) - (PORT datad (666:666:666) (718:718:718)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (401:401:401)) - (PORT datab (954:954:954) (1025:1025:1025)) - (PORT datac (1000:1000:1000) (1060:1060:1060)) - (PORT datad (711:711:711) (787:787:787)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1139:1139:1139)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (259:259:259) (337:337:337)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (440:440:440)) - (PORT datab (631:631:631) (657:657:657)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1505:1505:1505) (1519:1519:1519)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1537:1537:1537)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (653:653:653) (667:667:667)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1545:1545:1545) (1538:1538:1538)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (871:871:871)) - (PORT datab (612:612:612) (637:637:637)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1508:1508:1508) (1522:1522:1522)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1543:1543:1543) (1536:1536:1536)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (751:751:751)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datac (2427:2427:2427) (2603:2603:2603)) - (PORT datad (633:633:633) (684:684:684)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (622:622:622)) - (PORT datab (2465:2465:2465) (2646:2646:2646)) - (PORT datac (928:928:928) (975:975:975)) - (PORT datad (597:597:597) (633:633:633)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1204:1204:1204)) - (PORT datab (1206:1206:1206) (1216:1216:1216)) - (PORT datac (3269:3269:3269) (3535:3535:3535)) - (PORT datad (596:596:596) (633:633:633)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1025:1025:1025) (1033:1033:1033)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3329:3329:3329) (3586:3586:3586)) - (PORT d[1] (1573:1573:1573) (1649:1649:1649)) - (PORT d[2] (1037:1037:1037) (1080:1080:1080)) - (PORT d[3] (1599:1599:1599) (1696:1696:1696)) - (PORT d[4] (2959:2959:2959) (3149:3149:3149)) - (PORT d[5] (970:970:970) (999:999:999)) - (PORT d[6] (1576:1576:1576) (1694:1694:1694)) - (PORT d[7] (1281:1281:1281) (1303:1303:1303)) - (PORT d[8] (1219:1219:1219) (1280:1280:1280)) - (PORT d[9] (1098:1098:1098) (1184:1184:1184)) - (PORT d[10] (1037:1037:1037) (1112:1112:1112)) - (PORT d[11] (2217:2217:2217) (2342:2342:2342)) - (PORT d[12] (1083:1083:1083) (1173:1173:1173)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1145:1145:1145)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2363:2363:2363) (2340:2340:2340)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1004:1004:1004) (1015:1015:1015)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3337:3337:3337) (3609:3609:3609)) - (PORT d[1] (1306:1306:1306) (1388:1388:1388)) - (PORT d[2] (1698:1698:1698) (1789:1789:1789)) - (PORT d[3] (1595:1595:1595) (1675:1675:1675)) - (PORT d[4] (2970:2970:2970) (3138:3138:3138)) - (PORT d[5] (1270:1270:1270) (1328:1328:1328)) - (PORT d[6] (1305:1305:1305) (1402:1402:1402)) - (PORT d[7] (1331:1331:1331) (1362:1362:1362)) - (PORT d[8] (1550:1550:1550) (1637:1637:1637)) - (PORT d[9] (1103:1103:1103) (1195:1195:1195)) - (PORT d[10] (1045:1045:1045) (1128:1128:1128)) - (PORT d[11] (2177:2177:2177) (2321:2321:2321)) - (PORT d[12] (1373:1373:1373) (1464:1464:1464)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1223:1223:1223) (1198:1198:1198)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2348:2348:2348) (2353:2353:2353)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (956:956:956)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2672:2672:2672) (2905:2905:2905)) - (PORT d[1] (1536:1536:1536) (1605:1605:1605)) - (PORT d[2] (1356:1356:1356) (1434:1434:1434)) - (PORT d[3] (1321:1321:1321) (1406:1406:1406)) - (PORT d[4] (2655:2655:2655) (2825:2825:2825)) - (PORT d[5] (1588:1588:1588) (1655:1655:1655)) - (PORT d[6] (1518:1518:1518) (1625:1625:1625)) - (PORT d[7] (1580:1580:1580) (1612:1612:1612)) - (PORT d[8] (1535:1535:1535) (1634:1634:1634)) - (PORT d[9] (1648:1648:1648) (1754:1754:1754)) - (PORT d[10] (1343:1343:1343) (1445:1445:1445)) - (PORT d[11] (1880:1880:1880) (2005:2005:2005)) - (PORT d[12] (1391:1391:1391) (1503:1503:1503)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1260:1260:1260) (1255:1255:1255)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2386:2386:2386) (2419:2419:2419)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1837:1837:1837)) @@ -46425,7 +41587,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (995:995:995) (1000:1000:1000)) @@ -46434,7 +41596,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -46443,7 +41605,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -46453,7 +41615,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -46463,26 +41625,41 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~93) + (INSTANCE Selector14\~10) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (927:927:927)) - (PORT datab (1237:1237:1237) (1338:1338:1338)) - (PORT datad (912:912:912) (935:935:935)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (640:640:640) (669:669:669)) + (PORT datac (1123:1123:1123) (1187:1187:1187)) + (PORT datad (884:884:884) (922:922:922)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1339:1339:1339)) + (PORT datab (1293:1293:1293) (1367:1367:1367)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (215:215:215) (250:250:250)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1378:1378:1378) (1455:1455:1455)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1528:1528:1528) (1590:1590:1590)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -46491,23 +41668,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2978:2978:2978) (3192:3192:3192)) - (PORT d[1] (2894:2894:2894) (2985:2985:2985)) - (PORT d[2] (1003:1003:1003) (1051:1051:1051)) - (PORT d[3] (1298:1298:1298) (1337:1337:1337)) - (PORT d[4] (2072:2072:2072) (2172:2172:2172)) - (PORT d[5] (945:945:945) (991:991:991)) - (PORT d[6] (1183:1183:1183) (1217:1217:1217)) - (PORT d[7] (2655:2655:2655) (2814:2814:2814)) - (PORT d[8] (1565:1565:1565) (1650:1650:1650)) - (PORT d[9] (437:437:437) (473:473:473)) - (PORT d[10] (428:428:428) (460:460:460)) - (PORT d[11] (2780:2780:2780) (2977:2977:2977)) - (PORT d[12] (751:751:751) (792:792:792)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) + (PORT d[0] (2126:2126:2126) (2233:2233:2233)) + (PORT d[1] (1971:1971:1971) (2089:2089:2089)) + (PORT d[2] (3076:3076:3076) (3263:3263:3263)) + (PORT d[3] (2212:2212:2212) (2378:2378:2378)) + (PORT d[4] (4257:4257:4257) (4618:4618:4618)) + (PORT d[5] (3034:3034:3034) (3178:3178:3178)) + (PORT d[6] (2204:2204:2204) (2310:2310:2310)) + (PORT d[7] (2085:2085:2085) (2229:2229:2229)) + (PORT d[8] (2946:2946:2946) (3087:3087:3087)) + (PORT d[9] (3628:3628:3628) (3837:3837:3837)) + (PORT d[10] (1984:1984:1984) (2184:2184:2184)) + (PORT d[11] (2692:2692:2692) (2838:2838:2838)) + (PORT d[12] (1696:1696:1696) (1870:1870:1870)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -46516,11 +41693,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1248:1248:1248) (1217:1217:1217)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) + (PORT d[0] (1705:1705:1705) (1664:1664:1664)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -46529,60 +41706,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (1747:1747:1747) (1726:1726:1726)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) + (PORT d[0] (3157:3157:3157) (3128:3128:3128)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) + (PORT clk (1845:1845:1845) (1874:1874:1874)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) + (PORT clk (1799:1799:1799) (1798:1798:1798)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46593,65 +41770,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (999:999:999)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1205:1205:1205) (1303:1303:1303)) - (PORT datad (1455:1455:1455) (1474:1474:1474)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1180:1180:1180)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (1020:1020:1020) (1063:1063:1063)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) ) ) (TIMINGCHECK @@ -46660,23 +41783,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (3089:3089:3089) (3264:3264:3264)) - (PORT d[1] (2104:2104:2104) (2210:2210:2210)) - (PORT d[2] (1617:1617:1617) (1719:1719:1719)) - (PORT d[3] (1520:1520:1520) (1615:1615:1615)) - (PORT d[4] (2696:2696:2696) (2843:2843:2843)) - (PORT d[5] (1573:1573:1573) (1654:1654:1654)) - (PORT d[6] (1510:1510:1510) (1578:1578:1578)) - (PORT d[7] (1930:1930:1930) (1965:1965:1965)) - (PORT d[8] (3501:3501:3501) (3625:3625:3625)) - (PORT d[9] (1426:1426:1426) (1546:1546:1546)) - (PORT d[10] (1668:1668:1668) (1771:1771:1771)) - (PORT d[11] (1859:1859:1859) (1961:1961:1961)) - (PORT d[12] (1669:1669:1669) (1783:1783:1783)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) + (PORT d[0] (4176:4176:4176) (4333:4333:4333)) + (PORT d[1] (4220:4220:4220) (4394:4394:4394)) + (PORT d[2] (4160:4160:4160) (4244:4244:4244)) + (PORT d[3] (4208:4208:4208) (4285:4285:4285)) + (PORT d[4] (4178:4178:4178) (4279:4279:4279)) + (PORT d[5] (4295:4295:4295) (4600:4600:4600)) + (PORT d[6] (4240:4240:4240) (4537:4537:4537)) + (PORT d[7] (4386:4386:4386) (4494:4494:4494)) + (PORT d[8] (4221:4221:4221) (4224:4224:4224)) + (PORT d[9] (4068:4068:4068) (4043:4043:4043)) + (PORT d[10] (4099:4099:4099) (4152:4152:4152)) + (PORT d[11] (4177:4177:4177) (4257:4257:4257)) + (PORT d[12] (4299:4299:4299) (4300:4300:4300)) + (PORT clk (1805:1805:1805) (1800:1800:1800)) ) ) (TIMINGCHECK @@ -46685,174 +41808,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1494:1494:1494) (1487:1487:1487)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (2934:2934:2934) (2899:2899:2899)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1801:1801:1801)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1828:1828:1828) (1871:1871:1871)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4466:4466:4466) (4538:4538:4538)) - (PORT d[1] (4377:4377:4377) (4452:4452:4452)) - (PORT d[2] (4406:4406:4406) (4485:4485:4485)) - (PORT d[3] (4268:4268:4268) (4360:4360:4360)) - (PORT d[4] (4331:4331:4331) (4392:4392:4392)) - (PORT d[5] (4400:4400:4400) (4521:4521:4521)) - (PORT d[6] (4441:4441:4441) (4502:4502:4502)) - (PORT d[7] (4358:4358:4358) (4460:4460:4460)) - (PORT d[8] (4443:4443:4443) (4575:4575:4575)) - (PORT d[9] (4525:4525:4525) (4647:4647:4647)) - (PORT d[10] (4496:4496:4496) (4633:4633:4633)) - (PORT d[11] (4458:4458:4458) (4561:4561:4561)) - (PORT d[12] (4363:4363:4363) (4422:4422:4422)) - (PORT clk (1809:1809:1809) (1803:1803:1803)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (1810:1810:1810) (1805:1805:1805)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1805:1805:1805) (1803:1803:1803)) + (PORT clk (1801:1801:1801) (1800:1800:1800)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46863,11 +41871,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1223:1223:1223) (1232:1232:1232)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (1545:1545:1545) (1645:1645:1645)) + (PORT d[1] (1786:1786:1786) (1811:1811:1811)) + (PORT d[2] (1230:1230:1230) (1281:1281:1281)) + (PORT d[3] (2804:2804:2804) (2976:2976:2976)) + (PORT d[4] (2236:2236:2236) (2386:2386:2386)) + (PORT d[5] (1237:1237:1237) (1272:1272:1272)) + (PORT d[6] (1249:1249:1249) (1285:1285:1285)) + (PORT d[7] (1536:1536:1536) (1606:1606:1606)) + (PORT d[8] (1693:1693:1693) (1749:1749:1749)) + (PORT d[9] (1786:1786:1786) (1851:1851:1851)) + (PORT d[10] (2465:2465:2465) (2631:2631:2631)) + (PORT d[11] (1962:1962:1962) (2053:2053:2053)) + (PORT d[12] (1678:1678:1678) (1832:1832:1832)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -46876,98 +41896,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (3089:3089:3089) (3264:3264:3264)) - (PORT d[1] (1541:1541:1541) (1607:1607:1607)) - (PORT d[2] (1629:1629:1629) (1719:1719:1719)) - (PORT d[3] (1525:1525:1525) (1604:1604:1604)) - (PORT d[4] (2654:2654:2654) (2816:2816:2816)) - (PORT d[5] (1569:1569:1569) (1645:1645:1645)) - (PORT d[6] (1544:1544:1544) (1658:1658:1658)) - (PORT d[7] (1663:1663:1663) (1702:1702:1702)) - (PORT d[8] (1535:1535:1535) (1635:1635:1635)) - (PORT d[9] (1398:1398:1398) (1514:1514:1514)) - (PORT d[10] (1375:1375:1375) (1487:1487:1487)) - (PORT d[11] (1846:1846:1846) (1959:1959:1959)) - (PORT d[12] (1391:1391:1391) (1504:1504:1504)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1426:1426:1426) (1391:1391:1391)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (2602:2602:2602) (2625:2625:2625)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1650:1650:1650) (1633:1633:1633)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) + (PORT clk (1810:1810:1810) (1837:1837:1837)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46978,108 +41930,441 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1838:1838:1838) (1888:1888:1888)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4461:4461:4461) (4563:4563:4563)) - (PORT d[1] (4338:4338:4338) (4416:4416:4416)) - (PORT d[2] (4451:4451:4451) (4534:4534:4534)) - (PORT d[3] (4291:4291:4291) (4385:4385:4385)) - (PORT d[4] (4329:4329:4329) (4390:4390:4390)) - (PORT d[5] (4364:4364:4364) (4463:4463:4463)) - (PORT d[6] (4404:4404:4404) (4467:4467:4467)) - (PORT d[7] (4337:4337:4337) (4441:4441:4441)) - (PORT d[8] (4412:4412:4412) (4536:4536:4536)) - (PORT d[9] (4443:4443:4443) (4552:4552:4552)) - (PORT d[10] (4533:4533:4533) (4643:4643:4643)) - (PORT d[11] (4480:4480:4480) (4587:4587:4587)) - (PORT d[12] (4342:4342:4342) (4404:4404:4404)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) + (PORT clk (995:995:995) (1000:1000:1000)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1746:1746:1746) (1820:1820:1820)) + (PORT datab (1485:1485:1485) (1584:1584:1584)) + (PORT datac (1215:1215:1215) (1256:1256:1256)) + (PORT datad (1519:1519:1519) (1587:1587:1587)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1267:1267:1267)) + (PORT datab (1002:1002:1002) (1030:1030:1030)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~12) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (412:412:412)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector14\~14) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (2033:2033:2033) (2163:2163:2163)) + (PORT datac (1658:1658:1658) (1700:1700:1700)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (817:817:817)) + (PORT datab (922:922:922) (974:974:974)) + (PORT datac (1865:1865:1865) (1896:1896:1896)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (863:863:863)) + (PORT datab (1510:1510:1510) (1556:1556:1556)) + (PORT datac (1718:1718:1718) (1751:1751:1751)) + (PORT datad (221:221:221) (266:266:266)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (950:950:950)) + (PORT datab (941:941:941) (971:971:971)) + (PORT datac (1413:1413:1413) (1435:1435:1435)) + (PORT datad (185:185:185) (216:216:216)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (289:289:289)) + (PORT datab (810:810:810) (917:917:917)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (246:246:246) (291:291:291)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1537:1537:1537)) + (PORT ena (1830:1830:1830) (1880:1880:1880)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1124:1124:1124)) + (PORT datab (1097:1097:1097) (1224:1224:1224)) + (PORT datac (1683:1683:1683) (1781:1781:1781)) + (PORT datad (813:813:813) (831:831:831)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (800:800:800)) + (PORT datab (1895:1895:1895) (2026:2026:2026)) + (PORT datac (912:912:912) (969:969:969)) + (PORT datad (716:716:716) (798:798:798)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT datab (595:595:595) (607:607:607)) + (PORT datac (1169:1169:1169) (1195:1195:1195)) + (PORT datad (1205:1205:1205) (1277:1277:1277)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (2849:2849:2849) (2981:2981:2981)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (612:612:612) (667:667:667)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (417:417:417)) + (PORT datab (1372:1372:1372) (1537:1537:1537)) + (PORT datac (830:830:830) (908:908:908)) + (PORT datad (1751:1751:1751) (1871:1871:1871)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (931:931:931)) + (PORT datab (676:676:676) (711:711:711)) + (PORT datac (594:594:594) (611:611:611)) + (PORT datad (220:220:220) (255:255:255)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1594:1594:1594) (1660:1660:1660)) + (PORT datab (1090:1090:1090) (1141:1141:1141)) + (PORT datac (1822:1822:1822) (1903:1903:1903)) + (PORT datad (1765:1765:1765) (1819:1819:1819)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1793:1793:1793)) + (PORT datab (634:634:634) (686:686:686)) + (PORT datac (551:551:551) (565:565:565)) + (PORT datad (1062:1062:1062) (1098:1098:1098)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (849:849:849)) + (PORT datab (612:612:612) (637:637:637)) + (PORT datad (804:804:804) (811:811:811)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (714:714:714)) + (PORT datab (587:587:587) (608:608:608)) + (PORT datac (627:627:627) (662:662:662)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (896:896:896)) + (PORT datab (631:631:631) (645:645:645)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (616:616:616) (633:633:633)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (909:909:909)) + (PORT datab (565:565:565) (580:580:580)) + (PORT datac (680:680:680) (739:739:739)) + (PORT datad (1158:1158:1158) (1169:1169:1169)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (907:907:907)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (619:619:619) (640:640:640)) + (PORT datad (530:530:530) (553:553:553)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2135:2135:2135) (2270:2270:2270)) - (PORT d[1] (2360:2360:2360) (2503:2503:2503)) - (PORT d[2] (2439:2439:2439) (2591:2591:2591)) - (PORT d[3] (2316:2316:2316) (2447:2447:2447)) - (PORT d[4] (2038:2038:2038) (2142:2142:2142)) - (PORT d[5] (2419:2419:2419) (2559:2559:2559)) - (PORT d[6] (2470:2470:2470) (2638:2638:2638)) - (PORT d[7] (2535:2535:2535) (2601:2601:2601)) - (PORT d[8] (2536:2536:2536) (2603:2603:2603)) - (PORT d[9] (2337:2337:2337) (2521:2521:2521)) - (PORT d[10] (3019:3019:3019) (3165:3165:3165)) - (PORT d[11] (2078:2078:2078) (2172:2172:2172)) - (PORT d[12] (2284:2284:2284) (2462:2462:2462)) + (PORT d[0] (2928:2928:2928) (3051:3051:3051)) + (PORT d[1] (2140:2140:2140) (2224:2224:2224)) + (PORT d[2] (2635:2635:2635) (2784:2784:2784)) + (PORT d[3] (2334:2334:2334) (2472:2472:2472)) + (PORT d[4] (3404:3404:3404) (3708:3708:3708)) + (PORT d[5] (2606:2606:2606) (2712:2712:2712)) + (PORT d[6] (2839:2839:2839) (2959:2959:2959)) + (PORT d[7] (2698:2698:2698) (2890:2890:2890)) + (PORT d[8] (2083:2083:2083) (2170:2170:2170)) + (PORT d[9] (2545:2545:2545) (2691:2691:2691)) + (PORT d[10] (1989:1989:1989) (2190:2190:2190)) + (PORT d[11] (2288:2288:2288) (2411:2411:2411)) + (PORT d[12] (1889:1889:1889) (2049:2049:2049)) (PORT clk (1860:1860:1860) (1886:1886:1886)) ) ) @@ -47093,7 +42378,7 @@ (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1886:1886:1886)) - (PORT d[0] (2624:2624:2624) (2721:2721:2721)) + (PORT d[0] (2803:2803:2803) (2873:2873:2873)) ) ) ) @@ -47160,18 +42445,203 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1289:1289:1289)) - (PORT datab (720:720:720) (782:782:782)) - (PORT datac (933:933:933) (942:942:942)) - (PORT datad (1202:1202:1202) (1232:1232:1232)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (1668:1668:1668) (1774:1774:1774)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3743:3743:3743) (3863:3863:3863)) + (PORT d[1] (4648:4648:4648) (4797:4797:4797)) + (PORT d[2] (3048:3048:3048) (3144:3144:3144)) + (PORT d[3] (2913:2913:2913) (3163:3163:3163)) + (PORT d[4] (3168:3168:3168) (3439:3439:3439)) + (PORT d[5] (2928:2928:2928) (3013:3013:3013)) + (PORT d[6] (3347:3347:3347) (3516:3516:3516)) + (PORT d[7] (3863:3863:3863) (4045:4045:4045)) + (PORT d[8] (2699:2699:2699) (2873:2873:2873)) + (PORT d[9] (3273:3273:3273) (3490:3490:3490)) + (PORT d[10] (2329:2329:2329) (2567:2567:2567)) + (PORT d[11] (2347:2347:2347) (2456:2456:2456)) + (PORT d[12] (2339:2339:2339) (2564:2564:2564)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2208:2208:2208) (2241:2241:2241)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (4733:4733:4733) (4815:4815:4815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1821:1821:1821)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1411:1411:1411) (1426:1426:1426)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4143:4143:4143) (4264:4264:4264)) + (PORT d[1] (4254:4254:4254) (4440:4440:4440)) + (PORT d[2] (4182:4182:4182) (4230:4230:4230)) + (PORT d[3] (4296:4296:4296) (4320:4320:4320)) + (PORT d[4] (4153:4153:4153) (4183:4183:4183)) + (PORT d[5] (4181:4181:4181) (4349:4349:4349)) + (PORT d[6] (4208:4208:4208) (4379:4379:4379)) + (PORT d[7] (4392:4392:4392) (4575:4575:4575)) + (PORT d[8] (4170:4170:4170) (4217:4217:4217)) + (PORT d[9] (4183:4183:4183) (4269:4269:4269)) + (PORT d[10] (4224:4224:4224) (4268:4268:4268)) + (PORT d[11] (4207:4207:4207) (4284:4284:4284)) + (PORT d[12] (4185:4185:4185) (4246:4246:4246)) + (PORT clk (1831:1831:1831) (1823:1823:1823)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -47180,20 +42650,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2194:2194:2194) (2311:2311:2311)) - (PORT d[1] (2390:2390:2390) (2538:2538:2538)) - (PORT d[2] (2577:2577:2577) (2693:2693:2693)) - (PORT d[3] (3028:3028:3028) (3132:3132:3132)) - (PORT d[4] (1942:1942:1942) (2079:2079:2079)) - (PORT d[5] (3464:3464:3464) (3577:3577:3577)) - (PORT d[6] (2798:2798:2798) (2911:2911:2911)) - (PORT d[7] (3363:3363:3363) (3428:3428:3428)) - (PORT d[8] (2099:2099:2099) (2185:2185:2185)) - (PORT d[9] (3054:3054:3054) (3173:3173:3173)) - (PORT d[10] (2331:2331:2331) (2396:2396:2396)) - (PORT d[11] (2463:2463:2463) (2612:2612:2612)) - (PORT d[12] (3239:3239:3239) (3438:3438:3438)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (3526:3526:3526) (3702:3702:3702)) + (PORT d[1] (3723:3723:3723) (3811:3811:3811)) + (PORT d[2] (3391:3391:3391) (3505:3505:3505)) + (PORT d[3] (3482:3482:3482) (3740:3740:3740)) + (PORT d[4] (2925:2925:2925) (3167:3167:3167)) + (PORT d[5] (2710:2710:2710) (2783:2783:2783)) + (PORT d[6] (3126:3126:3126) (3315:3315:3315)) + (PORT d[7] (4490:4490:4490) (4722:4722:4722)) + (PORT d[8] (3321:3321:3321) (3511:3511:3511)) + (PORT d[9] (3931:3931:3931) (4159:4159:4159)) + (PORT d[10] (3169:3169:3169) (3461:3461:3461)) + (PORT d[11] (2978:2978:2978) (3135:3135:3135)) + (PORT d[12] (2055:2055:2055) (2281:2281:2281)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -47205,8 +42675,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1867:1867:1867) (1892:1892:1892)) - (PORT d[0] (2930:2930:2930) (2859:2859:2859)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (4473:4473:4473) (4350:4350:4350)) ) ) ) @@ -47215,7 +42685,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1868:1868:1868) (1893:1893:1893)) + (PORT clk (1855:1855:1855) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -47225,7 +42695,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1855:1855:1855)) + (PORT clk (1817:1817:1817) (1843:1843:1843)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -47239,7 +42709,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1015:1015:1015) (1018:1018:1018)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) ) ) ) @@ -47248,7 +42718,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) ) ) ) @@ -47257,7 +42727,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -47267,21 +42737,881 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1445:1445:1445) (1458:1458:1458)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3743:3743:3743) (3863:3863:3863)) + (PORT d[1] (4063:4063:4063) (4190:4190:4190)) + (PORT d[2] (3094:3094:3094) (3192:3192:3192)) + (PORT d[3] (3181:3181:3181) (3412:3412:3412)) + (PORT d[4] (3436:3436:3436) (3712:3712:3712)) + (PORT d[5] (2996:2996:2996) (3096:3096:3096)) + (PORT d[6] (3077:3077:3077) (3232:3232:3232)) + (PORT d[7] (4336:4336:4336) (4534:4534:4534)) + (PORT d[8] (3029:3029:3029) (3202:3202:3202)) + (PORT d[9] (3296:3296:3296) (3516:3516:3516)) + (PORT d[10] (2722:2722:2722) (3000:3000:3000)) + (PORT d[11] (2389:2389:2389) (2522:2522:2522)) + (PORT d[12] (2439:2439:2439) (2617:2617:2617)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2176:2176:2176) (2135:2135:2135)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (5094:5094:5094) (4987:4987:4987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1816:1816:1816)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1409:1409:1409) (1410:1410:1410)) + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4195:4195:4195) (4268:4268:4268)) + (PORT d[1] (4263:4263:4263) (4441:4441:4441)) + (PORT d[2] (4112:4112:4112) (4211:4211:4211)) + (PORT d[3] (4063:4063:4063) (4075:4075:4075)) + (PORT d[4] (4290:4290:4290) (4278:4278:4278)) + (PORT d[5] (4244:4244:4244) (4463:4463:4463)) + (PORT d[6] (4324:4324:4324) (4514:4514:4514)) + (PORT d[7] (4280:4280:4280) (4458:4458:4458)) + (PORT d[8] (4149:4149:4149) (4199:4199:4199)) + (PORT d[9] (4196:4196:4196) (4270:4270:4270)) + (PORT d[10] (4089:4089:4089) (4135:4135:4135)) + (PORT d[11] (4266:4266:4266) (4308:4308:4308)) + (PORT d[12] (4166:4166:4166) (4210:4210:4210)) + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1818:1818:1818)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (921:921:921)) + (PORT datab (1614:1614:1614) (1683:1683:1683)) + (PORT datac (1157:1157:1157) (1175:1175:1175)) + (PORT datad (1209:1209:1209) (1289:1289:1289)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1238:1238:1238)) + (PORT datab (1017:1017:1017) (1095:1095:1095)) + (PORT datac (1567:1567:1567) (1600:1600:1600)) + (PORT datad (583:583:583) (610:610:610)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (976:976:976) (1010:1010:1010)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2460:2460:2460) (2587:2587:2587)) + (PORT d[1] (2223:2223:2223) (2350:2350:2350)) + (PORT d[2] (3373:3373:3373) (3562:3562:3562)) + (PORT d[3] (2175:2175:2175) (2319:2319:2319)) + (PORT d[4] (4262:4262:4262) (4627:4627:4627)) + (PORT d[5] (2100:2100:2100) (2195:2195:2195)) + (PORT d[6] (1913:1913:1913) (1999:1999:1999)) + (PORT d[7] (2048:2048:2048) (2168:2168:2168)) + (PORT d[8] (2936:2936:2936) (3093:3093:3093)) + (PORT d[9] (3642:3642:3642) (3872:3872:3872)) + (PORT d[10] (1991:1991:1991) (2193:2193:2193)) + (PORT d[11] (2379:2379:2379) (2477:2477:2477)) + (PORT d[12] (1728:1728:1728) (1910:1910:1910)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1455:1455:1455) (1431:1431:1431)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (2137:2137:2137) (2149:2149:2149)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1134:1134:1134) (1138:1138:1138)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3520:3520:3520) (3692:3692:3692)) + (PORT d[1] (3450:3450:3450) (3536:3536:3536)) + (PORT d[2] (3680:3680:3680) (3802:3802:3802)) + (PORT d[3] (3797:3797:3797) (4073:4073:4073)) + (PORT d[4] (2880:2880:2880) (3122:3122:3122)) + (PORT d[5] (2707:2707:2707) (2778:2778:2778)) + (PORT d[6] (3391:3391:3391) (3597:3597:3597)) + (PORT d[7] (4783:4783:4783) (5030:5030:5030)) + (PORT d[8] (3602:3602:3602) (3844:3844:3844)) + (PORT d[9] (3887:3887:3887) (4153:4153:4153)) + (PORT d[10] (3443:3443:3443) (3750:3750:3750)) + (PORT d[11] (2968:2968:2968) (3140:3140:3140)) + (PORT d[12] (2374:2374:2374) (2602:2602:2602)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1699:1699:1699) (1624:1624:1624)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2921:2921:2921) (2925:2925:2925)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1377:1377:1377) (1441:1441:1441)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (987:987:987) (1047:1047:1047)) + (PORT d[1] (2064:2064:2064) (2106:2106:2106)) + (PORT d[2] (1298:1298:1298) (1364:1364:1364)) + (PORT d[3] (3371:3371:3371) (3575:3575:3575)) + (PORT d[4] (2292:2292:2292) (2462:2462:2462)) + (PORT d[5] (974:974:974) (1033:1033:1033)) + (PORT d[6] (947:947:947) (1006:1006:1006)) + (PORT d[7] (1221:1221:1221) (1288:1288:1288)) + (PORT d[8] (1433:1433:1433) (1495:1495:1495)) + (PORT d[9] (1491:1491:1491) (1540:1540:1540)) + (PORT d[10] (2477:2477:2477) (2659:2659:2659)) + (PORT d[11] (2032:2032:2032) (2130:2130:2130)) + (PORT d[12] (1353:1353:1353) (1487:1487:1487)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1840:1840:1840) (1816:1816:1816)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (2541:2541:2541) (2551:2551:2551)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1541:1541:1541) (1571:1571:1571)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2889:2889:2889) (2997:2997:2997)) + (PORT d[1] (2815:2815:2815) (2842:2842:2842)) + (PORT d[2] (2616:2616:2616) (2696:2696:2696)) + (PORT d[3] (868:868:868) (909:909:909)) + (PORT d[4] (2574:2574:2574) (2776:2776:2776)) + (PORT d[5] (3047:3047:3047) (3091:3091:3091)) + (PORT d[6] (3224:3224:3224) (3407:3407:3407)) + (PORT d[7] (1426:1426:1426) (1450:1450:1450)) + (PORT d[8] (1166:1166:1166) (1200:1200:1200)) + (PORT d[9] (971:971:971) (1015:1015:1015)) + (PORT d[10] (940:940:940) (998:998:998)) + (PORT d[11] (2860:2860:2860) (2986:2986:2986)) + (PORT d[12] (998:998:998) (1031:1031:1031)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2730:2730:2730) (2688:2688:2688)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2742:2742:2742) (2694:2694:2694)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~91) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) (DELAY (ABSOLUTE - (PORT dataa (897:897:897) (931:931:931)) - (PORT datab (1317:1317:1317) (1343:1343:1343)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (1569:1569:1569) (1584:1584:1584)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1611:1611:1611) (1693:1693:1693)) + (PORT datab (1406:1406:1406) (1506:1506:1506)) + (PORT datac (1205:1205:1205) (1260:1260:1260)) + (PORT datad (1417:1417:1417) (1454:1454:1454)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -47290,47 +43620,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~92) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) (DELAY (ABSOLUTE - (PORT dataa (975:975:975) (990:990:990)) - (PORT datab (721:721:721) (781:781:781)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1441:1441:1441) (1485:1485:1485)) + (PORT datab (1374:1374:1374) (1443:1443:1443)) + (PORT datac (2039:2039:2039) (2108:2108:2108)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~125) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (2570:2570:2570) (2815:2815:2815)) - (PORT datab (1396:1396:1396) (1468:1468:1468)) - (PORT datac (570:570:570) (585:585:585)) - (PORT datad (318:318:318) (337:337:337)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (976:976:976)) - (PORT datab (920:920:920) (940:940:940)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (632:632:632) (657:657:657)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (768:768:768) (853:853:853)) + (PORT datab (1174:1174:1174) (1239:1239:1239)) + (PORT datac (706:706:706) (772:772:772)) + (PORT datad (689:689:689) (755:755:755)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47338,29 +43652,2111 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~111) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~114) (DELAY (ABSOLUTE - (PORT dataa (2246:2246:2246) (2318:2318:2318)) - (PORT datab (436:436:436) (473:473:473)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1262:1262:1262) (1331:1331:1331)) + (PORT dataa (1137:1137:1137) (1156:1156:1156)) + (PORT datab (1472:1472:1472) (1540:1540:1540)) + (PORT datac (981:981:981) (1055:1055:1055)) + (PORT datad (1251:1251:1251) (1333:1333:1333)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (985:985:985)) + (PORT datab (768:768:768) (869:869:869)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (273:273:273) (358:358:358)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1797:1797:1797) (1916:1916:1916)) + (PORT datab (1194:1194:1194) (1255:1255:1255)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (643:643:643) (698:698:698)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (344:344:344)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (355:355:355)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (337:337:337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_Count\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (693:693:693) (756:756:756)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston_autofire_button\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (481:481:481) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~7) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (359:359:359)) + (PORT datac (233:233:233) (318:318:318)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (358:358:358)) + (PORT datab (261:261:261) (349:349:349)) + (PORT datac (340:340:340) (362:362:362)) + (PORT datad (392:392:392) (452:452:452)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (960:960:960)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (234:234:234) (318:318:318)) + (PORT datad (235:235:235) (314:314:314)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (262:262:262) (352:352:352)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (234:234:234) (312:312:312)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (494:494:494)) + (PORT datab (399:399:399) (465:465:465)) + (PORT datac (3381:3381:3381) (3693:3693:3693)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_Count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (1114:1114:1114) (1160:1160:1160)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~4) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (341:341:341)) + (PORT datab (250:250:250) (335:335:335)) + (PORT datac (223:223:223) (301:301:301)) + (PORT datad (225:225:225) (297:297:297)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~5) + (DELAY + (ABSOLUTE + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~2) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (792:792:792)) + (PORT datab (418:418:418) (487:487:487)) + (PORT datac (231:231:231) (318:318:318)) + (PORT datad (233:233:233) (310:310:310)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~0) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (354:354:354)) + (PORT datab (260:260:260) (348:348:348)) + (PORT datac (232:232:232) (315:315:315)) + (PORT datad (232:232:232) (308:308:308)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~1) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (357:357:357)) + (PORT datab (260:260:260) (347:347:347)) + (PORT datac (232:232:232) (315:315:315)) + (PORT datad (636:636:636) (689:689:689)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~3) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (581:581:581)) + (PORT datab (635:635:635) (654:654:654)) + (PORT datac (525:525:525) (535:535:535)) + (PORT datad (605:605:605) (621:621:621)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE debounce_autofire\|r_State\~6) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (664:664:664)) + (PORT datab (3428:3428:3428) (3730:3730:3730)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE debounce_autofire\|r_State) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1733:1733:1733)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_autofire_enabled\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_autofire_enabled) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (809:809:809)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (517:517:517)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (251:251:251) (337:337:337)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (263:263:263) (346:346:346)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[6\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[7\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[8\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (350:350:350)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1022:1022:1022) (1063:1063:1063)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[9\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (334:334:334)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[10\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[11\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[12\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[13\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[14\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[15\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (468:468:468)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (393:393:393) (466:466:466)) + (PORT datac (224:224:224) (303:303:303)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (514:514:514)) + (PORT datab (254:254:254) (340:340:340)) + (PORT datac (226:226:226) (306:306:306)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (380:380:380) (441:441:441)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (226:226:226) (307:307:307)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (625:625:625) (639:639:639)) + (PORT datad (554:554:554) (566:566:566)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[16\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (339:339:339)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire_counter\[17\]\~49) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire_counter\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1311:1311:1311) (1346:1346:1346)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE kempston_auto_fire\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (377:377:377)) + (PORT datab (254:254:254) (340:340:340)) + (PORT datad (226:226:226) (297:297:297)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE kempston_auto_fire) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT sload (1334:1334:1334) (1310:1310:1310)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (968:968:968)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1399:1399:1399) (1464:1464:1464)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (806:806:806)) + (PORT datab (929:929:929) (992:992:992)) + (PORT datac (947:947:947) (1006:1006:1006)) + (PORT datad (959:959:959) (1016:1016:1016)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (632:632:632)) + (PORT datab (761:761:761) (866:866:866)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (821:821:821)) + (PORT datab (904:904:904) (984:984:984)) + (PORT datac (713:713:713) (823:823:823)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (370:370:370)) + (PORT datab (694:694:694) (775:775:775)) + (PORT datac (932:932:932) (990:990:990)) + (PORT datad (361:361:361) (379:379:379)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1079:1079:1079)) + (PORT datab (762:762:762) (865:865:865)) + (PORT datad (604:604:604) (616:616:616)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (329:329:329)) + (PORT datab (2128:2128:2128) (2313:2313:2313)) + (PORT datac (2500:2500:2500) (2555:2555:2555)) + (PORT datad (217:217:217) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (856:856:856)) + (PORT datab (312:312:312) (410:410:410)) + (PORT datac (1479:1479:1479) (1523:1523:1523)) + (PORT datad (700:700:700) (762:762:762)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (889:889:889) (952:952:952)) + (PORT datad (736:736:736) (810:810:810)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (633:633:633)) + (PORT datab (632:632:632) (654:654:654)) + (PORT datad (978:978:978) (1057:1057:1057)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (822:822:822)) + (PORT datab (470:470:470) (544:544:544)) + (PORT datad (756:756:756) (855:855:855)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (962:962:962)) + (PORT datab (749:749:749) (825:825:825)) + (PORT datac (282:282:282) (375:375:375)) + (PORT datad (721:721:721) (811:811:811)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (425:425:425)) + (PORT datab (762:762:762) (839:839:839)) + (PORT datac (718:718:718) (801:801:801)) + (PORT datad (593:593:593) (606:606:606)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (728:728:728)) + (PORT datab (2339:2339:2339) (2440:2440:2440)) + (PORT datac (642:642:642) (700:700:700)) + (PORT datad (1959:1959:1959) (2162:2162:2162)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (396:396:396)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datad (247:247:247) (318:318:318)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (431:431:431)) + (PORT datab (885:885:885) (953:953:953)) + (PORT datac (395:395:395) (473:473:473)) + (PORT datad (758:758:758) (860:860:860)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT datab (723:723:723) (799:799:799)) + (PORT datad (690:690:690) (778:778:778)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (749:749:749)) + (PORT datac (706:706:706) (770:770:770)) + (PORT datad (959:959:959) (1016:1016:1016)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (653:653:653)) + (PORT datab (352:352:352) (386:386:386)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (908:908:908)) + (PORT datab (2246:2246:2246) (2362:2362:2362)) + (PORT datac (951:951:951) (1027:1027:1027)) + (PORT datad (1730:1730:1730) (1779:1779:1779)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (939:939:939)) + (PORT datab (843:843:843) (855:855:855)) + (PORT datac (822:822:822) (850:850:850)) + (PORT datad (598:598:598) (628:628:628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~6) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (651:651:651)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (876:876:876) (892:892:892)) + (PORT datad (1680:1680:1680) (1783:1783:1783)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~7) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (842:842:842) (848:848:848)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1506:1506:1506)) + (PORT datab (1115:1115:1115) (1223:1223:1223)) + (PORT datac (1237:1237:1237) (1260:1260:1260)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1678:1678:1678) (1784:1784:1784)) - (PORT datab (426:426:426) (465:465:465)) - (PORT datac (536:536:536) (545:545:545)) - (PORT datad (1131:1131:1131) (1161:1161:1161)) + (PORT dataa (1046:1046:1046) (1089:1089:1089)) + (PORT datab (255:255:255) (314:314:314)) + (PORT datac (1483:1483:1483) (1532:1532:1532)) + (PORT datad (897:897:897) (929:929:929)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -47373,197 +45769,7 @@ (INSTANCE z80_\|data_pins_\|dout\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (351:351:351)) - (PORT datab (420:420:420) (454:454:454)) - (PORT datad (386:386:386) (415:415:415)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1161:1161:1161)) - (PORT datab (335:335:335) (364:364:364)) - (PORT datac (525:525:525) (531:531:531)) - (PORT datad (218:218:218) (250:250:250)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (903:903:903) (914:914:914)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1940:1940:1940) (1962:1962:1962)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datac (1946:1946:1946) (2006:2006:2006)) - (PORT datad (2593:2593:2593) (2646:2646:2646)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (951:951:951)) - (PORT datab (684:684:684) (704:704:704)) - (PORT datac (2073:2073:2073) (2242:2242:2242)) - (PORT datad (1433:1433:1433) (1451:1451:1451)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datab (911:911:911) (925:925:925)) - (PORT datac (1751:1751:1751) (1844:1844:1844)) - (PORT datad (635:635:635) (684:684:684)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (699:699:699)) - (PORT datab (388:388:388) (432:432:432)) - (PORT datac (1409:1409:1409) (1477:1477:1477)) - (PORT datad (351:351:351) (382:382:382)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2309:2309:2309) (2429:2429:2429)) - (PORT datab (1622:1622:1622) (1658:1658:1658)) - (PORT datac (1347:1347:1347) (1529:1529:1529)) - (PORT datad (1271:1271:1271) (1279:1279:1279)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1550:1550:1550)) - (PORT asdata (1203:1203:1203) (1245:1245:1245)) - (PORT clrn (1590:1590:1590) (1567:1567:1567)) - (PORT ena (993:993:993) (1000:1000:1000)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (746:746:746)) - (PORT datab (925:925:925) (959:959:959)) - (PORT datac (1056:1056:1056) (1099:1099:1099)) - (PORT datad (1179:1179:1179) (1228:1228:1228)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (868:868:868)) - (PORT datab (1152:1152:1152) (1165:1165:1165)) - (PORT datac (1037:1037:1037) (1033:1033:1033)) - (PORT datad (823:823:823) (844:844:844)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT clk (1520:1520:1520) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -47576,15 +45782,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[4\]\~17) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (648:648:648)) - (PORT datab (1173:1173:1173) (1220:1220:1220)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (590:590:590) (621:621:621)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (256:256:256) (316:316:316)) + (PORT datac (637:637:637) (696:696:696)) + (PORT datad (244:244:244) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (969:969:969)) + (PORT datab (669:669:669) (692:692:692)) + (PORT datac (1462:1462:1462) (1482:1482:1482)) + (PORT datad (779:779:779) (848:848:848)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (280:280:280) (344:344:344)) + (PORT datad (245:245:245) (284:284:284)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1733:1733:1733) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1242:1242:1242)) + (PORT datab (459:459:459) (534:534:534)) + (PORT datad (678:678:678) (732:732:732)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|SYNTHESIZED_WIRE_2\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (859:859:859)) + (PORT datab (945:945:945) (968:968:968)) + (PORT datac (609:609:609) (673:673:673)) + (PORT datad (549:549:549) (564:564:564)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (952:952:952)) + (PORT datab (894:894:894) (916:916:916)) + (PORT datac (1119:1119:1119) (1127:1127:1127)) + (PORT datad (1137:1137:1137) (1155:1155:1155)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47592,13 +45888,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~16) + (INSTANCE z80_\|alu_control_\|db\[1\]\~20) (DELAY (ABSOLUTE - (PORT dataa (843:843:843) (895:895:895)) - (PORT datab (619:619:619) (657:657:657)) - (PORT datac (1400:1400:1400) (1464:1464:1464)) - (PORT datad (616:616:616) (628:628:628)) + (PORT dataa (1162:1162:1162) (1267:1267:1267)) + (PORT datab (388:388:388) (407:407:407)) + (PORT datad (642:642:642) (687:687:687)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (389:389:389)) + (PORT datab (708:708:708) (741:741:741)) + (PORT datac (575:575:575) (607:607:607)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -47608,642 +45918,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (INSTANCE z80_\|alu_control_\|db\[1\]\~22) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datab (1116:1116:1116) (1138:1138:1138)) - (PORT datac (843:843:843) (863:863:863)) - (PORT datad (202:202:202) (229:229:229)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (572:572:572) (580:580:580)) + (PORT datad (216:216:216) (252:252:252)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1475:1475:1475) (1500:1500:1500)) - (PORT clk (1844:1844:1844) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3077:3077:3077) (3235:3235:3235)) - (PORT d[1] (1841:1841:1841) (1953:1953:1953)) - (PORT d[2] (1661:1661:1661) (1762:1762:1762)) - (PORT d[3] (2157:2157:2157) (2296:2296:2296)) - (PORT d[4] (2379:2379:2379) (2508:2508:2508)) - (PORT d[5] (2076:2076:2076) (2143:2143:2143)) - (PORT d[6] (1866:1866:1866) (1988:1988:1988)) - (PORT d[7] (1974:1974:1974) (2008:2008:2008)) - (PORT d[8] (3446:3446:3446) (3559:3559:3559)) - (PORT d[9] (1737:1737:1737) (1876:1876:1876)) - (PORT d[10] (3876:3876:3876) (4076:4076:4076)) - (PORT d[11] (2655:2655:2655) (2799:2799:2799)) - (PORT d[12] (2471:2471:2471) (2621:2621:2621)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2338:2338:2338) (2292:2292:2292)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (2885:2885:2885) (2929:2929:2929)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1799:1799:1799) (1798:1798:1798)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1821:1821:1821) (1865:1865:1865)) - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4361:4361:4361) (4440:4440:4440)) - (PORT d[1] (4289:4289:4289) (4412:4412:4412)) - (PORT d[2] (4396:4396:4396) (4476:4476:4476)) - (PORT d[3] (4255:4255:4255) (4328:4328:4328)) - (PORT d[4] (4433:4433:4433) (4506:4506:4506)) - (PORT d[5] (4377:4377:4377) (4495:4495:4495)) - (PORT d[6] (4340:4340:4340) (4393:4393:4393)) - (PORT d[7] (4339:4339:4339) (4447:4447:4447)) - (PORT d[8] (4420:4420:4420) (4484:4484:4484)) - (PORT d[9] (4471:4471:4471) (4559:4559:4559)) - (PORT d[10] (4423:4423:4423) (4538:4538:4538)) - (PORT d[11] (4470:4470:4470) (4589:4589:4589)) - (PORT d[12] (4307:4307:4307) (4348:4348:4348)) - (PORT clk (1805:1805:1805) (1800:1800:1800)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1663:1663:1663) (1779:1779:1779)) - (PORT d[1] (2732:2732:2732) (2838:2838:2838)) - (PORT d[2] (2573:2573:2573) (2708:2708:2708)) - (PORT d[3] (2470:2470:2470) (2584:2584:2584)) - (PORT d[4] (2444:2444:2444) (2531:2531:2531)) - (PORT d[5] (2902:2902:2902) (3012:3012:3012)) - (PORT d[6] (2795:2795:2795) (2926:2926:2926)) - (PORT d[7] (3199:3199:3199) (3295:3295:3295)) - (PORT d[8] (2328:2328:2328) (2401:2401:2401)) - (PORT d[9] (3071:3071:3071) (3209:3209:3209)) - (PORT d[10] (2336:2336:2336) (2406:2406:2406)) - (PORT d[11] (2497:2497:2497) (2660:2660:2660)) - (PORT d[12] (2947:2947:2947) (3126:3126:3126)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (2872:2872:2872) (2960:2960:2960)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1398:1398:1398) (1419:1419:1419)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1941:1941:1941) (2052:2052:2052)) - (PORT d[1] (3029:3029:3029) (3163:3163:3163)) - (PORT d[2] (1746:1746:1746) (1840:1840:1840)) - (PORT d[3] (3627:3627:3627) (3762:3762:3762)) - (PORT d[4] (2618:2618:2618) (2777:2777:2777)) - (PORT d[5] (4105:4105:4105) (4233:4233:4233)) - (PORT d[6] (2302:2302:2302) (2398:2398:2398)) - (PORT d[7] (3712:3712:3712) (3787:3787:3787)) - (PORT d[8] (1894:1894:1894) (1995:1995:1995)) - (PORT d[9] (2469:2469:2469) (2541:2541:2541)) - (PORT d[10] (2650:2650:2650) (2739:2739:2739)) - (PORT d[11] (2800:2800:2800) (3007:3007:3007)) - (PORT d[12] (4296:4296:4296) (4557:4557:4557)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3119:3119:3119) (3165:3165:3165)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (3232:3232:3232) (3186:3186:3186)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2181:2181:2181) (2164:2164:2164)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4392:4392:4392) (4469:4469:4469)) - (PORT d[1] (4472:4472:4472) (4532:4532:4532)) - (PORT d[2] (4387:4387:4387) (4471:4471:4471)) - (PORT d[3] (4388:4388:4388) (4400:4400:4400)) - (PORT d[4] (4258:4258:4258) (4352:4352:4352)) - (PORT d[5] (4349:4349:4349) (4405:4405:4405)) - (PORT d[6] (4400:4400:4400) (4441:4441:4441)) - (PORT d[7] (4176:4176:4176) (4227:4227:4227)) - (PORT d[8] (4465:4465:4465) (4525:4525:4525)) - (PORT d[9] (4604:4604:4604) (4650:4650:4650)) - (PORT d[10] (4270:4270:4270) (4329:4329:4329)) - (PORT d[11] (4396:4396:4396) (4516:4516:4516)) - (PORT d[12] (4242:4242:4242) (4248:4248:4248)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1707:1707:1707) (1838:1838:1838)) - (PORT d[1] (1389:1389:1389) (1409:1409:1409)) - (PORT d[2] (2239:2239:2239) (2416:2416:2416)) - (PORT d[3] (1717:1717:1717) (1771:1771:1771)) - (PORT d[4] (2431:2431:2431) (2579:2579:2579)) - (PORT d[5] (2815:2815:2815) (2865:2865:2865)) - (PORT d[6] (1980:1980:1980) (2073:2073:2073)) - (PORT d[7] (1698:1698:1698) (1754:1754:1754)) - (PORT d[8] (2198:2198:2198) (2300:2300:2300)) - (PORT d[9] (1738:1738:1738) (1793:1793:1793)) - (PORT d[10] (2522:2522:2522) (2606:2606:2606)) - (PORT d[11] (4027:4027:4027) (4320:4320:4320)) - (PORT d[12] (1372:1372:1372) (1411:1411:1411)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1877:1877:1877)) - (PORT d[0] (2104:2104:2104) (2139:2139:2139)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) + (INSTANCE z80_\|bus_control_\|db\[1\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1290:1290:1290)) - (PORT datab (725:725:725) (787:787:787)) - (PORT datac (1356:1356:1356) (1394:1394:1394)) - (PORT datad (1654:1654:1654) (1694:1694:1694)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (869:869:869) (904:904:904)) + (PORT datac (360:360:360) (380:380:380)) + (PORT datad (1292:1292:1292) (1343:1343:1343)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48251,14 +45948,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1241:1241:1241)) - (PORT datab (720:720:720) (781:781:781)) - (PORT datac (1876:1876:1876) (1912:1912:1912)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (308:308:308)) + (PORT datab (469:469:469) (548:548:548)) + (PORT datac (719:719:719) (804:804:804)) + (PORT datad (696:696:696) (783:783:783)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -48266,11 +45961,574 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) (DELAY (ABSOLUTE - (PORT d[0] (1300:1300:1300) (1346:1346:1346)) + (PORT datab (770:770:770) (839:839:839)) + (PORT datac (853:853:853) (916:916:916)) + (PORT datad (723:723:723) (794:794:794)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (933:933:933)) + (PORT datab (1009:1009:1009) (1072:1072:1072)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1555:1555:1555)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (752:752:752)) + (PORT datab (2131:2131:2131) (2314:2314:2314)) + (PORT datac (2499:2499:2499) (2554:2554:2554)) + (PORT datad (616:616:616) (672:672:672)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (691:691:691)) + (PORT datab (766:766:766) (873:873:873)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1102:1102:1102)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datad (977:977:977) (1058:1058:1058)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2202:2202:2202) (2392:2392:2392)) + (PORT datab (386:386:386) (455:455:455)) + (PORT datac (2243:2243:2243) (2324:2324:2324)) + (PORT datad (382:382:382) (441:441:441)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1722:1722:1722) (1783:1783:1783)) + (PORT datab (688:688:688) (764:764:764)) + (PORT datac (268:268:268) (367:367:367)) + (PORT datad (253:253:253) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1048:1048:1048)) + (PORT datab (738:738:738) (822:822:822)) + (PORT datac (969:969:969) (1032:1032:1032)) + (PORT datad (946:946:946) (1024:1024:1024)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1056:1056:1056)) + (PORT datac (965:965:965) (1025:1025:1025)) + (PORT datad (706:706:706) (791:791:791)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (691:691:691) (776:776:776)) + (PORT datac (940:940:940) (1005:1005:1005)) + (PORT datad (205:205:205) (234:234:234)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (851:851:851)) + (PORT datab (751:751:751) (828:828:828)) + (PORT datac (282:282:282) (373:373:373)) + (PORT datad (420:420:420) (491:491:491)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (862:862:862)) + (PORT datab (885:885:885) (948:948:948)) + (PORT datac (792:792:792) (790:790:790)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (628:628:628)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (692:692:692) (775:775:775)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1549:1549:1549) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (765:765:765) (866:866:866)) + (PORT datac (668:668:668) (735:735:735)) + (PORT datad (1475:1475:1475) (1505:1505:1505)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (858:858:858)) + (PORT datab (741:741:741) (819:819:819)) + (PORT datac (857:857:857) (917:917:917)) + (PORT datad (414:414:414) (484:484:484)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (284:284:284) (378:378:378)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datad (334:334:334) (354:354:354)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1916:1916:1916)) + (PORT datab (411:411:411) (470:470:470)) + (PORT datac (1165:1165:1165) (1222:1222:1222)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (826:826:826)) + (PORT datac (254:254:254) (337:337:337)) + (PORT datad (919:919:919) (963:963:963)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (818:818:818)) + (PORT datab (731:731:731) (803:803:803)) + (PORT datac (254:254:254) (340:340:340)) + (PORT datad (725:725:725) (803:803:803)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (817:817:817)) + (PORT datab (435:435:435) (518:518:518)) + (PORT datac (1144:1144:1144) (1207:1207:1207)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (258:258:258)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (599:599:599) (614:614:614)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (633:633:633)) + (PORT datab (1014:1014:1014) (1085:1085:1085)) + (PORT datac (913:913:913) (951:951:951)) + (PORT datad (1438:1438:1438) (1505:1505:1505)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (766:766:766) (867:867:867)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4440:4440:4440) (4673:4673:4673)) + (PORT datab (3252:3252:3252) (3396:3396:3396)) + (PORT datac (637:637:637) (693:693:693)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~4) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (959:959:959)) + (PORT datab (843:843:843) (855:855:855)) + (PORT datac (873:873:873) (888:888:888)) + (PORT datad (1446:1446:1446) (1553:1553:1553)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (677:677:677) (704:704:704)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -48280,22 +46538,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2285:2285:2285) (2467:2467:2467)) - (PORT d[1] (2246:2246:2246) (2325:2325:2325)) - (PORT d[2] (1845:1845:1845) (1951:1951:1951)) - (PORT d[3] (2514:2514:2514) (2600:2600:2600)) - (PORT d[4] (2048:2048:2048) (2130:2130:2130)) - (PORT d[5] (1563:1563:1563) (1637:1637:1637)) - (PORT d[6] (1751:1751:1751) (1801:1801:1801)) - (PORT d[7] (2365:2365:2365) (2488:2488:2488)) - (PORT d[8] (2486:2486:2486) (2660:2660:2660)) - (PORT d[9] (1246:1246:1246) (1313:1313:1313)) - (PORT d[10] (1642:1642:1642) (1713:1713:1713)) - (PORT d[11] (1161:1161:1161) (1207:1207:1207)) - (PORT d[12] (1023:1023:1023) (1096:1096:1096)) + (PORT d[0] (2458:2458:2458) (2557:2557:2557)) + (PORT d[1] (1958:1958:1958) (2061:2061:2061)) + (PORT d[2] (3366:3366:3366) (3573:3573:3573)) + (PORT d[3] (1894:1894:1894) (2029:2029:2029)) + (PORT d[4] (1845:1845:1845) (1948:1948:1948)) + (PORT d[5] (2068:2068:2068) (2145:2145:2145)) + (PORT d[6] (1574:1574:1574) (1661:1661:1661)) + (PORT d[7] (1773:1773:1773) (1887:1887:1887)) + (PORT d[8] (3238:3238:3238) (3414:3414:3414)) + (PORT d[9] (3979:3979:3979) (4211:4211:4211)) + (PORT d[10] (2006:2006:2006) (2191:2191:2191)) + (PORT d[11] (2430:2430:2430) (2532:2532:2532)) + (PORT d[12] (1718:1718:1718) (1898:1898:1898)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48305,10 +46563,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1539:1539:1539) (1561:1561:1561)) + (PORT d[0] (1201:1201:1201) (1158:1158:1158)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48318,17 +46576,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2040:2040:2040) (2017:2017:2017)) + (PORT d[0] (1820:1820:1820) (1837:1837:1837)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48338,7 +46596,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48348,7 +46606,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48358,7 +46616,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1880:1880:1880)) @@ -48368,7 +46626,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -48382,7 +46640,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -48391,7 +46649,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -48400,7 +46658,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -48408,12 +46666,4370 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~10) + (DELAY + (ABSOLUTE + (PORT datab (666:666:666) (682:682:682)) + (PORT datac (1125:1125:1125) (1218:1218:1218)) + (PORT datad (1481:1481:1481) (1599:1599:1599)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (861:861:861) (872:872:872)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3511:3511:3511) (3670:3670:3670)) + (PORT d[1] (3445:3445:3445) (3524:3524:3524)) + (PORT d[2] (3677:3677:3677) (3821:3821:3821)) + (PORT d[3] (3801:3801:3801) (4081:4081:4081)) + (PORT d[4] (3186:3186:3186) (3455:3455:3455)) + (PORT d[5] (2694:2694:2694) (2781:2781:2781)) + (PORT d[6] (3419:3419:3419) (3629:3629:3629)) + (PORT d[7] (4759:4759:4759) (5005:5005:5005)) + (PORT d[8] (3618:3618:3618) (3834:3834:3834)) + (PORT d[9] (3888:3888:3888) (4154:4154:4154)) + (PORT d[10] (3471:3471:3471) (3786:3786:3786)) + (PORT d[11] (3244:3244:3244) (3411:3411:3411)) + (PORT d[12] (2341:2341:2341) (2585:2585:2585)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2593:2593:2593) (2578:2578:2578)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2250:2250:2250) (2222:2222:2222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1004:1004:1004) (1027:1027:1027)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2471:2471:2471) (2583:2583:2583)) + (PORT d[1] (1937:1937:1937) (2036:2036:2036)) + (PORT d[2] (3360:3360:3360) (3561:3561:3561)) + (PORT d[3] (1923:1923:1923) (2069:2069:2069)) + (PORT d[4] (1899:1899:1899) (2021:2021:2021)) + (PORT d[5] (1788:1788:1788) (1856:1856:1856)) + (PORT d[6] (2543:2543:2543) (2649:2649:2649)) + (PORT d[7] (1801:1801:1801) (1922:1922:1922)) + (PORT d[8] (2936:2936:2936) (3094:3094:3094)) + (PORT d[9] (3643:3643:3643) (3873:3873:3873)) + (PORT d[10] (2007:2007:2007) (2192:2192:2192)) + (PORT d[11] (2366:2366:2366) (2481:2481:2481)) + (PORT d[12] (1687:1687:1687) (1860:1860:1860)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1227:1227:1227) (1194:1194:1194)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (1757:1757:1757) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2705:2705:2705) (2831:2831:2831)) + (PORT d[1] (2202:2202:2202) (2290:2290:2290)) + (PORT d[2] (2631:2631:2631) (2767:2767:2767)) + (PORT d[3] (2831:2831:2831) (2959:2959:2959)) + (PORT d[4] (3671:3671:3671) (3974:3974:3974)) + (PORT d[5] (2942:2942:2942) (3056:3056:3056)) + (PORT d[6] (2838:2838:2838) (2958:2958:2958)) + (PORT d[7] (2670:2670:2670) (2857:2857:2857)) + (PORT d[8] (2318:2318:2318) (2411:2411:2411)) + (PORT d[9] (2646:2646:2646) (2838:2838:2838)) + (PORT d[10] (2010:2010:2010) (2196:2196:2196)) + (PORT d[11] (2355:2355:2355) (2461:2461:2461)) + (PORT d[12] (1976:1976:1976) (2153:2153:2153)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (2871:2871:2871) (2802:2802:2802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1421:1421:1421) (1457:1457:1457)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2903:2903:2903) (3028:3028:3028)) + (PORT d[1] (2801:2801:2801) (2834:2834:2834)) + (PORT d[2] (2607:2607:2607) (2703:2703:2703)) + (PORT d[3] (1723:1723:1723) (1798:1798:1798)) + (PORT d[4] (3230:3230:3230) (3519:3519:3519)) + (PORT d[5] (3059:3059:3059) (3120:3120:3120)) + (PORT d[6] (4018:4018:4018) (4276:4276:4276)) + (PORT d[7] (1465:1465:1465) (1474:1474:1474)) + (PORT d[8] (1126:1126:1126) (1158:1158:1158)) + (PORT d[9] (4517:4517:4517) (4792:4792:4792)) + (PORT d[10] (4152:4152:4152) (4478:4478:4478)) + (PORT d[11] (3591:3591:3591) (3808:3808:3808)) + (PORT d[12] (938:938:938) (950:950:950)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3058:3058:3058) (3012:3012:3012)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2996:2996:2996) (2964:2964:2964)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~7) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1073:1073:1073)) + (PORT datab (1208:1208:1208) (1277:1277:1277)) + (PORT datac (1380:1380:1380) (1421:1421:1421)) + (PORT datad (391:391:391) (414:414:414)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1304:1304:1304)) + (PORT datac (1704:1704:1704) (1794:1794:1794)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2064:2064:2064) (2151:2151:2151)) + (PORT datab (1553:1553:1553) (1601:1601:1601)) + (PORT datac (2069:2069:2069) (2116:2116:2116)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1284:1284:1284) (1308:1308:1308)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2138:2138:2138) (2231:2231:2231)) + (PORT d[1] (1634:1634:1634) (1729:1729:1729)) + (PORT d[2] (3077:3077:3077) (3264:3264:3264)) + (PORT d[3] (2207:2207:2207) (2366:2366:2366)) + (PORT d[4] (4261:4261:4261) (4626:4626:4626)) + (PORT d[5] (3331:3331:3331) (3477:3477:3477)) + (PORT d[6] (2504:2504:2504) (2621:2621:2621)) + (PORT d[7] (2083:2083:2083) (2221:2221:2221)) + (PORT d[8] (2082:2082:2082) (2181:2181:2181)) + (PORT d[9] (3636:3636:3636) (3859:3859:3859)) + (PORT d[10] (1995:1995:1995) (2200:2200:2200)) + (PORT d[11] (2035:2035:2035) (2124:2124:2124)) + (PORT d[12] (1700:1700:1700) (1877:1877:1877)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1726:1726:1726) (1682:1682:1682)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (3147:3147:3147) (3124:3124:3124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1289:1289:1289) (1329:1329:1329)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4098:4098:4098) (4215:4215:4215)) + (PORT d[1] (4338:4338:4338) (4406:4406:4406)) + (PORT d[2] (4186:4186:4186) (4325:4325:4325)) + (PORT d[3] (4270:4270:4270) (4352:4352:4352)) + (PORT d[4] (4260:4260:4260) (4352:4352:4352)) + (PORT d[5] (4164:4164:4164) (4287:4287:4287)) + (PORT d[6] (4217:4217:4217) (4512:4512:4512)) + (PORT d[7] (4199:4199:4199) (4363:4363:4363)) + (PORT d[8] (4254:4254:4254) (4239:4239:4239)) + (PORT d[9] (4195:4195:4195) (4264:4264:4264)) + (PORT d[10] (4071:4071:4071) (4136:4136:4136)) + (PORT d[11] (4195:4195:4195) (4246:4246:4246)) + (PORT d[12] (4407:4407:4407) (4410:4410:4410)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1546:1546:1546)) + (PORT datab (2773:2773:2773) (2863:2863:2863)) + (PORT datac (889:889:889) (934:934:934)) + (PORT datad (1420:1420:1420) (1458:1458:1458)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~5) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2144:2144:2144)) + (PORT datab (1015:1015:1015) (1092:1092:1092)) + (PORT datac (224:224:224) (261:261:261)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1355:1355:1355) (1384:1384:1384)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3818:3818:3818) (4013:4013:4013)) + (PORT d[1] (4013:4013:4013) (4117:4117:4117)) + (PORT d[2] (3095:3095:3095) (3188:3188:3188)) + (PORT d[3] (3467:3467:3467) (3706:3706:3706)) + (PORT d[4] (3479:3479:3479) (3765:3765:3765)) + (PORT d[5] (2966:2966:2966) (3051:3051:3051)) + (PORT d[6] (3110:3110:3110) (3279:3279:3279)) + (PORT d[7] (4449:4449:4449) (4657:4657:4657)) + (PORT d[8] (2994:2994:2994) (3190:3190:3190)) + (PORT d[9] (3588:3588:3588) (3826:3826:3826)) + (PORT d[10] (3131:3131:3131) (3402:3402:3402)) + (PORT d[11] (2682:2682:2682) (2831:2831:2831)) + (PORT d[12] (2042:2042:2042) (2248:2248:2248)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2433:2433:2433) (2433:2433:2433)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (5248:5248:5248) (5352:5352:5352)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1345:1345:1345) (1361:1361:1361)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4069:4069:4069) (4188:4188:4188)) + (PORT d[1] (4265:4265:4265) (4439:4439:4439)) + (PORT d[2] (4272:4272:4272) (4320:4320:4320)) + (PORT d[3] (4173:4173:4173) (4261:4261:4261)) + (PORT d[4] (4121:4121:4121) (4157:4157:4157)) + (PORT d[5] (4220:4220:4220) (4418:4418:4418)) + (PORT d[6] (4351:4351:4351) (4541:4541:4541)) + (PORT d[7] (4275:4275:4275) (4450:4450:4450)) + (PORT d[8] (4139:4139:4139) (4184:4184:4184)) + (PORT d[9] (4196:4196:4196) (4266:4266:4266)) + (PORT d[10] (4110:4110:4110) (4149:4149:4149)) + (PORT d[11] (4256:4256:4256) (4319:4319:4319)) + (PORT d[12] (4198:4198:4198) (4259:4259:4259)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3404:3404:3404) (3510:3510:3510)) + (PORT d[1] (4370:4370:4370) (4521:4521:4521)) + (PORT d[2] (2784:2784:2784) (2905:2905:2905)) + (PORT d[3] (2884:2884:2884) (3104:3104:3104)) + (PORT d[4] (2917:2917:2917) (3169:3169:3169)) + (PORT d[5] (2688:2688:2688) (2776:2776:2776)) + (PORT d[6] (3341:3341:3341) (3499:3499:3499)) + (PORT d[7] (3842:3842:3842) (4026:4026:4026)) + (PORT d[8] (2685:2685:2685) (2840:2840:2840)) + (PORT d[9] (3004:3004:3004) (3239:3239:3239)) + (PORT d[10] (2578:2578:2578) (2817:2817:2817)) + (PORT d[11] (2352:2352:2352) (2471:2471:2471)) + (PORT d[12] (2358:2358:2358) (2582:2582:2582)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (3766:3766:3766) (3836:3836:3836)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1541:1541:1541)) + (PORT datab (2774:2774:2774) (2866:2866:2866)) + (PORT datac (1380:1380:1380) (1406:1406:1406)) + (PORT datad (1683:1683:1683) (1769:1769:1769)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1560:1560:1560)) + (PORT datab (249:249:249) (291:291:291)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~11) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (462:462:462)) + (PORT datab (857:857:857) (864:864:864)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (340:340:340) (361:361:361)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (699:699:699)) + (PORT datab (1072:1072:1072) (1201:1201:1201)) + (PORT datac (1459:1459:1459) (1515:1515:1515)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (938:938:938)) + (PORT datab (1514:1514:1514) (1568:1568:1568)) + (PORT datac (1252:1252:1252) (1302:1302:1302)) + (PORT datad (225:225:225) (271:271:271)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (858:858:858) (917:917:917)) + (PORT datac (595:595:595) (604:604:604)) + (PORT datad (827:827:827) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1173:1173:1173) (1169:1169:1169)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1989:1989:1989) (1994:1994:1994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1594:1594:1594) (1734:1734:1734)) + (PORT datad (957:957:957) (1055:1055:1055)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (866:866:866)) + (PORT datab (906:906:906) (956:956:956)) + (PORT datac (1212:1212:1212) (1292:1292:1292)) + (PORT datad (628:628:628) (640:640:640)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1958:1958:1958)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (366:366:366) (430:430:430)) + (PORT datad (1871:1871:1871) (1981:1981:1981)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1124:1124:1124) (1182:1182:1182)) + (PORT datac (225:225:225) (306:306:306)) + (PORT datad (1178:1178:1178) (1240:1240:1240)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (361:361:361)) + (PORT datac (2095:2095:2095) (2215:2215:2215)) + (PORT datad (246:246:246) (318:318:318)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1198:1198:1198) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (2679:2679:2679) (2836:2836:2836)) + (PORT datab (1206:1206:1206) (1305:1305:1305)) + (PORT datac (1433:1433:1433) (1492:1492:1492)) + (PORT datad (875:875:875) (931:931:931)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1928:1928:1928) (1927:1927:1927)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (220:220:220) (289:289:289)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1261:1261:1261)) + (PORT datab (664:664:664) (727:727:727)) + (PORT datac (1422:1422:1422) (1476:1476:1476)) + (PORT datad (236:236:236) (305:305:305)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (698:698:698)) + (PORT datab (863:863:863) (905:905:905)) + (PORT datac (635:635:635) (653:653:653)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (689:689:689)) + (PORT datab (651:651:651) (706:706:706)) + (PORT datac (933:933:933) (994:994:994)) + (PORT datad (1500:1500:1500) (1593:1593:1593)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1547:1547:1547)) + (PORT datab (275:275:275) (360:360:360)) + (PORT datac (1494:1494:1494) (1590:1590:1590)) + (PORT datad (245:245:245) (317:317:317)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (337:337:337)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1086:1086:1086)) + (PORT datac (1226:1226:1226) (1297:1297:1297)) + (PORT datad (375:375:375) (440:440:440)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1743:1743:1743)) + (PORT datac (1545:1545:1545) (1649:1649:1649)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (1017:1017:1017)) + (PORT datab (604:604:604) (622:622:622)) + (PORT datac (1087:1087:1087) (1142:1142:1142)) + (PORT datad (1794:1794:1794) (1830:1830:1830)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (947:947:947)) + (PORT datab (1730:1730:1730) (1782:1782:1782)) + (PORT datac (939:939:939) (1007:1007:1007)) + (PORT datad (2115:2115:2115) (2235:2235:2235)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3460:3460:3460) (3588:3588:3588)) + (PORT d[1] (4366:4366:4366) (4514:4514:4514)) + (PORT d[2] (3311:3311:3311) (3436:3436:3436)) + (PORT d[3] (2638:2638:2638) (2853:2853:2853)) + (PORT d[4] (3137:3137:3137) (3393:3393:3393)) + (PORT d[5] (2802:2802:2802) (3001:3001:3001)) + (PORT d[6] (3092:3092:3092) (3256:3256:3256)) + (PORT d[7] (3879:3879:3879) (4087:4087:4087)) + (PORT d[8] (2689:2689:2689) (2854:2854:2854)) + (PORT d[9] (2982:2982:2982) (3198:3198:3198)) + (PORT d[10] (2565:2565:2565) (2795:2795:2795)) + (PORT d[11] (2321:2321:2321) (2418:2418:2418)) + (PORT d[12] (2348:2348:2348) (2591:2591:2591)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (3820:3820:3820) (3903:3903:3903)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1716:1716:1716) (1858:1858:1858)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3764:3764:3764) (3880:3880:3880)) + (PORT d[1] (4068:4068:4068) (4202:4202:4202)) + (PORT d[2] (2527:2527:2527) (2629:2629:2629)) + (PORT d[3] (3190:3190:3190) (3442:3442:3442)) + (PORT d[4] (3176:3176:3176) (3453:3453:3453)) + (PORT d[5] (2767:2767:2767) (2939:2939:2939)) + (PORT d[6] (3090:3090:3090) (3249:3249:3249)) + (PORT d[7] (4148:4148:4148) (4335:4335:4335)) + (PORT d[8] (3013:3013:3013) (3204:3204:3204)) + (PORT d[9] (3318:3318:3318) (3539:3539:3539)) + (PORT d[10] (2830:2830:2830) (3053:3053:3053)) + (PORT d[11] (2361:2361:2361) (2489:2489:2489)) + (PORT d[12] (2060:2060:2060) (2285:2285:2285)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2233:2233:2233) (2243:2243:2243)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (5014:5014:5014) (5095:5095:5095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1818:1818:1818)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1413:1413:1413) (1450:1450:1450)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4203:4203:4203) (4260:4260:4260)) + (PORT d[1] (4234:4234:4234) (4421:4421:4421)) + (PORT d[2] (4145:4145:4145) (4224:4224:4224)) + (PORT d[3] (4111:4111:4111) (4152:4152:4152)) + (PORT d[4] (4110:4110:4110) (4169:4169:4169)) + (PORT d[5] (4123:4123:4123) (4293:4293:4293)) + (PORT d[6] (4320:4320:4320) (4509:4509:4509)) + (PORT d[7] (4381:4381:4381) (4548:4548:4548)) + (PORT d[8] (4158:4158:4158) (4225:4225:4225)) + (PORT d[9] (4179:4179:4179) (4240:4240:4240)) + (PORT d[10] (4143:4143:4143) (4164:4164:4164)) + (PORT d[11] (4193:4193:4193) (4268:4268:4268)) + (PORT d[12] (4177:4177:4177) (4218:4218:4218)) + (PORT clk (1827:1827:1827) (1820:1820:1820)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1351:1351:1351) (1423:1423:1423)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3001:3001:3001) (3112:3112:3112)) + (PORT d[1] (1651:1651:1651) (1739:1739:1739)) + (PORT d[2] (2765:2765:2765) (2929:2929:2929)) + (PORT d[3] (2561:2561:2561) (2726:2726:2726)) + (PORT d[4] (3970:3970:3970) (4308:4308:4308)) + (PORT d[5] (2701:2701:2701) (2838:2838:2838)) + (PORT d[6] (2478:2478:2478) (2586:2586:2586)) + (PORT d[7] (2375:2375:2375) (2540:2540:2540)) + (PORT d[8] (2645:2645:2645) (2764:2764:2764)) + (PORT d[9] (2987:2987:2987) (3185:3185:3185)) + (PORT d[10] (2266:2266:2266) (2488:2488:2488)) + (PORT d[11] (2394:2394:2394) (2524:2524:2524)) + (PORT d[12] (1694:1694:1694) (1868:1868:1868)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2002:2002:2002) (1984:1984:1984)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3480:3480:3480) (3429:3429:3429)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1532:1532:1532) (1553:1553:1553)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4123:4123:4123) (4259:4259:4259)) + (PORT d[1] (4256:4256:4256) (4444:4444:4444)) + (PORT d[2] (4277:4277:4277) (4388:4388:4388)) + (PORT d[3] (4272:4272:4272) (4370:4370:4370)) + (PORT d[4] (4303:4303:4303) (4399:4399:4399)) + (PORT d[5] (4293:4293:4293) (4624:4624:4624)) + (PORT d[6] (4419:4419:4419) (4552:4552:4552)) + (PORT d[7] (4289:4289:4289) (4385:4385:4385)) + (PORT d[8] (4224:4224:4224) (4226:4226:4226)) + (PORT d[9] (4157:4157:4157) (4228:4228:4228)) + (PORT d[10] (4086:4086:4086) (4127:4127:4127)) + (PORT d[11] (4174:4174:4174) (4248:4248:4248)) + (PORT d[12] (4319:4319:4319) (4300:4300:4300)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2291:2291:2291) (2367:2367:2367)) + (PORT d[1] (2181:2181:2181) (2208:2208:2208)) + (PORT d[2] (1998:1998:1998) (2045:2045:2045)) + (PORT d[3] (1176:1176:1176) (1217:1217:1217)) + (PORT d[4] (2537:2537:2537) (2694:2694:2694)) + (PORT d[5] (2470:2470:2470) (2511:2511:2511)) + (PORT d[6] (3733:3733:3733) (3943:3943:3943)) + (PORT d[7] (1763:1763:1763) (1767:1767:1767)) + (PORT d[8] (1032:1032:1032) (1060:1060:1060)) + (PORT d[9] (952:952:952) (1010:1010:1010)) + (PORT d[10] (1804:1804:1804) (1872:1872:1872)) + (PORT d[11] (2242:2242:2242) (2320:2320:2320)) + (PORT d[12] (1528:1528:1528) (1601:1601:1601)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1740:1740:1740) (1700:1700:1700)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1264:1264:1264)) + (PORT datab (1231:1231:1231) (1269:1269:1269)) + (PORT datac (639:639:639) (718:718:718)) + (PORT datad (1704:1704:1704) (1749:1749:1749)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1569:1569:1569)) + (PORT datab (466:466:466) (539:539:539)) + (PORT datac (1718:1718:1718) (1842:1842:1842)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1340:1340:1340) (1411:1411:1411)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (993:993:993) (1059:1059:1059)) + (PORT d[1] (1784:1784:1784) (1818:1818:1818)) + (PORT d[2] (992:992:992) (1049:1049:1049)) + (PORT d[3] (2787:2787:2787) (2975:2975:2975)) + (PORT d[4] (2496:2496:2496) (2636:2636:2636)) + (PORT d[5] (960:960:960) (997:997:997)) + (PORT d[6] (1223:1223:1223) (1258:1258:1258)) + (PORT d[7] (1502:1502:1502) (1586:1586:1586)) + (PORT d[8] (1685:1685:1685) (1740:1740:1740)) + (PORT d[9] (1810:1810:1810) (1877:1877:1877)) + (PORT d[10] (2473:2473:2473) (2652:2652:2652)) + (PORT d[11] (1231:1231:1231) (1318:1318:1318)) + (PORT d[12] (1679:1679:1679) (1833:1833:1833)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2304:2304:2304) (2324:2324:2324)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2425:2425:2425) (2443:2443:2443)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1624:1624:1624) (1726:1726:1726)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2586:2586:2586) (2671:2671:2671)) + (PORT d[1] (2494:2494:2494) (2520:2520:2520)) + (PORT d[2] (2307:2307:2307) (2364:2364:2364)) + (PORT d[3] (901:901:901) (949:949:949)) + (PORT d[4] (2594:2594:2594) (2821:2821:2821)) + (PORT d[5] (2748:2748:2748) (2771:2771:2771)) + (PORT d[6] (4022:4022:4022) (4207:4207:4207)) + (PORT d[7] (1426:1426:1426) (1450:1450:1450)) + (PORT d[8] (959:959:959) (978:978:978)) + (PORT d[9] (1497:1497:1497) (1566:1566:1566)) + (PORT d[10] (2086:2086:2086) (2151:2151:2151)) + (PORT d[11] (2583:2583:2583) (2709:2709:2709)) + (PORT d[12] (1295:1295:1295) (1355:1355:1355)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2455:2455:2455) (2393:2393:2393)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (3001:3001:3001) (2952:2952:2952)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1014:1014:1014) (1051:1051:1051)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (988:988:988) (1051:1051:1051)) + (PORT d[1] (981:981:981) (1017:1017:1017)) + (PORT d[2] (1019:1019:1019) (1075:1075:1075)) + (PORT d[3] (2212:2212:2212) (2367:2367:2367)) + (PORT d[4] (951:951:951) (1003:1003:1003)) + (PORT d[5] (953:953:953) (987:987:987)) + (PORT d[6] (967:967:967) (1002:1002:1002)) + (PORT d[7] (1186:1186:1186) (1245:1245:1245)) + (PORT d[8] (1439:1439:1439) (1497:1497:1497)) + (PORT d[9] (1738:1738:1738) (1800:1800:1800)) + (PORT d[10] (1670:1670:1670) (1832:1832:1832)) + (PORT d[11] (1257:1257:1257) (1348:1348:1348)) + (PORT d[12] (1351:1351:1351) (1468:1468:1468)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1495:1495:1495) (1495:1495:1495)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (2024:2024:2024) (1999:1999:1999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1393:1393:1393) (1418:1418:1418)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2599:2599:2599) (2703:2703:2703)) + (PORT d[1] (2484:2484:2484) (2490:2490:2490)) + (PORT d[2] (2323:2323:2323) (2401:2401:2401)) + (PORT d[3] (597:597:597) (618:618:618)) + (PORT d[4] (2605:2605:2605) (2819:2819:2819)) + (PORT d[5] (2762:2762:2762) (2804:2804:2804)) + (PORT d[6] (3210:3210:3210) (3404:3404:3404)) + (PORT d[7] (1137:1137:1137) (1143:1143:1143)) + (PORT d[8] (1478:1478:1478) (1534:1534:1534)) + (PORT d[9] (1442:1442:1442) (1499:1499:1499)) + (PORT d[10] (2068:2068:2068) (2152:2152:2152)) + (PORT d[11] (2589:2589:2589) (2720:2720:2720)) + (PORT d[12] (1020:1020:1020) (1083:1083:1083)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1786:1786:1786) (1831:1831:1831)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2420:2420:2420) (2379:2379:2379)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1584:1584:1584)) + (PORT datab (1085:1085:1085) (1129:1129:1129)) + (PORT datac (1733:1733:1733) (1822:1822:1822)) + (PORT datad (1396:1396:1396) (1426:1426:1426)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1734:1734:1734) (1780:1780:1780)) + (PORT datab (1496:1496:1496) (1596:1596:1596)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (2079:2079:2079) (2106:2106:2106)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1065:1065:1065)) + (PORT datab (692:692:692) (777:777:777)) + (PORT datac (941:941:941) (1015:1015:1015)) + (PORT datad (405:405:405) (474:474:474)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1067:1067:1067)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (942:942:942) (1015:1015:1015)) + (PORT datad (213:213:213) (245:245:245)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (746:746:746)) + (PORT datab (442:442:442) (508:508:508)) + (PORT datac (320:320:320) (351:351:351)) + (PORT datad (314:314:314) (331:331:331)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (639:639:639) (662:662:662)) + (PORT datad (962:962:962) (1020:1020:1020)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (258:258:258)) + (PORT datab (236:236:236) (278:278:278)) + (PORT datac (942:942:942) (1014:1014:1014)) + (PORT datad (206:206:206) (235:235:235)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (412:412:412)) + (PORT datab (354:354:354) (386:386:386)) + (PORT datad (610:610:610) (622:622:622)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1552:1552:1552) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1588:1588:1588)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (2005:2005:2005) (2107:2107:2107)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (909:909:909)) + (PORT datab (756:756:756) (844:844:844)) + (PORT datac (739:739:739) (811:811:811)) + (PORT datad (718:718:718) (791:791:791)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (269:269:269)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (1017:1017:1017)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (635:635:635) (677:677:677)) + (PORT datad (925:925:925) (985:985:985)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1022:1022:1022) (1097:1097:1097)) + (PORT datad (449:449:449) (525:525:525)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (695:695:695)) + (PORT datab (3848:3848:3848) (4091:4091:4091)) + (PORT datac (213:213:213) (289:289:289)) + (PORT datad (3189:3189:3189) (3351:3351:3351)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (822:822:822)) + (PORT datac (699:699:699) (767:767:767)) + (PORT datad (687:687:687) (762:762:762)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (372:372:372)) + (PORT datab (209:209:209) (250:250:250)) + (PORT datad (448:448:448) (524:524:524)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (512:512:512)) + (PORT datab (881:881:881) (948:948:948)) + (PORT datac (718:718:718) (800:800:800)) + (PORT datad (755:755:755) (854:854:854)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT datab (771:771:771) (842:842:842)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (722:722:722) (796:796:796)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT datab (741:741:741) (830:830:830)) + (PORT datac (253:253:253) (338:338:338)) + (PORT datad (713:713:713) (778:778:778)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (371:371:371)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (1702:1702:1702) (1787:1787:1787)) + (PORT datac (2219:2219:2219) (2415:2415:2415)) + (PORT datad (607:607:607) (654:654:654)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1072:1072:1072)) + (PORT datab (981:981:981) (1073:1073:1073)) + (PORT datac (626:626:626) (648:648:648)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (513:513:513)) + (PORT datab (750:750:750) (839:839:839)) + (PORT datac (736:736:736) (808:808:808)) + (PORT datad (719:719:719) (793:793:793)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1364:1364:1364)) + (PORT datab (976:976:976) (1041:1041:1041)) + (PORT datad (367:367:367) (391:391:391)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1077:1077:1077)) + (PORT datab (983:983:983) (1074:1074:1074)) + (PORT datac (315:315:315) (333:333:333)) + (PORT datad (605:605:605) (620:620:620)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (747:747:747) (833:833:833)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (919:919:919) (965:965:965)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1078:1078:1078)) + (PORT datab (742:742:742) (831:831:831)) + (PORT datac (253:253:253) (335:335:335)) + (PORT datad (720:720:720) (788:788:788)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (243:243:243)) + (PORT datab (880:880:880) (904:904:904)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1554:1554:1554)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1103:1103:1103)) + (PORT datab (1271:1271:1271) (1321:1321:1321)) + (PORT datad (1127:1127:1127) (1181:1181:1181)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1110:1110:1110)) + (PORT datab (941:941:941) (962:962:962)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1551:1551:1551) (1544:1544:1544)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (700:700:700)) + (PORT datab (2117:2117:2117) (2268:2268:2268)) + (PORT datac (2005:2005:2005) (2082:2082:2082)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (672:672:672)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (574:574:574) (590:590:590)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE kempston\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1967:1967:1967) (2020:2020:2020)) + (PORT datab (1953:1953:1953) (1955:1955:1955)) + (PORT datac (1564:1564:1564) (1595:1595:1595)) + (PORT datad (1700:1700:1700) (1782:1782:1782)) + (IOPATH dataa combout (350:350:350) (367:367:367)) + (IOPATH datab combout (350:350:350) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1195:1195:1195) (1255:1255:1255)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1208:1208:1208)) + (PORT datab (1132:1132:1132) (1213:1213:1213)) + (PORT datac (1384:1384:1384) (1412:1412:1412)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (873:873:873)) + (PORT datab (1519:1519:1519) (1569:1569:1569)) + (PORT datac (904:904:904) (923:923:923)) + (PORT datad (230:230:230) (276:276:276)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (320:320:320)) + (PORT datac (632:632:632) (706:706:706)) + (PORT datad (243:243:243) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (911:911:911)) + (PORT datab (1058:1058:1058) (1073:1073:1073)) + (PORT datac (1459:1459:1459) (1478:1478:1478)) + (PORT datad (846:846:846) (921:921:921)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (247:247:247) (294:294:294)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1989:1989:1989) (1994:1994:1994)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1784:1784:1784) (1892:1892:1892)) + (PORT datab (235:235:235) (278:278:278)) + (PORT datac (853:853:853) (872:872:872)) + (PORT datad (953:953:953) (1017:1017:1017)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT datab (1103:1103:1103) (1169:1169:1169)) + (PORT datac (684:684:684) (725:725:725)) + (PORT datad (691:691:691) (751:751:751)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT datac (1126:1126:1126) (1129:1129:1129)) + (PORT datad (581:581:581) (604:604:604)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1334:1334:1334)) + (PORT datab (927:927:927) (982:982:982)) + (PORT datac (2092:2092:2092) (2240:2240:2240)) + (PORT datad (1472:1472:1472) (1548:1548:1548)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1881:1881:1881) (1923:1923:1923)) + (PORT datab (965:965:965) (1009:1009:1009)) + (PORT datac (930:930:930) (953:953:953)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2380:2380:2380) (2493:2493:2493)) + (PORT datab (643:643:643) (682:682:682)) + (PORT datac (1198:1198:1198) (1308:1308:1308)) + (PORT datad (1130:1130:1130) (1175:1175:1175)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (669:669:669)) + (PORT datab (690:690:690) (737:737:737)) + (PORT datac (879:879:879) (893:893:893)) + (PORT datad (608:608:608) (625:625:625)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (436:436:436)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1111:1111:1111) (1171:1171:1171)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1954:1954:1954) (2052:2052:2052)) + (PORT datab (656:656:656) (711:711:711)) + (PORT datac (1113:1113:1113) (1169:1169:1169)) + (PORT datad (2119:2119:2119) (2147:2147:2147)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1252:1252:1252)) + (PORT datab (825:825:825) (842:842:842)) + (PORT datac (805:805:805) (823:823:823)) + (PORT datad (1427:1427:1427) (1479:1479:1479)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1353:1353:1353)) + (PORT datab (1556:1556:1556) (1621:1621:1621)) + (PORT datac (1135:1135:1135) (1151:1151:1151)) + (PORT datad (1451:1451:1451) (1474:1474:1474)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1179:1179:1179)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1141:1141:1141) (1171:1171:1171)) + (PORT datad (646:646:646) (668:668:668)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (947:947:947)) + (PORT datab (876:876:876) (888:888:888)) + (PORT datac (1324:1324:1324) (1366:1366:1366)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1090:1090:1090)) + (PORT datab (273:273:273) (359:359:359)) + (PORT datac (1199:1199:1199) (1287:1287:1287)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (1372:1372:1372) (1543:1543:1543)) + (PORT datac (238:238:238) (316:316:316)) + (PORT datad (1755:1755:1755) (1877:1877:1877)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1563:1563:1563) (1546:1546:1546)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (1043:1043:1043)) + (PORT datad (868:868:868) (931:931:931)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|nmi_armed) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1844:1844:1844)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (766:766:766) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1130:1130:1130) (1176:1176:1176)) + (PORT clrn (1560:1560:1560) (1541:1541:1541)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|im1\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (202:202:202) (230:230:230)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1544:1544:1544)) + (PORT ena (1733:1733:1733) (1719:1719:1719)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (634:634:634)) + (PORT datab (461:461:461) (541:541:541)) + (PORT datac (1219:1219:1219) (1262:1262:1262)) + (PORT datad (676:676:676) (731:731:731)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1241:1241:1241)) + (PORT datab (709:709:709) (754:754:754)) + (PORT datac (1222:1222:1222) (1265:1265:1265)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (952:952:952)) + (PORT datab (273:273:273) (332:332:332)) + (PORT datac (1411:1411:1411) (1435:1435:1435)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (989:989:989) (1003:1003:1003)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3525:3525:3525) (3701:3701:3701)) + (PORT d[1] (3429:3429:3429) (3513:3513:3513)) + (PORT d[2] (3394:3394:3394) (3511:3511:3511)) + (PORT d[3] (3766:3766:3766) (4026:4026:4026)) + (PORT d[4] (2650:2650:2650) (2896:2896:2896)) + (PORT d[5] (2398:2398:2398) (2478:2478:2478)) + (PORT d[6] (3402:3402:3402) (3580:3580:3580)) + (PORT d[7] (4748:4748:4748) (4976:4976:4976)) + (PORT d[8] (3292:3292:3292) (3514:3514:3514)) + (PORT d[9] (3932:3932:3932) (4160:4160:4160)) + (PORT d[10] (3434:3434:3434) (3728:3728:3728)) + (PORT d[11] (2987:2987:2987) (3159:3159:3159)) + (PORT d[12] (2390:2390:2390) (2642:2642:2642)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1713:1713:1713) (1650:1650:1650)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (2508:2508:2508) (2510:2510:2510)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (985:985:985) (1010:1010:1010)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3226:3226:3226) (3381:3381:3381)) + (PORT d[1] (3121:3121:3121) (3182:3182:3182)) + (PORT d[2] (3690:3690:3690) (3825:3825:3825)) + (PORT d[3] (1731:1731:1731) (1774:1774:1774)) + (PORT d[4] (2937:2937:2937) (3200:3200:3200)) + (PORT d[5] (2819:2819:2819) (2909:2909:2909)) + (PORT d[6] (3693:3693:3693) (3923:3923:3923)) + (PORT d[7] (1737:1737:1737) (1793:1793:1793)) + (PORT d[8] (3590:3590:3590) (3837:3837:3837)) + (PORT d[9] (4222:4222:4222) (4471:4471:4471)) + (PORT d[10] (3794:3794:3794) (4126:4126:4126)) + (PORT d[11] (3296:3296:3296) (3491:3491:3491)) + (PORT d[12] (2704:2704:2704) (2953:2953:2953)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1807:1807:1807) (1857:1857:1857)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2404:2404:2404) (2385:2385:2385)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -48423,7 +51039,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1174:1174:1174) (1169:1169:1169)) + (PORT d[0] (965:965:965) (968:968:968)) (PORT clk (1860:1860:1860) (1888:1888:1888)) ) ) @@ -48436,19 +51052,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2884:2884:2884) (3084:3084:3084)) - (PORT d[1] (3296:3296:3296) (3485:3485:3485)) - (PORT d[2] (1967:1967:1967) (2035:2035:2035)) - (PORT d[3] (3971:3971:3971) (4151:4151:4151)) - (PORT d[4] (2885:2885:2885) (3085:3085:3085)) - (PORT d[5] (4454:4454:4454) (4597:4597:4597)) - (PORT d[6] (2220:2220:2220) (2291:2291:2291)) - (PORT d[7] (1721:1721:1721) (1766:1766:1766)) - (PORT d[8] (3141:3141:3141) (3324:3324:3324)) - (PORT d[9] (1847:1847:1847) (1916:1916:1916)) - (PORT d[10] (2061:2061:2061) (2130:2130:2130)) - (PORT d[11] (3118:3118:3118) (3322:3322:3322)) - (PORT d[12] (4307:4307:4307) (4577:4577:4577)) + (PORT d[0] (3227:3227:3227) (3382:3382:3382)) + (PORT d[1] (3414:3414:3414) (3478:3478:3478)) + (PORT d[2] (3713:3713:3713) (3838:3838:3838)) + (PORT d[3] (3780:3780:3780) (4058:4058:4058)) + (PORT d[4] (2638:2638:2638) (2900:2900:2900)) + (PORT d[5] (2731:2731:2731) (2790:2790:2790)) + (PORT d[6] (3407:3407:3407) (3612:3612:3612)) + (PORT d[7] (4787:4787:4787) (5037:5037:5037)) + (PORT d[8] (3619:3619:3619) (3835:3835:3835)) + (PORT d[9] (4243:4243:4243) (4495:4495:4495)) + (PORT d[10] (3498:3498:3498) (3819:3819:3819)) + (PORT d[11] (3267:3267:3267) (3442:3442:3442)) + (PORT d[12] (2341:2341:2341) (2586:2586:2586)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -48461,7 +51077,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1635:1635:1635) (1573:1573:1573)) + (PORT d[0] (2591:2591:2591) (2575:2575:2575)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -48475,7 +51091,7 @@ (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2528:2528:2528) (2508:2508:2508)) + (PORT d[0] (2247:2247:2247) (2219:2219:2219)) ) ) ) @@ -48571,170 +51187,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1400:1400:1400) (1441:1441:1441)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2389:2389:2389)) - (PORT d[1] (1122:1122:1122) (1125:1125:1125)) - (PORT d[2] (2684:2684:2684) (2759:2759:2759)) - (PORT d[3] (4593:4593:4593) (4819:4819:4819)) - (PORT d[4] (965:965:965) (1020:1020:1020)) - (PORT d[5] (1653:1653:1653) (1677:1677:1677)) - (PORT d[6] (1443:1443:1443) (1505:1505:1505)) - (PORT d[7] (1417:1417:1417) (1425:1425:1425)) - (PORT d[8] (2517:2517:2517) (2647:2647:2647)) - (PORT d[9] (1142:1142:1142) (1167:1167:1167)) - (PORT d[10] (2053:2053:2053) (2116:2116:2116)) - (PORT d[11] (3735:3735:3735) (3999:3999:3999)) - (PORT d[12] (2464:2464:2464) (2535:2535:2535)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2814:2814:2814) (2818:2818:2818)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (1909:1909:1909) (1894:1894:1894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) (DELAY (ABSOLUTE - (PORT dataa (857:857:857) (885:885:885)) - (PORT datab (1257:1257:1257) (1321:1321:1321)) - (PORT datac (1457:1457:1457) (1543:1543:1543)) - (PORT datad (1415:1415:1415) (1470:1470:1470)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (907:907:907) (915:915:915)) + (PORT datab (1124:1124:1124) (1211:1211:1211)) + (PORT datac (802:802:802) (810:810:810)) + (PORT datad (1340:1340:1340) (1406:1406:1406)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48745,8 +51208,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1461:1461:1461) (1498:1498:1498)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (989:989:989) (1029:1029:1029)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -48758,20 +51221,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1675:1675:1675) (1799:1799:1799)) - (PORT d[1] (2219:2219:2219) (2269:2269:2269)) - (PORT d[2] (2260:2260:2260) (2441:2441:2441)) - (PORT d[3] (1737:1737:1737) (1761:1761:1761)) - (PORT d[4] (2421:2421:2421) (2555:2555:2555)) - (PORT d[5] (2836:2836:2836) (2889:2889:2889)) - (PORT d[6] (2028:2028:2028) (2126:2126:2126)) - (PORT d[7] (1728:1728:1728) (1790:1790:1790)) - (PORT d[8] (2170:2170:2170) (2268:2268:2268)) - (PORT d[9] (1998:1998:1998) (2050:2050:2050)) - (PORT d[10] (2212:2212:2212) (2291:2291:2291)) - (PORT d[11] (4313:4313:4313) (4609:4609:4609)) - (PORT d[12] (2203:2203:2203) (2259:2259:2259)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (3210:3210:3210) (3342:3342:3342)) + (PORT d[1] (3136:3136:3136) (3194:3194:3194)) + (PORT d[2] (3968:3968:3968) (4136:4136:4136)) + (PORT d[3] (2001:2001:2001) (2070:2070:2070)) + (PORT d[4] (2943:2943:2943) (3223:3223:3223)) + (PORT d[5] (3520:3520:3520) (3590:3590:3590)) + (PORT d[6] (3986:3986:3986) (4237:4237:4237)) + (PORT d[7] (1223:1223:1223) (1277:1277:1277)) + (PORT d[8] (3923:3923:3923) (4174:4174:4174)) + (PORT d[9] (4191:4191:4191) (4487:4487:4487)) + (PORT d[10] (3858:3858:3858) (4185:4185:4185)) + (PORT d[11] (3578:3578:3578) (3778:3778:3778)) + (PORT d[12] (2685:2685:2685) (2937:2937:2937)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48783,8 +51246,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1909:1909:1909) (1957:1957:1957)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (3016:3016:3016) (2994:2994:2994)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48796,8 +51259,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (1899:1899:1899) (1859:1859:1859)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2978:2978:2978) (2947:2947:2947)) ) ) ) @@ -48806,7 +51269,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -48816,7 +51279,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -48826,7 +51289,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48836,7 +51299,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48846,7 +51309,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -48860,7 +51323,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) @@ -48869,7 +51332,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) @@ -48878,7 +51341,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -48888,22 +51351,649 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1194:1194:1194) (1262:1262:1262)) - (PORT datab (1708:1708:1708) (1802:1802:1802)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1682:1682:1682) (1783:1783:1783)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (1806:1806:1806) (1885:1885:1885)) + (PORT datab (1118:1118:1118) (1162:1162:1162)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1347:1347:1347) (1336:1336:1336)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1292:1292:1292) (1365:1365:1365)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3818:3818:3818) (4013:4013:4013)) + (PORT d[1] (4032:4032:4032) (4143:4143:4143)) + (PORT d[2] (3105:3105:3105) (3220:3220:3220)) + (PORT d[3] (3182:3182:3182) (3413:3413:3413)) + (PORT d[4] (3466:3466:3466) (3759:3759:3759)) + (PORT d[5] (3001:3001:3001) (3070:3070:3070)) + (PORT d[6] (2812:2812:2812) (2948:2948:2948)) + (PORT d[7] (4158:4158:4158) (4362:4362:4362)) + (PORT d[8] (3030:3030:3030) (3203:3203:3203)) + (PORT d[9] (3580:3580:3580) (3805:3805:3805)) + (PORT d[10] (2841:2841:2841) (3108:3108:3108)) + (PORT d[11] (2673:2673:2673) (2807:2807:2807)) + (PORT d[12] (2485:2485:2485) (2667:2667:2667)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1928:1928:1928) (1942:1942:1942)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (5245:5245:5245) (5346:5346:5346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1161:1161:1161)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4210:4210:4210) (4283:4283:4283)) + (PORT d[1] (4252:4252:4252) (4439:4439:4439)) + (PORT d[2] (4275:4275:4275) (4331:4331:4331)) + (PORT d[3] (4262:4262:4262) (4288:4288:4288)) + (PORT d[4] (4122:4122:4122) (4133:4133:4133)) + (PORT d[5] (4222:4222:4222) (4438:4438:4438)) + (PORT d[6] (4311:4311:4311) (4503:4503:4503)) + (PORT d[7] (4253:4253:4253) (4426:4426:4426)) + (PORT d[8] (4145:4145:4145) (4203:4203:4203)) + (PORT d[9] (4160:4160:4160) (4245:4245:4245)) + (PORT d[10] (4194:4194:4194) (4240:4240:4240)) + (PORT d[11] (4190:4190:4190) (4246:4246:4246)) + (PORT d[12] (4190:4190:4190) (4237:4237:4237)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2297:2297:2297) (2378:2378:2378)) + (PORT d[1] (2451:2451:2451) (2480:2480:2480)) + (PORT d[2] (1984:1984:1984) (2035:2035:2035)) + (PORT d[3] (1187:1187:1187) (1234:1234:1234)) + (PORT d[4] (2548:2548:2548) (2681:2681:2681)) + (PORT d[5] (2483:2483:2483) (2506:2506:2506)) + (PORT d[6] (3750:3750:3750) (3934:3934:3934)) + (PORT d[7] (1439:1439:1439) (1446:1446:1446)) + (PORT d[8] (990:990:990) (1030:1030:1030)) + (PORT d[9] (996:996:996) (1044:1044:1044)) + (PORT d[10] (1809:1809:1809) (1883:1883:1883)) + (PORT d[11] (2570:2570:2570) (2680:2680:2680)) + (PORT d[12] (1527:1527:1527) (1571:1571:1571)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (1691:1691:1691) (1707:1707:1707)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1294:1294:1294) (1353:1353:1353)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3806:3806:3806) (3984:3984:3984)) + (PORT d[1] (3754:3754:3754) (3857:3857:3857)) + (PORT d[2] (3404:3404:3404) (3506:3506:3506)) + (PORT d[3] (3481:3481:3481) (3739:3739:3739)) + (PORT d[4] (2622:2622:2622) (2872:2872:2872)) + (PORT d[5] (2719:2719:2719) (2812:2812:2812)) + (PORT d[6] (3098:3098:3098) (3283:3283:3283)) + (PORT d[7] (4462:4462:4462) (4689:4689:4689)) + (PORT d[8] (3320:3320:3320) (3510:3510:3510)) + (PORT d[9] (3593:3593:3593) (3836:3836:3836)) + (PORT d[10] (3168:3168:3168) (3460:3460:3460)) + (PORT d[11] (2943:2943:2943) (3089:3089:3089)) + (PORT d[12] (2418:2418:2418) (2570:2570:2570)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1881:1881:1881) (1817:1817:1817)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (5380:5380:5380) (5254:5254:5254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1386:1386:1386) (1413:1413:1413)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4212:4212:4212) (4290:4290:4290)) + (PORT d[1] (4206:4206:4206) (4314:4314:4314)) + (PORT d[2] (4290:4290:4290) (4320:4320:4320)) + (PORT d[3] (4144:4144:4144) (4163:4163:4163)) + (PORT d[4] (4125:4125:4125) (4163:4163:4163)) + (PORT d[5] (4399:4399:4399) (4775:4775:4775)) + (PORT d[6] (4274:4274:4274) (4458:4458:4458)) + (PORT d[7] (4213:4213:4213) (4376:4376:4376)) + (PORT d[8] (4147:4147:4147) (4214:4214:4214)) + (PORT d[9] (4192:4192:4192) (4273:4273:4273)) + (PORT d[10] (4148:4148:4148) (4202:4202:4202)) + (PORT d[11] (4194:4194:4194) (4252:4252:4252)) + (PORT d[12] (4228:4228:4228) (4297:4297:4297)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2853:2853:2853) (2974:2974:2974)) + (PORT d[1] (4349:4349:4349) (4498:4498:4498)) + (PORT d[2] (2808:2808:2808) (2944:2944:2944)) + (PORT d[3] (2497:2497:2497) (2704:2704:2704)) + (PORT d[4] (3076:3076:3076) (3317:3317:3317)) + (PORT d[5] (3063:3063:3063) (3131:3131:3131)) + (PORT d[6] (3084:3084:3084) (3269:3269:3269)) + (PORT d[7] (3381:3381:3381) (3572:3572:3572)) + (PORT d[8] (2448:2448:2448) (2587:2587:2587)) + (PORT d[9] (2990:2990:2990) (3199:3199:3199)) + (PORT d[10] (2315:2315:2315) (2557:2557:2557)) + (PORT d[11] (2281:2281:2281) (2377:2377:2377)) + (PORT d[12] (2568:2568:2568) (2777:2777:2777)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (3596:3596:3596) (3520:3520:3520)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1291:1291:1291)) + (PORT datab (1237:1237:1237) (1326:1326:1326)) + (PORT datac (1047:1047:1047) (1040:1040:1040)) + (PORT datad (1615:1615:1615) (1631:1631:1631)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48911,14 +52001,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~112) + (INSTANCE Selector4\~1) (DELAY (ABSOLUTE - (PORT dataa (1742:1742:1742) (1794:1794:1794)) - (PORT datab (667:667:667) (692:692:692)) - (PORT datac (628:628:628) (640:640:640)) - (PORT datad (319:319:319) (340:340:340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1456:1456:1456) (1537:1537:1537)) + (PORT datab (1162:1162:1162) (1194:1194:1194)) + (PORT datac (1385:1385:1385) (1437:1437:1437)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (3077:3077:3077) (3143:3143:3143)) + (PORT datab (1186:1186:1186) (1190:1190:1190)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1019:1019:1019)) + (PORT datab (1384:1384:1384) (1388:1388:1388)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (1728:1728:1728) (1791:1791:1791)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -48927,16 +52049,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~113) + (INSTANCE D\[5\]\~40) (DELAY (ABSOLUTE - (PORT dataa (2496:2496:2496) (2561:2561:2561)) - (PORT datab (700:700:700) (722:722:722)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (1174:1174:1174) (1248:1248:1248)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1084:1084:1084) (1099:1099:1099)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -48946,13 +52064,13 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (690:690:690)) - (PORT datab (1158:1158:1158) (1194:1194:1194)) - (PORT datac (219:219:219) (257:257:257)) - (PORT datad (1559:1559:1559) (1584:1584:1584)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1405:1405:1405) (1441:1441:1441)) + (PORT datab (855:855:855) (937:937:937)) + (PORT datac (1481:1481:1481) (1529:1529:1529)) + (PORT datad (227:227:227) (272:272:272)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -48962,9 +52080,9 @@ (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT clk (1520:1520:1520) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -48975,30 +52093,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT datab (431:431:431) (490:490:490)) - (PORT datac (218:218:218) (263:263:263)) - (PORT datad (227:227:227) (264:264:264)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (262:262:262) (323:323:323)) + (PORT datac (1018:1018:1018) (1093:1093:1093)) + (PORT datad (245:245:245) (291:291:291)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (873:873:873) (882:882:882)) - (PORT datab (592:592:592) (613:613:613)) - (PORT datac (532:532:532) (547:547:547)) - (PORT datad (1104:1104:1104) (1122:1122:1122)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (886:886:886) (970:970:970)) + (PORT datab (787:787:787) (866:866:866)) + (PORT datac (1461:1461:1461) (1480:1480:1480)) + (PORT datad (1157:1157:1157) (1192:1192:1192)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49008,10 +52126,84 @@ (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1709:1709:1709) (1778:1778:1778)) + (PORT clrn (1564:1564:1564) (1546:1546:1546)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2114:2114:2114) (2227:2227:2227)) + (PORT datac (1203:1203:1203) (1284:1284:1284)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (695:695:695)) + (PORT datab (724:724:724) (764:764:764)) + (PORT datac (911:911:911) (967:967:967)) + (PORT datad (1869:1869:1869) (1997:1997:1997)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (676:676:676)) + (PORT datab (667:667:667) (728:728:728)) + (PORT datac (1451:1451:1451) (1495:1495:1495)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1086:1086:1086)) + (PORT datab (265:265:265) (347:347:347)) + (PORT datac (1202:1202:1202) (1273:1273:1273)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (PORT ena (1940:1940:1940) (1962:1962:1962)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -49023,139 +52215,109 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (INSTANCE z80_\|execute_\|setM1\~16) (DELAY (ABSOLUTE - (PORT dataa (2126:2126:2126) (2295:2295:2295)) - (PORT datab (2009:2009:2009) (2098:2098:2098)) - (PORT datac (1374:1374:1374) (1481:1481:1481)) - (PORT datad (877:877:877) (904:904:904)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1340:1340:1340) (1387:1387:1387)) + (PORT datab (619:619:619) (644:644:644)) + (PORT datac (1139:1139:1139) (1180:1180:1180)) + (PORT datad (904:904:904) (975:975:975)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1028:1028:1028)) + (PORT datab (676:676:676) (699:699:699)) + (PORT datac (1508:1508:1508) (1599:1599:1599)) + (PORT datad (1006:1006:1006) (1064:1064:1064)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (685:685:685)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (315:315:315) (335:335:335)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (917:917:917)) + (PORT datab (703:703:703) (764:764:764)) + (PORT datac (1808:1808:1808) (1909:1909:1909)) + (PORT datad (641:641:641) (699:699:699)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1409:1409:1409)) + (PORT datab (877:877:877) (916:916:916)) + (PORT datac (553:553:553) (568:568:568)) + (PORT datad (343:343:343) (365:365:365)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (1208:1208:1208) (1251:1251:1251)) - (PORT datab (660:660:660) (700:700:700)) - (PORT datac (1413:1413:1413) (1458:1458:1458)) - (PORT datad (334:334:334) (357:357:357)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (638:638:638) (665:665:665)) + (PORT datab (925:925:925) (952:952:952)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) + (INSTANCE z80_\|execute_\|setM1\~47) (DELAY (ABSOLUTE - (PORT datac (1029:1029:1029) (1089:1089:1089)) - (PORT datad (603:603:603) (614:614:614)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1871:1871:1871) (1947:1947:1947)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (1085:1085:1085) (1121:1121:1121)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1239:1239:1239)) - (PORT datab (230:230:230) (272:272:272)) - (PORT datac (611:611:611) (641:641:641)) - (PORT datad (596:596:596) (616:616:616)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT dataa (1216:1216:1216) (1268:1268:1268)) + (PORT datab (1244:1244:1244) (1285:1285:1285)) + (PORT datac (891:891:891) (942:942:942)) + (PORT datad (848:848:848) (876:876:876)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1281:1281:1281) (1354:1354:1354)) - (PORT datab (757:757:757) (812:812:812)) - (PORT datac (1936:1936:1936) (1953:1953:1953)) - (PORT datad (827:827:827) (852:852:852)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (683:683:683)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1472:1472:1472) (1542:1542:1542)) - (PORT datad (632:632:632) (697:697:697)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1686:1686:1686) (1728:1728:1728)) - (PORT datab (924:924:924) (949:949:949)) - (PORT datac (1405:1405:1405) (1437:1437:1437)) - (PORT datad (869:869:869) (884:884:884)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (692:692:692)) - (PORT datab (1323:1323:1323) (1377:1377:1377)) - (PORT datac (213:213:213) (245:245:245)) - (PORT datad (1699:1699:1699) (1713:1713:1713)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49163,328 +52325,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) + (INSTANCE z80_\|execute_\|setM1\~53) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (658:658:658) (707:707:707)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (890:890:890)) - (PORT datab (2358:2358:2358) (2453:2453:2453)) - (PORT datac (1473:1473:1473) (1589:1589:1589)) - (PORT datad (1034:1034:1034) (1093:1093:1093)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (941:941:941)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (588:588:588) (602:602:602)) - (PORT datac (587:587:587) (646:646:646)) - (PORT datad (1400:1400:1400) (1419:1419:1419)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (679:679:679) (727:727:727)) - (PORT datad (889:889:889) (908:908:908)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (774:774:774)) - (PORT datac (683:683:683) (724:724:724)) - (PORT datad (890:890:890) (904:904:904)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (354:354:354)) - (PORT datac (685:685:685) (725:725:725)) - (PORT datad (891:891:891) (904:904:904)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datac (680:680:680) (727:727:727)) - (PORT datad (893:893:893) (910:910:910)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT datac (695:695:695) (789:789:789)) - (PORT datad (2317:2317:2317) (2438:2438:2438)) + (PORT dataa (589:589:589) (604:604:604)) + (PORT datab (615:615:615) (661:661:661)) + (PORT datac (910:910:910) (952:952:952)) + (PORT datad (1044:1044:1044) (1045:1045:1045)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1283:1283:1283)) - (PORT datab (1491:1491:1491) (1605:1605:1605)) - (PORT datac (1593:1593:1593) (1631:1631:1631)) - (PORT datad (953:953:953) (980:980:980)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~54) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1176:1176:1176)) - (PORT datab (662:662:662) (691:691:691)) - (PORT datac (1163:1163:1163) (1238:1238:1238)) - (PORT datad (898:898:898) (985:985:985)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (689:689:689)) - (PORT datab (1319:1319:1319) (1372:1372:1372)) - (PORT datac (624:624:624) (642:642:642)) - (PORT datad (866:866:866) (881:881:881)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1259:1259:1259)) - (PORT datab (974:974:974) (1000:1000:1000)) - (PORT datac (255:255:255) (313:313:313)) - (PORT datad (1134:1134:1134) (1181:1181:1181)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1200:1200:1200) (1254:1254:1254)) - (PORT datab (606:606:606) (649:649:649)) - (PORT datac (872:872:872) (901:901:901)) - (PORT datad (807:807:807) (862:862:862)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (1002:1002:1002)) - (PORT datab (1460:1460:1460) (1527:1527:1527)) - (PORT datac (2859:2859:2859) (2966:2966:2966)) - (PORT datad (229:229:229) (304:304:304)) + (PORT dataa (357:357:357) (403:403:403)) + (PORT datab (972:972:972) (1030:1030:1030)) + (PORT datac (930:930:930) (954:954:954)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (1419:1419:1419) (1546:1546:1546)) - (PORT datab (1084:1084:1084) (1106:1106:1106)) - (PORT datac (1238:1238:1238) (1330:1330:1330)) - (PORT datad (2052:2052:2052) (2171:2171:2171)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1150:1150:1150)) - (PORT datab (384:384:384) (410:410:410)) - (PORT datac (820:820:820) (894:894:894)) - (PORT datad (1655:1655:1655) (1717:1717:1717)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49494,10 +52360,58 @@ (INSTANCE z80_\|execute_\|setM1\~24) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (927:927:927) (989:989:989)) - (PORT datac (864:864:864) (890:890:890)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (998:998:998) (1081:1081:1081)) + (PORT datab (259:259:259) (340:340:340)) + (PORT datac (1964:1964:1964) (2044:2044:2044)) + (PORT datad (1190:1190:1190) (1261:1261:1261)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1369:1369:1369)) + (PORT datab (1243:1243:1243) (1338:1338:1338)) + (PORT datac (1428:1428:1428) (1523:1523:1523)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1137:1137:1137)) + (PORT datab (921:921:921) (958:958:958)) + (PORT datac (639:639:639) (666:666:666)) + (PORT datad (870:870:870) (922:922:922)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (968:968:968) (1008:1008:1008)) + (PORT datac (1088:1088:1088) (1107:1107:1107)) + (PORT datad (1330:1330:1330) (1333:1333:1333)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -49510,76 +52424,28 @@ (INSTANCE z80_\|execute_\|setM1\~28) (DELAY (ABSOLUTE - (PORT dataa (541:541:541) (570:570:570)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (611:611:611) (630:630:630)) - (PORT datad (875:875:875) (908:908:908)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1172:1172:1172)) - (PORT datab (1952:1952:1952) (2000:2000:2000)) - (PORT datac (939:939:939) (1020:1020:1020)) - (PORT datad (1208:1208:1208) (1249:1249:1249)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1344:1344:1344) (1436:1436:1436)) + (PORT datab (1393:1393:1393) (1505:1505:1505)) + (PORT datac (812:812:812) (849:849:849)) + (PORT datad (1233:1233:1233) (1285:1285:1285)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1722:1722:1722) (1767:1767:1767)) - (PORT datab (2033:2033:2033) (2073:2073:2073)) - (PORT datac (1628:1628:1628) (1671:1671:1671)) - (PORT datad (1597:1597:1597) (1619:1619:1619)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~29) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (886:886:886)) - (PORT datab (832:832:832) (896:896:896)) - (PORT datac (869:869:869) (939:939:939)) - (PORT datad (1271:1271:1271) (1354:1354:1354)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1190:1190:1190)) - (PORT datab (884:884:884) (932:932:932)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1296:1296:1296) (1353:1353:1353)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1384:1384:1384) (1443:1443:1443)) + (PORT datab (1127:1127:1127) (1145:1145:1145)) + (PORT datac (1371:1371:1371) (1467:1467:1467)) + (PORT datad (1097:1097:1097) (1131:1131:1131)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49587,64 +52453,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) + (INSTANCE z80_\|execute_\|setM1\~27) (DELAY (ABSOLUTE - (PORT dataa (880:880:880) (942:942:942)) - (PORT datab (1536:1536:1536) (1590:1590:1590)) - (PORT datac (1141:1141:1141) (1163:1163:1163)) - (PORT datad (1571:1571:1571) (1615:1615:1615)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1949:1949:1949) (2046:2046:2046)) + (PORT datab (1433:1433:1433) (1467:1467:1467)) + (PORT datac (624:624:624) (676:676:676)) + (PORT datad (945:945:945) (1000:1000:1000)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1781:1781:1781) (1842:1842:1842)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1086:1086:1086) (1118:1118:1118)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|setM1\~34) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (883:883:883)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (845:845:845) (843:843:843)) - (PORT datad (1659:1659:1659) (1685:1685:1685)) - (IOPATH dataa combout (303:303:303) (299:299:299)) + (PORT dataa (948:948:948) (1020:1020:1020)) + (PORT datab (1495:1495:1495) (1555:1555:1555)) + (PORT datac (863:863:863) (896:896:896)) + (PORT datad (607:607:607) (623:623:623)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1993:1993:1993) (2079:2079:2079)) + (PORT datab (1406:1406:1406) (1502:1502:1502)) + (PORT datac (965:965:965) (1047:1047:1047)) + (PORT datad (1191:1191:1191) (1262:1262:1262)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (988:988:988)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datac (1656:1656:1656) (1675:1675:1675)) - (PORT datad (928:928:928) (961:961:961)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1254:1254:1254)) - (PORT datab (1283:1283:1283) (1356:1356:1356)) - (PORT datac (899:899:899) (912:912:912)) - (PORT datad (812:812:812) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49654,12 +52520,60 @@ (INSTANCE z80_\|execute_\|setM1\~35) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (893:893:893) (944:944:944)) + (PORT datab (1224:1224:1224) (1270:1270:1270)) + (PORT datac (356:356:356) (382:382:382)) + (PORT datad (613:613:613) (655:655:655)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (471:471:471)) + (PORT datab (949:949:949) (1019:1019:1019)) + (PORT datac (946:946:946) (998:998:998)) + (PORT datad (1234:1234:1234) (1287:1287:1287)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1329:1329:1329)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (572:572:572) (591:591:591)) + (PORT datad (1209:1209:1209) (1278:1278:1278)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (292:292:292)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49667,15 +52581,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) + (INSTANCE z80_\|execute_\|setM1\~56) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (662:662:662)) - (PORT datab (1239:1239:1239) (1284:1284:1284)) - (PORT datac (1420:1420:1420) (1516:1516:1516)) - (PORT datad (610:610:610) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1879:1879:1879) (1973:1973:1973)) + (PORT datab (1953:1953:1953) (2083:2083:2083)) + (PORT datac (583:583:583) (597:597:597)) + (PORT datad (1178:1178:1178) (1226:1226:1226)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49683,13 +52597,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) + (INSTANCE z80_\|execute_\|setM1\~22) (DELAY (ABSOLUTE - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (607:607:607) (632:632:632)) - (PORT datad (1915:1915:1915) (1966:1966:1966)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1926:1926:1926) (1950:1950:1950)) + (PORT datab (656:656:656) (704:704:704)) + (PORT datac (936:936:936) (979:979:979)) + (PORT datad (616:616:616) (630:630:630)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49697,13 +52613,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) + (INSTANCE z80_\|execute_\|setM1\~23) (DELAY (ABSOLUTE - (PORT dataa (1167:1167:1167) (1219:1219:1219)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1354:1354:1354) (1355:1355:1355)) + (PORT dataa (230:230:230) (278:278:278)) + (PORT datab (1154:1154:1154) (1179:1179:1179)) + (PORT datac (1373:1373:1373) (1469:1469:1469)) + (PORT datad (172:172:172) (198:198:198)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -49713,15 +52629,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) + (INSTANCE z80_\|execute_\|setM1\~37) (DELAY (ABSOLUTE - (PORT dataa (1152:1152:1152) (1228:1228:1228)) - (PORT datab (1143:1143:1143) (1197:1197:1197)) - (PORT datac (1388:1388:1388) (1456:1456:1456)) - (PORT datad (1311:1311:1311) (1375:1375:1375)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (598:598:598) (619:619:619)) + (PORT datab (641:641:641) (691:691:691)) + (PORT datac (613:613:613) (634:634:634)) + (PORT datad (604:604:604) (620:620:620)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49732,152 +52648,12 @@ (INSTANCE z80_\|execute_\|setM1\~12) (DELAY (ABSOLUTE - (PORT dataa (1124:1124:1124) (1140:1140:1140)) - (PORT datab (1614:1614:1614) (1768:1768:1768)) - (PORT datac (1340:1340:1340) (1376:1376:1376)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (938:938:938)) - (PORT datab (1149:1149:1149) (1249:1249:1249)) - (PORT datac (666:666:666) (774:774:774)) - (PORT datad (876:876:876) (897:897:897)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (949:949:949)) - (PORT datac (1502:1502:1502) (1602:1602:1602)) - (PORT datad (838:838:838) (846:846:846)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (1193:1193:1193) (1237:1237:1237)) - (PORT datac (1207:1207:1207) (1228:1228:1228)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (979:979:979)) - (PORT datab (685:685:685) (706:706:706)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (1969:1969:1969) (2022:2022:2022)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (970:970:970)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1488:1488:1488) (1575:1575:1575)) - (PORT datad (633:633:633) (645:645:645)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1166:1166:1166)) - (PORT datab (1111:1111:1111) (1226:1226:1226)) - (PORT datac (565:565:565) (580:580:580)) - (PORT datad (818:818:818) (823:823:823)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1729:1729:1729) (1815:1815:1815)) - (PORT datab (1999:1999:1999) (2067:2067:2067)) - (PORT datac (939:939:939) (999:999:999)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1000:1000:1000) (1047:1047:1047)) - (PORT datab (1000:1000:1000) (1036:1036:1036)) - (PORT datac (170:170:170) (201:201:201)) - (PORT datad (937:937:937) (978:978:978)) + (PORT dataa (628:628:628) (655:655:655)) + (PORT datab (1195:1195:1195) (1223:1223:1223)) + (PORT datac (1161:1161:1161) (1182:1182:1182)) + (PORT datad (1145:1145:1145) (1184:1184:1184)) (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1471:1471:1471) (1555:1555:1555)) - (PORT datab (1379:1379:1379) (1419:1419:1419)) - (PORT datac (1473:1473:1473) (1586:1586:1586)) - (PORT datad (591:591:591) (624:624:624)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49885,61 +52661,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) + (INSTANCE z80_\|execute_\|setM1\~14) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (346:346:346) (362:362:362)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (680:680:680) (726:726:726)) - (PORT datad (894:894:894) (909:909:909)) + (PORT dataa (1233:1233:1233) (1273:1273:1273)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (2066:2066:2066) (2111:2111:2111)) + (PORT datad (613:613:613) (656:656:656)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) + (INSTANCE z80_\|execute_\|setM1\~10) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (915:915:915) (992:992:992)) - (PORT datac (1353:1353:1353) (1387:1387:1387)) - (PORT datad (360:360:360) (381:381:381)) + (PORT dataa (1230:1230:1230) (1301:1301:1301)) + (PORT datab (1309:1309:1309) (1419:1419:1419)) + (PORT datac (1183:1183:1183) (1222:1222:1222)) + (PORT datad (1272:1272:1272) (1370:1370:1370)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -49949,28 +52693,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (INSTANCE z80_\|execute_\|setM1\~11) (DELAY (ABSOLUTE - (PORT dataa (621:621:621) (652:652:652)) - (PORT datab (1116:1116:1116) (1149:1149:1149)) - (PORT datac (905:905:905) (992:992:992)) - (PORT datad (546:546:546) (553:553:553)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT datab (1494:1494:1494) (1578:1578:1578)) + (PORT datac (920:920:920) (944:944:944)) + (PORT datad (909:909:909) (950:950:950)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (665:665:665)) + (PORT datab (371:371:371) (394:394:394)) + (PORT datac (200:200:200) (238:238:238)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (814:814:814) (861:861:861)) + (PORT datac (637:637:637) (662:662:662)) + (PORT datad (899:899:899) (931:931:931)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (648:648:648)) + (PORT datab (863:863:863) (880:880:880)) + (PORT datac (587:587:587) (630:630:630)) + (PORT datad (923:923:923) (967:967:967)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (2597:2597:2597) (2742:2742:2742)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) (DELAY (ABSOLUTE - (PORT datab (705:705:705) (765:765:765)) - (PORT datad (895:895:895) (911:911:911)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1268:1268:1268) (1348:1348:1348)) + (PORT datad (972:972:972) (1033:1033:1033)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49981,9 +52787,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -49994,14 +52800,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) + (INSTANCE z80_\|resets_\|clrpc_int\~0) (DELAY (ABSOLUTE - (PORT dataa (661:661:661) (724:724:724)) - (PORT datab (720:720:720) (764:764:764)) - (PORT datad (890:890:890) (904:904:904)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (409:409:409) (485:485:485)) + (PORT datab (1783:1783:1783) (1915:1915:1915)) + (PORT datad (1344:1344:1344) (1503:1503:1503)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50009,12 +52815,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|resets_\|clrpc_int) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT clrn (1904:1904:1904) (1884:1884:1884)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50025,28 +52831,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT datab (982:982:982) (1081:1081:1081)) - (PORT datac (1243:1243:1243) (1342:1342:1342)) - (PORT datad (957:957:957) (1051:1051:1051)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (1537:1537:1537) (1666:1666:1666)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (224:224:224) (295:295:295)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT asdata (564:564:564) (641:641:641)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1274:1274:1274)) + (PORT datab (248:248:248) (333:333:333)) + (PORT datad (223:223:223) (294:294:294)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|address_latch_\|abusz\[0\]) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (1482:1482:1482) (1540:1540:1540)) - (PORT datad (1185:1185:1185) (1227:1227:1227)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (672:672:672) (713:713:713)) + (PORT datad (838:838:838) (847:847:847)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50056,11 +52923,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1177:1177:1177) (1260:1260:1260)) - (PORT datab (837:837:837) (857:857:857)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (382:382:382) (410:410:410)) + (PORT datab (888:888:888) (956:956:956)) + (PORT datad (897:897:897) (934:934:934)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50070,11 +52937,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT clk (1522:1522:1522) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (707:707:707) (769:769:769)) - (PORT sload (1432:1432:1432) (1514:1514:1514)) - (PORT ena (1459:1459:1459) (1480:1480:1480)) + (PORT asdata (917:917:917) (971:971:971)) + (PORT sload (1262:1262:1262) (1326:1326:1326)) + (PORT ena (1743:1743:1743) (1759:1759:1759)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50087,59 +52954,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~66) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~2) (DELAY (ABSOLUTE - (PORT datab (902:902:902) (924:924:924)) - (PORT datac (872:872:872) (926:926:926)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (2781:2781:2781) (2888:2888:2888)) - (PORT datab (1476:1476:1476) (1559:1559:1559)) - (PORT datac (1480:1480:1480) (1521:1521:1521)) - (PORT datad (308:308:308) (323:323:323)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (2634:2634:2634) (2765:2765:2765)) - (PORT datab (1935:1935:1935) (2079:2079:2079)) - (PORT datac (2771:2771:2771) (3001:3001:3001)) - (PORT datad (2441:2441:2441) (2545:2545:2545)) + (PORT dataa (641:641:641) (666:666:666)) + (PORT datab (956:956:956) (1029:1029:1029)) + (PORT datac (713:713:713) (817:817:817)) + (PORT datad (898:898:898) (904:904:904)) (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~68) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (709:709:709)) - (PORT datac (1085:1085:1085) (1132:1132:1132)) - (PORT datad (350:350:350) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (342:342:342) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50147,73 +52970,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~69) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (2782:2782:2782) (2888:2888:2888)) - (PORT datab (949:949:949) (1041:1041:1041)) - (PORT datac (1479:1479:1479) (1520:1520:1520)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (910:910:910) (934:934:934)) + (PORT datab (955:955:955) (1026:1026:1026)) + (PORT datac (929:929:929) (954:954:954)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT datab (1161:1161:1161) (1224:1224:1224)) - (PORT datac (844:844:844) (887:887:887)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (2196:2196:2196) (2279:2279:2279)) - (PORT datab (635:635:635) (666:666:666)) - (PORT datac (1696:1696:1696) (1794:1794:1794)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (2780:2780:2780) (2885:2885:2885)) - (PORT datac (912:912:912) (1002:1002:1002)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (409:409:409)) - (PORT datab (946:946:946) (982:982:982)) - (PORT datac (332:332:332) (348:348:348)) - (PORT datad (334:334:334) (351:351:351)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50221,121 +52986,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~95) + (INSTANCE Selector14\~15) (DELAY (ABSOLUTE - (PORT dataa (917:917:917) (978:978:978)) - (PORT datab (917:917:917) (942:942:942)) - (PORT datac (181:181:181) (218:218:218)) + (PORT dataa (1279:1279:1279) (1345:1345:1345)) + (PORT datab (1007:1007:1007) (1111:1111:1111)) + (PORT datac (1507:1507:1507) (1558:1558:1558)) + (PORT datad (1206:1206:1206) (1261:1261:1261)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~96) + (INSTANCE Selector14\~16) (DELAY (ABSOLUTE - (PORT dataa (1289:1289:1289) (1374:1374:1374)) - (PORT datab (436:436:436) (474:474:474)) - (PORT datac (2209:2209:2209) (2279:2279:2279)) + (PORT dataa (1207:1207:1207) (1255:1255:1255)) + (PORT datab (1008:1008:1008) (1109:1109:1109)) + (PORT datac (1260:1260:1260) (1276:1276:1276)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~126) + (INSTANCE D\[0\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1874:1874:1874) (1923:1923:1923)) - (PORT datab (3091:3091:3091) (3312:3312:3312)) - (PORT datac (627:627:627) (639:639:639)) - (PORT datad (321:321:321) (343:343:343)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (817:817:817) (825:825:825)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (617:617:617) (644:644:644)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~98) + (INSTANCE D\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1201:1201:1201) (1291:1291:1291)) - (PORT datab (672:672:672) (697:697:697)) - (PORT datac (2459:2459:2459) (2525:2525:2525)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~105) - (DELAY - (ABSOLUTE - (PORT datab (873:873:873) (921:921:921)) - (PORT datac (364:364:364) (389:389:389)) - (PORT datad (349:349:349) (365:365:365)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1328:1328:1328)) - (PORT datab (636:636:636) (664:664:664)) - (PORT datac (2169:2169:2169) (2244:2244:2244)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (2802:2802:2802) (3046:3046:3046)) - (PORT datab (2034:2034:2034) (2097:2097:2097)) - (PORT datac (180:180:180) (219:219:219)) - (PORT datad (615:615:615) (641:641:641)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1207:1207:1207) (1304:1304:1304)) - (PORT datab (2479:2479:2479) (2586:2586:2586)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (1030:1030:1030) (1119:1119:1119)) + (PORT datab (1732:1732:1732) (1813:1813:1813)) + (PORT datac (192:192:192) (224:224:224)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50345,12 +53050,381 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~4) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (857:857:857) (879:879:879)) - (PORT datad (230:230:230) (303:303:303)) + (PORT dataa (979:979:979) (1066:1066:1066)) + (PORT datab (1141:1141:1141) (1220:1220:1220)) + (PORT datac (778:778:778) (792:792:792)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1146:1146:1146)) + (PORT datab (948:948:948) (1043:1043:1043)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1357:1357:1357) (1395:1395:1395)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1118:1118:1118)) + (PORT datab (1168:1168:1168) (1239:1239:1239)) + (PORT datac (1107:1107:1107) (1139:1139:1139)) + (PORT datad (1421:1421:1421) (1463:1463:1463)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector12\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1122:1122:1122)) + (PORT datab (1409:1409:1409) (1443:1443:1443)) + (PORT datac (1673:1673:1673) (1756:1756:1756)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1224:1224:1224)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (343:343:343) (363:363:363)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1232:1232:1232)) + (PORT datab (1087:1087:1087) (1216:1216:1216)) + (PORT datac (1464:1464:1464) (1518:1518:1518)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (326:326:326) (354:354:354)) + (PORT datad (966:966:966) (988:988:988)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (939:939:939)) + (PORT datab (695:695:695) (785:785:785)) + (PORT datac (1864:1864:1864) (1894:1894:1894)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (801:801:801)) + (PORT datab (436:436:436) (517:517:517)) + (PORT datac (904:904:904) (914:914:914)) + (PORT datad (1393:1393:1393) (1424:1424:1424)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1732:1732:1732) (1780:1780:1780)) + (PORT datab (435:435:435) (517:517:517)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1458:1458:1458) (1558:1558:1558)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1265:1265:1265)) + (PORT datab (1232:1232:1232) (1270:1270:1270)) + (PORT datac (641:641:641) (719:719:719)) + (PORT datad (1704:1704:1704) (1749:1749:1749)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1572:1572:1572)) + (PORT datab (464:464:464) (535:535:535)) + (PORT datac (1721:1721:1721) (1844:1844:1844)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1500:1500:1500)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1265:1265:1265)) + (PORT datab (1412:1412:1412) (1444:1444:1444)) + (PORT datac (1142:1142:1142) (1173:1173:1173)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (2006:2006:2006) (2095:2095:2095)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1508:1508:1508)) + (PORT datab (1117:1117:1117) (1224:1224:1224)) + (PORT datac (1237:1237:1237) (1262:1262:1262)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (960:960:960)) + (PORT datab (710:710:710) (788:788:788)) + (PORT datad (882:882:882) (895:895:895)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (678:678:678)) + (PORT datab (706:706:706) (783:783:783)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (886:886:886) (916:916:916)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1843:1843:1843)) + (PORT datab (278:278:278) (366:366:366)) + (PORT datac (1458:1458:1458) (1518:1518:1518)) + (PORT datad (1522:1522:1522) (1592:1592:1592)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (682:682:682)) + (PORT datab (2520:2520:2520) (2611:2611:2611)) + (PORT datac (1179:1179:1179) (1223:1223:1223)) + (PORT datad (182:182:182) (214:214:214)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (1281:1281:1281) (1370:1370:1370)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1559:1559:1559)) + (PORT datab (695:695:695) (768:768:768)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (1342:1342:1342) (1380:1380:1380)) + (PORT datac (936:936:936) (973:973:973)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1508:1508:1508)) + (PORT datab (1185:1185:1185) (1226:1226:1226)) + (PORT datac (912:912:912) (953:953:953)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50362,12 +53436,12 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (706:706:706) (760:760:760)) - (PORT datac (668:668:668) (739:739:739)) - (PORT datad (617:617:617) (675:675:675)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (266:266:266) (354:354:354)) + (PORT datab (275:275:275) (362:362:362)) + (PORT datac (1225:1225:1225) (1299:1299:1299)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -50376,10 +53450,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50394,7 +53468,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (673:673:673) (730:730:730)) + (PORT datad (1405:1405:1405) (1466:1466:1466)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50404,10 +53478,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT clk (1518:1518:1518) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50422,10 +53496,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1530:1530:1530)) - (PORT asdata (569:569:569) (648:648:648)) - (PORT clrn (1581:1581:1581) (1557:1557:1557)) - (PORT ena (1253:1253:1253) (1263:1263:1263)) + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT asdata (567:567:567) (647:647:647)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1565:1565:1565) (1581:1581:1581)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50440,9 +53514,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (915:915:915) (998:998:998)) - (PORT datab (253:253:253) (338:338:338)) - (PORT datad (224:224:224) (295:295:295)) + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (630:630:630) (703:703:703)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50455,10 +53529,10 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (249:249:249) (340:340:340)) - (PORT datab (259:259:259) (348:348:348)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (180:180:180) (210:210:210)) + (PORT dataa (580:580:580) (620:620:620)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (1090:1090:1090) (1162:1162:1162)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50489,9 +53563,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50505,7 +53579,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (406:406:406) (480:480:480)) + (PORT dataa (403:403:403) (479:479:479)) (PORT datab (251:251:251) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) @@ -50520,9 +53594,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50550,9 +53624,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50580,9 +53654,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50591,22 +53665,6 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (264:264:264) (347:347:347)) - (PORT datac (223:223:223) (302:302:302)) - (PORT datad (225:225:225) (297:297:297)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) @@ -50626,9 +53684,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50642,7 +53700,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -50653,9 +53711,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT clk (1910:1910:1910) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50664,47 +53722,45 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (235:235:235) (311:311:311)) + (PORT datad (224:224:224) (297:297:297)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (224:224:224) (305:305:305)) - (PORT datad (225:225:225) (295:295:295)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (222:222:222) (301:301:301)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) - (PORT ena (1023:1023:1023) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1902:1902:1902) (1923:1923:1923)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1414:1414:1414) (1389:1389:1389)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50719,7 +53775,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (410:410:410) (477:477:477)) + (PORT datad (256:256:256) (330:330:330)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50730,10 +53786,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1597:1597:1597) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50748,9 +53804,9 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (453:453:453) (522:522:522)) - (PORT datad (395:395:395) (465:465:465)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datab (282:282:282) (369:369:369)) + (PORT datad (286:286:286) (369:369:369)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50761,10 +53817,28 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1565:1565:1565) (1557:1557:1557)) - (PORT ena (881:881:881) (820:820:820)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1597:1597:1597) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1902:1902:1902) (1923:1923:1923)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1414:1414:1414) (1389:1389:1389)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50779,9 +53853,9 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datab (455:455:455) (531:531:531)) - (PORT datac (266:266:266) (353:353:353)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (641:641:641) (716:716:716)) + (PORT datac (604:604:604) (665:665:665)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) @@ -50791,366 +53865,23 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (471:471:471) (542:542:542)) - (PORT datac (574:574:574) (630:630:630)) - (PORT datad (871:871:871) (934:934:934)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~4) - (DELAY - (ABSOLUTE - (PORT datad (701:701:701) (764:764:764)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (494:494:494)) - (PORT datab (652:652:652) (716:716:716)) - (PORT datad (718:718:718) (781:781:781)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT datab (472:472:472) (547:547:547)) + (PORT datad (730:730:730) (802:802:802)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (469:469:469) (541:541:541)) - (PORT datac (593:593:593) (652:652:652)) - (PORT datad (281:281:281) (362:362:362)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (605:605:605) (665:665:665)) - (PORT datac (628:628:628) (682:682:682)) - (PORT datad (856:856:856) (911:911:911)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (687:687:687)) - (PORT datab (642:642:642) (659:659:659)) - (PORT datac (634:634:634) (701:701:701)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1904:1904:1904) (1924:1924:1924)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1561:1561:1561)) - (PORT ena (1204:1204:1204) (1189:1189:1189)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~5) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (807:807:807)) - (PORT datad (388:388:388) (450:450:450)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1561:1561:1561)) - (PORT ena (1235:1235:1235) (1239:1239:1239)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (262:262:262) (351:351:351)) - (PORT datad (381:381:381) (445:445:445)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT datab (456:456:456) (528:528:528)) - (PORT datac (269:269:269) (358:358:358)) - (PORT datad (668:668:668) (706:706:706)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT datab (473:473:473) (541:541:541)) - (PORT datac (595:595:595) (653:653:653)) - (PORT datad (282:282:282) (363:363:363)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT datab (457:457:457) (530:530:530)) - (PORT datac (268:268:268) (356:356:356)) - (PORT datad (336:336:336) (359:359:359)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (688:688:688) (708:708:708)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sload (875:875:875) (1000:1000:1000)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (809:809:809)) - (PORT datab (260:260:260) (350:350:350)) - (PORT datad (384:384:384) (449:449:449)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1561:1561:1561)) - (PORT ena (1235:1235:1235) (1239:1239:1239)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (344:344:344)) - (PORT datab (407:407:407) (482:482:482)) - (PORT datac (887:887:887) (938:938:938)) - (PORT datad (236:236:236) (314:314:314)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (364:364:364)) - (PORT datab (308:308:308) (401:401:401)) - (PORT datac (572:572:572) (628:628:628)) - (PORT datad (619:619:619) (673:673:673)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (690:690:690)) - (PORT datab (661:661:661) (732:732:732)) - (PORT datac (627:627:627) (680:680:680)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (667:667:667)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (857:857:857) (913:913:913)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1927:1927:1927) (1950:1950:1950)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datac (668:668:668) (736:736:736)) - (PORT datad (436:436:436) (501:501:501)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (899:899:899) (962:962:962)) + (PORT datac (585:585:585) (643:643:643)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -51168,10 +53899,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (418:418:418) (494:494:494)) - (PORT datab (754:754:754) (826:826:826)) - (PORT datac (239:239:239) (316:316:316)) - (PORT datad (508:508:508) (502:502:502)) + (PORT dataa (430:430:430) (498:498:498)) + (PORT datab (473:473:473) (547:547:547)) + (PORT datac (261:261:261) (347:347:347)) + (PORT datad (682:682:682) (664:664:664)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51184,13 +53915,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (376:376:376)) - (PORT datab (646:646:646) (667:667:667)) - (PORT datac (618:618:618) (676:676:676)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (769:769:769) (848:848:848)) + (PORT datab (657:657:657) (677:677:677)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51200,11 +53931,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (712:712:712)) - (PORT datab (626:626:626) (641:641:641)) - (PORT datad (174:174:174) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT datab (424:424:424) (497:497:497)) + (PORT datac (830:830:830) (829:829:829)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51214,28 +53945,386 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT asdata (689:689:689) (712:712:712)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (848:848:848)) + (PORT datab (474:474:474) (550:550:550)) + (PORT datad (280:280:280) (360:360:360)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (895:895:895) (965:965:965)) + (PORT datac (261:261:261) (349:349:349)) + (PORT datad (279:279:279) (359:359:359)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT datab (642:642:642) (706:706:706)) + (PORT datac (421:421:421) (491:491:491)) + (PORT datad (511:511:511) (521:521:521)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~5) + (DELAY + (ABSOLUTE + (PORT datad (430:430:430) (498:498:498)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (716:716:716)) + (PORT datab (278:278:278) (365:365:365)) + (PORT datac (601:601:601) (663:663:663)) + (PORT datad (272:272:272) (354:354:354)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (528:528:528)) + (PORT datac (262:262:262) (350:350:350)) + (PORT datad (279:279:279) (355:355:355)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (269:269:269)) + (PORT datab (605:605:605) (620:620:620)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (725:725:725) (796:796:796)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (411:411:411)) + (PORT datab (280:280:280) (368:368:368)) + (PORT datac (609:609:609) (635:635:635)) + (PORT datad (800:800:800) (807:807:807)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (922:922:922) (904:904:904)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datad (254:254:254) (329:329:329)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (722:722:722)) + (PORT datac (605:605:605) (670:670:670)) + (PORT datad (539:539:539) (546:546:546)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (393:393:393)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (716:716:716) (747:747:747)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT sload (873:873:873) (990:990:990)) + (PORT ena (1439:1439:1439) (1421:1421:1421)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (458:458:458) (539:539:539)) + (PORT datad (252:252:252) (326:326:326)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (922:922:922) (904:904:904)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (512:512:512)) + (PORT datab (453:453:453) (536:536:536)) + (PORT datad (253:253:253) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (922:922:922) (904:904:904)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (275:275:275) (361:361:361)) + (PORT datac (386:386:386) (445:445:445)) + (PORT datad (422:422:422) (488:488:488)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (356:356:356)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (232:232:232) (316:316:316)) + (PORT datad (255:255:255) (331:331:331)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (443:443:443)) + (PORT datab (866:866:866) (912:912:912)) + (PORT datac (361:361:361) (382:382:382)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (850:850:850) (858:858:858)) + (PORT datad (272:272:272) (354:354:354)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT datab (471:471:471) (540:540:540)) - (PORT datac (593:593:593) (650:650:650)) - (PORT datad (278:278:278) (360:360:360)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT datab (900:900:900) (966:966:966)) + (PORT datac (263:263:263) (351:351:351)) + (PORT datad (280:280:280) (356:356:356)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51246,9 +54335,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (689:689:689)) - (PORT datab (639:639:639) (655:655:655)) - (PORT datad (175:175:175) (200:200:200)) + (PORT dataa (404:404:404) (444:444:444)) + (PORT datab (850:850:850) (858:858:858)) + (PORT datad (501:501:501) (512:512:512)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51261,9 +54350,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1927:1927:1927) (1950:1950:1950)) + (PORT clk (1534:1534:1534) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51277,12 +54366,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (362:362:362)) - (PORT datab (886:886:886) (951:951:951)) - (PORT datac (804:804:804) (848:848:848)) - (PORT datad (872:872:872) (930:930:930)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (642:642:642) (717:717:717)) + (PORT datab (260:260:260) (348:348:348)) + (PORT datac (605:605:605) (666:666:666)) + (PORT datad (278:278:278) (360:360:360)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51293,7 +54382,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (296:296:296) (389:389:389)) + (PORT datab (317:317:317) (418:418:418)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51302,13 +54391,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (655:655:655)) - (PORT datab (936:936:936) (980:980:980)) - (PORT datac (623:623:623) (676:676:676)) - (PORT datad (708:708:708) (690:690:690)) + (PORT dataa (620:620:620) (690:690:690)) + (PORT datab (453:453:453) (510:510:510)) + (PORT datac (729:729:729) (706:706:706)) + (PORT datad (375:375:375) (432:432:432)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51321,12 +54410,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (640:640:640)) - (PORT datab (457:457:457) (514:514:514)) - (PORT datac (786:786:786) (833:833:833)) - (PORT datad (176:176:176) (203:203:203)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (679:679:679) (741:741:741)) + (PORT datab (823:823:823) (820:820:820)) + (PORT datac (851:851:851) (907:907:907)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51337,11 +54426,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2650:2650:2650) (2671:2671:2671)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT asdata (2197:2197:2197) (2211:2211:2211)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51359,9 +54448,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (293:293:293) (394:394:394)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (289:289:289) (399:399:399)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51373,11 +54462,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2650:2650:2650) (2671:2671:2671)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT asdata (2197:2197:2197) (2211:2211:2211)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51395,9 +54484,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (412:412:412)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (301:301:301) (402:402:402)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51409,10 +54498,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51430,9 +54519,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (299:299:299) (395:395:395)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (289:289:289) (386:386:386)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -51444,11 +54533,43 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) + (PORT clk (1876:1876:1876) (1889:1889:1889)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2652:2652:2652) (2668:2668:2668)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT asdata (2198:2198:2198) (2213:2213:2213)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datad (276:276:276) (358:358:358)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1876:1876:1876) (1889:1889:1889)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT sload (1268:1268:1268) (1239:1239:1239)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51466,58 +54587,26 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (430:430:430) (520:520:520)) - (PORT datab (294:294:294) (394:394:394)) - (PORT datac (269:269:269) (375:375:375)) - (PORT datad (277:277:277) (359:359:359)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (295:295:295) (407:407:407)) + (PORT datab (304:304:304) (406:406:406)) + (PORT datac (295:295:295) (393:393:393)) + (PORT datad (263:263:263) (346:346:346)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (405:405:405)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1914:1914:1914)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1559:1559:1559)) - (PORT sload (1538:1538:1538) (1516:1516:1516)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (349:349:349) (374:374:374)) - (PORT datad (401:401:401) (464:464:464)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datac (612:612:612) (667:667:667)) + (PORT datad (502:502:502) (510:510:510)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51528,11 +54617,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (409:409:409) (485:485:485)) - (PORT datab (477:477:477) (546:546:546)) - (PORT datad (869:869:869) (920:920:920)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT datab (279:279:279) (368:368:368)) + (PORT datac (231:231:231) (315:315:315)) + (PORT datad (274:274:274) (356:356:356)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51542,13 +54631,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) (DELAY (ABSOLUTE - (PORT dataa (553:553:553) (572:572:572)) - (PORT datab (273:273:273) (357:357:357)) - (PORT datac (255:255:255) (340:340:340)) - (PORT datad (668:668:668) (704:704:704)) + (PORT dataa (225:225:225) (269:269:269)) + (PORT datab (305:305:305) (401:401:401)) + (PORT datac (231:231:231) (316:316:316)) + (PORT datad (541:541:541) (547:547:547)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51558,13 +54647,13 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (432:432:432) (515:515:515)) - (PORT datac (261:261:261) (346:346:346)) - (PORT datad (220:220:220) (258:258:258)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (866:866:866) (917:917:917)) + (PORT datac (367:367:367) (400:400:400)) + (PORT datad (263:263:263) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51574,11 +54663,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (910:910:910) (941:941:941)) - (PORT datab (630:630:630) (649:649:649)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (854:854:854) (863:863:863)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51589,9 +54678,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1534:1534:1534) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51605,11 +54694,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (249:249:249) (302:302:302)) - (PORT datab (274:274:274) (359:359:359)) - (PORT datad (405:405:405) (476:476:476)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (263:263:263) (356:356:356)) + (PORT datab (869:869:869) (918:918:918)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51620,10 +54709,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1534:1534:1534) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (1502:1502:1502) (1473:1473:1473)) + (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT ena (1439:1439:1439) (1421:1421:1421)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51638,12 +54727,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (701:701:701) (768:768:768)) - (PORT datac (620:620:620) (679:679:679)) - (PORT datad (717:717:717) (779:779:779)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (298:298:298) (403:403:403)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datac (717:717:717) (801:801:801)) + (PORT datad (285:285:285) (372:372:372)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51654,10 +54743,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datac (617:617:617) (676:676:676)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (713:713:713) (796:796:796)) + (PORT datad (601:601:601) (618:618:618)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51669,9 +54758,9 @@ (DELAY (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) - (PORT d (958:958:958) (1002:1002:1002)) + (PORT d (993:993:993) (1024:1024:1024)) (PORT aload (1697:1697:1697) (1760:1760:1760)) - (PORT ena (723:723:723) (714:714:714)) + (PORT ena (873:873:873) (869:869:869)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -51688,368 +54777,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1902:1902:1902) (1923:1923:1923)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1560:1560:1560)) - (PORT ena (1023:1023:1023) (976:976:976)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (516:516:516)) - (PORT datab (290:290:290) (389:389:389)) - (PORT datac (264:264:264) (368:368:368)) - (PORT datad (275:275:275) (353:353:353)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (616:616:616) (672:672:672)) - (PORT datad (868:868:868) (917:917:917)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (517:517:517)) - (PORT datab (292:292:292) (393:393:393)) - (PORT datac (276:276:276) (370:370:370)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (419:419:419)) - (PORT datab (584:584:584) (592:592:592)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (269:269:269) (349:349:349)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (418:418:418)) - (PORT datab (294:294:294) (385:385:385)) - (PORT datac (278:278:278) (369:369:369)) - (PORT datad (274:274:274) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (586:586:586)) - (PORT datab (293:293:293) (393:393:393)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (269:269:269) (349:349:349)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (493:493:493) (580:580:580)) - (PORT datac (679:679:679) (744:744:744)) - (PORT datad (662:662:662) (723:723:723)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT datab (280:280:280) (368:368:368)) - (PORT datac (265:265:265) (353:353:353)) - (PORT datad (417:417:417) (491:491:491)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (365:365:365) (400:400:400)) - (PORT datac (264:264:264) (352:352:352)) - (PORT datad (215:215:215) (253:253:253)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (936:936:936)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (410:410:410) (480:480:480)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sclr (1298:1298:1298) (1370:1370:1370)) - (PORT ena (949:949:949) (938:938:938)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sclr (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) - (DELAY - (ABSOLUTE - (PORT datab (629:629:629) (656:656:656)) - (PORT datac (457:457:457) (542:542:542)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (516:516:516)) - (PORT datab (365:365:365) (396:396:396)) - (PORT datac (266:266:266) (352:352:352)) - (PORT datad (420:420:420) (487:487:487)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (300:300:300)) - (PORT datab (281:281:281) (369:369:369)) - (PORT datac (258:258:258) (346:346:346)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (940:940:940)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (409:409:409) (478:478:478)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (649:649:649)) - (PORT datac (456:456:456) (542:542:542)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (418:418:418)) - (PORT datab (293:293:293) (393:393:393)) - (PORT datac (277:277:277) (370:370:370)) - (PORT datad (274:274:274) (355:355:355)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (418:418:418)) - (PORT datac (279:279:279) (373:373:373)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (625:625:625)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (681:681:681) (740:740:740)) - (PORT datad (662:662:662) (720:720:720)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (334:334:334)) - (PORT datab (831:831:831) (881:881:881)) - (PORT datac (460:460:460) (539:539:539)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) + (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT ena (1414:1414:1414) (1389:1389:1389)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52064,12 +54795,40 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (303:303:303) (418:418:418)) - (PORT datab (295:295:295) (395:395:395)) - (PORT datac (277:277:277) (371:371:371)) - (PORT datad (270:270:270) (351:351:351)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT datac (270:270:270) (367:367:367)) + (PORT datad (274:274:274) (356:356:356)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (398:398:398)) + (PORT datab (295:295:295) (399:399:399)) + (PORT datac (281:281:281) (381:381:381)) + (PORT datad (274:274:274) (352:352:352)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (644:644:644)) + (PORT datab (722:722:722) (794:794:794)) + (PORT datac (687:687:687) (752:752:752)) + (PORT datad (481:481:481) (496:496:496)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52080,12 +54839,138 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT dataa (687:687:687) (761:761:761)) - (PORT datab (657:657:657) (669:669:669)) - (PORT datac (679:679:679) (740:740:740)) - (PORT datad (329:329:329) (349:349:349)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (293:293:293) (405:405:405)) + (PORT datab (424:424:424) (496:496:496)) + (PORT datac (269:269:269) (371:371:371)) + (PORT datad (274:274:274) (356:356:356)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (643:643:643)) + (PORT datab (720:720:720) (794:794:794)) + (PORT datac (684:684:684) (752:752:752)) + (PORT datad (601:601:601) (611:611:611)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (861:861:861)) + (PORT datab (721:721:721) (793:793:793)) + (PORT datac (685:685:685) (751:751:751)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (406:406:406)) + (PORT datab (766:766:766) (836:836:836)) + (PORT datac (714:714:714) (799:799:799)) + (PORT datad (351:351:351) (380:380:380)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (317:317:317) (417:417:417)) + (PORT datac (565:565:565) (610:610:610)) + (PORT datad (801:801:801) (810:810:810)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1184:1184:1184) (1287:1287:1287)) + (PORT ena (1162:1162:1162) (1136:1136:1136)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (384:384:384)) + (PORT datab (304:304:304) (407:407:407)) + (PORT datac (293:293:293) (394:394:394)) + (PORT datad (273:273:273) (353:353:353)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~6) + (DELAY + (ABSOLUTE + (PORT datab (288:288:288) (379:379:379)) + (PORT datad (274:274:274) (357:357:357)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (821:821:821) (843:843:843)) + (PORT datac (294:294:294) (392:392:392)) + (PORT datad (265:265:265) (361:361:361)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52093,20 +54978,196 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) (DELAY (ABSOLUTE (PORT dataa (247:247:247) (335:335:335)) - (PORT datab (832:832:832) (884:884:884)) - (PORT datac (457:457:457) (542:542:542)) - (PORT datad (174:174:174) (200:200:200)) + (PORT datac (740:740:740) (820:820:820)) + (PORT datad (603:603:603) (613:613:613)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (401:401:401)) + (PORT datab (768:768:768) (833:833:833)) + (PORT datac (584:584:584) (638:638:638)) + (PORT datad (352:352:352) (377:377:377)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (751:751:751) (835:835:835)) + (PORT datac (607:607:607) (633:633:633)) + (PORT datad (728:728:728) (792:792:792)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (374:374:374) (395:395:395)) + (PORT datac (830:830:830) (829:829:829)) + (PORT datad (397:397:397) (458:458:458)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (408:408:408)) + (PORT datab (425:425:425) (497:497:497)) + (PORT datac (295:295:295) (393:393:393)) + (PORT datad (276:276:276) (358:358:358)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (303:303:303) (409:409:409)) + (PORT datac (292:292:292) (395:395:395)) + (PORT datad (813:813:813) (819:819:819)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (329:329:329)) + (PORT datac (744:744:744) (817:817:817)) + (PORT datad (774:774:774) (767:767:767)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (861:861:861)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (685:685:685) (758:758:758)) + (PORT datad (220:220:220) (289:289:289)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (860:860:860)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (688:688:688) (758:758:758)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) @@ -52115,7 +55176,7 @@ (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT ena (961:961:961) (968:968:968)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52127,14 +55188,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (656:656:656)) - (PORT datab (622:622:622) (686:686:686)) - (PORT datad (360:360:360) (411:411:411)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (295:295:295) (407:407:407)) + (PORT datab (304:304:304) (405:405:405)) + (PORT datac (295:295:295) (392:392:392)) + (PORT datad (263:263:263) (346:346:346)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (471:471:471)) + (PORT datab (751:751:751) (813:813:813)) + (PORT datad (782:782:782) (790:790:790)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52144,11 +55221,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1556:1556:1556)) - (PORT sload (1218:1218:1218) (1319:1319:1319)) - (PORT ena (1180:1180:1180) (1175:1175:1175)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT sload (1423:1423:1423) (1516:1516:1516)) + (PORT ena (1250:1250:1250) (1250:1250:1250)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52162,14 +55239,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (637:637:637) (656:656:656)) - (PORT datac (454:454:454) (537:537:537)) - (PORT datad (386:386:386) (445:445:445)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (417:417:417) (477:477:477)) + (PORT datac (744:744:744) (821:821:821)) + (PORT datad (970:970:970) (970:970:970)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52182,8 +55259,8 @@ (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sclr (1298:1298:1298) (1370:1370:1370)) - (PORT ena (961:961:961) (968:968:968)) + (PORT sclr (1184:1184:1184) (1287:1287:1287)) + (PORT ena (1221:1221:1221) (1223:1223:1223)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52196,11 +55273,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~7) (DELAY (ABSOLUTE - (PORT datac (461:461:461) (545:545:545)) - (PORT datad (221:221:221) (290:290:290)) + (PORT datac (745:745:745) (818:818:818)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52214,8 +55291,8 @@ (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (PORT clrn (1564:1564:1564) (1557:1557:1557)) - (PORT sclr (1298:1298:1298) (1370:1370:1370)) - (PORT ena (949:949:949) (938:938:938)) + (PORT sclr (1184:1184:1184) (1287:1287:1287)) + (PORT ena (1162:1162:1162) (1136:1136:1136)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52231,10 +55308,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (674:674:674) (733:733:733)) - (PORT datab (883:883:883) (952:952:952)) - (PORT datac (406:406:406) (468:468:468)) - (PORT datad (869:869:869) (932:932:932)) + (PORT dataa (693:693:693) (748:748:748)) + (PORT datab (313:313:313) (408:408:408)) + (PORT datac (668:668:668) (727:727:727)) + (PORT datad (728:728:728) (790:790:790)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -52247,10 +55324,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (381:381:381)) - (PORT datab (755:755:755) (824:824:824)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (507:507:507) (501:501:501)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (315:315:315) (415:415:415)) + (PORT datac (602:602:602) (622:622:622)) + (PORT datad (503:503:503) (496:496:496)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -52263,13 +55340,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (758:758:758) (822:822:822)) - (PORT datac (668:668:668) (731:731:731)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (299:299:299) (404:404:404)) + (PORT datab (313:313:313) (414:414:414)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52279,13 +55356,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (758:758:758) (822:822:822)) - (PORT datac (668:668:668) (732:732:732)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (298:298:298) (404:404:404)) + (PORT datab (314:314:314) (415:415:415)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52295,12 +55372,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (894:894:894)) - (PORT datab (231:231:231) (274:274:274)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (632:632:632) (664:664:664)) + (PORT datab (752:752:752) (836:836:836)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52313,8 +55390,8 @@ (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) (PORT d (691:691:691) (730:730:730)) - (PORT aload (1698:1698:1698) (1763:1763:1763)) - (PORT ena (942:942:942) (938:938:938)) + (PORT aload (1710:1710:1710) (1775:1775:1775)) + (PORT ena (1322:1322:1322) (1330:1330:1330)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52346,12 +55423,232 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux38\~0) + (INSTANCE sdram_\|Mux4\~3) (DELAY (ABSOLUTE - (PORT dataa (1565:1565:1565) (1641:1641:1641)) - (PORT datab (1300:1300:1300) (1343:1343:1343)) - (PORT datad (181:181:181) (212:212:212)) + (PORT dataa (731:731:731) (831:831:831)) + (PORT datac (670:670:670) (753:753:753)) + (PORT datad (683:683:683) (770:770:770)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1182:1182:1182)) + (PORT datac (1108:1108:1108) (1223:1223:1223)) + (PORT datad (1073:1073:1073) (1190:1190:1190)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1200:1200:1200)) + (PORT datac (1012:1012:1012) (1103:1103:1103)) + (PORT datad (1262:1262:1262) (1351:1351:1351)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1073:1073:1073)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1195:1195:1195) (1282:1282:1282)) + (PORT datad (1327:1327:1327) (1435:1435:1435)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (1085:1085:1085) (1193:1193:1193)) + (PORT datad (1034:1034:1034) (1129:1129:1129)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1480:1480:1480)) + (PORT datad (1211:1211:1211) (1299:1299:1299)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (1534:1534:1534) (1598:1598:1598)) + (PORT ena (821:821:821) (835:835:835)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (1034:1034:1034) (1068:1068:1068)) + (PORT ena (821:821:821) (835:835:835)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (764:764:764)) + (PORT datab (1222:1222:1222) (1288:1288:1288)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (3176:3176:3176) (3259:3259:3259)) + (PORT ena (821:821:821) (835:835:835)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1403:1403:1403)) + (PORT datab (1103:1103:1103) (1236:1236:1236)) + (PORT datac (1105:1105:1105) (1223:1223:1223)) + (PORT datad (1590:1590:1590) (1708:1708:1708)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1191:1191:1191)) + (PORT datac (909:909:909) (923:923:923)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1007:1007:1007)) + (PORT datab (1478:1478:1478) (1547:1547:1547)) + (PORT datad (321:321:321) (336:336:336)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1499:1499:1499)) + (PORT datab (951:951:951) (1038:1038:1038)) + (PORT datac (1543:1543:1543) (1657:1657:1657)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1058:1058:1058)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (321:321:321) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -52364,7 +55661,7 @@ (INSTANCE sdram_\|r\.rd_pending) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) + (PORT clk (1532:1532:1532) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -52373,12 +55670,162 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2867:2867:2867) (2954:2954:2954)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (446:446:446) (526:526:526)) + (PORT datad (682:682:682) (745:745:745)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1076:1076:1076)) + (PORT datab (1060:1060:1060) (1162:1162:1162)) + (PORT datac (1168:1168:1168) (1176:1176:1176)) + (PORT datad (1262:1262:1262) (1353:1353:1353)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (900:900:900)) + (PORT datab (222:222:222) (262:262:262)) + (PORT datac (1012:1012:1012) (1106:1106:1106)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT datab (958:958:958) (1039:1039:1039)) + (PORT datac (1057:1057:1057) (1164:1164:1164)) + (PORT datad (1329:1329:1329) (1435:1435:1435)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1145:1145:1145)) + (PORT datab (1004:1004:1004) (1086:1086:1086)) + (PORT datac (1057:1057:1057) (1164:1164:1164)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1073:1073:1073)) + (PORT datab (1061:1061:1061) (1161:1161:1161)) + (PORT datac (1166:1166:1166) (1172:1172:1172)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (942:942:942)) + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (853:853:853) (876:876:876)) + (PORT datad (830:830:830) (856:856:856)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1558:1558:1558)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datac (1633:1633:1633) (1743:1743:1743)) + (PORT datad (1538:1538:1538) (1626:1626:1626)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52387,16 +55834,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (INSTANCE sdram_\|r\.rf_counter\[8\]\~32) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (969:969:969) (1051:1051:1051)) - (PORT datac (661:661:661) (684:684:684)) - (PORT datad (1347:1347:1347) (1447:1447:1447)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (405:405:405) (430:430:430)) + (PORT datab (681:681:681) (747:747:747)) + (PORT datac (1633:1633:1633) (1743:1743:1743)) + (PORT datad (1538:1538:1538) (1627:1627:1627)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52422,9 +55869,9 @@ (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (251:251:251) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52452,7 +55899,7 @@ (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (335:335:335)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52482,7 +55929,7 @@ (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) + (PORT dataa (253:253:253) (345:345:345)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52507,14 +55954,30 @@ (HOLD sclr (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (225:225:225) (306:306:306)) + (PORT datad (226:226:226) (300:300:300)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (336:336:336)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (253:253:253) (346:346:346)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52542,9 +56005,9 @@ (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (337:337:337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52572,9 +56035,9 @@ (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (251:251:251) (337:337:337)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52627,22 +56090,6 @@ (HOLD sclr (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) @@ -52673,29 +56120,13 @@ (HOLD sclr (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (347:347:347)) - (PORT datab (254:254:254) (340:340:340)) - (PORT datac (226:226:226) (306:306:306)) - (PORT datad (228:228:228) (300:300:300)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (254:254:254) (344:344:344)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -52718,29 +56149,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal0\~2) + (INSTANCE sdram_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (374:374:374)) - (PORT datab (252:252:252) (336:336:336)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (224:224:224) (303:303:303)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~8) + (INSTANCE sdram_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT datab (1384:1384:1384) (1487:1487:1487)) - (PORT datac (941:941:941) (1018:1018:1018)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (225:225:225) (307:307:307)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52749,11 +56184,11 @@ (INSTANCE sdram_\|Mux37\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (259:259:259)) - (PORT datab (688:688:688) (717:717:717)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (680:680:680) (746:746:746)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52775,32 +56210,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~0) + (INSTANCE sdram_\|Mux4\~1) (DELAY (ABSOLUTE - (PORT dataa (774:774:774) (867:867:867)) - (PORT datab (765:765:765) (851:851:851)) - (PORT datac (642:642:642) (726:726:726)) - (PORT datad (862:862:862) (889:889:889)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (919:919:919) (1022:1022:1022)) + (PORT datab (998:998:998) (1094:1094:1094)) + (PORT datac (875:875:875) (937:937:937)) + (PORT datad (994:994:994) (1084:1084:1084)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~1) + (INSTANCE sdram_\|Mux4\~4) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (928:928:928)) - (PORT datab (1028:1028:1028) (1104:1104:1104)) - (PORT datac (1269:1269:1269) (1392:1392:1392)) - (PORT datad (571:571:571) (585:585:585)) + (PORT dataa (1278:1278:1278) (1401:1401:1401)) + (PORT datab (1139:1139:1139) (1253:1253:1253)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (815:815:815) (830:830:830)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52810,12 +56245,12 @@ (INSTANCE sdram_\|Mux4\~2) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (928:928:928)) - (PORT datab (1028:1028:1028) (1103:1103:1103)) - (PORT datac (1269:1269:1269) (1391:1391:1391)) - (PORT datad (571:571:571) (585:585:585)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (294:294:294) (384:384:384)) + (PORT datab (283:283:283) (371:371:371)) + (PORT datac (1791:1791:1791) (1881:1881:1881)) + (PORT datad (262:262:262) (345:345:345)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52823,14 +56258,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux4\~3) + (INSTANCE sdram_\|Mux4\~5) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (305:305:305) (398:398:398)) - (PORT datad (604:604:604) (636:636:636)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (647:647:647) (683:683:683)) + (PORT datab (908:908:908) (966:966:966)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52841,7 +56276,7 @@ (INSTANCE sdram_\|r\.state\[8\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -52852,13 +56287,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (INSTANCE sdram_\|process_0\~4) (DELAY (ABSOLUTE - (PORT dataa (1303:1303:1303) (1433:1433:1433)) - (PORT datab (1067:1067:1067) (1184:1184:1184)) - (PORT datac (1412:1412:1412) (1458:1458:1458)) - (PORT datad (995:995:995) (1084:1084:1084)) + (PORT datac (233:233:233) (309:309:309)) + (PORT datad (244:244:244) (314:314:314)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1087:1087:1087)) + (PORT datab (1106:1106:1106) (1205:1205:1205)) + (PORT datac (970:970:970) (1046:1046:1046)) + (PORT datad (1369:1369:1369) (1431:1431:1431)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52868,113 +56315,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~2) + (INSTANCE sdram_\|r\.act_row\[2\]\~1) (DELAY (ABSOLUTE - (PORT datac (264:264:264) (345:345:345)) - (PORT datad (285:285:285) (364:364:364)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (364:364:364) (399:399:399)) - (PORT datac (1029:1029:1029) (1132:1132:1132)) - (PORT datad (996:996:996) (1087:1087:1087)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1326:1326:1326) (1408:1408:1408)) + (PORT datab (1550:1550:1550) (1647:1647:1647)) + (PORT datac (1152:1152:1152) (1221:1221:1221)) + (PORT datad (610:610:610) (651:651:651)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (966:966:966) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (1576:1576:1576) (1606:1606:1606)) - (PORT ena (966:966:966) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1215:1215:1215) (1258:1258:1258)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.act_row\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (966:966:966) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1305:1305:1305)) - (PORT datab (1250:1250:1250) (1293:1293:1293)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.act_row\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (1323:1323:1323) (1390:1390:1390)) - (PORT ena (966:966:966) (964:964:964)) + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (2174:2174:2174) (2294:2294:2294)) + (PORT ena (821:821:821) (835:835:835)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -52988,9 +56350,9 @@ (INSTANCE sdram_\|r\.act_row\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1547:1547:1547)) - (PORT asdata (3043:3043:3043) (3212:3212:3212)) - (PORT ena (966:966:966) (964:964:964)) + (PORT clk (1531:1531:1531) (1548:1548:1548)) + (PORT asdata (1310:1310:1310) (1369:1369:1369)) + (PORT ena (821:821:821) (835:835:835)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53004,9 +56366,9 @@ (INSTANCE sdram_\|Equal7\~0) (DELAY (ABSOLUTE - (PORT dataa (2732:2732:2732) (2911:2911:2911)) - (PORT datab (1007:1007:1007) (1081:1081:1081)) - (PORT datad (216:216:216) (284:284:284)) + (PORT dataa (1192:1192:1192) (1253:1253:1253)) + (PORT datab (1857:1857:1857) (1985:1985:1985)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53019,114 +56381,11 @@ (INSTANCE sdram_\|Equal7\~2) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (468:468:468)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1442:1442:1442) (1496:1496:1496)) - (PORT datab (1034:1034:1034) (1124:1124:1124)) - (PORT datac (1028:1028:1028) (1131:1131:1131)) - (PORT datad (1030:1030:1030) (1145:1145:1145)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1281:1281:1281) (1388:1388:1388)) - (PORT datac (582:582:582) (600:600:600)) - (PORT datad (340:340:340) (361:361:361)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux39\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (253:253:253)) - (PORT datab (661:661:661) (681:681:681)) - (PORT datad (1354:1354:1354) (1381:1381:1381)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.wr_pending) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~8) - (DELAY - (ABSOLUTE - (PORT datac (1172:1172:1172) (1258:1258:1258)) - (PORT datad (1054:1054:1054) (1165:1165:1165)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~9) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (522:522:522)) - (PORT datab (614:614:614) (638:638:638)) - (PORT datac (668:668:668) (744:744:744)) - (PORT datad (286:286:286) (365:365:365)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux6\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1283:1283:1283) (1389:1389:1389)) - (PORT datab (311:311:311) (401:401:401)) - (PORT datac (195:195:195) (229:229:229)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (2866:2866:2866) (2957:2957:2957)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (225:225:225) (297:297:297)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53138,11 +56397,55 @@ (INSTANCE sdram_\|Mux6\~4) (DELAY (ABSOLUTE - (PORT datab (692:692:692) (771:771:771)) - (PORT datac (580:580:580) (597:597:597)) - (PORT datad (1249:1249:1249) (1337:1337:1337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (952:952:952) (1004:1004:1004)) + (PORT datab (785:785:785) (882:882:882)) + (PORT datad (1092:1092:1092) (1198:1198:1198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1045:1045:1045)) + (PORT datab (783:783:783) (878:878:878)) + (PORT datac (910:910:910) (981:981:981)) + (PORT datad (919:919:919) (953:953:953)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT datac (1128:1128:1128) (1241:1241:1241)) + (PORT datad (1196:1196:1196) (1268:1268:1268)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1133:1133:1133) (1245:1245:1245)) + (PORT datac (906:906:906) (1006:1006:1006)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53152,11 +56455,11 @@ (INSTANCE sdram_\|Mux6\~2) (DELAY (ABSOLUTE - (PORT dataa (1279:1279:1279) (1385:1385:1385)) - (PORT datac (1172:1172:1172) (1258:1258:1258)) - (PORT datad (1055:1055:1055) (1166:1166:1166)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1224:1224:1224) (1309:1309:1309)) + (PORT datac (1125:1125:1125) (1235:1235:1235)) + (PORT datad (1099:1099:1099) (1205:1205:1205)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53166,10 +56469,10 @@ (INSTANCE sdram_\|Mux6\~5) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (969:969:969) (1043:1043:1043)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (962:962:962) (1084:1084:1084)) + (PORT datad (175:175:175) (202:202:202)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -53179,13 +56482,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~3) + (INSTANCE sdram_\|process_0\~2) (DELAY (ABSOLUTE - (PORT dataa (900:900:900) (988:988:988)) - (PORT datac (793:793:793) (832:832:832)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (784:784:784) (878:878:878)) + (PORT datad (919:919:919) (952:952:952)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53194,10 +56497,10 @@ (INSTANCE sdram_\|Mux6\~0) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (388:388:388)) - (PORT datab (724:724:724) (811:811:811)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (738:738:738) (805:805:805)) + (PORT dataa (944:944:944) (1046:1046:1046)) + (PORT datab (1159:1159:1159) (1273:1273:1273)) + (PORT datac (196:196:196) (240:240:240)) + (PORT datad (1195:1195:1195) (1269:1269:1269)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -53210,12 +56513,12 @@ (INSTANCE sdram_\|Mux6\~1) (DELAY (ABSOLUTE - (PORT dataa (283:283:283) (378:378:378)) - (PORT datab (299:299:299) (395:395:395)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (739:739:739) (807:807:807)) + (PORT dataa (740:740:740) (835:835:835)) + (PORT datab (1533:1533:1533) (1632:1632:1632)) + (PORT datac (619:619:619) (663:663:663)) + (PORT datad (683:683:683) (774:774:774)) (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53226,10 +56529,10 @@ (INSTANCE sdram_\|Mux6\~6) (DELAY (ABSOLUTE - (PORT datab (304:304:304) (399:399:399)) - (PORT datac (605:605:605) (644:644:644)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (291:291:291) (389:389:389)) + (PORT datac (929:929:929) (943:943:943)) + (PORT datad (593:593:593) (622:622:622)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53240,7 +56543,7 @@ (INSTANCE sdram_\|r\.state\[6\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53251,160 +56554,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~6) + (INSTANCE sdram_\|Mux5\~7) (DELAY (ABSOLUTE - (PORT dataa (1305:1305:1305) (1435:1435:1435)) - (PORT datac (1028:1028:1028) (1132:1132:1132)) - (PORT datad (990:990:990) (1085:1085:1085)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~2) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (628:628:628)) - (PORT datab (1461:1461:1461) (1510:1510:1510)) - (PORT datac (668:668:668) (746:746:746)) - (PORT datad (1051:1051:1051) (1164:1164:1164)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~3) - (DELAY - (ABSOLUTE - (PORT datab (828:828:828) (934:934:934)) - (PORT datac (781:781:781) (892:892:892)) - (PORT datad (869:869:869) (909:909:909)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~3) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1007:1007:1007)) - (PORT datab (297:297:297) (391:391:391)) - (PORT datad (739:739:739) (802:802:802)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~4) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (297:297:297) (388:388:388)) - (PORT datac (870:870:870) (951:951:951)) - (PORT datad (275:275:275) (355:355:355)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~5) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (963:963:963)) - (PORT datab (300:300:300) (396:396:396)) - (PORT datac (690:690:690) (777:777:777)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~0) - (DELAY - (ABSOLUTE - (PORT datab (992:992:992) (1065:1065:1065)) - (PORT datac (1256:1256:1256) (1350:1350:1350)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~7) - (DELAY - (ABSOLUTE - (PORT datac (1261:1261:1261) (1385:1385:1385)) - (PORT datad (986:986:986) (1059:1059:1059)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~10) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (958:958:958)) - (PORT datab (995:995:995) (1070:1070:1070)) - (PORT datac (1256:1256:1256) (1357:1357:1357)) - (PORT datad (685:685:685) (768:768:768)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~1) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (450:450:450)) - (PORT datab (382:382:382) (407:407:407)) - (PORT datac (1029:1029:1029) (1106:1106:1106)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~6) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (830:830:830)) - (PORT datab (344:344:344) (369:369:369)) - (PORT datac (259:259:259) (349:349:349)) - (PORT datad (838:838:838) (843:843:843)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (996:996:996) (1079:1079:1079)) + (PORT datab (957:957:957) (1040:1040:1040)) + (PORT datac (1234:1234:1234) (1333:1333:1333)) + (PORT datad (1261:1261:1261) (1354:1354:1354)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53412,28 +56569,30 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.state\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1089:1089:1089) (1196:1196:1196)) + (PORT datab (1065:1065:1065) (1151:1151:1151)) + (PORT datac (953:953:953) (1030:1030:1030)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux5\~2) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (401:401:401)) - (PORT datab (1287:1287:1287) (1386:1386:1386)) - (PORT datac (961:961:961) (1031:1031:1031)) - (PORT datad (347:347:347) (368:368:368)) + (PORT dataa (1304:1304:1304) (1399:1399:1399)) + (PORT datab (1096:1096:1096) (1202:1202:1202)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (359:359:359) (379:379:379)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -53446,13 +56605,13 @@ (INSTANCE sdram_\|Mux5\~10) (DELAY (ABSOLUTE - (PORT dataa (777:777:777) (870:870:870)) - (PORT datab (765:765:765) (853:853:853)) - (PORT datac (766:766:766) (877:877:877)) - (PORT datad (675:675:675) (776:776:776)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1294:1294:1294) (1397:1397:1397)) + (PORT datab (1092:1092:1092) (1200:1200:1200)) + (PORT datac (966:966:966) (1059:1059:1059)) + (PORT datad (998:998:998) (1081:1081:1081)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53462,13 +56621,13 @@ (INSTANCE sdram_\|Mux5\~3) (DELAY (ABSOLUTE - (PORT dataa (801:801:801) (923:923:923)) - (PORT datab (1024:1024:1024) (1102:1102:1102)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1232:1232:1232) (1336:1336:1336)) + (PORT datab (229:229:229) (269:269:269)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1058:1058:1058) (1167:1167:1167)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53478,45 +56637,13 @@ (INSTANCE sdram_\|Mux5\~4) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (389:389:389)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1262:1262:1262) (1383:1383:1383)) - (PORT datad (711:711:711) (805:805:805)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~7) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (388:388:388)) - (PORT datab (775:775:775) (845:845:845)) - (PORT datac (870:870:870) (953:953:953)) - (PORT datad (889:889:889) (964:964:964)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux5\~8) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (297:297:297) (392:392:392)) - (PORT datac (689:689:689) (775:775:775)) - (PORT datad (275:275:275) (357:357:357)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1336:1336:1336) (1448:1448:1448)) + (PORT datab (1074:1074:1074) (1178:1178:1178)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53526,12 +56653,12 @@ (INSTANCE sdram_\|Mux5\~5) (DELAY (ABSOLUTE - (PORT dataa (932:932:932) (1011:1011:1011)) - (PORT datab (726:726:726) (812:812:812)) - (PORT datac (796:796:796) (836:836:836)) - (PORT datad (274:274:274) (354:354:354)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (937:937:937) (1019:1019:1019)) + (PORT datab (693:693:693) (785:785:785)) + (PORT datac (997:997:997) (1113:1113:1113)) + (PORT datad (923:923:923) (959:959:959)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53542,13 +56669,13 @@ (INSTANCE sdram_\|Mux5\~6) (DELAY (ABSOLUTE - (PORT dataa (431:431:431) (511:511:511)) - (PORT datab (229:229:229) (271:271:271)) - (PORT datac (631:631:631) (672:672:672)) - (PORT datad (914:914:914) (945:945:945)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datac (194:194:194) (236:236:236)) + (PORT datad (1098:1098:1098) (1204:1204:1204)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53558,13 +56685,13 @@ (INSTANCE sdram_\|Mux5\~9) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (379:379:379)) - (PORT datab (669:669:669) (707:707:707)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1189:1189:1189) (1188:1188:1188)) + (PORT datab (281:281:281) (370:370:370)) + (PORT datac (853:853:853) (886:886:886)) + (PORT datad (857:857:857) (902:902:902)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53574,7 +56701,7 @@ (INSTANCE sdram_\|r\.state\[7\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53588,64 +56715,98 @@ (INSTANCE sdram_\|n\~2) (DELAY (ABSOLUTE - (PORT datab (1023:1023:1023) (1112:1112:1112)) - (PORT datac (948:948:948) (1070:1070:1070)) - (PORT datad (994:994:994) (1080:1080:1080)) + (PORT datab (999:999:999) (1093:1093:1093)) + (PORT datac (887:887:887) (982:982:982)) + (PORT datad (994:994:994) (1083:1083:1083)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~6) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (675:675:675)) + (PORT datab (889:889:889) (983:983:983)) + (PORT datac (928:928:928) (1008:1008:1008)) + (PORT datad (1516:1516:1516) (1584:1584:1584)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (961:961:961) (1037:1037:1037)) + (PORT datac (929:929:929) (1006:1006:1006)) + (PORT datad (1515:1515:1515) (1583:1583:1583)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1046:1046:1046)) + (PORT datab (809:809:809) (911:911:911)) + (PORT datac (862:862:862) (953:953:953)) + (PORT datad (742:742:742) (849:849:849)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (894:894:894)) + (PORT datab (214:214:214) (260:260:260)) + (PORT datac (928:928:928) (1002:1002:1002)) + (PORT datad (612:612:612) (632:632:632)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux8\~3) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (396:396:396)) - (PORT datab (1264:1264:1264) (1347:1347:1347)) - (PORT datac (1576:1576:1576) (1655:1655:1655)) - (PORT datad (1570:1570:1570) (1693:1693:1693)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (773:773:773) (894:894:894)) + (PORT datab (214:214:214) (260:260:260)) + (PORT datac (849:849:849) (870:870:870)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1517:1517:1517)) - (PORT datab (1478:1478:1478) (1602:1602:1602)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1253:1253:1253) (1313:1313:1313)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~10) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1172:1172:1172) (1258:1258:1258)) - (PORT datad (1055:1055:1055) (1165:1165:1165)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (INSTANCE sdram_\|r\.init_counter\[0\]\~44) (DELAY (ABSOLUTE (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53657,7 +56818,7 @@ (INSTANCE sdram_\|r\.init_counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1561:1561:1561)) + (PORT clk (1530:1530:1530) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53668,20 +56829,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~1) + (INSTANCE sdram_\|r\.init_counter\[1\]\~15) (DELAY (ABSOLUTE - (PORT datab (734:734:734) (825:825:825)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (409:409:409) (485:485:485)) + (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~2) + (INSTANCE sdram_\|r\.init_counter\[1\]\~16) (DELAY (ABSOLUTE - (PORT datab (282:282:282) (364:364:364)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53695,7 +56856,7 @@ (INSTANCE sdram_\|r\.init_counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53706,7 +56867,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~4) + (INSTANCE sdram_\|r\.init_counter\[2\]\~18) (DELAY (ABSOLUTE (PORT dataa (264:264:264) (351:351:351)) @@ -53723,7 +56884,7 @@ (INSTANCE sdram_\|r\.init_counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53734,34 +56895,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~6) + (INSTANCE sdram_\|r\.init_counter\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (437:437:437) (497:497:497)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (263:263:263) (345:345:345)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.init_counter\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT datac (345:345:345) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.init_counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53772,7 +56923,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~8) + (INSTANCE sdram_\|r\.init_counter\[4\]\~22) (DELAY (ABSOLUTE (PORT dataa (265:265:265) (353:353:353)) @@ -53789,7 +56940,7 @@ (INSTANCE sdram_\|r\.init_counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53800,7 +56951,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~10) + (INSTANCE sdram_\|r\.init_counter\[5\]\~24) (DELAY (ABSOLUTE (PORT dataa (265:265:265) (353:353:353)) @@ -53817,7 +56968,7 @@ (INSTANCE sdram_\|r\.init_counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53828,7 +56979,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~12) + (INSTANCE sdram_\|r\.init_counter\[6\]\~26) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -53845,7 +56996,7 @@ (INSTANCE sdram_\|r\.init_counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53856,10 +57007,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~14) + (INSTANCE sdram_\|r\.init_counter\[7\]\~28) (DELAY (ABSOLUTE - (PORT datab (284:284:284) (367:367:367)) + (PORT datab (264:264:264) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53873,7 +57024,7 @@ (INSTANCE sdram_\|r\.init_counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53884,7 +57035,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~16) + (INSTANCE sdram_\|r\.init_counter\[8\]\~30) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -53901,7 +57052,7 @@ (INSTANCE sdram_\|r\.init_counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53912,10 +57063,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~18) + (INSTANCE sdram_\|r\.init_counter\[9\]\~32) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) + (PORT datab (251:251:251) (336:336:336)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53929,7 +57080,7 @@ (INSTANCE sdram_\|r\.init_counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53940,10 +57091,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~20) + (INSTANCE sdram_\|r\.init_counter\[10\]\~34) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (352:352:352)) + (PORT dataa (252:252:252) (342:342:342)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53957,7 +57108,7 @@ (INSTANCE sdram_\|r\.init_counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -53968,37 +57119,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (496:496:496)) - (PORT datab (447:447:447) (515:515:515)) - (PORT datac (387:387:387) (456:456:456)) - (PORT datad (407:407:407) (472:472:472)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT datab (449:449:449) (514:514:514)) - (PORT datac (416:416:416) (481:481:481)) - (PORT datad (244:244:244) (315:315:315)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~22) + (INSTANCE sdram_\|r\.init_counter\[11\]\~36) (DELAY (ABSOLUTE (PORT datab (250:250:250) (335:335:335)) @@ -54015,7 +57136,7 @@ (INSTANCE sdram_\|r\.init_counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54026,10 +57147,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~24) + (INSTANCE sdram_\|r\.init_counter\[12\]\~38) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (341:341:341)) + (PORT dataa (265:265:265) (351:351:351)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54043,7 +57164,7 @@ (INSTANCE sdram_\|r\.init_counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54054,10 +57175,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~26) + (INSTANCE sdram_\|r\.init_counter\[13\]\~40) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) + (PORT datab (263:263:263) (345:345:345)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54071,7 +57192,7 @@ (INSTANCE sdram_\|r\.init_counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54082,10 +57203,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Add1\~28) + (INSTANCE sdram_\|r\.init_counter\[14\]\~42) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) + (PORT dataa (266:266:266) (353:353:353)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -54096,7 +57217,7 @@ (INSTANCE sdram_\|r\.init_counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT clk (1529:1529:1529) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54105,15 +57226,45 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (444:444:444) (503:503:503)) + (PORT datac (410:410:410) (470:470:470)) + (PORT datad (381:381:381) (435:435:435)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|process_0\~5) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) + (PORT dataa (405:405:405) (480:480:480)) (PORT datab (252:252:252) (337:337:337)) - (PORT datac (224:224:224) (306:306:306)) - (PORT datad (227:227:227) (299:299:299)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (226:226:226) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (483:483:483)) + (PORT datab (591:591:591) (654:654:654)) + (PORT datac (383:383:383) (445:445:445)) + (PORT datad (391:391:391) (449:449:449)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -54126,59 +57277,13 @@ (INSTANCE sdram_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) + (PORT dataa (415:415:415) (486:486:486)) (PORT datab (197:197:197) (236:236:236)) - (PORT datac (353:353:353) (381:381:381)) - (PORT datad (388:388:388) (451:451:451)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~11) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (865:865:865)) - (PORT datab (304:304:304) (399:399:399)) - (PORT datad (752:752:752) (835:835:835)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~12) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (608:608:608)) - (PORT datab (662:662:662) (714:714:714)) - (PORT datac (1575:1575:1575) (1693:1693:1693)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1632:1632:1632)) - (PORT datab (1378:1378:1378) (1503:1503:1503)) - (PORT datac (566:566:566) (574:574:574)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (338:338:338) (357:357:357)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54188,11 +57293,27 @@ (INSTANCE sdram_\|Mux8\~0) (DELAY (ABSOLUTE - (PORT dataa (1278:1278:1278) (1384:1384:1384)) - (PORT datab (1463:1463:1463) (1512:1512:1512)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (862:862:862) (878:878:878)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT dataa (286:286:286) (382:382:382)) + (PORT datab (428:428:428) (498:498:498)) + (PORT datac (404:404:404) (469:469:469)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (863:863:863) (954:954:954)) + (PORT datad (582:582:582) (629:629:629)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54201,28 +57322,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~1) + (INSTANCE sdram_\|Mux8\~5) (DELAY (ABSOLUTE - (PORT dataa (1217:1217:1217) (1339:1339:1339)) - (PORT datab (975:975:975) (1056:1056:1056)) - (PORT datac (968:968:968) (1042:1042:1042)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux8\~2) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (811:811:811)) - (PORT datac (1118:1118:1118) (1180:1180:1180)) - (PORT datad (873:873:873) (903:903:903)) + (PORT dataa (288:288:288) (386:386:386)) + (PORT datac (607:607:607) (639:639:639)) + (PORT datad (572:572:572) (598:598:598)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54234,7 +57339,7 @@ (INSTANCE sdram_\|r\.state\[4\]) (DELAY (ABSOLUTE - (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54248,12 +57353,10 @@ (INSTANCE sdram_\|Mux72\~0) (DELAY (ABSOLUTE - (PORT datab (3068:3068:3068) (3183:3183:3183)) - (PORT datac (902:902:902) (1002:1002:1002)) - (PORT datad (278:278:278) (362:362:362)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (1710:1710:1710) (1782:1782:1782)) + (PORT datac (979:979:979) (1078:1078:1078)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54262,12 +57365,12 @@ (INSTANCE sdram_\|Mux72\~1) (DELAY (ABSOLUTE - (PORT dataa (1025:1025:1025) (1085:1085:1085)) - (PORT datab (3069:3069:3069) (3185:3185:3185)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (360:360:360) (379:379:379)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (755:755:755) (796:796:796)) + (PORT datab (326:326:326) (424:424:424)) + (PORT datac (314:314:314) (345:345:345)) + (PORT datad (627:627:627) (676:676:676)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54278,8 +57381,8 @@ (INSTANCE sdram_\|Mux84\~0) (DELAY (ABSOLUTE - (PORT datac (252:252:252) (338:338:338)) - (PORT datad (739:739:739) (806:806:806)) + (PORT datac (291:291:291) (382:382:382)) + (PORT datad (251:251:251) (327:327:327)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54290,13 +57393,13 @@ (INSTANCE sdram_\|Mux84\~1) (DELAY (ABSOLUTE - (PORT dataa (429:429:429) (511:511:511)) - (PORT datab (303:303:303) (398:398:398)) - (PORT datac (261:261:261) (351:351:351)) - (PORT datad (171:171:171) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (290:290:290) (389:389:389)) + (PORT datab (271:271:271) (354:354:354)) + (PORT datac (262:262:262) (343:343:343)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54306,11 +57409,9 @@ (INSTANCE sdram_\|Mux3\~0) (DELAY (ABSOLUTE - (PORT datab (3069:3069:3069) (3191:3191:3191)) - (PORT datac (1141:1141:1141) (1223:1223:1223)) - (PORT datad (280:280:280) (365:365:365)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1083:1083:1083) (1208:1208:1208)) + (PORT datad (1685:1685:1685) (1743:1743:1743)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54320,13 +57421,13 @@ (INSTANCE sdram_\|Mux3\~1) (DELAY (ABSOLUTE - (PORT dataa (1024:1024:1024) (1092:1092:1092)) - (PORT datab (3070:3070:3070) (3193:3193:3193)) - (PORT datac (312:312:312) (331:331:331)) - (PORT datad (343:343:343) (365:365:365)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (323:323:323) (419:419:419)) + (PORT datac (720:720:720) (756:756:756)) + (PORT datad (342:342:342) (361:361:361)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54336,12 +57437,10 @@ (INSTANCE sdram_\|Mux2\~0) (DELAY (ABSOLUTE - (PORT datab (3070:3070:3070) (3185:3185:3185)) - (PORT datac (1121:1121:1121) (1216:1216:1216)) - (PORT datad (283:283:283) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (1493:1493:1493) (1543:1543:1543)) + (PORT datac (855:855:855) (962:962:962)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54350,13 +57449,13 @@ (INSTANCE sdram_\|Mux2\~1) (DELAY (ABSOLUTE - (PORT dataa (1027:1027:1027) (1093:1093:1093)) - (PORT datab (3073:3073:3073) (3192:3192:3192)) - (PORT datac (347:347:347) (370:370:370)) - (PORT datad (628:628:628) (674:674:674)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (600:600:600) (634:634:634)) + (PORT datab (327:327:327) (424:424:424)) + (PORT datac (627:627:627) (673:673:673)) + (PORT datad (1431:1431:1431) (1448:1448:1448)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54366,11 +57465,9 @@ (INSTANCE sdram_\|Mux1\~0) (DELAY (ABSOLUTE - (PORT datab (3073:3073:3073) (3191:3191:3191)) - (PORT datac (1123:1123:1123) (1214:1214:1214)) - (PORT datad (280:280:280) (360:360:360)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (1775:1775:1775) (1836:1836:1836)) + (PORT datad (651:651:651) (718:718:718)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54380,13 +57477,13 @@ (INSTANCE sdram_\|Mux1\~1) (DELAY (ABSOLUTE - (PORT dataa (1024:1024:1024) (1093:1093:1093)) - (PORT datab (3064:3064:3064) (3191:3191:3191)) - (PORT datac (609:609:609) (617:617:617)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (768:768:768) (864:864:864)) + (PORT datab (1153:1153:1153) (1204:1204:1204)) + (PORT datac (1380:1380:1380) (1407:1407:1407)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54396,11 +57493,9 @@ (INSTANCE sdram_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT datab (3064:3064:3064) (3190:3190:3190)) - (PORT datac (972:972:972) (1042:1042:1042)) - (PORT datad (282:282:282) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (1775:1775:1775) (1836:1836:1836)) + (PORT datad (396:396:396) (465:465:465)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54410,13 +57505,13 @@ (INSTANCE sdram_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (1027:1027:1027) (1093:1093:1093)) - (PORT datab (3072:3072:3072) (3191:3191:3191)) - (PORT datac (312:312:312) (340:340:340)) - (PORT datad (608:608:608) (655:655:655)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1112:1112:1112) (1132:1132:1132)) + (PORT datab (322:322:322) (417:417:417)) + (PORT datac (718:718:718) (759:759:759)) + (PORT datad (643:643:643) (655:655:655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54426,26 +57521,10 @@ (INSTANCE sdram_\|Mux73\~0) (DELAY (ABSOLUTE - (PORT datab (3066:3066:3066) (3187:3187:3187)) - (PORT datac (1488:1488:1488) (1592:1592:1592)) - (PORT datad (279:279:279) (362:362:362)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux73\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1090:1090:1090)) - (PORT datab (3063:3063:3063) (3193:3193:3193)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (611:611:611) (659:659:659)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT datab (1088:1088:1088) (1101:1101:1101)) + (PORT datac (835:835:835) (875:875:875)) + (PORT datad (201:201:201) (228:228:228)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54456,11 +57535,9 @@ (INSTANCE sdram_\|Mux74\~0) (DELAY (ABSOLUTE - (PORT datab (3072:3072:3072) (3189:3189:3189)) - (PORT datac (922:922:922) (1010:1010:1010)) - (PORT datad (277:277:277) (361:361:361)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (890:890:890) (924:924:924)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54470,13 +57547,13 @@ (INSTANCE sdram_\|Mux74\~1) (DELAY (ABSOLUTE - (PORT dataa (1025:1025:1025) (1085:1085:1085)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (3027:3027:3027) (3147:3147:3147)) - (PORT datad (635:635:635) (683:683:683)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (756:756:756) (796:796:796)) + (PORT datab (867:867:867) (909:909:909)) + (PORT datac (294:294:294) (387:387:387)) + (PORT datad (592:592:592) (638:638:638)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54486,9 +57563,23 @@ (INSTANCE sdram_\|Mux75\~0) (DELAY (ABSOLUTE - (PORT datac (1505:1505:1505) (1638:1638:1638)) - (PORT datad (1359:1359:1359) (1405:1405:1405)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (744:744:744) (841:841:841)) + (PORT datab (845:845:845) (876:876:876)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE LED\~0) + (DELAY + (ABSOLUTE + (PORT datac (1303:1303:1303) (1368:1368:1368)) + (PORT datad (1496:1496:1496) (1562:1562:1562)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54507,9 +57598,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1921:1921:1921) (1947:1947:1947)) + (PORT clk (1896:1896:1896) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1556:1556:1556)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54524,7 +57615,7 @@ (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (976:976:976) (1002:1002:1002)) + (PORT d (953:953:953) (987:987:987)) (PORT clrn (1750:1750:1750) (1800:1800:1800)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -54535,13 +57626,29 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT datab (684:684:684) (751:751:751)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (1012:1012:1012) (1100:1100:1100)) + (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) ) @@ -54550,7 +57657,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (336:336:336)) + (PORT datab (251:251:251) (335:335:335)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54564,10 +57671,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (210:210:210) (240:240:240)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (238:238:238) (289:289:289)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54576,9 +57683,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1917:1917:1917)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1563:1563:1563) (1555:1555:1555)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54592,9 +57699,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (480:480:480)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (429:429:429) (498:498:498)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54606,8 +57713,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datac (315:315:315) (334:334:334)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (330:330:330) (344:344:344)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54616,9 +57723,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54632,9 +57739,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (435:435:435) (503:503:503)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (430:430:430) (497:497:497)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54646,7 +57753,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datad (557:557:557) (571:571:571)) + (PORT datad (328:328:328) (343:343:343)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54656,9 +57763,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1921:1921:1921) (1947:1947:1947)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1556:1556:1556)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54672,7 +57779,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54686,10 +57793,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (239:239:239) (292:292:292)) + (PORT datac (172:172:172) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54698,9 +57805,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1917:1917:1917)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1563:1563:1563) (1555:1555:1555)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54714,7 +57821,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (438:438:438) (505:505:505)) + (PORT dataa (399:399:399) (480:480:480)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54728,8 +57835,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (314:314:314) (330:330:330)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (317:317:317) (336:336:336)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -54738,9 +57845,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54754,13 +57861,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (480:480:480)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (395:395:395) (461:461:461)) - (PORT datad (394:394:394) (457:457:457)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (401:401:401) (482:482:482)) + (PORT datab (433:433:433) (499:499:499)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (388:388:388) (455:455:455)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54770,7 +57877,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT datab (426:426:426) (495:495:495)) + (PORT datab (429:429:429) (498:498:498)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54784,7 +57891,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (330:330:330) (348:348:348)) + (PORT datad (310:310:310) (329:329:329)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54794,9 +57901,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54810,9 +57917,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (477:477:477)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (397:397:397) (473:473:473)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54824,8 +57931,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datac (335:335:335) (357:357:357)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54834,9 +57941,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1918:1918:1918)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1564:1564:1564) (1555:1555:1555)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54850,7 +57957,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (253:253:253) (338:338:338)) + (PORT datab (252:252:252) (337:337:337)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54864,10 +57971,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datad (210:210:210) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (242:242:242) (296:296:296)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54876,9 +57983,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1917:1917:1917)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1563:1563:1563) (1555:1555:1555)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54892,7 +57999,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (383:383:383) (441:441:441)) + (PORT datad (398:398:398) (459:459:459)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -54903,8 +58010,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datac (343:343:343) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (333:333:333) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54913,9 +58020,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1893:1893:1893) (1916:1916:1916)) + (PORT clk (1898:1898:1898) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1562:1562:1562) (1554:1554:1554)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -54929,13 +58036,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (478:478:478)) - (PORT datab (422:422:422) (482:482:482)) - (PORT datac (222:222:222) (301:301:301)) - (PORT datad (393:393:393) (456:456:456)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (434:434:434) (502:502:502)) + (PORT datab (396:396:396) (469:469:469)) + (PORT datac (397:397:397) (462:462:462)) + (PORT datad (222:222:222) (294:294:294)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54945,41 +58052,24 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (248:248:248) (333:333:333)) - (PORT datac (317:317:317) (336:336:336)) - (PORT datad (650:650:650) (712:712:712)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (975:975:975) (1059:1059:1059)) + (PORT datad (223:223:223) (294:294:294)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT asdata (535:535:535) (565:565:565)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (962:962:962) (999:999:999)) - (PORT datad (231:231:231) (304:304:304)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datad (1181:1181:1181) (1271:1271:1271)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54990,7 +58080,7 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (1379:1379:1379) (1433:1433:1433)) + (PORT d (1567:1567:1567) (1679:1679:1679)) (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -55007,7 +58097,7 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (1386:1386:1386) (1428:1428:1428)) + (PORT d (1931:1931:1931) (2013:2013:2013)) (PORT clrn (1749:1749:1749) (1799:1799:1799)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -55018,37 +58108,6 @@ (HOLD d (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (458:458:458)) - (PORT datab (965:965:965) (1004:1004:1004)) - (PORT datad (217:217:217) (253:253:253)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) @@ -55062,22 +58121,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT datac (193:193:193) (226:226:226)) + (PORT datab (738:738:738) (824:824:824)) + (IOPATH datab cout (446:446:446) (318:318:318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1099:1099:1099)) + (PORT datab (1206:1206:1206) (1305:1305:1305)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (701:701:701) (782:782:782)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55088,15 +58177,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) + (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (913:913:913) (945:945:945)) - (PORT datab (277:277:277) (369:369:369)) - (PORT datac (204:204:204) (241:241:241)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (664:664:664) (753:753:753)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~17) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (719:719:719)) + (PORT datab (968:968:968) (1061:1061:1061)) + (PORT datac (215:215:215) (263:263:263)) + (PORT datad (214:214:214) (259:259:259)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (809:809:809)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~19) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (911:911:911)) + (PORT datab (978:978:978) (1072:1072:1072)) + (PORT datac (248:248:248) (331:331:331)) + (PORT datad (620:620:620) (660:660:660)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT datad (641:641:641) (724:724:724)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (635:635:635)) + (PORT datab (967:967:967) (1064:1064:1064)) + (PORT datac (211:211:211) (261:261:261)) + (PORT datad (212:212:212) (256:256:256)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (812:812:812)) + (PORT datab (659:659:659) (750:750:750)) + (PORT datac (221:221:221) (302:302:302)) + (PORT datad (637:637:637) (720:720:720)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (304:304:304)) + (PORT datab (967:967:967) (1060:1060:1060)) + (PORT datad (615:615:615) (654:654:654)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (364:364:364)) + (PORT datad (619:619:619) (656:656:656)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (299:299:299)) + (PORT datab (976:976:976) (1069:1069:1069)) + (PORT datac (209:209:209) (256:256:256)) + (PORT datad (234:234:234) (309:309:309)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -55105,12 +58406,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (570:570:570) (611:611:611)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1002:1002:1002) (1050:1050:1050)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55141,12 +58442,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (570:570:570) (612:612:612)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1003:1003:1003) (1051:1051:1051)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55160,10 +58461,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) + (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~10) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) + (PORT datab (264:264:264) (347:347:347)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55177,12 +58478,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (567:567:567) (608:608:608)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1003:1003:1003) (1052:1052:1052)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55196,10 +58497,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) + (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~12) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (348:348:348)) + (PORT datab (252:252:252) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55213,12 +58514,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (568:568:568) (608:608:608)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1003:1003:1003) (1053:1053:1053)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55232,10 +58533,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~14) (DELAY (ABSOLUTE - (PORT dataa (270:270:270) (366:366:366)) + (PORT dataa (262:262:262) (355:355:355)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -55246,12 +58547,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT clk (1517:1517:1517) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (568:568:568) (610:610:610)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (PORT sload (1495:1495:1495) (1558:1558:1558)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (1004:1004:1004) (1054:1054:1054)) + (PORT clrn (1562:1562:1562) (1557:1557:1557)) + (PORT sload (1558:1558:1558) (1680:1680:1680)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55268,10 +58569,10 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (409:409:409) (479:479:479)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (223:223:223) (301:301:301)) - (PORT datad (225:225:225) (296:296:296)) + (PORT dataa (404:404:404) (480:480:480)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (226:226:226) (298:298:298)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -55281,265 +58582,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) + (INSTANCE ula_\|i2s_intf_\|LessThan0\~1) (DELAY (ABSOLUTE - (PORT dataa (384:384:384) (461:461:461)) - (PORT datab (551:551:551) (565:565:565)) - (PORT datac (238:238:238) (326:326:326)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datac (232:232:232) (317:317:317)) + (PORT datad (182:182:182) (213:213:213)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~7) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (507:507:507)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~8) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~20) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (505:505:505)) - (PORT datab (966:966:966) (1004:1004:1004)) - (PORT datac (318:318:318) (335:335:335)) - (PORT datad (217:217:217) (252:252:252)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~10) - (DELAY - (ABSOLUTE - (PORT datab (573:573:573) (642:642:642)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~17) - (DELAY - (ABSOLUTE - (PORT dataa (427:427:427) (459:459:459)) - (PORT datab (962:962:962) (1006:1006:1006)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (331:331:331) (353:353:353)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~12) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~19) - (DELAY - (ABSOLUTE - (PORT dataa (419:419:419) (509:509:509)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (879:879:879) (891:891:891)) - (PORT datad (219:219:219) (255:255:255)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~14) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~16) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (457:457:457)) - (PORT datab (965:965:965) (1004:1004:1004)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (333:333:333) (353:353:353)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (339:339:339)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (223:223:223) (302:302:302)) - (PORT datad (549:549:549) (606:606:606)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT datab (246:246:246) (293:293:293)) - (PORT datad (391:391:391) (462:462:462)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datac (241:241:241) (330:330:330)) - (PORT datad (251:251:251) (332:332:332)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (569:569:569)) - (PORT datab (276:276:276) (367:367:367)) - (PORT datac (881:881:881) (906:906:906)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (241:241:241) (303:303:303)) + (PORT datab (244:244:244) (297:297:297)) + (PORT datad (939:939:939) (1019:1019:1019)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55550,7 +58613,7 @@ (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (1492:1492:1492) (1572:1572:1572)) + (PORT d (2073:2073:2073) (2219:2219:2219)) (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) @@ -55566,7 +58629,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (931:931:931) (990:990:990)) + (PORT datad (643:643:643) (695:695:695)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55576,12 +58639,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT datab (1869:1869:1869) (2024:2024:2024)) - (PORT datac (3075:3075:3075) (3301:3301:3301)) - (PORT datad (2569:2569:2569) (2679:2679:2679)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (1248:1248:1248) (1333:1333:1333)) + (PORT datab (1163:1163:1163) (1207:1207:1207)) + (PORT datac (1134:1134:1134) (1180:1180:1180)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -55590,13 +58653,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (2571:2571:2571) (2819:2819:2819)) - (PORT datab (1226:1226:1226) (1334:1334:1334)) - (PORT datac (2100:2100:2100) (2229:2229:2229)) - (PORT datad (1093:1093:1093) (1082:1082:1082)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1203:1203:1203) (1271:1271:1271)) + (PORT datab (1691:1691:1691) (1786:1786:1786)) + (PORT datac (1213:1213:1213) (1289:1289:1289)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55606,9 +58669,9 @@ (INSTANCE ula_\|pcm_outl\[13\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (997:997:997) (1007:1007:1007)) + (PORT ena (1653:1653:1653) (1635:1635:1635)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55619,15 +58682,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (551:551:551) (575:575:575)) - (PORT datab (279:279:279) (373:373:373)) - (PORT datac (242:242:242) (331:331:331)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (256:256:256) (349:349:349)) + (PORT datab (912:912:912) (982:982:982)) + (PORT datad (1180:1180:1180) (1268:1268:1268)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (349:349:349)) + (PORT datab (912:912:912) (982:982:982)) + (PORT datad (1181:1181:1181) (1270:1270:1270)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outr\~0) + (DELAY + (ABSOLUTE + (PORT datac (218:218:218) (295:295:295)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1442:1442:1442) (1438:1438:1438)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (253:253:253)) + (PORT datab (238:238:238) (290:290:290)) + (PORT datac (231:231:231) (315:315:315)) + (PORT datad (233:233:233) (308:308:308)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55644,14 +58797,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (985:985:985) (1054:1054:1054)) - (PORT datab (567:567:567) (582:582:582)) - (PORT datad (752:752:752) (742:742:742)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (904:904:904) (961:961:961)) + (PORT datab (517:517:517) (586:586:586)) + (PORT datad (768:768:768) (761:761:761)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55662,9 +58815,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1908:1908:1908) (1928:1928:1928)) + (PORT clk (1868:1868:1868) (1876:1876:1876)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55675,27 +58828,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (928:928:928) (981:981:981)) - (PORT datad (220:220:220) (290:290:290)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (217:217:217) (295:295:295)) + (PORT datad (482:482:482) (547:547:547)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]\~1) (DELAY (ABSOLUTE - (PORT dataa (911:911:911) (946:946:946)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datac (202:202:202) (239:239:239)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (238:238:238) (298:298:298)) + (PORT datab (977:977:977) (1071:1071:1071)) + (PORT datac (207:207:207) (254:254:254)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -55704,40 +58859,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT datac (945:945:945) (999:999:999)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55752,22 +58877,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (329:329:329)) - (PORT datac (941:941:941) (995:995:995)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (536:536:536) (605:605:605)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55782,22 +58907,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datac (925:925:925) (991:991:991)) - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (517:517:517) (592:592:592)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55812,22 +58937,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (248:248:248) (336:336:336)) - (PORT datac (946:946:946) (1001:1001:1001)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (534:534:534) (608:608:608)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55842,22 +58967,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT datac (939:939:939) (985:985:985)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (535:535:535) (604:604:604)) + (PORT datad (218:218:218) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55872,22 +58997,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datac (946:946:946) (1005:1005:1005)) - (PORT datad (219:219:219) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (513:513:513) (587:587:587)) + (PORT datad (220:220:220) (289:289:289)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55902,22 +59027,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datac (949:949:949) (1004:1004:1004)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (473:473:473) (539:539:539)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55932,22 +59057,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datac (948:948:948) (1006:1006:1006)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (516:516:516) (595:595:595)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55962,22 +59087,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datac (947:947:947) (1002:1002:1002)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (219:219:219) (296:296:296)) + (PORT datad (495:495:495) (559:559:559)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55992,22 +59117,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datac (950:950:950) (1004:1004:1004)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (531:531:531) (600:600:600)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56022,22 +59147,22 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datac (927:927:927) (980:980:980)) - (PORT datad (221:221:221) (291:291:291)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datac (217:217:217) (293:293:293)) + (PORT datad (491:491:491) (560:560:560)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56047,119 +59172,27 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (530:530:530)) - (PORT datab (964:964:964) (1007:1007:1007)) - (PORT datad (235:235:235) (310:310:310)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (530:530:530)) - (PORT datab (964:964:964) (1006:1006:1006)) - (PORT datad (234:234:234) (310:310:310)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outr\~0) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (334:334:334)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1539:1539:1539)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2947:2947:2947) (2964:2964:2964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (938:938:938) (987:987:987)) - (PORT datad (368:368:368) (428:428:428)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (484:484:484) (545:545:545)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56174,24 +59207,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1401:1401:1401) (1507:1507:1507)) - (PORT datac (929:929:929) (981:981:981)) + (PORT datab (535:535:535) (608:608:608)) + (PORT datac (1209:1209:1209) (1305:1305:1305)) (PORT datad (218:218:218) (287:287:287)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56201,42 +59234,64 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (595:595:595) (610:610:610)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (997:997:997) (1007:1007:1007)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (354:354:354)) - (PORT datac (926:926:926) (989:989:989)) - (PORT datad (1495:1495:1495) (1587:1587:1587)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1175:1175:1175) (1251:1251:1251)) + (PORT datac (657:657:657) (734:734:734)) + (PORT datad (1182:1182:1182) (1276:1276:1276)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1886:1886:1886) (1908:1908:1908)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (PORT ena (1205:1205:1205) (1192:1192:1192)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (558:558:558) (589:589:589)) + (PORT ena (2210:2210:2210) (2208:2208:2208)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (DELAY + (ABSOLUTE + (PORT datab (941:941:941) (1017:1017:1017)) + (PORT datac (656:656:656) (707:707:707)) + (PORT datad (903:903:903) (977:977:977)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -56246,10 +59301,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1545:1545:1545) (1561:1561:1561)) + (PORT clk (1884:1884:1884) (1908:1908:1908)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1569:1569:1569) (1561:1561:1561)) - (PORT ena (1385:1385:1385) (1360:1360:1360)) + (PORT clrn (1564:1564:1564) (1558:1558:1558)) + (PORT ena (1225:1225:1225) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56261,11 +59316,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) + (INSTANCE ula_\|i2s_intf_\|shiftreg\~2) (DELAY (ABSOLUTE - (PORT datab (619:619:619) (640:640:640)) - (PORT datad (664:664:664) (716:716:716)) + (PORT datab (528:528:528) (601:601:601)) + (PORT datad (916:916:916) (1010:1010:1010)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -56276,10 +59331,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1932:1932:1932)) + (PORT clk (1532:1532:1532) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1558:1558:1558)) - (PORT ena (1437:1437:1437) (1422:1422:1422)) + (PORT clrn (1566:1566:1566) (1557:1557:1557)) + (PORT ena (1703:1703:1703) (1718:1718:1718)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -56294,8 +59349,8 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (615:615:615) (638:638:638)) - (PORT datad (218:218:218) (287:287:287)) + (PORT datab (536:536:536) (605:605:605)) + (PORT datad (219:219:219) (288:288:288)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -56307,9 +59362,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1138:1138:1138) (1176:1176:1176)) + (PORT d (960:960:960) (1023:1023:1023)) (PORT clrn (1752:1752:1752) (1802:1802:1802)) - (PORT ena (867:867:867) (864:864:864)) + (PORT ena (1453:1453:1453) (1490:1490:1490)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -56323,116 +59378,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1169:1169:1169) (1173:1173:1173)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1802:1802:1802) (1799:1799:1799)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (371:371:371)) - (PORT datab (261:261:261) (342:342:342)) - (PORT datac (234:234:234) (309:309:309)) - (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (371:371:371)) - (PORT datab (282:282:282) (365:365:365)) - (PORT datac (395:395:395) (452:452:452)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (511:511:511)) - (PORT datab (270:270:270) (355:355:355)) - (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (506:506:506)) - (PORT datab (678:678:678) (734:734:734)) - (PORT datac (607:607:607) (669:669:669)) - (PORT datad (515:515:515) (528:528:528)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (371:371:371)) - (PORT datab (288:288:288) (373:373:373)) - (PORT datac (344:344:344) (366:366:366)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (897:897:897) (930:930:930)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (1266:1266:1266) (1303:1303:1303)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -56441,25 +59391,25 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (545:545:545)) - (PORT datab (978:978:978) (1051:1051:1051)) - (PORT datac (708:708:708) (773:773:773)) - (PORT datad (743:743:743) (801:801:801)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (513:513:513) (592:592:592)) + (PORT datab (1410:1410:1410) (1563:1563:1563)) + (PORT datac (1639:1639:1639) (1703:1703:1703)) + (PORT datad (275:275:275) (357:357:357)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56473,25 +59423,98 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (443:443:443) (543:543:543)) - (PORT datab (973:973:973) (1046:1046:1046)) - (PORT datac (708:708:708) (775:775:775)) - (PORT datad (740:740:740) (796:796:796)) + (PORT dataa (664:664:664) (717:717:717)) + (PORT datab (1662:1662:1662) (1711:1711:1711)) + (PORT datad (638:638:638) (683:683:683)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1438:1438:1438) (1470:1470:1470)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1207:1207:1207) (1254:1254:1254)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1510:1510:1510) (1556:1556:1556)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT asdata (1486:1486:1486) (1503:1503:1503)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1142:1142:1142) (1195:1195:1195)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1453:1453:1453) (1491:1491:1491)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56505,10 +59528,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT datab (1176:1176:1176) (1194:1194:1194)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (228:228:228) (269:269:269)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) ) ) ) @@ -56517,13 +59539,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1878:1878:1878) (1891:1891:1891)) - (PORT asdata (517:517:517) (548:548:548)) + (PORT clk (1541:1541:1541) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -56531,8 +59553,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (389:389:389) (459:459:459)) - (PORT datab (251:251:251) (336:336:336)) + (PORT dataa (999:999:999) (1057:1057:1057)) + (PORT datab (243:243:243) (326:326:326)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -56546,9 +59568,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56576,9 +59598,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56606,9 +59628,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56622,25 +59644,35 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT datad (380:380:380) (439:439:439)) + (PORT datad (227:227:227) (299:299:299)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1549:1549:1549)) - (PORT asdata (661:661:661) (675:675:675)) - (PORT ena (1765:1765:1765) (1740:1740:1740)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1733:1733:1733) (1708:1708:1708)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -56649,31 +59681,21 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (663:663:663) (721:721:721)) + (PORT datad (222:222:222) (293:293:293)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1069:1069:1069) (1058:1058:1058)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (444:444:444) (543:543:543)) - (PORT datab (975:975:975) (1047:1047:1047)) - (PORT datac (710:710:710) (775:775:775)) - (PORT datad (742:742:742) (800:800:800)) + (PORT dataa (517:517:517) (586:586:586)) + (PORT datab (1411:1411:1411) (1560:1560:1560)) + (PORT datac (1638:1638:1638) (1700:1700:1700)) + (PORT datad (273:273:273) (353:353:353)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -56681,279 +59703,51 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1321:1321:1321) (1397:1397:1397)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1432:1432:1432) (1427:1427:1427)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (973:973:973) (1033:1033:1033)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (933:933:933) (975:975:975)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (650:650:650) (704:704:704)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (894:894:894) (929:929:929)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (991:991:991) (1050:1050:1050)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (306:306:306) (408:408:408)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (378:378:378) (431:431:431)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (404:404:404)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1044:1044:1044) (1032:1032:1032)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1185:1185:1185) (1195:1195:1195)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (645:645:645) (702:702:702)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1127:1127:1127) (1176:1176:1176)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (910:910:910) (917:917:917)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1459:1459:1459) (1485:1485:1485)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -56962,9 +59756,25 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1488:1488:1488) (1559:1559:1559)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (979:979:979) (1025:1025:1025)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1607:1607:1607) (1642:1642:1642)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -56973,38 +59783,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (645:645:645) (655:655:655)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|bits_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (643:643:643) (702:702:702)) + (PORT datad (1310:1310:1310) (1346:1346:1346)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57014,9 +59798,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57025,29 +59809,19 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (925:925:925) (942:942:942)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1883:1883:1883) (1894:1894:1894)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1217:1217:1217) (1218:1218:1218)) + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1216:1216:1216) (1226:1226:1226)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -57056,9 +59830,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1153:1153:1153) (1205:1205:1205)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1134:1134:1134) (1182:1182:1182)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57072,11 +59846,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (309:309:309) (409:409:409)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (381:381:381) (435:435:435)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (271:271:271) (357:357:357)) + (PORT datad (261:261:261) (342:342:342)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57087,9 +59861,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (309:309:309) (409:409:409)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (289:289:289) (386:386:386)) + (PORT datab (244:244:244) (326:326:326)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -57099,13 +59873,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[2\]\~0) + (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (200:200:200) (239:239:239)) + (PORT datad (811:811:811) (812:812:812)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1496:1496:1496) (1537:1537:1537)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1495:1495:1495) (1532:1532:1532)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1653:1653:1653) (1703:1703:1703)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1459:1459:1459) (1511:1511:1511)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1386:1386:1386) (1423:1423:1423)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits_prefetch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1878:1878:1878) (1889:1889:1889)) + (PORT asdata (1484:1484:1484) (1500:1500:1500)) + (PORT ena (1377:1377:1377) (1393:1393:1393)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|bits\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1719:1719:1719) (1746:1746:1746)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (460:460:460)) + (PORT datab (271:271:271) (357:357:357)) + (PORT datad (262:262:262) (345:345:345)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (386:386:386)) + (PORT datab (410:410:410) (468:468:468)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (737:737:737)) + (PORT datab (337:337:337) (360:360:360)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|cindex\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (484:484:484)) + (PORT datad (188:188:188) (217:217:217)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (352:352:352)) + (PORT datab (263:263:263) (345:345:345)) + (PORT datad (237:237:237) (306:306:306)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -57114,96 +60095,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT datad (1431:1431:1431) (1427:1427:1427)) + (PORT dataa (283:283:283) (376:376:376)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (263:263:263) (343:343:343)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (999:999:999) (1058:1058:1058)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datad (645:645:645) (655:655:655)) + (PORT dataa (271:271:271) (360:360:360)) + (PORT datad (243:243:243) (314:314:314)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (998:998:998) (1057:1057:1057)) - (PORT ena (1452:1452:1452) (1445:1445:1445)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~1) + (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datad (351:351:351) (406:406:406)) + (PORT dataa (416:416:416) (490:490:490)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57214,10 +60142,10 @@ (INSTANCE ula_\|video_\|LessThan2\~0) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (501:501:501)) - (PORT datab (289:289:289) (374:374:374)) - (PORT datac (249:249:249) (334:334:334)) - (PORT datad (264:264:264) (337:337:337)) + (PORT dataa (272:272:272) (363:363:363)) + (PORT datab (290:290:290) (376:376:376)) + (PORT datac (263:263:263) (343:343:343)) + (PORT datad (252:252:252) (328:328:328)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -57230,57 +60158,13 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (705:705:705)) - (PORT datab (467:467:467) (530:530:530)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (350:350:350) (372:372:372)) + (PORT dataa (300:300:300) (395:395:395)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (251:251:251) (335:335:335)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (504:504:504)) - (PORT datab (468:468:468) (533:533:533)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (348:348:348) (370:370:370)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (262:262:262) (348:348:348)) - (PORT datad (248:248:248) (321:321:321)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (727:727:727)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57290,10 +60174,90 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (511:511:511) (525:525:525)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (553:553:553) (568:568:568)) + (PORT datab (565:565:565) (583:583:583)) + (PORT datad (526:526:526) (522:522:522)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1442:1442:1442) (1438:1438:1438)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (397:397:397)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (254:254:254) (339:339:339)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (361:361:361)) + (PORT datab (269:269:269) (353:353:353)) + (PORT datac (385:385:385) (449:449:449)) + (PORT datad (244:244:244) (314:314:314)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (820:820:820)) + (PORT datab (416:416:416) (482:482:482)) + (PORT datac (634:634:634) (700:700:700)) + (PORT datad (555:555:555) (571:571:571)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (490:490:490)) + (PORT datab (410:410:410) (475:475:475)) + (PORT datac (332:332:332) (351:351:351)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57304,23 +60268,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1435:1435:1435) (1539:1539:1539)) - (PORT datab (236:236:236) (279:279:279)) - (PORT datac (325:325:325) (348:348:348)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1068:1068:1068) (1056:1056:1056)) + (PORT dataa (224:224:224) (268:268:268)) + (PORT datab (216:216:216) (262:262:262)) + (PORT datac (1606:1606:1606) (1684:1684:1684)) + (PORT datad (356:356:356) (379:379:379)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57330,14 +60284,14 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT asdata (1174:1174:1174) (1180:1180:1180)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -57346,9 +60300,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (970:970:970) (1019:1019:1019)) - (PORT ena (1289:1289:1289) (1289:1289:1289)) + (PORT clk (1542:1542:1542) (1555:1555:1555)) + (PORT asdata (953:953:953) (1007:1007:1007)) + (PORT ena (1192:1192:1192) (1191:1191:1191)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57362,11 +60316,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (395:395:395)) - (PORT datab (1103:1103:1103) (1116:1116:1116)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (407:407:407) (448:448:448)) + (PORT datab (593:593:593) (619:619:619)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57377,21 +60331,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (395:395:395)) - (PORT datab (237:237:237) (282:282:282)) - (PORT datac (325:325:325) (348:348:348)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1310:1310:1310) (1352:1352:1352)) + (PORT dataa (410:410:410) (435:435:435)) + (PORT datac (201:201:201) (239:239:239)) + (PORT datad (361:361:361) (379:379:379)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57401,51 +60345,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1944:1944:1944) (1933:1933:1933)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (930:930:930) (973:973:973)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1010:1010:1010) (1067:1067:1067)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1974:1974:1974) (2015:2015:2015)) + (PORT ena (1442:1442:1442) (1438:1438:1438)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57459,8 +60361,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1045:1045:1045) (1032:1032:1032)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (842:842:842) (852:852:852)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -57469,9 +60371,61 @@ (INSTANCE ula_\|video_\|attr_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (626:626:626) (669:669:669)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1459:1459:1459) (1511:1511:1511)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57482,12 +60436,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) + (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (1430:1430:1430) (1470:1470:1470)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1733:1733:1733) (1770:1770:1770)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57501,9 +60455,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (269:269:269)) - (PORT datad (218:218:218) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (378:378:378) (443:443:443)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57514,13 +60468,13 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (240:240:240) (285:285:285)) - (PORT datac (859:859:859) (931:931:931)) - (PORT datad (318:318:318) (335:335:335)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1588:1588:1588) (1694:1694:1694)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (781:781:781) (783:783:783)) + (PORT datad (358:358:358) (378:378:378)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57530,75 +60484,23 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (394:394:394)) - (PORT datac (603:603:603) (618:618:618)) - (PORT datad (315:315:315) (331:331:331)) + (PORT dataa (232:232:232) (279:279:279)) + (PORT datac (370:370:370) (397:397:397)) + (PORT datad (360:360:360) (381:381:381)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|border\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (578:578:578) (598:598:598)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1516:1516:1516) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1726:1726:1726) (1702:1702:1702)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (912:912:912) (918:918:918)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (973:973:973) (1033:1033:1033)) - (PORT ena (1452:1452:1452) (1445:1445:1445)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1530:1530:1530) (1570:1570:1570)) + (PORT ena (1642:1642:1642) (1632:1632:1632)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57607,13 +60509,65 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (1119:1119:1119) (1146:1146:1146)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1907:1907:1907) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (889:889:889) (928:928:928)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1247:1247:1247) (1238:1238:1238)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (929:929:929) (945:945:945)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (876:876:876) (886:886:886)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -57622,9 +60576,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT clk (1907:1907:1907) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1204:1204:1204)) + (PORT ena (1692:1692:1692) (1680:1680:1680)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57638,9 +60592,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1553:1553:1553)) - (PORT asdata (974:974:974) (1030:1030:1030)) - (PORT ena (1227:1227:1227) (1206:1206:1206)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) + (PORT asdata (1188:1188:1188) (1223:1223:1223)) + (PORT ena (1720:1720:1720) (1693:1693:1693)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57654,9 +60608,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (379:379:379) (445:445:445)) - (PORT datad (187:187:187) (222:222:222)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (414:414:414) (476:476:476)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57667,13 +60621,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1720:1720:1720) (1842:1842:1842)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (364:364:364) (389:389:389)) - (PORT datad (369:369:369) (393:393:393)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1358:1358:1358) (1420:1420:1420)) + (PORT datab (383:383:383) (414:414:414)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57683,35 +60637,21 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (393:393:393)) - (PORT datab (348:348:348) (385:385:385)) - (PORT datad (371:371:371) (397:397:397)) + (PORT dataa (660:660:660) (694:694:694)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (358:358:358) (379:379:379)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (960:960:960)) - (PORT datac (851:851:851) (897:897:897)) - (PORT datad (1129:1129:1129) (1171:1171:1171)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT clk (1542:1542:1542) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -57720,14 +60660,28 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (812:812:812)) + (PORT datac (696:696:696) (765:765:765)) + (PORT datad (1593:1593:1593) (1636:1636:1636)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (401:401:401) (435:435:435)) - (PORT datad (362:362:362) (380:380:380)) + (PORT dataa (211:211:211) (260:260:260)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -57741,7 +60695,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (2297:2297:2297) (2325:2325:2325)) + (PORT d (1857:1857:1857) (1908:1908:1908)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -57755,7 +60709,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT clk (1541:1541:1541) (1554:1554:1554)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -57769,11 +60723,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (381:381:381)) - (PORT datab (527:527:527) (549:549:549)) - (PORT datad (1470:1470:1470) (1488:1488:1488)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (231:231:231) (273:273:273)) + (PORT datad (720:720:720) (777:777:777)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57785,7 +60739,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1566:1566:1566) (1671:1671:1671)) + (PORT d (1667:1667:1667) (1712:1712:1712)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -57799,7 +60753,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (252:252:252) (325:325:325)) + (PORT datad (248:248:248) (320:320:320)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57809,10 +60763,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -57827,10 +60781,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT asdata (558:558:558) (632:632:632)) - (PORT clrn (1582:1582:1582) (1558:1558:1558)) - (PORT ena (1243:1243:1243) (1234:1234:1234)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (562:562:562) (636:636:636)) + (PORT clrn (1553:1553:1553) (1535:1535:1535)) + (PORT ena (1408:1408:1408) (1391:1391:1391)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -57845,7 +60799,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (252:252:252) (324:324:324)) + (PORT datad (243:243:243) (313:313:313)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -57856,9 +60810,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1472:1472:1472) (1513:1513:1513)) - (PORT datad (250:250:250) (324:324:324)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (4333:4333:4333) (4475:4475:4475)) + (PORT datad (1446:1446:1446) (1474:1474:1474)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57868,11 +60822,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT dataa (973:973:973) (1037:1037:1037)) - (PORT datac (3465:3465:3465) (3837:3837:3837)) - (PORT datad (596:596:596) (610:610:610)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (3483:3483:3483) (3768:3768:3768)) + (PORT datab (682:682:682) (735:735:735)) + (PORT datad (1183:1183:1183) (1230:1230:1230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57882,9 +60836,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (997:997:997) (1007:1007:1007)) + (PORT ena (1653:1653:1653) (1635:1635:1635)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -57898,69 +60852,11 @@ (INSTANCE sdram_\|Mux26\~4) (DELAY (ABSOLUTE - (PORT dataa (2317:2317:2317) (2532:2532:2532)) - (PORT datab (938:938:938) (974:974:974)) - (PORT datad (1425:1425:1425) (1536:1536:1536)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT datac (989:989:989) (1111:1111:1111)) - (PORT datad (1785:1785:1785) (1929:1929:1929)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (953:953:953)) - (PORT datab (830:830:830) (930:930:930)) - (PORT datac (782:782:782) (889:889:889)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (292:292:292) (378:378:378)) - (PORT datac (585:585:585) (604:604:604)) - (PORT datad (284:284:284) (364:364:364)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1121:1121:1121)) - (PORT datab (1035:1035:1035) (1089:1089:1089)) - (PORT datac (1056:1056:1056) (1136:1136:1136)) - (PORT datad (599:599:599) (611:611:611)) + (PORT dataa (2172:2172:2172) (2322:2322:2322)) + (PORT datac (1891:1891:1891) (1929:1929:1929)) + (PORT datad (245:245:245) (317:317:317)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -57970,26 +60866,40 @@ (INSTANCE sdram_\|r\.bank\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1427:1427:1427)) - (PORT datab (1874:1874:1874) (2002:2002:2002)) - (PORT datac (992:992:992) (1110:1110:1110)) - (PORT datad (778:778:778) (811:811:811)) + (PORT dataa (1578:1578:1578) (1710:1710:1710)) + (PORT datac (1837:1837:1837) (1945:1945:1945)) + (PORT datad (1315:1315:1315) (1431:1431:1431)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~8) + (INSTANCE sdram_\|r\.bank\[0\]\~4) (DELAY (ABSOLUTE - (PORT datab (1299:1299:1299) (1369:1369:1369)) - (PORT datac (1841:1841:1841) (1973:1973:1973)) - (PORT datad (995:995:995) (1099:1099:1099)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (910:910:910) (978:978:978)) + (PORT datac (1257:1257:1257) (1361:1361:1361)) + (PORT datad (1577:1577:1577) (1678:1678:1678)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1422:1422:1422)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (881:881:881) (948:948:948)) + (PORT datad (851:851:851) (881:881:881)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58000,13 +60910,43 @@ (INSTANCE sdram_\|r\.bank\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (897:897:897) (958:958:958)) - (PORT datab (829:829:829) (935:935:935)) + (PORT dataa (1288:1288:1288) (1407:1407:1407)) + (PORT datab (208:208:208) (250:250:250)) (PORT datac (180:180:180) (217:217:217)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (851:851:851) (884:884:884)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1578:1578:1578) (1712:1712:1712)) + (PORT datac (1839:1839:1839) (1941:1941:1941)) + (PORT datad (1315:1315:1315) (1426:1426:1426)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1472:1472:1472)) + (PORT datab (910:910:910) (982:982:982)) + (PORT datac (1541:1541:1541) (1673:1673:1673)) + (PORT datad (1247:1247:1247) (1360:1360:1360)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58016,13 +60956,61 @@ (INSTANCE sdram_\|r\.bank\[0\]\~9) (DELAY (ABSOLUTE - (PORT dataa (1316:1316:1316) (1427:1427:1427)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1584:1584:1584) (1713:1713:1713)) + (PORT datab (888:888:888) (919:919:919)) + (PORT datac (1837:1837:1837) (1940:1940:1940)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1421:1421:1421)) + (PORT datab (1574:1574:1574) (1707:1707:1707)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1718:1718:1718)) + (PORT datab (207:207:207) (247:247:247)) + (PORT datac (1837:1837:1837) (1941:1941:1941)) + (PORT datad (1309:1309:1309) (1423:1423:1423)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1572:1572:1572) (1707:1707:1707)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58033,8 +61021,8 @@ (DELAY (ABSOLUTE (PORT clk (1514:1514:1514) (1539:1539:1539)) - (PORT d (1777:1777:1777) (1875:1875:1875)) - (PORT ena (1774:1774:1774) (1775:1775:1775)) + (PORT d (2089:2089:2089) (2206:2206:2206)) + (PORT ena (1461:1461:1461) (1494:1494:1494)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58050,11 +61038,11 @@ (INSTANCE sdram_\|Mux25\~4) (DELAY (ABSOLUTE - (PORT dataa (2317:2317:2317) (2534:2534:2534)) - (PORT datab (1431:1431:1431) (1561:1561:1561)) - (PORT datad (913:913:913) (939:939:939)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (825:825:825) (883:883:883)) + (PORT datab (1919:1919:1919) (1962:1962:1962)) + (PORT datad (2145:2145:2145) (2277:2277:2277)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58065,8 +61053,8 @@ (DELAY (ABSOLUTE (PORT clk (1516:1516:1516) (1540:1540:1540)) - (PORT d (2321:2321:2321) (2432:2432:2432)) - (PORT ena (1597:1597:1597) (1608:1608:1608)) + (PORT d (1811:1811:1811) (1934:1934:1934)) + (PORT ena (1453:1453:1453) (1487:1487:1487)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58079,74 +61067,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~5) + (INSTANCE sdram_\|Mux71\~6) (DELAY (ABSOLUTE - (PORT dataa (1066:1066:1066) (1202:1202:1202)) - (PORT datab (1024:1024:1024) (1113:1113:1113)) - (PORT datac (1152:1152:1152) (1196:1196:1196)) - (PORT datad (994:994:994) (1081:1081:1081)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1631:1631:1631) (1756:1756:1756)) + (PORT datab (1139:1139:1139) (1252:1252:1252)) + (PORT datac (1030:1030:1030) (1149:1149:1149)) + (PORT datad (1072:1072:1072) (1197:1197:1197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~0) - (DELAY - (ABSOLUTE - (PORT datab (1399:1399:1399) (1527:1527:1527)) - (PORT datac (1575:1575:1575) (1656:1656:1656)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~7) - (DELAY - (ABSOLUTE - (PORT datab (1709:1709:1709) (1882:1882:1882)) - (PORT datac (221:221:221) (300:300:300)) - (PORT datad (2617:2617:2617) (2813:2813:2813)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (772:772:772)) - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux71\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1307:1307:1307) (1422:1422:1422)) - (PORT datab (1474:1474:1474) (1580:1580:1580)) - (PORT datac (1576:1576:1576) (1657:1657:1657)) - (PORT datad (1362:1362:1362) (1488:1488:1488)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58156,13 +61086,9 @@ (INSTANCE sdram_\|Mux71\~2) (DELAY (ABSOLUTE - (PORT dataa (1306:1306:1306) (1421:1421:1421)) - (PORT datab (1020:1020:1020) (1139:1139:1139)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (189:189:189) (219:219:219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (1104:1104:1104) (1217:1217:1217)) + (PORT datad (1589:1589:1589) (1704:1704:1704)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58172,13 +61098,42 @@ (INSTANCE sdram_\|Mux71\~3) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1128:1128:1128)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1032:1032:1032) (1159:1159:1159)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1278:1278:1278) (1400:1400:1400)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (1070:1070:1070) (1196:1196:1196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1352:1352:1352)) + (PORT datad (1506:1506:1506) (1605:1605:1605)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (789:789:789)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (488:488:488) (500:500:500)) + (PORT datad (334:334:334) (351:351:351)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58188,12 +61143,44 @@ (INSTANCE sdram_\|Mux71\~4) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (171:171:171) (202:202:202)) - (PORT datad (996:996:996) (1103:1103:1103)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (625:625:625) (647:647:647)) + (PORT datad (1253:1253:1253) (1356:1356:1356)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~8) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (549:549:549)) + (PORT datab (939:939:939) (952:952:952)) + (PORT datac (1032:1032:1032) (1150:1150:1150)) + (PORT datad (628:628:628) (679:679:679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~5) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1102:1102:1102) (1233:1233:1233)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58205,7 +61192,7 @@ (DELAY (ABSOLUTE (PORT clk (1513:1513:1513) (1537:1537:1537)) - (PORT d (1467:1467:1467) (1545:1545:1545)) + (PORT d (1509:1509:1509) (1602:1602:1602)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58220,7 +61207,7 @@ (DELAY (ABSOLUTE (PORT clk (1513:1513:1513) (1537:1537:1537)) - (PORT d (1454:1454:1454) (1530:1530:1530)) + (PORT d (1509:1509:1509) (1602:1602:1602)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -58231,43 +61218,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.bank\[0\]\~10) + (INSTANCE sdram_\|n\~6) (DELAY (ABSOLUTE - (PORT datac (1570:1570:1570) (1649:1649:1649)) - (PORT datad (996:996:996) (1103:1103:1103)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~3) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (399:399:399)) - (PORT datab (1477:1477:1477) (1604:1604:1604)) - (PORT datac (1329:1329:1329) (1470:1470:1470)) - (PORT datad (353:353:353) (368:368:368)) + (PORT dataa (918:918:918) (1021:1021:1021)) + (PORT datab (999:999:999) (1096:1096:1096)) + (PORT datac (875:875:875) (938:938:938)) + (PORT datad (994:994:994) (1085:1085:1085)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~5) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (521:521:521)) - (PORT datab (698:698:698) (778:778:778)) - (PORT datac (586:586:586) (604:604:604)) - (PORT datad (285:285:285) (364:364:364)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58275,153 +61234,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~4) + (INSTANCE sdram_\|Mux9\~0) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (378:378:378)) - (PORT datab (1370:1370:1370) (1466:1466:1466)) - (PORT datac (882:882:882) (893:893:893)) - (PORT datad (1440:1440:1440) (1565:1565:1565)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1518:1518:1518)) - (PORT datab (1371:1371:1371) (1460:1460:1460)) - (PORT datac (881:881:881) (891:891:891)) - (PORT datad (1253:1253:1253) (1312:1312:1312)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (870:870:870)) - (PORT datab (302:302:302) (394:394:394)) - (PORT datac (631:631:631) (680:680:680)) - (PORT datad (754:754:754) (832:832:832)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (696:696:696) (717:717:717)) + (PORT datab (790:790:790) (876:876:876)) + (PORT datac (775:775:775) (878:878:878)) + (PORT datad (863:863:863) (936:936:936)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~2) - (DELAY - (ABSOLUTE - (PORT datab (449:449:449) (513:513:513)) - (PORT datac (415:415:415) (481:481:481)) - (PORT datad (588:588:588) (645:645:645)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~3) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (498:498:498)) - (PORT datab (272:272:272) (357:357:357)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (425:425:425) (483:483:483)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|process_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (497:497:497)) - (PORT datab (450:450:450) (516:516:516)) - (PORT datac (353:353:353) (381:381:381)) - (PORT datad (411:411:411) (473:473:473)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~4) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (423:423:423) (493:493:493)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (683:683:683) (766:766:766)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux9\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1547:1547:1547)) - (PORT datab (1604:1604:1604) (1732:1732:1732)) - (PORT datac (1336:1336:1336) (1427:1427:1427)) - (PORT datad (332:332:332) (354:354:354)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux7\~0) - (DELAY - (ABSOLUTE - (PORT datab (1369:1369:1369) (1466:1466:1466)) - (PORT datad (1568:1568:1568) (1695:1695:1695)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux9\~6) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (423:423:423)) - (PORT datab (643:643:643) (685:685:685)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (639:639:639) (675:675:675)) + (PORT datab (961:961:961) (1036:1036:1036)) + (PORT datac (776:776:776) (877:877:877)) + (PORT datad (656:656:656) (671:671:671)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58432,13 +61269,167 @@ (INSTANCE sdram_\|Mux9\~7) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1269:1269:1269) (1350:1350:1350)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (772:772:772) (889:889:889)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (858:858:858) (948:948:948)) + (PORT datad (755:755:755) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datac (775:775:775) (878:878:878)) + (PORT datad (752:752:752) (834:834:834)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (386:386:386)) + (PORT datab (431:431:431) (502:502:502)) + (PORT datac (404:404:404) (469:469:469)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (402:402:402)) + (PORT datab (439:439:439) (499:499:499)) + (PORT datac (405:405:405) (466:466:466)) + (PORT datad (376:376:376) (431:431:431)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (488:488:488)) + (PORT datac (404:404:404) (469:469:469)) + (PORT datad (262:262:262) (344:344:344)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (399:399:399) (468:468:468)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (509:509:509)) + (PORT datab (429:429:429) (501:501:501)) + (PORT datac (384:384:384) (445:445:445)) + (PORT datad (260:260:260) (342:342:342)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (482:482:482)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (671:671:671)) + (PORT datab (791:791:791) (872:872:872)) + (PORT datac (775:775:775) (873:873:873)) + (PORT datad (743:743:743) (844:844:844)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (385:385:385)) + (PORT datab (624:624:624) (691:691:691)) + (PORT datac (609:609:609) (652:652:652)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (931:931:931) (1005:1005:1005)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58448,8 +61439,8 @@ (INSTANCE sdram_\|r\.state\[2\]) (DELAY (ABSOLUTE - (PORT clk (1498:1498:1498) (1529:1529:1529)) - (PORT d (1472:1472:1472) (1557:1557:1557)) + (PORT clk (1489:1489:1489) (1513:1513:1513)) + (PORT d (1600:1600:1600) (1700:1700:1700)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58460,32 +61451,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~11) + (INSTANCE sdram_\|Mux10\~6) (DELAY (ABSOLUTE - (PORT dataa (981:981:981) (1112:1112:1112)) - (PORT datab (1023:1023:1023) (1115:1115:1115)) - (PORT datac (1152:1152:1152) (1199:1199:1199)) - (PORT datad (995:995:995) (1083:1083:1083)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1357:1357:1357) (1482:1482:1482)) + (PORT datab (958:958:958) (1039:1039:1039)) + (PORT datac (1050:1050:1050) (1161:1161:1161)) + (PORT datad (1262:1262:1262) (1353:1353:1353)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~6) + (INSTANCE sdram_\|Mux10\~10) (DELAY (ABSOLUTE - (PORT dataa (1063:1063:1063) (1201:1201:1201)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (1060:1060:1060) (1092:1092:1092)) - (PORT datad (968:968:968) (1089:1089:1089)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1630:1630:1630) (1751:1751:1751)) + (PORT datab (1103:1103:1103) (1232:1232:1232)) + (PORT datac (634:634:634) (645:645:645)) + (PORT datad (612:612:612) (634:634:634)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1483:1483:1483)) + (PORT datab (880:880:880) (983:983:983)) + (PORT datac (1011:1011:1011) (1104:1104:1104)) + (PORT datad (1262:1262:1262) (1352:1352:1352)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1478:1478:1478)) + (PORT datab (878:878:878) (981:981:981)) + (PORT datac (1012:1012:1012) (1101:1101:1101)) + (PORT datad (1261:1261:1261) (1348:1348:1348)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58495,13 +61518,13 @@ (INSTANCE sdram_\|Mux10\~5) (DELAY (ABSOLUTE - (PORT dataa (1306:1306:1306) (1421:1421:1421)) - (PORT datab (1399:1399:1399) (1528:1528:1528)) - (PORT datac (948:948:948) (1069:1069:1069)) - (PORT datad (635:635:635) (671:671:671)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1089:1089:1089) (1196:1196:1196)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1168:1168:1168) (1176:1176:1176)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58511,12 +61534,44 @@ (INSTANCE sdram_\|Mux10\~7) (DELAY (ABSOLUTE - (PORT dataa (1062:1062:1062) (1202:1202:1202)) - (PORT datab (1398:1398:1398) (1531:1531:1531)) - (PORT datac (948:948:948) (1074:1074:1074)) - (PORT datad (968:968:968) (1089:1089:1089)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (992:992:992) (1071:1071:1071)) + (PORT datab (1005:1005:1005) (1086:1086:1086)) + (PORT datac (1049:1049:1049) (1156:1156:1156)) + (PORT datad (1261:1261:1261) (1348:1348:1348)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1060:1060:1060) (1185:1185:1185)) + (PORT datab (984:984:984) (1016:1016:1016)) + (PORT datac (590:590:590) (614:614:614)) + (PORT datad (609:609:609) (633:633:633)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1182:1182:1182)) + (PORT datab (1103:1103:1103) (1231:1231:1231)) + (PORT datac (625:625:625) (649:649:649)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58527,29 +61582,13 @@ (INSTANCE sdram_\|Mux10\~8) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (1021:1021:1021) (1144:1144:1144)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux10\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1104:1104:1104) (1239:1239:1239)) + (PORT datac (618:618:618) (631:631:631)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58559,8 +61598,8 @@ (INSTANCE sdram_\|r\.state\[1\]) (DELAY (ABSOLUTE - (PORT clk (1498:1498:1498) (1529:1529:1529)) - (PORT d (1253:1253:1253) (1356:1356:1356)) + (PORT clk (1489:1489:1489) (1513:1513:1513)) + (PORT d (1273:1273:1273) (1377:1377:1377)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58599,16 +61638,50 @@ (HOLD d (posedge clk) (83:83:83)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1332:1332:1332)) + (PORT datab (1071:1071:1071) (1170:1170:1170)) + (PORT datac (1255:1255:1255) (1352:1352:1352)) + (PORT datad (1308:1308:1308) (1406:1406:1406)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (661:661:661)) + (PORT datab (1093:1093:1093) (1203:1203:1203)) + (PORT datac (1260:1260:1260) (1357:1357:1357)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux11\~2) (DELAY (ABSOLUTE - (PORT dataa (743:743:743) (861:861:861)) - (PORT datab (780:780:780) (870:870:870)) - (PORT datad (273:273:273) (356:356:356)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (591:591:591) (613:613:613)) + (PORT datab (1079:1079:1079) (1175:1175:1175)) + (PORT datac (617:617:617) (636:636:636)) + (PORT datad (1064:1064:1064) (1157:1157:1157)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58618,28 +61691,12 @@ (INSTANCE sdram_\|Mux11\~3) (DELAY (ABSOLUTE - (PORT dataa (1511:1511:1511) (1631:1631:1631)) - (PORT datab (655:655:655) (707:707:707)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1409:1409:1409) (1518:1518:1518)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1360:1360:1360) (1508:1508:1508)) - (PORT datab (1372:1372:1372) (1466:1466:1466)) - (PORT datac (626:626:626) (666:666:666)) - (PORT datad (323:323:323) (345:345:345)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1316:1316:1316) (1447:1447:1447)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (1836:1836:1836) (1947:1947:1947)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58650,13 +61707,13 @@ (INSTANCE sdram_\|Mux11\~5) (DELAY (ABSOLUTE - (PORT dataa (1359:1359:1359) (1509:1509:1509)) - (PORT datab (1372:1372:1372) (1466:1466:1466)) - (PORT datac (1581:1581:1581) (1661:1661:1661)) - (PORT datad (1257:1257:1257) (1317:1317:1317)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1303:1303:1303) (1398:1398:1398)) + (PORT datab (1072:1072:1072) (1171:1171:1171)) + (PORT datac (889:889:889) (984:984:984)) + (PORT datad (1058:1058:1058) (1161:1161:1161)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58666,12 +61723,12 @@ (INSTANCE sdram_\|Mux11\~6) (DELAY (ABSOLUTE - (PORT dataa (985:985:985) (1116:1116:1116)) - (PORT datab (1024:1024:1024) (1143:1143:1143)) - (PORT datac (1035:1035:1035) (1162:1162:1162)) - (PORT datad (971:971:971) (1090:1090:1090)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (337:337:337) (374:374:374)) + (PORT datab (904:904:904) (969:969:969)) + (PORT datac (961:961:961) (1058:1058:1058)) + (PORT datad (995:995:995) (1086:1086:1086)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58682,42 +61739,10 @@ (INSTANCE sdram_\|Mux11\~7) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (960:960:960)) - (PORT datab (829:829:829) (930:930:930)) - (PORT datac (783:783:783) (893:893:893)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1426:1426:1426) (1549:1549:1549)) - (PORT datab (1264:1264:1264) (1350:1350:1350)) - (PORT datac (883:883:883) (894:894:894)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux11\~8) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (597:597:597) (604:604:604)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (798:798:798) (810:810:810)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -58731,7 +61756,7 @@ (DELAY (ABSOLUTE (PORT clk (1495:1495:1495) (1520:1520:1520)) - (PORT d (1809:1809:1809) (1935:1935:1935)) + (PORT d (1562:1562:1562) (1673:1673:1673)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58742,62 +61767,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux24\~2) + (INSTANCE sdram_\|Mux24\~5) (DELAY (ABSOLUTE - (PORT dataa (776:776:776) (869:869:869)) - (PORT datab (765:765:765) (852:852:852)) - (PORT datac (764:764:764) (877:877:877)) - (PORT datad (860:860:860) (888:888:888)) - (IOPATH dataa combout (303:303:303) (299:299:299)) + (PORT dataa (1190:1190:1190) (1263:1263:1263)) + (PORT datab (689:689:689) (755:755:755)) + (PORT datac (966:966:966) (1030:1030:1030)) + (PORT datad (649:649:649) (666:666:666)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~7) + (INSTANCE sdram_\|Mux24\~6) (DELAY (ABSOLUTE - (PORT dataa (3061:3061:3061) (3225:3225:3225)) - (PORT datab (612:612:612) (668:668:668)) - (PORT datac (1038:1038:1038) (1141:1141:1141)) - (PORT datad (632:632:632) (661:661:661)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (632:632:632)) - (PORT datab (993:993:993) (1068:1068:1068)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux13\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1510:1510:1510)) - (PORT datab (1269:1269:1269) (1353:1353:1353)) - (PORT datac (1581:1581:1581) (1661:1661:1661)) - (PORT datad (1441:1441:1441) (1561:1561:1561)) + (PORT dataa (349:349:349) (382:382:382)) + (PORT datab (689:689:689) (755:755:755)) + (PORT datac (1308:1308:1308) (1392:1392:1392)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58808,10 +61802,10 @@ (INSTANCE sdram_\|Mux13\~4) (DELAY (ABSOLUTE - (PORT dataa (1367:1367:1367) (1518:1518:1518)) - (PORT datab (1264:1264:1264) (1346:1346:1346)) - (PORT datac (1575:1575:1575) (1654:1654:1654)) - (PORT datad (1444:1444:1444) (1567:1567:1567)) + (PORT dataa (1877:1877:1877) (1991:1991:1991)) + (PORT datab (1077:1077:1077) (1173:1173:1173)) + (PORT datac (996:996:996) (1112:1112:1112)) + (PORT datad (1062:1062:1062) (1156:1156:1156)) (IOPATH dataa combout (337:337:337) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -58819,16 +61813,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1877:1877:1877) (1991:1991:1991)) + (PORT datab (1078:1078:1078) (1174:1174:1174)) + (PORT datac (995:995:995) (1111:1111:1111)) + (PORT datad (1063:1063:1063) (1157:1157:1157)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux13\~5) (DELAY (ABSOLUTE - (PORT datab (1371:1371:1371) (1460:1460:1460)) - (PORT datac (175:175:175) (208:208:208)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datac (1283:1283:1283) (1408:1408:1408)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58838,11 +61848,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1560:1560:1560)) + (PORT clk (1531:1531:1531) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (523:523:523) (557:557:557)) - (PORT sload (1639:1639:1639) (1751:1751:1751)) - (PORT ena (1247:1247:1247) (1254:1254:1254)) + (PORT asdata (923:923:923) (937:937:937)) + (PORT sload (1918:1918:1918) (2069:2069:2069)) + (PORT ena (1276:1276:1276) (1258:1258:1258)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -58853,18 +61863,30 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (891:891:891)) + (PORT datab (848:848:848) (890:890:890)) + (PORT datac (623:623:623) (691:691:691)) + (PORT datad (1840:1840:1840) (1924:1924:1924)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux24\~3) (DELAY (ABSOLUTE - (PORT dataa (3061:3061:3061) (3223:3223:3223)) - (PORT datab (613:613:613) (668:668:668)) - (PORT datac (380:380:380) (405:405:405)) - (PORT datad (632:632:632) (657:657:657)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (481:481:481) (562:562:562)) + (PORT datad (1330:1330:1330) (1467:1467:1467)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58874,13 +61896,27 @@ (INSTANCE sdram_\|Mux24\~4) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (956:956:956)) - (PORT datab (614:614:614) (671:671:671)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1100:1100:1100) (1185:1185:1185)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (706:706:706) (789:789:789)) + (PORT datab (689:689:689) (751:751:751)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (512:512:512) (525:525:525)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (656:656:656)) + (PORT datab (1638:1638:1638) (1747:1747:1747)) + (PORT datad (322:322:322) (344:344:344)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58890,11 +61926,11 @@ (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (1063:1063:1063) (1134:1134:1134)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1306:1306:1306) (1425:1425:1425)) + (PORT datad (358:358:358) (375:375:375)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -58905,8 +61941,8 @@ (DELAY (ABSOLUTE (PORT clk (1497:1497:1497) (1522:1522:1522)) - (PORT d (2000:2000:2000) (2102:2102:2102)) - (PORT ena (1672:1672:1672) (1717:1717:1717)) + (PORT d (1682:1682:1682) (1777:1777:1777)) + (PORT ena (1912:1912:1912) (1959:1959:1959)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -58919,57 +61955,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (INSTANCE sdram_\|Mux23\~1) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (257:257:257)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1137:1137:1137)) - (PORT datab (251:251:251) (337:337:337)) - (PORT datac (1288:1288:1288) (1347:1347:1347)) - (PORT datad (333:333:333) (361:361:361)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Equal5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (748:748:748) (867:867:867)) - (PORT datab (780:780:780) (874:874:874)) - (PORT datac (627:627:627) (678:678:678)) - (PORT datad (275:275:275) (357:357:357)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1030:1030:1030) (1138:1138:1138)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (957:957:957) (1041:1041:1041)) - (PORT datad (864:864:864) (898:898:898)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1699:1699:1699) (1817:1817:1817)) + (PORT datab (691:691:691) (742:742:742)) + (PORT datac (817:817:817) (841:841:841)) + (PORT datad (1340:1340:1340) (1475:1475:1475)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -58977,32 +61971,100 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~6) + (INSTANCE sdram_\|r\.address\[1\]\~8) (DELAY (ABSOLUTE - (PORT dataa (1033:1033:1033) (1138:1138:1138)) - (PORT datab (1067:1067:1067) (1184:1184:1184)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (886:886:886) (884:884:884)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1701:1701:1701) (1818:1818:1818)) + (PORT datab (1367:1367:1367) (1519:1519:1519)) + (PORT datad (843:843:843) (859:859:859)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1356:1356:1356)) + (PORT datab (1260:1260:1260) (1338:1338:1338)) + (PORT datad (1329:1329:1329) (1462:1462:1462)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1700:1700:1700) (1816:1816:1816)) + (PORT datab (1363:1363:1363) (1517:1517:1517)) + (PORT datac (897:897:897) (973:973:973)) + (PORT datad (1535:1535:1535) (1659:1659:1659)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (1565:1565:1565) (1695:1695:1695)) + (PORT datac (573:573:573) (581:581:581)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (890:890:890) (941:941:941)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~0) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1361:1361:1361)) - (PORT datab (1090:1090:1090) (1165:1165:1165)) - (PORT datac (1257:1257:1257) (1368:1368:1368)) - (PORT datad (1000:1000:1000) (1053:1053:1053)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1315:1315:1315) (1445:1445:1445)) + (PORT datab (1034:1034:1034) (1151:1151:1151)) + (PORT datac (1214:1214:1214) (1307:1307:1307)) + (PORT datad (1054:1054:1054) (1152:1152:1152)) + (IOPATH dataa combout (350:350:350) (367:367:367)) + (IOPATH datab combout (350:350:350) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59012,11 +62074,11 @@ (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT clk (1535:1535:1535) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (523:523:523) (558:558:558)) - (PORT sload (1747:1747:1747) (1674:1674:1674)) - (PORT ena (1291:1291:1291) (1292:1292:1292)) + (PORT asdata (1394:1394:1394) (1420:1420:1420)) + (PORT sload (2223:2223:2223) (2152:2152:2152)) + (PORT ena (1223:1223:1223) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -59029,15 +62091,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~2) + (INSTANCE sdram_\|Mux23\~3) (DELAY (ABSOLUTE - (PORT dataa (1311:1311:1311) (1441:1441:1441)) - (PORT datab (360:360:360) (395:395:395)) - (PORT datac (957:957:957) (1039:1039:1039)) - (PORT datad (989:989:989) (1074:1074:1074)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1432:1432:1432) (1522:1522:1522)) + (PORT datab (675:675:675) (705:705:705)) + (PORT datac (931:931:931) (999:999:999)) + (PORT datad (1817:1817:1817) (1943:1943:1943)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59045,44 +62107,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~3) + (INSTANCE sdram_\|Mux23\~4) (DELAY (ABSOLUTE - (PORT dataa (1312:1312:1312) (1442:1442:1442)) - (PORT datac (518:518:518) (537:537:537)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (660:660:660) (701:701:701)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1402:1402:1402) (1480:1480:1480)) + (PORT datad (1058:1058:1058) (1172:1172:1172)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~1) + (INSTANCE sdram_\|Mux23\~2) (DELAY (ABSOLUTE - (PORT dataa (1308:1308:1308) (1440:1440:1440)) - (PORT datab (2607:2607:2607) (2785:2785:2785)) - (PORT datac (1734:1734:1734) (1812:1812:1812)) - (PORT datad (991:991:991) (1080:1080:1080)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1105:1105:1105) (1221:1221:1221)) + (PORT datab (912:912:912) (939:939:939)) + (PORT datac (717:717:717) (801:801:801)) + (PORT datad (896:896:896) (967:967:967)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[1\]\~1) + (INSTANCE sdram_\|Mux23\~5) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1429:1429:1429) (1520:1520:1520)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (342:342:342) (363:363:363)) + (PORT datad (1058:1058:1058) (1173:1173:1173)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59092,12 +62158,12 @@ (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1028:1028:1028) (1131:1131:1131)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (666:666:666) (699:699:699)) + (PORT datac (1286:1286:1286) (1406:1406:1406)) + (PORT datad (606:606:606) (649:649:649)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -59107,8 +62173,8 @@ (DELAY (ABSOLUTE (PORT clk (1516:1516:1516) (1540:1540:1540)) - (PORT d (1503:1503:1503) (1609:1609:1609)) - (PORT ena (1911:1911:1911) (1938:1938:1938)) + (PORT d (1764:1764:1764) (1872:1872:1872)) + (PORT ena (2195:2195:2195) (2247:2247:2247)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59119,91 +62185,17 @@ (HOLD ena (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1437:1437:1437)) - (PORT datab (1036:1036:1036) (1094:1094:1094)) - (PORT datac (1028:1028:1028) (1133:1133:1133)) - (PORT datad (990:990:990) (1085:1085:1085)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT datab (1036:1036:1036) (1091:1091:1091)) - (PORT datad (1280:1280:1280) (1394:1394:1394)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux21\~0) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (287:287:287)) - (PORT datab (1062:1062:1062) (1180:1180:1180)) - (PORT datac (314:314:314) (333:333:333)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux22\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (748:748:748)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (879:879:879) (894:894:894)) - (PORT datad (635:635:635) (660:660:660)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1813:1813:1813) (1972:1972:1972)) - (PORT datab (1021:1021:1021) (1144:1144:1144)) - (PORT datac (781:781:781) (894:894:894)) - (PORT datad (790:790:790) (895:895:895)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~11) (DELAY (ABSOLUTE - (PORT datab (816:816:816) (925:925:925)) - (PORT datac (1840:1840:1840) (1973:1973:1973)) - (PORT datad (994:994:994) (1103:1103:1103)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1630:1630:1630) (1751:1751:1751)) + (PORT datab (1102:1102:1102) (1231:1231:1231)) + (PORT datac (1030:1030:1030) (1149:1149:1149)) + (PORT datad (1194:1194:1194) (1280:1280:1280)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59214,12 +62206,8 @@ (INSTANCE sdram_\|r\.address\[3\]\~12) (DELAY (ABSOLUTE - (PORT dataa (897:897:897) (953:953:953)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1841:1841:1841) (1971:1971:1971)) - (PORT datad (1238:1238:1238) (1284:1284:1284)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT datac (1001:1001:1001) (1118:1118:1118)) + (PORT datad (1054:1054:1054) (1152:1152:1152)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59227,31 +62215,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[3\]\~13) + (INSTANCE sdram_\|Mux21\~0) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1427:1427:1427)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (1396:1396:1396) (1469:1469:1469)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (893:893:893) (919:919:919)) + (PORT datab (1300:1300:1300) (1366:1366:1366)) + (PORT datac (953:953:953) (999:999:999)) + (PORT datad (903:903:903) (922:922:922)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1593:1593:1593) (1624:1624:1624)) + (PORT datab (1165:1165:1165) (1219:1219:1219)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (853:853:853) (888:888:888)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1812:1812:1812) (1971:1971:1971)) - (PORT datab (1021:1021:1021) (1141:1141:1141)) - (PORT datac (782:782:782) (892:892:892)) - (PORT datad (790:790:790) (893:893:893)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (1359:1359:1359) (1468:1468:1468)) + (PORT datac (962:962:962) (1056:1056:1056)) + (PORT datad (1044:1044:1044) (1136:1136:1136)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59262,13 +62264,29 @@ (INSTANCE sdram_\|r\.address\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (954:954:954)) - (PORT datab (199:199:199) (236:236:236)) - (PORT datac (1395:1395:1395) (1469:1469:1469)) - (PORT datad (994:994:994) (1100:1100:1100)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1297:1297:1297) (1393:1393:1393)) + (PORT datab (1360:1360:1360) (1469:1469:1469)) + (PORT datac (877:877:877) (938:938:938)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1128:1128:1128)) + (PORT datab (1072:1072:1072) (1171:1171:1171)) + (PORT datac (960:960:960) (1055:1055:1055)) + (PORT datad (1307:1307:1307) (1403:1403:1403)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59278,13 +62296,13 @@ (INSTANCE sdram_\|r\.address\[3\]\~16) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1233:1233:1233) (1279:1279:1279)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1296:1296:1296) (1393:1393:1393)) + (PORT datab (1269:1269:1269) (1363:1363:1363)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59292,13 +62310,61 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1473:1473:1473)) + (PORT datab (913:913:913) (980:980:980)) + (PORT datac (1258:1258:1258) (1362:1362:1362)) + (PORT datad (1577:1577:1577) (1678:1678:1678)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1353:1353:1353) (1475:1475:1475)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (1539:1539:1539) (1675:1675:1675)) + (PORT datad (851:851:851) (884:884:884)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~19) (DELAY (ABSOLUTE (PORT dataa (201:201:201) (245:245:245)) - (PORT datac (988:988:988) (1107:1107:1107)) - (PORT datad (172:172:172) (197:197:197)) + (PORT datab (1572:1572:1572) (1710:1710:1710)) + (PORT datac (810:810:810) (816:816:816)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1421:1421:1421)) + (PORT datac (612:612:612) (652:652:652)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59309,8 +62375,8 @@ (DELAY (ABSOLUTE (PORT clk (1516:1516:1516) (1540:1540:1540)) - (PORT d (1841:1841:1841) (1973:1973:1973)) - (PORT ena (1809:1809:1809) (1846:1846:1846)) + (PORT d (1594:1594:1594) (1730:1730:1730)) + (PORT ena (1696:1696:1696) (1760:1760:1760)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59326,13 +62392,13 @@ (INSTANCE sdram_\|Mux21\~1) (DELAY (ABSOLUTE - (PORT dataa (696:696:696) (743:743:743)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (194:194:194) (226:226:226)) - (PORT datad (638:638:638) (663:663:663)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1594:1594:1594) (1619:1619:1619)) + (PORT datab (1466:1466:1466) (1516:1516:1516)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (855:855:855) (886:886:886)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59343,8 +62409,8 @@ (DELAY (ABSOLUTE (PORT clk (1515:1515:1515) (1539:1539:1539)) - (PORT d (1556:1556:1556) (1651:1651:1651)) - (PORT ena (1611:1611:1611) (1629:1629:1629)) + (PORT d (1247:1247:1247) (1336:1336:1336)) + (PORT ena (1569:1569:1569) (1588:1588:1588)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59355,47 +62421,33 @@ (HOLD ena (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~7) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (997:997:997)) + (PORT datab (782:782:782) (882:882:882)) + (PORT datac (906:906:906) (984:984:984)) + (PORT datad (1097:1097:1097) (1205:1205:1205)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux20\~4) (DELAY (ABSOLUTE - (PORT dataa (748:748:748) (867:867:867)) - (PORT datab (781:781:781) (871:871:871)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1114:1114:1114)) - (PORT datab (2651:2651:2651) (2850:2850:2850)) - (PORT datac (1684:1684:1684) (1854:1854:1854)) - (PORT datad (931:931:931) (983:983:983)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux23\~7) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (926:926:926)) - (PORT datab (897:897:897) (930:930:930)) - (PORT datac (1265:1265:1265) (1390:1390:1390)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1910:1910:1910) (2069:2069:2069)) + (PORT datab (601:601:601) (647:647:647)) + (PORT datac (1632:1632:1632) (1746:1746:1746)) + (PORT datad (233:233:233) (309:309:309)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59403,31 +62455,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~8) + (INSTANCE sdram_\|Mux20\~2) (DELAY (ABSOLUTE - (PORT dataa (1032:1032:1032) (1126:1126:1126)) - (PORT datab (959:959:959) (1003:1003:1003)) - (PORT datac (1256:1256:1256) (1370:1370:1370)) - (PORT datad (1256:1256:1256) (1321:1321:1321)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1700:1700:1700) (1818:1818:1818)) + (PORT datab (259:259:259) (347:347:347)) + (PORT datac (1106:1106:1106) (1165:1165:1165)) + (PORT datad (653:653:653) (705:705:705)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~10) + (INSTANCE sdram_\|Mux20\~3) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1370:1370:1370)) - (PORT datab (658:658:658) (687:687:687)) - (PORT datac (589:589:589) (593:593:593)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1701:1701:1701) (1819:1819:1819)) + (PORT datac (861:861:861) (900:900:900)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59435,15 +62485,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~9) + (INSTANCE sdram_\|r\.address\[4\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1362:1362:1362)) - (PORT datab (660:660:660) (691:691:691)) - (PORT datac (588:588:588) (590:590:590)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (341:341:341) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (1563:1563:1563) (1694:1694:1694)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59451,16 +62499,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~11) + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (406:406:406) (492:492:492)) - (PORT datab (904:904:904) (946:946:946)) - (PORT datac (312:312:312) (339:339:339)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59470,11 +62512,11 @@ (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT clk (1530:1530:1530) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (684:684:684) (700:700:700)) - (PORT sload (1665:1665:1665) (1784:1784:1784)) - (PORT ena (980:980:980) (972:972:972)) + (PORT asdata (523:523:523) (557:557:557)) + (PORT sload (2191:2191:2191) (2334:2334:2334)) + (PORT ena (1460:1460:1460) (1483:1483:1483)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -59487,14 +62529,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~12) + (INSTANCE sdram_\|Mux20\~5) (DELAY (ABSOLUTE - (PORT dataa (714:714:714) (813:813:813)) - (PORT datab (2069:2069:2069) (2248:2248:2248)) - (PORT datac (2283:2283:2283) (2471:2471:2471)) - (PORT datad (867:867:867) (902:902:902)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (1241:1241:1241) (1319:1319:1319)) + (PORT datab (1297:1297:1297) (1404:1404:1404)) + (PORT datac (1487:1487:1487) (1575:1575:1575)) + (PORT datad (1336:1336:1336) (1474:1474:1474)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59503,16 +62545,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux20\~5) + (INSTANCE sdram_\|Mux20\~10) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (654:654:654) (706:706:706)) - (PORT datac (1578:1578:1578) (1695:1695:1695)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1240:1240:1240) (1316:1316:1316)) + (PORT datab (1562:1562:1562) (1695:1695:1695)) + (PORT datac (1488:1488:1488) (1573:1573:1573)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59522,27 +62564,57 @@ (INSTANCE sdram_\|Mux20\~6) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (658:658:658)) - (PORT datab (905:905:905) (948:948:948)) - (PORT datac (994:994:994) (1085:1085:1085)) - (PORT datad (378:378:378) (448:448:448)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (447:447:447) (526:526:526)) + (PORT datad (683:683:683) (749:749:749)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[4\]\~2) + (INSTANCE sdram_\|Mux20\~7) (DELAY (ABSOLUTE - (PORT dataa (1283:1283:1283) (1363:1363:1363)) - (PORT datab (616:616:616) (667:667:667)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1700:1700:1700) (1817:1817:1817)) + (PORT datab (1361:1361:1361) (1511:1511:1511)) + (PORT datac (365:365:365) (387:387:387)) + (PORT datad (1536:1536:1536) (1655:1655:1655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1535:1535:1535) (1655:1655:1655)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (345:345:345)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59552,10 +62624,10 @@ (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (1089:1089:1089) (1165:1165:1165)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1621:1621:1621) (1722:1722:1722)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59567,8 +62639,8 @@ (DELAY (ABSOLUTE (PORT clk (1517:1517:1517) (1542:1542:1542)) - (PORT d (1700:1700:1700) (1761:1761:1761)) - (PORT ena (2295:2295:2295) (2346:2346:2346)) + (PORT d (1665:1665:1665) (1726:1726:1726)) + (PORT ena (2611:2611:2611) (2649:2649:2649)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59579,48 +62651,16 @@ (HOLD ena (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (869:869:869)) - (PORT datab (781:781:781) (872:872:872)) - (PORT datac (630:630:630) (679:679:679)) - (PORT datad (274:274:274) (354:354:354)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~4) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1367:1367:1367)) - (PORT datac (589:589:589) (593:593:593)) - (PORT datad (598:598:598) (611:611:611)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1289:1289:1289) (1364:1364:1364)) - (PORT datab (1055:1055:1055) (1148:1148:1148)) - (PORT datac (1259:1259:1259) (1369:1369:1369)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (223:223:223) (267:267:267)) + (PORT datac (602:602:602) (620:620:620)) + (PORT datad (1515:1515:1515) (1610:1610:1610)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59630,10 +62670,10 @@ (INSTANCE sdram_\|Mux19\~6) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1371:1371:1371)) - (PORT datab (1057:1057:1057) (1150:1150:1150)) - (PORT datac (1257:1257:1257) (1371:1371:1371)) - (PORT datad (181:181:181) (211:211:211)) + (PORT dataa (1437:1437:1437) (1591:1591:1591)) + (PORT datab (1637:1637:1637) (1751:1751:1751)) + (PORT datac (350:350:350) (379:379:379)) + (PORT datad (1376:1376:1376) (1465:1465:1465)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -59641,17 +62681,33 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1585:1585:1585)) + (PORT datab (1637:1637:1637) (1743:1743:1743)) + (PORT datac (352:352:352) (381:381:381)) + (PORT datad (1376:1376:1376) (1462:1462:1462)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~7) (DELAY (ABSOLUTE - (PORT dataa (1377:1377:1377) (1426:1426:1426)) - (PORT datab (404:404:404) (482:482:482)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (407:407:407) (479:479:479)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1367:1367:1367) (1437:1437:1437)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59662,11 +62718,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT clk (1531:1531:1531) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (524:524:524) (559:559:559)) - (PORT sload (1665:1665:1665) (1784:1784:1784)) - (PORT ena (980:980:980) (972:972:972)) + (PORT asdata (676:676:676) (702:702:702)) + (PORT sload (1918:1918:1918) (2069:2069:2069)) + (PORT ena (1521:1521:1521) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -59679,13 +62735,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux19\~2) + (INSTANCE sdram_\|Mux19\~1) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (889:889:889) (939:939:939)) - (PORT datac (1575:1575:1575) (1696:1696:1696)) - (PORT datad (635:635:635) (714:714:714)) + (PORT dataa (639:639:639) (672:672:672)) + (PORT datab (1182:1182:1182) (1258:1258:1258)) + (PORT datac (378:378:378) (445:445:445)) + (PORT datad (1376:1376:1376) (1462:1462:1462)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -59693,18 +62749,34 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1019:1019:1019)) + (PORT datab (1160:1160:1160) (1269:1269:1269)) + (PORT datac (751:751:751) (844:844:844)) + (PORT datad (1093:1093:1093) (1198:1198:1198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|Mux19\~3) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (656:656:656)) - (PORT datab (1058:1058:1058) (1148:1148:1148)) - (PORT datac (1348:1348:1348) (1386:1386:1386)) - (PORT datad (380:380:380) (445:445:445)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (617:617:617) (645:645:645)) + (PORT datab (406:406:406) (476:476:476)) + (PORT datac (613:613:613) (623:623:623)) + (PORT datad (1366:1366:1366) (1436:1436:1436)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59714,11 +62786,11 @@ (INSTANCE sdram_\|r\.address\[5\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1290:1290:1290) (1371:1371:1371)) - (PORT datab (642:642:642) (688:688:688)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1636:1636:1636) (1751:1751:1751)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59728,12 +62800,12 @@ (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1091:1091:1091) (1170:1170:1170)) - (PORT datac (181:181:181) (218:218:218)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1333:1333:1333) (1457:1457:1457)) + (PORT datad (195:195:195) (220:220:220)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -59743,8 +62815,8 @@ (DELAY (ABSOLUTE (PORT clk (1514:1514:1514) (1539:1539:1539)) - (PORT d (1443:1443:1443) (1520:1520:1520)) - (PORT ena (2198:2198:2198) (2202:2202:2202)) + (PORT d (1250:1250:1250) (1340:1340:1340)) + (PORT ena (1955:1955:1955) (2028:2028:2028)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59760,9 +62832,9 @@ (INSTANCE sdram_\|Mux18\~0) (DELAY (ABSOLUTE - (PORT dataa (2415:2415:2415) (2626:2626:2626)) - (PORT datac (1237:1237:1237) (1358:1358:1358)) - (PORT datad (667:667:667) (699:699:699)) + (PORT dataa (1338:1338:1338) (1486:1486:1486)) + (PORT datac (1130:1130:1130) (1202:1202:1202)) + (PORT datad (1551:1551:1551) (1578:1578:1578)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59775,8 +62847,8 @@ (DELAY (ABSOLUTE (PORT clk (1515:1515:1515) (1539:1539:1539)) - (PORT d (1527:1527:1527) (1623:1623:1623)) - (PORT ena (1611:1611:1611) (1629:1629:1629)) + (PORT d (1490:1490:1490) (1582:1582:1582)) + (PORT ena (1569:1569:1569) (1588:1588:1588)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59789,12 +62861,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux17\~0) + (INSTANCE sdram_\|Mux17\~2) (DELAY (ABSOLUTE - (PORT dataa (2411:2411:2411) (2624:2624:2624)) - (PORT datac (1497:1497:1497) (1597:1597:1597)) - (PORT datad (667:667:667) (698:698:698)) + (PORT dataa (1338:1338:1338) (1484:1484:1484)) + (PORT datac (873:873:873) (953:953:953)) + (PORT datad (1553:1553:1553) (1573:1573:1573)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59807,8 +62879,8 @@ (DELAY (ABSOLUTE (PORT clk (1513:1513:1513) (1537:1537:1537)) - (PORT d (1993:1993:1993) (2101:2101:2101)) - (PORT ena (1609:1609:1609) (1676:1676:1676)) + (PORT d (1907:1907:1907) (2009:2009:2009)) + (PORT ena (1784:1784:1784) (1824:1824:1824)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -59821,12 +62893,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux16\~0) + (INSTANCE sdram_\|Mux16\~2) (DELAY (ABSOLUTE - (PORT dataa (2422:2422:2422) (2635:2635:2635)) - (PORT datac (243:243:243) (322:322:322)) - (PORT datad (667:667:667) (698:698:698)) + (PORT dataa (1341:1341:1341) (1483:1483:1483)) + (PORT datac (1154:1154:1154) (1207:1207:1207)) + (PORT datad (1553:1553:1553) (1578:1578:1578)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -59839,8 +62911,8 @@ (DELAY (ABSOLUTE (PORT clk (1495:1495:1495) (1520:1520:1520)) - (PORT d (2142:2142:2142) (2266:2266:2266)) - (PORT ena (1415:1415:1415) (1456:1456:1456)) + (PORT d (1804:1804:1804) (1915:1915:1915)) + (PORT ena (1774:1774:1774) (1848:1848:1848)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -59856,11 +62928,11 @@ (INSTANCE sdram_\|Mux15\~2) (DELAY (ABSOLUTE - (PORT dataa (2424:2424:2424) (2635:2635:2635)) - (PORT datab (933:933:933) (1032:1032:1032)) - (PORT datad (667:667:667) (702:702:702)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1333:1333:1333) (1479:1479:1479)) + (PORT datac (1411:1411:1411) (1464:1464:1464)) + (PORT datad (1551:1551:1551) (1573:1573:1573)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -59871,8 +62943,8 @@ (DELAY (ABSOLUTE (PORT clk (1497:1497:1497) (1522:1522:1522)) - (PORT d (2142:2142:2142) (2261:2261:2261)) - (PORT ena (1453:1453:1453) (1505:1505:1505)) + (PORT d (2038:2038:2038) (2128:2128:2128)) + (PORT ena (1775:1775:1775) (1850:1850:1850)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -59885,79 +62957,23 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~0) + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1feeder) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (737:737:737)) - (PORT datab (711:711:711) (800:800:800)) - (PORT datac (1260:1260:1260) (1352:1352:1352)) - (PORT datad (181:181:181) (207:207:207)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|Mux14\~1) + (INSTANCE sdram_\|n\~5) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (729:729:729)) - (PORT datab (407:407:407) (478:478:478)) - (PORT datac (1035:1035:1035) (1137:1137:1137)) - (PORT datad (627:627:627) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[10\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (993:993:993) (1068:1068:1068)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1560:1560:1560)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (523:523:523) (557:557:557)) - (PORT sload (1639:1639:1639) (1751:1751:1751)) - (PORT ena (1247:1247:1247) (1254:1254:1254)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|n\~4) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (923:923:923)) - (PORT datab (406:406:406) (476:476:476)) - (PORT datac (676:676:676) (747:747:747)) - (PORT datad (675:675:675) (725:725:725)) + (PORT dataa (947:947:947) (996:996:996)) + (PORT datab (784:784:784) (877:877:877)) + (PORT datac (911:911:911) (985:985:985)) + (PORT datad (404:404:404) (466:466:466)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -59970,12 +62986,12 @@ (INSTANCE sdram_\|Mux14\~2) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (740:740:740)) - (PORT datab (712:712:712) (801:801:801)) - (PORT datac (1257:1257:1257) (1357:1357:1357)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (946:946:946) (1047:1047:1047)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1097:1097:1097) (1206:1206:1206)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -59986,28 +63002,94 @@ (INSTANCE sdram_\|Mux14\~3) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (406:406:406) (474:474:474)) - (PORT datac (381:381:381) (407:407:407)) - (PORT datad (632:632:632) (657:657:657)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (666:666:666) (705:705:705)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (202:202:202) (238:238:238)) + (PORT datad (315:315:315) (325:325:325)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (556:556:556)) + (PORT sload (1900:1900:1900) (2061:2061:2061)) + (PORT ena (842:842:842) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (609:609:609)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (1050:1050:1050) (1142:1142:1142)) + (PORT datad (639:639:639) (664:664:664)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1049:1049:1049)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1097:1097:1097) (1204:1204:1204)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (1073:1073:1073) (1173:1173:1173)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (327:327:327) (344:344:344)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT datab (1064:1064:1064) (1139:1139:1139)) - (PORT datac (181:181:181) (217:217:217)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1315:1315:1315) (1450:1450:1450)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (179:179:179) (216:216:216)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -60017,8 +63099,8 @@ (DELAY (ABSOLUTE (PORT clk (1488:1488:1488) (1513:1513:1513)) - (PORT d (1458:1458:1458) (1539:1539:1539)) - (PORT ena (1669:1669:1669) (1698:1698:1698)) + (PORT d (1561:1561:1561) (1677:1677:1677)) + (PORT ena (1666:1666:1666) (1721:1721:1721)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -60031,14 +63113,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~18) + (INSTANCE sdram_\|r\.address\[11\]\~21) (DELAY (ABSOLUTE - (PORT datab (766:766:766) (848:848:848)) - (PORT datac (1262:1262:1262) (1381:1381:1381)) - (PORT datad (735:735:735) (822:822:822)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1437:1437:1437) (1585:1585:1585)) + (PORT datab (1636:1636:1636) (1742:1742:1742)) + (PORT datac (1083:1083:1083) (1121:1121:1121)) + (PORT datad (661:661:661) (724:724:724)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (1634:1634:1634) (1746:1746:1746)) + (PORT datac (1822:1822:1822) (1913:1913:1913)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -60048,37 +63146,26 @@ (INSTANCE sdram_\|r\.address\[11\]\~5) (DELAY (ABSOLUTE - (PORT dataa (1000:1000:1000) (1091:1091:1091)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1639:1639:1639) (1751:1751:1751)) + (PORT datad (577:577:577) (595:595:595)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (266:266:266)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1559:1559:1559)) + (PORT clk (1531:1531:1531) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (530:530:530) (570:570:570)) - (PORT sload (1322:1322:1322) (1457:1457:1457)) - (PORT ena (1290:1290:1290) (1318:1318:1318)) + (PORT asdata (869:869:869) (879:879:879)) + (PORT sload (1918:1918:1918) (2069:2069:2069)) + (PORT ena (1276:1276:1276) (1258:1258:1258)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -60094,11 +63181,11 @@ (INSTANCE sdram_\|Mux13\~10) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (334:334:334)) - (PORT datac (768:768:768) (884:884:884)) - (PORT datad (677:677:677) (777:777:777)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1437:1437:1437) (1588:1588:1588)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (1599:1599:1599) (1709:1709:1709)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -60108,13 +63195,13 @@ (INSTANCE sdram_\|Mux13\~6) (DELAY (ABSOLUTE - (PORT dataa (793:793:793) (920:920:920)) - (PORT datab (895:895:895) (926:926:926)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (818:818:818) (836:836:836)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (619:619:619) (643:643:643)) + (PORT datab (1186:1186:1186) (1263:1263:1263)) + (PORT datac (1402:1402:1402) (1552:1552:1552)) + (PORT datad (319:319:319) (329:329:329)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -60124,12 +63211,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (270:270:270)) - (PORT datab (737:737:737) (847:847:847)) - (PORT datac (189:189:189) (231:231:231)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (1302:1302:1302) (1422:1422:1422)) + (PORT datad (321:321:321) (338:338:338)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -60138,9 +63225,9 @@ (INSTANCE sdram_\|r\.address\[11\]) (DELAY (ABSOLUTE - (PORT clk (1502:1502:1502) (1530:1530:1530)) - (PORT d (1252:1252:1252) (1354:1354:1354)) - (PORT ena (1396:1396:1396) (1412:1412:1412)) + (PORT clk (1491:1491:1491) (1515:1515:1515)) + (PORT d (1544:1544:1544) (1627:1627:1627)) + (PORT ena (2237:2237:2237) (2280:2280:2280)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) @@ -60156,12 +63243,12 @@ (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (267:267:267)) - (PORT datab (738:738:738) (843:843:843)) - (PORT datac (187:187:187) (229:229:229)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (226:226:226) (268:268:268)) + (PORT datac (1302:1302:1302) (1422:1422:1422)) + (PORT datad (321:321:321) (339:339:339)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -60171,8 +63258,8 @@ (DELAY (ABSOLUTE (PORT clk (1493:1493:1493) (1518:1518:1518)) - (PORT d (1706:1706:1706) (1798:1798:1798)) - (PORT ena (1700:1700:1700) (1737:1737:1737)) + (PORT d (1762:1762:1762) (1884:1884:1884)) + (PORT ena (2226:2226:2226) (2288:2288:2288)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) ) ) diff --git a/spectrum.qsf b/spectrum.qsf index e4cc034..f0b1f36 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -269,18 +269,6 @@ set_location_assignment PIN_A2 -to GPIO_0[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] set_location_assignment PIN_A3 -to GPIO_0[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] -set_location_assignment PIN_B3 -to GPIO_0[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] -set_location_assignment PIN_B4 -to GPIO_0[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] -set_location_assignment PIN_A4 -to GPIO_0[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] -set_location_assignment PIN_B5 -to GPIO_0[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] -set_location_assignment PIN_A5 -to GPIO_0[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] -set_location_assignment PIN_D5 -to GPIO_0[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] #============================================================ # GPIO_1, GPIO_1 connect to GPIO Default @@ -353,10 +341,6 @@ set_location_assignment PIN_J16 -to GPIO_1[30] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] set_location_assignment PIN_K15 -to GPIO_1[31] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] -set_location_assignment PIN_J13 -to GPIO_1[32] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] -set_location_assignment PIN_J14 -to GPIO_1[33] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name MIF_FILE led_patterns.mif @@ -464,4 +448,37 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to raw_loader_in set_global_assignment -name QIP_FILE ram_video.qip set_global_assignment -name VHDL_FILE sdram.vhdl set_global_assignment -name QIP_FILE sdram_clk_gen.qip +set_global_assignment -name VERILOG_FILE sdram.v +set_global_assignment -name VERILOG_FILE sdram_ctrl.v +set_global_assignment -name VERILOG_FILE sdram_controller.v +set_global_assignment -name QIP_FILE pll_sdram.qip +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name ENABLE_LOGIC_ANALYZER_INTERFACE OFF +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_location_assignment PIN_D5 -to kempston[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston[4] +set_location_assignment PIN_A5 -to kempston[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston[3] +set_location_assignment PIN_B5 -to kempston[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston[2] +set_location_assignment PIN_A4 -to kempston[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston[1] +set_location_assignment PIN_B4 -to kempston[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston[0] +set_location_assignment PIN_B3 -to kempston_gnd +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston_gnd +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[4] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[0] +set_location_assignment PIN_J13 -to turbo_button +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to turbo_button +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to turbo_button +set_global_assignment -name VERILOG_FILE debouncer.v +set_location_assignment PIN_J14 -to kempston_autofire_button +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to kempston_autofire_button +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston_autofire_button set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.sv b/spectrum.sv index 5dd3e68..221acaf 100644 --- a/spectrum.sv +++ b/spectrum.sv @@ -17,7 +17,7 @@ module spectrum(output wire[7:0] LED, output wire VGA_HS, output wire VGA_VS, input wire[3:0] SW, // 0 = ROM selection, 1 = enable/disable interrupts, 2 = turbo speed - output wire[33:0] GPIO_1, // Exports CPU chip pins, + output wire[31:0] GPIO_1, // Exports CPU chip pins, output wire buzzer_out, input wire raw_loader_in, output wire[1:0] DRAM_BA, @@ -29,56 +29,61 @@ module spectrum(output wire[7:0] LED, output wire DRAM_WE_N, output wire DRAM_CS_N, inout wire[15:0] DRAM_DQ, - output wire[12:0] DRAM_ADDR + output wire[12:0] DRAM_ADDR, + // output wire[2:0] GPIO_0, + //-------- Atari joystick mapped as Kempston + input wire [4:0] kempston, // Input with weak pull-up + output wire kempston_gnd, // Helps mapping to DB9 cable + input wire turbo_button, + input wire kempston_autofire_button ); `default_nettype none -/* -assign GPIO_1[0] = VGA_VS; -assign GPIO_1[1] = VGA_HS; -assign GPIO_1[2] = VGA_B[0]; -assign GPIO_1[3] = vs_nintr; - -wire clk_pix; // VGA pixel clock (25.175 MHz) -wire locked; -wire clk_vram; - -pll_video pll_( - .locked(locked), - .inclk0(CLOCK_50), - .c0(clk_pix) -); - - -reg [12:0] vram_address; -reg [7:0] vram_data; -rom_scr rom_( - .clock(CLOCK_50), - .address(vram_address), - .q(vram_data) -// .q(8'b10111000) -); - -wire [2:0] border; // Border color index value -assign border = SW[2:0]; - -wire vs_nintr; // Vertical retrace interrupt -video video_( .*, .vram_address(vram_address), .vram_data(vram_data) ); -//video video_( .*, .vram_address(vram_address), .vram_data(8'b10111000) ); -*/ - - wire reset; wire locked; assign reset = locked & KEY[0:0]; +reg turbo = 0; +wire turbo_button_debounced; +debouncer debounce_turbo( + .i_Clk(CLOCK_50), + .i_Switch(turbo_button), + .o_Switch(turbo_button_debounced) +); + +always @(negedge turbo_button_debounced) +begin + turbo = !turbo; +end + + +reg kempston_autofire_enabled = 0; +wire kempston_autofire_button_debounced; +debouncer debounce_autofire( + .i_Clk(CLOCK_50), + .i_Switch(kempston_autofire_button), + .o_Switch(kempston_autofire_button_debounced) +); +always @(negedge kempston_autofire_button_debounced) +begin + kempston_autofire_enabled = !kempston_autofire_enabled; +end + // Export selected pins to the extension connector assign GPIO_1[15:0] = A[15:0]; assign GPIO_1[23:16] = D[7:0]; assign GPIO_1[31:24] = {nM1,nMREQ,nIORQ,nRD,nWR,nRFSH,nHALT,nBUSACK}; +assign kempston_gnd = 0; // enable kempston + +assign LED[7] = !kempston[4] & kempston_auto_fire; +assign LED[6] = !kempston[3]; +assign LED[5] = !kempston[2]; +assign LED[4] = !kempston[1]; +assign LED[3] = !kempston[0]; + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Internal buses and address map selection logic @@ -91,7 +96,7 @@ wire RamWE; assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0; wire ExtRamWE; // Extended (and external) 32K RAM -assign ExtRamWE = A[15]==1 && nIORQ==1 && nRD==1 && nWR==0; +assign ExtRamWE = A[15]==1'b1 && nIORQ==1 && nRD==1 && nWR==0; wire [7:0] ula_data; // ULA wire io_we; @@ -102,6 +107,43 @@ assign io_we = nIORQ==0 && nRD==1 && nWR==0; // 0000 - 3FFF 16K ROM (mapped to rom0) // 4000 - 7FFF 16K dual-port ram0 // 8000 - FFFF 32K RAM (mapped to ram1) + + + + +wire is_io_read_requested; +wire is_io_write_requested; +wire is_mem_read_requested; +wire is_mem_write_requested; +wire is_rom_address; +wire is_upper_ram_address; + +assign is_rom_address = A[15:14] == 2'b00; +assign is_upper_ram_address = A[15] == 1'b1; +assign is_io_read_requested = {nIORQ,nRD,nWR} == 3'b001 ? 1'b1 : 1'b0; +assign is_io_write_requested = {nIORQ,nRD,nWR} == 3'b010 ? 1'b1 : 1'b0; +assign is_mem_read_requested = {nIORQ,nRD,nWR} == 3'b101 ? 1'b1 : 1'b0; +assign is_mem_write_requested = {nIORQ,nRD,nWR} == 3'b110 ? 1'b1 : 1'b0; + +// assign D = sdram_out_valid ? sdram_out_data[7:0] : 8b'zzzzzzzz; + +//assign D = is_io_read_requested ? ula_data : (is_mem_read_requested ? (A[15:14] == 2'b00 ? rom_data : (sdram_out_valid ? sdram_out_data : {8{1'bz}})) : {8{1'bz}}); + +reg kempston_auto_fire = 0; +reg kempston_last_fire_state = 0; +reg[17:0] kempston_auto_fire_counter = 0; + +always @(posedge clk_cpu) +begin + if (kempston_autofire_enabled == 0) + kempston_auto_fire <= 1; + else begin + kempston_auto_fire_counter <= kempston_auto_fire_counter + 1; + if (kempston_auto_fire_counter == 0) + kempston_auto_fire <= !kempston_auto_fire; + end +end + always @(*) // always_comb begin case ({nIORQ,nRD,nWR}) @@ -110,32 +152,28 @@ begin // Memory read -------------------------------- 3'b101: begin - casez (A[15:14]) - 2'b00: D[7:0] = rom_data; - 2'b01: D[7:0] = ram0_data; + casez (A[15:14]) + 2'b00: D[7:0] = rom_data; + 2'b01: D[7:0] = ram0_data; 2'b1?: D[7:0] = ram1_data; -// 2'b1?: D[7:0] = sdram_out_data[7:0]; - endcase + endcase end // ---------------------------------- IO read ---------------------------------- 3'b001: begin // Normally data supplied by the ULA D[7:0] = ula_data; - /* // Kempston joystick at the IO address 0x1F; active bits are high: // FIRE UP DOWN LEFT RIGHT if (A[7:0]==8'h1F) begin - D[7:0] = { 3'b0, !kempston[4],!kempston[0],!kempston[1],!kempston[2],!kempston[3] }; + D[7:0] = { 3'b0, !kempston[4] & kempston_auto_fire,!kempston[0],!kempston[1],!kempston[2],!kempston[3] }; end - */ end default: D[7:0] = {8{1'bz}}; endcase end - // ---------------------------------------------------- // Instantiate ROM, 16K // ---------------------------------------------------- @@ -185,14 +223,18 @@ ram32 ram1( // // SDRAM for 128K // - + +wire[23:0] sdram_address; wire[31:0] sdram_out_data; -wire sdram_out_valid; +wire[31:0] sdram_in_data; wire sdram_read_request; wire sdram_write_request; +wire sdram_out_valid; -assign sdram_read_request = nIORQ == 1 && nRD == 0 && nWR == 1; -assign sdram_write_request = ExtRamWE; +assign sdram_write_request = is_upper_ram_address && is_mem_write_requested; +assign sdram_read_request = is_upper_ram_address && is_mem_read_requested; +assign sdram_in_data = {24'd0, D[7:0]}; +assign sdram_address = {8'd0, A[15:0]}; sdram_controller sdram_( .CLOCK_50(CLOCK_50), @@ -207,48 +249,23 @@ sdram_controller sdram_( .DRAM_RAS_N(DRAM_RAS_N), .DRAM_WE_N(DRAM_WE_N), - .address({8'd0, A}), + .address(sdram_address), .req_read(sdram_read_request), - .req_write(sdram_write_request), + .req_write(ExtRamWE), .data_out(sdram_out_data), .data_out_valid(sdram_out_valid), - .data_in({24'd0, D[7:0]}) + .data_in(sdram_in_data) ); -/* -entity sdram_controller is - PORT ( - CLOCK_50 : IN STD_LOGIC; - - -- Signals to/from the SDRAM chip - DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0); - DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); - DRAM_CAS_N : OUT STD_LOGIC; - DRAM_CKE : OUT STD_LOGIC; - DRAM_CLK : OUT STD_LOGIC; - DRAM_CS_N : OUT STD_LOGIC; - DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); - DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); - DRAM_RAS_N : OUT STD_LOGIC; - DRAM_WE_N : OUT STD_LOGIC; - - --- Inputs from rest of the system - address : IN STD_LOGIC_VECTOR (23 downto 0); - req_read : IN STD_LOGIC; - req_write : IN STD_LOGIC; - data_out : OUT STD_LOGIC_VECTOR (31 downto 0); - data_out_valid : OUT STD_LOGIC; - data_in : IN STD_LOGIC_VECTOR (31 downto 0) - ); -end entity; -*/ + + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Instantiate ULA //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ wire clk_cpu; // Global CPU clock of 3.5 MHz -assign LED[2:2] = SW[2:2]; // Glow red when in turbo mode (7.0 MHz) -assign LED[3:3] = raw_loader_in; // feedback from audio in +assign LED[2] = turbo; // Glow red when in turbo mode (7.0 MHz) +assign LED[1] = raw_loader_in; // feedback from audio in wire [12:0] vram_address; // ULA video block requests a byte from the video RAM wire [7:0] vram_data; // ULA video block reads a byte from the video RAM wire vs_nintr; // Generates a vertical retrace interrupt @@ -258,7 +275,7 @@ wire beeper; // Show the beeper state ula ula_( //-------- Clocks and reset ----------------- .CLOCK_50 (CLOCK_50), // Input clock 50 MHz - .turbo (SW[2:2]), // Turbo speed (3.5 MHz x 2 = 7.0 MHz) + .turbo (turbo), // Turbo speed (3.5 MHz x 2 = 7.0 MHz) .clk_vram (clk_vram), .nreset (reset), // KEY0 is reset; on DE1, keys are active low! .locked (locked), // PLL is locked signal @@ -281,7 +298,7 @@ ula ula_( .PS2_DAT (PS2_DAT), .pressed (pressed), - //-------- Audio (Tape player) -------------- + //-------- Audio (e player) -------------- .I2C_SCLK (I2C_SCLK), .I2C_SDAT (I2C_SDAT), .AUD_XCK (AUD_XCK), @@ -300,6 +317,7 @@ ula ula_( .VGA_B (VGA_B), .VGA_HS (VGA_HS), .VGA_VS (VGA_VS) + ); //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~